X86ISelLowering.cpp revision 0c8607ba6a21578996a7532b9390afba13bd2087
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "Utils/X86ShuffleDecode.h" 18#include "X86.h" 19#include "X86InstrBuilder.h" 20#include "X86TargetMachine.h" 21#include "X86TargetObjectFile.h" 22#include "llvm/ADT/SmallSet.h" 23#include "llvm/ADT/Statistic.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/VariadicFunction.h" 26#include "llvm/CodeGen/IntrinsicLowering.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineJumpTableInfo.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/IR/CallingConv.h" 34#include "llvm/IR/Constants.h" 35#include "llvm/IR/DerivedTypes.h" 36#include "llvm/IR/Function.h" 37#include "llvm/IR/GlobalAlias.h" 38#include "llvm/IR/GlobalVariable.h" 39#include "llvm/IR/Instructions.h" 40#include "llvm/IR/Intrinsics.h" 41#include "llvm/IR/LLVMContext.h" 42#include "llvm/MC/MCAsmInfo.h" 43#include "llvm/MC/MCContext.h" 44#include "llvm/MC/MCExpr.h" 45#include "llvm/MC/MCSymbol.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52#include <cctype> 53using namespace llvm; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57// Forward declarations. 58static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 59 SDValue V2); 60 61/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 62/// sets things up to match to an AVX VEXTRACTF128 instruction or a 63/// simple subregister reference. Idx is an index in the 128 bits we 64/// want. It need not be aligned to a 128-bit bounday. That makes 65/// lowering EXTRACT_VECTOR_ELT operations easier. 66static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 67 SelectionDAG &DAG, DebugLoc dl) { 68 EVT VT = Vec.getValueType(); 69 assert(VT.is256BitVector() && "Unexpected vector size!"); 70 EVT ElVT = VT.getVectorElementType(); 71 unsigned Factor = VT.getSizeInBits()/128; 72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 73 VT.getVectorNumElements()/Factor); 74 75 // Extract from UNDEF is UNDEF. 76 if (Vec.getOpcode() == ISD::UNDEF) 77 return DAG.getUNDEF(ResultVT); 78 79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 80 // we can match to VEXTRACTF128. 81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 82 83 // This is the index of the first element of the 128-bit chunk 84 // we want. 85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 86 * ElemsPerChunk); 87 88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 90 VecIdx); 91 92 return Result; 93} 94 95/// Generate a DAG to put 128-bits into a vector > 128 bits. This 96/// sets things up to match to an AVX VINSERTF128 instruction or a 97/// simple superregister reference. Idx is an index in the 128 bits 98/// we want. It need not be aligned to a 128-bit bounday. That makes 99/// lowering INSERT_VECTOR_ELT operations easier. 100static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 101 unsigned IdxVal, SelectionDAG &DAG, 102 DebugLoc dl) { 103 // Inserting UNDEF is Result 104 if (Vec.getOpcode() == ISD::UNDEF) 105 return Result; 106 107 EVT VT = Vec.getValueType(); 108 assert(VT.is128BitVector() && "Unexpected vector size!"); 109 110 EVT ElVT = VT.getVectorElementType(); 111 EVT ResultVT = Result.getValueType(); 112 113 // Insert the relevant 128 bits. 114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 115 116 // This is the index of the first element of the 128-bit chunk 117 // we want. 118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 119 * ElemsPerChunk); 120 121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal); 122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 123 VecIdx); 124} 125 126/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 127/// instructions. This is used because creating CONCAT_VECTOR nodes of 128/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 129/// large BUILD_VECTORS. 130static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 131 unsigned NumElems, SelectionDAG &DAG, 132 DebugLoc dl) { 133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 135} 136 137static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 139 bool is64Bit = Subtarget->is64Bit(); 140 141 if (Subtarget->isTargetEnvMacho()) { 142 if (is64Bit) 143 return new X86_64MachoTargetObjectFile(); 144 return new TargetLoweringObjectFileMachO(); 145 } 146 147 if (Subtarget->isTargetLinux()) 148 return new X86LinuxTargetObjectFile(); 149 if (Subtarget->isTargetELF()) 150 return new TargetLoweringObjectFileELF(); 151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 152 return new TargetLoweringObjectFileCOFF(); 153 llvm_unreachable("unknown subtarget type"); 154} 155 156X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 157 : TargetLowering(TM, createTLOF(TM)) { 158 Subtarget = &TM.getSubtarget<X86Subtarget>(); 159 X86ScalarSSEf64 = Subtarget->hasSSE2(); 160 X86ScalarSSEf32 = Subtarget->hasSSE1(); 161 162 RegInfo = TM.getRegisterInfo(); 163 TD = getDataLayout(); 164 165 // Set up the TargetLowering object. 166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 167 168 // X86 is weird, it always uses i8 for shift amounts and setcc results. 169 setBooleanContents(ZeroOrOneBooleanContent); 170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 172 173 // For 64-bit since we have so many registers use the ILP scheduler, for 174 // 32-bit code use the register pressure specific scheduling. 175 // For Atom, always use ILP scheduling. 176 if (Subtarget->isAtom()) 177 setSchedulingPreference(Sched::ILP); 178 else if (Subtarget->is64Bit()) 179 setSchedulingPreference(Sched::ILP); 180 else 181 setSchedulingPreference(Sched::RegPressure); 182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister()); 183 184 // Bypass i32 with i8 on Atom when compiling with O2 185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) 186 addBypassSlowDiv(32, 8); 187 188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 189 // Setup Windows compiler runtime calls. 190 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 192 setLibcallName(RTLIB::SREM_I64, "_allrem"); 193 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 194 setLibcallName(RTLIB::MUL_I64, "_allmul"); 195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 200 201 // The _ftol2 runtime function has an unusual calling conv, which 202 // is modeled by a special pseudo-instruction. 203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 207 } 208 209 if (Subtarget->isTargetDarwin()) { 210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 211 setUseUnderscoreSetJmp(false); 212 setUseUnderscoreLongJmp(false); 213 } else if (Subtarget->isTargetMingw()) { 214 // MS runtime is weird: it exports _setjmp, but longjmp! 215 setUseUnderscoreSetJmp(true); 216 setUseUnderscoreLongJmp(false); 217 } else { 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(true); 220 } 221 222 // Set up the register classes. 223 addRegisterClass(MVT::i8, &X86::GR8RegClass); 224 addRegisterClass(MVT::i16, &X86::GR16RegClass); 225 addRegisterClass(MVT::i32, &X86::GR32RegClass); 226 if (Subtarget->is64Bit()) 227 addRegisterClass(MVT::i64, &X86::GR64RegClass); 228 229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 230 231 // We don't accept any truncstore of integer registers. 232 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 233 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 235 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 237 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 238 239 // SETOEQ and SETUNE require checking two conditions. 240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 246 247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 248 // operation. 249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 252 253 if (Subtarget->is64Bit()) { 254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 256 } else if (!TM.Options.UseSoftFloat) { 257 // We have an algorithm for SSE2->double, and we turn this into a 258 // 64-bit FILD followed by conditional FADD for other targets. 259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 260 // We have an algorithm for SSE2, and we turn this into a 64-bit 261 // FILD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 263 } 264 265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 266 // this operation. 267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 269 270 if (!TM.Options.UseSoftFloat) { 271 // SSE has no i16 to fp conversion, only i32 272 if (X86ScalarSSEf32) { 273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 274 // f32 and f64 cases are Legal, f80 case is not 275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 276 } else { 277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } 280 } else { 281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 283 } 284 285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 286 // are Legal, f80 is custom lowered. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 289 290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 291 // this operation. 292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 294 295 if (X86ScalarSSEf32) { 296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 297 // f32 and f64 cases are Legal, f80 case is not 298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 299 } else { 300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } 303 304 // Handle FP_TO_UINT by promoting the destination to a larger signed 305 // conversion. 306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 309 310 if (Subtarget->is64Bit()) { 311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 313 } else if (!TM.Options.UseSoftFloat) { 314 // Since AVX is a superset of SSE3, only check for SSE here. 315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 316 // Expand FP_TO_UINT into a select. 317 // FIXME: We would like to use a Custom expander here eventually to do 318 // the optimal thing for SSE vs. the default expansion in the legalizer. 319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 320 else 321 // With SSE3 we can use fisttpll to convert to a signed i64; without 322 // SSE, we're stuck with a fistpll. 323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 324 } 325 326 if (isTargetFTOL()) { 327 // Use the _ftol2 runtime function, which has a pseudo-instruction 328 // to handle its weird calling convention. 329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 330 } 331 332 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 333 if (!X86ScalarSSEf64) { 334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 336 if (Subtarget->is64Bit()) { 337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 338 // Without SSE, i64->f64 goes through memory. 339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 340 } 341 } 342 343 // Scalar integer divide and remainder are lowered to use operations that 344 // produce two results, to match the available instructions. This exposes 345 // the two-result form to trivial CSE, which is able to combine x/y and x%y 346 // into a single instruction. 347 // 348 // Scalar integer multiply-high is also lowered to use two-result 349 // operations, to match the available instructions. However, plain multiply 350 // (low) operations are left as Legal, as there are single-result 351 // instructions for this in x86. Using the two-result multiply instructions 352 // when both high and low results are needed must be arranged by dagcombine. 353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 354 MVT VT = IntVTs[i]; 355 setOperationAction(ISD::MULHS, VT, Expand); 356 setOperationAction(ISD::MULHU, VT, Expand); 357 setOperationAction(ISD::SDIV, VT, Expand); 358 setOperationAction(ISD::UDIV, VT, Expand); 359 setOperationAction(ISD::SREM, VT, Expand); 360 setOperationAction(ISD::UREM, VT, Expand); 361 362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 363 setOperationAction(ISD::ADDC, VT, Custom); 364 setOperationAction(ISD::ADDE, VT, Custom); 365 setOperationAction(ISD::SUBC, VT, Custom); 366 setOperationAction(ISD::SUBE, VT, Custom); 367 } 368 369 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 370 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 371 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 373 if (Subtarget->is64Bit()) 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 379 setOperationAction(ISD::FREM , MVT::f32 , Expand); 380 setOperationAction(ISD::FREM , MVT::f64 , Expand); 381 setOperationAction(ISD::FREM , MVT::f80 , Expand); 382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 383 384 // Promote the i8 variants and force them on up to i32 which has a shorter 385 // encoding. 386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 390 if (Subtarget->hasBMI()) { 391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 393 if (Subtarget->is64Bit()) 394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 395 } else { 396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 398 if (Subtarget->is64Bit()) 399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 400 } 401 402 if (Subtarget->hasLZCNT()) { 403 // When promoting the i8 variants, force them to i32 for a shorter 404 // encoding. 405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 411 if (Subtarget->is64Bit()) 412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 413 } else { 414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 420 if (Subtarget->is64Bit()) { 421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 423 } 424 } 425 426 if (Subtarget->hasPOPCNT()) { 427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 428 } else { 429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 432 if (Subtarget->is64Bit()) 433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 434 } 435 436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 438 439 // These should be promoted to a larger select which is supported. 440 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 441 // X86 wants to expand cmov itself. 442 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 443 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 444 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 445 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 446 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 447 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 448 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 449 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 450 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 451 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 452 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 453 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 454 if (Subtarget->is64Bit()) { 455 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 456 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 457 } 458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support 460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to 461 // support continuation, user-level threading, and etc.. As a result, no 462 // other SjLj exception interfaces are implemented and please don't build 463 // your own exception handling based on them. 464 // LLVM/Clang supports zero-cost DWARF exception handling. 465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 467 468 // Darwin ABI issue. 469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 473 if (Subtarget->is64Bit()) 474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 477 if (Subtarget->is64Bit()) { 478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 483 } 484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 488 if (Subtarget->is64Bit()) { 489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 492 } 493 494 if (Subtarget->hasSSE1()) 495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 496 497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 499 500 // On X86 and X86-64, atomic operations are lowered to locked instructions. 501 // Locked instructions, in turn, have implicit fence semantics (all memory 502 // operations are flushed before issuing the locked instruction, and they 503 // are not buffered), so we can fold away the common pattern of 504 // fence-atomic-fence. 505 setShouldFoldAtomicFences(true); 506 507 // Expand certain atomics 508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 509 MVT VT = IntVTs[i]; 510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 513 } 514 515 if (!Subtarget->is64Bit()) { 516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom); 525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom); 526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom); 527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom); 528 } 529 530 if (Subtarget->hasCmpxchg16b()) { 531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 532 } 533 534 // FIXME - use subtarget debug flags 535 if (!Subtarget->isTargetDarwin() && 536 !Subtarget->isTargetELF() && 537 !Subtarget->isTargetCygMing()) { 538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 539 } 540 541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 545 if (Subtarget->is64Bit()) { 546 setExceptionPointerRegister(X86::RAX); 547 setExceptionSelectorRegister(X86::RDX); 548 } else { 549 setExceptionPointerRegister(X86::EAX); 550 setExceptionSelectorRegister(X86::EDX); 551 } 552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 554 555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 557 558 setOperationAction(ISD::TRAP, MVT::Other, Legal); 559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); 560 561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 562 setOperationAction(ISD::VASTART , MVT::Other, Custom); 563 setOperationAction(ISD::VAEND , MVT::Other, Expand); 564 if (Subtarget->is64Bit()) { 565 setOperationAction(ISD::VAARG , MVT::Other, Custom); 566 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 567 } else { 568 setOperationAction(ISD::VAARG , MVT::Other, Expand); 569 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 570 } 571 572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 574 575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 577 MVT::i64 : MVT::i32, Custom); 578 else if (TM.Options.EnableSegmentedStacks) 579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 580 MVT::i64 : MVT::i32, Custom); 581 else 582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 583 MVT::i64 : MVT::i32, Expand); 584 585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 586 // f32 and f64 use SSE. 587 // Set up the FP register classes. 588 addRegisterClass(MVT::f32, &X86::FR32RegClass); 589 addRegisterClass(MVT::f64, &X86::FR64RegClass); 590 591 // Use ANDPD to simulate FABS. 592 setOperationAction(ISD::FABS , MVT::f64, Custom); 593 setOperationAction(ISD::FABS , MVT::f32, Custom); 594 595 // Use XORP to simulate FNEG. 596 setOperationAction(ISD::FNEG , MVT::f64, Custom); 597 setOperationAction(ISD::FNEG , MVT::f32, Custom); 598 599 // Use ANDPD and ORPD to simulate FCOPYSIGN. 600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 602 603 // Lower this to FGETSIGNx86 plus an AND. 604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 606 607 // We don't support sin/cos/fmod 608 setOperationAction(ISD::FSIN , MVT::f64, Expand); 609 setOperationAction(ISD::FCOS , MVT::f64, Expand); 610 setOperationAction(ISD::FSIN , MVT::f32, Expand); 611 setOperationAction(ISD::FCOS , MVT::f32, Expand); 612 613 // Expand FP immediates into loads from the stack, except for the special 614 // cases we handle. 615 addLegalFPImmediate(APFloat(+0.0)); // xorpd 616 addLegalFPImmediate(APFloat(+0.0f)); // xorps 617 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 618 // Use SSE for f32, x87 for f64. 619 // Set up the FP register classes. 620 addRegisterClass(MVT::f32, &X86::FR32RegClass); 621 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 622 623 // Use ANDPS to simulate FABS. 624 setOperationAction(ISD::FABS , MVT::f32, Custom); 625 626 // Use XORP to simulate FNEG. 627 setOperationAction(ISD::FNEG , MVT::f32, Custom); 628 629 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 630 631 // Use ANDPS and ORPS to simulate FCOPYSIGN. 632 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 633 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 634 635 // We don't support sin/cos/fmod 636 setOperationAction(ISD::FSIN , MVT::f32, Expand); 637 setOperationAction(ISD::FCOS , MVT::f32, Expand); 638 639 // Special cases we handle for FP constants. 640 addLegalFPImmediate(APFloat(+0.0f)); // xorps 641 addLegalFPImmediate(APFloat(+0.0)); // FLD0 642 addLegalFPImmediate(APFloat(+1.0)); // FLD1 643 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 644 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 645 646 if (!TM.Options.UnsafeFPMath) { 647 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 648 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 649 } 650 } else if (!TM.Options.UseSoftFloat) { 651 // f32 and f64 in x87. 652 // Set up the FP register classes. 653 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 654 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 655 656 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 657 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 660 661 if (!TM.Options.UnsafeFPMath) { 662 setOperationAction(ISD::FSIN , MVT::f32 , Expand); 663 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 664 setOperationAction(ISD::FCOS , MVT::f32 , Expand); 665 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 666 } 667 addLegalFPImmediate(APFloat(+0.0)); // FLD0 668 addLegalFPImmediate(APFloat(+1.0)); // FLD1 669 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 670 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 671 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 672 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 673 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 674 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 675 } 676 677 // We don't support FMA. 678 setOperationAction(ISD::FMA, MVT::f64, Expand); 679 setOperationAction(ISD::FMA, MVT::f32, Expand); 680 681 // Long double always uses X87. 682 if (!TM.Options.UseSoftFloat) { 683 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 684 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 685 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 686 { 687 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 688 addLegalFPImmediate(TmpFlt); // FLD0 689 TmpFlt.changeSign(); 690 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 691 692 bool ignored; 693 APFloat TmpFlt2(+1.0); 694 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 695 &ignored); 696 addLegalFPImmediate(TmpFlt2); // FLD1 697 TmpFlt2.changeSign(); 698 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 699 } 700 701 if (!TM.Options.UnsafeFPMath) { 702 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 703 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 704 } 705 706 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 707 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 708 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 709 setOperationAction(ISD::FRINT, MVT::f80, Expand); 710 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 711 setOperationAction(ISD::FMA, MVT::f80, Expand); 712 } 713 714 // Always use a library call for pow. 715 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 716 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 717 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 718 719 setOperationAction(ISD::FLOG, MVT::f80, Expand); 720 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 721 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 722 setOperationAction(ISD::FEXP, MVT::f80, Expand); 723 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 724 725 // First set operation action for all vector types to either promote 726 // (for widening) or expand (for scalarization). Then we will selectively 727 // turn on ones that can be effectively codegen'd. 728 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 729 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 730 MVT VT = (MVT::SimpleValueType)i; 731 setOperationAction(ISD::ADD , VT, Expand); 732 setOperationAction(ISD::SUB , VT, Expand); 733 setOperationAction(ISD::FADD, VT, Expand); 734 setOperationAction(ISD::FNEG, VT, Expand); 735 setOperationAction(ISD::FSUB, VT, Expand); 736 setOperationAction(ISD::MUL , VT, Expand); 737 setOperationAction(ISD::FMUL, VT, Expand); 738 setOperationAction(ISD::SDIV, VT, Expand); 739 setOperationAction(ISD::UDIV, VT, Expand); 740 setOperationAction(ISD::FDIV, VT, Expand); 741 setOperationAction(ISD::SREM, VT, Expand); 742 setOperationAction(ISD::UREM, VT, Expand); 743 setOperationAction(ISD::LOAD, VT, Expand); 744 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); 745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand); 746 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 747 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); 748 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); 749 setOperationAction(ISD::FABS, VT, Expand); 750 setOperationAction(ISD::FSIN, VT, Expand); 751 setOperationAction(ISD::FCOS, VT, Expand); 752 setOperationAction(ISD::FREM, VT, Expand); 753 setOperationAction(ISD::FMA, VT, Expand); 754 setOperationAction(ISD::FPOWI, VT, Expand); 755 setOperationAction(ISD::FSQRT, VT, Expand); 756 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 757 setOperationAction(ISD::FFLOOR, VT, Expand); 758 setOperationAction(ISD::FCEIL, VT, Expand); 759 setOperationAction(ISD::FTRUNC, VT, Expand); 760 setOperationAction(ISD::FRINT, VT, Expand); 761 setOperationAction(ISD::FNEARBYINT, VT, Expand); 762 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 763 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 764 setOperationAction(ISD::SDIVREM, VT, Expand); 765 setOperationAction(ISD::UDIVREM, VT, Expand); 766 setOperationAction(ISD::FPOW, VT, Expand); 767 setOperationAction(ISD::CTPOP, VT, Expand); 768 setOperationAction(ISD::CTTZ, VT, Expand); 769 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 770 setOperationAction(ISD::CTLZ, VT, Expand); 771 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 772 setOperationAction(ISD::SHL, VT, Expand); 773 setOperationAction(ISD::SRA, VT, Expand); 774 setOperationAction(ISD::SRL, VT, Expand); 775 setOperationAction(ISD::ROTL, VT, Expand); 776 setOperationAction(ISD::ROTR, VT, Expand); 777 setOperationAction(ISD::BSWAP, VT, Expand); 778 setOperationAction(ISD::SETCC, VT, Expand); 779 setOperationAction(ISD::FLOG, VT, Expand); 780 setOperationAction(ISD::FLOG2, VT, Expand); 781 setOperationAction(ISD::FLOG10, VT, Expand); 782 setOperationAction(ISD::FEXP, VT, Expand); 783 setOperationAction(ISD::FEXP2, VT, Expand); 784 setOperationAction(ISD::FP_TO_UINT, VT, Expand); 785 setOperationAction(ISD::FP_TO_SINT, VT, Expand); 786 setOperationAction(ISD::UINT_TO_FP, VT, Expand); 787 setOperationAction(ISD::SINT_TO_FP, VT, Expand); 788 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand); 789 setOperationAction(ISD::TRUNCATE, VT, Expand); 790 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); 791 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); 792 setOperationAction(ISD::ANY_EXTEND, VT, Expand); 793 setOperationAction(ISD::VSELECT, VT, Expand); 794 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 795 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 796 setTruncStoreAction(VT, 797 (MVT::SimpleValueType)InnerVT, Expand); 798 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 799 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 800 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 801 } 802 803 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 804 // with -msoft-float, disable use of MMX as well. 805 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 806 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 807 // No operations on x86mmx supported, everything uses intrinsics. 808 } 809 810 // MMX-sized vectors (other than x86mmx) are expected to be expanded 811 // into smaller operations. 812 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 813 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 814 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 815 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 816 setOperationAction(ISD::AND, MVT::v8i8, Expand); 817 setOperationAction(ISD::AND, MVT::v4i16, Expand); 818 setOperationAction(ISD::AND, MVT::v2i32, Expand); 819 setOperationAction(ISD::AND, MVT::v1i64, Expand); 820 setOperationAction(ISD::OR, MVT::v8i8, Expand); 821 setOperationAction(ISD::OR, MVT::v4i16, Expand); 822 setOperationAction(ISD::OR, MVT::v2i32, Expand); 823 setOperationAction(ISD::OR, MVT::v1i64, Expand); 824 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 825 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 826 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 827 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 831 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 833 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 834 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 835 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 836 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 837 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 838 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 839 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 840 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 841 842 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 843 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 844 845 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 846 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 847 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 848 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 849 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 850 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 851 setOperationAction(ISD::FABS, MVT::v4f32, Custom); 852 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 853 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 854 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 856 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 857 } 858 859 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 860 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 861 862 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 863 // registers cannot be used even for integer operations. 864 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 865 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 866 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 867 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 868 869 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 870 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 871 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 872 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 873 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 874 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 875 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 876 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 877 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 878 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 879 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 880 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 881 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 882 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 883 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 884 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 885 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 886 setOperationAction(ISD::FABS, MVT::v2f64, Custom); 887 888 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 889 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 890 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 891 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 892 893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 894 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 895 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 898 899 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 900 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 901 MVT VT = (MVT::SimpleValueType)i; 902 // Do not attempt to custom lower non-power-of-2 vectors 903 if (!isPowerOf2_32(VT.getVectorNumElements())) 904 continue; 905 // Do not attempt to custom lower non-128-bit vectors 906 if (!VT.is128BitVector()) 907 continue; 908 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 909 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 910 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 911 } 912 913 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 914 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 919 920 if (Subtarget->is64Bit()) { 921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 923 } 924 925 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 926 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 927 MVT VT = (MVT::SimpleValueType)i; 928 929 // Do not attempt to promote non-128-bit vectors 930 if (!VT.is128BitVector()) 931 continue; 932 933 setOperationAction(ISD::AND, VT, Promote); 934 AddPromotedToType (ISD::AND, VT, MVT::v2i64); 935 setOperationAction(ISD::OR, VT, Promote); 936 AddPromotedToType (ISD::OR, VT, MVT::v2i64); 937 setOperationAction(ISD::XOR, VT, Promote); 938 AddPromotedToType (ISD::XOR, VT, MVT::v2i64); 939 setOperationAction(ISD::LOAD, VT, Promote); 940 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64); 941 setOperationAction(ISD::SELECT, VT, Promote); 942 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64); 943 } 944 945 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 946 947 // Custom lower v2i64 and v2f64 selects. 948 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 949 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 950 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 951 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 952 953 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 954 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 955 956 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); 957 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 958 // As there is no 64-bit GPR available, we need build a special custom 959 // sequence to convert from v2i32 to v2f32. 960 if (!Subtarget->is64Bit()) 961 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom); 962 963 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); 964 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom); 965 966 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal); 967 } 968 969 if (Subtarget->hasSSE41()) { 970 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 971 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 972 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 973 setOperationAction(ISD::FRINT, MVT::f32, Legal); 974 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 975 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 976 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 977 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 978 setOperationAction(ISD::FRINT, MVT::f64, Legal); 979 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 980 981 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 982 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 983 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 984 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); 985 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 986 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); 987 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); 988 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); 989 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); 990 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); 991 992 // FIXME: Do we need to handle scalar-to-vector here? 993 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 994 995 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 996 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 997 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 998 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 999 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 1000 1001 // i8 and i16 vectors are custom , because the source register and source 1002 // source memory operand types are not the same width. f32 vectors are 1003 // custom since the immediate controlling the insert encodes additional 1004 // information. 1005 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 1007 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 1009 1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 1013 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 1014 1015 // FIXME: these should be Legal but thats only for the case where 1016 // the index is constant. For now custom expand to deal with that. 1017 if (Subtarget->is64Bit()) { 1018 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 1020 } 1021 } 1022 1023 if (Subtarget->hasSSE2()) { 1024 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 1025 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 1026 1027 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 1028 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 1029 1030 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 1031 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 1032 1033 if (Subtarget->hasInt256()) { 1034 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 1035 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 1036 1037 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 1038 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 1039 1040 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1041 } else { 1042 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1043 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1044 1045 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1046 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1047 1048 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1049 } 1050 setOperationAction(ISD::SDIV, MVT::v8i16, Custom); 1051 setOperationAction(ISD::SDIV, MVT::v4i32, Custom); 1052 } 1053 1054 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) { 1055 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1056 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1057 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1058 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1059 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1060 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1061 1062 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1063 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1064 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1065 1066 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1067 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1068 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1069 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1070 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1071 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal); 1072 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); 1073 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal); 1074 setOperationAction(ISD::FRINT, MVT::v8f32, Legal); 1075 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal); 1076 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1077 setOperationAction(ISD::FABS, MVT::v8f32, Custom); 1078 1079 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1080 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1081 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1082 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1083 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1084 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); 1085 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); 1086 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); 1087 setOperationAction(ISD::FRINT, MVT::v4f64, Legal); 1088 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal); 1089 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1090 setOperationAction(ISD::FABS, MVT::v4f64, Custom); 1091 1092 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom); 1093 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom); 1094 1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); 1096 1097 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1100 1101 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); 1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); 1103 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); 1104 1105 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal); 1106 1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1109 1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1112 1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1115 1116 setOperationAction(ISD::SDIV, MVT::v16i16, Custom); 1117 1118 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1119 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1120 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1121 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1122 1123 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1124 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1125 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1126 1127 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1128 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1129 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1130 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1131 1132 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); 1133 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); 1134 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); 1135 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); 1136 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom); 1137 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom); 1138 1139 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) { 1140 setOperationAction(ISD::FMA, MVT::v8f32, Legal); 1141 setOperationAction(ISD::FMA, MVT::v4f64, Legal); 1142 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 1143 setOperationAction(ISD::FMA, MVT::v2f64, Legal); 1144 setOperationAction(ISD::FMA, MVT::f32, Legal); 1145 setOperationAction(ISD::FMA, MVT::f64, Legal); 1146 } 1147 1148 if (Subtarget->hasInt256()) { 1149 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1150 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1151 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1152 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1153 1154 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1155 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1156 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1157 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1158 1159 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1160 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1161 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1162 // Don't lower v32i8 because there is no 128-bit byte mul 1163 1164 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1165 1166 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1167 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1168 1169 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1170 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1171 1172 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1173 1174 setOperationAction(ISD::SDIV, MVT::v8i32, Custom); 1175 } else { 1176 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1177 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1178 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1179 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1180 1181 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1182 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1183 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1184 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1185 1186 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1187 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1188 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1189 // Don't lower v32i8 because there is no 128-bit byte mul 1190 1191 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1192 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1193 1194 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1195 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1196 1197 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1198 } 1199 1200 // Custom lower several nodes for 256-bit types. 1201 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1202 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1203 MVT VT = (MVT::SimpleValueType)i; 1204 1205 // Extract subvector is special because the value type 1206 // (result) is 128-bit but the source is 256-bit wide. 1207 if (VT.is128BitVector()) 1208 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); 1209 1210 // Do not attempt to custom lower other non-256-bit vectors 1211 if (!VT.is256BitVector()) 1212 continue; 1213 1214 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 1215 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 1216 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 1217 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 1218 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); 1219 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); 1220 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); 1221 } 1222 1223 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1224 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1225 MVT VT = (MVT::SimpleValueType)i; 1226 1227 // Do not attempt to promote non-256-bit vectors 1228 if (!VT.is256BitVector()) 1229 continue; 1230 1231 setOperationAction(ISD::AND, VT, Promote); 1232 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 1233 setOperationAction(ISD::OR, VT, Promote); 1234 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 1235 setOperationAction(ISD::XOR, VT, Promote); 1236 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 1237 setOperationAction(ISD::LOAD, VT, Promote); 1238 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 1239 setOperationAction(ISD::SELECT, VT, Promote); 1240 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 1241 } 1242 } 1243 1244 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1245 // of this type with custom code. 1246 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1247 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1248 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1249 Custom); 1250 } 1251 1252 // We want to custom lower some of our intrinsics. 1253 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1254 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 1255 1256 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1257 // handle type legalization for these operations here. 1258 // 1259 // FIXME: We really should do custom legalization for addition and 1260 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1261 // than generic legalization for 64-bit multiplication-with-overflow, though. 1262 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1263 // Add/Sub/Mul with overflow operations are custom lowered. 1264 MVT VT = IntVTs[i]; 1265 setOperationAction(ISD::SADDO, VT, Custom); 1266 setOperationAction(ISD::UADDO, VT, Custom); 1267 setOperationAction(ISD::SSUBO, VT, Custom); 1268 setOperationAction(ISD::USUBO, VT, Custom); 1269 setOperationAction(ISD::SMULO, VT, Custom); 1270 setOperationAction(ISD::UMULO, VT, Custom); 1271 } 1272 1273 // There are no 8-bit 3-address imul/mul instructions 1274 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1275 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1276 1277 if (!Subtarget->is64Bit()) { 1278 // These libcalls are not available in 32-bit. 1279 setLibcallName(RTLIB::SHL_I128, 0); 1280 setLibcallName(RTLIB::SRL_I128, 0); 1281 setLibcallName(RTLIB::SRA_I128, 0); 1282 } 1283 1284 // We have target-specific dag combine patterns for the following nodes: 1285 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1286 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1287 setTargetDAGCombine(ISD::VSELECT); 1288 setTargetDAGCombine(ISD::SELECT); 1289 setTargetDAGCombine(ISD::SHL); 1290 setTargetDAGCombine(ISD::SRA); 1291 setTargetDAGCombine(ISD::SRL); 1292 setTargetDAGCombine(ISD::OR); 1293 setTargetDAGCombine(ISD::AND); 1294 setTargetDAGCombine(ISD::ADD); 1295 setTargetDAGCombine(ISD::FADD); 1296 setTargetDAGCombine(ISD::FSUB); 1297 setTargetDAGCombine(ISD::FMA); 1298 setTargetDAGCombine(ISD::SUB); 1299 setTargetDAGCombine(ISD::LOAD); 1300 setTargetDAGCombine(ISD::STORE); 1301 setTargetDAGCombine(ISD::ZERO_EXTEND); 1302 setTargetDAGCombine(ISD::ANY_EXTEND); 1303 setTargetDAGCombine(ISD::SIGN_EXTEND); 1304 setTargetDAGCombine(ISD::TRUNCATE); 1305 setTargetDAGCombine(ISD::SINT_TO_FP); 1306 setTargetDAGCombine(ISD::SETCC); 1307 if (Subtarget->is64Bit()) 1308 setTargetDAGCombine(ISD::MUL); 1309 setTargetDAGCombine(ISD::XOR); 1310 1311 computeRegisterProperties(); 1312 1313 // On Darwin, -Os means optimize for size without hurting performance, 1314 // do not reduce the limit. 1315 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1316 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1317 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1318 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1319 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1320 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1321 setPrefLoopAlignment(4); // 2^4 bytes. 1322 benefitFromCodePlacementOpt = true; 1323 1324 // Predictable cmov don't hurt on atom because it's in-order. 1325 predictableSelectIsExpensive = !Subtarget->isAtom(); 1326 1327 setPrefFunctionAlignment(4); // 2^4 bytes. 1328} 1329 1330EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1331 if (!VT.isVector()) return MVT::i8; 1332 return VT.changeVectorElementTypeToInteger(); 1333} 1334 1335/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1336/// the desired ByVal argument alignment. 1337static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1338 if (MaxAlign == 16) 1339 return; 1340 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1341 if (VTy->getBitWidth() == 128) 1342 MaxAlign = 16; 1343 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1344 unsigned EltAlign = 0; 1345 getMaxByValAlign(ATy->getElementType(), EltAlign); 1346 if (EltAlign > MaxAlign) 1347 MaxAlign = EltAlign; 1348 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1349 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1350 unsigned EltAlign = 0; 1351 getMaxByValAlign(STy->getElementType(i), EltAlign); 1352 if (EltAlign > MaxAlign) 1353 MaxAlign = EltAlign; 1354 if (MaxAlign == 16) 1355 break; 1356 } 1357 } 1358} 1359 1360/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1361/// function arguments in the caller parameter area. For X86, aggregates 1362/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1363/// are at 4-byte boundaries. 1364unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1365 if (Subtarget->is64Bit()) { 1366 // Max of 8 and alignment of type. 1367 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1368 if (TyAlign > 8) 1369 return TyAlign; 1370 return 8; 1371 } 1372 1373 unsigned Align = 4; 1374 if (Subtarget->hasSSE1()) 1375 getMaxByValAlign(Ty, Align); 1376 return Align; 1377} 1378 1379/// getOptimalMemOpType - Returns the target specific optimal type for load 1380/// and store operations as a result of memset, memcpy, and memmove 1381/// lowering. If DstAlign is zero that means it's safe to destination 1382/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1383/// means there isn't a need to check it against alignment requirement, 1384/// probably because the source does not need to be loaded. If 'IsMemset' is 1385/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 1386/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 1387/// source is constant so it does not need to be loaded. 1388/// It returns EVT::Other if the type should be determined using generic 1389/// target-independent logic. 1390EVT 1391X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1392 unsigned DstAlign, unsigned SrcAlign, 1393 bool IsMemset, bool ZeroMemset, 1394 bool MemcpyStrSrc, 1395 MachineFunction &MF) const { 1396 const Function *F = MF.getFunction(); 1397 if ((!IsMemset || ZeroMemset) && 1398 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 1399 Attribute::NoImplicitFloat)) { 1400 if (Size >= 16 && 1401 (Subtarget->isUnalignedMemAccessFast() || 1402 ((DstAlign == 0 || DstAlign >= 16) && 1403 (SrcAlign == 0 || SrcAlign >= 16)))) { 1404 if (Size >= 32) { 1405 if (Subtarget->hasInt256()) 1406 return MVT::v8i32; 1407 if (Subtarget->hasFp256()) 1408 return MVT::v8f32; 1409 } 1410 if (Subtarget->hasSSE2()) 1411 return MVT::v4i32; 1412 if (Subtarget->hasSSE1()) 1413 return MVT::v4f32; 1414 } else if (!MemcpyStrSrc && Size >= 8 && 1415 !Subtarget->is64Bit() && 1416 Subtarget->hasSSE2()) { 1417 // Do not use f64 to lower memcpy if source is string constant. It's 1418 // better to use i32 to avoid the loads. 1419 return MVT::f64; 1420 } 1421 } 1422 if (Subtarget->is64Bit() && Size >= 8) 1423 return MVT::i64; 1424 return MVT::i32; 1425} 1426 1427bool X86TargetLowering::isSafeMemOpType(MVT VT) const { 1428 if (VT == MVT::f32) 1429 return X86ScalarSSEf32; 1430 else if (VT == MVT::f64) 1431 return X86ScalarSSEf64; 1432 return true; 1433} 1434 1435bool 1436X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 1437 if (Fast) 1438 *Fast = Subtarget->isUnalignedMemAccessFast(); 1439 return true; 1440} 1441 1442/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1443/// current function. The returned value is a member of the 1444/// MachineJumpTableInfo::JTEntryKind enum. 1445unsigned X86TargetLowering::getJumpTableEncoding() const { 1446 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1447 // symbol. 1448 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1449 Subtarget->isPICStyleGOT()) 1450 return MachineJumpTableInfo::EK_Custom32; 1451 1452 // Otherwise, use the normal jump table encoding heuristics. 1453 return TargetLowering::getJumpTableEncoding(); 1454} 1455 1456const MCExpr * 1457X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1458 const MachineBasicBlock *MBB, 1459 unsigned uid,MCContext &Ctx) const{ 1460 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1461 Subtarget->isPICStyleGOT()); 1462 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1463 // entries. 1464 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1465 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1466} 1467 1468/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1469/// jumptable. 1470SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1471 SelectionDAG &DAG) const { 1472 if (!Subtarget->is64Bit()) 1473 // This doesn't have DebugLoc associated with it, but is not really the 1474 // same as a Register. 1475 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1476 return Table; 1477} 1478 1479/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1480/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1481/// MCExpr. 1482const MCExpr *X86TargetLowering:: 1483getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1484 MCContext &Ctx) const { 1485 // X86-64 uses RIP relative addressing based on the jump table label. 1486 if (Subtarget->isPICStyleRIPRel()) 1487 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1488 1489 // Otherwise, the reference is relative to the PIC base. 1490 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1491} 1492 1493// FIXME: Why this routine is here? Move to RegInfo! 1494std::pair<const TargetRegisterClass*, uint8_t> 1495X86TargetLowering::findRepresentativeClass(MVT VT) const{ 1496 const TargetRegisterClass *RRC = 0; 1497 uint8_t Cost = 1; 1498 switch (VT.SimpleTy) { 1499 default: 1500 return TargetLowering::findRepresentativeClass(VT); 1501 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1502 RRC = Subtarget->is64Bit() ? 1503 (const TargetRegisterClass*)&X86::GR64RegClass : 1504 (const TargetRegisterClass*)&X86::GR32RegClass; 1505 break; 1506 case MVT::x86mmx: 1507 RRC = &X86::VR64RegClass; 1508 break; 1509 case MVT::f32: case MVT::f64: 1510 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1511 case MVT::v4f32: case MVT::v2f64: 1512 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1513 case MVT::v4f64: 1514 RRC = &X86::VR128RegClass; 1515 break; 1516 } 1517 return std::make_pair(RRC, Cost); 1518} 1519 1520bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1521 unsigned &Offset) const { 1522 if (!Subtarget->isTargetLinux()) 1523 return false; 1524 1525 if (Subtarget->is64Bit()) { 1526 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1527 Offset = 0x28; 1528 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1529 AddressSpace = 256; 1530 else 1531 AddressSpace = 257; 1532 } else { 1533 // %gs:0x14 on i386 1534 Offset = 0x14; 1535 AddressSpace = 256; 1536 } 1537 return true; 1538} 1539 1540//===----------------------------------------------------------------------===// 1541// Return Value Calling Convention Implementation 1542//===----------------------------------------------------------------------===// 1543 1544#include "X86GenCallingConv.inc" 1545 1546bool 1547X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1548 MachineFunction &MF, bool isVarArg, 1549 const SmallVectorImpl<ISD::OutputArg> &Outs, 1550 LLVMContext &Context) const { 1551 SmallVector<CCValAssign, 16> RVLocs; 1552 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1553 RVLocs, Context); 1554 return CCInfo.CheckReturn(Outs, RetCC_X86); 1555} 1556 1557SDValue 1558X86TargetLowering::LowerReturn(SDValue Chain, 1559 CallingConv::ID CallConv, bool isVarArg, 1560 const SmallVectorImpl<ISD::OutputArg> &Outs, 1561 const SmallVectorImpl<SDValue> &OutVals, 1562 DebugLoc dl, SelectionDAG &DAG) const { 1563 MachineFunction &MF = DAG.getMachineFunction(); 1564 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1565 1566 SmallVector<CCValAssign, 16> RVLocs; 1567 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1568 RVLocs, *DAG.getContext()); 1569 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1570 1571 // Add the regs to the liveout set for the function. 1572 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1573 for (unsigned i = 0; i != RVLocs.size(); ++i) 1574 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1575 MRI.addLiveOut(RVLocs[i].getLocReg()); 1576 1577 SDValue Flag; 1578 1579 SmallVector<SDValue, 6> RetOps; 1580 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1581 // Operand #1 = Bytes To Pop 1582 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1583 MVT::i16)); 1584 1585 // Copy the result values into the output registers. 1586 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1587 CCValAssign &VA = RVLocs[i]; 1588 assert(VA.isRegLoc() && "Can only return in registers!"); 1589 SDValue ValToCopy = OutVals[i]; 1590 EVT ValVT = ValToCopy.getValueType(); 1591 1592 // Promote values to the appropriate types 1593 if (VA.getLocInfo() == CCValAssign::SExt) 1594 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1595 else if (VA.getLocInfo() == CCValAssign::ZExt) 1596 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1597 else if (VA.getLocInfo() == CCValAssign::AExt) 1598 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1599 else if (VA.getLocInfo() == CCValAssign::BCvt) 1600 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); 1601 1602 // If this is x86-64, and we disabled SSE, we can't return FP values, 1603 // or SSE or MMX vectors. 1604 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1605 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1606 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1607 report_fatal_error("SSE register return with SSE disabled"); 1608 } 1609 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1610 // llvm-gcc has never done it right and no one has noticed, so this 1611 // should be OK for now. 1612 if (ValVT == MVT::f64 && 1613 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1614 report_fatal_error("SSE2 register return with SSE2 disabled"); 1615 1616 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1617 // the RET instruction and handled by the FP Stackifier. 1618 if (VA.getLocReg() == X86::ST0 || 1619 VA.getLocReg() == X86::ST1) { 1620 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1621 // change the value to the FP stack register class. 1622 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1623 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1624 RetOps.push_back(ValToCopy); 1625 // Don't emit a copytoreg. 1626 continue; 1627 } 1628 1629 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1630 // which is returned in RAX / RDX. 1631 if (Subtarget->is64Bit()) { 1632 if (ValVT == MVT::x86mmx) { 1633 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1634 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1635 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1636 ValToCopy); 1637 // If we don't have SSE2 available, convert to v4f32 so the generated 1638 // register is legal. 1639 if (!Subtarget->hasSSE2()) 1640 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1641 } 1642 } 1643 } 1644 1645 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1646 Flag = Chain.getValue(1); 1647 } 1648 1649 // The x86-64 ABI for returning structs by value requires that we copy 1650 // the sret argument into %rax for the return. We saved the argument into 1651 // a virtual register in the entry block, so now we copy the value out 1652 // and into %rax. 1653 if (Subtarget->is64Bit() && 1654 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1655 MachineFunction &MF = DAG.getMachineFunction(); 1656 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1657 unsigned Reg = FuncInfo->getSRetReturnReg(); 1658 assert(Reg && 1659 "SRetReturnReg should have been set in LowerFormalArguments()."); 1660 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1661 1662 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1663 Flag = Chain.getValue(1); 1664 1665 // RAX now acts like a return value. 1666 MRI.addLiveOut(X86::RAX); 1667 } 1668 1669 RetOps[0] = Chain; // Update chain. 1670 1671 // Add the flag if we have it. 1672 if (Flag.getNode()) 1673 RetOps.push_back(Flag); 1674 1675 return DAG.getNode(X86ISD::RET_FLAG, dl, 1676 MVT::Other, &RetOps[0], RetOps.size()); 1677} 1678 1679bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1680 if (N->getNumValues() != 1) 1681 return false; 1682 if (!N->hasNUsesOfValue(1, 0)) 1683 return false; 1684 1685 SDValue TCChain = Chain; 1686 SDNode *Copy = *N->use_begin(); 1687 if (Copy->getOpcode() == ISD::CopyToReg) { 1688 // If the copy has a glue operand, we conservatively assume it isn't safe to 1689 // perform a tail call. 1690 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1691 return false; 1692 TCChain = Copy->getOperand(0); 1693 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1694 return false; 1695 1696 bool HasRet = false; 1697 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1698 UI != UE; ++UI) { 1699 if (UI->getOpcode() != X86ISD::RET_FLAG) 1700 return false; 1701 HasRet = true; 1702 } 1703 1704 if (!HasRet) 1705 return false; 1706 1707 Chain = TCChain; 1708 return true; 1709} 1710 1711MVT 1712X86TargetLowering::getTypeForExtArgOrReturn(MVT VT, 1713 ISD::NodeType ExtendKind) const { 1714 MVT ReturnMVT; 1715 // TODO: Is this also valid on 32-bit? 1716 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1717 ReturnMVT = MVT::i8; 1718 else 1719 ReturnMVT = MVT::i32; 1720 1721 MVT MinVT = getRegisterType(ReturnMVT); 1722 return VT.bitsLT(MinVT) ? MinVT : VT; 1723} 1724 1725/// LowerCallResult - Lower the result values of a call into the 1726/// appropriate copies out of appropriate physical registers. 1727/// 1728SDValue 1729X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1730 CallingConv::ID CallConv, bool isVarArg, 1731 const SmallVectorImpl<ISD::InputArg> &Ins, 1732 DebugLoc dl, SelectionDAG &DAG, 1733 SmallVectorImpl<SDValue> &InVals) const { 1734 1735 // Assign locations to each value returned by this call. 1736 SmallVector<CCValAssign, 16> RVLocs; 1737 bool Is64Bit = Subtarget->is64Bit(); 1738 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1739 getTargetMachine(), RVLocs, *DAG.getContext()); 1740 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1741 1742 // Copy all of the result registers out of their specified physreg. 1743 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1744 CCValAssign &VA = RVLocs[i]; 1745 EVT CopyVT = VA.getValVT(); 1746 1747 // If this is x86-64, and we disabled SSE, we can't return FP values 1748 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1749 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1750 report_fatal_error("SSE register return with SSE disabled"); 1751 } 1752 1753 SDValue Val; 1754 1755 // If this is a call to a function that returns an fp value on the floating 1756 // point stack, we must guarantee the value is popped from the stack, so 1757 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1758 // if the return value is not used. We use the FpPOP_RETVAL instruction 1759 // instead. 1760 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1761 // If we prefer to use the value in xmm registers, copy it out as f80 and 1762 // use a truncate to move it from fp stack reg to xmm reg. 1763 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1764 SDValue Ops[] = { Chain, InFlag }; 1765 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1766 MVT::Other, MVT::Glue, Ops, 2), 1); 1767 Val = Chain.getValue(0); 1768 1769 // Round the f80 to the right size, which also moves it to the appropriate 1770 // xmm register. 1771 if (CopyVT != VA.getValVT()) 1772 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1773 // This truncation won't change the value. 1774 DAG.getIntPtrConstant(1)); 1775 } else { 1776 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1777 CopyVT, InFlag).getValue(1); 1778 Val = Chain.getValue(0); 1779 } 1780 InFlag = Chain.getValue(2); 1781 InVals.push_back(Val); 1782 } 1783 1784 return Chain; 1785} 1786 1787//===----------------------------------------------------------------------===// 1788// C & StdCall & Fast Calling Convention implementation 1789//===----------------------------------------------------------------------===// 1790// StdCall calling convention seems to be standard for many Windows' API 1791// routines and around. It differs from C calling convention just a little: 1792// callee should clean up the stack, not caller. Symbols should be also 1793// decorated in some fancy way :) It doesn't support any vector arguments. 1794// For info on fast calling convention see Fast Calling Convention (tail call) 1795// implementation LowerX86_32FastCCCallTo. 1796 1797/// CallIsStructReturn - Determines whether a call uses struct return 1798/// semantics. 1799enum StructReturnType { 1800 NotStructReturn, 1801 RegStructReturn, 1802 StackStructReturn 1803}; 1804static StructReturnType 1805callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1806 if (Outs.empty()) 1807 return NotStructReturn; 1808 1809 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; 1810 if (!Flags.isSRet()) 1811 return NotStructReturn; 1812 if (Flags.isInReg()) 1813 return RegStructReturn; 1814 return StackStructReturn; 1815} 1816 1817/// ArgsAreStructReturn - Determines whether a function uses struct 1818/// return semantics. 1819static StructReturnType 1820argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1821 if (Ins.empty()) 1822 return NotStructReturn; 1823 1824 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; 1825 if (!Flags.isSRet()) 1826 return NotStructReturn; 1827 if (Flags.isInReg()) 1828 return RegStructReturn; 1829 return StackStructReturn; 1830} 1831 1832/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1833/// by "Src" to address "Dst" with size and alignment information specified by 1834/// the specific parameter attribute. The copy will be passed as a byval 1835/// function parameter. 1836static SDValue 1837CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1838 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1839 DebugLoc dl) { 1840 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1841 1842 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1843 /*isVolatile*/false, /*AlwaysInline=*/true, 1844 MachinePointerInfo(), MachinePointerInfo()); 1845} 1846 1847/// IsTailCallConvention - Return true if the calling convention is one that 1848/// supports tail call optimization. 1849static bool IsTailCallConvention(CallingConv::ID CC) { 1850 return (CC == CallingConv::Fast || CC == CallingConv::GHC || 1851 CC == CallingConv::HiPE); 1852} 1853 1854bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1855 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1856 return false; 1857 1858 CallSite CS(CI); 1859 CallingConv::ID CalleeCC = CS.getCallingConv(); 1860 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1861 return false; 1862 1863 return true; 1864} 1865 1866/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1867/// a tailcall target by changing its ABI. 1868static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1869 bool GuaranteedTailCallOpt) { 1870 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1871} 1872 1873SDValue 1874X86TargetLowering::LowerMemArgument(SDValue Chain, 1875 CallingConv::ID CallConv, 1876 const SmallVectorImpl<ISD::InputArg> &Ins, 1877 DebugLoc dl, SelectionDAG &DAG, 1878 const CCValAssign &VA, 1879 MachineFrameInfo *MFI, 1880 unsigned i) const { 1881 // Create the nodes corresponding to a load from this parameter slot. 1882 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1883 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1884 getTargetMachine().Options.GuaranteedTailCallOpt); 1885 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1886 EVT ValVT; 1887 1888 // If value is passed by pointer we have address passed instead of the value 1889 // itself. 1890 if (VA.getLocInfo() == CCValAssign::Indirect) 1891 ValVT = VA.getLocVT(); 1892 else 1893 ValVT = VA.getValVT(); 1894 1895 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1896 // changed with more analysis. 1897 // In case of tail call optimization mark all arguments mutable. Since they 1898 // could be overwritten by lowering of arguments in case of a tail call. 1899 if (Flags.isByVal()) { 1900 unsigned Bytes = Flags.getByValSize(); 1901 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1902 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1903 return DAG.getFrameIndex(FI, getPointerTy()); 1904 } else { 1905 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1906 VA.getLocMemOffset(), isImmutable); 1907 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1908 return DAG.getLoad(ValVT, dl, Chain, FIN, 1909 MachinePointerInfo::getFixedStack(FI), 1910 false, false, false, 0); 1911 } 1912} 1913 1914SDValue 1915X86TargetLowering::LowerFormalArguments(SDValue Chain, 1916 CallingConv::ID CallConv, 1917 bool isVarArg, 1918 const SmallVectorImpl<ISD::InputArg> &Ins, 1919 DebugLoc dl, 1920 SelectionDAG &DAG, 1921 SmallVectorImpl<SDValue> &InVals) 1922 const { 1923 MachineFunction &MF = DAG.getMachineFunction(); 1924 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1925 1926 const Function* Fn = MF.getFunction(); 1927 if (Fn->hasExternalLinkage() && 1928 Subtarget->isTargetCygMing() && 1929 Fn->getName() == "main") 1930 FuncInfo->setForceFramePointer(true); 1931 1932 MachineFrameInfo *MFI = MF.getFrameInfo(); 1933 bool Is64Bit = Subtarget->is64Bit(); 1934 bool IsWindows = Subtarget->isTargetWindows(); 1935 bool IsWin64 = Subtarget->isTargetWin64(); 1936 1937 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1938 "Var args not supported with calling convention fastcc, ghc or hipe"); 1939 1940 // Assign locations to all of the incoming arguments. 1941 SmallVector<CCValAssign, 16> ArgLocs; 1942 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1943 ArgLocs, *DAG.getContext()); 1944 1945 // Allocate shadow area for Win64 1946 if (IsWin64) { 1947 CCInfo.AllocateStack(32, 8); 1948 } 1949 1950 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1951 1952 unsigned LastVal = ~0U; 1953 SDValue ArgValue; 1954 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1955 CCValAssign &VA = ArgLocs[i]; 1956 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1957 // places. 1958 assert(VA.getValNo() != LastVal && 1959 "Don't support value assigned to multiple locs yet"); 1960 (void)LastVal; 1961 LastVal = VA.getValNo(); 1962 1963 if (VA.isRegLoc()) { 1964 EVT RegVT = VA.getLocVT(); 1965 const TargetRegisterClass *RC; 1966 if (RegVT == MVT::i32) 1967 RC = &X86::GR32RegClass; 1968 else if (Is64Bit && RegVT == MVT::i64) 1969 RC = &X86::GR64RegClass; 1970 else if (RegVT == MVT::f32) 1971 RC = &X86::FR32RegClass; 1972 else if (RegVT == MVT::f64) 1973 RC = &X86::FR64RegClass; 1974 else if (RegVT.is256BitVector()) 1975 RC = &X86::VR256RegClass; 1976 else if (RegVT.is128BitVector()) 1977 RC = &X86::VR128RegClass; 1978 else if (RegVT == MVT::x86mmx) 1979 RC = &X86::VR64RegClass; 1980 else 1981 llvm_unreachable("Unknown argument type!"); 1982 1983 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1984 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1985 1986 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1987 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1988 // right size. 1989 if (VA.getLocInfo() == CCValAssign::SExt) 1990 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1991 DAG.getValueType(VA.getValVT())); 1992 else if (VA.getLocInfo() == CCValAssign::ZExt) 1993 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1994 DAG.getValueType(VA.getValVT())); 1995 else if (VA.getLocInfo() == CCValAssign::BCvt) 1996 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1997 1998 if (VA.isExtInLoc()) { 1999 // Handle MMX values passed in XMM regs. 2000 if (RegVT.isVector()) 2001 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue); 2002 else 2003 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2004 } 2005 } else { 2006 assert(VA.isMemLoc()); 2007 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 2008 } 2009 2010 // If value is passed via pointer - do a load. 2011 if (VA.getLocInfo() == CCValAssign::Indirect) 2012 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 2013 MachinePointerInfo(), false, false, false, 0); 2014 2015 InVals.push_back(ArgValue); 2016 } 2017 2018 // The x86-64 ABI for returning structs by value requires that we copy 2019 // the sret argument into %rax for the return. Save the argument into 2020 // a virtual register so that we can access it from the return points. 2021 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 2022 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2023 unsigned Reg = FuncInfo->getSRetReturnReg(); 2024 if (!Reg) { 2025 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 2026 FuncInfo->setSRetReturnReg(Reg); 2027 } 2028 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2029 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2030 } 2031 2032 unsigned StackSize = CCInfo.getNextStackOffset(); 2033 // Align stack specially for tail calls. 2034 if (FuncIsMadeTailCallSafe(CallConv, 2035 MF.getTarget().Options.GuaranteedTailCallOpt)) 2036 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 2037 2038 // If the function takes variable number of arguments, make a frame index for 2039 // the start of the first vararg value... for expansion of llvm.va_start. 2040 if (isVarArg) { 2041 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 2042 CallConv != CallingConv::X86_ThisCall)) { 2043 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 2044 } 2045 if (Is64Bit) { 2046 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 2047 2048 // FIXME: We should really autogenerate these arrays 2049 static const uint16_t GPR64ArgRegsWin64[] = { 2050 X86::RCX, X86::RDX, X86::R8, X86::R9 2051 }; 2052 static const uint16_t GPR64ArgRegs64Bit[] = { 2053 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 2054 }; 2055 static const uint16_t XMMArgRegs64Bit[] = { 2056 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2057 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2058 }; 2059 const uint16_t *GPR64ArgRegs; 2060 unsigned NumXMMRegs = 0; 2061 2062 if (IsWin64) { 2063 // The XMM registers which might contain var arg parameters are shadowed 2064 // in their paired GPR. So we only need to save the GPR to their home 2065 // slots. 2066 TotalNumIntRegs = 4; 2067 GPR64ArgRegs = GPR64ArgRegsWin64; 2068 } else { 2069 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 2070 GPR64ArgRegs = GPR64ArgRegs64Bit; 2071 2072 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 2073 TotalNumXMMRegs); 2074 } 2075 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 2076 TotalNumIntRegs); 2077 2078 bool NoImplicitFloatOps = Fn->getAttributes(). 2079 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 2080 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 2081 "SSE register cannot be used when SSE is disabled!"); 2082 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 2083 NoImplicitFloatOps) && 2084 "SSE register cannot be used when SSE is disabled!"); 2085 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 2086 !Subtarget->hasSSE1()) 2087 // Kernel mode asks for SSE to be disabled, so don't push them 2088 // on the stack. 2089 TotalNumXMMRegs = 0; 2090 2091 if (IsWin64) { 2092 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 2093 // Get to the caller-allocated home save location. Add 8 to account 2094 // for the return address. 2095 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 2096 FuncInfo->setRegSaveFrameIndex( 2097 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 2098 // Fixup to set vararg frame on shadow area (4 x i64). 2099 if (NumIntRegs < 4) 2100 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 2101 } else { 2102 // For X86-64, if there are vararg parameters that are passed via 2103 // registers, then we must store them to their spots on the stack so 2104 // they may be loaded by deferencing the result of va_next. 2105 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 2106 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 2107 FuncInfo->setRegSaveFrameIndex( 2108 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 2109 false)); 2110 } 2111 2112 // Store the integer parameter registers. 2113 SmallVector<SDValue, 8> MemOps; 2114 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2115 getPointerTy()); 2116 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2117 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2118 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2119 DAG.getIntPtrConstant(Offset)); 2120 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2121 &X86::GR64RegClass); 2122 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2123 SDValue Store = 2124 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2125 MachinePointerInfo::getFixedStack( 2126 FuncInfo->getRegSaveFrameIndex(), Offset), 2127 false, false, 0); 2128 MemOps.push_back(Store); 2129 Offset += 8; 2130 } 2131 2132 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2133 // Now store the XMM (fp + vector) parameter registers. 2134 SmallVector<SDValue, 11> SaveXMMOps; 2135 SaveXMMOps.push_back(Chain); 2136 2137 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2138 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2139 SaveXMMOps.push_back(ALVal); 2140 2141 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2142 FuncInfo->getRegSaveFrameIndex())); 2143 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2144 FuncInfo->getVarArgsFPOffset())); 2145 2146 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2147 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2148 &X86::VR128RegClass); 2149 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2150 SaveXMMOps.push_back(Val); 2151 } 2152 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2153 MVT::Other, 2154 &SaveXMMOps[0], SaveXMMOps.size())); 2155 } 2156 2157 if (!MemOps.empty()) 2158 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2159 &MemOps[0], MemOps.size()); 2160 } 2161 } 2162 2163 // Some CCs need callee pop. 2164 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2165 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2166 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2167 } else { 2168 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2169 // If this is an sret function, the return should pop the hidden pointer. 2170 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2171 argsAreStructReturn(Ins) == StackStructReturn) 2172 FuncInfo->setBytesToPopOnReturn(4); 2173 } 2174 2175 if (!Is64Bit) { 2176 // RegSaveFrameIndex is X86-64 only. 2177 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2178 if (CallConv == CallingConv::X86_FastCall || 2179 CallConv == CallingConv::X86_ThisCall) 2180 // fastcc functions can't have varargs. 2181 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2182 } 2183 2184 FuncInfo->setArgumentStackSize(StackSize); 2185 2186 return Chain; 2187} 2188 2189SDValue 2190X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2191 SDValue StackPtr, SDValue Arg, 2192 DebugLoc dl, SelectionDAG &DAG, 2193 const CCValAssign &VA, 2194 ISD::ArgFlagsTy Flags) const { 2195 unsigned LocMemOffset = VA.getLocMemOffset(); 2196 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2197 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2198 if (Flags.isByVal()) 2199 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2200 2201 return DAG.getStore(Chain, dl, Arg, PtrOff, 2202 MachinePointerInfo::getStack(LocMemOffset), 2203 false, false, 0); 2204} 2205 2206/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2207/// optimization is performed and it is required. 2208SDValue 2209X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2210 SDValue &OutRetAddr, SDValue Chain, 2211 bool IsTailCall, bool Is64Bit, 2212 int FPDiff, DebugLoc dl) const { 2213 // Adjust the Return address stack slot. 2214 EVT VT = getPointerTy(); 2215 OutRetAddr = getReturnAddressFrameIndex(DAG); 2216 2217 // Load the "old" Return address. 2218 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2219 false, false, false, 0); 2220 return SDValue(OutRetAddr.getNode(), 1); 2221} 2222 2223/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2224/// optimization is performed and it is required (FPDiff!=0). 2225static SDValue 2226EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2227 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, 2228 unsigned SlotSize, int FPDiff, DebugLoc dl) { 2229 // Store the return address to the appropriate stack slot. 2230 if (!FPDiff) return Chain; 2231 // Calculate the new stack slot for the return address. 2232 int NewReturnAddrFI = 2233 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2234 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT); 2235 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2236 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2237 false, false, 0); 2238 return Chain; 2239} 2240 2241SDValue 2242X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2243 SmallVectorImpl<SDValue> &InVals) const { 2244 SelectionDAG &DAG = CLI.DAG; 2245 DebugLoc &dl = CLI.DL; 2246 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2247 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2248 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2249 SDValue Chain = CLI.Chain; 2250 SDValue Callee = CLI.Callee; 2251 CallingConv::ID CallConv = CLI.CallConv; 2252 bool &isTailCall = CLI.IsTailCall; 2253 bool isVarArg = CLI.IsVarArg; 2254 2255 MachineFunction &MF = DAG.getMachineFunction(); 2256 bool Is64Bit = Subtarget->is64Bit(); 2257 bool IsWin64 = Subtarget->isTargetWin64(); 2258 bool IsWindows = Subtarget->isTargetWindows(); 2259 StructReturnType SR = callIsStructReturn(Outs); 2260 bool IsSibcall = false; 2261 2262 if (MF.getTarget().Options.DisableTailCalls) 2263 isTailCall = false; 2264 2265 if (isTailCall) { 2266 // Check if it's really possible to do a tail call. 2267 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2268 isVarArg, SR != NotStructReturn, 2269 MF.getFunction()->hasStructRetAttr(), CLI.RetTy, 2270 Outs, OutVals, Ins, DAG); 2271 2272 // Sibcalls are automatically detected tailcalls which do not require 2273 // ABI changes. 2274 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2275 IsSibcall = true; 2276 2277 if (isTailCall) 2278 ++NumTailCalls; 2279 } 2280 2281 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2282 "Var args not supported with calling convention fastcc, ghc or hipe"); 2283 2284 // Analyze operands of the call, assigning locations to each operand. 2285 SmallVector<CCValAssign, 16> ArgLocs; 2286 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2287 ArgLocs, *DAG.getContext()); 2288 2289 // Allocate shadow area for Win64 2290 if (IsWin64) { 2291 CCInfo.AllocateStack(32, 8); 2292 } 2293 2294 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2295 2296 // Get a count of how many bytes are to be pushed on the stack. 2297 unsigned NumBytes = CCInfo.getNextStackOffset(); 2298 if (IsSibcall) 2299 // This is a sibcall. The memory operands are available in caller's 2300 // own caller's stack. 2301 NumBytes = 0; 2302 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2303 IsTailCallConvention(CallConv)) 2304 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2305 2306 int FPDiff = 0; 2307 if (isTailCall && !IsSibcall) { 2308 // Lower arguments at fp - stackoffset + fpdiff. 2309 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>(); 2310 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn(); 2311 2312 FPDiff = NumBytesCallerPushed - NumBytes; 2313 2314 // Set the delta of movement of the returnaddr stackslot. 2315 // But only set if delta is greater than previous delta. 2316 if (FPDiff < X86Info->getTCReturnAddrDelta()) 2317 X86Info->setTCReturnAddrDelta(FPDiff); 2318 } 2319 2320 if (!IsSibcall) 2321 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2322 2323 SDValue RetAddrFrIdx; 2324 // Load return address for tail calls. 2325 if (isTailCall && FPDiff) 2326 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2327 Is64Bit, FPDiff, dl); 2328 2329 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2330 SmallVector<SDValue, 8> MemOpChains; 2331 SDValue StackPtr; 2332 2333 // Walk the register/memloc assignments, inserting copies/loads. In the case 2334 // of tail call optimization arguments are handle later. 2335 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2336 CCValAssign &VA = ArgLocs[i]; 2337 EVT RegVT = VA.getLocVT(); 2338 SDValue Arg = OutVals[i]; 2339 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2340 bool isByVal = Flags.isByVal(); 2341 2342 // Promote the value if needed. 2343 switch (VA.getLocInfo()) { 2344 default: llvm_unreachable("Unknown loc info!"); 2345 case CCValAssign::Full: break; 2346 case CCValAssign::SExt: 2347 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2348 break; 2349 case CCValAssign::ZExt: 2350 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2351 break; 2352 case CCValAssign::AExt: 2353 if (RegVT.is128BitVector()) { 2354 // Special case: passing MMX values in XMM registers. 2355 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2356 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2357 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2358 } else 2359 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2360 break; 2361 case CCValAssign::BCvt: 2362 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2363 break; 2364 case CCValAssign::Indirect: { 2365 // Store the argument. 2366 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2367 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2368 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2369 MachinePointerInfo::getFixedStack(FI), 2370 false, false, 0); 2371 Arg = SpillSlot; 2372 break; 2373 } 2374 } 2375 2376 if (VA.isRegLoc()) { 2377 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2378 if (isVarArg && IsWin64) { 2379 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2380 // shadow reg if callee is a varargs function. 2381 unsigned ShadowReg = 0; 2382 switch (VA.getLocReg()) { 2383 case X86::XMM0: ShadowReg = X86::RCX; break; 2384 case X86::XMM1: ShadowReg = X86::RDX; break; 2385 case X86::XMM2: ShadowReg = X86::R8; break; 2386 case X86::XMM3: ShadowReg = X86::R9; break; 2387 } 2388 if (ShadowReg) 2389 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2390 } 2391 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2392 assert(VA.isMemLoc()); 2393 if (StackPtr.getNode() == 0) 2394 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), 2395 getPointerTy()); 2396 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2397 dl, DAG, VA, Flags)); 2398 } 2399 } 2400 2401 if (!MemOpChains.empty()) 2402 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2403 &MemOpChains[0], MemOpChains.size()); 2404 2405 if (Subtarget->isPICStyleGOT()) { 2406 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2407 // GOT pointer. 2408 if (!isTailCall) { 2409 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX), 2410 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()))); 2411 } else { 2412 // If we are tail calling and generating PIC/GOT style code load the 2413 // address of the callee into ECX. The value in ecx is used as target of 2414 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2415 // for tail calls on PIC/GOT architectures. Normally we would just put the 2416 // address of GOT into ebx and then call target@PLT. But for tail calls 2417 // ebx would be restored (since ebx is callee saved) before jumping to the 2418 // target@PLT. 2419 2420 // Note: The actual moving to ECX is done further down. 2421 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2422 if (G && !G->getGlobal()->hasHiddenVisibility() && 2423 !G->getGlobal()->hasProtectedVisibility()) 2424 Callee = LowerGlobalAddress(Callee, DAG); 2425 else if (isa<ExternalSymbolSDNode>(Callee)) 2426 Callee = LowerExternalSymbol(Callee, DAG); 2427 } 2428 } 2429 2430 if (Is64Bit && isVarArg && !IsWin64) { 2431 // From AMD64 ABI document: 2432 // For calls that may call functions that use varargs or stdargs 2433 // (prototype-less calls or calls to functions containing ellipsis (...) in 2434 // the declaration) %al is used as hidden argument to specify the number 2435 // of SSE registers used. The contents of %al do not need to match exactly 2436 // the number of registers, but must be an ubound on the number of SSE 2437 // registers used and is in the range 0 - 8 inclusive. 2438 2439 // Count the number of XMM registers allocated. 2440 static const uint16_t XMMArgRegs[] = { 2441 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2442 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2443 }; 2444 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2445 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2446 && "SSE registers cannot be used when SSE is disabled"); 2447 2448 RegsToPass.push_back(std::make_pair(unsigned(X86::AL), 2449 DAG.getConstant(NumXMMRegs, MVT::i8))); 2450 } 2451 2452 // For tail calls lower the arguments to the 'real' stack slot. 2453 if (isTailCall) { 2454 // Force all the incoming stack arguments to be loaded from the stack 2455 // before any new outgoing arguments are stored to the stack, because the 2456 // outgoing stack slots may alias the incoming argument stack slots, and 2457 // the alias isn't otherwise explicit. This is slightly more conservative 2458 // than necessary, because it means that each store effectively depends 2459 // on every argument instead of just those arguments it would clobber. 2460 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2461 2462 SmallVector<SDValue, 8> MemOpChains2; 2463 SDValue FIN; 2464 int FI = 0; 2465 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2467 CCValAssign &VA = ArgLocs[i]; 2468 if (VA.isRegLoc()) 2469 continue; 2470 assert(VA.isMemLoc()); 2471 SDValue Arg = OutVals[i]; 2472 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2473 // Create frame index. 2474 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2475 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2476 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2477 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2478 2479 if (Flags.isByVal()) { 2480 // Copy relative to framepointer. 2481 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2482 if (StackPtr.getNode() == 0) 2483 StackPtr = DAG.getCopyFromReg(Chain, dl, 2484 RegInfo->getStackRegister(), 2485 getPointerTy()); 2486 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2487 2488 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2489 ArgChain, 2490 Flags, DAG, dl)); 2491 } else { 2492 // Store relative to framepointer. 2493 MemOpChains2.push_back( 2494 DAG.getStore(ArgChain, dl, Arg, FIN, 2495 MachinePointerInfo::getFixedStack(FI), 2496 false, false, 0)); 2497 } 2498 } 2499 } 2500 2501 if (!MemOpChains2.empty()) 2502 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2503 &MemOpChains2[0], MemOpChains2.size()); 2504 2505 // Store the return address to the appropriate stack slot. 2506 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, 2507 getPointerTy(), RegInfo->getSlotSize(), 2508 FPDiff, dl); 2509 } 2510 2511 // Build a sequence of copy-to-reg nodes chained together with token chain 2512 // and flag operands which copy the outgoing args into registers. 2513 SDValue InFlag; 2514 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2515 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2516 RegsToPass[i].second, InFlag); 2517 InFlag = Chain.getValue(1); 2518 } 2519 2520 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2521 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2522 // In the 64-bit large code model, we have to make all calls 2523 // through a register, since the call instruction's 32-bit 2524 // pc-relative offset may not be large enough to hold the whole 2525 // address. 2526 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2527 // If the callee is a GlobalAddress node (quite common, every direct call 2528 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2529 // it. 2530 2531 // We should use extra load for direct calls to dllimported functions in 2532 // non-JIT mode. 2533 const GlobalValue *GV = G->getGlobal(); 2534 if (!GV->hasDLLImportLinkage()) { 2535 unsigned char OpFlags = 0; 2536 bool ExtraLoad = false; 2537 unsigned WrapperKind = ISD::DELETED_NODE; 2538 2539 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2540 // external symbols most go through the PLT in PIC mode. If the symbol 2541 // has hidden or protected visibility, or if it is static or local, then 2542 // we don't need to use the PLT - we can directly call it. 2543 if (Subtarget->isTargetELF() && 2544 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2545 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2546 OpFlags = X86II::MO_PLT; 2547 } else if (Subtarget->isPICStyleStubAny() && 2548 (GV->isDeclaration() || GV->isWeakForLinker()) && 2549 (!Subtarget->getTargetTriple().isMacOSX() || 2550 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2551 // PC-relative references to external symbols should go through $stub, 2552 // unless we're building with the leopard linker or later, which 2553 // automatically synthesizes these stubs. 2554 OpFlags = X86II::MO_DARWIN_STUB; 2555 } else if (Subtarget->isPICStyleRIPRel() && 2556 isa<Function>(GV) && 2557 cast<Function>(GV)->getAttributes(). 2558 hasAttribute(AttributeSet::FunctionIndex, 2559 Attribute::NonLazyBind)) { 2560 // If the function is marked as non-lazy, generate an indirect call 2561 // which loads from the GOT directly. This avoids runtime overhead 2562 // at the cost of eager binding (and one extra byte of encoding). 2563 OpFlags = X86II::MO_GOTPCREL; 2564 WrapperKind = X86ISD::WrapperRIP; 2565 ExtraLoad = true; 2566 } 2567 2568 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2569 G->getOffset(), OpFlags); 2570 2571 // Add a wrapper if needed. 2572 if (WrapperKind != ISD::DELETED_NODE) 2573 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2574 // Add extra indirection if needed. 2575 if (ExtraLoad) 2576 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2577 MachinePointerInfo::getGOT(), 2578 false, false, false, 0); 2579 } 2580 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2581 unsigned char OpFlags = 0; 2582 2583 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2584 // external symbols should go through the PLT. 2585 if (Subtarget->isTargetELF() && 2586 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2587 OpFlags = X86II::MO_PLT; 2588 } else if (Subtarget->isPICStyleStubAny() && 2589 (!Subtarget->getTargetTriple().isMacOSX() || 2590 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2591 // PC-relative references to external symbols should go through $stub, 2592 // unless we're building with the leopard linker or later, which 2593 // automatically synthesizes these stubs. 2594 OpFlags = X86II::MO_DARWIN_STUB; 2595 } 2596 2597 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2598 OpFlags); 2599 } 2600 2601 // Returns a chain & a flag for retval copy to use. 2602 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2603 SmallVector<SDValue, 8> Ops; 2604 2605 if (!IsSibcall && isTailCall) { 2606 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2607 DAG.getIntPtrConstant(0, true), InFlag); 2608 InFlag = Chain.getValue(1); 2609 } 2610 2611 Ops.push_back(Chain); 2612 Ops.push_back(Callee); 2613 2614 if (isTailCall) 2615 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2616 2617 // Add argument registers to the end of the list so that they are known live 2618 // into the call. 2619 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2620 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2621 RegsToPass[i].second.getValueType())); 2622 2623 // Add a register mask operand representing the call-preserved registers. 2624 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2625 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2626 assert(Mask && "Missing call preserved mask for calling convention"); 2627 Ops.push_back(DAG.getRegisterMask(Mask)); 2628 2629 if (InFlag.getNode()) 2630 Ops.push_back(InFlag); 2631 2632 if (isTailCall) { 2633 // We used to do: 2634 //// If this is the first return lowered for this function, add the regs 2635 //// to the liveout set for the function. 2636 // This isn't right, although it's probably harmless on x86; liveouts 2637 // should be computed from returns not tail calls. Consider a void 2638 // function making a tail call to a function returning int. 2639 return DAG.getNode(X86ISD::TC_RETURN, dl, 2640 NodeTys, &Ops[0], Ops.size()); 2641 } 2642 2643 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2644 InFlag = Chain.getValue(1); 2645 2646 // Create the CALLSEQ_END node. 2647 unsigned NumBytesForCalleeToPush; 2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2649 getTargetMachine().Options.GuaranteedTailCallOpt)) 2650 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2651 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2652 SR == StackStructReturn) 2653 // If this is a call to a struct-return function, the callee 2654 // pops the hidden struct pointer, so we have to push it back. 2655 // This is common for Darwin/X86, Linux & Mingw32 targets. 2656 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2657 NumBytesForCalleeToPush = 4; 2658 else 2659 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2660 2661 // Returns a flag for retval copy to use. 2662 if (!IsSibcall) { 2663 Chain = DAG.getCALLSEQ_END(Chain, 2664 DAG.getIntPtrConstant(NumBytes, true), 2665 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2666 true), 2667 InFlag); 2668 InFlag = Chain.getValue(1); 2669 } 2670 2671 // Handle result values, copying them out of physregs into vregs that we 2672 // return. 2673 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2674 Ins, dl, DAG, InVals); 2675} 2676 2677//===----------------------------------------------------------------------===// 2678// Fast Calling Convention (tail call) implementation 2679//===----------------------------------------------------------------------===// 2680 2681// Like std call, callee cleans arguments, convention except that ECX is 2682// reserved for storing the tail called function address. Only 2 registers are 2683// free for argument passing (inreg). Tail call optimization is performed 2684// provided: 2685// * tailcallopt is enabled 2686// * caller/callee are fastcc 2687// On X86_64 architecture with GOT-style position independent code only local 2688// (within module) calls are supported at the moment. 2689// To keep the stack aligned according to platform abi the function 2690// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2691// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2692// If a tail called function callee has more arguments than the caller the 2693// caller needs to make sure that there is room to move the RETADDR to. This is 2694// achieved by reserving an area the size of the argument delta right after the 2695// original REtADDR, but before the saved framepointer or the spilled registers 2696// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2697// stack layout: 2698// arg1 2699// arg2 2700// RETADDR 2701// [ new RETADDR 2702// move area ] 2703// (possible EBP) 2704// ESI 2705// EDI 2706// local1 .. 2707 2708/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2709/// for a 16 byte align requirement. 2710unsigned 2711X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2712 SelectionDAG& DAG) const { 2713 MachineFunction &MF = DAG.getMachineFunction(); 2714 const TargetMachine &TM = MF.getTarget(); 2715 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2716 unsigned StackAlignment = TFI.getStackAlignment(); 2717 uint64_t AlignMask = StackAlignment - 1; 2718 int64_t Offset = StackSize; 2719 unsigned SlotSize = RegInfo->getSlotSize(); 2720 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2721 // Number smaller than 12 so just add the difference. 2722 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2723 } else { 2724 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2725 Offset = ((~AlignMask) & Offset) + StackAlignment + 2726 (StackAlignment-SlotSize); 2727 } 2728 return Offset; 2729} 2730 2731/// MatchingStackOffset - Return true if the given stack call argument is 2732/// already available in the same position (relatively) of the caller's 2733/// incoming argument stack. 2734static 2735bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2736 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2737 const X86InstrInfo *TII) { 2738 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2739 int FI = INT_MAX; 2740 if (Arg.getOpcode() == ISD::CopyFromReg) { 2741 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2742 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2743 return false; 2744 MachineInstr *Def = MRI->getVRegDef(VR); 2745 if (!Def) 2746 return false; 2747 if (!Flags.isByVal()) { 2748 if (!TII->isLoadFromStackSlot(Def, FI)) 2749 return false; 2750 } else { 2751 unsigned Opcode = Def->getOpcode(); 2752 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2753 Def->getOperand(1).isFI()) { 2754 FI = Def->getOperand(1).getIndex(); 2755 Bytes = Flags.getByValSize(); 2756 } else 2757 return false; 2758 } 2759 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2760 if (Flags.isByVal()) 2761 // ByVal argument is passed in as a pointer but it's now being 2762 // dereferenced. e.g. 2763 // define @foo(%struct.X* %A) { 2764 // tail call @bar(%struct.X* byval %A) 2765 // } 2766 return false; 2767 SDValue Ptr = Ld->getBasePtr(); 2768 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2769 if (!FINode) 2770 return false; 2771 FI = FINode->getIndex(); 2772 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2773 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2774 FI = FINode->getIndex(); 2775 Bytes = Flags.getByValSize(); 2776 } else 2777 return false; 2778 2779 assert(FI != INT_MAX); 2780 if (!MFI->isFixedObjectIndex(FI)) 2781 return false; 2782 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2783} 2784 2785/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2786/// for tail call optimization. Targets which want to do tail call 2787/// optimization should implement this function. 2788bool 2789X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2790 CallingConv::ID CalleeCC, 2791 bool isVarArg, 2792 bool isCalleeStructRet, 2793 bool isCallerStructRet, 2794 Type *RetTy, 2795 const SmallVectorImpl<ISD::OutputArg> &Outs, 2796 const SmallVectorImpl<SDValue> &OutVals, 2797 const SmallVectorImpl<ISD::InputArg> &Ins, 2798 SelectionDAG& DAG) const { 2799 if (!IsTailCallConvention(CalleeCC) && 2800 CalleeCC != CallingConv::C) 2801 return false; 2802 2803 // If -tailcallopt is specified, make fastcc functions tail-callable. 2804 const MachineFunction &MF = DAG.getMachineFunction(); 2805 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2806 2807 // If the function return type is x86_fp80 and the callee return type is not, 2808 // then the FP_EXTEND of the call result is not a nop. It's not safe to 2809 // perform a tailcall optimization here. 2810 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty()) 2811 return false; 2812 2813 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2814 bool CCMatch = CallerCC == CalleeCC; 2815 2816 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2817 if (IsTailCallConvention(CalleeCC) && CCMatch) 2818 return true; 2819 return false; 2820 } 2821 2822 // Look for obvious safe cases to perform tail call optimization that do not 2823 // require ABI changes. This is what gcc calls sibcall. 2824 2825 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2826 // emit a special epilogue. 2827 if (RegInfo->needsStackRealignment(MF)) 2828 return false; 2829 2830 // Also avoid sibcall optimization if either caller or callee uses struct 2831 // return semantics. 2832 if (isCalleeStructRet || isCallerStructRet) 2833 return false; 2834 2835 // An stdcall caller is expected to clean up its arguments; the callee 2836 // isn't going to do that. 2837 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2838 return false; 2839 2840 // Do not sibcall optimize vararg calls unless all arguments are passed via 2841 // registers. 2842 if (isVarArg && !Outs.empty()) { 2843 2844 // Optimizing for varargs on Win64 is unlikely to be safe without 2845 // additional testing. 2846 if (Subtarget->isTargetWin64()) 2847 return false; 2848 2849 SmallVector<CCValAssign, 16> ArgLocs; 2850 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2851 getTargetMachine(), ArgLocs, *DAG.getContext()); 2852 2853 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2855 if (!ArgLocs[i].isRegLoc()) 2856 return false; 2857 } 2858 2859 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2860 // stack. Therefore, if it's not used by the call it is not safe to optimize 2861 // this into a sibcall. 2862 bool Unused = false; 2863 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2864 if (!Ins[i].Used) { 2865 Unused = true; 2866 break; 2867 } 2868 } 2869 if (Unused) { 2870 SmallVector<CCValAssign, 16> RVLocs; 2871 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2872 getTargetMachine(), RVLocs, *DAG.getContext()); 2873 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2874 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2875 CCValAssign &VA = RVLocs[i]; 2876 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2877 return false; 2878 } 2879 } 2880 2881 // If the calling conventions do not match, then we'd better make sure the 2882 // results are returned in the same way as what the caller expects. 2883 if (!CCMatch) { 2884 SmallVector<CCValAssign, 16> RVLocs1; 2885 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2886 getTargetMachine(), RVLocs1, *DAG.getContext()); 2887 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2888 2889 SmallVector<CCValAssign, 16> RVLocs2; 2890 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2891 getTargetMachine(), RVLocs2, *DAG.getContext()); 2892 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2893 2894 if (RVLocs1.size() != RVLocs2.size()) 2895 return false; 2896 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2897 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2898 return false; 2899 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2900 return false; 2901 if (RVLocs1[i].isRegLoc()) { 2902 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2903 return false; 2904 } else { 2905 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2906 return false; 2907 } 2908 } 2909 } 2910 2911 // If the callee takes no arguments then go on to check the results of the 2912 // call. 2913 if (!Outs.empty()) { 2914 // Check if stack adjustment is needed. For now, do not do this if any 2915 // argument is passed on the stack. 2916 SmallVector<CCValAssign, 16> ArgLocs; 2917 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2918 getTargetMachine(), ArgLocs, *DAG.getContext()); 2919 2920 // Allocate shadow area for Win64 2921 if (Subtarget->isTargetWin64()) { 2922 CCInfo.AllocateStack(32, 8); 2923 } 2924 2925 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2926 if (CCInfo.getNextStackOffset()) { 2927 MachineFunction &MF = DAG.getMachineFunction(); 2928 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2929 return false; 2930 2931 // Check if the arguments are already laid out in the right way as 2932 // the caller's fixed stack objects. 2933 MachineFrameInfo *MFI = MF.getFrameInfo(); 2934 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2935 const X86InstrInfo *TII = 2936 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2937 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2938 CCValAssign &VA = ArgLocs[i]; 2939 SDValue Arg = OutVals[i]; 2940 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2941 if (VA.getLocInfo() == CCValAssign::Indirect) 2942 return false; 2943 if (!VA.isRegLoc()) { 2944 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2945 MFI, MRI, TII)) 2946 return false; 2947 } 2948 } 2949 } 2950 2951 // If the tailcall address may be in a register, then make sure it's 2952 // possible to register allocate for it. In 32-bit, the call address can 2953 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2954 // callee-saved registers are restored. These happen to be the same 2955 // registers used to pass 'inreg' arguments so watch out for those. 2956 if (!Subtarget->is64Bit() && 2957 !isa<GlobalAddressSDNode>(Callee) && 2958 !isa<ExternalSymbolSDNode>(Callee)) { 2959 unsigned NumInRegs = 0; 2960 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2961 CCValAssign &VA = ArgLocs[i]; 2962 if (!VA.isRegLoc()) 2963 continue; 2964 unsigned Reg = VA.getLocReg(); 2965 switch (Reg) { 2966 default: break; 2967 case X86::EAX: case X86::EDX: case X86::ECX: 2968 if (++NumInRegs == 3) 2969 return false; 2970 break; 2971 } 2972 } 2973 } 2974 } 2975 2976 return true; 2977} 2978 2979FastISel * 2980X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 2981 const TargetLibraryInfo *libInfo) const { 2982 return X86::createFastISel(funcInfo, libInfo); 2983} 2984 2985//===----------------------------------------------------------------------===// 2986// Other Lowering Hooks 2987//===----------------------------------------------------------------------===// 2988 2989static bool MayFoldLoad(SDValue Op) { 2990 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2991} 2992 2993static bool MayFoldIntoStore(SDValue Op) { 2994 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2995} 2996 2997static bool isTargetShuffle(unsigned Opcode) { 2998 switch(Opcode) { 2999 default: return false; 3000 case X86ISD::PSHUFD: 3001 case X86ISD::PSHUFHW: 3002 case X86ISD::PSHUFLW: 3003 case X86ISD::SHUFP: 3004 case X86ISD::PALIGN: 3005 case X86ISD::MOVLHPS: 3006 case X86ISD::MOVLHPD: 3007 case X86ISD::MOVHLPS: 3008 case X86ISD::MOVLPS: 3009 case X86ISD::MOVLPD: 3010 case X86ISD::MOVSHDUP: 3011 case X86ISD::MOVSLDUP: 3012 case X86ISD::MOVDDUP: 3013 case X86ISD::MOVSS: 3014 case X86ISD::MOVSD: 3015 case X86ISD::UNPCKL: 3016 case X86ISD::UNPCKH: 3017 case X86ISD::VPERMILP: 3018 case X86ISD::VPERM2X128: 3019 case X86ISD::VPERMI: 3020 return true; 3021 } 3022} 3023 3024static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3025 SDValue V1, SelectionDAG &DAG) { 3026 switch(Opc) { 3027 default: llvm_unreachable("Unknown x86 shuffle node"); 3028 case X86ISD::MOVSHDUP: 3029 case X86ISD::MOVSLDUP: 3030 case X86ISD::MOVDDUP: 3031 return DAG.getNode(Opc, dl, VT, V1); 3032 } 3033} 3034 3035static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3036 SDValue V1, unsigned TargetMask, 3037 SelectionDAG &DAG) { 3038 switch(Opc) { 3039 default: llvm_unreachable("Unknown x86 shuffle node"); 3040 case X86ISD::PSHUFD: 3041 case X86ISD::PSHUFHW: 3042 case X86ISD::PSHUFLW: 3043 case X86ISD::VPERMILP: 3044 case X86ISD::VPERMI: 3045 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 3046 } 3047} 3048 3049static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3050 SDValue V1, SDValue V2, unsigned TargetMask, 3051 SelectionDAG &DAG) { 3052 switch(Opc) { 3053 default: llvm_unreachable("Unknown x86 shuffle node"); 3054 case X86ISD::PALIGN: 3055 case X86ISD::SHUFP: 3056 case X86ISD::VPERM2X128: 3057 return DAG.getNode(Opc, dl, VT, V1, V2, 3058 DAG.getConstant(TargetMask, MVT::i8)); 3059 } 3060} 3061 3062static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 3063 SDValue V1, SDValue V2, SelectionDAG &DAG) { 3064 switch(Opc) { 3065 default: llvm_unreachable("Unknown x86 shuffle node"); 3066 case X86ISD::MOVLHPS: 3067 case X86ISD::MOVLHPD: 3068 case X86ISD::MOVHLPS: 3069 case X86ISD::MOVLPS: 3070 case X86ISD::MOVLPD: 3071 case X86ISD::MOVSS: 3072 case X86ISD::MOVSD: 3073 case X86ISD::UNPCKL: 3074 case X86ISD::UNPCKH: 3075 return DAG.getNode(Opc, dl, VT, V1, V2); 3076 } 3077} 3078 3079SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 3080 MachineFunction &MF = DAG.getMachineFunction(); 3081 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 3082 int ReturnAddrIndex = FuncInfo->getRAIndex(); 3083 3084 if (ReturnAddrIndex == 0) { 3085 // Set up a frame object for the return address. 3086 unsigned SlotSize = RegInfo->getSlotSize(); 3087 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 3088 false); 3089 FuncInfo->setRAIndex(ReturnAddrIndex); 3090 } 3091 3092 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 3093} 3094 3095bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 3096 bool hasSymbolicDisplacement) { 3097 // Offset should fit into 32 bit immediate field. 3098 if (!isInt<32>(Offset)) 3099 return false; 3100 3101 // If we don't have a symbolic displacement - we don't have any extra 3102 // restrictions. 3103 if (!hasSymbolicDisplacement) 3104 return true; 3105 3106 // FIXME: Some tweaks might be needed for medium code model. 3107 if (M != CodeModel::Small && M != CodeModel::Kernel) 3108 return false; 3109 3110 // For small code model we assume that latest object is 16MB before end of 31 3111 // bits boundary. We may also accept pretty large negative constants knowing 3112 // that all objects are in the positive half of address space. 3113 if (M == CodeModel::Small && Offset < 16*1024*1024) 3114 return true; 3115 3116 // For kernel code model we know that all object resist in the negative half 3117 // of 32bits address space. We may not accept negative offsets, since they may 3118 // be just off and we may accept pretty large positive ones. 3119 if (M == CodeModel::Kernel && Offset > 0) 3120 return true; 3121 3122 return false; 3123} 3124 3125/// isCalleePop - Determines whether the callee is required to pop its 3126/// own arguments. Callee pop is necessary to support tail calls. 3127bool X86::isCalleePop(CallingConv::ID CallingConv, 3128 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3129 if (IsVarArg) 3130 return false; 3131 3132 switch (CallingConv) { 3133 default: 3134 return false; 3135 case CallingConv::X86_StdCall: 3136 return !is64Bit; 3137 case CallingConv::X86_FastCall: 3138 return !is64Bit; 3139 case CallingConv::X86_ThisCall: 3140 return !is64Bit; 3141 case CallingConv::Fast: 3142 return TailCallOpt; 3143 case CallingConv::GHC: 3144 return TailCallOpt; 3145 case CallingConv::HiPE: 3146 return TailCallOpt; 3147 } 3148} 3149 3150/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3151/// specific condition code, returning the condition code and the LHS/RHS of the 3152/// comparison to make. 3153static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3154 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3155 if (!isFP) { 3156 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3157 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3158 // X > -1 -> X == 0, jump !sign. 3159 RHS = DAG.getConstant(0, RHS.getValueType()); 3160 return X86::COND_NS; 3161 } 3162 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3163 // X < 0 -> X == 0, jump on sign. 3164 return X86::COND_S; 3165 } 3166 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3167 // X < 1 -> X <= 0 3168 RHS = DAG.getConstant(0, RHS.getValueType()); 3169 return X86::COND_LE; 3170 } 3171 } 3172 3173 switch (SetCCOpcode) { 3174 default: llvm_unreachable("Invalid integer condition!"); 3175 case ISD::SETEQ: return X86::COND_E; 3176 case ISD::SETGT: return X86::COND_G; 3177 case ISD::SETGE: return X86::COND_GE; 3178 case ISD::SETLT: return X86::COND_L; 3179 case ISD::SETLE: return X86::COND_LE; 3180 case ISD::SETNE: return X86::COND_NE; 3181 case ISD::SETULT: return X86::COND_B; 3182 case ISD::SETUGT: return X86::COND_A; 3183 case ISD::SETULE: return X86::COND_BE; 3184 case ISD::SETUGE: return X86::COND_AE; 3185 } 3186 } 3187 3188 // First determine if it is required or is profitable to flip the operands. 3189 3190 // If LHS is a foldable load, but RHS is not, flip the condition. 3191 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3192 !ISD::isNON_EXTLoad(RHS.getNode())) { 3193 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3194 std::swap(LHS, RHS); 3195 } 3196 3197 switch (SetCCOpcode) { 3198 default: break; 3199 case ISD::SETOLT: 3200 case ISD::SETOLE: 3201 case ISD::SETUGT: 3202 case ISD::SETUGE: 3203 std::swap(LHS, RHS); 3204 break; 3205 } 3206 3207 // On a floating point condition, the flags are set as follows: 3208 // ZF PF CF op 3209 // 0 | 0 | 0 | X > Y 3210 // 0 | 0 | 1 | X < Y 3211 // 1 | 0 | 0 | X == Y 3212 // 1 | 1 | 1 | unordered 3213 switch (SetCCOpcode) { 3214 default: llvm_unreachable("Condcode should be pre-legalized away"); 3215 case ISD::SETUEQ: 3216 case ISD::SETEQ: return X86::COND_E; 3217 case ISD::SETOLT: // flipped 3218 case ISD::SETOGT: 3219 case ISD::SETGT: return X86::COND_A; 3220 case ISD::SETOLE: // flipped 3221 case ISD::SETOGE: 3222 case ISD::SETGE: return X86::COND_AE; 3223 case ISD::SETUGT: // flipped 3224 case ISD::SETULT: 3225 case ISD::SETLT: return X86::COND_B; 3226 case ISD::SETUGE: // flipped 3227 case ISD::SETULE: 3228 case ISD::SETLE: return X86::COND_BE; 3229 case ISD::SETONE: 3230 case ISD::SETNE: return X86::COND_NE; 3231 case ISD::SETUO: return X86::COND_P; 3232 case ISD::SETO: return X86::COND_NP; 3233 case ISD::SETOEQ: 3234 case ISD::SETUNE: return X86::COND_INVALID; 3235 } 3236} 3237 3238/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3239/// code. Current x86 isa includes the following FP cmov instructions: 3240/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3241static bool hasFPCMov(unsigned X86CC) { 3242 switch (X86CC) { 3243 default: 3244 return false; 3245 case X86::COND_B: 3246 case X86::COND_BE: 3247 case X86::COND_E: 3248 case X86::COND_P: 3249 case X86::COND_A: 3250 case X86::COND_AE: 3251 case X86::COND_NE: 3252 case X86::COND_NP: 3253 return true; 3254 } 3255} 3256 3257/// isFPImmLegal - Returns true if the target can instruction select the 3258/// specified FP immediate natively. If false, the legalizer will 3259/// materialize the FP immediate as a load from a constant pool. 3260bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3261 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3262 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3263 return true; 3264 } 3265 return false; 3266} 3267 3268/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3269/// the specified range (L, H]. 3270static bool isUndefOrInRange(int Val, int Low, int Hi) { 3271 return (Val < 0) || (Val >= Low && Val < Hi); 3272} 3273 3274/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3275/// specified value. 3276static bool isUndefOrEqual(int Val, int CmpVal) { 3277 return (Val < 0 || Val == CmpVal); 3278} 3279 3280/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning 3281/// from position Pos and ending in Pos+Size, falls within the specified 3282/// sequential range (L, L+Pos]. or is undef. 3283static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3284 unsigned Pos, unsigned Size, int Low) { 3285 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3286 if (!isUndefOrEqual(Mask[i], Low)) 3287 return false; 3288 return true; 3289} 3290 3291/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3292/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3293/// the second operand. 3294static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3295 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3296 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3297 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3298 return (Mask[0] < 2 && Mask[1] < 2); 3299 return false; 3300} 3301 3302/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3303/// is suitable for input to PSHUFHW. 3304static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3305 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) 3306 return false; 3307 3308 // Lower quadword copied in order or undef. 3309 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3310 return false; 3311 3312 // Upper quadword shuffled. 3313 for (unsigned i = 4; i != 8; ++i) 3314 if (!isUndefOrInRange(Mask[i], 4, 8)) 3315 return false; 3316 3317 if (VT == MVT::v16i16) { 3318 // Lower quadword copied in order or undef. 3319 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3320 return false; 3321 3322 // Upper quadword shuffled. 3323 for (unsigned i = 12; i != 16; ++i) 3324 if (!isUndefOrInRange(Mask[i], 12, 16)) 3325 return false; 3326 } 3327 3328 return true; 3329} 3330 3331/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3332/// is suitable for input to PSHUFLW. 3333static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3334 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) 3335 return false; 3336 3337 // Upper quadword copied in order. 3338 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3339 return false; 3340 3341 // Lower quadword shuffled. 3342 for (unsigned i = 0; i != 4; ++i) 3343 if (!isUndefOrInRange(Mask[i], 0, 4)) 3344 return false; 3345 3346 if (VT == MVT::v16i16) { 3347 // Upper quadword copied in order. 3348 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3349 return false; 3350 3351 // Lower quadword shuffled. 3352 for (unsigned i = 8; i != 12; ++i) 3353 if (!isUndefOrInRange(Mask[i], 8, 12)) 3354 return false; 3355 } 3356 3357 return true; 3358} 3359 3360/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3361/// is suitable for input to PALIGNR. 3362static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3363 const X86Subtarget *Subtarget) { 3364 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) || 3365 (VT.is256BitVector() && !Subtarget->hasInt256())) 3366 return false; 3367 3368 unsigned NumElts = VT.getVectorNumElements(); 3369 unsigned NumLanes = VT.getSizeInBits()/128; 3370 unsigned NumLaneElts = NumElts/NumLanes; 3371 3372 // Do not handle 64-bit element shuffles with palignr. 3373 if (NumLaneElts == 2) 3374 return false; 3375 3376 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3377 unsigned i; 3378 for (i = 0; i != NumLaneElts; ++i) { 3379 if (Mask[i+l] >= 0) 3380 break; 3381 } 3382 3383 // Lane is all undef, go to next lane 3384 if (i == NumLaneElts) 3385 continue; 3386 3387 int Start = Mask[i+l]; 3388 3389 // Make sure its in this lane in one of the sources 3390 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3391 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3392 return false; 3393 3394 // If not lane 0, then we must match lane 0 3395 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3396 return false; 3397 3398 // Correct second source to be contiguous with first source 3399 if (Start >= (int)NumElts) 3400 Start -= NumElts - NumLaneElts; 3401 3402 // Make sure we're shifting in the right direction. 3403 if (Start <= (int)(i+l)) 3404 return false; 3405 3406 Start -= i; 3407 3408 // Check the rest of the elements to see if they are consecutive. 3409 for (++i; i != NumLaneElts; ++i) { 3410 int Idx = Mask[i+l]; 3411 3412 // Make sure its in this lane 3413 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3414 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3415 return false; 3416 3417 // If not lane 0, then we must match lane 0 3418 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3419 return false; 3420 3421 if (Idx >= (int)NumElts) 3422 Idx -= NumElts - NumLaneElts; 3423 3424 if (!isUndefOrEqual(Idx, Start+i)) 3425 return false; 3426 3427 } 3428 } 3429 3430 return true; 3431} 3432 3433/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3434/// the two vector operands have swapped position. 3435static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3436 unsigned NumElems) { 3437 for (unsigned i = 0; i != NumElems; ++i) { 3438 int idx = Mask[i]; 3439 if (idx < 0) 3440 continue; 3441 else if (idx < (int)NumElems) 3442 Mask[i] = idx + NumElems; 3443 else 3444 Mask[i] = idx - NumElems; 3445 } 3446} 3447 3448/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3449/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3450/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3451/// reverse of what x86 shuffles want. 3452static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256, 3453 bool Commuted = false) { 3454 if (!HasFp256 && VT.is256BitVector()) 3455 return false; 3456 3457 unsigned NumElems = VT.getVectorNumElements(); 3458 unsigned NumLanes = VT.getSizeInBits()/128; 3459 unsigned NumLaneElems = NumElems/NumLanes; 3460 3461 if (NumLaneElems != 2 && NumLaneElems != 4) 3462 return false; 3463 3464 // VSHUFPSY divides the resulting vector into 4 chunks. 3465 // The sources are also splitted into 4 chunks, and each destination 3466 // chunk must come from a different source chunk. 3467 // 3468 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3469 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3470 // 3471 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3472 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3473 // 3474 // VSHUFPDY divides the resulting vector into 4 chunks. 3475 // The sources are also splitted into 4 chunks, and each destination 3476 // chunk must come from a different source chunk. 3477 // 3478 // SRC1 => X3 X2 X1 X0 3479 // SRC2 => Y3 Y2 Y1 Y0 3480 // 3481 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3482 // 3483 unsigned HalfLaneElems = NumLaneElems/2; 3484 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3485 for (unsigned i = 0; i != NumLaneElems; ++i) { 3486 int Idx = Mask[i+l]; 3487 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3488 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3489 return false; 3490 // For VSHUFPSY, the mask of the second half must be the same as the 3491 // first but with the appropriate offsets. This works in the same way as 3492 // VPERMILPS works with masks. 3493 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3494 continue; 3495 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3496 return false; 3497 } 3498 } 3499 3500 return true; 3501} 3502 3503/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3504/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3505static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3506 if (!VT.is128BitVector()) 3507 return false; 3508 3509 unsigned NumElems = VT.getVectorNumElements(); 3510 3511 if (NumElems != 4) 3512 return false; 3513 3514 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3515 return isUndefOrEqual(Mask[0], 6) && 3516 isUndefOrEqual(Mask[1], 7) && 3517 isUndefOrEqual(Mask[2], 2) && 3518 isUndefOrEqual(Mask[3], 3); 3519} 3520 3521/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3522/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3523/// <2, 3, 2, 3> 3524static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3525 if (!VT.is128BitVector()) 3526 return false; 3527 3528 unsigned NumElems = VT.getVectorNumElements(); 3529 3530 if (NumElems != 4) 3531 return false; 3532 3533 return isUndefOrEqual(Mask[0], 2) && 3534 isUndefOrEqual(Mask[1], 3) && 3535 isUndefOrEqual(Mask[2], 2) && 3536 isUndefOrEqual(Mask[3], 3); 3537} 3538 3539/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3540/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3541static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3542 if (!VT.is128BitVector()) 3543 return false; 3544 3545 unsigned NumElems = VT.getVectorNumElements(); 3546 3547 if (NumElems != 2 && NumElems != 4) 3548 return false; 3549 3550 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3551 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3552 return false; 3553 3554 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3555 if (!isUndefOrEqual(Mask[i], i)) 3556 return false; 3557 3558 return true; 3559} 3560 3561/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3562/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3563static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3564 if (!VT.is128BitVector()) 3565 return false; 3566 3567 unsigned NumElems = VT.getVectorNumElements(); 3568 3569 if (NumElems != 2 && NumElems != 4) 3570 return false; 3571 3572 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3573 if (!isUndefOrEqual(Mask[i], i)) 3574 return false; 3575 3576 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3577 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3578 return false; 3579 3580 return true; 3581} 3582 3583// 3584// Some special combinations that can be optimized. 3585// 3586static 3587SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, 3588 SelectionDAG &DAG) { 3589 MVT VT = SVOp->getValueType(0).getSimpleVT(); 3590 DebugLoc dl = SVOp->getDebugLoc(); 3591 3592 if (VT != MVT::v8i32 && VT != MVT::v8f32) 3593 return SDValue(); 3594 3595 ArrayRef<int> Mask = SVOp->getMask(); 3596 3597 // These are the special masks that may be optimized. 3598 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14}; 3599 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15}; 3600 bool MatchEvenMask = true; 3601 bool MatchOddMask = true; 3602 for (int i=0; i<8; ++i) { 3603 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i])) 3604 MatchEvenMask = false; 3605 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i])) 3606 MatchOddMask = false; 3607 } 3608 3609 if (!MatchEvenMask && !MatchOddMask) 3610 return SDValue(); 3611 3612 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT); 3613 3614 SDValue Op0 = SVOp->getOperand(0); 3615 SDValue Op1 = SVOp->getOperand(1); 3616 3617 if (MatchEvenMask) { 3618 // Shift the second operand right to 32 bits. 3619 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 }; 3620 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask); 3621 } else { 3622 // Shift the first operand left to 32 bits. 3623 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 }; 3624 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask); 3625 } 3626 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15}; 3627 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask); 3628} 3629 3630/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3631/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3632static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3633 bool HasInt256, bool V2IsSplat = false) { 3634 unsigned NumElts = VT.getVectorNumElements(); 3635 3636 assert((VT.is128BitVector() || VT.is256BitVector()) && 3637 "Unsupported vector type for unpckh"); 3638 3639 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 3640 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3641 return false; 3642 3643 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3644 // independently on 128-bit lanes. 3645 unsigned NumLanes = VT.getSizeInBits()/128; 3646 unsigned NumLaneElts = NumElts/NumLanes; 3647 3648 for (unsigned l = 0; l != NumLanes; ++l) { 3649 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3650 i != (l+1)*NumLaneElts; 3651 i += 2, ++j) { 3652 int BitI = Mask[i]; 3653 int BitI1 = Mask[i+1]; 3654 if (!isUndefOrEqual(BitI, j)) 3655 return false; 3656 if (V2IsSplat) { 3657 if (!isUndefOrEqual(BitI1, NumElts)) 3658 return false; 3659 } else { 3660 if (!isUndefOrEqual(BitI1, j + NumElts)) 3661 return false; 3662 } 3663 } 3664 } 3665 3666 return true; 3667} 3668 3669/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3670/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3671static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3672 bool HasInt256, bool V2IsSplat = false) { 3673 unsigned NumElts = VT.getVectorNumElements(); 3674 3675 assert((VT.is128BitVector() || VT.is256BitVector()) && 3676 "Unsupported vector type for unpckh"); 3677 3678 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 3679 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3680 return false; 3681 3682 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3683 // independently on 128-bit lanes. 3684 unsigned NumLanes = VT.getSizeInBits()/128; 3685 unsigned NumLaneElts = NumElts/NumLanes; 3686 3687 for (unsigned l = 0; l != NumLanes; ++l) { 3688 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3689 i != (l+1)*NumLaneElts; i += 2, ++j) { 3690 int BitI = Mask[i]; 3691 int BitI1 = Mask[i+1]; 3692 if (!isUndefOrEqual(BitI, j)) 3693 return false; 3694 if (V2IsSplat) { 3695 if (isUndefOrEqual(BitI1, NumElts)) 3696 return false; 3697 } else { 3698 if (!isUndefOrEqual(BitI1, j+NumElts)) 3699 return false; 3700 } 3701 } 3702 } 3703 return true; 3704} 3705 3706/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3707/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3708/// <0, 0, 1, 1> 3709static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3710 unsigned NumElts = VT.getVectorNumElements(); 3711 bool Is256BitVec = VT.is256BitVector(); 3712 3713 assert((VT.is128BitVector() || VT.is256BitVector()) && 3714 "Unsupported vector type for unpckh"); 3715 3716 if (Is256BitVec && NumElts != 4 && NumElts != 8 && 3717 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3718 return false; 3719 3720 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3721 // FIXME: Need a better way to get rid of this, there's no latency difference 3722 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3723 // the former later. We should also remove the "_undef" special mask. 3724 if (NumElts == 4 && Is256BitVec) 3725 return false; 3726 3727 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3728 // independently on 128-bit lanes. 3729 unsigned NumLanes = VT.getSizeInBits()/128; 3730 unsigned NumLaneElts = NumElts/NumLanes; 3731 3732 for (unsigned l = 0; l != NumLanes; ++l) { 3733 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3734 i != (l+1)*NumLaneElts; 3735 i += 2, ++j) { 3736 int BitI = Mask[i]; 3737 int BitI1 = Mask[i+1]; 3738 3739 if (!isUndefOrEqual(BitI, j)) 3740 return false; 3741 if (!isUndefOrEqual(BitI1, j)) 3742 return false; 3743 } 3744 } 3745 3746 return true; 3747} 3748 3749/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3750/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3751/// <2, 2, 3, 3> 3752static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) { 3753 unsigned NumElts = VT.getVectorNumElements(); 3754 3755 assert((VT.is128BitVector() || VT.is256BitVector()) && 3756 "Unsupported vector type for unpckh"); 3757 3758 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 && 3759 (!HasInt256 || (NumElts != 16 && NumElts != 32))) 3760 return false; 3761 3762 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3763 // independently on 128-bit lanes. 3764 unsigned NumLanes = VT.getSizeInBits()/128; 3765 unsigned NumLaneElts = NumElts/NumLanes; 3766 3767 for (unsigned l = 0; l != NumLanes; ++l) { 3768 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3769 i != (l+1)*NumLaneElts; i += 2, ++j) { 3770 int BitI = Mask[i]; 3771 int BitI1 = Mask[i+1]; 3772 if (!isUndefOrEqual(BitI, j)) 3773 return false; 3774 if (!isUndefOrEqual(BitI1, j)) 3775 return false; 3776 } 3777 } 3778 return true; 3779} 3780 3781/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3782/// specifies a shuffle of elements that is suitable for input to MOVSS, 3783/// MOVSD, and MOVD, i.e. setting the lowest element. 3784static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3785 if (VT.getVectorElementType().getSizeInBits() < 32) 3786 return false; 3787 if (!VT.is128BitVector()) 3788 return false; 3789 3790 unsigned NumElts = VT.getVectorNumElements(); 3791 3792 if (!isUndefOrEqual(Mask[0], NumElts)) 3793 return false; 3794 3795 for (unsigned i = 1; i != NumElts; ++i) 3796 if (!isUndefOrEqual(Mask[i], i)) 3797 return false; 3798 3799 return true; 3800} 3801 3802/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3803/// as permutations between 128-bit chunks or halves. As an example: this 3804/// shuffle bellow: 3805/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3806/// The first half comes from the second half of V1 and the second half from the 3807/// the second half of V2. 3808static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { 3809 if (!HasFp256 || !VT.is256BitVector()) 3810 return false; 3811 3812 // The shuffle result is divided into half A and half B. In total the two 3813 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3814 // B must come from C, D, E or F. 3815 unsigned HalfSize = VT.getVectorNumElements()/2; 3816 bool MatchA = false, MatchB = false; 3817 3818 // Check if A comes from one of C, D, E, F. 3819 for (unsigned Half = 0; Half != 4; ++Half) { 3820 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3821 MatchA = true; 3822 break; 3823 } 3824 } 3825 3826 // Check if B comes from one of C, D, E, F. 3827 for (unsigned Half = 0; Half != 4; ++Half) { 3828 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3829 MatchB = true; 3830 break; 3831 } 3832 } 3833 3834 return MatchA && MatchB; 3835} 3836 3837/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3838/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3839static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3840 MVT VT = SVOp->getValueType(0).getSimpleVT(); 3841 3842 unsigned HalfSize = VT.getVectorNumElements()/2; 3843 3844 unsigned FstHalf = 0, SndHalf = 0; 3845 for (unsigned i = 0; i < HalfSize; ++i) { 3846 if (SVOp->getMaskElt(i) > 0) { 3847 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3848 break; 3849 } 3850 } 3851 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3852 if (SVOp->getMaskElt(i) > 0) { 3853 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3854 break; 3855 } 3856 } 3857 3858 return (FstHalf | (SndHalf << 4)); 3859} 3860 3861/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3862/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3863/// Note that VPERMIL mask matching is different depending whether theunderlying 3864/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3865/// to the same elements of the low, but to the higher half of the source. 3866/// In VPERMILPD the two lanes could be shuffled independently of each other 3867/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3868static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { 3869 if (!HasFp256) 3870 return false; 3871 3872 unsigned NumElts = VT.getVectorNumElements(); 3873 // Only match 256-bit with 32/64-bit types 3874 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8)) 3875 return false; 3876 3877 unsigned NumLanes = VT.getSizeInBits()/128; 3878 unsigned LaneSize = NumElts/NumLanes; 3879 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3880 for (unsigned i = 0; i != LaneSize; ++i) { 3881 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3882 return false; 3883 if (NumElts != 8 || l == 0) 3884 continue; 3885 // VPERMILPS handling 3886 if (Mask[i] < 0) 3887 continue; 3888 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3889 return false; 3890 } 3891 } 3892 3893 return true; 3894} 3895 3896/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3897/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3898/// element of vector 2 and the other elements to come from vector 1 in order. 3899static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3900 bool V2IsSplat = false, bool V2IsUndef = false) { 3901 if (!VT.is128BitVector()) 3902 return false; 3903 3904 unsigned NumOps = VT.getVectorNumElements(); 3905 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3906 return false; 3907 3908 if (!isUndefOrEqual(Mask[0], 0)) 3909 return false; 3910 3911 for (unsigned i = 1; i != NumOps; ++i) 3912 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3913 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3914 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3915 return false; 3916 3917 return true; 3918} 3919 3920/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3921/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3922/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3923static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3924 const X86Subtarget *Subtarget) { 3925 if (!Subtarget->hasSSE3()) 3926 return false; 3927 3928 unsigned NumElems = VT.getVectorNumElements(); 3929 3930 if ((VT.is128BitVector() && NumElems != 4) || 3931 (VT.is256BitVector() && NumElems != 8)) 3932 return false; 3933 3934 // "i+1" is the value the indexed mask element must have 3935 for (unsigned i = 0; i != NumElems; i += 2) 3936 if (!isUndefOrEqual(Mask[i], i+1) || 3937 !isUndefOrEqual(Mask[i+1], i+1)) 3938 return false; 3939 3940 return true; 3941} 3942 3943/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3944/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3945/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3946static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3947 const X86Subtarget *Subtarget) { 3948 if (!Subtarget->hasSSE3()) 3949 return false; 3950 3951 unsigned NumElems = VT.getVectorNumElements(); 3952 3953 if ((VT.is128BitVector() && NumElems != 4) || 3954 (VT.is256BitVector() && NumElems != 8)) 3955 return false; 3956 3957 // "i" is the value the indexed mask element must have 3958 for (unsigned i = 0; i != NumElems; i += 2) 3959 if (!isUndefOrEqual(Mask[i], i) || 3960 !isUndefOrEqual(Mask[i+1], i)) 3961 return false; 3962 3963 return true; 3964} 3965 3966/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3967/// specifies a shuffle of elements that is suitable for input to 256-bit 3968/// version of MOVDDUP. 3969static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) { 3970 if (!HasFp256 || !VT.is256BitVector()) 3971 return false; 3972 3973 unsigned NumElts = VT.getVectorNumElements(); 3974 if (NumElts != 4) 3975 return false; 3976 3977 for (unsigned i = 0; i != NumElts/2; ++i) 3978 if (!isUndefOrEqual(Mask[i], 0)) 3979 return false; 3980 for (unsigned i = NumElts/2; i != NumElts; ++i) 3981 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3982 return false; 3983 return true; 3984} 3985 3986/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3987/// specifies a shuffle of elements that is suitable for input to 128-bit 3988/// version of MOVDDUP. 3989static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3990 if (!VT.is128BitVector()) 3991 return false; 3992 3993 unsigned e = VT.getVectorNumElements() / 2; 3994 for (unsigned i = 0; i != e; ++i) 3995 if (!isUndefOrEqual(Mask[i], i)) 3996 return false; 3997 for (unsigned i = 0; i != e; ++i) 3998 if (!isUndefOrEqual(Mask[e+i], i)) 3999 return false; 4000 return true; 4001} 4002 4003/// isVEXTRACTF128Index - Return true if the specified 4004/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 4005/// suitable for input to VEXTRACTF128. 4006bool X86::isVEXTRACTF128Index(SDNode *N) { 4007 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4008 return false; 4009 4010 // The index should be aligned on a 128-bit boundary. 4011 uint64_t Index = 4012 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4013 4014 MVT VT = N->getValueType(0).getSimpleVT(); 4015 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); 4016 bool Result = (Index * ElSize) % 128 == 0; 4017 4018 return Result; 4019} 4020 4021/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 4022/// operand specifies a subvector insert that is suitable for input to 4023/// VINSERTF128. 4024bool X86::isVINSERTF128Index(SDNode *N) { 4025 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4026 return false; 4027 4028 // The index should be aligned on a 128-bit boundary. 4029 uint64_t Index = 4030 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4031 4032 MVT VT = N->getValueType(0).getSimpleVT(); 4033 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); 4034 bool Result = (Index * ElSize) % 128 == 0; 4035 4036 return Result; 4037} 4038 4039/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4040/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4041/// Handles 128-bit and 256-bit. 4042static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 4043 MVT VT = N->getValueType(0).getSimpleVT(); 4044 4045 assert((VT.is128BitVector() || VT.is256BitVector()) && 4046 "Unsupported vector type for PSHUF/SHUFP"); 4047 4048 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 4049 // independently on 128-bit lanes. 4050 unsigned NumElts = VT.getVectorNumElements(); 4051 unsigned NumLanes = VT.getSizeInBits()/128; 4052 unsigned NumLaneElts = NumElts/NumLanes; 4053 4054 assert((NumLaneElts == 2 || NumLaneElts == 4) && 4055 "Only supports 2 or 4 elements per lane"); 4056 4057 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 4058 unsigned Mask = 0; 4059 for (unsigned i = 0; i != NumElts; ++i) { 4060 int Elt = N->getMaskElt(i); 4061 if (Elt < 0) continue; 4062 Elt &= NumLaneElts - 1; 4063 unsigned ShAmt = (i << Shift) % 8; 4064 Mask |= Elt << ShAmt; 4065 } 4066 4067 return Mask; 4068} 4069 4070/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4071/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4072static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 4073 MVT VT = N->getValueType(0).getSimpleVT(); 4074 4075 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4076 "Unsupported vector type for PSHUFHW"); 4077 4078 unsigned NumElts = VT.getVectorNumElements(); 4079 4080 unsigned Mask = 0; 4081 for (unsigned l = 0; l != NumElts; l += 8) { 4082 // 8 nodes per lane, but we only care about the last 4. 4083 for (unsigned i = 0; i < 4; ++i) { 4084 int Elt = N->getMaskElt(l+i+4); 4085 if (Elt < 0) continue; 4086 Elt &= 0x3; // only 2-bits. 4087 Mask |= Elt << (i * 2); 4088 } 4089 } 4090 4091 return Mask; 4092} 4093 4094/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4095/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4096static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 4097 MVT VT = N->getValueType(0).getSimpleVT(); 4098 4099 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4100 "Unsupported vector type for PSHUFHW"); 4101 4102 unsigned NumElts = VT.getVectorNumElements(); 4103 4104 unsigned Mask = 0; 4105 for (unsigned l = 0; l != NumElts; l += 8) { 4106 // 8 nodes per lane, but we only care about the first 4. 4107 for (unsigned i = 0; i < 4; ++i) { 4108 int Elt = N->getMaskElt(l+i); 4109 if (Elt < 0) continue; 4110 Elt &= 0x3; // only 2-bits 4111 Mask |= Elt << (i * 2); 4112 } 4113 } 4114 4115 return Mask; 4116} 4117 4118/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4119/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4120static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4121 MVT VT = SVOp->getValueType(0).getSimpleVT(); 4122 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4123 4124 unsigned NumElts = VT.getVectorNumElements(); 4125 unsigned NumLanes = VT.getSizeInBits()/128; 4126 unsigned NumLaneElts = NumElts/NumLanes; 4127 4128 int Val = 0; 4129 unsigned i; 4130 for (i = 0; i != NumElts; ++i) { 4131 Val = SVOp->getMaskElt(i); 4132 if (Val >= 0) 4133 break; 4134 } 4135 if (Val >= (int)NumElts) 4136 Val -= NumElts - NumLaneElts; 4137 4138 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4139 return (Val - i) * EltSize; 4140} 4141 4142/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4143/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4144/// instructions. 4145unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4146 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4147 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4148 4149 uint64_t Index = 4150 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4151 4152 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT(); 4153 MVT ElVT = VecVT.getVectorElementType(); 4154 4155 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4156 return Index / NumElemsPerChunk; 4157} 4158 4159/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4160/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4161/// instructions. 4162unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4163 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4164 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4165 4166 uint64_t Index = 4167 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4168 4169 MVT VecVT = N->getValueType(0).getSimpleVT(); 4170 MVT ElVT = VecVT.getVectorElementType(); 4171 4172 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4173 return Index / NumElemsPerChunk; 4174} 4175 4176/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 4177/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 4178/// Handles 256-bit. 4179static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 4180 MVT VT = N->getValueType(0).getSimpleVT(); 4181 4182 unsigned NumElts = VT.getVectorNumElements(); 4183 4184 assert((VT.is256BitVector() && NumElts == 4) && 4185 "Unsupported vector type for VPERMQ/VPERMPD"); 4186 4187 unsigned Mask = 0; 4188 for (unsigned i = 0; i != NumElts; ++i) { 4189 int Elt = N->getMaskElt(i); 4190 if (Elt < 0) 4191 continue; 4192 Mask |= Elt << (i*2); 4193 } 4194 4195 return Mask; 4196} 4197/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4198/// constant +0.0. 4199bool X86::isZeroNode(SDValue Elt) { 4200 return ((isa<ConstantSDNode>(Elt) && 4201 cast<ConstantSDNode>(Elt)->isNullValue()) || 4202 (isa<ConstantFPSDNode>(Elt) && 4203 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4204} 4205 4206/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4207/// their permute mask. 4208static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4209 SelectionDAG &DAG) { 4210 MVT VT = SVOp->getValueType(0).getSimpleVT(); 4211 unsigned NumElems = VT.getVectorNumElements(); 4212 SmallVector<int, 8> MaskVec; 4213 4214 for (unsigned i = 0; i != NumElems; ++i) { 4215 int Idx = SVOp->getMaskElt(i); 4216 if (Idx >= 0) { 4217 if (Idx < (int)NumElems) 4218 Idx += NumElems; 4219 else 4220 Idx -= NumElems; 4221 } 4222 MaskVec.push_back(Idx); 4223 } 4224 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4225 SVOp->getOperand(0), &MaskVec[0]); 4226} 4227 4228/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4229/// match movhlps. The lower half elements should come from upper half of 4230/// V1 (and in order), and the upper half elements should come from the upper 4231/// half of V2 (and in order). 4232static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4233 if (!VT.is128BitVector()) 4234 return false; 4235 if (VT.getVectorNumElements() != 4) 4236 return false; 4237 for (unsigned i = 0, e = 2; i != e; ++i) 4238 if (!isUndefOrEqual(Mask[i], i+2)) 4239 return false; 4240 for (unsigned i = 2; i != 4; ++i) 4241 if (!isUndefOrEqual(Mask[i], i+4)) 4242 return false; 4243 return true; 4244} 4245 4246/// isScalarLoadToVector - Returns true if the node is a scalar load that 4247/// is promoted to a vector. It also returns the LoadSDNode by reference if 4248/// required. 4249static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4250 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4251 return false; 4252 N = N->getOperand(0).getNode(); 4253 if (!ISD::isNON_EXTLoad(N)) 4254 return false; 4255 if (LD) 4256 *LD = cast<LoadSDNode>(N); 4257 return true; 4258} 4259 4260// Test whether the given value is a vector value which will be legalized 4261// into a load. 4262static bool WillBeConstantPoolLoad(SDNode *N) { 4263 if (N->getOpcode() != ISD::BUILD_VECTOR) 4264 return false; 4265 4266 // Check for any non-constant elements. 4267 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4268 switch (N->getOperand(i).getNode()->getOpcode()) { 4269 case ISD::UNDEF: 4270 case ISD::ConstantFP: 4271 case ISD::Constant: 4272 break; 4273 default: 4274 return false; 4275 } 4276 4277 // Vectors of all-zeros and all-ones are materialized with special 4278 // instructions rather than being loaded. 4279 return !ISD::isBuildVectorAllZeros(N) && 4280 !ISD::isBuildVectorAllOnes(N); 4281} 4282 4283/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4284/// match movlp{s|d}. The lower half elements should come from lower half of 4285/// V1 (and in order), and the upper half elements should come from the upper 4286/// half of V2 (and in order). And since V1 will become the source of the 4287/// MOVLP, it must be either a vector load or a scalar load to vector. 4288static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4289 ArrayRef<int> Mask, EVT VT) { 4290 if (!VT.is128BitVector()) 4291 return false; 4292 4293 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4294 return false; 4295 // Is V2 is a vector load, don't do this transformation. We will try to use 4296 // load folding shufps op. 4297 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4298 return false; 4299 4300 unsigned NumElems = VT.getVectorNumElements(); 4301 4302 if (NumElems != 2 && NumElems != 4) 4303 return false; 4304 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4305 if (!isUndefOrEqual(Mask[i], i)) 4306 return false; 4307 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4308 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4309 return false; 4310 return true; 4311} 4312 4313/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4314/// all the same. 4315static bool isSplatVector(SDNode *N) { 4316 if (N->getOpcode() != ISD::BUILD_VECTOR) 4317 return false; 4318 4319 SDValue SplatValue = N->getOperand(0); 4320 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4321 if (N->getOperand(i) != SplatValue) 4322 return false; 4323 return true; 4324} 4325 4326/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4327/// to an zero vector. 4328/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4329static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4330 SDValue V1 = N->getOperand(0); 4331 SDValue V2 = N->getOperand(1); 4332 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4333 for (unsigned i = 0; i != NumElems; ++i) { 4334 int Idx = N->getMaskElt(i); 4335 if (Idx >= (int)NumElems) { 4336 unsigned Opc = V2.getOpcode(); 4337 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4338 continue; 4339 if (Opc != ISD::BUILD_VECTOR || 4340 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4341 return false; 4342 } else if (Idx >= 0) { 4343 unsigned Opc = V1.getOpcode(); 4344 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4345 continue; 4346 if (Opc != ISD::BUILD_VECTOR || 4347 !X86::isZeroNode(V1.getOperand(Idx))) 4348 return false; 4349 } 4350 } 4351 return true; 4352} 4353 4354/// getZeroVector - Returns a vector of specified type with all zero elements. 4355/// 4356static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4357 SelectionDAG &DAG, DebugLoc dl) { 4358 assert(VT.isVector() && "Expected a vector type"); 4359 4360 // Always build SSE zero vectors as <4 x i32> bitcasted 4361 // to their dest type. This ensures they get CSE'd. 4362 SDValue Vec; 4363 if (VT.is128BitVector()) { // SSE 4364 if (Subtarget->hasSSE2()) { // SSE2 4365 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4366 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4367 } else { // SSE1 4368 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4369 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4370 } 4371 } else if (VT.is256BitVector()) { // AVX 4372 if (Subtarget->hasInt256()) { // AVX2 4373 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4374 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4375 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4376 } else { 4377 // 256-bit logic and arithmetic instructions in AVX are all 4378 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4379 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4380 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4381 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4382 } 4383 } else 4384 llvm_unreachable("Unexpected vector type"); 4385 4386 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4387} 4388 4389/// getOnesVector - Returns a vector of specified type with all bits set. 4390/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4391/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4392/// Then bitcast to their original type, ensuring they get CSE'd. 4393static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG, 4394 DebugLoc dl) { 4395 assert(VT.isVector() && "Expected a vector type"); 4396 4397 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4398 SDValue Vec; 4399 if (VT.is256BitVector()) { 4400 if (HasInt256) { // AVX2 4401 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4402 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4403 } else { // AVX 4404 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4405 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4406 } 4407 } else if (VT.is128BitVector()) { 4408 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4409 } else 4410 llvm_unreachable("Unexpected vector type"); 4411 4412 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4413} 4414 4415/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4416/// that point to V2 points to its first element. 4417static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4418 for (unsigned i = 0; i != NumElems; ++i) { 4419 if (Mask[i] > (int)NumElems) { 4420 Mask[i] = NumElems; 4421 } 4422 } 4423} 4424 4425/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4426/// operation of specified width. 4427static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4428 SDValue V2) { 4429 unsigned NumElems = VT.getVectorNumElements(); 4430 SmallVector<int, 8> Mask; 4431 Mask.push_back(NumElems); 4432 for (unsigned i = 1; i != NumElems; ++i) 4433 Mask.push_back(i); 4434 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4435} 4436 4437/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4438static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4439 SDValue V2) { 4440 unsigned NumElems = VT.getVectorNumElements(); 4441 SmallVector<int, 8> Mask; 4442 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4443 Mask.push_back(i); 4444 Mask.push_back(i + NumElems); 4445 } 4446 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4447} 4448 4449/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4450static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4451 SDValue V2) { 4452 unsigned NumElems = VT.getVectorNumElements(); 4453 SmallVector<int, 8> Mask; 4454 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4455 Mask.push_back(i + Half); 4456 Mask.push_back(i + NumElems + Half); 4457 } 4458 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4459} 4460 4461// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4462// a generic shuffle instruction because the target has no such instructions. 4463// Generate shuffles which repeat i16 and i8 several times until they can be 4464// represented by v4f32 and then be manipulated by target suported shuffles. 4465static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4466 EVT VT = V.getValueType(); 4467 int NumElems = VT.getVectorNumElements(); 4468 DebugLoc dl = V.getDebugLoc(); 4469 4470 while (NumElems > 4) { 4471 if (EltNo < NumElems/2) { 4472 V = getUnpackl(DAG, dl, VT, V, V); 4473 } else { 4474 V = getUnpackh(DAG, dl, VT, V, V); 4475 EltNo -= NumElems/2; 4476 } 4477 NumElems >>= 1; 4478 } 4479 return V; 4480} 4481 4482/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4483static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4484 EVT VT = V.getValueType(); 4485 DebugLoc dl = V.getDebugLoc(); 4486 4487 if (VT.is128BitVector()) { 4488 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4489 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4490 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4491 &SplatMask[0]); 4492 } else if (VT.is256BitVector()) { 4493 // To use VPERMILPS to splat scalars, the second half of indicies must 4494 // refer to the higher part, which is a duplication of the lower one, 4495 // because VPERMILPS can only handle in-lane permutations. 4496 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4497 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4498 4499 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4500 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4501 &SplatMask[0]); 4502 } else 4503 llvm_unreachable("Vector size not supported"); 4504 4505 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4506} 4507 4508/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4509static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4510 EVT SrcVT = SV->getValueType(0); 4511 SDValue V1 = SV->getOperand(0); 4512 DebugLoc dl = SV->getDebugLoc(); 4513 4514 int EltNo = SV->getSplatIndex(); 4515 int NumElems = SrcVT.getVectorNumElements(); 4516 bool Is256BitVec = SrcVT.is256BitVector(); 4517 4518 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) && 4519 "Unknown how to promote splat for type"); 4520 4521 // Extract the 128-bit part containing the splat element and update 4522 // the splat element index when it refers to the higher register. 4523 if (Is256BitVec) { 4524 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4525 if (EltNo >= NumElems/2) 4526 EltNo -= NumElems/2; 4527 } 4528 4529 // All i16 and i8 vector types can't be used directly by a generic shuffle 4530 // instruction because the target has no such instruction. Generate shuffles 4531 // which repeat i16 and i8 several times until they fit in i32, and then can 4532 // be manipulated by target suported shuffles. 4533 EVT EltVT = SrcVT.getVectorElementType(); 4534 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4535 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4536 4537 // Recreate the 256-bit vector and place the same 128-bit vector 4538 // into the low and high part. This is necessary because we want 4539 // to use VPERM* to shuffle the vectors 4540 if (Is256BitVec) { 4541 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4542 } 4543 4544 return getLegalSplat(DAG, V1, EltNo); 4545} 4546 4547/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4548/// vector of zero or undef vector. This produces a shuffle where the low 4549/// element of V2 is swizzled into the zero/undef vector, landing at element 4550/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4551static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4552 bool IsZero, 4553 const X86Subtarget *Subtarget, 4554 SelectionDAG &DAG) { 4555 EVT VT = V2.getValueType(); 4556 SDValue V1 = IsZero 4557 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4558 unsigned NumElems = VT.getVectorNumElements(); 4559 SmallVector<int, 16> MaskVec; 4560 for (unsigned i = 0; i != NumElems; ++i) 4561 // If this is the insertion idx, put the low elt of V2 here. 4562 MaskVec.push_back(i == Idx ? NumElems : i); 4563 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4564} 4565 4566/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4567/// target specific opcode. Returns true if the Mask could be calculated. 4568/// Sets IsUnary to true if only uses one source. 4569static bool getTargetShuffleMask(SDNode *N, MVT VT, 4570 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4571 unsigned NumElems = VT.getVectorNumElements(); 4572 SDValue ImmN; 4573 4574 IsUnary = false; 4575 switch(N->getOpcode()) { 4576 case X86ISD::SHUFP: 4577 ImmN = N->getOperand(N->getNumOperands()-1); 4578 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4579 break; 4580 case X86ISD::UNPCKH: 4581 DecodeUNPCKHMask(VT, Mask); 4582 break; 4583 case X86ISD::UNPCKL: 4584 DecodeUNPCKLMask(VT, Mask); 4585 break; 4586 case X86ISD::MOVHLPS: 4587 DecodeMOVHLPSMask(NumElems, Mask); 4588 break; 4589 case X86ISD::MOVLHPS: 4590 DecodeMOVLHPSMask(NumElems, Mask); 4591 break; 4592 case X86ISD::PSHUFD: 4593 case X86ISD::VPERMILP: 4594 ImmN = N->getOperand(N->getNumOperands()-1); 4595 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4596 IsUnary = true; 4597 break; 4598 case X86ISD::PSHUFHW: 4599 ImmN = N->getOperand(N->getNumOperands()-1); 4600 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4601 IsUnary = true; 4602 break; 4603 case X86ISD::PSHUFLW: 4604 ImmN = N->getOperand(N->getNumOperands()-1); 4605 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4606 IsUnary = true; 4607 break; 4608 case X86ISD::VPERMI: 4609 ImmN = N->getOperand(N->getNumOperands()-1); 4610 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4611 IsUnary = true; 4612 break; 4613 case X86ISD::MOVSS: 4614 case X86ISD::MOVSD: { 4615 // The index 0 always comes from the first element of the second source, 4616 // this is why MOVSS and MOVSD are used in the first place. The other 4617 // elements come from the other positions of the first source vector 4618 Mask.push_back(NumElems); 4619 for (unsigned i = 1; i != NumElems; ++i) { 4620 Mask.push_back(i); 4621 } 4622 break; 4623 } 4624 case X86ISD::VPERM2X128: 4625 ImmN = N->getOperand(N->getNumOperands()-1); 4626 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4627 if (Mask.empty()) return false; 4628 break; 4629 case X86ISD::MOVDDUP: 4630 case X86ISD::MOVLHPD: 4631 case X86ISD::MOVLPD: 4632 case X86ISD::MOVLPS: 4633 case X86ISD::MOVSHDUP: 4634 case X86ISD::MOVSLDUP: 4635 case X86ISD::PALIGN: 4636 // Not yet implemented 4637 return false; 4638 default: llvm_unreachable("unknown target shuffle node"); 4639 } 4640 4641 return true; 4642} 4643 4644/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4645/// element of the result of the vector shuffle. 4646static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4647 unsigned Depth) { 4648 if (Depth == 6) 4649 return SDValue(); // Limit search depth. 4650 4651 SDValue V = SDValue(N, 0); 4652 EVT VT = V.getValueType(); 4653 unsigned Opcode = V.getOpcode(); 4654 4655 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4656 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4657 int Elt = SV->getMaskElt(Index); 4658 4659 if (Elt < 0) 4660 return DAG.getUNDEF(VT.getVectorElementType()); 4661 4662 unsigned NumElems = VT.getVectorNumElements(); 4663 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4664 : SV->getOperand(1); 4665 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4666 } 4667 4668 // Recurse into target specific vector shuffles to find scalars. 4669 if (isTargetShuffle(Opcode)) { 4670 MVT ShufVT = V.getValueType().getSimpleVT(); 4671 unsigned NumElems = ShufVT.getVectorNumElements(); 4672 SmallVector<int, 16> ShuffleMask; 4673 bool IsUnary; 4674 4675 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary)) 4676 return SDValue(); 4677 4678 int Elt = ShuffleMask[Index]; 4679 if (Elt < 0) 4680 return DAG.getUNDEF(ShufVT.getVectorElementType()); 4681 4682 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4683 : N->getOperand(1); 4684 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4685 Depth+1); 4686 } 4687 4688 // Actual nodes that may contain scalar elements 4689 if (Opcode == ISD::BITCAST) { 4690 V = V.getOperand(0); 4691 EVT SrcVT = V.getValueType(); 4692 unsigned NumElems = VT.getVectorNumElements(); 4693 4694 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4695 return SDValue(); 4696 } 4697 4698 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4699 return (Index == 0) ? V.getOperand(0) 4700 : DAG.getUNDEF(VT.getVectorElementType()); 4701 4702 if (V.getOpcode() == ISD::BUILD_VECTOR) 4703 return V.getOperand(Index); 4704 4705 return SDValue(); 4706} 4707 4708/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4709/// shuffle operation which come from a consecutively from a zero. The 4710/// search can start in two different directions, from left or right. 4711static 4712unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4713 bool ZerosFromLeft, SelectionDAG &DAG) { 4714 unsigned i; 4715 for (i = 0; i != NumElems; ++i) { 4716 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4717 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4718 if (!(Elt.getNode() && 4719 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4720 break; 4721 } 4722 4723 return i; 4724} 4725 4726/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4727/// correspond consecutively to elements from one of the vector operands, 4728/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4729static 4730bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4731 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4732 unsigned NumElems, unsigned &OpNum) { 4733 bool SeenV1 = false; 4734 bool SeenV2 = false; 4735 4736 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4737 int Idx = SVOp->getMaskElt(i); 4738 // Ignore undef indicies 4739 if (Idx < 0) 4740 continue; 4741 4742 if (Idx < (int)NumElems) 4743 SeenV1 = true; 4744 else 4745 SeenV2 = true; 4746 4747 // Only accept consecutive elements from the same vector 4748 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4749 return false; 4750 } 4751 4752 OpNum = SeenV1 ? 0 : 1; 4753 return true; 4754} 4755 4756/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4757/// logical left shift of a vector. 4758static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4759 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4760 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4761 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4762 false /* check zeros from right */, DAG); 4763 unsigned OpSrc; 4764 4765 if (!NumZeros) 4766 return false; 4767 4768 // Considering the elements in the mask that are not consecutive zeros, 4769 // check if they consecutively come from only one of the source vectors. 4770 // 4771 // V1 = {X, A, B, C} 0 4772 // \ \ \ / 4773 // vector_shuffle V1, V2 <1, 2, 3, X> 4774 // 4775 if (!isShuffleMaskConsecutive(SVOp, 4776 0, // Mask Start Index 4777 NumElems-NumZeros, // Mask End Index(exclusive) 4778 NumZeros, // Where to start looking in the src vector 4779 NumElems, // Number of elements in vector 4780 OpSrc)) // Which source operand ? 4781 return false; 4782 4783 isLeft = false; 4784 ShAmt = NumZeros; 4785 ShVal = SVOp->getOperand(OpSrc); 4786 return true; 4787} 4788 4789/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4790/// logical left shift of a vector. 4791static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4792 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4793 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4794 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4795 true /* check zeros from left */, DAG); 4796 unsigned OpSrc; 4797 4798 if (!NumZeros) 4799 return false; 4800 4801 // Considering the elements in the mask that are not consecutive zeros, 4802 // check if they consecutively come from only one of the source vectors. 4803 // 4804 // 0 { A, B, X, X } = V2 4805 // / \ / / 4806 // vector_shuffle V1, V2 <X, X, 4, 5> 4807 // 4808 if (!isShuffleMaskConsecutive(SVOp, 4809 NumZeros, // Mask Start Index 4810 NumElems, // Mask End Index(exclusive) 4811 0, // Where to start looking in the src vector 4812 NumElems, // Number of elements in vector 4813 OpSrc)) // Which source operand ? 4814 return false; 4815 4816 isLeft = true; 4817 ShAmt = NumZeros; 4818 ShVal = SVOp->getOperand(OpSrc); 4819 return true; 4820} 4821 4822/// isVectorShift - Returns true if the shuffle can be implemented as a 4823/// logical left or right shift of a vector. 4824static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4825 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4826 // Although the logic below support any bitwidth size, there are no 4827 // shift instructions which handle more than 128-bit vectors. 4828 if (!SVOp->getValueType(0).is128BitVector()) 4829 return false; 4830 4831 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4832 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4833 return true; 4834 4835 return false; 4836} 4837 4838/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4839/// 4840static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4841 unsigned NumNonZero, unsigned NumZero, 4842 SelectionDAG &DAG, 4843 const X86Subtarget* Subtarget, 4844 const TargetLowering &TLI) { 4845 if (NumNonZero > 8) 4846 return SDValue(); 4847 4848 DebugLoc dl = Op.getDebugLoc(); 4849 SDValue V(0, 0); 4850 bool First = true; 4851 for (unsigned i = 0; i < 16; ++i) { 4852 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4853 if (ThisIsNonZero && First) { 4854 if (NumZero) 4855 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4856 else 4857 V = DAG.getUNDEF(MVT::v8i16); 4858 First = false; 4859 } 4860 4861 if ((i & 1) != 0) { 4862 SDValue ThisElt(0, 0), LastElt(0, 0); 4863 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4864 if (LastIsNonZero) { 4865 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4866 MVT::i16, Op.getOperand(i-1)); 4867 } 4868 if (ThisIsNonZero) { 4869 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4870 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4871 ThisElt, DAG.getConstant(8, MVT::i8)); 4872 if (LastIsNonZero) 4873 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4874 } else 4875 ThisElt = LastElt; 4876 4877 if (ThisElt.getNode()) 4878 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4879 DAG.getIntPtrConstant(i/2)); 4880 } 4881 } 4882 4883 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4884} 4885 4886/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4887/// 4888static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4889 unsigned NumNonZero, unsigned NumZero, 4890 SelectionDAG &DAG, 4891 const X86Subtarget* Subtarget, 4892 const TargetLowering &TLI) { 4893 if (NumNonZero > 4) 4894 return SDValue(); 4895 4896 DebugLoc dl = Op.getDebugLoc(); 4897 SDValue V(0, 0); 4898 bool First = true; 4899 for (unsigned i = 0; i < 8; ++i) { 4900 bool isNonZero = (NonZeros & (1 << i)) != 0; 4901 if (isNonZero) { 4902 if (First) { 4903 if (NumZero) 4904 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4905 else 4906 V = DAG.getUNDEF(MVT::v8i16); 4907 First = false; 4908 } 4909 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4910 MVT::v8i16, V, Op.getOperand(i), 4911 DAG.getIntPtrConstant(i)); 4912 } 4913 } 4914 4915 return V; 4916} 4917 4918/// getVShift - Return a vector logical shift node. 4919/// 4920static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4921 unsigned NumBits, SelectionDAG &DAG, 4922 const TargetLowering &TLI, DebugLoc dl) { 4923 assert(VT.is128BitVector() && "Unknown type for VShift"); 4924 EVT ShVT = MVT::v2i64; 4925 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4926 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4927 return DAG.getNode(ISD::BITCAST, dl, VT, 4928 DAG.getNode(Opc, dl, ShVT, SrcOp, 4929 DAG.getConstant(NumBits, 4930 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4931} 4932 4933SDValue 4934X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4935 SelectionDAG &DAG) const { 4936 4937 // Check if the scalar load can be widened into a vector load. And if 4938 // the address is "base + cst" see if the cst can be "absorbed" into 4939 // the shuffle mask. 4940 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4941 SDValue Ptr = LD->getBasePtr(); 4942 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4943 return SDValue(); 4944 EVT PVT = LD->getValueType(0); 4945 if (PVT != MVT::i32 && PVT != MVT::f32) 4946 return SDValue(); 4947 4948 int FI = -1; 4949 int64_t Offset = 0; 4950 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4951 FI = FINode->getIndex(); 4952 Offset = 0; 4953 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4954 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4955 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4956 Offset = Ptr.getConstantOperandVal(1); 4957 Ptr = Ptr.getOperand(0); 4958 } else { 4959 return SDValue(); 4960 } 4961 4962 // FIXME: 256-bit vector instructions don't require a strict alignment, 4963 // improve this code to support it better. 4964 unsigned RequiredAlign = VT.getSizeInBits()/8; 4965 SDValue Chain = LD->getChain(); 4966 // Make sure the stack object alignment is at least 16 or 32. 4967 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4968 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4969 if (MFI->isFixedObjectIndex(FI)) { 4970 // Can't change the alignment. FIXME: It's possible to compute 4971 // the exact stack offset and reference FI + adjust offset instead. 4972 // If someone *really* cares about this. That's the way to implement it. 4973 return SDValue(); 4974 } else { 4975 MFI->setObjectAlignment(FI, RequiredAlign); 4976 } 4977 } 4978 4979 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4980 // Ptr + (Offset & ~15). 4981 if (Offset < 0) 4982 return SDValue(); 4983 if ((Offset % RequiredAlign) & 3) 4984 return SDValue(); 4985 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4986 if (StartOffset) 4987 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4988 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4989 4990 int EltNo = (Offset - StartOffset) >> 2; 4991 unsigned NumElems = VT.getVectorNumElements(); 4992 4993 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4994 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4995 LD->getPointerInfo().getWithOffset(StartOffset), 4996 false, false, false, 0); 4997 4998 SmallVector<int, 8> Mask; 4999 for (unsigned i = 0; i != NumElems; ++i) 5000 Mask.push_back(EltNo); 5001 5002 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 5003 } 5004 5005 return SDValue(); 5006} 5007 5008/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 5009/// vector of type 'VT', see if the elements can be replaced by a single large 5010/// load which has the same value as a build_vector whose operands are 'elts'. 5011/// 5012/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 5013/// 5014/// FIXME: we'd also like to handle the case where the last elements are zero 5015/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 5016/// There's even a handy isZeroNode for that purpose. 5017static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 5018 DebugLoc &DL, SelectionDAG &DAG) { 5019 EVT EltVT = VT.getVectorElementType(); 5020 unsigned NumElems = Elts.size(); 5021 5022 LoadSDNode *LDBase = NULL; 5023 unsigned LastLoadedElt = -1U; 5024 5025 // For each element in the initializer, see if we've found a load or an undef. 5026 // If we don't find an initial load element, or later load elements are 5027 // non-consecutive, bail out. 5028 for (unsigned i = 0; i < NumElems; ++i) { 5029 SDValue Elt = Elts[i]; 5030 5031 if (!Elt.getNode() || 5032 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 5033 return SDValue(); 5034 if (!LDBase) { 5035 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 5036 return SDValue(); 5037 LDBase = cast<LoadSDNode>(Elt.getNode()); 5038 LastLoadedElt = i; 5039 continue; 5040 } 5041 if (Elt.getOpcode() == ISD::UNDEF) 5042 continue; 5043 5044 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5045 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5046 return SDValue(); 5047 LastLoadedElt = i; 5048 } 5049 5050 // If we have found an entire vector of loads and undefs, then return a large 5051 // load of the entire vector width starting at the base pointer. If we found 5052 // consecutive loads for the low half, generate a vzext_load node. 5053 if (LastLoadedElt == NumElems - 1) { 5054 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5055 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5056 LDBase->getPointerInfo(), 5057 LDBase->isVolatile(), LDBase->isNonTemporal(), 5058 LDBase->isInvariant(), 0); 5059 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5060 LDBase->getPointerInfo(), 5061 LDBase->isVolatile(), LDBase->isNonTemporal(), 5062 LDBase->isInvariant(), LDBase->getAlignment()); 5063 } 5064 if (NumElems == 4 && LastLoadedElt == 1 && 5065 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5066 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5067 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5068 SDValue ResNode = 5069 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5070 LDBase->getPointerInfo(), 5071 LDBase->getAlignment(), 5072 false/*isVolatile*/, true/*ReadMem*/, 5073 false/*WriteMem*/); 5074 5075 // Make sure the newly-created LOAD is in the same position as LDBase in 5076 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and 5077 // update uses of LDBase's output chain to use the TokenFactor. 5078 if (LDBase->hasAnyUseOfValue(1)) { 5079 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 5080 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1)); 5081 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain); 5082 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1), 5083 SDValue(ResNode.getNode(), 1)); 5084 } 5085 5086 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5087 } 5088 return SDValue(); 5089} 5090 5091/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 5092/// to generate a splat value for the following cases: 5093/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 5094/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 5095/// a scalar load, or a constant. 5096/// The VBROADCAST node is returned when a pattern is found, 5097/// or SDValue() otherwise. 5098SDValue 5099X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const { 5100 if (!Subtarget->hasFp256()) 5101 return SDValue(); 5102 5103 MVT VT = Op.getValueType().getSimpleVT(); 5104 DebugLoc dl = Op.getDebugLoc(); 5105 5106 assert((VT.is128BitVector() || VT.is256BitVector()) && 5107 "Unsupported vector type for broadcast."); 5108 5109 SDValue Ld; 5110 bool ConstSplatVal; 5111 5112 switch (Op.getOpcode()) { 5113 default: 5114 // Unknown pattern found. 5115 return SDValue(); 5116 5117 case ISD::BUILD_VECTOR: { 5118 // The BUILD_VECTOR node must be a splat. 5119 if (!isSplatVector(Op.getNode())) 5120 return SDValue(); 5121 5122 Ld = Op.getOperand(0); 5123 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5124 Ld.getOpcode() == ISD::ConstantFP); 5125 5126 // The suspected load node has several users. Make sure that all 5127 // of its users are from the BUILD_VECTOR node. 5128 // Constants may have multiple users. 5129 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 5130 return SDValue(); 5131 break; 5132 } 5133 5134 case ISD::VECTOR_SHUFFLE: { 5135 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5136 5137 // Shuffles must have a splat mask where the first element is 5138 // broadcasted. 5139 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5140 return SDValue(); 5141 5142 SDValue Sc = Op.getOperand(0); 5143 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR && 5144 Sc.getOpcode() != ISD::BUILD_VECTOR) { 5145 5146 if (!Subtarget->hasInt256()) 5147 return SDValue(); 5148 5149 // Use the register form of the broadcast instruction available on AVX2. 5150 if (VT.is256BitVector()) 5151 Sc = Extract128BitVector(Sc, 0, DAG, dl); 5152 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc); 5153 } 5154 5155 Ld = Sc.getOperand(0); 5156 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5157 Ld.getOpcode() == ISD::ConstantFP); 5158 5159 // The scalar_to_vector node and the suspected 5160 // load node must have exactly one user. 5161 // Constants may have multiple users. 5162 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 5163 return SDValue(); 5164 break; 5165 } 5166 } 5167 5168 bool Is256 = VT.is256BitVector(); 5169 5170 // Handle the broadcasting a single constant scalar from the constant pool 5171 // into a vector. On Sandybridge it is still better to load a constant vector 5172 // from the constant pool and not to broadcast it from a scalar. 5173 if (ConstSplatVal && Subtarget->hasInt256()) { 5174 EVT CVT = Ld.getValueType(); 5175 assert(!CVT.isVector() && "Must not broadcast a vector type"); 5176 unsigned ScalarSize = CVT.getSizeInBits(); 5177 5178 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) { 5179 const Constant *C = 0; 5180 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 5181 C = CI->getConstantIntValue(); 5182 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 5183 C = CF->getConstantFPValue(); 5184 5185 assert(C && "Invalid constant type"); 5186 5187 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 5188 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 5189 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 5190 MachinePointerInfo::getConstantPool(), 5191 false, false, false, Alignment); 5192 5193 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5194 } 5195 } 5196 5197 bool IsLoad = ISD::isNormalLoad(Ld.getNode()); 5198 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5199 5200 // Handle AVX2 in-register broadcasts. 5201 if (!IsLoad && Subtarget->hasInt256() && 5202 (ScalarSize == 32 || (Is256 && ScalarSize == 64))) 5203 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5204 5205 // The scalar source must be a normal load. 5206 if (!IsLoad) 5207 return SDValue(); 5208 5209 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) 5210 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5211 5212 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5213 // double since there is no vbroadcastsd xmm 5214 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) { 5215 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64) 5216 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5217 } 5218 5219 // Unsupported broadcast. 5220 return SDValue(); 5221} 5222 5223SDValue 5224X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const { 5225 EVT VT = Op.getValueType(); 5226 5227 // Skip if insert_vec_elt is not supported. 5228 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) 5229 return SDValue(); 5230 5231 DebugLoc DL = Op.getDebugLoc(); 5232 unsigned NumElems = Op.getNumOperands(); 5233 5234 SDValue VecIn1; 5235 SDValue VecIn2; 5236 SmallVector<unsigned, 4> InsertIndices; 5237 SmallVector<int, 8> Mask(NumElems, -1); 5238 5239 for (unsigned i = 0; i != NumElems; ++i) { 5240 unsigned Opc = Op.getOperand(i).getOpcode(); 5241 5242 if (Opc == ISD::UNDEF) 5243 continue; 5244 5245 if (Opc != ISD::EXTRACT_VECTOR_ELT) { 5246 // Quit if more than 1 elements need inserting. 5247 if (InsertIndices.size() > 1) 5248 return SDValue(); 5249 5250 InsertIndices.push_back(i); 5251 continue; 5252 } 5253 5254 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0); 5255 SDValue ExtIdx = Op.getOperand(i).getOperand(1); 5256 5257 // Quit if extracted from vector of different type. 5258 if (ExtractedFromVec.getValueType() != VT) 5259 return SDValue(); 5260 5261 // Quit if non-constant index. 5262 if (!isa<ConstantSDNode>(ExtIdx)) 5263 return SDValue(); 5264 5265 if (VecIn1.getNode() == 0) 5266 VecIn1 = ExtractedFromVec; 5267 else if (VecIn1 != ExtractedFromVec) { 5268 if (VecIn2.getNode() == 0) 5269 VecIn2 = ExtractedFromVec; 5270 else if (VecIn2 != ExtractedFromVec) 5271 // Quit if more than 2 vectors to shuffle 5272 return SDValue(); 5273 } 5274 5275 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue(); 5276 5277 if (ExtractedFromVec == VecIn1) 5278 Mask[i] = Idx; 5279 else if (ExtractedFromVec == VecIn2) 5280 Mask[i] = Idx + NumElems; 5281 } 5282 5283 if (VecIn1.getNode() == 0) 5284 return SDValue(); 5285 5286 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5287 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]); 5288 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) { 5289 unsigned Idx = InsertIndices[i]; 5290 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx), 5291 DAG.getIntPtrConstant(Idx)); 5292 } 5293 5294 return NV; 5295} 5296 5297SDValue 5298X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5299 DebugLoc dl = Op.getDebugLoc(); 5300 5301 MVT VT = Op.getValueType().getSimpleVT(); 5302 MVT ExtVT = VT.getVectorElementType(); 5303 unsigned NumElems = Op.getNumOperands(); 5304 5305 // Vectors containing all zeros can be matched by pxor and xorps later 5306 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5307 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5308 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5309 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5310 return Op; 5311 5312 return getZeroVector(VT, Subtarget, DAG, dl); 5313 } 5314 5315 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5316 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5317 // vpcmpeqd on 256-bit vectors. 5318 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5319 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256())) 5320 return Op; 5321 5322 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl); 5323 } 5324 5325 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5326 if (Broadcast.getNode()) 5327 return Broadcast; 5328 5329 unsigned EVTBits = ExtVT.getSizeInBits(); 5330 5331 unsigned NumZero = 0; 5332 unsigned NumNonZero = 0; 5333 unsigned NonZeros = 0; 5334 bool IsAllConstants = true; 5335 SmallSet<SDValue, 8> Values; 5336 for (unsigned i = 0; i < NumElems; ++i) { 5337 SDValue Elt = Op.getOperand(i); 5338 if (Elt.getOpcode() == ISD::UNDEF) 5339 continue; 5340 Values.insert(Elt); 5341 if (Elt.getOpcode() != ISD::Constant && 5342 Elt.getOpcode() != ISD::ConstantFP) 5343 IsAllConstants = false; 5344 if (X86::isZeroNode(Elt)) 5345 NumZero++; 5346 else { 5347 NonZeros |= (1 << i); 5348 NumNonZero++; 5349 } 5350 } 5351 5352 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5353 if (NumNonZero == 0) 5354 return DAG.getUNDEF(VT); 5355 5356 // Special case for single non-zero, non-undef, element. 5357 if (NumNonZero == 1) { 5358 unsigned Idx = CountTrailingZeros_32(NonZeros); 5359 SDValue Item = Op.getOperand(Idx); 5360 5361 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5362 // the value are obviously zero, truncate the value to i32 and do the 5363 // insertion that way. Only do this if the value is non-constant or if the 5364 // value is a constant being inserted into element 0. It is cheaper to do 5365 // a constant pool load than it is to do a movd + shuffle. 5366 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5367 (!IsAllConstants || Idx == 0)) { 5368 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5369 // Handle SSE only. 5370 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5371 EVT VecVT = MVT::v4i32; 5372 unsigned VecElts = 4; 5373 5374 // Truncate the value (which may itself be a constant) to i32, and 5375 // convert it to a vector with movd (S2V+shuffle to zero extend). 5376 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5377 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5378 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5379 5380 // Now we have our 32-bit value zero extended in the low element of 5381 // a vector. If Idx != 0, swizzle it into place. 5382 if (Idx != 0) { 5383 SmallVector<int, 4> Mask; 5384 Mask.push_back(Idx); 5385 for (unsigned i = 1; i != VecElts; ++i) 5386 Mask.push_back(i); 5387 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5388 &Mask[0]); 5389 } 5390 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5391 } 5392 } 5393 5394 // If we have a constant or non-constant insertion into the low element of 5395 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5396 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5397 // depending on what the source datatype is. 5398 if (Idx == 0) { 5399 if (NumZero == 0) 5400 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5401 5402 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5403 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5404 if (VT.is256BitVector()) { 5405 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5406 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5407 Item, DAG.getIntPtrConstant(0)); 5408 } 5409 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5410 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5411 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5412 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5413 } 5414 5415 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5416 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5417 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5418 if (VT.is256BitVector()) { 5419 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5420 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5421 } else { 5422 assert(VT.is128BitVector() && "Expected an SSE value type!"); 5423 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5424 } 5425 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5426 } 5427 } 5428 5429 // Is it a vector logical left shift? 5430 if (NumElems == 2 && Idx == 1 && 5431 X86::isZeroNode(Op.getOperand(0)) && 5432 !X86::isZeroNode(Op.getOperand(1))) { 5433 unsigned NumBits = VT.getSizeInBits(); 5434 return getVShift(true, VT, 5435 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5436 VT, Op.getOperand(1)), 5437 NumBits/2, DAG, *this, dl); 5438 } 5439 5440 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5441 return SDValue(); 5442 5443 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5444 // is a non-constant being inserted into an element other than the low one, 5445 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5446 // movd/movss) to move this into the low element, then shuffle it into 5447 // place. 5448 if (EVTBits == 32) { 5449 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5450 5451 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5452 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5453 SmallVector<int, 8> MaskVec; 5454 for (unsigned i = 0; i != NumElems; ++i) 5455 MaskVec.push_back(i == Idx ? 0 : 1); 5456 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5457 } 5458 } 5459 5460 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5461 if (Values.size() == 1) { 5462 if (EVTBits == 32) { 5463 // Instead of a shuffle like this: 5464 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5465 // Check if it's possible to issue this instead. 5466 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5467 unsigned Idx = CountTrailingZeros_32(NonZeros); 5468 SDValue Item = Op.getOperand(Idx); 5469 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5470 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5471 } 5472 return SDValue(); 5473 } 5474 5475 // A vector full of immediates; various special cases are already 5476 // handled, so this is best done with a single constant-pool load. 5477 if (IsAllConstants) 5478 return SDValue(); 5479 5480 // For AVX-length vectors, build the individual 128-bit pieces and use 5481 // shuffles to put them in place. 5482 if (VT.is256BitVector()) { 5483 SmallVector<SDValue, 32> V; 5484 for (unsigned i = 0; i != NumElems; ++i) 5485 V.push_back(Op.getOperand(i)); 5486 5487 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5488 5489 // Build both the lower and upper subvector. 5490 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5491 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5492 NumElems/2); 5493 5494 // Recreate the wider vector with the lower and upper part. 5495 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5496 } 5497 5498 // Let legalizer expand 2-wide build_vectors. 5499 if (EVTBits == 64) { 5500 if (NumNonZero == 1) { 5501 // One half is zero or undef. 5502 unsigned Idx = CountTrailingZeros_32(NonZeros); 5503 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5504 Op.getOperand(Idx)); 5505 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5506 } 5507 return SDValue(); 5508 } 5509 5510 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5511 if (EVTBits == 8 && NumElems == 16) { 5512 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5513 Subtarget, *this); 5514 if (V.getNode()) return V; 5515 } 5516 5517 if (EVTBits == 16 && NumElems == 8) { 5518 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5519 Subtarget, *this); 5520 if (V.getNode()) return V; 5521 } 5522 5523 // If element VT is == 32 bits, turn it into a number of shuffles. 5524 SmallVector<SDValue, 8> V(NumElems); 5525 if (NumElems == 4 && NumZero > 0) { 5526 for (unsigned i = 0; i < 4; ++i) { 5527 bool isZero = !(NonZeros & (1 << i)); 5528 if (isZero) 5529 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5530 else 5531 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5532 } 5533 5534 for (unsigned i = 0; i < 2; ++i) { 5535 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5536 default: break; 5537 case 0: 5538 V[i] = V[i*2]; // Must be a zero vector. 5539 break; 5540 case 1: 5541 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5542 break; 5543 case 2: 5544 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5545 break; 5546 case 3: 5547 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5548 break; 5549 } 5550 } 5551 5552 bool Reverse1 = (NonZeros & 0x3) == 2; 5553 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5554 int MaskVec[] = { 5555 Reverse1 ? 1 : 0, 5556 Reverse1 ? 0 : 1, 5557 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5558 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5559 }; 5560 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5561 } 5562 5563 if (Values.size() > 1 && VT.is128BitVector()) { 5564 // Check for a build vector of consecutive loads. 5565 for (unsigned i = 0; i < NumElems; ++i) 5566 V[i] = Op.getOperand(i); 5567 5568 // Check for elements which are consecutive loads. 5569 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5570 if (LD.getNode()) 5571 return LD; 5572 5573 // Check for a build vector from mostly shuffle plus few inserting. 5574 SDValue Sh = buildFromShuffleMostly(Op, DAG); 5575 if (Sh.getNode()) 5576 return Sh; 5577 5578 // For SSE 4.1, use insertps to put the high elements into the low element. 5579 if (getSubtarget()->hasSSE41()) { 5580 SDValue Result; 5581 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5582 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5583 else 5584 Result = DAG.getUNDEF(VT); 5585 5586 for (unsigned i = 1; i < NumElems; ++i) { 5587 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5588 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5589 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5590 } 5591 return Result; 5592 } 5593 5594 // Otherwise, expand into a number of unpckl*, start by extending each of 5595 // our (non-undef) elements to the full vector width with the element in the 5596 // bottom slot of the vector (which generates no code for SSE). 5597 for (unsigned i = 0; i < NumElems; ++i) { 5598 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5599 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5600 else 5601 V[i] = DAG.getUNDEF(VT); 5602 } 5603 5604 // Next, we iteratively mix elements, e.g. for v4f32: 5605 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5606 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5607 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5608 unsigned EltStride = NumElems >> 1; 5609 while (EltStride != 0) { 5610 for (unsigned i = 0; i < EltStride; ++i) { 5611 // If V[i+EltStride] is undef and this is the first round of mixing, 5612 // then it is safe to just drop this shuffle: V[i] is already in the 5613 // right place, the one element (since it's the first round) being 5614 // inserted as undef can be dropped. This isn't safe for successive 5615 // rounds because they will permute elements within both vectors. 5616 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5617 EltStride == NumElems/2) 5618 continue; 5619 5620 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5621 } 5622 EltStride >>= 1; 5623 } 5624 return V[0]; 5625 } 5626 return SDValue(); 5627} 5628 5629// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5630// to create 256-bit vectors from two other 128-bit ones. 5631static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5632 DebugLoc dl = Op.getDebugLoc(); 5633 MVT ResVT = Op.getValueType().getSimpleVT(); 5634 5635 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide"); 5636 5637 SDValue V1 = Op.getOperand(0); 5638 SDValue V2 = Op.getOperand(1); 5639 unsigned NumElems = ResVT.getVectorNumElements(); 5640 5641 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5642} 5643 5644static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5645 assert(Op.getNumOperands() == 2); 5646 5647 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5648 // from two other 128-bit ones. 5649 return LowerAVXCONCAT_VECTORS(Op, DAG); 5650} 5651 5652// Try to lower a shuffle node into a simple blend instruction. 5653static SDValue 5654LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5655 const X86Subtarget *Subtarget, SelectionDAG &DAG) { 5656 SDValue V1 = SVOp->getOperand(0); 5657 SDValue V2 = SVOp->getOperand(1); 5658 DebugLoc dl = SVOp->getDebugLoc(); 5659 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5660 MVT EltVT = VT.getVectorElementType(); 5661 unsigned NumElems = VT.getVectorNumElements(); 5662 5663 if (!Subtarget->hasSSE41() || EltVT == MVT::i8) 5664 return SDValue(); 5665 if (!Subtarget->hasInt256() && VT == MVT::v16i16) 5666 return SDValue(); 5667 5668 // Check the mask for BLEND and build the value. 5669 unsigned MaskValue = 0; 5670 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise. 5671 unsigned NumLanes = (NumElems-1)/8 + 1; 5672 unsigned NumElemsInLane = NumElems / NumLanes; 5673 5674 // Blend for v16i16 should be symetric for the both lanes. 5675 for (unsigned i = 0; i < NumElemsInLane; ++i) { 5676 5677 int SndLaneEltIdx = (NumLanes == 2) ? 5678 SVOp->getMaskElt(i + NumElemsInLane) : -1; 5679 int EltIdx = SVOp->getMaskElt(i); 5680 5681 if ((EltIdx == -1 || EltIdx == (int)i) && 5682 (SndLaneEltIdx == -1 || SndLaneEltIdx == (int)(i + NumElemsInLane))) 5683 continue; 5684 5685 if (((unsigned)EltIdx == (i + NumElems)) && 5686 (SndLaneEltIdx == -1 || 5687 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane)) 5688 MaskValue |= (1<<i); 5689 else 5690 return SDValue(); 5691 } 5692 5693 // Convert i32 vectors to floating point if it is not AVX2. 5694 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors. 5695 EVT BlendVT = VT; 5696 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) { 5697 BlendVT = EVT::getVectorVT(*DAG.getContext(), 5698 EVT::getFloatingPointVT(EltVT.getSizeInBits()), 5699 NumElems); 5700 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1); 5701 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2); 5702 } 5703 5704 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2, 5705 DAG.getConstant(MaskValue, MVT::i32)); 5706 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5707} 5708 5709// v8i16 shuffles - Prefer shuffles in the following order: 5710// 1. [all] pshuflw, pshufhw, optional move 5711// 2. [ssse3] 1 x pshufb 5712// 3. [ssse3] 2 x pshufb + 1 x por 5713// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5714static SDValue 5715LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget, 5716 SelectionDAG &DAG) { 5717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5718 SDValue V1 = SVOp->getOperand(0); 5719 SDValue V2 = SVOp->getOperand(1); 5720 DebugLoc dl = SVOp->getDebugLoc(); 5721 SmallVector<int, 8> MaskVals; 5722 5723 // Determine if more than 1 of the words in each of the low and high quadwords 5724 // of the result come from the same quadword of one of the two inputs. Undef 5725 // mask values count as coming from any quadword, for better codegen. 5726 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5727 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5728 std::bitset<4> InputQuads; 5729 for (unsigned i = 0; i < 8; ++i) { 5730 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5731 int EltIdx = SVOp->getMaskElt(i); 5732 MaskVals.push_back(EltIdx); 5733 if (EltIdx < 0) { 5734 ++Quad[0]; 5735 ++Quad[1]; 5736 ++Quad[2]; 5737 ++Quad[3]; 5738 continue; 5739 } 5740 ++Quad[EltIdx / 4]; 5741 InputQuads.set(EltIdx / 4); 5742 } 5743 5744 int BestLoQuad = -1; 5745 unsigned MaxQuad = 1; 5746 for (unsigned i = 0; i < 4; ++i) { 5747 if (LoQuad[i] > MaxQuad) { 5748 BestLoQuad = i; 5749 MaxQuad = LoQuad[i]; 5750 } 5751 } 5752 5753 int BestHiQuad = -1; 5754 MaxQuad = 1; 5755 for (unsigned i = 0; i < 4; ++i) { 5756 if (HiQuad[i] > MaxQuad) { 5757 BestHiQuad = i; 5758 MaxQuad = HiQuad[i]; 5759 } 5760 } 5761 5762 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5763 // of the two input vectors, shuffle them into one input vector so only a 5764 // single pshufb instruction is necessary. If There are more than 2 input 5765 // quads, disable the next transformation since it does not help SSSE3. 5766 bool V1Used = InputQuads[0] || InputQuads[1]; 5767 bool V2Used = InputQuads[2] || InputQuads[3]; 5768 if (Subtarget->hasSSSE3()) { 5769 if (InputQuads.count() == 2 && V1Used && V2Used) { 5770 BestLoQuad = InputQuads[0] ? 0 : 1; 5771 BestHiQuad = InputQuads[2] ? 2 : 3; 5772 } 5773 if (InputQuads.count() > 2) { 5774 BestLoQuad = -1; 5775 BestHiQuad = -1; 5776 } 5777 } 5778 5779 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5780 // the shuffle mask. If a quad is scored as -1, that means that it contains 5781 // words from all 4 input quadwords. 5782 SDValue NewV; 5783 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5784 int MaskV[] = { 5785 BestLoQuad < 0 ? 0 : BestLoQuad, 5786 BestHiQuad < 0 ? 1 : BestHiQuad 5787 }; 5788 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5789 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5790 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5791 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5792 5793 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5794 // source words for the shuffle, to aid later transformations. 5795 bool AllWordsInNewV = true; 5796 bool InOrder[2] = { true, true }; 5797 for (unsigned i = 0; i != 8; ++i) { 5798 int idx = MaskVals[i]; 5799 if (idx != (int)i) 5800 InOrder[i/4] = false; 5801 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5802 continue; 5803 AllWordsInNewV = false; 5804 break; 5805 } 5806 5807 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5808 if (AllWordsInNewV) { 5809 for (int i = 0; i != 8; ++i) { 5810 int idx = MaskVals[i]; 5811 if (idx < 0) 5812 continue; 5813 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5814 if ((idx != i) && idx < 4) 5815 pshufhw = false; 5816 if ((idx != i) && idx > 3) 5817 pshuflw = false; 5818 } 5819 V1 = NewV; 5820 V2Used = false; 5821 BestLoQuad = 0; 5822 BestHiQuad = 1; 5823 } 5824 5825 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5826 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5827 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5828 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5829 unsigned TargetMask = 0; 5830 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5831 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5833 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5834 getShufflePSHUFLWImmediate(SVOp); 5835 V1 = NewV.getOperand(0); 5836 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5837 } 5838 } 5839 5840 // If we have SSSE3, and all words of the result are from 1 input vector, 5841 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5842 // is present, fall back to case 4. 5843 if (Subtarget->hasSSSE3()) { 5844 SmallVector<SDValue,16> pshufbMask; 5845 5846 // If we have elements from both input vectors, set the high bit of the 5847 // shuffle mask element to zero out elements that come from V2 in the V1 5848 // mask, and elements that come from V1 in the V2 mask, so that the two 5849 // results can be OR'd together. 5850 bool TwoInputs = V1Used && V2Used; 5851 for (unsigned i = 0; i != 8; ++i) { 5852 int EltIdx = MaskVals[i] * 2; 5853 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx; 5854 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1; 5855 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5856 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5857 } 5858 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5859 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5860 DAG.getNode(ISD::BUILD_VECTOR, dl, 5861 MVT::v16i8, &pshufbMask[0], 16)); 5862 if (!TwoInputs) 5863 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5864 5865 // Calculate the shuffle mask for the second input, shuffle it, and 5866 // OR it with the first shuffled input. 5867 pshufbMask.clear(); 5868 for (unsigned i = 0; i != 8; ++i) { 5869 int EltIdx = MaskVals[i] * 2; 5870 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16; 5871 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15; 5872 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5873 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5874 } 5875 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5876 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5877 DAG.getNode(ISD::BUILD_VECTOR, dl, 5878 MVT::v16i8, &pshufbMask[0], 16)); 5879 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5880 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5881 } 5882 5883 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5884 // and update MaskVals with new element order. 5885 std::bitset<8> InOrder; 5886 if (BestLoQuad >= 0) { 5887 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5888 for (int i = 0; i != 4; ++i) { 5889 int idx = MaskVals[i]; 5890 if (idx < 0) { 5891 InOrder.set(i); 5892 } else if ((idx / 4) == BestLoQuad) { 5893 MaskV[i] = idx & 3; 5894 InOrder.set(i); 5895 } 5896 } 5897 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5898 &MaskV[0]); 5899 5900 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5902 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5903 NewV.getOperand(0), 5904 getShufflePSHUFLWImmediate(SVOp), DAG); 5905 } 5906 } 5907 5908 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5909 // and update MaskVals with the new element order. 5910 if (BestHiQuad >= 0) { 5911 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5912 for (unsigned i = 4; i != 8; ++i) { 5913 int idx = MaskVals[i]; 5914 if (idx < 0) { 5915 InOrder.set(i); 5916 } else if ((idx / 4) == BestHiQuad) { 5917 MaskV[i] = (idx & 3) + 4; 5918 InOrder.set(i); 5919 } 5920 } 5921 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5922 &MaskV[0]); 5923 5924 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5925 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5926 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5927 NewV.getOperand(0), 5928 getShufflePSHUFHWImmediate(SVOp), DAG); 5929 } 5930 } 5931 5932 // In case BestHi & BestLo were both -1, which means each quadword has a word 5933 // from each of the four input quadwords, calculate the InOrder bitvector now 5934 // before falling through to the insert/extract cleanup. 5935 if (BestLoQuad == -1 && BestHiQuad == -1) { 5936 NewV = V1; 5937 for (int i = 0; i != 8; ++i) 5938 if (MaskVals[i] < 0 || MaskVals[i] == i) 5939 InOrder.set(i); 5940 } 5941 5942 // The other elements are put in the right place using pextrw and pinsrw. 5943 for (unsigned i = 0; i != 8; ++i) { 5944 if (InOrder[i]) 5945 continue; 5946 int EltIdx = MaskVals[i]; 5947 if (EltIdx < 0) 5948 continue; 5949 SDValue ExtOp = (EltIdx < 8) ? 5950 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5951 DAG.getIntPtrConstant(EltIdx)) : 5952 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5953 DAG.getIntPtrConstant(EltIdx - 8)); 5954 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5955 DAG.getIntPtrConstant(i)); 5956 } 5957 return NewV; 5958} 5959 5960// v16i8 shuffles - Prefer shuffles in the following order: 5961// 1. [ssse3] 1 x pshufb 5962// 2. [ssse3] 2 x pshufb + 1 x por 5963// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5964static 5965SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5966 SelectionDAG &DAG, 5967 const X86TargetLowering &TLI) { 5968 SDValue V1 = SVOp->getOperand(0); 5969 SDValue V2 = SVOp->getOperand(1); 5970 DebugLoc dl = SVOp->getDebugLoc(); 5971 ArrayRef<int> MaskVals = SVOp->getMask(); 5972 5973 // If we have SSSE3, case 1 is generated when all result bytes come from 5974 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5975 // present, fall back to case 3. 5976 5977 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5978 if (TLI.getSubtarget()->hasSSSE3()) { 5979 SmallVector<SDValue,16> pshufbMask; 5980 5981 // If all result elements are from one input vector, then only translate 5982 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5983 // 5984 // Otherwise, we have elements from both input vectors, and must zero out 5985 // elements that come from V2 in the first mask, and V1 in the second mask 5986 // so that we can OR them together. 5987 for (unsigned i = 0; i != 16; ++i) { 5988 int EltIdx = MaskVals[i]; 5989 if (EltIdx < 0 || EltIdx >= 16) 5990 EltIdx = 0x80; 5991 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5992 } 5993 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5994 DAG.getNode(ISD::BUILD_VECTOR, dl, 5995 MVT::v16i8, &pshufbMask[0], 16)); 5996 5997 // As PSHUFB will zero elements with negative indices, it's safe to ignore 5998 // the 2nd operand if it's undefined or zero. 5999 if (V2.getOpcode() == ISD::UNDEF || 6000 ISD::isBuildVectorAllZeros(V2.getNode())) 6001 return V1; 6002 6003 // Calculate the shuffle mask for the second input, shuffle it, and 6004 // OR it with the first shuffled input. 6005 pshufbMask.clear(); 6006 for (unsigned i = 0; i != 16; ++i) { 6007 int EltIdx = MaskVals[i]; 6008 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16; 6009 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6010 } 6011 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 6012 DAG.getNode(ISD::BUILD_VECTOR, dl, 6013 MVT::v16i8, &pshufbMask[0], 16)); 6014 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 6015 } 6016 6017 // No SSSE3 - Calculate in place words and then fix all out of place words 6018 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 6019 // the 16 different words that comprise the two doublequadword input vectors. 6020 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 6021 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 6022 SDValue NewV = V1; 6023 for (int i = 0; i != 8; ++i) { 6024 int Elt0 = MaskVals[i*2]; 6025 int Elt1 = MaskVals[i*2+1]; 6026 6027 // This word of the result is all undef, skip it. 6028 if (Elt0 < 0 && Elt1 < 0) 6029 continue; 6030 6031 // This word of the result is already in the correct place, skip it. 6032 if ((Elt0 == i*2) && (Elt1 == i*2+1)) 6033 continue; 6034 6035 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 6036 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 6037 SDValue InsElt; 6038 6039 // If Elt0 and Elt1 are defined, are consecutive, and can be load 6040 // using a single extract together, load it and store it. 6041 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 6042 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6043 DAG.getIntPtrConstant(Elt1 / 2)); 6044 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6045 DAG.getIntPtrConstant(i)); 6046 continue; 6047 } 6048 6049 // If Elt1 is defined, extract it from the appropriate source. If the 6050 // source byte is not also odd, shift the extracted word left 8 bits 6051 // otherwise clear the bottom 8 bits if we need to do an or. 6052 if (Elt1 >= 0) { 6053 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 6054 DAG.getIntPtrConstant(Elt1 / 2)); 6055 if ((Elt1 & 1) == 0) 6056 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 6057 DAG.getConstant(8, 6058 TLI.getShiftAmountTy(InsElt.getValueType()))); 6059 else if (Elt0 >= 0) 6060 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 6061 DAG.getConstant(0xFF00, MVT::i16)); 6062 } 6063 // If Elt0 is defined, extract it from the appropriate source. If the 6064 // source byte is not also even, shift the extracted word right 8 bits. If 6065 // Elt1 was also defined, OR the extracted values together before 6066 // inserting them in the result. 6067 if (Elt0 >= 0) { 6068 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 6069 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 6070 if ((Elt0 & 1) != 0) 6071 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 6072 DAG.getConstant(8, 6073 TLI.getShiftAmountTy(InsElt0.getValueType()))); 6074 else if (Elt1 >= 0) 6075 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 6076 DAG.getConstant(0x00FF, MVT::i16)); 6077 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 6078 : InsElt0; 6079 } 6080 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 6081 DAG.getIntPtrConstant(i)); 6082 } 6083 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 6084} 6085 6086// v32i8 shuffles - Translate to VPSHUFB if possible. 6087static 6088SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, 6089 const X86Subtarget *Subtarget, 6090 SelectionDAG &DAG) { 6091 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6092 SDValue V1 = SVOp->getOperand(0); 6093 SDValue V2 = SVOp->getOperand(1); 6094 DebugLoc dl = SVOp->getDebugLoc(); 6095 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end()); 6096 6097 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6098 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode()); 6099 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode()); 6100 6101 // VPSHUFB may be generated if 6102 // (1) one of input vector is undefined or zeroinitializer. 6103 // The mask value 0x80 puts 0 in the corresponding slot of the vector. 6104 // And (2) the mask indexes don't cross the 128-bit lane. 6105 if (VT != MVT::v32i8 || !Subtarget->hasInt256() || 6106 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero)) 6107 return SDValue(); 6108 6109 if (V1IsAllZero && !V2IsAllZero) { 6110 CommuteVectorShuffleMask(MaskVals, 32); 6111 V1 = V2; 6112 } 6113 SmallVector<SDValue, 32> pshufbMask; 6114 for (unsigned i = 0; i != 32; i++) { 6115 int EltIdx = MaskVals[i]; 6116 if (EltIdx < 0 || EltIdx >= 32) 6117 EltIdx = 0x80; 6118 else { 6119 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16)) 6120 // Cross lane is not allowed. 6121 return SDValue(); 6122 EltIdx &= 0xf; 6123 } 6124 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 6125 } 6126 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1, 6127 DAG.getNode(ISD::BUILD_VECTOR, dl, 6128 MVT::v32i8, &pshufbMask[0], 32)); 6129} 6130 6131/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 6132/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 6133/// done when every pair / quad of shuffle mask elements point to elements in 6134/// the right sequence. e.g. 6135/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 6136static 6137SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 6138 SelectionDAG &DAG) { 6139 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6140 DebugLoc dl = SVOp->getDebugLoc(); 6141 unsigned NumElems = VT.getVectorNumElements(); 6142 MVT NewVT; 6143 unsigned Scale; 6144 switch (VT.SimpleTy) { 6145 default: llvm_unreachable("Unexpected!"); 6146 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 6147 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 6148 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 6149 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 6150 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 6151 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 6152 } 6153 6154 SmallVector<int, 8> MaskVec; 6155 for (unsigned i = 0; i != NumElems; i += Scale) { 6156 int StartIdx = -1; 6157 for (unsigned j = 0; j != Scale; ++j) { 6158 int EltIdx = SVOp->getMaskElt(i+j); 6159 if (EltIdx < 0) 6160 continue; 6161 if (StartIdx < 0) 6162 StartIdx = (EltIdx / Scale); 6163 if (EltIdx != (int)(StartIdx*Scale + j)) 6164 return SDValue(); 6165 } 6166 MaskVec.push_back(StartIdx); 6167 } 6168 6169 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 6170 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 6171 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 6172} 6173 6174/// getVZextMovL - Return a zero-extending vector move low node. 6175/// 6176static SDValue getVZextMovL(MVT VT, EVT OpVT, 6177 SDValue SrcOp, SelectionDAG &DAG, 6178 const X86Subtarget *Subtarget, DebugLoc dl) { 6179 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 6180 LoadSDNode *LD = NULL; 6181 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 6182 LD = dyn_cast<LoadSDNode>(SrcOp); 6183 if (!LD) { 6184 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 6185 // instead. 6186 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 6187 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 6188 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 6189 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 6190 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 6191 // PR2108 6192 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 6193 return DAG.getNode(ISD::BITCAST, dl, VT, 6194 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6195 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6196 OpVT, 6197 SrcOp.getOperand(0) 6198 .getOperand(0)))); 6199 } 6200 } 6201 } 6202 6203 return DAG.getNode(ISD::BITCAST, dl, VT, 6204 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6205 DAG.getNode(ISD::BITCAST, dl, 6206 OpVT, SrcOp))); 6207} 6208 6209/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6210/// which could not be matched by any known target speficic shuffle 6211static SDValue 6212LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6213 6214 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG); 6215 if (NewOp.getNode()) 6216 return NewOp; 6217 6218 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6219 6220 unsigned NumElems = VT.getVectorNumElements(); 6221 unsigned NumLaneElems = NumElems / 2; 6222 6223 DebugLoc dl = SVOp->getDebugLoc(); 6224 MVT EltVT = VT.getVectorElementType(); 6225 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 6226 SDValue Output[2]; 6227 6228 SmallVector<int, 16> Mask; 6229 for (unsigned l = 0; l < 2; ++l) { 6230 // Build a shuffle mask for the output, discovering on the fly which 6231 // input vectors to use as shuffle operands (recorded in InputUsed). 6232 // If building a suitable shuffle vector proves too hard, then bail 6233 // out with UseBuildVector set. 6234 bool UseBuildVector = false; 6235 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 6236 unsigned LaneStart = l * NumLaneElems; 6237 for (unsigned i = 0; i != NumLaneElems; ++i) { 6238 // The mask element. This indexes into the input. 6239 int Idx = SVOp->getMaskElt(i+LaneStart); 6240 if (Idx < 0) { 6241 // the mask element does not index into any input vector. 6242 Mask.push_back(-1); 6243 continue; 6244 } 6245 6246 // The input vector this mask element indexes into. 6247 int Input = Idx / NumLaneElems; 6248 6249 // Turn the index into an offset from the start of the input vector. 6250 Idx -= Input * NumLaneElems; 6251 6252 // Find or create a shuffle vector operand to hold this input. 6253 unsigned OpNo; 6254 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6255 if (InputUsed[OpNo] == Input) 6256 // This input vector is already an operand. 6257 break; 6258 if (InputUsed[OpNo] < 0) { 6259 // Create a new operand for this input vector. 6260 InputUsed[OpNo] = Input; 6261 break; 6262 } 6263 } 6264 6265 if (OpNo >= array_lengthof(InputUsed)) { 6266 // More than two input vectors used! Give up on trying to create a 6267 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 6268 UseBuildVector = true; 6269 break; 6270 } 6271 6272 // Add the mask index for the new shuffle vector. 6273 Mask.push_back(Idx + OpNo * NumLaneElems); 6274 } 6275 6276 if (UseBuildVector) { 6277 SmallVector<SDValue, 16> SVOps; 6278 for (unsigned i = 0; i != NumLaneElems; ++i) { 6279 // The mask element. This indexes into the input. 6280 int Idx = SVOp->getMaskElt(i+LaneStart); 6281 if (Idx < 0) { 6282 SVOps.push_back(DAG.getUNDEF(EltVT)); 6283 continue; 6284 } 6285 6286 // The input vector this mask element indexes into. 6287 int Input = Idx / NumElems; 6288 6289 // Turn the index into an offset from the start of the input vector. 6290 Idx -= Input * NumElems; 6291 6292 // Extract the vector element by hand. 6293 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 6294 SVOp->getOperand(Input), 6295 DAG.getIntPtrConstant(Idx))); 6296 } 6297 6298 // Construct the output using a BUILD_VECTOR. 6299 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0], 6300 SVOps.size()); 6301 } else if (InputUsed[0] < 0) { 6302 // No input vectors were used! The result is undefined. 6303 Output[l] = DAG.getUNDEF(NVT); 6304 } else { 6305 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6306 (InputUsed[0] % 2) * NumLaneElems, 6307 DAG, dl); 6308 // If only one input was used, use an undefined vector for the other. 6309 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6310 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6311 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6312 // At least one input vector was used. Create a new shuffle vector. 6313 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6314 } 6315 6316 Mask.clear(); 6317 } 6318 6319 // Concatenate the result back 6320 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]); 6321} 6322 6323/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6324/// 4 elements, and match them with several different shuffle types. 6325static SDValue 6326LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6327 SDValue V1 = SVOp->getOperand(0); 6328 SDValue V2 = SVOp->getOperand(1); 6329 DebugLoc dl = SVOp->getDebugLoc(); 6330 MVT VT = SVOp->getValueType(0).getSimpleVT(); 6331 6332 assert(VT.is128BitVector() && "Unsupported vector size"); 6333 6334 std::pair<int, int> Locs[4]; 6335 int Mask1[] = { -1, -1, -1, -1 }; 6336 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6337 6338 unsigned NumHi = 0; 6339 unsigned NumLo = 0; 6340 for (unsigned i = 0; i != 4; ++i) { 6341 int Idx = PermMask[i]; 6342 if (Idx < 0) { 6343 Locs[i] = std::make_pair(-1, -1); 6344 } else { 6345 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6346 if (Idx < 4) { 6347 Locs[i] = std::make_pair(0, NumLo); 6348 Mask1[NumLo] = Idx; 6349 NumLo++; 6350 } else { 6351 Locs[i] = std::make_pair(1, NumHi); 6352 if (2+NumHi < 4) 6353 Mask1[2+NumHi] = Idx; 6354 NumHi++; 6355 } 6356 } 6357 } 6358 6359 if (NumLo <= 2 && NumHi <= 2) { 6360 // If no more than two elements come from either vector. This can be 6361 // implemented with two shuffles. First shuffle gather the elements. 6362 // The second shuffle, which takes the first shuffle as both of its 6363 // vector operands, put the elements into the right order. 6364 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6365 6366 int Mask2[] = { -1, -1, -1, -1 }; 6367 6368 for (unsigned i = 0; i != 4; ++i) 6369 if (Locs[i].first != -1) { 6370 unsigned Idx = (i < 2) ? 0 : 4; 6371 Idx += Locs[i].first * 2 + Locs[i].second; 6372 Mask2[i] = Idx; 6373 } 6374 6375 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6376 } 6377 6378 if (NumLo == 3 || NumHi == 3) { 6379 // Otherwise, we must have three elements from one vector, call it X, and 6380 // one element from the other, call it Y. First, use a shufps to build an 6381 // intermediate vector with the one element from Y and the element from X 6382 // that will be in the same half in the final destination (the indexes don't 6383 // matter). Then, use a shufps to build the final vector, taking the half 6384 // containing the element from Y from the intermediate, and the other half 6385 // from X. 6386 if (NumHi == 3) { 6387 // Normalize it so the 3 elements come from V1. 6388 CommuteVectorShuffleMask(PermMask, 4); 6389 std::swap(V1, V2); 6390 } 6391 6392 // Find the element from V2. 6393 unsigned HiIndex; 6394 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6395 int Val = PermMask[HiIndex]; 6396 if (Val < 0) 6397 continue; 6398 if (Val >= 4) 6399 break; 6400 } 6401 6402 Mask1[0] = PermMask[HiIndex]; 6403 Mask1[1] = -1; 6404 Mask1[2] = PermMask[HiIndex^1]; 6405 Mask1[3] = -1; 6406 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6407 6408 if (HiIndex >= 2) { 6409 Mask1[0] = PermMask[0]; 6410 Mask1[1] = PermMask[1]; 6411 Mask1[2] = HiIndex & 1 ? 6 : 4; 6412 Mask1[3] = HiIndex & 1 ? 4 : 6; 6413 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6414 } 6415 6416 Mask1[0] = HiIndex & 1 ? 2 : 0; 6417 Mask1[1] = HiIndex & 1 ? 0 : 2; 6418 Mask1[2] = PermMask[2]; 6419 Mask1[3] = PermMask[3]; 6420 if (Mask1[2] >= 0) 6421 Mask1[2] += 4; 6422 if (Mask1[3] >= 0) 6423 Mask1[3] += 4; 6424 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6425 } 6426 6427 // Break it into (shuffle shuffle_hi, shuffle_lo). 6428 int LoMask[] = { -1, -1, -1, -1 }; 6429 int HiMask[] = { -1, -1, -1, -1 }; 6430 6431 int *MaskPtr = LoMask; 6432 unsigned MaskIdx = 0; 6433 unsigned LoIdx = 0; 6434 unsigned HiIdx = 2; 6435 for (unsigned i = 0; i != 4; ++i) { 6436 if (i == 2) { 6437 MaskPtr = HiMask; 6438 MaskIdx = 1; 6439 LoIdx = 0; 6440 HiIdx = 2; 6441 } 6442 int Idx = PermMask[i]; 6443 if (Idx < 0) { 6444 Locs[i] = std::make_pair(-1, -1); 6445 } else if (Idx < 4) { 6446 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6447 MaskPtr[LoIdx] = Idx; 6448 LoIdx++; 6449 } else { 6450 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6451 MaskPtr[HiIdx] = Idx; 6452 HiIdx++; 6453 } 6454 } 6455 6456 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6457 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6458 int MaskOps[] = { -1, -1, -1, -1 }; 6459 for (unsigned i = 0; i != 4; ++i) 6460 if (Locs[i].first != -1) 6461 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6462 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6463} 6464 6465static bool MayFoldVectorLoad(SDValue V) { 6466 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6467 V = V.getOperand(0); 6468 6469 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6470 V = V.getOperand(0); 6471 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6472 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6473 // BUILD_VECTOR (load), undef 6474 V = V.getOperand(0); 6475 6476 return MayFoldLoad(V); 6477} 6478 6479static 6480SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6481 EVT VT = Op.getValueType(); 6482 6483 // Canonizalize to v2f64. 6484 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6485 return DAG.getNode(ISD::BITCAST, dl, VT, 6486 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6487 V1, DAG)); 6488} 6489 6490static 6491SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6492 bool HasSSE2) { 6493 SDValue V1 = Op.getOperand(0); 6494 SDValue V2 = Op.getOperand(1); 6495 EVT VT = Op.getValueType(); 6496 6497 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6498 6499 if (HasSSE2 && VT == MVT::v2f64) 6500 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6501 6502 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6503 return DAG.getNode(ISD::BITCAST, dl, VT, 6504 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6505 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6506 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6507} 6508 6509static 6510SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6511 SDValue V1 = Op.getOperand(0); 6512 SDValue V2 = Op.getOperand(1); 6513 EVT VT = Op.getValueType(); 6514 6515 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6516 "unsupported shuffle type"); 6517 6518 if (V2.getOpcode() == ISD::UNDEF) 6519 V2 = V1; 6520 6521 // v4i32 or v4f32 6522 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6523} 6524 6525static 6526SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6527 SDValue V1 = Op.getOperand(0); 6528 SDValue V2 = Op.getOperand(1); 6529 EVT VT = Op.getValueType(); 6530 unsigned NumElems = VT.getVectorNumElements(); 6531 6532 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6533 // operand of these instructions is only memory, so check if there's a 6534 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6535 // same masks. 6536 bool CanFoldLoad = false; 6537 6538 // Trivial case, when V2 comes from a load. 6539 if (MayFoldVectorLoad(V2)) 6540 CanFoldLoad = true; 6541 6542 // When V1 is a load, it can be folded later into a store in isel, example: 6543 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6544 // turns into: 6545 // (MOVLPSmr addr:$src1, VR128:$src2) 6546 // So, recognize this potential and also use MOVLPS or MOVLPD 6547 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6548 CanFoldLoad = true; 6549 6550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6551 if (CanFoldLoad) { 6552 if (HasSSE2 && NumElems == 2) 6553 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6554 6555 if (NumElems == 4) 6556 // If we don't care about the second element, proceed to use movss. 6557 if (SVOp->getMaskElt(1) != -1) 6558 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6559 } 6560 6561 // movl and movlp will both match v2i64, but v2i64 is never matched by 6562 // movl earlier because we make it strict to avoid messing with the movlp load 6563 // folding logic (see the code above getMOVLP call). Match it here then, 6564 // this is horrible, but will stay like this until we move all shuffle 6565 // matching to x86 specific nodes. Note that for the 1st condition all 6566 // types are matched with movsd. 6567 if (HasSSE2) { 6568 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6569 // as to remove this logic from here, as much as possible 6570 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6571 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6572 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6573 } 6574 6575 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6576 6577 // Invert the operand order and use SHUFPS to match it. 6578 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6579 getShuffleSHUFImmediate(SVOp), DAG); 6580} 6581 6582// Reduce a vector shuffle to zext. 6583SDValue 6584X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const { 6585 // PMOVZX is only available from SSE41. 6586 if (!Subtarget->hasSSE41()) 6587 return SDValue(); 6588 6589 EVT VT = Op.getValueType(); 6590 6591 // Only AVX2 support 256-bit vector integer extending. 6592 if (!Subtarget->hasInt256() && VT.is256BitVector()) 6593 return SDValue(); 6594 6595 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6596 DebugLoc DL = Op.getDebugLoc(); 6597 SDValue V1 = Op.getOperand(0); 6598 SDValue V2 = Op.getOperand(1); 6599 unsigned NumElems = VT.getVectorNumElements(); 6600 6601 // Extending is an unary operation and the element type of the source vector 6602 // won't be equal to or larger than i64. 6603 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() || 6604 VT.getVectorElementType() == MVT::i64) 6605 return SDValue(); 6606 6607 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4. 6608 unsigned Shift = 1; // Start from 2, i.e. 1 << 1. 6609 while ((1U << Shift) < NumElems) { 6610 if (SVOp->getMaskElt(1U << Shift) == 1) 6611 break; 6612 Shift += 1; 6613 // The maximal ratio is 8, i.e. from i8 to i64. 6614 if (Shift > 3) 6615 return SDValue(); 6616 } 6617 6618 // Check the shuffle mask. 6619 unsigned Mask = (1U << Shift) - 1; 6620 for (unsigned i = 0; i != NumElems; ++i) { 6621 int EltIdx = SVOp->getMaskElt(i); 6622 if ((i & Mask) != 0 && EltIdx != -1) 6623 return SDValue(); 6624 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift)) 6625 return SDValue(); 6626 } 6627 6628 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift; 6629 EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits); 6630 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift); 6631 6632 if (!isTypeLegal(NVT)) 6633 return SDValue(); 6634 6635 // Simplify the operand as it's prepared to be fed into shuffle. 6636 unsigned SignificantBits = NVT.getSizeInBits() >> Shift; 6637 if (V1.getOpcode() == ISD::BITCAST && 6638 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 6639 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT && 6640 V1.getOperand(0) 6641 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) { 6642 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x) 6643 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0); 6644 ConstantSDNode *CIdx = 6645 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1)); 6646 // If it's foldable, i.e. normal load with single use, we will let code 6647 // selection to fold it. Otherwise, we will short the conversion sequence. 6648 if (CIdx && CIdx->getZExtValue() == 0 && 6649 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) 6650 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V); 6651 } 6652 6653 return DAG.getNode(ISD::BITCAST, DL, VT, 6654 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1)); 6655} 6656 6657SDValue 6658X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6659 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6660 MVT VT = Op.getValueType().getSimpleVT(); 6661 DebugLoc dl = Op.getDebugLoc(); 6662 SDValue V1 = Op.getOperand(0); 6663 SDValue V2 = Op.getOperand(1); 6664 6665 if (isZeroShuffle(SVOp)) 6666 return getZeroVector(VT, Subtarget, DAG, dl); 6667 6668 // Handle splat operations 6669 if (SVOp->isSplat()) { 6670 unsigned NumElem = VT.getVectorNumElements(); 6671 6672 // Use vbroadcast whenever the splat comes from a foldable load 6673 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6674 if (Broadcast.getNode()) 6675 return Broadcast; 6676 6677 // Handle splats by matching through known shuffle masks 6678 if ((VT.is128BitVector() && NumElem <= 4) || 6679 (VT.is256BitVector() && NumElem <= 8)) 6680 return SDValue(); 6681 6682 // All remaning splats are promoted to target supported vector shuffles. 6683 return PromoteSplat(SVOp, DAG); 6684 } 6685 6686 // Check integer expanding shuffles. 6687 SDValue NewOp = LowerVectorIntExtend(Op, DAG); 6688 if (NewOp.getNode()) 6689 return NewOp; 6690 6691 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6692 // do it! 6693 if (VT == MVT::v8i16 || VT == MVT::v16i8 || 6694 VT == MVT::v16i16 || VT == MVT::v32i8) { 6695 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 6696 if (NewOp.getNode()) 6697 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6698 } else if ((VT == MVT::v4i32 || 6699 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6700 // FIXME: Figure out a cleaner way to do this. 6701 // Try to make use of movq to zero out the top part. 6702 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6703 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 6704 if (NewOp.getNode()) { 6705 MVT NewVT = NewOp.getValueType().getSimpleVT(); 6706 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6707 NewVT, true, false)) 6708 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6709 DAG, Subtarget, dl); 6710 } 6711 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6712 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG); 6713 if (NewOp.getNode()) { 6714 MVT NewVT = NewOp.getValueType().getSimpleVT(); 6715 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6716 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6717 DAG, Subtarget, dl); 6718 } 6719 } 6720 } 6721 return SDValue(); 6722} 6723 6724SDValue 6725X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6727 SDValue V1 = Op.getOperand(0); 6728 SDValue V2 = Op.getOperand(1); 6729 MVT VT = Op.getValueType().getSimpleVT(); 6730 DebugLoc dl = Op.getDebugLoc(); 6731 unsigned NumElems = VT.getVectorNumElements(); 6732 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6733 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6734 bool V1IsSplat = false; 6735 bool V2IsSplat = false; 6736 bool HasSSE2 = Subtarget->hasSSE2(); 6737 bool HasFp256 = Subtarget->hasFp256(); 6738 bool HasInt256 = Subtarget->hasInt256(); 6739 MachineFunction &MF = DAG.getMachineFunction(); 6740 bool OptForSize = MF.getFunction()->getAttributes(). 6741 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); 6742 6743 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6744 6745 if (V1IsUndef && V2IsUndef) 6746 return DAG.getUNDEF(VT); 6747 6748 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6749 6750 // Vector shuffle lowering takes 3 steps: 6751 // 6752 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6753 // narrowing and commutation of operands should be handled. 6754 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6755 // shuffle nodes. 6756 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6757 // so the shuffle can be broken into other shuffles and the legalizer can 6758 // try the lowering again. 6759 // 6760 // The general idea is that no vector_shuffle operation should be left to 6761 // be matched during isel, all of them must be converted to a target specific 6762 // node here. 6763 6764 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6765 // narrowing and commutation of operands should be handled. The actual code 6766 // doesn't include all of those, work in progress... 6767 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6768 if (NewOp.getNode()) 6769 return NewOp; 6770 6771 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6772 6773 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6774 // unpckh_undef). Only use pshufd if speed is more important than size. 6775 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256)) 6776 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6777 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256)) 6778 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6779 6780 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6781 V2IsUndef && MayFoldVectorLoad(V1)) 6782 return getMOVDDup(Op, dl, V1, DAG); 6783 6784 if (isMOVHLPS_v_undef_Mask(M, VT)) 6785 return getMOVHighToLow(Op, dl, DAG); 6786 6787 // Use to match splats 6788 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef && 6789 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6790 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6791 6792 if (isPSHUFDMask(M, VT)) { 6793 // The actual implementation will match the mask in the if above and then 6794 // during isel it can match several different instructions, not only pshufd 6795 // as its name says, sad but true, emulate the behavior for now... 6796 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6797 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6798 6799 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6800 6801 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6802 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6803 6804 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6805 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, 6806 DAG); 6807 6808 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6809 TargetMask, DAG); 6810 } 6811 6812 // Check if this can be converted into a logical shift. 6813 bool isLeft = false; 6814 unsigned ShAmt = 0; 6815 SDValue ShVal; 6816 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6817 if (isShift && ShVal.hasOneUse()) { 6818 // If the shifted value has multiple uses, it may be cheaper to use 6819 // v_set0 + movlhps or movhlps, etc. 6820 MVT EltVT = VT.getVectorElementType(); 6821 ShAmt *= EltVT.getSizeInBits(); 6822 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6823 } 6824 6825 if (isMOVLMask(M, VT)) { 6826 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6827 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6828 if (!isMOVLPMask(M, VT)) { 6829 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6830 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6831 6832 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6833 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6834 } 6835 } 6836 6837 // FIXME: fold these into legal mask. 6838 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256)) 6839 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6840 6841 if (isMOVHLPSMask(M, VT)) 6842 return getMOVHighToLow(Op, dl, DAG); 6843 6844 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6845 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6846 6847 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6848 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6849 6850 if (isMOVLPMask(M, VT)) 6851 return getMOVLP(Op, dl, DAG, HasSSE2); 6852 6853 if (ShouldXformToMOVHLPS(M, VT) || 6854 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6855 return CommuteVectorShuffle(SVOp, DAG); 6856 6857 if (isShift) { 6858 // No better options. Use a vshldq / vsrldq. 6859 MVT EltVT = VT.getVectorElementType(); 6860 ShAmt *= EltVT.getSizeInBits(); 6861 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6862 } 6863 6864 bool Commuted = false; 6865 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6866 // 1,1,1,1 -> v8i16 though. 6867 V1IsSplat = isSplatVector(V1.getNode()); 6868 V2IsSplat = isSplatVector(V2.getNode()); 6869 6870 // Canonicalize the splat or undef, if present, to be on the RHS. 6871 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6872 CommuteVectorShuffleMask(M, NumElems); 6873 std::swap(V1, V2); 6874 std::swap(V1IsSplat, V2IsSplat); 6875 Commuted = true; 6876 } 6877 6878 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6879 // Shuffling low element of v1 into undef, just return v1. 6880 if (V2IsUndef) 6881 return V1; 6882 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6883 // the instruction selector will not match, so get a canonical MOVL with 6884 // swapped operands to undo the commute. 6885 return getMOVL(DAG, dl, VT, V2, V1); 6886 } 6887 6888 if (isUNPCKLMask(M, VT, HasInt256)) 6889 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6890 6891 if (isUNPCKHMask(M, VT, HasInt256)) 6892 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6893 6894 if (V2IsSplat) { 6895 // Normalize mask so all entries that point to V2 points to its first 6896 // element then try to match unpck{h|l} again. If match, return a 6897 // new vector_shuffle with the corrected mask.p 6898 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6899 NormalizeMask(NewMask, NumElems); 6900 if (isUNPCKLMask(NewMask, VT, HasInt256, true)) 6901 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6902 if (isUNPCKHMask(NewMask, VT, HasInt256, true)) 6903 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6904 } 6905 6906 if (Commuted) { 6907 // Commute is back and try unpck* again. 6908 // FIXME: this seems wrong. 6909 CommuteVectorShuffleMask(M, NumElems); 6910 std::swap(V1, V2); 6911 std::swap(V1IsSplat, V2IsSplat); 6912 Commuted = false; 6913 6914 if (isUNPCKLMask(M, VT, HasInt256)) 6915 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6916 6917 if (isUNPCKHMask(M, VT, HasInt256)) 6918 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6919 } 6920 6921 // Normalize the node to match x86 shuffle ops if needed 6922 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true))) 6923 return CommuteVectorShuffle(SVOp, DAG); 6924 6925 // The checks below are all present in isShuffleMaskLegal, but they are 6926 // inlined here right now to enable us to directly emit target specific 6927 // nodes, and remove one by one until they don't return Op anymore. 6928 6929 if (isPALIGNRMask(M, VT, Subtarget)) 6930 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6931 getShufflePALIGNRImmediate(SVOp), 6932 DAG); 6933 6934 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6935 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6936 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6937 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6938 } 6939 6940 if (isPSHUFHWMask(M, VT, HasInt256)) 6941 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6942 getShufflePSHUFHWImmediate(SVOp), 6943 DAG); 6944 6945 if (isPSHUFLWMask(M, VT, HasInt256)) 6946 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6947 getShufflePSHUFLWImmediate(SVOp), 6948 DAG); 6949 6950 if (isSHUFPMask(M, VT, HasFp256)) 6951 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6952 getShuffleSHUFImmediate(SVOp), DAG); 6953 6954 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256)) 6955 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6956 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256)) 6957 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6958 6959 //===--------------------------------------------------------------------===// 6960 // Generate target specific nodes for 128 or 256-bit shuffles only 6961 // supported in the AVX instruction set. 6962 // 6963 6964 // Handle VMOVDDUPY permutations 6965 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256)) 6966 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6967 6968 // Handle VPERMILPS/D* permutations 6969 if (isVPERMILPMask(M, VT, HasFp256)) { 6970 if (HasInt256 && VT == MVT::v8i32) 6971 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6972 getShuffleSHUFImmediate(SVOp), DAG); 6973 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6974 getShuffleSHUFImmediate(SVOp), DAG); 6975 } 6976 6977 // Handle VPERM2F128/VPERM2I128 permutations 6978 if (isVPERM2X128Mask(M, VT, HasFp256)) 6979 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6980 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6981 6982 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 6983 if (BlendOp.getNode()) 6984 return BlendOp; 6985 6986 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6987 SmallVector<SDValue, 8> permclMask; 6988 for (unsigned i = 0; i != 8; ++i) { 6989 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6990 } 6991 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6992 &permclMask[0], 8); 6993 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6994 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6995 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6996 } 6997 6998 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6999 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 7000 getShuffleCLImmediate(SVOp), DAG); 7001 7002 //===--------------------------------------------------------------------===// 7003 // Since no target specific shuffle was selected for this generic one, 7004 // lower it into other known shuffles. FIXME: this isn't true yet, but 7005 // this is the plan. 7006 // 7007 7008 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 7009 if (VT == MVT::v8i16) { 7010 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG); 7011 if (NewOp.getNode()) 7012 return NewOp; 7013 } 7014 7015 if (VT == MVT::v16i8) { 7016 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 7017 if (NewOp.getNode()) 7018 return NewOp; 7019 } 7020 7021 if (VT == MVT::v32i8) { 7022 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG); 7023 if (NewOp.getNode()) 7024 return NewOp; 7025 } 7026 7027 // Handle all 128-bit wide vectors with 4 elements, and match them with 7028 // several different shuffle types. 7029 if (NumElems == 4 && VT.is128BitVector()) 7030 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 7031 7032 // Handle general 256-bit shuffles 7033 if (VT.is256BitVector()) 7034 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 7035 7036 return SDValue(); 7037} 7038 7039static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { 7040 MVT VT = Op.getValueType().getSimpleVT(); 7041 DebugLoc dl = Op.getDebugLoc(); 7042 7043 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector()) 7044 return SDValue(); 7045 7046 if (VT.getSizeInBits() == 8) { 7047 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 7048 Op.getOperand(0), Op.getOperand(1)); 7049 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7050 DAG.getValueType(VT)); 7051 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7052 } 7053 7054 if (VT.getSizeInBits() == 16) { 7055 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7056 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 7057 if (Idx == 0) 7058 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7059 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7060 DAG.getNode(ISD::BITCAST, dl, 7061 MVT::v4i32, 7062 Op.getOperand(0)), 7063 Op.getOperand(1))); 7064 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 7065 Op.getOperand(0), Op.getOperand(1)); 7066 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 7067 DAG.getValueType(VT)); 7068 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7069 } 7070 7071 if (VT == MVT::f32) { 7072 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 7073 // the result back to FR32 register. It's only worth matching if the 7074 // result has a single use which is a store or a bitcast to i32. And in 7075 // the case of a store, it's not worth it if the index is a constant 0, 7076 // because a MOVSSmr can be used instead, which is smaller and faster. 7077 if (!Op.hasOneUse()) 7078 return SDValue(); 7079 SDNode *User = *Op.getNode()->use_begin(); 7080 if ((User->getOpcode() != ISD::STORE || 7081 (isa<ConstantSDNode>(Op.getOperand(1)) && 7082 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 7083 (User->getOpcode() != ISD::BITCAST || 7084 User->getValueType(0) != MVT::i32)) 7085 return SDValue(); 7086 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7087 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 7088 Op.getOperand(0)), 7089 Op.getOperand(1)); 7090 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 7091 } 7092 7093 if (VT == MVT::i32 || VT == MVT::i64) { 7094 // ExtractPS/pextrq works with constant index. 7095 if (isa<ConstantSDNode>(Op.getOperand(1))) 7096 return Op; 7097 } 7098 return SDValue(); 7099} 7100 7101SDValue 7102X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 7103 SelectionDAG &DAG) const { 7104 if (!isa<ConstantSDNode>(Op.getOperand(1))) 7105 return SDValue(); 7106 7107 SDValue Vec = Op.getOperand(0); 7108 MVT VecVT = Vec.getValueType().getSimpleVT(); 7109 7110 // If this is a 256-bit vector result, first extract the 128-bit vector and 7111 // then extract the element from the 128-bit vector. 7112 if (VecVT.is256BitVector()) { 7113 DebugLoc dl = Op.getNode()->getDebugLoc(); 7114 unsigned NumElems = VecVT.getVectorNumElements(); 7115 SDValue Idx = Op.getOperand(1); 7116 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7117 7118 // Get the 128-bit vector. 7119 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 7120 7121 if (IdxVal >= NumElems/2) 7122 IdxVal -= NumElems/2; 7123 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 7124 DAG.getConstant(IdxVal, MVT::i32)); 7125 } 7126 7127 assert(VecVT.is128BitVector() && "Unexpected vector length"); 7128 7129 if (Subtarget->hasSSE41()) { 7130 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 7131 if (Res.getNode()) 7132 return Res; 7133 } 7134 7135 MVT VT = Op.getValueType().getSimpleVT(); 7136 DebugLoc dl = Op.getDebugLoc(); 7137 // TODO: handle v16i8. 7138 if (VT.getSizeInBits() == 16) { 7139 SDValue Vec = Op.getOperand(0); 7140 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7141 if (Idx == 0) 7142 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7143 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7144 DAG.getNode(ISD::BITCAST, dl, 7145 MVT::v4i32, Vec), 7146 Op.getOperand(1))); 7147 // Transform it so it match pextrw which produces a 32-bit result. 7148 MVT EltVT = MVT::i32; 7149 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 7150 Op.getOperand(0), Op.getOperand(1)); 7151 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 7152 DAG.getValueType(VT)); 7153 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7154 } 7155 7156 if (VT.getSizeInBits() == 32) { 7157 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7158 if (Idx == 0) 7159 return Op; 7160 7161 // SHUFPS the element to the lowest double word, then movss. 7162 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 7163 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT(); 7164 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7165 DAG.getUNDEF(VVT), Mask); 7166 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7167 DAG.getIntPtrConstant(0)); 7168 } 7169 7170 if (VT.getSizeInBits() == 64) { 7171 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 7172 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 7173 // to match extract_elt for f64. 7174 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7175 if (Idx == 0) 7176 return Op; 7177 7178 // UNPCKHPD the element to the lowest double word, then movsd. 7179 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 7180 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 7181 int Mask[2] = { 1, -1 }; 7182 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT(); 7183 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7184 DAG.getUNDEF(VVT), Mask); 7185 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7186 DAG.getIntPtrConstant(0)); 7187 } 7188 7189 return SDValue(); 7190} 7191 7192static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { 7193 MVT VT = Op.getValueType().getSimpleVT(); 7194 MVT EltVT = VT.getVectorElementType(); 7195 DebugLoc dl = Op.getDebugLoc(); 7196 7197 SDValue N0 = Op.getOperand(0); 7198 SDValue N1 = Op.getOperand(1); 7199 SDValue N2 = Op.getOperand(2); 7200 7201 if (!VT.is128BitVector()) 7202 return SDValue(); 7203 7204 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7205 isa<ConstantSDNode>(N2)) { 7206 unsigned Opc; 7207 if (VT == MVT::v8i16) 7208 Opc = X86ISD::PINSRW; 7209 else if (VT == MVT::v16i8) 7210 Opc = X86ISD::PINSRB; 7211 else 7212 Opc = X86ISD::PINSRB; 7213 7214 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7215 // argument. 7216 if (N1.getValueType() != MVT::i32) 7217 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7218 if (N2.getValueType() != MVT::i32) 7219 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7220 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7221 } 7222 7223 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7224 // Bits [7:6] of the constant are the source select. This will always be 7225 // zero here. The DAG Combiner may combine an extract_elt index into these 7226 // bits. For example (insert (extract, 3), 2) could be matched by putting 7227 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7228 // Bits [5:4] of the constant are the destination select. This is the 7229 // value of the incoming immediate. 7230 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7231 // combine either bitwise AND or insert of float 0.0 to set these bits. 7232 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7233 // Create this as a scalar to vector.. 7234 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7235 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7236 } 7237 7238 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 7239 // PINSR* works with constant index. 7240 return Op; 7241 } 7242 return SDValue(); 7243} 7244 7245SDValue 7246X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7247 MVT VT = Op.getValueType().getSimpleVT(); 7248 MVT EltVT = VT.getVectorElementType(); 7249 7250 DebugLoc dl = Op.getDebugLoc(); 7251 SDValue N0 = Op.getOperand(0); 7252 SDValue N1 = Op.getOperand(1); 7253 SDValue N2 = Op.getOperand(2); 7254 7255 // If this is a 256-bit vector result, first extract the 128-bit vector, 7256 // insert the element into the extracted half and then place it back. 7257 if (VT.is256BitVector()) { 7258 if (!isa<ConstantSDNode>(N2)) 7259 return SDValue(); 7260 7261 // Get the desired 128-bit vector half. 7262 unsigned NumElems = VT.getVectorNumElements(); 7263 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7264 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 7265 7266 // Insert the element into the desired half. 7267 bool Upper = IdxVal >= NumElems/2; 7268 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 7269 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32)); 7270 7271 // Insert the changed part back to the 256-bit vector 7272 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 7273 } 7274 7275 if (Subtarget->hasSSE41()) 7276 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7277 7278 if (EltVT == MVT::i8) 7279 return SDValue(); 7280 7281 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7282 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7283 // as its second argument. 7284 if (N1.getValueType() != MVT::i32) 7285 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7286 if (N2.getValueType() != MVT::i32) 7287 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7288 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7289 } 7290 return SDValue(); 7291} 7292 7293static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 7294 LLVMContext *Context = DAG.getContext(); 7295 DebugLoc dl = Op.getDebugLoc(); 7296 MVT OpVT = Op.getValueType().getSimpleVT(); 7297 7298 // If this is a 256-bit vector result, first insert into a 128-bit 7299 // vector and then insert into the 256-bit vector. 7300 if (!OpVT.is128BitVector()) { 7301 // Insert into a 128-bit vector. 7302 EVT VT128 = EVT::getVectorVT(*Context, 7303 OpVT.getVectorElementType(), 7304 OpVT.getVectorNumElements() / 2); 7305 7306 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7307 7308 // Insert the 128-bit vector. 7309 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 7310 } 7311 7312 if (OpVT == MVT::v1i64 && 7313 Op.getOperand(0).getValueType() == MVT::i64) 7314 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7315 7316 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7317 assert(OpVT.is128BitVector() && "Expected an SSE type!"); 7318 return DAG.getNode(ISD::BITCAST, dl, OpVT, 7319 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7320} 7321 7322// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7323// a simple subregister reference or explicit instructions to grab 7324// upper bits of a vector. 7325static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7326 SelectionDAG &DAG) { 7327 if (Subtarget->hasFp256()) { 7328 DebugLoc dl = Op.getNode()->getDebugLoc(); 7329 SDValue Vec = Op.getNode()->getOperand(0); 7330 SDValue Idx = Op.getNode()->getOperand(1); 7331 7332 if (Op.getNode()->getValueType(0).is128BitVector() && 7333 Vec.getNode()->getValueType(0).is256BitVector() && 7334 isa<ConstantSDNode>(Idx)) { 7335 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7336 return Extract128BitVector(Vec, IdxVal, DAG, dl); 7337 } 7338 } 7339 return SDValue(); 7340} 7341 7342// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7343// simple superregister reference or explicit instructions to insert 7344// the upper bits of a vector. 7345static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, 7346 SelectionDAG &DAG) { 7347 if (Subtarget->hasFp256()) { 7348 DebugLoc dl = Op.getNode()->getDebugLoc(); 7349 SDValue Vec = Op.getNode()->getOperand(0); 7350 SDValue SubVec = Op.getNode()->getOperand(1); 7351 SDValue Idx = Op.getNode()->getOperand(2); 7352 7353 if (Op.getNode()->getValueType(0).is256BitVector() && 7354 SubVec.getNode()->getValueType(0).is128BitVector() && 7355 isa<ConstantSDNode>(Idx)) { 7356 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7357 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7358 } 7359 } 7360 return SDValue(); 7361} 7362 7363// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7364// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7365// one of the above mentioned nodes. It has to be wrapped because otherwise 7366// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7367// be used to form addressing mode. These wrapped nodes will be selected 7368// into MOV32ri. 7369SDValue 7370X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7371 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7372 7373 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7374 // global base reg. 7375 unsigned char OpFlag = 0; 7376 unsigned WrapperKind = X86ISD::Wrapper; 7377 CodeModel::Model M = getTargetMachine().getCodeModel(); 7378 7379 if (Subtarget->isPICStyleRIPRel() && 7380 (M == CodeModel::Small || M == CodeModel::Kernel)) 7381 WrapperKind = X86ISD::WrapperRIP; 7382 else if (Subtarget->isPICStyleGOT()) 7383 OpFlag = X86II::MO_GOTOFF; 7384 else if (Subtarget->isPICStyleStubPIC()) 7385 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7386 7387 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7388 CP->getAlignment(), 7389 CP->getOffset(), OpFlag); 7390 DebugLoc DL = CP->getDebugLoc(); 7391 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7392 // With PIC, the address is actually $g + Offset. 7393 if (OpFlag) { 7394 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7395 DAG.getNode(X86ISD::GlobalBaseReg, 7396 DebugLoc(), getPointerTy()), 7397 Result); 7398 } 7399 7400 return Result; 7401} 7402 7403SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7404 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7405 7406 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7407 // global base reg. 7408 unsigned char OpFlag = 0; 7409 unsigned WrapperKind = X86ISD::Wrapper; 7410 CodeModel::Model M = getTargetMachine().getCodeModel(); 7411 7412 if (Subtarget->isPICStyleRIPRel() && 7413 (M == CodeModel::Small || M == CodeModel::Kernel)) 7414 WrapperKind = X86ISD::WrapperRIP; 7415 else if (Subtarget->isPICStyleGOT()) 7416 OpFlag = X86II::MO_GOTOFF; 7417 else if (Subtarget->isPICStyleStubPIC()) 7418 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7419 7420 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7421 OpFlag); 7422 DebugLoc DL = JT->getDebugLoc(); 7423 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7424 7425 // With PIC, the address is actually $g + Offset. 7426 if (OpFlag) 7427 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7428 DAG.getNode(X86ISD::GlobalBaseReg, 7429 DebugLoc(), getPointerTy()), 7430 Result); 7431 7432 return Result; 7433} 7434 7435SDValue 7436X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7437 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7438 7439 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7440 // global base reg. 7441 unsigned char OpFlag = 0; 7442 unsigned WrapperKind = X86ISD::Wrapper; 7443 CodeModel::Model M = getTargetMachine().getCodeModel(); 7444 7445 if (Subtarget->isPICStyleRIPRel() && 7446 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7447 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7448 OpFlag = X86II::MO_GOTPCREL; 7449 WrapperKind = X86ISD::WrapperRIP; 7450 } else if (Subtarget->isPICStyleGOT()) { 7451 OpFlag = X86II::MO_GOT; 7452 } else if (Subtarget->isPICStyleStubPIC()) { 7453 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7454 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7455 OpFlag = X86II::MO_DARWIN_NONLAZY; 7456 } 7457 7458 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7459 7460 DebugLoc DL = Op.getDebugLoc(); 7461 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7462 7463 // With PIC, the address is actually $g + Offset. 7464 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7465 !Subtarget->is64Bit()) { 7466 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7467 DAG.getNode(X86ISD::GlobalBaseReg, 7468 DebugLoc(), getPointerTy()), 7469 Result); 7470 } 7471 7472 // For symbols that require a load from a stub to get the address, emit the 7473 // load. 7474 if (isGlobalStubReference(OpFlag)) 7475 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7476 MachinePointerInfo::getGOT(), false, false, false, 0); 7477 7478 return Result; 7479} 7480 7481SDValue 7482X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7483 // Create the TargetBlockAddressAddress node. 7484 unsigned char OpFlags = 7485 Subtarget->ClassifyBlockAddressReference(); 7486 CodeModel::Model M = getTargetMachine().getCodeModel(); 7487 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7488 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset(); 7489 DebugLoc dl = Op.getDebugLoc(); 7490 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset, 7491 OpFlags); 7492 7493 if (Subtarget->isPICStyleRIPRel() && 7494 (M == CodeModel::Small || M == CodeModel::Kernel)) 7495 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7496 else 7497 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7498 7499 // With PIC, the address is actually $g + Offset. 7500 if (isGlobalRelativeToPICBase(OpFlags)) { 7501 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7502 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7503 Result); 7504 } 7505 7506 return Result; 7507} 7508 7509SDValue 7510X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7511 int64_t Offset, 7512 SelectionDAG &DAG) const { 7513 // Create the TargetGlobalAddress node, folding in the constant 7514 // offset if it is legal. 7515 unsigned char OpFlags = 7516 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7517 CodeModel::Model M = getTargetMachine().getCodeModel(); 7518 SDValue Result; 7519 if (OpFlags == X86II::MO_NO_FLAG && 7520 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7521 // A direct static reference to a global. 7522 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7523 Offset = 0; 7524 } else { 7525 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7526 } 7527 7528 if (Subtarget->isPICStyleRIPRel() && 7529 (M == CodeModel::Small || M == CodeModel::Kernel)) 7530 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7531 else 7532 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7533 7534 // With PIC, the address is actually $g + Offset. 7535 if (isGlobalRelativeToPICBase(OpFlags)) { 7536 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7537 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7538 Result); 7539 } 7540 7541 // For globals that require a load from a stub to get the address, emit the 7542 // load. 7543 if (isGlobalStubReference(OpFlags)) 7544 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7545 MachinePointerInfo::getGOT(), false, false, false, 0); 7546 7547 // If there was a non-zero offset that we didn't fold, create an explicit 7548 // addition for it. 7549 if (Offset != 0) 7550 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7551 DAG.getConstant(Offset, getPointerTy())); 7552 7553 return Result; 7554} 7555 7556SDValue 7557X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7558 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7559 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7560 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7561} 7562 7563static SDValue 7564GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7565 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7566 unsigned char OperandFlags, bool LocalDynamic = false) { 7567 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7568 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7569 DebugLoc dl = GA->getDebugLoc(); 7570 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7571 GA->getValueType(0), 7572 GA->getOffset(), 7573 OperandFlags); 7574 7575 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR 7576 : X86ISD::TLSADDR; 7577 7578 if (InFlag) { 7579 SDValue Ops[] = { Chain, TGA, *InFlag }; 7580 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3); 7581 } else { 7582 SDValue Ops[] = { Chain, TGA }; 7583 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2); 7584 } 7585 7586 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7587 MFI->setAdjustsStack(true); 7588 7589 SDValue Flag = Chain.getValue(1); 7590 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7591} 7592 7593// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7594static SDValue 7595LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7596 const EVT PtrVT) { 7597 SDValue InFlag; 7598 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7599 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7600 DAG.getNode(X86ISD::GlobalBaseReg, 7601 DebugLoc(), PtrVT), InFlag); 7602 InFlag = Chain.getValue(1); 7603 7604 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7605} 7606 7607// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7608static SDValue 7609LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7610 const EVT PtrVT) { 7611 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7612 X86::RAX, X86II::MO_TLSGD); 7613} 7614 7615static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, 7616 SelectionDAG &DAG, 7617 const EVT PtrVT, 7618 bool is64Bit) { 7619 DebugLoc dl = GA->getDebugLoc(); 7620 7621 // Get the start address of the TLS block for this module. 7622 X86MachineFunctionInfo* MFI = DAG.getMachineFunction() 7623 .getInfo<X86MachineFunctionInfo>(); 7624 MFI->incNumLocalDynamicTLSAccesses(); 7625 7626 SDValue Base; 7627 if (is64Bit) { 7628 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX, 7629 X86II::MO_TLSLD, /*LocalDynamic=*/true); 7630 } else { 7631 SDValue InFlag; 7632 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7633 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag); 7634 InFlag = Chain.getValue(1); 7635 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, 7636 X86II::MO_TLSLDM, /*LocalDynamic=*/true); 7637 } 7638 7639 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations 7640 // of Base. 7641 7642 // Build x@dtpoff. 7643 unsigned char OperandFlags = X86II::MO_DTPOFF; 7644 unsigned WrapperKind = X86ISD::Wrapper; 7645 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7646 GA->getValueType(0), 7647 GA->getOffset(), OperandFlags); 7648 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7649 7650 // Add x@dtpoff with the base. 7651 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base); 7652} 7653 7654// Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model. 7655static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7656 const EVT PtrVT, TLSModel::Model model, 7657 bool is64Bit, bool isPIC) { 7658 DebugLoc dl = GA->getDebugLoc(); 7659 7660 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7661 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7662 is64Bit ? 257 : 256)); 7663 7664 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7665 DAG.getIntPtrConstant(0), 7666 MachinePointerInfo(Ptr), 7667 false, false, false, 0); 7668 7669 unsigned char OperandFlags = 0; 7670 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7671 // initialexec. 7672 unsigned WrapperKind = X86ISD::Wrapper; 7673 if (model == TLSModel::LocalExec) { 7674 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7675 } else if (model == TLSModel::InitialExec) { 7676 if (is64Bit) { 7677 OperandFlags = X86II::MO_GOTTPOFF; 7678 WrapperKind = X86ISD::WrapperRIP; 7679 } else { 7680 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF; 7681 } 7682 } else { 7683 llvm_unreachable("Unexpected model"); 7684 } 7685 7686 // emit "addl x@ntpoff,%eax" (local exec) 7687 // or "addl x@indntpoff,%eax" (initial exec) 7688 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic) 7689 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7690 GA->getValueType(0), 7691 GA->getOffset(), OperandFlags); 7692 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7693 7694 if (model == TLSModel::InitialExec) { 7695 if (isPIC && !is64Bit) { 7696 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, 7697 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), 7698 Offset); 7699 } 7700 7701 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7702 MachinePointerInfo::getGOT(), false, false, false, 7703 0); 7704 } 7705 7706 // The address of the thread local variable is the add of the thread 7707 // pointer with the offset of the variable. 7708 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7709} 7710 7711SDValue 7712X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7713 7714 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7715 const GlobalValue *GV = GA->getGlobal(); 7716 7717 if (Subtarget->isTargetELF()) { 7718 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7719 7720 switch (model) { 7721 case TLSModel::GeneralDynamic: 7722 if (Subtarget->is64Bit()) 7723 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7724 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7725 case TLSModel::LocalDynamic: 7726 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(), 7727 Subtarget->is64Bit()); 7728 case TLSModel::InitialExec: 7729 case TLSModel::LocalExec: 7730 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7731 Subtarget->is64Bit(), 7732 getTargetMachine().getRelocationModel() == Reloc::PIC_); 7733 } 7734 llvm_unreachable("Unknown TLS model."); 7735 } 7736 7737 if (Subtarget->isTargetDarwin()) { 7738 // Darwin only has one model of TLS. Lower to that. 7739 unsigned char OpFlag = 0; 7740 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7741 X86ISD::WrapperRIP : X86ISD::Wrapper; 7742 7743 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7744 // global base reg. 7745 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7746 !Subtarget->is64Bit(); 7747 if (PIC32) 7748 OpFlag = X86II::MO_TLVP_PIC_BASE; 7749 else 7750 OpFlag = X86II::MO_TLVP; 7751 DebugLoc DL = Op.getDebugLoc(); 7752 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7753 GA->getValueType(0), 7754 GA->getOffset(), OpFlag); 7755 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7756 7757 // With PIC32, the address is actually $g + Offset. 7758 if (PIC32) 7759 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7760 DAG.getNode(X86ISD::GlobalBaseReg, 7761 DebugLoc(), getPointerTy()), 7762 Offset); 7763 7764 // Lowering the machine isd will make sure everything is in the right 7765 // location. 7766 SDValue Chain = DAG.getEntryNode(); 7767 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7768 SDValue Args[] = { Chain, Offset }; 7769 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7770 7771 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7772 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7773 MFI->setAdjustsStack(true); 7774 7775 // And our return value (tls address) is in the standard call return value 7776 // location. 7777 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7778 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7779 Chain.getValue(1)); 7780 } 7781 7782 if (Subtarget->isTargetWindows()) { 7783 // Just use the implicit TLS architecture 7784 // Need to generate someting similar to: 7785 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7786 // ; from TEB 7787 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7788 // mov rcx, qword [rdx+rcx*8] 7789 // mov eax, .tls$:tlsvar 7790 // [rax+rcx] contains the address 7791 // Windows 64bit: gs:0x58 7792 // Windows 32bit: fs:__tls_array 7793 7794 // If GV is an alias then use the aliasee for determining 7795 // thread-localness. 7796 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7797 GV = GA->resolveAliasedGlobal(false); 7798 DebugLoc dl = GA->getDebugLoc(); 7799 SDValue Chain = DAG.getEntryNode(); 7800 7801 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7802 // %gs:0x58 (64-bit). 7803 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7804 ? Type::getInt8PtrTy(*DAG.getContext(), 7805 256) 7806 : Type::getInt32PtrTy(*DAG.getContext(), 7807 257)); 7808 7809 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7810 Subtarget->is64Bit() 7811 ? DAG.getIntPtrConstant(0x58) 7812 : DAG.getExternalSymbol("_tls_array", 7813 getPointerTy()), 7814 MachinePointerInfo(Ptr), 7815 false, false, false, 0); 7816 7817 // Load the _tls_index variable 7818 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7819 if (Subtarget->is64Bit()) 7820 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7821 IDX, MachinePointerInfo(), MVT::i32, 7822 false, false, 0); 7823 else 7824 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7825 false, false, false, 0); 7826 7827 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7828 getPointerTy()); 7829 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7830 7831 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7832 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7833 false, false, false, 0); 7834 7835 // Get the offset of start of .tls section 7836 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7837 GA->getValueType(0), 7838 GA->getOffset(), X86II::MO_SECREL); 7839 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7840 7841 // The address of the thread local variable is the add of the thread 7842 // pointer with the offset of the variable. 7843 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7844 } 7845 7846 llvm_unreachable("TLS not implemented for this target."); 7847} 7848 7849/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7850/// and take a 2 x i32 value to shift plus a shift amount. 7851SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7852 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7853 EVT VT = Op.getValueType(); 7854 unsigned VTBits = VT.getSizeInBits(); 7855 DebugLoc dl = Op.getDebugLoc(); 7856 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7857 SDValue ShOpLo = Op.getOperand(0); 7858 SDValue ShOpHi = Op.getOperand(1); 7859 SDValue ShAmt = Op.getOperand(2); 7860 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7861 DAG.getConstant(VTBits - 1, MVT::i8)) 7862 : DAG.getConstant(0, VT); 7863 7864 SDValue Tmp2, Tmp3; 7865 if (Op.getOpcode() == ISD::SHL_PARTS) { 7866 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7867 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7868 } else { 7869 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7870 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7871 } 7872 7873 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7874 DAG.getConstant(VTBits, MVT::i8)); 7875 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7876 AndNode, DAG.getConstant(0, MVT::i8)); 7877 7878 SDValue Hi, Lo; 7879 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7880 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7881 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7882 7883 if (Op.getOpcode() == ISD::SHL_PARTS) { 7884 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7885 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7886 } else { 7887 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7888 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7889 } 7890 7891 SDValue Ops[2] = { Lo, Hi }; 7892 return DAG.getMergeValues(Ops, 2, dl); 7893} 7894 7895SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7896 SelectionDAG &DAG) const { 7897 EVT SrcVT = Op.getOperand(0).getValueType(); 7898 7899 if (SrcVT.isVector()) 7900 return SDValue(); 7901 7902 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7903 "Unknown SINT_TO_FP to lower!"); 7904 7905 // These are really Legal; return the operand so the caller accepts it as 7906 // Legal. 7907 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7908 return Op; 7909 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7910 Subtarget->is64Bit()) { 7911 return Op; 7912 } 7913 7914 DebugLoc dl = Op.getDebugLoc(); 7915 unsigned Size = SrcVT.getSizeInBits()/8; 7916 MachineFunction &MF = DAG.getMachineFunction(); 7917 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7918 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7919 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7920 StackSlot, 7921 MachinePointerInfo::getFixedStack(SSFI), 7922 false, false, 0); 7923 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7924} 7925 7926SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7927 SDValue StackSlot, 7928 SelectionDAG &DAG) const { 7929 // Build the FILD 7930 DebugLoc DL = Op.getDebugLoc(); 7931 SDVTList Tys; 7932 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7933 if (useSSE) 7934 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7935 else 7936 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7937 7938 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7939 7940 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7941 MachineMemOperand *MMO; 7942 if (FI) { 7943 int SSFI = FI->getIndex(); 7944 MMO = 7945 DAG.getMachineFunction() 7946 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7947 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7948 } else { 7949 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7950 StackSlot = StackSlot.getOperand(1); 7951 } 7952 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7953 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7954 X86ISD::FILD, DL, 7955 Tys, Ops, array_lengthof(Ops), 7956 SrcVT, MMO); 7957 7958 if (useSSE) { 7959 Chain = Result.getValue(1); 7960 SDValue InFlag = Result.getValue(2); 7961 7962 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7963 // shouldn't be necessary except that RFP cannot be live across 7964 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7965 MachineFunction &MF = DAG.getMachineFunction(); 7966 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7967 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7968 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7969 Tys = DAG.getVTList(MVT::Other); 7970 SDValue Ops[] = { 7971 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7972 }; 7973 MachineMemOperand *MMO = 7974 DAG.getMachineFunction() 7975 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7976 MachineMemOperand::MOStore, SSFISize, SSFISize); 7977 7978 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7979 Ops, array_lengthof(Ops), 7980 Op.getValueType(), MMO); 7981 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7982 MachinePointerInfo::getFixedStack(SSFI), 7983 false, false, false, 0); 7984 } 7985 7986 return Result; 7987} 7988 7989// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7990SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7991 SelectionDAG &DAG) const { 7992 // This algorithm is not obvious. Here it is what we're trying to output: 7993 /* 7994 movq %rax, %xmm0 7995 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7996 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7997 #ifdef __SSE3__ 7998 haddpd %xmm0, %xmm0 7999 #else 8000 pshufd $0x4e, %xmm0, %xmm1 8001 addpd %xmm1, %xmm0 8002 #endif 8003 */ 8004 8005 DebugLoc dl = Op.getDebugLoc(); 8006 LLVMContext *Context = DAG.getContext(); 8007 8008 // Build some magic constants. 8009 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 8010 Constant *C0 = ConstantDataVector::get(*Context, CV0); 8011 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 8012 8013 SmallVector<Constant*,2> CV1; 8014 CV1.push_back( 8015 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 8016 CV1.push_back( 8017 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 8018 Constant *C1 = ConstantVector::get(CV1); 8019 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 8020 8021 // Load the 64-bit value into an XMM register. 8022 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 8023 Op.getOperand(0)); 8024 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 8025 MachinePointerInfo::getConstantPool(), 8026 false, false, false, 16); 8027 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 8028 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 8029 CLod0); 8030 8031 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 8032 MachinePointerInfo::getConstantPool(), 8033 false, false, false, 16); 8034 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 8035 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 8036 SDValue Result; 8037 8038 if (Subtarget->hasSSE3()) { 8039 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 8040 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 8041 } else { 8042 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 8043 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 8044 S2F, 0x4E, DAG); 8045 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 8046 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 8047 Sub); 8048 } 8049 8050 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 8051 DAG.getIntPtrConstant(0)); 8052} 8053 8054// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 8055SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 8056 SelectionDAG &DAG) const { 8057 DebugLoc dl = Op.getDebugLoc(); 8058 // FP constant to bias correct the final result. 8059 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 8060 MVT::f64); 8061 8062 // Load the 32-bit value into an XMM register. 8063 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 8064 Op.getOperand(0)); 8065 8066 // Zero out the upper parts of the register. 8067 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 8068 8069 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8070 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 8071 DAG.getIntPtrConstant(0)); 8072 8073 // Or the load with the bias. 8074 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 8075 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8076 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 8077 MVT::v2f64, Load)), 8078 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8079 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 8080 MVT::v2f64, Bias))); 8081 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 8082 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 8083 DAG.getIntPtrConstant(0)); 8084 8085 // Subtract the bias. 8086 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 8087 8088 // Handle final rounding. 8089 EVT DestVT = Op.getValueType(); 8090 8091 if (DestVT.bitsLT(MVT::f64)) 8092 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 8093 DAG.getIntPtrConstant(0)); 8094 if (DestVT.bitsGT(MVT::f64)) 8095 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 8096 8097 // Handle final rounding. 8098 return Sub; 8099} 8100 8101SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op, 8102 SelectionDAG &DAG) const { 8103 SDValue N0 = Op.getOperand(0); 8104 EVT SVT = N0.getValueType(); 8105 DebugLoc dl = Op.getDebugLoc(); 8106 8107 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 || 8108 SVT == MVT::v8i8 || SVT == MVT::v8i16) && 8109 "Custom UINT_TO_FP is not supported!"); 8110 8111 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements()); 8112 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), 8113 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); 8114} 8115 8116SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 8117 SelectionDAG &DAG) const { 8118 SDValue N0 = Op.getOperand(0); 8119 DebugLoc dl = Op.getDebugLoc(); 8120 8121 if (Op.getValueType().isVector()) 8122 return lowerUINT_TO_FP_vec(Op, DAG); 8123 8124 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 8125 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 8126 // the optimization here. 8127 if (DAG.SignBitIsZero(N0)) 8128 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 8129 8130 EVT SrcVT = N0.getValueType(); 8131 EVT DstVT = Op.getValueType(); 8132 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 8133 return LowerUINT_TO_FP_i64(Op, DAG); 8134 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 8135 return LowerUINT_TO_FP_i32(Op, DAG); 8136 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 8137 return SDValue(); 8138 8139 // Make a 64-bit buffer, and use it to build an FILD. 8140 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 8141 if (SrcVT == MVT::i32) { 8142 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 8143 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 8144 getPointerTy(), StackSlot, WordOff); 8145 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8146 StackSlot, MachinePointerInfo(), 8147 false, false, 0); 8148 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 8149 OffsetSlot, MachinePointerInfo(), 8150 false, false, 0); 8151 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 8152 return Fild; 8153 } 8154 8155 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 8156 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 8157 StackSlot, MachinePointerInfo(), 8158 false, false, 0); 8159 // For i64 source, we need to add the appropriate power of 2 if the input 8160 // was negative. This is the same as the optimization in 8161 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 8162 // we must be careful to do the computation in x87 extended precision, not 8163 // in SSE. (The generic code can't know it's OK to do this, or how to.) 8164 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 8165 MachineMemOperand *MMO = 8166 DAG.getMachineFunction() 8167 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8168 MachineMemOperand::MOLoad, 8, 8); 8169 8170 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 8171 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 8172 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 8173 MVT::i64, MMO); 8174 8175 APInt FF(32, 0x5F800000ULL); 8176 8177 // Check whether the sign bit is set. 8178 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 8179 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 8180 ISD::SETLT); 8181 8182 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 8183 SDValue FudgePtr = DAG.getConstantPool( 8184 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 8185 getPointerTy()); 8186 8187 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 8188 SDValue Zero = DAG.getIntPtrConstant(0); 8189 SDValue Four = DAG.getIntPtrConstant(4); 8190 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 8191 Zero, Four); 8192 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 8193 8194 // Load the value out, extending it from f32 to f80. 8195 // FIXME: Avoid the extend by constructing the right constant pool? 8196 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 8197 FudgePtr, MachinePointerInfo::getConstantPool(), 8198 MVT::f32, false, false, 4); 8199 // Extend everything to 80 bits to force it to be done on x87. 8200 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 8201 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 8202} 8203 8204std::pair<SDValue,SDValue> X86TargetLowering:: 8205FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 8206 DebugLoc DL = Op.getDebugLoc(); 8207 8208 EVT DstTy = Op.getValueType(); 8209 8210 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 8211 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 8212 DstTy = MVT::i64; 8213 } 8214 8215 assert(DstTy.getSimpleVT() <= MVT::i64 && 8216 DstTy.getSimpleVT() >= MVT::i16 && 8217 "Unknown FP_TO_INT to lower!"); 8218 8219 // These are really Legal. 8220 if (DstTy == MVT::i32 && 8221 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8222 return std::make_pair(SDValue(), SDValue()); 8223 if (Subtarget->is64Bit() && 8224 DstTy == MVT::i64 && 8225 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 8226 return std::make_pair(SDValue(), SDValue()); 8227 8228 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 8229 // stack slot, or into the FTOL runtime function. 8230 MachineFunction &MF = DAG.getMachineFunction(); 8231 unsigned MemSize = DstTy.getSizeInBits()/8; 8232 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8233 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8234 8235 unsigned Opc; 8236 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 8237 Opc = X86ISD::WIN_FTOL; 8238 else 8239 switch (DstTy.getSimpleVT().SimpleTy) { 8240 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 8241 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 8242 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 8243 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 8244 } 8245 8246 SDValue Chain = DAG.getEntryNode(); 8247 SDValue Value = Op.getOperand(0); 8248 EVT TheVT = Op.getOperand(0).getValueType(); 8249 // FIXME This causes a redundant load/store if the SSE-class value is already 8250 // in memory, such as if it is on the callstack. 8251 if (isScalarFPTypeInSSEReg(TheVT)) { 8252 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8253 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8254 MachinePointerInfo::getFixedStack(SSFI), 8255 false, false, 0); 8256 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8257 SDValue Ops[] = { 8258 Chain, StackSlot, DAG.getValueType(TheVT) 8259 }; 8260 8261 MachineMemOperand *MMO = 8262 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8263 MachineMemOperand::MOLoad, MemSize, MemSize); 8264 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 8265 DstTy, MMO); 8266 Chain = Value.getValue(1); 8267 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8268 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8269 } 8270 8271 MachineMemOperand *MMO = 8272 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8273 MachineMemOperand::MOStore, MemSize, MemSize); 8274 8275 if (Opc != X86ISD::WIN_FTOL) { 8276 // Build the FP_TO_INT*_IN_MEM 8277 SDValue Ops[] = { Chain, Value, StackSlot }; 8278 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8279 Ops, 3, DstTy, MMO); 8280 return std::make_pair(FIST, StackSlot); 8281 } else { 8282 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 8283 DAG.getVTList(MVT::Other, MVT::Glue), 8284 Chain, Value); 8285 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 8286 MVT::i32, ftol.getValue(1)); 8287 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 8288 MVT::i32, eax.getValue(2)); 8289 SDValue Ops[] = { eax, edx }; 8290 SDValue pair = IsReplace 8291 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 8292 : DAG.getMergeValues(Ops, 2, DL); 8293 return std::make_pair(pair, SDValue()); 8294 } 8295} 8296 8297static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG, 8298 const X86Subtarget *Subtarget) { 8299 EVT VT = Op->getValueType(0); 8300 SDValue In = Op->getOperand(0); 8301 EVT InVT = In.getValueType(); 8302 DebugLoc dl = Op->getDebugLoc(); 8303 8304 // Optimize vectors in AVX mode: 8305 // 8306 // v8i16 -> v8i32 8307 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 8308 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 8309 // Concat upper and lower parts. 8310 // 8311 // v4i32 -> v4i64 8312 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 8313 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 8314 // Concat upper and lower parts. 8315 // 8316 8317 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) && 8318 ((VT != MVT::v4i64) || (InVT != MVT::v4i32))) 8319 return SDValue(); 8320 8321 if (Subtarget->hasInt256()) 8322 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In); 8323 8324 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl); 8325 SDValue Undef = DAG.getUNDEF(InVT); 8326 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND; 8327 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); 8328 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); 8329 8330 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 8331 VT.getVectorNumElements()/2); 8332 8333 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 8334 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 8335 8336 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 8337} 8338 8339SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op, 8340 SelectionDAG &DAG) const { 8341 if (Subtarget->hasFp256()) { 8342 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget); 8343 if (Res.getNode()) 8344 return Res; 8345 } 8346 8347 return SDValue(); 8348} 8349SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op, 8350 SelectionDAG &DAG) const { 8351 DebugLoc DL = Op.getDebugLoc(); 8352 EVT VT = Op.getValueType(); 8353 SDValue In = Op.getOperand(0); 8354 EVT SVT = In.getValueType(); 8355 8356 if (Subtarget->hasFp256()) { 8357 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget); 8358 if (Res.getNode()) 8359 return Res; 8360 } 8361 8362 if (!VT.is256BitVector() || !SVT.is128BitVector() || 8363 VT.getVectorNumElements() != SVT.getVectorNumElements()) 8364 return SDValue(); 8365 8366 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!"); 8367 8368 // AVX2 has better support of integer extending. 8369 if (Subtarget->hasInt256()) 8370 return DAG.getNode(X86ISD::VZEXT, DL, VT, In); 8371 8372 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In); 8373 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1}; 8374 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, 8375 DAG.getVectorShuffle(MVT::v8i16, DL, In, 8376 DAG.getUNDEF(MVT::v8i16), 8377 &Mask[0])); 8378 8379 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi); 8380} 8381 8382SDValue X86TargetLowering::lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { 8383 DebugLoc DL = Op.getDebugLoc(); 8384 EVT VT = Op.getValueType(); 8385 SDValue In = Op.getOperand(0); 8386 EVT SVT = In.getValueType(); 8387 8388 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) { 8389 // On AVX2, v4i64 -> v4i32 becomes VPERMD. 8390 if (Subtarget->hasInt256()) { 8391 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 8392 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In); 8393 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32), 8394 ShufMask); 8395 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In, 8396 DAG.getIntPtrConstant(0)); 8397 } 8398 8399 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS. 8400 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 8401 DAG.getIntPtrConstant(0)); 8402 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 8403 DAG.getIntPtrConstant(2)); 8404 8405 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo); 8406 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi); 8407 8408 // The PSHUFD mask: 8409 static const int ShufMask1[] = {0, 2, 0, 0}; 8410 SDValue Undef = DAG.getUNDEF(VT); 8411 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1); 8412 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1); 8413 8414 // The MOVLHPS mask: 8415 static const int ShufMask2[] = {0, 1, 4, 5}; 8416 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2); 8417 } 8418 8419 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) { 8420 // On AVX2, v8i32 -> v8i16 becomed PSHUFB. 8421 if (Subtarget->hasInt256()) { 8422 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In); 8423 8424 SmallVector<SDValue,32> pshufbMask; 8425 for (unsigned i = 0; i < 2; ++i) { 8426 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 8427 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 8428 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 8429 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 8430 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 8431 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 8432 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 8433 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 8434 for (unsigned j = 0; j < 8; ++j) 8435 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 8436 } 8437 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, 8438 &pshufbMask[0], 32); 8439 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV); 8440 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In); 8441 8442 static const int ShufMask[] = {0, 2, -1, -1}; 8443 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64), 8444 &ShufMask[0]); 8445 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In, 8446 DAG.getIntPtrConstant(0)); 8447 return DAG.getNode(ISD::BITCAST, DL, VT, In); 8448 } 8449 8450 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, 8451 DAG.getIntPtrConstant(0)); 8452 8453 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In, 8454 DAG.getIntPtrConstant(4)); 8455 8456 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo); 8457 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi); 8458 8459 // The PSHUFB mask: 8460 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 8461 -1, -1, -1, -1, -1, -1, -1, -1}; 8462 8463 SDValue Undef = DAG.getUNDEF(MVT::v16i8); 8464 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1); 8465 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1); 8466 8467 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo); 8468 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi); 8469 8470 // The MOVLHPS Mask: 8471 static const int ShufMask2[] = {0, 1, 4, 5}; 8472 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2); 8473 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res); 8474 } 8475 8476 // Handle truncation of V256 to V128 using shuffles. 8477 if (!VT.is128BitVector() || !SVT.is256BitVector()) 8478 return SDValue(); 8479 8480 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() && 8481 "Invalid op"); 8482 assert(Subtarget->hasFp256() && "256-bit vector without AVX!"); 8483 8484 unsigned NumElems = VT.getVectorNumElements(); 8485 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 8486 NumElems * 2); 8487 8488 SmallVector<int, 16> MaskVec(NumElems * 2, -1); 8489 // Prepare truncation shuffle mask 8490 for (unsigned i = 0; i != NumElems; ++i) 8491 MaskVec[i] = i * 2; 8492 SDValue V = DAG.getVectorShuffle(NVT, DL, 8493 DAG.getNode(ISD::BITCAST, DL, NVT, In), 8494 DAG.getUNDEF(NVT), &MaskVec[0]); 8495 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, 8496 DAG.getIntPtrConstant(0)); 8497} 8498 8499SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 8500 SelectionDAG &DAG) const { 8501 if (Op.getValueType().isVector()) { 8502 if (Op.getValueType() == MVT::v8i16) 8503 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), Op.getValueType(), 8504 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(), 8505 MVT::v8i32, Op.getOperand(0))); 8506 return SDValue(); 8507 } 8508 8509 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8510 /*IsSigned=*/ true, /*IsReplace=*/ false); 8511 SDValue FIST = Vals.first, StackSlot = Vals.second; 8512 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 8513 if (FIST.getNode() == 0) return Op; 8514 8515 if (StackSlot.getNode()) 8516 // Load the result. 8517 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8518 FIST, StackSlot, MachinePointerInfo(), 8519 false, false, false, 0); 8520 8521 // The node is the result. 8522 return FIST; 8523} 8524 8525SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 8526 SelectionDAG &DAG) const { 8527 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8528 /*IsSigned=*/ false, /*IsReplace=*/ false); 8529 SDValue FIST = Vals.first, StackSlot = Vals.second; 8530 assert(FIST.getNode() && "Unexpected failure"); 8531 8532 if (StackSlot.getNode()) 8533 // Load the result. 8534 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8535 FIST, StackSlot, MachinePointerInfo(), 8536 false, false, false, 0); 8537 8538 // The node is the result. 8539 return FIST; 8540} 8541 8542SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op, 8543 SelectionDAG &DAG) const { 8544 DebugLoc DL = Op.getDebugLoc(); 8545 EVT VT = Op.getValueType(); 8546 SDValue In = Op.getOperand(0); 8547 EVT SVT = In.getValueType(); 8548 8549 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!"); 8550 8551 return DAG.getNode(X86ISD::VFPEXT, DL, VT, 8552 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32, 8553 In, DAG.getUNDEF(SVT))); 8554} 8555 8556SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const { 8557 LLVMContext *Context = DAG.getContext(); 8558 DebugLoc dl = Op.getDebugLoc(); 8559 EVT VT = Op.getValueType(); 8560 EVT EltVT = VT; 8561 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8562 if (VT.isVector()) { 8563 EltVT = VT.getVectorElementType(); 8564 NumElts = VT.getVectorNumElements(); 8565 } 8566 Constant *C; 8567 if (EltVT == MVT::f64) 8568 C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 8569 else 8570 C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 8571 C = ConstantVector::getSplat(NumElts, C); 8572 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 8573 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8574 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8575 MachinePointerInfo::getConstantPool(), 8576 false, false, false, Alignment); 8577 if (VT.isVector()) { 8578 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8579 return DAG.getNode(ISD::BITCAST, dl, VT, 8580 DAG.getNode(ISD::AND, dl, ANDVT, 8581 DAG.getNode(ISD::BITCAST, dl, ANDVT, 8582 Op.getOperand(0)), 8583 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask))); 8584 } 8585 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8586} 8587 8588SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8589 LLVMContext *Context = DAG.getContext(); 8590 DebugLoc dl = Op.getDebugLoc(); 8591 EVT VT = Op.getValueType(); 8592 EVT EltVT = VT; 8593 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8594 if (VT.isVector()) { 8595 EltVT = VT.getVectorElementType(); 8596 NumElts = VT.getVectorNumElements(); 8597 } 8598 Constant *C; 8599 if (EltVT == MVT::f64) 8600 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8601 else 8602 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8603 C = ConstantVector::getSplat(NumElts, C); 8604 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy()); 8605 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8606 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8607 MachinePointerInfo::getConstantPool(), 8608 false, false, false, Alignment); 8609 if (VT.isVector()) { 8610 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8611 return DAG.getNode(ISD::BITCAST, dl, VT, 8612 DAG.getNode(ISD::XOR, dl, XORVT, 8613 DAG.getNode(ISD::BITCAST, dl, XORVT, 8614 Op.getOperand(0)), 8615 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 8616 } 8617 8618 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8619} 8620 8621SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8622 LLVMContext *Context = DAG.getContext(); 8623 SDValue Op0 = Op.getOperand(0); 8624 SDValue Op1 = Op.getOperand(1); 8625 DebugLoc dl = Op.getDebugLoc(); 8626 EVT VT = Op.getValueType(); 8627 EVT SrcVT = Op1.getValueType(); 8628 8629 // If second operand is smaller, extend it first. 8630 if (SrcVT.bitsLT(VT)) { 8631 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8632 SrcVT = VT; 8633 } 8634 // And if it is bigger, shrink it first. 8635 if (SrcVT.bitsGT(VT)) { 8636 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8637 SrcVT = VT; 8638 } 8639 8640 // At this point the operands and the result should have the same 8641 // type, and that won't be f80 since that is not custom lowered. 8642 8643 // First get the sign bit of second operand. 8644 SmallVector<Constant*,4> CV; 8645 if (SrcVT == MVT::f64) { 8646 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8647 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8648 } else { 8649 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8650 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8651 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8652 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8653 } 8654 Constant *C = ConstantVector::get(CV); 8655 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8656 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8657 MachinePointerInfo::getConstantPool(), 8658 false, false, false, 16); 8659 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8660 8661 // Shift sign bit right or left if the two operands have different types. 8662 if (SrcVT.bitsGT(VT)) { 8663 // Op0 is MVT::f32, Op1 is MVT::f64. 8664 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8665 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8666 DAG.getConstant(32, MVT::i32)); 8667 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8668 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8669 DAG.getIntPtrConstant(0)); 8670 } 8671 8672 // Clear first operand sign bit. 8673 CV.clear(); 8674 if (VT == MVT::f64) { 8675 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8676 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8677 } else { 8678 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8679 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8680 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8681 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8682 } 8683 C = ConstantVector::get(CV); 8684 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8685 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8686 MachinePointerInfo::getConstantPool(), 8687 false, false, false, 16); 8688 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8689 8690 // Or the value with the sign bit. 8691 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8692} 8693 8694static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) { 8695 SDValue N0 = Op.getOperand(0); 8696 DebugLoc dl = Op.getDebugLoc(); 8697 EVT VT = Op.getValueType(); 8698 8699 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8700 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8701 DAG.getConstant(1, VT)); 8702 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8703} 8704 8705// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able. 8706// 8707SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const { 8708 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree."); 8709 8710 if (!Subtarget->hasSSE41()) 8711 return SDValue(); 8712 8713 if (!Op->hasOneUse()) 8714 return SDValue(); 8715 8716 SDNode *N = Op.getNode(); 8717 DebugLoc DL = N->getDebugLoc(); 8718 8719 SmallVector<SDValue, 8> Opnds; 8720 DenseMap<SDValue, unsigned> VecInMap; 8721 EVT VT = MVT::Other; 8722 8723 // Recognize a special case where a vector is casted into wide integer to 8724 // test all 0s. 8725 Opnds.push_back(N->getOperand(0)); 8726 Opnds.push_back(N->getOperand(1)); 8727 8728 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) { 8729 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot; 8730 // BFS traverse all OR'd operands. 8731 if (I->getOpcode() == ISD::OR) { 8732 Opnds.push_back(I->getOperand(0)); 8733 Opnds.push_back(I->getOperand(1)); 8734 // Re-evaluate the number of nodes to be traversed. 8735 e += 2; // 2 more nodes (LHS and RHS) are pushed. 8736 continue; 8737 } 8738 8739 // Quit if a non-EXTRACT_VECTOR_ELT 8740 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8741 return SDValue(); 8742 8743 // Quit if without a constant index. 8744 SDValue Idx = I->getOperand(1); 8745 if (!isa<ConstantSDNode>(Idx)) 8746 return SDValue(); 8747 8748 SDValue ExtractedFromVec = I->getOperand(0); 8749 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec); 8750 if (M == VecInMap.end()) { 8751 VT = ExtractedFromVec.getValueType(); 8752 // Quit if not 128/256-bit vector. 8753 if (!VT.is128BitVector() && !VT.is256BitVector()) 8754 return SDValue(); 8755 // Quit if not the same type. 8756 if (VecInMap.begin() != VecInMap.end() && 8757 VT != VecInMap.begin()->first.getValueType()) 8758 return SDValue(); 8759 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first; 8760 } 8761 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue(); 8762 } 8763 8764 assert((VT.is128BitVector() || VT.is256BitVector()) && 8765 "Not extracted from 128-/256-bit vector."); 8766 8767 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U; 8768 SmallVector<SDValue, 8> VecIns; 8769 8770 for (DenseMap<SDValue, unsigned>::const_iterator 8771 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) { 8772 // Quit if not all elements are used. 8773 if (I->second != FullMask) 8774 return SDValue(); 8775 VecIns.push_back(I->first); 8776 } 8777 8778 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64; 8779 8780 // Cast all vectors into TestVT for PTEST. 8781 for (unsigned i = 0, e = VecIns.size(); i < e; ++i) 8782 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]); 8783 8784 // If more than one full vectors are evaluated, OR them first before PTEST. 8785 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) { 8786 // Each iteration will OR 2 nodes and append the result until there is only 8787 // 1 node left, i.e. the final OR'd value of all vectors. 8788 SDValue LHS = VecIns[Slot]; 8789 SDValue RHS = VecIns[Slot + 1]; 8790 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS)); 8791 } 8792 8793 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, 8794 VecIns.back(), VecIns.back()); 8795} 8796 8797/// Emit nodes that will be selected as "test Op0,Op0", or something 8798/// equivalent. 8799SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8800 SelectionDAG &DAG) const { 8801 DebugLoc dl = Op.getDebugLoc(); 8802 8803 // CF and OF aren't always set the way we want. Determine which 8804 // of these we need. 8805 bool NeedCF = false; 8806 bool NeedOF = false; 8807 switch (X86CC) { 8808 default: break; 8809 case X86::COND_A: case X86::COND_AE: 8810 case X86::COND_B: case X86::COND_BE: 8811 NeedCF = true; 8812 break; 8813 case X86::COND_G: case X86::COND_GE: 8814 case X86::COND_L: case X86::COND_LE: 8815 case X86::COND_O: case X86::COND_NO: 8816 NeedOF = true; 8817 break; 8818 } 8819 8820 // See if we can use the EFLAGS value from the operand instead of 8821 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8822 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8823 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8824 // Emit a CMP with 0, which is the TEST pattern. 8825 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8826 DAG.getConstant(0, Op.getValueType())); 8827 8828 unsigned Opcode = 0; 8829 unsigned NumOperands = 0; 8830 8831 // Truncate operations may prevent the merge of the SETCC instruction 8832 // and the arithmetic intruction before it. Attempt to truncate the operands 8833 // of the arithmetic instruction and use a reduced bit-width instruction. 8834 bool NeedTruncation = false; 8835 SDValue ArithOp = Op; 8836 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) { 8837 SDValue Arith = Op->getOperand(0); 8838 // Both the trunc and the arithmetic op need to have one user each. 8839 if (Arith->hasOneUse()) 8840 switch (Arith.getOpcode()) { 8841 default: break; 8842 case ISD::ADD: 8843 case ISD::SUB: 8844 case ISD::AND: 8845 case ISD::OR: 8846 case ISD::XOR: { 8847 NeedTruncation = true; 8848 ArithOp = Arith; 8849 } 8850 } 8851 } 8852 8853 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation 8854 // which may be the result of a CAST. We use the variable 'Op', which is the 8855 // non-casted variable when we check for possible users. 8856 switch (ArithOp.getOpcode()) { 8857 case ISD::ADD: 8858 // Due to an isel shortcoming, be conservative if this add is likely to be 8859 // selected as part of a load-modify-store instruction. When the root node 8860 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8861 // uses of other nodes in the match, such as the ADD in this case. This 8862 // leads to the ADD being left around and reselected, with the result being 8863 // two adds in the output. Alas, even if none our users are stores, that 8864 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8865 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8866 // climbing the DAG back to the root, and it doesn't seem to be worth the 8867 // effort. 8868 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8869 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8870 if (UI->getOpcode() != ISD::CopyToReg && 8871 UI->getOpcode() != ISD::SETCC && 8872 UI->getOpcode() != ISD::STORE) 8873 goto default_case; 8874 8875 if (ConstantSDNode *C = 8876 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) { 8877 // An add of one will be selected as an INC. 8878 if (C->getAPIntValue() == 1) { 8879 Opcode = X86ISD::INC; 8880 NumOperands = 1; 8881 break; 8882 } 8883 8884 // An add of negative one (subtract of one) will be selected as a DEC. 8885 if (C->getAPIntValue().isAllOnesValue()) { 8886 Opcode = X86ISD::DEC; 8887 NumOperands = 1; 8888 break; 8889 } 8890 } 8891 8892 // Otherwise use a regular EFLAGS-setting add. 8893 Opcode = X86ISD::ADD; 8894 NumOperands = 2; 8895 break; 8896 case ISD::AND: { 8897 // If the primary and result isn't used, don't bother using X86ISD::AND, 8898 // because a TEST instruction will be better. 8899 bool NonFlagUse = false; 8900 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8901 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8902 SDNode *User = *UI; 8903 unsigned UOpNo = UI.getOperandNo(); 8904 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8905 // Look pass truncate. 8906 UOpNo = User->use_begin().getOperandNo(); 8907 User = *User->use_begin(); 8908 } 8909 8910 if (User->getOpcode() != ISD::BRCOND && 8911 User->getOpcode() != ISD::SETCC && 8912 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) { 8913 NonFlagUse = true; 8914 break; 8915 } 8916 } 8917 8918 if (!NonFlagUse) 8919 break; 8920 } 8921 // FALL THROUGH 8922 case ISD::SUB: 8923 case ISD::OR: 8924 case ISD::XOR: 8925 // Due to the ISEL shortcoming noted above, be conservative if this op is 8926 // likely to be selected as part of a load-modify-store instruction. 8927 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8928 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8929 if (UI->getOpcode() == ISD::STORE) 8930 goto default_case; 8931 8932 // Otherwise use a regular EFLAGS-setting instruction. 8933 switch (ArithOp.getOpcode()) { 8934 default: llvm_unreachable("unexpected operator!"); 8935 case ISD::SUB: Opcode = X86ISD::SUB; break; 8936 case ISD::XOR: Opcode = X86ISD::XOR; break; 8937 case ISD::AND: Opcode = X86ISD::AND; break; 8938 case ISD::OR: { 8939 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) { 8940 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG); 8941 if (EFLAGS.getNode()) 8942 return EFLAGS; 8943 } 8944 Opcode = X86ISD::OR; 8945 break; 8946 } 8947 } 8948 8949 NumOperands = 2; 8950 break; 8951 case X86ISD::ADD: 8952 case X86ISD::SUB: 8953 case X86ISD::INC: 8954 case X86ISD::DEC: 8955 case X86ISD::OR: 8956 case X86ISD::XOR: 8957 case X86ISD::AND: 8958 return SDValue(Op.getNode(), 1); 8959 default: 8960 default_case: 8961 break; 8962 } 8963 8964 // If we found that truncation is beneficial, perform the truncation and 8965 // update 'Op'. 8966 if (NeedTruncation) { 8967 EVT VT = Op.getValueType(); 8968 SDValue WideVal = Op->getOperand(0); 8969 EVT WideVT = WideVal.getValueType(); 8970 unsigned ConvertedOp = 0; 8971 // Use a target machine opcode to prevent further DAGCombine 8972 // optimizations that may separate the arithmetic operations 8973 // from the setcc node. 8974 switch (WideVal.getOpcode()) { 8975 default: break; 8976 case ISD::ADD: ConvertedOp = X86ISD::ADD; break; 8977 case ISD::SUB: ConvertedOp = X86ISD::SUB; break; 8978 case ISD::AND: ConvertedOp = X86ISD::AND; break; 8979 case ISD::OR: ConvertedOp = X86ISD::OR; break; 8980 case ISD::XOR: ConvertedOp = X86ISD::XOR; break; 8981 } 8982 8983 if (ConvertedOp) { 8984 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8985 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) { 8986 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0)); 8987 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1)); 8988 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1); 8989 } 8990 } 8991 } 8992 8993 if (Opcode == 0) 8994 // Emit a CMP with 0, which is the TEST pattern. 8995 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8996 DAG.getConstant(0, Op.getValueType())); 8997 8998 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8999 SmallVector<SDValue, 4> Ops; 9000 for (unsigned i = 0; i != NumOperands; ++i) 9001 Ops.push_back(Op.getOperand(i)); 9002 9003 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 9004 DAG.ReplaceAllUsesWith(Op, New); 9005 return SDValue(New.getNode(), 1); 9006} 9007 9008/// Emit nodes that will be selected as "cmp Op0,Op1", or something 9009/// equivalent. 9010SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 9011 SelectionDAG &DAG) const { 9012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 9013 if (C->getAPIntValue() == 0) 9014 return EmitTest(Op0, X86CC, DAG); 9015 9016 DebugLoc dl = Op0.getDebugLoc(); 9017 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || 9018 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { 9019 // Use SUB instead of CMP to enable CSE between SUB and CMP. 9020 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); 9021 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, 9022 Op0, Op1); 9023 return SDValue(Sub.getNode(), 1); 9024 } 9025 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 9026} 9027 9028/// Convert a comparison if required by the subtarget. 9029SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 9030 SelectionDAG &DAG) const { 9031 // If the subtarget does not support the FUCOMI instruction, floating-point 9032 // comparisons have to be converted. 9033 if (Subtarget->hasCMov() || 9034 Cmp.getOpcode() != X86ISD::CMP || 9035 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 9036 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 9037 return Cmp; 9038 9039 // The instruction selector will select an FUCOM instruction instead of 9040 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 9041 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 9042 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 9043 DebugLoc dl = Cmp.getDebugLoc(); 9044 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 9045 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 9046 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 9047 DAG.getConstant(8, MVT::i8)); 9048 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 9049 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 9050} 9051 9052static bool isAllOnes(SDValue V) { 9053 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9054 return C && C->isAllOnesValue(); 9055} 9056 9057/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 9058/// if it's possible. 9059SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 9060 DebugLoc dl, SelectionDAG &DAG) const { 9061 SDValue Op0 = And.getOperand(0); 9062 SDValue Op1 = And.getOperand(1); 9063 if (Op0.getOpcode() == ISD::TRUNCATE) 9064 Op0 = Op0.getOperand(0); 9065 if (Op1.getOpcode() == ISD::TRUNCATE) 9066 Op1 = Op1.getOperand(0); 9067 9068 SDValue LHS, RHS; 9069 if (Op1.getOpcode() == ISD::SHL) 9070 std::swap(Op0, Op1); 9071 if (Op0.getOpcode() == ISD::SHL) { 9072 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 9073 if (And00C->getZExtValue() == 1) { 9074 // If we looked past a truncate, check that it's only truncating away 9075 // known zeros. 9076 unsigned BitWidth = Op0.getValueSizeInBits(); 9077 unsigned AndBitWidth = And.getValueSizeInBits(); 9078 if (BitWidth > AndBitWidth) { 9079 APInt Zeros, Ones; 9080 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 9081 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 9082 return SDValue(); 9083 } 9084 LHS = Op1; 9085 RHS = Op0.getOperand(1); 9086 } 9087 } else if (Op1.getOpcode() == ISD::Constant) { 9088 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 9089 uint64_t AndRHSVal = AndRHS->getZExtValue(); 9090 SDValue AndLHS = Op0; 9091 9092 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 9093 LHS = AndLHS.getOperand(0); 9094 RHS = AndLHS.getOperand(1); 9095 } 9096 9097 // Use BT if the immediate can't be encoded in a TEST instruction. 9098 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 9099 LHS = AndLHS; 9100 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 9101 } 9102 } 9103 9104 if (LHS.getNode()) { 9105 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip 9106 // the condition code later. 9107 bool Invert = false; 9108 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) { 9109 Invert = true; 9110 LHS = LHS.getOperand(0); 9111 } 9112 9113 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 9114 // instruction. Since the shift amount is in-range-or-undefined, we know 9115 // that doing a bittest on the i32 value is ok. We extend to i32 because 9116 // the encoding for the i16 version is larger than the i32 version. 9117 // Also promote i16 to i32 for performance / code size reason. 9118 if (LHS.getValueType() == MVT::i8 || 9119 LHS.getValueType() == MVT::i16) 9120 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 9121 9122 // If the operand types disagree, extend the shift amount to match. Since 9123 // BT ignores high bits (like shifts) we can use anyextend. 9124 if (LHS.getValueType() != RHS.getValueType()) 9125 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 9126 9127 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 9128 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 9129 // Flip the condition if the LHS was a not instruction 9130 if (Invert) 9131 Cond = X86::GetOppositeBranchCondition(Cond); 9132 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9133 DAG.getConstant(Cond, MVT::i8), BT); 9134 } 9135 9136 return SDValue(); 9137} 9138 9139SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 9140 9141 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 9142 9143 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 9144 SDValue Op0 = Op.getOperand(0); 9145 SDValue Op1 = Op.getOperand(1); 9146 DebugLoc dl = Op.getDebugLoc(); 9147 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 9148 9149 // Optimize to BT if possible. 9150 // Lower (X & (1 << N)) == 0 to BT(X, N). 9151 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 9152 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 9153 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 9154 Op1.getOpcode() == ISD::Constant && 9155 cast<ConstantSDNode>(Op1)->isNullValue() && 9156 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 9157 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 9158 if (NewSetCC.getNode()) 9159 return NewSetCC; 9160 } 9161 9162 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 9163 // these. 9164 if (Op1.getOpcode() == ISD::Constant && 9165 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 9166 cast<ConstantSDNode>(Op1)->isNullValue()) && 9167 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 9168 9169 // If the input is a setcc, then reuse the input setcc or use a new one with 9170 // the inverted condition. 9171 if (Op0.getOpcode() == X86ISD::SETCC) { 9172 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 9173 bool Invert = (CC == ISD::SETNE) ^ 9174 cast<ConstantSDNode>(Op1)->isNullValue(); 9175 if (!Invert) return Op0; 9176 9177 CCode = X86::GetOppositeBranchCondition(CCode); 9178 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9179 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 9180 } 9181 } 9182 9183 bool isFP = Op1.getValueType().isFloatingPoint(); 9184 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 9185 if (X86CC == X86::COND_INVALID) 9186 return SDValue(); 9187 9188 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 9189 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 9190 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9191 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 9192} 9193 9194// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 9195// ones, and then concatenate the result back. 9196static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 9197 EVT VT = Op.getValueType(); 9198 9199 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC && 9200 "Unsupported value type for operation"); 9201 9202 unsigned NumElems = VT.getVectorNumElements(); 9203 DebugLoc dl = Op.getDebugLoc(); 9204 SDValue CC = Op.getOperand(2); 9205 9206 // Extract the LHS vectors 9207 SDValue LHS = Op.getOperand(0); 9208 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 9209 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 9210 9211 // Extract the RHS vectors 9212 SDValue RHS = Op.getOperand(1); 9213 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 9214 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 9215 9216 // Issue the operation on the smaller types and concatenate the result back 9217 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9218 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9219 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9220 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 9221 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 9222} 9223 9224SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 9225 SDValue Cond; 9226 SDValue Op0 = Op.getOperand(0); 9227 SDValue Op1 = Op.getOperand(1); 9228 SDValue CC = Op.getOperand(2); 9229 EVT VT = Op.getValueType(); 9230 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 9231 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 9232 DebugLoc dl = Op.getDebugLoc(); 9233 9234 if (isFP) { 9235#ifndef NDEBUG 9236 EVT EltVT = Op0.getValueType().getVectorElementType(); 9237 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 9238#endif 9239 9240 unsigned SSECC; 9241 bool Swap = false; 9242 9243 // SSE Condition code mapping: 9244 // 0 - EQ 9245 // 1 - LT 9246 // 2 - LE 9247 // 3 - UNORD 9248 // 4 - NEQ 9249 // 5 - NLT 9250 // 6 - NLE 9251 // 7 - ORD 9252 switch (SetCCOpcode) { 9253 default: llvm_unreachable("Unexpected SETCC condition"); 9254 case ISD::SETOEQ: 9255 case ISD::SETEQ: SSECC = 0; break; 9256 case ISD::SETOGT: 9257 case ISD::SETGT: Swap = true; // Fallthrough 9258 case ISD::SETLT: 9259 case ISD::SETOLT: SSECC = 1; break; 9260 case ISD::SETOGE: 9261 case ISD::SETGE: Swap = true; // Fallthrough 9262 case ISD::SETLE: 9263 case ISD::SETOLE: SSECC = 2; break; 9264 case ISD::SETUO: SSECC = 3; break; 9265 case ISD::SETUNE: 9266 case ISD::SETNE: SSECC = 4; break; 9267 case ISD::SETULE: Swap = true; // Fallthrough 9268 case ISD::SETUGE: SSECC = 5; break; 9269 case ISD::SETULT: Swap = true; // Fallthrough 9270 case ISD::SETUGT: SSECC = 6; break; 9271 case ISD::SETO: SSECC = 7; break; 9272 case ISD::SETUEQ: 9273 case ISD::SETONE: SSECC = 8; break; 9274 } 9275 if (Swap) 9276 std::swap(Op0, Op1); 9277 9278 // In the two special cases we can't handle, emit two comparisons. 9279 if (SSECC == 8) { 9280 unsigned CC0, CC1; 9281 unsigned CombineOpc; 9282 if (SetCCOpcode == ISD::SETUEQ) { 9283 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR; 9284 } else { 9285 assert(SetCCOpcode == ISD::SETONE); 9286 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND; 9287 } 9288 9289 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 9290 DAG.getConstant(CC0, MVT::i8)); 9291 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 9292 DAG.getConstant(CC1, MVT::i8)); 9293 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1); 9294 } 9295 // Handle all other FP comparisons here. 9296 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 9297 DAG.getConstant(SSECC, MVT::i8)); 9298 } 9299 9300 // Break 256-bit integer vector compare into smaller ones. 9301 if (VT.is256BitVector() && !Subtarget->hasInt256()) 9302 return Lower256IntVSETCC(Op, DAG); 9303 9304 // We are handling one of the integer comparisons here. Since SSE only has 9305 // GT and EQ comparisons for integer, swapping operands and multiple 9306 // operations may be required for some comparisons. 9307 unsigned Opc; 9308 bool Swap = false, Invert = false, FlipSigns = false; 9309 9310 switch (SetCCOpcode) { 9311 default: llvm_unreachable("Unexpected SETCC condition"); 9312 case ISD::SETNE: Invert = true; 9313 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 9314 case ISD::SETLT: Swap = true; 9315 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 9316 case ISD::SETGE: Swap = true; 9317 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 9318 case ISD::SETULT: Swap = true; 9319 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 9320 case ISD::SETUGE: Swap = true; 9321 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 9322 } 9323 if (Swap) 9324 std::swap(Op0, Op1); 9325 9326 // Check that the operation in question is available (most are plain SSE2, 9327 // but PCMPGTQ and PCMPEQQ have different requirements). 9328 if (VT == MVT::v2i64) { 9329 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) 9330 return SDValue(); 9331 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) { 9332 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with 9333 // pcmpeqd + pshufd + pand. 9334 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!"); 9335 9336 // First cast everything to the right type, 9337 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0); 9338 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); 9339 9340 // Do the compare. 9341 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1); 9342 9343 // Make sure the lower and upper halves are both all-ones. 9344 const int Mask[] = { 1, 0, 3, 2 }; 9345 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask); 9346 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf); 9347 9348 if (Invert) 9349 Result = DAG.getNOT(dl, Result, MVT::v4i32); 9350 9351 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 9352 } 9353 } 9354 9355 // Since SSE has no unsigned integer comparisons, we need to flip the sign 9356 // bits of the inputs before performing those operations. 9357 if (FlipSigns) { 9358 EVT EltVT = VT.getVectorElementType(); 9359 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 9360 EltVT); 9361 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 9362 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 9363 SignBits.size()); 9364 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 9365 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 9366 } 9367 9368 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 9369 9370 // If the logical-not of the result is required, perform that now. 9371 if (Invert) 9372 Result = DAG.getNOT(dl, Result, VT); 9373 9374 return Result; 9375} 9376 9377// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 9378static bool isX86LogicalCmp(SDValue Op) { 9379 unsigned Opc = Op.getNode()->getOpcode(); 9380 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 9381 Opc == X86ISD::SAHF) 9382 return true; 9383 if (Op.getResNo() == 1 && 9384 (Opc == X86ISD::ADD || 9385 Opc == X86ISD::SUB || 9386 Opc == X86ISD::ADC || 9387 Opc == X86ISD::SBB || 9388 Opc == X86ISD::SMUL || 9389 Opc == X86ISD::UMUL || 9390 Opc == X86ISD::INC || 9391 Opc == X86ISD::DEC || 9392 Opc == X86ISD::OR || 9393 Opc == X86ISD::XOR || 9394 Opc == X86ISD::AND)) 9395 return true; 9396 9397 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 9398 return true; 9399 9400 return false; 9401} 9402 9403static bool isZero(SDValue V) { 9404 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 9405 return C && C->isNullValue(); 9406} 9407 9408static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) { 9409 if (V.getOpcode() != ISD::TRUNCATE) 9410 return false; 9411 9412 SDValue VOp0 = V.getOperand(0); 9413 unsigned InBits = VOp0.getValueSizeInBits(); 9414 unsigned Bits = V.getValueSizeInBits(); 9415 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits)); 9416} 9417 9418SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 9419 bool addTest = true; 9420 SDValue Cond = Op.getOperand(0); 9421 SDValue Op1 = Op.getOperand(1); 9422 SDValue Op2 = Op.getOperand(2); 9423 DebugLoc DL = Op.getDebugLoc(); 9424 SDValue CC; 9425 9426 if (Cond.getOpcode() == ISD::SETCC) { 9427 SDValue NewCond = LowerSETCC(Cond, DAG); 9428 if (NewCond.getNode()) 9429 Cond = NewCond; 9430 } 9431 9432 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 9433 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 9434 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 9435 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 9436 if (Cond.getOpcode() == X86ISD::SETCC && 9437 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 9438 isZero(Cond.getOperand(1).getOperand(1))) { 9439 SDValue Cmp = Cond.getOperand(1); 9440 9441 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 9442 9443 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 9444 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 9445 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 9446 9447 SDValue CmpOp0 = Cmp.getOperand(0); 9448 // Apply further optimizations for special cases 9449 // (select (x != 0), -1, 0) -> neg & sbb 9450 // (select (x == 0), 0, -1) -> neg & sbb 9451 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 9452 if (YC->isNullValue() && 9453 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 9454 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 9455 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs, 9456 DAG.getConstant(0, CmpOp0.getValueType()), 9457 CmpOp0); 9458 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9459 DAG.getConstant(X86::COND_B, MVT::i8), 9460 SDValue(Neg.getNode(), 1)); 9461 return Res; 9462 } 9463 9464 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 9465 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 9466 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9467 9468 SDValue Res = // Res = 0 or -1. 9469 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9470 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 9471 9472 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 9473 Res = DAG.getNOT(DL, Res, Res.getValueType()); 9474 9475 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 9476 if (N2C == 0 || !N2C->isNullValue()) 9477 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 9478 return Res; 9479 } 9480 } 9481 9482 // Look past (and (setcc_carry (cmp ...)), 1). 9483 if (Cond.getOpcode() == ISD::AND && 9484 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9485 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9486 if (C && C->getAPIntValue() == 1) 9487 Cond = Cond.getOperand(0); 9488 } 9489 9490 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9491 // setting operand in place of the X86ISD::SETCC. 9492 unsigned CondOpcode = Cond.getOpcode(); 9493 if (CondOpcode == X86ISD::SETCC || 9494 CondOpcode == X86ISD::SETCC_CARRY) { 9495 CC = Cond.getOperand(0); 9496 9497 SDValue Cmp = Cond.getOperand(1); 9498 unsigned Opc = Cmp.getOpcode(); 9499 EVT VT = Op.getValueType(); 9500 9501 bool IllegalFPCMov = false; 9502 if (VT.isFloatingPoint() && !VT.isVector() && 9503 !isScalarFPTypeInSSEReg(VT)) // FPStack? 9504 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 9505 9506 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 9507 Opc == X86ISD::BT) { // FIXME 9508 Cond = Cmp; 9509 addTest = false; 9510 } 9511 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9512 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9513 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9514 Cond.getOperand(0).getValueType() != MVT::i8)) { 9515 SDValue LHS = Cond.getOperand(0); 9516 SDValue RHS = Cond.getOperand(1); 9517 unsigned X86Opcode; 9518 unsigned X86Cond; 9519 SDVTList VTs; 9520 switch (CondOpcode) { 9521 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9522 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9523 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9524 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9525 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9526 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9527 default: llvm_unreachable("unexpected overflowing operator"); 9528 } 9529 if (CondOpcode == ISD::UMULO) 9530 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9531 MVT::i32); 9532 else 9533 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9534 9535 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 9536 9537 if (CondOpcode == ISD::UMULO) 9538 Cond = X86Op.getValue(2); 9539 else 9540 Cond = X86Op.getValue(1); 9541 9542 CC = DAG.getConstant(X86Cond, MVT::i8); 9543 addTest = false; 9544 } 9545 9546 if (addTest) { 9547 // Look pass the truncate if the high bits are known zero. 9548 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 9549 Cond = Cond.getOperand(0); 9550 9551 // We know the result of AND is compared against zero. Try to match 9552 // it to BT. 9553 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9554 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 9555 if (NewSetCC.getNode()) { 9556 CC = NewSetCC.getOperand(0); 9557 Cond = NewSetCC.getOperand(1); 9558 addTest = false; 9559 } 9560 } 9561 } 9562 9563 if (addTest) { 9564 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9565 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9566 } 9567 9568 // a < b ? -1 : 0 -> RES = ~setcc_carry 9569 // a < b ? 0 : -1 -> RES = setcc_carry 9570 // a >= b ? -1 : 0 -> RES = setcc_carry 9571 // a >= b ? 0 : -1 -> RES = ~setcc_carry 9572 if (Cond.getOpcode() == X86ISD::SUB) { 9573 Cond = ConvertCmpIfNecessary(Cond, DAG); 9574 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 9575 9576 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 9577 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 9578 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 9579 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 9580 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 9581 return DAG.getNOT(DL, Res, Res.getValueType()); 9582 return Res; 9583 } 9584 } 9585 9586 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate 9587 // widen the cmov and push the truncate through. This avoids introducing a new 9588 // branch during isel and doesn't add any extensions. 9589 if (Op.getValueType() == MVT::i8 && 9590 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) { 9591 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0); 9592 if (T1.getValueType() == T2.getValueType() && 9593 // Blacklist CopyFromReg to avoid partial register stalls. 9594 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){ 9595 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue); 9596 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond); 9597 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov); 9598 } 9599 } 9600 9601 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 9602 // condition is true. 9603 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 9604 SDValue Ops[] = { Op2, Op1, CC, Cond }; 9605 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 9606} 9607 9608SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op, 9609 SelectionDAG &DAG) const { 9610 EVT VT = Op->getValueType(0); 9611 SDValue In = Op->getOperand(0); 9612 EVT InVT = In.getValueType(); 9613 DebugLoc dl = Op->getDebugLoc(); 9614 9615 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) && 9616 (VT != MVT::v8i32 || InVT != MVT::v8i16)) 9617 return SDValue(); 9618 9619 if (Subtarget->hasInt256()) 9620 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In); 9621 9622 // Optimize vectors in AVX mode 9623 // Sign extend v8i16 to v8i32 and 9624 // v4i32 to v4i64 9625 // 9626 // Divide input vector into two parts 9627 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 9628 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 9629 // concat the vectors to original VT 9630 9631 unsigned NumElems = InVT.getVectorNumElements(); 9632 SDValue Undef = DAG.getUNDEF(InVT); 9633 9634 SmallVector<int,8> ShufMask1(NumElems, -1); 9635 for (unsigned i = 0; i != NumElems/2; ++i) 9636 ShufMask1[i] = i; 9637 9638 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]); 9639 9640 SmallVector<int,8> ShufMask2(NumElems, -1); 9641 for (unsigned i = 0; i != NumElems/2; ++i) 9642 ShufMask2[i] = i + NumElems/2; 9643 9644 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]); 9645 9646 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 9647 VT.getVectorNumElements()/2); 9648 9649 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 9650 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 9651 9652 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 9653} 9654 9655// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 9656// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 9657// from the AND / OR. 9658static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 9659 Opc = Op.getOpcode(); 9660 if (Opc != ISD::OR && Opc != ISD::AND) 9661 return false; 9662 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9663 Op.getOperand(0).hasOneUse() && 9664 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 9665 Op.getOperand(1).hasOneUse()); 9666} 9667 9668// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 9669// 1 and that the SETCC node has a single use. 9670static bool isXor1OfSetCC(SDValue Op) { 9671 if (Op.getOpcode() != ISD::XOR) 9672 return false; 9673 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 9674 if (N1C && N1C->getAPIntValue() == 1) { 9675 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 9676 Op.getOperand(0).hasOneUse(); 9677 } 9678 return false; 9679} 9680 9681SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 9682 bool addTest = true; 9683 SDValue Chain = Op.getOperand(0); 9684 SDValue Cond = Op.getOperand(1); 9685 SDValue Dest = Op.getOperand(2); 9686 DebugLoc dl = Op.getDebugLoc(); 9687 SDValue CC; 9688 bool Inverted = false; 9689 9690 if (Cond.getOpcode() == ISD::SETCC) { 9691 // Check for setcc([su]{add,sub,mul}o == 0). 9692 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 9693 isa<ConstantSDNode>(Cond.getOperand(1)) && 9694 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 9695 Cond.getOperand(0).getResNo() == 1 && 9696 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 9697 Cond.getOperand(0).getOpcode() == ISD::UADDO || 9698 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 9699 Cond.getOperand(0).getOpcode() == ISD::USUBO || 9700 Cond.getOperand(0).getOpcode() == ISD::SMULO || 9701 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 9702 Inverted = true; 9703 Cond = Cond.getOperand(0); 9704 } else { 9705 SDValue NewCond = LowerSETCC(Cond, DAG); 9706 if (NewCond.getNode()) 9707 Cond = NewCond; 9708 } 9709 } 9710#if 0 9711 // FIXME: LowerXALUO doesn't handle these!! 9712 else if (Cond.getOpcode() == X86ISD::ADD || 9713 Cond.getOpcode() == X86ISD::SUB || 9714 Cond.getOpcode() == X86ISD::SMUL || 9715 Cond.getOpcode() == X86ISD::UMUL) 9716 Cond = LowerXALUO(Cond, DAG); 9717#endif 9718 9719 // Look pass (and (setcc_carry (cmp ...)), 1). 9720 if (Cond.getOpcode() == ISD::AND && 9721 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9722 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9723 if (C && C->getAPIntValue() == 1) 9724 Cond = Cond.getOperand(0); 9725 } 9726 9727 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9728 // setting operand in place of the X86ISD::SETCC. 9729 unsigned CondOpcode = Cond.getOpcode(); 9730 if (CondOpcode == X86ISD::SETCC || 9731 CondOpcode == X86ISD::SETCC_CARRY) { 9732 CC = Cond.getOperand(0); 9733 9734 SDValue Cmp = Cond.getOperand(1); 9735 unsigned Opc = Cmp.getOpcode(); 9736 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 9737 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 9738 Cond = Cmp; 9739 addTest = false; 9740 } else { 9741 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 9742 default: break; 9743 case X86::COND_O: 9744 case X86::COND_B: 9745 // These can only come from an arithmetic instruction with overflow, 9746 // e.g. SADDO, UADDO. 9747 Cond = Cond.getNode()->getOperand(1); 9748 addTest = false; 9749 break; 9750 } 9751 } 9752 } 9753 CondOpcode = Cond.getOpcode(); 9754 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9755 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9756 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9757 Cond.getOperand(0).getValueType() != MVT::i8)) { 9758 SDValue LHS = Cond.getOperand(0); 9759 SDValue RHS = Cond.getOperand(1); 9760 unsigned X86Opcode; 9761 unsigned X86Cond; 9762 SDVTList VTs; 9763 switch (CondOpcode) { 9764 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9765 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9766 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9767 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9768 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9769 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9770 default: llvm_unreachable("unexpected overflowing operator"); 9771 } 9772 if (Inverted) 9773 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 9774 if (CondOpcode == ISD::UMULO) 9775 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9776 MVT::i32); 9777 else 9778 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9779 9780 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 9781 9782 if (CondOpcode == ISD::UMULO) 9783 Cond = X86Op.getValue(2); 9784 else 9785 Cond = X86Op.getValue(1); 9786 9787 CC = DAG.getConstant(X86Cond, MVT::i8); 9788 addTest = false; 9789 } else { 9790 unsigned CondOpc; 9791 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 9792 SDValue Cmp = Cond.getOperand(0).getOperand(1); 9793 if (CondOpc == ISD::OR) { 9794 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 9795 // two branches instead of an explicit OR instruction with a 9796 // separate test. 9797 if (Cmp == Cond.getOperand(1).getOperand(1) && 9798 isX86LogicalCmp(Cmp)) { 9799 CC = Cond.getOperand(0).getOperand(0); 9800 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9801 Chain, Dest, CC, Cmp); 9802 CC = Cond.getOperand(1).getOperand(0); 9803 Cond = Cmp; 9804 addTest = false; 9805 } 9806 } else { // ISD::AND 9807 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 9808 // two branches instead of an explicit AND instruction with a 9809 // separate test. However, we only do this if this block doesn't 9810 // have a fall-through edge, because this requires an explicit 9811 // jmp when the condition is false. 9812 if (Cmp == Cond.getOperand(1).getOperand(1) && 9813 isX86LogicalCmp(Cmp) && 9814 Op.getNode()->hasOneUse()) { 9815 X86::CondCode CCode = 9816 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9817 CCode = X86::GetOppositeBranchCondition(CCode); 9818 CC = DAG.getConstant(CCode, MVT::i8); 9819 SDNode *User = *Op.getNode()->use_begin(); 9820 // Look for an unconditional branch following this conditional branch. 9821 // We need this because we need to reverse the successors in order 9822 // to implement FCMP_OEQ. 9823 if (User->getOpcode() == ISD::BR) { 9824 SDValue FalseBB = User->getOperand(1); 9825 SDNode *NewBR = 9826 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9827 assert(NewBR == User); 9828 (void)NewBR; 9829 Dest = FalseBB; 9830 9831 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9832 Chain, Dest, CC, Cmp); 9833 X86::CondCode CCode = 9834 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9835 CCode = X86::GetOppositeBranchCondition(CCode); 9836 CC = DAG.getConstant(CCode, MVT::i8); 9837 Cond = Cmp; 9838 addTest = false; 9839 } 9840 } 9841 } 9842 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9843 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9844 // It should be transformed during dag combiner except when the condition 9845 // is set by a arithmetics with overflow node. 9846 X86::CondCode CCode = 9847 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9848 CCode = X86::GetOppositeBranchCondition(CCode); 9849 CC = DAG.getConstant(CCode, MVT::i8); 9850 Cond = Cond.getOperand(0).getOperand(1); 9851 addTest = false; 9852 } else if (Cond.getOpcode() == ISD::SETCC && 9853 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9854 // For FCMP_OEQ, we can emit 9855 // two branches instead of an explicit AND instruction with a 9856 // separate test. However, we only do this if this block doesn't 9857 // have a fall-through edge, because this requires an explicit 9858 // jmp when the condition is false. 9859 if (Op.getNode()->hasOneUse()) { 9860 SDNode *User = *Op.getNode()->use_begin(); 9861 // Look for an unconditional branch following this conditional branch. 9862 // We need this because we need to reverse the successors in order 9863 // to implement FCMP_OEQ. 9864 if (User->getOpcode() == ISD::BR) { 9865 SDValue FalseBB = User->getOperand(1); 9866 SDNode *NewBR = 9867 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9868 assert(NewBR == User); 9869 (void)NewBR; 9870 Dest = FalseBB; 9871 9872 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9873 Cond.getOperand(0), Cond.getOperand(1)); 9874 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9875 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9876 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9877 Chain, Dest, CC, Cmp); 9878 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9879 Cond = Cmp; 9880 addTest = false; 9881 } 9882 } 9883 } else if (Cond.getOpcode() == ISD::SETCC && 9884 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9885 // For FCMP_UNE, we can emit 9886 // two branches instead of an explicit AND instruction with a 9887 // separate test. However, we only do this if this block doesn't 9888 // have a fall-through edge, because this requires an explicit 9889 // jmp when the condition is false. 9890 if (Op.getNode()->hasOneUse()) { 9891 SDNode *User = *Op.getNode()->use_begin(); 9892 // Look for an unconditional branch following this conditional branch. 9893 // We need this because we need to reverse the successors in order 9894 // to implement FCMP_UNE. 9895 if (User->getOpcode() == ISD::BR) { 9896 SDValue FalseBB = User->getOperand(1); 9897 SDNode *NewBR = 9898 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9899 assert(NewBR == User); 9900 (void)NewBR; 9901 9902 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9903 Cond.getOperand(0), Cond.getOperand(1)); 9904 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9905 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9906 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9907 Chain, Dest, CC, Cmp); 9908 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9909 Cond = Cmp; 9910 addTest = false; 9911 Dest = FalseBB; 9912 } 9913 } 9914 } 9915 } 9916 9917 if (addTest) { 9918 // Look pass the truncate if the high bits are known zero. 9919 if (isTruncWithZeroHighBitsInput(Cond, DAG)) 9920 Cond = Cond.getOperand(0); 9921 9922 // We know the result of AND is compared against zero. Try to match 9923 // it to BT. 9924 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9925 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9926 if (NewSetCC.getNode()) { 9927 CC = NewSetCC.getOperand(0); 9928 Cond = NewSetCC.getOperand(1); 9929 addTest = false; 9930 } 9931 } 9932 } 9933 9934 if (addTest) { 9935 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9936 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9937 } 9938 Cond = ConvertCmpIfNecessary(Cond, DAG); 9939 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9940 Chain, Dest, CC, Cond); 9941} 9942 9943// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9944// Calls to _alloca is needed to probe the stack when allocating more than 4k 9945// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9946// that the guard pages used by the OS virtual memory manager are allocated in 9947// correct sequence. 9948SDValue 9949X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9950 SelectionDAG &DAG) const { 9951 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9952 getTargetMachine().Options.EnableSegmentedStacks) && 9953 "This should be used only on Windows targets or when segmented stacks " 9954 "are being used"); 9955 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9956 DebugLoc dl = Op.getDebugLoc(); 9957 9958 // Get the inputs. 9959 SDValue Chain = Op.getOperand(0); 9960 SDValue Size = Op.getOperand(1); 9961 // FIXME: Ensure alignment here 9962 9963 bool Is64Bit = Subtarget->is64Bit(); 9964 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9965 9966 if (getTargetMachine().Options.EnableSegmentedStacks) { 9967 MachineFunction &MF = DAG.getMachineFunction(); 9968 MachineRegisterInfo &MRI = MF.getRegInfo(); 9969 9970 if (Is64Bit) { 9971 // The 64 bit implementation of segmented stacks needs to clobber both r10 9972 // r11. This makes it impossible to use it along with nested parameters. 9973 const Function *F = MF.getFunction(); 9974 9975 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9976 I != E; ++I) 9977 if (I->hasNestAttr()) 9978 report_fatal_error("Cannot use segmented stacks with functions that " 9979 "have nested arguments."); 9980 } 9981 9982 const TargetRegisterClass *AddrRegClass = 9983 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9984 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9985 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9986 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9987 DAG.getRegister(Vreg, SPTy)); 9988 SDValue Ops1[2] = { Value, Chain }; 9989 return DAG.getMergeValues(Ops1, 2, dl); 9990 } else { 9991 SDValue Flag; 9992 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9993 9994 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9995 Flag = Chain.getValue(1); 9996 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9997 9998 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9999 Flag = Chain.getValue(1); 10000 10001 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), 10002 SPTy).getValue(1); 10003 10004 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 10005 return DAG.getMergeValues(Ops1, 2, dl); 10006 } 10007} 10008 10009SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 10010 MachineFunction &MF = DAG.getMachineFunction(); 10011 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 10012 10013 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 10014 DebugLoc DL = Op.getDebugLoc(); 10015 10016 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 10017 // vastart just stores the address of the VarArgsFrameIndex slot into the 10018 // memory location argument. 10019 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 10020 getPointerTy()); 10021 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 10022 MachinePointerInfo(SV), false, false, 0); 10023 } 10024 10025 // __va_list_tag: 10026 // gp_offset (0 - 6 * 8) 10027 // fp_offset (48 - 48 + 8 * 16) 10028 // overflow_arg_area (point to parameters coming in memory). 10029 // reg_save_area 10030 SmallVector<SDValue, 8> MemOps; 10031 SDValue FIN = Op.getOperand(1); 10032 // Store gp_offset 10033 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 10034 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 10035 MVT::i32), 10036 FIN, MachinePointerInfo(SV), false, false, 0); 10037 MemOps.push_back(Store); 10038 10039 // Store fp_offset 10040 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10041 FIN, DAG.getIntPtrConstant(4)); 10042 Store = DAG.getStore(Op.getOperand(0), DL, 10043 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 10044 MVT::i32), 10045 FIN, MachinePointerInfo(SV, 4), false, false, 0); 10046 MemOps.push_back(Store); 10047 10048 // Store ptr to overflow_arg_area 10049 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10050 FIN, DAG.getIntPtrConstant(4)); 10051 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 10052 getPointerTy()); 10053 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 10054 MachinePointerInfo(SV, 8), 10055 false, false, 0); 10056 MemOps.push_back(Store); 10057 10058 // Store ptr to reg_save_area. 10059 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 10060 FIN, DAG.getIntPtrConstant(8)); 10061 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 10062 getPointerTy()); 10063 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 10064 MachinePointerInfo(SV, 16), false, false, 0); 10065 MemOps.push_back(Store); 10066 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 10067 &MemOps[0], MemOps.size()); 10068} 10069 10070SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 10071 assert(Subtarget->is64Bit() && 10072 "LowerVAARG only handles 64-bit va_arg!"); 10073 assert((Subtarget->isTargetLinux() || 10074 Subtarget->isTargetDarwin()) && 10075 "Unhandled target in LowerVAARG"); 10076 assert(Op.getNode()->getNumOperands() == 4); 10077 SDValue Chain = Op.getOperand(0); 10078 SDValue SrcPtr = Op.getOperand(1); 10079 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 10080 unsigned Align = Op.getConstantOperandVal(3); 10081 DebugLoc dl = Op.getDebugLoc(); 10082 10083 EVT ArgVT = Op.getNode()->getValueType(0); 10084 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 10085 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy); 10086 uint8_t ArgMode; 10087 10088 // Decide which area this value should be read from. 10089 // TODO: Implement the AMD64 ABI in its entirety. This simple 10090 // selection mechanism works only for the basic types. 10091 if (ArgVT == MVT::f80) { 10092 llvm_unreachable("va_arg for f80 not yet implemented"); 10093 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 10094 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 10095 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 10096 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 10097 } else { 10098 llvm_unreachable("Unhandled argument type in LowerVAARG"); 10099 } 10100 10101 if (ArgMode == 2) { 10102 // Sanity Check: Make sure using fp_offset makes sense. 10103 assert(!getTargetMachine().Options.UseSoftFloat && 10104 !(DAG.getMachineFunction() 10105 .getFunction()->getAttributes() 10106 .hasAttribute(AttributeSet::FunctionIndex, 10107 Attribute::NoImplicitFloat)) && 10108 Subtarget->hasSSE1()); 10109 } 10110 10111 // Insert VAARG_64 node into the DAG 10112 // VAARG_64 returns two values: Variable Argument Address, Chain 10113 SmallVector<SDValue, 11> InstOps; 10114 InstOps.push_back(Chain); 10115 InstOps.push_back(SrcPtr); 10116 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 10117 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 10118 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 10119 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 10120 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 10121 VTs, &InstOps[0], InstOps.size(), 10122 MVT::i64, 10123 MachinePointerInfo(SV), 10124 /*Align=*/0, 10125 /*Volatile=*/false, 10126 /*ReadMem=*/true, 10127 /*WriteMem=*/true); 10128 Chain = VAARG.getValue(1); 10129 10130 // Load the next argument and return it 10131 return DAG.getLoad(ArgVT, dl, 10132 Chain, 10133 VAARG, 10134 MachinePointerInfo(), 10135 false, false, false, 0); 10136} 10137 10138static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget, 10139 SelectionDAG &DAG) { 10140 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 10141 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 10142 SDValue Chain = Op.getOperand(0); 10143 SDValue DstPtr = Op.getOperand(1); 10144 SDValue SrcPtr = Op.getOperand(2); 10145 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 10146 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 10147 DebugLoc DL = Op.getDebugLoc(); 10148 10149 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 10150 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 10151 false, 10152 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 10153} 10154 10155// getTargetVShiftNOde - Handle vector element shifts where the shift amount 10156// may or may not be a constant. Takes immediate version of shift as input. 10157static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 10158 SDValue SrcOp, SDValue ShAmt, 10159 SelectionDAG &DAG) { 10160 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 10161 10162 if (isa<ConstantSDNode>(ShAmt)) { 10163 // Constant may be a TargetConstant. Use a regular constant. 10164 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 10165 switch (Opc) { 10166 default: llvm_unreachable("Unknown target vector shift node"); 10167 case X86ISD::VSHLI: 10168 case X86ISD::VSRLI: 10169 case X86ISD::VSRAI: 10170 return DAG.getNode(Opc, dl, VT, SrcOp, 10171 DAG.getConstant(ShiftAmt, MVT::i32)); 10172 } 10173 } 10174 10175 // Change opcode to non-immediate version 10176 switch (Opc) { 10177 default: llvm_unreachable("Unknown target vector shift node"); 10178 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 10179 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 10180 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 10181 } 10182 10183 // Need to build a vector containing shift amount 10184 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 10185 SDValue ShOps[4]; 10186 ShOps[0] = ShAmt; 10187 ShOps[1] = DAG.getConstant(0, MVT::i32); 10188 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32); 10189 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 10190 10191 // The return type has to be a 128-bit type with the same element 10192 // type as the input type. 10193 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10194 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); 10195 10196 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt); 10197 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 10198} 10199 10200static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 10201 DebugLoc dl = Op.getDebugLoc(); 10202 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10203 switch (IntNo) { 10204 default: return SDValue(); // Don't custom lower most intrinsics. 10205 // Comparison intrinsics. 10206 case Intrinsic::x86_sse_comieq_ss: 10207 case Intrinsic::x86_sse_comilt_ss: 10208 case Intrinsic::x86_sse_comile_ss: 10209 case Intrinsic::x86_sse_comigt_ss: 10210 case Intrinsic::x86_sse_comige_ss: 10211 case Intrinsic::x86_sse_comineq_ss: 10212 case Intrinsic::x86_sse_ucomieq_ss: 10213 case Intrinsic::x86_sse_ucomilt_ss: 10214 case Intrinsic::x86_sse_ucomile_ss: 10215 case Intrinsic::x86_sse_ucomigt_ss: 10216 case Intrinsic::x86_sse_ucomige_ss: 10217 case Intrinsic::x86_sse_ucomineq_ss: 10218 case Intrinsic::x86_sse2_comieq_sd: 10219 case Intrinsic::x86_sse2_comilt_sd: 10220 case Intrinsic::x86_sse2_comile_sd: 10221 case Intrinsic::x86_sse2_comigt_sd: 10222 case Intrinsic::x86_sse2_comige_sd: 10223 case Intrinsic::x86_sse2_comineq_sd: 10224 case Intrinsic::x86_sse2_ucomieq_sd: 10225 case Intrinsic::x86_sse2_ucomilt_sd: 10226 case Intrinsic::x86_sse2_ucomile_sd: 10227 case Intrinsic::x86_sse2_ucomigt_sd: 10228 case Intrinsic::x86_sse2_ucomige_sd: 10229 case Intrinsic::x86_sse2_ucomineq_sd: { 10230 unsigned Opc; 10231 ISD::CondCode CC; 10232 switch (IntNo) { 10233 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10234 case Intrinsic::x86_sse_comieq_ss: 10235 case Intrinsic::x86_sse2_comieq_sd: 10236 Opc = X86ISD::COMI; 10237 CC = ISD::SETEQ; 10238 break; 10239 case Intrinsic::x86_sse_comilt_ss: 10240 case Intrinsic::x86_sse2_comilt_sd: 10241 Opc = X86ISD::COMI; 10242 CC = ISD::SETLT; 10243 break; 10244 case Intrinsic::x86_sse_comile_ss: 10245 case Intrinsic::x86_sse2_comile_sd: 10246 Opc = X86ISD::COMI; 10247 CC = ISD::SETLE; 10248 break; 10249 case Intrinsic::x86_sse_comigt_ss: 10250 case Intrinsic::x86_sse2_comigt_sd: 10251 Opc = X86ISD::COMI; 10252 CC = ISD::SETGT; 10253 break; 10254 case Intrinsic::x86_sse_comige_ss: 10255 case Intrinsic::x86_sse2_comige_sd: 10256 Opc = X86ISD::COMI; 10257 CC = ISD::SETGE; 10258 break; 10259 case Intrinsic::x86_sse_comineq_ss: 10260 case Intrinsic::x86_sse2_comineq_sd: 10261 Opc = X86ISD::COMI; 10262 CC = ISD::SETNE; 10263 break; 10264 case Intrinsic::x86_sse_ucomieq_ss: 10265 case Intrinsic::x86_sse2_ucomieq_sd: 10266 Opc = X86ISD::UCOMI; 10267 CC = ISD::SETEQ; 10268 break; 10269 case Intrinsic::x86_sse_ucomilt_ss: 10270 case Intrinsic::x86_sse2_ucomilt_sd: 10271 Opc = X86ISD::UCOMI; 10272 CC = ISD::SETLT; 10273 break; 10274 case Intrinsic::x86_sse_ucomile_ss: 10275 case Intrinsic::x86_sse2_ucomile_sd: 10276 Opc = X86ISD::UCOMI; 10277 CC = ISD::SETLE; 10278 break; 10279 case Intrinsic::x86_sse_ucomigt_ss: 10280 case Intrinsic::x86_sse2_ucomigt_sd: 10281 Opc = X86ISD::UCOMI; 10282 CC = ISD::SETGT; 10283 break; 10284 case Intrinsic::x86_sse_ucomige_ss: 10285 case Intrinsic::x86_sse2_ucomige_sd: 10286 Opc = X86ISD::UCOMI; 10287 CC = ISD::SETGE; 10288 break; 10289 case Intrinsic::x86_sse_ucomineq_ss: 10290 case Intrinsic::x86_sse2_ucomineq_sd: 10291 Opc = X86ISD::UCOMI; 10292 CC = ISD::SETNE; 10293 break; 10294 } 10295 10296 SDValue LHS = Op.getOperand(1); 10297 SDValue RHS = Op.getOperand(2); 10298 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 10299 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 10300 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 10301 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10302 DAG.getConstant(X86CC, MVT::i8), Cond); 10303 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10304 } 10305 10306 // Arithmetic intrinsics. 10307 case Intrinsic::x86_sse2_pmulu_dq: 10308 case Intrinsic::x86_avx2_pmulu_dq: 10309 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 10310 Op.getOperand(1), Op.getOperand(2)); 10311 10312 // SSE2/AVX2 sub with unsigned saturation intrinsics 10313 case Intrinsic::x86_sse2_psubus_b: 10314 case Intrinsic::x86_sse2_psubus_w: 10315 case Intrinsic::x86_avx2_psubus_b: 10316 case Intrinsic::x86_avx2_psubus_w: 10317 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(), 10318 Op.getOperand(1), Op.getOperand(2)); 10319 10320 // SSE3/AVX horizontal add/sub intrinsics 10321 case Intrinsic::x86_sse3_hadd_ps: 10322 case Intrinsic::x86_sse3_hadd_pd: 10323 case Intrinsic::x86_avx_hadd_ps_256: 10324 case Intrinsic::x86_avx_hadd_pd_256: 10325 case Intrinsic::x86_sse3_hsub_ps: 10326 case Intrinsic::x86_sse3_hsub_pd: 10327 case Intrinsic::x86_avx_hsub_ps_256: 10328 case Intrinsic::x86_avx_hsub_pd_256: 10329 case Intrinsic::x86_ssse3_phadd_w_128: 10330 case Intrinsic::x86_ssse3_phadd_d_128: 10331 case Intrinsic::x86_avx2_phadd_w: 10332 case Intrinsic::x86_avx2_phadd_d: 10333 case Intrinsic::x86_ssse3_phsub_w_128: 10334 case Intrinsic::x86_ssse3_phsub_d_128: 10335 case Intrinsic::x86_avx2_phsub_w: 10336 case Intrinsic::x86_avx2_phsub_d: { 10337 unsigned Opcode; 10338 switch (IntNo) { 10339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10340 case Intrinsic::x86_sse3_hadd_ps: 10341 case Intrinsic::x86_sse3_hadd_pd: 10342 case Intrinsic::x86_avx_hadd_ps_256: 10343 case Intrinsic::x86_avx_hadd_pd_256: 10344 Opcode = X86ISD::FHADD; 10345 break; 10346 case Intrinsic::x86_sse3_hsub_ps: 10347 case Intrinsic::x86_sse3_hsub_pd: 10348 case Intrinsic::x86_avx_hsub_ps_256: 10349 case Intrinsic::x86_avx_hsub_pd_256: 10350 Opcode = X86ISD::FHSUB; 10351 break; 10352 case Intrinsic::x86_ssse3_phadd_w_128: 10353 case Intrinsic::x86_ssse3_phadd_d_128: 10354 case Intrinsic::x86_avx2_phadd_w: 10355 case Intrinsic::x86_avx2_phadd_d: 10356 Opcode = X86ISD::HADD; 10357 break; 10358 case Intrinsic::x86_ssse3_phsub_w_128: 10359 case Intrinsic::x86_ssse3_phsub_d_128: 10360 case Intrinsic::x86_avx2_phsub_w: 10361 case Intrinsic::x86_avx2_phsub_d: 10362 Opcode = X86ISD::HSUB; 10363 break; 10364 } 10365 return DAG.getNode(Opcode, dl, Op.getValueType(), 10366 Op.getOperand(1), Op.getOperand(2)); 10367 } 10368 10369 // SSE2/SSE41/AVX2 integer max/min intrinsics. 10370 case Intrinsic::x86_sse2_pmaxu_b: 10371 case Intrinsic::x86_sse41_pmaxuw: 10372 case Intrinsic::x86_sse41_pmaxud: 10373 case Intrinsic::x86_avx2_pmaxu_b: 10374 case Intrinsic::x86_avx2_pmaxu_w: 10375 case Intrinsic::x86_avx2_pmaxu_d: 10376 case Intrinsic::x86_sse2_pminu_b: 10377 case Intrinsic::x86_sse41_pminuw: 10378 case Intrinsic::x86_sse41_pminud: 10379 case Intrinsic::x86_avx2_pminu_b: 10380 case Intrinsic::x86_avx2_pminu_w: 10381 case Intrinsic::x86_avx2_pminu_d: 10382 case Intrinsic::x86_sse41_pmaxsb: 10383 case Intrinsic::x86_sse2_pmaxs_w: 10384 case Intrinsic::x86_sse41_pmaxsd: 10385 case Intrinsic::x86_avx2_pmaxs_b: 10386 case Intrinsic::x86_avx2_pmaxs_w: 10387 case Intrinsic::x86_avx2_pmaxs_d: 10388 case Intrinsic::x86_sse41_pminsb: 10389 case Intrinsic::x86_sse2_pmins_w: 10390 case Intrinsic::x86_sse41_pminsd: 10391 case Intrinsic::x86_avx2_pmins_b: 10392 case Intrinsic::x86_avx2_pmins_w: 10393 case Intrinsic::x86_avx2_pmins_d: { 10394 unsigned Opcode; 10395 switch (IntNo) { 10396 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10397 case Intrinsic::x86_sse2_pmaxu_b: 10398 case Intrinsic::x86_sse41_pmaxuw: 10399 case Intrinsic::x86_sse41_pmaxud: 10400 case Intrinsic::x86_avx2_pmaxu_b: 10401 case Intrinsic::x86_avx2_pmaxu_w: 10402 case Intrinsic::x86_avx2_pmaxu_d: 10403 Opcode = X86ISD::UMAX; 10404 break; 10405 case Intrinsic::x86_sse2_pminu_b: 10406 case Intrinsic::x86_sse41_pminuw: 10407 case Intrinsic::x86_sse41_pminud: 10408 case Intrinsic::x86_avx2_pminu_b: 10409 case Intrinsic::x86_avx2_pminu_w: 10410 case Intrinsic::x86_avx2_pminu_d: 10411 Opcode = X86ISD::UMIN; 10412 break; 10413 case Intrinsic::x86_sse41_pmaxsb: 10414 case Intrinsic::x86_sse2_pmaxs_w: 10415 case Intrinsic::x86_sse41_pmaxsd: 10416 case Intrinsic::x86_avx2_pmaxs_b: 10417 case Intrinsic::x86_avx2_pmaxs_w: 10418 case Intrinsic::x86_avx2_pmaxs_d: 10419 Opcode = X86ISD::SMAX; 10420 break; 10421 case Intrinsic::x86_sse41_pminsb: 10422 case Intrinsic::x86_sse2_pmins_w: 10423 case Intrinsic::x86_sse41_pminsd: 10424 case Intrinsic::x86_avx2_pmins_b: 10425 case Intrinsic::x86_avx2_pmins_w: 10426 case Intrinsic::x86_avx2_pmins_d: 10427 Opcode = X86ISD::SMIN; 10428 break; 10429 } 10430 return DAG.getNode(Opcode, dl, Op.getValueType(), 10431 Op.getOperand(1), Op.getOperand(2)); 10432 } 10433 10434 // SSE/SSE2/AVX floating point max/min intrinsics. 10435 case Intrinsic::x86_sse_max_ps: 10436 case Intrinsic::x86_sse2_max_pd: 10437 case Intrinsic::x86_avx_max_ps_256: 10438 case Intrinsic::x86_avx_max_pd_256: 10439 case Intrinsic::x86_sse_min_ps: 10440 case Intrinsic::x86_sse2_min_pd: 10441 case Intrinsic::x86_avx_min_ps_256: 10442 case Intrinsic::x86_avx_min_pd_256: { 10443 unsigned Opcode; 10444 switch (IntNo) { 10445 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10446 case Intrinsic::x86_sse_max_ps: 10447 case Intrinsic::x86_sse2_max_pd: 10448 case Intrinsic::x86_avx_max_ps_256: 10449 case Intrinsic::x86_avx_max_pd_256: 10450 Opcode = X86ISD::FMAX; 10451 break; 10452 case Intrinsic::x86_sse_min_ps: 10453 case Intrinsic::x86_sse2_min_pd: 10454 case Intrinsic::x86_avx_min_ps_256: 10455 case Intrinsic::x86_avx_min_pd_256: 10456 Opcode = X86ISD::FMIN; 10457 break; 10458 } 10459 return DAG.getNode(Opcode, dl, Op.getValueType(), 10460 Op.getOperand(1), Op.getOperand(2)); 10461 } 10462 10463 // AVX2 variable shift intrinsics 10464 case Intrinsic::x86_avx2_psllv_d: 10465 case Intrinsic::x86_avx2_psllv_q: 10466 case Intrinsic::x86_avx2_psllv_d_256: 10467 case Intrinsic::x86_avx2_psllv_q_256: 10468 case Intrinsic::x86_avx2_psrlv_d: 10469 case Intrinsic::x86_avx2_psrlv_q: 10470 case Intrinsic::x86_avx2_psrlv_d_256: 10471 case Intrinsic::x86_avx2_psrlv_q_256: 10472 case Intrinsic::x86_avx2_psrav_d: 10473 case Intrinsic::x86_avx2_psrav_d_256: { 10474 unsigned Opcode; 10475 switch (IntNo) { 10476 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10477 case Intrinsic::x86_avx2_psllv_d: 10478 case Intrinsic::x86_avx2_psllv_q: 10479 case Intrinsic::x86_avx2_psllv_d_256: 10480 case Intrinsic::x86_avx2_psllv_q_256: 10481 Opcode = ISD::SHL; 10482 break; 10483 case Intrinsic::x86_avx2_psrlv_d: 10484 case Intrinsic::x86_avx2_psrlv_q: 10485 case Intrinsic::x86_avx2_psrlv_d_256: 10486 case Intrinsic::x86_avx2_psrlv_q_256: 10487 Opcode = ISD::SRL; 10488 break; 10489 case Intrinsic::x86_avx2_psrav_d: 10490 case Intrinsic::x86_avx2_psrav_d_256: 10491 Opcode = ISD::SRA; 10492 break; 10493 } 10494 return DAG.getNode(Opcode, dl, Op.getValueType(), 10495 Op.getOperand(1), Op.getOperand(2)); 10496 } 10497 10498 case Intrinsic::x86_ssse3_pshuf_b_128: 10499 case Intrinsic::x86_avx2_pshuf_b: 10500 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 10501 Op.getOperand(1), Op.getOperand(2)); 10502 10503 case Intrinsic::x86_ssse3_psign_b_128: 10504 case Intrinsic::x86_ssse3_psign_w_128: 10505 case Intrinsic::x86_ssse3_psign_d_128: 10506 case Intrinsic::x86_avx2_psign_b: 10507 case Intrinsic::x86_avx2_psign_w: 10508 case Intrinsic::x86_avx2_psign_d: 10509 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 10510 Op.getOperand(1), Op.getOperand(2)); 10511 10512 case Intrinsic::x86_sse41_insertps: 10513 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 10514 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 10515 10516 case Intrinsic::x86_avx_vperm2f128_ps_256: 10517 case Intrinsic::x86_avx_vperm2f128_pd_256: 10518 case Intrinsic::x86_avx_vperm2f128_si_256: 10519 case Intrinsic::x86_avx2_vperm2i128: 10520 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 10521 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 10522 10523 case Intrinsic::x86_avx2_permd: 10524 case Intrinsic::x86_avx2_permps: 10525 // Operands intentionally swapped. Mask is last operand to intrinsic, 10526 // but second operand for node/intruction. 10527 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 10528 Op.getOperand(2), Op.getOperand(1)); 10529 10530 case Intrinsic::x86_sse_sqrt_ps: 10531 case Intrinsic::x86_sse2_sqrt_pd: 10532 case Intrinsic::x86_avx_sqrt_ps_256: 10533 case Intrinsic::x86_avx_sqrt_pd_256: 10534 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1)); 10535 10536 // ptest and testp intrinsics. The intrinsic these come from are designed to 10537 // return an integer value, not just an instruction so lower it to the ptest 10538 // or testp pattern and a setcc for the result. 10539 case Intrinsic::x86_sse41_ptestz: 10540 case Intrinsic::x86_sse41_ptestc: 10541 case Intrinsic::x86_sse41_ptestnzc: 10542 case Intrinsic::x86_avx_ptestz_256: 10543 case Intrinsic::x86_avx_ptestc_256: 10544 case Intrinsic::x86_avx_ptestnzc_256: 10545 case Intrinsic::x86_avx_vtestz_ps: 10546 case Intrinsic::x86_avx_vtestc_ps: 10547 case Intrinsic::x86_avx_vtestnzc_ps: 10548 case Intrinsic::x86_avx_vtestz_pd: 10549 case Intrinsic::x86_avx_vtestc_pd: 10550 case Intrinsic::x86_avx_vtestnzc_pd: 10551 case Intrinsic::x86_avx_vtestz_ps_256: 10552 case Intrinsic::x86_avx_vtestc_ps_256: 10553 case Intrinsic::x86_avx_vtestnzc_ps_256: 10554 case Intrinsic::x86_avx_vtestz_pd_256: 10555 case Intrinsic::x86_avx_vtestc_pd_256: 10556 case Intrinsic::x86_avx_vtestnzc_pd_256: { 10557 bool IsTestPacked = false; 10558 unsigned X86CC; 10559 switch (IntNo) { 10560 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 10561 case Intrinsic::x86_avx_vtestz_ps: 10562 case Intrinsic::x86_avx_vtestz_pd: 10563 case Intrinsic::x86_avx_vtestz_ps_256: 10564 case Intrinsic::x86_avx_vtestz_pd_256: 10565 IsTestPacked = true; // Fallthrough 10566 case Intrinsic::x86_sse41_ptestz: 10567 case Intrinsic::x86_avx_ptestz_256: 10568 // ZF = 1 10569 X86CC = X86::COND_E; 10570 break; 10571 case Intrinsic::x86_avx_vtestc_ps: 10572 case Intrinsic::x86_avx_vtestc_pd: 10573 case Intrinsic::x86_avx_vtestc_ps_256: 10574 case Intrinsic::x86_avx_vtestc_pd_256: 10575 IsTestPacked = true; // Fallthrough 10576 case Intrinsic::x86_sse41_ptestc: 10577 case Intrinsic::x86_avx_ptestc_256: 10578 // CF = 1 10579 X86CC = X86::COND_B; 10580 break; 10581 case Intrinsic::x86_avx_vtestnzc_ps: 10582 case Intrinsic::x86_avx_vtestnzc_pd: 10583 case Intrinsic::x86_avx_vtestnzc_ps_256: 10584 case Intrinsic::x86_avx_vtestnzc_pd_256: 10585 IsTestPacked = true; // Fallthrough 10586 case Intrinsic::x86_sse41_ptestnzc: 10587 case Intrinsic::x86_avx_ptestnzc_256: 10588 // ZF and CF = 0 10589 X86CC = X86::COND_A; 10590 break; 10591 } 10592 10593 SDValue LHS = Op.getOperand(1); 10594 SDValue RHS = Op.getOperand(2); 10595 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 10596 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 10597 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 10598 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 10599 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10600 } 10601 10602 // SSE/AVX shift intrinsics 10603 case Intrinsic::x86_sse2_psll_w: 10604 case Intrinsic::x86_sse2_psll_d: 10605 case Intrinsic::x86_sse2_psll_q: 10606 case Intrinsic::x86_avx2_psll_w: 10607 case Intrinsic::x86_avx2_psll_d: 10608 case Intrinsic::x86_avx2_psll_q: 10609 case Intrinsic::x86_sse2_psrl_w: 10610 case Intrinsic::x86_sse2_psrl_d: 10611 case Intrinsic::x86_sse2_psrl_q: 10612 case Intrinsic::x86_avx2_psrl_w: 10613 case Intrinsic::x86_avx2_psrl_d: 10614 case Intrinsic::x86_avx2_psrl_q: 10615 case Intrinsic::x86_sse2_psra_w: 10616 case Intrinsic::x86_sse2_psra_d: 10617 case Intrinsic::x86_avx2_psra_w: 10618 case Intrinsic::x86_avx2_psra_d: { 10619 unsigned Opcode; 10620 switch (IntNo) { 10621 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10622 case Intrinsic::x86_sse2_psll_w: 10623 case Intrinsic::x86_sse2_psll_d: 10624 case Intrinsic::x86_sse2_psll_q: 10625 case Intrinsic::x86_avx2_psll_w: 10626 case Intrinsic::x86_avx2_psll_d: 10627 case Intrinsic::x86_avx2_psll_q: 10628 Opcode = X86ISD::VSHL; 10629 break; 10630 case Intrinsic::x86_sse2_psrl_w: 10631 case Intrinsic::x86_sse2_psrl_d: 10632 case Intrinsic::x86_sse2_psrl_q: 10633 case Intrinsic::x86_avx2_psrl_w: 10634 case Intrinsic::x86_avx2_psrl_d: 10635 case Intrinsic::x86_avx2_psrl_q: 10636 Opcode = X86ISD::VSRL; 10637 break; 10638 case Intrinsic::x86_sse2_psra_w: 10639 case Intrinsic::x86_sse2_psra_d: 10640 case Intrinsic::x86_avx2_psra_w: 10641 case Intrinsic::x86_avx2_psra_d: 10642 Opcode = X86ISD::VSRA; 10643 break; 10644 } 10645 return DAG.getNode(Opcode, dl, Op.getValueType(), 10646 Op.getOperand(1), Op.getOperand(2)); 10647 } 10648 10649 // SSE/AVX immediate shift intrinsics 10650 case Intrinsic::x86_sse2_pslli_w: 10651 case Intrinsic::x86_sse2_pslli_d: 10652 case Intrinsic::x86_sse2_pslli_q: 10653 case Intrinsic::x86_avx2_pslli_w: 10654 case Intrinsic::x86_avx2_pslli_d: 10655 case Intrinsic::x86_avx2_pslli_q: 10656 case Intrinsic::x86_sse2_psrli_w: 10657 case Intrinsic::x86_sse2_psrli_d: 10658 case Intrinsic::x86_sse2_psrli_q: 10659 case Intrinsic::x86_avx2_psrli_w: 10660 case Intrinsic::x86_avx2_psrli_d: 10661 case Intrinsic::x86_avx2_psrli_q: 10662 case Intrinsic::x86_sse2_psrai_w: 10663 case Intrinsic::x86_sse2_psrai_d: 10664 case Intrinsic::x86_avx2_psrai_w: 10665 case Intrinsic::x86_avx2_psrai_d: { 10666 unsigned Opcode; 10667 switch (IntNo) { 10668 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10669 case Intrinsic::x86_sse2_pslli_w: 10670 case Intrinsic::x86_sse2_pslli_d: 10671 case Intrinsic::x86_sse2_pslli_q: 10672 case Intrinsic::x86_avx2_pslli_w: 10673 case Intrinsic::x86_avx2_pslli_d: 10674 case Intrinsic::x86_avx2_pslli_q: 10675 Opcode = X86ISD::VSHLI; 10676 break; 10677 case Intrinsic::x86_sse2_psrli_w: 10678 case Intrinsic::x86_sse2_psrli_d: 10679 case Intrinsic::x86_sse2_psrli_q: 10680 case Intrinsic::x86_avx2_psrli_w: 10681 case Intrinsic::x86_avx2_psrli_d: 10682 case Intrinsic::x86_avx2_psrli_q: 10683 Opcode = X86ISD::VSRLI; 10684 break; 10685 case Intrinsic::x86_sse2_psrai_w: 10686 case Intrinsic::x86_sse2_psrai_d: 10687 case Intrinsic::x86_avx2_psrai_w: 10688 case Intrinsic::x86_avx2_psrai_d: 10689 Opcode = X86ISD::VSRAI; 10690 break; 10691 } 10692 return getTargetVShiftNode(Opcode, dl, Op.getValueType(), 10693 Op.getOperand(1), Op.getOperand(2), DAG); 10694 } 10695 10696 case Intrinsic::x86_sse42_pcmpistria128: 10697 case Intrinsic::x86_sse42_pcmpestria128: 10698 case Intrinsic::x86_sse42_pcmpistric128: 10699 case Intrinsic::x86_sse42_pcmpestric128: 10700 case Intrinsic::x86_sse42_pcmpistrio128: 10701 case Intrinsic::x86_sse42_pcmpestrio128: 10702 case Intrinsic::x86_sse42_pcmpistris128: 10703 case Intrinsic::x86_sse42_pcmpestris128: 10704 case Intrinsic::x86_sse42_pcmpistriz128: 10705 case Intrinsic::x86_sse42_pcmpestriz128: { 10706 unsigned Opcode; 10707 unsigned X86CC; 10708 switch (IntNo) { 10709 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10710 case Intrinsic::x86_sse42_pcmpistria128: 10711 Opcode = X86ISD::PCMPISTRI; 10712 X86CC = X86::COND_A; 10713 break; 10714 case Intrinsic::x86_sse42_pcmpestria128: 10715 Opcode = X86ISD::PCMPESTRI; 10716 X86CC = X86::COND_A; 10717 break; 10718 case Intrinsic::x86_sse42_pcmpistric128: 10719 Opcode = X86ISD::PCMPISTRI; 10720 X86CC = X86::COND_B; 10721 break; 10722 case Intrinsic::x86_sse42_pcmpestric128: 10723 Opcode = X86ISD::PCMPESTRI; 10724 X86CC = X86::COND_B; 10725 break; 10726 case Intrinsic::x86_sse42_pcmpistrio128: 10727 Opcode = X86ISD::PCMPISTRI; 10728 X86CC = X86::COND_O; 10729 break; 10730 case Intrinsic::x86_sse42_pcmpestrio128: 10731 Opcode = X86ISD::PCMPESTRI; 10732 X86CC = X86::COND_O; 10733 break; 10734 case Intrinsic::x86_sse42_pcmpistris128: 10735 Opcode = X86ISD::PCMPISTRI; 10736 X86CC = X86::COND_S; 10737 break; 10738 case Intrinsic::x86_sse42_pcmpestris128: 10739 Opcode = X86ISD::PCMPESTRI; 10740 X86CC = X86::COND_S; 10741 break; 10742 case Intrinsic::x86_sse42_pcmpistriz128: 10743 Opcode = X86ISD::PCMPISTRI; 10744 X86CC = X86::COND_E; 10745 break; 10746 case Intrinsic::x86_sse42_pcmpestriz128: 10747 Opcode = X86ISD::PCMPESTRI; 10748 X86CC = X86::COND_E; 10749 break; 10750 } 10751 SmallVector<SDValue, 5> NewOps; 10752 NewOps.append(Op->op_begin()+1, Op->op_end()); 10753 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 10754 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 10755 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 10756 DAG.getConstant(X86CC, MVT::i8), 10757 SDValue(PCMP.getNode(), 1)); 10758 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 10759 } 10760 10761 case Intrinsic::x86_sse42_pcmpistri128: 10762 case Intrinsic::x86_sse42_pcmpestri128: { 10763 unsigned Opcode; 10764 if (IntNo == Intrinsic::x86_sse42_pcmpistri128) 10765 Opcode = X86ISD::PCMPISTRI; 10766 else 10767 Opcode = X86ISD::PCMPESTRI; 10768 10769 SmallVector<SDValue, 5> NewOps; 10770 NewOps.append(Op->op_begin()+1, Op->op_end()); 10771 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 10772 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size()); 10773 } 10774 case Intrinsic::x86_fma_vfmadd_ps: 10775 case Intrinsic::x86_fma_vfmadd_pd: 10776 case Intrinsic::x86_fma_vfmsub_ps: 10777 case Intrinsic::x86_fma_vfmsub_pd: 10778 case Intrinsic::x86_fma_vfnmadd_ps: 10779 case Intrinsic::x86_fma_vfnmadd_pd: 10780 case Intrinsic::x86_fma_vfnmsub_ps: 10781 case Intrinsic::x86_fma_vfnmsub_pd: 10782 case Intrinsic::x86_fma_vfmaddsub_ps: 10783 case Intrinsic::x86_fma_vfmaddsub_pd: 10784 case Intrinsic::x86_fma_vfmsubadd_ps: 10785 case Intrinsic::x86_fma_vfmsubadd_pd: 10786 case Intrinsic::x86_fma_vfmadd_ps_256: 10787 case Intrinsic::x86_fma_vfmadd_pd_256: 10788 case Intrinsic::x86_fma_vfmsub_ps_256: 10789 case Intrinsic::x86_fma_vfmsub_pd_256: 10790 case Intrinsic::x86_fma_vfnmadd_ps_256: 10791 case Intrinsic::x86_fma_vfnmadd_pd_256: 10792 case Intrinsic::x86_fma_vfnmsub_ps_256: 10793 case Intrinsic::x86_fma_vfnmsub_pd_256: 10794 case Intrinsic::x86_fma_vfmaddsub_ps_256: 10795 case Intrinsic::x86_fma_vfmaddsub_pd_256: 10796 case Intrinsic::x86_fma_vfmsubadd_ps_256: 10797 case Intrinsic::x86_fma_vfmsubadd_pd_256: { 10798 unsigned Opc; 10799 switch (IntNo) { 10800 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 10801 case Intrinsic::x86_fma_vfmadd_ps: 10802 case Intrinsic::x86_fma_vfmadd_pd: 10803 case Intrinsic::x86_fma_vfmadd_ps_256: 10804 case Intrinsic::x86_fma_vfmadd_pd_256: 10805 Opc = X86ISD::FMADD; 10806 break; 10807 case Intrinsic::x86_fma_vfmsub_ps: 10808 case Intrinsic::x86_fma_vfmsub_pd: 10809 case Intrinsic::x86_fma_vfmsub_ps_256: 10810 case Intrinsic::x86_fma_vfmsub_pd_256: 10811 Opc = X86ISD::FMSUB; 10812 break; 10813 case Intrinsic::x86_fma_vfnmadd_ps: 10814 case Intrinsic::x86_fma_vfnmadd_pd: 10815 case Intrinsic::x86_fma_vfnmadd_ps_256: 10816 case Intrinsic::x86_fma_vfnmadd_pd_256: 10817 Opc = X86ISD::FNMADD; 10818 break; 10819 case Intrinsic::x86_fma_vfnmsub_ps: 10820 case Intrinsic::x86_fma_vfnmsub_pd: 10821 case Intrinsic::x86_fma_vfnmsub_ps_256: 10822 case Intrinsic::x86_fma_vfnmsub_pd_256: 10823 Opc = X86ISD::FNMSUB; 10824 break; 10825 case Intrinsic::x86_fma_vfmaddsub_ps: 10826 case Intrinsic::x86_fma_vfmaddsub_pd: 10827 case Intrinsic::x86_fma_vfmaddsub_ps_256: 10828 case Intrinsic::x86_fma_vfmaddsub_pd_256: 10829 Opc = X86ISD::FMADDSUB; 10830 break; 10831 case Intrinsic::x86_fma_vfmsubadd_ps: 10832 case Intrinsic::x86_fma_vfmsubadd_pd: 10833 case Intrinsic::x86_fma_vfmsubadd_ps_256: 10834 case Intrinsic::x86_fma_vfmsubadd_pd_256: 10835 Opc = X86ISD::FMSUBADD; 10836 break; 10837 } 10838 10839 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1), 10840 Op.getOperand(2), Op.getOperand(3)); 10841 } 10842 } 10843} 10844 10845static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) { 10846 DebugLoc dl = Op.getDebugLoc(); 10847 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10848 switch (IntNo) { 10849 default: return SDValue(); // Don't custom lower most intrinsics. 10850 10851 // RDRAND intrinsics. 10852 case Intrinsic::x86_rdrand_16: 10853 case Intrinsic::x86_rdrand_32: 10854 case Intrinsic::x86_rdrand_64: { 10855 // Emit the node with the right value type. 10856 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other); 10857 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0)); 10858 10859 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise 10860 // return the value from Rand, which is always 0, casted to i32. 10861 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)), 10862 DAG.getConstant(1, Op->getValueType(1)), 10863 DAG.getConstant(X86::COND_B, MVT::i32), 10864 SDValue(Result.getNode(), 1) }; 10865 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, 10866 DAG.getVTList(Op->getValueType(1), MVT::Glue), 10867 Ops, 4); 10868 10869 // Return { result, isValid, chain }. 10870 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid, 10871 SDValue(Result.getNode(), 2)); 10872 } 10873 } 10874} 10875 10876SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 10877 SelectionDAG &DAG) const { 10878 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10879 MFI->setReturnAddressIsTaken(true); 10880 10881 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10882 DebugLoc dl = Op.getDebugLoc(); 10883 EVT PtrVT = getPointerTy(); 10884 10885 if (Depth > 0) { 10886 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 10887 SDValue Offset = 10888 DAG.getConstant(RegInfo->getSlotSize(), PtrVT); 10889 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 10890 DAG.getNode(ISD::ADD, dl, PtrVT, 10891 FrameAddr, Offset), 10892 MachinePointerInfo(), false, false, false, 0); 10893 } 10894 10895 // Just load the return address. 10896 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 10897 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 10898 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 10899} 10900 10901SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 10902 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10903 MFI->setFrameAddressIsTaken(true); 10904 10905 EVT VT = Op.getValueType(); 10906 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 10907 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 10908 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 10909 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 10910 while (Depth--) 10911 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 10912 MachinePointerInfo(), 10913 false, false, false, 0); 10914 return FrameAddr; 10915} 10916 10917SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 10918 SelectionDAG &DAG) const { 10919 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize()); 10920} 10921 10922SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 10923 SDValue Chain = Op.getOperand(0); 10924 SDValue Offset = Op.getOperand(1); 10925 SDValue Handler = Op.getOperand(2); 10926 DebugLoc dl = Op.getDebugLoc(); 10927 10928 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 10929 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 10930 getPointerTy()); 10931 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 10932 10933 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 10934 DAG.getIntPtrConstant(RegInfo->getSlotSize())); 10935 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 10936 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 10937 false, false, 0); 10938 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 10939 10940 return DAG.getNode(X86ISD::EH_RETURN, dl, 10941 MVT::Other, 10942 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 10943} 10944 10945SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op, 10946 SelectionDAG &DAG) const { 10947 DebugLoc DL = Op.getDebugLoc(); 10948 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL, 10949 DAG.getVTList(MVT::i32, MVT::Other), 10950 Op.getOperand(0), Op.getOperand(1)); 10951} 10952 10953SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op, 10954 SelectionDAG &DAG) const { 10955 DebugLoc DL = Op.getDebugLoc(); 10956 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other, 10957 Op.getOperand(0), Op.getOperand(1)); 10958} 10959 10960static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) { 10961 return Op.getOperand(0); 10962} 10963 10964SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 10965 SelectionDAG &DAG) const { 10966 SDValue Root = Op.getOperand(0); 10967 SDValue Trmp = Op.getOperand(1); // trampoline 10968 SDValue FPtr = Op.getOperand(2); // nested function 10969 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 10970 DebugLoc dl = Op.getDebugLoc(); 10971 10972 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 10973 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 10974 10975 if (Subtarget->is64Bit()) { 10976 SDValue OutChains[6]; 10977 10978 // Large code-model. 10979 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 10980 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 10981 10982 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7; 10983 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7; 10984 10985 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 10986 10987 // Load the pointer to the nested function into R11. 10988 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 10989 SDValue Addr = Trmp; 10990 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10991 Addr, MachinePointerInfo(TrmpAddr), 10992 false, false, 0); 10993 10994 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10995 DAG.getConstant(2, MVT::i64)); 10996 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 10997 MachinePointerInfo(TrmpAddr, 2), 10998 false, false, 2); 10999 11000 // Load the 'nest' parameter value into R10. 11001 // R10 is specified in X86CallingConv.td 11002 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 11003 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11004 DAG.getConstant(10, MVT::i64)); 11005 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 11006 Addr, MachinePointerInfo(TrmpAddr, 10), 11007 false, false, 0); 11008 11009 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11010 DAG.getConstant(12, MVT::i64)); 11011 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 11012 MachinePointerInfo(TrmpAddr, 12), 11013 false, false, 2); 11014 11015 // Jump to the nested function. 11016 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 11017 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11018 DAG.getConstant(20, MVT::i64)); 11019 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 11020 Addr, MachinePointerInfo(TrmpAddr, 20), 11021 false, false, 0); 11022 11023 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 11024 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 11025 DAG.getConstant(22, MVT::i64)); 11026 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 11027 MachinePointerInfo(TrmpAddr, 22), 11028 false, false, 0); 11029 11030 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 11031 } else { 11032 const Function *Func = 11033 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 11034 CallingConv::ID CC = Func->getCallingConv(); 11035 unsigned NestReg; 11036 11037 switch (CC) { 11038 default: 11039 llvm_unreachable("Unsupported calling convention"); 11040 case CallingConv::C: 11041 case CallingConv::X86_StdCall: { 11042 // Pass 'nest' parameter in ECX. 11043 // Must be kept in sync with X86CallingConv.td 11044 NestReg = X86::ECX; 11045 11046 // Check that ECX wasn't needed by an 'inreg' parameter. 11047 FunctionType *FTy = Func->getFunctionType(); 11048 const AttributeSet &Attrs = Func->getAttributes(); 11049 11050 if (!Attrs.isEmpty() && !Func->isVarArg()) { 11051 unsigned InRegCount = 0; 11052 unsigned Idx = 1; 11053 11054 for (FunctionType::param_iterator I = FTy->param_begin(), 11055 E = FTy->param_end(); I != E; ++I, ++Idx) 11056 if (Attrs.hasAttribute(Idx, Attribute::InReg)) 11057 // FIXME: should only count parameters that are lowered to integers. 11058 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 11059 11060 if (InRegCount > 2) { 11061 report_fatal_error("Nest register in use - reduce number of inreg" 11062 " parameters!"); 11063 } 11064 } 11065 break; 11066 } 11067 case CallingConv::X86_FastCall: 11068 case CallingConv::X86_ThisCall: 11069 case CallingConv::Fast: 11070 // Pass 'nest' parameter in EAX. 11071 // Must be kept in sync with X86CallingConv.td 11072 NestReg = X86::EAX; 11073 break; 11074 } 11075 11076 SDValue OutChains[4]; 11077 SDValue Addr, Disp; 11078 11079 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11080 DAG.getConstant(10, MVT::i32)); 11081 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 11082 11083 // This is storing the opcode for MOV32ri. 11084 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 11085 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7; 11086 OutChains[0] = DAG.getStore(Root, dl, 11087 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 11088 Trmp, MachinePointerInfo(TrmpAddr), 11089 false, false, 0); 11090 11091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11092 DAG.getConstant(1, MVT::i32)); 11093 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 11094 MachinePointerInfo(TrmpAddr, 1), 11095 false, false, 1); 11096 11097 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 11098 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11099 DAG.getConstant(5, MVT::i32)); 11100 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 11101 MachinePointerInfo(TrmpAddr, 5), 11102 false, false, 1); 11103 11104 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 11105 DAG.getConstant(6, MVT::i32)); 11106 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 11107 MachinePointerInfo(TrmpAddr, 6), 11108 false, false, 1); 11109 11110 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 11111 } 11112} 11113 11114SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 11115 SelectionDAG &DAG) const { 11116 /* 11117 The rounding mode is in bits 11:10 of FPSR, and has the following 11118 settings: 11119 00 Round to nearest 11120 01 Round to -inf 11121 10 Round to +inf 11122 11 Round to 0 11123 11124 FLT_ROUNDS, on the other hand, expects the following: 11125 -1 Undefined 11126 0 Round to 0 11127 1 Round to nearest 11128 2 Round to +inf 11129 3 Round to -inf 11130 11131 To perform the conversion, we do: 11132 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 11133 */ 11134 11135 MachineFunction &MF = DAG.getMachineFunction(); 11136 const TargetMachine &TM = MF.getTarget(); 11137 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 11138 unsigned StackAlignment = TFI.getStackAlignment(); 11139 EVT VT = Op.getValueType(); 11140 DebugLoc DL = Op.getDebugLoc(); 11141 11142 // Save FP Control Word to stack slot 11143 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 11144 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 11145 11146 MachineMemOperand *MMO = 11147 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 11148 MachineMemOperand::MOStore, 2, 2); 11149 11150 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 11151 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 11152 DAG.getVTList(MVT::Other), 11153 Ops, 2, MVT::i16, MMO); 11154 11155 // Load FP Control Word from stack slot 11156 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 11157 MachinePointerInfo(), false, false, false, 0); 11158 11159 // Transform as necessary 11160 SDValue CWD1 = 11161 DAG.getNode(ISD::SRL, DL, MVT::i16, 11162 DAG.getNode(ISD::AND, DL, MVT::i16, 11163 CWD, DAG.getConstant(0x800, MVT::i16)), 11164 DAG.getConstant(11, MVT::i8)); 11165 SDValue CWD2 = 11166 DAG.getNode(ISD::SRL, DL, MVT::i16, 11167 DAG.getNode(ISD::AND, DL, MVT::i16, 11168 CWD, DAG.getConstant(0x400, MVT::i16)), 11169 DAG.getConstant(9, MVT::i8)); 11170 11171 SDValue RetVal = 11172 DAG.getNode(ISD::AND, DL, MVT::i16, 11173 DAG.getNode(ISD::ADD, DL, MVT::i16, 11174 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 11175 DAG.getConstant(1, MVT::i16)), 11176 DAG.getConstant(3, MVT::i16)); 11177 11178 return DAG.getNode((VT.getSizeInBits() < 16 ? 11179 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 11180} 11181 11182static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 11183 EVT VT = Op.getValueType(); 11184 EVT OpVT = VT; 11185 unsigned NumBits = VT.getSizeInBits(); 11186 DebugLoc dl = Op.getDebugLoc(); 11187 11188 Op = Op.getOperand(0); 11189 if (VT == MVT::i8) { 11190 // Zero extend to i32 since there is not an i8 bsr. 11191 OpVT = MVT::i32; 11192 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 11193 } 11194 11195 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 11196 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 11197 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 11198 11199 // If src is zero (i.e. bsr sets ZF), returns NumBits. 11200 SDValue Ops[] = { 11201 Op, 11202 DAG.getConstant(NumBits+NumBits-1, OpVT), 11203 DAG.getConstant(X86::COND_E, MVT::i8), 11204 Op.getValue(1) 11205 }; 11206 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 11207 11208 // Finally xor with NumBits-1. 11209 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 11210 11211 if (VT == MVT::i8) 11212 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 11213 return Op; 11214} 11215 11216static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) { 11217 EVT VT = Op.getValueType(); 11218 EVT OpVT = VT; 11219 unsigned NumBits = VT.getSizeInBits(); 11220 DebugLoc dl = Op.getDebugLoc(); 11221 11222 Op = Op.getOperand(0); 11223 if (VT == MVT::i8) { 11224 // Zero extend to i32 since there is not an i8 bsr. 11225 OpVT = MVT::i32; 11226 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 11227 } 11228 11229 // Issue a bsr (scan bits in reverse). 11230 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 11231 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 11232 11233 // And xor with NumBits-1. 11234 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 11235 11236 if (VT == MVT::i8) 11237 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 11238 return Op; 11239} 11240 11241static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 11242 EVT VT = Op.getValueType(); 11243 unsigned NumBits = VT.getSizeInBits(); 11244 DebugLoc dl = Op.getDebugLoc(); 11245 Op = Op.getOperand(0); 11246 11247 // Issue a bsf (scan bits forward) which also sets EFLAGS. 11248 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 11249 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 11250 11251 // If src is zero (i.e. bsf sets ZF), returns NumBits. 11252 SDValue Ops[] = { 11253 Op, 11254 DAG.getConstant(NumBits, VT), 11255 DAG.getConstant(X86::COND_E, MVT::i8), 11256 Op.getValue(1) 11257 }; 11258 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 11259} 11260 11261// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 11262// ones, and then concatenate the result back. 11263static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 11264 EVT VT = Op.getValueType(); 11265 11266 assert(VT.is256BitVector() && VT.isInteger() && 11267 "Unsupported value type for operation"); 11268 11269 unsigned NumElems = VT.getVectorNumElements(); 11270 DebugLoc dl = Op.getDebugLoc(); 11271 11272 // Extract the LHS vectors 11273 SDValue LHS = Op.getOperand(0); 11274 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 11275 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 11276 11277 // Extract the RHS vectors 11278 SDValue RHS = Op.getOperand(1); 11279 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 11280 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 11281 11282 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 11283 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 11284 11285 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 11286 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 11287 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 11288} 11289 11290static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) { 11291 assert(Op.getValueType().is256BitVector() && 11292 Op.getValueType().isInteger() && 11293 "Only handle AVX 256-bit vector integer operation"); 11294 return Lower256IntArith(Op, DAG); 11295} 11296 11297static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) { 11298 assert(Op.getValueType().is256BitVector() && 11299 Op.getValueType().isInteger() && 11300 "Only handle AVX 256-bit vector integer operation"); 11301 return Lower256IntArith(Op, DAG); 11302} 11303 11304static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget, 11305 SelectionDAG &DAG) { 11306 DebugLoc dl = Op.getDebugLoc(); 11307 EVT VT = Op.getValueType(); 11308 11309 // Decompose 256-bit ops into smaller 128-bit ops. 11310 if (VT.is256BitVector() && !Subtarget->hasInt256()) 11311 return Lower256IntArith(Op, DAG); 11312 11313 SDValue A = Op.getOperand(0); 11314 SDValue B = Op.getOperand(1); 11315 11316 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle. 11317 if (VT == MVT::v4i32) { 11318 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() && 11319 "Should not custom lower when pmuldq is available!"); 11320 11321 // Extract the odd parts. 11322 const int UnpackMask[] = { 1, -1, 3, -1 }; 11323 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask); 11324 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask); 11325 11326 // Multiply the even parts. 11327 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B); 11328 // Now multiply odd parts. 11329 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds); 11330 11331 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens); 11332 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds); 11333 11334 // Merge the two vectors back together with a shuffle. This expands into 2 11335 // shuffles. 11336 const int ShufMask[] = { 0, 4, 2, 6 }; 11337 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask); 11338 } 11339 11340 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 11341 "Only know how to lower V2I64/V4I64 multiply"); 11342 11343 // Ahi = psrlqi(a, 32); 11344 // Bhi = psrlqi(b, 32); 11345 // 11346 // AloBlo = pmuludq(a, b); 11347 // AloBhi = pmuludq(a, Bhi); 11348 // AhiBlo = pmuludq(Ahi, b); 11349 11350 // AloBhi = psllqi(AloBhi, 32); 11351 // AhiBlo = psllqi(AhiBlo, 32); 11352 // return AloBlo + AloBhi + AhiBlo; 11353 11354 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 11355 11356 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 11357 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 11358 11359 // Bit cast to 32-bit vectors for MULUDQ 11360 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 11361 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 11362 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 11363 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 11364 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 11365 11366 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 11367 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 11368 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 11369 11370 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 11371 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 11372 11373 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 11374 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 11375} 11376 11377SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const { 11378 EVT VT = Op.getValueType(); 11379 EVT EltTy = VT.getVectorElementType(); 11380 unsigned NumElts = VT.getVectorNumElements(); 11381 SDValue N0 = Op.getOperand(0); 11382 DebugLoc dl = Op.getDebugLoc(); 11383 11384 // Lower sdiv X, pow2-const. 11385 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1)); 11386 if (!C) 11387 return SDValue(); 11388 11389 APInt SplatValue, SplatUndef; 11390 unsigned MinSplatBits; 11391 bool HasAnyUndefs; 11392 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs)) 11393 return SDValue(); 11394 11395 if ((SplatValue != 0) && 11396 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) { 11397 unsigned lg2 = SplatValue.countTrailingZeros(); 11398 // Splat the sign bit. 11399 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32); 11400 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG); 11401 // Add (N0 < 0) ? abs2 - 1 : 0; 11402 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32); 11403 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG); 11404 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL); 11405 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32); 11406 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG); 11407 11408 // If we're dividing by a positive value, we're done. Otherwise, we must 11409 // negate the result. 11410 if (SplatValue.isNonNegative()) 11411 return SRA; 11412 11413 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy)); 11414 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts); 11415 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA); 11416 } 11417 return SDValue(); 11418} 11419 11420SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 11421 11422 EVT VT = Op.getValueType(); 11423 DebugLoc dl = Op.getDebugLoc(); 11424 SDValue R = Op.getOperand(0); 11425 SDValue Amt = Op.getOperand(1); 11426 LLVMContext *Context = DAG.getContext(); 11427 11428 if (!Subtarget->hasSSE2()) 11429 return SDValue(); 11430 11431 // Optimize shl/srl/sra with constant shift amount. 11432 if (isSplatVector(Amt.getNode())) { 11433 SDValue SclrAmt = Amt->getOperand(0); 11434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 11435 uint64_t ShiftAmt = C->getZExtValue(); 11436 11437 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 11438 (Subtarget->hasInt256() && 11439 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 11440 if (Op.getOpcode() == ISD::SHL) 11441 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 11442 DAG.getConstant(ShiftAmt, MVT::i32)); 11443 if (Op.getOpcode() == ISD::SRL) 11444 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 11445 DAG.getConstant(ShiftAmt, MVT::i32)); 11446 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 11447 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 11448 DAG.getConstant(ShiftAmt, MVT::i32)); 11449 } 11450 11451 if (VT == MVT::v16i8) { 11452 if (Op.getOpcode() == ISD::SHL) { 11453 // Make a large shift. 11454 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 11455 DAG.getConstant(ShiftAmt, MVT::i32)); 11456 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 11457 // Zero out the rightmost bits. 11458 SmallVector<SDValue, 16> V(16, 11459 DAG.getConstant(uint8_t(-1U << ShiftAmt), 11460 MVT::i8)); 11461 return DAG.getNode(ISD::AND, dl, VT, SHL, 11462 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 11463 } 11464 if (Op.getOpcode() == ISD::SRL) { 11465 // Make a large shift. 11466 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 11467 DAG.getConstant(ShiftAmt, MVT::i32)); 11468 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 11469 // Zero out the leftmost bits. 11470 SmallVector<SDValue, 16> V(16, 11471 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 11472 MVT::i8)); 11473 return DAG.getNode(ISD::AND, dl, VT, SRL, 11474 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 11475 } 11476 if (Op.getOpcode() == ISD::SRA) { 11477 if (ShiftAmt == 7) { 11478 // R s>> 7 === R s< 0 11479 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 11480 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 11481 } 11482 11483 // R s>> a === ((R u>> a) ^ m) - m 11484 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 11485 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 11486 MVT::i8)); 11487 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 11488 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 11489 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 11490 return Res; 11491 } 11492 llvm_unreachable("Unknown shift opcode."); 11493 } 11494 11495 if (Subtarget->hasInt256() && VT == MVT::v32i8) { 11496 if (Op.getOpcode() == ISD::SHL) { 11497 // Make a large shift. 11498 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 11499 DAG.getConstant(ShiftAmt, MVT::i32)); 11500 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 11501 // Zero out the rightmost bits. 11502 SmallVector<SDValue, 32> V(32, 11503 DAG.getConstant(uint8_t(-1U << ShiftAmt), 11504 MVT::i8)); 11505 return DAG.getNode(ISD::AND, dl, VT, SHL, 11506 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 11507 } 11508 if (Op.getOpcode() == ISD::SRL) { 11509 // Make a large shift. 11510 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 11511 DAG.getConstant(ShiftAmt, MVT::i32)); 11512 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 11513 // Zero out the leftmost bits. 11514 SmallVector<SDValue, 32> V(32, 11515 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 11516 MVT::i8)); 11517 return DAG.getNode(ISD::AND, dl, VT, SRL, 11518 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 11519 } 11520 if (Op.getOpcode() == ISD::SRA) { 11521 if (ShiftAmt == 7) { 11522 // R s>> 7 === R s< 0 11523 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 11524 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 11525 } 11526 11527 // R s>> a === ((R u>> a) ^ m) - m 11528 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 11529 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 11530 MVT::i8)); 11531 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 11532 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 11533 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 11534 return Res; 11535 } 11536 llvm_unreachable("Unknown shift opcode."); 11537 } 11538 } 11539 } 11540 11541 // Lower SHL with variable shift amount. 11542 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 11543 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 11544 DAG.getConstant(23, MVT::i32)); 11545 11546 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 11547 Constant *C = ConstantDataVector::get(*Context, CV); 11548 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 11549 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 11550 MachinePointerInfo::getConstantPool(), 11551 false, false, false, 16); 11552 11553 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 11554 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 11555 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 11556 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 11557 } 11558 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 11559 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 11560 11561 // a = a << 5; 11562 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 11563 DAG.getConstant(5, MVT::i32)); 11564 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 11565 11566 // Turn 'a' into a mask suitable for VSELECT 11567 SDValue VSelM = DAG.getConstant(0x80, VT); 11568 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 11569 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 11570 11571 SDValue CM1 = DAG.getConstant(0x0f, VT); 11572 SDValue CM2 = DAG.getConstant(0x3f, VT); 11573 11574 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 11575 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 11576 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 11577 DAG.getConstant(4, MVT::i32), DAG); 11578 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 11579 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 11580 11581 // a += a 11582 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 11583 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 11584 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 11585 11586 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 11587 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 11588 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 11589 DAG.getConstant(2, MVT::i32), DAG); 11590 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 11591 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 11592 11593 // a += a 11594 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 11595 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 11596 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 11597 11598 // return VSELECT(r, r+r, a); 11599 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 11600 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 11601 return R; 11602 } 11603 11604 // Decompose 256-bit shifts into smaller 128-bit shifts. 11605 if (VT.is256BitVector()) { 11606 unsigned NumElems = VT.getVectorNumElements(); 11607 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 11608 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 11609 11610 // Extract the two vectors 11611 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 11612 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 11613 11614 // Recreate the shift amount vectors 11615 SDValue Amt1, Amt2; 11616 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 11617 // Constant shift amount 11618 SmallVector<SDValue, 4> Amt1Csts; 11619 SmallVector<SDValue, 4> Amt2Csts; 11620 for (unsigned i = 0; i != NumElems/2; ++i) 11621 Amt1Csts.push_back(Amt->getOperand(i)); 11622 for (unsigned i = NumElems/2; i != NumElems; ++i) 11623 Amt2Csts.push_back(Amt->getOperand(i)); 11624 11625 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 11626 &Amt1Csts[0], NumElems/2); 11627 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 11628 &Amt2Csts[0], NumElems/2); 11629 } else { 11630 // Variable shift amount 11631 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 11632 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 11633 } 11634 11635 // Issue new vector shifts for the smaller types 11636 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 11637 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 11638 11639 // Concatenate the result back 11640 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 11641 } 11642 11643 return SDValue(); 11644} 11645 11646static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { 11647 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 11648 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 11649 // looks for this combo and may remove the "setcc" instruction if the "setcc" 11650 // has only one use. 11651 SDNode *N = Op.getNode(); 11652 SDValue LHS = N->getOperand(0); 11653 SDValue RHS = N->getOperand(1); 11654 unsigned BaseOp = 0; 11655 unsigned Cond = 0; 11656 DebugLoc DL = Op.getDebugLoc(); 11657 switch (Op.getOpcode()) { 11658 default: llvm_unreachable("Unknown ovf instruction!"); 11659 case ISD::SADDO: 11660 // A subtract of one will be selected as a INC. Note that INC doesn't 11661 // set CF, so we can't do this for UADDO. 11662 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 11663 if (C->isOne()) { 11664 BaseOp = X86ISD::INC; 11665 Cond = X86::COND_O; 11666 break; 11667 } 11668 BaseOp = X86ISD::ADD; 11669 Cond = X86::COND_O; 11670 break; 11671 case ISD::UADDO: 11672 BaseOp = X86ISD::ADD; 11673 Cond = X86::COND_B; 11674 break; 11675 case ISD::SSUBO: 11676 // A subtract of one will be selected as a DEC. Note that DEC doesn't 11677 // set CF, so we can't do this for USUBO. 11678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 11679 if (C->isOne()) { 11680 BaseOp = X86ISD::DEC; 11681 Cond = X86::COND_O; 11682 break; 11683 } 11684 BaseOp = X86ISD::SUB; 11685 Cond = X86::COND_O; 11686 break; 11687 case ISD::USUBO: 11688 BaseOp = X86ISD::SUB; 11689 Cond = X86::COND_B; 11690 break; 11691 case ISD::SMULO: 11692 BaseOp = X86ISD::SMUL; 11693 Cond = X86::COND_O; 11694 break; 11695 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 11696 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 11697 MVT::i32); 11698 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 11699 11700 SDValue SetCC = 11701 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11702 DAG.getConstant(X86::COND_O, MVT::i32), 11703 SDValue(Sum.getNode(), 2)); 11704 11705 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 11706 } 11707 } 11708 11709 // Also sets EFLAGS. 11710 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 11711 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 11712 11713 SDValue SetCC = 11714 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 11715 DAG.getConstant(Cond, MVT::i32), 11716 SDValue(Sum.getNode(), 1)); 11717 11718 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 11719} 11720 11721SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 11722 SelectionDAG &DAG) const { 11723 DebugLoc dl = Op.getDebugLoc(); 11724 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 11725 EVT VT = Op.getValueType(); 11726 11727 if (!Subtarget->hasSSE2() || !VT.isVector()) 11728 return SDValue(); 11729 11730 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 11731 ExtraVT.getScalarType().getSizeInBits(); 11732 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 11733 11734 switch (VT.getSimpleVT().SimpleTy) { 11735 default: return SDValue(); 11736 case MVT::v8i32: 11737 case MVT::v16i16: 11738 if (!Subtarget->hasFp256()) 11739 return SDValue(); 11740 if (!Subtarget->hasInt256()) { 11741 // needs to be split 11742 unsigned NumElems = VT.getVectorNumElements(); 11743 11744 // Extract the LHS vectors 11745 SDValue LHS = Op.getOperand(0); 11746 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 11747 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 11748 11749 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 11750 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 11751 11752 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 11753 unsigned ExtraNumElems = ExtraVT.getVectorNumElements(); 11754 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 11755 ExtraNumElems/2); 11756 SDValue Extra = DAG.getValueType(ExtraVT); 11757 11758 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 11759 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 11760 11761 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2); 11762 } 11763 // fall through 11764 case MVT::v4i32: 11765 case MVT::v8i16: { 11766 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 11767 Op.getOperand(0), ShAmt, DAG); 11768 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 11769 } 11770 } 11771} 11772 11773static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget, 11774 SelectionDAG &DAG) { 11775 DebugLoc dl = Op.getDebugLoc(); 11776 11777 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 11778 // There isn't any reason to disable it if the target processor supports it. 11779 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 11780 SDValue Chain = Op.getOperand(0); 11781 SDValue Zero = DAG.getConstant(0, MVT::i32); 11782 SDValue Ops[] = { 11783 DAG.getRegister(X86::ESP, MVT::i32), // Base 11784 DAG.getTargetConstant(1, MVT::i8), // Scale 11785 DAG.getRegister(0, MVT::i32), // Index 11786 DAG.getTargetConstant(0, MVT::i32), // Disp 11787 DAG.getRegister(0, MVT::i32), // Segment. 11788 Zero, 11789 Chain 11790 }; 11791 SDNode *Res = 11792 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 11793 array_lengthof(Ops)); 11794 return SDValue(Res, 0); 11795 } 11796 11797 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 11798 if (!isDev) 11799 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 11800 11801 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 11802 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 11803 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 11804 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 11805 11806 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 11807 if (!Op1 && !Op2 && !Op3 && Op4) 11808 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 11809 11810 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 11811 if (Op1 && !Op2 && !Op3 && !Op4) 11812 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 11813 11814 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 11815 // (MFENCE)>; 11816 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 11817} 11818 11819static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget, 11820 SelectionDAG &DAG) { 11821 DebugLoc dl = Op.getDebugLoc(); 11822 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 11823 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 11824 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 11825 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 11826 11827 // The only fence that needs an instruction is a sequentially-consistent 11828 // cross-thread fence. 11829 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 11830 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 11831 // no-sse2). There isn't any reason to disable it if the target processor 11832 // supports it. 11833 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 11834 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 11835 11836 SDValue Chain = Op.getOperand(0); 11837 SDValue Zero = DAG.getConstant(0, MVT::i32); 11838 SDValue Ops[] = { 11839 DAG.getRegister(X86::ESP, MVT::i32), // Base 11840 DAG.getTargetConstant(1, MVT::i8), // Scale 11841 DAG.getRegister(0, MVT::i32), // Index 11842 DAG.getTargetConstant(0, MVT::i32), // Disp 11843 DAG.getRegister(0, MVT::i32), // Segment. 11844 Zero, 11845 Chain 11846 }; 11847 SDNode *Res = 11848 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 11849 array_lengthof(Ops)); 11850 return SDValue(Res, 0); 11851 } 11852 11853 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 11854 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 11855} 11856 11857static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget, 11858 SelectionDAG &DAG) { 11859 EVT T = Op.getValueType(); 11860 DebugLoc DL = Op.getDebugLoc(); 11861 unsigned Reg = 0; 11862 unsigned size = 0; 11863 switch(T.getSimpleVT().SimpleTy) { 11864 default: llvm_unreachable("Invalid value type!"); 11865 case MVT::i8: Reg = X86::AL; size = 1; break; 11866 case MVT::i16: Reg = X86::AX; size = 2; break; 11867 case MVT::i32: Reg = X86::EAX; size = 4; break; 11868 case MVT::i64: 11869 assert(Subtarget->is64Bit() && "Node not type legal!"); 11870 Reg = X86::RAX; size = 8; 11871 break; 11872 } 11873 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 11874 Op.getOperand(2), SDValue()); 11875 SDValue Ops[] = { cpIn.getValue(0), 11876 Op.getOperand(1), 11877 Op.getOperand(3), 11878 DAG.getTargetConstant(size, MVT::i8), 11879 cpIn.getValue(1) }; 11880 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11881 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 11882 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 11883 Ops, 5, T, MMO); 11884 SDValue cpOut = 11885 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 11886 return cpOut; 11887} 11888 11889static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget, 11890 SelectionDAG &DAG) { 11891 assert(Subtarget->is64Bit() && "Result not type legalized?"); 11892 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11893 SDValue TheChain = Op.getOperand(0); 11894 DebugLoc dl = Op.getDebugLoc(); 11895 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11896 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 11897 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 11898 rax.getValue(2)); 11899 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 11900 DAG.getConstant(32, MVT::i8)); 11901 SDValue Ops[] = { 11902 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 11903 rdx.getValue(1) 11904 }; 11905 return DAG.getMergeValues(Ops, 2, dl); 11906} 11907 11908SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const { 11909 EVT SrcVT = Op.getOperand(0).getValueType(); 11910 EVT DstVT = Op.getValueType(); 11911 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 11912 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 11913 assert((DstVT == MVT::i64 || 11914 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 11915 "Unexpected custom BITCAST"); 11916 // i64 <=> MMX conversions are Legal. 11917 if (SrcVT==MVT::i64 && DstVT.isVector()) 11918 return Op; 11919 if (DstVT==MVT::i64 && SrcVT.isVector()) 11920 return Op; 11921 // MMX <=> MMX conversions are Legal. 11922 if (SrcVT.isVector() && DstVT.isVector()) 11923 return Op; 11924 // All other conversions need to be expanded. 11925 return SDValue(); 11926} 11927 11928static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 11929 SDNode *Node = Op.getNode(); 11930 DebugLoc dl = Node->getDebugLoc(); 11931 EVT T = Node->getValueType(0); 11932 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 11933 DAG.getConstant(0, T), Node->getOperand(2)); 11934 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 11935 cast<AtomicSDNode>(Node)->getMemoryVT(), 11936 Node->getOperand(0), 11937 Node->getOperand(1), negOp, 11938 cast<AtomicSDNode>(Node)->getSrcValue(), 11939 cast<AtomicSDNode>(Node)->getAlignment(), 11940 cast<AtomicSDNode>(Node)->getOrdering(), 11941 cast<AtomicSDNode>(Node)->getSynchScope()); 11942} 11943 11944static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 11945 SDNode *Node = Op.getNode(); 11946 DebugLoc dl = Node->getDebugLoc(); 11947 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 11948 11949 // Convert seq_cst store -> xchg 11950 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 11951 // FIXME: On 32-bit, store -> fist or movq would be more efficient 11952 // (The only way to get a 16-byte store is cmpxchg16b) 11953 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 11954 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 11955 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 11956 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 11957 cast<AtomicSDNode>(Node)->getMemoryVT(), 11958 Node->getOperand(0), 11959 Node->getOperand(1), Node->getOperand(2), 11960 cast<AtomicSDNode>(Node)->getMemOperand(), 11961 cast<AtomicSDNode>(Node)->getOrdering(), 11962 cast<AtomicSDNode>(Node)->getSynchScope()); 11963 return Swap.getValue(1); 11964 } 11965 // Other atomic stores have a simple pattern. 11966 return Op; 11967} 11968 11969static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 11970 EVT VT = Op.getNode()->getValueType(0); 11971 11972 // Let legalize expand this if it isn't a legal type yet. 11973 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 11974 return SDValue(); 11975 11976 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 11977 11978 unsigned Opc; 11979 bool ExtraOp = false; 11980 switch (Op.getOpcode()) { 11981 default: llvm_unreachable("Invalid code"); 11982 case ISD::ADDC: Opc = X86ISD::ADD; break; 11983 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 11984 case ISD::SUBC: Opc = X86ISD::SUB; break; 11985 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 11986 } 11987 11988 if (!ExtraOp) 11989 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 11990 Op.getOperand(1)); 11991 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 11992 Op.getOperand(1), Op.getOperand(2)); 11993} 11994 11995/// LowerOperation - Provide custom lowering hooks for some operations. 11996/// 11997SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 11998 switch (Op.getOpcode()) { 11999 default: llvm_unreachable("Should not custom lower this!"); 12000 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 12001 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG); 12002 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG); 12003 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG); 12004 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 12005 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 12006 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 12007 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 12008 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 12009 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 12010 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 12011 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG); 12012 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG); 12013 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 12014 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 12015 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 12016 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 12017 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 12018 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 12019 case ISD::SHL_PARTS: 12020 case ISD::SRA_PARTS: 12021 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 12022 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 12023 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 12024 case ISD::TRUNCATE: return lowerTRUNCATE(Op, DAG); 12025 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG); 12026 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 12027 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG); 12028 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 12029 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 12030 case ISD::FP_EXTEND: return lowerFP_EXTEND(Op, DAG); 12031 case ISD::FABS: return LowerFABS(Op, DAG); 12032 case ISD::FNEG: return LowerFNEG(Op, DAG); 12033 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 12034 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 12035 case ISD::SETCC: return LowerSETCC(Op, DAG); 12036 case ISD::SELECT: return LowerSELECT(Op, DAG); 12037 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 12038 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 12039 case ISD::VASTART: return LowerVASTART(Op, DAG); 12040 case ISD::VAARG: return LowerVAARG(Op, DAG); 12041 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG); 12042 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 12043 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 12044 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 12045 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 12046 case ISD::FRAME_TO_ARGS_OFFSET: 12047 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 12048 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 12049 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 12050 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG); 12051 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG); 12052 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 12053 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 12054 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 12055 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 12056 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 12057 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 12058 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG); 12059 case ISD::SRA: 12060 case ISD::SRL: 12061 case ISD::SHL: return LowerShift(Op, DAG); 12062 case ISD::SADDO: 12063 case ISD::UADDO: 12064 case ISD::SSUBO: 12065 case ISD::USUBO: 12066 case ISD::SMULO: 12067 case ISD::UMULO: return LowerXALUO(Op, DAG); 12068 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG); 12069 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 12070 case ISD::ADDC: 12071 case ISD::ADDE: 12072 case ISD::SUBC: 12073 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 12074 case ISD::ADD: return LowerADD(Op, DAG); 12075 case ISD::SUB: return LowerSUB(Op, DAG); 12076 case ISD::SDIV: return LowerSDIV(Op, DAG); 12077 } 12078} 12079 12080static void ReplaceATOMIC_LOAD(SDNode *Node, 12081 SmallVectorImpl<SDValue> &Results, 12082 SelectionDAG &DAG) { 12083 DebugLoc dl = Node->getDebugLoc(); 12084 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 12085 12086 // Convert wide load -> cmpxchg8b/cmpxchg16b 12087 // FIXME: On 32-bit, load -> fild or movq would be more efficient 12088 // (The only way to get a 16-byte load is cmpxchg16b) 12089 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 12090 SDValue Zero = DAG.getConstant(0, VT); 12091 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 12092 Node->getOperand(0), 12093 Node->getOperand(1), Zero, Zero, 12094 cast<AtomicSDNode>(Node)->getMemOperand(), 12095 cast<AtomicSDNode>(Node)->getOrdering(), 12096 cast<AtomicSDNode>(Node)->getSynchScope()); 12097 Results.push_back(Swap.getValue(0)); 12098 Results.push_back(Swap.getValue(1)); 12099} 12100 12101static void 12102ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 12103 SelectionDAG &DAG, unsigned NewOp) { 12104 DebugLoc dl = Node->getDebugLoc(); 12105 assert (Node->getValueType(0) == MVT::i64 && 12106 "Only know how to expand i64 atomics"); 12107 12108 SDValue Chain = Node->getOperand(0); 12109 SDValue In1 = Node->getOperand(1); 12110 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 12111 Node->getOperand(2), DAG.getIntPtrConstant(0)); 12112 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 12113 Node->getOperand(2), DAG.getIntPtrConstant(1)); 12114 SDValue Ops[] = { Chain, In1, In2L, In2H }; 12115 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 12116 SDValue Result = 12117 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 12118 cast<MemSDNode>(Node)->getMemOperand()); 12119 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 12120 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 12121 Results.push_back(Result.getValue(2)); 12122} 12123 12124/// ReplaceNodeResults - Replace a node with an illegal result type 12125/// with a new node built out of custom code. 12126void X86TargetLowering::ReplaceNodeResults(SDNode *N, 12127 SmallVectorImpl<SDValue>&Results, 12128 SelectionDAG &DAG) const { 12129 DebugLoc dl = N->getDebugLoc(); 12130 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12131 switch (N->getOpcode()) { 12132 default: 12133 llvm_unreachable("Do not know how to custom type legalize this operation!"); 12134 case ISD::SIGN_EXTEND_INREG: 12135 case ISD::ADDC: 12136 case ISD::ADDE: 12137 case ISD::SUBC: 12138 case ISD::SUBE: 12139 // We don't want to expand or promote these. 12140 return; 12141 case ISD::FP_TO_SINT: 12142 case ISD::FP_TO_UINT: { 12143 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 12144 12145 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 12146 return; 12147 12148 std::pair<SDValue,SDValue> Vals = 12149 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 12150 SDValue FIST = Vals.first, StackSlot = Vals.second; 12151 if (FIST.getNode() != 0) { 12152 EVT VT = N->getValueType(0); 12153 // Return a load from the stack slot. 12154 if (StackSlot.getNode() != 0) 12155 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 12156 MachinePointerInfo(), 12157 false, false, false, 0)); 12158 else 12159 Results.push_back(FIST); 12160 } 12161 return; 12162 } 12163 case ISD::UINT_TO_FP: { 12164 if (N->getOperand(0).getValueType() != MVT::v2i32 && 12165 N->getValueType(0) != MVT::v2f32) 12166 return; 12167 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, 12168 N->getOperand(0)); 12169 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 12170 MVT::f64); 12171 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias); 12172 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn, 12173 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias)); 12174 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or); 12175 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias); 12176 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub)); 12177 return; 12178 } 12179 case ISD::FP_ROUND: { 12180 if (!TLI.isTypeLegal(N->getOperand(0).getValueType())) 12181 return; 12182 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0)); 12183 Results.push_back(V); 12184 return; 12185 } 12186 case ISD::READCYCLECOUNTER: { 12187 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 12188 SDValue TheChain = N->getOperand(0); 12189 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 12190 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 12191 rd.getValue(1)); 12192 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 12193 eax.getValue(2)); 12194 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 12195 SDValue Ops[] = { eax, edx }; 12196 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 12197 Results.push_back(edx.getValue(1)); 12198 return; 12199 } 12200 case ISD::ATOMIC_CMP_SWAP: { 12201 EVT T = N->getValueType(0); 12202 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 12203 bool Regs64bit = T == MVT::i128; 12204 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 12205 SDValue cpInL, cpInH; 12206 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 12207 DAG.getConstant(0, HalfT)); 12208 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 12209 DAG.getConstant(1, HalfT)); 12210 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 12211 Regs64bit ? X86::RAX : X86::EAX, 12212 cpInL, SDValue()); 12213 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 12214 Regs64bit ? X86::RDX : X86::EDX, 12215 cpInH, cpInL.getValue(1)); 12216 SDValue swapInL, swapInH; 12217 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 12218 DAG.getConstant(0, HalfT)); 12219 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 12220 DAG.getConstant(1, HalfT)); 12221 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 12222 Regs64bit ? X86::RBX : X86::EBX, 12223 swapInL, cpInH.getValue(1)); 12224 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 12225 Regs64bit ? X86::RCX : X86::ECX, 12226 swapInH, swapInL.getValue(1)); 12227 SDValue Ops[] = { swapInH.getValue(0), 12228 N->getOperand(1), 12229 swapInH.getValue(1) }; 12230 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 12231 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 12232 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 12233 X86ISD::LCMPXCHG8_DAG; 12234 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 12235 Ops, 3, T, MMO); 12236 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 12237 Regs64bit ? X86::RAX : X86::EAX, 12238 HalfT, Result.getValue(1)); 12239 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 12240 Regs64bit ? X86::RDX : X86::EDX, 12241 HalfT, cpOutL.getValue(2)); 12242 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 12243 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 12244 Results.push_back(cpOutH.getValue(1)); 12245 return; 12246 } 12247 case ISD::ATOMIC_LOAD_ADD: 12248 case ISD::ATOMIC_LOAD_AND: 12249 case ISD::ATOMIC_LOAD_NAND: 12250 case ISD::ATOMIC_LOAD_OR: 12251 case ISD::ATOMIC_LOAD_SUB: 12252 case ISD::ATOMIC_LOAD_XOR: 12253 case ISD::ATOMIC_LOAD_MAX: 12254 case ISD::ATOMIC_LOAD_MIN: 12255 case ISD::ATOMIC_LOAD_UMAX: 12256 case ISD::ATOMIC_LOAD_UMIN: 12257 case ISD::ATOMIC_SWAP: { 12258 unsigned Opc; 12259 switch (N->getOpcode()) { 12260 default: llvm_unreachable("Unexpected opcode"); 12261 case ISD::ATOMIC_LOAD_ADD: 12262 Opc = X86ISD::ATOMADD64_DAG; 12263 break; 12264 case ISD::ATOMIC_LOAD_AND: 12265 Opc = X86ISD::ATOMAND64_DAG; 12266 break; 12267 case ISD::ATOMIC_LOAD_NAND: 12268 Opc = X86ISD::ATOMNAND64_DAG; 12269 break; 12270 case ISD::ATOMIC_LOAD_OR: 12271 Opc = X86ISD::ATOMOR64_DAG; 12272 break; 12273 case ISD::ATOMIC_LOAD_SUB: 12274 Opc = X86ISD::ATOMSUB64_DAG; 12275 break; 12276 case ISD::ATOMIC_LOAD_XOR: 12277 Opc = X86ISD::ATOMXOR64_DAG; 12278 break; 12279 case ISD::ATOMIC_LOAD_MAX: 12280 Opc = X86ISD::ATOMMAX64_DAG; 12281 break; 12282 case ISD::ATOMIC_LOAD_MIN: 12283 Opc = X86ISD::ATOMMIN64_DAG; 12284 break; 12285 case ISD::ATOMIC_LOAD_UMAX: 12286 Opc = X86ISD::ATOMUMAX64_DAG; 12287 break; 12288 case ISD::ATOMIC_LOAD_UMIN: 12289 Opc = X86ISD::ATOMUMIN64_DAG; 12290 break; 12291 case ISD::ATOMIC_SWAP: 12292 Opc = X86ISD::ATOMSWAP64_DAG; 12293 break; 12294 } 12295 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc); 12296 return; 12297 } 12298 case ISD::ATOMIC_LOAD: 12299 ReplaceATOMIC_LOAD(N, Results, DAG); 12300 } 12301} 12302 12303const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 12304 switch (Opcode) { 12305 default: return NULL; 12306 case X86ISD::BSF: return "X86ISD::BSF"; 12307 case X86ISD::BSR: return "X86ISD::BSR"; 12308 case X86ISD::SHLD: return "X86ISD::SHLD"; 12309 case X86ISD::SHRD: return "X86ISD::SHRD"; 12310 case X86ISD::FAND: return "X86ISD::FAND"; 12311 case X86ISD::FOR: return "X86ISD::FOR"; 12312 case X86ISD::FXOR: return "X86ISD::FXOR"; 12313 case X86ISD::FSRL: return "X86ISD::FSRL"; 12314 case X86ISD::FILD: return "X86ISD::FILD"; 12315 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 12316 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 12317 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 12318 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 12319 case X86ISD::FLD: return "X86ISD::FLD"; 12320 case X86ISD::FST: return "X86ISD::FST"; 12321 case X86ISD::CALL: return "X86ISD::CALL"; 12322 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 12323 case X86ISD::BT: return "X86ISD::BT"; 12324 case X86ISD::CMP: return "X86ISD::CMP"; 12325 case X86ISD::COMI: return "X86ISD::COMI"; 12326 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 12327 case X86ISD::SETCC: return "X86ISD::SETCC"; 12328 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 12329 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 12330 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 12331 case X86ISD::CMOV: return "X86ISD::CMOV"; 12332 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 12333 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 12334 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 12335 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 12336 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 12337 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 12338 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 12339 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 12340 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 12341 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 12342 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 12343 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 12344 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 12345 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 12346 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 12347 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 12348 case X86ISD::BLENDI: return "X86ISD::BLENDI"; 12349 case X86ISD::SUBUS: return "X86ISD::SUBUS"; 12350 case X86ISD::HADD: return "X86ISD::HADD"; 12351 case X86ISD::HSUB: return "X86ISD::HSUB"; 12352 case X86ISD::FHADD: return "X86ISD::FHADD"; 12353 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 12354 case X86ISD::UMAX: return "X86ISD::UMAX"; 12355 case X86ISD::UMIN: return "X86ISD::UMIN"; 12356 case X86ISD::SMAX: return "X86ISD::SMAX"; 12357 case X86ISD::SMIN: return "X86ISD::SMIN"; 12358 case X86ISD::FMAX: return "X86ISD::FMAX"; 12359 case X86ISD::FMIN: return "X86ISD::FMIN"; 12360 case X86ISD::FMAXC: return "X86ISD::FMAXC"; 12361 case X86ISD::FMINC: return "X86ISD::FMINC"; 12362 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 12363 case X86ISD::FRCP: return "X86ISD::FRCP"; 12364 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 12365 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR"; 12366 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 12367 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP"; 12368 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP"; 12369 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 12370 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 12371 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 12372 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 12373 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 12374 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 12375 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 12376 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 12377 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 12378 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 12379 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 12380 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 12381 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 12382 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL"; 12383 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 12384 case X86ISD::VZEXT: return "X86ISD::VZEXT"; 12385 case X86ISD::VSEXT: return "X86ISD::VSEXT"; 12386 case X86ISD::VFPEXT: return "X86ISD::VFPEXT"; 12387 case X86ISD::VFPROUND: return "X86ISD::VFPROUND"; 12388 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 12389 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 12390 case X86ISD::VSHL: return "X86ISD::VSHL"; 12391 case X86ISD::VSRL: return "X86ISD::VSRL"; 12392 case X86ISD::VSRA: return "X86ISD::VSRA"; 12393 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 12394 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 12395 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 12396 case X86ISD::CMPP: return "X86ISD::CMPP"; 12397 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 12398 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 12399 case X86ISD::ADD: return "X86ISD::ADD"; 12400 case X86ISD::SUB: return "X86ISD::SUB"; 12401 case X86ISD::ADC: return "X86ISD::ADC"; 12402 case X86ISD::SBB: return "X86ISD::SBB"; 12403 case X86ISD::SMUL: return "X86ISD::SMUL"; 12404 case X86ISD::UMUL: return "X86ISD::UMUL"; 12405 case X86ISD::INC: return "X86ISD::INC"; 12406 case X86ISD::DEC: return "X86ISD::DEC"; 12407 case X86ISD::OR: return "X86ISD::OR"; 12408 case X86ISD::XOR: return "X86ISD::XOR"; 12409 case X86ISD::AND: return "X86ISD::AND"; 12410 case X86ISD::BLSI: return "X86ISD::BLSI"; 12411 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 12412 case X86ISD::BLSR: return "X86ISD::BLSR"; 12413 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 12414 case X86ISD::PTEST: return "X86ISD::PTEST"; 12415 case X86ISD::TESTP: return "X86ISD::TESTP"; 12416 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 12417 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 12418 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 12419 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 12420 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 12421 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 12422 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 12423 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 12424 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 12425 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 12426 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 12427 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 12428 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 12429 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 12430 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 12431 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 12432 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 12433 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 12434 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 12435 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 12436 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 12437 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 12438 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 12439 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 12440 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 12441 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 12442 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 12443 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 12444 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 12445 case X86ISD::SAHF: return "X86ISD::SAHF"; 12446 case X86ISD::RDRAND: return "X86ISD::RDRAND"; 12447 case X86ISD::FMADD: return "X86ISD::FMADD"; 12448 case X86ISD::FMSUB: return "X86ISD::FMSUB"; 12449 case X86ISD::FNMADD: return "X86ISD::FNMADD"; 12450 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; 12451 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB"; 12452 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD"; 12453 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI"; 12454 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI"; 12455 } 12456} 12457 12458// isLegalAddressingMode - Return true if the addressing mode represented 12459// by AM is legal for this target, for a load/store of the specified type. 12460bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 12461 Type *Ty) const { 12462 // X86 supports extremely general addressing modes. 12463 CodeModel::Model M = getTargetMachine().getCodeModel(); 12464 Reloc::Model R = getTargetMachine().getRelocationModel(); 12465 12466 // X86 allows a sign-extended 32-bit immediate field as a displacement. 12467 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 12468 return false; 12469 12470 if (AM.BaseGV) { 12471 unsigned GVFlags = 12472 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 12473 12474 // If a reference to this global requires an extra load, we can't fold it. 12475 if (isGlobalStubReference(GVFlags)) 12476 return false; 12477 12478 // If BaseGV requires a register for the PIC base, we cannot also have a 12479 // BaseReg specified. 12480 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 12481 return false; 12482 12483 // If lower 4G is not available, then we must use rip-relative addressing. 12484 if ((M != CodeModel::Small || R != Reloc::Static) && 12485 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 12486 return false; 12487 } 12488 12489 switch (AM.Scale) { 12490 case 0: 12491 case 1: 12492 case 2: 12493 case 4: 12494 case 8: 12495 // These scales always work. 12496 break; 12497 case 3: 12498 case 5: 12499 case 9: 12500 // These scales are formed with basereg+scalereg. Only accept if there is 12501 // no basereg yet. 12502 if (AM.HasBaseReg) 12503 return false; 12504 break; 12505 default: // Other stuff never works. 12506 return false; 12507 } 12508 12509 return true; 12510} 12511 12512bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 12513 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 12514 return false; 12515 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 12516 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 12517 return NumBits1 > NumBits2; 12518} 12519 12520bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const { 12521 return isInt<32>(Imm); 12522} 12523 12524bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const { 12525 // Can also use sub to handle negated immediates. 12526 return isInt<32>(Imm); 12527} 12528 12529bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 12530 if (!VT1.isInteger() || !VT2.isInteger()) 12531 return false; 12532 unsigned NumBits1 = VT1.getSizeInBits(); 12533 unsigned NumBits2 = VT2.getSizeInBits(); 12534 return NumBits1 > NumBits2; 12535} 12536 12537bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 12538 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 12539 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 12540} 12541 12542bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 12543 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 12544 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 12545} 12546 12547bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 12548 EVT VT1 = Val.getValueType(); 12549 if (isZExtFree(VT1, VT2)) 12550 return true; 12551 12552 if (Val.getOpcode() != ISD::LOAD) 12553 return false; 12554 12555 if (!VT1.isSimple() || !VT1.isInteger() || 12556 !VT2.isSimple() || !VT2.isInteger()) 12557 return false; 12558 12559 switch (VT1.getSimpleVT().SimpleTy) { 12560 default: break; 12561 case MVT::i8: 12562 case MVT::i16: 12563 case MVT::i32: 12564 // X86 has 8, 16, and 32-bit zero-extending loads. 12565 return true; 12566 } 12567 12568 return false; 12569} 12570 12571bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 12572 // i16 instructions are longer (0x66 prefix) and potentially slower. 12573 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 12574} 12575 12576/// isShuffleMaskLegal - Targets can use this to indicate that they only 12577/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 12578/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 12579/// are assumed to be legal. 12580bool 12581X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 12582 EVT VT) const { 12583 // Very little shuffling can be done for 64-bit vectors right now. 12584 if (VT.getSizeInBits() == 64) 12585 return false; 12586 12587 // FIXME: pshufb, blends, shifts. 12588 return (VT.getVectorNumElements() == 2 || 12589 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 12590 isMOVLMask(M, VT) || 12591 isSHUFPMask(M, VT, Subtarget->hasFp256()) || 12592 isPSHUFDMask(M, VT) || 12593 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) || 12594 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) || 12595 isPALIGNRMask(M, VT, Subtarget) || 12596 isUNPCKLMask(M, VT, Subtarget->hasInt256()) || 12597 isUNPCKHMask(M, VT, Subtarget->hasInt256()) || 12598 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) || 12599 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256())); 12600} 12601 12602bool 12603X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 12604 EVT VT) const { 12605 unsigned NumElts = VT.getVectorNumElements(); 12606 // FIXME: This collection of masks seems suspect. 12607 if (NumElts == 2) 12608 return true; 12609 if (NumElts == 4 && VT.is128BitVector()) { 12610 return (isMOVLMask(Mask, VT) || 12611 isCommutedMOVLMask(Mask, VT, true) || 12612 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) || 12613 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true)); 12614 } 12615 return false; 12616} 12617 12618//===----------------------------------------------------------------------===// 12619// X86 Scheduler Hooks 12620//===----------------------------------------------------------------------===// 12621 12622/// Utility function to emit xbegin specifying the start of an RTM region. 12623static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, 12624 const TargetInstrInfo *TII) { 12625 DebugLoc DL = MI->getDebugLoc(); 12626 12627 const BasicBlock *BB = MBB->getBasicBlock(); 12628 MachineFunction::iterator I = MBB; 12629 ++I; 12630 12631 // For the v = xbegin(), we generate 12632 // 12633 // thisMBB: 12634 // xbegin sinkMBB 12635 // 12636 // mainMBB: 12637 // eax = -1 12638 // 12639 // sinkMBB: 12640 // v = eax 12641 12642 MachineBasicBlock *thisMBB = MBB; 12643 MachineFunction *MF = MBB->getParent(); 12644 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 12645 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 12646 MF->insert(I, mainMBB); 12647 MF->insert(I, sinkMBB); 12648 12649 // Transfer the remainder of BB and its successor edges to sinkMBB. 12650 sinkMBB->splice(sinkMBB->begin(), MBB, 12651 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 12652 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 12653 12654 // thisMBB: 12655 // xbegin sinkMBB 12656 // # fallthrough to mainMBB 12657 // # abortion to sinkMBB 12658 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB); 12659 thisMBB->addSuccessor(mainMBB); 12660 thisMBB->addSuccessor(sinkMBB); 12661 12662 // mainMBB: 12663 // EAX = -1 12664 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1); 12665 mainMBB->addSuccessor(sinkMBB); 12666 12667 // sinkMBB: 12668 // EAX is live into the sinkMBB 12669 sinkMBB->addLiveIn(X86::EAX); 12670 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12671 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 12672 .addReg(X86::EAX); 12673 12674 MI->eraseFromParent(); 12675 return sinkMBB; 12676} 12677 12678// Get CMPXCHG opcode for the specified data type. 12679static unsigned getCmpXChgOpcode(EVT VT) { 12680 switch (VT.getSimpleVT().SimpleTy) { 12681 case MVT::i8: return X86::LCMPXCHG8; 12682 case MVT::i16: return X86::LCMPXCHG16; 12683 case MVT::i32: return X86::LCMPXCHG32; 12684 case MVT::i64: return X86::LCMPXCHG64; 12685 default: 12686 break; 12687 } 12688 llvm_unreachable("Invalid operand size!"); 12689} 12690 12691// Get LOAD opcode for the specified data type. 12692static unsigned getLoadOpcode(EVT VT) { 12693 switch (VT.getSimpleVT().SimpleTy) { 12694 case MVT::i8: return X86::MOV8rm; 12695 case MVT::i16: return X86::MOV16rm; 12696 case MVT::i32: return X86::MOV32rm; 12697 case MVT::i64: return X86::MOV64rm; 12698 default: 12699 break; 12700 } 12701 llvm_unreachable("Invalid operand size!"); 12702} 12703 12704// Get opcode of the non-atomic one from the specified atomic instruction. 12705static unsigned getNonAtomicOpcode(unsigned Opc) { 12706 switch (Opc) { 12707 case X86::ATOMAND8: return X86::AND8rr; 12708 case X86::ATOMAND16: return X86::AND16rr; 12709 case X86::ATOMAND32: return X86::AND32rr; 12710 case X86::ATOMAND64: return X86::AND64rr; 12711 case X86::ATOMOR8: return X86::OR8rr; 12712 case X86::ATOMOR16: return X86::OR16rr; 12713 case X86::ATOMOR32: return X86::OR32rr; 12714 case X86::ATOMOR64: return X86::OR64rr; 12715 case X86::ATOMXOR8: return X86::XOR8rr; 12716 case X86::ATOMXOR16: return X86::XOR16rr; 12717 case X86::ATOMXOR32: return X86::XOR32rr; 12718 case X86::ATOMXOR64: return X86::XOR64rr; 12719 } 12720 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12721} 12722 12723// Get opcode of the non-atomic one from the specified atomic instruction with 12724// extra opcode. 12725static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc, 12726 unsigned &ExtraOpc) { 12727 switch (Opc) { 12728 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr; 12729 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr; 12730 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr; 12731 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr; 12732 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr; 12733 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr; 12734 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr; 12735 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr; 12736 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr; 12737 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr; 12738 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr; 12739 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr; 12740 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr; 12741 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr; 12742 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr; 12743 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr; 12744 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr; 12745 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr; 12746 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr; 12747 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr; 12748 } 12749 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12750} 12751 12752// Get opcode of the non-atomic one from the specified atomic instruction for 12753// 64-bit data type on 32-bit target. 12754static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) { 12755 switch (Opc) { 12756 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr; 12757 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr; 12758 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr; 12759 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr; 12760 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr; 12761 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr; 12762 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr; 12763 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr; 12764 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr; 12765 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr; 12766 } 12767 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12768} 12769 12770// Get opcode of the non-atomic one from the specified atomic instruction for 12771// 64-bit data type on 32-bit target with extra opcode. 12772static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc, 12773 unsigned &HiOpc, 12774 unsigned &ExtraOpc) { 12775 switch (Opc) { 12776 case X86::ATOMNAND6432: 12777 ExtraOpc = X86::NOT32r; 12778 HiOpc = X86::AND32rr; 12779 return X86::AND32rr; 12780 } 12781 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12782} 12783 12784// Get pseudo CMOV opcode from the specified data type. 12785static unsigned getPseudoCMOVOpc(EVT VT) { 12786 switch (VT.getSimpleVT().SimpleTy) { 12787 case MVT::i8: return X86::CMOV_GR8; 12788 case MVT::i16: return X86::CMOV_GR16; 12789 case MVT::i32: return X86::CMOV_GR32; 12790 default: 12791 break; 12792 } 12793 llvm_unreachable("Unknown CMOV opcode!"); 12794} 12795 12796// EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions. 12797// They will be translated into a spin-loop or compare-exchange loop from 12798// 12799// ... 12800// dst = atomic-fetch-op MI.addr, MI.val 12801// ... 12802// 12803// to 12804// 12805// ... 12806// EAX = LOAD MI.addr 12807// loop: 12808// t1 = OP MI.val, EAX 12809// LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] 12810// JNE loop 12811// sink: 12812// dst = EAX 12813// ... 12814MachineBasicBlock * 12815X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI, 12816 MachineBasicBlock *MBB) const { 12817 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12818 DebugLoc DL = MI->getDebugLoc(); 12819 12820 MachineFunction *MF = MBB->getParent(); 12821 MachineRegisterInfo &MRI = MF->getRegInfo(); 12822 12823 const BasicBlock *BB = MBB->getBasicBlock(); 12824 MachineFunction::iterator I = MBB; 12825 ++I; 12826 12827 assert(MI->getNumOperands() <= X86::AddrNumOperands + 2 && 12828 "Unexpected number of operands"); 12829 12830 assert(MI->hasOneMemOperand() && 12831 "Expected atomic-load-op to have one memoperand"); 12832 12833 // Memory Reference 12834 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 12835 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 12836 12837 unsigned DstReg, SrcReg; 12838 unsigned MemOpndSlot; 12839 12840 unsigned CurOp = 0; 12841 12842 DstReg = MI->getOperand(CurOp++).getReg(); 12843 MemOpndSlot = CurOp; 12844 CurOp += X86::AddrNumOperands; 12845 SrcReg = MI->getOperand(CurOp++).getReg(); 12846 12847 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 12848 MVT::SimpleValueType VT = *RC->vt_begin(); 12849 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT); 12850 12851 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT); 12852 unsigned LOADOpc = getLoadOpcode(VT); 12853 12854 // For the atomic load-arith operator, we generate 12855 // 12856 // thisMBB: 12857 // EAX = LOAD [MI.addr] 12858 // mainMBB: 12859 // t1 = OP MI.val, EAX 12860 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] 12861 // JNE mainMBB 12862 // sinkMBB: 12863 12864 MachineBasicBlock *thisMBB = MBB; 12865 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 12866 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 12867 MF->insert(I, mainMBB); 12868 MF->insert(I, sinkMBB); 12869 12870 MachineInstrBuilder MIB; 12871 12872 // Transfer the remainder of BB and its successor edges to sinkMBB. 12873 sinkMBB->splice(sinkMBB->begin(), MBB, 12874 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 12875 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 12876 12877 // thisMBB: 12878 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg); 12879 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 12880 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 12881 MIB.setMemRefs(MMOBegin, MMOEnd); 12882 12883 thisMBB->addSuccessor(mainMBB); 12884 12885 // mainMBB: 12886 MachineBasicBlock *origMainMBB = mainMBB; 12887 mainMBB->addLiveIn(AccPhyReg); 12888 12889 // Copy AccPhyReg as it is used more than once. 12890 unsigned AccReg = MRI.createVirtualRegister(RC); 12891 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg) 12892 .addReg(AccPhyReg); 12893 12894 unsigned t1 = MRI.createVirtualRegister(RC); 12895 unsigned Opc = MI->getOpcode(); 12896 switch (Opc) { 12897 default: 12898 llvm_unreachable("Unhandled atomic-load-op opcode!"); 12899 case X86::ATOMAND8: 12900 case X86::ATOMAND16: 12901 case X86::ATOMAND32: 12902 case X86::ATOMAND64: 12903 case X86::ATOMOR8: 12904 case X86::ATOMOR16: 12905 case X86::ATOMOR32: 12906 case X86::ATOMOR64: 12907 case X86::ATOMXOR8: 12908 case X86::ATOMXOR16: 12909 case X86::ATOMXOR32: 12910 case X86::ATOMXOR64: { 12911 unsigned ARITHOpc = getNonAtomicOpcode(Opc); 12912 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg) 12913 .addReg(AccReg); 12914 break; 12915 } 12916 case X86::ATOMNAND8: 12917 case X86::ATOMNAND16: 12918 case X86::ATOMNAND32: 12919 case X86::ATOMNAND64: { 12920 unsigned t2 = MRI.createVirtualRegister(RC); 12921 unsigned NOTOpc; 12922 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc); 12923 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg) 12924 .addReg(AccReg); 12925 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2); 12926 break; 12927 } 12928 case X86::ATOMMAX8: 12929 case X86::ATOMMAX16: 12930 case X86::ATOMMAX32: 12931 case X86::ATOMMAX64: 12932 case X86::ATOMMIN8: 12933 case X86::ATOMMIN16: 12934 case X86::ATOMMIN32: 12935 case X86::ATOMMIN64: 12936 case X86::ATOMUMAX8: 12937 case X86::ATOMUMAX16: 12938 case X86::ATOMUMAX32: 12939 case X86::ATOMUMAX64: 12940 case X86::ATOMUMIN8: 12941 case X86::ATOMUMIN16: 12942 case X86::ATOMUMIN32: 12943 case X86::ATOMUMIN64: { 12944 unsigned CMPOpc; 12945 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc); 12946 12947 BuildMI(mainMBB, DL, TII->get(CMPOpc)) 12948 .addReg(SrcReg) 12949 .addReg(AccReg); 12950 12951 if (Subtarget->hasCMov()) { 12952 if (VT != MVT::i8) { 12953 // Native support 12954 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1) 12955 .addReg(SrcReg) 12956 .addReg(AccReg); 12957 } else { 12958 // Promote i8 to i32 to use CMOV32 12959 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32); 12960 unsigned SrcReg32 = MRI.createVirtualRegister(RC32); 12961 unsigned AccReg32 = MRI.createVirtualRegister(RC32); 12962 unsigned t2 = MRI.createVirtualRegister(RC32); 12963 12964 unsigned Undef = MRI.createVirtualRegister(RC32); 12965 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef); 12966 12967 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32) 12968 .addReg(Undef) 12969 .addReg(SrcReg) 12970 .addImm(X86::sub_8bit); 12971 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32) 12972 .addReg(Undef) 12973 .addReg(AccReg) 12974 .addImm(X86::sub_8bit); 12975 12976 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2) 12977 .addReg(SrcReg32) 12978 .addReg(AccReg32); 12979 12980 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1) 12981 .addReg(t2, 0, X86::sub_8bit); 12982 } 12983 } else { 12984 // Use pseudo select and lower them. 12985 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && 12986 "Invalid atomic-load-op transformation!"); 12987 unsigned SelOpc = getPseudoCMOVOpc(VT); 12988 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc); 12989 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!"); 12990 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1) 12991 .addReg(SrcReg).addReg(AccReg) 12992 .addImm(CC); 12993 mainMBB = EmitLoweredSelect(MIB, mainMBB); 12994 } 12995 break; 12996 } 12997 } 12998 12999 // Copy AccPhyReg back from virtual register. 13000 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg) 13001 .addReg(AccReg); 13002 13003 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 13004 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 13005 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 13006 MIB.addReg(t1); 13007 MIB.setMemRefs(MMOBegin, MMOEnd); 13008 13009 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 13010 13011 mainMBB->addSuccessor(origMainMBB); 13012 mainMBB->addSuccessor(sinkMBB); 13013 13014 // sinkMBB: 13015 sinkMBB->addLiveIn(AccPhyReg); 13016 13017 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13018 TII->get(TargetOpcode::COPY), DstReg) 13019 .addReg(AccPhyReg); 13020 13021 MI->eraseFromParent(); 13022 return sinkMBB; 13023} 13024 13025// EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic 13026// instructions. They will be translated into a spin-loop or compare-exchange 13027// loop from 13028// 13029// ... 13030// dst = atomic-fetch-op MI.addr, MI.val 13031// ... 13032// 13033// to 13034// 13035// ... 13036// EAX = LOAD [MI.addr + 0] 13037// EDX = LOAD [MI.addr + 4] 13038// loop: 13039// EBX = OP MI.val.lo, EAX 13040// ECX = OP MI.val.hi, EDX 13041// LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 13042// JNE loop 13043// sink: 13044// dst = EDX:EAX 13045// ... 13046MachineBasicBlock * 13047X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI, 13048 MachineBasicBlock *MBB) const { 13049 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13050 DebugLoc DL = MI->getDebugLoc(); 13051 13052 MachineFunction *MF = MBB->getParent(); 13053 MachineRegisterInfo &MRI = MF->getRegInfo(); 13054 13055 const BasicBlock *BB = MBB->getBasicBlock(); 13056 MachineFunction::iterator I = MBB; 13057 ++I; 13058 13059 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 && 13060 "Unexpected number of operands"); 13061 13062 assert(MI->hasOneMemOperand() && 13063 "Expected atomic-load-op32 to have one memoperand"); 13064 13065 // Memory Reference 13066 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 13067 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 13068 13069 unsigned DstLoReg, DstHiReg; 13070 unsigned SrcLoReg, SrcHiReg; 13071 unsigned MemOpndSlot; 13072 13073 unsigned CurOp = 0; 13074 13075 DstLoReg = MI->getOperand(CurOp++).getReg(); 13076 DstHiReg = MI->getOperand(CurOp++).getReg(); 13077 MemOpndSlot = CurOp; 13078 CurOp += X86::AddrNumOperands; 13079 SrcLoReg = MI->getOperand(CurOp++).getReg(); 13080 SrcHiReg = MI->getOperand(CurOp++).getReg(); 13081 13082 const TargetRegisterClass *RC = &X86::GR32RegClass; 13083 const TargetRegisterClass *RC8 = &X86::GR8RegClass; 13084 13085 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B; 13086 unsigned LOADOpc = X86::MOV32rm; 13087 13088 // For the atomic load-arith operator, we generate 13089 // 13090 // thisMBB: 13091 // EAX = LOAD [MI.addr + 0] 13092 // EDX = LOAD [MI.addr + 4] 13093 // mainMBB: 13094 // EBX = OP MI.vallo, EAX 13095 // ECX = OP MI.valhi, EDX 13096 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined] 13097 // JNE mainMBB 13098 // sinkMBB: 13099 13100 MachineBasicBlock *thisMBB = MBB; 13101 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 13102 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 13103 MF->insert(I, mainMBB); 13104 MF->insert(I, sinkMBB); 13105 13106 MachineInstrBuilder MIB; 13107 13108 // Transfer the remainder of BB and its successor edges to sinkMBB. 13109 sinkMBB->splice(sinkMBB->begin(), MBB, 13110 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 13111 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 13112 13113 // thisMBB: 13114 // Lo 13115 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX); 13116 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 13117 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 13118 MIB.setMemRefs(MMOBegin, MMOEnd); 13119 // Hi 13120 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX); 13121 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 13122 if (i == X86::AddrDisp) 13123 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32) 13124 else 13125 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 13126 } 13127 MIB.setMemRefs(MMOBegin, MMOEnd); 13128 13129 thisMBB->addSuccessor(mainMBB); 13130 13131 // mainMBB: 13132 MachineBasicBlock *origMainMBB = mainMBB; 13133 mainMBB->addLiveIn(X86::EAX); 13134 mainMBB->addLiveIn(X86::EDX); 13135 13136 // Copy EDX:EAX as they are used more than once. 13137 unsigned LoReg = MRI.createVirtualRegister(RC); 13138 unsigned HiReg = MRI.createVirtualRegister(RC); 13139 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX); 13140 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX); 13141 13142 unsigned t1L = MRI.createVirtualRegister(RC); 13143 unsigned t1H = MRI.createVirtualRegister(RC); 13144 13145 unsigned Opc = MI->getOpcode(); 13146 switch (Opc) { 13147 default: 13148 llvm_unreachable("Unhandled atomic-load-op6432 opcode!"); 13149 case X86::ATOMAND6432: 13150 case X86::ATOMOR6432: 13151 case X86::ATOMXOR6432: 13152 case X86::ATOMADD6432: 13153 case X86::ATOMSUB6432: { 13154 unsigned HiOpc; 13155 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 13156 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg); 13157 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg); 13158 break; 13159 } 13160 case X86::ATOMNAND6432: { 13161 unsigned HiOpc, NOTOpc; 13162 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc); 13163 unsigned t2L = MRI.createVirtualRegister(RC); 13164 unsigned t2H = MRI.createVirtualRegister(RC); 13165 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg); 13166 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg); 13167 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L); 13168 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H); 13169 break; 13170 } 13171 case X86::ATOMMAX6432: 13172 case X86::ATOMMIN6432: 13173 case X86::ATOMUMAX6432: 13174 case X86::ATOMUMIN6432: { 13175 unsigned HiOpc; 13176 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 13177 unsigned cL = MRI.createVirtualRegister(RC8); 13178 unsigned cH = MRI.createVirtualRegister(RC8); 13179 unsigned cL32 = MRI.createVirtualRegister(RC); 13180 unsigned cH32 = MRI.createVirtualRegister(RC); 13181 unsigned cc = MRI.createVirtualRegister(RC); 13182 // cl := cmp src_lo, lo 13183 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr)) 13184 .addReg(SrcLoReg).addReg(LoReg); 13185 BuildMI(mainMBB, DL, TII->get(LoOpc), cL); 13186 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL); 13187 // ch := cmp src_hi, hi 13188 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr)) 13189 .addReg(SrcHiReg).addReg(HiReg); 13190 BuildMI(mainMBB, DL, TII->get(HiOpc), cH); 13191 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH); 13192 // cc := if (src_hi == hi) ? cl : ch; 13193 if (Subtarget->hasCMov()) { 13194 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc) 13195 .addReg(cH32).addReg(cL32); 13196 } else { 13197 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc) 13198 .addReg(cH32).addReg(cL32) 13199 .addImm(X86::COND_E); 13200 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13201 } 13202 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc); 13203 if (Subtarget->hasCMov()) { 13204 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L) 13205 .addReg(SrcLoReg).addReg(LoReg); 13206 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H) 13207 .addReg(SrcHiReg).addReg(HiReg); 13208 } else { 13209 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L) 13210 .addReg(SrcLoReg).addReg(LoReg) 13211 .addImm(X86::COND_NE); 13212 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13213 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H) 13214 .addReg(SrcHiReg).addReg(HiReg) 13215 .addImm(X86::COND_NE); 13216 mainMBB = EmitLoweredSelect(MIB, mainMBB); 13217 } 13218 break; 13219 } 13220 case X86::ATOMSWAP6432: { 13221 unsigned HiOpc; 13222 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); 13223 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg); 13224 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg); 13225 break; 13226 } 13227 } 13228 13229 // Copy EDX:EAX back from HiReg:LoReg 13230 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg); 13231 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg); 13232 // Copy ECX:EBX from t1H:t1L 13233 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L); 13234 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H); 13235 13236 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc)); 13237 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 13238 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 13239 MIB.setMemRefs(MMOBegin, MMOEnd); 13240 13241 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB); 13242 13243 mainMBB->addSuccessor(origMainMBB); 13244 mainMBB->addSuccessor(sinkMBB); 13245 13246 // sinkMBB: 13247 sinkMBB->addLiveIn(X86::EAX); 13248 sinkMBB->addLiveIn(X86::EDX); 13249 13250 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13251 TII->get(TargetOpcode::COPY), DstLoReg) 13252 .addReg(X86::EAX); 13253 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13254 TII->get(TargetOpcode::COPY), DstHiReg) 13255 .addReg(X86::EDX); 13256 13257 MI->eraseFromParent(); 13258 return sinkMBB; 13259} 13260 13261// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 13262// or XMM0_V32I8 in AVX all of this code can be replaced with that 13263// in the .td file. 13264static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, 13265 const TargetInstrInfo *TII) { 13266 unsigned Opc; 13267 switch (MI->getOpcode()) { 13268 default: llvm_unreachable("illegal opcode!"); 13269 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break; 13270 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break; 13271 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break; 13272 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break; 13273 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break; 13274 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break; 13275 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break; 13276 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break; 13277 } 13278 13279 DebugLoc dl = MI->getDebugLoc(); 13280 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 13281 13282 unsigned NumArgs = MI->getNumOperands(); 13283 for (unsigned i = 1; i < NumArgs; ++i) { 13284 MachineOperand &Op = MI->getOperand(i); 13285 if (!(Op.isReg() && Op.isImplicit())) 13286 MIB.addOperand(Op); 13287 } 13288 if (MI->hasOneMemOperand()) 13289 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 13290 13291 BuildMI(*BB, MI, dl, 13292 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 13293 .addReg(X86::XMM0); 13294 13295 MI->eraseFromParent(); 13296 return BB; 13297} 13298 13299// FIXME: Custom handling because TableGen doesn't support multiple implicit 13300// defs in an instruction pattern 13301static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, 13302 const TargetInstrInfo *TII) { 13303 unsigned Opc; 13304 switch (MI->getOpcode()) { 13305 default: llvm_unreachable("illegal opcode!"); 13306 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break; 13307 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break; 13308 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break; 13309 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break; 13310 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break; 13311 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break; 13312 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break; 13313 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break; 13314 } 13315 13316 DebugLoc dl = MI->getDebugLoc(); 13317 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 13318 13319 unsigned NumArgs = MI->getNumOperands(); // remove the results 13320 for (unsigned i = 1; i < NumArgs; ++i) { 13321 MachineOperand &Op = MI->getOperand(i); 13322 if (!(Op.isReg() && Op.isImplicit())) 13323 MIB.addOperand(Op); 13324 } 13325 if (MI->hasOneMemOperand()) 13326 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 13327 13328 BuildMI(*BB, MI, dl, 13329 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg()) 13330 .addReg(X86::ECX); 13331 13332 MI->eraseFromParent(); 13333 return BB; 13334} 13335 13336static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB, 13337 const TargetInstrInfo *TII, 13338 const X86Subtarget* Subtarget) { 13339 DebugLoc dl = MI->getDebugLoc(); 13340 13341 // Address into RAX/EAX, other two args into ECX, EDX. 13342 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 13343 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 13344 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 13345 for (int i = 0; i < X86::AddrNumOperands; ++i) 13346 MIB.addOperand(MI->getOperand(i)); 13347 13348 unsigned ValOps = X86::AddrNumOperands; 13349 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 13350 .addReg(MI->getOperand(ValOps).getReg()); 13351 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 13352 .addReg(MI->getOperand(ValOps+1).getReg()); 13353 13354 // The instruction doesn't actually take any operands though. 13355 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 13356 13357 MI->eraseFromParent(); // The pseudo is gone now. 13358 return BB; 13359} 13360 13361MachineBasicBlock * 13362X86TargetLowering::EmitVAARG64WithCustomInserter( 13363 MachineInstr *MI, 13364 MachineBasicBlock *MBB) const { 13365 // Emit va_arg instruction on X86-64. 13366 13367 // Operands to this pseudo-instruction: 13368 // 0 ) Output : destination address (reg) 13369 // 1-5) Input : va_list address (addr, i64mem) 13370 // 6 ) ArgSize : Size (in bytes) of vararg type 13371 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 13372 // 8 ) Align : Alignment of type 13373 // 9 ) EFLAGS (implicit-def) 13374 13375 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 13376 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 13377 13378 unsigned DestReg = MI->getOperand(0).getReg(); 13379 MachineOperand &Base = MI->getOperand(1); 13380 MachineOperand &Scale = MI->getOperand(2); 13381 MachineOperand &Index = MI->getOperand(3); 13382 MachineOperand &Disp = MI->getOperand(4); 13383 MachineOperand &Segment = MI->getOperand(5); 13384 unsigned ArgSize = MI->getOperand(6).getImm(); 13385 unsigned ArgMode = MI->getOperand(7).getImm(); 13386 unsigned Align = MI->getOperand(8).getImm(); 13387 13388 // Memory Reference 13389 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 13390 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 13391 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 13392 13393 // Machine Information 13394 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13395 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 13396 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 13397 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 13398 DebugLoc DL = MI->getDebugLoc(); 13399 13400 // struct va_list { 13401 // i32 gp_offset 13402 // i32 fp_offset 13403 // i64 overflow_area (address) 13404 // i64 reg_save_area (address) 13405 // } 13406 // sizeof(va_list) = 24 13407 // alignment(va_list) = 8 13408 13409 unsigned TotalNumIntRegs = 6; 13410 unsigned TotalNumXMMRegs = 8; 13411 bool UseGPOffset = (ArgMode == 1); 13412 bool UseFPOffset = (ArgMode == 2); 13413 unsigned MaxOffset = TotalNumIntRegs * 8 + 13414 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 13415 13416 /* Align ArgSize to a multiple of 8 */ 13417 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 13418 bool NeedsAlign = (Align > 8); 13419 13420 MachineBasicBlock *thisMBB = MBB; 13421 MachineBasicBlock *overflowMBB; 13422 MachineBasicBlock *offsetMBB; 13423 MachineBasicBlock *endMBB; 13424 13425 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 13426 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 13427 unsigned OffsetReg = 0; 13428 13429 if (!UseGPOffset && !UseFPOffset) { 13430 // If we only pull from the overflow region, we don't create a branch. 13431 // We don't need to alter control flow. 13432 OffsetDestReg = 0; // unused 13433 OverflowDestReg = DestReg; 13434 13435 offsetMBB = NULL; 13436 overflowMBB = thisMBB; 13437 endMBB = thisMBB; 13438 } else { 13439 // First emit code to check if gp_offset (or fp_offset) is below the bound. 13440 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 13441 // If not, pull from overflow_area. (branch to overflowMBB) 13442 // 13443 // thisMBB 13444 // | . 13445 // | . 13446 // offsetMBB overflowMBB 13447 // | . 13448 // | . 13449 // endMBB 13450 13451 // Registers for the PHI in endMBB 13452 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 13453 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 13454 13455 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 13456 MachineFunction *MF = MBB->getParent(); 13457 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13458 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13459 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13460 13461 MachineFunction::iterator MBBIter = MBB; 13462 ++MBBIter; 13463 13464 // Insert the new basic blocks 13465 MF->insert(MBBIter, offsetMBB); 13466 MF->insert(MBBIter, overflowMBB); 13467 MF->insert(MBBIter, endMBB); 13468 13469 // Transfer the remainder of MBB and its successor edges to endMBB. 13470 endMBB->splice(endMBB->begin(), thisMBB, 13471 llvm::next(MachineBasicBlock::iterator(MI)), 13472 thisMBB->end()); 13473 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 13474 13475 // Make offsetMBB and overflowMBB successors of thisMBB 13476 thisMBB->addSuccessor(offsetMBB); 13477 thisMBB->addSuccessor(overflowMBB); 13478 13479 // endMBB is a successor of both offsetMBB and overflowMBB 13480 offsetMBB->addSuccessor(endMBB); 13481 overflowMBB->addSuccessor(endMBB); 13482 13483 // Load the offset value into a register 13484 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 13485 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 13486 .addOperand(Base) 13487 .addOperand(Scale) 13488 .addOperand(Index) 13489 .addDisp(Disp, UseFPOffset ? 4 : 0) 13490 .addOperand(Segment) 13491 .setMemRefs(MMOBegin, MMOEnd); 13492 13493 // Check if there is enough room left to pull this argument. 13494 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 13495 .addReg(OffsetReg) 13496 .addImm(MaxOffset + 8 - ArgSizeA8); 13497 13498 // Branch to "overflowMBB" if offset >= max 13499 // Fall through to "offsetMBB" otherwise 13500 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 13501 .addMBB(overflowMBB); 13502 } 13503 13504 // In offsetMBB, emit code to use the reg_save_area. 13505 if (offsetMBB) { 13506 assert(OffsetReg != 0); 13507 13508 // Read the reg_save_area address. 13509 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 13510 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 13511 .addOperand(Base) 13512 .addOperand(Scale) 13513 .addOperand(Index) 13514 .addDisp(Disp, 16) 13515 .addOperand(Segment) 13516 .setMemRefs(MMOBegin, MMOEnd); 13517 13518 // Zero-extend the offset 13519 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 13520 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 13521 .addImm(0) 13522 .addReg(OffsetReg) 13523 .addImm(X86::sub_32bit); 13524 13525 // Add the offset to the reg_save_area to get the final address. 13526 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 13527 .addReg(OffsetReg64) 13528 .addReg(RegSaveReg); 13529 13530 // Compute the offset for the next argument 13531 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 13532 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 13533 .addReg(OffsetReg) 13534 .addImm(UseFPOffset ? 16 : 8); 13535 13536 // Store it back into the va_list. 13537 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 13538 .addOperand(Base) 13539 .addOperand(Scale) 13540 .addOperand(Index) 13541 .addDisp(Disp, UseFPOffset ? 4 : 0) 13542 .addOperand(Segment) 13543 .addReg(NextOffsetReg) 13544 .setMemRefs(MMOBegin, MMOEnd); 13545 13546 // Jump to endMBB 13547 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 13548 .addMBB(endMBB); 13549 } 13550 13551 // 13552 // Emit code to use overflow area 13553 // 13554 13555 // Load the overflow_area address into a register. 13556 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 13557 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 13558 .addOperand(Base) 13559 .addOperand(Scale) 13560 .addOperand(Index) 13561 .addDisp(Disp, 8) 13562 .addOperand(Segment) 13563 .setMemRefs(MMOBegin, MMOEnd); 13564 13565 // If we need to align it, do so. Otherwise, just copy the address 13566 // to OverflowDestReg. 13567 if (NeedsAlign) { 13568 // Align the overflow address 13569 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 13570 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 13571 13572 // aligned_addr = (addr + (align-1)) & ~(align-1) 13573 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 13574 .addReg(OverflowAddrReg) 13575 .addImm(Align-1); 13576 13577 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 13578 .addReg(TmpReg) 13579 .addImm(~(uint64_t)(Align-1)); 13580 } else { 13581 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 13582 .addReg(OverflowAddrReg); 13583 } 13584 13585 // Compute the next overflow address after this argument. 13586 // (the overflow address should be kept 8-byte aligned) 13587 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 13588 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 13589 .addReg(OverflowDestReg) 13590 .addImm(ArgSizeA8); 13591 13592 // Store the new overflow address. 13593 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 13594 .addOperand(Base) 13595 .addOperand(Scale) 13596 .addOperand(Index) 13597 .addDisp(Disp, 8) 13598 .addOperand(Segment) 13599 .addReg(NextAddrReg) 13600 .setMemRefs(MMOBegin, MMOEnd); 13601 13602 // If we branched, emit the PHI to the front of endMBB. 13603 if (offsetMBB) { 13604 BuildMI(*endMBB, endMBB->begin(), DL, 13605 TII->get(X86::PHI), DestReg) 13606 .addReg(OffsetDestReg).addMBB(offsetMBB) 13607 .addReg(OverflowDestReg).addMBB(overflowMBB); 13608 } 13609 13610 // Erase the pseudo instruction 13611 MI->eraseFromParent(); 13612 13613 return endMBB; 13614} 13615 13616MachineBasicBlock * 13617X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 13618 MachineInstr *MI, 13619 MachineBasicBlock *MBB) const { 13620 // Emit code to save XMM registers to the stack. The ABI says that the 13621 // number of registers to save is given in %al, so it's theoretically 13622 // possible to do an indirect jump trick to avoid saving all of them, 13623 // however this code takes a simpler approach and just executes all 13624 // of the stores if %al is non-zero. It's less code, and it's probably 13625 // easier on the hardware branch predictor, and stores aren't all that 13626 // expensive anyway. 13627 13628 // Create the new basic blocks. One block contains all the XMM stores, 13629 // and one block is the final destination regardless of whether any 13630 // stores were performed. 13631 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 13632 MachineFunction *F = MBB->getParent(); 13633 MachineFunction::iterator MBBIter = MBB; 13634 ++MBBIter; 13635 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 13636 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 13637 F->insert(MBBIter, XMMSaveMBB); 13638 F->insert(MBBIter, EndMBB); 13639 13640 // Transfer the remainder of MBB and its successor edges to EndMBB. 13641 EndMBB->splice(EndMBB->begin(), MBB, 13642 llvm::next(MachineBasicBlock::iterator(MI)), 13643 MBB->end()); 13644 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 13645 13646 // The original block will now fall through to the XMM save block. 13647 MBB->addSuccessor(XMMSaveMBB); 13648 // The XMMSaveMBB will fall through to the end block. 13649 XMMSaveMBB->addSuccessor(EndMBB); 13650 13651 // Now add the instructions. 13652 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13653 DebugLoc DL = MI->getDebugLoc(); 13654 13655 unsigned CountReg = MI->getOperand(0).getReg(); 13656 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 13657 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 13658 13659 if (!Subtarget->isTargetWin64()) { 13660 // If %al is 0, branch around the XMM save block. 13661 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 13662 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 13663 MBB->addSuccessor(EndMBB); 13664 } 13665 13666 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr; 13667 // In the XMM save block, save all the XMM argument registers. 13668 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 13669 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 13670 MachineMemOperand *MMO = 13671 F->getMachineMemOperand( 13672 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 13673 MachineMemOperand::MOStore, 13674 /*Size=*/16, /*Align=*/16); 13675 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 13676 .addFrameIndex(RegSaveFrameIndex) 13677 .addImm(/*Scale=*/1) 13678 .addReg(/*IndexReg=*/0) 13679 .addImm(/*Disp=*/Offset) 13680 .addReg(/*Segment=*/0) 13681 .addReg(MI->getOperand(i).getReg()) 13682 .addMemOperand(MMO); 13683 } 13684 13685 MI->eraseFromParent(); // The pseudo instruction is gone now. 13686 13687 return EndMBB; 13688} 13689 13690// The EFLAGS operand of SelectItr might be missing a kill marker 13691// because there were multiple uses of EFLAGS, and ISel didn't know 13692// which to mark. Figure out whether SelectItr should have had a 13693// kill marker, and set it if it should. Returns the correct kill 13694// marker value. 13695static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 13696 MachineBasicBlock* BB, 13697 const TargetRegisterInfo* TRI) { 13698 // Scan forward through BB for a use/def of EFLAGS. 13699 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 13700 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 13701 const MachineInstr& mi = *miI; 13702 if (mi.readsRegister(X86::EFLAGS)) 13703 return false; 13704 if (mi.definesRegister(X86::EFLAGS)) 13705 break; // Should have kill-flag - update below. 13706 } 13707 13708 // If we hit the end of the block, check whether EFLAGS is live into a 13709 // successor. 13710 if (miI == BB->end()) { 13711 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 13712 sEnd = BB->succ_end(); 13713 sItr != sEnd; ++sItr) { 13714 MachineBasicBlock* succ = *sItr; 13715 if (succ->isLiveIn(X86::EFLAGS)) 13716 return false; 13717 } 13718 } 13719 13720 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 13721 // out. SelectMI should have a kill flag on EFLAGS. 13722 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 13723 return true; 13724} 13725 13726MachineBasicBlock * 13727X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 13728 MachineBasicBlock *BB) const { 13729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13730 DebugLoc DL = MI->getDebugLoc(); 13731 13732 // To "insert" a SELECT_CC instruction, we actually have to insert the 13733 // diamond control-flow pattern. The incoming instruction knows the 13734 // destination vreg to set, the condition code register to branch on, the 13735 // true/false values to select between, and a branch opcode to use. 13736 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 13737 MachineFunction::iterator It = BB; 13738 ++It; 13739 13740 // thisMBB: 13741 // ... 13742 // TrueVal = ... 13743 // cmpTY ccX, r1, r2 13744 // bCC copy1MBB 13745 // fallthrough --> copy0MBB 13746 MachineBasicBlock *thisMBB = BB; 13747 MachineFunction *F = BB->getParent(); 13748 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 13749 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 13750 F->insert(It, copy0MBB); 13751 F->insert(It, sinkMBB); 13752 13753 // If the EFLAGS register isn't dead in the terminator, then claim that it's 13754 // live into the sink and copy blocks. 13755 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 13756 if (!MI->killsRegister(X86::EFLAGS) && 13757 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 13758 copy0MBB->addLiveIn(X86::EFLAGS); 13759 sinkMBB->addLiveIn(X86::EFLAGS); 13760 } 13761 13762 // Transfer the remainder of BB and its successor edges to sinkMBB. 13763 sinkMBB->splice(sinkMBB->begin(), BB, 13764 llvm::next(MachineBasicBlock::iterator(MI)), 13765 BB->end()); 13766 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 13767 13768 // Add the true and fallthrough blocks as its successors. 13769 BB->addSuccessor(copy0MBB); 13770 BB->addSuccessor(sinkMBB); 13771 13772 // Create the conditional branch instruction. 13773 unsigned Opc = 13774 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 13775 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 13776 13777 // copy0MBB: 13778 // %FalseValue = ... 13779 // # fallthrough to sinkMBB 13780 copy0MBB->addSuccessor(sinkMBB); 13781 13782 // sinkMBB: 13783 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 13784 // ... 13785 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 13786 TII->get(X86::PHI), MI->getOperand(0).getReg()) 13787 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 13788 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 13789 13790 MI->eraseFromParent(); // The pseudo instruction is gone now. 13791 return sinkMBB; 13792} 13793 13794MachineBasicBlock * 13795X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 13796 bool Is64Bit) const { 13797 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13798 DebugLoc DL = MI->getDebugLoc(); 13799 MachineFunction *MF = BB->getParent(); 13800 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 13801 13802 assert(getTargetMachine().Options.EnableSegmentedStacks); 13803 13804 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 13805 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 13806 13807 // BB: 13808 // ... [Till the alloca] 13809 // If stacklet is not large enough, jump to mallocMBB 13810 // 13811 // bumpMBB: 13812 // Allocate by subtracting from RSP 13813 // Jump to continueMBB 13814 // 13815 // mallocMBB: 13816 // Allocate by call to runtime 13817 // 13818 // continueMBB: 13819 // ... 13820 // [rest of original BB] 13821 // 13822 13823 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13824 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13825 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 13826 13827 MachineRegisterInfo &MRI = MF->getRegInfo(); 13828 const TargetRegisterClass *AddrRegClass = 13829 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 13830 13831 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 13832 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 13833 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 13834 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 13835 sizeVReg = MI->getOperand(1).getReg(), 13836 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 13837 13838 MachineFunction::iterator MBBIter = BB; 13839 ++MBBIter; 13840 13841 MF->insert(MBBIter, bumpMBB); 13842 MF->insert(MBBIter, mallocMBB); 13843 MF->insert(MBBIter, continueMBB); 13844 13845 continueMBB->splice(continueMBB->begin(), BB, llvm::next 13846 (MachineBasicBlock::iterator(MI)), BB->end()); 13847 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 13848 13849 // Add code to the main basic block to check if the stack limit has been hit, 13850 // and if so, jump to mallocMBB otherwise to bumpMBB. 13851 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 13852 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 13853 .addReg(tmpSPVReg).addReg(sizeVReg); 13854 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 13855 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 13856 .addReg(SPLimitVReg); 13857 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 13858 13859 // bumpMBB simply decreases the stack pointer, since we know the current 13860 // stacklet has enough space. 13861 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 13862 .addReg(SPLimitVReg); 13863 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 13864 .addReg(SPLimitVReg); 13865 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 13866 13867 // Calls into a routine in libgcc to allocate more space from the heap. 13868 const uint32_t *RegMask = 13869 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 13870 if (Is64Bit) { 13871 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 13872 .addReg(sizeVReg); 13873 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 13874 .addExternalSymbol("__morestack_allocate_stack_space") 13875 .addRegMask(RegMask) 13876 .addReg(X86::RDI, RegState::Implicit) 13877 .addReg(X86::RAX, RegState::ImplicitDefine); 13878 } else { 13879 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 13880 .addImm(12); 13881 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 13882 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 13883 .addExternalSymbol("__morestack_allocate_stack_space") 13884 .addRegMask(RegMask) 13885 .addReg(X86::EAX, RegState::ImplicitDefine); 13886 } 13887 13888 if (!Is64Bit) 13889 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 13890 .addImm(16); 13891 13892 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 13893 .addReg(Is64Bit ? X86::RAX : X86::EAX); 13894 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 13895 13896 // Set up the CFG correctly. 13897 BB->addSuccessor(bumpMBB); 13898 BB->addSuccessor(mallocMBB); 13899 mallocMBB->addSuccessor(continueMBB); 13900 bumpMBB->addSuccessor(continueMBB); 13901 13902 // Take care of the PHI nodes. 13903 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 13904 MI->getOperand(0).getReg()) 13905 .addReg(mallocPtrVReg).addMBB(mallocMBB) 13906 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 13907 13908 // Delete the original pseudo instruction. 13909 MI->eraseFromParent(); 13910 13911 // And we're done. 13912 return continueMBB; 13913} 13914 13915MachineBasicBlock * 13916X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 13917 MachineBasicBlock *BB) const { 13918 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 13919 DebugLoc DL = MI->getDebugLoc(); 13920 13921 assert(!Subtarget->isTargetEnvMacho()); 13922 13923 // The lowering is pretty easy: we're just emitting the call to _alloca. The 13924 // non-trivial part is impdef of ESP. 13925 13926 if (Subtarget->isTargetWin64()) { 13927 if (Subtarget->isTargetCygMing()) { 13928 // ___chkstk(Mingw64): 13929 // Clobbers R10, R11, RAX and EFLAGS. 13930 // Updates RSP. 13931 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 13932 .addExternalSymbol("___chkstk") 13933 .addReg(X86::RAX, RegState::Implicit) 13934 .addReg(X86::RSP, RegState::Implicit) 13935 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 13936 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 13937 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 13938 } else { 13939 // __chkstk(MSVCRT): does not update stack pointer. 13940 // Clobbers R10, R11 and EFLAGS. 13941 // FIXME: RAX(allocated size) might be reused and not killed. 13942 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 13943 .addExternalSymbol("__chkstk") 13944 .addReg(X86::RAX, RegState::Implicit) 13945 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 13946 // RAX has the offset to subtracted from RSP. 13947 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 13948 .addReg(X86::RSP) 13949 .addReg(X86::RAX); 13950 } 13951 } else { 13952 const char *StackProbeSymbol = 13953 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 13954 13955 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 13956 .addExternalSymbol(StackProbeSymbol) 13957 .addReg(X86::EAX, RegState::Implicit) 13958 .addReg(X86::ESP, RegState::Implicit) 13959 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 13960 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 13961 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 13962 } 13963 13964 MI->eraseFromParent(); // The pseudo instruction is gone now. 13965 return BB; 13966} 13967 13968MachineBasicBlock * 13969X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 13970 MachineBasicBlock *BB) const { 13971 // This is pretty easy. We're taking the value that we received from 13972 // our load from the relocation, sticking it in either RDI (x86-64) 13973 // or EAX and doing an indirect call. The return value will then 13974 // be in the normal return register. 13975 const X86InstrInfo *TII 13976 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 13977 DebugLoc DL = MI->getDebugLoc(); 13978 MachineFunction *F = BB->getParent(); 13979 13980 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 13981 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 13982 13983 // Get a register mask for the lowered call. 13984 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 13985 // proper register mask. 13986 const uint32_t *RegMask = 13987 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 13988 if (Subtarget->is64Bit()) { 13989 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 13990 TII->get(X86::MOV64rm), X86::RDI) 13991 .addReg(X86::RIP) 13992 .addImm(0).addReg(0) 13993 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 13994 MI->getOperand(3).getTargetFlags()) 13995 .addReg(0); 13996 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 13997 addDirectMem(MIB, X86::RDI); 13998 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 13999 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 14000 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 14001 TII->get(X86::MOV32rm), X86::EAX) 14002 .addReg(0) 14003 .addImm(0).addReg(0) 14004 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 14005 MI->getOperand(3).getTargetFlags()) 14006 .addReg(0); 14007 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 14008 addDirectMem(MIB, X86::EAX); 14009 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 14010 } else { 14011 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 14012 TII->get(X86::MOV32rm), X86::EAX) 14013 .addReg(TII->getGlobalBaseReg(F)) 14014 .addImm(0).addReg(0) 14015 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 14016 MI->getOperand(3).getTargetFlags()) 14017 .addReg(0); 14018 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 14019 addDirectMem(MIB, X86::EAX); 14020 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 14021 } 14022 14023 MI->eraseFromParent(); // The pseudo instruction is gone now. 14024 return BB; 14025} 14026 14027MachineBasicBlock * 14028X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, 14029 MachineBasicBlock *MBB) const { 14030 DebugLoc DL = MI->getDebugLoc(); 14031 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14032 14033 MachineFunction *MF = MBB->getParent(); 14034 MachineRegisterInfo &MRI = MF->getRegInfo(); 14035 14036 const BasicBlock *BB = MBB->getBasicBlock(); 14037 MachineFunction::iterator I = MBB; 14038 ++I; 14039 14040 // Memory Reference 14041 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14042 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14043 14044 unsigned DstReg; 14045 unsigned MemOpndSlot = 0; 14046 14047 unsigned CurOp = 0; 14048 14049 DstReg = MI->getOperand(CurOp++).getReg(); 14050 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 14051 assert(RC->hasType(MVT::i32) && "Invalid destination!"); 14052 unsigned mainDstReg = MRI.createVirtualRegister(RC); 14053 unsigned restoreDstReg = MRI.createVirtualRegister(RC); 14054 14055 MemOpndSlot = CurOp; 14056 14057 MVT PVT = getPointerTy(); 14058 assert((PVT == MVT::i64 || PVT == MVT::i32) && 14059 "Invalid Pointer Size!"); 14060 14061 // For v = setjmp(buf), we generate 14062 // 14063 // thisMBB: 14064 // buf[LabelOffset] = restoreMBB 14065 // SjLjSetup restoreMBB 14066 // 14067 // mainMBB: 14068 // v_main = 0 14069 // 14070 // sinkMBB: 14071 // v = phi(main, restore) 14072 // 14073 // restoreMBB: 14074 // v_restore = 1 14075 14076 MachineBasicBlock *thisMBB = MBB; 14077 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 14078 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 14079 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB); 14080 MF->insert(I, mainMBB); 14081 MF->insert(I, sinkMBB); 14082 MF->push_back(restoreMBB); 14083 14084 MachineInstrBuilder MIB; 14085 14086 // Transfer the remainder of BB and its successor edges to sinkMBB. 14087 sinkMBB->splice(sinkMBB->begin(), MBB, 14088 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 14089 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 14090 14091 // thisMBB: 14092 unsigned PtrStoreOpc = 0; 14093 unsigned LabelReg = 0; 14094 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 14095 Reloc::Model RM = getTargetMachine().getRelocationModel(); 14096 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) && 14097 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC); 14098 14099 // Prepare IP either in reg or imm. 14100 if (!UseImmLabel) { 14101 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr; 14102 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); 14103 LabelReg = MRI.createVirtualRegister(PtrRC); 14104 if (Subtarget->is64Bit()) { 14105 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg) 14106 .addReg(X86::RIP) 14107 .addImm(0) 14108 .addReg(0) 14109 .addMBB(restoreMBB) 14110 .addReg(0); 14111 } else { 14112 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII); 14113 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg) 14114 .addReg(XII->getGlobalBaseReg(MF)) 14115 .addImm(0) 14116 .addReg(0) 14117 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference()) 14118 .addReg(0); 14119 } 14120 } else 14121 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi; 14122 // Store IP 14123 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc)); 14124 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14125 if (i == X86::AddrDisp) 14126 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset); 14127 else 14128 MIB.addOperand(MI->getOperand(MemOpndSlot + i)); 14129 } 14130 if (!UseImmLabel) 14131 MIB.addReg(LabelReg); 14132 else 14133 MIB.addMBB(restoreMBB); 14134 MIB.setMemRefs(MMOBegin, MMOEnd); 14135 // Setup 14136 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup)) 14137 .addMBB(restoreMBB); 14138 MIB.addRegMask(RegInfo->getNoPreservedMask()); 14139 thisMBB->addSuccessor(mainMBB); 14140 thisMBB->addSuccessor(restoreMBB); 14141 14142 // mainMBB: 14143 // EAX = 0 14144 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg); 14145 mainMBB->addSuccessor(sinkMBB); 14146 14147 // sinkMBB: 14148 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 14149 TII->get(X86::PHI), DstReg) 14150 .addReg(mainDstReg).addMBB(mainMBB) 14151 .addReg(restoreDstReg).addMBB(restoreMBB); 14152 14153 // restoreMBB: 14154 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1); 14155 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB); 14156 restoreMBB->addSuccessor(sinkMBB); 14157 14158 MI->eraseFromParent(); 14159 return sinkMBB; 14160} 14161 14162MachineBasicBlock * 14163X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, 14164 MachineBasicBlock *MBB) const { 14165 DebugLoc DL = MI->getDebugLoc(); 14166 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14167 14168 MachineFunction *MF = MBB->getParent(); 14169 MachineRegisterInfo &MRI = MF->getRegInfo(); 14170 14171 // Memory Reference 14172 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 14173 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 14174 14175 MVT PVT = getPointerTy(); 14176 assert((PVT == MVT::i64 || PVT == MVT::i32) && 14177 "Invalid Pointer Size!"); 14178 14179 const TargetRegisterClass *RC = 14180 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass; 14181 unsigned Tmp = MRI.createVirtualRegister(RC); 14182 // Since FP is only updated here but NOT referenced, it's treated as GPR. 14183 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; 14184 unsigned SP = RegInfo->getStackRegister(); 14185 14186 MachineInstrBuilder MIB; 14187 14188 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 14189 const int64_t SPOffset = 2 * PVT.getStoreSize(); 14190 14191 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm; 14192 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r; 14193 14194 // Reload FP 14195 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP); 14196 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) 14197 MIB.addOperand(MI->getOperand(i)); 14198 MIB.setMemRefs(MMOBegin, MMOEnd); 14199 // Reload IP 14200 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp); 14201 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14202 if (i == X86::AddrDisp) 14203 MIB.addDisp(MI->getOperand(i), LabelOffset); 14204 else 14205 MIB.addOperand(MI->getOperand(i)); 14206 } 14207 MIB.setMemRefs(MMOBegin, MMOEnd); 14208 // Reload SP 14209 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP); 14210 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) { 14211 if (i == X86::AddrDisp) 14212 MIB.addDisp(MI->getOperand(i), SPOffset); 14213 else 14214 MIB.addOperand(MI->getOperand(i)); 14215 } 14216 MIB.setMemRefs(MMOBegin, MMOEnd); 14217 // Jump 14218 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp); 14219 14220 MI->eraseFromParent(); 14221 return MBB; 14222} 14223 14224MachineBasicBlock * 14225X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 14226 MachineBasicBlock *BB) const { 14227 switch (MI->getOpcode()) { 14228 default: llvm_unreachable("Unexpected instr type to insert"); 14229 case X86::TAILJMPd64: 14230 case X86::TAILJMPr64: 14231 case X86::TAILJMPm64: 14232 llvm_unreachable("TAILJMP64 would not be touched here."); 14233 case X86::TCRETURNdi64: 14234 case X86::TCRETURNri64: 14235 case X86::TCRETURNmi64: 14236 return BB; 14237 case X86::WIN_ALLOCA: 14238 return EmitLoweredWinAlloca(MI, BB); 14239 case X86::SEG_ALLOCA_32: 14240 return EmitLoweredSegAlloca(MI, BB, false); 14241 case X86::SEG_ALLOCA_64: 14242 return EmitLoweredSegAlloca(MI, BB, true); 14243 case X86::TLSCall_32: 14244 case X86::TLSCall_64: 14245 return EmitLoweredTLSCall(MI, BB); 14246 case X86::CMOV_GR8: 14247 case X86::CMOV_FR32: 14248 case X86::CMOV_FR64: 14249 case X86::CMOV_V4F32: 14250 case X86::CMOV_V2F64: 14251 case X86::CMOV_V2I64: 14252 case X86::CMOV_V8F32: 14253 case X86::CMOV_V4F64: 14254 case X86::CMOV_V4I64: 14255 case X86::CMOV_GR16: 14256 case X86::CMOV_GR32: 14257 case X86::CMOV_RFP32: 14258 case X86::CMOV_RFP64: 14259 case X86::CMOV_RFP80: 14260 return EmitLoweredSelect(MI, BB); 14261 14262 case X86::FP32_TO_INT16_IN_MEM: 14263 case X86::FP32_TO_INT32_IN_MEM: 14264 case X86::FP32_TO_INT64_IN_MEM: 14265 case X86::FP64_TO_INT16_IN_MEM: 14266 case X86::FP64_TO_INT32_IN_MEM: 14267 case X86::FP64_TO_INT64_IN_MEM: 14268 case X86::FP80_TO_INT16_IN_MEM: 14269 case X86::FP80_TO_INT32_IN_MEM: 14270 case X86::FP80_TO_INT64_IN_MEM: { 14271 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 14272 DebugLoc DL = MI->getDebugLoc(); 14273 14274 // Change the floating point control register to use "round towards zero" 14275 // mode when truncating to an integer value. 14276 MachineFunction *F = BB->getParent(); 14277 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 14278 addFrameReference(BuildMI(*BB, MI, DL, 14279 TII->get(X86::FNSTCW16m)), CWFrameIdx); 14280 14281 // Load the old value of the high byte of the control word... 14282 unsigned OldCW = 14283 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 14284 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 14285 CWFrameIdx); 14286 14287 // Set the high part to be round to zero... 14288 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 14289 .addImm(0xC7F); 14290 14291 // Reload the modified control word now... 14292 addFrameReference(BuildMI(*BB, MI, DL, 14293 TII->get(X86::FLDCW16m)), CWFrameIdx); 14294 14295 // Restore the memory image of control word to original value 14296 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 14297 .addReg(OldCW); 14298 14299 // Get the X86 opcode to use. 14300 unsigned Opc; 14301 switch (MI->getOpcode()) { 14302 default: llvm_unreachable("illegal opcode!"); 14303 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 14304 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 14305 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 14306 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 14307 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 14308 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 14309 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 14310 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 14311 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 14312 } 14313 14314 X86AddressMode AM; 14315 MachineOperand &Op = MI->getOperand(0); 14316 if (Op.isReg()) { 14317 AM.BaseType = X86AddressMode::RegBase; 14318 AM.Base.Reg = Op.getReg(); 14319 } else { 14320 AM.BaseType = X86AddressMode::FrameIndexBase; 14321 AM.Base.FrameIndex = Op.getIndex(); 14322 } 14323 Op = MI->getOperand(1); 14324 if (Op.isImm()) 14325 AM.Scale = Op.getImm(); 14326 Op = MI->getOperand(2); 14327 if (Op.isImm()) 14328 AM.IndexReg = Op.getImm(); 14329 Op = MI->getOperand(3); 14330 if (Op.isGlobal()) { 14331 AM.GV = Op.getGlobal(); 14332 } else { 14333 AM.Disp = Op.getImm(); 14334 } 14335 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 14336 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 14337 14338 // Reload the original control word now. 14339 addFrameReference(BuildMI(*BB, MI, DL, 14340 TII->get(X86::FLDCW16m)), CWFrameIdx); 14341 14342 MI->eraseFromParent(); // The pseudo instruction is gone now. 14343 return BB; 14344 } 14345 // String/text processing lowering. 14346 case X86::PCMPISTRM128REG: 14347 case X86::VPCMPISTRM128REG: 14348 case X86::PCMPISTRM128MEM: 14349 case X86::VPCMPISTRM128MEM: 14350 case X86::PCMPESTRM128REG: 14351 case X86::VPCMPESTRM128REG: 14352 case X86::PCMPESTRM128MEM: 14353 case X86::VPCMPESTRM128MEM: 14354 assert(Subtarget->hasSSE42() && 14355 "Target must have SSE4.2 or AVX features enabled"); 14356 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo()); 14357 14358 // String/text processing lowering. 14359 case X86::PCMPISTRIREG: 14360 case X86::VPCMPISTRIREG: 14361 case X86::PCMPISTRIMEM: 14362 case X86::VPCMPISTRIMEM: 14363 case X86::PCMPESTRIREG: 14364 case X86::VPCMPESTRIREG: 14365 case X86::PCMPESTRIMEM: 14366 case X86::VPCMPESTRIMEM: 14367 assert(Subtarget->hasSSE42() && 14368 "Target must have SSE4.2 or AVX features enabled"); 14369 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo()); 14370 14371 // Thread synchronization. 14372 case X86::MONITOR: 14373 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget); 14374 14375 // xbegin 14376 case X86::XBEGIN: 14377 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo()); 14378 14379 // Atomic Lowering. 14380 case X86::ATOMAND8: 14381 case X86::ATOMAND16: 14382 case X86::ATOMAND32: 14383 case X86::ATOMAND64: 14384 // Fall through 14385 case X86::ATOMOR8: 14386 case X86::ATOMOR16: 14387 case X86::ATOMOR32: 14388 case X86::ATOMOR64: 14389 // Fall through 14390 case X86::ATOMXOR16: 14391 case X86::ATOMXOR8: 14392 case X86::ATOMXOR32: 14393 case X86::ATOMXOR64: 14394 // Fall through 14395 case X86::ATOMNAND8: 14396 case X86::ATOMNAND16: 14397 case X86::ATOMNAND32: 14398 case X86::ATOMNAND64: 14399 // Fall through 14400 case X86::ATOMMAX8: 14401 case X86::ATOMMAX16: 14402 case X86::ATOMMAX32: 14403 case X86::ATOMMAX64: 14404 // Fall through 14405 case X86::ATOMMIN8: 14406 case X86::ATOMMIN16: 14407 case X86::ATOMMIN32: 14408 case X86::ATOMMIN64: 14409 // Fall through 14410 case X86::ATOMUMAX8: 14411 case X86::ATOMUMAX16: 14412 case X86::ATOMUMAX32: 14413 case X86::ATOMUMAX64: 14414 // Fall through 14415 case X86::ATOMUMIN8: 14416 case X86::ATOMUMIN16: 14417 case X86::ATOMUMIN32: 14418 case X86::ATOMUMIN64: 14419 return EmitAtomicLoadArith(MI, BB); 14420 14421 // This group does 64-bit operations on a 32-bit host. 14422 case X86::ATOMAND6432: 14423 case X86::ATOMOR6432: 14424 case X86::ATOMXOR6432: 14425 case X86::ATOMNAND6432: 14426 case X86::ATOMADD6432: 14427 case X86::ATOMSUB6432: 14428 case X86::ATOMMAX6432: 14429 case X86::ATOMMIN6432: 14430 case X86::ATOMUMAX6432: 14431 case X86::ATOMUMIN6432: 14432 case X86::ATOMSWAP6432: 14433 return EmitAtomicLoadArith6432(MI, BB); 14434 14435 case X86::VASTART_SAVE_XMM_REGS: 14436 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 14437 14438 case X86::VAARG_64: 14439 return EmitVAARG64WithCustomInserter(MI, BB); 14440 14441 case X86::EH_SjLj_SetJmp32: 14442 case X86::EH_SjLj_SetJmp64: 14443 return emitEHSjLjSetJmp(MI, BB); 14444 14445 case X86::EH_SjLj_LongJmp32: 14446 case X86::EH_SjLj_LongJmp64: 14447 return emitEHSjLjLongJmp(MI, BB); 14448 } 14449} 14450 14451//===----------------------------------------------------------------------===// 14452// X86 Optimization Hooks 14453//===----------------------------------------------------------------------===// 14454 14455void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 14456 APInt &KnownZero, 14457 APInt &KnownOne, 14458 const SelectionDAG &DAG, 14459 unsigned Depth) const { 14460 unsigned BitWidth = KnownZero.getBitWidth(); 14461 unsigned Opc = Op.getOpcode(); 14462 assert((Opc >= ISD::BUILTIN_OP_END || 14463 Opc == ISD::INTRINSIC_WO_CHAIN || 14464 Opc == ISD::INTRINSIC_W_CHAIN || 14465 Opc == ISD::INTRINSIC_VOID) && 14466 "Should use MaskedValueIsZero if you don't know whether Op" 14467 " is a target node!"); 14468 14469 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 14470 switch (Opc) { 14471 default: break; 14472 case X86ISD::ADD: 14473 case X86ISD::SUB: 14474 case X86ISD::ADC: 14475 case X86ISD::SBB: 14476 case X86ISD::SMUL: 14477 case X86ISD::UMUL: 14478 case X86ISD::INC: 14479 case X86ISD::DEC: 14480 case X86ISD::OR: 14481 case X86ISD::XOR: 14482 case X86ISD::AND: 14483 // These nodes' second result is a boolean. 14484 if (Op.getResNo() == 0) 14485 break; 14486 // Fallthrough 14487 case X86ISD::SETCC: 14488 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 14489 break; 14490 case ISD::INTRINSIC_WO_CHAIN: { 14491 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 14492 unsigned NumLoBits = 0; 14493 switch (IntId) { 14494 default: break; 14495 case Intrinsic::x86_sse_movmsk_ps: 14496 case Intrinsic::x86_avx_movmsk_ps_256: 14497 case Intrinsic::x86_sse2_movmsk_pd: 14498 case Intrinsic::x86_avx_movmsk_pd_256: 14499 case Intrinsic::x86_mmx_pmovmskb: 14500 case Intrinsic::x86_sse2_pmovmskb_128: 14501 case Intrinsic::x86_avx2_pmovmskb: { 14502 // High bits of movmskp{s|d}, pmovmskb are known zero. 14503 switch (IntId) { 14504 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 14505 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 14506 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 14507 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 14508 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 14509 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 14510 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 14511 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 14512 } 14513 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 14514 break; 14515 } 14516 } 14517 break; 14518 } 14519 } 14520} 14521 14522unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 14523 unsigned Depth) const { 14524 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 14525 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 14526 return Op.getValueType().getScalarType().getSizeInBits(); 14527 14528 // Fallback case. 14529 return 1; 14530} 14531 14532/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 14533/// node is a GlobalAddress + offset. 14534bool X86TargetLowering::isGAPlusOffset(SDNode *N, 14535 const GlobalValue* &GA, 14536 int64_t &Offset) const { 14537 if (N->getOpcode() == X86ISD::Wrapper) { 14538 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 14539 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 14540 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 14541 return true; 14542 } 14543 } 14544 return TargetLowering::isGAPlusOffset(N, GA, Offset); 14545} 14546 14547/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 14548/// same as extracting the high 128-bit part of 256-bit vector and then 14549/// inserting the result into the low part of a new 256-bit vector 14550static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 14551 EVT VT = SVOp->getValueType(0); 14552 unsigned NumElems = VT.getVectorNumElements(); 14553 14554 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 14555 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 14556 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 14557 SVOp->getMaskElt(j) >= 0) 14558 return false; 14559 14560 return true; 14561} 14562 14563/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 14564/// same as extracting the low 128-bit part of 256-bit vector and then 14565/// inserting the result into the high part of a new 256-bit vector 14566static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 14567 EVT VT = SVOp->getValueType(0); 14568 unsigned NumElems = VT.getVectorNumElements(); 14569 14570 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 14571 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 14572 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 14573 SVOp->getMaskElt(j) >= 0) 14574 return false; 14575 14576 return true; 14577} 14578 14579/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 14580static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 14581 TargetLowering::DAGCombinerInfo &DCI, 14582 const X86Subtarget* Subtarget) { 14583 DebugLoc dl = N->getDebugLoc(); 14584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 14585 SDValue V1 = SVOp->getOperand(0); 14586 SDValue V2 = SVOp->getOperand(1); 14587 EVT VT = SVOp->getValueType(0); 14588 unsigned NumElems = VT.getVectorNumElements(); 14589 14590 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 14591 V2.getOpcode() == ISD::CONCAT_VECTORS) { 14592 // 14593 // 0,0,0,... 14594 // | 14595 // V UNDEF BUILD_VECTOR UNDEF 14596 // \ / \ / 14597 // CONCAT_VECTOR CONCAT_VECTOR 14598 // \ / 14599 // \ / 14600 // RESULT: V + zero extended 14601 // 14602 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 14603 V2.getOperand(1).getOpcode() != ISD::UNDEF || 14604 V1.getOperand(1).getOpcode() != ISD::UNDEF) 14605 return SDValue(); 14606 14607 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 14608 return SDValue(); 14609 14610 // To match the shuffle mask, the first half of the mask should 14611 // be exactly the first vector, and all the rest a splat with the 14612 // first element of the second one. 14613 for (unsigned i = 0; i != NumElems/2; ++i) 14614 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 14615 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 14616 return SDValue(); 14617 14618 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 14619 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 14620 if (Ld->hasNUsesOfValue(1, 0)) { 14621 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 14622 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 14623 SDValue ResNode = 14624 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 14625 Ld->getMemoryVT(), 14626 Ld->getPointerInfo(), 14627 Ld->getAlignment(), 14628 false/*isVolatile*/, true/*ReadMem*/, 14629 false/*WriteMem*/); 14630 14631 // Make sure the newly-created LOAD is in the same position as Ld in 14632 // terms of dependency. We create a TokenFactor for Ld and ResNode, 14633 // and update uses of Ld's output chain to use the TokenFactor. 14634 if (Ld->hasAnyUseOfValue(1)) { 14635 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 14636 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1)); 14637 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain); 14638 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1), 14639 SDValue(ResNode.getNode(), 1)); 14640 } 14641 14642 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 14643 } 14644 } 14645 14646 // Emit a zeroed vector and insert the desired subvector on its 14647 // first half. 14648 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 14649 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 14650 return DCI.CombineTo(N, InsV); 14651 } 14652 14653 //===--------------------------------------------------------------------===// 14654 // Combine some shuffles into subvector extracts and inserts: 14655 // 14656 14657 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 14658 if (isShuffleHigh128VectorInsertLow(SVOp)) { 14659 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 14660 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 14661 return DCI.CombineTo(N, InsV); 14662 } 14663 14664 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 14665 if (isShuffleLow128VectorInsertHigh(SVOp)) { 14666 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 14667 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 14668 return DCI.CombineTo(N, InsV); 14669 } 14670 14671 return SDValue(); 14672} 14673 14674/// PerformShuffleCombine - Performs several different shuffle combines. 14675static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 14676 TargetLowering::DAGCombinerInfo &DCI, 14677 const X86Subtarget *Subtarget) { 14678 DebugLoc dl = N->getDebugLoc(); 14679 EVT VT = N->getValueType(0); 14680 14681 // Don't create instructions with illegal types after legalize types has run. 14682 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14683 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 14684 return SDValue(); 14685 14686 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 14687 if (Subtarget->hasFp256() && VT.is256BitVector() && 14688 N->getOpcode() == ISD::VECTOR_SHUFFLE) 14689 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 14690 14691 // Only handle 128 wide vector from here on. 14692 if (!VT.is128BitVector()) 14693 return SDValue(); 14694 14695 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 14696 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 14697 // consecutive, non-overlapping, and in the right order. 14698 SmallVector<SDValue, 16> Elts; 14699 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 14700 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 14701 14702 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 14703} 14704 14705/// PerformTruncateCombine - Converts truncate operation to 14706/// a sequence of vector shuffle operations. 14707/// It is possible when we truncate 256-bit vector to 128-bit vector 14708static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 14709 TargetLowering::DAGCombinerInfo &DCI, 14710 const X86Subtarget *Subtarget) { 14711 return SDValue(); 14712} 14713 14714/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 14715/// specific shuffle of a load can be folded into a single element load. 14716/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 14717/// shuffles have been customed lowered so we need to handle those here. 14718static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 14719 TargetLowering::DAGCombinerInfo &DCI) { 14720 if (DCI.isBeforeLegalizeOps()) 14721 return SDValue(); 14722 14723 SDValue InVec = N->getOperand(0); 14724 SDValue EltNo = N->getOperand(1); 14725 14726 if (!isa<ConstantSDNode>(EltNo)) 14727 return SDValue(); 14728 14729 EVT VT = InVec.getValueType(); 14730 14731 bool HasShuffleIntoBitcast = false; 14732 if (InVec.getOpcode() == ISD::BITCAST) { 14733 // Don't duplicate a load with other uses. 14734 if (!InVec.hasOneUse()) 14735 return SDValue(); 14736 EVT BCVT = InVec.getOperand(0).getValueType(); 14737 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 14738 return SDValue(); 14739 InVec = InVec.getOperand(0); 14740 HasShuffleIntoBitcast = true; 14741 } 14742 14743 if (!isTargetShuffle(InVec.getOpcode())) 14744 return SDValue(); 14745 14746 // Don't duplicate a load with other uses. 14747 if (!InVec.hasOneUse()) 14748 return SDValue(); 14749 14750 SmallVector<int, 16> ShuffleMask; 14751 bool UnaryShuffle; 14752 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask, 14753 UnaryShuffle)) 14754 return SDValue(); 14755 14756 // Select the input vector, guarding against out of range extract vector. 14757 unsigned NumElems = VT.getVectorNumElements(); 14758 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 14759 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 14760 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 14761 : InVec.getOperand(1); 14762 14763 // If inputs to shuffle are the same for both ops, then allow 2 uses 14764 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 14765 14766 if (LdNode.getOpcode() == ISD::BITCAST) { 14767 // Don't duplicate a load with other uses. 14768 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 14769 return SDValue(); 14770 14771 AllowedUses = 1; // only allow 1 load use if we have a bitcast 14772 LdNode = LdNode.getOperand(0); 14773 } 14774 14775 if (!ISD::isNormalLoad(LdNode.getNode())) 14776 return SDValue(); 14777 14778 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 14779 14780 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 14781 return SDValue(); 14782 14783 if (HasShuffleIntoBitcast) { 14784 // If there's a bitcast before the shuffle, check if the load type and 14785 // alignment is valid. 14786 unsigned Align = LN0->getAlignment(); 14787 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14788 unsigned NewAlign = TLI.getDataLayout()-> 14789 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 14790 14791 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 14792 return SDValue(); 14793 } 14794 14795 // All checks match so transform back to vector_shuffle so that DAG combiner 14796 // can finish the job 14797 DebugLoc dl = N->getDebugLoc(); 14798 14799 // Create shuffle node taking into account the case that its a unary shuffle 14800 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 14801 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 14802 InVec.getOperand(0), Shuffle, 14803 &ShuffleMask[0]); 14804 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 14805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 14806 EltNo); 14807} 14808 14809/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 14810/// generation and convert it from being a bunch of shuffles and extracts 14811/// to a simple store and scalar loads to extract the elements. 14812static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 14813 TargetLowering::DAGCombinerInfo &DCI) { 14814 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 14815 if (NewOp.getNode()) 14816 return NewOp; 14817 14818 SDValue InputVector = N->getOperand(0); 14819 // Detect whether we are trying to convert from mmx to i32 and the bitcast 14820 // from mmx to v2i32 has a single usage. 14821 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST && 14822 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx && 14823 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32) 14824 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(), 14825 N->getValueType(0), 14826 InputVector.getNode()->getOperand(0)); 14827 14828 // Only operate on vectors of 4 elements, where the alternative shuffling 14829 // gets to be more expensive. 14830 if (InputVector.getValueType() != MVT::v4i32) 14831 return SDValue(); 14832 14833 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 14834 // single use which is a sign-extend or zero-extend, and all elements are 14835 // used. 14836 SmallVector<SDNode *, 4> Uses; 14837 unsigned ExtractedElements = 0; 14838 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 14839 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 14840 if (UI.getUse().getResNo() != InputVector.getResNo()) 14841 return SDValue(); 14842 14843 SDNode *Extract = *UI; 14844 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 14845 return SDValue(); 14846 14847 if (Extract->getValueType(0) != MVT::i32) 14848 return SDValue(); 14849 if (!Extract->hasOneUse()) 14850 return SDValue(); 14851 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 14852 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 14853 return SDValue(); 14854 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 14855 return SDValue(); 14856 14857 // Record which element was extracted. 14858 ExtractedElements |= 14859 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 14860 14861 Uses.push_back(Extract); 14862 } 14863 14864 // If not all the elements were used, this may not be worthwhile. 14865 if (ExtractedElements != 15) 14866 return SDValue(); 14867 14868 // Ok, we've now decided to do the transformation. 14869 DebugLoc dl = InputVector.getDebugLoc(); 14870 14871 // Store the value to a temporary stack slot. 14872 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 14873 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 14874 MachinePointerInfo(), false, false, 0); 14875 14876 // Replace each use (extract) with a load of the appropriate element. 14877 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 14878 UE = Uses.end(); UI != UE; ++UI) { 14879 SDNode *Extract = *UI; 14880 14881 // cOMpute the element's address. 14882 SDValue Idx = Extract->getOperand(1); 14883 unsigned EltSize = 14884 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 14885 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 14886 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14887 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 14888 14889 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 14890 StackPtr, OffsetVal); 14891 14892 // Load the scalar. 14893 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 14894 ScalarAddr, MachinePointerInfo(), 14895 false, false, false, 0); 14896 14897 // Replace the exact with the load. 14898 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 14899 } 14900 14901 // The replacement was made in place; don't return anything. 14902 return SDValue(); 14903} 14904 14905/// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match. 14906static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, 14907 SDValue RHS, SelectionDAG &DAG, 14908 const X86Subtarget *Subtarget) { 14909 if (!VT.isVector()) 14910 return 0; 14911 14912 switch (VT.getSimpleVT().SimpleTy) { 14913 default: return 0; 14914 case MVT::v32i8: 14915 case MVT::v16i16: 14916 case MVT::v8i32: 14917 if (!Subtarget->hasAVX2()) 14918 return 0; 14919 case MVT::v16i8: 14920 case MVT::v8i16: 14921 case MVT::v4i32: 14922 if (!Subtarget->hasSSE2()) 14923 return 0; 14924 } 14925 14926 // SSE2 has only a small subset of the operations. 14927 bool hasUnsigned = Subtarget->hasSSE41() || 14928 (Subtarget->hasSSE2() && VT == MVT::v16i8); 14929 bool hasSigned = Subtarget->hasSSE41() || 14930 (Subtarget->hasSSE2() && VT == MVT::v8i16); 14931 14932 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 14933 14934 // Check for x CC y ? x : y. 14935 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 14936 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 14937 switch (CC) { 14938 default: break; 14939 case ISD::SETULT: 14940 case ISD::SETULE: 14941 return hasUnsigned ? X86ISD::UMIN : 0; 14942 case ISD::SETUGT: 14943 case ISD::SETUGE: 14944 return hasUnsigned ? X86ISD::UMAX : 0; 14945 case ISD::SETLT: 14946 case ISD::SETLE: 14947 return hasSigned ? X86ISD::SMIN : 0; 14948 case ISD::SETGT: 14949 case ISD::SETGE: 14950 return hasSigned ? X86ISD::SMAX : 0; 14951 } 14952 // Check for x CC y ? y : x -- a min/max with reversed arms. 14953 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 14954 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 14955 switch (CC) { 14956 default: break; 14957 case ISD::SETULT: 14958 case ISD::SETULE: 14959 return hasUnsigned ? X86ISD::UMAX : 0; 14960 case ISD::SETUGT: 14961 case ISD::SETUGE: 14962 return hasUnsigned ? X86ISD::UMIN : 0; 14963 case ISD::SETLT: 14964 case ISD::SETLE: 14965 return hasSigned ? X86ISD::SMAX : 0; 14966 case ISD::SETGT: 14967 case ISD::SETGE: 14968 return hasSigned ? X86ISD::SMIN : 0; 14969 } 14970 } 14971 14972 return 0; 14973} 14974 14975/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 14976/// nodes. 14977static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 14978 TargetLowering::DAGCombinerInfo &DCI, 14979 const X86Subtarget *Subtarget) { 14980 DebugLoc DL = N->getDebugLoc(); 14981 SDValue Cond = N->getOperand(0); 14982 // Get the LHS/RHS of the select. 14983 SDValue LHS = N->getOperand(1); 14984 SDValue RHS = N->getOperand(2); 14985 EVT VT = LHS.getValueType(); 14986 14987 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 14988 // instructions match the semantics of the common C idiom x<y?x:y but not 14989 // x<=y?x:y, because of how they handle negative zero (which can be 14990 // ignored in unsafe-math mode). 14991 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 14992 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 14993 (Subtarget->hasSSE2() || 14994 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 14995 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 14996 14997 unsigned Opcode = 0; 14998 // Check for x CC y ? x : y. 14999 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 15000 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 15001 switch (CC) { 15002 default: break; 15003 case ISD::SETULT: 15004 // Converting this to a min would handle NaNs incorrectly, and swapping 15005 // the operands would cause it to handle comparisons between positive 15006 // and negative zero incorrectly. 15007 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 15008 if (!DAG.getTarget().Options.UnsafeFPMath && 15009 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 15010 break; 15011 std::swap(LHS, RHS); 15012 } 15013 Opcode = X86ISD::FMIN; 15014 break; 15015 case ISD::SETOLE: 15016 // Converting this to a min would handle comparisons between positive 15017 // and negative zero incorrectly. 15018 if (!DAG.getTarget().Options.UnsafeFPMath && 15019 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 15020 break; 15021 Opcode = X86ISD::FMIN; 15022 break; 15023 case ISD::SETULE: 15024 // Converting this to a min would handle both negative zeros and NaNs 15025 // incorrectly, but we can swap the operands to fix both. 15026 std::swap(LHS, RHS); 15027 case ISD::SETOLT: 15028 case ISD::SETLT: 15029 case ISD::SETLE: 15030 Opcode = X86ISD::FMIN; 15031 break; 15032 15033 case ISD::SETOGE: 15034 // Converting this to a max would handle comparisons between positive 15035 // and negative zero incorrectly. 15036 if (!DAG.getTarget().Options.UnsafeFPMath && 15037 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 15038 break; 15039 Opcode = X86ISD::FMAX; 15040 break; 15041 case ISD::SETUGT: 15042 // Converting this to a max would handle NaNs incorrectly, and swapping 15043 // the operands would cause it to handle comparisons between positive 15044 // and negative zero incorrectly. 15045 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 15046 if (!DAG.getTarget().Options.UnsafeFPMath && 15047 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 15048 break; 15049 std::swap(LHS, RHS); 15050 } 15051 Opcode = X86ISD::FMAX; 15052 break; 15053 case ISD::SETUGE: 15054 // Converting this to a max would handle both negative zeros and NaNs 15055 // incorrectly, but we can swap the operands to fix both. 15056 std::swap(LHS, RHS); 15057 case ISD::SETOGT: 15058 case ISD::SETGT: 15059 case ISD::SETGE: 15060 Opcode = X86ISD::FMAX; 15061 break; 15062 } 15063 // Check for x CC y ? y : x -- a min/max with reversed arms. 15064 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 15065 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 15066 switch (CC) { 15067 default: break; 15068 case ISD::SETOGE: 15069 // Converting this to a min would handle comparisons between positive 15070 // and negative zero incorrectly, and swapping the operands would 15071 // cause it to handle NaNs incorrectly. 15072 if (!DAG.getTarget().Options.UnsafeFPMath && 15073 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 15074 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 15075 break; 15076 std::swap(LHS, RHS); 15077 } 15078 Opcode = X86ISD::FMIN; 15079 break; 15080 case ISD::SETUGT: 15081 // Converting this to a min would handle NaNs incorrectly. 15082 if (!DAG.getTarget().Options.UnsafeFPMath && 15083 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 15084 break; 15085 Opcode = X86ISD::FMIN; 15086 break; 15087 case ISD::SETUGE: 15088 // Converting this to a min would handle both negative zeros and NaNs 15089 // incorrectly, but we can swap the operands to fix both. 15090 std::swap(LHS, RHS); 15091 case ISD::SETOGT: 15092 case ISD::SETGT: 15093 case ISD::SETGE: 15094 Opcode = X86ISD::FMIN; 15095 break; 15096 15097 case ISD::SETULT: 15098 // Converting this to a max would handle NaNs incorrectly. 15099 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 15100 break; 15101 Opcode = X86ISD::FMAX; 15102 break; 15103 case ISD::SETOLE: 15104 // Converting this to a max would handle comparisons between positive 15105 // and negative zero incorrectly, and swapping the operands would 15106 // cause it to handle NaNs incorrectly. 15107 if (!DAG.getTarget().Options.UnsafeFPMath && 15108 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 15109 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 15110 break; 15111 std::swap(LHS, RHS); 15112 } 15113 Opcode = X86ISD::FMAX; 15114 break; 15115 case ISD::SETULE: 15116 // Converting this to a max would handle both negative zeros and NaNs 15117 // incorrectly, but we can swap the operands to fix both. 15118 std::swap(LHS, RHS); 15119 case ISD::SETOLT: 15120 case ISD::SETLT: 15121 case ISD::SETLE: 15122 Opcode = X86ISD::FMAX; 15123 break; 15124 } 15125 } 15126 15127 if (Opcode) 15128 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 15129 } 15130 15131 // If this is a select between two integer constants, try to do some 15132 // optimizations. 15133 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 15134 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 15135 // Don't do this for crazy integer types. 15136 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 15137 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 15138 // so that TrueC (the true value) is larger than FalseC. 15139 bool NeedsCondInvert = false; 15140 15141 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 15142 // Efficiently invertible. 15143 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 15144 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 15145 isa<ConstantSDNode>(Cond.getOperand(1))))) { 15146 NeedsCondInvert = true; 15147 std::swap(TrueC, FalseC); 15148 } 15149 15150 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 15151 if (FalseC->getAPIntValue() == 0 && 15152 TrueC->getAPIntValue().isPowerOf2()) { 15153 if (NeedsCondInvert) // Invert the condition if needed. 15154 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 15155 DAG.getConstant(1, Cond.getValueType())); 15156 15157 // Zero extend the condition if needed. 15158 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 15159 15160 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 15161 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 15162 DAG.getConstant(ShAmt, MVT::i8)); 15163 } 15164 15165 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 15166 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 15167 if (NeedsCondInvert) // Invert the condition if needed. 15168 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 15169 DAG.getConstant(1, Cond.getValueType())); 15170 15171 // Zero extend the condition if needed. 15172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 15173 FalseC->getValueType(0), Cond); 15174 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15175 SDValue(FalseC, 0)); 15176 } 15177 15178 // Optimize cases that will turn into an LEA instruction. This requires 15179 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 15180 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 15181 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 15182 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 15183 15184 bool isFastMultiplier = false; 15185 if (Diff < 10) { 15186 switch ((unsigned char)Diff) { 15187 default: break; 15188 case 1: // result = add base, cond 15189 case 2: // result = lea base( , cond*2) 15190 case 3: // result = lea base(cond, cond*2) 15191 case 4: // result = lea base( , cond*4) 15192 case 5: // result = lea base(cond, cond*4) 15193 case 8: // result = lea base( , cond*8) 15194 case 9: // result = lea base(cond, cond*8) 15195 isFastMultiplier = true; 15196 break; 15197 } 15198 } 15199 15200 if (isFastMultiplier) { 15201 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 15202 if (NeedsCondInvert) // Invert the condition if needed. 15203 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 15204 DAG.getConstant(1, Cond.getValueType())); 15205 15206 // Zero extend the condition if needed. 15207 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 15208 Cond); 15209 // Scale the condition by the difference. 15210 if (Diff != 1) 15211 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 15212 DAG.getConstant(Diff, Cond.getValueType())); 15213 15214 // Add the base if non-zero. 15215 if (FalseC->getAPIntValue() != 0) 15216 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15217 SDValue(FalseC, 0)); 15218 return Cond; 15219 } 15220 } 15221 } 15222 } 15223 15224 // Canonicalize max and min: 15225 // (x > y) ? x : y -> (x >= y) ? x : y 15226 // (x < y) ? x : y -> (x <= y) ? x : y 15227 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 15228 // the need for an extra compare 15229 // against zero. e.g. 15230 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 15231 // subl %esi, %edi 15232 // testl %edi, %edi 15233 // movl $0, %eax 15234 // cmovgl %edi, %eax 15235 // => 15236 // xorl %eax, %eax 15237 // subl %esi, $edi 15238 // cmovsl %eax, %edi 15239 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 15240 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 15241 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 15242 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 15243 switch (CC) { 15244 default: break; 15245 case ISD::SETLT: 15246 case ISD::SETGT: { 15247 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 15248 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 15249 Cond.getOperand(0), Cond.getOperand(1), NewCC); 15250 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 15251 } 15252 } 15253 } 15254 15255 // Match VSELECTs into subs with unsigned saturation. 15256 if (!DCI.isBeforeLegalize() && 15257 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC && 15258 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors. 15259 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) || 15260 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) { 15261 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 15262 15263 // Check if one of the arms of the VSELECT is a zero vector. If it's on the 15264 // left side invert the predicate to simplify logic below. 15265 SDValue Other; 15266 if (ISD::isBuildVectorAllZeros(LHS.getNode())) { 15267 Other = RHS; 15268 CC = ISD::getSetCCInverse(CC, true); 15269 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) { 15270 Other = LHS; 15271 } 15272 15273 if (Other.getNode() && Other->getNumOperands() == 2 && 15274 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) { 15275 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1); 15276 SDValue CondRHS = Cond->getOperand(1); 15277 15278 // Look for a general sub with unsigned saturation first. 15279 // x >= y ? x-y : 0 --> subus x, y 15280 // x > y ? x-y : 0 --> subus x, y 15281 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) && 15282 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS)) 15283 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS); 15284 15285 // If the RHS is a constant we have to reverse the const canonicalization. 15286 // x > C-1 ? x+-C : 0 --> subus x, C 15287 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD && 15288 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) { 15289 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue(); 15290 if (CondRHS.getConstantOperandVal(0) == -A-1) { 15291 SmallVector<SDValue, 32> V(VT.getVectorNumElements(), 15292 DAG.getConstant(-A, VT.getScalarType())); 15293 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, 15294 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 15295 V.data(), V.size())); 15296 } 15297 } 15298 15299 // Another special case: If C was a sign bit, the sub has been 15300 // canonicalized into a xor. 15301 // FIXME: Would it be better to use ComputeMaskedBits to determine whether 15302 // it's safe to decanonicalize the xor? 15303 // x s< 0 ? x^C : 0 --> subus x, C 15304 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR && 15305 ISD::isBuildVectorAllZeros(CondRHS.getNode()) && 15306 isSplatVector(OpRHS.getNode())) { 15307 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue(); 15308 if (A.isSignBit()) 15309 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS); 15310 } 15311 } 15312 } 15313 15314 // Try to match a min/max vector operation. 15315 if (!DCI.isBeforeLegalize() && 15316 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) 15317 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget)) 15318 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS); 15319 15320 // If we know that this node is legal then we know that it is going to be 15321 // matched by one of the SSE/AVX BLEND instructions. These instructions only 15322 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 15323 // to simplify previous instructions. 15324 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15325 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 15326 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) { 15327 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 15328 15329 // Don't optimize vector selects that map to mask-registers. 15330 if (BitWidth == 1) 15331 return SDValue(); 15332 15333 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 15334 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 15335 15336 APInt KnownZero, KnownOne; 15337 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 15338 DCI.isBeforeLegalizeOps()); 15339 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 15340 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 15341 DCI.CommitTargetLoweringOpt(TLO); 15342 } 15343 15344 return SDValue(); 15345} 15346 15347// Check whether a boolean test is testing a boolean value generated by 15348// X86ISD::SETCC. If so, return the operand of that SETCC and proper condition 15349// code. 15350// 15351// Simplify the following patterns: 15352// (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or 15353// (Op (CMP (SETCC Cond EFLAGS) 0) NEQ) 15354// to (Op EFLAGS Cond) 15355// 15356// (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or 15357// (Op (CMP (SETCC Cond EFLAGS) 1) NEQ) 15358// to (Op EFLAGS !Cond) 15359// 15360// where Op could be BRCOND or CMOV. 15361// 15362static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) { 15363 // Quit if not CMP and SUB with its value result used. 15364 if (Cmp.getOpcode() != X86ISD::CMP && 15365 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0))) 15366 return SDValue(); 15367 15368 // Quit if not used as a boolean value. 15369 if (CC != X86::COND_E && CC != X86::COND_NE) 15370 return SDValue(); 15371 15372 // Check CMP operands. One of them should be 0 or 1 and the other should be 15373 // an SetCC or extended from it. 15374 SDValue Op1 = Cmp.getOperand(0); 15375 SDValue Op2 = Cmp.getOperand(1); 15376 15377 SDValue SetCC; 15378 const ConstantSDNode* C = 0; 15379 bool needOppositeCond = (CC == X86::COND_E); 15380 15381 if ((C = dyn_cast<ConstantSDNode>(Op1))) 15382 SetCC = Op2; 15383 else if ((C = dyn_cast<ConstantSDNode>(Op2))) 15384 SetCC = Op1; 15385 else // Quit if all operands are not constants. 15386 return SDValue(); 15387 15388 if (C->getZExtValue() == 1) 15389 needOppositeCond = !needOppositeCond; 15390 else if (C->getZExtValue() != 0) 15391 // Quit if the constant is neither 0 or 1. 15392 return SDValue(); 15393 15394 // Skip 'zext' node. 15395 if (SetCC.getOpcode() == ISD::ZERO_EXTEND) 15396 SetCC = SetCC.getOperand(0); 15397 15398 switch (SetCC.getOpcode()) { 15399 case X86ISD::SETCC: 15400 // Set the condition code or opposite one if necessary. 15401 CC = X86::CondCode(SetCC.getConstantOperandVal(0)); 15402 if (needOppositeCond) 15403 CC = X86::GetOppositeBranchCondition(CC); 15404 return SetCC.getOperand(1); 15405 case X86ISD::CMOV: { 15406 // Check whether false/true value has canonical one, i.e. 0 or 1. 15407 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0)); 15408 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1)); 15409 // Quit if true value is not a constant. 15410 if (!TVal) 15411 return SDValue(); 15412 // Quit if false value is not a constant. 15413 if (!FVal) { 15414 // A special case for rdrand, where 0 is set if false cond is found. 15415 SDValue Op = SetCC.getOperand(0); 15416 if (Op.getOpcode() != X86ISD::RDRAND) 15417 return SDValue(); 15418 } 15419 // Quit if false value is not the constant 0 or 1. 15420 bool FValIsFalse = true; 15421 if (FVal && FVal->getZExtValue() != 0) { 15422 if (FVal->getZExtValue() != 1) 15423 return SDValue(); 15424 // If FVal is 1, opposite cond is needed. 15425 needOppositeCond = !needOppositeCond; 15426 FValIsFalse = false; 15427 } 15428 // Quit if TVal is not the constant opposite of FVal. 15429 if (FValIsFalse && TVal->getZExtValue() != 1) 15430 return SDValue(); 15431 if (!FValIsFalse && TVal->getZExtValue() != 0) 15432 return SDValue(); 15433 CC = X86::CondCode(SetCC.getConstantOperandVal(2)); 15434 if (needOppositeCond) 15435 CC = X86::GetOppositeBranchCondition(CC); 15436 return SetCC.getOperand(3); 15437 } 15438 } 15439 15440 return SDValue(); 15441} 15442 15443/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 15444static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 15445 TargetLowering::DAGCombinerInfo &DCI, 15446 const X86Subtarget *Subtarget) { 15447 DebugLoc DL = N->getDebugLoc(); 15448 15449 // If the flag operand isn't dead, don't touch this CMOV. 15450 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 15451 return SDValue(); 15452 15453 SDValue FalseOp = N->getOperand(0); 15454 SDValue TrueOp = N->getOperand(1); 15455 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 15456 SDValue Cond = N->getOperand(3); 15457 15458 if (CC == X86::COND_E || CC == X86::COND_NE) { 15459 switch (Cond.getOpcode()) { 15460 default: break; 15461 case X86ISD::BSR: 15462 case X86ISD::BSF: 15463 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 15464 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 15465 return (CC == X86::COND_E) ? FalseOp : TrueOp; 15466 } 15467 } 15468 15469 SDValue Flags; 15470 15471 Flags = checkBoolTestSetCCCombine(Cond, CC); 15472 if (Flags.getNode() && 15473 // Extra check as FCMOV only supports a subset of X86 cond. 15474 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) { 15475 SDValue Ops[] = { FalseOp, TrueOp, 15476 DAG.getConstant(CC, MVT::i8), Flags }; 15477 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), 15478 Ops, array_lengthof(Ops)); 15479 } 15480 15481 // If this is a select between two integer constants, try to do some 15482 // optimizations. Note that the operands are ordered the opposite of SELECT 15483 // operands. 15484 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 15485 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 15486 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 15487 // larger than FalseC (the false value). 15488 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 15489 CC = X86::GetOppositeBranchCondition(CC); 15490 std::swap(TrueC, FalseC); 15491 std::swap(TrueOp, FalseOp); 15492 } 15493 15494 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 15495 // This is efficient for any integer data type (including i8/i16) and 15496 // shift amount. 15497 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 15498 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 15499 DAG.getConstant(CC, MVT::i8), Cond); 15500 15501 // Zero extend the condition if needed. 15502 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 15503 15504 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 15505 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 15506 DAG.getConstant(ShAmt, MVT::i8)); 15507 if (N->getNumValues() == 2) // Dead flag value? 15508 return DCI.CombineTo(N, Cond, SDValue()); 15509 return Cond; 15510 } 15511 15512 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 15513 // for any integer data type, including i8/i16. 15514 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 15515 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 15516 DAG.getConstant(CC, MVT::i8), Cond); 15517 15518 // Zero extend the condition if needed. 15519 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 15520 FalseC->getValueType(0), Cond); 15521 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15522 SDValue(FalseC, 0)); 15523 15524 if (N->getNumValues() == 2) // Dead flag value? 15525 return DCI.CombineTo(N, Cond, SDValue()); 15526 return Cond; 15527 } 15528 15529 // Optimize cases that will turn into an LEA instruction. This requires 15530 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 15531 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 15532 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 15533 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 15534 15535 bool isFastMultiplier = false; 15536 if (Diff < 10) { 15537 switch ((unsigned char)Diff) { 15538 default: break; 15539 case 1: // result = add base, cond 15540 case 2: // result = lea base( , cond*2) 15541 case 3: // result = lea base(cond, cond*2) 15542 case 4: // result = lea base( , cond*4) 15543 case 5: // result = lea base(cond, cond*4) 15544 case 8: // result = lea base( , cond*8) 15545 case 9: // result = lea base(cond, cond*8) 15546 isFastMultiplier = true; 15547 break; 15548 } 15549 } 15550 15551 if (isFastMultiplier) { 15552 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 15553 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 15554 DAG.getConstant(CC, MVT::i8), Cond); 15555 // Zero extend the condition if needed. 15556 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 15557 Cond); 15558 // Scale the condition by the difference. 15559 if (Diff != 1) 15560 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 15561 DAG.getConstant(Diff, Cond.getValueType())); 15562 15563 // Add the base if non-zero. 15564 if (FalseC->getAPIntValue() != 0) 15565 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 15566 SDValue(FalseC, 0)); 15567 if (N->getNumValues() == 2) // Dead flag value? 15568 return DCI.CombineTo(N, Cond, SDValue()); 15569 return Cond; 15570 } 15571 } 15572 } 15573 } 15574 15575 // Handle these cases: 15576 // (select (x != c), e, c) -> select (x != c), e, x), 15577 // (select (x == c), c, e) -> select (x == c), x, e) 15578 // where the c is an integer constant, and the "select" is the combination 15579 // of CMOV and CMP. 15580 // 15581 // The rationale for this change is that the conditional-move from a constant 15582 // needs two instructions, however, conditional-move from a register needs 15583 // only one instruction. 15584 // 15585 // CAVEAT: By replacing a constant with a symbolic value, it may obscure 15586 // some instruction-combining opportunities. This opt needs to be 15587 // postponed as late as possible. 15588 // 15589 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { 15590 // the DCI.xxxx conditions are provided to postpone the optimization as 15591 // late as possible. 15592 15593 ConstantSDNode *CmpAgainst = 0; 15594 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) && 15595 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) && 15596 dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) { 15597 15598 if (CC == X86::COND_NE && 15599 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) { 15600 CC = X86::GetOppositeBranchCondition(CC); 15601 std::swap(TrueOp, FalseOp); 15602 } 15603 15604 if (CC == X86::COND_E && 15605 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) { 15606 SDValue Ops[] = { FalseOp, Cond.getOperand(0), 15607 DAG.getConstant(CC, MVT::i8), Cond }; 15608 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops, 15609 array_lengthof(Ops)); 15610 } 15611 } 15612 } 15613 15614 return SDValue(); 15615} 15616 15617/// PerformMulCombine - Optimize a single multiply with constant into two 15618/// in order to implement it with two cheaper instructions, e.g. 15619/// LEA + SHL, LEA + LEA. 15620static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 15621 TargetLowering::DAGCombinerInfo &DCI) { 15622 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 15623 return SDValue(); 15624 15625 EVT VT = N->getValueType(0); 15626 if (VT != MVT::i64) 15627 return SDValue(); 15628 15629 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 15630 if (!C) 15631 return SDValue(); 15632 uint64_t MulAmt = C->getZExtValue(); 15633 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 15634 return SDValue(); 15635 15636 uint64_t MulAmt1 = 0; 15637 uint64_t MulAmt2 = 0; 15638 if ((MulAmt % 9) == 0) { 15639 MulAmt1 = 9; 15640 MulAmt2 = MulAmt / 9; 15641 } else if ((MulAmt % 5) == 0) { 15642 MulAmt1 = 5; 15643 MulAmt2 = MulAmt / 5; 15644 } else if ((MulAmt % 3) == 0) { 15645 MulAmt1 = 3; 15646 MulAmt2 = MulAmt / 3; 15647 } 15648 if (MulAmt2 && 15649 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 15650 DebugLoc DL = N->getDebugLoc(); 15651 15652 if (isPowerOf2_64(MulAmt2) && 15653 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 15654 // If second multiplifer is pow2, issue it first. We want the multiply by 15655 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 15656 // is an add. 15657 std::swap(MulAmt1, MulAmt2); 15658 15659 SDValue NewMul; 15660 if (isPowerOf2_64(MulAmt1)) 15661 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 15662 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 15663 else 15664 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 15665 DAG.getConstant(MulAmt1, VT)); 15666 15667 if (isPowerOf2_64(MulAmt2)) 15668 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 15669 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 15670 else 15671 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 15672 DAG.getConstant(MulAmt2, VT)); 15673 15674 // Do not add new nodes to DAG combiner worklist. 15675 DCI.CombineTo(N, NewMul, false); 15676 } 15677 return SDValue(); 15678} 15679 15680static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 15681 SDValue N0 = N->getOperand(0); 15682 SDValue N1 = N->getOperand(1); 15683 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 15684 EVT VT = N0.getValueType(); 15685 15686 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 15687 // since the result of setcc_c is all zero's or all ones. 15688 if (VT.isInteger() && !VT.isVector() && 15689 N1C && N0.getOpcode() == ISD::AND && 15690 N0.getOperand(1).getOpcode() == ISD::Constant) { 15691 SDValue N00 = N0.getOperand(0); 15692 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 15693 ((N00.getOpcode() == ISD::ANY_EXTEND || 15694 N00.getOpcode() == ISD::ZERO_EXTEND) && 15695 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 15696 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 15697 APInt ShAmt = N1C->getAPIntValue(); 15698 Mask = Mask.shl(ShAmt); 15699 if (Mask != 0) 15700 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 15701 N00, DAG.getConstant(Mask, VT)); 15702 } 15703 } 15704 15705 // Hardware support for vector shifts is sparse which makes us scalarize the 15706 // vector operations in many cases. Also, on sandybridge ADD is faster than 15707 // shl. 15708 // (shl V, 1) -> add V,V 15709 if (isSplatVector(N1.getNode())) { 15710 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 15711 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 15712 // We shift all of the values by one. In many cases we do not have 15713 // hardware support for this operation. This is better expressed as an ADD 15714 // of two values. 15715 if (N1C && (1 == N1C->getZExtValue())) { 15716 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 15717 } 15718 } 15719 15720 return SDValue(); 15721} 15722 15723/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 15724/// when possible. 15725static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 15726 TargetLowering::DAGCombinerInfo &DCI, 15727 const X86Subtarget *Subtarget) { 15728 EVT VT = N->getValueType(0); 15729 if (N->getOpcode() == ISD::SHL) { 15730 SDValue V = PerformSHLCombine(N, DAG); 15731 if (V.getNode()) return V; 15732 } 15733 15734 // On X86 with SSE2 support, we can transform this to a vector shift if 15735 // all elements are shifted by the same amount. We can't do this in legalize 15736 // because the a constant vector is typically transformed to a constant pool 15737 // so we have no knowledge of the shift amount. 15738 if (!Subtarget->hasSSE2()) 15739 return SDValue(); 15740 15741 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 15742 (!Subtarget->hasInt256() || 15743 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 15744 return SDValue(); 15745 15746 SDValue ShAmtOp = N->getOperand(1); 15747 EVT EltVT = VT.getVectorElementType(); 15748 DebugLoc DL = N->getDebugLoc(); 15749 SDValue BaseShAmt = SDValue(); 15750 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 15751 unsigned NumElts = VT.getVectorNumElements(); 15752 unsigned i = 0; 15753 for (; i != NumElts; ++i) { 15754 SDValue Arg = ShAmtOp.getOperand(i); 15755 if (Arg.getOpcode() == ISD::UNDEF) continue; 15756 BaseShAmt = Arg; 15757 break; 15758 } 15759 // Handle the case where the build_vector is all undef 15760 // FIXME: Should DAG allow this? 15761 if (i == NumElts) 15762 return SDValue(); 15763 15764 for (; i != NumElts; ++i) { 15765 SDValue Arg = ShAmtOp.getOperand(i); 15766 if (Arg.getOpcode() == ISD::UNDEF) continue; 15767 if (Arg != BaseShAmt) { 15768 return SDValue(); 15769 } 15770 } 15771 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 15772 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 15773 SDValue InVec = ShAmtOp.getOperand(0); 15774 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 15775 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 15776 unsigned i = 0; 15777 for (; i != NumElts; ++i) { 15778 SDValue Arg = InVec.getOperand(i); 15779 if (Arg.getOpcode() == ISD::UNDEF) continue; 15780 BaseShAmt = Arg; 15781 break; 15782 } 15783 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 15784 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 15785 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 15786 if (C->getZExtValue() == SplatIdx) 15787 BaseShAmt = InVec.getOperand(1); 15788 } 15789 } 15790 if (BaseShAmt.getNode() == 0) { 15791 // Don't create instructions with illegal types after legalize 15792 // types has run. 15793 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 15794 !DCI.isBeforeLegalize()) 15795 return SDValue(); 15796 15797 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 15798 DAG.getIntPtrConstant(0)); 15799 } 15800 } else 15801 return SDValue(); 15802 15803 // The shift amount is an i32. 15804 if (EltVT.bitsGT(MVT::i32)) 15805 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 15806 else if (EltVT.bitsLT(MVT::i32)) 15807 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 15808 15809 // The shift amount is identical so we can do a vector shift. 15810 SDValue ValOp = N->getOperand(0); 15811 switch (N->getOpcode()) { 15812 default: 15813 llvm_unreachable("Unknown shift opcode!"); 15814 case ISD::SHL: 15815 switch (VT.getSimpleVT().SimpleTy) { 15816 default: return SDValue(); 15817 case MVT::v2i64: 15818 case MVT::v4i32: 15819 case MVT::v8i16: 15820 case MVT::v4i64: 15821 case MVT::v8i32: 15822 case MVT::v16i16: 15823 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 15824 } 15825 case ISD::SRA: 15826 switch (VT.getSimpleVT().SimpleTy) { 15827 default: return SDValue(); 15828 case MVT::v4i32: 15829 case MVT::v8i16: 15830 case MVT::v8i32: 15831 case MVT::v16i16: 15832 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 15833 } 15834 case ISD::SRL: 15835 switch (VT.getSimpleVT().SimpleTy) { 15836 default: return SDValue(); 15837 case MVT::v2i64: 15838 case MVT::v4i32: 15839 case MVT::v8i16: 15840 case MVT::v4i64: 15841 case MVT::v8i32: 15842 case MVT::v16i16: 15843 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 15844 } 15845 } 15846} 15847 15848// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 15849// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 15850// and friends. Likewise for OR -> CMPNEQSS. 15851static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 15852 TargetLowering::DAGCombinerInfo &DCI, 15853 const X86Subtarget *Subtarget) { 15854 unsigned opcode; 15855 15856 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 15857 // we're requiring SSE2 for both. 15858 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 15859 SDValue N0 = N->getOperand(0); 15860 SDValue N1 = N->getOperand(1); 15861 SDValue CMP0 = N0->getOperand(1); 15862 SDValue CMP1 = N1->getOperand(1); 15863 DebugLoc DL = N->getDebugLoc(); 15864 15865 // The SETCCs should both refer to the same CMP. 15866 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 15867 return SDValue(); 15868 15869 SDValue CMP00 = CMP0->getOperand(0); 15870 SDValue CMP01 = CMP0->getOperand(1); 15871 EVT VT = CMP00.getValueType(); 15872 15873 if (VT == MVT::f32 || VT == MVT::f64) { 15874 bool ExpectingFlags = false; 15875 // Check for any users that want flags: 15876 for (SDNode::use_iterator UI = N->use_begin(), 15877 UE = N->use_end(); 15878 !ExpectingFlags && UI != UE; ++UI) 15879 switch (UI->getOpcode()) { 15880 default: 15881 case ISD::BR_CC: 15882 case ISD::BRCOND: 15883 case ISD::SELECT: 15884 ExpectingFlags = true; 15885 break; 15886 case ISD::CopyToReg: 15887 case ISD::SIGN_EXTEND: 15888 case ISD::ZERO_EXTEND: 15889 case ISD::ANY_EXTEND: 15890 break; 15891 } 15892 15893 if (!ExpectingFlags) { 15894 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 15895 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 15896 15897 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 15898 X86::CondCode tmp = cc0; 15899 cc0 = cc1; 15900 cc1 = tmp; 15901 } 15902 15903 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 15904 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 15905 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 15906 X86ISD::NodeType NTOperator = is64BitFP ? 15907 X86ISD::FSETCCsd : X86ISD::FSETCCss; 15908 // FIXME: need symbolic constants for these magic numbers. 15909 // See X86ATTInstPrinter.cpp:printSSECC(). 15910 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 15911 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 15912 DAG.getConstant(x86cc, MVT::i8)); 15913 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 15914 OnesOrZeroesF); 15915 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 15916 DAG.getConstant(1, MVT::i32)); 15917 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 15918 return OneBitOfTruth; 15919 } 15920 } 15921 } 15922 } 15923 return SDValue(); 15924} 15925 15926/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 15927/// so it can be folded inside ANDNP. 15928static bool CanFoldXORWithAllOnes(const SDNode *N) { 15929 EVT VT = N->getValueType(0); 15930 15931 // Match direct AllOnes for 128 and 256-bit vectors 15932 if (ISD::isBuildVectorAllOnes(N)) 15933 return true; 15934 15935 // Look through a bit convert. 15936 if (N->getOpcode() == ISD::BITCAST) 15937 N = N->getOperand(0).getNode(); 15938 15939 // Sometimes the operand may come from a insert_subvector building a 256-bit 15940 // allones vector 15941 if (VT.is256BitVector() && 15942 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 15943 SDValue V1 = N->getOperand(0); 15944 SDValue V2 = N->getOperand(1); 15945 15946 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 15947 V1.getOperand(0).getOpcode() == ISD::UNDEF && 15948 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 15949 ISD::isBuildVectorAllOnes(V2.getNode())) 15950 return true; 15951 } 15952 15953 return false; 15954} 15955 15956// On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 15957// register. In most cases we actually compare or select YMM-sized registers 15958// and mixing the two types creates horrible code. This method optimizes 15959// some of the transition sequences. 15960static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG, 15961 TargetLowering::DAGCombinerInfo &DCI, 15962 const X86Subtarget *Subtarget) { 15963 EVT VT = N->getValueType(0); 15964 if (!VT.is256BitVector()) 15965 return SDValue(); 15966 15967 assert((N->getOpcode() == ISD::ANY_EXTEND || 15968 N->getOpcode() == ISD::ZERO_EXTEND || 15969 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node"); 15970 15971 SDValue Narrow = N->getOperand(0); 15972 EVT NarrowVT = Narrow->getValueType(0); 15973 if (!NarrowVT.is128BitVector()) 15974 return SDValue(); 15975 15976 if (Narrow->getOpcode() != ISD::XOR && 15977 Narrow->getOpcode() != ISD::AND && 15978 Narrow->getOpcode() != ISD::OR) 15979 return SDValue(); 15980 15981 SDValue N0 = Narrow->getOperand(0); 15982 SDValue N1 = Narrow->getOperand(1); 15983 DebugLoc DL = Narrow->getDebugLoc(); 15984 15985 // The Left side has to be a trunc. 15986 if (N0.getOpcode() != ISD::TRUNCATE) 15987 return SDValue(); 15988 15989 // The type of the truncated inputs. 15990 EVT WideVT = N0->getOperand(0)->getValueType(0); 15991 if (WideVT != VT) 15992 return SDValue(); 15993 15994 // The right side has to be a 'trunc' or a constant vector. 15995 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE; 15996 bool RHSConst = (isSplatVector(N1.getNode()) && 15997 isa<ConstantSDNode>(N1->getOperand(0))); 15998 if (!RHSTrunc && !RHSConst) 15999 return SDValue(); 16000 16001 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16002 16003 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT)) 16004 return SDValue(); 16005 16006 // Set N0 and N1 to hold the inputs to the new wide operation. 16007 N0 = N0->getOperand(0); 16008 if (RHSConst) { 16009 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(), 16010 N1->getOperand(0)); 16011 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1); 16012 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size()); 16013 } else if (RHSTrunc) { 16014 N1 = N1->getOperand(0); 16015 } 16016 16017 // Generate the wide operation. 16018 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1); 16019 unsigned Opcode = N->getOpcode(); 16020 switch (Opcode) { 16021 case ISD::ANY_EXTEND: 16022 return Op; 16023 case ISD::ZERO_EXTEND: { 16024 unsigned InBits = NarrowVT.getScalarType().getSizeInBits(); 16025 APInt Mask = APInt::getAllOnesValue(InBits); 16026 Mask = Mask.zext(VT.getScalarType().getSizeInBits()); 16027 return DAG.getNode(ISD::AND, DL, VT, 16028 Op, DAG.getConstant(Mask, VT)); 16029 } 16030 case ISD::SIGN_EXTEND: 16031 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, 16032 Op, DAG.getValueType(NarrowVT)); 16033 default: 16034 llvm_unreachable("Unexpected opcode"); 16035 } 16036} 16037 16038static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 16039 TargetLowering::DAGCombinerInfo &DCI, 16040 const X86Subtarget *Subtarget) { 16041 EVT VT = N->getValueType(0); 16042 if (DCI.isBeforeLegalizeOps()) 16043 return SDValue(); 16044 16045 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 16046 if (R.getNode()) 16047 return R; 16048 16049 // Create BLSI, and BLSR instructions 16050 // BLSI is X & (-X) 16051 // BLSR is X & (X-1) 16052 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 16053 SDValue N0 = N->getOperand(0); 16054 SDValue N1 = N->getOperand(1); 16055 DebugLoc DL = N->getDebugLoc(); 16056 16057 // Check LHS for neg 16058 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 16059 isZero(N0.getOperand(0))) 16060 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 16061 16062 // Check RHS for neg 16063 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 16064 isZero(N1.getOperand(0))) 16065 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 16066 16067 // Check LHS for X-1 16068 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 16069 isAllOnes(N0.getOperand(1))) 16070 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 16071 16072 // Check RHS for X-1 16073 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 16074 isAllOnes(N1.getOperand(1))) 16075 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 16076 16077 return SDValue(); 16078 } 16079 16080 // Want to form ANDNP nodes: 16081 // 1) In the hopes of then easily combining them with OR and AND nodes 16082 // to form PBLEND/PSIGN. 16083 // 2) To match ANDN packed intrinsics 16084 if (VT != MVT::v2i64 && VT != MVT::v4i64) 16085 return SDValue(); 16086 16087 SDValue N0 = N->getOperand(0); 16088 SDValue N1 = N->getOperand(1); 16089 DebugLoc DL = N->getDebugLoc(); 16090 16091 // Check LHS for vnot 16092 if (N0.getOpcode() == ISD::XOR && 16093 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 16094 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 16095 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 16096 16097 // Check RHS for vnot 16098 if (N1.getOpcode() == ISD::XOR && 16099 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 16100 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 16101 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 16102 16103 return SDValue(); 16104} 16105 16106static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 16107 TargetLowering::DAGCombinerInfo &DCI, 16108 const X86Subtarget *Subtarget) { 16109 EVT VT = N->getValueType(0); 16110 if (DCI.isBeforeLegalizeOps()) 16111 return SDValue(); 16112 16113 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 16114 if (R.getNode()) 16115 return R; 16116 16117 SDValue N0 = N->getOperand(0); 16118 SDValue N1 = N->getOperand(1); 16119 16120 // look for psign/blend 16121 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 16122 if (!Subtarget->hasSSSE3() || 16123 (VT == MVT::v4i64 && !Subtarget->hasInt256())) 16124 return SDValue(); 16125 16126 // Canonicalize pandn to RHS 16127 if (N0.getOpcode() == X86ISD::ANDNP) 16128 std::swap(N0, N1); 16129 // or (and (m, y), (pandn m, x)) 16130 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 16131 SDValue Mask = N1.getOperand(0); 16132 SDValue X = N1.getOperand(1); 16133 SDValue Y; 16134 if (N0.getOperand(0) == Mask) 16135 Y = N0.getOperand(1); 16136 if (N0.getOperand(1) == Mask) 16137 Y = N0.getOperand(0); 16138 16139 // Check to see if the mask appeared in both the AND and ANDNP and 16140 if (!Y.getNode()) 16141 return SDValue(); 16142 16143 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 16144 // Look through mask bitcast. 16145 if (Mask.getOpcode() == ISD::BITCAST) 16146 Mask = Mask.getOperand(0); 16147 if (X.getOpcode() == ISD::BITCAST) 16148 X = X.getOperand(0); 16149 if (Y.getOpcode() == ISD::BITCAST) 16150 Y = Y.getOperand(0); 16151 16152 EVT MaskVT = Mask.getValueType(); 16153 16154 // Validate that the Mask operand is a vector sra node. 16155 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 16156 // there is no psrai.b 16157 if (Mask.getOpcode() != X86ISD::VSRAI) 16158 return SDValue(); 16159 16160 // Check that the SRA is all signbits. 16161 SDValue SraC = Mask.getOperand(1); 16162 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 16163 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 16164 if ((SraAmt + 1) != EltBits) 16165 return SDValue(); 16166 16167 DebugLoc DL = N->getDebugLoc(); 16168 16169 // We are going to replace the AND, OR, NAND with either BLEND 16170 // or PSIGN, which only look at the MSB. The VSRAI instruction 16171 // does not affect the highest bit, so we can get rid of it. 16172 Mask = Mask.getOperand(0); 16173 16174 // Now we know we at least have a plendvb with the mask val. See if 16175 // we can form a psignb/w/d. 16176 // psign = x.type == y.type == mask.type && y = sub(0, x); 16177 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 16178 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 16179 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 16180 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 16181 "Unsupported VT for PSIGN"); 16182 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask); 16183 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 16184 } 16185 // PBLENDVB only available on SSE 4.1 16186 if (!Subtarget->hasSSE41()) 16187 return SDValue(); 16188 16189 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 16190 16191 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 16192 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 16193 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 16194 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 16195 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 16196 } 16197 } 16198 16199 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 16200 return SDValue(); 16201 16202 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 16203 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 16204 std::swap(N0, N1); 16205 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 16206 return SDValue(); 16207 if (!N0.hasOneUse() || !N1.hasOneUse()) 16208 return SDValue(); 16209 16210 SDValue ShAmt0 = N0.getOperand(1); 16211 if (ShAmt0.getValueType() != MVT::i8) 16212 return SDValue(); 16213 SDValue ShAmt1 = N1.getOperand(1); 16214 if (ShAmt1.getValueType() != MVT::i8) 16215 return SDValue(); 16216 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 16217 ShAmt0 = ShAmt0.getOperand(0); 16218 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 16219 ShAmt1 = ShAmt1.getOperand(0); 16220 16221 DebugLoc DL = N->getDebugLoc(); 16222 unsigned Opc = X86ISD::SHLD; 16223 SDValue Op0 = N0.getOperand(0); 16224 SDValue Op1 = N1.getOperand(0); 16225 if (ShAmt0.getOpcode() == ISD::SUB) { 16226 Opc = X86ISD::SHRD; 16227 std::swap(Op0, Op1); 16228 std::swap(ShAmt0, ShAmt1); 16229 } 16230 16231 unsigned Bits = VT.getSizeInBits(); 16232 if (ShAmt1.getOpcode() == ISD::SUB) { 16233 SDValue Sum = ShAmt1.getOperand(0); 16234 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 16235 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 16236 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 16237 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 16238 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 16239 return DAG.getNode(Opc, DL, VT, 16240 Op0, Op1, 16241 DAG.getNode(ISD::TRUNCATE, DL, 16242 MVT::i8, ShAmt0)); 16243 } 16244 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 16245 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 16246 if (ShAmt0C && 16247 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 16248 return DAG.getNode(Opc, DL, VT, 16249 N0.getOperand(0), N1.getOperand(0), 16250 DAG.getNode(ISD::TRUNCATE, DL, 16251 MVT::i8, ShAmt0)); 16252 } 16253 16254 return SDValue(); 16255} 16256 16257// Generate NEG and CMOV for integer abs. 16258static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 16259 EVT VT = N->getValueType(0); 16260 16261 // Since X86 does not have CMOV for 8-bit integer, we don't convert 16262 // 8-bit integer abs to NEG and CMOV. 16263 if (VT.isInteger() && VT.getSizeInBits() == 8) 16264 return SDValue(); 16265 16266 SDValue N0 = N->getOperand(0); 16267 SDValue N1 = N->getOperand(1); 16268 DebugLoc DL = N->getDebugLoc(); 16269 16270 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 16271 // and change it to SUB and CMOV. 16272 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 16273 N0.getOpcode() == ISD::ADD && 16274 N0.getOperand(1) == N1 && 16275 N1.getOpcode() == ISD::SRA && 16276 N1.getOperand(0) == N0.getOperand(0)) 16277 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 16278 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) { 16279 // Generate SUB & CMOV. 16280 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32), 16281 DAG.getConstant(0, VT), N0.getOperand(0)); 16282 16283 SDValue Ops[] = { N0.getOperand(0), Neg, 16284 DAG.getConstant(X86::COND_GE, MVT::i8), 16285 SDValue(Neg.getNode(), 1) }; 16286 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), 16287 Ops, array_lengthof(Ops)); 16288 } 16289 return SDValue(); 16290} 16291 16292// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 16293static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 16294 TargetLowering::DAGCombinerInfo &DCI, 16295 const X86Subtarget *Subtarget) { 16296 EVT VT = N->getValueType(0); 16297 if (DCI.isBeforeLegalizeOps()) 16298 return SDValue(); 16299 16300 if (Subtarget->hasCMov()) { 16301 SDValue RV = performIntegerAbsCombine(N, DAG); 16302 if (RV.getNode()) 16303 return RV; 16304 } 16305 16306 // Try forming BMI if it is available. 16307 if (!Subtarget->hasBMI()) 16308 return SDValue(); 16309 16310 if (VT != MVT::i32 && VT != MVT::i64) 16311 return SDValue(); 16312 16313 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 16314 16315 // Create BLSMSK instructions by finding X ^ (X-1) 16316 SDValue N0 = N->getOperand(0); 16317 SDValue N1 = N->getOperand(1); 16318 DebugLoc DL = N->getDebugLoc(); 16319 16320 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 16321 isAllOnes(N0.getOperand(1))) 16322 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 16323 16324 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 16325 isAllOnes(N1.getOperand(1))) 16326 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 16327 16328 return SDValue(); 16329} 16330 16331/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 16332static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 16333 TargetLowering::DAGCombinerInfo &DCI, 16334 const X86Subtarget *Subtarget) { 16335 LoadSDNode *Ld = cast<LoadSDNode>(N); 16336 EVT RegVT = Ld->getValueType(0); 16337 EVT MemVT = Ld->getMemoryVT(); 16338 DebugLoc dl = Ld->getDebugLoc(); 16339 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16340 unsigned RegSz = RegVT.getSizeInBits(); 16341 16342 ISD::LoadExtType Ext = Ld->getExtensionType(); 16343 unsigned Alignment = Ld->getAlignment(); 16344 bool IsAligned = Alignment == 0 || Alignment == MemVT.getSizeInBits()/8; 16345 16346 // On Sandybridge unaligned 256bit loads are inefficient. 16347 if (RegVT.is256BitVector() && !Subtarget->hasInt256() && 16348 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) { 16349 unsigned NumElems = RegVT.getVectorNumElements(); 16350 if (NumElems < 2) 16351 return SDValue(); 16352 16353 SDValue Ptr = Ld->getBasePtr(); 16354 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy()); 16355 16356 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 16357 NumElems/2); 16358 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 16359 Ld->getPointerInfo(), Ld->isVolatile(), 16360 Ld->isNonTemporal(), Ld->isInvariant(), 16361 Alignment); 16362 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 16363 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr, 16364 Ld->getPointerInfo(), Ld->isVolatile(), 16365 Ld->isNonTemporal(), Ld->isInvariant(), 16366 std::max(Alignment/2U, 1U)); 16367 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 16368 Load1.getValue(1), 16369 Load2.getValue(1)); 16370 16371 SDValue NewVec = DAG.getUNDEF(RegVT); 16372 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl); 16373 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl); 16374 return DCI.CombineTo(N, NewVec, TF, true); 16375 } 16376 16377 // If this is a vector EXT Load then attempt to optimize it using a 16378 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the 16379 // expansion is still better than scalar code. 16380 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll 16381 // emit a shuffle and a arithmetic shift. 16382 // TODO: It is possible to support ZExt by zeroing the undef values 16383 // during the shuffle phase or after the shuffle. 16384 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() && 16385 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) { 16386 assert(MemVT != RegVT && "Cannot extend to the same type"); 16387 assert(MemVT.isVector() && "Must load a vector from memory"); 16388 16389 unsigned NumElems = RegVT.getVectorNumElements(); 16390 unsigned MemSz = MemVT.getSizeInBits(); 16391 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 16392 16393 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) 16394 return SDValue(); 16395 16396 // All sizes must be a power of two. 16397 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) 16398 return SDValue(); 16399 16400 // Attempt to load the original value using scalar loads. 16401 // Find the largest scalar type that divides the total loaded size. 16402 MVT SclrLoadTy = MVT::i8; 16403 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 16404 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 16405 MVT Tp = (MVT::SimpleValueType)tp; 16406 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { 16407 SclrLoadTy = Tp; 16408 } 16409 } 16410 16411 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 16412 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && 16413 (64 <= MemSz)) 16414 SclrLoadTy = MVT::f64; 16415 16416 // Calculate the number of scalar loads that we need to perform 16417 // in order to load our vector from memory. 16418 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits(); 16419 if (Ext == ISD::SEXTLOAD && NumLoads > 1) 16420 return SDValue(); 16421 16422 unsigned loadRegZize = RegSz; 16423 if (Ext == ISD::SEXTLOAD && RegSz == 256) 16424 loadRegZize /= 2; 16425 16426 // Represent our vector as a sequence of elements which are the 16427 // largest scalar that we can load. 16428 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 16429 loadRegZize/SclrLoadTy.getSizeInBits()); 16430 16431 // Represent the data using the same element type that is stored in 16432 // memory. In practice, we ''widen'' MemVT. 16433 EVT WideVecVT = 16434 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 16435 loadRegZize/MemVT.getScalarType().getSizeInBits()); 16436 16437 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && 16438 "Invalid vector type"); 16439 16440 // We can't shuffle using an illegal type. 16441 if (!TLI.isTypeLegal(WideVecVT)) 16442 return SDValue(); 16443 16444 SmallVector<SDValue, 8> Chains; 16445 SDValue Ptr = Ld->getBasePtr(); 16446 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8, 16447 TLI.getPointerTy()); 16448 SDValue Res = DAG.getUNDEF(LoadUnitVecVT); 16449 16450 for (unsigned i = 0; i < NumLoads; ++i) { 16451 // Perform a single load. 16452 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 16453 Ptr, Ld->getPointerInfo(), 16454 Ld->isVolatile(), Ld->isNonTemporal(), 16455 Ld->isInvariant(), Ld->getAlignment()); 16456 Chains.push_back(ScalarLoad.getValue(1)); 16457 // Create the first element type using SCALAR_TO_VECTOR in order to avoid 16458 // another round of DAGCombining. 16459 if (i == 0) 16460 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad); 16461 else 16462 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res, 16463 ScalarLoad, DAG.getIntPtrConstant(i)); 16464 16465 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 16466 } 16467 16468 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 16469 Chains.size()); 16470 16471 // Bitcast the loaded value to a vector of the original element type, in 16472 // the size of the target vector type. 16473 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res); 16474 unsigned SizeRatio = RegSz/MemSz; 16475 16476 if (Ext == ISD::SEXTLOAD) { 16477 // If we have SSE4.1 we can directly emit a VSEXT node. 16478 if (Subtarget->hasSSE41()) { 16479 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec); 16480 return DCI.CombineTo(N, Sext, TF, true); 16481 } 16482 16483 // Otherwise we'll shuffle the small elements in the high bits of the 16484 // larger type and perform an arithmetic shift. If the shift is not legal 16485 // it's better to scalarize. 16486 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT)) 16487 return SDValue(); 16488 16489 // Redistribute the loaded elements into the different locations. 16490 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 16491 for (unsigned i = 0; i != NumElems; ++i) 16492 ShuffleVec[i*SizeRatio + SizeRatio-1] = i; 16493 16494 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 16495 DAG.getUNDEF(WideVecVT), 16496 &ShuffleVec[0]); 16497 16498 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 16499 16500 // Build the arithmetic shift. 16501 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() - 16502 MemVT.getVectorElementType().getSizeInBits(); 16503 SmallVector<SDValue, 8> C(NumElems, 16504 DAG.getConstant(Amt, RegVT.getScalarType())); 16505 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, RegVT, &C[0], C.size()); 16506 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff, BV); 16507 16508 return DCI.CombineTo(N, Shuff, TF, true); 16509 } 16510 16511 // Redistribute the loaded elements into the different locations. 16512 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 16513 for (unsigned i = 0; i != NumElems; ++i) 16514 ShuffleVec[i*SizeRatio] = i; 16515 16516 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 16517 DAG.getUNDEF(WideVecVT), 16518 &ShuffleVec[0]); 16519 16520 // Bitcast to the requested type. 16521 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 16522 // Replace the original load with the new sequence 16523 // and return the new chain. 16524 return DCI.CombineTo(N, Shuff, TF, true); 16525 } 16526 16527 return SDValue(); 16528} 16529 16530/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 16531static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 16532 const X86Subtarget *Subtarget) { 16533 StoreSDNode *St = cast<StoreSDNode>(N); 16534 EVT VT = St->getValue().getValueType(); 16535 EVT StVT = St->getMemoryVT(); 16536 DebugLoc dl = St->getDebugLoc(); 16537 SDValue StoredVal = St->getOperand(1); 16538 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16539 unsigned Alignment = St->getAlignment(); 16540 bool IsAligned = Alignment == 0 || Alignment == VT.getSizeInBits()/8; 16541 16542 // If we are saving a concatenation of two XMM registers, perform two stores. 16543 // On Sandy Bridge, 256-bit memory operations are executed by two 16544 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit 16545 // memory operation. 16546 if (VT.is256BitVector() && !Subtarget->hasInt256() && 16547 StVT == VT && !IsAligned) { 16548 unsigned NumElems = VT.getVectorNumElements(); 16549 if (NumElems < 2) 16550 return SDValue(); 16551 16552 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl); 16553 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl); 16554 16555 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 16556 SDValue Ptr0 = St->getBasePtr(); 16557 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 16558 16559 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 16560 St->getPointerInfo(), St->isVolatile(), 16561 St->isNonTemporal(), Alignment); 16562 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 16563 St->getPointerInfo(), St->isVolatile(), 16564 St->isNonTemporal(), 16565 std::max(Alignment/2U, 1U)); 16566 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 16567 } 16568 16569 // Optimize trunc store (of multiple scalars) to shuffle and store. 16570 // First, pack all of the elements in one place. Next, store to memory 16571 // in fewer chunks. 16572 if (St->isTruncatingStore() && VT.isVector()) { 16573 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16574 unsigned NumElems = VT.getVectorNumElements(); 16575 assert(StVT != VT && "Cannot truncate to the same type"); 16576 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 16577 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 16578 16579 // From, To sizes and ElemCount must be pow of two 16580 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 16581 // We are going to use the original vector elt for storing. 16582 // Accumulated smaller vector elements must be a multiple of the store size. 16583 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 16584 16585 unsigned SizeRatio = FromSz / ToSz; 16586 16587 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 16588 16589 // Create a type on which we perform the shuffle 16590 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 16591 StVT.getScalarType(), NumElems*SizeRatio); 16592 16593 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 16594 16595 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 16596 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 16597 for (unsigned i = 0; i != NumElems; ++i) 16598 ShuffleVec[i] = i * SizeRatio; 16599 16600 // Can't shuffle using an illegal type. 16601 if (!TLI.isTypeLegal(WideVecVT)) 16602 return SDValue(); 16603 16604 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 16605 DAG.getUNDEF(WideVecVT), 16606 &ShuffleVec[0]); 16607 // At this point all of the data is stored at the bottom of the 16608 // register. We now need to save it to mem. 16609 16610 // Find the largest store unit 16611 MVT StoreType = MVT::i8; 16612 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 16613 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 16614 MVT Tp = (MVT::SimpleValueType)tp; 16615 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz) 16616 StoreType = Tp; 16617 } 16618 16619 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 16620 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 && 16621 (64 <= NumElems * ToSz)) 16622 StoreType = MVT::f64; 16623 16624 // Bitcast the original vector into a vector of store-size units 16625 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 16626 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits()); 16627 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 16628 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 16629 SmallVector<SDValue, 8> Chains; 16630 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 16631 TLI.getPointerTy()); 16632 SDValue Ptr = St->getBasePtr(); 16633 16634 // Perform one or more big stores into memory. 16635 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { 16636 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 16637 StoreType, ShuffWide, 16638 DAG.getIntPtrConstant(i)); 16639 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 16640 St->getPointerInfo(), St->isVolatile(), 16641 St->isNonTemporal(), St->getAlignment()); 16642 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 16643 Chains.push_back(Ch); 16644 } 16645 16646 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 16647 Chains.size()); 16648 } 16649 16650 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 16651 // the FP state in cases where an emms may be missing. 16652 // A preferable solution to the general problem is to figure out the right 16653 // places to insert EMMS. This qualifies as a quick hack. 16654 16655 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 16656 if (VT.getSizeInBits() != 64) 16657 return SDValue(); 16658 16659 const Function *F = DAG.getMachineFunction().getFunction(); 16660 bool NoImplicitFloatOps = F->getAttributes(). 16661 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 16662 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 16663 && Subtarget->hasSSE2(); 16664 if ((VT.isVector() || 16665 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 16666 isa<LoadSDNode>(St->getValue()) && 16667 !cast<LoadSDNode>(St->getValue())->isVolatile() && 16668 St->getChain().hasOneUse() && !St->isVolatile()) { 16669 SDNode* LdVal = St->getValue().getNode(); 16670 LoadSDNode *Ld = 0; 16671 int TokenFactorIndex = -1; 16672 SmallVector<SDValue, 8> Ops; 16673 SDNode* ChainVal = St->getChain().getNode(); 16674 // Must be a store of a load. We currently handle two cases: the load 16675 // is a direct child, and it's under an intervening TokenFactor. It is 16676 // possible to dig deeper under nested TokenFactors. 16677 if (ChainVal == LdVal) 16678 Ld = cast<LoadSDNode>(St->getChain()); 16679 else if (St->getValue().hasOneUse() && 16680 ChainVal->getOpcode() == ISD::TokenFactor) { 16681 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 16682 if (ChainVal->getOperand(i).getNode() == LdVal) { 16683 TokenFactorIndex = i; 16684 Ld = cast<LoadSDNode>(St->getValue()); 16685 } else 16686 Ops.push_back(ChainVal->getOperand(i)); 16687 } 16688 } 16689 16690 if (!Ld || !ISD::isNormalLoad(Ld)) 16691 return SDValue(); 16692 16693 // If this is not the MMX case, i.e. we are just turning i64 load/store 16694 // into f64 load/store, avoid the transformation if there are multiple 16695 // uses of the loaded value. 16696 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 16697 return SDValue(); 16698 16699 DebugLoc LdDL = Ld->getDebugLoc(); 16700 DebugLoc StDL = N->getDebugLoc(); 16701 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 16702 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 16703 // pair instead. 16704 if (Subtarget->is64Bit() || F64IsLegal) { 16705 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 16706 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 16707 Ld->getPointerInfo(), Ld->isVolatile(), 16708 Ld->isNonTemporal(), Ld->isInvariant(), 16709 Ld->getAlignment()); 16710 SDValue NewChain = NewLd.getValue(1); 16711 if (TokenFactorIndex != -1) { 16712 Ops.push_back(NewChain); 16713 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 16714 Ops.size()); 16715 } 16716 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 16717 St->getPointerInfo(), 16718 St->isVolatile(), St->isNonTemporal(), 16719 St->getAlignment()); 16720 } 16721 16722 // Otherwise, lower to two pairs of 32-bit loads / stores. 16723 SDValue LoAddr = Ld->getBasePtr(); 16724 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 16725 DAG.getConstant(4, MVT::i32)); 16726 16727 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 16728 Ld->getPointerInfo(), 16729 Ld->isVolatile(), Ld->isNonTemporal(), 16730 Ld->isInvariant(), Ld->getAlignment()); 16731 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 16732 Ld->getPointerInfo().getWithOffset(4), 16733 Ld->isVolatile(), Ld->isNonTemporal(), 16734 Ld->isInvariant(), 16735 MinAlign(Ld->getAlignment(), 4)); 16736 16737 SDValue NewChain = LoLd.getValue(1); 16738 if (TokenFactorIndex != -1) { 16739 Ops.push_back(LoLd); 16740 Ops.push_back(HiLd); 16741 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 16742 Ops.size()); 16743 } 16744 16745 LoAddr = St->getBasePtr(); 16746 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 16747 DAG.getConstant(4, MVT::i32)); 16748 16749 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 16750 St->getPointerInfo(), 16751 St->isVolatile(), St->isNonTemporal(), 16752 St->getAlignment()); 16753 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 16754 St->getPointerInfo().getWithOffset(4), 16755 St->isVolatile(), 16756 St->isNonTemporal(), 16757 MinAlign(St->getAlignment(), 4)); 16758 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 16759 } 16760 return SDValue(); 16761} 16762 16763/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 16764/// and return the operands for the horizontal operation in LHS and RHS. A 16765/// horizontal operation performs the binary operation on successive elements 16766/// of its first operand, then on successive elements of its second operand, 16767/// returning the resulting values in a vector. For example, if 16768/// A = < float a0, float a1, float a2, float a3 > 16769/// and 16770/// B = < float b0, float b1, float b2, float b3 > 16771/// then the result of doing a horizontal operation on A and B is 16772/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 16773/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 16774/// A horizontal-op B, for some already available A and B, and if so then LHS is 16775/// set to A, RHS to B, and the routine returns 'true'. 16776/// Note that the binary operation should have the property that if one of the 16777/// operands is UNDEF then the result is UNDEF. 16778static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 16779 // Look for the following pattern: if 16780 // A = < float a0, float a1, float a2, float a3 > 16781 // B = < float b0, float b1, float b2, float b3 > 16782 // and 16783 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 16784 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 16785 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 16786 // which is A horizontal-op B. 16787 16788 // At least one of the operands should be a vector shuffle. 16789 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 16790 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 16791 return false; 16792 16793 EVT VT = LHS.getValueType(); 16794 16795 assert((VT.is128BitVector() || VT.is256BitVector()) && 16796 "Unsupported vector type for horizontal add/sub"); 16797 16798 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 16799 // operate independently on 128-bit lanes. 16800 unsigned NumElts = VT.getVectorNumElements(); 16801 unsigned NumLanes = VT.getSizeInBits()/128; 16802 unsigned NumLaneElts = NumElts / NumLanes; 16803 assert((NumLaneElts % 2 == 0) && 16804 "Vector type should have an even number of elements in each lane"); 16805 unsigned HalfLaneElts = NumLaneElts/2; 16806 16807 // View LHS in the form 16808 // LHS = VECTOR_SHUFFLE A, B, LMask 16809 // If LHS is not a shuffle then pretend it is the shuffle 16810 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 16811 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 16812 // type VT. 16813 SDValue A, B; 16814 SmallVector<int, 16> LMask(NumElts); 16815 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 16816 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 16817 A = LHS.getOperand(0); 16818 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 16819 B = LHS.getOperand(1); 16820 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 16821 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 16822 } else { 16823 if (LHS.getOpcode() != ISD::UNDEF) 16824 A = LHS; 16825 for (unsigned i = 0; i != NumElts; ++i) 16826 LMask[i] = i; 16827 } 16828 16829 // Likewise, view RHS in the form 16830 // RHS = VECTOR_SHUFFLE C, D, RMask 16831 SDValue C, D; 16832 SmallVector<int, 16> RMask(NumElts); 16833 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 16834 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 16835 C = RHS.getOperand(0); 16836 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 16837 D = RHS.getOperand(1); 16838 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 16839 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 16840 } else { 16841 if (RHS.getOpcode() != ISD::UNDEF) 16842 C = RHS; 16843 for (unsigned i = 0; i != NumElts; ++i) 16844 RMask[i] = i; 16845 } 16846 16847 // Check that the shuffles are both shuffling the same vectors. 16848 if (!(A == C && B == D) && !(A == D && B == C)) 16849 return false; 16850 16851 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 16852 if (!A.getNode() && !B.getNode()) 16853 return false; 16854 16855 // If A and B occur in reverse order in RHS, then "swap" them (which means 16856 // rewriting the mask). 16857 if (A != C) 16858 CommuteVectorShuffleMask(RMask, NumElts); 16859 16860 // At this point LHS and RHS are equivalent to 16861 // LHS = VECTOR_SHUFFLE A, B, LMask 16862 // RHS = VECTOR_SHUFFLE A, B, RMask 16863 // Check that the masks correspond to performing a horizontal operation. 16864 for (unsigned i = 0; i != NumElts; ++i) { 16865 int LIdx = LMask[i], RIdx = RMask[i]; 16866 16867 // Ignore any UNDEF components. 16868 if (LIdx < 0 || RIdx < 0 || 16869 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 16870 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 16871 continue; 16872 16873 // Check that successive elements are being operated on. If not, this is 16874 // not a horizontal operation. 16875 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 16876 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 16877 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 16878 if (!(LIdx == Index && RIdx == Index + 1) && 16879 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 16880 return false; 16881 } 16882 16883 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 16884 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 16885 return true; 16886} 16887 16888/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 16889static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 16890 const X86Subtarget *Subtarget) { 16891 EVT VT = N->getValueType(0); 16892 SDValue LHS = N->getOperand(0); 16893 SDValue RHS = N->getOperand(1); 16894 16895 // Try to synthesize horizontal adds from adds of shuffles. 16896 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 16897 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 16898 isHorizontalBinOp(LHS, RHS, true)) 16899 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 16900 return SDValue(); 16901} 16902 16903/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 16904static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 16905 const X86Subtarget *Subtarget) { 16906 EVT VT = N->getValueType(0); 16907 SDValue LHS = N->getOperand(0); 16908 SDValue RHS = N->getOperand(1); 16909 16910 // Try to synthesize horizontal subs from subs of shuffles. 16911 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 16912 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 16913 isHorizontalBinOp(LHS, RHS, false)) 16914 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 16915 return SDValue(); 16916} 16917 16918/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 16919/// X86ISD::FXOR nodes. 16920static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 16921 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 16922 // F[X]OR(0.0, x) -> x 16923 // F[X]OR(x, 0.0) -> x 16924 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 16925 if (C->getValueAPF().isPosZero()) 16926 return N->getOperand(1); 16927 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 16928 if (C->getValueAPF().isPosZero()) 16929 return N->getOperand(0); 16930 return SDValue(); 16931} 16932 16933/// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and 16934/// X86ISD::FMAX nodes. 16935static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) { 16936 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); 16937 16938 // Only perform optimizations if UnsafeMath is used. 16939 if (!DAG.getTarget().Options.UnsafeFPMath) 16940 return SDValue(); 16941 16942 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes 16943 // into FMINC and FMAXC, which are Commutative operations. 16944 unsigned NewOp = 0; 16945 switch (N->getOpcode()) { 16946 default: llvm_unreachable("unknown opcode"); 16947 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; 16948 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break; 16949 } 16950 16951 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0), 16952 N->getOperand(0), N->getOperand(1)); 16953} 16954 16955/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 16956static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 16957 // FAND(0.0, x) -> 0.0 16958 // FAND(x, 0.0) -> 0.0 16959 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 16960 if (C->getValueAPF().isPosZero()) 16961 return N->getOperand(0); 16962 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 16963 if (C->getValueAPF().isPosZero()) 16964 return N->getOperand(1); 16965 return SDValue(); 16966} 16967 16968static SDValue PerformBTCombine(SDNode *N, 16969 SelectionDAG &DAG, 16970 TargetLowering::DAGCombinerInfo &DCI) { 16971 // BT ignores high bits in the bit index operand. 16972 SDValue Op1 = N->getOperand(1); 16973 if (Op1.hasOneUse()) { 16974 unsigned BitWidth = Op1.getValueSizeInBits(); 16975 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 16976 APInt KnownZero, KnownOne; 16977 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 16978 !DCI.isBeforeLegalizeOps()); 16979 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 16980 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 16981 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 16982 DCI.CommitTargetLoweringOpt(TLO); 16983 } 16984 return SDValue(); 16985} 16986 16987static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 16988 SDValue Op = N->getOperand(0); 16989 if (Op.getOpcode() == ISD::BITCAST) 16990 Op = Op.getOperand(0); 16991 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 16992 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 16993 VT.getVectorElementType().getSizeInBits() == 16994 OpVT.getVectorElementType().getSizeInBits()) { 16995 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 16996 } 16997 return SDValue(); 16998} 16999 17000static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 17001 TargetLowering::DAGCombinerInfo &DCI, 17002 const X86Subtarget *Subtarget) { 17003 if (!DCI.isBeforeLegalizeOps()) 17004 return SDValue(); 17005 17006 if (!Subtarget->hasFp256()) 17007 return SDValue(); 17008 17009 EVT VT = N->getValueType(0); 17010 if (VT.isVector() && VT.getSizeInBits() == 256) { 17011 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); 17012 if (R.getNode()) 17013 return R; 17014 } 17015 17016 return SDValue(); 17017} 17018 17019static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG, 17020 const X86Subtarget* Subtarget) { 17021 DebugLoc dl = N->getDebugLoc(); 17022 EVT VT = N->getValueType(0); 17023 17024 // Let legalize expand this if it isn't a legal type yet. 17025 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 17026 return SDValue(); 17027 17028 EVT ScalarVT = VT.getScalarType(); 17029 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || 17030 (!Subtarget->hasFMA() && !Subtarget->hasFMA4())) 17031 return SDValue(); 17032 17033 SDValue A = N->getOperand(0); 17034 SDValue B = N->getOperand(1); 17035 SDValue C = N->getOperand(2); 17036 17037 bool NegA = (A.getOpcode() == ISD::FNEG); 17038 bool NegB = (B.getOpcode() == ISD::FNEG); 17039 bool NegC = (C.getOpcode() == ISD::FNEG); 17040 17041 // Negative multiplication when NegA xor NegB 17042 bool NegMul = (NegA != NegB); 17043 if (NegA) 17044 A = A.getOperand(0); 17045 if (NegB) 17046 B = B.getOperand(0); 17047 if (NegC) 17048 C = C.getOperand(0); 17049 17050 unsigned Opcode; 17051 if (!NegMul) 17052 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB; 17053 else 17054 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB; 17055 17056 return DAG.getNode(Opcode, dl, VT, A, B, C); 17057} 17058 17059static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 17060 TargetLowering::DAGCombinerInfo &DCI, 17061 const X86Subtarget *Subtarget) { 17062 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 17063 // (and (i32 x86isd::setcc_carry), 1) 17064 // This eliminates the zext. This transformation is necessary because 17065 // ISD::SETCC is always legalized to i8. 17066 DebugLoc dl = N->getDebugLoc(); 17067 SDValue N0 = N->getOperand(0); 17068 EVT VT = N->getValueType(0); 17069 17070 if (N0.getOpcode() == ISD::AND && 17071 N0.hasOneUse() && 17072 N0.getOperand(0).hasOneUse()) { 17073 SDValue N00 = N0.getOperand(0); 17074 if (N00.getOpcode() == X86ISD::SETCC_CARRY) { 17075 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 17076 if (!C || C->getZExtValue() != 1) 17077 return SDValue(); 17078 return DAG.getNode(ISD::AND, dl, VT, 17079 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 17080 N00.getOperand(0), N00.getOperand(1)), 17081 DAG.getConstant(1, VT)); 17082 } 17083 } 17084 17085 if (VT.is256BitVector()) { 17086 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); 17087 if (R.getNode()) 17088 return R; 17089 } 17090 17091 return SDValue(); 17092} 17093 17094// Optimize x == -y --> x+y == 0 17095// x != -y --> x+y != 0 17096static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 17097 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 17098 SDValue LHS = N->getOperand(0); 17099 SDValue RHS = N->getOperand(1); 17100 17101 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 17102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 17103 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 17104 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 17105 LHS.getValueType(), RHS, LHS.getOperand(1)); 17106 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 17107 addV, DAG.getConstant(0, addV.getValueType()), CC); 17108 } 17109 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 17110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 17111 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 17112 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 17113 RHS.getValueType(), LHS, RHS.getOperand(1)); 17114 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 17115 addV, DAG.getConstant(0, addV.getValueType()), CC); 17116 } 17117 return SDValue(); 17118} 17119 17120// Helper function of PerformSETCCCombine. It is to materialize "setb reg" 17121// as "sbb reg,reg", since it can be extended without zext and produces 17122// an all-ones bit which is more useful than 0/1 in some cases. 17123static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) { 17124 return DAG.getNode(ISD::AND, DL, MVT::i8, 17125 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 17126 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS), 17127 DAG.getConstant(1, MVT::i8)); 17128} 17129 17130// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 17131static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG, 17132 TargetLowering::DAGCombinerInfo &DCI, 17133 const X86Subtarget *Subtarget) { 17134 DebugLoc DL = N->getDebugLoc(); 17135 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0)); 17136 SDValue EFLAGS = N->getOperand(1); 17137 17138 if (CC == X86::COND_A) { 17139 // Try to convert COND_A into COND_B in an attempt to facilitate 17140 // materializing "setb reg". 17141 // 17142 // Do not flip "e > c", where "c" is a constant, because Cmp instruction 17143 // cannot take an immediate as its first operand. 17144 // 17145 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() && 17146 EFLAGS.getValueType().isInteger() && 17147 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) { 17148 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(), 17149 EFLAGS.getNode()->getVTList(), 17150 EFLAGS.getOperand(1), EFLAGS.getOperand(0)); 17151 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo()); 17152 return MaterializeSETB(DL, NewEFLAGS, DAG); 17153 } 17154 } 17155 17156 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 17157 // a zext and produces an all-ones bit which is more useful than 0/1 in some 17158 // cases. 17159 if (CC == X86::COND_B) 17160 return MaterializeSETB(DL, EFLAGS, DAG); 17161 17162 SDValue Flags; 17163 17164 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 17165 if (Flags.getNode()) { 17166 SDValue Cond = DAG.getConstant(CC, MVT::i8); 17167 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags); 17168 } 17169 17170 return SDValue(); 17171} 17172 17173// Optimize branch condition evaluation. 17174// 17175static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG, 17176 TargetLowering::DAGCombinerInfo &DCI, 17177 const X86Subtarget *Subtarget) { 17178 DebugLoc DL = N->getDebugLoc(); 17179 SDValue Chain = N->getOperand(0); 17180 SDValue Dest = N->getOperand(1); 17181 SDValue EFLAGS = N->getOperand(3); 17182 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2)); 17183 17184 SDValue Flags; 17185 17186 Flags = checkBoolTestSetCCCombine(EFLAGS, CC); 17187 if (Flags.getNode()) { 17188 SDValue Cond = DAG.getConstant(CC, MVT::i8); 17189 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond, 17190 Flags); 17191 } 17192 17193 return SDValue(); 17194} 17195 17196static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 17197 const X86TargetLowering *XTLI) { 17198 SDValue Op0 = N->getOperand(0); 17199 EVT InVT = Op0->getValueType(0); 17200 17201 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 17202 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 17203 DebugLoc dl = N->getDebugLoc(); 17204 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 17205 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 17206 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 17207 } 17208 17209 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 17210 // a 32-bit target where SSE doesn't support i64->FP operations. 17211 if (Op0.getOpcode() == ISD::LOAD) { 17212 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 17213 EVT VT = Ld->getValueType(0); 17214 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 17215 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 17216 !XTLI->getSubtarget()->is64Bit() && 17217 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 17218 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 17219 Ld->getChain(), Op0, DAG); 17220 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 17221 return FILDChain; 17222 } 17223 } 17224 return SDValue(); 17225} 17226 17227// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 17228static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 17229 X86TargetLowering::DAGCombinerInfo &DCI) { 17230 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 17231 // the result is either zero or one (depending on the input carry bit). 17232 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 17233 if (X86::isZeroNode(N->getOperand(0)) && 17234 X86::isZeroNode(N->getOperand(1)) && 17235 // We don't have a good way to replace an EFLAGS use, so only do this when 17236 // dead right now. 17237 SDValue(N, 1).use_empty()) { 17238 DebugLoc DL = N->getDebugLoc(); 17239 EVT VT = N->getValueType(0); 17240 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 17241 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 17242 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 17243 DAG.getConstant(X86::COND_B,MVT::i8), 17244 N->getOperand(2)), 17245 DAG.getConstant(1, VT)); 17246 return DCI.CombineTo(N, Res1, CarryOut); 17247 } 17248 17249 return SDValue(); 17250} 17251 17252// fold (add Y, (sete X, 0)) -> adc 0, Y 17253// (add Y, (setne X, 0)) -> sbb -1, Y 17254// (sub (sete X, 0), Y) -> sbb 0, Y 17255// (sub (setne X, 0), Y) -> adc -1, Y 17256static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 17257 DebugLoc DL = N->getDebugLoc(); 17258 17259 // Look through ZExts. 17260 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 17261 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 17262 return SDValue(); 17263 17264 SDValue SetCC = Ext.getOperand(0); 17265 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 17266 return SDValue(); 17267 17268 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 17269 if (CC != X86::COND_E && CC != X86::COND_NE) 17270 return SDValue(); 17271 17272 SDValue Cmp = SetCC.getOperand(1); 17273 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 17274 !X86::isZeroNode(Cmp.getOperand(1)) || 17275 !Cmp.getOperand(0).getValueType().isInteger()) 17276 return SDValue(); 17277 17278 SDValue CmpOp0 = Cmp.getOperand(0); 17279 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 17280 DAG.getConstant(1, CmpOp0.getValueType())); 17281 17282 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 17283 if (CC == X86::COND_NE) 17284 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 17285 DL, OtherVal.getValueType(), OtherVal, 17286 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 17287 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 17288 DL, OtherVal.getValueType(), OtherVal, 17289 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 17290} 17291 17292/// PerformADDCombine - Do target-specific dag combines on integer adds. 17293static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 17294 const X86Subtarget *Subtarget) { 17295 EVT VT = N->getValueType(0); 17296 SDValue Op0 = N->getOperand(0); 17297 SDValue Op1 = N->getOperand(1); 17298 17299 // Try to synthesize horizontal adds from adds of shuffles. 17300 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 17301 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 17302 isHorizontalBinOp(Op0, Op1, true)) 17303 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 17304 17305 return OptimizeConditionalInDecrement(N, DAG); 17306} 17307 17308static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 17309 const X86Subtarget *Subtarget) { 17310 SDValue Op0 = N->getOperand(0); 17311 SDValue Op1 = N->getOperand(1); 17312 17313 // X86 can't encode an immediate LHS of a sub. See if we can push the 17314 // negation into a preceding instruction. 17315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 17316 // If the RHS of the sub is a XOR with one use and a constant, invert the 17317 // immediate. Then add one to the LHS of the sub so we can turn 17318 // X-Y -> X+~Y+1, saving one register. 17319 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 17320 isa<ConstantSDNode>(Op1.getOperand(1))) { 17321 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 17322 EVT VT = Op0.getValueType(); 17323 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 17324 Op1.getOperand(0), 17325 DAG.getConstant(~XorC, VT)); 17326 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 17327 DAG.getConstant(C->getAPIntValue()+1, VT)); 17328 } 17329 } 17330 17331 // Try to synthesize horizontal adds from adds of shuffles. 17332 EVT VT = N->getValueType(0); 17333 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 17334 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 17335 isHorizontalBinOp(Op0, Op1, true)) 17336 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 17337 17338 return OptimizeConditionalInDecrement(N, DAG); 17339} 17340 17341/// performVZEXTCombine - Performs build vector combines 17342static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG, 17343 TargetLowering::DAGCombinerInfo &DCI, 17344 const X86Subtarget *Subtarget) { 17345 // (vzext (bitcast (vzext (x)) -> (vzext x) 17346 SDValue In = N->getOperand(0); 17347 while (In.getOpcode() == ISD::BITCAST) 17348 In = In.getOperand(0); 17349 17350 if (In.getOpcode() != X86ISD::VZEXT) 17351 return SDValue(); 17352 17353 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0)); 17354} 17355 17356SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 17357 DAGCombinerInfo &DCI) const { 17358 SelectionDAG &DAG = DCI.DAG; 17359 switch (N->getOpcode()) { 17360 default: break; 17361 case ISD::EXTRACT_VECTOR_ELT: 17362 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 17363 case ISD::VSELECT: 17364 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 17365 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget); 17366 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 17367 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 17368 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 17369 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 17370 case ISD::SHL: 17371 case ISD::SRA: 17372 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 17373 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 17374 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 17375 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 17376 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); 17377 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 17378 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 17379 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 17380 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 17381 case X86ISD::FXOR: 17382 case X86ISD::FOR: return PerformFORCombine(N, DAG); 17383 case X86ISD::FMIN: 17384 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG); 17385 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 17386 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 17387 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 17388 case ISD::ANY_EXTEND: 17389 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 17390 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 17391 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget); 17392 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 17393 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); 17394 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget); 17395 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget); 17396 case X86ISD::SHUFP: // Handle all target specific shuffles 17397 case X86ISD::PALIGN: 17398 case X86ISD::UNPCKH: 17399 case X86ISD::UNPCKL: 17400 case X86ISD::MOVHLPS: 17401 case X86ISD::MOVLHPS: 17402 case X86ISD::PSHUFD: 17403 case X86ISD::PSHUFHW: 17404 case X86ISD::PSHUFLW: 17405 case X86ISD::MOVSS: 17406 case X86ISD::MOVSD: 17407 case X86ISD::VPERMILP: 17408 case X86ISD::VPERM2X128: 17409 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 17410 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget); 17411 } 17412 17413 return SDValue(); 17414} 17415 17416/// isTypeDesirableForOp - Return true if the target has native support for 17417/// the specified value type and it is 'desirable' to use the type for the 17418/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 17419/// instruction encodings are longer and some i16 instructions are slow. 17420bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 17421 if (!isTypeLegal(VT)) 17422 return false; 17423 if (VT != MVT::i16) 17424 return true; 17425 17426 switch (Opc) { 17427 default: 17428 return true; 17429 case ISD::LOAD: 17430 case ISD::SIGN_EXTEND: 17431 case ISD::ZERO_EXTEND: 17432 case ISD::ANY_EXTEND: 17433 case ISD::SHL: 17434 case ISD::SRL: 17435 case ISD::SUB: 17436 case ISD::ADD: 17437 case ISD::MUL: 17438 case ISD::AND: 17439 case ISD::OR: 17440 case ISD::XOR: 17441 return false; 17442 } 17443} 17444 17445/// IsDesirableToPromoteOp - This method query the target whether it is 17446/// beneficial for dag combiner to promote the specified node. If true, it 17447/// should return the desired promotion type by reference. 17448bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 17449 EVT VT = Op.getValueType(); 17450 if (VT != MVT::i16) 17451 return false; 17452 17453 bool Promote = false; 17454 bool Commute = false; 17455 switch (Op.getOpcode()) { 17456 default: break; 17457 case ISD::LOAD: { 17458 LoadSDNode *LD = cast<LoadSDNode>(Op); 17459 // If the non-extending load has a single use and it's not live out, then it 17460 // might be folded. 17461 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 17462 Op.hasOneUse()*/) { 17463 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 17464 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 17465 // The only case where we'd want to promote LOAD (rather then it being 17466 // promoted as an operand is when it's only use is liveout. 17467 if (UI->getOpcode() != ISD::CopyToReg) 17468 return false; 17469 } 17470 } 17471 Promote = true; 17472 break; 17473 } 17474 case ISD::SIGN_EXTEND: 17475 case ISD::ZERO_EXTEND: 17476 case ISD::ANY_EXTEND: 17477 Promote = true; 17478 break; 17479 case ISD::SHL: 17480 case ISD::SRL: { 17481 SDValue N0 = Op.getOperand(0); 17482 // Look out for (store (shl (load), x)). 17483 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 17484 return false; 17485 Promote = true; 17486 break; 17487 } 17488 case ISD::ADD: 17489 case ISD::MUL: 17490 case ISD::AND: 17491 case ISD::OR: 17492 case ISD::XOR: 17493 Commute = true; 17494 // fallthrough 17495 case ISD::SUB: { 17496 SDValue N0 = Op.getOperand(0); 17497 SDValue N1 = Op.getOperand(1); 17498 if (!Commute && MayFoldLoad(N1)) 17499 return false; 17500 // Avoid disabling potential load folding opportunities. 17501 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 17502 return false; 17503 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 17504 return false; 17505 Promote = true; 17506 } 17507 } 17508 17509 PVT = MVT::i32; 17510 return Promote; 17511} 17512 17513//===----------------------------------------------------------------------===// 17514// X86 Inline Assembly Support 17515//===----------------------------------------------------------------------===// 17516 17517namespace { 17518 // Helper to match a string separated by whitespace. 17519 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 17520 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 17521 17522 for (unsigned i = 0, e = args.size(); i != e; ++i) { 17523 StringRef piece(*args[i]); 17524 if (!s.startswith(piece)) // Check if the piece matches. 17525 return false; 17526 17527 s = s.substr(piece.size()); 17528 StringRef::size_type pos = s.find_first_not_of(" \t"); 17529 if (pos == 0) // We matched a prefix. 17530 return false; 17531 17532 s = s.substr(pos); 17533 } 17534 17535 return s.empty(); 17536 } 17537 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 17538} 17539 17540bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 17541 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 17542 17543 std::string AsmStr = IA->getAsmString(); 17544 17545 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 17546 if (!Ty || Ty->getBitWidth() % 16 != 0) 17547 return false; 17548 17549 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 17550 SmallVector<StringRef, 4> AsmPieces; 17551 SplitString(AsmStr, AsmPieces, ";\n"); 17552 17553 switch (AsmPieces.size()) { 17554 default: return false; 17555 case 1: 17556 // FIXME: this should verify that we are targeting a 486 or better. If not, 17557 // we will turn this bswap into something that will be lowered to logical 17558 // ops instead of emitting the bswap asm. For now, we don't support 486 or 17559 // lower so don't worry about this. 17560 // bswap $0 17561 if (matchAsm(AsmPieces[0], "bswap", "$0") || 17562 matchAsm(AsmPieces[0], "bswapl", "$0") || 17563 matchAsm(AsmPieces[0], "bswapq", "$0") || 17564 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 17565 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 17566 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 17567 // No need to check constraints, nothing other than the equivalent of 17568 // "=r,0" would be valid here. 17569 return IntrinsicLowering::LowerToByteSwap(CI); 17570 } 17571 17572 // rorw $$8, ${0:w} --> llvm.bswap.i16 17573 if (CI->getType()->isIntegerTy(16) && 17574 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 17575 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 17576 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 17577 AsmPieces.clear(); 17578 const std::string &ConstraintsStr = IA->getConstraintString(); 17579 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 17580 std::sort(AsmPieces.begin(), AsmPieces.end()); 17581 if (AsmPieces.size() == 4 && 17582 AsmPieces[0] == "~{cc}" && 17583 AsmPieces[1] == "~{dirflag}" && 17584 AsmPieces[2] == "~{flags}" && 17585 AsmPieces[3] == "~{fpsr}") 17586 return IntrinsicLowering::LowerToByteSwap(CI); 17587 } 17588 break; 17589 case 3: 17590 if (CI->getType()->isIntegerTy(32) && 17591 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 17592 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 17593 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 17594 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 17595 AsmPieces.clear(); 17596 const std::string &ConstraintsStr = IA->getConstraintString(); 17597 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 17598 std::sort(AsmPieces.begin(), AsmPieces.end()); 17599 if (AsmPieces.size() == 4 && 17600 AsmPieces[0] == "~{cc}" && 17601 AsmPieces[1] == "~{dirflag}" && 17602 AsmPieces[2] == "~{flags}" && 17603 AsmPieces[3] == "~{fpsr}") 17604 return IntrinsicLowering::LowerToByteSwap(CI); 17605 } 17606 17607 if (CI->getType()->isIntegerTy(64)) { 17608 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 17609 if (Constraints.size() >= 2 && 17610 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 17611 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 17612 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 17613 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 17614 matchAsm(AsmPieces[1], "bswap", "%edx") && 17615 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 17616 return IntrinsicLowering::LowerToByteSwap(CI); 17617 } 17618 } 17619 break; 17620 } 17621 return false; 17622} 17623 17624/// getConstraintType - Given a constraint letter, return the type of 17625/// constraint it is for this target. 17626X86TargetLowering::ConstraintType 17627X86TargetLowering::getConstraintType(const std::string &Constraint) const { 17628 if (Constraint.size() == 1) { 17629 switch (Constraint[0]) { 17630 case 'R': 17631 case 'q': 17632 case 'Q': 17633 case 'f': 17634 case 't': 17635 case 'u': 17636 case 'y': 17637 case 'x': 17638 case 'Y': 17639 case 'l': 17640 return C_RegisterClass; 17641 case 'a': 17642 case 'b': 17643 case 'c': 17644 case 'd': 17645 case 'S': 17646 case 'D': 17647 case 'A': 17648 return C_Register; 17649 case 'I': 17650 case 'J': 17651 case 'K': 17652 case 'L': 17653 case 'M': 17654 case 'N': 17655 case 'G': 17656 case 'C': 17657 case 'e': 17658 case 'Z': 17659 return C_Other; 17660 default: 17661 break; 17662 } 17663 } 17664 return TargetLowering::getConstraintType(Constraint); 17665} 17666 17667/// Examine constraint type and operand type and determine a weight value. 17668/// This object must already have been set up with the operand type 17669/// and the current alternative constraint selected. 17670TargetLowering::ConstraintWeight 17671 X86TargetLowering::getSingleConstraintMatchWeight( 17672 AsmOperandInfo &info, const char *constraint) const { 17673 ConstraintWeight weight = CW_Invalid; 17674 Value *CallOperandVal = info.CallOperandVal; 17675 // If we don't have a value, we can't do a match, 17676 // but allow it at the lowest weight. 17677 if (CallOperandVal == NULL) 17678 return CW_Default; 17679 Type *type = CallOperandVal->getType(); 17680 // Look at the constraint type. 17681 switch (*constraint) { 17682 default: 17683 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 17684 case 'R': 17685 case 'q': 17686 case 'Q': 17687 case 'a': 17688 case 'b': 17689 case 'c': 17690 case 'd': 17691 case 'S': 17692 case 'D': 17693 case 'A': 17694 if (CallOperandVal->getType()->isIntegerTy()) 17695 weight = CW_SpecificReg; 17696 break; 17697 case 'f': 17698 case 't': 17699 case 'u': 17700 if (type->isFloatingPointTy()) 17701 weight = CW_SpecificReg; 17702 break; 17703 case 'y': 17704 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 17705 weight = CW_SpecificReg; 17706 break; 17707 case 'x': 17708 case 'Y': 17709 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 17710 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256())) 17711 weight = CW_Register; 17712 break; 17713 case 'I': 17714 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 17715 if (C->getZExtValue() <= 31) 17716 weight = CW_Constant; 17717 } 17718 break; 17719 case 'J': 17720 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17721 if (C->getZExtValue() <= 63) 17722 weight = CW_Constant; 17723 } 17724 break; 17725 case 'K': 17726 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17727 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 17728 weight = CW_Constant; 17729 } 17730 break; 17731 case 'L': 17732 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17733 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 17734 weight = CW_Constant; 17735 } 17736 break; 17737 case 'M': 17738 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17739 if (C->getZExtValue() <= 3) 17740 weight = CW_Constant; 17741 } 17742 break; 17743 case 'N': 17744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17745 if (C->getZExtValue() <= 0xff) 17746 weight = CW_Constant; 17747 } 17748 break; 17749 case 'G': 17750 case 'C': 17751 if (dyn_cast<ConstantFP>(CallOperandVal)) { 17752 weight = CW_Constant; 17753 } 17754 break; 17755 case 'e': 17756 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17757 if ((C->getSExtValue() >= -0x80000000LL) && 17758 (C->getSExtValue() <= 0x7fffffffLL)) 17759 weight = CW_Constant; 17760 } 17761 break; 17762 case 'Z': 17763 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 17764 if (C->getZExtValue() <= 0xffffffff) 17765 weight = CW_Constant; 17766 } 17767 break; 17768 } 17769 return weight; 17770} 17771 17772/// LowerXConstraint - try to replace an X constraint, which matches anything, 17773/// with another that has more specific requirements based on the type of the 17774/// corresponding operand. 17775const char *X86TargetLowering:: 17776LowerXConstraint(EVT ConstraintVT) const { 17777 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 17778 // 'f' like normal targets. 17779 if (ConstraintVT.isFloatingPoint()) { 17780 if (Subtarget->hasSSE2()) 17781 return "Y"; 17782 if (Subtarget->hasSSE1()) 17783 return "x"; 17784 } 17785 17786 return TargetLowering::LowerXConstraint(ConstraintVT); 17787} 17788 17789/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 17790/// vector. If it is invalid, don't add anything to Ops. 17791void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 17792 std::string &Constraint, 17793 std::vector<SDValue>&Ops, 17794 SelectionDAG &DAG) const { 17795 SDValue Result(0, 0); 17796 17797 // Only support length 1 constraints for now. 17798 if (Constraint.length() > 1) return; 17799 17800 char ConstraintLetter = Constraint[0]; 17801 switch (ConstraintLetter) { 17802 default: break; 17803 case 'I': 17804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 17805 if (C->getZExtValue() <= 31) { 17806 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 17807 break; 17808 } 17809 } 17810 return; 17811 case 'J': 17812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 17813 if (C->getZExtValue() <= 63) { 17814 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 17815 break; 17816 } 17817 } 17818 return; 17819 case 'K': 17820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 17821 if (isInt<8>(C->getSExtValue())) { 17822 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 17823 break; 17824 } 17825 } 17826 return; 17827 case 'N': 17828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 17829 if (C->getZExtValue() <= 255) { 17830 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 17831 break; 17832 } 17833 } 17834 return; 17835 case 'e': { 17836 // 32-bit signed value 17837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 17838 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 17839 C->getSExtValue())) { 17840 // Widen to 64 bits here to get it sign extended. 17841 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 17842 break; 17843 } 17844 // FIXME gcc accepts some relocatable values here too, but only in certain 17845 // memory models; it's complicated. 17846 } 17847 return; 17848 } 17849 case 'Z': { 17850 // 32-bit unsigned value 17851 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 17852 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 17853 C->getZExtValue())) { 17854 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 17855 break; 17856 } 17857 } 17858 // FIXME gcc accepts some relocatable values here too, but only in certain 17859 // memory models; it's complicated. 17860 return; 17861 } 17862 case 'i': { 17863 // Literal immediates are always ok. 17864 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 17865 // Widen to 64 bits here to get it sign extended. 17866 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 17867 break; 17868 } 17869 17870 // In any sort of PIC mode addresses need to be computed at runtime by 17871 // adding in a register or some sort of table lookup. These can't 17872 // be used as immediates. 17873 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 17874 return; 17875 17876 // If we are in non-pic codegen mode, we allow the address of a global (with 17877 // an optional displacement) to be used with 'i'. 17878 GlobalAddressSDNode *GA = 0; 17879 int64_t Offset = 0; 17880 17881 // Match either (GA), (GA+C), (GA+C1+C2), etc. 17882 while (1) { 17883 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 17884 Offset += GA->getOffset(); 17885 break; 17886 } else if (Op.getOpcode() == ISD::ADD) { 17887 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 17888 Offset += C->getZExtValue(); 17889 Op = Op.getOperand(0); 17890 continue; 17891 } 17892 } else if (Op.getOpcode() == ISD::SUB) { 17893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 17894 Offset += -C->getZExtValue(); 17895 Op = Op.getOperand(0); 17896 continue; 17897 } 17898 } 17899 17900 // Otherwise, this isn't something we can handle, reject it. 17901 return; 17902 } 17903 17904 const GlobalValue *GV = GA->getGlobal(); 17905 // If we require an extra load to get this address, as in PIC mode, we 17906 // can't accept it. 17907 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 17908 getTargetMachine()))) 17909 return; 17910 17911 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 17912 GA->getValueType(0), Offset); 17913 break; 17914 } 17915 } 17916 17917 if (Result.getNode()) { 17918 Ops.push_back(Result); 17919 return; 17920 } 17921 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 17922} 17923 17924std::pair<unsigned, const TargetRegisterClass*> 17925X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 17926 EVT VT) const { 17927 // First, see if this is a constraint that directly corresponds to an LLVM 17928 // register class. 17929 if (Constraint.size() == 1) { 17930 // GCC Constraint Letters 17931 switch (Constraint[0]) { 17932 default: break; 17933 // TODO: Slight differences here in allocation order and leaving 17934 // RIP in the class. Do they matter any more here than they do 17935 // in the normal allocation? 17936 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 17937 if (Subtarget->is64Bit()) { 17938 if (VT == MVT::i32 || VT == MVT::f32) 17939 return std::make_pair(0U, &X86::GR32RegClass); 17940 if (VT == MVT::i16) 17941 return std::make_pair(0U, &X86::GR16RegClass); 17942 if (VT == MVT::i8 || VT == MVT::i1) 17943 return std::make_pair(0U, &X86::GR8RegClass); 17944 if (VT == MVT::i64 || VT == MVT::f64) 17945 return std::make_pair(0U, &X86::GR64RegClass); 17946 break; 17947 } 17948 // 32-bit fallthrough 17949 case 'Q': // Q_REGS 17950 if (VT == MVT::i32 || VT == MVT::f32) 17951 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 17952 if (VT == MVT::i16) 17953 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 17954 if (VT == MVT::i8 || VT == MVT::i1) 17955 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 17956 if (VT == MVT::i64) 17957 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 17958 break; 17959 case 'r': // GENERAL_REGS 17960 case 'l': // INDEX_REGS 17961 if (VT == MVT::i8 || VT == MVT::i1) 17962 return std::make_pair(0U, &X86::GR8RegClass); 17963 if (VT == MVT::i16) 17964 return std::make_pair(0U, &X86::GR16RegClass); 17965 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 17966 return std::make_pair(0U, &X86::GR32RegClass); 17967 return std::make_pair(0U, &X86::GR64RegClass); 17968 case 'R': // LEGACY_REGS 17969 if (VT == MVT::i8 || VT == MVT::i1) 17970 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 17971 if (VT == MVT::i16) 17972 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 17973 if (VT == MVT::i32 || !Subtarget->is64Bit()) 17974 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 17975 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 17976 case 'f': // FP Stack registers. 17977 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 17978 // value to the correct fpstack register class. 17979 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 17980 return std::make_pair(0U, &X86::RFP32RegClass); 17981 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 17982 return std::make_pair(0U, &X86::RFP64RegClass); 17983 return std::make_pair(0U, &X86::RFP80RegClass); 17984 case 'y': // MMX_REGS if MMX allowed. 17985 if (!Subtarget->hasMMX()) break; 17986 return std::make_pair(0U, &X86::VR64RegClass); 17987 case 'Y': // SSE_REGS if SSE2 allowed 17988 if (!Subtarget->hasSSE2()) break; 17989 // FALL THROUGH. 17990 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 17991 if (!Subtarget->hasSSE1()) break; 17992 17993 switch (VT.getSimpleVT().SimpleTy) { 17994 default: break; 17995 // Scalar SSE types. 17996 case MVT::f32: 17997 case MVT::i32: 17998 return std::make_pair(0U, &X86::FR32RegClass); 17999 case MVT::f64: 18000 case MVT::i64: 18001 return std::make_pair(0U, &X86::FR64RegClass); 18002 // Vector types. 18003 case MVT::v16i8: 18004 case MVT::v8i16: 18005 case MVT::v4i32: 18006 case MVT::v2i64: 18007 case MVT::v4f32: 18008 case MVT::v2f64: 18009 return std::make_pair(0U, &X86::VR128RegClass); 18010 // AVX types. 18011 case MVT::v32i8: 18012 case MVT::v16i16: 18013 case MVT::v8i32: 18014 case MVT::v4i64: 18015 case MVT::v8f32: 18016 case MVT::v4f64: 18017 return std::make_pair(0U, &X86::VR256RegClass); 18018 } 18019 break; 18020 } 18021 } 18022 18023 // Use the default implementation in TargetLowering to convert the register 18024 // constraint into a member of a register class. 18025 std::pair<unsigned, const TargetRegisterClass*> Res; 18026 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 18027 18028 // Not found as a standard register? 18029 if (Res.second == 0) { 18030 // Map st(0) -> st(7) -> ST0 18031 if (Constraint.size() == 7 && Constraint[0] == '{' && 18032 tolower(Constraint[1]) == 's' && 18033 tolower(Constraint[2]) == 't' && 18034 Constraint[3] == '(' && 18035 (Constraint[4] >= '0' && Constraint[4] <= '7') && 18036 Constraint[5] == ')' && 18037 Constraint[6] == '}') { 18038 18039 Res.first = X86::ST0+Constraint[4]-'0'; 18040 Res.second = &X86::RFP80RegClass; 18041 return Res; 18042 } 18043 18044 // GCC allows "st(0)" to be called just plain "st". 18045 if (StringRef("{st}").equals_lower(Constraint)) { 18046 Res.first = X86::ST0; 18047 Res.second = &X86::RFP80RegClass; 18048 return Res; 18049 } 18050 18051 // flags -> EFLAGS 18052 if (StringRef("{flags}").equals_lower(Constraint)) { 18053 Res.first = X86::EFLAGS; 18054 Res.second = &X86::CCRRegClass; 18055 return Res; 18056 } 18057 18058 // 'A' means EAX + EDX. 18059 if (Constraint == "A") { 18060 Res.first = X86::EAX; 18061 Res.second = &X86::GR32_ADRegClass; 18062 return Res; 18063 } 18064 return Res; 18065 } 18066 18067 // Otherwise, check to see if this is a register class of the wrong value 18068 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 18069 // turn into {ax},{dx}. 18070 if (Res.second->hasType(VT)) 18071 return Res; // Correct type already, nothing to do. 18072 18073 // All of the single-register GCC register classes map their values onto 18074 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 18075 // really want an 8-bit or 32-bit register, map to the appropriate register 18076 // class and return the appropriate register. 18077 if (Res.second == &X86::GR16RegClass) { 18078 if (VT == MVT::i8) { 18079 unsigned DestReg = 0; 18080 switch (Res.first) { 18081 default: break; 18082 case X86::AX: DestReg = X86::AL; break; 18083 case X86::DX: DestReg = X86::DL; break; 18084 case X86::CX: DestReg = X86::CL; break; 18085 case X86::BX: DestReg = X86::BL; break; 18086 } 18087 if (DestReg) { 18088 Res.first = DestReg; 18089 Res.second = &X86::GR8RegClass; 18090 } 18091 } else if (VT == MVT::i32) { 18092 unsigned DestReg = 0; 18093 switch (Res.first) { 18094 default: break; 18095 case X86::AX: DestReg = X86::EAX; break; 18096 case X86::DX: DestReg = X86::EDX; break; 18097 case X86::CX: DestReg = X86::ECX; break; 18098 case X86::BX: DestReg = X86::EBX; break; 18099 case X86::SI: DestReg = X86::ESI; break; 18100 case X86::DI: DestReg = X86::EDI; break; 18101 case X86::BP: DestReg = X86::EBP; break; 18102 case X86::SP: DestReg = X86::ESP; break; 18103 } 18104 if (DestReg) { 18105 Res.first = DestReg; 18106 Res.second = &X86::GR32RegClass; 18107 } 18108 } else if (VT == MVT::i64) { 18109 unsigned DestReg = 0; 18110 switch (Res.first) { 18111 default: break; 18112 case X86::AX: DestReg = X86::RAX; break; 18113 case X86::DX: DestReg = X86::RDX; break; 18114 case X86::CX: DestReg = X86::RCX; break; 18115 case X86::BX: DestReg = X86::RBX; break; 18116 case X86::SI: DestReg = X86::RSI; break; 18117 case X86::DI: DestReg = X86::RDI; break; 18118 case X86::BP: DestReg = X86::RBP; break; 18119 case X86::SP: DestReg = X86::RSP; break; 18120 } 18121 if (DestReg) { 18122 Res.first = DestReg; 18123 Res.second = &X86::GR64RegClass; 18124 } 18125 } 18126 } else if (Res.second == &X86::FR32RegClass || 18127 Res.second == &X86::FR64RegClass || 18128 Res.second == &X86::VR128RegClass) { 18129 // Handle references to XMM physical registers that got mapped into the 18130 // wrong class. This can happen with constraints like {xmm0} where the 18131 // target independent register mapper will just pick the first match it can 18132 // find, ignoring the required type. 18133 18134 if (VT == MVT::f32 || VT == MVT::i32) 18135 Res.second = &X86::FR32RegClass; 18136 else if (VT == MVT::f64 || VT == MVT::i64) 18137 Res.second = &X86::FR64RegClass; 18138 else if (X86::VR128RegClass.hasType(VT)) 18139 Res.second = &X86::VR128RegClass; 18140 else if (X86::VR256RegClass.hasType(VT)) 18141 Res.second = &X86::VR256RegClass; 18142 } 18143 18144 return Res; 18145} 18146