X86ISelLowering.cpp revision 0e8671bf4acbd27f759c14e9cc0271b544979283
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86TargetMachine.h" 19#include "llvm/CallingConv.h" 20#include "llvm/Constants.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetOptions.h" 29#include "llvm/ADT/VectorExtras.h" 30using namespace llvm; 31 32// FIXME: temporary. 33#include "llvm/Support/CommandLine.h" 34static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, 35 cl::desc("Enable fastcc on X86")); 36 37X86TargetLowering::X86TargetLowering(TargetMachine &TM) 38 : TargetLowering(TM) { 39 Subtarget = &TM.getSubtarget<X86Subtarget>(); 40 X86ScalarSSE = Subtarget->hasSSE2(); 41 42 // Set up the TargetLowering object. 43 44 // X86 is weird, it always uses i8 for shift amounts and setcc results. 45 setShiftAmountType(MVT::i8); 46 setSetCCResultType(MVT::i8); 47 setSetCCResultContents(ZeroOrOneSetCCResult); 48 setSchedulingPreference(SchedulingForRegPressure); 49 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 50 setStackPointerRegisterToSaveRestore(X86::ESP); 51 52 // Set up the register classes. 53 addRegisterClass(MVT::i8, X86::R8RegisterClass); 54 addRegisterClass(MVT::i16, X86::R16RegisterClass); 55 addRegisterClass(MVT::i32, X86::R32RegisterClass); 56 57 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 58 // operation. 59 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 60 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 61 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 62 63 if (X86ScalarSSE) 64 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead. 65 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 66 else 67 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 68 69 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 70 // this operation. 71 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 72 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 73 if (X86ScalarSSE) 74 // SSE has no i16 to fp conversion, only i32 75 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 76 else if (!X86PatIsel) { 77 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 78 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 79 } 80 81 // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64 82 // isn't legal. 83 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 84 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 85 86 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 87 // this operation. 88 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 89 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 90 91 if (X86ScalarSSE) { 92 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 93 } else { 94 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 95 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 96 } 97 98 // Handle FP_TO_UINT by promoting the destination to a larger signed 99 // conversion. 100 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 101 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 102 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 103 104 if (X86ScalarSSE) 105 // Expand FP_TO_UINT into a select. 106 // FIXME: We would like to use a Custom expander here eventually to do 107 // the optimal thing for SSE vs. the default expansion in the legalizer. 108 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 109 else 110 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 111 112 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 113 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 114 115 if (!X86PatIsel) { 116 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 117 } 118 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); 119 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); 120 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); 122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 124 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 125 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); 126 setOperationAction(ISD::FREM , MVT::f64 , Expand); 127 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 128 setOperationAction(ISD::CTTZ , MVT::i8 , Expand); 129 setOperationAction(ISD::CTLZ , MVT::i8 , Expand); 130 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 131 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 132 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 133 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 134 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 135 setOperationAction(ISD::CTLZ , MVT::i32 , Expand); 136 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 137 138 if (X86PatIsel) { 139 setOperationAction(ISD::BSWAP , MVT::i32 , Expand); 140 setOperationAction(ISD::ROTL , MVT::i8 , Expand); 141 setOperationAction(ISD::ROTR , MVT::i8 , Expand); 142 setOperationAction(ISD::ROTL , MVT::i16 , Expand); 143 setOperationAction(ISD::ROTR , MVT::i16 , Expand); 144 setOperationAction(ISD::ROTL , MVT::i32 , Expand); 145 setOperationAction(ISD::ROTR , MVT::i32 , Expand); 146 } 147 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 148 149 setOperationAction(ISD::READIO , MVT::i1 , Expand); 150 setOperationAction(ISD::READIO , MVT::i8 , Expand); 151 setOperationAction(ISD::READIO , MVT::i16 , Expand); 152 setOperationAction(ISD::READIO , MVT::i32 , Expand); 153 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand); 154 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); 155 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); 156 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); 157 158 // These should be promoted to a larger select which is supported. 159 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 160 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 161 if (!X86PatIsel) { 162 // X86 wants to expand cmov itself. 163 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 164 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 165 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 166 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 167 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 168 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 169 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 170 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 171 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 172 // X86 ret instruction may pop stack. 173 setOperationAction(ISD::RET , MVT::Other, Custom); 174 // Darwin ABI issue. 175 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 176 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 177 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom); 178 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom); 179 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 180 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 181 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 182 // X86 wants to expand memset / memcpy itself. 183 setOperationAction(ISD::MEMSET , MVT::Other, Custom); 184 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 185 } 186 187 // We don't have line number support yet. 188 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 189 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 190 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 191 192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 193 setOperationAction(ISD::VASTART , MVT::Other, Custom); 194 195 // Use the default implementation. 196 setOperationAction(ISD::VAARG , MVT::Other, Expand); 197 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 198 setOperationAction(ISD::VAEND , MVT::Other, Expand); 199 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 200 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 201 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 202 203 if (X86ScalarSSE) { 204 // Set up the FP register classes. 205 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 206 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 207 208 // SSE has no load+extend ops 209 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 210 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); 211 212 // Use ANDPD to simulate FABS. 213 setOperationAction(ISD::FABS , MVT::f64, Custom); 214 setOperationAction(ISD::FABS , MVT::f32, Custom); 215 216 // Use XORP to simulate FNEG. 217 setOperationAction(ISD::FNEG , MVT::f64, Custom); 218 setOperationAction(ISD::FNEG , MVT::f32, Custom); 219 220 // We don't support sin/cos/sqrt/fmod 221 setOperationAction(ISD::FSIN , MVT::f64, Expand); 222 setOperationAction(ISD::FCOS , MVT::f64, Expand); 223 setOperationAction(ISD::FREM , MVT::f64, Expand); 224 setOperationAction(ISD::FSIN , MVT::f32, Expand); 225 setOperationAction(ISD::FCOS , MVT::f32, Expand); 226 setOperationAction(ISD::FREM , MVT::f32, Expand); 227 228 // Expand FP immediates into loads from the stack, except for the special 229 // cases we handle. 230 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 231 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 232 addLegalFPImmediate(+0.0); // xorps / xorpd 233 } else { 234 // Set up the FP register classes. 235 addRegisterClass(MVT::f64, X86::RFPRegisterClass); 236 237 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 238 239 if (!UnsafeFPMath) { 240 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 241 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 242 } 243 244 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 245 addLegalFPImmediate(+0.0); // FLD0 246 addLegalFPImmediate(+1.0); // FLD1 247 addLegalFPImmediate(-0.0); // FLD0/FCHS 248 addLegalFPImmediate(-1.0); // FLD1/FCHS 249 } 250 computeRegisterProperties(); 251 252 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores 253 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores 254 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores 255 allowUnalignedMemoryAccesses = true; // x86 supports it! 256} 257 258std::vector<SDOperand> 259X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 260 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) 261 return LowerFastCCArguments(F, DAG); 262 return LowerCCCArguments(F, DAG); 263} 264 265std::pair<SDOperand, SDOperand> 266X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 267 bool isVarArg, unsigned CallingConv, 268 bool isTailCall, 269 SDOperand Callee, ArgListTy &Args, 270 SelectionDAG &DAG) { 271 assert((!isVarArg || CallingConv == CallingConv::C) && 272 "Only C takes varargs!"); 273 274 // If the callee is a GlobalAddress node (quite common, every direct call is) 275 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 276 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 277 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 278 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 279 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 280 281 if (CallingConv == CallingConv::Fast && EnableFastCC) 282 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG); 283 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG); 284} 285 286//===----------------------------------------------------------------------===// 287// C Calling Convention implementation 288//===----------------------------------------------------------------------===// 289 290std::vector<SDOperand> 291X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) { 292 std::vector<SDOperand> ArgValues; 293 294 MachineFunction &MF = DAG.getMachineFunction(); 295 MachineFrameInfo *MFI = MF.getFrameInfo(); 296 297 // Add DAG nodes to load the arguments... On entry to a function on the X86, 298 // the stack frame looks like this: 299 // 300 // [ESP] -- return address 301 // [ESP + 4] -- first argument (leftmost lexically) 302 // [ESP + 8] -- second argument, if first argument is four bytes in size 303 // ... 304 // 305 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 306 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 307 MVT::ValueType ObjectVT = getValueType(I->getType()); 308 unsigned ArgIncrement = 4; 309 unsigned ObjSize; 310 switch (ObjectVT) { 311 default: assert(0 && "Unhandled argument type!"); 312 case MVT::i1: 313 case MVT::i8: ObjSize = 1; break; 314 case MVT::i16: ObjSize = 2; break; 315 case MVT::i32: ObjSize = 4; break; 316 case MVT::i64: ObjSize = ArgIncrement = 8; break; 317 case MVT::f32: ObjSize = 4; break; 318 case MVT::f64: ObjSize = ArgIncrement = 8; break; 319 } 320 // Create the frame index object for this incoming parameter... 321 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 322 323 // Create the SelectionDAG nodes corresponding to a load from this parameter 324 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 325 326 // Don't codegen dead arguments. FIXME: remove this check when we can nuke 327 // dead loads. 328 SDOperand ArgValue; 329 if (!I->use_empty()) 330 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 331 DAG.getSrcValue(NULL)); 332 else { 333 if (MVT::isInteger(ObjectVT)) 334 ArgValue = DAG.getConstant(0, ObjectVT); 335 else 336 ArgValue = DAG.getConstantFP(0, ObjectVT); 337 } 338 ArgValues.push_back(ArgValue); 339 340 ArgOffset += ArgIncrement; // Move on to the next argument... 341 } 342 343 // If the function takes variable number of arguments, make a frame index for 344 // the start of the first vararg value... for expansion of llvm.va_start. 345 if (F.isVarArg()) 346 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 347 ReturnAddrIndex = 0; // No return address slot generated yet. 348 BytesToPopOnReturn = 0; // Callee pops nothing. 349 BytesCallerReserves = ArgOffset; 350 351 // Finally, inform the code generator which regs we return values in. 352 switch (getValueType(F.getReturnType())) { 353 default: assert(0 && "Unknown type!"); 354 case MVT::isVoid: break; 355 case MVT::i1: 356 case MVT::i8: 357 case MVT::i16: 358 case MVT::i32: 359 MF.addLiveOut(X86::EAX); 360 break; 361 case MVT::i64: 362 MF.addLiveOut(X86::EAX); 363 MF.addLiveOut(X86::EDX); 364 break; 365 case MVT::f32: 366 case MVT::f64: 367 MF.addLiveOut(X86::ST0); 368 break; 369 } 370 return ArgValues; 371} 372 373std::pair<SDOperand, SDOperand> 374X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy, 375 bool isVarArg, bool isTailCall, 376 SDOperand Callee, ArgListTy &Args, 377 SelectionDAG &DAG) { 378 // Count how many bytes are to be pushed on the stack. 379 unsigned NumBytes = 0; 380 381 if (Args.empty()) { 382 // Save zero bytes. 383 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 384 DAG.getConstant(0, getPointerTy())); 385 } else { 386 for (unsigned i = 0, e = Args.size(); i != e; ++i) 387 switch (getValueType(Args[i].second)) { 388 default: assert(0 && "Unknown value type!"); 389 case MVT::i1: 390 case MVT::i8: 391 case MVT::i16: 392 case MVT::i32: 393 case MVT::f32: 394 NumBytes += 4; 395 break; 396 case MVT::i64: 397 case MVT::f64: 398 NumBytes += 8; 399 break; 400 } 401 402 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 403 DAG.getConstant(NumBytes, getPointerTy())); 404 405 // Arguments go on the stack in reverse order, as specified by the ABI. 406 unsigned ArgOffset = 0; 407 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32); 408 std::vector<SDOperand> Stores; 409 410 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 411 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 412 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 413 414 switch (getValueType(Args[i].second)) { 415 default: assert(0 && "Unexpected ValueType for argument!"); 416 case MVT::i1: 417 case MVT::i8: 418 case MVT::i16: 419 // Promote the integer to 32 bits. If the input type is signed use a 420 // sign extend, otherwise use a zero extend. 421 if (Args[i].second->isSigned()) 422 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 423 else 424 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 425 426 // FALL THROUGH 427 case MVT::i32: 428 case MVT::f32: 429 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 430 Args[i].first, PtrOff, 431 DAG.getSrcValue(NULL))); 432 ArgOffset += 4; 433 break; 434 case MVT::i64: 435 case MVT::f64: 436 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 437 Args[i].first, PtrOff, 438 DAG.getSrcValue(NULL))); 439 ArgOffset += 8; 440 break; 441 } 442 } 443 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 444 } 445 446 std::vector<MVT::ValueType> RetVals; 447 MVT::ValueType RetTyVT = getValueType(RetTy); 448 RetVals.push_back(MVT::Other); 449 450 // The result values produced have to be legal. Promote the result. 451 switch (RetTyVT) { 452 case MVT::isVoid: break; 453 default: 454 RetVals.push_back(RetTyVT); 455 break; 456 case MVT::i1: 457 case MVT::i8: 458 case MVT::i16: 459 RetVals.push_back(MVT::i32); 460 break; 461 case MVT::f32: 462 if (X86ScalarSSE) 463 RetVals.push_back(MVT::f32); 464 else 465 RetVals.push_back(MVT::f64); 466 break; 467 case MVT::i64: 468 RetVals.push_back(MVT::i32); 469 RetVals.push_back(MVT::i32); 470 break; 471 } 472 473 if (!X86PatIsel) { 474 std::vector<MVT::ValueType> NodeTys; 475 NodeTys.push_back(MVT::Other); // Returns a chain 476 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 477 std::vector<SDOperand> Ops; 478 Ops.push_back(Chain); 479 Ops.push_back(Callee); 480 481 // FIXME: Do not generate X86ISD::TAILCALL for now. 482 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); 483 SDOperand InFlag = Chain.getValue(1); 484 485 NodeTys.clear(); 486 NodeTys.push_back(MVT::Other); // Returns a chain 487 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 488 Ops.clear(); 489 Ops.push_back(Chain); 490 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 491 Ops.push_back(DAG.getConstant(0, getPointerTy())); 492 Ops.push_back(InFlag); 493 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops); 494 InFlag = Chain.getValue(1); 495 496 SDOperand RetVal; 497 if (RetTyVT != MVT::isVoid) { 498 switch (RetTyVT) { 499 default: assert(0 && "Unknown value type to return!"); 500 case MVT::i1: 501 case MVT::i8: 502 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); 503 Chain = RetVal.getValue(1); 504 if (RetTyVT == MVT::i1) 505 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal); 506 break; 507 case MVT::i16: 508 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); 509 Chain = RetVal.getValue(1); 510 break; 511 case MVT::i32: 512 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 513 Chain = RetVal.getValue(1); 514 break; 515 case MVT::i64: { 516 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 517 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, 518 Lo.getValue(2)); 519 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 520 Chain = Hi.getValue(1); 521 break; 522 } 523 case MVT::f32: 524 case MVT::f64: { 525 std::vector<MVT::ValueType> Tys; 526 Tys.push_back(MVT::f64); 527 Tys.push_back(MVT::Other); 528 Tys.push_back(MVT::Flag); 529 std::vector<SDOperand> Ops; 530 Ops.push_back(Chain); 531 Ops.push_back(InFlag); 532 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); 533 Chain = RetVal.getValue(1); 534 InFlag = RetVal.getValue(2); 535 if (X86ScalarSSE) { 536 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 537 // shouldn't be necessary except that RFP cannot be live across 538 // multiple blocks. When stackifier is fixed, they can be uncoupled. 539 MachineFunction &MF = DAG.getMachineFunction(); 540 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 541 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 542 Tys.clear(); 543 Tys.push_back(MVT::Other); 544 Ops.clear(); 545 Ops.push_back(Chain); 546 Ops.push_back(RetVal); 547 Ops.push_back(StackSlot); 548 Ops.push_back(DAG.getValueType(RetTyVT)); 549 Ops.push_back(InFlag); 550 Chain = DAG.getNode(X86ISD::FST, Tys, Ops); 551 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, 552 DAG.getSrcValue(NULL)); 553 Chain = RetVal.getValue(1); 554 } 555 556 if (RetTyVT == MVT::f32 && !X86ScalarSSE) 557 // FIXME: we would really like to remember that this FP_ROUND 558 // operation is okay to eliminate if we allow excess FP precision. 559 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 560 break; 561 } 562 } 563 } 564 565 return std::make_pair(RetVal, Chain); 566 } else { 567 std::vector<SDOperand> Ops; 568 Ops.push_back(Chain); 569 Ops.push_back(Callee); 570 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 571 Ops.push_back(DAG.getConstant(0, getPointerTy())); 572 573 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL :X86ISD::CALL, 574 RetVals, Ops); 575 576 SDOperand ResultVal; 577 switch (RetTyVT) { 578 case MVT::isVoid: break; 579 default: 580 ResultVal = TheCall.getValue(1); 581 break; 582 case MVT::i1: 583 case MVT::i8: 584 case MVT::i16: 585 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); 586 break; 587 case MVT::f32: 588 // FIXME: we would really like to remember that this FP_ROUND operation is 589 // okay to eliminate if we allow excess FP precision. 590 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); 591 break; 592 case MVT::i64: 593 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), 594 TheCall.getValue(2)); 595 break; 596 } 597 598 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); 599 return std::make_pair(ResultVal, Chain); 600 } 601} 602 603//===----------------------------------------------------------------------===// 604// Fast Calling Convention implementation 605//===----------------------------------------------------------------------===// 606// 607// The X86 'fast' calling convention passes up to two integer arguments in 608// registers (an appropriate portion of EAX/EDX), passes arguments in C order, 609// and requires that the callee pop its arguments off the stack (allowing proper 610// tail calls), and has the same return value conventions as C calling convs. 611// 612// This calling convention always arranges for the callee pop value to be 8n+4 613// bytes, which is needed for tail recursion elimination and stack alignment 614// reasons. 615// 616// Note that this can be enhanced in the future to pass fp vals in registers 617// (when we have a global fp allocator) and do other tricks. 618// 619 620/// AddLiveIn - This helper function adds the specified physical register to the 621/// MachineFunction as a live in value. It also creates a corresponding virtual 622/// register for it. 623static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 624 TargetRegisterClass *RC) { 625 assert(RC->contains(PReg) && "Not the correct regclass!"); 626 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 627 MF.addLiveIn(PReg, VReg); 628 return VReg; 629} 630 631 632std::vector<SDOperand> 633X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { 634 std::vector<SDOperand> ArgValues; 635 636 MachineFunction &MF = DAG.getMachineFunction(); 637 MachineFrameInfo *MFI = MF.getFrameInfo(); 638 639 // Add DAG nodes to load the arguments... On entry to a function the stack 640 // frame looks like this: 641 // 642 // [ESP] -- return address 643 // [ESP + 4] -- first nonreg argument (leftmost lexically) 644 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size 645 // ... 646 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 647 648 // Keep track of the number of integer regs passed so far. This can be either 649 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 650 // used). 651 unsigned NumIntRegs = 0; 652 653 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 654 MVT::ValueType ObjectVT = getValueType(I->getType()); 655 unsigned ArgIncrement = 4; 656 unsigned ObjSize = 0; 657 SDOperand ArgValue; 658 659 switch (ObjectVT) { 660 default: assert(0 && "Unhandled argument type!"); 661 case MVT::i1: 662 case MVT::i8: 663 if (NumIntRegs < 2) { 664 if (!I->use_empty()) { 665 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, 666 X86::R8RegisterClass); 667 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8); 668 DAG.setRoot(ArgValue.getValue(1)); 669 if (ObjectVT == MVT::i1) 670 // FIXME: Should insert a assertzext here. 671 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue); 672 } 673 ++NumIntRegs; 674 break; 675 } 676 677 ObjSize = 1; 678 break; 679 case MVT::i16: 680 if (NumIntRegs < 2) { 681 if (!I->use_empty()) { 682 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, 683 X86::R16RegisterClass); 684 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16); 685 DAG.setRoot(ArgValue.getValue(1)); 686 } 687 ++NumIntRegs; 688 break; 689 } 690 ObjSize = 2; 691 break; 692 case MVT::i32: 693 if (NumIntRegs < 2) { 694 if (!I->use_empty()) { 695 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, 696 X86::R32RegisterClass); 697 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 698 DAG.setRoot(ArgValue.getValue(1)); 699 } 700 ++NumIntRegs; 701 break; 702 } 703 ObjSize = 4; 704 break; 705 case MVT::i64: 706 if (NumIntRegs == 0) { 707 if (!I->use_empty()) { 708 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); 709 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); 710 711 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); 712 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32); 713 DAG.setRoot(Hi.getValue(1)); 714 715 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); 716 } 717 NumIntRegs = 2; 718 break; 719 } else if (NumIntRegs == 1) { 720 if (!I->use_empty()) { 721 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); 722 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); 723 DAG.setRoot(Low.getValue(1)); 724 725 // Load the high part from memory. 726 // Create the frame index object for this incoming parameter... 727 int FI = MFI->CreateFixedObject(4, ArgOffset); 728 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 729 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 730 DAG.getSrcValue(NULL)); 731 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); 732 } 733 ArgOffset += 4; 734 NumIntRegs = 2; 735 break; 736 } 737 ObjSize = ArgIncrement = 8; 738 break; 739 case MVT::f32: ObjSize = 4; break; 740 case MVT::f64: ObjSize = ArgIncrement = 8; break; 741 } 742 743 // Don't codegen dead arguments. FIXME: remove this check when we can nuke 744 // dead loads. 745 if (ObjSize && !I->use_empty()) { 746 // Create the frame index object for this incoming parameter... 747 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 748 749 // Create the SelectionDAG nodes corresponding to a load from this 750 // parameter. 751 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 752 753 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 754 DAG.getSrcValue(NULL)); 755 } else if (ArgValue.Val == 0) { 756 if (MVT::isInteger(ObjectVT)) 757 ArgValue = DAG.getConstant(0, ObjectVT); 758 else 759 ArgValue = DAG.getConstantFP(0, ObjectVT); 760 } 761 ArgValues.push_back(ArgValue); 762 763 if (ObjSize) 764 ArgOffset += ArgIncrement; // Move on to the next argument. 765 } 766 767 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 768 // arguments and the arguments after the retaddr has been pushed are aligned. 769 if ((ArgOffset & 7) == 0) 770 ArgOffset += 4; 771 772 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 773 ReturnAddrIndex = 0; // No return address slot generated yet. 774 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. 775 BytesCallerReserves = 0; 776 777 // Finally, inform the code generator which regs we return values in. 778 switch (getValueType(F.getReturnType())) { 779 default: assert(0 && "Unknown type!"); 780 case MVT::isVoid: break; 781 case MVT::i1: 782 case MVT::i8: 783 case MVT::i16: 784 case MVT::i32: 785 MF.addLiveOut(X86::EAX); 786 break; 787 case MVT::i64: 788 MF.addLiveOut(X86::EAX); 789 MF.addLiveOut(X86::EDX); 790 break; 791 case MVT::f32: 792 case MVT::f64: 793 MF.addLiveOut(X86::ST0); 794 break; 795 } 796 return ArgValues; 797} 798 799std::pair<SDOperand, SDOperand> 800X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, 801 bool isTailCall, SDOperand Callee, 802 ArgListTy &Args, SelectionDAG &DAG) { 803 // Count how many bytes are to be pushed on the stack. 804 unsigned NumBytes = 0; 805 806 // Keep track of the number of integer regs passed so far. This can be either 807 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 808 // used). 809 unsigned NumIntRegs = 0; 810 811 for (unsigned i = 0, e = Args.size(); i != e; ++i) 812 switch (getValueType(Args[i].second)) { 813 default: assert(0 && "Unknown value type!"); 814 case MVT::i1: 815 case MVT::i8: 816 case MVT::i16: 817 case MVT::i32: 818 if (NumIntRegs < 2) { 819 ++NumIntRegs; 820 break; 821 } 822 // fall through 823 case MVT::f32: 824 NumBytes += 4; 825 break; 826 case MVT::i64: 827 if (NumIntRegs == 0) { 828 NumIntRegs = 2; 829 break; 830 } else if (NumIntRegs == 1) { 831 NumIntRegs = 2; 832 NumBytes += 4; 833 break; 834 } 835 836 // fall through 837 case MVT::f64: 838 NumBytes += 8; 839 break; 840 } 841 842 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 843 // arguments and the arguments after the retaddr has been pushed are aligned. 844 if ((NumBytes & 7) == 0) 845 NumBytes += 4; 846 847 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 848 DAG.getConstant(NumBytes, getPointerTy())); 849 850 // Arguments go on the stack in reverse order, as specified by the ABI. 851 unsigned ArgOffset = 0; 852 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32); 853 NumIntRegs = 0; 854 std::vector<SDOperand> Stores; 855 std::vector<SDOperand> RegValuesToPass; 856 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 857 switch (getValueType(Args[i].second)) { 858 default: assert(0 && "Unexpected ValueType for argument!"); 859 case MVT::i1: 860 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first); 861 // Fall through. 862 case MVT::i8: 863 case MVT::i16: 864 case MVT::i32: 865 if (NumIntRegs < 2) { 866 RegValuesToPass.push_back(Args[i].first); 867 ++NumIntRegs; 868 break; 869 } 870 // Fall through 871 case MVT::f32: { 872 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 873 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 874 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 875 Args[i].first, PtrOff, 876 DAG.getSrcValue(NULL))); 877 ArgOffset += 4; 878 break; 879 } 880 case MVT::i64: 881 if (NumIntRegs < 2) { // Can pass part of it in regs? 882 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 883 Args[i].first, DAG.getConstant(1, MVT::i32)); 884 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 885 Args[i].first, DAG.getConstant(0, MVT::i32)); 886 RegValuesToPass.push_back(Lo); 887 ++NumIntRegs; 888 if (NumIntRegs < 2) { // Pass both parts in regs? 889 RegValuesToPass.push_back(Hi); 890 ++NumIntRegs; 891 } else { 892 // Pass the high part in memory. 893 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 894 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 895 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 896 Hi, PtrOff, DAG.getSrcValue(NULL))); 897 ArgOffset += 4; 898 } 899 break; 900 } 901 // Fall through 902 case MVT::f64: 903 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 904 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 905 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 906 Args[i].first, PtrOff, 907 DAG.getSrcValue(NULL))); 908 ArgOffset += 8; 909 break; 910 } 911 } 912 if (!Stores.empty()) 913 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 914 915 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 916 // arguments and the arguments after the retaddr has been pushed are aligned. 917 if ((ArgOffset & 7) == 0) 918 ArgOffset += 4; 919 920 std::vector<MVT::ValueType> RetVals; 921 MVT::ValueType RetTyVT = getValueType(RetTy); 922 923 RetVals.push_back(MVT::Other); 924 925 // The result values produced have to be legal. Promote the result. 926 switch (RetTyVT) { 927 case MVT::isVoid: break; 928 default: 929 RetVals.push_back(RetTyVT); 930 break; 931 case MVT::i1: 932 case MVT::i8: 933 case MVT::i16: 934 RetVals.push_back(MVT::i32); 935 break; 936 case MVT::f32: 937 if (X86ScalarSSE) 938 RetVals.push_back(MVT::f32); 939 else 940 RetVals.push_back(MVT::f64); 941 break; 942 case MVT::i64: 943 RetVals.push_back(MVT::i32); 944 RetVals.push_back(MVT::i32); 945 break; 946 } 947 948 if (!X86PatIsel) { 949 // Build a sequence of copy-to-reg nodes chained together with token chain 950 // and flag operands which copy the outgoing args into registers. 951 SDOperand InFlag; 952 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 953 unsigned CCReg; 954 SDOperand RegToPass = RegValuesToPass[i]; 955 switch (RegToPass.getValueType()) { 956 default: assert(0 && "Bad thing to pass in regs"); 957 case MVT::i8: 958 CCReg = (i == 0) ? X86::AL : X86::DL; 959 break; 960 case MVT::i16: 961 CCReg = (i == 0) ? X86::AX : X86::DX; 962 break; 963 case MVT::i32: 964 CCReg = (i == 0) ? X86::EAX : X86::EDX; 965 break; 966 } 967 968 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag); 969 InFlag = Chain.getValue(1); 970 } 971 972 std::vector<MVT::ValueType> NodeTys; 973 NodeTys.push_back(MVT::Other); // Returns a chain 974 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 975 std::vector<SDOperand> Ops; 976 Ops.push_back(Chain); 977 Ops.push_back(Callee); 978 if (InFlag.Val) 979 Ops.push_back(InFlag); 980 981 // FIXME: Do not generate X86ISD::TAILCALL for now. 982 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops); 983 InFlag = Chain.getValue(1); 984 985 NodeTys.clear(); 986 NodeTys.push_back(MVT::Other); // Returns a chain 987 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 988 Ops.clear(); 989 Ops.push_back(Chain); 990 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 991 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 992 Ops.push_back(InFlag); 993 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops); 994 InFlag = Chain.getValue(1); 995 996 SDOperand RetVal; 997 if (RetTyVT != MVT::isVoid) { 998 switch (RetTyVT) { 999 default: assert(0 && "Unknown value type to return!"); 1000 case MVT::i1: 1001 case MVT::i8: 1002 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag); 1003 Chain = RetVal.getValue(1); 1004 if (RetTyVT == MVT::i1) 1005 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal); 1006 break; 1007 case MVT::i16: 1008 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag); 1009 Chain = RetVal.getValue(1); 1010 break; 1011 case MVT::i32: 1012 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 1013 Chain = RetVal.getValue(1); 1014 break; 1015 case MVT::i64: { 1016 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag); 1017 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32, 1018 Lo.getValue(2)); 1019 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1020 Chain = Hi.getValue(1); 1021 break; 1022 } 1023 case MVT::f32: 1024 case MVT::f64: { 1025 std::vector<MVT::ValueType> Tys; 1026 Tys.push_back(MVT::f64); 1027 Tys.push_back(MVT::Other); 1028 Tys.push_back(MVT::Flag); 1029 std::vector<SDOperand> Ops; 1030 Ops.push_back(Chain); 1031 Ops.push_back(InFlag); 1032 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops); 1033 Chain = RetVal.getValue(1); 1034 InFlag = RetVal.getValue(2); 1035 if (X86ScalarSSE) { 1036 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This 1037 // shouldn't be necessary except that RFP cannot be live across 1038 // multiple blocks. When stackifier is fixed, they can be uncoupled. 1039 MachineFunction &MF = DAG.getMachineFunction(); 1040 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 1041 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1042 Tys.clear(); 1043 Tys.push_back(MVT::Other); 1044 Ops.clear(); 1045 Ops.push_back(Chain); 1046 Ops.push_back(RetVal); 1047 Ops.push_back(StackSlot); 1048 Ops.push_back(DAG.getValueType(RetTyVT)); 1049 Ops.push_back(InFlag); 1050 Chain = DAG.getNode(X86ISD::FST, Tys, Ops); 1051 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot, 1052 DAG.getSrcValue(NULL)); 1053 Chain = RetVal.getValue(1); 1054 } 1055 1056 if (RetTyVT == MVT::f32 && !X86ScalarSSE) 1057 // FIXME: we would really like to remember that this FP_ROUND 1058 // operation is okay to eliminate if we allow excess FP precision. 1059 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal); 1060 break; 1061 } 1062 } 1063 } 1064 1065 return std::make_pair(RetVal, Chain); 1066 } else { 1067 std::vector<SDOperand> Ops; 1068 Ops.push_back(Chain); 1069 Ops.push_back(Callee); 1070 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 1071 // Callee pops all arg values on the stack. 1072 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 1073 1074 // Pass register arguments as needed. 1075 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end()); 1076 1077 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL :X86ISD::CALL, 1078 RetVals, Ops); 1079 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); 1080 1081 SDOperand ResultVal; 1082 switch (RetTyVT) { 1083 case MVT::isVoid: break; 1084 default: 1085 ResultVal = TheCall.getValue(1); 1086 break; 1087 case MVT::i1: 1088 case MVT::i8: 1089 case MVT::i16: 1090 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); 1091 break; 1092 case MVT::f32: 1093 // FIXME: we would really like to remember that this FP_ROUND operation is 1094 // okay to eliminate if we allow excess FP precision. 1095 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); 1096 break; 1097 case MVT::i64: 1098 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), 1099 TheCall.getValue(2)); 1100 break; 1101 } 1102 1103 return std::make_pair(ResultVal, Chain); 1104 } 1105} 1106 1107SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1108 if (ReturnAddrIndex == 0) { 1109 // Set up a frame object for the return address. 1110 MachineFunction &MF = DAG.getMachineFunction(); 1111 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 1112 } 1113 1114 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32); 1115} 1116 1117 1118 1119std::pair<SDOperand, SDOperand> X86TargetLowering:: 1120LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 1121 SelectionDAG &DAG) { 1122 SDOperand Result; 1123 if (Depth) // Depths > 0 not supported yet! 1124 Result = DAG.getConstant(0, getPointerTy()); 1125 else { 1126 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 1127 if (!isFrameAddress) 1128 // Just load the return address 1129 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, 1130 DAG.getSrcValue(NULL)); 1131 else 1132 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI, 1133 DAG.getConstant(4, MVT::i32)); 1134 } 1135 return std::make_pair(Result, Chain); 1136} 1137 1138/// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode 1139/// which corresponds to the condition code. 1140static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) { 1141 switch (X86CC) { 1142 default: assert(0 && "Unknown X86 conditional code!"); 1143 case X86ISD::COND_A: return X86::JA; 1144 case X86ISD::COND_AE: return X86::JAE; 1145 case X86ISD::COND_B: return X86::JB; 1146 case X86ISD::COND_BE: return X86::JBE; 1147 case X86ISD::COND_E: return X86::JE; 1148 case X86ISD::COND_G: return X86::JG; 1149 case X86ISD::COND_GE: return X86::JGE; 1150 case X86ISD::COND_L: return X86::JL; 1151 case X86ISD::COND_LE: return X86::JLE; 1152 case X86ISD::COND_NE: return X86::JNE; 1153 case X86ISD::COND_NO: return X86::JNO; 1154 case X86ISD::COND_NP: return X86::JNP; 1155 case X86ISD::COND_NS: return X86::JNS; 1156 case X86ISD::COND_O: return X86::JO; 1157 case X86ISD::COND_P: return X86::JP; 1158 case X86ISD::COND_S: return X86::JS; 1159 } 1160} 1161 1162/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 1163/// specific condition code. It returns a false if it cannot do a direct 1164/// translation. X86CC is the translated CondCode. Flip is set to true if the 1165/// the order of comparison operands should be flipped. 1166static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC, 1167 bool &Flip) { 1168 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 1169 Flip = false; 1170 X86CC = X86ISD::COND_INVALID; 1171 if (!isFP) { 1172 switch (SetCCOpcode) { 1173 default: break; 1174 case ISD::SETEQ: X86CC = X86ISD::COND_E; break; 1175 case ISD::SETGT: X86CC = X86ISD::COND_G; break; 1176 case ISD::SETGE: X86CC = X86ISD::COND_GE; break; 1177 case ISD::SETLT: X86CC = X86ISD::COND_L; break; 1178 case ISD::SETLE: X86CC = X86ISD::COND_LE; break; 1179 case ISD::SETNE: X86CC = X86ISD::COND_NE; break; 1180 case ISD::SETULT: X86CC = X86ISD::COND_B; break; 1181 case ISD::SETUGT: X86CC = X86ISD::COND_A; break; 1182 case ISD::SETULE: X86CC = X86ISD::COND_BE; break; 1183 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break; 1184 } 1185 } else { 1186 // On a floating point condition, the flags are set as follows: 1187 // ZF PF CF op 1188 // 0 | 0 | 0 | X > Y 1189 // 0 | 0 | 1 | X < Y 1190 // 1 | 0 | 0 | X == Y 1191 // 1 | 1 | 1 | unordered 1192 switch (SetCCOpcode) { 1193 default: break; 1194 case ISD::SETUEQ: 1195 case ISD::SETEQ: X86CC = X86ISD::COND_E; break; 1196 case ISD::SETOLE: Flip = true; // Fallthrough 1197 case ISD::SETOGT: 1198 case ISD::SETGT: X86CC = X86ISD::COND_A; break; 1199 case ISD::SETOLT: Flip = true; // Fallthrough 1200 case ISD::SETOGE: 1201 case ISD::SETGE: X86CC = X86ISD::COND_AE; break; 1202 case ISD::SETUGE: Flip = true; // Fallthrough 1203 case ISD::SETULT: 1204 case ISD::SETLT: X86CC = X86ISD::COND_B; break; 1205 case ISD::SETUGT: Flip = true; // Fallthrough 1206 case ISD::SETULE: 1207 case ISD::SETLE: X86CC = X86ISD::COND_BE; break; 1208 case ISD::SETONE: 1209 case ISD::SETNE: X86CC = X86ISD::COND_NE; break; 1210 case ISD::SETUO: X86CC = X86ISD::COND_P; break; 1211 case ISD::SETO: X86CC = X86ISD::COND_NP; break; 1212 } 1213 } 1214 1215 return X86CC != X86ISD::COND_INVALID; 1216} 1217 1218/// hasFPCMov - is there a floating point cmov for the specific X86 condition 1219/// code. Current x86 isa includes the following FP cmov instructions: 1220/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 1221static bool hasFPCMov(unsigned X86CC) { 1222 switch (X86CC) { 1223 default: 1224 return false; 1225 case X86ISD::COND_B: 1226 case X86ISD::COND_BE: 1227 case X86ISD::COND_E: 1228 case X86ISD::COND_P: 1229 case X86ISD::COND_A: 1230 case X86ISD::COND_AE: 1231 case X86ISD::COND_NE: 1232 case X86ISD::COND_NP: 1233 return true; 1234 } 1235} 1236 1237MachineBasicBlock * 1238X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1239 MachineBasicBlock *BB) { 1240 switch (MI->getOpcode()) { 1241 default: assert(false && "Unexpected instr type to insert"); 1242 case X86::CMOV_FR32: 1243 case X86::CMOV_FR64: { 1244 // To "insert" a SELECT_CC instruction, we actually have to insert the 1245 // diamond control-flow pattern. The incoming instruction knows the 1246 // destination vreg to set, the condition code register to branch on, the 1247 // true/false values to select between, and a branch opcode to use. 1248 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1249 ilist<MachineBasicBlock>::iterator It = BB; 1250 ++It; 1251 1252 // thisMBB: 1253 // ... 1254 // TrueVal = ... 1255 // cmpTY ccX, r1, r2 1256 // bCC copy1MBB 1257 // fallthrough --> copy0MBB 1258 MachineBasicBlock *thisMBB = BB; 1259 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1260 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1261 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue()); 1262 BuildMI(BB, Opc, 1).addMBB(sinkMBB); 1263 MachineFunction *F = BB->getParent(); 1264 F->getBasicBlockList().insert(It, copy0MBB); 1265 F->getBasicBlockList().insert(It, sinkMBB); 1266 // Update machine-CFG edges 1267 BB->addSuccessor(copy0MBB); 1268 BB->addSuccessor(sinkMBB); 1269 1270 // copy0MBB: 1271 // %FalseValue = ... 1272 // # fallthrough to sinkMBB 1273 BB = copy0MBB; 1274 1275 // Update machine-CFG edges 1276 BB->addSuccessor(sinkMBB); 1277 1278 // sinkMBB: 1279 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1280 // ... 1281 BB = sinkMBB; 1282 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg()) 1283 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1284 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1285 1286 delete MI; // The pseudo instruction is gone now. 1287 return BB; 1288 } 1289 1290 case X86::FP_TO_INT16_IN_MEM: 1291 case X86::FP_TO_INT32_IN_MEM: 1292 case X86::FP_TO_INT64_IN_MEM: { 1293 // Change the floating point control register to use "round towards zero" 1294 // mode when truncating to an integer value. 1295 MachineFunction *F = BB->getParent(); 1296 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 1297 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); 1298 1299 // Load the old value of the high byte of the control word... 1300 unsigned OldCW = 1301 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass); 1302 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); 1303 1304 // Set the high part to be round to zero... 1305 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); 1306 1307 // Reload the modified control word now... 1308 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); 1309 1310 // Restore the memory image of control word to original value 1311 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); 1312 1313 // Get the X86 opcode to use. 1314 unsigned Opc; 1315 switch (MI->getOpcode()) { 1316 default: assert(0 && "illegal opcode!"); 1317 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break; 1318 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break; 1319 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break; 1320 } 1321 1322 X86AddressMode AM; 1323 MachineOperand &Op = MI->getOperand(0); 1324 if (Op.isRegister()) { 1325 AM.BaseType = X86AddressMode::RegBase; 1326 AM.Base.Reg = Op.getReg(); 1327 } else { 1328 AM.BaseType = X86AddressMode::FrameIndexBase; 1329 AM.Base.FrameIndex = Op.getFrameIndex(); 1330 } 1331 Op = MI->getOperand(1); 1332 if (Op.isImmediate()) 1333 AM.Scale = Op.getImmedValue(); 1334 Op = MI->getOperand(2); 1335 if (Op.isImmediate()) 1336 AM.IndexReg = Op.getImmedValue(); 1337 Op = MI->getOperand(3); 1338 if (Op.isGlobalAddress()) { 1339 AM.GV = Op.getGlobal(); 1340 } else { 1341 AM.Disp = Op.getImmedValue(); 1342 } 1343 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg()); 1344 1345 // Reload the original control word now. 1346 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); 1347 1348 delete MI; // The pseudo instruction is gone now. 1349 return BB; 1350 } 1351 } 1352} 1353 1354 1355//===----------------------------------------------------------------------===// 1356// X86 Custom Lowering Hooks 1357//===----------------------------------------------------------------------===// 1358 1359/// LowerOperation - Provide custom lowering hooks for some operations. 1360/// 1361SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1362 switch (Op.getOpcode()) { 1363 default: assert(0 && "Should not custom lower this!"); 1364 case ISD::ADD_PARTS: 1365 case ISD::SUB_PARTS: { 1366 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 && 1367 "Not an i64 add/sub!"); 1368 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS; 1369 std::vector<MVT::ValueType> Tys; 1370 Tys.push_back(MVT::i32); 1371 Tys.push_back(MVT::Flag); 1372 std::vector<SDOperand> Ops; 1373 Ops.push_back(Op.getOperand(0)); 1374 Ops.push_back(Op.getOperand(2)); 1375 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG, 1376 Tys, Ops); 1377 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32, 1378 Op.getOperand(1), Op.getOperand(3), 1379 Lo.getValue(1)); 1380 Tys.clear(); 1381 Tys.push_back(MVT::i32); 1382 Tys.push_back(MVT::i32); 1383 Ops.clear(); 1384 Ops.push_back(Lo); 1385 Ops.push_back(Hi); 1386 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 1387 } 1388 case ISD::SHL_PARTS: 1389 case ISD::SRA_PARTS: 1390 case ISD::SRL_PARTS: { 1391 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 1392 "Not an i64 shift!"); 1393 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 1394 SDOperand ShOpLo = Op.getOperand(0); 1395 SDOperand ShOpHi = Op.getOperand(1); 1396 SDOperand ShAmt = Op.getOperand(2); 1397 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, 1398 DAG.getConstant(31, MVT::i8)) 1399 : DAG.getConstant(0, MVT::i32); 1400 1401 SDOperand Tmp2, Tmp3; 1402 if (Op.getOpcode() == ISD::SHL_PARTS) { 1403 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt); 1404 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt); 1405 } else { 1406 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt); 1407 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); 1408 } 1409 1410 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag, 1411 ShAmt, DAG.getConstant(32, MVT::i8)); 1412 1413 SDOperand Hi, Lo; 1414 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 1415 1416 std::vector<MVT::ValueType> Tys; 1417 Tys.push_back(MVT::i32); 1418 Tys.push_back(MVT::Flag); 1419 std::vector<SDOperand> Ops; 1420 if (Op.getOpcode() == ISD::SHL_PARTS) { 1421 Ops.push_back(Tmp2); 1422 Ops.push_back(Tmp3); 1423 Ops.push_back(CC); 1424 Ops.push_back(InFlag); 1425 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1426 InFlag = Hi.getValue(1); 1427 1428 Ops.clear(); 1429 Ops.push_back(Tmp3); 1430 Ops.push_back(Tmp1); 1431 Ops.push_back(CC); 1432 Ops.push_back(InFlag); 1433 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1434 } else { 1435 Ops.push_back(Tmp2); 1436 Ops.push_back(Tmp3); 1437 Ops.push_back(CC); 1438 Ops.push_back(InFlag); 1439 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1440 InFlag = Lo.getValue(1); 1441 1442 Ops.clear(); 1443 Ops.push_back(Tmp3); 1444 Ops.push_back(Tmp1); 1445 Ops.push_back(CC); 1446 Ops.push_back(InFlag); 1447 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops); 1448 } 1449 1450 Tys.clear(); 1451 Tys.push_back(MVT::i32); 1452 Tys.push_back(MVT::i32); 1453 Ops.clear(); 1454 Ops.push_back(Lo); 1455 Ops.push_back(Hi); 1456 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 1457 } 1458 case ISD::SINT_TO_FP: { 1459 assert(Op.getOperand(0).getValueType() <= MVT::i64 && 1460 Op.getOperand(0).getValueType() >= MVT::i16 && 1461 "Unknown SINT_TO_FP to lower!"); 1462 1463 SDOperand Result; 1464 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 1465 unsigned Size = MVT::getSizeInBits(SrcVT)/8; 1466 MachineFunction &MF = DAG.getMachineFunction(); 1467 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 1468 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1469 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other, 1470 DAG.getEntryNode(), Op.getOperand(0), 1471 StackSlot, DAG.getSrcValue(NULL)); 1472 1473 // Build the FILD 1474 std::vector<MVT::ValueType> Tys; 1475 Tys.push_back(MVT::f64); 1476 Tys.push_back(MVT::Other); 1477 Tys.push_back(MVT::Flag); 1478 std::vector<SDOperand> Ops; 1479 Ops.push_back(Chain); 1480 Ops.push_back(StackSlot); 1481 Ops.push_back(DAG.getValueType(SrcVT)); 1482 Result = DAG.getNode(X86ISD::FILD, Tys, Ops); 1483 1484 if (X86ScalarSSE) { 1485 Chain = Result.getValue(1); 1486 SDOperand InFlag = Result.getValue(2); 1487 1488 // FIXME: Currently the FST is flagged to the FILD. This 1489 // shouldn't be necessary except that RFP cannot be live across 1490 // multiple blocks. When stackifier is fixed, they can be uncoupled. 1491 MachineFunction &MF = DAG.getMachineFunction(); 1492 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 1493 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1494 std::vector<MVT::ValueType> Tys; 1495 Tys.push_back(MVT::Other); 1496 std::vector<SDOperand> Ops; 1497 Ops.push_back(Chain); 1498 Ops.push_back(Result); 1499 Ops.push_back(StackSlot); 1500 Ops.push_back(DAG.getValueType(Op.getValueType())); 1501 Ops.push_back(InFlag); 1502 Chain = DAG.getNode(X86ISD::FST, Tys, Ops); 1503 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, 1504 DAG.getSrcValue(NULL)); 1505 } 1506 1507 return Result; 1508 } 1509 case ISD::FP_TO_SINT: { 1510 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 1511 "Unknown FP_TO_SINT to lower!"); 1512 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 1513 // stack slot. 1514 MachineFunction &MF = DAG.getMachineFunction(); 1515 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 1516 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 1517 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1518 1519 unsigned Opc; 1520 switch (Op.getValueType()) { 1521 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 1522 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 1523 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 1524 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 1525 } 1526 1527 SDOperand Chain = DAG.getEntryNode(); 1528 SDOperand Value = Op.getOperand(0); 1529 if (X86ScalarSSE) { 1530 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 1531 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot, 1532 DAG.getSrcValue(0)); 1533 std::vector<MVT::ValueType> Tys; 1534 Tys.push_back(MVT::f64); 1535 Tys.push_back(MVT::Other); 1536 std::vector<SDOperand> Ops; 1537 Ops.push_back(Chain); 1538 Ops.push_back(StackSlot); 1539 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType())); 1540 Value = DAG.getNode(X86ISD::FLD, Tys, Ops); 1541 Chain = Value.getValue(1); 1542 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 1543 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 1544 } 1545 1546 // Build the FP_TO_INT*_IN_MEM 1547 std::vector<SDOperand> Ops; 1548 Ops.push_back(Chain); 1549 Ops.push_back(Value); 1550 Ops.push_back(StackSlot); 1551 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); 1552 1553 // Load the result. 1554 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, 1555 DAG.getSrcValue(NULL)); 1556 } 1557 case ISD::READCYCLECOUNTER: { 1558 std::vector<MVT::ValueType> Tys; 1559 Tys.push_back(MVT::Other); 1560 Tys.push_back(MVT::Flag); 1561 std::vector<SDOperand> Ops; 1562 Ops.push_back(Op.getOperand(0)); 1563 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops); 1564 Ops.clear(); 1565 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); 1566 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, 1567 MVT::i32, Ops[0].getValue(2))); 1568 Ops.push_back(Ops[1].getValue(1)); 1569 Tys[0] = Tys[1] = MVT::i32; 1570 Tys.push_back(MVT::Other); 1571 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 1572 } 1573 case ISD::FABS: { 1574 MVT::ValueType VT = Op.getValueType(); 1575 const Type *OpNTy = MVT::getTypeForValueType(VT); 1576 std::vector<Constant*> CV; 1577 if (VT == MVT::f64) { 1578 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63)))); 1579 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1580 } else { 1581 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31)))); 1582 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1583 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1584 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1585 } 1586 Constant *CS = ConstantStruct::get(CV); 1587 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 1588 SDOperand Mask 1589 = DAG.getNode(X86ISD::LOAD_PACK, 1590 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 1591 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 1592 } 1593 case ISD::FNEG: { 1594 MVT::ValueType VT = Op.getValueType(); 1595 const Type *OpNTy = MVT::getTypeForValueType(VT); 1596 std::vector<Constant*> CV; 1597 if (VT == MVT::f64) { 1598 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63))); 1599 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1600 } else { 1601 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31))); 1602 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1603 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1604 CV.push_back(ConstantFP::get(OpNTy, 0.0)); 1605 } 1606 Constant *CS = ConstantStruct::get(CV); 1607 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4); 1608 SDOperand Mask 1609 = DAG.getNode(X86ISD::LOAD_PACK, 1610 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 1611 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 1612 } 1613 case ISD::SETCC: { 1614 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 1615 SDOperand Cond; 1616 SDOperand CC = Op.getOperand(2); 1617 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 1618 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); 1619 bool Flip; 1620 unsigned X86CC; 1621 if (translateX86CC(CC, isFP, X86CC, Flip)) { 1622 if (Flip) 1623 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1624 Op.getOperand(1), Op.getOperand(0)); 1625 else 1626 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1627 Op.getOperand(0), Op.getOperand(1)); 1628 return DAG.getNode(X86ISD::SETCC, MVT::i8, 1629 DAG.getConstant(X86CC, MVT::i8), Cond); 1630 } else { 1631 assert(isFP && "Illegal integer SetCC!"); 1632 1633 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1634 Op.getOperand(0), Op.getOperand(1)); 1635 std::vector<MVT::ValueType> Tys; 1636 std::vector<SDOperand> Ops; 1637 switch (SetCCOpcode) { 1638 default: assert(false && "Illegal floating point SetCC!"); 1639 case ISD::SETOEQ: { // !PF & ZF 1640 Tys.push_back(MVT::i8); 1641 Tys.push_back(MVT::Flag); 1642 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8)); 1643 Ops.push_back(Cond); 1644 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1645 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1646 DAG.getConstant(X86ISD::COND_E, MVT::i8), 1647 Tmp1.getValue(1)); 1648 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 1649 } 1650 case ISD::SETUNE: { // PF | !ZF 1651 Tys.push_back(MVT::i8); 1652 Tys.push_back(MVT::Flag); 1653 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8)); 1654 Ops.push_back(Cond); 1655 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1656 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 1657 DAG.getConstant(X86ISD::COND_NE, MVT::i8), 1658 Tmp1.getValue(1)); 1659 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 1660 } 1661 } 1662 } 1663 } 1664 case ISD::SELECT: { 1665 MVT::ValueType VT = Op.getValueType(); 1666 bool isFP = MVT::isFloatingPoint(VT); 1667 bool isFPStack = isFP && !X86ScalarSSE; 1668 bool isFPSSE = isFP && X86ScalarSSE; 1669 bool addTest = false; 1670 SDOperand Op0 = Op.getOperand(0); 1671 SDOperand Cond, CC; 1672 if (Op0.getOpcode() == ISD::SETCC) 1673 Op0 = LowerOperation(Op0, DAG); 1674 1675 if (Op0.getOpcode() == X86ISD::SETCC) { 1676 // If condition flag is set by a X86ISD::CMP, then make a copy of it 1677 // (since flag operand cannot be shared). If the X86ISD::SETCC does not 1678 // have another use it will be eliminated. 1679 // If the X86ISD::SETCC has more than one use, then it's probably better 1680 // to use a test instead of duplicating the X86ISD::CMP (for register 1681 // pressure reason). 1682 if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) { 1683 if (!Op0.hasOneUse()) { 1684 std::vector<MVT::ValueType> Tys; 1685 for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i) 1686 Tys.push_back(Op0.Val->getValueType(i)); 1687 std::vector<SDOperand> Ops; 1688 for (unsigned i = 0; i < Op0.getNumOperands(); ++i) 1689 Ops.push_back(Op0.getOperand(i)); 1690 Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1691 } 1692 1693 CC = Op0.getOperand(0); 1694 Cond = Op0.getOperand(1); 1695 // Make a copy as flag result cannot be used by more than one. 1696 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1697 Cond.getOperand(0), Cond.getOperand(1)); 1698 addTest = 1699 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); 1700 } else 1701 addTest = true; 1702 } else 1703 addTest = true; 1704 1705 if (addTest) { 1706 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 1707 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0); 1708 } 1709 1710 std::vector<MVT::ValueType> Tys; 1711 Tys.push_back(Op.getValueType()); 1712 Tys.push_back(MVT::Flag); 1713 std::vector<SDOperand> Ops; 1714 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 1715 // condition is true. 1716 Ops.push_back(Op.getOperand(2)); 1717 Ops.push_back(Op.getOperand(1)); 1718 Ops.push_back(CC); 1719 Ops.push_back(Cond); 1720 return DAG.getNode(X86ISD::CMOV, Tys, Ops); 1721 } 1722 case ISD::BRCOND: { 1723 bool addTest = false; 1724 SDOperand Cond = Op.getOperand(1); 1725 SDOperand Dest = Op.getOperand(2); 1726 SDOperand CC; 1727 if (Cond.getOpcode() == ISD::SETCC) 1728 Cond = LowerOperation(Cond, DAG); 1729 1730 if (Cond.getOpcode() == X86ISD::SETCC) { 1731 // If condition flag is set by a X86ISD::CMP, then make a copy of it 1732 // (since flag operand cannot be shared). If the X86ISD::SETCC does not 1733 // have another use it will be eliminated. 1734 // If the X86ISD::SETCC has more than one use, then it's probably better 1735 // to use a test instead of duplicating the X86ISD::CMP (for register 1736 // pressure reason). 1737 if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) { 1738 if (!Cond.hasOneUse()) { 1739 std::vector<MVT::ValueType> Tys; 1740 for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i) 1741 Tys.push_back(Cond.Val->getValueType(i)); 1742 std::vector<SDOperand> Ops; 1743 for (unsigned i = 0; i < Cond.getNumOperands(); ++i) 1744 Ops.push_back(Cond.getOperand(i)); 1745 Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops); 1746 } 1747 1748 CC = Cond.getOperand(0); 1749 Cond = Cond.getOperand(1); 1750 // Make a copy as flag result cannot be used by more than one. 1751 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 1752 Cond.getOperand(0), Cond.getOperand(1)); 1753 } else 1754 addTest = true; 1755 } else 1756 addTest = true; 1757 1758 if (addTest) { 1759 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); 1760 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); 1761 } 1762 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 1763 Op.getOperand(0), Op.getOperand(2), CC, Cond); 1764 } 1765 case ISD::MEMSET: { 1766 SDOperand InFlag; 1767 SDOperand Chain = Op.getOperand(0); 1768 unsigned Align = 1769 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 1770 if (Align == 0) Align = 1; 1771 1772 MVT::ValueType AVT; 1773 SDOperand Count; 1774 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) { 1775 unsigned ValReg; 1776 unsigned Val = ValC->getValue() & 255; 1777 1778 // If the value is a constant, then we can potentially use larger sets. 1779 switch (Align & 3) { 1780 case 2: // WORD aligned 1781 AVT = MVT::i16; 1782 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) 1783 Count = DAG.getConstant(I->getValue() / 2, MVT::i32); 1784 else 1785 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), 1786 DAG.getConstant(1, MVT::i8)); 1787 Val = (Val << 8) | Val; 1788 ValReg = X86::AX; 1789 break; 1790 case 0: // DWORD aligned 1791 AVT = MVT::i32; 1792 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) 1793 Count = DAG.getConstant(I->getValue() / 4, MVT::i32); 1794 else 1795 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), 1796 DAG.getConstant(2, MVT::i8)); 1797 Val = (Val << 8) | Val; 1798 Val = (Val << 16) | Val; 1799 ValReg = X86::EAX; 1800 break; 1801 default: // Byte aligned 1802 AVT = MVT::i8; 1803 Count = Op.getOperand(3); 1804 ValReg = X86::AL; 1805 break; 1806 } 1807 1808 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 1809 InFlag); 1810 InFlag = Chain.getValue(1); 1811 } else { 1812 AVT = MVT::i8; 1813 Count = Op.getOperand(3); 1814 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); 1815 InFlag = Chain.getValue(1); 1816 } 1817 1818 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag); 1819 InFlag = Chain.getValue(1); 1820 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag); 1821 InFlag = Chain.getValue(1); 1822 1823 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain, 1824 DAG.getValueType(AVT), InFlag); 1825 } 1826 case ISD::MEMCPY: { 1827 SDOperand Chain = Op.getOperand(0); 1828 unsigned Align = 1829 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 1830 if (Align == 0) Align = 1; 1831 1832 MVT::ValueType AVT; 1833 SDOperand Count; 1834 switch (Align & 3) { 1835 case 2: // WORD aligned 1836 AVT = MVT::i16; 1837 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) 1838 Count = DAG.getConstant(I->getValue() / 2, MVT::i32); 1839 else 1840 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), 1841 DAG.getConstant(1, MVT::i8)); 1842 break; 1843 case 0: // DWORD aligned 1844 AVT = MVT::i32; 1845 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3))) 1846 Count = DAG.getConstant(I->getValue() / 4, MVT::i32); 1847 else 1848 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3), 1849 DAG.getConstant(2, MVT::i8)); 1850 break; 1851 default: // Byte aligned 1852 AVT = MVT::i8; 1853 Count = Op.getOperand(3); 1854 break; 1855 } 1856 1857 SDOperand InFlag; 1858 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag); 1859 InFlag = Chain.getValue(1); 1860 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag); 1861 InFlag = Chain.getValue(1); 1862 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag); 1863 InFlag = Chain.getValue(1); 1864 1865 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain, 1866 DAG.getValueType(AVT), InFlag); 1867 } 1868 case ISD::GlobalAddress: { 1869 SDOperand Result; 1870 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1871 // For Darwin, external and weak symbols are indirect, so we want to load 1872 // the value at address GV, not the value of GV itself. This means that 1873 // the GlobalAddress must be in the base or index register of the address, 1874 // not the GV offset field. 1875 if (getTargetMachine(). 1876 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() && 1877 (GV->hasWeakLinkage() || GV->isExternal())) 1878 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), 1879 DAG.getTargetGlobalAddress(GV, getPointerTy()), 1880 DAG.getSrcValue(NULL)); 1881 return Result; 1882 } 1883 case ISD::VASTART: { 1884 // vastart just stores the address of the VarArgsFrameIndex slot into the 1885 // memory location argument. 1886 // FIXME: Replace MVT::i32 with PointerTy 1887 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 1888 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 1889 Op.getOperand(1), Op.getOperand(2)); 1890 } 1891 case ISD::RET: { 1892 SDOperand Copy; 1893 1894 switch(Op.getNumOperands()) { 1895 default: 1896 assert(0 && "Do not know how to return this many arguments!"); 1897 abort(); 1898 case 1: 1899 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0), 1900 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 1901 case 2: { 1902 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 1903 if (MVT::isInteger(ArgVT)) 1904 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1), 1905 SDOperand()); 1906 else if (!X86ScalarSSE) { 1907 std::vector<MVT::ValueType> Tys; 1908 Tys.push_back(MVT::Other); 1909 Tys.push_back(MVT::Flag); 1910 std::vector<SDOperand> Ops; 1911 Ops.push_back(Op.getOperand(0)); 1912 Ops.push_back(Op.getOperand(1)); 1913 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); 1914 } else { 1915 SDOperand MemLoc, Chain; 1916 SDOperand Value = Op.getOperand(1); 1917 1918 if (Value.getOpcode() == ISD::LOAD) { 1919 Chain = Value.getOperand(0); 1920 MemLoc = Value.getOperand(1); 1921 } else { 1922 // Spill the value to memory and reload it into top of stack. 1923 unsigned Size = MVT::getSizeInBits(ArgVT)/8; 1924 MachineFunction &MF = DAG.getMachineFunction(); 1925 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 1926 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy()); 1927 Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), 1928 Value, MemLoc, DAG.getSrcValue(0)); 1929 } 1930 std::vector<MVT::ValueType> Tys; 1931 Tys.push_back(MVT::f64); 1932 Tys.push_back(MVT::Other); 1933 std::vector<SDOperand> Ops; 1934 Ops.push_back(Chain); 1935 Ops.push_back(MemLoc); 1936 Ops.push_back(DAG.getValueType(ArgVT)); 1937 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops); 1938 Tys.clear(); 1939 Tys.push_back(MVT::Other); 1940 Tys.push_back(MVT::Flag); 1941 Ops.clear(); 1942 Ops.push_back(Copy.getValue(1)); 1943 Ops.push_back(Copy); 1944 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops); 1945 } 1946 break; 1947 } 1948 case 3: 1949 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2), 1950 SDOperand()); 1951 Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1)); 1952 break; 1953 } 1954 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, 1955 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16), 1956 Copy.getValue(1)); 1957 } 1958 } 1959} 1960 1961const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 1962 switch (Opcode) { 1963 default: return NULL; 1964 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG"; 1965 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG"; 1966 case X86ISD::ADC: return "X86ISD::ADC"; 1967 case X86ISD::SBB: return "X86ISD::SBB"; 1968 case X86ISD::SHLD: return "X86ISD::SHLD"; 1969 case X86ISD::SHRD: return "X86ISD::SHRD"; 1970 case X86ISD::FAND: return "X86ISD::FAND"; 1971 case X86ISD::FXOR: return "X86ISD::FXOR"; 1972 case X86ISD::FILD: return "X86ISD::FILD"; 1973 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 1974 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 1975 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 1976 case X86ISD::FLD: return "X86ISD::FLD"; 1977 case X86ISD::FST: return "X86ISD::FST"; 1978 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT"; 1979 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT"; 1980 case X86ISD::CALL: return "X86ISD::CALL"; 1981 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 1982 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 1983 case X86ISD::CMP: return "X86ISD::CMP"; 1984 case X86ISD::TEST: return "X86ISD::TEST"; 1985 case X86ISD::SETCC: return "X86ISD::SETCC"; 1986 case X86ISD::CMOV: return "X86ISD::CMOV"; 1987 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 1988 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 1989 case X86ISD::REP_STOS: return "X86ISD::RET_STOS"; 1990 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS"; 1991 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK"; 1992 } 1993} 1994 1995bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op, 1996 uint64_t Mask) const { 1997 1998 unsigned Opc = Op.getOpcode(); 1999 2000 switch (Opc) { 2001 default: 2002 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node"); 2003 break; 2004 case X86ISD::SETCC: return (Mask & 1) == 0; 2005 } 2006 2007 return false; 2008} 2009 2010std::vector<unsigned> X86TargetLowering:: 2011getRegForInlineAsmConstraint(const std::string &Constraint) const { 2012 if (Constraint.size() == 1) { 2013 // FIXME: not handling fp-stack yet! 2014 // FIXME: not handling MMX registers yet ('y' constraint). 2015 switch (Constraint[0]) { // GCC X86 Constraint Letters 2016 default: break; // Unknown constriant letter 2017 case 'r': // GENERAL_REGS 2018 case 'R': // LEGACY_REGS 2019 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 2020 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); 2021 case 'l': // INDEX_REGS 2022 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 2023 X86::ESI, X86::EDI, X86::EBP, 0); 2024 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 2025 case 'Q': // Q_REGS 2026 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0); 2027 case 'x': // SSE_REGS if SSE1 allowed 2028 if (Subtarget->hasSSE1()) 2029 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2030 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 2031 0); 2032 return std::vector<unsigned>(); 2033 case 'Y': // SSE_REGS if SSE2 allowed 2034 if (Subtarget->hasSSE2()) 2035 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2036 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 2037 0); 2038 return std::vector<unsigned>(); 2039 } 2040 } 2041 2042 // Handle explicit register names. 2043 return TargetLowering::getRegForInlineAsmConstraint(Constraint); 2044} 2045