X86ISelLowering.cpp revision 1449f29100a0d3950a1a17e962f7cf718198e283
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Function.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCExpr.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52using namespace llvm; 53using namespace dwarf; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57static cl::opt<bool> 58DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 59 60// Disable16Bit - 16-bit operations typically have a larger encoding than 61// corresponding 32-bit instructions, and 16-bit code is slow on some 62// processors. This is an experimental flag to disable 16-bit operations 63// (which forces them to be Legalized to 32-bit operations). 64static cl::opt<bool> 65Disable16Bit("disable-16bit", cl::Hidden, 66 cl::desc("Disable use of 16-bit instructions")); 67 68// Forward declarations. 69static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 70 SDValue V2); 71 72static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 73 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 74 default: llvm_unreachable("unknown subtarget type"); 75 case X86Subtarget::isDarwin: 76 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 77 return new X8664_MachoTargetObjectFile(); 78 return new TargetLoweringObjectFileMachO(); 79 case X86Subtarget::isELF: 80 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 81 return new X8664_ELFTargetObjectFile(TM); 82 return new X8632_ELFTargetObjectFile(TM); 83 case X86Subtarget::isMingw: 84 case X86Subtarget::isCygwin: 85 case X86Subtarget::isWindows: 86 return new TargetLoweringObjectFileCOFF(); 87 } 88} 89 90X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 91 : TargetLowering(TM, createTLOF(TM)) { 92 Subtarget = &TM.getSubtarget<X86Subtarget>(); 93 X86ScalarSSEf64 = Subtarget->hasSSE2(); 94 X86ScalarSSEf32 = Subtarget->hasSSE1(); 95 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 96 97 RegInfo = TM.getRegisterInfo(); 98 TD = getTargetData(); 99 100 // Set up the TargetLowering object. 101 102 // X86 is weird, it always uses i8 for shift amounts and setcc results. 103 setShiftAmountType(MVT::i8); 104 setBooleanContents(ZeroOrOneBooleanContent); 105 setSchedulingPreference(SchedulingForRegPressure); 106 setStackPointerRegisterToSaveRestore(X86StackPtr); 107 108 if (Subtarget->isTargetDarwin()) { 109 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 110 setUseUnderscoreSetJmp(false); 111 setUseUnderscoreLongJmp(false); 112 } else if (Subtarget->isTargetMingw()) { 113 // MS runtime is weird: it exports _setjmp, but longjmp! 114 setUseUnderscoreSetJmp(true); 115 setUseUnderscoreLongJmp(false); 116 } else { 117 setUseUnderscoreSetJmp(true); 118 setUseUnderscoreLongJmp(true); 119 } 120 121 // Set up the register classes. 122 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 123 if (!Disable16Bit) 124 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 125 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 126 if (Subtarget->is64Bit()) 127 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 128 129 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 130 131 // We don't accept any truncstore of integer registers. 132 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 133 if (!Disable16Bit) 134 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 135 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 136 if (!Disable16Bit) 137 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 139 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 140 141 // SETOEQ and SETUNE require checking two conditions. 142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 148 149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 150 // operation. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 154 155 if (Subtarget->is64Bit()) { 156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 158 } else if (!UseSoftFloat) { 159 if (X86ScalarSSEf64) { 160 // We have an impenetrably clever algorithm for ui64->double only. 161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 162 } 163 // We have an algorithm for SSE2, and we turn this into a 64-bit 164 // FILD for other targets. 165 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 166 } 167 168 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 169 // this operation. 170 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 171 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 172 173 if (!UseSoftFloat) { 174 // SSE has no i16 to fp conversion, only i32 175 if (X86ScalarSSEf32) { 176 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 177 // f32 and f64 cases are Legal, f80 case is not 178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 179 } else { 180 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 181 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 182 } 183 } else { 184 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 185 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 186 } 187 188 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 189 // are Legal, f80 is custom lowered. 190 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 191 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 192 193 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 194 // this operation. 195 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 196 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 197 198 if (X86ScalarSSEf32) { 199 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 200 // f32 and f64 cases are Legal, f80 case is not 201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 202 } else { 203 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 204 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 205 } 206 207 // Handle FP_TO_UINT by promoting the destination to a larger signed 208 // conversion. 209 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 210 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 211 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 212 213 if (Subtarget->is64Bit()) { 214 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 215 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 216 } else if (!UseSoftFloat) { 217 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 218 // Expand FP_TO_UINT into a select. 219 // FIXME: We would like to use a Custom expander here eventually to do 220 // the optimal thing for SSE vs. the default expansion in the legalizer. 221 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 222 else 223 // With SSE3 we can use fisttpll to convert to a signed i64; without 224 // SSE, we're stuck with a fistpll. 225 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 226 } 227 228 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 229 if (!X86ScalarSSEf64) { 230 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 231 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 232 } 233 234 // Scalar integer divide and remainder are lowered to use operations that 235 // produce two results, to match the available instructions. This exposes 236 // the two-result form to trivial CSE, which is able to combine x/y and x%y 237 // into a single instruction. 238 // 239 // Scalar integer multiply-high is also lowered to use two-result 240 // operations, to match the available instructions. However, plain multiply 241 // (low) operations are left as Legal, as there are single-result 242 // instructions for this in x86. Using the two-result multiply instructions 243 // when both high and low results are needed must be arranged by dagcombine. 244 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 245 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 246 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 247 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 248 setOperationAction(ISD::SREM , MVT::i8 , Expand); 249 setOperationAction(ISD::UREM , MVT::i8 , Expand); 250 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 251 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 252 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 253 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 254 setOperationAction(ISD::SREM , MVT::i16 , Expand); 255 setOperationAction(ISD::UREM , MVT::i16 , Expand); 256 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 257 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 258 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 259 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 260 setOperationAction(ISD::SREM , MVT::i32 , Expand); 261 setOperationAction(ISD::UREM , MVT::i32 , Expand); 262 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 263 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 264 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 265 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 266 setOperationAction(ISD::SREM , MVT::i64 , Expand); 267 setOperationAction(ISD::UREM , MVT::i64 , Expand); 268 269 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 270 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 271 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 272 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 273 if (Subtarget->is64Bit()) 274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 276 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 278 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 279 setOperationAction(ISD::FREM , MVT::f32 , Expand); 280 setOperationAction(ISD::FREM , MVT::f64 , Expand); 281 setOperationAction(ISD::FREM , MVT::f80 , Expand); 282 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 283 284 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 287 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 288 if (Disable16Bit) { 289 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 290 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 291 } else { 292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 294 } 295 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 296 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 297 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 298 if (Subtarget->is64Bit()) { 299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 300 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 301 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 302 } 303 304 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 305 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 306 307 // These should be promoted to a larger select which is supported. 308 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 309 // X86 wants to expand cmov itself. 310 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 311 if (Disable16Bit) 312 setOperationAction(ISD::SELECT , MVT::i16 , Expand); 313 else 314 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 315 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 316 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 317 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 318 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 319 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 320 if (Disable16Bit) 321 setOperationAction(ISD::SETCC , MVT::i16 , Expand); 322 else 323 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 324 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 325 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 326 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 327 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 328 if (Subtarget->is64Bit()) { 329 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 330 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 331 } 332 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 333 334 // Darwin ABI issue. 335 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 336 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 337 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 338 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 339 if (Subtarget->is64Bit()) 340 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 341 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 342 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 343 if (Subtarget->is64Bit()) { 344 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 345 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 346 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 347 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 348 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 349 } 350 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 351 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 352 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 353 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 354 if (Subtarget->is64Bit()) { 355 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 356 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 357 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 358 } 359 360 if (Subtarget->hasSSE1()) 361 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 362 363 if (!Subtarget->hasSSE2()) 364 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 365 366 // Expand certain atomics 367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 371 372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 376 377 if (!Subtarget->is64Bit()) { 378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 385 } 386 387 // FIXME - use subtarget debug flags 388 if (!Subtarget->isTargetDarwin() && 389 !Subtarget->isTargetELF() && 390 !Subtarget->isTargetCygMing()) { 391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 392 } 393 394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 398 if (Subtarget->is64Bit()) { 399 setExceptionPointerRegister(X86::RAX); 400 setExceptionSelectorRegister(X86::RDX); 401 } else { 402 setExceptionPointerRegister(X86::EAX); 403 setExceptionSelectorRegister(X86::EDX); 404 } 405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 407 408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 409 410 setOperationAction(ISD::TRAP, MVT::Other, Legal); 411 412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 413 setOperationAction(ISD::VASTART , MVT::Other, Custom); 414 setOperationAction(ISD::VAEND , MVT::Other, Expand); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::VAARG , MVT::Other, Custom); 417 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 418 } else { 419 setOperationAction(ISD::VAARG , MVT::Other, Expand); 420 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 421 } 422 423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 425 if (Subtarget->is64Bit()) 426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 427 if (Subtarget->isTargetCygMing()) 428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 429 else 430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 431 432 if (!UseSoftFloat && X86ScalarSSEf64) { 433 // f32 and f64 use SSE. 434 // Set up the FP register classes. 435 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 436 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 437 438 // Use ANDPD to simulate FABS. 439 setOperationAction(ISD::FABS , MVT::f64, Custom); 440 setOperationAction(ISD::FABS , MVT::f32, Custom); 441 442 // Use XORP to simulate FNEG. 443 setOperationAction(ISD::FNEG , MVT::f64, Custom); 444 setOperationAction(ISD::FNEG , MVT::f32, Custom); 445 446 // Use ANDPD and ORPD to simulate FCOPYSIGN. 447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 449 450 // We don't support sin/cos/fmod 451 setOperationAction(ISD::FSIN , MVT::f64, Expand); 452 setOperationAction(ISD::FCOS , MVT::f64, Expand); 453 setOperationAction(ISD::FSIN , MVT::f32, Expand); 454 setOperationAction(ISD::FCOS , MVT::f32, Expand); 455 456 // Expand FP immediates into loads from the stack, except for the special 457 // cases we handle. 458 addLegalFPImmediate(APFloat(+0.0)); // xorpd 459 addLegalFPImmediate(APFloat(+0.0f)); // xorps 460 } else if (!UseSoftFloat && X86ScalarSSEf32) { 461 // Use SSE for f32, x87 for f64. 462 // Set up the FP register classes. 463 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 465 466 // Use ANDPS to simulate FABS. 467 setOperationAction(ISD::FABS , MVT::f32, Custom); 468 469 // Use XORP to simulate FNEG. 470 setOperationAction(ISD::FNEG , MVT::f32, Custom); 471 472 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 473 474 // Use ANDPS and ORPS to simulate FCOPYSIGN. 475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 477 478 // We don't support sin/cos/fmod 479 setOperationAction(ISD::FSIN , MVT::f32, Expand); 480 setOperationAction(ISD::FCOS , MVT::f32, Expand); 481 482 // Special cases we handle for FP constants. 483 addLegalFPImmediate(APFloat(+0.0f)); // xorps 484 addLegalFPImmediate(APFloat(+0.0)); // FLD0 485 addLegalFPImmediate(APFloat(+1.0)); // FLD1 486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 488 489 if (!UnsafeFPMath) { 490 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 491 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 492 } 493 } else if (!UseSoftFloat) { 494 // f32 and f64 in x87. 495 // Set up the FP register classes. 496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 498 499 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 500 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 503 504 if (!UnsafeFPMath) { 505 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 506 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 507 } 508 addLegalFPImmediate(APFloat(+0.0)); // FLD0 509 addLegalFPImmediate(APFloat(+1.0)); // FLD1 510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 516 } 517 518 // Long double always uses X87. 519 if (!UseSoftFloat) { 520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 521 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 523 { 524 bool ignored; 525 APFloat TmpFlt(+0.0); 526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 527 &ignored); 528 addLegalFPImmediate(TmpFlt); // FLD0 529 TmpFlt.changeSign(); 530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 531 APFloat TmpFlt2(+1.0); 532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 533 &ignored); 534 addLegalFPImmediate(TmpFlt2); // FLD1 535 TmpFlt2.changeSign(); 536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 537 } 538 539 if (!UnsafeFPMath) { 540 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 541 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 542 } 543 } 544 545 // Always use a library call for pow. 546 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 547 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 548 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 549 550 setOperationAction(ISD::FLOG, MVT::f80, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 552 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 553 setOperationAction(ISD::FEXP, MVT::f80, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 555 556 // First set operation action for all vector types to either promote 557 // (for widening) or expand (for scalarization). Then we will selectively 558 // turn on ones that can be effectively codegen'd. 559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 616 setTruncStoreAction((MVT::SimpleValueType)VT, 617 (MVT::SimpleValueType)InnerVT, Expand); 618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 621 } 622 623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 624 // with -msoft-float, disable use of MMX as well. 625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 626 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 627 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 628 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 629 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 630 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 631 632 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 633 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 634 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 635 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 636 637 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 638 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 639 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 640 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 641 642 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 643 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 644 645 setOperationAction(ISD::AND, MVT::v8i8, Promote); 646 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 647 setOperationAction(ISD::AND, MVT::v4i16, Promote); 648 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 649 setOperationAction(ISD::AND, MVT::v2i32, Promote); 650 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 651 setOperationAction(ISD::AND, MVT::v1i64, Legal); 652 653 setOperationAction(ISD::OR, MVT::v8i8, Promote); 654 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 655 setOperationAction(ISD::OR, MVT::v4i16, Promote); 656 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 657 setOperationAction(ISD::OR, MVT::v2i32, Promote); 658 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 659 setOperationAction(ISD::OR, MVT::v1i64, Legal); 660 661 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 662 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 663 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 664 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 665 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 666 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 667 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 668 669 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 670 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 671 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 672 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 673 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 674 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 675 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 676 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 677 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 678 679 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 680 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 681 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 683 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 684 685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 689 690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 692 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 694 695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 696 697 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 698 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 699 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 700 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 701 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 702 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 703 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 704 } 705 706 if (!UseSoftFloat && Subtarget->hasSSE1()) { 707 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 708 709 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 710 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 711 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 712 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 713 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 714 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 715 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 716 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 717 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 719 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 720 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 721 } 722 723 if (!UseSoftFloat && Subtarget->hasSSE2()) { 724 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 725 726 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 727 // registers cannot be used even for integer operations. 728 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 729 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 730 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 731 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 732 733 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 734 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 735 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 736 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 737 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 738 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 739 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 740 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 741 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 742 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 743 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 744 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 745 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 746 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 747 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 748 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 749 750 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 751 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 752 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 753 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 754 755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 758 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 760 761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 764 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 765 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 766 767 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 768 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 769 EVT VT = (MVT::SimpleValueType)i; 770 // Do not attempt to custom lower non-power-of-2 vectors 771 if (!isPowerOf2_32(VT.getVectorNumElements())) 772 continue; 773 // Do not attempt to custom lower non-128-bit vectors 774 if (!VT.is128BitVector()) 775 continue; 776 setOperationAction(ISD::BUILD_VECTOR, 777 VT.getSimpleVT().SimpleTy, Custom); 778 setOperationAction(ISD::VECTOR_SHUFFLE, 779 VT.getSimpleVT().SimpleTy, Custom); 780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 781 VT.getSimpleVT().SimpleTy, Custom); 782 } 783 784 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 785 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 790 791 if (Subtarget->is64Bit()) { 792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 794 } 795 796 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 797 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 798 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 799 EVT VT = SVT; 800 801 // Do not attempt to promote non-128-bit vectors 802 if (!VT.is128BitVector()) { 803 continue; 804 } 805 setOperationAction(ISD::AND, SVT, Promote); 806 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 807 setOperationAction(ISD::OR, SVT, Promote); 808 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 809 setOperationAction(ISD::XOR, SVT, Promote); 810 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 811 setOperationAction(ISD::LOAD, SVT, Promote); 812 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 813 setOperationAction(ISD::SELECT, SVT, Promote); 814 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 815 } 816 817 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 818 819 // Custom lower v2i64 and v2f64 selects. 820 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 821 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 822 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 823 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 824 825 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 826 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 827 if (!DisableMMX && Subtarget->hasMMX()) { 828 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 829 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 830 } 831 } 832 833 if (Subtarget->hasSSE41()) { 834 // FIXME: Do we need to handle scalar-to-vector here? 835 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 836 837 // i8 and i16 vectors are custom , because the source register and source 838 // source memory operand types are not the same width. f32 vectors are 839 // custom since the immediate controlling the insert encodes additional 840 // information. 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 843 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 845 846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 849 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 850 851 if (Subtarget->is64Bit()) { 852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 854 } 855 } 856 857 if (Subtarget->hasSSE42()) { 858 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 859 } 860 861 if (!UseSoftFloat && Subtarget->hasAVX()) { 862 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 863 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 864 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 865 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 866 867 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 868 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 869 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 870 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 871 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 872 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 873 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 874 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 875 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 876 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 877 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 878 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 879 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 880 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 881 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 882 883 // Operations to consider commented out -v16i16 v32i8 884 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 885 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 886 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 887 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 888 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 889 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 890 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 891 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 892 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 893 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 894 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 895 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 896 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 897 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 898 899 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 900 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 901 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 902 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 903 904 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 905 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 906 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 908 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 909 910 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 911 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 912 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 913 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 916 917#if 0 918 // Not sure we want to do this since there are no 256-bit integer 919 // operations in AVX 920 921 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 922 // This includes 256-bit vectors 923 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 924 EVT VT = (MVT::SimpleValueType)i; 925 926 // Do not attempt to custom lower non-power-of-2 vectors 927 if (!isPowerOf2_32(VT.getVectorNumElements())) 928 continue; 929 930 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 931 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 932 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 933 } 934 935 if (Subtarget->is64Bit()) { 936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 938 } 939#endif 940 941#if 0 942 // Not sure we want to do this since there are no 256-bit integer 943 // operations in AVX 944 945 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 946 // Including 256-bit vectors 947 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 948 EVT VT = (MVT::SimpleValueType)i; 949 950 if (!VT.is256BitVector()) { 951 continue; 952 } 953 setOperationAction(ISD::AND, VT, Promote); 954 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 955 setOperationAction(ISD::OR, VT, Promote); 956 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 957 setOperationAction(ISD::XOR, VT, Promote); 958 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 959 setOperationAction(ISD::LOAD, VT, Promote); 960 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 961 setOperationAction(ISD::SELECT, VT, Promote); 962 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 963 } 964 965 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 966#endif 967 } 968 969 // We want to custom lower some of our intrinsics. 970 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 971 972 // Add/Sub/Mul with overflow operations are custom lowered. 973 setOperationAction(ISD::SADDO, MVT::i32, Custom); 974 setOperationAction(ISD::SADDO, MVT::i64, Custom); 975 setOperationAction(ISD::UADDO, MVT::i32, Custom); 976 setOperationAction(ISD::UADDO, MVT::i64, Custom); 977 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 978 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 979 setOperationAction(ISD::USUBO, MVT::i32, Custom); 980 setOperationAction(ISD::USUBO, MVT::i64, Custom); 981 setOperationAction(ISD::SMULO, MVT::i32, Custom); 982 setOperationAction(ISD::SMULO, MVT::i64, Custom); 983 984 if (!Subtarget->is64Bit()) { 985 // These libcalls are not available in 32-bit. 986 setLibcallName(RTLIB::SHL_I128, 0); 987 setLibcallName(RTLIB::SRL_I128, 0); 988 setLibcallName(RTLIB::SRA_I128, 0); 989 } 990 991 // We have target-specific dag combine patterns for the following nodes: 992 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 993 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 994 setTargetDAGCombine(ISD::BUILD_VECTOR); 995 setTargetDAGCombine(ISD::SELECT); 996 setTargetDAGCombine(ISD::SHL); 997 setTargetDAGCombine(ISD::SRA); 998 setTargetDAGCombine(ISD::SRL); 999 setTargetDAGCombine(ISD::OR); 1000 setTargetDAGCombine(ISD::STORE); 1001 setTargetDAGCombine(ISD::MEMBARRIER); 1002 setTargetDAGCombine(ISD::ZERO_EXTEND); 1003 if (Subtarget->is64Bit()) 1004 setTargetDAGCombine(ISD::MUL); 1005 1006 computeRegisterProperties(); 1007 1008 // FIXME: These should be based on subtarget info. Plus, the values should 1009 // be smaller when we are in optimizing for size mode. 1010 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1011 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 1012 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1013 setPrefLoopAlignment(16); 1014 benefitFromCodePlacementOpt = true; 1015} 1016 1017 1018MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1019 return MVT::i8; 1020} 1021 1022 1023/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1024/// the desired ByVal argument alignment. 1025static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1026 if (MaxAlign == 16) 1027 return; 1028 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1029 if (VTy->getBitWidth() == 128) 1030 MaxAlign = 16; 1031 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1032 unsigned EltAlign = 0; 1033 getMaxByValAlign(ATy->getElementType(), EltAlign); 1034 if (EltAlign > MaxAlign) 1035 MaxAlign = EltAlign; 1036 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1037 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1038 unsigned EltAlign = 0; 1039 getMaxByValAlign(STy->getElementType(i), EltAlign); 1040 if (EltAlign > MaxAlign) 1041 MaxAlign = EltAlign; 1042 if (MaxAlign == 16) 1043 break; 1044 } 1045 } 1046 return; 1047} 1048 1049/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1050/// function arguments in the caller parameter area. For X86, aggregates 1051/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1052/// are at 4-byte boundaries. 1053unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1054 if (Subtarget->is64Bit()) { 1055 // Max of 8 and alignment of type. 1056 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1057 if (TyAlign > 8) 1058 return TyAlign; 1059 return 8; 1060 } 1061 1062 unsigned Align = 4; 1063 if (Subtarget->hasSSE1()) 1064 getMaxByValAlign(Ty, Align); 1065 return Align; 1066} 1067 1068/// getOptimalMemOpType - Returns the target specific optimal type for load 1069/// and store operations as a result of memset, memcpy, and memmove 1070/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 1071/// determining it. 1072EVT 1073X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1074 bool isSrcConst, bool isSrcStr, 1075 SelectionDAG &DAG) const { 1076 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1077 // linux. This is because the stack realignment code can't handle certain 1078 // cases like PR2962. This should be removed when PR2962 is fixed. 1079 const Function *F = DAG.getMachineFunction().getFunction(); 1080 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1081 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1082 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1083 return MVT::v4i32; 1084 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1085 return MVT::v4f32; 1086 } 1087 if (Subtarget->is64Bit() && Size >= 8) 1088 return MVT::i64; 1089 return MVT::i32; 1090} 1091 1092/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1093/// current function. The returned value is a member of the 1094/// MachineJumpTableInfo::JTEntryKind enum. 1095unsigned X86TargetLowering::getJumpTableEncoding() const { 1096 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1097 // symbol. 1098 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1099 Subtarget->isPICStyleGOT()) 1100 return MachineJumpTableInfo::EK_Custom32; 1101 1102 // Otherwise, use the normal jump table encoding heuristics. 1103 return TargetLowering::getJumpTableEncoding(); 1104} 1105 1106/// getPICBaseSymbol - Return the X86-32 PIC base. 1107MCSymbol * 1108X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1109 MCContext &Ctx) const { 1110 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1111 return Ctx.GetOrCreateTemporarySymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1112 Twine(MF->getFunctionNumber())+"$pb"); 1113} 1114 1115 1116const MCExpr * 1117X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1118 const MachineBasicBlock *MBB, 1119 unsigned uid,MCContext &Ctx) const{ 1120 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1121 Subtarget->isPICStyleGOT()); 1122 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1123 // entries. 1124 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1125 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1126} 1127 1128/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1129/// jumptable. 1130SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1131 SelectionDAG &DAG) const { 1132 if (!Subtarget->is64Bit()) 1133 // This doesn't have DebugLoc associated with it, but is not really the 1134 // same as a Register. 1135 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1136 getPointerTy()); 1137 return Table; 1138} 1139 1140/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1141/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1142/// MCExpr. 1143const MCExpr *X86TargetLowering:: 1144getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1145 MCContext &Ctx) const { 1146 // X86-64 uses RIP relative addressing based on the jump table label. 1147 if (Subtarget->isPICStyleRIPRel()) 1148 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1149 1150 // Otherwise, the reference is relative to the PIC base. 1151 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1152} 1153 1154/// getFunctionAlignment - Return the Log2 alignment of this function. 1155unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1156 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1157} 1158 1159//===----------------------------------------------------------------------===// 1160// Return Value Calling Convention Implementation 1161//===----------------------------------------------------------------------===// 1162 1163#include "X86GenCallingConv.inc" 1164 1165bool 1166X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1167 const SmallVectorImpl<EVT> &OutTys, 1168 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1169 SelectionDAG &DAG) { 1170 SmallVector<CCValAssign, 16> RVLocs; 1171 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1172 RVLocs, *DAG.getContext()); 1173 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86); 1174} 1175 1176SDValue 1177X86TargetLowering::LowerReturn(SDValue Chain, 1178 CallingConv::ID CallConv, bool isVarArg, 1179 const SmallVectorImpl<ISD::OutputArg> &Outs, 1180 DebugLoc dl, SelectionDAG &DAG) { 1181 1182 SmallVector<CCValAssign, 16> RVLocs; 1183 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1184 RVLocs, *DAG.getContext()); 1185 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1186 1187 // Add the regs to the liveout set for the function. 1188 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1189 for (unsigned i = 0; i != RVLocs.size(); ++i) 1190 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1191 MRI.addLiveOut(RVLocs[i].getLocReg()); 1192 1193 SDValue Flag; 1194 1195 SmallVector<SDValue, 6> RetOps; 1196 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1197 // Operand #1 = Bytes To Pop 1198 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16)); 1199 1200 // Copy the result values into the output registers. 1201 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1202 CCValAssign &VA = RVLocs[i]; 1203 assert(VA.isRegLoc() && "Can only return in registers!"); 1204 SDValue ValToCopy = Outs[i].Val; 1205 1206 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1207 // the RET instruction and handled by the FP Stackifier. 1208 if (VA.getLocReg() == X86::ST0 || 1209 VA.getLocReg() == X86::ST1) { 1210 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1211 // change the value to the FP stack register class. 1212 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1213 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1214 RetOps.push_back(ValToCopy); 1215 // Don't emit a copytoreg. 1216 continue; 1217 } 1218 1219 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1220 // which is returned in RAX / RDX. 1221 if (Subtarget->is64Bit()) { 1222 EVT ValVT = ValToCopy.getValueType(); 1223 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1224 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1225 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1226 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1227 } 1228 } 1229 1230 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1231 Flag = Chain.getValue(1); 1232 } 1233 1234 // The x86-64 ABI for returning structs by value requires that we copy 1235 // the sret argument into %rax for the return. We saved the argument into 1236 // a virtual register in the entry block, so now we copy the value out 1237 // and into %rax. 1238 if (Subtarget->is64Bit() && 1239 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1240 MachineFunction &MF = DAG.getMachineFunction(); 1241 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1242 unsigned Reg = FuncInfo->getSRetReturnReg(); 1243 if (!Reg) { 1244 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64)); 1245 FuncInfo->setSRetReturnReg(Reg); 1246 } 1247 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1248 1249 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1250 Flag = Chain.getValue(1); 1251 1252 // RAX now acts like a return value. 1253 MRI.addLiveOut(X86::RAX); 1254 } 1255 1256 RetOps[0] = Chain; // Update chain. 1257 1258 // Add the flag if we have it. 1259 if (Flag.getNode()) 1260 RetOps.push_back(Flag); 1261 1262 return DAG.getNode(X86ISD::RET_FLAG, dl, 1263 MVT::Other, &RetOps[0], RetOps.size()); 1264} 1265 1266/// LowerCallResult - Lower the result values of a call into the 1267/// appropriate copies out of appropriate physical registers. 1268/// 1269SDValue 1270X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1271 CallingConv::ID CallConv, bool isVarArg, 1272 const SmallVectorImpl<ISD::InputArg> &Ins, 1273 DebugLoc dl, SelectionDAG &DAG, 1274 SmallVectorImpl<SDValue> &InVals) { 1275 1276 // Assign locations to each value returned by this call. 1277 SmallVector<CCValAssign, 16> RVLocs; 1278 bool Is64Bit = Subtarget->is64Bit(); 1279 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1280 RVLocs, *DAG.getContext()); 1281 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1282 1283 // Copy all of the result registers out of their specified physreg. 1284 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1285 CCValAssign &VA = RVLocs[i]; 1286 EVT CopyVT = VA.getValVT(); 1287 1288 // If this is x86-64, and we disabled SSE, we can't return FP values 1289 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1290 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1291 llvm_report_error("SSE register return with SSE disabled"); 1292 } 1293 1294 // If this is a call to a function that returns an fp value on the floating 1295 // point stack, but where we prefer to use the value in xmm registers, copy 1296 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1297 if ((VA.getLocReg() == X86::ST0 || 1298 VA.getLocReg() == X86::ST1) && 1299 isScalarFPTypeInSSEReg(VA.getValVT())) { 1300 CopyVT = MVT::f80; 1301 } 1302 1303 SDValue Val; 1304 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1305 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1306 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1307 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1308 MVT::v2i64, InFlag).getValue(1); 1309 Val = Chain.getValue(0); 1310 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1311 Val, DAG.getConstant(0, MVT::i64)); 1312 } else { 1313 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1314 MVT::i64, InFlag).getValue(1); 1315 Val = Chain.getValue(0); 1316 } 1317 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1318 } else { 1319 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1320 CopyVT, InFlag).getValue(1); 1321 Val = Chain.getValue(0); 1322 } 1323 InFlag = Chain.getValue(2); 1324 1325 if (CopyVT != VA.getValVT()) { 1326 // Round the F80 the right size, which also moves to the appropriate xmm 1327 // register. 1328 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1329 // This truncation won't change the value. 1330 DAG.getIntPtrConstant(1)); 1331 } 1332 1333 InVals.push_back(Val); 1334 } 1335 1336 return Chain; 1337} 1338 1339 1340//===----------------------------------------------------------------------===// 1341// C & StdCall & Fast Calling Convention implementation 1342//===----------------------------------------------------------------------===// 1343// StdCall calling convention seems to be standard for many Windows' API 1344// routines and around. It differs from C calling convention just a little: 1345// callee should clean up the stack, not caller. Symbols should be also 1346// decorated in some fancy way :) It doesn't support any vector arguments. 1347// For info on fast calling convention see Fast Calling Convention (tail call) 1348// implementation LowerX86_32FastCCCallTo. 1349 1350/// CallIsStructReturn - Determines whether a call uses struct return 1351/// semantics. 1352static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1353 if (Outs.empty()) 1354 return false; 1355 1356 return Outs[0].Flags.isSRet(); 1357} 1358 1359/// ArgsAreStructReturn - Determines whether a function uses struct 1360/// return semantics. 1361static bool 1362ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1363 if (Ins.empty()) 1364 return false; 1365 1366 return Ins[0].Flags.isSRet(); 1367} 1368 1369/// IsCalleePop - Determines whether the callee is required to pop its 1370/// own arguments. Callee pop is necessary to support tail calls. 1371bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ 1372 if (IsVarArg) 1373 return false; 1374 1375 switch (CallingConv) { 1376 default: 1377 return false; 1378 case CallingConv::X86_StdCall: 1379 return !Subtarget->is64Bit(); 1380 case CallingConv::X86_FastCall: 1381 return !Subtarget->is64Bit(); 1382 case CallingConv::Fast: 1383 return GuaranteedTailCallOpt; 1384 case CallingConv::GHC: 1385 return GuaranteedTailCallOpt; 1386 } 1387} 1388 1389/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1390/// given CallingConvention value. 1391CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1392 if (Subtarget->is64Bit()) { 1393 if (CC == CallingConv::GHC) 1394 return CC_X86_64_GHC; 1395 else if (Subtarget->isTargetWin64()) 1396 return CC_X86_Win64_C; 1397 else 1398 return CC_X86_64_C; 1399 } 1400 1401 if (CC == CallingConv::X86_FastCall) 1402 return CC_X86_32_FastCall; 1403 else if (CC == CallingConv::Fast) 1404 return CC_X86_32_FastCC; 1405 else if (CC == CallingConv::GHC) 1406 return CC_X86_32_GHC; 1407 else 1408 return CC_X86_32_C; 1409} 1410 1411/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1412/// by "Src" to address "Dst" with size and alignment information specified by 1413/// the specific parameter attribute. The copy will be passed as a byval 1414/// function parameter. 1415static SDValue 1416CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1417 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1418 DebugLoc dl) { 1419 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1420 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1421 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1422} 1423 1424/// IsTailCallConvention - Return true if the calling convention is one that 1425/// supports tail call optimization. 1426static bool IsTailCallConvention(CallingConv::ID CC) { 1427 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1428} 1429 1430/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1431/// a tailcall target by changing its ABI. 1432static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1433 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1434} 1435 1436SDValue 1437X86TargetLowering::LowerMemArgument(SDValue Chain, 1438 CallingConv::ID CallConv, 1439 const SmallVectorImpl<ISD::InputArg> &Ins, 1440 DebugLoc dl, SelectionDAG &DAG, 1441 const CCValAssign &VA, 1442 MachineFrameInfo *MFI, 1443 unsigned i) { 1444 // Create the nodes corresponding to a load from this parameter slot. 1445 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1446 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1447 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1448 EVT ValVT; 1449 1450 // If value is passed by pointer we have address passed instead of the value 1451 // itself. 1452 if (VA.getLocInfo() == CCValAssign::Indirect) 1453 ValVT = VA.getLocVT(); 1454 else 1455 ValVT = VA.getValVT(); 1456 1457 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1458 // changed with more analysis. 1459 // In case of tail call optimization mark all arguments mutable. Since they 1460 // could be overwritten by lowering of arguments in case of a tail call. 1461 if (Flags.isByVal()) { 1462 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1463 VA.getLocMemOffset(), isImmutable, false); 1464 return DAG.getFrameIndex(FI, getPointerTy()); 1465 } else { 1466 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1467 VA.getLocMemOffset(), isImmutable, false); 1468 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1469 return DAG.getLoad(ValVT, dl, Chain, FIN, 1470 PseudoSourceValue::getFixedStack(FI), 0, 1471 false, false, 0); 1472 } 1473} 1474 1475SDValue 1476X86TargetLowering::LowerFormalArguments(SDValue Chain, 1477 CallingConv::ID CallConv, 1478 bool isVarArg, 1479 const SmallVectorImpl<ISD::InputArg> &Ins, 1480 DebugLoc dl, 1481 SelectionDAG &DAG, 1482 SmallVectorImpl<SDValue> &InVals) { 1483 MachineFunction &MF = DAG.getMachineFunction(); 1484 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1485 1486 const Function* Fn = MF.getFunction(); 1487 if (Fn->hasExternalLinkage() && 1488 Subtarget->isTargetCygMing() && 1489 Fn->getName() == "main") 1490 FuncInfo->setForceFramePointer(true); 1491 1492 MachineFrameInfo *MFI = MF.getFrameInfo(); 1493 bool Is64Bit = Subtarget->is64Bit(); 1494 bool IsWin64 = Subtarget->isTargetWin64(); 1495 1496 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1497 "Var args not supported with calling convention fastcc or ghc"); 1498 1499 // Assign locations to all of the incoming arguments. 1500 SmallVector<CCValAssign, 16> ArgLocs; 1501 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1502 ArgLocs, *DAG.getContext()); 1503 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1504 1505 unsigned LastVal = ~0U; 1506 SDValue ArgValue; 1507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1508 CCValAssign &VA = ArgLocs[i]; 1509 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1510 // places. 1511 assert(VA.getValNo() != LastVal && 1512 "Don't support value assigned to multiple locs yet"); 1513 LastVal = VA.getValNo(); 1514 1515 if (VA.isRegLoc()) { 1516 EVT RegVT = VA.getLocVT(); 1517 TargetRegisterClass *RC = NULL; 1518 if (RegVT == MVT::i32) 1519 RC = X86::GR32RegisterClass; 1520 else if (Is64Bit && RegVT == MVT::i64) 1521 RC = X86::GR64RegisterClass; 1522 else if (RegVT == MVT::f32) 1523 RC = X86::FR32RegisterClass; 1524 else if (RegVT == MVT::f64) 1525 RC = X86::FR64RegisterClass; 1526 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1527 RC = X86::VR128RegisterClass; 1528 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1529 RC = X86::VR64RegisterClass; 1530 else 1531 llvm_unreachable("Unknown argument type!"); 1532 1533 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1534 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1535 1536 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1537 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1538 // right size. 1539 if (VA.getLocInfo() == CCValAssign::SExt) 1540 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1541 DAG.getValueType(VA.getValVT())); 1542 else if (VA.getLocInfo() == CCValAssign::ZExt) 1543 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1544 DAG.getValueType(VA.getValVT())); 1545 else if (VA.getLocInfo() == CCValAssign::BCvt) 1546 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1547 1548 if (VA.isExtInLoc()) { 1549 // Handle MMX values passed in XMM regs. 1550 if (RegVT.isVector()) { 1551 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1552 ArgValue, DAG.getConstant(0, MVT::i64)); 1553 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1554 } else 1555 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1556 } 1557 } else { 1558 assert(VA.isMemLoc()); 1559 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1560 } 1561 1562 // If value is passed via pointer - do a load. 1563 if (VA.getLocInfo() == CCValAssign::Indirect) 1564 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1565 false, false, 0); 1566 1567 InVals.push_back(ArgValue); 1568 } 1569 1570 // The x86-64 ABI for returning structs by value requires that we copy 1571 // the sret argument into %rax for the return. Save the argument into 1572 // a virtual register so that we can access it from the return points. 1573 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1574 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1575 unsigned Reg = FuncInfo->getSRetReturnReg(); 1576 if (!Reg) { 1577 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1578 FuncInfo->setSRetReturnReg(Reg); 1579 } 1580 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1581 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1582 } 1583 1584 unsigned StackSize = CCInfo.getNextStackOffset(); 1585 // Align stack specially for tail calls. 1586 if (FuncIsMadeTailCallSafe(CallConv)) 1587 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1588 1589 // If the function takes variable number of arguments, make a frame index for 1590 // the start of the first vararg value... for expansion of llvm.va_start. 1591 if (isVarArg) { 1592 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1593 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false); 1594 } 1595 if (Is64Bit) { 1596 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1597 1598 // FIXME: We should really autogenerate these arrays 1599 static const unsigned GPR64ArgRegsWin64[] = { 1600 X86::RCX, X86::RDX, X86::R8, X86::R9 1601 }; 1602 static const unsigned XMMArgRegsWin64[] = { 1603 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1604 }; 1605 static const unsigned GPR64ArgRegs64Bit[] = { 1606 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1607 }; 1608 static const unsigned XMMArgRegs64Bit[] = { 1609 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1610 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1611 }; 1612 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1613 1614 if (IsWin64) { 1615 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1616 GPR64ArgRegs = GPR64ArgRegsWin64; 1617 XMMArgRegs = XMMArgRegsWin64; 1618 } else { 1619 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1620 GPR64ArgRegs = GPR64ArgRegs64Bit; 1621 XMMArgRegs = XMMArgRegs64Bit; 1622 } 1623 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1624 TotalNumIntRegs); 1625 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1626 TotalNumXMMRegs); 1627 1628 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1629 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1630 "SSE register cannot be used when SSE is disabled!"); 1631 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1632 "SSE register cannot be used when SSE is disabled!"); 1633 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1634 // Kernel mode asks for SSE to be disabled, so don't push them 1635 // on the stack. 1636 TotalNumXMMRegs = 0; 1637 1638 // For X86-64, if there are vararg parameters that are passed via 1639 // registers, then we must store them to their spots on the stack so they 1640 // may be loaded by deferencing the result of va_next. 1641 VarArgsGPOffset = NumIntRegs * 8; 1642 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1643 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1644 TotalNumXMMRegs * 16, 16, 1645 false); 1646 1647 // Store the integer parameter registers. 1648 SmallVector<SDValue, 8> MemOps; 1649 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1650 unsigned Offset = VarArgsGPOffset; 1651 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1652 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1653 DAG.getIntPtrConstant(Offset)); 1654 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1655 X86::GR64RegisterClass); 1656 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1657 SDValue Store = 1658 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1659 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1660 Offset, false, false, 0); 1661 MemOps.push_back(Store); 1662 Offset += 8; 1663 } 1664 1665 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1666 // Now store the XMM (fp + vector) parameter registers. 1667 SmallVector<SDValue, 11> SaveXMMOps; 1668 SaveXMMOps.push_back(Chain); 1669 1670 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1671 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1672 SaveXMMOps.push_back(ALVal); 1673 1674 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1675 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1676 1677 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1678 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1679 X86::VR128RegisterClass); 1680 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1681 SaveXMMOps.push_back(Val); 1682 } 1683 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1684 MVT::Other, 1685 &SaveXMMOps[0], SaveXMMOps.size())); 1686 } 1687 1688 if (!MemOps.empty()) 1689 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1690 &MemOps[0], MemOps.size()); 1691 } 1692 } 1693 1694 // Some CCs need callee pop. 1695 if (IsCalleePop(isVarArg, CallConv)) { 1696 BytesToPopOnReturn = StackSize; // Callee pops everything. 1697 } else { 1698 BytesToPopOnReturn = 0; // Callee pops nothing. 1699 // If this is an sret function, the return should pop the hidden pointer. 1700 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1701 BytesToPopOnReturn = 4; 1702 } 1703 1704 if (!Is64Bit) { 1705 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1706 if (CallConv == CallingConv::X86_FastCall) 1707 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1708 } 1709 1710 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1711 1712 return Chain; 1713} 1714 1715SDValue 1716X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1717 SDValue StackPtr, SDValue Arg, 1718 DebugLoc dl, SelectionDAG &DAG, 1719 const CCValAssign &VA, 1720 ISD::ArgFlagsTy Flags) { 1721 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1722 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1723 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1724 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1725 if (Flags.isByVal()) { 1726 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1727 } 1728 return DAG.getStore(Chain, dl, Arg, PtrOff, 1729 PseudoSourceValue::getStack(), LocMemOffset, 1730 false, false, 0); 1731} 1732 1733/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1734/// optimization is performed and it is required. 1735SDValue 1736X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1737 SDValue &OutRetAddr, SDValue Chain, 1738 bool IsTailCall, bool Is64Bit, 1739 int FPDiff, DebugLoc dl) { 1740 // Adjust the Return address stack slot. 1741 EVT VT = getPointerTy(); 1742 OutRetAddr = getReturnAddressFrameIndex(DAG); 1743 1744 // Load the "old" Return address. 1745 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1746 return SDValue(OutRetAddr.getNode(), 1); 1747} 1748 1749/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1750/// optimization is performed and it is required (FPDiff!=0). 1751static SDValue 1752EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1753 SDValue Chain, SDValue RetAddrFrIdx, 1754 bool Is64Bit, int FPDiff, DebugLoc dl) { 1755 // Store the return address to the appropriate stack slot. 1756 if (!FPDiff) return Chain; 1757 // Calculate the new stack slot for the return address. 1758 int SlotSize = Is64Bit ? 8 : 4; 1759 int NewReturnAddrFI = 1760 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false); 1761 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1762 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1763 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1764 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1765 false, false, 0); 1766 return Chain; 1767} 1768 1769SDValue 1770X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1771 CallingConv::ID CallConv, bool isVarArg, 1772 bool &isTailCall, 1773 const SmallVectorImpl<ISD::OutputArg> &Outs, 1774 const SmallVectorImpl<ISD::InputArg> &Ins, 1775 DebugLoc dl, SelectionDAG &DAG, 1776 SmallVectorImpl<SDValue> &InVals) { 1777 MachineFunction &MF = DAG.getMachineFunction(); 1778 bool Is64Bit = Subtarget->is64Bit(); 1779 bool IsStructRet = CallIsStructReturn(Outs); 1780 bool IsSibcall = false; 1781 1782 if (isTailCall) { 1783 // Check if it's really possible to do a tail call. 1784 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1785 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1786 Outs, Ins, DAG); 1787 1788 // Sibcalls are automatically detected tailcalls which do not require 1789 // ABI changes. 1790 if (!GuaranteedTailCallOpt && isTailCall) 1791 IsSibcall = true; 1792 1793 if (isTailCall) 1794 ++NumTailCalls; 1795 } 1796 1797 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1798 "Var args not supported with calling convention fastcc or ghc"); 1799 1800 // Analyze operands of the call, assigning locations to each operand. 1801 SmallVector<CCValAssign, 16> ArgLocs; 1802 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1803 ArgLocs, *DAG.getContext()); 1804 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1805 1806 // Get a count of how many bytes are to be pushed on the stack. 1807 unsigned NumBytes = CCInfo.getNextStackOffset(); 1808 if (IsSibcall) 1809 // This is a sibcall. The memory operands are available in caller's 1810 // own caller's stack. 1811 NumBytes = 0; 1812 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1813 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1814 1815 int FPDiff = 0; 1816 if (isTailCall && !IsSibcall) { 1817 // Lower arguments at fp - stackoffset + fpdiff. 1818 unsigned NumBytesCallerPushed = 1819 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1820 FPDiff = NumBytesCallerPushed - NumBytes; 1821 1822 // Set the delta of movement of the returnaddr stackslot. 1823 // But only set if delta is greater than previous delta. 1824 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1825 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1826 } 1827 1828 if (!IsSibcall) 1829 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1830 1831 SDValue RetAddrFrIdx; 1832 // Load return adress for tail calls. 1833 if (isTailCall && FPDiff) 1834 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1835 Is64Bit, FPDiff, dl); 1836 1837 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1838 SmallVector<SDValue, 8> MemOpChains; 1839 SDValue StackPtr; 1840 1841 // Walk the register/memloc assignments, inserting copies/loads. In the case 1842 // of tail call optimization arguments are handle later. 1843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1844 CCValAssign &VA = ArgLocs[i]; 1845 EVT RegVT = VA.getLocVT(); 1846 SDValue Arg = Outs[i].Val; 1847 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1848 bool isByVal = Flags.isByVal(); 1849 1850 // Promote the value if needed. 1851 switch (VA.getLocInfo()) { 1852 default: llvm_unreachable("Unknown loc info!"); 1853 case CCValAssign::Full: break; 1854 case CCValAssign::SExt: 1855 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1856 break; 1857 case CCValAssign::ZExt: 1858 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1859 break; 1860 case CCValAssign::AExt: 1861 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1862 // Special case: passing MMX values in XMM registers. 1863 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1864 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1865 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1866 } else 1867 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1868 break; 1869 case CCValAssign::BCvt: 1870 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1871 break; 1872 case CCValAssign::Indirect: { 1873 // Store the argument. 1874 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1875 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1876 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1877 PseudoSourceValue::getFixedStack(FI), 0, 1878 false, false, 0); 1879 Arg = SpillSlot; 1880 break; 1881 } 1882 } 1883 1884 if (VA.isRegLoc()) { 1885 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1886 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1887 assert(VA.isMemLoc()); 1888 if (StackPtr.getNode() == 0) 1889 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1890 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1891 dl, DAG, VA, Flags)); 1892 } 1893 } 1894 1895 if (!MemOpChains.empty()) 1896 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1897 &MemOpChains[0], MemOpChains.size()); 1898 1899 // Build a sequence of copy-to-reg nodes chained together with token chain 1900 // and flag operands which copy the outgoing args into registers. 1901 SDValue InFlag; 1902 // Tail call byval lowering might overwrite argument registers so in case of 1903 // tail call optimization the copies to registers are lowered later. 1904 if (!isTailCall) 1905 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1906 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1907 RegsToPass[i].second, InFlag); 1908 InFlag = Chain.getValue(1); 1909 } 1910 1911 if (Subtarget->isPICStyleGOT()) { 1912 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1913 // GOT pointer. 1914 if (!isTailCall) { 1915 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1916 DAG.getNode(X86ISD::GlobalBaseReg, 1917 DebugLoc::getUnknownLoc(), 1918 getPointerTy()), 1919 InFlag); 1920 InFlag = Chain.getValue(1); 1921 } else { 1922 // If we are tail calling and generating PIC/GOT style code load the 1923 // address of the callee into ECX. The value in ecx is used as target of 1924 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1925 // for tail calls on PIC/GOT architectures. Normally we would just put the 1926 // address of GOT into ebx and then call target@PLT. But for tail calls 1927 // ebx would be restored (since ebx is callee saved) before jumping to the 1928 // target@PLT. 1929 1930 // Note: The actual moving to ECX is done further down. 1931 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1932 if (G && !G->getGlobal()->hasHiddenVisibility() && 1933 !G->getGlobal()->hasProtectedVisibility()) 1934 Callee = LowerGlobalAddress(Callee, DAG); 1935 else if (isa<ExternalSymbolSDNode>(Callee)) 1936 Callee = LowerExternalSymbol(Callee, DAG); 1937 } 1938 } 1939 1940 if (Is64Bit && isVarArg) { 1941 // From AMD64 ABI document: 1942 // For calls that may call functions that use varargs or stdargs 1943 // (prototype-less calls or calls to functions containing ellipsis (...) in 1944 // the declaration) %al is used as hidden argument to specify the number 1945 // of SSE registers used. The contents of %al do not need to match exactly 1946 // the number of registers, but must be an ubound on the number of SSE 1947 // registers used and is in the range 0 - 8 inclusive. 1948 1949 // FIXME: Verify this on Win64 1950 // Count the number of XMM registers allocated. 1951 static const unsigned XMMArgRegs[] = { 1952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1954 }; 1955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1956 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1957 && "SSE registers cannot be used when SSE is disabled"); 1958 1959 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1960 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1961 InFlag = Chain.getValue(1); 1962 } 1963 1964 1965 // For tail calls lower the arguments to the 'real' stack slot. 1966 if (isTailCall) { 1967 // Force all the incoming stack arguments to be loaded from the stack 1968 // before any new outgoing arguments are stored to the stack, because the 1969 // outgoing stack slots may alias the incoming argument stack slots, and 1970 // the alias isn't otherwise explicit. This is slightly more conservative 1971 // than necessary, because it means that each store effectively depends 1972 // on every argument instead of just those arguments it would clobber. 1973 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1974 1975 SmallVector<SDValue, 8> MemOpChains2; 1976 SDValue FIN; 1977 int FI = 0; 1978 // Do not flag preceeding copytoreg stuff together with the following stuff. 1979 InFlag = SDValue(); 1980 if (GuaranteedTailCallOpt) { 1981 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1982 CCValAssign &VA = ArgLocs[i]; 1983 if (VA.isRegLoc()) 1984 continue; 1985 assert(VA.isMemLoc()); 1986 SDValue Arg = Outs[i].Val; 1987 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1988 // Create frame index. 1989 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1990 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1991 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false); 1992 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1993 1994 if (Flags.isByVal()) { 1995 // Copy relative to framepointer. 1996 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1997 if (StackPtr.getNode() == 0) 1998 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1999 getPointerTy()); 2000 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2001 2002 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2003 ArgChain, 2004 Flags, DAG, dl)); 2005 } else { 2006 // Store relative to framepointer. 2007 MemOpChains2.push_back( 2008 DAG.getStore(ArgChain, dl, Arg, FIN, 2009 PseudoSourceValue::getFixedStack(FI), 0, 2010 false, false, 0)); 2011 } 2012 } 2013 } 2014 2015 if (!MemOpChains2.empty()) 2016 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2017 &MemOpChains2[0], MemOpChains2.size()); 2018 2019 // Copy arguments to their registers. 2020 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2021 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2022 RegsToPass[i].second, InFlag); 2023 InFlag = Chain.getValue(1); 2024 } 2025 InFlag =SDValue(); 2026 2027 // Store the return address to the appropriate stack slot. 2028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2029 FPDiff, dl); 2030 } 2031 2032 bool WasGlobalOrExternal = false; 2033 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2034 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2035 // In the 64-bit large code model, we have to make all calls 2036 // through a register, since the call instruction's 32-bit 2037 // pc-relative offset may not be large enough to hold the whole 2038 // address. 2039 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2040 WasGlobalOrExternal = true; 2041 // If the callee is a GlobalAddress node (quite common, every direct call 2042 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2043 // it. 2044 2045 // We should use extra load for direct calls to dllimported functions in 2046 // non-JIT mode. 2047 GlobalValue *GV = G->getGlobal(); 2048 if (!GV->hasDLLImportLinkage()) { 2049 unsigned char OpFlags = 0; 2050 2051 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2052 // external symbols most go through the PLT in PIC mode. If the symbol 2053 // has hidden or protected visibility, or if it is static or local, then 2054 // we don't need to use the PLT - we can directly call it. 2055 if (Subtarget->isTargetELF() && 2056 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2057 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2058 OpFlags = X86II::MO_PLT; 2059 } else if (Subtarget->isPICStyleStubAny() && 2060 (GV->isDeclaration() || GV->isWeakForLinker()) && 2061 Subtarget->getDarwinVers() < 9) { 2062 // PC-relative references to external symbols should go through $stub, 2063 // unless we're building with the leopard linker or later, which 2064 // automatically synthesizes these stubs. 2065 OpFlags = X86II::MO_DARWIN_STUB; 2066 } 2067 2068 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 2069 G->getOffset(), OpFlags); 2070 } 2071 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2072 WasGlobalOrExternal = true; 2073 unsigned char OpFlags = 0; 2074 2075 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2076 // symbols should go through the PLT. 2077 if (Subtarget->isTargetELF() && 2078 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2079 OpFlags = X86II::MO_PLT; 2080 } else if (Subtarget->isPICStyleStubAny() && 2081 Subtarget->getDarwinVers() < 9) { 2082 // PC-relative references to external symbols should go through $stub, 2083 // unless we're building with the leopard linker or later, which 2084 // automatically synthesizes these stubs. 2085 OpFlags = X86II::MO_DARWIN_STUB; 2086 } 2087 2088 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2089 OpFlags); 2090 } 2091 2092 // Returns a chain & a flag for retval copy to use. 2093 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2094 SmallVector<SDValue, 8> Ops; 2095 2096 if (!IsSibcall && isTailCall) { 2097 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2098 DAG.getIntPtrConstant(0, true), InFlag); 2099 InFlag = Chain.getValue(1); 2100 } 2101 2102 Ops.push_back(Chain); 2103 Ops.push_back(Callee); 2104 2105 if (isTailCall) 2106 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2107 2108 // Add argument registers to the end of the list so that they are known live 2109 // into the call. 2110 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2111 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2112 RegsToPass[i].second.getValueType())); 2113 2114 // Add an implicit use GOT pointer in EBX. 2115 if (!isTailCall && Subtarget->isPICStyleGOT()) 2116 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2117 2118 // Add an implicit use of AL for x86 vararg functions. 2119 if (Is64Bit && isVarArg) 2120 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2121 2122 if (InFlag.getNode()) 2123 Ops.push_back(InFlag); 2124 2125 if (isTailCall) { 2126 // If this is the first return lowered for this function, add the regs 2127 // to the liveout set for the function. 2128 if (MF.getRegInfo().liveout_empty()) { 2129 SmallVector<CCValAssign, 16> RVLocs; 2130 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2131 *DAG.getContext()); 2132 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2133 for (unsigned i = 0; i != RVLocs.size(); ++i) 2134 if (RVLocs[i].isRegLoc()) 2135 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2136 } 2137 return DAG.getNode(X86ISD::TC_RETURN, dl, 2138 NodeTys, &Ops[0], Ops.size()); 2139 } 2140 2141 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2142 InFlag = Chain.getValue(1); 2143 2144 // Create the CALLSEQ_END node. 2145 unsigned NumBytesForCalleeToPush; 2146 if (IsCalleePop(isVarArg, CallConv)) 2147 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2148 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2149 // If this is a call to a struct-return function, the callee 2150 // pops the hidden struct pointer, so we have to push it back. 2151 // This is common for Darwin/X86, Linux & Mingw32 targets. 2152 NumBytesForCalleeToPush = 4; 2153 else 2154 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2155 2156 // Returns a flag for retval copy to use. 2157 if (!IsSibcall) { 2158 Chain = DAG.getCALLSEQ_END(Chain, 2159 DAG.getIntPtrConstant(NumBytes, true), 2160 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2161 true), 2162 InFlag); 2163 InFlag = Chain.getValue(1); 2164 } 2165 2166 // Handle result values, copying them out of physregs into vregs that we 2167 // return. 2168 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2169 Ins, dl, DAG, InVals); 2170} 2171 2172 2173//===----------------------------------------------------------------------===// 2174// Fast Calling Convention (tail call) implementation 2175//===----------------------------------------------------------------------===// 2176 2177// Like std call, callee cleans arguments, convention except that ECX is 2178// reserved for storing the tail called function address. Only 2 registers are 2179// free for argument passing (inreg). Tail call optimization is performed 2180// provided: 2181// * tailcallopt is enabled 2182// * caller/callee are fastcc 2183// On X86_64 architecture with GOT-style position independent code only local 2184// (within module) calls are supported at the moment. 2185// To keep the stack aligned according to platform abi the function 2186// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2187// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2188// If a tail called function callee has more arguments than the caller the 2189// caller needs to make sure that there is room to move the RETADDR to. This is 2190// achieved by reserving an area the size of the argument delta right after the 2191// original REtADDR, but before the saved framepointer or the spilled registers 2192// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2193// stack layout: 2194// arg1 2195// arg2 2196// RETADDR 2197// [ new RETADDR 2198// move area ] 2199// (possible EBP) 2200// ESI 2201// EDI 2202// local1 .. 2203 2204/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2205/// for a 16 byte align requirement. 2206unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2207 SelectionDAG& DAG) { 2208 MachineFunction &MF = DAG.getMachineFunction(); 2209 const TargetMachine &TM = MF.getTarget(); 2210 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2211 unsigned StackAlignment = TFI.getStackAlignment(); 2212 uint64_t AlignMask = StackAlignment - 1; 2213 int64_t Offset = StackSize; 2214 uint64_t SlotSize = TD->getPointerSize(); 2215 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2216 // Number smaller than 12 so just add the difference. 2217 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2218 } else { 2219 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2220 Offset = ((~AlignMask) & Offset) + StackAlignment + 2221 (StackAlignment-SlotSize); 2222 } 2223 return Offset; 2224} 2225 2226/// MatchingStackOffset - Return true if the given stack call argument is 2227/// already available in the same position (relatively) of the caller's 2228/// incoming argument stack. 2229static 2230bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2231 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2232 const X86InstrInfo *TII) { 2233 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2234 int FI = INT_MAX; 2235 if (Arg.getOpcode() == ISD::CopyFromReg) { 2236 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2237 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2238 return false; 2239 MachineInstr *Def = MRI->getVRegDef(VR); 2240 if (!Def) 2241 return false; 2242 if (!Flags.isByVal()) { 2243 if (!TII->isLoadFromStackSlot(Def, FI)) 2244 return false; 2245 } else { 2246 unsigned Opcode = Def->getOpcode(); 2247 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2248 Def->getOperand(1).isFI()) { 2249 FI = Def->getOperand(1).getIndex(); 2250 Bytes = Flags.getByValSize(); 2251 } else 2252 return false; 2253 } 2254 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2255 if (Flags.isByVal()) 2256 // ByVal argument is passed in as a pointer but it's now being 2257 // dereferenced. e.g. 2258 // define @foo(%struct.X* %A) { 2259 // tail call @bar(%struct.X* byval %A) 2260 // } 2261 return false; 2262 SDValue Ptr = Ld->getBasePtr(); 2263 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2264 if (!FINode) 2265 return false; 2266 FI = FINode->getIndex(); 2267 } else 2268 return false; 2269 2270 assert(FI != INT_MAX); 2271 if (!MFI->isFixedObjectIndex(FI)) 2272 return false; 2273 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2274} 2275 2276/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2277/// for tail call optimization. Targets which want to do tail call 2278/// optimization should implement this function. 2279bool 2280X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2281 CallingConv::ID CalleeCC, 2282 bool isVarArg, 2283 bool isCalleeStructRet, 2284 bool isCallerStructRet, 2285 const SmallVectorImpl<ISD::OutputArg> &Outs, 2286 const SmallVectorImpl<ISD::InputArg> &Ins, 2287 SelectionDAG& DAG) const { 2288 if (!IsTailCallConvention(CalleeCC) && 2289 CalleeCC != CallingConv::C) 2290 return false; 2291 2292 // If -tailcallopt is specified, make fastcc functions tail-callable. 2293 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2294 if (GuaranteedTailCallOpt) { 2295 if (IsTailCallConvention(CalleeCC) && 2296 CallerF->getCallingConv() == CalleeCC) 2297 return true; 2298 return false; 2299 } 2300 2301 // Look for obvious safe cases to perform tail call optimization that does not 2302 // requite ABI changes. This is what gcc calls sibcall. 2303 2304 // Do not sibcall optimize vararg calls for now. 2305 if (isVarArg) 2306 return false; 2307 2308 // Also avoid sibcall optimization if either caller or callee uses struct 2309 // return semantics. 2310 if (isCalleeStructRet || isCallerStructRet) 2311 return false; 2312 2313 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2314 // Therefore if it's not used by the call it is not safe to optimize this into 2315 // a sibcall. 2316 bool Unused = false; 2317 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2318 if (!Ins[i].Used) { 2319 Unused = true; 2320 break; 2321 } 2322 } 2323 if (Unused) { 2324 SmallVector<CCValAssign, 16> RVLocs; 2325 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2326 RVLocs, *DAG.getContext()); 2327 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2328 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2329 CCValAssign &VA = RVLocs[i]; 2330 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2331 return false; 2332 } 2333 } 2334 2335 // If the callee takes no arguments then go on to check the results of the 2336 // call. 2337 if (!Outs.empty()) { 2338 // Check if stack adjustment is needed. For now, do not do this if any 2339 // argument is passed on the stack. 2340 SmallVector<CCValAssign, 16> ArgLocs; 2341 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2342 ArgLocs, *DAG.getContext()); 2343 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2344 if (CCInfo.getNextStackOffset()) { 2345 MachineFunction &MF = DAG.getMachineFunction(); 2346 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2347 return false; 2348 if (Subtarget->isTargetWin64()) 2349 // Win64 ABI has additional complications. 2350 return false; 2351 2352 // Check if the arguments are already laid out in the right way as 2353 // the caller's fixed stack objects. 2354 MachineFrameInfo *MFI = MF.getFrameInfo(); 2355 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2356 const X86InstrInfo *TII = 2357 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2358 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2359 CCValAssign &VA = ArgLocs[i]; 2360 EVT RegVT = VA.getLocVT(); 2361 SDValue Arg = Outs[i].Val; 2362 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2363 if (VA.getLocInfo() == CCValAssign::Indirect) 2364 return false; 2365 if (!VA.isRegLoc()) { 2366 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2367 MFI, MRI, TII)) 2368 return false; 2369 } 2370 } 2371 } 2372 } 2373 2374 return true; 2375} 2376 2377FastISel * 2378X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, 2379 DwarfWriter *dw, 2380 DenseMap<const Value *, unsigned> &vm, 2381 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm, 2382 DenseMap<const AllocaInst *, int> &am 2383#ifndef NDEBUG 2384 , SmallSet<Instruction*, 8> &cil 2385#endif 2386 ) { 2387 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2388#ifndef NDEBUG 2389 , cil 2390#endif 2391 ); 2392} 2393 2394 2395//===----------------------------------------------------------------------===// 2396// Other Lowering Hooks 2397//===----------------------------------------------------------------------===// 2398 2399 2400SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2401 MachineFunction &MF = DAG.getMachineFunction(); 2402 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2403 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2404 2405 if (ReturnAddrIndex == 0) { 2406 // Set up a frame object for the return address. 2407 uint64_t SlotSize = TD->getPointerSize(); 2408 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2409 false, false); 2410 FuncInfo->setRAIndex(ReturnAddrIndex); 2411 } 2412 2413 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2414} 2415 2416 2417bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2418 bool hasSymbolicDisplacement) { 2419 // Offset should fit into 32 bit immediate field. 2420 if (!isInt32(Offset)) 2421 return false; 2422 2423 // If we don't have a symbolic displacement - we don't have any extra 2424 // restrictions. 2425 if (!hasSymbolicDisplacement) 2426 return true; 2427 2428 // FIXME: Some tweaks might be needed for medium code model. 2429 if (M != CodeModel::Small && M != CodeModel::Kernel) 2430 return false; 2431 2432 // For small code model we assume that latest object is 16MB before end of 31 2433 // bits boundary. We may also accept pretty large negative constants knowing 2434 // that all objects are in the positive half of address space. 2435 if (M == CodeModel::Small && Offset < 16*1024*1024) 2436 return true; 2437 2438 // For kernel code model we know that all object resist in the negative half 2439 // of 32bits address space. We may not accept negative offsets, since they may 2440 // be just off and we may accept pretty large positive ones. 2441 if (M == CodeModel::Kernel && Offset > 0) 2442 return true; 2443 2444 return false; 2445} 2446 2447/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2448/// specific condition code, returning the condition code and the LHS/RHS of the 2449/// comparison to make. 2450static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2451 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2452 if (!isFP) { 2453 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2454 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2455 // X > -1 -> X == 0, jump !sign. 2456 RHS = DAG.getConstant(0, RHS.getValueType()); 2457 return X86::COND_NS; 2458 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2459 // X < 0 -> X == 0, jump on sign. 2460 return X86::COND_S; 2461 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2462 // X < 1 -> X <= 0 2463 RHS = DAG.getConstant(0, RHS.getValueType()); 2464 return X86::COND_LE; 2465 } 2466 } 2467 2468 switch (SetCCOpcode) { 2469 default: llvm_unreachable("Invalid integer condition!"); 2470 case ISD::SETEQ: return X86::COND_E; 2471 case ISD::SETGT: return X86::COND_G; 2472 case ISD::SETGE: return X86::COND_GE; 2473 case ISD::SETLT: return X86::COND_L; 2474 case ISD::SETLE: return X86::COND_LE; 2475 case ISD::SETNE: return X86::COND_NE; 2476 case ISD::SETULT: return X86::COND_B; 2477 case ISD::SETUGT: return X86::COND_A; 2478 case ISD::SETULE: return X86::COND_BE; 2479 case ISD::SETUGE: return X86::COND_AE; 2480 } 2481 } 2482 2483 // First determine if it is required or is profitable to flip the operands. 2484 2485 // If LHS is a foldable load, but RHS is not, flip the condition. 2486 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2487 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2488 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2489 std::swap(LHS, RHS); 2490 } 2491 2492 switch (SetCCOpcode) { 2493 default: break; 2494 case ISD::SETOLT: 2495 case ISD::SETOLE: 2496 case ISD::SETUGT: 2497 case ISD::SETUGE: 2498 std::swap(LHS, RHS); 2499 break; 2500 } 2501 2502 // On a floating point condition, the flags are set as follows: 2503 // ZF PF CF op 2504 // 0 | 0 | 0 | X > Y 2505 // 0 | 0 | 1 | X < Y 2506 // 1 | 0 | 0 | X == Y 2507 // 1 | 1 | 1 | unordered 2508 switch (SetCCOpcode) { 2509 default: llvm_unreachable("Condcode should be pre-legalized away"); 2510 case ISD::SETUEQ: 2511 case ISD::SETEQ: return X86::COND_E; 2512 case ISD::SETOLT: // flipped 2513 case ISD::SETOGT: 2514 case ISD::SETGT: return X86::COND_A; 2515 case ISD::SETOLE: // flipped 2516 case ISD::SETOGE: 2517 case ISD::SETGE: return X86::COND_AE; 2518 case ISD::SETUGT: // flipped 2519 case ISD::SETULT: 2520 case ISD::SETLT: return X86::COND_B; 2521 case ISD::SETUGE: // flipped 2522 case ISD::SETULE: 2523 case ISD::SETLE: return X86::COND_BE; 2524 case ISD::SETONE: 2525 case ISD::SETNE: return X86::COND_NE; 2526 case ISD::SETUO: return X86::COND_P; 2527 case ISD::SETO: return X86::COND_NP; 2528 case ISD::SETOEQ: 2529 case ISD::SETUNE: return X86::COND_INVALID; 2530 } 2531} 2532 2533/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2534/// code. Current x86 isa includes the following FP cmov instructions: 2535/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2536static bool hasFPCMov(unsigned X86CC) { 2537 switch (X86CC) { 2538 default: 2539 return false; 2540 case X86::COND_B: 2541 case X86::COND_BE: 2542 case X86::COND_E: 2543 case X86::COND_P: 2544 case X86::COND_A: 2545 case X86::COND_AE: 2546 case X86::COND_NE: 2547 case X86::COND_NP: 2548 return true; 2549 } 2550} 2551 2552/// isFPImmLegal - Returns true if the target can instruction select the 2553/// specified FP immediate natively. If false, the legalizer will 2554/// materialize the FP immediate as a load from a constant pool. 2555bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2556 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2557 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2558 return true; 2559 } 2560 return false; 2561} 2562 2563/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2564/// the specified range (L, H]. 2565static bool isUndefOrInRange(int Val, int Low, int Hi) { 2566 return (Val < 0) || (Val >= Low && Val < Hi); 2567} 2568 2569/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2570/// specified value. 2571static bool isUndefOrEqual(int Val, int CmpVal) { 2572 if (Val < 0 || Val == CmpVal) 2573 return true; 2574 return false; 2575} 2576 2577/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2578/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2579/// the second operand. 2580static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2581 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2582 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2583 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2584 return (Mask[0] < 2 && Mask[1] < 2); 2585 return false; 2586} 2587 2588bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2589 SmallVector<int, 8> M; 2590 N->getMask(M); 2591 return ::isPSHUFDMask(M, N->getValueType(0)); 2592} 2593 2594/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2595/// is suitable for input to PSHUFHW. 2596static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2597 if (VT != MVT::v8i16) 2598 return false; 2599 2600 // Lower quadword copied in order or undef. 2601 for (int i = 0; i != 4; ++i) 2602 if (Mask[i] >= 0 && Mask[i] != i) 2603 return false; 2604 2605 // Upper quadword shuffled. 2606 for (int i = 4; i != 8; ++i) 2607 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2608 return false; 2609 2610 return true; 2611} 2612 2613bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2614 SmallVector<int, 8> M; 2615 N->getMask(M); 2616 return ::isPSHUFHWMask(M, N->getValueType(0)); 2617} 2618 2619/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2620/// is suitable for input to PSHUFLW. 2621static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2622 if (VT != MVT::v8i16) 2623 return false; 2624 2625 // Upper quadword copied in order. 2626 for (int i = 4; i != 8; ++i) 2627 if (Mask[i] >= 0 && Mask[i] != i) 2628 return false; 2629 2630 // Lower quadword shuffled. 2631 for (int i = 0; i != 4; ++i) 2632 if (Mask[i] >= 4) 2633 return false; 2634 2635 return true; 2636} 2637 2638bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2639 SmallVector<int, 8> M; 2640 N->getMask(M); 2641 return ::isPSHUFLWMask(M, N->getValueType(0)); 2642} 2643 2644/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2645/// is suitable for input to PALIGNR. 2646static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2647 bool hasSSSE3) { 2648 int i, e = VT.getVectorNumElements(); 2649 2650 // Do not handle v2i64 / v2f64 shuffles with palignr. 2651 if (e < 4 || !hasSSSE3) 2652 return false; 2653 2654 for (i = 0; i != e; ++i) 2655 if (Mask[i] >= 0) 2656 break; 2657 2658 // All undef, not a palignr. 2659 if (i == e) 2660 return false; 2661 2662 // Determine if it's ok to perform a palignr with only the LHS, since we 2663 // don't have access to the actual shuffle elements to see if RHS is undef. 2664 bool Unary = Mask[i] < (int)e; 2665 bool NeedsUnary = false; 2666 2667 int s = Mask[i] - i; 2668 2669 // Check the rest of the elements to see if they are consecutive. 2670 for (++i; i != e; ++i) { 2671 int m = Mask[i]; 2672 if (m < 0) 2673 continue; 2674 2675 Unary = Unary && (m < (int)e); 2676 NeedsUnary = NeedsUnary || (m < s); 2677 2678 if (NeedsUnary && !Unary) 2679 return false; 2680 if (Unary && m != ((s+i) & (e-1))) 2681 return false; 2682 if (!Unary && m != (s+i)) 2683 return false; 2684 } 2685 return true; 2686} 2687 2688bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2689 SmallVector<int, 8> M; 2690 N->getMask(M); 2691 return ::isPALIGNRMask(M, N->getValueType(0), true); 2692} 2693 2694/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2695/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2696static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2697 int NumElems = VT.getVectorNumElements(); 2698 if (NumElems != 2 && NumElems != 4) 2699 return false; 2700 2701 int Half = NumElems / 2; 2702 for (int i = 0; i < Half; ++i) 2703 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2704 return false; 2705 for (int i = Half; i < NumElems; ++i) 2706 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2707 return false; 2708 2709 return true; 2710} 2711 2712bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2713 SmallVector<int, 8> M; 2714 N->getMask(M); 2715 return ::isSHUFPMask(M, N->getValueType(0)); 2716} 2717 2718/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2719/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2720/// half elements to come from vector 1 (which would equal the dest.) and 2721/// the upper half to come from vector 2. 2722static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2723 int NumElems = VT.getVectorNumElements(); 2724 2725 if (NumElems != 2 && NumElems != 4) 2726 return false; 2727 2728 int Half = NumElems / 2; 2729 for (int i = 0; i < Half; ++i) 2730 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2731 return false; 2732 for (int i = Half; i < NumElems; ++i) 2733 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2734 return false; 2735 return true; 2736} 2737 2738static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2739 SmallVector<int, 8> M; 2740 N->getMask(M); 2741 return isCommutedSHUFPMask(M, N->getValueType(0)); 2742} 2743 2744/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2745/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2746bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2747 if (N->getValueType(0).getVectorNumElements() != 4) 2748 return false; 2749 2750 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2751 return isUndefOrEqual(N->getMaskElt(0), 6) && 2752 isUndefOrEqual(N->getMaskElt(1), 7) && 2753 isUndefOrEqual(N->getMaskElt(2), 2) && 2754 isUndefOrEqual(N->getMaskElt(3), 3); 2755} 2756 2757/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2758/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2759/// <2, 3, 2, 3> 2760bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2761 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2762 2763 if (NumElems != 4) 2764 return false; 2765 2766 return isUndefOrEqual(N->getMaskElt(0), 2) && 2767 isUndefOrEqual(N->getMaskElt(1), 3) && 2768 isUndefOrEqual(N->getMaskElt(2), 2) && 2769 isUndefOrEqual(N->getMaskElt(3), 3); 2770} 2771 2772/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2773/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2774bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2775 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2776 2777 if (NumElems != 2 && NumElems != 4) 2778 return false; 2779 2780 for (unsigned i = 0; i < NumElems/2; ++i) 2781 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2782 return false; 2783 2784 for (unsigned i = NumElems/2; i < NumElems; ++i) 2785 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2786 return false; 2787 2788 return true; 2789} 2790 2791/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 2792/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 2793bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 2794 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2795 2796 if (NumElems != 2 && NumElems != 4) 2797 return false; 2798 2799 for (unsigned i = 0; i < NumElems/2; ++i) 2800 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2801 return false; 2802 2803 for (unsigned i = 0; i < NumElems/2; ++i) 2804 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2805 return false; 2806 2807 return true; 2808} 2809 2810/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2811/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2812static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2813 bool V2IsSplat = false) { 2814 int NumElts = VT.getVectorNumElements(); 2815 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2816 return false; 2817 2818 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2819 int BitI = Mask[i]; 2820 int BitI1 = Mask[i+1]; 2821 if (!isUndefOrEqual(BitI, j)) 2822 return false; 2823 if (V2IsSplat) { 2824 if (!isUndefOrEqual(BitI1, NumElts)) 2825 return false; 2826 } else { 2827 if (!isUndefOrEqual(BitI1, j + NumElts)) 2828 return false; 2829 } 2830 } 2831 return true; 2832} 2833 2834bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2835 SmallVector<int, 8> M; 2836 N->getMask(M); 2837 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2838} 2839 2840/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2841/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2842static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2843 bool V2IsSplat = false) { 2844 int NumElts = VT.getVectorNumElements(); 2845 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2846 return false; 2847 2848 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2849 int BitI = Mask[i]; 2850 int BitI1 = Mask[i+1]; 2851 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2852 return false; 2853 if (V2IsSplat) { 2854 if (isUndefOrEqual(BitI1, NumElts)) 2855 return false; 2856 } else { 2857 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2858 return false; 2859 } 2860 } 2861 return true; 2862} 2863 2864bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2865 SmallVector<int, 8> M; 2866 N->getMask(M); 2867 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2868} 2869 2870/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2871/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2872/// <0, 0, 1, 1> 2873static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2874 int NumElems = VT.getVectorNumElements(); 2875 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2876 return false; 2877 2878 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2879 int BitI = Mask[i]; 2880 int BitI1 = Mask[i+1]; 2881 if (!isUndefOrEqual(BitI, j)) 2882 return false; 2883 if (!isUndefOrEqual(BitI1, j)) 2884 return false; 2885 } 2886 return true; 2887} 2888 2889bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2890 SmallVector<int, 8> M; 2891 N->getMask(M); 2892 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2893} 2894 2895/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2896/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2897/// <2, 2, 3, 3> 2898static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2899 int NumElems = VT.getVectorNumElements(); 2900 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2901 return false; 2902 2903 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2904 int BitI = Mask[i]; 2905 int BitI1 = Mask[i+1]; 2906 if (!isUndefOrEqual(BitI, j)) 2907 return false; 2908 if (!isUndefOrEqual(BitI1, j)) 2909 return false; 2910 } 2911 return true; 2912} 2913 2914bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2915 SmallVector<int, 8> M; 2916 N->getMask(M); 2917 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2918} 2919 2920/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2921/// specifies a shuffle of elements that is suitable for input to MOVSS, 2922/// MOVSD, and MOVD, i.e. setting the lowest element. 2923static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2924 if (VT.getVectorElementType().getSizeInBits() < 32) 2925 return false; 2926 2927 int NumElts = VT.getVectorNumElements(); 2928 2929 if (!isUndefOrEqual(Mask[0], NumElts)) 2930 return false; 2931 2932 for (int i = 1; i < NumElts; ++i) 2933 if (!isUndefOrEqual(Mask[i], i)) 2934 return false; 2935 2936 return true; 2937} 2938 2939bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2940 SmallVector<int, 8> M; 2941 N->getMask(M); 2942 return ::isMOVLMask(M, N->getValueType(0)); 2943} 2944 2945/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2946/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2947/// element of vector 2 and the other elements to come from vector 1 in order. 2948static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2949 bool V2IsSplat = false, bool V2IsUndef = false) { 2950 int NumOps = VT.getVectorNumElements(); 2951 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2952 return false; 2953 2954 if (!isUndefOrEqual(Mask[0], 0)) 2955 return false; 2956 2957 for (int i = 1; i < NumOps; ++i) 2958 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2959 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2960 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2961 return false; 2962 2963 return true; 2964} 2965 2966static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2967 bool V2IsUndef = false) { 2968 SmallVector<int, 8> M; 2969 N->getMask(M); 2970 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2971} 2972 2973/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2974/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2975bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2976 if (N->getValueType(0).getVectorNumElements() != 4) 2977 return false; 2978 2979 // Expect 1, 1, 3, 3 2980 for (unsigned i = 0; i < 2; ++i) { 2981 int Elt = N->getMaskElt(i); 2982 if (Elt >= 0 && Elt != 1) 2983 return false; 2984 } 2985 2986 bool HasHi = false; 2987 for (unsigned i = 2; i < 4; ++i) { 2988 int Elt = N->getMaskElt(i); 2989 if (Elt >= 0 && Elt != 3) 2990 return false; 2991 if (Elt == 3) 2992 HasHi = true; 2993 } 2994 // Don't use movshdup if it can be done with a shufps. 2995 // FIXME: verify that matching u, u, 3, 3 is what we want. 2996 return HasHi; 2997} 2998 2999/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3000/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3001bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3002 if (N->getValueType(0).getVectorNumElements() != 4) 3003 return false; 3004 3005 // Expect 0, 0, 2, 2 3006 for (unsigned i = 0; i < 2; ++i) 3007 if (N->getMaskElt(i) > 0) 3008 return false; 3009 3010 bool HasHi = false; 3011 for (unsigned i = 2; i < 4; ++i) { 3012 int Elt = N->getMaskElt(i); 3013 if (Elt >= 0 && Elt != 2) 3014 return false; 3015 if (Elt == 2) 3016 HasHi = true; 3017 } 3018 // Don't use movsldup if it can be done with a shufps. 3019 return HasHi; 3020} 3021 3022/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3023/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3024bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3025 int e = N->getValueType(0).getVectorNumElements() / 2; 3026 3027 for (int i = 0; i < e; ++i) 3028 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3029 return false; 3030 for (int i = 0; i < e; ++i) 3031 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3032 return false; 3033 return true; 3034} 3035 3036/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3037/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3038unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3040 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3041 3042 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3043 unsigned Mask = 0; 3044 for (int i = 0; i < NumOperands; ++i) { 3045 int Val = SVOp->getMaskElt(NumOperands-i-1); 3046 if (Val < 0) Val = 0; 3047 if (Val >= NumOperands) Val -= NumOperands; 3048 Mask |= Val; 3049 if (i != NumOperands - 1) 3050 Mask <<= Shift; 3051 } 3052 return Mask; 3053} 3054 3055/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3056/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3057unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3059 unsigned Mask = 0; 3060 // 8 nodes, but we only care about the last 4. 3061 for (unsigned i = 7; i >= 4; --i) { 3062 int Val = SVOp->getMaskElt(i); 3063 if (Val >= 0) 3064 Mask |= (Val - 4); 3065 if (i != 4) 3066 Mask <<= 2; 3067 } 3068 return Mask; 3069} 3070 3071/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3072/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3073unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3075 unsigned Mask = 0; 3076 // 8 nodes, but we only care about the first 4. 3077 for (int i = 3; i >= 0; --i) { 3078 int Val = SVOp->getMaskElt(i); 3079 if (Val >= 0) 3080 Mask |= Val; 3081 if (i != 0) 3082 Mask <<= 2; 3083 } 3084 return Mask; 3085} 3086 3087/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3088/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3089unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3091 EVT VVT = N->getValueType(0); 3092 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3093 int Val = 0; 3094 3095 unsigned i, e; 3096 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3097 Val = SVOp->getMaskElt(i); 3098 if (Val >= 0) 3099 break; 3100 } 3101 return (Val - i) * EltSize; 3102} 3103 3104/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3105/// constant +0.0. 3106bool X86::isZeroNode(SDValue Elt) { 3107 return ((isa<ConstantSDNode>(Elt) && 3108 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 3109 (isa<ConstantFPSDNode>(Elt) && 3110 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3111} 3112 3113/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3114/// their permute mask. 3115static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3116 SelectionDAG &DAG) { 3117 EVT VT = SVOp->getValueType(0); 3118 unsigned NumElems = VT.getVectorNumElements(); 3119 SmallVector<int, 8> MaskVec; 3120 3121 for (unsigned i = 0; i != NumElems; ++i) { 3122 int idx = SVOp->getMaskElt(i); 3123 if (idx < 0) 3124 MaskVec.push_back(idx); 3125 else if (idx < (int)NumElems) 3126 MaskVec.push_back(idx + NumElems); 3127 else 3128 MaskVec.push_back(idx - NumElems); 3129 } 3130 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3131 SVOp->getOperand(0), &MaskVec[0]); 3132} 3133 3134/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3135/// the two vector operands have swapped position. 3136static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3137 unsigned NumElems = VT.getVectorNumElements(); 3138 for (unsigned i = 0; i != NumElems; ++i) { 3139 int idx = Mask[i]; 3140 if (idx < 0) 3141 continue; 3142 else if (idx < (int)NumElems) 3143 Mask[i] = idx + NumElems; 3144 else 3145 Mask[i] = idx - NumElems; 3146 } 3147} 3148 3149/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3150/// match movhlps. The lower half elements should come from upper half of 3151/// V1 (and in order), and the upper half elements should come from the upper 3152/// half of V2 (and in order). 3153static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3154 if (Op->getValueType(0).getVectorNumElements() != 4) 3155 return false; 3156 for (unsigned i = 0, e = 2; i != e; ++i) 3157 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3158 return false; 3159 for (unsigned i = 2; i != 4; ++i) 3160 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3161 return false; 3162 return true; 3163} 3164 3165/// isScalarLoadToVector - Returns true if the node is a scalar load that 3166/// is promoted to a vector. It also returns the LoadSDNode by reference if 3167/// required. 3168static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3169 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3170 return false; 3171 N = N->getOperand(0).getNode(); 3172 if (!ISD::isNON_EXTLoad(N)) 3173 return false; 3174 if (LD) 3175 *LD = cast<LoadSDNode>(N); 3176 return true; 3177} 3178 3179/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3180/// match movlp{s|d}. The lower half elements should come from lower half of 3181/// V1 (and in order), and the upper half elements should come from the upper 3182/// half of V2 (and in order). And since V1 will become the source of the 3183/// MOVLP, it must be either a vector load or a scalar load to vector. 3184static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3185 ShuffleVectorSDNode *Op) { 3186 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3187 return false; 3188 // Is V2 is a vector load, don't do this transformation. We will try to use 3189 // load folding shufps op. 3190 if (ISD::isNON_EXTLoad(V2)) 3191 return false; 3192 3193 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3194 3195 if (NumElems != 2 && NumElems != 4) 3196 return false; 3197 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3198 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3199 return false; 3200 for (unsigned i = NumElems/2; i != NumElems; ++i) 3201 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3202 return false; 3203 return true; 3204} 3205 3206/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3207/// all the same. 3208static bool isSplatVector(SDNode *N) { 3209 if (N->getOpcode() != ISD::BUILD_VECTOR) 3210 return false; 3211 3212 SDValue SplatValue = N->getOperand(0); 3213 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3214 if (N->getOperand(i) != SplatValue) 3215 return false; 3216 return true; 3217} 3218 3219/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3220/// to an zero vector. 3221/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3222static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3223 SDValue V1 = N->getOperand(0); 3224 SDValue V2 = N->getOperand(1); 3225 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3226 for (unsigned i = 0; i != NumElems; ++i) { 3227 int Idx = N->getMaskElt(i); 3228 if (Idx >= (int)NumElems) { 3229 unsigned Opc = V2.getOpcode(); 3230 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3231 continue; 3232 if (Opc != ISD::BUILD_VECTOR || 3233 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3234 return false; 3235 } else if (Idx >= 0) { 3236 unsigned Opc = V1.getOpcode(); 3237 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3238 continue; 3239 if (Opc != ISD::BUILD_VECTOR || 3240 !X86::isZeroNode(V1.getOperand(Idx))) 3241 return false; 3242 } 3243 } 3244 return true; 3245} 3246 3247/// getZeroVector - Returns a vector of specified type with all zero elements. 3248/// 3249static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3250 DebugLoc dl) { 3251 assert(VT.isVector() && "Expected a vector type"); 3252 3253 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3254 // type. This ensures they get CSE'd. 3255 SDValue Vec; 3256 if (VT.getSizeInBits() == 64) { // MMX 3257 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3259 } else if (HasSSE2) { // SSE2 3260 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3262 } else { // SSE1 3263 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3264 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3265 } 3266 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3267} 3268 3269/// getOnesVector - Returns a vector of specified type with all bits set. 3270/// 3271static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3272 assert(VT.isVector() && "Expected a vector type"); 3273 3274 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3275 // type. This ensures they get CSE'd. 3276 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3277 SDValue Vec; 3278 if (VT.getSizeInBits() == 64) // MMX 3279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3280 else // SSE 3281 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3282 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3283} 3284 3285 3286/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3287/// that point to V2 points to its first element. 3288static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3289 EVT VT = SVOp->getValueType(0); 3290 unsigned NumElems = VT.getVectorNumElements(); 3291 3292 bool Changed = false; 3293 SmallVector<int, 8> MaskVec; 3294 SVOp->getMask(MaskVec); 3295 3296 for (unsigned i = 0; i != NumElems; ++i) { 3297 if (MaskVec[i] > (int)NumElems) { 3298 MaskVec[i] = NumElems; 3299 Changed = true; 3300 } 3301 } 3302 if (Changed) 3303 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3304 SVOp->getOperand(1), &MaskVec[0]); 3305 return SDValue(SVOp, 0); 3306} 3307 3308/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3309/// operation of specified width. 3310static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3311 SDValue V2) { 3312 unsigned NumElems = VT.getVectorNumElements(); 3313 SmallVector<int, 8> Mask; 3314 Mask.push_back(NumElems); 3315 for (unsigned i = 1; i != NumElems; ++i) 3316 Mask.push_back(i); 3317 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3318} 3319 3320/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3321static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3322 SDValue V2) { 3323 unsigned NumElems = VT.getVectorNumElements(); 3324 SmallVector<int, 8> Mask; 3325 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3326 Mask.push_back(i); 3327 Mask.push_back(i + NumElems); 3328 } 3329 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3330} 3331 3332/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3333static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3334 SDValue V2) { 3335 unsigned NumElems = VT.getVectorNumElements(); 3336 unsigned Half = NumElems/2; 3337 SmallVector<int, 8> Mask; 3338 for (unsigned i = 0; i != Half; ++i) { 3339 Mask.push_back(i + Half); 3340 Mask.push_back(i + NumElems + Half); 3341 } 3342 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3343} 3344 3345/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3346static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3347 bool HasSSE2) { 3348 if (SV->getValueType(0).getVectorNumElements() <= 4) 3349 return SDValue(SV, 0); 3350 3351 EVT PVT = MVT::v4f32; 3352 EVT VT = SV->getValueType(0); 3353 DebugLoc dl = SV->getDebugLoc(); 3354 SDValue V1 = SV->getOperand(0); 3355 int NumElems = VT.getVectorNumElements(); 3356 int EltNo = SV->getSplatIndex(); 3357 3358 // unpack elements to the correct location 3359 while (NumElems > 4) { 3360 if (EltNo < NumElems/2) { 3361 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3362 } else { 3363 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3364 EltNo -= NumElems/2; 3365 } 3366 NumElems >>= 1; 3367 } 3368 3369 // Perform the splat. 3370 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3371 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3372 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3373 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3374} 3375 3376/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3377/// vector of zero or undef vector. This produces a shuffle where the low 3378/// element of V2 is swizzled into the zero/undef vector, landing at element 3379/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3380static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3381 bool isZero, bool HasSSE2, 3382 SelectionDAG &DAG) { 3383 EVT VT = V2.getValueType(); 3384 SDValue V1 = isZero 3385 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3386 unsigned NumElems = VT.getVectorNumElements(); 3387 SmallVector<int, 16> MaskVec; 3388 for (unsigned i = 0; i != NumElems; ++i) 3389 // If this is the insertion idx, put the low elt of V2 here. 3390 MaskVec.push_back(i == Idx ? NumElems : i); 3391 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3392} 3393 3394/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3395/// a shuffle that is zero. 3396static 3397unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3398 bool Low, SelectionDAG &DAG) { 3399 unsigned NumZeros = 0; 3400 for (int i = 0; i < NumElems; ++i) { 3401 unsigned Index = Low ? i : NumElems-i-1; 3402 int Idx = SVOp->getMaskElt(Index); 3403 if (Idx < 0) { 3404 ++NumZeros; 3405 continue; 3406 } 3407 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3408 if (Elt.getNode() && X86::isZeroNode(Elt)) 3409 ++NumZeros; 3410 else 3411 break; 3412 } 3413 return NumZeros; 3414} 3415 3416/// isVectorShift - Returns true if the shuffle can be implemented as a 3417/// logical left or right shift of a vector. 3418/// FIXME: split into pslldqi, psrldqi, palignr variants. 3419static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3420 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3421 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3422 3423 isLeft = true; 3424 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3425 if (!NumZeros) { 3426 isLeft = false; 3427 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3428 if (!NumZeros) 3429 return false; 3430 } 3431 bool SeenV1 = false; 3432 bool SeenV2 = false; 3433 for (int i = NumZeros; i < NumElems; ++i) { 3434 int Val = isLeft ? (i - NumZeros) : i; 3435 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3436 if (Idx < 0) 3437 continue; 3438 if (Idx < NumElems) 3439 SeenV1 = true; 3440 else { 3441 Idx -= NumElems; 3442 SeenV2 = true; 3443 } 3444 if (Idx != Val) 3445 return false; 3446 } 3447 if (SeenV1 && SeenV2) 3448 return false; 3449 3450 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3451 ShAmt = NumZeros; 3452 return true; 3453} 3454 3455 3456/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3457/// 3458static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3459 unsigned NumNonZero, unsigned NumZero, 3460 SelectionDAG &DAG, TargetLowering &TLI) { 3461 if (NumNonZero > 8) 3462 return SDValue(); 3463 3464 DebugLoc dl = Op.getDebugLoc(); 3465 SDValue V(0, 0); 3466 bool First = true; 3467 for (unsigned i = 0; i < 16; ++i) { 3468 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3469 if (ThisIsNonZero && First) { 3470 if (NumZero) 3471 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3472 else 3473 V = DAG.getUNDEF(MVT::v8i16); 3474 First = false; 3475 } 3476 3477 if ((i & 1) != 0) { 3478 SDValue ThisElt(0, 0), LastElt(0, 0); 3479 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3480 if (LastIsNonZero) { 3481 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3482 MVT::i16, Op.getOperand(i-1)); 3483 } 3484 if (ThisIsNonZero) { 3485 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3486 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3487 ThisElt, DAG.getConstant(8, MVT::i8)); 3488 if (LastIsNonZero) 3489 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3490 } else 3491 ThisElt = LastElt; 3492 3493 if (ThisElt.getNode()) 3494 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3495 DAG.getIntPtrConstant(i/2)); 3496 } 3497 } 3498 3499 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3500} 3501 3502/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3503/// 3504static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3505 unsigned NumNonZero, unsigned NumZero, 3506 SelectionDAG &DAG, TargetLowering &TLI) { 3507 if (NumNonZero > 4) 3508 return SDValue(); 3509 3510 DebugLoc dl = Op.getDebugLoc(); 3511 SDValue V(0, 0); 3512 bool First = true; 3513 for (unsigned i = 0; i < 8; ++i) { 3514 bool isNonZero = (NonZeros & (1 << i)) != 0; 3515 if (isNonZero) { 3516 if (First) { 3517 if (NumZero) 3518 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3519 else 3520 V = DAG.getUNDEF(MVT::v8i16); 3521 First = false; 3522 } 3523 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3524 MVT::v8i16, V, Op.getOperand(i), 3525 DAG.getIntPtrConstant(i)); 3526 } 3527 } 3528 3529 return V; 3530} 3531 3532/// getVShift - Return a vector logical shift node. 3533/// 3534static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3535 unsigned NumBits, SelectionDAG &DAG, 3536 const TargetLowering &TLI, DebugLoc dl) { 3537 bool isMMX = VT.getSizeInBits() == 64; 3538 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3539 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3540 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3541 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3542 DAG.getNode(Opc, dl, ShVT, SrcOp, 3543 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3544} 3545 3546SDValue 3547X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3548 SelectionDAG &DAG) { 3549 3550 // Check if the scalar load can be widened into a vector load. And if 3551 // the address is "base + cst" see if the cst can be "absorbed" into 3552 // the shuffle mask. 3553 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3554 SDValue Ptr = LD->getBasePtr(); 3555 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3556 return SDValue(); 3557 EVT PVT = LD->getValueType(0); 3558 if (PVT != MVT::i32 && PVT != MVT::f32) 3559 return SDValue(); 3560 3561 int FI = -1; 3562 int64_t Offset = 0; 3563 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3564 FI = FINode->getIndex(); 3565 Offset = 0; 3566 } else if (Ptr.getOpcode() == ISD::ADD && 3567 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3568 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3569 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3570 Offset = Ptr.getConstantOperandVal(1); 3571 Ptr = Ptr.getOperand(0); 3572 } else { 3573 return SDValue(); 3574 } 3575 3576 SDValue Chain = LD->getChain(); 3577 // Make sure the stack object alignment is at least 16. 3578 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3579 if (DAG.InferPtrAlignment(Ptr) < 16) { 3580 if (MFI->isFixedObjectIndex(FI)) { 3581 // Can't change the alignment. FIXME: It's possible to compute 3582 // the exact stack offset and reference FI + adjust offset instead. 3583 // If someone *really* cares about this. That's the way to implement it. 3584 return SDValue(); 3585 } else { 3586 MFI->setObjectAlignment(FI, 16); 3587 } 3588 } 3589 3590 // (Offset % 16) must be multiple of 4. Then address is then 3591 // Ptr + (Offset & ~15). 3592 if (Offset < 0) 3593 return SDValue(); 3594 if ((Offset % 16) & 3) 3595 return SDValue(); 3596 int64_t StartOffset = Offset & ~15; 3597 if (StartOffset) 3598 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3599 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3600 3601 int EltNo = (Offset - StartOffset) >> 2; 3602 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3603 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3604 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3605 false, false, 0); 3606 // Canonicalize it to a v4i32 shuffle. 3607 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3608 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3609 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3610 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3611 } 3612 3613 return SDValue(); 3614} 3615 3616/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 3617/// vector of type 'VT', see if the elements can be replaced by a single large 3618/// load which has the same value as a build_vector whose operands are 'elts'. 3619/// 3620/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 3621/// 3622/// FIXME: we'd also like to handle the case where the last elements are zero 3623/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 3624/// There's even a handy isZeroNode for that purpose. 3625static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 3626 DebugLoc &dl, SelectionDAG &DAG) { 3627 EVT EltVT = VT.getVectorElementType(); 3628 unsigned NumElems = Elts.size(); 3629 3630 LoadSDNode *LDBase = NULL; 3631 unsigned LastLoadedElt = -1U; 3632 3633 // For each element in the initializer, see if we've found a load or an undef. 3634 // If we don't find an initial load element, or later load elements are 3635 // non-consecutive, bail out. 3636 for (unsigned i = 0; i < NumElems; ++i) { 3637 SDValue Elt = Elts[i]; 3638 3639 if (!Elt.getNode() || 3640 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 3641 return SDValue(); 3642 if (!LDBase) { 3643 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 3644 return SDValue(); 3645 LDBase = cast<LoadSDNode>(Elt.getNode()); 3646 LastLoadedElt = i; 3647 continue; 3648 } 3649 if (Elt.getOpcode() == ISD::UNDEF) 3650 continue; 3651 3652 LoadSDNode *LD = cast<LoadSDNode>(Elt); 3653 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 3654 return SDValue(); 3655 LastLoadedElt = i; 3656 } 3657 3658 // If we have found an entire vector of loads and undefs, then return a large 3659 // load of the entire vector width starting at the base pointer. If we found 3660 // consecutive loads for the low half, generate a vzext_load node. 3661 if (LastLoadedElt == NumElems - 1) { 3662 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 3663 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 3664 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 3665 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 3666 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 3667 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 3668 LDBase->isVolatile(), LDBase->isNonTemporal(), 3669 LDBase->getAlignment()); 3670 } else if (NumElems == 4 && LastLoadedElt == 1) { 3671 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 3672 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 3673 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 3674 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 3675 } 3676 return SDValue(); 3677} 3678 3679SDValue 3680X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3681 DebugLoc dl = Op.getDebugLoc(); 3682 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3683 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3684 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3685 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3686 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3687 // eliminated on x86-32 hosts. 3688 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3689 return Op; 3690 3691 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3692 return getOnesVector(Op.getValueType(), DAG, dl); 3693 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3694 } 3695 3696 EVT VT = Op.getValueType(); 3697 EVT ExtVT = VT.getVectorElementType(); 3698 unsigned EVTBits = ExtVT.getSizeInBits(); 3699 3700 unsigned NumElems = Op.getNumOperands(); 3701 unsigned NumZero = 0; 3702 unsigned NumNonZero = 0; 3703 unsigned NonZeros = 0; 3704 bool IsAllConstants = true; 3705 SmallSet<SDValue, 8> Values; 3706 for (unsigned i = 0; i < NumElems; ++i) { 3707 SDValue Elt = Op.getOperand(i); 3708 if (Elt.getOpcode() == ISD::UNDEF) 3709 continue; 3710 Values.insert(Elt); 3711 if (Elt.getOpcode() != ISD::Constant && 3712 Elt.getOpcode() != ISD::ConstantFP) 3713 IsAllConstants = false; 3714 if (X86::isZeroNode(Elt)) 3715 NumZero++; 3716 else { 3717 NonZeros |= (1 << i); 3718 NumNonZero++; 3719 } 3720 } 3721 3722 if (NumNonZero == 0) { 3723 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3724 return DAG.getUNDEF(VT); 3725 } 3726 3727 // Special case for single non-zero, non-undef, element. 3728 if (NumNonZero == 1) { 3729 unsigned Idx = CountTrailingZeros_32(NonZeros); 3730 SDValue Item = Op.getOperand(Idx); 3731 3732 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3733 // the value are obviously zero, truncate the value to i32 and do the 3734 // insertion that way. Only do this if the value is non-constant or if the 3735 // value is a constant being inserted into element 0. It is cheaper to do 3736 // a constant pool load than it is to do a movd + shuffle. 3737 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3738 (!IsAllConstants || Idx == 0)) { 3739 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3740 // Handle MMX and SSE both. 3741 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3742 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3743 3744 // Truncate the value (which may itself be a constant) to i32, and 3745 // convert it to a vector with movd (S2V+shuffle to zero extend). 3746 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3747 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3748 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3749 Subtarget->hasSSE2(), DAG); 3750 3751 // Now we have our 32-bit value zero extended in the low element of 3752 // a vector. If Idx != 0, swizzle it into place. 3753 if (Idx != 0) { 3754 SmallVector<int, 4> Mask; 3755 Mask.push_back(Idx); 3756 for (unsigned i = 1; i != VecElts; ++i) 3757 Mask.push_back(i); 3758 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3759 DAG.getUNDEF(Item.getValueType()), 3760 &Mask[0]); 3761 } 3762 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3763 } 3764 } 3765 3766 // If we have a constant or non-constant insertion into the low element of 3767 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3768 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3769 // depending on what the source datatype is. 3770 if (Idx == 0) { 3771 if (NumZero == 0) { 3772 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3773 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3774 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3775 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3776 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3777 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3778 DAG); 3779 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3780 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3781 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3782 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3783 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3784 Subtarget->hasSSE2(), DAG); 3785 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3786 } 3787 } 3788 3789 // Is it a vector logical left shift? 3790 if (NumElems == 2 && Idx == 1 && 3791 X86::isZeroNode(Op.getOperand(0)) && 3792 !X86::isZeroNode(Op.getOperand(1))) { 3793 unsigned NumBits = VT.getSizeInBits(); 3794 return getVShift(true, VT, 3795 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3796 VT, Op.getOperand(1)), 3797 NumBits/2, DAG, *this, dl); 3798 } 3799 3800 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3801 return SDValue(); 3802 3803 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3804 // is a non-constant being inserted into an element other than the low one, 3805 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3806 // movd/movss) to move this into the low element, then shuffle it into 3807 // place. 3808 if (EVTBits == 32) { 3809 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3810 3811 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3812 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3813 Subtarget->hasSSE2(), DAG); 3814 SmallVector<int, 8> MaskVec; 3815 for (unsigned i = 0; i < NumElems; i++) 3816 MaskVec.push_back(i == Idx ? 0 : 1); 3817 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3818 } 3819 } 3820 3821 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3822 if (Values.size() == 1) { 3823 if (EVTBits == 32) { 3824 // Instead of a shuffle like this: 3825 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 3826 // Check if it's possible to issue this instead. 3827 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 3828 unsigned Idx = CountTrailingZeros_32(NonZeros); 3829 SDValue Item = Op.getOperand(Idx); 3830 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 3831 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 3832 } 3833 return SDValue(); 3834 } 3835 3836 // A vector full of immediates; various special cases are already 3837 // handled, so this is best done with a single constant-pool load. 3838 if (IsAllConstants) 3839 return SDValue(); 3840 3841 // Let legalizer expand 2-wide build_vectors. 3842 if (EVTBits == 64) { 3843 if (NumNonZero == 1) { 3844 // One half is zero or undef. 3845 unsigned Idx = CountTrailingZeros_32(NonZeros); 3846 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3847 Op.getOperand(Idx)); 3848 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3849 Subtarget->hasSSE2(), DAG); 3850 } 3851 return SDValue(); 3852 } 3853 3854 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3855 if (EVTBits == 8 && NumElems == 16) { 3856 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3857 *this); 3858 if (V.getNode()) return V; 3859 } 3860 3861 if (EVTBits == 16 && NumElems == 8) { 3862 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3863 *this); 3864 if (V.getNode()) return V; 3865 } 3866 3867 // If element VT is == 32 bits, turn it into a number of shuffles. 3868 SmallVector<SDValue, 8> V; 3869 V.resize(NumElems); 3870 if (NumElems == 4 && NumZero > 0) { 3871 for (unsigned i = 0; i < 4; ++i) { 3872 bool isZero = !(NonZeros & (1 << i)); 3873 if (isZero) 3874 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3875 else 3876 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3877 } 3878 3879 for (unsigned i = 0; i < 2; ++i) { 3880 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3881 default: break; 3882 case 0: 3883 V[i] = V[i*2]; // Must be a zero vector. 3884 break; 3885 case 1: 3886 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3887 break; 3888 case 2: 3889 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3890 break; 3891 case 3: 3892 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3893 break; 3894 } 3895 } 3896 3897 SmallVector<int, 8> MaskVec; 3898 bool Reverse = (NonZeros & 0x3) == 2; 3899 for (unsigned i = 0; i < 2; ++i) 3900 MaskVec.push_back(Reverse ? 1-i : i); 3901 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3902 for (unsigned i = 0; i < 2; ++i) 3903 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3904 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3905 } 3906 3907 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 3908 // Check for a build vector of consecutive loads. 3909 for (unsigned i = 0; i < NumElems; ++i) 3910 V[i] = Op.getOperand(i); 3911 3912 // Check for elements which are consecutive loads. 3913 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 3914 if (LD.getNode()) 3915 return LD; 3916 3917 // For SSE 4.1, use inserts into undef. 3918 if (getSubtarget()->hasSSE41()) { 3919 V[0] = DAG.getUNDEF(VT); 3920 for (unsigned i = 0; i < NumElems; ++i) 3921 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3922 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3923 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3924 return V[0]; 3925 } 3926 3927 // Otherwise, expand into a number of unpckl* 3928 // e.g. for v4f32 3929 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3930 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3931 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3932 for (unsigned i = 0; i < NumElems; ++i) 3933 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3934 NumElems >>= 1; 3935 while (NumElems != 0) { 3936 for (unsigned i = 0; i < NumElems; ++i) 3937 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3938 NumElems >>= 1; 3939 } 3940 return V[0]; 3941 } 3942 return SDValue(); 3943} 3944 3945SDValue 3946X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3947 // We support concatenate two MMX registers and place them in a MMX 3948 // register. This is better than doing a stack convert. 3949 DebugLoc dl = Op.getDebugLoc(); 3950 EVT ResVT = Op.getValueType(); 3951 assert(Op.getNumOperands() == 2); 3952 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 3953 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 3954 int Mask[2]; 3955 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 3956 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3957 InVec = Op.getOperand(1); 3958 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3959 unsigned NumElts = ResVT.getVectorNumElements(); 3960 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3961 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 3962 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 3963 } else { 3964 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 3965 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3966 Mask[0] = 0; Mask[1] = 2; 3967 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 3968 } 3969 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3970} 3971 3972// v8i16 shuffles - Prefer shuffles in the following order: 3973// 1. [all] pshuflw, pshufhw, optional move 3974// 2. [ssse3] 1 x pshufb 3975// 3. [ssse3] 2 x pshufb + 1 x por 3976// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3977static 3978SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3979 SelectionDAG &DAG, X86TargetLowering &TLI) { 3980 SDValue V1 = SVOp->getOperand(0); 3981 SDValue V2 = SVOp->getOperand(1); 3982 DebugLoc dl = SVOp->getDebugLoc(); 3983 SmallVector<int, 8> MaskVals; 3984 3985 // Determine if more than 1 of the words in each of the low and high quadwords 3986 // of the result come from the same quadword of one of the two inputs. Undef 3987 // mask values count as coming from any quadword, for better codegen. 3988 SmallVector<unsigned, 4> LoQuad(4); 3989 SmallVector<unsigned, 4> HiQuad(4); 3990 BitVector InputQuads(4); 3991 for (unsigned i = 0; i < 8; ++i) { 3992 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3993 int EltIdx = SVOp->getMaskElt(i); 3994 MaskVals.push_back(EltIdx); 3995 if (EltIdx < 0) { 3996 ++Quad[0]; 3997 ++Quad[1]; 3998 ++Quad[2]; 3999 ++Quad[3]; 4000 continue; 4001 } 4002 ++Quad[EltIdx / 4]; 4003 InputQuads.set(EltIdx / 4); 4004 } 4005 4006 int BestLoQuad = -1; 4007 unsigned MaxQuad = 1; 4008 for (unsigned i = 0; i < 4; ++i) { 4009 if (LoQuad[i] > MaxQuad) { 4010 BestLoQuad = i; 4011 MaxQuad = LoQuad[i]; 4012 } 4013 } 4014 4015 int BestHiQuad = -1; 4016 MaxQuad = 1; 4017 for (unsigned i = 0; i < 4; ++i) { 4018 if (HiQuad[i] > MaxQuad) { 4019 BestHiQuad = i; 4020 MaxQuad = HiQuad[i]; 4021 } 4022 } 4023 4024 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4025 // of the two input vectors, shuffle them into one input vector so only a 4026 // single pshufb instruction is necessary. If There are more than 2 input 4027 // quads, disable the next transformation since it does not help SSSE3. 4028 bool V1Used = InputQuads[0] || InputQuads[1]; 4029 bool V2Used = InputQuads[2] || InputQuads[3]; 4030 if (TLI.getSubtarget()->hasSSSE3()) { 4031 if (InputQuads.count() == 2 && V1Used && V2Used) { 4032 BestLoQuad = InputQuads.find_first(); 4033 BestHiQuad = InputQuads.find_next(BestLoQuad); 4034 } 4035 if (InputQuads.count() > 2) { 4036 BestLoQuad = -1; 4037 BestHiQuad = -1; 4038 } 4039 } 4040 4041 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4042 // the shuffle mask. If a quad is scored as -1, that means that it contains 4043 // words from all 4 input quadwords. 4044 SDValue NewV; 4045 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4046 SmallVector<int, 8> MaskV; 4047 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4048 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4049 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4050 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 4051 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 4052 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 4053 4054 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4055 // source words for the shuffle, to aid later transformations. 4056 bool AllWordsInNewV = true; 4057 bool InOrder[2] = { true, true }; 4058 for (unsigned i = 0; i != 8; ++i) { 4059 int idx = MaskVals[i]; 4060 if (idx != (int)i) 4061 InOrder[i/4] = false; 4062 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4063 continue; 4064 AllWordsInNewV = false; 4065 break; 4066 } 4067 4068 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4069 if (AllWordsInNewV) { 4070 for (int i = 0; i != 8; ++i) { 4071 int idx = MaskVals[i]; 4072 if (idx < 0) 4073 continue; 4074 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4075 if ((idx != i) && idx < 4) 4076 pshufhw = false; 4077 if ((idx != i) && idx > 3) 4078 pshuflw = false; 4079 } 4080 V1 = NewV; 4081 V2Used = false; 4082 BestLoQuad = 0; 4083 BestHiQuad = 1; 4084 } 4085 4086 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4087 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4088 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4089 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4090 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4091 } 4092 } 4093 4094 // If we have SSSE3, and all words of the result are from 1 input vector, 4095 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4096 // is present, fall back to case 4. 4097 if (TLI.getSubtarget()->hasSSSE3()) { 4098 SmallVector<SDValue,16> pshufbMask; 4099 4100 // If we have elements from both input vectors, set the high bit of the 4101 // shuffle mask element to zero out elements that come from V2 in the V1 4102 // mask, and elements that come from V1 in the V2 mask, so that the two 4103 // results can be OR'd together. 4104 bool TwoInputs = V1Used && V2Used; 4105 for (unsigned i = 0; i != 8; ++i) { 4106 int EltIdx = MaskVals[i] * 2; 4107 if (TwoInputs && (EltIdx >= 16)) { 4108 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4109 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4110 continue; 4111 } 4112 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4113 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4114 } 4115 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4116 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4117 DAG.getNode(ISD::BUILD_VECTOR, dl, 4118 MVT::v16i8, &pshufbMask[0], 16)); 4119 if (!TwoInputs) 4120 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4121 4122 // Calculate the shuffle mask for the second input, shuffle it, and 4123 // OR it with the first shuffled input. 4124 pshufbMask.clear(); 4125 for (unsigned i = 0; i != 8; ++i) { 4126 int EltIdx = MaskVals[i] * 2; 4127 if (EltIdx < 16) { 4128 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4129 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4130 continue; 4131 } 4132 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4133 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4134 } 4135 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4136 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4137 DAG.getNode(ISD::BUILD_VECTOR, dl, 4138 MVT::v16i8, &pshufbMask[0], 16)); 4139 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4140 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4141 } 4142 4143 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4144 // and update MaskVals with new element order. 4145 BitVector InOrder(8); 4146 if (BestLoQuad >= 0) { 4147 SmallVector<int, 8> MaskV; 4148 for (int i = 0; i != 4; ++i) { 4149 int idx = MaskVals[i]; 4150 if (idx < 0) { 4151 MaskV.push_back(-1); 4152 InOrder.set(i); 4153 } else if ((idx / 4) == BestLoQuad) { 4154 MaskV.push_back(idx & 3); 4155 InOrder.set(i); 4156 } else { 4157 MaskV.push_back(-1); 4158 } 4159 } 4160 for (unsigned i = 4; i != 8; ++i) 4161 MaskV.push_back(i); 4162 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4163 &MaskV[0]); 4164 } 4165 4166 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4167 // and update MaskVals with the new element order. 4168 if (BestHiQuad >= 0) { 4169 SmallVector<int, 8> MaskV; 4170 for (unsigned i = 0; i != 4; ++i) 4171 MaskV.push_back(i); 4172 for (unsigned i = 4; i != 8; ++i) { 4173 int idx = MaskVals[i]; 4174 if (idx < 0) { 4175 MaskV.push_back(-1); 4176 InOrder.set(i); 4177 } else if ((idx / 4) == BestHiQuad) { 4178 MaskV.push_back((idx & 3) + 4); 4179 InOrder.set(i); 4180 } else { 4181 MaskV.push_back(-1); 4182 } 4183 } 4184 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4185 &MaskV[0]); 4186 } 4187 4188 // In case BestHi & BestLo were both -1, which means each quadword has a word 4189 // from each of the four input quadwords, calculate the InOrder bitvector now 4190 // before falling through to the insert/extract cleanup. 4191 if (BestLoQuad == -1 && BestHiQuad == -1) { 4192 NewV = V1; 4193 for (int i = 0; i != 8; ++i) 4194 if (MaskVals[i] < 0 || MaskVals[i] == i) 4195 InOrder.set(i); 4196 } 4197 4198 // The other elements are put in the right place using pextrw and pinsrw. 4199 for (unsigned i = 0; i != 8; ++i) { 4200 if (InOrder[i]) 4201 continue; 4202 int EltIdx = MaskVals[i]; 4203 if (EltIdx < 0) 4204 continue; 4205 SDValue ExtOp = (EltIdx < 8) 4206 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4207 DAG.getIntPtrConstant(EltIdx)) 4208 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4209 DAG.getIntPtrConstant(EltIdx - 8)); 4210 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4211 DAG.getIntPtrConstant(i)); 4212 } 4213 return NewV; 4214} 4215 4216// v16i8 shuffles - Prefer shuffles in the following order: 4217// 1. [ssse3] 1 x pshufb 4218// 2. [ssse3] 2 x pshufb + 1 x por 4219// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4220static 4221SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4222 SelectionDAG &DAG, X86TargetLowering &TLI) { 4223 SDValue V1 = SVOp->getOperand(0); 4224 SDValue V2 = SVOp->getOperand(1); 4225 DebugLoc dl = SVOp->getDebugLoc(); 4226 SmallVector<int, 16> MaskVals; 4227 SVOp->getMask(MaskVals); 4228 4229 // If we have SSSE3, case 1 is generated when all result bytes come from 4230 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4231 // present, fall back to case 3. 4232 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4233 bool V1Only = true; 4234 bool V2Only = true; 4235 for (unsigned i = 0; i < 16; ++i) { 4236 int EltIdx = MaskVals[i]; 4237 if (EltIdx < 0) 4238 continue; 4239 if (EltIdx < 16) 4240 V2Only = false; 4241 else 4242 V1Only = false; 4243 } 4244 4245 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4246 if (TLI.getSubtarget()->hasSSSE3()) { 4247 SmallVector<SDValue,16> pshufbMask; 4248 4249 // If all result elements are from one input vector, then only translate 4250 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4251 // 4252 // Otherwise, we have elements from both input vectors, and must zero out 4253 // elements that come from V2 in the first mask, and V1 in the second mask 4254 // so that we can OR them together. 4255 bool TwoInputs = !(V1Only || V2Only); 4256 for (unsigned i = 0; i != 16; ++i) { 4257 int EltIdx = MaskVals[i]; 4258 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4259 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4260 continue; 4261 } 4262 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4263 } 4264 // If all the elements are from V2, assign it to V1 and return after 4265 // building the first pshufb. 4266 if (V2Only) 4267 V1 = V2; 4268 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4269 DAG.getNode(ISD::BUILD_VECTOR, dl, 4270 MVT::v16i8, &pshufbMask[0], 16)); 4271 if (!TwoInputs) 4272 return V1; 4273 4274 // Calculate the shuffle mask for the second input, shuffle it, and 4275 // OR it with the first shuffled input. 4276 pshufbMask.clear(); 4277 for (unsigned i = 0; i != 16; ++i) { 4278 int EltIdx = MaskVals[i]; 4279 if (EltIdx < 16) { 4280 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4281 continue; 4282 } 4283 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4284 } 4285 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4286 DAG.getNode(ISD::BUILD_VECTOR, dl, 4287 MVT::v16i8, &pshufbMask[0], 16)); 4288 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4289 } 4290 4291 // No SSSE3 - Calculate in place words and then fix all out of place words 4292 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4293 // the 16 different words that comprise the two doublequadword input vectors. 4294 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4295 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4296 SDValue NewV = V2Only ? V2 : V1; 4297 for (int i = 0; i != 8; ++i) { 4298 int Elt0 = MaskVals[i*2]; 4299 int Elt1 = MaskVals[i*2+1]; 4300 4301 // This word of the result is all undef, skip it. 4302 if (Elt0 < 0 && Elt1 < 0) 4303 continue; 4304 4305 // This word of the result is already in the correct place, skip it. 4306 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4307 continue; 4308 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4309 continue; 4310 4311 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4312 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4313 SDValue InsElt; 4314 4315 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4316 // using a single extract together, load it and store it. 4317 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4318 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4319 DAG.getIntPtrConstant(Elt1 / 2)); 4320 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4321 DAG.getIntPtrConstant(i)); 4322 continue; 4323 } 4324 4325 // If Elt1 is defined, extract it from the appropriate source. If the 4326 // source byte is not also odd, shift the extracted word left 8 bits 4327 // otherwise clear the bottom 8 bits if we need to do an or. 4328 if (Elt1 >= 0) { 4329 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4330 DAG.getIntPtrConstant(Elt1 / 2)); 4331 if ((Elt1 & 1) == 0) 4332 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4333 DAG.getConstant(8, TLI.getShiftAmountTy())); 4334 else if (Elt0 >= 0) 4335 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4336 DAG.getConstant(0xFF00, MVT::i16)); 4337 } 4338 // If Elt0 is defined, extract it from the appropriate source. If the 4339 // source byte is not also even, shift the extracted word right 8 bits. If 4340 // Elt1 was also defined, OR the extracted values together before 4341 // inserting them in the result. 4342 if (Elt0 >= 0) { 4343 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4344 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4345 if ((Elt0 & 1) != 0) 4346 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4347 DAG.getConstant(8, TLI.getShiftAmountTy())); 4348 else if (Elt1 >= 0) 4349 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4350 DAG.getConstant(0x00FF, MVT::i16)); 4351 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4352 : InsElt0; 4353 } 4354 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4355 DAG.getIntPtrConstant(i)); 4356 } 4357 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4358} 4359 4360/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4361/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 4362/// done when every pair / quad of shuffle mask elements point to elements in 4363/// the right sequence. e.g. 4364/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4365static 4366SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4367 SelectionDAG &DAG, 4368 TargetLowering &TLI, DebugLoc dl) { 4369 EVT VT = SVOp->getValueType(0); 4370 SDValue V1 = SVOp->getOperand(0); 4371 SDValue V2 = SVOp->getOperand(1); 4372 unsigned NumElems = VT.getVectorNumElements(); 4373 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4374 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 4375 EVT MaskEltVT = MaskVT.getVectorElementType(); 4376 EVT NewVT = MaskVT; 4377 switch (VT.getSimpleVT().SimpleTy) { 4378 default: assert(false && "Unexpected!"); 4379 case MVT::v4f32: NewVT = MVT::v2f64; break; 4380 case MVT::v4i32: NewVT = MVT::v2i64; break; 4381 case MVT::v8i16: NewVT = MVT::v4i32; break; 4382 case MVT::v16i8: NewVT = MVT::v4i32; break; 4383 } 4384 4385 if (NewWidth == 2) { 4386 if (VT.isInteger()) 4387 NewVT = MVT::v2i64; 4388 else 4389 NewVT = MVT::v2f64; 4390 } 4391 int Scale = NumElems / NewWidth; 4392 SmallVector<int, 8> MaskVec; 4393 for (unsigned i = 0; i < NumElems; i += Scale) { 4394 int StartIdx = -1; 4395 for (int j = 0; j < Scale; ++j) { 4396 int EltIdx = SVOp->getMaskElt(i+j); 4397 if (EltIdx < 0) 4398 continue; 4399 if (StartIdx == -1) 4400 StartIdx = EltIdx - (EltIdx % Scale); 4401 if (EltIdx != StartIdx + j) 4402 return SDValue(); 4403 } 4404 if (StartIdx == -1) 4405 MaskVec.push_back(-1); 4406 else 4407 MaskVec.push_back(StartIdx / Scale); 4408 } 4409 4410 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4411 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4412 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4413} 4414 4415/// getVZextMovL - Return a zero-extending vector move low node. 4416/// 4417static SDValue getVZextMovL(EVT VT, EVT OpVT, 4418 SDValue SrcOp, SelectionDAG &DAG, 4419 const X86Subtarget *Subtarget, DebugLoc dl) { 4420 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4421 LoadSDNode *LD = NULL; 4422 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4423 LD = dyn_cast<LoadSDNode>(SrcOp); 4424 if (!LD) { 4425 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4426 // instead. 4427 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4428 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4429 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4430 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4431 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4432 // PR2108 4433 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4434 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4435 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4436 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4437 OpVT, 4438 SrcOp.getOperand(0) 4439 .getOperand(0)))); 4440 } 4441 } 4442 } 4443 4444 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4445 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4446 DAG.getNode(ISD::BIT_CONVERT, dl, 4447 OpVT, SrcOp))); 4448} 4449 4450/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4451/// shuffles. 4452static SDValue 4453LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4454 SDValue V1 = SVOp->getOperand(0); 4455 SDValue V2 = SVOp->getOperand(1); 4456 DebugLoc dl = SVOp->getDebugLoc(); 4457 EVT VT = SVOp->getValueType(0); 4458 4459 SmallVector<std::pair<int, int>, 8> Locs; 4460 Locs.resize(4); 4461 SmallVector<int, 8> Mask1(4U, -1); 4462 SmallVector<int, 8> PermMask; 4463 SVOp->getMask(PermMask); 4464 4465 unsigned NumHi = 0; 4466 unsigned NumLo = 0; 4467 for (unsigned i = 0; i != 4; ++i) { 4468 int Idx = PermMask[i]; 4469 if (Idx < 0) { 4470 Locs[i] = std::make_pair(-1, -1); 4471 } else { 4472 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4473 if (Idx < 4) { 4474 Locs[i] = std::make_pair(0, NumLo); 4475 Mask1[NumLo] = Idx; 4476 NumLo++; 4477 } else { 4478 Locs[i] = std::make_pair(1, NumHi); 4479 if (2+NumHi < 4) 4480 Mask1[2+NumHi] = Idx; 4481 NumHi++; 4482 } 4483 } 4484 } 4485 4486 if (NumLo <= 2 && NumHi <= 2) { 4487 // If no more than two elements come from either vector. This can be 4488 // implemented with two shuffles. First shuffle gather the elements. 4489 // The second shuffle, which takes the first shuffle as both of its 4490 // vector operands, put the elements into the right order. 4491 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4492 4493 SmallVector<int, 8> Mask2(4U, -1); 4494 4495 for (unsigned i = 0; i != 4; ++i) { 4496 if (Locs[i].first == -1) 4497 continue; 4498 else { 4499 unsigned Idx = (i < 2) ? 0 : 4; 4500 Idx += Locs[i].first * 2 + Locs[i].second; 4501 Mask2[i] = Idx; 4502 } 4503 } 4504 4505 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4506 } else if (NumLo == 3 || NumHi == 3) { 4507 // Otherwise, we must have three elements from one vector, call it X, and 4508 // one element from the other, call it Y. First, use a shufps to build an 4509 // intermediate vector with the one element from Y and the element from X 4510 // that will be in the same half in the final destination (the indexes don't 4511 // matter). Then, use a shufps to build the final vector, taking the half 4512 // containing the element from Y from the intermediate, and the other half 4513 // from X. 4514 if (NumHi == 3) { 4515 // Normalize it so the 3 elements come from V1. 4516 CommuteVectorShuffleMask(PermMask, VT); 4517 std::swap(V1, V2); 4518 } 4519 4520 // Find the element from V2. 4521 unsigned HiIndex; 4522 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4523 int Val = PermMask[HiIndex]; 4524 if (Val < 0) 4525 continue; 4526 if (Val >= 4) 4527 break; 4528 } 4529 4530 Mask1[0] = PermMask[HiIndex]; 4531 Mask1[1] = -1; 4532 Mask1[2] = PermMask[HiIndex^1]; 4533 Mask1[3] = -1; 4534 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4535 4536 if (HiIndex >= 2) { 4537 Mask1[0] = PermMask[0]; 4538 Mask1[1] = PermMask[1]; 4539 Mask1[2] = HiIndex & 1 ? 6 : 4; 4540 Mask1[3] = HiIndex & 1 ? 4 : 6; 4541 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4542 } else { 4543 Mask1[0] = HiIndex & 1 ? 2 : 0; 4544 Mask1[1] = HiIndex & 1 ? 0 : 2; 4545 Mask1[2] = PermMask[2]; 4546 Mask1[3] = PermMask[3]; 4547 if (Mask1[2] >= 0) 4548 Mask1[2] += 4; 4549 if (Mask1[3] >= 0) 4550 Mask1[3] += 4; 4551 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4552 } 4553 } 4554 4555 // Break it into (shuffle shuffle_hi, shuffle_lo). 4556 Locs.clear(); 4557 SmallVector<int,8> LoMask(4U, -1); 4558 SmallVector<int,8> HiMask(4U, -1); 4559 4560 SmallVector<int,8> *MaskPtr = &LoMask; 4561 unsigned MaskIdx = 0; 4562 unsigned LoIdx = 0; 4563 unsigned HiIdx = 2; 4564 for (unsigned i = 0; i != 4; ++i) { 4565 if (i == 2) { 4566 MaskPtr = &HiMask; 4567 MaskIdx = 1; 4568 LoIdx = 0; 4569 HiIdx = 2; 4570 } 4571 int Idx = PermMask[i]; 4572 if (Idx < 0) { 4573 Locs[i] = std::make_pair(-1, -1); 4574 } else if (Idx < 4) { 4575 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4576 (*MaskPtr)[LoIdx] = Idx; 4577 LoIdx++; 4578 } else { 4579 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4580 (*MaskPtr)[HiIdx] = Idx; 4581 HiIdx++; 4582 } 4583 } 4584 4585 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4586 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4587 SmallVector<int, 8> MaskOps; 4588 for (unsigned i = 0; i != 4; ++i) { 4589 if (Locs[i].first == -1) { 4590 MaskOps.push_back(-1); 4591 } else { 4592 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4593 MaskOps.push_back(Idx); 4594 } 4595 } 4596 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4597} 4598 4599SDValue 4600X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4601 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4602 SDValue V1 = Op.getOperand(0); 4603 SDValue V2 = Op.getOperand(1); 4604 EVT VT = Op.getValueType(); 4605 DebugLoc dl = Op.getDebugLoc(); 4606 unsigned NumElems = VT.getVectorNumElements(); 4607 bool isMMX = VT.getSizeInBits() == 64; 4608 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4609 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4610 bool V1IsSplat = false; 4611 bool V2IsSplat = false; 4612 4613 if (isZeroShuffle(SVOp)) 4614 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4615 4616 // Promote splats to v4f32. 4617 if (SVOp->isSplat()) { 4618 if (isMMX || NumElems < 4) 4619 return Op; 4620 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4621 } 4622 4623 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4624 // do it! 4625 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4626 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4627 if (NewOp.getNode()) 4628 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4629 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4630 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4631 // FIXME: Figure out a cleaner way to do this. 4632 // Try to make use of movq to zero out the top part. 4633 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4634 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4635 if (NewOp.getNode()) { 4636 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4637 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4638 DAG, Subtarget, dl); 4639 } 4640 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4641 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4642 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4643 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4644 DAG, Subtarget, dl); 4645 } 4646 } 4647 4648 if (X86::isPSHUFDMask(SVOp)) 4649 return Op; 4650 4651 // Check if this can be converted into a logical shift. 4652 bool isLeft = false; 4653 unsigned ShAmt = 0; 4654 SDValue ShVal; 4655 bool isShift = getSubtarget()->hasSSE2() && 4656 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4657 if (isShift && ShVal.hasOneUse()) { 4658 // If the shifted value has multiple uses, it may be cheaper to use 4659 // v_set0 + movlhps or movhlps, etc. 4660 EVT EltVT = VT.getVectorElementType(); 4661 ShAmt *= EltVT.getSizeInBits(); 4662 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4663 } 4664 4665 if (X86::isMOVLMask(SVOp)) { 4666 if (V1IsUndef) 4667 return V2; 4668 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4669 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4670 if (!isMMX) 4671 return Op; 4672 } 4673 4674 // FIXME: fold these into legal mask. 4675 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4676 X86::isMOVSLDUPMask(SVOp) || 4677 X86::isMOVHLPSMask(SVOp) || 4678 X86::isMOVLHPSMask(SVOp) || 4679 X86::isMOVLPMask(SVOp))) 4680 return Op; 4681 4682 if (ShouldXformToMOVHLPS(SVOp) || 4683 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4684 return CommuteVectorShuffle(SVOp, DAG); 4685 4686 if (isShift) { 4687 // No better options. Use a vshl / vsrl. 4688 EVT EltVT = VT.getVectorElementType(); 4689 ShAmt *= EltVT.getSizeInBits(); 4690 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4691 } 4692 4693 bool Commuted = false; 4694 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4695 // 1,1,1,1 -> v8i16 though. 4696 V1IsSplat = isSplatVector(V1.getNode()); 4697 V2IsSplat = isSplatVector(V2.getNode()); 4698 4699 // Canonicalize the splat or undef, if present, to be on the RHS. 4700 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4701 Op = CommuteVectorShuffle(SVOp, DAG); 4702 SVOp = cast<ShuffleVectorSDNode>(Op); 4703 V1 = SVOp->getOperand(0); 4704 V2 = SVOp->getOperand(1); 4705 std::swap(V1IsSplat, V2IsSplat); 4706 std::swap(V1IsUndef, V2IsUndef); 4707 Commuted = true; 4708 } 4709 4710 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4711 // Shuffling low element of v1 into undef, just return v1. 4712 if (V2IsUndef) 4713 return V1; 4714 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4715 // the instruction selector will not match, so get a canonical MOVL with 4716 // swapped operands to undo the commute. 4717 return getMOVL(DAG, dl, VT, V2, V1); 4718 } 4719 4720 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4721 X86::isUNPCKH_v_undef_Mask(SVOp) || 4722 X86::isUNPCKLMask(SVOp) || 4723 X86::isUNPCKHMask(SVOp)) 4724 return Op; 4725 4726 if (V2IsSplat) { 4727 // Normalize mask so all entries that point to V2 points to its first 4728 // element then try to match unpck{h|l} again. If match, return a 4729 // new vector_shuffle with the corrected mask. 4730 SDValue NewMask = NormalizeMask(SVOp, DAG); 4731 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4732 if (NSVOp != SVOp) { 4733 if (X86::isUNPCKLMask(NSVOp, true)) { 4734 return NewMask; 4735 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4736 return NewMask; 4737 } 4738 } 4739 } 4740 4741 if (Commuted) { 4742 // Commute is back and try unpck* again. 4743 // FIXME: this seems wrong. 4744 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4745 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4746 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4747 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4748 X86::isUNPCKLMask(NewSVOp) || 4749 X86::isUNPCKHMask(NewSVOp)) 4750 return NewOp; 4751 } 4752 4753 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4754 4755 // Normalize the node to match x86 shuffle ops if needed 4756 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4757 return CommuteVectorShuffle(SVOp, DAG); 4758 4759 // Check for legal shuffle and return? 4760 SmallVector<int, 16> PermMask; 4761 SVOp->getMask(PermMask); 4762 if (isShuffleMaskLegal(PermMask, VT)) 4763 return Op; 4764 4765 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4766 if (VT == MVT::v8i16) { 4767 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4768 if (NewOp.getNode()) 4769 return NewOp; 4770 } 4771 4772 if (VT == MVT::v16i8) { 4773 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4774 if (NewOp.getNode()) 4775 return NewOp; 4776 } 4777 4778 // Handle all 4 wide cases with a number of shuffles except for MMX. 4779 if (NumElems == 4 && !isMMX) 4780 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4781 4782 return SDValue(); 4783} 4784 4785SDValue 4786X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4787 SelectionDAG &DAG) { 4788 EVT VT = Op.getValueType(); 4789 DebugLoc dl = Op.getDebugLoc(); 4790 if (VT.getSizeInBits() == 8) { 4791 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4792 Op.getOperand(0), Op.getOperand(1)); 4793 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4794 DAG.getValueType(VT)); 4795 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4796 } else if (VT.getSizeInBits() == 16) { 4797 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4798 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4799 if (Idx == 0) 4800 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4801 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4802 DAG.getNode(ISD::BIT_CONVERT, dl, 4803 MVT::v4i32, 4804 Op.getOperand(0)), 4805 Op.getOperand(1))); 4806 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4807 Op.getOperand(0), Op.getOperand(1)); 4808 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4809 DAG.getValueType(VT)); 4810 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4811 } else if (VT == MVT::f32) { 4812 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4813 // the result back to FR32 register. It's only worth matching if the 4814 // result has a single use which is a store or a bitcast to i32. And in 4815 // the case of a store, it's not worth it if the index is a constant 0, 4816 // because a MOVSSmr can be used instead, which is smaller and faster. 4817 if (!Op.hasOneUse()) 4818 return SDValue(); 4819 SDNode *User = *Op.getNode()->use_begin(); 4820 if ((User->getOpcode() != ISD::STORE || 4821 (isa<ConstantSDNode>(Op.getOperand(1)) && 4822 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4823 (User->getOpcode() != ISD::BIT_CONVERT || 4824 User->getValueType(0) != MVT::i32)) 4825 return SDValue(); 4826 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4827 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4828 Op.getOperand(0)), 4829 Op.getOperand(1)); 4830 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4831 } else if (VT == MVT::i32) { 4832 // ExtractPS works with constant index. 4833 if (isa<ConstantSDNode>(Op.getOperand(1))) 4834 return Op; 4835 } 4836 return SDValue(); 4837} 4838 4839 4840SDValue 4841X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4842 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4843 return SDValue(); 4844 4845 if (Subtarget->hasSSE41()) { 4846 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4847 if (Res.getNode()) 4848 return Res; 4849 } 4850 4851 EVT VT = Op.getValueType(); 4852 DebugLoc dl = Op.getDebugLoc(); 4853 // TODO: handle v16i8. 4854 if (VT.getSizeInBits() == 16) { 4855 SDValue Vec = Op.getOperand(0); 4856 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4857 if (Idx == 0) 4858 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4859 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4860 DAG.getNode(ISD::BIT_CONVERT, dl, 4861 MVT::v4i32, Vec), 4862 Op.getOperand(1))); 4863 // Transform it so it match pextrw which produces a 32-bit result. 4864 EVT EltVT = MVT::i32; 4865 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 4866 Op.getOperand(0), Op.getOperand(1)); 4867 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 4868 DAG.getValueType(VT)); 4869 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4870 } else if (VT.getSizeInBits() == 32) { 4871 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4872 if (Idx == 0) 4873 return Op; 4874 4875 // SHUFPS the element to the lowest double word, then movss. 4876 int Mask[4] = { Idx, -1, -1, -1 }; 4877 EVT VVT = Op.getOperand(0).getValueType(); 4878 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4879 DAG.getUNDEF(VVT), Mask); 4880 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4881 DAG.getIntPtrConstant(0)); 4882 } else if (VT.getSizeInBits() == 64) { 4883 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4884 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4885 // to match extract_elt for f64. 4886 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4887 if (Idx == 0) 4888 return Op; 4889 4890 // UNPCKHPD the element to the lowest double word, then movsd. 4891 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4892 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4893 int Mask[2] = { 1, -1 }; 4894 EVT VVT = Op.getOperand(0).getValueType(); 4895 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4896 DAG.getUNDEF(VVT), Mask); 4897 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4898 DAG.getIntPtrConstant(0)); 4899 } 4900 4901 return SDValue(); 4902} 4903 4904SDValue 4905X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4906 EVT VT = Op.getValueType(); 4907 EVT EltVT = VT.getVectorElementType(); 4908 DebugLoc dl = Op.getDebugLoc(); 4909 4910 SDValue N0 = Op.getOperand(0); 4911 SDValue N1 = Op.getOperand(1); 4912 SDValue N2 = Op.getOperand(2); 4913 4914 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 4915 isa<ConstantSDNode>(N2)) { 4916 unsigned Opc; 4917 if (VT == MVT::v8i16) 4918 Opc = X86ISD::PINSRW; 4919 else if (VT == MVT::v4i16) 4920 Opc = X86ISD::MMX_PINSRW; 4921 else if (VT == MVT::v16i8) 4922 Opc = X86ISD::PINSRB; 4923 else 4924 Opc = X86ISD::PINSRB; 4925 4926 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4927 // argument. 4928 if (N1.getValueType() != MVT::i32) 4929 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4930 if (N2.getValueType() != MVT::i32) 4931 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4932 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4933 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4934 // Bits [7:6] of the constant are the source select. This will always be 4935 // zero here. The DAG Combiner may combine an extract_elt index into these 4936 // bits. For example (insert (extract, 3), 2) could be matched by putting 4937 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4938 // Bits [5:4] of the constant are the destination select. This is the 4939 // value of the incoming immediate. 4940 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4941 // combine either bitwise AND or insert of float 0.0 to set these bits. 4942 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4943 // Create this as a scalar to vector.. 4944 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4945 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4946 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4947 // PINSR* works with constant index. 4948 return Op; 4949 } 4950 return SDValue(); 4951} 4952 4953SDValue 4954X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4955 EVT VT = Op.getValueType(); 4956 EVT EltVT = VT.getVectorElementType(); 4957 4958 if (Subtarget->hasSSE41()) 4959 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4960 4961 if (EltVT == MVT::i8) 4962 return SDValue(); 4963 4964 DebugLoc dl = Op.getDebugLoc(); 4965 SDValue N0 = Op.getOperand(0); 4966 SDValue N1 = Op.getOperand(1); 4967 SDValue N2 = Op.getOperand(2); 4968 4969 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4970 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4971 // as its second argument. 4972 if (N1.getValueType() != MVT::i32) 4973 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4974 if (N2.getValueType() != MVT::i32) 4975 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4976 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW, 4977 dl, VT, N0, N1, N2); 4978 } 4979 return SDValue(); 4980} 4981 4982SDValue 4983X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4984 DebugLoc dl = Op.getDebugLoc(); 4985 if (Op.getValueType() == MVT::v2f32) 4986 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4987 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4988 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4989 Op.getOperand(0)))); 4990 4991 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 4992 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 4993 4994 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4995 EVT VT = MVT::v2i32; 4996 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4997 default: break; 4998 case MVT::v16i8: 4999 case MVT::v8i16: 5000 VT = MVT::v4i32; 5001 break; 5002 } 5003 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 5004 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 5005} 5006 5007// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 5008// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 5009// one of the above mentioned nodes. It has to be wrapped because otherwise 5010// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 5011// be used to form addressing mode. These wrapped nodes will be selected 5012// into MOV32ri. 5013SDValue 5014X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 5015 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5016 5017 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5018 // global base reg. 5019 unsigned char OpFlag = 0; 5020 unsigned WrapperKind = X86ISD::Wrapper; 5021 CodeModel::Model M = getTargetMachine().getCodeModel(); 5022 5023 if (Subtarget->isPICStyleRIPRel() && 5024 (M == CodeModel::Small || M == CodeModel::Kernel)) 5025 WrapperKind = X86ISD::WrapperRIP; 5026 else if (Subtarget->isPICStyleGOT()) 5027 OpFlag = X86II::MO_GOTOFF; 5028 else if (Subtarget->isPICStyleStubPIC()) 5029 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5030 5031 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 5032 CP->getAlignment(), 5033 CP->getOffset(), OpFlag); 5034 DebugLoc DL = CP->getDebugLoc(); 5035 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5036 // With PIC, the address is actually $g + Offset. 5037 if (OpFlag) { 5038 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5039 DAG.getNode(X86ISD::GlobalBaseReg, 5040 DebugLoc::getUnknownLoc(), getPointerTy()), 5041 Result); 5042 } 5043 5044 return Result; 5045} 5046 5047SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 5048 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 5049 5050 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5051 // global base reg. 5052 unsigned char OpFlag = 0; 5053 unsigned WrapperKind = X86ISD::Wrapper; 5054 CodeModel::Model M = getTargetMachine().getCodeModel(); 5055 5056 if (Subtarget->isPICStyleRIPRel() && 5057 (M == CodeModel::Small || M == CodeModel::Kernel)) 5058 WrapperKind = X86ISD::WrapperRIP; 5059 else if (Subtarget->isPICStyleGOT()) 5060 OpFlag = X86II::MO_GOTOFF; 5061 else if (Subtarget->isPICStyleStubPIC()) 5062 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5063 5064 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 5065 OpFlag); 5066 DebugLoc DL = JT->getDebugLoc(); 5067 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5068 5069 // With PIC, the address is actually $g + Offset. 5070 if (OpFlag) { 5071 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5072 DAG.getNode(X86ISD::GlobalBaseReg, 5073 DebugLoc::getUnknownLoc(), getPointerTy()), 5074 Result); 5075 } 5076 5077 return Result; 5078} 5079 5080SDValue 5081X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 5082 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5083 5084 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5085 // global base reg. 5086 unsigned char OpFlag = 0; 5087 unsigned WrapperKind = X86ISD::Wrapper; 5088 CodeModel::Model M = getTargetMachine().getCodeModel(); 5089 5090 if (Subtarget->isPICStyleRIPRel() && 5091 (M == CodeModel::Small || M == CodeModel::Kernel)) 5092 WrapperKind = X86ISD::WrapperRIP; 5093 else if (Subtarget->isPICStyleGOT()) 5094 OpFlag = X86II::MO_GOTOFF; 5095 else if (Subtarget->isPICStyleStubPIC()) 5096 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5097 5098 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5099 5100 DebugLoc DL = Op.getDebugLoc(); 5101 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5102 5103 5104 // With PIC, the address is actually $g + Offset. 5105 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5106 !Subtarget->is64Bit()) { 5107 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5108 DAG.getNode(X86ISD::GlobalBaseReg, 5109 DebugLoc::getUnknownLoc(), 5110 getPointerTy()), 5111 Result); 5112 } 5113 5114 return Result; 5115} 5116 5117SDValue 5118X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 5119 // Create the TargetBlockAddressAddress node. 5120 unsigned char OpFlags = 5121 Subtarget->ClassifyBlockAddressReference(); 5122 CodeModel::Model M = getTargetMachine().getCodeModel(); 5123 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5124 DebugLoc dl = Op.getDebugLoc(); 5125 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5126 /*isTarget=*/true, OpFlags); 5127 5128 if (Subtarget->isPICStyleRIPRel() && 5129 (M == CodeModel::Small || M == CodeModel::Kernel)) 5130 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5131 else 5132 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5133 5134 // With PIC, the address is actually $g + Offset. 5135 if (isGlobalRelativeToPICBase(OpFlags)) { 5136 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5137 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5138 Result); 5139 } 5140 5141 return Result; 5142} 5143 5144SDValue 5145X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5146 int64_t Offset, 5147 SelectionDAG &DAG) const { 5148 // Create the TargetGlobalAddress node, folding in the constant 5149 // offset if it is legal. 5150 unsigned char OpFlags = 5151 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5152 CodeModel::Model M = getTargetMachine().getCodeModel(); 5153 SDValue Result; 5154 if (OpFlags == X86II::MO_NO_FLAG && 5155 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5156 // A direct static reference to a global. 5157 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 5158 Offset = 0; 5159 } else { 5160 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 5161 } 5162 5163 if (Subtarget->isPICStyleRIPRel() && 5164 (M == CodeModel::Small || M == CodeModel::Kernel)) 5165 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5166 else 5167 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5168 5169 // With PIC, the address is actually $g + Offset. 5170 if (isGlobalRelativeToPICBase(OpFlags)) { 5171 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5172 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5173 Result); 5174 } 5175 5176 // For globals that require a load from a stub to get the address, emit the 5177 // load. 5178 if (isGlobalStubReference(OpFlags)) 5179 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5180 PseudoSourceValue::getGOT(), 0, false, false, 0); 5181 5182 // If there was a non-zero offset that we didn't fold, create an explicit 5183 // addition for it. 5184 if (Offset != 0) 5185 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5186 DAG.getConstant(Offset, getPointerTy())); 5187 5188 return Result; 5189} 5190 5191SDValue 5192X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 5193 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5194 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5195 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5196} 5197 5198static SDValue 5199GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5200 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5201 unsigned char OperandFlags) { 5202 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5203 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5204 DebugLoc dl = GA->getDebugLoc(); 5205 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 5206 GA->getValueType(0), 5207 GA->getOffset(), 5208 OperandFlags); 5209 if (InFlag) { 5210 SDValue Ops[] = { Chain, TGA, *InFlag }; 5211 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5212 } else { 5213 SDValue Ops[] = { Chain, TGA }; 5214 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5215 } 5216 5217 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5218 MFI->setHasCalls(true); 5219 5220 SDValue Flag = Chain.getValue(1); 5221 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5222} 5223 5224// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5225static SDValue 5226LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5227 const EVT PtrVT) { 5228 SDValue InFlag; 5229 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5230 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5231 DAG.getNode(X86ISD::GlobalBaseReg, 5232 DebugLoc::getUnknownLoc(), 5233 PtrVT), InFlag); 5234 InFlag = Chain.getValue(1); 5235 5236 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5237} 5238 5239// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5240static SDValue 5241LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5242 const EVT PtrVT) { 5243 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5244 X86::RAX, X86II::MO_TLSGD); 5245} 5246 5247// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5248// "local exec" model. 5249static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5250 const EVT PtrVT, TLSModel::Model model, 5251 bool is64Bit) { 5252 DebugLoc dl = GA->getDebugLoc(); 5253 // Get the Thread Pointer 5254 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5255 DebugLoc::getUnknownLoc(), PtrVT, 5256 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5257 MVT::i32)); 5258 5259 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5260 NULL, 0, false, false, 0); 5261 5262 unsigned char OperandFlags = 0; 5263 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5264 // initialexec. 5265 unsigned WrapperKind = X86ISD::Wrapper; 5266 if (model == TLSModel::LocalExec) { 5267 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5268 } else if (is64Bit) { 5269 assert(model == TLSModel::InitialExec); 5270 OperandFlags = X86II::MO_GOTTPOFF; 5271 WrapperKind = X86ISD::WrapperRIP; 5272 } else { 5273 assert(model == TLSModel::InitialExec); 5274 OperandFlags = X86II::MO_INDNTPOFF; 5275 } 5276 5277 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5278 // exec) 5279 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 5280 GA->getOffset(), OperandFlags); 5281 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5282 5283 if (model == TLSModel::InitialExec) 5284 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5285 PseudoSourceValue::getGOT(), 0, false, false, 0); 5286 5287 // The address of the thread local variable is the add of the thread 5288 // pointer with the offset of the variable. 5289 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5290} 5291 5292SDValue 5293X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 5294 // TODO: implement the "local dynamic" model 5295 // TODO: implement the "initial exec"model for pic executables 5296 assert(Subtarget->isTargetELF() && 5297 "TLS not implemented for non-ELF targets"); 5298 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5299 const GlobalValue *GV = GA->getGlobal(); 5300 5301 // If GV is an alias then use the aliasee for determining 5302 // thread-localness. 5303 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5304 GV = GA->resolveAliasedGlobal(false); 5305 5306 TLSModel::Model model = getTLSModel(GV, 5307 getTargetMachine().getRelocationModel()); 5308 5309 switch (model) { 5310 case TLSModel::GeneralDynamic: 5311 case TLSModel::LocalDynamic: // not implemented 5312 if (Subtarget->is64Bit()) 5313 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5314 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5315 5316 case TLSModel::InitialExec: 5317 case TLSModel::LocalExec: 5318 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5319 Subtarget->is64Bit()); 5320 } 5321 5322 llvm_unreachable("Unreachable"); 5323 return SDValue(); 5324} 5325 5326 5327/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5328/// take a 2 x i32 value to shift plus a shift amount. 5329SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 5330 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5331 EVT VT = Op.getValueType(); 5332 unsigned VTBits = VT.getSizeInBits(); 5333 DebugLoc dl = Op.getDebugLoc(); 5334 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5335 SDValue ShOpLo = Op.getOperand(0); 5336 SDValue ShOpHi = Op.getOperand(1); 5337 SDValue ShAmt = Op.getOperand(2); 5338 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5339 DAG.getConstant(VTBits - 1, MVT::i8)) 5340 : DAG.getConstant(0, VT); 5341 5342 SDValue Tmp2, Tmp3; 5343 if (Op.getOpcode() == ISD::SHL_PARTS) { 5344 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5345 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5346 } else { 5347 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5348 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5349 } 5350 5351 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5352 DAG.getConstant(VTBits, MVT::i8)); 5353 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5354 AndNode, DAG.getConstant(0, MVT::i8)); 5355 5356 SDValue Hi, Lo; 5357 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5358 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5359 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5360 5361 if (Op.getOpcode() == ISD::SHL_PARTS) { 5362 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5363 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5364 } else { 5365 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5366 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5367 } 5368 5369 SDValue Ops[2] = { Lo, Hi }; 5370 return DAG.getMergeValues(Ops, 2, dl); 5371} 5372 5373SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5374 EVT SrcVT = Op.getOperand(0).getValueType(); 5375 5376 if (SrcVT.isVector()) { 5377 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5378 return Op; 5379 } 5380 return SDValue(); 5381 } 5382 5383 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5384 "Unknown SINT_TO_FP to lower!"); 5385 5386 // These are really Legal; return the operand so the caller accepts it as 5387 // Legal. 5388 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5389 return Op; 5390 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5391 Subtarget->is64Bit()) { 5392 return Op; 5393 } 5394 5395 DebugLoc dl = Op.getDebugLoc(); 5396 unsigned Size = SrcVT.getSizeInBits()/8; 5397 MachineFunction &MF = DAG.getMachineFunction(); 5398 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5399 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5400 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5401 StackSlot, 5402 PseudoSourceValue::getFixedStack(SSFI), 0, 5403 false, false, 0); 5404 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5405} 5406 5407SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5408 SDValue StackSlot, 5409 SelectionDAG &DAG) { 5410 // Build the FILD 5411 DebugLoc dl = Op.getDebugLoc(); 5412 SDVTList Tys; 5413 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5414 if (useSSE) 5415 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5416 else 5417 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5418 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5419 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5420 Tys, Ops, array_lengthof(Ops)); 5421 5422 if (useSSE) { 5423 Chain = Result.getValue(1); 5424 SDValue InFlag = Result.getValue(2); 5425 5426 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5427 // shouldn't be necessary except that RFP cannot be live across 5428 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5429 MachineFunction &MF = DAG.getMachineFunction(); 5430 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5431 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5432 Tys = DAG.getVTList(MVT::Other); 5433 SDValue Ops[] = { 5434 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5435 }; 5436 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5437 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5438 PseudoSourceValue::getFixedStack(SSFI), 0, 5439 false, false, 0); 5440 } 5441 5442 return Result; 5443} 5444 5445// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5446SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 5447 // This algorithm is not obvious. Here it is in C code, more or less: 5448 /* 5449 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5450 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5451 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5452 5453 // Copy ints to xmm registers. 5454 __m128i xh = _mm_cvtsi32_si128( hi ); 5455 __m128i xl = _mm_cvtsi32_si128( lo ); 5456 5457 // Combine into low half of a single xmm register. 5458 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5459 __m128d d; 5460 double sd; 5461 5462 // Merge in appropriate exponents to give the integer bits the right 5463 // magnitude. 5464 x = _mm_unpacklo_epi32( x, exp ); 5465 5466 // Subtract away the biases to deal with the IEEE-754 double precision 5467 // implicit 1. 5468 d = _mm_sub_pd( (__m128d) x, bias ); 5469 5470 // All conversions up to here are exact. The correctly rounded result is 5471 // calculated using the current rounding mode using the following 5472 // horizontal add. 5473 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5474 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5475 // store doesn't really need to be here (except 5476 // maybe to zero the other double) 5477 return sd; 5478 } 5479 */ 5480 5481 DebugLoc dl = Op.getDebugLoc(); 5482 LLVMContext *Context = DAG.getContext(); 5483 5484 // Build some magic constants. 5485 std::vector<Constant*> CV0; 5486 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5487 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5488 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5489 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5490 Constant *C0 = ConstantVector::get(CV0); 5491 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5492 5493 std::vector<Constant*> CV1; 5494 CV1.push_back( 5495 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5496 CV1.push_back( 5497 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 5498 Constant *C1 = ConstantVector::get(CV1); 5499 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 5500 5501 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5502 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5503 Op.getOperand(0), 5504 DAG.getIntPtrConstant(1))); 5505 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5506 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5507 Op.getOperand(0), 5508 DAG.getIntPtrConstant(0))); 5509 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 5510 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5511 PseudoSourceValue::getConstantPool(), 0, 5512 false, false, 16); 5513 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 5514 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5515 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5516 PseudoSourceValue::getConstantPool(), 0, 5517 false, false, 16); 5518 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5519 5520 // Add the halves; easiest way is to swap them into another reg first. 5521 int ShufMask[2] = { 1, -1 }; 5522 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 5523 DAG.getUNDEF(MVT::v2f64), ShufMask); 5524 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5525 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5526 DAG.getIntPtrConstant(0)); 5527} 5528 5529// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5530SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5531 DebugLoc dl = Op.getDebugLoc(); 5532 // FP constant to bias correct the final result. 5533 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5534 MVT::f64); 5535 5536 // Load the 32-bit value into an XMM register. 5537 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5538 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5539 Op.getOperand(0), 5540 DAG.getIntPtrConstant(0))); 5541 5542 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5543 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5544 DAG.getIntPtrConstant(0)); 5545 5546 // Or the load with the bias. 5547 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5548 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5549 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5550 MVT::v2f64, Load)), 5551 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5552 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5553 MVT::v2f64, Bias))); 5554 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5555 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5556 DAG.getIntPtrConstant(0)); 5557 5558 // Subtract the bias. 5559 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5560 5561 // Handle final rounding. 5562 EVT DestVT = Op.getValueType(); 5563 5564 if (DestVT.bitsLT(MVT::f64)) { 5565 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5566 DAG.getIntPtrConstant(0)); 5567 } else if (DestVT.bitsGT(MVT::f64)) { 5568 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5569 } 5570 5571 // Handle final rounding. 5572 return Sub; 5573} 5574 5575SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5576 SDValue N0 = Op.getOperand(0); 5577 DebugLoc dl = Op.getDebugLoc(); 5578 5579 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5580 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5581 // the optimization here. 5582 if (DAG.SignBitIsZero(N0)) 5583 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5584 5585 EVT SrcVT = N0.getValueType(); 5586 if (SrcVT == MVT::i64) { 5587 // We only handle SSE2 f64 target here; caller can expand the rest. 5588 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5589 return SDValue(); 5590 5591 return LowerUINT_TO_FP_i64(Op, DAG); 5592 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5593 return LowerUINT_TO_FP_i32(Op, DAG); 5594 } 5595 5596 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5597 5598 // Make a 64-bit buffer, and use it to build an FILD. 5599 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5600 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5601 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5602 getPointerTy(), StackSlot, WordOff); 5603 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5604 StackSlot, NULL, 0, false, false, 0); 5605 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5606 OffsetSlot, NULL, 0, false, false, 0); 5607 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5608} 5609 5610std::pair<SDValue,SDValue> X86TargetLowering:: 5611FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5612 DebugLoc dl = Op.getDebugLoc(); 5613 5614 EVT DstTy = Op.getValueType(); 5615 5616 if (!IsSigned) { 5617 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5618 DstTy = MVT::i64; 5619 } 5620 5621 assert(DstTy.getSimpleVT() <= MVT::i64 && 5622 DstTy.getSimpleVT() >= MVT::i16 && 5623 "Unknown FP_TO_SINT to lower!"); 5624 5625 // These are really Legal. 5626 if (DstTy == MVT::i32 && 5627 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5628 return std::make_pair(SDValue(), SDValue()); 5629 if (Subtarget->is64Bit() && 5630 DstTy == MVT::i64 && 5631 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5632 return std::make_pair(SDValue(), SDValue()); 5633 5634 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5635 // stack slot. 5636 MachineFunction &MF = DAG.getMachineFunction(); 5637 unsigned MemSize = DstTy.getSizeInBits()/8; 5638 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5639 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5640 5641 unsigned Opc; 5642 switch (DstTy.getSimpleVT().SimpleTy) { 5643 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5644 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5645 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5646 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5647 } 5648 5649 SDValue Chain = DAG.getEntryNode(); 5650 SDValue Value = Op.getOperand(0); 5651 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5652 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5653 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5654 PseudoSourceValue::getFixedStack(SSFI), 0, 5655 false, false, 0); 5656 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5657 SDValue Ops[] = { 5658 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5659 }; 5660 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5661 Chain = Value.getValue(1); 5662 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5663 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5664 } 5665 5666 // Build the FP_TO_INT*_IN_MEM 5667 SDValue Ops[] = { Chain, Value, StackSlot }; 5668 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5669 5670 return std::make_pair(FIST, StackSlot); 5671} 5672 5673SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5674 if (Op.getValueType().isVector()) { 5675 if (Op.getValueType() == MVT::v2i32 && 5676 Op.getOperand(0).getValueType() == MVT::v2f64) { 5677 return Op; 5678 } 5679 return SDValue(); 5680 } 5681 5682 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5683 SDValue FIST = Vals.first, StackSlot = Vals.second; 5684 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5685 if (FIST.getNode() == 0) return Op; 5686 5687 // Load the result. 5688 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5689 FIST, StackSlot, NULL, 0, false, false, 0); 5690} 5691 5692SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5693 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5694 SDValue FIST = Vals.first, StackSlot = Vals.second; 5695 assert(FIST.getNode() && "Unexpected failure"); 5696 5697 // Load the result. 5698 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5699 FIST, StackSlot, NULL, 0, false, false, 0); 5700} 5701 5702SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5703 LLVMContext *Context = DAG.getContext(); 5704 DebugLoc dl = Op.getDebugLoc(); 5705 EVT VT = Op.getValueType(); 5706 EVT EltVT = VT; 5707 if (VT.isVector()) 5708 EltVT = VT.getVectorElementType(); 5709 std::vector<Constant*> CV; 5710 if (EltVT == MVT::f64) { 5711 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5712 CV.push_back(C); 5713 CV.push_back(C); 5714 } else { 5715 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5716 CV.push_back(C); 5717 CV.push_back(C); 5718 CV.push_back(C); 5719 CV.push_back(C); 5720 } 5721 Constant *C = ConstantVector::get(CV); 5722 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5723 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5724 PseudoSourceValue::getConstantPool(), 0, 5725 false, false, 16); 5726 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5727} 5728 5729SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5730 LLVMContext *Context = DAG.getContext(); 5731 DebugLoc dl = Op.getDebugLoc(); 5732 EVT VT = Op.getValueType(); 5733 EVT EltVT = VT; 5734 if (VT.isVector()) 5735 EltVT = VT.getVectorElementType(); 5736 std::vector<Constant*> CV; 5737 if (EltVT == MVT::f64) { 5738 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5739 CV.push_back(C); 5740 CV.push_back(C); 5741 } else { 5742 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5743 CV.push_back(C); 5744 CV.push_back(C); 5745 CV.push_back(C); 5746 CV.push_back(C); 5747 } 5748 Constant *C = ConstantVector::get(CV); 5749 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5750 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5751 PseudoSourceValue::getConstantPool(), 0, 5752 false, false, 16); 5753 if (VT.isVector()) { 5754 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5755 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5756 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5757 Op.getOperand(0)), 5758 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5759 } else { 5760 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5761 } 5762} 5763 5764SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5765 LLVMContext *Context = DAG.getContext(); 5766 SDValue Op0 = Op.getOperand(0); 5767 SDValue Op1 = Op.getOperand(1); 5768 DebugLoc dl = Op.getDebugLoc(); 5769 EVT VT = Op.getValueType(); 5770 EVT SrcVT = Op1.getValueType(); 5771 5772 // If second operand is smaller, extend it first. 5773 if (SrcVT.bitsLT(VT)) { 5774 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5775 SrcVT = VT; 5776 } 5777 // And if it is bigger, shrink it first. 5778 if (SrcVT.bitsGT(VT)) { 5779 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5780 SrcVT = VT; 5781 } 5782 5783 // At this point the operands and the result should have the same 5784 // type, and that won't be f80 since that is not custom lowered. 5785 5786 // First get the sign bit of second operand. 5787 std::vector<Constant*> CV; 5788 if (SrcVT == MVT::f64) { 5789 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5790 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5791 } else { 5792 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5793 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5794 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5795 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5796 } 5797 Constant *C = ConstantVector::get(CV); 5798 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5799 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5800 PseudoSourceValue::getConstantPool(), 0, 5801 false, false, 16); 5802 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5803 5804 // Shift sign bit right or left if the two operands have different types. 5805 if (SrcVT.bitsGT(VT)) { 5806 // Op0 is MVT::f32, Op1 is MVT::f64. 5807 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5808 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5809 DAG.getConstant(32, MVT::i32)); 5810 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5811 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5812 DAG.getIntPtrConstant(0)); 5813 } 5814 5815 // Clear first operand sign bit. 5816 CV.clear(); 5817 if (VT == MVT::f64) { 5818 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5819 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5820 } else { 5821 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5822 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5823 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5824 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5825 } 5826 C = ConstantVector::get(CV); 5827 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5828 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5829 PseudoSourceValue::getConstantPool(), 0, 5830 false, false, 16); 5831 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5832 5833 // Or the value with the sign bit. 5834 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5835} 5836 5837/// Emit nodes that will be selected as "test Op0,Op0", or something 5838/// equivalent. 5839SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5840 SelectionDAG &DAG) { 5841 DebugLoc dl = Op.getDebugLoc(); 5842 5843 // CF and OF aren't always set the way we want. Determine which 5844 // of these we need. 5845 bool NeedCF = false; 5846 bool NeedOF = false; 5847 switch (X86CC) { 5848 case X86::COND_A: case X86::COND_AE: 5849 case X86::COND_B: case X86::COND_BE: 5850 NeedCF = true; 5851 break; 5852 case X86::COND_G: case X86::COND_GE: 5853 case X86::COND_L: case X86::COND_LE: 5854 case X86::COND_O: case X86::COND_NO: 5855 NeedOF = true; 5856 break; 5857 default: break; 5858 } 5859 5860 // See if we can use the EFLAGS value from the operand instead of 5861 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5862 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5863 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5864 unsigned Opcode = 0; 5865 unsigned NumOperands = 0; 5866 switch (Op.getNode()->getOpcode()) { 5867 case ISD::ADD: 5868 // Due to an isel shortcoming, be conservative if this add is likely to 5869 // be selected as part of a load-modify-store instruction. When the root 5870 // node in a match is a store, isel doesn't know how to remap non-chain 5871 // non-flag uses of other nodes in the match, such as the ADD in this 5872 // case. This leads to the ADD being left around and reselected, with 5873 // the result being two adds in the output. 5874 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5875 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5876 if (UI->getOpcode() == ISD::STORE) 5877 goto default_case; 5878 if (ConstantSDNode *C = 5879 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5880 // An add of one will be selected as an INC. 5881 if (C->getAPIntValue() == 1) { 5882 Opcode = X86ISD::INC; 5883 NumOperands = 1; 5884 break; 5885 } 5886 // An add of negative one (subtract of one) will be selected as a DEC. 5887 if (C->getAPIntValue().isAllOnesValue()) { 5888 Opcode = X86ISD::DEC; 5889 NumOperands = 1; 5890 break; 5891 } 5892 } 5893 // Otherwise use a regular EFLAGS-setting add. 5894 Opcode = X86ISD::ADD; 5895 NumOperands = 2; 5896 break; 5897 case ISD::AND: { 5898 // If the primary and result isn't used, don't bother using X86ISD::AND, 5899 // because a TEST instruction will be better. 5900 bool NonFlagUse = false; 5901 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5902 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 5903 SDNode *User = *UI; 5904 unsigned UOpNo = UI.getOperandNo(); 5905 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 5906 // Look pass truncate. 5907 UOpNo = User->use_begin().getOperandNo(); 5908 User = *User->use_begin(); 5909 } 5910 if (User->getOpcode() != ISD::BRCOND && 5911 User->getOpcode() != ISD::SETCC && 5912 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 5913 NonFlagUse = true; 5914 break; 5915 } 5916 } 5917 if (!NonFlagUse) 5918 break; 5919 } 5920 // FALL THROUGH 5921 case ISD::SUB: 5922 case ISD::OR: 5923 case ISD::XOR: 5924 // Due to the ISEL shortcoming noted above, be conservative if this op is 5925 // likely to be selected as part of a load-modify-store instruction. 5926 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5927 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5928 if (UI->getOpcode() == ISD::STORE) 5929 goto default_case; 5930 // Otherwise use a regular EFLAGS-setting instruction. 5931 switch (Op.getNode()->getOpcode()) { 5932 case ISD::SUB: Opcode = X86ISD::SUB; break; 5933 case ISD::OR: Opcode = X86ISD::OR; break; 5934 case ISD::XOR: Opcode = X86ISD::XOR; break; 5935 case ISD::AND: Opcode = X86ISD::AND; break; 5936 default: llvm_unreachable("unexpected operator!"); 5937 } 5938 NumOperands = 2; 5939 break; 5940 case X86ISD::ADD: 5941 case X86ISD::SUB: 5942 case X86ISD::INC: 5943 case X86ISD::DEC: 5944 case X86ISD::OR: 5945 case X86ISD::XOR: 5946 case X86ISD::AND: 5947 return SDValue(Op.getNode(), 1); 5948 default: 5949 default_case: 5950 break; 5951 } 5952 if (Opcode != 0) { 5953 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5954 SmallVector<SDValue, 4> Ops; 5955 for (unsigned i = 0; i != NumOperands; ++i) 5956 Ops.push_back(Op.getOperand(i)); 5957 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5958 DAG.ReplaceAllUsesWith(Op, New); 5959 return SDValue(New.getNode(), 1); 5960 } 5961 } 5962 5963 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5964 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5965 DAG.getConstant(0, Op.getValueType())); 5966} 5967 5968/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5969/// equivalent. 5970SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5971 SelectionDAG &DAG) { 5972 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5973 if (C->getAPIntValue() == 0) 5974 return EmitTest(Op0, X86CC, DAG); 5975 5976 DebugLoc dl = Op0.getDebugLoc(); 5977 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5978} 5979 5980/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 5981/// if it's possible. 5982static SDValue LowerToBT(SDValue And, ISD::CondCode CC, 5983 DebugLoc dl, SelectionDAG &DAG) { 5984 SDValue Op0 = And.getOperand(0); 5985 SDValue Op1 = And.getOperand(1); 5986 if (Op0.getOpcode() == ISD::TRUNCATE) 5987 Op0 = Op0.getOperand(0); 5988 if (Op1.getOpcode() == ISD::TRUNCATE) 5989 Op1 = Op1.getOperand(0); 5990 5991 SDValue LHS, RHS; 5992 if (Op1.getOpcode() == ISD::SHL) { 5993 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0))) 5994 if (And10C->getZExtValue() == 1) { 5995 LHS = Op0; 5996 RHS = Op1.getOperand(1); 5997 } 5998 } else if (Op0.getOpcode() == ISD::SHL) { 5999 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 6000 if (And00C->getZExtValue() == 1) { 6001 LHS = Op1; 6002 RHS = Op0.getOperand(1); 6003 } 6004 } else if (Op1.getOpcode() == ISD::Constant) { 6005 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 6006 SDValue AndLHS = Op0; 6007 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 6008 LHS = AndLHS.getOperand(0); 6009 RHS = AndLHS.getOperand(1); 6010 } 6011 } 6012 6013 if (LHS.getNode()) { 6014 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 6015 // instruction. Since the shift amount is in-range-or-undefined, we know 6016 // that doing a bittest on the i16 value is ok. We extend to i32 because 6017 // the encoding for the i16 version is larger than the i32 version. 6018 if (LHS.getValueType() == MVT::i8) 6019 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 6020 6021 // If the operand types disagree, extend the shift amount to match. Since 6022 // BT ignores high bits (like shifts) we can use anyextend. 6023 if (LHS.getValueType() != RHS.getValueType()) 6024 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 6025 6026 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 6027 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 6028 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6029 DAG.getConstant(Cond, MVT::i8), BT); 6030 } 6031 6032 return SDValue(); 6033} 6034 6035SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 6036 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 6037 SDValue Op0 = Op.getOperand(0); 6038 SDValue Op1 = Op.getOperand(1); 6039 DebugLoc dl = Op.getDebugLoc(); 6040 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6041 6042 // Optimize to BT if possible. 6043 // Lower (X & (1 << N)) == 0 to BT(X, N). 6044 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 6045 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 6046 if (Op0.getOpcode() == ISD::AND && 6047 Op0.hasOneUse() && 6048 Op1.getOpcode() == ISD::Constant && 6049 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 6050 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6051 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 6052 if (NewSetCC.getNode()) 6053 return NewSetCC; 6054 } 6055 6056 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 6057 if (Op0.getOpcode() == X86ISD::SETCC && 6058 Op1.getOpcode() == ISD::Constant && 6059 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 6060 cast<ConstantSDNode>(Op1)->isNullValue()) && 6061 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6062 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 6063 bool Invert = (CC == ISD::SETNE) ^ 6064 cast<ConstantSDNode>(Op1)->isNullValue(); 6065 if (Invert) 6066 CCode = X86::GetOppositeBranchCondition(CCode); 6067 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6068 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 6069 } 6070 6071 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6072 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 6073 if (X86CC == X86::COND_INVALID) 6074 return SDValue(); 6075 6076 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 6077 6078 // Use sbb x, x to materialize carry bit into a GPR. 6079 if (X86CC == X86::COND_B) 6080 return DAG.getNode(ISD::AND, dl, MVT::i8, 6081 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 6082 DAG.getConstant(X86CC, MVT::i8), Cond), 6083 DAG.getConstant(1, MVT::i8)); 6084 6085 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6086 DAG.getConstant(X86CC, MVT::i8), Cond); 6087} 6088 6089SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 6090 SDValue Cond; 6091 SDValue Op0 = Op.getOperand(0); 6092 SDValue Op1 = Op.getOperand(1); 6093 SDValue CC = Op.getOperand(2); 6094 EVT VT = Op.getValueType(); 6095 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 6096 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6097 DebugLoc dl = Op.getDebugLoc(); 6098 6099 if (isFP) { 6100 unsigned SSECC = 8; 6101 EVT VT0 = Op0.getValueType(); 6102 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 6103 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 6104 bool Swap = false; 6105 6106 switch (SetCCOpcode) { 6107 default: break; 6108 case ISD::SETOEQ: 6109 case ISD::SETEQ: SSECC = 0; break; 6110 case ISD::SETOGT: 6111 case ISD::SETGT: Swap = true; // Fallthrough 6112 case ISD::SETLT: 6113 case ISD::SETOLT: SSECC = 1; break; 6114 case ISD::SETOGE: 6115 case ISD::SETGE: Swap = true; // Fallthrough 6116 case ISD::SETLE: 6117 case ISD::SETOLE: SSECC = 2; break; 6118 case ISD::SETUO: SSECC = 3; break; 6119 case ISD::SETUNE: 6120 case ISD::SETNE: SSECC = 4; break; 6121 case ISD::SETULE: Swap = true; 6122 case ISD::SETUGE: SSECC = 5; break; 6123 case ISD::SETULT: Swap = true; 6124 case ISD::SETUGT: SSECC = 6; break; 6125 case ISD::SETO: SSECC = 7; break; 6126 } 6127 if (Swap) 6128 std::swap(Op0, Op1); 6129 6130 // In the two special cases we can't handle, emit two comparisons. 6131 if (SSECC == 8) { 6132 if (SetCCOpcode == ISD::SETUEQ) { 6133 SDValue UNORD, EQ; 6134 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6135 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6136 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6137 } 6138 else if (SetCCOpcode == ISD::SETONE) { 6139 SDValue ORD, NEQ; 6140 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6141 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6142 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6143 } 6144 llvm_unreachable("Illegal FP comparison"); 6145 } 6146 // Handle all other FP comparisons here. 6147 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6148 } 6149 6150 // We are handling one of the integer comparisons here. Since SSE only has 6151 // GT and EQ comparisons for integer, swapping operands and multiple 6152 // operations may be required for some comparisons. 6153 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6154 bool Swap = false, Invert = false, FlipSigns = false; 6155 6156 switch (VT.getSimpleVT().SimpleTy) { 6157 default: break; 6158 case MVT::v8i8: 6159 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6160 case MVT::v4i16: 6161 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6162 case MVT::v2i32: 6163 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6164 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6165 } 6166 6167 switch (SetCCOpcode) { 6168 default: break; 6169 case ISD::SETNE: Invert = true; 6170 case ISD::SETEQ: Opc = EQOpc; break; 6171 case ISD::SETLT: Swap = true; 6172 case ISD::SETGT: Opc = GTOpc; break; 6173 case ISD::SETGE: Swap = true; 6174 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6175 case ISD::SETULT: Swap = true; 6176 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6177 case ISD::SETUGE: Swap = true; 6178 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6179 } 6180 if (Swap) 6181 std::swap(Op0, Op1); 6182 6183 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6184 // bits of the inputs before performing those operations. 6185 if (FlipSigns) { 6186 EVT EltVT = VT.getVectorElementType(); 6187 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6188 EltVT); 6189 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6190 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6191 SignBits.size()); 6192 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6193 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6194 } 6195 6196 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6197 6198 // If the logical-not of the result is required, perform that now. 6199 if (Invert) 6200 Result = DAG.getNOT(dl, Result, VT); 6201 6202 return Result; 6203} 6204 6205// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6206static bool isX86LogicalCmp(SDValue Op) { 6207 unsigned Opc = Op.getNode()->getOpcode(); 6208 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6209 return true; 6210 if (Op.getResNo() == 1 && 6211 (Opc == X86ISD::ADD || 6212 Opc == X86ISD::SUB || 6213 Opc == X86ISD::SMUL || 6214 Opc == X86ISD::UMUL || 6215 Opc == X86ISD::INC || 6216 Opc == X86ISD::DEC || 6217 Opc == X86ISD::OR || 6218 Opc == X86ISD::XOR || 6219 Opc == X86ISD::AND)) 6220 return true; 6221 6222 return false; 6223} 6224 6225SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 6226 bool addTest = true; 6227 SDValue Cond = Op.getOperand(0); 6228 DebugLoc dl = Op.getDebugLoc(); 6229 SDValue CC; 6230 6231 if (Cond.getOpcode() == ISD::SETCC) { 6232 SDValue NewCond = LowerSETCC(Cond, DAG); 6233 if (NewCond.getNode()) 6234 Cond = NewCond; 6235 } 6236 6237 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6238 SDValue Op1 = Op.getOperand(1); 6239 SDValue Op2 = Op.getOperand(2); 6240 if (Cond.getOpcode() == X86ISD::SETCC && 6241 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6242 SDValue Cmp = Cond.getOperand(1); 6243 if (Cmp.getOpcode() == X86ISD::CMP) { 6244 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6245 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6246 ConstantSDNode *RHSC = 6247 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6248 if (N1C && N1C->isAllOnesValue() && 6249 N2C && N2C->isNullValue() && 6250 RHSC && RHSC->isNullValue()) { 6251 SDValue CmpOp0 = Cmp.getOperand(0); 6252 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6253 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6254 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6255 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6256 } 6257 } 6258 } 6259 6260 // Look pass (and (setcc_carry (cmp ...)), 1). 6261 if (Cond.getOpcode() == ISD::AND && 6262 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6263 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6264 if (C && C->getAPIntValue() == 1) 6265 Cond = Cond.getOperand(0); 6266 } 6267 6268 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6269 // setting operand in place of the X86ISD::SETCC. 6270 if (Cond.getOpcode() == X86ISD::SETCC || 6271 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6272 CC = Cond.getOperand(0); 6273 6274 SDValue Cmp = Cond.getOperand(1); 6275 unsigned Opc = Cmp.getOpcode(); 6276 EVT VT = Op.getValueType(); 6277 6278 bool IllegalFPCMov = false; 6279 if (VT.isFloatingPoint() && !VT.isVector() && 6280 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6281 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6282 6283 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6284 Opc == X86ISD::BT) { // FIXME 6285 Cond = Cmp; 6286 addTest = false; 6287 } 6288 } 6289 6290 if (addTest) { 6291 // Look pass the truncate. 6292 if (Cond.getOpcode() == ISD::TRUNCATE) 6293 Cond = Cond.getOperand(0); 6294 6295 // We know the result of AND is compared against zero. Try to match 6296 // it to BT. 6297 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6298 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6299 if (NewSetCC.getNode()) { 6300 CC = NewSetCC.getOperand(0); 6301 Cond = NewSetCC.getOperand(1); 6302 addTest = false; 6303 } 6304 } 6305 } 6306 6307 if (addTest) { 6308 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6309 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6310 } 6311 6312 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6313 // condition is true. 6314 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6315 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6316 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6317} 6318 6319// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6320// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6321// from the AND / OR. 6322static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6323 Opc = Op.getOpcode(); 6324 if (Opc != ISD::OR && Opc != ISD::AND) 6325 return false; 6326 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6327 Op.getOperand(0).hasOneUse() && 6328 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6329 Op.getOperand(1).hasOneUse()); 6330} 6331 6332// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6333// 1 and that the SETCC node has a single use. 6334static bool isXor1OfSetCC(SDValue Op) { 6335 if (Op.getOpcode() != ISD::XOR) 6336 return false; 6337 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6338 if (N1C && N1C->getAPIntValue() == 1) { 6339 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6340 Op.getOperand(0).hasOneUse(); 6341 } 6342 return false; 6343} 6344 6345SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 6346 bool addTest = true; 6347 SDValue Chain = Op.getOperand(0); 6348 SDValue Cond = Op.getOperand(1); 6349 SDValue Dest = Op.getOperand(2); 6350 DebugLoc dl = Op.getDebugLoc(); 6351 SDValue CC; 6352 6353 if (Cond.getOpcode() == ISD::SETCC) { 6354 SDValue NewCond = LowerSETCC(Cond, DAG); 6355 if (NewCond.getNode()) 6356 Cond = NewCond; 6357 } 6358#if 0 6359 // FIXME: LowerXALUO doesn't handle these!! 6360 else if (Cond.getOpcode() == X86ISD::ADD || 6361 Cond.getOpcode() == X86ISD::SUB || 6362 Cond.getOpcode() == X86ISD::SMUL || 6363 Cond.getOpcode() == X86ISD::UMUL) 6364 Cond = LowerXALUO(Cond, DAG); 6365#endif 6366 6367 // Look pass (and (setcc_carry (cmp ...)), 1). 6368 if (Cond.getOpcode() == ISD::AND && 6369 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6370 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6371 if (C && C->getAPIntValue() == 1) 6372 Cond = Cond.getOperand(0); 6373 } 6374 6375 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6376 // setting operand in place of the X86ISD::SETCC. 6377 if (Cond.getOpcode() == X86ISD::SETCC || 6378 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6379 CC = Cond.getOperand(0); 6380 6381 SDValue Cmp = Cond.getOperand(1); 6382 unsigned Opc = Cmp.getOpcode(); 6383 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6384 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6385 Cond = Cmp; 6386 addTest = false; 6387 } else { 6388 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6389 default: break; 6390 case X86::COND_O: 6391 case X86::COND_B: 6392 // These can only come from an arithmetic instruction with overflow, 6393 // e.g. SADDO, UADDO. 6394 Cond = Cond.getNode()->getOperand(1); 6395 addTest = false; 6396 break; 6397 } 6398 } 6399 } else { 6400 unsigned CondOpc; 6401 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6402 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6403 if (CondOpc == ISD::OR) { 6404 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6405 // two branches instead of an explicit OR instruction with a 6406 // separate test. 6407 if (Cmp == Cond.getOperand(1).getOperand(1) && 6408 isX86LogicalCmp(Cmp)) { 6409 CC = Cond.getOperand(0).getOperand(0); 6410 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6411 Chain, Dest, CC, Cmp); 6412 CC = Cond.getOperand(1).getOperand(0); 6413 Cond = Cmp; 6414 addTest = false; 6415 } 6416 } else { // ISD::AND 6417 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6418 // two branches instead of an explicit AND instruction with a 6419 // separate test. However, we only do this if this block doesn't 6420 // have a fall-through edge, because this requires an explicit 6421 // jmp when the condition is false. 6422 if (Cmp == Cond.getOperand(1).getOperand(1) && 6423 isX86LogicalCmp(Cmp) && 6424 Op.getNode()->hasOneUse()) { 6425 X86::CondCode CCode = 6426 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6427 CCode = X86::GetOppositeBranchCondition(CCode); 6428 CC = DAG.getConstant(CCode, MVT::i8); 6429 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 6430 // Look for an unconditional branch following this conditional branch. 6431 // We need this because we need to reverse the successors in order 6432 // to implement FCMP_OEQ. 6433 if (User.getOpcode() == ISD::BR) { 6434 SDValue FalseBB = User.getOperand(1); 6435 SDValue NewBR = 6436 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 6437 assert(NewBR == User); 6438 Dest = FalseBB; 6439 6440 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6441 Chain, Dest, CC, Cmp); 6442 X86::CondCode CCode = 6443 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 6444 CCode = X86::GetOppositeBranchCondition(CCode); 6445 CC = DAG.getConstant(CCode, MVT::i8); 6446 Cond = Cmp; 6447 addTest = false; 6448 } 6449 } 6450 } 6451 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 6452 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 6453 // It should be transformed during dag combiner except when the condition 6454 // is set by a arithmetics with overflow node. 6455 X86::CondCode CCode = 6456 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6457 CCode = X86::GetOppositeBranchCondition(CCode); 6458 CC = DAG.getConstant(CCode, MVT::i8); 6459 Cond = Cond.getOperand(0).getOperand(1); 6460 addTest = false; 6461 } 6462 } 6463 6464 if (addTest) { 6465 // Look pass the truncate. 6466 if (Cond.getOpcode() == ISD::TRUNCATE) 6467 Cond = Cond.getOperand(0); 6468 6469 // We know the result of AND is compared against zero. Try to match 6470 // it to BT. 6471 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6472 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6473 if (NewSetCC.getNode()) { 6474 CC = NewSetCC.getOperand(0); 6475 Cond = NewSetCC.getOperand(1); 6476 addTest = false; 6477 } 6478 } 6479 } 6480 6481 if (addTest) { 6482 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6483 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6484 } 6485 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6486 Chain, Dest, CC, Cond); 6487} 6488 6489 6490// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 6491// Calls to _alloca is needed to probe the stack when allocating more than 4k 6492// bytes in one go. Touching the stack at 4K increments is necessary to ensure 6493// that the guard pages used by the OS virtual memory manager are allocated in 6494// correct sequence. 6495SDValue 6496X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 6497 SelectionDAG &DAG) { 6498 assert(Subtarget->isTargetCygMing() && 6499 "This should be used only on Cygwin/Mingw targets"); 6500 DebugLoc dl = Op.getDebugLoc(); 6501 6502 // Get the inputs. 6503 SDValue Chain = Op.getOperand(0); 6504 SDValue Size = Op.getOperand(1); 6505 // FIXME: Ensure alignment here 6506 6507 SDValue Flag; 6508 6509 EVT IntPtr = getPointerTy(); 6510 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 6511 6512 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 6513 Flag = Chain.getValue(1); 6514 6515 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6516 6517 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag); 6518 Flag = Chain.getValue(1); 6519 6520 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 6521 6522 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 6523 return DAG.getMergeValues(Ops1, 2, dl); 6524} 6525 6526SDValue 6527X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 6528 SDValue Chain, 6529 SDValue Dst, SDValue Src, 6530 SDValue Size, unsigned Align, 6531 const Value *DstSV, 6532 uint64_t DstSVOff) { 6533 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6534 6535 // If not DWORD aligned or size is more than the threshold, call the library. 6536 // The libc version is likely to be faster for these cases. It can use the 6537 // address value and run time information about the CPU. 6538 if ((Align & 3) != 0 || 6539 !ConstantSize || 6540 ConstantSize->getZExtValue() > 6541 getSubtarget()->getMaxInlineSizeThreshold()) { 6542 SDValue InFlag(0, 0); 6543 6544 // Check to see if there is a specialized entry-point for memory zeroing. 6545 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 6546 6547 if (const char *bzeroEntry = V && 6548 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 6549 EVT IntPtr = getPointerTy(); 6550 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 6551 TargetLowering::ArgListTy Args; 6552 TargetLowering::ArgListEntry Entry; 6553 Entry.Node = Dst; 6554 Entry.Ty = IntPtrTy; 6555 Args.push_back(Entry); 6556 Entry.Node = Size; 6557 Args.push_back(Entry); 6558 std::pair<SDValue,SDValue> CallResult = 6559 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 6560 false, false, false, false, 6561 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 6562 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 6563 return CallResult.second; 6564 } 6565 6566 // Otherwise have the target-independent code call memset. 6567 return SDValue(); 6568 } 6569 6570 uint64_t SizeVal = ConstantSize->getZExtValue(); 6571 SDValue InFlag(0, 0); 6572 EVT AVT; 6573 SDValue Count; 6574 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 6575 unsigned BytesLeft = 0; 6576 bool TwoRepStos = false; 6577 if (ValC) { 6578 unsigned ValReg; 6579 uint64_t Val = ValC->getZExtValue() & 255; 6580 6581 // If the value is a constant, then we can potentially use larger sets. 6582 switch (Align & 3) { 6583 case 2: // WORD aligned 6584 AVT = MVT::i16; 6585 ValReg = X86::AX; 6586 Val = (Val << 8) | Val; 6587 break; 6588 case 0: // DWORD aligned 6589 AVT = MVT::i32; 6590 ValReg = X86::EAX; 6591 Val = (Val << 8) | Val; 6592 Val = (Val << 16) | Val; 6593 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 6594 AVT = MVT::i64; 6595 ValReg = X86::RAX; 6596 Val = (Val << 32) | Val; 6597 } 6598 break; 6599 default: // Byte aligned 6600 AVT = MVT::i8; 6601 ValReg = X86::AL; 6602 Count = DAG.getIntPtrConstant(SizeVal); 6603 break; 6604 } 6605 6606 if (AVT.bitsGT(MVT::i8)) { 6607 unsigned UBytes = AVT.getSizeInBits() / 8; 6608 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 6609 BytesLeft = SizeVal % UBytes; 6610 } 6611 6612 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 6613 InFlag); 6614 InFlag = Chain.getValue(1); 6615 } else { 6616 AVT = MVT::i8; 6617 Count = DAG.getIntPtrConstant(SizeVal); 6618 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 6619 InFlag = Chain.getValue(1); 6620 } 6621 6622 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6623 X86::ECX, 6624 Count, InFlag); 6625 InFlag = Chain.getValue(1); 6626 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6627 X86::EDI, 6628 Dst, InFlag); 6629 InFlag = Chain.getValue(1); 6630 6631 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6632 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6633 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6634 6635 if (TwoRepStos) { 6636 InFlag = Chain.getValue(1); 6637 Count = Size; 6638 EVT CVT = Count.getValueType(); 6639 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 6640 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 6641 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 6642 X86::ECX, 6643 Left, InFlag); 6644 InFlag = Chain.getValue(1); 6645 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6646 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; 6647 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6648 } else if (BytesLeft) { 6649 // Handle the last 1 - 7 bytes. 6650 unsigned Offset = SizeVal - BytesLeft; 6651 EVT AddrVT = Dst.getValueType(); 6652 EVT SizeVT = Size.getValueType(); 6653 6654 Chain = DAG.getMemset(Chain, dl, 6655 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 6656 DAG.getConstant(Offset, AddrVT)), 6657 Src, 6658 DAG.getConstant(BytesLeft, SizeVT), 6659 Align, DstSV, DstSVOff + Offset); 6660 } 6661 6662 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 6663 return Chain; 6664} 6665 6666SDValue 6667X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 6668 SDValue Chain, SDValue Dst, SDValue Src, 6669 SDValue Size, unsigned Align, 6670 bool AlwaysInline, 6671 const Value *DstSV, uint64_t DstSVOff, 6672 const Value *SrcSV, uint64_t SrcSVOff) { 6673 // This requires the copy size to be a constant, preferrably 6674 // within a subtarget-specific limit. 6675 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6676 if (!ConstantSize) 6677 return SDValue(); 6678 uint64_t SizeVal = ConstantSize->getZExtValue(); 6679 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 6680 return SDValue(); 6681 6682 /// If not DWORD aligned, call the library. 6683 if ((Align & 3) != 0) 6684 return SDValue(); 6685 6686 // DWORD aligned 6687 EVT AVT = MVT::i32; 6688 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 6689 AVT = MVT::i64; 6690 6691 unsigned UBytes = AVT.getSizeInBits() / 8; 6692 unsigned CountVal = SizeVal / UBytes; 6693 SDValue Count = DAG.getIntPtrConstant(CountVal); 6694 unsigned BytesLeft = SizeVal % UBytes; 6695 6696 SDValue InFlag(0, 0); 6697 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6698 X86::ECX, 6699 Count, InFlag); 6700 InFlag = Chain.getValue(1); 6701 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6702 X86::EDI, 6703 Dst, InFlag); 6704 InFlag = Chain.getValue(1); 6705 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6706 X86::ESI, 6707 Src, InFlag); 6708 InFlag = Chain.getValue(1); 6709 6710 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6711 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6712 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops, 6713 array_lengthof(Ops)); 6714 6715 SmallVector<SDValue, 4> Results; 6716 Results.push_back(RepMovs); 6717 if (BytesLeft) { 6718 // Handle the last 1 - 7 bytes. 6719 unsigned Offset = SizeVal - BytesLeft; 6720 EVT DstVT = Dst.getValueType(); 6721 EVT SrcVT = Src.getValueType(); 6722 EVT SizeVT = Size.getValueType(); 6723 Results.push_back(DAG.getMemcpy(Chain, dl, 6724 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6725 DAG.getConstant(Offset, DstVT)), 6726 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6727 DAG.getConstant(Offset, SrcVT)), 6728 DAG.getConstant(BytesLeft, SizeVT), 6729 Align, AlwaysInline, 6730 DstSV, DstSVOff + Offset, 6731 SrcSV, SrcSVOff + Offset)); 6732 } 6733 6734 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6735 &Results[0], Results.size()); 6736} 6737 6738SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6739 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6740 DebugLoc dl = Op.getDebugLoc(); 6741 6742 if (!Subtarget->is64Bit()) { 6743 // vastart just stores the address of the VarArgsFrameIndex slot into the 6744 // memory location argument. 6745 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6746 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 6747 false, false, 0); 6748 } 6749 6750 // __va_list_tag: 6751 // gp_offset (0 - 6 * 8) 6752 // fp_offset (48 - 48 + 8 * 16) 6753 // overflow_arg_area (point to parameters coming in memory). 6754 // reg_save_area 6755 SmallVector<SDValue, 8> MemOps; 6756 SDValue FIN = Op.getOperand(1); 6757 // Store gp_offset 6758 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6759 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6760 FIN, SV, 0, false, false, 0); 6761 MemOps.push_back(Store); 6762 6763 // Store fp_offset 6764 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6765 FIN, DAG.getIntPtrConstant(4)); 6766 Store = DAG.getStore(Op.getOperand(0), dl, 6767 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6768 FIN, SV, 0, false, false, 0); 6769 MemOps.push_back(Store); 6770 6771 // Store ptr to overflow_arg_area 6772 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6773 FIN, DAG.getIntPtrConstant(4)); 6774 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6775 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0, 6776 false, false, 0); 6777 MemOps.push_back(Store); 6778 6779 // Store ptr to reg_save_area. 6780 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6781 FIN, DAG.getIntPtrConstant(8)); 6782 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6783 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0, 6784 false, false, 0); 6785 MemOps.push_back(Store); 6786 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6787 &MemOps[0], MemOps.size()); 6788} 6789 6790SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6791 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6792 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6793 SDValue Chain = Op.getOperand(0); 6794 SDValue SrcPtr = Op.getOperand(1); 6795 SDValue SrcSV = Op.getOperand(2); 6796 6797 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6798 return SDValue(); 6799} 6800 6801SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6802 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6803 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6804 SDValue Chain = Op.getOperand(0); 6805 SDValue DstPtr = Op.getOperand(1); 6806 SDValue SrcPtr = Op.getOperand(2); 6807 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6808 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6809 DebugLoc dl = Op.getDebugLoc(); 6810 6811 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6812 DAG.getIntPtrConstant(24), 8, false, 6813 DstSV, 0, SrcSV, 0); 6814} 6815 6816SDValue 6817X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6818 DebugLoc dl = Op.getDebugLoc(); 6819 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6820 switch (IntNo) { 6821 default: return SDValue(); // Don't custom lower most intrinsics. 6822 // Comparison intrinsics. 6823 case Intrinsic::x86_sse_comieq_ss: 6824 case Intrinsic::x86_sse_comilt_ss: 6825 case Intrinsic::x86_sse_comile_ss: 6826 case Intrinsic::x86_sse_comigt_ss: 6827 case Intrinsic::x86_sse_comige_ss: 6828 case Intrinsic::x86_sse_comineq_ss: 6829 case Intrinsic::x86_sse_ucomieq_ss: 6830 case Intrinsic::x86_sse_ucomilt_ss: 6831 case Intrinsic::x86_sse_ucomile_ss: 6832 case Intrinsic::x86_sse_ucomigt_ss: 6833 case Intrinsic::x86_sse_ucomige_ss: 6834 case Intrinsic::x86_sse_ucomineq_ss: 6835 case Intrinsic::x86_sse2_comieq_sd: 6836 case Intrinsic::x86_sse2_comilt_sd: 6837 case Intrinsic::x86_sse2_comile_sd: 6838 case Intrinsic::x86_sse2_comigt_sd: 6839 case Intrinsic::x86_sse2_comige_sd: 6840 case Intrinsic::x86_sse2_comineq_sd: 6841 case Intrinsic::x86_sse2_ucomieq_sd: 6842 case Intrinsic::x86_sse2_ucomilt_sd: 6843 case Intrinsic::x86_sse2_ucomile_sd: 6844 case Intrinsic::x86_sse2_ucomigt_sd: 6845 case Intrinsic::x86_sse2_ucomige_sd: 6846 case Intrinsic::x86_sse2_ucomineq_sd: { 6847 unsigned Opc = 0; 6848 ISD::CondCode CC = ISD::SETCC_INVALID; 6849 switch (IntNo) { 6850 default: break; 6851 case Intrinsic::x86_sse_comieq_ss: 6852 case Intrinsic::x86_sse2_comieq_sd: 6853 Opc = X86ISD::COMI; 6854 CC = ISD::SETEQ; 6855 break; 6856 case Intrinsic::x86_sse_comilt_ss: 6857 case Intrinsic::x86_sse2_comilt_sd: 6858 Opc = X86ISD::COMI; 6859 CC = ISD::SETLT; 6860 break; 6861 case Intrinsic::x86_sse_comile_ss: 6862 case Intrinsic::x86_sse2_comile_sd: 6863 Opc = X86ISD::COMI; 6864 CC = ISD::SETLE; 6865 break; 6866 case Intrinsic::x86_sse_comigt_ss: 6867 case Intrinsic::x86_sse2_comigt_sd: 6868 Opc = X86ISD::COMI; 6869 CC = ISD::SETGT; 6870 break; 6871 case Intrinsic::x86_sse_comige_ss: 6872 case Intrinsic::x86_sse2_comige_sd: 6873 Opc = X86ISD::COMI; 6874 CC = ISD::SETGE; 6875 break; 6876 case Intrinsic::x86_sse_comineq_ss: 6877 case Intrinsic::x86_sse2_comineq_sd: 6878 Opc = X86ISD::COMI; 6879 CC = ISD::SETNE; 6880 break; 6881 case Intrinsic::x86_sse_ucomieq_ss: 6882 case Intrinsic::x86_sse2_ucomieq_sd: 6883 Opc = X86ISD::UCOMI; 6884 CC = ISD::SETEQ; 6885 break; 6886 case Intrinsic::x86_sse_ucomilt_ss: 6887 case Intrinsic::x86_sse2_ucomilt_sd: 6888 Opc = X86ISD::UCOMI; 6889 CC = ISD::SETLT; 6890 break; 6891 case Intrinsic::x86_sse_ucomile_ss: 6892 case Intrinsic::x86_sse2_ucomile_sd: 6893 Opc = X86ISD::UCOMI; 6894 CC = ISD::SETLE; 6895 break; 6896 case Intrinsic::x86_sse_ucomigt_ss: 6897 case Intrinsic::x86_sse2_ucomigt_sd: 6898 Opc = X86ISD::UCOMI; 6899 CC = ISD::SETGT; 6900 break; 6901 case Intrinsic::x86_sse_ucomige_ss: 6902 case Intrinsic::x86_sse2_ucomige_sd: 6903 Opc = X86ISD::UCOMI; 6904 CC = ISD::SETGE; 6905 break; 6906 case Intrinsic::x86_sse_ucomineq_ss: 6907 case Intrinsic::x86_sse2_ucomineq_sd: 6908 Opc = X86ISD::UCOMI; 6909 CC = ISD::SETNE; 6910 break; 6911 } 6912 6913 SDValue LHS = Op.getOperand(1); 6914 SDValue RHS = Op.getOperand(2); 6915 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6916 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 6917 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6918 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6919 DAG.getConstant(X86CC, MVT::i8), Cond); 6920 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6921 } 6922 // ptest intrinsics. The intrinsic these come from are designed to return 6923 // an integer value, not just an instruction so lower it to the ptest 6924 // pattern and a setcc for the result. 6925 case Intrinsic::x86_sse41_ptestz: 6926 case Intrinsic::x86_sse41_ptestc: 6927 case Intrinsic::x86_sse41_ptestnzc:{ 6928 unsigned X86CC = 0; 6929 switch (IntNo) { 6930 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6931 case Intrinsic::x86_sse41_ptestz: 6932 // ZF = 1 6933 X86CC = X86::COND_E; 6934 break; 6935 case Intrinsic::x86_sse41_ptestc: 6936 // CF = 1 6937 X86CC = X86::COND_B; 6938 break; 6939 case Intrinsic::x86_sse41_ptestnzc: 6940 // ZF and CF = 0 6941 X86CC = X86::COND_A; 6942 break; 6943 } 6944 6945 SDValue LHS = Op.getOperand(1); 6946 SDValue RHS = Op.getOperand(2); 6947 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6948 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6949 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6950 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6951 } 6952 6953 // Fix vector shift instructions where the last operand is a non-immediate 6954 // i32 value. 6955 case Intrinsic::x86_sse2_pslli_w: 6956 case Intrinsic::x86_sse2_pslli_d: 6957 case Intrinsic::x86_sse2_pslli_q: 6958 case Intrinsic::x86_sse2_psrli_w: 6959 case Intrinsic::x86_sse2_psrli_d: 6960 case Intrinsic::x86_sse2_psrli_q: 6961 case Intrinsic::x86_sse2_psrai_w: 6962 case Intrinsic::x86_sse2_psrai_d: 6963 case Intrinsic::x86_mmx_pslli_w: 6964 case Intrinsic::x86_mmx_pslli_d: 6965 case Intrinsic::x86_mmx_pslli_q: 6966 case Intrinsic::x86_mmx_psrli_w: 6967 case Intrinsic::x86_mmx_psrli_d: 6968 case Intrinsic::x86_mmx_psrli_q: 6969 case Intrinsic::x86_mmx_psrai_w: 6970 case Intrinsic::x86_mmx_psrai_d: { 6971 SDValue ShAmt = Op.getOperand(2); 6972 if (isa<ConstantSDNode>(ShAmt)) 6973 return SDValue(); 6974 6975 unsigned NewIntNo = 0; 6976 EVT ShAmtVT = MVT::v4i32; 6977 switch (IntNo) { 6978 case Intrinsic::x86_sse2_pslli_w: 6979 NewIntNo = Intrinsic::x86_sse2_psll_w; 6980 break; 6981 case Intrinsic::x86_sse2_pslli_d: 6982 NewIntNo = Intrinsic::x86_sse2_psll_d; 6983 break; 6984 case Intrinsic::x86_sse2_pslli_q: 6985 NewIntNo = Intrinsic::x86_sse2_psll_q; 6986 break; 6987 case Intrinsic::x86_sse2_psrli_w: 6988 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6989 break; 6990 case Intrinsic::x86_sse2_psrli_d: 6991 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6992 break; 6993 case Intrinsic::x86_sse2_psrli_q: 6994 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6995 break; 6996 case Intrinsic::x86_sse2_psrai_w: 6997 NewIntNo = Intrinsic::x86_sse2_psra_w; 6998 break; 6999 case Intrinsic::x86_sse2_psrai_d: 7000 NewIntNo = Intrinsic::x86_sse2_psra_d; 7001 break; 7002 default: { 7003 ShAmtVT = MVT::v2i32; 7004 switch (IntNo) { 7005 case Intrinsic::x86_mmx_pslli_w: 7006 NewIntNo = Intrinsic::x86_mmx_psll_w; 7007 break; 7008 case Intrinsic::x86_mmx_pslli_d: 7009 NewIntNo = Intrinsic::x86_mmx_psll_d; 7010 break; 7011 case Intrinsic::x86_mmx_pslli_q: 7012 NewIntNo = Intrinsic::x86_mmx_psll_q; 7013 break; 7014 case Intrinsic::x86_mmx_psrli_w: 7015 NewIntNo = Intrinsic::x86_mmx_psrl_w; 7016 break; 7017 case Intrinsic::x86_mmx_psrli_d: 7018 NewIntNo = Intrinsic::x86_mmx_psrl_d; 7019 break; 7020 case Intrinsic::x86_mmx_psrli_q: 7021 NewIntNo = Intrinsic::x86_mmx_psrl_q; 7022 break; 7023 case Intrinsic::x86_mmx_psrai_w: 7024 NewIntNo = Intrinsic::x86_mmx_psra_w; 7025 break; 7026 case Intrinsic::x86_mmx_psrai_d: 7027 NewIntNo = Intrinsic::x86_mmx_psra_d; 7028 break; 7029 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7030 } 7031 break; 7032 } 7033 } 7034 7035 // The vector shift intrinsics with scalars uses 32b shift amounts but 7036 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 7037 // to be zero. 7038 SDValue ShOps[4]; 7039 ShOps[0] = ShAmt; 7040 ShOps[1] = DAG.getConstant(0, MVT::i32); 7041 if (ShAmtVT == MVT::v4i32) { 7042 ShOps[2] = DAG.getUNDEF(MVT::i32); 7043 ShOps[3] = DAG.getUNDEF(MVT::i32); 7044 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 7045 } else { 7046 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 7047 } 7048 7049 EVT VT = Op.getValueType(); 7050 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 7051 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7052 DAG.getConstant(NewIntNo, MVT::i32), 7053 Op.getOperand(1), ShAmt); 7054 } 7055 } 7056} 7057 7058SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 7059 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7060 DebugLoc dl = Op.getDebugLoc(); 7061 7062 if (Depth > 0) { 7063 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7064 SDValue Offset = 7065 DAG.getConstant(TD->getPointerSize(), 7066 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7067 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7068 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7069 FrameAddr, Offset), 7070 NULL, 0, false, false, 0); 7071 } 7072 7073 // Just load the return address. 7074 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7075 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7076 RetAddrFI, NULL, 0, false, false, 0); 7077} 7078 7079SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 7080 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7081 MFI->setFrameAddressIsTaken(true); 7082 EVT VT = Op.getValueType(); 7083 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7084 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7085 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7086 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7087 while (Depth--) 7088 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 7089 false, false, 0); 7090 return FrameAddr; 7091} 7092 7093SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7094 SelectionDAG &DAG) { 7095 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7096} 7097 7098SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 7099{ 7100 MachineFunction &MF = DAG.getMachineFunction(); 7101 SDValue Chain = Op.getOperand(0); 7102 SDValue Offset = Op.getOperand(1); 7103 SDValue Handler = Op.getOperand(2); 7104 DebugLoc dl = Op.getDebugLoc(); 7105 7106 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 7107 getPointerTy()); 7108 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 7109 7110 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 7111 DAG.getIntPtrConstant(-TD->getPointerSize())); 7112 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7113 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7114 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7115 MF.getRegInfo().addLiveOut(StoreAddrReg); 7116 7117 return DAG.getNode(X86ISD::EH_RETURN, dl, 7118 MVT::Other, 7119 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7120} 7121 7122SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7123 SelectionDAG &DAG) { 7124 SDValue Root = Op.getOperand(0); 7125 SDValue Trmp = Op.getOperand(1); // trampoline 7126 SDValue FPtr = Op.getOperand(2); // nested function 7127 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7128 DebugLoc dl = Op.getDebugLoc(); 7129 7130 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7131 7132 if (Subtarget->is64Bit()) { 7133 SDValue OutChains[6]; 7134 7135 // Large code-model. 7136 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7137 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7138 7139 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7140 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7141 7142 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7143 7144 // Load the pointer to the nested function into R11. 7145 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7146 SDValue Addr = Trmp; 7147 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7148 Addr, TrmpAddr, 0, false, false, 0); 7149 7150 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7151 DAG.getConstant(2, MVT::i64)); 7152 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7153 false, false, 2); 7154 7155 // Load the 'nest' parameter value into R10. 7156 // R10 is specified in X86CallingConv.td 7157 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7159 DAG.getConstant(10, MVT::i64)); 7160 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7161 Addr, TrmpAddr, 10, false, false, 0); 7162 7163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7164 DAG.getConstant(12, MVT::i64)); 7165 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7166 false, false, 2); 7167 7168 // Jump to the nested function. 7169 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7170 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7171 DAG.getConstant(20, MVT::i64)); 7172 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7173 Addr, TrmpAddr, 20, false, false, 0); 7174 7175 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7176 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7177 DAG.getConstant(22, MVT::i64)); 7178 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7179 TrmpAddr, 22, false, false, 0); 7180 7181 SDValue Ops[] = 7182 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7183 return DAG.getMergeValues(Ops, 2, dl); 7184 } else { 7185 const Function *Func = 7186 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7187 CallingConv::ID CC = Func->getCallingConv(); 7188 unsigned NestReg; 7189 7190 switch (CC) { 7191 default: 7192 llvm_unreachable("Unsupported calling convention"); 7193 case CallingConv::C: 7194 case CallingConv::X86_StdCall: { 7195 // Pass 'nest' parameter in ECX. 7196 // Must be kept in sync with X86CallingConv.td 7197 NestReg = X86::ECX; 7198 7199 // Check that ECX wasn't needed by an 'inreg' parameter. 7200 const FunctionType *FTy = Func->getFunctionType(); 7201 const AttrListPtr &Attrs = Func->getAttributes(); 7202 7203 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7204 unsigned InRegCount = 0; 7205 unsigned Idx = 1; 7206 7207 for (FunctionType::param_iterator I = FTy->param_begin(), 7208 E = FTy->param_end(); I != E; ++I, ++Idx) 7209 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7210 // FIXME: should only count parameters that are lowered to integers. 7211 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7212 7213 if (InRegCount > 2) { 7214 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 7215 } 7216 } 7217 break; 7218 } 7219 case CallingConv::X86_FastCall: 7220 case CallingConv::Fast: 7221 // Pass 'nest' parameter in EAX. 7222 // Must be kept in sync with X86CallingConv.td 7223 NestReg = X86::EAX; 7224 break; 7225 } 7226 7227 SDValue OutChains[4]; 7228 SDValue Addr, Disp; 7229 7230 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7231 DAG.getConstant(10, MVT::i32)); 7232 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7233 7234 // This is storing the opcode for MOV32ri. 7235 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7236 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7237 OutChains[0] = DAG.getStore(Root, dl, 7238 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7239 Trmp, TrmpAddr, 0, false, false, 0); 7240 7241 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7242 DAG.getConstant(1, MVT::i32)); 7243 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7244 false, false, 1); 7245 7246 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7247 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7248 DAG.getConstant(5, MVT::i32)); 7249 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7250 TrmpAddr, 5, false, false, 1); 7251 7252 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7253 DAG.getConstant(6, MVT::i32)); 7254 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7255 false, false, 1); 7256 7257 SDValue Ops[] = 7258 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7259 return DAG.getMergeValues(Ops, 2, dl); 7260 } 7261} 7262 7263SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 7264 /* 7265 The rounding mode is in bits 11:10 of FPSR, and has the following 7266 settings: 7267 00 Round to nearest 7268 01 Round to -inf 7269 10 Round to +inf 7270 11 Round to 0 7271 7272 FLT_ROUNDS, on the other hand, expects the following: 7273 -1 Undefined 7274 0 Round to 0 7275 1 Round to nearest 7276 2 Round to +inf 7277 3 Round to -inf 7278 7279 To perform the conversion, we do: 7280 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7281 */ 7282 7283 MachineFunction &MF = DAG.getMachineFunction(); 7284 const TargetMachine &TM = MF.getTarget(); 7285 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7286 unsigned StackAlignment = TFI.getStackAlignment(); 7287 EVT VT = Op.getValueType(); 7288 DebugLoc dl = Op.getDebugLoc(); 7289 7290 // Save FP Control Word to stack slot 7291 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7292 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7293 7294 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7295 DAG.getEntryNode(), StackSlot); 7296 7297 // Load FP Control Word from stack slot 7298 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7299 false, false, 0); 7300 7301 // Transform as necessary 7302 SDValue CWD1 = 7303 DAG.getNode(ISD::SRL, dl, MVT::i16, 7304 DAG.getNode(ISD::AND, dl, MVT::i16, 7305 CWD, DAG.getConstant(0x800, MVT::i16)), 7306 DAG.getConstant(11, MVT::i8)); 7307 SDValue CWD2 = 7308 DAG.getNode(ISD::SRL, dl, MVT::i16, 7309 DAG.getNode(ISD::AND, dl, MVT::i16, 7310 CWD, DAG.getConstant(0x400, MVT::i16)), 7311 DAG.getConstant(9, MVT::i8)); 7312 7313 SDValue RetVal = 7314 DAG.getNode(ISD::AND, dl, MVT::i16, 7315 DAG.getNode(ISD::ADD, dl, MVT::i16, 7316 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7317 DAG.getConstant(1, MVT::i16)), 7318 DAG.getConstant(3, MVT::i16)); 7319 7320 7321 return DAG.getNode((VT.getSizeInBits() < 16 ? 7322 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7323} 7324 7325SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 7326 EVT VT = Op.getValueType(); 7327 EVT OpVT = VT; 7328 unsigned NumBits = VT.getSizeInBits(); 7329 DebugLoc dl = Op.getDebugLoc(); 7330 7331 Op = Op.getOperand(0); 7332 if (VT == MVT::i8) { 7333 // Zero extend to i32 since there is not an i8 bsr. 7334 OpVT = MVT::i32; 7335 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7336 } 7337 7338 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7339 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7340 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7341 7342 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7343 SDValue Ops[] = { 7344 Op, 7345 DAG.getConstant(NumBits+NumBits-1, OpVT), 7346 DAG.getConstant(X86::COND_E, MVT::i8), 7347 Op.getValue(1) 7348 }; 7349 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7350 7351 // Finally xor with NumBits-1. 7352 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7353 7354 if (VT == MVT::i8) 7355 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7356 return Op; 7357} 7358 7359SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 7360 EVT VT = Op.getValueType(); 7361 EVT OpVT = VT; 7362 unsigned NumBits = VT.getSizeInBits(); 7363 DebugLoc dl = Op.getDebugLoc(); 7364 7365 Op = Op.getOperand(0); 7366 if (VT == MVT::i8) { 7367 OpVT = MVT::i32; 7368 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7369 } 7370 7371 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7372 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7373 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7374 7375 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7376 SDValue Ops[] = { 7377 Op, 7378 DAG.getConstant(NumBits, OpVT), 7379 DAG.getConstant(X86::COND_E, MVT::i8), 7380 Op.getValue(1) 7381 }; 7382 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7383 7384 if (VT == MVT::i8) 7385 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7386 return Op; 7387} 7388 7389SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 7390 EVT VT = Op.getValueType(); 7391 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7392 DebugLoc dl = Op.getDebugLoc(); 7393 7394 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7395 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7396 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7397 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7398 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7399 // 7400 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7401 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7402 // return AloBlo + AloBhi + AhiBlo; 7403 7404 SDValue A = Op.getOperand(0); 7405 SDValue B = Op.getOperand(1); 7406 7407 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7408 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7409 A, DAG.getConstant(32, MVT::i32)); 7410 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7411 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7412 B, DAG.getConstant(32, MVT::i32)); 7413 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7414 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7415 A, B); 7416 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7417 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7418 A, Bhi); 7419 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7420 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7421 Ahi, B); 7422 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7423 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7424 AloBhi, DAG.getConstant(32, MVT::i32)); 7425 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7426 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7427 AhiBlo, DAG.getConstant(32, MVT::i32)); 7428 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7429 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7430 return Res; 7431} 7432 7433 7434SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 7435 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7436 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7437 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7438 // has only one use. 7439 SDNode *N = Op.getNode(); 7440 SDValue LHS = N->getOperand(0); 7441 SDValue RHS = N->getOperand(1); 7442 unsigned BaseOp = 0; 7443 unsigned Cond = 0; 7444 DebugLoc dl = Op.getDebugLoc(); 7445 7446 switch (Op.getOpcode()) { 7447 default: llvm_unreachable("Unknown ovf instruction!"); 7448 case ISD::SADDO: 7449 // A subtract of one will be selected as a INC. Note that INC doesn't 7450 // set CF, so we can't do this for UADDO. 7451 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7452 if (C->getAPIntValue() == 1) { 7453 BaseOp = X86ISD::INC; 7454 Cond = X86::COND_O; 7455 break; 7456 } 7457 BaseOp = X86ISD::ADD; 7458 Cond = X86::COND_O; 7459 break; 7460 case ISD::UADDO: 7461 BaseOp = X86ISD::ADD; 7462 Cond = X86::COND_B; 7463 break; 7464 case ISD::SSUBO: 7465 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7466 // set CF, so we can't do this for USUBO. 7467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7468 if (C->getAPIntValue() == 1) { 7469 BaseOp = X86ISD::DEC; 7470 Cond = X86::COND_O; 7471 break; 7472 } 7473 BaseOp = X86ISD::SUB; 7474 Cond = X86::COND_O; 7475 break; 7476 case ISD::USUBO: 7477 BaseOp = X86ISD::SUB; 7478 Cond = X86::COND_B; 7479 break; 7480 case ISD::SMULO: 7481 BaseOp = X86ISD::SMUL; 7482 Cond = X86::COND_O; 7483 break; 7484 case ISD::UMULO: 7485 BaseOp = X86ISD::UMUL; 7486 Cond = X86::COND_B; 7487 break; 7488 } 7489 7490 // Also sets EFLAGS. 7491 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7492 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7493 7494 SDValue SetCC = 7495 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7496 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7497 7498 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7499 return Sum; 7500} 7501 7502SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 7503 EVT T = Op.getValueType(); 7504 DebugLoc dl = Op.getDebugLoc(); 7505 unsigned Reg = 0; 7506 unsigned size = 0; 7507 switch(T.getSimpleVT().SimpleTy) { 7508 default: 7509 assert(false && "Invalid value type!"); 7510 case MVT::i8: Reg = X86::AL; size = 1; break; 7511 case MVT::i16: Reg = X86::AX; size = 2; break; 7512 case MVT::i32: Reg = X86::EAX; size = 4; break; 7513 case MVT::i64: 7514 assert(Subtarget->is64Bit() && "Node not type legal!"); 7515 Reg = X86::RAX; size = 8; 7516 break; 7517 } 7518 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 7519 Op.getOperand(2), SDValue()); 7520 SDValue Ops[] = { cpIn.getValue(0), 7521 Op.getOperand(1), 7522 Op.getOperand(3), 7523 DAG.getTargetConstant(size, MVT::i8), 7524 cpIn.getValue(1) }; 7525 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7526 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 7527 SDValue cpOut = 7528 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 7529 return cpOut; 7530} 7531 7532SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 7533 SelectionDAG &DAG) { 7534 assert(Subtarget->is64Bit() && "Result not type legalized?"); 7535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7536 SDValue TheChain = Op.getOperand(0); 7537 DebugLoc dl = Op.getDebugLoc(); 7538 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7539 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 7540 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 7541 rax.getValue(2)); 7542 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 7543 DAG.getConstant(32, MVT::i8)); 7544 SDValue Ops[] = { 7545 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 7546 rdx.getValue(1) 7547 }; 7548 return DAG.getMergeValues(Ops, 2, dl); 7549} 7550 7551SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 7552 SDNode *Node = Op.getNode(); 7553 DebugLoc dl = Node->getDebugLoc(); 7554 EVT T = Node->getValueType(0); 7555 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 7556 DAG.getConstant(0, T), Node->getOperand(2)); 7557 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 7558 cast<AtomicSDNode>(Node)->getMemoryVT(), 7559 Node->getOperand(0), 7560 Node->getOperand(1), negOp, 7561 cast<AtomicSDNode>(Node)->getSrcValue(), 7562 cast<AtomicSDNode>(Node)->getAlignment()); 7563} 7564 7565/// LowerOperation - Provide custom lowering hooks for some operations. 7566/// 7567SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 7568 switch (Op.getOpcode()) { 7569 default: llvm_unreachable("Should not custom lower this!"); 7570 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 7571 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 7572 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 7573 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 7574 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 7575 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 7576 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 7577 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 7578 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 7579 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 7580 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 7581 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 7582 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 7583 case ISD::SHL_PARTS: 7584 case ISD::SRA_PARTS: 7585 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 7586 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 7587 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 7588 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 7589 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 7590 case ISD::FABS: return LowerFABS(Op, DAG); 7591 case ISD::FNEG: return LowerFNEG(Op, DAG); 7592 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 7593 case ISD::SETCC: return LowerSETCC(Op, DAG); 7594 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 7595 case ISD::SELECT: return LowerSELECT(Op, DAG); 7596 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 7597 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 7598 case ISD::VASTART: return LowerVASTART(Op, DAG); 7599 case ISD::VAARG: return LowerVAARG(Op, DAG); 7600 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 7601 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 7602 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 7603 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 7604 case ISD::FRAME_TO_ARGS_OFFSET: 7605 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 7606 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 7607 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 7608 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 7609 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 7610 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 7611 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 7612 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 7613 case ISD::SADDO: 7614 case ISD::UADDO: 7615 case ISD::SSUBO: 7616 case ISD::USUBO: 7617 case ISD::SMULO: 7618 case ISD::UMULO: return LowerXALUO(Op, DAG); 7619 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 7620 } 7621} 7622 7623void X86TargetLowering:: 7624ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 7625 SelectionDAG &DAG, unsigned NewOp) { 7626 EVT T = Node->getValueType(0); 7627 DebugLoc dl = Node->getDebugLoc(); 7628 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 7629 7630 SDValue Chain = Node->getOperand(0); 7631 SDValue In1 = Node->getOperand(1); 7632 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7633 Node->getOperand(2), DAG.getIntPtrConstant(0)); 7634 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7635 Node->getOperand(2), DAG.getIntPtrConstant(1)); 7636 SDValue Ops[] = { Chain, In1, In2L, In2H }; 7637 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 7638 SDValue Result = 7639 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 7640 cast<MemSDNode>(Node)->getMemOperand()); 7641 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 7642 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7643 Results.push_back(Result.getValue(2)); 7644} 7645 7646/// ReplaceNodeResults - Replace a node with an illegal result type 7647/// with a new node built out of custom code. 7648void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7649 SmallVectorImpl<SDValue>&Results, 7650 SelectionDAG &DAG) { 7651 DebugLoc dl = N->getDebugLoc(); 7652 switch (N->getOpcode()) { 7653 default: 7654 assert(false && "Do not know how to custom type legalize this operation!"); 7655 return; 7656 case ISD::FP_TO_SINT: { 7657 std::pair<SDValue,SDValue> Vals = 7658 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7659 SDValue FIST = Vals.first, StackSlot = Vals.second; 7660 if (FIST.getNode() != 0) { 7661 EVT VT = N->getValueType(0); 7662 // Return a load from the stack slot. 7663 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 7664 false, false, 0)); 7665 } 7666 return; 7667 } 7668 case ISD::READCYCLECOUNTER: { 7669 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7670 SDValue TheChain = N->getOperand(0); 7671 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7672 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7673 rd.getValue(1)); 7674 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7675 eax.getValue(2)); 7676 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7677 SDValue Ops[] = { eax, edx }; 7678 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7679 Results.push_back(edx.getValue(1)); 7680 return; 7681 } 7682 case ISD::ATOMIC_CMP_SWAP: { 7683 EVT T = N->getValueType(0); 7684 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7685 SDValue cpInL, cpInH; 7686 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7687 DAG.getConstant(0, MVT::i32)); 7688 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7689 DAG.getConstant(1, MVT::i32)); 7690 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7691 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7692 cpInL.getValue(1)); 7693 SDValue swapInL, swapInH; 7694 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7695 DAG.getConstant(0, MVT::i32)); 7696 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7697 DAG.getConstant(1, MVT::i32)); 7698 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7699 cpInH.getValue(1)); 7700 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7701 swapInL.getValue(1)); 7702 SDValue Ops[] = { swapInH.getValue(0), 7703 N->getOperand(1), 7704 swapInH.getValue(1) }; 7705 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7706 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7707 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7708 MVT::i32, Result.getValue(1)); 7709 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7710 MVT::i32, cpOutL.getValue(2)); 7711 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7712 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7713 Results.push_back(cpOutH.getValue(1)); 7714 return; 7715 } 7716 case ISD::ATOMIC_LOAD_ADD: 7717 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7718 return; 7719 case ISD::ATOMIC_LOAD_AND: 7720 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7721 return; 7722 case ISD::ATOMIC_LOAD_NAND: 7723 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7724 return; 7725 case ISD::ATOMIC_LOAD_OR: 7726 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7727 return; 7728 case ISD::ATOMIC_LOAD_SUB: 7729 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7730 return; 7731 case ISD::ATOMIC_LOAD_XOR: 7732 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7733 return; 7734 case ISD::ATOMIC_SWAP: 7735 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7736 return; 7737 } 7738} 7739 7740const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7741 switch (Opcode) { 7742 default: return NULL; 7743 case X86ISD::BSF: return "X86ISD::BSF"; 7744 case X86ISD::BSR: return "X86ISD::BSR"; 7745 case X86ISD::SHLD: return "X86ISD::SHLD"; 7746 case X86ISD::SHRD: return "X86ISD::SHRD"; 7747 case X86ISD::FAND: return "X86ISD::FAND"; 7748 case X86ISD::FOR: return "X86ISD::FOR"; 7749 case X86ISD::FXOR: return "X86ISD::FXOR"; 7750 case X86ISD::FSRL: return "X86ISD::FSRL"; 7751 case X86ISD::FILD: return "X86ISD::FILD"; 7752 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7753 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7754 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7755 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7756 case X86ISD::FLD: return "X86ISD::FLD"; 7757 case X86ISD::FST: return "X86ISD::FST"; 7758 case X86ISD::CALL: return "X86ISD::CALL"; 7759 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7760 case X86ISD::BT: return "X86ISD::BT"; 7761 case X86ISD::CMP: return "X86ISD::CMP"; 7762 case X86ISD::COMI: return "X86ISD::COMI"; 7763 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7764 case X86ISD::SETCC: return "X86ISD::SETCC"; 7765 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 7766 case X86ISD::CMOV: return "X86ISD::CMOV"; 7767 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7768 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7769 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7770 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7771 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7772 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7773 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7774 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7775 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7776 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7777 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7778 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7779 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW"; 7780 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7781 case X86ISD::FMAX: return "X86ISD::FMAX"; 7782 case X86ISD::FMIN: return "X86ISD::FMIN"; 7783 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7784 case X86ISD::FRCP: return "X86ISD::FRCP"; 7785 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7786 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7787 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7788 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7789 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7790 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7791 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7792 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7793 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7794 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7795 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7796 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7797 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7798 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7799 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7800 case X86ISD::VSHL: return "X86ISD::VSHL"; 7801 case X86ISD::VSRL: return "X86ISD::VSRL"; 7802 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7803 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7804 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7805 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7806 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7807 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7808 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7809 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7810 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7811 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7812 case X86ISD::ADD: return "X86ISD::ADD"; 7813 case X86ISD::SUB: return "X86ISD::SUB"; 7814 case X86ISD::SMUL: return "X86ISD::SMUL"; 7815 case X86ISD::UMUL: return "X86ISD::UMUL"; 7816 case X86ISD::INC: return "X86ISD::INC"; 7817 case X86ISD::DEC: return "X86ISD::DEC"; 7818 case X86ISD::OR: return "X86ISD::OR"; 7819 case X86ISD::XOR: return "X86ISD::XOR"; 7820 case X86ISD::AND: return "X86ISD::AND"; 7821 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7822 case X86ISD::PTEST: return "X86ISD::PTEST"; 7823 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7824 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA"; 7825 } 7826} 7827 7828// isLegalAddressingMode - Return true if the addressing mode represented 7829// by AM is legal for this target, for a load/store of the specified type. 7830bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7831 const Type *Ty) const { 7832 // X86 supports extremely general addressing modes. 7833 CodeModel::Model M = getTargetMachine().getCodeModel(); 7834 7835 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7836 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7837 return false; 7838 7839 if (AM.BaseGV) { 7840 unsigned GVFlags = 7841 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7842 7843 // If a reference to this global requires an extra load, we can't fold it. 7844 if (isGlobalStubReference(GVFlags)) 7845 return false; 7846 7847 // If BaseGV requires a register for the PIC base, we cannot also have a 7848 // BaseReg specified. 7849 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7850 return false; 7851 7852 // If lower 4G is not available, then we must use rip-relative addressing. 7853 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7854 return false; 7855 } 7856 7857 switch (AM.Scale) { 7858 case 0: 7859 case 1: 7860 case 2: 7861 case 4: 7862 case 8: 7863 // These scales always work. 7864 break; 7865 case 3: 7866 case 5: 7867 case 9: 7868 // These scales are formed with basereg+scalereg. Only accept if there is 7869 // no basereg yet. 7870 if (AM.HasBaseReg) 7871 return false; 7872 break; 7873 default: // Other stuff never works. 7874 return false; 7875 } 7876 7877 return true; 7878} 7879 7880 7881bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7882 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 7883 return false; 7884 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7885 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7886 if (NumBits1 <= NumBits2) 7887 return false; 7888 return true; 7889} 7890 7891bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7892 if (!VT1.isInteger() || !VT2.isInteger()) 7893 return false; 7894 unsigned NumBits1 = VT1.getSizeInBits(); 7895 unsigned NumBits2 = VT2.getSizeInBits(); 7896 if (NumBits1 <= NumBits2) 7897 return false; 7898 return true; 7899} 7900 7901bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7902 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7903 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 7904} 7905 7906bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7907 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7908 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7909} 7910 7911bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7912 // i16 instructions are longer (0x66 prefix) and potentially slower. 7913 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7914} 7915 7916/// isShuffleMaskLegal - Targets can use this to indicate that they only 7917/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7918/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7919/// are assumed to be legal. 7920bool 7921X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7922 EVT VT) const { 7923 // Only do shuffles on 128-bit vector types for now. 7924 if (VT.getSizeInBits() == 64) 7925 return false; 7926 7927 // FIXME: pshufb, blends, shifts. 7928 return (VT.getVectorNumElements() == 2 || 7929 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7930 isMOVLMask(M, VT) || 7931 isSHUFPMask(M, VT) || 7932 isPSHUFDMask(M, VT) || 7933 isPSHUFHWMask(M, VT) || 7934 isPSHUFLWMask(M, VT) || 7935 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 7936 isUNPCKLMask(M, VT) || 7937 isUNPCKHMask(M, VT) || 7938 isUNPCKL_v_undef_Mask(M, VT) || 7939 isUNPCKH_v_undef_Mask(M, VT)); 7940} 7941 7942bool 7943X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7944 EVT VT) const { 7945 unsigned NumElts = VT.getVectorNumElements(); 7946 // FIXME: This collection of masks seems suspect. 7947 if (NumElts == 2) 7948 return true; 7949 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7950 return (isMOVLMask(Mask, VT) || 7951 isCommutedMOVLMask(Mask, VT, true) || 7952 isSHUFPMask(Mask, VT) || 7953 isCommutedSHUFPMask(Mask, VT)); 7954 } 7955 return false; 7956} 7957 7958//===----------------------------------------------------------------------===// 7959// X86 Scheduler Hooks 7960//===----------------------------------------------------------------------===// 7961 7962// private utility function 7963MachineBasicBlock * 7964X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7965 MachineBasicBlock *MBB, 7966 unsigned regOpc, 7967 unsigned immOpc, 7968 unsigned LoadOpc, 7969 unsigned CXchgOpc, 7970 unsigned copyOpc, 7971 unsigned notOpc, 7972 unsigned EAXreg, 7973 TargetRegisterClass *RC, 7974 bool invSrc) const { 7975 // For the atomic bitwise operator, we generate 7976 // thisMBB: 7977 // newMBB: 7978 // ld t1 = [bitinstr.addr] 7979 // op t2 = t1, [bitinstr.val] 7980 // mov EAX = t1 7981 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7982 // bz newMBB 7983 // fallthrough -->nextMBB 7984 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7985 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7986 MachineFunction::iterator MBBIter = MBB; 7987 ++MBBIter; 7988 7989 /// First build the CFG 7990 MachineFunction *F = MBB->getParent(); 7991 MachineBasicBlock *thisMBB = MBB; 7992 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7993 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7994 F->insert(MBBIter, newMBB); 7995 F->insert(MBBIter, nextMBB); 7996 7997 // Move all successors to thisMBB to nextMBB 7998 nextMBB->transferSuccessors(thisMBB); 7999 8000 // Update thisMBB to fall through to newMBB 8001 thisMBB->addSuccessor(newMBB); 8002 8003 // newMBB jumps to itself and fall through to nextMBB 8004 newMBB->addSuccessor(nextMBB); 8005 newMBB->addSuccessor(newMBB); 8006 8007 // Insert instructions into newMBB based on incoming instruction 8008 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 8009 "unexpected number of operands"); 8010 DebugLoc dl = bInstr->getDebugLoc(); 8011 MachineOperand& destOper = bInstr->getOperand(0); 8012 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8013 int numArgs = bInstr->getNumOperands() - 1; 8014 for (int i=0; i < numArgs; ++i) 8015 argOpers[i] = &bInstr->getOperand(i+1); 8016 8017 // x86 address has 4 operands: base, index, scale, and displacement 8018 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8019 int valArgIndx = lastAddrIndx + 1; 8020 8021 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8022 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 8023 for (int i=0; i <= lastAddrIndx; ++i) 8024 (*MIB).addOperand(*argOpers[i]); 8025 8026 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 8027 if (invSrc) { 8028 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 8029 } 8030 else 8031 tt = t1; 8032 8033 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8034 assert((argOpers[valArgIndx]->isReg() || 8035 argOpers[valArgIndx]->isImm()) && 8036 "invalid operand"); 8037 if (argOpers[valArgIndx]->isReg()) 8038 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 8039 else 8040 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 8041 MIB.addReg(tt); 8042 (*MIB).addOperand(*argOpers[valArgIndx]); 8043 8044 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 8045 MIB.addReg(t1); 8046 8047 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 8048 for (int i=0; i <= lastAddrIndx; ++i) 8049 (*MIB).addOperand(*argOpers[i]); 8050 MIB.addReg(t2); 8051 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8052 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8053 bInstr->memoperands_end()); 8054 8055 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 8056 MIB.addReg(EAXreg); 8057 8058 // insert branch 8059 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8060 8061 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8062 return nextMBB; 8063} 8064 8065// private utility function: 64 bit atomics on 32 bit host. 8066MachineBasicBlock * 8067X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 8068 MachineBasicBlock *MBB, 8069 unsigned regOpcL, 8070 unsigned regOpcH, 8071 unsigned immOpcL, 8072 unsigned immOpcH, 8073 bool invSrc) const { 8074 // For the atomic bitwise operator, we generate 8075 // thisMBB (instructions are in pairs, except cmpxchg8b) 8076 // ld t1,t2 = [bitinstr.addr] 8077 // newMBB: 8078 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 8079 // op t5, t6 <- out1, out2, [bitinstr.val] 8080 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 8081 // mov ECX, EBX <- t5, t6 8082 // mov EAX, EDX <- t1, t2 8083 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 8084 // mov t3, t4 <- EAX, EDX 8085 // bz newMBB 8086 // result in out1, out2 8087 // fallthrough -->nextMBB 8088 8089 const TargetRegisterClass *RC = X86::GR32RegisterClass; 8090 const unsigned LoadOpc = X86::MOV32rm; 8091 const unsigned copyOpc = X86::MOV32rr; 8092 const unsigned NotOpc = X86::NOT32r; 8093 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8094 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8095 MachineFunction::iterator MBBIter = MBB; 8096 ++MBBIter; 8097 8098 /// First build the CFG 8099 MachineFunction *F = MBB->getParent(); 8100 MachineBasicBlock *thisMBB = MBB; 8101 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8102 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8103 F->insert(MBBIter, newMBB); 8104 F->insert(MBBIter, nextMBB); 8105 8106 // Move all successors to thisMBB to nextMBB 8107 nextMBB->transferSuccessors(thisMBB); 8108 8109 // Update thisMBB to fall through to newMBB 8110 thisMBB->addSuccessor(newMBB); 8111 8112 // newMBB jumps to itself and fall through to nextMBB 8113 newMBB->addSuccessor(nextMBB); 8114 newMBB->addSuccessor(newMBB); 8115 8116 DebugLoc dl = bInstr->getDebugLoc(); 8117 // Insert instructions into newMBB based on incoming instruction 8118 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8119 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 8120 "unexpected number of operands"); 8121 MachineOperand& dest1Oper = bInstr->getOperand(0); 8122 MachineOperand& dest2Oper = bInstr->getOperand(1); 8123 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8124 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 8125 argOpers[i] = &bInstr->getOperand(i+2); 8126 8127 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8128 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8129 8130 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8131 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8132 for (int i=0; i <= lastAddrIndx; ++i) 8133 (*MIB).addOperand(*argOpers[i]); 8134 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8135 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8136 // add 4 to displacement. 8137 for (int i=0; i <= lastAddrIndx-2; ++i) 8138 (*MIB).addOperand(*argOpers[i]); 8139 MachineOperand newOp3 = *(argOpers[3]); 8140 if (newOp3.isImm()) 8141 newOp3.setImm(newOp3.getImm()+4); 8142 else 8143 newOp3.setOffset(newOp3.getOffset()+4); 8144 (*MIB).addOperand(newOp3); 8145 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8146 8147 // t3/4 are defined later, at the bottom of the loop 8148 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8149 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8150 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8151 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8152 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8153 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8154 8155 // The subsequent operations should be using the destination registers of 8156 //the PHI instructions. 8157 if (invSrc) { 8158 t1 = F->getRegInfo().createVirtualRegister(RC); 8159 t2 = F->getRegInfo().createVirtualRegister(RC); 8160 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8161 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8162 } else { 8163 t1 = dest1Oper.getReg(); 8164 t2 = dest2Oper.getReg(); 8165 } 8166 8167 int valArgIndx = lastAddrIndx + 1; 8168 assert((argOpers[valArgIndx]->isReg() || 8169 argOpers[valArgIndx]->isImm()) && 8170 "invalid operand"); 8171 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8172 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8173 if (argOpers[valArgIndx]->isReg()) 8174 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8175 else 8176 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8177 if (regOpcL != X86::MOV32rr) 8178 MIB.addReg(t1); 8179 (*MIB).addOperand(*argOpers[valArgIndx]); 8180 assert(argOpers[valArgIndx + 1]->isReg() == 8181 argOpers[valArgIndx]->isReg()); 8182 assert(argOpers[valArgIndx + 1]->isImm() == 8183 argOpers[valArgIndx]->isImm()); 8184 if (argOpers[valArgIndx + 1]->isReg()) 8185 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8186 else 8187 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8188 if (regOpcH != X86::MOV32rr) 8189 MIB.addReg(t2); 8190 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8191 8192 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 8193 MIB.addReg(t1); 8194 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 8195 MIB.addReg(t2); 8196 8197 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 8198 MIB.addReg(t5); 8199 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 8200 MIB.addReg(t6); 8201 8202 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8203 for (int i=0; i <= lastAddrIndx; ++i) 8204 (*MIB).addOperand(*argOpers[i]); 8205 8206 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8207 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8208 bInstr->memoperands_end()); 8209 8210 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 8211 MIB.addReg(X86::EAX); 8212 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 8213 MIB.addReg(X86::EDX); 8214 8215 // insert branch 8216 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8217 8218 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8219 return nextMBB; 8220} 8221 8222// private utility function 8223MachineBasicBlock * 8224X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8225 MachineBasicBlock *MBB, 8226 unsigned cmovOpc) const { 8227 // For the atomic min/max operator, we generate 8228 // thisMBB: 8229 // newMBB: 8230 // ld t1 = [min/max.addr] 8231 // mov t2 = [min/max.val] 8232 // cmp t1, t2 8233 // cmov[cond] t2 = t1 8234 // mov EAX = t1 8235 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8236 // bz newMBB 8237 // fallthrough -->nextMBB 8238 // 8239 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8240 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8241 MachineFunction::iterator MBBIter = MBB; 8242 ++MBBIter; 8243 8244 /// First build the CFG 8245 MachineFunction *F = MBB->getParent(); 8246 MachineBasicBlock *thisMBB = MBB; 8247 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8248 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8249 F->insert(MBBIter, newMBB); 8250 F->insert(MBBIter, nextMBB); 8251 8252 // Move all successors of thisMBB to nextMBB 8253 nextMBB->transferSuccessors(thisMBB); 8254 8255 // Update thisMBB to fall through to newMBB 8256 thisMBB->addSuccessor(newMBB); 8257 8258 // newMBB jumps to newMBB and fall through to nextMBB 8259 newMBB->addSuccessor(nextMBB); 8260 newMBB->addSuccessor(newMBB); 8261 8262 DebugLoc dl = mInstr->getDebugLoc(); 8263 // Insert instructions into newMBB based on incoming instruction 8264 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 8265 "unexpected number of operands"); 8266 MachineOperand& destOper = mInstr->getOperand(0); 8267 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8268 int numArgs = mInstr->getNumOperands() - 1; 8269 for (int i=0; i < numArgs; ++i) 8270 argOpers[i] = &mInstr->getOperand(i+1); 8271 8272 // x86 address has 4 operands: base, index, scale, and displacement 8273 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8274 int valArgIndx = lastAddrIndx + 1; 8275 8276 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8277 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8278 for (int i=0; i <= lastAddrIndx; ++i) 8279 (*MIB).addOperand(*argOpers[i]); 8280 8281 // We only support register and immediate values 8282 assert((argOpers[valArgIndx]->isReg() || 8283 argOpers[valArgIndx]->isImm()) && 8284 "invalid operand"); 8285 8286 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8287 if (argOpers[valArgIndx]->isReg()) 8288 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8289 else 8290 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8291 (*MIB).addOperand(*argOpers[valArgIndx]); 8292 8293 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 8294 MIB.addReg(t1); 8295 8296 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8297 MIB.addReg(t1); 8298 MIB.addReg(t2); 8299 8300 // Generate movc 8301 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8302 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8303 MIB.addReg(t2); 8304 MIB.addReg(t1); 8305 8306 // Cmp and exchange if none has modified the memory location 8307 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8308 for (int i=0; i <= lastAddrIndx; ++i) 8309 (*MIB).addOperand(*argOpers[i]); 8310 MIB.addReg(t3); 8311 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8312 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8313 mInstr->memoperands_end()); 8314 8315 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 8316 MIB.addReg(X86::EAX); 8317 8318 // insert branch 8319 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8320 8321 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 8322 return nextMBB; 8323} 8324 8325// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8326// all of this code can be replaced with that in the .td file. 8327MachineBasicBlock * 8328X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8329 unsigned numArgs, bool memArg) const { 8330 8331 MachineFunction *F = BB->getParent(); 8332 DebugLoc dl = MI->getDebugLoc(); 8333 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8334 8335 unsigned Opc; 8336 if (memArg) 8337 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8338 else 8339 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8340 8341 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8342 8343 for (unsigned i = 0; i < numArgs; ++i) { 8344 MachineOperand &Op = MI->getOperand(i+1); 8345 8346 if (!(Op.isReg() && Op.isImplicit())) 8347 MIB.addOperand(Op); 8348 } 8349 8350 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8351 .addReg(X86::XMM0); 8352 8353 F->DeleteMachineInstr(MI); 8354 8355 return BB; 8356} 8357 8358MachineBasicBlock * 8359X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8360 MachineInstr *MI, 8361 MachineBasicBlock *MBB) const { 8362 // Emit code to save XMM registers to the stack. The ABI says that the 8363 // number of registers to save is given in %al, so it's theoretically 8364 // possible to do an indirect jump trick to avoid saving all of them, 8365 // however this code takes a simpler approach and just executes all 8366 // of the stores if %al is non-zero. It's less code, and it's probably 8367 // easier on the hardware branch predictor, and stores aren't all that 8368 // expensive anyway. 8369 8370 // Create the new basic blocks. One block contains all the XMM stores, 8371 // and one block is the final destination regardless of whether any 8372 // stores were performed. 8373 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8374 MachineFunction *F = MBB->getParent(); 8375 MachineFunction::iterator MBBIter = MBB; 8376 ++MBBIter; 8377 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8378 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8379 F->insert(MBBIter, XMMSaveMBB); 8380 F->insert(MBBIter, EndMBB); 8381 8382 // Set up the CFG. 8383 // Move any original successors of MBB to the end block. 8384 EndMBB->transferSuccessors(MBB); 8385 // The original block will now fall through to the XMM save block. 8386 MBB->addSuccessor(XMMSaveMBB); 8387 // The XMMSaveMBB will fall through to the end block. 8388 XMMSaveMBB->addSuccessor(EndMBB); 8389 8390 // Now add the instructions. 8391 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8392 DebugLoc DL = MI->getDebugLoc(); 8393 8394 unsigned CountReg = MI->getOperand(0).getReg(); 8395 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 8396 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 8397 8398 if (!Subtarget->isTargetWin64()) { 8399 // If %al is 0, branch around the XMM save block. 8400 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 8401 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 8402 MBB->addSuccessor(EndMBB); 8403 } 8404 8405 // In the XMM save block, save all the XMM argument registers. 8406 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 8407 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 8408 MachineMemOperand *MMO = 8409 F->getMachineMemOperand( 8410 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 8411 MachineMemOperand::MOStore, Offset, 8412 /*Size=*/16, /*Align=*/16); 8413 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 8414 .addFrameIndex(RegSaveFrameIndex) 8415 .addImm(/*Scale=*/1) 8416 .addReg(/*IndexReg=*/0) 8417 .addImm(/*Disp=*/Offset) 8418 .addReg(/*Segment=*/0) 8419 .addReg(MI->getOperand(i).getReg()) 8420 .addMemOperand(MMO); 8421 } 8422 8423 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8424 8425 return EndMBB; 8426} 8427 8428MachineBasicBlock * 8429X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 8430 MachineBasicBlock *BB, 8431 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8432 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8433 DebugLoc DL = MI->getDebugLoc(); 8434 8435 // To "insert" a SELECT_CC instruction, we actually have to insert the 8436 // diamond control-flow pattern. The incoming instruction knows the 8437 // destination vreg to set, the condition code register to branch on, the 8438 // true/false values to select between, and a branch opcode to use. 8439 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 8440 MachineFunction::iterator It = BB; 8441 ++It; 8442 8443 // thisMBB: 8444 // ... 8445 // TrueVal = ... 8446 // cmpTY ccX, r1, r2 8447 // bCC copy1MBB 8448 // fallthrough --> copy0MBB 8449 MachineBasicBlock *thisMBB = BB; 8450 MachineFunction *F = BB->getParent(); 8451 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 8452 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 8453 unsigned Opc = 8454 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 8455 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 8456 F->insert(It, copy0MBB); 8457 F->insert(It, sinkMBB); 8458 // Update machine-CFG edges by first adding all successors of the current 8459 // block to the new block which will contain the Phi node for the select. 8460 // Also inform sdisel of the edge changes. 8461 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 8462 E = BB->succ_end(); I != E; ++I) { 8463 EM->insert(std::make_pair(*I, sinkMBB)); 8464 sinkMBB->addSuccessor(*I); 8465 } 8466 // Next, remove all successors of the current block, and add the true 8467 // and fallthrough blocks as its successors. 8468 while (!BB->succ_empty()) 8469 BB->removeSuccessor(BB->succ_begin()); 8470 // Add the true and fallthrough blocks as its successors. 8471 BB->addSuccessor(copy0MBB); 8472 BB->addSuccessor(sinkMBB); 8473 8474 // copy0MBB: 8475 // %FalseValue = ... 8476 // # fallthrough to sinkMBB 8477 BB = copy0MBB; 8478 8479 // Update machine-CFG edges 8480 BB->addSuccessor(sinkMBB); 8481 8482 // sinkMBB: 8483 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 8484 // ... 8485 BB = sinkMBB; 8486 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) 8487 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 8488 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 8489 8490 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8491 return BB; 8492} 8493 8494MachineBasicBlock * 8495X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI, 8496 MachineBasicBlock *BB, 8497 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8498 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8499 DebugLoc DL = MI->getDebugLoc(); 8500 MachineFunction *F = BB->getParent(); 8501 8502 // The lowering is pretty easy: we're just emitting the call to _alloca. The 8503 // non-trivial part is impdef of ESP. 8504 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 8505 // mingw-w64. 8506 8507 BuildMI(BB, DL, TII->get(X86::CALLpcrel32)) 8508 .addExternalSymbol("_alloca") 8509 .addReg(X86::EAX, RegState::Implicit) 8510 .addReg(X86::ESP, RegState::Implicit) 8511 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 8512 .addReg(X86::ESP, RegState::Define | RegState::Implicit); 8513 8514 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8515 return BB; 8516} 8517 8518MachineBasicBlock * 8519X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 8520 MachineBasicBlock *BB, 8521 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8522 switch (MI->getOpcode()) { 8523 default: assert(false && "Unexpected instr type to insert"); 8524 case X86::MINGW_ALLOCA: 8525 return EmitLoweredMingwAlloca(MI, BB, EM); 8526 case X86::CMOV_GR8: 8527 case X86::CMOV_V1I64: 8528 case X86::CMOV_FR32: 8529 case X86::CMOV_FR64: 8530 case X86::CMOV_V4F32: 8531 case X86::CMOV_V2F64: 8532 case X86::CMOV_V2I64: 8533 case X86::CMOV_GR16: 8534 case X86::CMOV_GR32: 8535 case X86::CMOV_RFP32: 8536 case X86::CMOV_RFP64: 8537 case X86::CMOV_RFP80: 8538 return EmitLoweredSelect(MI, BB, EM); 8539 8540 case X86::FP32_TO_INT16_IN_MEM: 8541 case X86::FP32_TO_INT32_IN_MEM: 8542 case X86::FP32_TO_INT64_IN_MEM: 8543 case X86::FP64_TO_INT16_IN_MEM: 8544 case X86::FP64_TO_INT32_IN_MEM: 8545 case X86::FP64_TO_INT64_IN_MEM: 8546 case X86::FP80_TO_INT16_IN_MEM: 8547 case X86::FP80_TO_INT32_IN_MEM: 8548 case X86::FP80_TO_INT64_IN_MEM: { 8549 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8550 DebugLoc DL = MI->getDebugLoc(); 8551 8552 // Change the floating point control register to use "round towards zero" 8553 // mode when truncating to an integer value. 8554 MachineFunction *F = BB->getParent(); 8555 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 8556 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); 8557 8558 // Load the old value of the high byte of the control word... 8559 unsigned OldCW = 8560 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 8561 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), 8562 CWFrameIdx); 8563 8564 // Set the high part to be round to zero... 8565 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 8566 .addImm(0xC7F); 8567 8568 // Reload the modified control word now... 8569 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8570 8571 // Restore the memory image of control word to original value 8572 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 8573 .addReg(OldCW); 8574 8575 // Get the X86 opcode to use. 8576 unsigned Opc; 8577 switch (MI->getOpcode()) { 8578 default: llvm_unreachable("illegal opcode!"); 8579 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 8580 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 8581 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 8582 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 8583 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 8584 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 8585 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 8586 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 8587 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 8588 } 8589 8590 X86AddressMode AM; 8591 MachineOperand &Op = MI->getOperand(0); 8592 if (Op.isReg()) { 8593 AM.BaseType = X86AddressMode::RegBase; 8594 AM.Base.Reg = Op.getReg(); 8595 } else { 8596 AM.BaseType = X86AddressMode::FrameIndexBase; 8597 AM.Base.FrameIndex = Op.getIndex(); 8598 } 8599 Op = MI->getOperand(1); 8600 if (Op.isImm()) 8601 AM.Scale = Op.getImm(); 8602 Op = MI->getOperand(2); 8603 if (Op.isImm()) 8604 AM.IndexReg = Op.getImm(); 8605 Op = MI->getOperand(3); 8606 if (Op.isGlobal()) { 8607 AM.GV = Op.getGlobal(); 8608 } else { 8609 AM.Disp = Op.getImm(); 8610 } 8611 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) 8612 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 8613 8614 // Reload the original control word now. 8615 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8616 8617 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8618 return BB; 8619 } 8620 // DBG_VALUE. Only the frame index case is done here. 8621 case X86::DBG_VALUE: { 8622 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8623 DebugLoc DL = MI->getDebugLoc(); 8624 X86AddressMode AM; 8625 MachineFunction *F = BB->getParent(); 8626 AM.BaseType = X86AddressMode::FrameIndexBase; 8627 AM.Base.FrameIndex = MI->getOperand(0).getImm(); 8628 addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM). 8629 addImm(MI->getOperand(1).getImm()). 8630 addMetadata(MI->getOperand(2).getMetadata()); 8631 F->DeleteMachineInstr(MI); // Remove pseudo. 8632 return BB; 8633 } 8634 8635 // String/text processing lowering. 8636 case X86::PCMPISTRM128REG: 8637 return EmitPCMP(MI, BB, 3, false /* in-mem */); 8638 case X86::PCMPISTRM128MEM: 8639 return EmitPCMP(MI, BB, 3, true /* in-mem */); 8640 case X86::PCMPESTRM128REG: 8641 return EmitPCMP(MI, BB, 5, false /* in mem */); 8642 case X86::PCMPESTRM128MEM: 8643 return EmitPCMP(MI, BB, 5, true /* in mem */); 8644 8645 // Atomic Lowering. 8646 case X86::ATOMAND32: 8647 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8648 X86::AND32ri, X86::MOV32rm, 8649 X86::LCMPXCHG32, X86::MOV32rr, 8650 X86::NOT32r, X86::EAX, 8651 X86::GR32RegisterClass); 8652 case X86::ATOMOR32: 8653 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 8654 X86::OR32ri, X86::MOV32rm, 8655 X86::LCMPXCHG32, X86::MOV32rr, 8656 X86::NOT32r, X86::EAX, 8657 X86::GR32RegisterClass); 8658 case X86::ATOMXOR32: 8659 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 8660 X86::XOR32ri, X86::MOV32rm, 8661 X86::LCMPXCHG32, X86::MOV32rr, 8662 X86::NOT32r, X86::EAX, 8663 X86::GR32RegisterClass); 8664 case X86::ATOMNAND32: 8665 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8666 X86::AND32ri, X86::MOV32rm, 8667 X86::LCMPXCHG32, X86::MOV32rr, 8668 X86::NOT32r, X86::EAX, 8669 X86::GR32RegisterClass, true); 8670 case X86::ATOMMIN32: 8671 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 8672 case X86::ATOMMAX32: 8673 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 8674 case X86::ATOMUMIN32: 8675 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 8676 case X86::ATOMUMAX32: 8677 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 8678 8679 case X86::ATOMAND16: 8680 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8681 X86::AND16ri, X86::MOV16rm, 8682 X86::LCMPXCHG16, X86::MOV16rr, 8683 X86::NOT16r, X86::AX, 8684 X86::GR16RegisterClass); 8685 case X86::ATOMOR16: 8686 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 8687 X86::OR16ri, X86::MOV16rm, 8688 X86::LCMPXCHG16, X86::MOV16rr, 8689 X86::NOT16r, X86::AX, 8690 X86::GR16RegisterClass); 8691 case X86::ATOMXOR16: 8692 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 8693 X86::XOR16ri, X86::MOV16rm, 8694 X86::LCMPXCHG16, X86::MOV16rr, 8695 X86::NOT16r, X86::AX, 8696 X86::GR16RegisterClass); 8697 case X86::ATOMNAND16: 8698 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8699 X86::AND16ri, X86::MOV16rm, 8700 X86::LCMPXCHG16, X86::MOV16rr, 8701 X86::NOT16r, X86::AX, 8702 X86::GR16RegisterClass, true); 8703 case X86::ATOMMIN16: 8704 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8705 case X86::ATOMMAX16: 8706 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8707 case X86::ATOMUMIN16: 8708 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8709 case X86::ATOMUMAX16: 8710 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8711 8712 case X86::ATOMAND8: 8713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8714 X86::AND8ri, X86::MOV8rm, 8715 X86::LCMPXCHG8, X86::MOV8rr, 8716 X86::NOT8r, X86::AL, 8717 X86::GR8RegisterClass); 8718 case X86::ATOMOR8: 8719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8720 X86::OR8ri, X86::MOV8rm, 8721 X86::LCMPXCHG8, X86::MOV8rr, 8722 X86::NOT8r, X86::AL, 8723 X86::GR8RegisterClass); 8724 case X86::ATOMXOR8: 8725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8726 X86::XOR8ri, X86::MOV8rm, 8727 X86::LCMPXCHG8, X86::MOV8rr, 8728 X86::NOT8r, X86::AL, 8729 X86::GR8RegisterClass); 8730 case X86::ATOMNAND8: 8731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8732 X86::AND8ri, X86::MOV8rm, 8733 X86::LCMPXCHG8, X86::MOV8rr, 8734 X86::NOT8r, X86::AL, 8735 X86::GR8RegisterClass, true); 8736 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8737 // This group is for 64-bit host. 8738 case X86::ATOMAND64: 8739 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8740 X86::AND64ri32, X86::MOV64rm, 8741 X86::LCMPXCHG64, X86::MOV64rr, 8742 X86::NOT64r, X86::RAX, 8743 X86::GR64RegisterClass); 8744 case X86::ATOMOR64: 8745 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8746 X86::OR64ri32, X86::MOV64rm, 8747 X86::LCMPXCHG64, X86::MOV64rr, 8748 X86::NOT64r, X86::RAX, 8749 X86::GR64RegisterClass); 8750 case X86::ATOMXOR64: 8751 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8752 X86::XOR64ri32, X86::MOV64rm, 8753 X86::LCMPXCHG64, X86::MOV64rr, 8754 X86::NOT64r, X86::RAX, 8755 X86::GR64RegisterClass); 8756 case X86::ATOMNAND64: 8757 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8758 X86::AND64ri32, X86::MOV64rm, 8759 X86::LCMPXCHG64, X86::MOV64rr, 8760 X86::NOT64r, X86::RAX, 8761 X86::GR64RegisterClass, true); 8762 case X86::ATOMMIN64: 8763 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8764 case X86::ATOMMAX64: 8765 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8766 case X86::ATOMUMIN64: 8767 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8768 case X86::ATOMUMAX64: 8769 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8770 8771 // This group does 64-bit operations on a 32-bit host. 8772 case X86::ATOMAND6432: 8773 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8774 X86::AND32rr, X86::AND32rr, 8775 X86::AND32ri, X86::AND32ri, 8776 false); 8777 case X86::ATOMOR6432: 8778 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8779 X86::OR32rr, X86::OR32rr, 8780 X86::OR32ri, X86::OR32ri, 8781 false); 8782 case X86::ATOMXOR6432: 8783 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8784 X86::XOR32rr, X86::XOR32rr, 8785 X86::XOR32ri, X86::XOR32ri, 8786 false); 8787 case X86::ATOMNAND6432: 8788 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8789 X86::AND32rr, X86::AND32rr, 8790 X86::AND32ri, X86::AND32ri, 8791 true); 8792 case X86::ATOMADD6432: 8793 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8794 X86::ADD32rr, X86::ADC32rr, 8795 X86::ADD32ri, X86::ADC32ri, 8796 false); 8797 case X86::ATOMSUB6432: 8798 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8799 X86::SUB32rr, X86::SBB32rr, 8800 X86::SUB32ri, X86::SBB32ri, 8801 false); 8802 case X86::ATOMSWAP6432: 8803 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8804 X86::MOV32rr, X86::MOV32rr, 8805 X86::MOV32ri, X86::MOV32ri, 8806 false); 8807 case X86::VASTART_SAVE_XMM_REGS: 8808 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8809 } 8810} 8811 8812//===----------------------------------------------------------------------===// 8813// X86 Optimization Hooks 8814//===----------------------------------------------------------------------===// 8815 8816void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8817 const APInt &Mask, 8818 APInt &KnownZero, 8819 APInt &KnownOne, 8820 const SelectionDAG &DAG, 8821 unsigned Depth) const { 8822 unsigned Opc = Op.getOpcode(); 8823 assert((Opc >= ISD::BUILTIN_OP_END || 8824 Opc == ISD::INTRINSIC_WO_CHAIN || 8825 Opc == ISD::INTRINSIC_W_CHAIN || 8826 Opc == ISD::INTRINSIC_VOID) && 8827 "Should use MaskedValueIsZero if you don't know whether Op" 8828 " is a target node!"); 8829 8830 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8831 switch (Opc) { 8832 default: break; 8833 case X86ISD::ADD: 8834 case X86ISD::SUB: 8835 case X86ISD::SMUL: 8836 case X86ISD::UMUL: 8837 case X86ISD::INC: 8838 case X86ISD::DEC: 8839 case X86ISD::OR: 8840 case X86ISD::XOR: 8841 case X86ISD::AND: 8842 // These nodes' second result is a boolean. 8843 if (Op.getResNo() == 0) 8844 break; 8845 // Fallthrough 8846 case X86ISD::SETCC: 8847 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8848 Mask.getBitWidth() - 1); 8849 break; 8850 } 8851} 8852 8853/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8854/// node is a GlobalAddress + offset. 8855bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8856 GlobalValue* &GA, int64_t &Offset) const{ 8857 if (N->getOpcode() == X86ISD::Wrapper) { 8858 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8859 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8860 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8861 return true; 8862 } 8863 } 8864 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8865} 8866 8867/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8868/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8869/// if the load addresses are consecutive, non-overlapping, and in the right 8870/// order. 8871static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8872 const TargetLowering &TLI) { 8873 DebugLoc dl = N->getDebugLoc(); 8874 EVT VT = N->getValueType(0); 8875 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8876 8877 if (VT.getSizeInBits() != 128) 8878 return SDValue(); 8879 8880 SmallVector<SDValue, 16> Elts; 8881 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 8882 Elts.push_back(DAG.getShuffleScalarElt(SVN, i)); 8883 8884 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 8885} 8886 8887/// PerformShuffleCombine - Detect vector gather/scatter index generation 8888/// and convert it from being a bunch of shuffles and extracts to a simple 8889/// store and scalar loads to extract the elements. 8890static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 8891 const TargetLowering &TLI) { 8892 SDValue InputVector = N->getOperand(0); 8893 8894 // Only operate on vectors of 4 elements, where the alternative shuffling 8895 // gets to be more expensive. 8896 if (InputVector.getValueType() != MVT::v4i32) 8897 return SDValue(); 8898 8899 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 8900 // single use which is a sign-extend or zero-extend, and all elements are 8901 // used. 8902 SmallVector<SDNode *, 4> Uses; 8903 unsigned ExtractedElements = 0; 8904 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 8905 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 8906 if (UI.getUse().getResNo() != InputVector.getResNo()) 8907 return SDValue(); 8908 8909 SDNode *Extract = *UI; 8910 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8911 return SDValue(); 8912 8913 if (Extract->getValueType(0) != MVT::i32) 8914 return SDValue(); 8915 if (!Extract->hasOneUse()) 8916 return SDValue(); 8917 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 8918 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 8919 return SDValue(); 8920 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 8921 return SDValue(); 8922 8923 // Record which element was extracted. 8924 ExtractedElements |= 8925 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 8926 8927 Uses.push_back(Extract); 8928 } 8929 8930 // If not all the elements were used, this may not be worthwhile. 8931 if (ExtractedElements != 15) 8932 return SDValue(); 8933 8934 // Ok, we've now decided to do the transformation. 8935 DebugLoc dl = InputVector.getDebugLoc(); 8936 8937 // Store the value to a temporary stack slot. 8938 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 8939 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0, 8940 false, false, 0); 8941 8942 // Replace each use (extract) with a load of the appropriate element. 8943 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 8944 UE = Uses.end(); UI != UE; ++UI) { 8945 SDNode *Extract = *UI; 8946 8947 // Compute the element's address. 8948 SDValue Idx = Extract->getOperand(1); 8949 unsigned EltSize = 8950 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 8951 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 8952 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 8953 8954 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr); 8955 8956 // Load the scalar. 8957 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr, 8958 NULL, 0, false, false, 0); 8959 8960 // Replace the exact with the load. 8961 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 8962 } 8963 8964 // The replacement was made in place; don't return anything. 8965 return SDValue(); 8966} 8967 8968/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8969static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8970 const X86Subtarget *Subtarget) { 8971 DebugLoc DL = N->getDebugLoc(); 8972 SDValue Cond = N->getOperand(0); 8973 // Get the LHS/RHS of the select. 8974 SDValue LHS = N->getOperand(1); 8975 SDValue RHS = N->getOperand(2); 8976 8977 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 8978 // instructions match the semantics of the common C idiom x<y?x:y but not 8979 // x<=y?x:y, because of how they handle negative zero (which can be 8980 // ignored in unsafe-math mode). 8981 if (Subtarget->hasSSE2() && 8982 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 8983 Cond.getOpcode() == ISD::SETCC) { 8984 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 8985 8986 unsigned Opcode = 0; 8987 // Check for x CC y ? x : y. 8988 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 8989 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 8990 switch (CC) { 8991 default: break; 8992 case ISD::SETULT: 8993 // Converting this to a min would handle NaNs incorrectly, and swapping 8994 // the operands would cause it to handle comparisons between positive 8995 // and negative zero incorrectly. 8996 if (!FiniteOnlyFPMath() && 8997 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { 8998 if (!UnsafeFPMath && 8999 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9000 break; 9001 std::swap(LHS, RHS); 9002 } 9003 Opcode = X86ISD::FMIN; 9004 break; 9005 case ISD::SETOLE: 9006 // Converting this to a min would handle comparisons between positive 9007 // and negative zero incorrectly. 9008 if (!UnsafeFPMath && 9009 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 9010 break; 9011 Opcode = X86ISD::FMIN; 9012 break; 9013 case ISD::SETULE: 9014 // Converting this to a min would handle both negative zeros and NaNs 9015 // incorrectly, but we can swap the operands to fix both. 9016 std::swap(LHS, RHS); 9017 case ISD::SETOLT: 9018 case ISD::SETLT: 9019 case ISD::SETLE: 9020 Opcode = X86ISD::FMIN; 9021 break; 9022 9023 case ISD::SETOGE: 9024 // Converting this to a max would handle comparisons between positive 9025 // and negative zero incorrectly. 9026 if (!UnsafeFPMath && 9027 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 9028 break; 9029 Opcode = X86ISD::FMAX; 9030 break; 9031 case ISD::SETUGT: 9032 // Converting this to a max would handle NaNs incorrectly, and swapping 9033 // the operands would cause it to handle comparisons between positive 9034 // and negative zero incorrectly. 9035 if (!FiniteOnlyFPMath() && 9036 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { 9037 if (!UnsafeFPMath && 9038 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9039 break; 9040 std::swap(LHS, RHS); 9041 } 9042 Opcode = X86ISD::FMAX; 9043 break; 9044 case ISD::SETUGE: 9045 // Converting this to a max would handle both negative zeros and NaNs 9046 // incorrectly, but we can swap the operands to fix both. 9047 std::swap(LHS, RHS); 9048 case ISD::SETOGT: 9049 case ISD::SETGT: 9050 case ISD::SETGE: 9051 Opcode = X86ISD::FMAX; 9052 break; 9053 } 9054 // Check for x CC y ? y : x -- a min/max with reversed arms. 9055 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 9056 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 9057 switch (CC) { 9058 default: break; 9059 case ISD::SETOGE: 9060 // Converting this to a min would handle comparisons between positive 9061 // and negative zero incorrectly, and swapping the operands would 9062 // cause it to handle NaNs incorrectly. 9063 if (!UnsafeFPMath && 9064 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 9065 if (!FiniteOnlyFPMath() && 9066 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9067 break; 9068 std::swap(LHS, RHS); 9069 } 9070 Opcode = X86ISD::FMIN; 9071 break; 9072 case ISD::SETUGT: 9073 // Converting this to a min would handle NaNs incorrectly. 9074 if (!UnsafeFPMath && 9075 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9076 break; 9077 Opcode = X86ISD::FMIN; 9078 break; 9079 case ISD::SETUGE: 9080 // Converting this to a min would handle both negative zeros and NaNs 9081 // incorrectly, but we can swap the operands to fix both. 9082 std::swap(LHS, RHS); 9083 case ISD::SETOGT: 9084 case ISD::SETGT: 9085 case ISD::SETGE: 9086 Opcode = X86ISD::FMIN; 9087 break; 9088 9089 case ISD::SETULT: 9090 // Converting this to a max would handle NaNs incorrectly. 9091 if (!FiniteOnlyFPMath() && 9092 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9093 break; 9094 Opcode = X86ISD::FMAX; 9095 break; 9096 case ISD::SETOLE: 9097 // Converting this to a max would handle comparisons between positive 9098 // and negative zero incorrectly, and swapping the operands would 9099 // cause it to handle NaNs incorrectly. 9100 if (!UnsafeFPMath && 9101 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 9102 if (!FiniteOnlyFPMath() && 9103 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9104 break; 9105 std::swap(LHS, RHS); 9106 } 9107 Opcode = X86ISD::FMAX; 9108 break; 9109 case ISD::SETULE: 9110 // Converting this to a max would handle both negative zeros and NaNs 9111 // incorrectly, but we can swap the operands to fix both. 9112 std::swap(LHS, RHS); 9113 case ISD::SETOLT: 9114 case ISD::SETLT: 9115 case ISD::SETLE: 9116 Opcode = X86ISD::FMAX; 9117 break; 9118 } 9119 } 9120 9121 if (Opcode) 9122 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 9123 } 9124 9125 // If this is a select between two integer constants, try to do some 9126 // optimizations. 9127 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 9128 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 9129 // Don't do this for crazy integer types. 9130 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 9131 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 9132 // so that TrueC (the true value) is larger than FalseC. 9133 bool NeedsCondInvert = false; 9134 9135 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 9136 // Efficiently invertible. 9137 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 9138 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 9139 isa<ConstantSDNode>(Cond.getOperand(1))))) { 9140 NeedsCondInvert = true; 9141 std::swap(TrueC, FalseC); 9142 } 9143 9144 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 9145 if (FalseC->getAPIntValue() == 0 && 9146 TrueC->getAPIntValue().isPowerOf2()) { 9147 if (NeedsCondInvert) // Invert the condition if needed. 9148 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9149 DAG.getConstant(1, Cond.getValueType())); 9150 9151 // Zero extend the condition if needed. 9152 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 9153 9154 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9155 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 9156 DAG.getConstant(ShAmt, MVT::i8)); 9157 } 9158 9159 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 9160 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9161 if (NeedsCondInvert) // Invert the condition if needed. 9162 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9163 DAG.getConstant(1, Cond.getValueType())); 9164 9165 // Zero extend the condition if needed. 9166 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9167 FalseC->getValueType(0), Cond); 9168 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9169 SDValue(FalseC, 0)); 9170 } 9171 9172 // Optimize cases that will turn into an LEA instruction. This requires 9173 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9174 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9175 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9176 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9177 9178 bool isFastMultiplier = false; 9179 if (Diff < 10) { 9180 switch ((unsigned char)Diff) { 9181 default: break; 9182 case 1: // result = add base, cond 9183 case 2: // result = lea base( , cond*2) 9184 case 3: // result = lea base(cond, cond*2) 9185 case 4: // result = lea base( , cond*4) 9186 case 5: // result = lea base(cond, cond*4) 9187 case 8: // result = lea base( , cond*8) 9188 case 9: // result = lea base(cond, cond*8) 9189 isFastMultiplier = true; 9190 break; 9191 } 9192 } 9193 9194 if (isFastMultiplier) { 9195 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9196 if (NeedsCondInvert) // Invert the condition if needed. 9197 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9198 DAG.getConstant(1, Cond.getValueType())); 9199 9200 // Zero extend the condition if needed. 9201 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9202 Cond); 9203 // Scale the condition by the difference. 9204 if (Diff != 1) 9205 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9206 DAG.getConstant(Diff, Cond.getValueType())); 9207 9208 // Add the base if non-zero. 9209 if (FalseC->getAPIntValue() != 0) 9210 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9211 SDValue(FalseC, 0)); 9212 return Cond; 9213 } 9214 } 9215 } 9216 } 9217 9218 return SDValue(); 9219} 9220 9221/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9222static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9223 TargetLowering::DAGCombinerInfo &DCI) { 9224 DebugLoc DL = N->getDebugLoc(); 9225 9226 // If the flag operand isn't dead, don't touch this CMOV. 9227 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9228 return SDValue(); 9229 9230 // If this is a select between two integer constants, try to do some 9231 // optimizations. Note that the operands are ordered the opposite of SELECT 9232 // operands. 9233 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9234 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9235 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9236 // larger than FalseC (the false value). 9237 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9238 9239 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9240 CC = X86::GetOppositeBranchCondition(CC); 9241 std::swap(TrueC, FalseC); 9242 } 9243 9244 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9245 // This is efficient for any integer data type (including i8/i16) and 9246 // shift amount. 9247 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9248 SDValue Cond = N->getOperand(3); 9249 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9250 DAG.getConstant(CC, MVT::i8), Cond); 9251 9252 // Zero extend the condition if needed. 9253 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9254 9255 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9256 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9257 DAG.getConstant(ShAmt, MVT::i8)); 9258 if (N->getNumValues() == 2) // Dead flag value? 9259 return DCI.CombineTo(N, Cond, SDValue()); 9260 return Cond; 9261 } 9262 9263 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9264 // for any integer data type, including i8/i16. 9265 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9266 SDValue Cond = N->getOperand(3); 9267 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9268 DAG.getConstant(CC, MVT::i8), Cond); 9269 9270 // Zero extend the condition if needed. 9271 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9272 FalseC->getValueType(0), Cond); 9273 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9274 SDValue(FalseC, 0)); 9275 9276 if (N->getNumValues() == 2) // Dead flag value? 9277 return DCI.CombineTo(N, Cond, SDValue()); 9278 return Cond; 9279 } 9280 9281 // Optimize cases that will turn into an LEA instruction. This requires 9282 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9283 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9284 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9285 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9286 9287 bool isFastMultiplier = false; 9288 if (Diff < 10) { 9289 switch ((unsigned char)Diff) { 9290 default: break; 9291 case 1: // result = add base, cond 9292 case 2: // result = lea base( , cond*2) 9293 case 3: // result = lea base(cond, cond*2) 9294 case 4: // result = lea base( , cond*4) 9295 case 5: // result = lea base(cond, cond*4) 9296 case 8: // result = lea base( , cond*8) 9297 case 9: // result = lea base(cond, cond*8) 9298 isFastMultiplier = true; 9299 break; 9300 } 9301 } 9302 9303 if (isFastMultiplier) { 9304 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9305 SDValue Cond = N->getOperand(3); 9306 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9307 DAG.getConstant(CC, MVT::i8), Cond); 9308 // Zero extend the condition if needed. 9309 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9310 Cond); 9311 // Scale the condition by the difference. 9312 if (Diff != 1) 9313 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9314 DAG.getConstant(Diff, Cond.getValueType())); 9315 9316 // Add the base if non-zero. 9317 if (FalseC->getAPIntValue() != 0) 9318 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9319 SDValue(FalseC, 0)); 9320 if (N->getNumValues() == 2) // Dead flag value? 9321 return DCI.CombineTo(N, Cond, SDValue()); 9322 return Cond; 9323 } 9324 } 9325 } 9326 } 9327 return SDValue(); 9328} 9329 9330 9331/// PerformMulCombine - Optimize a single multiply with constant into two 9332/// in order to implement it with two cheaper instructions, e.g. 9333/// LEA + SHL, LEA + LEA. 9334static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9335 TargetLowering::DAGCombinerInfo &DCI) { 9336 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9337 return SDValue(); 9338 9339 EVT VT = N->getValueType(0); 9340 if (VT != MVT::i64) 9341 return SDValue(); 9342 9343 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9344 if (!C) 9345 return SDValue(); 9346 uint64_t MulAmt = C->getZExtValue(); 9347 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 9348 return SDValue(); 9349 9350 uint64_t MulAmt1 = 0; 9351 uint64_t MulAmt2 = 0; 9352 if ((MulAmt % 9) == 0) { 9353 MulAmt1 = 9; 9354 MulAmt2 = MulAmt / 9; 9355 } else if ((MulAmt % 5) == 0) { 9356 MulAmt1 = 5; 9357 MulAmt2 = MulAmt / 5; 9358 } else if ((MulAmt % 3) == 0) { 9359 MulAmt1 = 3; 9360 MulAmt2 = MulAmt / 3; 9361 } 9362 if (MulAmt2 && 9363 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 9364 DebugLoc DL = N->getDebugLoc(); 9365 9366 if (isPowerOf2_64(MulAmt2) && 9367 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 9368 // If second multiplifer is pow2, issue it first. We want the multiply by 9369 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 9370 // is an add. 9371 std::swap(MulAmt1, MulAmt2); 9372 9373 SDValue NewMul; 9374 if (isPowerOf2_64(MulAmt1)) 9375 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 9376 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 9377 else 9378 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 9379 DAG.getConstant(MulAmt1, VT)); 9380 9381 if (isPowerOf2_64(MulAmt2)) 9382 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 9383 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 9384 else 9385 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 9386 DAG.getConstant(MulAmt2, VT)); 9387 9388 // Do not add new nodes to DAG combiner worklist. 9389 DCI.CombineTo(N, NewMul, false); 9390 } 9391 return SDValue(); 9392} 9393 9394static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 9395 SDValue N0 = N->getOperand(0); 9396 SDValue N1 = N->getOperand(1); 9397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 9398 EVT VT = N0.getValueType(); 9399 9400 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 9401 // since the result of setcc_c is all zero's or all ones. 9402 if (N1C && N0.getOpcode() == ISD::AND && 9403 N0.getOperand(1).getOpcode() == ISD::Constant) { 9404 SDValue N00 = N0.getOperand(0); 9405 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 9406 ((N00.getOpcode() == ISD::ANY_EXTEND || 9407 N00.getOpcode() == ISD::ZERO_EXTEND) && 9408 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 9409 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 9410 APInt ShAmt = N1C->getAPIntValue(); 9411 Mask = Mask.shl(ShAmt); 9412 if (Mask != 0) 9413 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9414 N00, DAG.getConstant(Mask, VT)); 9415 } 9416 } 9417 9418 return SDValue(); 9419} 9420 9421/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 9422/// when possible. 9423static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 9424 const X86Subtarget *Subtarget) { 9425 EVT VT = N->getValueType(0); 9426 if (!VT.isVector() && VT.isInteger() && 9427 N->getOpcode() == ISD::SHL) 9428 return PerformSHLCombine(N, DAG); 9429 9430 // On X86 with SSE2 support, we can transform this to a vector shift if 9431 // all elements are shifted by the same amount. We can't do this in legalize 9432 // because the a constant vector is typically transformed to a constant pool 9433 // so we have no knowledge of the shift amount. 9434 if (!Subtarget->hasSSE2()) 9435 return SDValue(); 9436 9437 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 9438 return SDValue(); 9439 9440 SDValue ShAmtOp = N->getOperand(1); 9441 EVT EltVT = VT.getVectorElementType(); 9442 DebugLoc DL = N->getDebugLoc(); 9443 SDValue BaseShAmt = SDValue(); 9444 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 9445 unsigned NumElts = VT.getVectorNumElements(); 9446 unsigned i = 0; 9447 for (; i != NumElts; ++i) { 9448 SDValue Arg = ShAmtOp.getOperand(i); 9449 if (Arg.getOpcode() == ISD::UNDEF) continue; 9450 BaseShAmt = Arg; 9451 break; 9452 } 9453 for (; i != NumElts; ++i) { 9454 SDValue Arg = ShAmtOp.getOperand(i); 9455 if (Arg.getOpcode() == ISD::UNDEF) continue; 9456 if (Arg != BaseShAmt) { 9457 return SDValue(); 9458 } 9459 } 9460 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 9461 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 9462 SDValue InVec = ShAmtOp.getOperand(0); 9463 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 9464 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 9465 unsigned i = 0; 9466 for (; i != NumElts; ++i) { 9467 SDValue Arg = InVec.getOperand(i); 9468 if (Arg.getOpcode() == ISD::UNDEF) continue; 9469 BaseShAmt = Arg; 9470 break; 9471 } 9472 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 9473 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 9474 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 9475 if (C->getZExtValue() == SplatIdx) 9476 BaseShAmt = InVec.getOperand(1); 9477 } 9478 } 9479 if (BaseShAmt.getNode() == 0) 9480 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 9481 DAG.getIntPtrConstant(0)); 9482 } else 9483 return SDValue(); 9484 9485 // The shift amount is an i32. 9486 if (EltVT.bitsGT(MVT::i32)) 9487 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 9488 else if (EltVT.bitsLT(MVT::i32)) 9489 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 9490 9491 // The shift amount is identical so we can do a vector shift. 9492 SDValue ValOp = N->getOperand(0); 9493 switch (N->getOpcode()) { 9494 default: 9495 llvm_unreachable("Unknown shift opcode!"); 9496 break; 9497 case ISD::SHL: 9498 if (VT == MVT::v2i64) 9499 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9500 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9501 ValOp, BaseShAmt); 9502 if (VT == MVT::v4i32) 9503 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9504 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9505 ValOp, BaseShAmt); 9506 if (VT == MVT::v8i16) 9507 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9508 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9509 ValOp, BaseShAmt); 9510 break; 9511 case ISD::SRA: 9512 if (VT == MVT::v4i32) 9513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9514 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9515 ValOp, BaseShAmt); 9516 if (VT == MVT::v8i16) 9517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9518 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9519 ValOp, BaseShAmt); 9520 break; 9521 case ISD::SRL: 9522 if (VT == MVT::v2i64) 9523 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9524 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9525 ValOp, BaseShAmt); 9526 if (VT == MVT::v4i32) 9527 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9528 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9529 ValOp, BaseShAmt); 9530 if (VT == MVT::v8i16) 9531 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9532 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9533 ValOp, BaseShAmt); 9534 break; 9535 } 9536 return SDValue(); 9537} 9538 9539static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 9540 const X86Subtarget *Subtarget) { 9541 EVT VT = N->getValueType(0); 9542 if (VT != MVT::i64 || !Subtarget->is64Bit()) 9543 return SDValue(); 9544 9545 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 9546 SDValue N0 = N->getOperand(0); 9547 SDValue N1 = N->getOperand(1); 9548 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 9549 std::swap(N0, N1); 9550 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 9551 return SDValue(); 9552 9553 SDValue ShAmt0 = N0.getOperand(1); 9554 if (ShAmt0.getValueType() != MVT::i8) 9555 return SDValue(); 9556 SDValue ShAmt1 = N1.getOperand(1); 9557 if (ShAmt1.getValueType() != MVT::i8) 9558 return SDValue(); 9559 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 9560 ShAmt0 = ShAmt0.getOperand(0); 9561 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 9562 ShAmt1 = ShAmt1.getOperand(0); 9563 9564 DebugLoc DL = N->getDebugLoc(); 9565 unsigned Opc = X86ISD::SHLD; 9566 SDValue Op0 = N0.getOperand(0); 9567 SDValue Op1 = N1.getOperand(0); 9568 if (ShAmt0.getOpcode() == ISD::SUB) { 9569 Opc = X86ISD::SHRD; 9570 std::swap(Op0, Op1); 9571 std::swap(ShAmt0, ShAmt1); 9572 } 9573 9574 if (ShAmt1.getOpcode() == ISD::SUB) { 9575 SDValue Sum = ShAmt1.getOperand(0); 9576 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 9577 if (SumC->getSExtValue() == 64 && 9578 ShAmt1.getOperand(1) == ShAmt0) 9579 return DAG.getNode(Opc, DL, VT, 9580 Op0, Op1, 9581 DAG.getNode(ISD::TRUNCATE, DL, 9582 MVT::i8, ShAmt0)); 9583 } 9584 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 9585 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 9586 if (ShAmt0C && 9587 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64) 9588 return DAG.getNode(Opc, DL, VT, 9589 N0.getOperand(0), N1.getOperand(0), 9590 DAG.getNode(ISD::TRUNCATE, DL, 9591 MVT::i8, ShAmt0)); 9592 } 9593 9594 return SDValue(); 9595} 9596 9597/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 9598static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 9599 const X86Subtarget *Subtarget) { 9600 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 9601 // the FP state in cases where an emms may be missing. 9602 // A preferable solution to the general problem is to figure out the right 9603 // places to insert EMMS. This qualifies as a quick hack. 9604 9605 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 9606 StoreSDNode *St = cast<StoreSDNode>(N); 9607 EVT VT = St->getValue().getValueType(); 9608 if (VT.getSizeInBits() != 64) 9609 return SDValue(); 9610 9611 const Function *F = DAG.getMachineFunction().getFunction(); 9612 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 9613 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 9614 && Subtarget->hasSSE2(); 9615 if ((VT.isVector() || 9616 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 9617 isa<LoadSDNode>(St->getValue()) && 9618 !cast<LoadSDNode>(St->getValue())->isVolatile() && 9619 St->getChain().hasOneUse() && !St->isVolatile()) { 9620 SDNode* LdVal = St->getValue().getNode(); 9621 LoadSDNode *Ld = 0; 9622 int TokenFactorIndex = -1; 9623 SmallVector<SDValue, 8> Ops; 9624 SDNode* ChainVal = St->getChain().getNode(); 9625 // Must be a store of a load. We currently handle two cases: the load 9626 // is a direct child, and it's under an intervening TokenFactor. It is 9627 // possible to dig deeper under nested TokenFactors. 9628 if (ChainVal == LdVal) 9629 Ld = cast<LoadSDNode>(St->getChain()); 9630 else if (St->getValue().hasOneUse() && 9631 ChainVal->getOpcode() == ISD::TokenFactor) { 9632 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 9633 if (ChainVal->getOperand(i).getNode() == LdVal) { 9634 TokenFactorIndex = i; 9635 Ld = cast<LoadSDNode>(St->getValue()); 9636 } else 9637 Ops.push_back(ChainVal->getOperand(i)); 9638 } 9639 } 9640 9641 if (!Ld || !ISD::isNormalLoad(Ld)) 9642 return SDValue(); 9643 9644 // If this is not the MMX case, i.e. we are just turning i64 load/store 9645 // into f64 load/store, avoid the transformation if there are multiple 9646 // uses of the loaded value. 9647 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 9648 return SDValue(); 9649 9650 DebugLoc LdDL = Ld->getDebugLoc(); 9651 DebugLoc StDL = N->getDebugLoc(); 9652 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 9653 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 9654 // pair instead. 9655 if (Subtarget->is64Bit() || F64IsLegal) { 9656 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 9657 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 9658 Ld->getBasePtr(), Ld->getSrcValue(), 9659 Ld->getSrcValueOffset(), Ld->isVolatile(), 9660 Ld->isNonTemporal(), Ld->getAlignment()); 9661 SDValue NewChain = NewLd.getValue(1); 9662 if (TokenFactorIndex != -1) { 9663 Ops.push_back(NewChain); 9664 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9665 Ops.size()); 9666 } 9667 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 9668 St->getSrcValue(), St->getSrcValueOffset(), 9669 St->isVolatile(), St->isNonTemporal(), 9670 St->getAlignment()); 9671 } 9672 9673 // Otherwise, lower to two pairs of 32-bit loads / stores. 9674 SDValue LoAddr = Ld->getBasePtr(); 9675 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 9676 DAG.getConstant(4, MVT::i32)); 9677 9678 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 9679 Ld->getSrcValue(), Ld->getSrcValueOffset(), 9680 Ld->isVolatile(), Ld->isNonTemporal(), 9681 Ld->getAlignment()); 9682 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 9683 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 9684 Ld->isVolatile(), Ld->isNonTemporal(), 9685 MinAlign(Ld->getAlignment(), 4)); 9686 9687 SDValue NewChain = LoLd.getValue(1); 9688 if (TokenFactorIndex != -1) { 9689 Ops.push_back(LoLd); 9690 Ops.push_back(HiLd); 9691 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9692 Ops.size()); 9693 } 9694 9695 LoAddr = St->getBasePtr(); 9696 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 9697 DAG.getConstant(4, MVT::i32)); 9698 9699 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 9700 St->getSrcValue(), St->getSrcValueOffset(), 9701 St->isVolatile(), St->isNonTemporal(), 9702 St->getAlignment()); 9703 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 9704 St->getSrcValue(), 9705 St->getSrcValueOffset() + 4, 9706 St->isVolatile(), 9707 St->isNonTemporal(), 9708 MinAlign(St->getAlignment(), 4)); 9709 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 9710 } 9711 return SDValue(); 9712} 9713 9714/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 9715/// X86ISD::FXOR nodes. 9716static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 9717 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 9718 // F[X]OR(0.0, x) -> x 9719 // F[X]OR(x, 0.0) -> x 9720 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9721 if (C->getValueAPF().isPosZero()) 9722 return N->getOperand(1); 9723 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9724 if (C->getValueAPF().isPosZero()) 9725 return N->getOperand(0); 9726 return SDValue(); 9727} 9728 9729/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 9730static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 9731 // FAND(0.0, x) -> 0.0 9732 // FAND(x, 0.0) -> 0.0 9733 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9734 if (C->getValueAPF().isPosZero()) 9735 return N->getOperand(0); 9736 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9737 if (C->getValueAPF().isPosZero()) 9738 return N->getOperand(1); 9739 return SDValue(); 9740} 9741 9742static SDValue PerformBTCombine(SDNode *N, 9743 SelectionDAG &DAG, 9744 TargetLowering::DAGCombinerInfo &DCI) { 9745 // BT ignores high bits in the bit index operand. 9746 SDValue Op1 = N->getOperand(1); 9747 if (Op1.hasOneUse()) { 9748 unsigned BitWidth = Op1.getValueSizeInBits(); 9749 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 9750 APInt KnownZero, KnownOne; 9751 TargetLowering::TargetLoweringOpt TLO(DAG); 9752 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9753 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 9754 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 9755 DCI.CommitTargetLoweringOpt(TLO); 9756 } 9757 return SDValue(); 9758} 9759 9760static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 9761 SDValue Op = N->getOperand(0); 9762 if (Op.getOpcode() == ISD::BIT_CONVERT) 9763 Op = Op.getOperand(0); 9764 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 9765 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 9766 VT.getVectorElementType().getSizeInBits() == 9767 OpVT.getVectorElementType().getSizeInBits()) { 9768 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 9769 } 9770 return SDValue(); 9771} 9772 9773// On X86 and X86-64, atomic operations are lowered to locked instructions. 9774// Locked instructions, in turn, have implicit fence semantics (all memory 9775// operations are flushed before issuing the locked instruction, and the 9776// are not buffered), so we can fold away the common pattern of 9777// fence-atomic-fence. 9778static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 9779 SDValue atomic = N->getOperand(0); 9780 switch (atomic.getOpcode()) { 9781 case ISD::ATOMIC_CMP_SWAP: 9782 case ISD::ATOMIC_SWAP: 9783 case ISD::ATOMIC_LOAD_ADD: 9784 case ISD::ATOMIC_LOAD_SUB: 9785 case ISD::ATOMIC_LOAD_AND: 9786 case ISD::ATOMIC_LOAD_OR: 9787 case ISD::ATOMIC_LOAD_XOR: 9788 case ISD::ATOMIC_LOAD_NAND: 9789 case ISD::ATOMIC_LOAD_MIN: 9790 case ISD::ATOMIC_LOAD_MAX: 9791 case ISD::ATOMIC_LOAD_UMIN: 9792 case ISD::ATOMIC_LOAD_UMAX: 9793 break; 9794 default: 9795 return SDValue(); 9796 } 9797 9798 SDValue fence = atomic.getOperand(0); 9799 if (fence.getOpcode() != ISD::MEMBARRIER) 9800 return SDValue(); 9801 9802 switch (atomic.getOpcode()) { 9803 case ISD::ATOMIC_CMP_SWAP: 9804 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9805 atomic.getOperand(1), atomic.getOperand(2), 9806 atomic.getOperand(3)); 9807 case ISD::ATOMIC_SWAP: 9808 case ISD::ATOMIC_LOAD_ADD: 9809 case ISD::ATOMIC_LOAD_SUB: 9810 case ISD::ATOMIC_LOAD_AND: 9811 case ISD::ATOMIC_LOAD_OR: 9812 case ISD::ATOMIC_LOAD_XOR: 9813 case ISD::ATOMIC_LOAD_NAND: 9814 case ISD::ATOMIC_LOAD_MIN: 9815 case ISD::ATOMIC_LOAD_MAX: 9816 case ISD::ATOMIC_LOAD_UMIN: 9817 case ISD::ATOMIC_LOAD_UMAX: 9818 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9819 atomic.getOperand(1), atomic.getOperand(2)); 9820 default: 9821 return SDValue(); 9822 } 9823} 9824 9825static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 9826 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 9827 // (and (i32 x86isd::setcc_carry), 1) 9828 // This eliminates the zext. This transformation is necessary because 9829 // ISD::SETCC is always legalized to i8. 9830 DebugLoc dl = N->getDebugLoc(); 9831 SDValue N0 = N->getOperand(0); 9832 EVT VT = N->getValueType(0); 9833 if (N0.getOpcode() == ISD::AND && 9834 N0.hasOneUse() && 9835 N0.getOperand(0).hasOneUse()) { 9836 SDValue N00 = N0.getOperand(0); 9837 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 9838 return SDValue(); 9839 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 9840 if (!C || C->getZExtValue() != 1) 9841 return SDValue(); 9842 return DAG.getNode(ISD::AND, dl, VT, 9843 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 9844 N00.getOperand(0), N00.getOperand(1)), 9845 DAG.getConstant(1, VT)); 9846 } 9847 9848 return SDValue(); 9849} 9850 9851SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9852 DAGCombinerInfo &DCI) const { 9853 SelectionDAG &DAG = DCI.DAG; 9854 switch (N->getOpcode()) { 9855 default: break; 9856 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9857 case ISD::EXTRACT_VECTOR_ELT: 9858 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 9859 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9860 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9861 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9862 case ISD::SHL: 9863 case ISD::SRA: 9864 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9865 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget); 9866 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9867 case X86ISD::FXOR: 9868 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9869 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9870 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9871 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9872 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 9873 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 9874 } 9875 9876 return SDValue(); 9877} 9878 9879//===----------------------------------------------------------------------===// 9880// X86 Inline Assembly Support 9881//===----------------------------------------------------------------------===// 9882 9883static bool LowerToBSwap(CallInst *CI) { 9884 // FIXME: this should verify that we are targetting a 486 or better. If not, 9885 // we will turn this bswap into something that will be lowered to logical ops 9886 // instead of emitting the bswap asm. For now, we don't support 486 or lower 9887 // so don't worry about this. 9888 9889 // Verify this is a simple bswap. 9890 if (CI->getNumOperands() != 2 || 9891 CI->getType() != CI->getOperand(1)->getType() || 9892 !CI->getType()->isIntegerTy()) 9893 return false; 9894 9895 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9896 if (!Ty || Ty->getBitWidth() % 16 != 0) 9897 return false; 9898 9899 // Okay, we can do this xform, do so now. 9900 const Type *Tys[] = { Ty }; 9901 Module *M = CI->getParent()->getParent()->getParent(); 9902 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 9903 9904 Value *Op = CI->getOperand(1); 9905 Op = CallInst::Create(Int, Op, CI->getName(), CI); 9906 9907 CI->replaceAllUsesWith(Op); 9908 CI->eraseFromParent(); 9909 return true; 9910} 9911 9912bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 9913 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9914 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 9915 9916 std::string AsmStr = IA->getAsmString(); 9917 9918 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 9919 SmallVector<StringRef, 4> AsmPieces; 9920 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 9921 9922 switch (AsmPieces.size()) { 9923 default: return false; 9924 case 1: 9925 AsmStr = AsmPieces[0]; 9926 AsmPieces.clear(); 9927 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 9928 9929 // bswap $0 9930 if (AsmPieces.size() == 2 && 9931 (AsmPieces[0] == "bswap" || 9932 AsmPieces[0] == "bswapq" || 9933 AsmPieces[0] == "bswapl") && 9934 (AsmPieces[1] == "$0" || 9935 AsmPieces[1] == "${0:q}")) { 9936 // No need to check constraints, nothing other than the equivalent of 9937 // "=r,0" would be valid here. 9938 return LowerToBSwap(CI); 9939 } 9940 // rorw $$8, ${0:w} --> llvm.bswap.i16 9941 if (CI->getType()->isIntegerTy(16) && 9942 AsmPieces.size() == 3 && 9943 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 9944 AsmPieces[1] == "$$8," && 9945 AsmPieces[2] == "${0:w}" && 9946 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 9947 AsmPieces.clear(); 9948 const std::string &Constraints = IA->getConstraintString(); 9949 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 9950 std::sort(AsmPieces.begin(), AsmPieces.end()); 9951 if (AsmPieces.size() == 4 && 9952 AsmPieces[0] == "~{cc}" && 9953 AsmPieces[1] == "~{dirflag}" && 9954 AsmPieces[2] == "~{flags}" && 9955 AsmPieces[3] == "~{fpsr}") { 9956 return LowerToBSwap(CI); 9957 } 9958 } 9959 break; 9960 case 3: 9961 if (CI->getType()->isIntegerTy(64) && 9962 Constraints.size() >= 2 && 9963 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 9964 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 9965 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 9966 SmallVector<StringRef, 4> Words; 9967 SplitString(AsmPieces[0], Words, " \t"); 9968 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 9969 Words.clear(); 9970 SplitString(AsmPieces[1], Words, " \t"); 9971 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 9972 Words.clear(); 9973 SplitString(AsmPieces[2], Words, " \t,"); 9974 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 9975 Words[2] == "%edx") { 9976 return LowerToBSwap(CI); 9977 } 9978 } 9979 } 9980 } 9981 break; 9982 } 9983 return false; 9984} 9985 9986 9987 9988/// getConstraintType - Given a constraint letter, return the type of 9989/// constraint it is for this target. 9990X86TargetLowering::ConstraintType 9991X86TargetLowering::getConstraintType(const std::string &Constraint) const { 9992 if (Constraint.size() == 1) { 9993 switch (Constraint[0]) { 9994 case 'A': 9995 return C_Register; 9996 case 'f': 9997 case 'r': 9998 case 'R': 9999 case 'l': 10000 case 'q': 10001 case 'Q': 10002 case 'x': 10003 case 'y': 10004 case 'Y': 10005 return C_RegisterClass; 10006 case 'e': 10007 case 'Z': 10008 return C_Other; 10009 default: 10010 break; 10011 } 10012 } 10013 return TargetLowering::getConstraintType(Constraint); 10014} 10015 10016/// LowerXConstraint - try to replace an X constraint, which matches anything, 10017/// with another that has more specific requirements based on the type of the 10018/// corresponding operand. 10019const char *X86TargetLowering:: 10020LowerXConstraint(EVT ConstraintVT) const { 10021 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 10022 // 'f' like normal targets. 10023 if (ConstraintVT.isFloatingPoint()) { 10024 if (Subtarget->hasSSE2()) 10025 return "Y"; 10026 if (Subtarget->hasSSE1()) 10027 return "x"; 10028 } 10029 10030 return TargetLowering::LowerXConstraint(ConstraintVT); 10031} 10032 10033/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 10034/// vector. If it is invalid, don't add anything to Ops. 10035void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 10036 char Constraint, 10037 bool hasMemory, 10038 std::vector<SDValue>&Ops, 10039 SelectionDAG &DAG) const { 10040 SDValue Result(0, 0); 10041 10042 switch (Constraint) { 10043 default: break; 10044 case 'I': 10045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10046 if (C->getZExtValue() <= 31) { 10047 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10048 break; 10049 } 10050 } 10051 return; 10052 case 'J': 10053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10054 if (C->getZExtValue() <= 63) { 10055 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10056 break; 10057 } 10058 } 10059 return; 10060 case 'K': 10061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10062 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 10063 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10064 break; 10065 } 10066 } 10067 return; 10068 case 'N': 10069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10070 if (C->getZExtValue() <= 255) { 10071 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10072 break; 10073 } 10074 } 10075 return; 10076 case 'e': { 10077 // 32-bit signed value 10078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10079 const ConstantInt *CI = C->getConstantIntValue(); 10080 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10081 C->getSExtValue())) { 10082 // Widen to 64 bits here to get it sign extended. 10083 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 10084 break; 10085 } 10086 // FIXME gcc accepts some relocatable values here too, but only in certain 10087 // memory models; it's complicated. 10088 } 10089 return; 10090 } 10091 case 'Z': { 10092 // 32-bit unsigned value 10093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10094 const ConstantInt *CI = C->getConstantIntValue(); 10095 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10096 C->getZExtValue())) { 10097 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10098 break; 10099 } 10100 } 10101 // FIXME gcc accepts some relocatable values here too, but only in certain 10102 // memory models; it's complicated. 10103 return; 10104 } 10105 case 'i': { 10106 // Literal immediates are always ok. 10107 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 10108 // Widen to 64 bits here to get it sign extended. 10109 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 10110 break; 10111 } 10112 10113 // If we are in non-pic codegen mode, we allow the address of a global (with 10114 // an optional displacement) to be used with 'i'. 10115 GlobalAddressSDNode *GA = 0; 10116 int64_t Offset = 0; 10117 10118 // Match either (GA), (GA+C), (GA+C1+C2), etc. 10119 while (1) { 10120 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 10121 Offset += GA->getOffset(); 10122 break; 10123 } else if (Op.getOpcode() == ISD::ADD) { 10124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10125 Offset += C->getZExtValue(); 10126 Op = Op.getOperand(0); 10127 continue; 10128 } 10129 } else if (Op.getOpcode() == ISD::SUB) { 10130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10131 Offset += -C->getZExtValue(); 10132 Op = Op.getOperand(0); 10133 continue; 10134 } 10135 } 10136 10137 // Otherwise, this isn't something we can handle, reject it. 10138 return; 10139 } 10140 10141 GlobalValue *GV = GA->getGlobal(); 10142 // If we require an extra load to get this address, as in PIC mode, we 10143 // can't accept it. 10144 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10145 getTargetMachine()))) 10146 return; 10147 10148 if (hasMemory) 10149 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 10150 else 10151 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 10152 Result = Op; 10153 break; 10154 } 10155 } 10156 10157 if (Result.getNode()) { 10158 Ops.push_back(Result); 10159 return; 10160 } 10161 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 10162 Ops, DAG); 10163} 10164 10165std::vector<unsigned> X86TargetLowering:: 10166getRegClassForInlineAsmConstraint(const std::string &Constraint, 10167 EVT VT) const { 10168 if (Constraint.size() == 1) { 10169 // FIXME: not handling fp-stack yet! 10170 switch (Constraint[0]) { // GCC X86 Constraint Letters 10171 default: break; // Unknown constraint letter 10172 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 10173 if (Subtarget->is64Bit()) { 10174 if (VT == MVT::i32) 10175 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 10176 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 10177 X86::R10D,X86::R11D,X86::R12D, 10178 X86::R13D,X86::R14D,X86::R15D, 10179 X86::EBP, X86::ESP, 0); 10180 else if (VT == MVT::i16) 10181 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10182 X86::SI, X86::DI, X86::R8W,X86::R9W, 10183 X86::R10W,X86::R11W,X86::R12W, 10184 X86::R13W,X86::R14W,X86::R15W, 10185 X86::BP, X86::SP, 0); 10186 else if (VT == MVT::i8) 10187 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10188 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10189 X86::R10B,X86::R11B,X86::R12B, 10190 X86::R13B,X86::R14B,X86::R15B, 10191 X86::BPL, X86::SPL, 0); 10192 10193 else if (VT == MVT::i64) 10194 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10195 X86::RSI, X86::RDI, X86::R8, X86::R9, 10196 X86::R10, X86::R11, X86::R12, 10197 X86::R13, X86::R14, X86::R15, 10198 X86::RBP, X86::RSP, 0); 10199 10200 break; 10201 } 10202 // 32-bit fallthrough 10203 case 'Q': // Q_REGS 10204 if (VT == MVT::i32) 10205 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10206 else if (VT == MVT::i16) 10207 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10208 else if (VT == MVT::i8) 10209 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10210 else if (VT == MVT::i64) 10211 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10212 break; 10213 } 10214 } 10215 10216 return std::vector<unsigned>(); 10217} 10218 10219std::pair<unsigned, const TargetRegisterClass*> 10220X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10221 EVT VT) const { 10222 // First, see if this is a constraint that directly corresponds to an LLVM 10223 // register class. 10224 if (Constraint.size() == 1) { 10225 // GCC Constraint Letters 10226 switch (Constraint[0]) { 10227 default: break; 10228 case 'r': // GENERAL_REGS 10229 case 'l': // INDEX_REGS 10230 if (VT == MVT::i8) 10231 return std::make_pair(0U, X86::GR8RegisterClass); 10232 if (VT == MVT::i16) 10233 return std::make_pair(0U, X86::GR16RegisterClass); 10234 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10235 return std::make_pair(0U, X86::GR32RegisterClass); 10236 return std::make_pair(0U, X86::GR64RegisterClass); 10237 case 'R': // LEGACY_REGS 10238 if (VT == MVT::i8) 10239 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10240 if (VT == MVT::i16) 10241 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10242 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10243 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10244 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10245 case 'f': // FP Stack registers. 10246 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10247 // value to the correct fpstack register class. 10248 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10249 return std::make_pair(0U, X86::RFP32RegisterClass); 10250 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10251 return std::make_pair(0U, X86::RFP64RegisterClass); 10252 return std::make_pair(0U, X86::RFP80RegisterClass); 10253 case 'y': // MMX_REGS if MMX allowed. 10254 if (!Subtarget->hasMMX()) break; 10255 return std::make_pair(0U, X86::VR64RegisterClass); 10256 case 'Y': // SSE_REGS if SSE2 allowed 10257 if (!Subtarget->hasSSE2()) break; 10258 // FALL THROUGH. 10259 case 'x': // SSE_REGS if SSE1 allowed 10260 if (!Subtarget->hasSSE1()) break; 10261 10262 switch (VT.getSimpleVT().SimpleTy) { 10263 default: break; 10264 // Scalar SSE types. 10265 case MVT::f32: 10266 case MVT::i32: 10267 return std::make_pair(0U, X86::FR32RegisterClass); 10268 case MVT::f64: 10269 case MVT::i64: 10270 return std::make_pair(0U, X86::FR64RegisterClass); 10271 // Vector types. 10272 case MVT::v16i8: 10273 case MVT::v8i16: 10274 case MVT::v4i32: 10275 case MVT::v2i64: 10276 case MVT::v4f32: 10277 case MVT::v2f64: 10278 return std::make_pair(0U, X86::VR128RegisterClass); 10279 } 10280 break; 10281 } 10282 } 10283 10284 // Use the default implementation in TargetLowering to convert the register 10285 // constraint into a member of a register class. 10286 std::pair<unsigned, const TargetRegisterClass*> Res; 10287 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 10288 10289 // Not found as a standard register? 10290 if (Res.second == 0) { 10291 // Map st(0) -> st(7) -> ST0 10292 if (Constraint.size() == 7 && Constraint[0] == '{' && 10293 tolower(Constraint[1]) == 's' && 10294 tolower(Constraint[2]) == 't' && 10295 Constraint[3] == '(' && 10296 (Constraint[4] >= '0' && Constraint[4] <= '7') && 10297 Constraint[5] == ')' && 10298 Constraint[6] == '}') { 10299 10300 Res.first = X86::ST0+Constraint[4]-'0'; 10301 Res.second = X86::RFP80RegisterClass; 10302 return Res; 10303 } 10304 10305 // GCC allows "st(0)" to be called just plain "st". 10306 if (StringRef("{st}").equals_lower(Constraint)) { 10307 Res.first = X86::ST0; 10308 Res.second = X86::RFP80RegisterClass; 10309 return Res; 10310 } 10311 10312 // flags -> EFLAGS 10313 if (StringRef("{flags}").equals_lower(Constraint)) { 10314 Res.first = X86::EFLAGS; 10315 Res.second = X86::CCRRegisterClass; 10316 return Res; 10317 } 10318 10319 // 'A' means EAX + EDX. 10320 if (Constraint == "A") { 10321 Res.first = X86::EAX; 10322 Res.second = X86::GR32_ADRegisterClass; 10323 return Res; 10324 } 10325 return Res; 10326 } 10327 10328 // Otherwise, check to see if this is a register class of the wrong value 10329 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 10330 // turn into {ax},{dx}. 10331 if (Res.second->hasType(VT)) 10332 return Res; // Correct type already, nothing to do. 10333 10334 // All of the single-register GCC register classes map their values onto 10335 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 10336 // really want an 8-bit or 32-bit register, map to the appropriate register 10337 // class and return the appropriate register. 10338 if (Res.second == X86::GR16RegisterClass) { 10339 if (VT == MVT::i8) { 10340 unsigned DestReg = 0; 10341 switch (Res.first) { 10342 default: break; 10343 case X86::AX: DestReg = X86::AL; break; 10344 case X86::DX: DestReg = X86::DL; break; 10345 case X86::CX: DestReg = X86::CL; break; 10346 case X86::BX: DestReg = X86::BL; break; 10347 } 10348 if (DestReg) { 10349 Res.first = DestReg; 10350 Res.second = X86::GR8RegisterClass; 10351 } 10352 } else if (VT == MVT::i32) { 10353 unsigned DestReg = 0; 10354 switch (Res.first) { 10355 default: break; 10356 case X86::AX: DestReg = X86::EAX; break; 10357 case X86::DX: DestReg = X86::EDX; break; 10358 case X86::CX: DestReg = X86::ECX; break; 10359 case X86::BX: DestReg = X86::EBX; break; 10360 case X86::SI: DestReg = X86::ESI; break; 10361 case X86::DI: DestReg = X86::EDI; break; 10362 case X86::BP: DestReg = X86::EBP; break; 10363 case X86::SP: DestReg = X86::ESP; break; 10364 } 10365 if (DestReg) { 10366 Res.first = DestReg; 10367 Res.second = X86::GR32RegisterClass; 10368 } 10369 } else if (VT == MVT::i64) { 10370 unsigned DestReg = 0; 10371 switch (Res.first) { 10372 default: break; 10373 case X86::AX: DestReg = X86::RAX; break; 10374 case X86::DX: DestReg = X86::RDX; break; 10375 case X86::CX: DestReg = X86::RCX; break; 10376 case X86::BX: DestReg = X86::RBX; break; 10377 case X86::SI: DestReg = X86::RSI; break; 10378 case X86::DI: DestReg = X86::RDI; break; 10379 case X86::BP: DestReg = X86::RBP; break; 10380 case X86::SP: DestReg = X86::RSP; break; 10381 } 10382 if (DestReg) { 10383 Res.first = DestReg; 10384 Res.second = X86::GR64RegisterClass; 10385 } 10386 } 10387 } else if (Res.second == X86::FR32RegisterClass || 10388 Res.second == X86::FR64RegisterClass || 10389 Res.second == X86::VR128RegisterClass) { 10390 // Handle references to XMM physical registers that got mapped into the 10391 // wrong class. This can happen with constraints like {xmm0} where the 10392 // target independent register mapper will just pick the first match it can 10393 // find, ignoring the required type. 10394 if (VT == MVT::f32) 10395 Res.second = X86::FR32RegisterClass; 10396 else if (VT == MVT::f64) 10397 Res.second = X86::FR64RegisterClass; 10398 else if (X86::VR128RegisterClass->hasType(VT)) 10399 Res.second = X86::VR128RegisterClass; 10400 } 10401 10402 return Res; 10403} 10404