X86ISelLowering.cpp revision 1503aba4a036f5394c7983417bc1e64613b2fc77
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 66 SelectionDAG &DAG, DebugLoc dl) { 67 EVT VT = Vec.getValueType(); 68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 69 EVT ElVT = VT.getVectorElementType(); 70 unsigned Factor = VT.getSizeInBits()/128; 71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 72 VT.getVectorNumElements()/Factor); 73 74 // Extract from UNDEF is UNDEF. 75 if (Vec.getOpcode() == ISD::UNDEF) 76 return DAG.getUNDEF(ResultVT); 77 78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 79 // we can match to VEXTRACTF128. 80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 81 82 // This is the index of the first element of the 128-bit chunk 83 // we want. 84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 85 * ElemsPerChunk); 86 87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 89 VecIdx); 90 91 return Result; 92} 93 94/// Generate a DAG to put 128-bits into a vector > 128 bits. This 95/// sets things up to match to an AVX VINSERTF128 instruction or a 96/// simple superregister reference. Idx is an index in the 128 bits 97/// we want. It need not be aligned to a 128-bit bounday. That makes 98/// lowering INSERT_VECTOR_ELT operations easier. 99static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 100 unsigned IdxVal, SelectionDAG &DAG, 101 DebugLoc dl) { 102 // Inserting UNDEF is Result 103 if (Vec.getOpcode() == ISD::UNDEF) 104 return Result; 105 106 EVT VT = Vec.getValueType(); 107 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 108 109 EVT ElVT = VT.getVectorElementType(); 110 EVT ResultVT = Result.getValueType(); 111 112 // Insert the relevant 128 bits. 113 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 114 115 // This is the index of the first element of the 128-bit chunk 116 // we want. 117 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 118 * ElemsPerChunk); 119 120 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 121 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 122 VecIdx); 123} 124 125/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 126/// instructions. This is used because creating CONCAT_VECTOR nodes of 127/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 128/// large BUILD_VECTORS. 129static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 130 unsigned NumElems, SelectionDAG &DAG, 131 DebugLoc dl) { 132 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 133 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 134} 135 136static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 137 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 138 bool is64Bit = Subtarget->is64Bit(); 139 140 if (Subtarget->isTargetEnvMacho()) { 141 if (is64Bit) 142 return new X86_64MachoTargetObjectFile(); 143 return new TargetLoweringObjectFileMachO(); 144 } 145 146 if (Subtarget->isTargetLinux()) 147 return new X86LinuxTargetObjectFile(); 148 if (Subtarget->isTargetELF()) 149 return new TargetLoweringObjectFileELF(); 150 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 151 return new TargetLoweringObjectFileCOFF(); 152 llvm_unreachable("unknown subtarget type"); 153} 154 155X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 156 : TargetLowering(TM, createTLOF(TM)) { 157 Subtarget = &TM.getSubtarget<X86Subtarget>(); 158 X86ScalarSSEf64 = Subtarget->hasSSE2(); 159 X86ScalarSSEf32 = Subtarget->hasSSE1(); 160 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 161 162 RegInfo = TM.getRegisterInfo(); 163 TD = getTargetData(); 164 165 // Set up the TargetLowering object. 166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 167 168 // X86 is weird, it always uses i8 for shift amounts and setcc results. 169 setBooleanContents(ZeroOrOneBooleanContent); 170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 172 173 // For 64-bit since we have so many registers use the ILP scheduler, for 174 // 32-bit code use the register pressure specific scheduling. 175 // For Atom, always use ILP scheduling. 176 if (Subtarget->isAtom()) 177 setSchedulingPreference(Sched::ILP); 178 else if (Subtarget->is64Bit()) 179 setSchedulingPreference(Sched::ILP); 180 else 181 setSchedulingPreference(Sched::RegPressure); 182 setStackPointerRegisterToSaveRestore(X86StackPtr); 183 184 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 185 // Setup Windows compiler runtime calls. 186 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 187 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 188 setLibcallName(RTLIB::SREM_I64, "_allrem"); 189 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 190 setLibcallName(RTLIB::MUL_I64, "_allmul"); 191 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 192 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 193 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 194 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 195 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 196 197 // The _ftol2 runtime function has an unusual calling conv, which 198 // is modeled by a special pseudo-instruction. 199 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 200 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 201 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 202 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 203 } 204 205 if (Subtarget->isTargetDarwin()) { 206 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 207 setUseUnderscoreSetJmp(false); 208 setUseUnderscoreLongJmp(false); 209 } else if (Subtarget->isTargetMingw()) { 210 // MS runtime is weird: it exports _setjmp, but longjmp! 211 setUseUnderscoreSetJmp(true); 212 setUseUnderscoreLongJmp(false); 213 } else { 214 setUseUnderscoreSetJmp(true); 215 setUseUnderscoreLongJmp(true); 216 } 217 218 // Set up the register classes. 219 addRegisterClass(MVT::i8, &X86::GR8RegClass); 220 addRegisterClass(MVT::i16, &X86::GR16RegClass); 221 addRegisterClass(MVT::i32, &X86::GR32RegClass); 222 if (Subtarget->is64Bit()) 223 addRegisterClass(MVT::i64, &X86::GR64RegClass); 224 225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 226 227 // We don't accept any truncstore of integer registers. 228 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 229 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 230 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 231 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 232 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 233 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 234 235 // SETOEQ and SETUNE require checking two conditions. 236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 242 243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 244 // operation. 245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 248 249 if (Subtarget->is64Bit()) { 250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 252 } else if (!TM.Options.UseSoftFloat) { 253 // We have an algorithm for SSE2->double, and we turn this into a 254 // 64-bit FILD followed by conditional FADD for other targets. 255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 256 // We have an algorithm for SSE2, and we turn this into a 64-bit 257 // FILD for other targets. 258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 259 } 260 261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 262 // this operation. 263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 265 266 if (!TM.Options.UseSoftFloat) { 267 // SSE has no i16 to fp conversion, only i32 268 if (X86ScalarSSEf32) { 269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 270 // f32 and f64 cases are Legal, f80 case is not 271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 272 } else { 273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 275 } 276 } else { 277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 279 } 280 281 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 282 // are Legal, f80 is custom lowered. 283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 285 286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 287 // this operation. 288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 290 291 if (X86ScalarSSEf32) { 292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 293 // f32 and f64 cases are Legal, f80 case is not 294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 295 } else { 296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 298 } 299 300 // Handle FP_TO_UINT by promoting the destination to a larger signed 301 // conversion. 302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 305 306 if (Subtarget->is64Bit()) { 307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 309 } else if (!TM.Options.UseSoftFloat) { 310 // Since AVX is a superset of SSE3, only check for SSE here. 311 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 312 // Expand FP_TO_UINT into a select. 313 // FIXME: We would like to use a Custom expander here eventually to do 314 // the optimal thing for SSE vs. the default expansion in the legalizer. 315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 316 else 317 // With SSE3 we can use fisttpll to convert to a signed i64; without 318 // SSE, we're stuck with a fistpll. 319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 320 } 321 322 if (isTargetFTOL()) { 323 // Use the _ftol2 runtime function, which has a pseudo-instruction 324 // to handle its weird calling convention. 325 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 326 } 327 328 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 329 if (!X86ScalarSSEf64) { 330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 332 if (Subtarget->is64Bit()) { 333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 334 // Without SSE, i64->f64 goes through memory. 335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 336 } 337 } 338 339 // Scalar integer divide and remainder are lowered to use operations that 340 // produce two results, to match the available instructions. This exposes 341 // the two-result form to trivial CSE, which is able to combine x/y and x%y 342 // into a single instruction. 343 // 344 // Scalar integer multiply-high is also lowered to use two-result 345 // operations, to match the available instructions. However, plain multiply 346 // (low) operations are left as Legal, as there are single-result 347 // instructions for this in x86. Using the two-result multiply instructions 348 // when both high and low results are needed must be arranged by dagcombine. 349 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 350 MVT VT = IntVTs[i]; 351 setOperationAction(ISD::MULHS, VT, Expand); 352 setOperationAction(ISD::MULHU, VT, Expand); 353 setOperationAction(ISD::SDIV, VT, Expand); 354 setOperationAction(ISD::UDIV, VT, Expand); 355 setOperationAction(ISD::SREM, VT, Expand); 356 setOperationAction(ISD::UREM, VT, Expand); 357 358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 359 setOperationAction(ISD::ADDC, VT, Custom); 360 setOperationAction(ISD::ADDE, VT, Custom); 361 setOperationAction(ISD::SUBC, VT, Custom); 362 setOperationAction(ISD::SUBE, VT, Custom); 363 } 364 365 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 366 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 367 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 368 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 369 if (Subtarget->is64Bit()) 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 374 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 375 setOperationAction(ISD::FREM , MVT::f32 , Expand); 376 setOperationAction(ISD::FREM , MVT::f64 , Expand); 377 setOperationAction(ISD::FREM , MVT::f80 , Expand); 378 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 379 380 // Promote the i8 variants and force them on up to i32 which has a shorter 381 // encoding. 382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 383 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 385 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 386 if (Subtarget->hasBMI()) { 387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 389 if (Subtarget->is64Bit()) 390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 391 } else { 392 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 393 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 394 if (Subtarget->is64Bit()) 395 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 396 } 397 398 if (Subtarget->hasLZCNT()) { 399 // When promoting the i8 variants, force them to i32 for a shorter 400 // encoding. 401 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 402 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 404 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 407 if (Subtarget->is64Bit()) 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 409 } else { 410 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 411 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 412 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 416 if (Subtarget->is64Bit()) { 417 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 419 } 420 } 421 422 if (Subtarget->hasPOPCNT()) { 423 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 424 } else { 425 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 426 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 427 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 428 if (Subtarget->is64Bit()) 429 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 430 } 431 432 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 433 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 434 435 // These should be promoted to a larger select which is supported. 436 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 437 // X86 wants to expand cmov itself. 438 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 439 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 440 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 441 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 443 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 444 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 446 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 447 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 449 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 450 if (Subtarget->is64Bit()) { 451 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 452 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 453 } 454 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 455 456 // Darwin ABI issue. 457 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 458 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 459 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 460 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 461 if (Subtarget->is64Bit()) 462 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 463 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 464 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 465 if (Subtarget->is64Bit()) { 466 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 467 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 468 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 469 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 470 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 471 } 472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 473 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 474 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 475 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 476 if (Subtarget->is64Bit()) { 477 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 478 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 479 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 480 } 481 482 if (Subtarget->hasSSE1()) 483 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 484 485 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 486 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 487 488 // On X86 and X86-64, atomic operations are lowered to locked instructions. 489 // Locked instructions, in turn, have implicit fence semantics (all memory 490 // operations are flushed before issuing the locked instruction, and they 491 // are not buffered), so we can fold away the common pattern of 492 // fence-atomic-fence. 493 setShouldFoldAtomicFences(true); 494 495 // Expand certain atomics 496 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 497 MVT VT = IntVTs[i]; 498 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 499 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 500 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 501 } 502 503 if (!Subtarget->is64Bit()) { 504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 512 } 513 514 if (Subtarget->hasCmpxchg16b()) { 515 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 516 } 517 518 // FIXME - use subtarget debug flags 519 if (!Subtarget->isTargetDarwin() && 520 !Subtarget->isTargetELF() && 521 !Subtarget->isTargetCygMing()) { 522 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 523 } 524 525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 526 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 528 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 529 if (Subtarget->is64Bit()) { 530 setExceptionPointerRegister(X86::RAX); 531 setExceptionSelectorRegister(X86::RDX); 532 } else { 533 setExceptionPointerRegister(X86::EAX); 534 setExceptionSelectorRegister(X86::EDX); 535 } 536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 538 539 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 540 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 541 542 setOperationAction(ISD::TRAP, MVT::Other, Legal); 543 544 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 545 setOperationAction(ISD::VASTART , MVT::Other, Custom); 546 setOperationAction(ISD::VAEND , MVT::Other, Expand); 547 if (Subtarget->is64Bit()) { 548 setOperationAction(ISD::VAARG , MVT::Other, Custom); 549 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 550 } else { 551 setOperationAction(ISD::VAARG , MVT::Other, Expand); 552 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 553 } 554 555 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 556 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 557 558 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 560 MVT::i64 : MVT::i32, Custom); 561 else if (TM.Options.EnableSegmentedStacks) 562 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 563 MVT::i64 : MVT::i32, Custom); 564 else 565 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 566 MVT::i64 : MVT::i32, Expand); 567 568 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 569 // f32 and f64 use SSE. 570 // Set up the FP register classes. 571 addRegisterClass(MVT::f32, &X86::FR32RegClass); 572 addRegisterClass(MVT::f64, &X86::FR64RegClass); 573 574 // Use ANDPD to simulate FABS. 575 setOperationAction(ISD::FABS , MVT::f64, Custom); 576 setOperationAction(ISD::FABS , MVT::f32, Custom); 577 578 // Use XORP to simulate FNEG. 579 setOperationAction(ISD::FNEG , MVT::f64, Custom); 580 setOperationAction(ISD::FNEG , MVT::f32, Custom); 581 582 // Use ANDPD and ORPD to simulate FCOPYSIGN. 583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 585 586 // Lower this to FGETSIGNx86 plus an AND. 587 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 588 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 589 590 // We don't support sin/cos/fmod 591 setOperationAction(ISD::FSIN , MVT::f64, Expand); 592 setOperationAction(ISD::FCOS , MVT::f64, Expand); 593 setOperationAction(ISD::FSIN , MVT::f32, Expand); 594 setOperationAction(ISD::FCOS , MVT::f32, Expand); 595 596 // Expand FP immediates into loads from the stack, except for the special 597 // cases we handle. 598 addLegalFPImmediate(APFloat(+0.0)); // xorpd 599 addLegalFPImmediate(APFloat(+0.0f)); // xorps 600 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 601 // Use SSE for f32, x87 for f64. 602 // Set up the FP register classes. 603 addRegisterClass(MVT::f32, &X86::FR32RegClass); 604 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 605 606 // Use ANDPS to simulate FABS. 607 setOperationAction(ISD::FABS , MVT::f32, Custom); 608 609 // Use XORP to simulate FNEG. 610 setOperationAction(ISD::FNEG , MVT::f32, Custom); 611 612 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 613 614 // Use ANDPS and ORPS to simulate FCOPYSIGN. 615 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 616 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 617 618 // We don't support sin/cos/fmod 619 setOperationAction(ISD::FSIN , MVT::f32, Expand); 620 setOperationAction(ISD::FCOS , MVT::f32, Expand); 621 622 // Special cases we handle for FP constants. 623 addLegalFPImmediate(APFloat(+0.0f)); // xorps 624 addLegalFPImmediate(APFloat(+0.0)); // FLD0 625 addLegalFPImmediate(APFloat(+1.0)); // FLD1 626 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 627 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 628 629 if (!TM.Options.UnsafeFPMath) { 630 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 631 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 632 } 633 } else if (!TM.Options.UseSoftFloat) { 634 // f32 and f64 in x87. 635 // Set up the FP register classes. 636 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 637 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 638 639 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 640 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 643 644 if (!TM.Options.UnsafeFPMath) { 645 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 646 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 647 } 648 addLegalFPImmediate(APFloat(+0.0)); // FLD0 649 addLegalFPImmediate(APFloat(+1.0)); // FLD1 650 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 651 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 652 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 653 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 654 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 655 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 656 } 657 658 // We don't support FMA. 659 setOperationAction(ISD::FMA, MVT::f64, Expand); 660 setOperationAction(ISD::FMA, MVT::f32, Expand); 661 662 // Long double always uses X87. 663 if (!TM.Options.UseSoftFloat) { 664 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 665 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 666 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 667 { 668 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 669 addLegalFPImmediate(TmpFlt); // FLD0 670 TmpFlt.changeSign(); 671 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 672 673 bool ignored; 674 APFloat TmpFlt2(+1.0); 675 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 676 &ignored); 677 addLegalFPImmediate(TmpFlt2); // FLD1 678 TmpFlt2.changeSign(); 679 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 680 } 681 682 if (!TM.Options.UnsafeFPMath) { 683 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 684 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 685 } 686 687 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 688 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 689 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 690 setOperationAction(ISD::FRINT, MVT::f80, Expand); 691 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 692 setOperationAction(ISD::FMA, MVT::f80, Expand); 693 } 694 695 // Always use a library call for pow. 696 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 697 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 698 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 699 700 setOperationAction(ISD::FLOG, MVT::f80, Expand); 701 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 702 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 703 setOperationAction(ISD::FEXP, MVT::f80, Expand); 704 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 705 706 // First set operation action for all vector types to either promote 707 // (for widening) or expand (for scalarization). Then we will selectively 708 // turn on ones that can be effectively codegen'd. 709 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 710 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) { 711 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 726 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 728 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 729 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FMA, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 764 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 767 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 769 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 770 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 771 setTruncStoreAction((MVT::SimpleValueType)VT, 772 (MVT::SimpleValueType)InnerVT, Expand); 773 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 775 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 776 } 777 778 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 779 // with -msoft-float, disable use of MMX as well. 780 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 781 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 782 // No operations on x86mmx supported, everything uses intrinsics. 783 } 784 785 // MMX-sized vectors (other than x86mmx) are expected to be expanded 786 // into smaller operations. 787 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 788 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 789 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 790 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 791 setOperationAction(ISD::AND, MVT::v8i8, Expand); 792 setOperationAction(ISD::AND, MVT::v4i16, Expand); 793 setOperationAction(ISD::AND, MVT::v2i32, Expand); 794 setOperationAction(ISD::AND, MVT::v1i64, Expand); 795 setOperationAction(ISD::OR, MVT::v8i8, Expand); 796 setOperationAction(ISD::OR, MVT::v4i16, Expand); 797 setOperationAction(ISD::OR, MVT::v2i32, Expand); 798 setOperationAction(ISD::OR, MVT::v1i64, Expand); 799 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 800 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 801 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 802 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 806 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 808 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 809 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 810 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 811 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 814 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 815 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 816 817 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 818 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 819 820 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 821 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 822 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 823 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 824 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 825 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 826 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 827 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 828 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 830 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 831 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 832 } 833 834 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 835 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 836 837 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 838 // registers cannot be used even for integer operations. 839 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 840 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 841 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 842 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 843 844 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 845 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 846 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 847 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 848 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 849 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 850 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 851 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 852 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 853 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 854 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 855 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 856 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 857 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 858 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 859 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 860 861 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 862 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 863 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 864 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 865 866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 867 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 871 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 877 878 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 879 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 880 EVT VT = (MVT::SimpleValueType)i; 881 // Do not attempt to custom lower non-power-of-2 vectors 882 if (!isPowerOf2_32(VT.getVectorNumElements())) 883 continue; 884 // Do not attempt to custom lower non-128-bit vectors 885 if (!VT.is128BitVector()) 886 continue; 887 setOperationAction(ISD::BUILD_VECTOR, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::VECTOR_SHUFFLE, 890 VT.getSimpleVT().SimpleTy, Custom); 891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 892 VT.getSimpleVT().SimpleTy, Custom); 893 } 894 895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 896 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 898 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 901 902 if (Subtarget->is64Bit()) { 903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 905 } 906 907 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 908 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 909 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 910 EVT VT = SVT; 911 912 // Do not attempt to promote non-128-bit vectors 913 if (!VT.is128BitVector()) 914 continue; 915 916 setOperationAction(ISD::AND, SVT, Promote); 917 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 918 setOperationAction(ISD::OR, SVT, Promote); 919 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 920 setOperationAction(ISD::XOR, SVT, Promote); 921 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 922 setOperationAction(ISD::LOAD, SVT, Promote); 923 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 924 setOperationAction(ISD::SELECT, SVT, Promote); 925 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 926 } 927 928 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 929 930 // Custom lower v2i64 and v2f64 selects. 931 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 932 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 933 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 934 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 935 936 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 937 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 938 } 939 940 if (Subtarget->hasSSE41()) { 941 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 942 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 943 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 944 setOperationAction(ISD::FRINT, MVT::f32, Legal); 945 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 946 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 947 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 948 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 949 setOperationAction(ISD::FRINT, MVT::f64, Legal); 950 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 951 952 // FIXME: Do we need to handle scalar-to-vector here? 953 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 954 955 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 958 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 959 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 960 961 // i8 and i16 vectors are custom , because the source register and source 962 // source memory operand types are not the same width. f32 vectors are 963 // custom since the immediate controlling the insert encodes additional 964 // information. 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 968 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 969 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 974 975 // FIXME: these should be Legal but thats only for the case where 976 // the index is constant. For now custom expand to deal with that. 977 if (Subtarget->is64Bit()) { 978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 980 } 981 } 982 983 if (Subtarget->hasSSE2()) { 984 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 986 987 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 988 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 989 990 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 991 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 992 993 if (Subtarget->hasAVX2()) { 994 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 995 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 996 997 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 998 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 999 1000 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1001 } else { 1002 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1003 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1004 1005 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1006 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1007 1008 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1009 } 1010 } 1011 1012 if (Subtarget->hasSSE42()) 1013 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1014 1015 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1016 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1017 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1018 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1019 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1020 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1021 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1022 1023 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1024 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1025 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1026 1027 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1031 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1032 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1033 1034 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1038 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1039 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1040 1041 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1042 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1043 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1044 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1051 1052 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1056 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1057 1058 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1059 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1060 1061 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1063 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1064 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1065 1066 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1067 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1068 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1069 1070 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1072 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1073 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1074 1075 if (Subtarget->hasFMA()) { 1076 setOperationAction(ISD::FMA, MVT::v8f32, Custom); 1077 setOperationAction(ISD::FMA, MVT::v4f64, Custom); 1078 setOperationAction(ISD::FMA, MVT::v4f32, Custom); 1079 setOperationAction(ISD::FMA, MVT::v2f64, Custom); 1080 setOperationAction(ISD::FMA, MVT::f32, Custom); 1081 setOperationAction(ISD::FMA, MVT::f64, Custom); 1082 } 1083 if (Subtarget->hasAVX2()) { 1084 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1085 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1086 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1087 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1088 1089 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1090 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1091 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1092 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1093 1094 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1095 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1096 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1097 // Don't lower v32i8 because there is no 128-bit byte mul 1098 1099 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1100 1101 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1102 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1103 1104 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1105 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1106 1107 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1108 } else { 1109 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1110 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1111 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1112 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1113 1114 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1115 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1116 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1117 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1118 1119 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1120 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1121 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1122 // Don't lower v32i8 because there is no 128-bit byte mul 1123 1124 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1125 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1126 1127 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1128 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1129 1130 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1131 } 1132 1133 // Custom lower several nodes for 256-bit types. 1134 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1135 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1136 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1137 EVT VT = SVT; 1138 1139 // Extract subvector is special because the value type 1140 // (result) is 128-bit but the source is 256-bit wide. 1141 if (VT.is128BitVector()) 1142 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1143 1144 // Do not attempt to custom lower other non-256-bit vectors 1145 if (!VT.is256BitVector()) 1146 continue; 1147 1148 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1149 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1150 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1152 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1153 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1154 } 1155 1156 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1157 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1158 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1159 EVT VT = SVT; 1160 1161 // Do not attempt to promote non-256-bit vectors 1162 if (!VT.is256BitVector()) 1163 continue; 1164 1165 setOperationAction(ISD::AND, SVT, Promote); 1166 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1167 setOperationAction(ISD::OR, SVT, Promote); 1168 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1169 setOperationAction(ISD::XOR, SVT, Promote); 1170 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1171 setOperationAction(ISD::LOAD, SVT, Promote); 1172 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1173 setOperationAction(ISD::SELECT, SVT, Promote); 1174 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1175 } 1176 } 1177 1178 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1179 // of this type with custom code. 1180 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1181 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1182 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1183 Custom); 1184 } 1185 1186 // We want to custom lower some of our intrinsics. 1187 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1188 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 1189 1190 1191 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1192 // handle type legalization for these operations here. 1193 // 1194 // FIXME: We really should do custom legalization for addition and 1195 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1196 // than generic legalization for 64-bit multiplication-with-overflow, though. 1197 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1198 // Add/Sub/Mul with overflow operations are custom lowered. 1199 MVT VT = IntVTs[i]; 1200 setOperationAction(ISD::SADDO, VT, Custom); 1201 setOperationAction(ISD::UADDO, VT, Custom); 1202 setOperationAction(ISD::SSUBO, VT, Custom); 1203 setOperationAction(ISD::USUBO, VT, Custom); 1204 setOperationAction(ISD::SMULO, VT, Custom); 1205 setOperationAction(ISD::UMULO, VT, Custom); 1206 } 1207 1208 // There are no 8-bit 3-address imul/mul instructions 1209 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1210 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1211 1212 if (!Subtarget->is64Bit()) { 1213 // These libcalls are not available in 32-bit. 1214 setLibcallName(RTLIB::SHL_I128, 0); 1215 setLibcallName(RTLIB::SRL_I128, 0); 1216 setLibcallName(RTLIB::SRA_I128, 0); 1217 } 1218 1219 // We have target-specific dag combine patterns for the following nodes: 1220 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1221 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1222 setTargetDAGCombine(ISD::VSELECT); 1223 setTargetDAGCombine(ISD::SELECT); 1224 setTargetDAGCombine(ISD::SHL); 1225 setTargetDAGCombine(ISD::SRA); 1226 setTargetDAGCombine(ISD::SRL); 1227 setTargetDAGCombine(ISD::OR); 1228 setTargetDAGCombine(ISD::AND); 1229 setTargetDAGCombine(ISD::ADD); 1230 setTargetDAGCombine(ISD::FADD); 1231 setTargetDAGCombine(ISD::FSUB); 1232 setTargetDAGCombine(ISD::FMA); 1233 setTargetDAGCombine(ISD::SUB); 1234 setTargetDAGCombine(ISD::LOAD); 1235 setTargetDAGCombine(ISD::STORE); 1236 setTargetDAGCombine(ISD::ZERO_EXTEND); 1237 setTargetDAGCombine(ISD::ANY_EXTEND); 1238 setTargetDAGCombine(ISD::SIGN_EXTEND); 1239 setTargetDAGCombine(ISD::TRUNCATE); 1240 setTargetDAGCombine(ISD::UINT_TO_FP); 1241 setTargetDAGCombine(ISD::SINT_TO_FP); 1242 setTargetDAGCombine(ISD::SETCC); 1243 setTargetDAGCombine(ISD::FP_TO_SINT); 1244 if (Subtarget->is64Bit()) 1245 setTargetDAGCombine(ISD::MUL); 1246 setTargetDAGCombine(ISD::XOR); 1247 1248 computeRegisterProperties(); 1249 1250 // On Darwin, -Os means optimize for size without hurting performance, 1251 // do not reduce the limit. 1252 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1253 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1254 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1255 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1256 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1257 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1258 setPrefLoopAlignment(4); // 2^4 bytes. 1259 benefitFromCodePlacementOpt = true; 1260 1261 // Predictable cmov don't hurt on atom because it's in-order. 1262 predictableSelectIsExpensive = !Subtarget->isAtom(); 1263 1264 setPrefFunctionAlignment(4); // 2^4 bytes. 1265} 1266 1267 1268EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1269 if (!VT.isVector()) return MVT::i8; 1270 return VT.changeVectorElementTypeToInteger(); 1271} 1272 1273 1274/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1275/// the desired ByVal argument alignment. 1276static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1277 if (MaxAlign == 16) 1278 return; 1279 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1280 if (VTy->getBitWidth() == 128) 1281 MaxAlign = 16; 1282 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1283 unsigned EltAlign = 0; 1284 getMaxByValAlign(ATy->getElementType(), EltAlign); 1285 if (EltAlign > MaxAlign) 1286 MaxAlign = EltAlign; 1287 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1288 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1289 unsigned EltAlign = 0; 1290 getMaxByValAlign(STy->getElementType(i), EltAlign); 1291 if (EltAlign > MaxAlign) 1292 MaxAlign = EltAlign; 1293 if (MaxAlign == 16) 1294 break; 1295 } 1296 } 1297} 1298 1299/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1300/// function arguments in the caller parameter area. For X86, aggregates 1301/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1302/// are at 4-byte boundaries. 1303unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1304 if (Subtarget->is64Bit()) { 1305 // Max of 8 and alignment of type. 1306 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1307 if (TyAlign > 8) 1308 return TyAlign; 1309 return 8; 1310 } 1311 1312 unsigned Align = 4; 1313 if (Subtarget->hasSSE1()) 1314 getMaxByValAlign(Ty, Align); 1315 return Align; 1316} 1317 1318/// getOptimalMemOpType - Returns the target specific optimal type for load 1319/// and store operations as a result of memset, memcpy, and memmove 1320/// lowering. If DstAlign is zero that means it's safe to destination 1321/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1322/// means there isn't a need to check it against alignment requirement, 1323/// probably because the source does not need to be loaded. If 1324/// 'IsZeroVal' is true, that means it's safe to return a 1325/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1326/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1327/// constant so it does not need to be loaded. 1328/// It returns EVT::Other if the type should be determined using generic 1329/// target-independent logic. 1330EVT 1331X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1332 unsigned DstAlign, unsigned SrcAlign, 1333 bool IsZeroVal, 1334 bool MemcpyStrSrc, 1335 MachineFunction &MF) const { 1336 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1337 // linux. This is because the stack realignment code can't handle certain 1338 // cases like PR2962. This should be removed when PR2962 is fixed. 1339 const Function *F = MF.getFunction(); 1340 if (IsZeroVal && 1341 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1342 if (Size >= 16 && 1343 (Subtarget->isUnalignedMemAccessFast() || 1344 ((DstAlign == 0 || DstAlign >= 16) && 1345 (SrcAlign == 0 || SrcAlign >= 16))) && 1346 Subtarget->getStackAlignment() >= 16) { 1347 if (Subtarget->getStackAlignment() >= 32) { 1348 if (Subtarget->hasAVX2()) 1349 return MVT::v8i32; 1350 if (Subtarget->hasAVX()) 1351 return MVT::v8f32; 1352 } 1353 if (Subtarget->hasSSE2()) 1354 return MVT::v4i32; 1355 if (Subtarget->hasSSE1()) 1356 return MVT::v4f32; 1357 } else if (!MemcpyStrSrc && Size >= 8 && 1358 !Subtarget->is64Bit() && 1359 Subtarget->getStackAlignment() >= 8 && 1360 Subtarget->hasSSE2()) { 1361 // Do not use f64 to lower memcpy if source is string constant. It's 1362 // better to use i32 to avoid the loads. 1363 return MVT::f64; 1364 } 1365 } 1366 if (Subtarget->is64Bit() && Size >= 8) 1367 return MVT::i64; 1368 return MVT::i32; 1369} 1370 1371/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1372/// current function. The returned value is a member of the 1373/// MachineJumpTableInfo::JTEntryKind enum. 1374unsigned X86TargetLowering::getJumpTableEncoding() const { 1375 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1376 // symbol. 1377 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1378 Subtarget->isPICStyleGOT()) 1379 return MachineJumpTableInfo::EK_Custom32; 1380 1381 // Otherwise, use the normal jump table encoding heuristics. 1382 return TargetLowering::getJumpTableEncoding(); 1383} 1384 1385const MCExpr * 1386X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1387 const MachineBasicBlock *MBB, 1388 unsigned uid,MCContext &Ctx) const{ 1389 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1390 Subtarget->isPICStyleGOT()); 1391 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1392 // entries. 1393 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1394 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1395} 1396 1397/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1398/// jumptable. 1399SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1400 SelectionDAG &DAG) const { 1401 if (!Subtarget->is64Bit()) 1402 // This doesn't have DebugLoc associated with it, but is not really the 1403 // same as a Register. 1404 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1405 return Table; 1406} 1407 1408/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1409/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1410/// MCExpr. 1411const MCExpr *X86TargetLowering:: 1412getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1413 MCContext &Ctx) const { 1414 // X86-64 uses RIP relative addressing based on the jump table label. 1415 if (Subtarget->isPICStyleRIPRel()) 1416 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1417 1418 // Otherwise, the reference is relative to the PIC base. 1419 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1420} 1421 1422// FIXME: Why this routine is here? Move to RegInfo! 1423std::pair<const TargetRegisterClass*, uint8_t> 1424X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1425 const TargetRegisterClass *RRC = 0; 1426 uint8_t Cost = 1; 1427 switch (VT.getSimpleVT().SimpleTy) { 1428 default: 1429 return TargetLowering::findRepresentativeClass(VT); 1430 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1431 RRC = Subtarget->is64Bit() ? 1432 (const TargetRegisterClass*)&X86::GR64RegClass : 1433 (const TargetRegisterClass*)&X86::GR32RegClass; 1434 break; 1435 case MVT::x86mmx: 1436 RRC = &X86::VR64RegClass; 1437 break; 1438 case MVT::f32: case MVT::f64: 1439 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1440 case MVT::v4f32: case MVT::v2f64: 1441 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1442 case MVT::v4f64: 1443 RRC = &X86::VR128RegClass; 1444 break; 1445 } 1446 return std::make_pair(RRC, Cost); 1447} 1448 1449bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1450 unsigned &Offset) const { 1451 if (!Subtarget->isTargetLinux()) 1452 return false; 1453 1454 if (Subtarget->is64Bit()) { 1455 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1456 Offset = 0x28; 1457 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1458 AddressSpace = 256; 1459 else 1460 AddressSpace = 257; 1461 } else { 1462 // %gs:0x14 on i386 1463 Offset = 0x14; 1464 AddressSpace = 256; 1465 } 1466 return true; 1467} 1468 1469 1470//===----------------------------------------------------------------------===// 1471// Return Value Calling Convention Implementation 1472//===----------------------------------------------------------------------===// 1473 1474#include "X86GenCallingConv.inc" 1475 1476bool 1477X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1478 MachineFunction &MF, bool isVarArg, 1479 const SmallVectorImpl<ISD::OutputArg> &Outs, 1480 LLVMContext &Context) const { 1481 SmallVector<CCValAssign, 16> RVLocs; 1482 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1483 RVLocs, Context); 1484 return CCInfo.CheckReturn(Outs, RetCC_X86); 1485} 1486 1487SDValue 1488X86TargetLowering::LowerReturn(SDValue Chain, 1489 CallingConv::ID CallConv, bool isVarArg, 1490 const SmallVectorImpl<ISD::OutputArg> &Outs, 1491 const SmallVectorImpl<SDValue> &OutVals, 1492 DebugLoc dl, SelectionDAG &DAG) const { 1493 MachineFunction &MF = DAG.getMachineFunction(); 1494 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1495 1496 SmallVector<CCValAssign, 16> RVLocs; 1497 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1498 RVLocs, *DAG.getContext()); 1499 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1500 1501 // Add the regs to the liveout set for the function. 1502 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1503 for (unsigned i = 0; i != RVLocs.size(); ++i) 1504 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1505 MRI.addLiveOut(RVLocs[i].getLocReg()); 1506 1507 SDValue Flag; 1508 1509 SmallVector<SDValue, 6> RetOps; 1510 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1511 // Operand #1 = Bytes To Pop 1512 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1513 MVT::i16)); 1514 1515 // Copy the result values into the output registers. 1516 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1517 CCValAssign &VA = RVLocs[i]; 1518 assert(VA.isRegLoc() && "Can only return in registers!"); 1519 SDValue ValToCopy = OutVals[i]; 1520 EVT ValVT = ValToCopy.getValueType(); 1521 1522 // Promote values to the appropriate types 1523 if (VA.getLocInfo() == CCValAssign::SExt) 1524 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1525 else if (VA.getLocInfo() == CCValAssign::ZExt) 1526 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1527 else if (VA.getLocInfo() == CCValAssign::AExt) 1528 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1529 else if (VA.getLocInfo() == CCValAssign::BCvt) 1530 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); 1531 1532 // If this is x86-64, and we disabled SSE, we can't return FP values, 1533 // or SSE or MMX vectors. 1534 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1535 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1536 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1537 report_fatal_error("SSE register return with SSE disabled"); 1538 } 1539 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1540 // llvm-gcc has never done it right and no one has noticed, so this 1541 // should be OK for now. 1542 if (ValVT == MVT::f64 && 1543 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1544 report_fatal_error("SSE2 register return with SSE2 disabled"); 1545 1546 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1547 // the RET instruction and handled by the FP Stackifier. 1548 if (VA.getLocReg() == X86::ST0 || 1549 VA.getLocReg() == X86::ST1) { 1550 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1551 // change the value to the FP stack register class. 1552 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1553 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1554 RetOps.push_back(ValToCopy); 1555 // Don't emit a copytoreg. 1556 continue; 1557 } 1558 1559 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1560 // which is returned in RAX / RDX. 1561 if (Subtarget->is64Bit()) { 1562 if (ValVT == MVT::x86mmx) { 1563 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1564 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1565 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1566 ValToCopy); 1567 // If we don't have SSE2 available, convert to v4f32 so the generated 1568 // register is legal. 1569 if (!Subtarget->hasSSE2()) 1570 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1571 } 1572 } 1573 } 1574 1575 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1576 Flag = Chain.getValue(1); 1577 } 1578 1579 // The x86-64 ABI for returning structs by value requires that we copy 1580 // the sret argument into %rax for the return. We saved the argument into 1581 // a virtual register in the entry block, so now we copy the value out 1582 // and into %rax. 1583 if (Subtarget->is64Bit() && 1584 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1585 MachineFunction &MF = DAG.getMachineFunction(); 1586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1587 unsigned Reg = FuncInfo->getSRetReturnReg(); 1588 assert(Reg && 1589 "SRetReturnReg should have been set in LowerFormalArguments()."); 1590 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1591 1592 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1593 Flag = Chain.getValue(1); 1594 1595 // RAX now acts like a return value. 1596 MRI.addLiveOut(X86::RAX); 1597 } 1598 1599 RetOps[0] = Chain; // Update chain. 1600 1601 // Add the flag if we have it. 1602 if (Flag.getNode()) 1603 RetOps.push_back(Flag); 1604 1605 return DAG.getNode(X86ISD::RET_FLAG, dl, 1606 MVT::Other, &RetOps[0], RetOps.size()); 1607} 1608 1609bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1610 if (N->getNumValues() != 1) 1611 return false; 1612 if (!N->hasNUsesOfValue(1, 0)) 1613 return false; 1614 1615 SDValue TCChain = Chain; 1616 SDNode *Copy = *N->use_begin(); 1617 if (Copy->getOpcode() == ISD::CopyToReg) { 1618 // If the copy has a glue operand, we conservatively assume it isn't safe to 1619 // perform a tail call. 1620 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1621 return false; 1622 TCChain = Copy->getOperand(0); 1623 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1624 return false; 1625 1626 bool HasRet = false; 1627 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1628 UI != UE; ++UI) { 1629 if (UI->getOpcode() != X86ISD::RET_FLAG) 1630 return false; 1631 HasRet = true; 1632 } 1633 1634 if (!HasRet) 1635 return false; 1636 1637 Chain = TCChain; 1638 return true; 1639} 1640 1641EVT 1642X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1643 ISD::NodeType ExtendKind) const { 1644 MVT ReturnMVT; 1645 // TODO: Is this also valid on 32-bit? 1646 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1647 ReturnMVT = MVT::i8; 1648 else 1649 ReturnMVT = MVT::i32; 1650 1651 EVT MinVT = getRegisterType(Context, ReturnMVT); 1652 return VT.bitsLT(MinVT) ? MinVT : VT; 1653} 1654 1655/// LowerCallResult - Lower the result values of a call into the 1656/// appropriate copies out of appropriate physical registers. 1657/// 1658SDValue 1659X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1660 CallingConv::ID CallConv, bool isVarArg, 1661 const SmallVectorImpl<ISD::InputArg> &Ins, 1662 DebugLoc dl, SelectionDAG &DAG, 1663 SmallVectorImpl<SDValue> &InVals) const { 1664 1665 // Assign locations to each value returned by this call. 1666 SmallVector<CCValAssign, 16> RVLocs; 1667 bool Is64Bit = Subtarget->is64Bit(); 1668 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1669 getTargetMachine(), RVLocs, *DAG.getContext()); 1670 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1671 1672 // Copy all of the result registers out of their specified physreg. 1673 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1674 CCValAssign &VA = RVLocs[i]; 1675 EVT CopyVT = VA.getValVT(); 1676 1677 // If this is x86-64, and we disabled SSE, we can't return FP values 1678 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1679 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1680 report_fatal_error("SSE register return with SSE disabled"); 1681 } 1682 1683 SDValue Val; 1684 1685 // If this is a call to a function that returns an fp value on the floating 1686 // point stack, we must guarantee the value is popped from the stack, so 1687 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1688 // if the return value is not used. We use the FpPOP_RETVAL instruction 1689 // instead. 1690 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1691 // If we prefer to use the value in xmm registers, copy it out as f80 and 1692 // use a truncate to move it from fp stack reg to xmm reg. 1693 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1694 SDValue Ops[] = { Chain, InFlag }; 1695 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1696 MVT::Other, MVT::Glue, Ops, 2), 1); 1697 Val = Chain.getValue(0); 1698 1699 // Round the f80 to the right size, which also moves it to the appropriate 1700 // xmm register. 1701 if (CopyVT != VA.getValVT()) 1702 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1703 // This truncation won't change the value. 1704 DAG.getIntPtrConstant(1)); 1705 } else { 1706 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1707 CopyVT, InFlag).getValue(1); 1708 Val = Chain.getValue(0); 1709 } 1710 InFlag = Chain.getValue(2); 1711 InVals.push_back(Val); 1712 } 1713 1714 return Chain; 1715} 1716 1717 1718//===----------------------------------------------------------------------===// 1719// C & StdCall & Fast Calling Convention implementation 1720//===----------------------------------------------------------------------===// 1721// StdCall calling convention seems to be standard for many Windows' API 1722// routines and around. It differs from C calling convention just a little: 1723// callee should clean up the stack, not caller. Symbols should be also 1724// decorated in some fancy way :) It doesn't support any vector arguments. 1725// For info on fast calling convention see Fast Calling Convention (tail call) 1726// implementation LowerX86_32FastCCCallTo. 1727 1728/// CallIsStructReturn - Determines whether a call uses struct return 1729/// semantics. 1730enum StructReturnType { 1731 NotStructReturn, 1732 RegStructReturn, 1733 StackStructReturn 1734}; 1735static StructReturnType 1736callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1737 if (Outs.empty()) 1738 return NotStructReturn; 1739 1740 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; 1741 if (!Flags.isSRet()) 1742 return NotStructReturn; 1743 if (Flags.isInReg()) 1744 return RegStructReturn; 1745 return StackStructReturn; 1746} 1747 1748/// ArgsAreStructReturn - Determines whether a function uses struct 1749/// return semantics. 1750static StructReturnType 1751argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1752 if (Ins.empty()) 1753 return NotStructReturn; 1754 1755 const ISD::ArgFlagsTy &Flags = Ins[0].Flags; 1756 if (!Flags.isSRet()) 1757 return NotStructReturn; 1758 if (Flags.isInReg()) 1759 return RegStructReturn; 1760 return StackStructReturn; 1761} 1762 1763/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1764/// by "Src" to address "Dst" with size and alignment information specified by 1765/// the specific parameter attribute. The copy will be passed as a byval 1766/// function parameter. 1767static SDValue 1768CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1769 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1770 DebugLoc dl) { 1771 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1772 1773 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1774 /*isVolatile*/false, /*AlwaysInline=*/true, 1775 MachinePointerInfo(), MachinePointerInfo()); 1776} 1777 1778/// IsTailCallConvention - Return true if the calling convention is one that 1779/// supports tail call optimization. 1780static bool IsTailCallConvention(CallingConv::ID CC) { 1781 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1782} 1783 1784bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1785 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1786 return false; 1787 1788 CallSite CS(CI); 1789 CallingConv::ID CalleeCC = CS.getCallingConv(); 1790 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1791 return false; 1792 1793 return true; 1794} 1795 1796/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1797/// a tailcall target by changing its ABI. 1798static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1799 bool GuaranteedTailCallOpt) { 1800 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1801} 1802 1803SDValue 1804X86TargetLowering::LowerMemArgument(SDValue Chain, 1805 CallingConv::ID CallConv, 1806 const SmallVectorImpl<ISD::InputArg> &Ins, 1807 DebugLoc dl, SelectionDAG &DAG, 1808 const CCValAssign &VA, 1809 MachineFrameInfo *MFI, 1810 unsigned i) const { 1811 // Create the nodes corresponding to a load from this parameter slot. 1812 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1813 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1814 getTargetMachine().Options.GuaranteedTailCallOpt); 1815 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1816 EVT ValVT; 1817 1818 // If value is passed by pointer we have address passed instead of the value 1819 // itself. 1820 if (VA.getLocInfo() == CCValAssign::Indirect) 1821 ValVT = VA.getLocVT(); 1822 else 1823 ValVT = VA.getValVT(); 1824 1825 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1826 // changed with more analysis. 1827 // In case of tail call optimization mark all arguments mutable. Since they 1828 // could be overwritten by lowering of arguments in case of a tail call. 1829 if (Flags.isByVal()) { 1830 unsigned Bytes = Flags.getByValSize(); 1831 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1832 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1833 return DAG.getFrameIndex(FI, getPointerTy()); 1834 } else { 1835 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1836 VA.getLocMemOffset(), isImmutable); 1837 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1838 return DAG.getLoad(ValVT, dl, Chain, FIN, 1839 MachinePointerInfo::getFixedStack(FI), 1840 false, false, false, 0); 1841 } 1842} 1843 1844SDValue 1845X86TargetLowering::LowerFormalArguments(SDValue Chain, 1846 CallingConv::ID CallConv, 1847 bool isVarArg, 1848 const SmallVectorImpl<ISD::InputArg> &Ins, 1849 DebugLoc dl, 1850 SelectionDAG &DAG, 1851 SmallVectorImpl<SDValue> &InVals) 1852 const { 1853 MachineFunction &MF = DAG.getMachineFunction(); 1854 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1855 1856 const Function* Fn = MF.getFunction(); 1857 if (Fn->hasExternalLinkage() && 1858 Subtarget->isTargetCygMing() && 1859 Fn->getName() == "main") 1860 FuncInfo->setForceFramePointer(true); 1861 1862 MachineFrameInfo *MFI = MF.getFrameInfo(); 1863 bool Is64Bit = Subtarget->is64Bit(); 1864 bool IsWindows = Subtarget->isTargetWindows(); 1865 bool IsWin64 = Subtarget->isTargetWin64(); 1866 1867 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1868 "Var args not supported with calling convention fastcc or ghc"); 1869 1870 // Assign locations to all of the incoming arguments. 1871 SmallVector<CCValAssign, 16> ArgLocs; 1872 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1873 ArgLocs, *DAG.getContext()); 1874 1875 // Allocate shadow area for Win64 1876 if (IsWin64) { 1877 CCInfo.AllocateStack(32, 8); 1878 } 1879 1880 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1881 1882 unsigned LastVal = ~0U; 1883 SDValue ArgValue; 1884 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1885 CCValAssign &VA = ArgLocs[i]; 1886 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1887 // places. 1888 assert(VA.getValNo() != LastVal && 1889 "Don't support value assigned to multiple locs yet"); 1890 (void)LastVal; 1891 LastVal = VA.getValNo(); 1892 1893 if (VA.isRegLoc()) { 1894 EVT RegVT = VA.getLocVT(); 1895 const TargetRegisterClass *RC; 1896 if (RegVT == MVT::i32) 1897 RC = &X86::GR32RegClass; 1898 else if (Is64Bit && RegVT == MVT::i64) 1899 RC = &X86::GR64RegClass; 1900 else if (RegVT == MVT::f32) 1901 RC = &X86::FR32RegClass; 1902 else if (RegVT == MVT::f64) 1903 RC = &X86::FR64RegClass; 1904 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1905 RC = &X86::VR256RegClass; 1906 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1907 RC = &X86::VR128RegClass; 1908 else if (RegVT == MVT::x86mmx) 1909 RC = &X86::VR64RegClass; 1910 else 1911 llvm_unreachable("Unknown argument type!"); 1912 1913 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1914 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1915 1916 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1917 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1918 // right size. 1919 if (VA.getLocInfo() == CCValAssign::SExt) 1920 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1921 DAG.getValueType(VA.getValVT())); 1922 else if (VA.getLocInfo() == CCValAssign::ZExt) 1923 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1924 DAG.getValueType(VA.getValVT())); 1925 else if (VA.getLocInfo() == CCValAssign::BCvt) 1926 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1927 1928 if (VA.isExtInLoc()) { 1929 // Handle MMX values passed in XMM regs. 1930 if (RegVT.isVector()) { 1931 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1932 ArgValue); 1933 } else 1934 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1935 } 1936 } else { 1937 assert(VA.isMemLoc()); 1938 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1939 } 1940 1941 // If value is passed via pointer - do a load. 1942 if (VA.getLocInfo() == CCValAssign::Indirect) 1943 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1944 MachinePointerInfo(), false, false, false, 0); 1945 1946 InVals.push_back(ArgValue); 1947 } 1948 1949 // The x86-64 ABI for returning structs by value requires that we copy 1950 // the sret argument into %rax for the return. Save the argument into 1951 // a virtual register so that we can access it from the return points. 1952 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1953 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1954 unsigned Reg = FuncInfo->getSRetReturnReg(); 1955 if (!Reg) { 1956 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1957 FuncInfo->setSRetReturnReg(Reg); 1958 } 1959 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1960 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1961 } 1962 1963 unsigned StackSize = CCInfo.getNextStackOffset(); 1964 // Align stack specially for tail calls. 1965 if (FuncIsMadeTailCallSafe(CallConv, 1966 MF.getTarget().Options.GuaranteedTailCallOpt)) 1967 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1968 1969 // If the function takes variable number of arguments, make a frame index for 1970 // the start of the first vararg value... for expansion of llvm.va_start. 1971 if (isVarArg) { 1972 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1973 CallConv != CallingConv::X86_ThisCall)) { 1974 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1975 } 1976 if (Is64Bit) { 1977 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1978 1979 // FIXME: We should really autogenerate these arrays 1980 static const uint16_t GPR64ArgRegsWin64[] = { 1981 X86::RCX, X86::RDX, X86::R8, X86::R9 1982 }; 1983 static const uint16_t GPR64ArgRegs64Bit[] = { 1984 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1985 }; 1986 static const uint16_t XMMArgRegs64Bit[] = { 1987 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1988 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1989 }; 1990 const uint16_t *GPR64ArgRegs; 1991 unsigned NumXMMRegs = 0; 1992 1993 if (IsWin64) { 1994 // The XMM registers which might contain var arg parameters are shadowed 1995 // in their paired GPR. So we only need to save the GPR to their home 1996 // slots. 1997 TotalNumIntRegs = 4; 1998 GPR64ArgRegs = GPR64ArgRegsWin64; 1999 } else { 2000 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 2001 GPR64ArgRegs = GPR64ArgRegs64Bit; 2002 2003 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 2004 TotalNumXMMRegs); 2005 } 2006 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 2007 TotalNumIntRegs); 2008 2009 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 2010 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 2011 "SSE register cannot be used when SSE is disabled!"); 2012 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 2013 NoImplicitFloatOps) && 2014 "SSE register cannot be used when SSE is disabled!"); 2015 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 2016 !Subtarget->hasSSE1()) 2017 // Kernel mode asks for SSE to be disabled, so don't push them 2018 // on the stack. 2019 TotalNumXMMRegs = 0; 2020 2021 if (IsWin64) { 2022 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 2023 // Get to the caller-allocated home save location. Add 8 to account 2024 // for the return address. 2025 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 2026 FuncInfo->setRegSaveFrameIndex( 2027 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 2028 // Fixup to set vararg frame on shadow area (4 x i64). 2029 if (NumIntRegs < 4) 2030 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 2031 } else { 2032 // For X86-64, if there are vararg parameters that are passed via 2033 // registers, then we must store them to their spots on the stack so 2034 // they may be loaded by deferencing the result of va_next. 2035 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 2036 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 2037 FuncInfo->setRegSaveFrameIndex( 2038 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 2039 false)); 2040 } 2041 2042 // Store the integer parameter registers. 2043 SmallVector<SDValue, 8> MemOps; 2044 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2045 getPointerTy()); 2046 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2047 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2048 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2049 DAG.getIntPtrConstant(Offset)); 2050 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2051 &X86::GR64RegClass); 2052 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2053 SDValue Store = 2054 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2055 MachinePointerInfo::getFixedStack( 2056 FuncInfo->getRegSaveFrameIndex(), Offset), 2057 false, false, 0); 2058 MemOps.push_back(Store); 2059 Offset += 8; 2060 } 2061 2062 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2063 // Now store the XMM (fp + vector) parameter registers. 2064 SmallVector<SDValue, 11> SaveXMMOps; 2065 SaveXMMOps.push_back(Chain); 2066 2067 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2068 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2069 SaveXMMOps.push_back(ALVal); 2070 2071 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2072 FuncInfo->getRegSaveFrameIndex())); 2073 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2074 FuncInfo->getVarArgsFPOffset())); 2075 2076 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2077 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2078 &X86::VR128RegClass); 2079 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2080 SaveXMMOps.push_back(Val); 2081 } 2082 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2083 MVT::Other, 2084 &SaveXMMOps[0], SaveXMMOps.size())); 2085 } 2086 2087 if (!MemOps.empty()) 2088 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2089 &MemOps[0], MemOps.size()); 2090 } 2091 } 2092 2093 // Some CCs need callee pop. 2094 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2095 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2096 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2097 } else { 2098 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2099 // If this is an sret function, the return should pop the hidden pointer. 2100 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2101 argsAreStructReturn(Ins) == StackStructReturn) 2102 FuncInfo->setBytesToPopOnReturn(4); 2103 } 2104 2105 if (!Is64Bit) { 2106 // RegSaveFrameIndex is X86-64 only. 2107 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2108 if (CallConv == CallingConv::X86_FastCall || 2109 CallConv == CallingConv::X86_ThisCall) 2110 // fastcc functions can't have varargs. 2111 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2112 } 2113 2114 FuncInfo->setArgumentStackSize(StackSize); 2115 2116 return Chain; 2117} 2118 2119SDValue 2120X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2121 SDValue StackPtr, SDValue Arg, 2122 DebugLoc dl, SelectionDAG &DAG, 2123 const CCValAssign &VA, 2124 ISD::ArgFlagsTy Flags) const { 2125 unsigned LocMemOffset = VA.getLocMemOffset(); 2126 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2127 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2128 if (Flags.isByVal()) 2129 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2130 2131 return DAG.getStore(Chain, dl, Arg, PtrOff, 2132 MachinePointerInfo::getStack(LocMemOffset), 2133 false, false, 0); 2134} 2135 2136/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2137/// optimization is performed and it is required. 2138SDValue 2139X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2140 SDValue &OutRetAddr, SDValue Chain, 2141 bool IsTailCall, bool Is64Bit, 2142 int FPDiff, DebugLoc dl) const { 2143 // Adjust the Return address stack slot. 2144 EVT VT = getPointerTy(); 2145 OutRetAddr = getReturnAddressFrameIndex(DAG); 2146 2147 // Load the "old" Return address. 2148 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2149 false, false, false, 0); 2150 return SDValue(OutRetAddr.getNode(), 1); 2151} 2152 2153/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2154/// optimization is performed and it is required (FPDiff!=0). 2155static SDValue 2156EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2157 SDValue Chain, SDValue RetAddrFrIdx, 2158 bool Is64Bit, int FPDiff, DebugLoc dl) { 2159 // Store the return address to the appropriate stack slot. 2160 if (!FPDiff) return Chain; 2161 // Calculate the new stack slot for the return address. 2162 int SlotSize = Is64Bit ? 8 : 4; 2163 int NewReturnAddrFI = 2164 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2165 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2166 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2167 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2168 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2169 false, false, 0); 2170 return Chain; 2171} 2172 2173SDValue 2174X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2175 SmallVectorImpl<SDValue> &InVals) const { 2176 SelectionDAG &DAG = CLI.DAG; 2177 DebugLoc &dl = CLI.DL; 2178 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2179 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2180 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2181 SDValue Chain = CLI.Chain; 2182 SDValue Callee = CLI.Callee; 2183 CallingConv::ID CallConv = CLI.CallConv; 2184 bool &isTailCall = CLI.IsTailCall; 2185 bool isVarArg = CLI.IsVarArg; 2186 2187 MachineFunction &MF = DAG.getMachineFunction(); 2188 bool Is64Bit = Subtarget->is64Bit(); 2189 bool IsWin64 = Subtarget->isTargetWin64(); 2190 bool IsWindows = Subtarget->isTargetWindows(); 2191 StructReturnType SR = callIsStructReturn(Outs); 2192 bool IsSibcall = false; 2193 2194 if (MF.getTarget().Options.DisableTailCalls) 2195 isTailCall = false; 2196 2197 if (isTailCall) { 2198 // Check if it's really possible to do a tail call. 2199 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2200 isVarArg, SR != NotStructReturn, 2201 MF.getFunction()->hasStructRetAttr(), 2202 Outs, OutVals, Ins, DAG); 2203 2204 // Sibcalls are automatically detected tailcalls which do not require 2205 // ABI changes. 2206 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2207 IsSibcall = true; 2208 2209 if (isTailCall) 2210 ++NumTailCalls; 2211 } 2212 2213 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2214 "Var args not supported with calling convention fastcc or ghc"); 2215 2216 // Analyze operands of the call, assigning locations to each operand. 2217 SmallVector<CCValAssign, 16> ArgLocs; 2218 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2219 ArgLocs, *DAG.getContext()); 2220 2221 // Allocate shadow area for Win64 2222 if (IsWin64) { 2223 CCInfo.AllocateStack(32, 8); 2224 } 2225 2226 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2227 2228 // Get a count of how many bytes are to be pushed on the stack. 2229 unsigned NumBytes = CCInfo.getNextStackOffset(); 2230 if (IsSibcall) 2231 // This is a sibcall. The memory operands are available in caller's 2232 // own caller's stack. 2233 NumBytes = 0; 2234 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2235 IsTailCallConvention(CallConv)) 2236 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2237 2238 int FPDiff = 0; 2239 if (isTailCall && !IsSibcall) { 2240 // Lower arguments at fp - stackoffset + fpdiff. 2241 unsigned NumBytesCallerPushed = 2242 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2243 FPDiff = NumBytesCallerPushed - NumBytes; 2244 2245 // Set the delta of movement of the returnaddr stackslot. 2246 // But only set if delta is greater than previous delta. 2247 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2248 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2249 } 2250 2251 if (!IsSibcall) 2252 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2253 2254 SDValue RetAddrFrIdx; 2255 // Load return address for tail calls. 2256 if (isTailCall && FPDiff) 2257 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2258 Is64Bit, FPDiff, dl); 2259 2260 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2261 SmallVector<SDValue, 8> MemOpChains; 2262 SDValue StackPtr; 2263 2264 // Walk the register/memloc assignments, inserting copies/loads. In the case 2265 // of tail call optimization arguments are handle later. 2266 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2267 CCValAssign &VA = ArgLocs[i]; 2268 EVT RegVT = VA.getLocVT(); 2269 SDValue Arg = OutVals[i]; 2270 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2271 bool isByVal = Flags.isByVal(); 2272 2273 // Promote the value if needed. 2274 switch (VA.getLocInfo()) { 2275 default: llvm_unreachable("Unknown loc info!"); 2276 case CCValAssign::Full: break; 2277 case CCValAssign::SExt: 2278 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2279 break; 2280 case CCValAssign::ZExt: 2281 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2282 break; 2283 case CCValAssign::AExt: 2284 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2285 // Special case: passing MMX values in XMM registers. 2286 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2287 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2288 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2289 } else 2290 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2291 break; 2292 case CCValAssign::BCvt: 2293 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2294 break; 2295 case CCValAssign::Indirect: { 2296 // Store the argument. 2297 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2298 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2299 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2300 MachinePointerInfo::getFixedStack(FI), 2301 false, false, 0); 2302 Arg = SpillSlot; 2303 break; 2304 } 2305 } 2306 2307 if (VA.isRegLoc()) { 2308 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2309 if (isVarArg && IsWin64) { 2310 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2311 // shadow reg if callee is a varargs function. 2312 unsigned ShadowReg = 0; 2313 switch (VA.getLocReg()) { 2314 case X86::XMM0: ShadowReg = X86::RCX; break; 2315 case X86::XMM1: ShadowReg = X86::RDX; break; 2316 case X86::XMM2: ShadowReg = X86::R8; break; 2317 case X86::XMM3: ShadowReg = X86::R9; break; 2318 } 2319 if (ShadowReg) 2320 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2321 } 2322 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2323 assert(VA.isMemLoc()); 2324 if (StackPtr.getNode() == 0) 2325 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2326 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2327 dl, DAG, VA, Flags)); 2328 } 2329 } 2330 2331 if (!MemOpChains.empty()) 2332 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2333 &MemOpChains[0], MemOpChains.size()); 2334 2335 if (Subtarget->isPICStyleGOT()) { 2336 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2337 // GOT pointer. 2338 if (!isTailCall) { 2339 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX), 2340 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()))); 2341 } else { 2342 // If we are tail calling and generating PIC/GOT style code load the 2343 // address of the callee into ECX. The value in ecx is used as target of 2344 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2345 // for tail calls on PIC/GOT architectures. Normally we would just put the 2346 // address of GOT into ebx and then call target@PLT. But for tail calls 2347 // ebx would be restored (since ebx is callee saved) before jumping to the 2348 // target@PLT. 2349 2350 // Note: The actual moving to ECX is done further down. 2351 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2352 if (G && !G->getGlobal()->hasHiddenVisibility() && 2353 !G->getGlobal()->hasProtectedVisibility()) 2354 Callee = LowerGlobalAddress(Callee, DAG); 2355 else if (isa<ExternalSymbolSDNode>(Callee)) 2356 Callee = LowerExternalSymbol(Callee, DAG); 2357 } 2358 } 2359 2360 if (Is64Bit && isVarArg && !IsWin64) { 2361 // From AMD64 ABI document: 2362 // For calls that may call functions that use varargs or stdargs 2363 // (prototype-less calls or calls to functions containing ellipsis (...) in 2364 // the declaration) %al is used as hidden argument to specify the number 2365 // of SSE registers used. The contents of %al do not need to match exactly 2366 // the number of registers, but must be an ubound on the number of SSE 2367 // registers used and is in the range 0 - 8 inclusive. 2368 2369 // Count the number of XMM registers allocated. 2370 static const uint16_t XMMArgRegs[] = { 2371 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2372 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2373 }; 2374 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2375 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2376 && "SSE registers cannot be used when SSE is disabled"); 2377 2378 RegsToPass.push_back(std::make_pair(unsigned(X86::AL), 2379 DAG.getConstant(NumXMMRegs, MVT::i8))); 2380 } 2381 2382 // For tail calls lower the arguments to the 'real' stack slot. 2383 if (isTailCall) { 2384 // Force all the incoming stack arguments to be loaded from the stack 2385 // before any new outgoing arguments are stored to the stack, because the 2386 // outgoing stack slots may alias the incoming argument stack slots, and 2387 // the alias isn't otherwise explicit. This is slightly more conservative 2388 // than necessary, because it means that each store effectively depends 2389 // on every argument instead of just those arguments it would clobber. 2390 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2391 2392 SmallVector<SDValue, 8> MemOpChains2; 2393 SDValue FIN; 2394 int FI = 0; 2395 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2397 CCValAssign &VA = ArgLocs[i]; 2398 if (VA.isRegLoc()) 2399 continue; 2400 assert(VA.isMemLoc()); 2401 SDValue Arg = OutVals[i]; 2402 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2403 // Create frame index. 2404 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2405 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2406 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2407 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2408 2409 if (Flags.isByVal()) { 2410 // Copy relative to framepointer. 2411 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2412 if (StackPtr.getNode() == 0) 2413 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2414 getPointerTy()); 2415 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2416 2417 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2418 ArgChain, 2419 Flags, DAG, dl)); 2420 } else { 2421 // Store relative to framepointer. 2422 MemOpChains2.push_back( 2423 DAG.getStore(ArgChain, dl, Arg, FIN, 2424 MachinePointerInfo::getFixedStack(FI), 2425 false, false, 0)); 2426 } 2427 } 2428 } 2429 2430 if (!MemOpChains2.empty()) 2431 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2432 &MemOpChains2[0], MemOpChains2.size()); 2433 2434 // Store the return address to the appropriate stack slot. 2435 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2436 FPDiff, dl); 2437 } 2438 2439 // Build a sequence of copy-to-reg nodes chained together with token chain 2440 // and flag operands which copy the outgoing args into registers. 2441 SDValue InFlag; 2442 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2443 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2444 RegsToPass[i].second, InFlag); 2445 InFlag = Chain.getValue(1); 2446 } 2447 2448 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2449 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2450 // In the 64-bit large code model, we have to make all calls 2451 // through a register, since the call instruction's 32-bit 2452 // pc-relative offset may not be large enough to hold the whole 2453 // address. 2454 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2455 // If the callee is a GlobalAddress node (quite common, every direct call 2456 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2457 // it. 2458 2459 // We should use extra load for direct calls to dllimported functions in 2460 // non-JIT mode. 2461 const GlobalValue *GV = G->getGlobal(); 2462 if (!GV->hasDLLImportLinkage()) { 2463 unsigned char OpFlags = 0; 2464 bool ExtraLoad = false; 2465 unsigned WrapperKind = ISD::DELETED_NODE; 2466 2467 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2468 // external symbols most go through the PLT in PIC mode. If the symbol 2469 // has hidden or protected visibility, or if it is static or local, then 2470 // we don't need to use the PLT - we can directly call it. 2471 if (Subtarget->isTargetELF() && 2472 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2473 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2474 OpFlags = X86II::MO_PLT; 2475 } else if (Subtarget->isPICStyleStubAny() && 2476 (GV->isDeclaration() || GV->isWeakForLinker()) && 2477 (!Subtarget->getTargetTriple().isMacOSX() || 2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2479 // PC-relative references to external symbols should go through $stub, 2480 // unless we're building with the leopard linker or later, which 2481 // automatically synthesizes these stubs. 2482 OpFlags = X86II::MO_DARWIN_STUB; 2483 } else if (Subtarget->isPICStyleRIPRel() && 2484 isa<Function>(GV) && 2485 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2486 // If the function is marked as non-lazy, generate an indirect call 2487 // which loads from the GOT directly. This avoids runtime overhead 2488 // at the cost of eager binding (and one extra byte of encoding). 2489 OpFlags = X86II::MO_GOTPCREL; 2490 WrapperKind = X86ISD::WrapperRIP; 2491 ExtraLoad = true; 2492 } 2493 2494 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2495 G->getOffset(), OpFlags); 2496 2497 // Add a wrapper if needed. 2498 if (WrapperKind != ISD::DELETED_NODE) 2499 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2500 // Add extra indirection if needed. 2501 if (ExtraLoad) 2502 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2503 MachinePointerInfo::getGOT(), 2504 false, false, false, 0); 2505 } 2506 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2507 unsigned char OpFlags = 0; 2508 2509 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2510 // external symbols should go through the PLT. 2511 if (Subtarget->isTargetELF() && 2512 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2513 OpFlags = X86II::MO_PLT; 2514 } else if (Subtarget->isPICStyleStubAny() && 2515 (!Subtarget->getTargetTriple().isMacOSX() || 2516 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2517 // PC-relative references to external symbols should go through $stub, 2518 // unless we're building with the leopard linker or later, which 2519 // automatically synthesizes these stubs. 2520 OpFlags = X86II::MO_DARWIN_STUB; 2521 } 2522 2523 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2524 OpFlags); 2525 } 2526 2527 // Returns a chain & a flag for retval copy to use. 2528 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2529 SmallVector<SDValue, 8> Ops; 2530 2531 if (!IsSibcall && isTailCall) { 2532 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2533 DAG.getIntPtrConstant(0, true), InFlag); 2534 InFlag = Chain.getValue(1); 2535 } 2536 2537 Ops.push_back(Chain); 2538 Ops.push_back(Callee); 2539 2540 if (isTailCall) 2541 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2542 2543 // Add argument registers to the end of the list so that they are known live 2544 // into the call. 2545 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2546 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2547 RegsToPass[i].second.getValueType())); 2548 2549 // Add a register mask operand representing the call-preserved registers. 2550 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2551 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2552 assert(Mask && "Missing call preserved mask for calling convention"); 2553 Ops.push_back(DAG.getRegisterMask(Mask)); 2554 2555 if (InFlag.getNode()) 2556 Ops.push_back(InFlag); 2557 2558 if (isTailCall) { 2559 // We used to do: 2560 //// If this is the first return lowered for this function, add the regs 2561 //// to the liveout set for the function. 2562 // This isn't right, although it's probably harmless on x86; liveouts 2563 // should be computed from returns not tail calls. Consider a void 2564 // function making a tail call to a function returning int. 2565 return DAG.getNode(X86ISD::TC_RETURN, dl, 2566 NodeTys, &Ops[0], Ops.size()); 2567 } 2568 2569 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2570 InFlag = Chain.getValue(1); 2571 2572 // Create the CALLSEQ_END node. 2573 unsigned NumBytesForCalleeToPush; 2574 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2575 getTargetMachine().Options.GuaranteedTailCallOpt)) 2576 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2577 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2578 SR == StackStructReturn) 2579 // If this is a call to a struct-return function, the callee 2580 // pops the hidden struct pointer, so we have to push it back. 2581 // This is common for Darwin/X86, Linux & Mingw32 targets. 2582 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2583 NumBytesForCalleeToPush = 4; 2584 else 2585 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2586 2587 // Returns a flag for retval copy to use. 2588 if (!IsSibcall) { 2589 Chain = DAG.getCALLSEQ_END(Chain, 2590 DAG.getIntPtrConstant(NumBytes, true), 2591 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2592 true), 2593 InFlag); 2594 InFlag = Chain.getValue(1); 2595 } 2596 2597 // Handle result values, copying them out of physregs into vregs that we 2598 // return. 2599 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2600 Ins, dl, DAG, InVals); 2601} 2602 2603 2604//===----------------------------------------------------------------------===// 2605// Fast Calling Convention (tail call) implementation 2606//===----------------------------------------------------------------------===// 2607 2608// Like std call, callee cleans arguments, convention except that ECX is 2609// reserved for storing the tail called function address. Only 2 registers are 2610// free for argument passing (inreg). Tail call optimization is performed 2611// provided: 2612// * tailcallopt is enabled 2613// * caller/callee are fastcc 2614// On X86_64 architecture with GOT-style position independent code only local 2615// (within module) calls are supported at the moment. 2616// To keep the stack aligned according to platform abi the function 2617// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2618// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2619// If a tail called function callee has more arguments than the caller the 2620// caller needs to make sure that there is room to move the RETADDR to. This is 2621// achieved by reserving an area the size of the argument delta right after the 2622// original REtADDR, but before the saved framepointer or the spilled registers 2623// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2624// stack layout: 2625// arg1 2626// arg2 2627// RETADDR 2628// [ new RETADDR 2629// move area ] 2630// (possible EBP) 2631// ESI 2632// EDI 2633// local1 .. 2634 2635/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2636/// for a 16 byte align requirement. 2637unsigned 2638X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2639 SelectionDAG& DAG) const { 2640 MachineFunction &MF = DAG.getMachineFunction(); 2641 const TargetMachine &TM = MF.getTarget(); 2642 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2643 unsigned StackAlignment = TFI.getStackAlignment(); 2644 uint64_t AlignMask = StackAlignment - 1; 2645 int64_t Offset = StackSize; 2646 uint64_t SlotSize = TD->getPointerSize(); 2647 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2648 // Number smaller than 12 so just add the difference. 2649 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2650 } else { 2651 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2652 Offset = ((~AlignMask) & Offset) + StackAlignment + 2653 (StackAlignment-SlotSize); 2654 } 2655 return Offset; 2656} 2657 2658/// MatchingStackOffset - Return true if the given stack call argument is 2659/// already available in the same position (relatively) of the caller's 2660/// incoming argument stack. 2661static 2662bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2663 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2664 const X86InstrInfo *TII) { 2665 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2666 int FI = INT_MAX; 2667 if (Arg.getOpcode() == ISD::CopyFromReg) { 2668 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2669 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2670 return false; 2671 MachineInstr *Def = MRI->getVRegDef(VR); 2672 if (!Def) 2673 return false; 2674 if (!Flags.isByVal()) { 2675 if (!TII->isLoadFromStackSlot(Def, FI)) 2676 return false; 2677 } else { 2678 unsigned Opcode = Def->getOpcode(); 2679 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2680 Def->getOperand(1).isFI()) { 2681 FI = Def->getOperand(1).getIndex(); 2682 Bytes = Flags.getByValSize(); 2683 } else 2684 return false; 2685 } 2686 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2687 if (Flags.isByVal()) 2688 // ByVal argument is passed in as a pointer but it's now being 2689 // dereferenced. e.g. 2690 // define @foo(%struct.X* %A) { 2691 // tail call @bar(%struct.X* byval %A) 2692 // } 2693 return false; 2694 SDValue Ptr = Ld->getBasePtr(); 2695 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2696 if (!FINode) 2697 return false; 2698 FI = FINode->getIndex(); 2699 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2700 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2701 FI = FINode->getIndex(); 2702 Bytes = Flags.getByValSize(); 2703 } else 2704 return false; 2705 2706 assert(FI != INT_MAX); 2707 if (!MFI->isFixedObjectIndex(FI)) 2708 return false; 2709 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2710} 2711 2712/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2713/// for tail call optimization. Targets which want to do tail call 2714/// optimization should implement this function. 2715bool 2716X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2717 CallingConv::ID CalleeCC, 2718 bool isVarArg, 2719 bool isCalleeStructRet, 2720 bool isCallerStructRet, 2721 const SmallVectorImpl<ISD::OutputArg> &Outs, 2722 const SmallVectorImpl<SDValue> &OutVals, 2723 const SmallVectorImpl<ISD::InputArg> &Ins, 2724 SelectionDAG& DAG) const { 2725 if (!IsTailCallConvention(CalleeCC) && 2726 CalleeCC != CallingConv::C) 2727 return false; 2728 2729 // If -tailcallopt is specified, make fastcc functions tail-callable. 2730 const MachineFunction &MF = DAG.getMachineFunction(); 2731 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2732 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2733 bool CCMatch = CallerCC == CalleeCC; 2734 2735 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2736 if (IsTailCallConvention(CalleeCC) && CCMatch) 2737 return true; 2738 return false; 2739 } 2740 2741 // Look for obvious safe cases to perform tail call optimization that do not 2742 // require ABI changes. This is what gcc calls sibcall. 2743 2744 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2745 // emit a special epilogue. 2746 if (RegInfo->needsStackRealignment(MF)) 2747 return false; 2748 2749 // Also avoid sibcall optimization if either caller or callee uses struct 2750 // return semantics. 2751 if (isCalleeStructRet || isCallerStructRet) 2752 return false; 2753 2754 // An stdcall caller is expected to clean up its arguments; the callee 2755 // isn't going to do that. 2756 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2757 return false; 2758 2759 // Do not sibcall optimize vararg calls unless all arguments are passed via 2760 // registers. 2761 if (isVarArg && !Outs.empty()) { 2762 2763 // Optimizing for varargs on Win64 is unlikely to be safe without 2764 // additional testing. 2765 if (Subtarget->isTargetWin64()) 2766 return false; 2767 2768 SmallVector<CCValAssign, 16> ArgLocs; 2769 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2770 getTargetMachine(), ArgLocs, *DAG.getContext()); 2771 2772 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2774 if (!ArgLocs[i].isRegLoc()) 2775 return false; 2776 } 2777 2778 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2779 // stack. Therefore, if it's not used by the call it is not safe to optimize 2780 // this into a sibcall. 2781 bool Unused = false; 2782 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2783 if (!Ins[i].Used) { 2784 Unused = true; 2785 break; 2786 } 2787 } 2788 if (Unused) { 2789 SmallVector<CCValAssign, 16> RVLocs; 2790 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2791 getTargetMachine(), RVLocs, *DAG.getContext()); 2792 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2793 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2794 CCValAssign &VA = RVLocs[i]; 2795 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2796 return false; 2797 } 2798 } 2799 2800 // If the calling conventions do not match, then we'd better make sure the 2801 // results are returned in the same way as what the caller expects. 2802 if (!CCMatch) { 2803 SmallVector<CCValAssign, 16> RVLocs1; 2804 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2805 getTargetMachine(), RVLocs1, *DAG.getContext()); 2806 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2807 2808 SmallVector<CCValAssign, 16> RVLocs2; 2809 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2810 getTargetMachine(), RVLocs2, *DAG.getContext()); 2811 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2812 2813 if (RVLocs1.size() != RVLocs2.size()) 2814 return false; 2815 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2816 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2817 return false; 2818 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2819 return false; 2820 if (RVLocs1[i].isRegLoc()) { 2821 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2822 return false; 2823 } else { 2824 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2825 return false; 2826 } 2827 } 2828 } 2829 2830 // If the callee takes no arguments then go on to check the results of the 2831 // call. 2832 if (!Outs.empty()) { 2833 // Check if stack adjustment is needed. For now, do not do this if any 2834 // argument is passed on the stack. 2835 SmallVector<CCValAssign, 16> ArgLocs; 2836 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2837 getTargetMachine(), ArgLocs, *DAG.getContext()); 2838 2839 // Allocate shadow area for Win64 2840 if (Subtarget->isTargetWin64()) { 2841 CCInfo.AllocateStack(32, 8); 2842 } 2843 2844 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2845 if (CCInfo.getNextStackOffset()) { 2846 MachineFunction &MF = DAG.getMachineFunction(); 2847 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2848 return false; 2849 2850 // Check if the arguments are already laid out in the right way as 2851 // the caller's fixed stack objects. 2852 MachineFrameInfo *MFI = MF.getFrameInfo(); 2853 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2854 const X86InstrInfo *TII = 2855 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2856 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2857 CCValAssign &VA = ArgLocs[i]; 2858 SDValue Arg = OutVals[i]; 2859 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2860 if (VA.getLocInfo() == CCValAssign::Indirect) 2861 return false; 2862 if (!VA.isRegLoc()) { 2863 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2864 MFI, MRI, TII)) 2865 return false; 2866 } 2867 } 2868 } 2869 2870 // If the tailcall address may be in a register, then make sure it's 2871 // possible to register allocate for it. In 32-bit, the call address can 2872 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2873 // callee-saved registers are restored. These happen to be the same 2874 // registers used to pass 'inreg' arguments so watch out for those. 2875 if (!Subtarget->is64Bit() && 2876 !isa<GlobalAddressSDNode>(Callee) && 2877 !isa<ExternalSymbolSDNode>(Callee)) { 2878 unsigned NumInRegs = 0; 2879 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2880 CCValAssign &VA = ArgLocs[i]; 2881 if (!VA.isRegLoc()) 2882 continue; 2883 unsigned Reg = VA.getLocReg(); 2884 switch (Reg) { 2885 default: break; 2886 case X86::EAX: case X86::EDX: case X86::ECX: 2887 if (++NumInRegs == 3) 2888 return false; 2889 break; 2890 } 2891 } 2892 } 2893 } 2894 2895 return true; 2896} 2897 2898FastISel * 2899X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2900 return X86::createFastISel(funcInfo); 2901} 2902 2903 2904//===----------------------------------------------------------------------===// 2905// Other Lowering Hooks 2906//===----------------------------------------------------------------------===// 2907 2908static bool MayFoldLoad(SDValue Op) { 2909 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2910} 2911 2912static bool MayFoldIntoStore(SDValue Op) { 2913 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2914} 2915 2916static bool isTargetShuffle(unsigned Opcode) { 2917 switch(Opcode) { 2918 default: return false; 2919 case X86ISD::PSHUFD: 2920 case X86ISD::PSHUFHW: 2921 case X86ISD::PSHUFLW: 2922 case X86ISD::SHUFP: 2923 case X86ISD::PALIGN: 2924 case X86ISD::MOVLHPS: 2925 case X86ISD::MOVLHPD: 2926 case X86ISD::MOVHLPS: 2927 case X86ISD::MOVLPS: 2928 case X86ISD::MOVLPD: 2929 case X86ISD::MOVSHDUP: 2930 case X86ISD::MOVSLDUP: 2931 case X86ISD::MOVDDUP: 2932 case X86ISD::MOVSS: 2933 case X86ISD::MOVSD: 2934 case X86ISD::UNPCKL: 2935 case X86ISD::UNPCKH: 2936 case X86ISD::VPERMILP: 2937 case X86ISD::VPERM2X128: 2938 case X86ISD::VPERMI: 2939 return true; 2940 } 2941} 2942 2943static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2944 SDValue V1, SelectionDAG &DAG) { 2945 switch(Opc) { 2946 default: llvm_unreachable("Unknown x86 shuffle node"); 2947 case X86ISD::MOVSHDUP: 2948 case X86ISD::MOVSLDUP: 2949 case X86ISD::MOVDDUP: 2950 return DAG.getNode(Opc, dl, VT, V1); 2951 } 2952} 2953 2954static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2955 SDValue V1, unsigned TargetMask, 2956 SelectionDAG &DAG) { 2957 switch(Opc) { 2958 default: llvm_unreachable("Unknown x86 shuffle node"); 2959 case X86ISD::PSHUFD: 2960 case X86ISD::PSHUFHW: 2961 case X86ISD::PSHUFLW: 2962 case X86ISD::VPERMILP: 2963 case X86ISD::VPERMI: 2964 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2965 } 2966} 2967 2968static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2969 SDValue V1, SDValue V2, unsigned TargetMask, 2970 SelectionDAG &DAG) { 2971 switch(Opc) { 2972 default: llvm_unreachable("Unknown x86 shuffle node"); 2973 case X86ISD::PALIGN: 2974 case X86ISD::SHUFP: 2975 case X86ISD::VPERM2X128: 2976 return DAG.getNode(Opc, dl, VT, V1, V2, 2977 DAG.getConstant(TargetMask, MVT::i8)); 2978 } 2979} 2980 2981static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2982 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2983 switch(Opc) { 2984 default: llvm_unreachable("Unknown x86 shuffle node"); 2985 case X86ISD::MOVLHPS: 2986 case X86ISD::MOVLHPD: 2987 case X86ISD::MOVHLPS: 2988 case X86ISD::MOVLPS: 2989 case X86ISD::MOVLPD: 2990 case X86ISD::MOVSS: 2991 case X86ISD::MOVSD: 2992 case X86ISD::UNPCKL: 2993 case X86ISD::UNPCKH: 2994 return DAG.getNode(Opc, dl, VT, V1, V2); 2995 } 2996} 2997 2998SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2999 MachineFunction &MF = DAG.getMachineFunction(); 3000 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 3001 int ReturnAddrIndex = FuncInfo->getRAIndex(); 3002 3003 if (ReturnAddrIndex == 0) { 3004 // Set up a frame object for the return address. 3005 uint64_t SlotSize = TD->getPointerSize(); 3006 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 3007 false); 3008 FuncInfo->setRAIndex(ReturnAddrIndex); 3009 } 3010 3011 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 3012} 3013 3014 3015bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 3016 bool hasSymbolicDisplacement) { 3017 // Offset should fit into 32 bit immediate field. 3018 if (!isInt<32>(Offset)) 3019 return false; 3020 3021 // If we don't have a symbolic displacement - we don't have any extra 3022 // restrictions. 3023 if (!hasSymbolicDisplacement) 3024 return true; 3025 3026 // FIXME: Some tweaks might be needed for medium code model. 3027 if (M != CodeModel::Small && M != CodeModel::Kernel) 3028 return false; 3029 3030 // For small code model we assume that latest object is 16MB before end of 31 3031 // bits boundary. We may also accept pretty large negative constants knowing 3032 // that all objects are in the positive half of address space. 3033 if (M == CodeModel::Small && Offset < 16*1024*1024) 3034 return true; 3035 3036 // For kernel code model we know that all object resist in the negative half 3037 // of 32bits address space. We may not accept negative offsets, since they may 3038 // be just off and we may accept pretty large positive ones. 3039 if (M == CodeModel::Kernel && Offset > 0) 3040 return true; 3041 3042 return false; 3043} 3044 3045/// isCalleePop - Determines whether the callee is required to pop its 3046/// own arguments. Callee pop is necessary to support tail calls. 3047bool X86::isCalleePop(CallingConv::ID CallingConv, 3048 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3049 if (IsVarArg) 3050 return false; 3051 3052 switch (CallingConv) { 3053 default: 3054 return false; 3055 case CallingConv::X86_StdCall: 3056 return !is64Bit; 3057 case CallingConv::X86_FastCall: 3058 return !is64Bit; 3059 case CallingConv::X86_ThisCall: 3060 return !is64Bit; 3061 case CallingConv::Fast: 3062 return TailCallOpt; 3063 case CallingConv::GHC: 3064 return TailCallOpt; 3065 } 3066} 3067 3068/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3069/// specific condition code, returning the condition code and the LHS/RHS of the 3070/// comparison to make. 3071static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3072 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3073 if (!isFP) { 3074 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3075 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3076 // X > -1 -> X == 0, jump !sign. 3077 RHS = DAG.getConstant(0, RHS.getValueType()); 3078 return X86::COND_NS; 3079 } 3080 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3081 // X < 0 -> X == 0, jump on sign. 3082 return X86::COND_S; 3083 } 3084 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3085 // X < 1 -> X <= 0 3086 RHS = DAG.getConstant(0, RHS.getValueType()); 3087 return X86::COND_LE; 3088 } 3089 } 3090 3091 switch (SetCCOpcode) { 3092 default: llvm_unreachable("Invalid integer condition!"); 3093 case ISD::SETEQ: return X86::COND_E; 3094 case ISD::SETGT: return X86::COND_G; 3095 case ISD::SETGE: return X86::COND_GE; 3096 case ISD::SETLT: return X86::COND_L; 3097 case ISD::SETLE: return X86::COND_LE; 3098 case ISD::SETNE: return X86::COND_NE; 3099 case ISD::SETULT: return X86::COND_B; 3100 case ISD::SETUGT: return X86::COND_A; 3101 case ISD::SETULE: return X86::COND_BE; 3102 case ISD::SETUGE: return X86::COND_AE; 3103 } 3104 } 3105 3106 // First determine if it is required or is profitable to flip the operands. 3107 3108 // If LHS is a foldable load, but RHS is not, flip the condition. 3109 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3110 !ISD::isNON_EXTLoad(RHS.getNode())) { 3111 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3112 std::swap(LHS, RHS); 3113 } 3114 3115 switch (SetCCOpcode) { 3116 default: break; 3117 case ISD::SETOLT: 3118 case ISD::SETOLE: 3119 case ISD::SETUGT: 3120 case ISD::SETUGE: 3121 std::swap(LHS, RHS); 3122 break; 3123 } 3124 3125 // On a floating point condition, the flags are set as follows: 3126 // ZF PF CF op 3127 // 0 | 0 | 0 | X > Y 3128 // 0 | 0 | 1 | X < Y 3129 // 1 | 0 | 0 | X == Y 3130 // 1 | 1 | 1 | unordered 3131 switch (SetCCOpcode) { 3132 default: llvm_unreachable("Condcode should be pre-legalized away"); 3133 case ISD::SETUEQ: 3134 case ISD::SETEQ: return X86::COND_E; 3135 case ISD::SETOLT: // flipped 3136 case ISD::SETOGT: 3137 case ISD::SETGT: return X86::COND_A; 3138 case ISD::SETOLE: // flipped 3139 case ISD::SETOGE: 3140 case ISD::SETGE: return X86::COND_AE; 3141 case ISD::SETUGT: // flipped 3142 case ISD::SETULT: 3143 case ISD::SETLT: return X86::COND_B; 3144 case ISD::SETUGE: // flipped 3145 case ISD::SETULE: 3146 case ISD::SETLE: return X86::COND_BE; 3147 case ISD::SETONE: 3148 case ISD::SETNE: return X86::COND_NE; 3149 case ISD::SETUO: return X86::COND_P; 3150 case ISD::SETO: return X86::COND_NP; 3151 case ISD::SETOEQ: 3152 case ISD::SETUNE: return X86::COND_INVALID; 3153 } 3154} 3155 3156/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3157/// code. Current x86 isa includes the following FP cmov instructions: 3158/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3159static bool hasFPCMov(unsigned X86CC) { 3160 switch (X86CC) { 3161 default: 3162 return false; 3163 case X86::COND_B: 3164 case X86::COND_BE: 3165 case X86::COND_E: 3166 case X86::COND_P: 3167 case X86::COND_A: 3168 case X86::COND_AE: 3169 case X86::COND_NE: 3170 case X86::COND_NP: 3171 return true; 3172 } 3173} 3174 3175/// isFPImmLegal - Returns true if the target can instruction select the 3176/// specified FP immediate natively. If false, the legalizer will 3177/// materialize the FP immediate as a load from a constant pool. 3178bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3179 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3180 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3181 return true; 3182 } 3183 return false; 3184} 3185 3186/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3187/// the specified range (L, H]. 3188static bool isUndefOrInRange(int Val, int Low, int Hi) { 3189 return (Val < 0) || (Val >= Low && Val < Hi); 3190} 3191 3192/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3193/// specified value. 3194static bool isUndefOrEqual(int Val, int CmpVal) { 3195 if (Val < 0 || Val == CmpVal) 3196 return true; 3197 return false; 3198} 3199 3200/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning 3201/// from position Pos and ending in Pos+Size, falls within the specified 3202/// sequential range (L, L+Pos]. or is undef. 3203static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3204 unsigned Pos, unsigned Size, int Low) { 3205 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3206 if (!isUndefOrEqual(Mask[i], Low)) 3207 return false; 3208 return true; 3209} 3210 3211/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3212/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3213/// the second operand. 3214static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3215 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3216 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3217 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3218 return (Mask[0] < 2 && Mask[1] < 2); 3219 return false; 3220} 3221 3222/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3223/// is suitable for input to PSHUFHW. 3224static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3225 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3226 return false; 3227 3228 // Lower quadword copied in order or undef. 3229 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3230 return false; 3231 3232 // Upper quadword shuffled. 3233 for (unsigned i = 4; i != 8; ++i) 3234 if (!isUndefOrInRange(Mask[i], 4, 8)) 3235 return false; 3236 3237 if (VT == MVT::v16i16) { 3238 // Lower quadword copied in order or undef. 3239 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3240 return false; 3241 3242 // Upper quadword shuffled. 3243 for (unsigned i = 12; i != 16; ++i) 3244 if (!isUndefOrInRange(Mask[i], 12, 16)) 3245 return false; 3246 } 3247 3248 return true; 3249} 3250 3251/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3252/// is suitable for input to PSHUFLW. 3253static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3254 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3255 return false; 3256 3257 // Upper quadword copied in order. 3258 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3259 return false; 3260 3261 // Lower quadword shuffled. 3262 for (unsigned i = 0; i != 4; ++i) 3263 if (!isUndefOrInRange(Mask[i], 0, 4)) 3264 return false; 3265 3266 if (VT == MVT::v16i16) { 3267 // Upper quadword copied in order. 3268 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3269 return false; 3270 3271 // Lower quadword shuffled. 3272 for (unsigned i = 8; i != 12; ++i) 3273 if (!isUndefOrInRange(Mask[i], 8, 12)) 3274 return false; 3275 } 3276 3277 return true; 3278} 3279 3280/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3281/// is suitable for input to PALIGNR. 3282static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3283 const X86Subtarget *Subtarget) { 3284 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3285 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3286 return false; 3287 3288 unsigned NumElts = VT.getVectorNumElements(); 3289 unsigned NumLanes = VT.getSizeInBits()/128; 3290 unsigned NumLaneElts = NumElts/NumLanes; 3291 3292 // Do not handle 64-bit element shuffles with palignr. 3293 if (NumLaneElts == 2) 3294 return false; 3295 3296 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3297 unsigned i; 3298 for (i = 0; i != NumLaneElts; ++i) { 3299 if (Mask[i+l] >= 0) 3300 break; 3301 } 3302 3303 // Lane is all undef, go to next lane 3304 if (i == NumLaneElts) 3305 continue; 3306 3307 int Start = Mask[i+l]; 3308 3309 // Make sure its in this lane in one of the sources 3310 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3311 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3312 return false; 3313 3314 // If not lane 0, then we must match lane 0 3315 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3316 return false; 3317 3318 // Correct second source to be contiguous with first source 3319 if (Start >= (int)NumElts) 3320 Start -= NumElts - NumLaneElts; 3321 3322 // Make sure we're shifting in the right direction. 3323 if (Start <= (int)(i+l)) 3324 return false; 3325 3326 Start -= i; 3327 3328 // Check the rest of the elements to see if they are consecutive. 3329 for (++i; i != NumLaneElts; ++i) { 3330 int Idx = Mask[i+l]; 3331 3332 // Make sure its in this lane 3333 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3334 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3335 return false; 3336 3337 // If not lane 0, then we must match lane 0 3338 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3339 return false; 3340 3341 if (Idx >= (int)NumElts) 3342 Idx -= NumElts - NumLaneElts; 3343 3344 if (!isUndefOrEqual(Idx, Start+i)) 3345 return false; 3346 3347 } 3348 } 3349 3350 return true; 3351} 3352 3353/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3354/// the two vector operands have swapped position. 3355static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3356 unsigned NumElems) { 3357 for (unsigned i = 0; i != NumElems; ++i) { 3358 int idx = Mask[i]; 3359 if (idx < 0) 3360 continue; 3361 else if (idx < (int)NumElems) 3362 Mask[i] = idx + NumElems; 3363 else 3364 Mask[i] = idx - NumElems; 3365 } 3366} 3367 3368/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3369/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3370/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3371/// reverse of what x86 shuffles want. 3372static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3373 bool Commuted = false) { 3374 if (!HasAVX && VT.getSizeInBits() == 256) 3375 return false; 3376 3377 unsigned NumElems = VT.getVectorNumElements(); 3378 unsigned NumLanes = VT.getSizeInBits()/128; 3379 unsigned NumLaneElems = NumElems/NumLanes; 3380 3381 if (NumLaneElems != 2 && NumLaneElems != 4) 3382 return false; 3383 3384 // VSHUFPSY divides the resulting vector into 4 chunks. 3385 // The sources are also splitted into 4 chunks, and each destination 3386 // chunk must come from a different source chunk. 3387 // 3388 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3389 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3390 // 3391 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3392 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3393 // 3394 // VSHUFPDY divides the resulting vector into 4 chunks. 3395 // The sources are also splitted into 4 chunks, and each destination 3396 // chunk must come from a different source chunk. 3397 // 3398 // SRC1 => X3 X2 X1 X0 3399 // SRC2 => Y3 Y2 Y1 Y0 3400 // 3401 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3402 // 3403 unsigned HalfLaneElems = NumLaneElems/2; 3404 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3405 for (unsigned i = 0; i != NumLaneElems; ++i) { 3406 int Idx = Mask[i+l]; 3407 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3408 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3409 return false; 3410 // For VSHUFPSY, the mask of the second half must be the same as the 3411 // first but with the appropriate offsets. This works in the same way as 3412 // VPERMILPS works with masks. 3413 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3414 continue; 3415 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3416 return false; 3417 } 3418 } 3419 3420 return true; 3421} 3422 3423/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3424/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3425static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3426 unsigned NumElems = VT.getVectorNumElements(); 3427 3428 if (VT.getSizeInBits() != 128) 3429 return false; 3430 3431 if (NumElems != 4) 3432 return false; 3433 3434 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3435 return isUndefOrEqual(Mask[0], 6) && 3436 isUndefOrEqual(Mask[1], 7) && 3437 isUndefOrEqual(Mask[2], 2) && 3438 isUndefOrEqual(Mask[3], 3); 3439} 3440 3441/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3442/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3443/// <2, 3, 2, 3> 3444static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3445 unsigned NumElems = VT.getVectorNumElements(); 3446 3447 if (VT.getSizeInBits() != 128) 3448 return false; 3449 3450 if (NumElems != 4) 3451 return false; 3452 3453 return isUndefOrEqual(Mask[0], 2) && 3454 isUndefOrEqual(Mask[1], 3) && 3455 isUndefOrEqual(Mask[2], 2) && 3456 isUndefOrEqual(Mask[3], 3); 3457} 3458 3459/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3460/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3461static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3462 if (VT.getSizeInBits() != 128) 3463 return false; 3464 3465 unsigned NumElems = VT.getVectorNumElements(); 3466 3467 if (NumElems != 2 && NumElems != 4) 3468 return false; 3469 3470 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3471 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3472 return false; 3473 3474 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3475 if (!isUndefOrEqual(Mask[i], i)) 3476 return false; 3477 3478 return true; 3479} 3480 3481/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3482/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3483static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3484 unsigned NumElems = VT.getVectorNumElements(); 3485 3486 if ((NumElems != 2 && NumElems != 4) 3487 || VT.getSizeInBits() > 128) 3488 return false; 3489 3490 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3491 if (!isUndefOrEqual(Mask[i], i)) 3492 return false; 3493 3494 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3495 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3496 return false; 3497 3498 return true; 3499} 3500 3501// 3502// Some special combinations that can be optimized. 3503// 3504static 3505SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, 3506 SelectionDAG &DAG) { 3507 EVT VT = SVOp->getValueType(0); 3508 DebugLoc dl = SVOp->getDebugLoc(); 3509 3510 if (VT != MVT::v8i32 && VT != MVT::v8f32) 3511 return SDValue(); 3512 3513 ArrayRef<int> Mask = SVOp->getMask(); 3514 3515 // These are the special masks that may be optimized. 3516 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14}; 3517 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15}; 3518 bool MatchEvenMask = true; 3519 bool MatchOddMask = true; 3520 for (int i=0; i<8; ++i) { 3521 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i])) 3522 MatchEvenMask = false; 3523 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i])) 3524 MatchOddMask = false; 3525 } 3526 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1}; 3527 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1}; 3528 3529 const int *CompactionMask; 3530 if (MatchEvenMask) 3531 CompactionMask = CompactionMaskEven; 3532 else if (MatchOddMask) 3533 CompactionMask = CompactionMaskOdd; 3534 else 3535 return SDValue(); 3536 3537 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT); 3538 3539 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0), 3540 UndefNode, CompactionMask); 3541 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1), 3542 UndefNode, CompactionMask); 3543 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13}; 3544 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask); 3545} 3546 3547/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3548/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3549static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3550 bool HasAVX2, bool V2IsSplat = false) { 3551 unsigned NumElts = VT.getVectorNumElements(); 3552 3553 assert((VT.is128BitVector() || VT.is256BitVector()) && 3554 "Unsupported vector type for unpckh"); 3555 3556 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3557 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3558 return false; 3559 3560 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3561 // independently on 128-bit lanes. 3562 unsigned NumLanes = VT.getSizeInBits()/128; 3563 unsigned NumLaneElts = NumElts/NumLanes; 3564 3565 for (unsigned l = 0; l != NumLanes; ++l) { 3566 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3567 i != (l+1)*NumLaneElts; 3568 i += 2, ++j) { 3569 int BitI = Mask[i]; 3570 int BitI1 = Mask[i+1]; 3571 if (!isUndefOrEqual(BitI, j)) 3572 return false; 3573 if (V2IsSplat) { 3574 if (!isUndefOrEqual(BitI1, NumElts)) 3575 return false; 3576 } else { 3577 if (!isUndefOrEqual(BitI1, j + NumElts)) 3578 return false; 3579 } 3580 } 3581 } 3582 3583 return true; 3584} 3585 3586/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3587/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3588static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3589 bool HasAVX2, bool V2IsSplat = false) { 3590 unsigned NumElts = VT.getVectorNumElements(); 3591 3592 assert((VT.is128BitVector() || VT.is256BitVector()) && 3593 "Unsupported vector type for unpckh"); 3594 3595 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3596 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3597 return false; 3598 3599 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3600 // independently on 128-bit lanes. 3601 unsigned NumLanes = VT.getSizeInBits()/128; 3602 unsigned NumLaneElts = NumElts/NumLanes; 3603 3604 for (unsigned l = 0; l != NumLanes; ++l) { 3605 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3606 i != (l+1)*NumLaneElts; i += 2, ++j) { 3607 int BitI = Mask[i]; 3608 int BitI1 = Mask[i+1]; 3609 if (!isUndefOrEqual(BitI, j)) 3610 return false; 3611 if (V2IsSplat) { 3612 if (isUndefOrEqual(BitI1, NumElts)) 3613 return false; 3614 } else { 3615 if (!isUndefOrEqual(BitI1, j+NumElts)) 3616 return false; 3617 } 3618 } 3619 } 3620 return true; 3621} 3622 3623/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3624/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3625/// <0, 0, 1, 1> 3626static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3627 bool HasAVX2) { 3628 unsigned NumElts = VT.getVectorNumElements(); 3629 3630 assert((VT.is128BitVector() || VT.is256BitVector()) && 3631 "Unsupported vector type for unpckh"); 3632 3633 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3634 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3635 return false; 3636 3637 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3638 // FIXME: Need a better way to get rid of this, there's no latency difference 3639 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3640 // the former later. We should also remove the "_undef" special mask. 3641 if (NumElts == 4 && VT.getSizeInBits() == 256) 3642 return false; 3643 3644 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3645 // independently on 128-bit lanes. 3646 unsigned NumLanes = VT.getSizeInBits()/128; 3647 unsigned NumLaneElts = NumElts/NumLanes; 3648 3649 for (unsigned l = 0; l != NumLanes; ++l) { 3650 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3651 i != (l+1)*NumLaneElts; 3652 i += 2, ++j) { 3653 int BitI = Mask[i]; 3654 int BitI1 = Mask[i+1]; 3655 3656 if (!isUndefOrEqual(BitI, j)) 3657 return false; 3658 if (!isUndefOrEqual(BitI1, j)) 3659 return false; 3660 } 3661 } 3662 3663 return true; 3664} 3665 3666/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3667/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3668/// <2, 2, 3, 3> 3669static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3670 unsigned NumElts = VT.getVectorNumElements(); 3671 3672 assert((VT.is128BitVector() || VT.is256BitVector()) && 3673 "Unsupported vector type for unpckh"); 3674 3675 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3676 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3677 return false; 3678 3679 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3680 // independently on 128-bit lanes. 3681 unsigned NumLanes = VT.getSizeInBits()/128; 3682 unsigned NumLaneElts = NumElts/NumLanes; 3683 3684 for (unsigned l = 0; l != NumLanes; ++l) { 3685 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3686 i != (l+1)*NumLaneElts; i += 2, ++j) { 3687 int BitI = Mask[i]; 3688 int BitI1 = Mask[i+1]; 3689 if (!isUndefOrEqual(BitI, j)) 3690 return false; 3691 if (!isUndefOrEqual(BitI1, j)) 3692 return false; 3693 } 3694 } 3695 return true; 3696} 3697 3698/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3699/// specifies a shuffle of elements that is suitable for input to MOVSS, 3700/// MOVSD, and MOVD, i.e. setting the lowest element. 3701static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3702 if (VT.getVectorElementType().getSizeInBits() < 32) 3703 return false; 3704 if (VT.getSizeInBits() == 256) 3705 return false; 3706 3707 unsigned NumElts = VT.getVectorNumElements(); 3708 3709 if (!isUndefOrEqual(Mask[0], NumElts)) 3710 return false; 3711 3712 for (unsigned i = 1; i != NumElts; ++i) 3713 if (!isUndefOrEqual(Mask[i], i)) 3714 return false; 3715 3716 return true; 3717} 3718 3719/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3720/// as permutations between 128-bit chunks or halves. As an example: this 3721/// shuffle bellow: 3722/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3723/// The first half comes from the second half of V1 and the second half from the 3724/// the second half of V2. 3725static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3726 if (!HasAVX || VT.getSizeInBits() != 256) 3727 return false; 3728 3729 // The shuffle result is divided into half A and half B. In total the two 3730 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3731 // B must come from C, D, E or F. 3732 unsigned HalfSize = VT.getVectorNumElements()/2; 3733 bool MatchA = false, MatchB = false; 3734 3735 // Check if A comes from one of C, D, E, F. 3736 for (unsigned Half = 0; Half != 4; ++Half) { 3737 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3738 MatchA = true; 3739 break; 3740 } 3741 } 3742 3743 // Check if B comes from one of C, D, E, F. 3744 for (unsigned Half = 0; Half != 4; ++Half) { 3745 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3746 MatchB = true; 3747 break; 3748 } 3749 } 3750 3751 return MatchA && MatchB; 3752} 3753 3754/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3755/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3756static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3757 EVT VT = SVOp->getValueType(0); 3758 3759 unsigned HalfSize = VT.getVectorNumElements()/2; 3760 3761 unsigned FstHalf = 0, SndHalf = 0; 3762 for (unsigned i = 0; i < HalfSize; ++i) { 3763 if (SVOp->getMaskElt(i) > 0) { 3764 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3765 break; 3766 } 3767 } 3768 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3769 if (SVOp->getMaskElt(i) > 0) { 3770 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3771 break; 3772 } 3773 } 3774 3775 return (FstHalf | (SndHalf << 4)); 3776} 3777 3778/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3779/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3780/// Note that VPERMIL mask matching is different depending whether theunderlying 3781/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3782/// to the same elements of the low, but to the higher half of the source. 3783/// In VPERMILPD the two lanes could be shuffled independently of each other 3784/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3785static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3786 if (!HasAVX) 3787 return false; 3788 3789 unsigned NumElts = VT.getVectorNumElements(); 3790 // Only match 256-bit with 32/64-bit types 3791 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3792 return false; 3793 3794 unsigned NumLanes = VT.getSizeInBits()/128; 3795 unsigned LaneSize = NumElts/NumLanes; 3796 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3797 for (unsigned i = 0; i != LaneSize; ++i) { 3798 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3799 return false; 3800 if (NumElts != 8 || l == 0) 3801 continue; 3802 // VPERMILPS handling 3803 if (Mask[i] < 0) 3804 continue; 3805 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3806 return false; 3807 } 3808 } 3809 3810 return true; 3811} 3812 3813/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3814/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3815/// element of vector 2 and the other elements to come from vector 1 in order. 3816static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3817 bool V2IsSplat = false, bool V2IsUndef = false) { 3818 unsigned NumOps = VT.getVectorNumElements(); 3819 if (VT.getSizeInBits() == 256) 3820 return false; 3821 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3822 return false; 3823 3824 if (!isUndefOrEqual(Mask[0], 0)) 3825 return false; 3826 3827 for (unsigned i = 1; i != NumOps; ++i) 3828 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3829 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3830 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3831 return false; 3832 3833 return true; 3834} 3835 3836/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3837/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3838/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3839static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3840 const X86Subtarget *Subtarget) { 3841 if (!Subtarget->hasSSE3()) 3842 return false; 3843 3844 unsigned NumElems = VT.getVectorNumElements(); 3845 3846 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3847 (VT.getSizeInBits() == 256 && NumElems != 8)) 3848 return false; 3849 3850 // "i+1" is the value the indexed mask element must have 3851 for (unsigned i = 0; i != NumElems; i += 2) 3852 if (!isUndefOrEqual(Mask[i], i+1) || 3853 !isUndefOrEqual(Mask[i+1], i+1)) 3854 return false; 3855 3856 return true; 3857} 3858 3859/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3860/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3861/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3862static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3863 const X86Subtarget *Subtarget) { 3864 if (!Subtarget->hasSSE3()) 3865 return false; 3866 3867 unsigned NumElems = VT.getVectorNumElements(); 3868 3869 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3870 (VT.getSizeInBits() == 256 && NumElems != 8)) 3871 return false; 3872 3873 // "i" is the value the indexed mask element must have 3874 for (unsigned i = 0; i != NumElems; i += 2) 3875 if (!isUndefOrEqual(Mask[i], i) || 3876 !isUndefOrEqual(Mask[i+1], i)) 3877 return false; 3878 3879 return true; 3880} 3881 3882/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3883/// specifies a shuffle of elements that is suitable for input to 256-bit 3884/// version of MOVDDUP. 3885static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3886 unsigned NumElts = VT.getVectorNumElements(); 3887 3888 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3889 return false; 3890 3891 for (unsigned i = 0; i != NumElts/2; ++i) 3892 if (!isUndefOrEqual(Mask[i], 0)) 3893 return false; 3894 for (unsigned i = NumElts/2; i != NumElts; ++i) 3895 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3896 return false; 3897 return true; 3898} 3899 3900/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3901/// specifies a shuffle of elements that is suitable for input to 128-bit 3902/// version of MOVDDUP. 3903static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3904 if (VT.getSizeInBits() != 128) 3905 return false; 3906 3907 unsigned e = VT.getVectorNumElements() / 2; 3908 for (unsigned i = 0; i != e; ++i) 3909 if (!isUndefOrEqual(Mask[i], i)) 3910 return false; 3911 for (unsigned i = 0; i != e; ++i) 3912 if (!isUndefOrEqual(Mask[e+i], i)) 3913 return false; 3914 return true; 3915} 3916 3917/// isVEXTRACTF128Index - Return true if the specified 3918/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3919/// suitable for input to VEXTRACTF128. 3920bool X86::isVEXTRACTF128Index(SDNode *N) { 3921 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3922 return false; 3923 3924 // The index should be aligned on a 128-bit boundary. 3925 uint64_t Index = 3926 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3927 3928 unsigned VL = N->getValueType(0).getVectorNumElements(); 3929 unsigned VBits = N->getValueType(0).getSizeInBits(); 3930 unsigned ElSize = VBits / VL; 3931 bool Result = (Index * ElSize) % 128 == 0; 3932 3933 return Result; 3934} 3935 3936/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3937/// operand specifies a subvector insert that is suitable for input to 3938/// VINSERTF128. 3939bool X86::isVINSERTF128Index(SDNode *N) { 3940 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3941 return false; 3942 3943 // The index should be aligned on a 128-bit boundary. 3944 uint64_t Index = 3945 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3946 3947 unsigned VL = N->getValueType(0).getVectorNumElements(); 3948 unsigned VBits = N->getValueType(0).getSizeInBits(); 3949 unsigned ElSize = VBits / VL; 3950 bool Result = (Index * ElSize) % 128 == 0; 3951 3952 return Result; 3953} 3954 3955/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3956/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3957/// Handles 128-bit and 256-bit. 3958static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3959 EVT VT = N->getValueType(0); 3960 3961 assert((VT.is128BitVector() || VT.is256BitVector()) && 3962 "Unsupported vector type for PSHUF/SHUFP"); 3963 3964 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3965 // independently on 128-bit lanes. 3966 unsigned NumElts = VT.getVectorNumElements(); 3967 unsigned NumLanes = VT.getSizeInBits()/128; 3968 unsigned NumLaneElts = NumElts/NumLanes; 3969 3970 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3971 "Only supports 2 or 4 elements per lane"); 3972 3973 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3974 unsigned Mask = 0; 3975 for (unsigned i = 0; i != NumElts; ++i) { 3976 int Elt = N->getMaskElt(i); 3977 if (Elt < 0) continue; 3978 Elt &= NumLaneElts - 1; 3979 unsigned ShAmt = (i << Shift) % 8; 3980 Mask |= Elt << ShAmt; 3981 } 3982 3983 return Mask; 3984} 3985 3986/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3987/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3988static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3989 EVT VT = N->getValueType(0); 3990 3991 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 3992 "Unsupported vector type for PSHUFHW"); 3993 3994 unsigned NumElts = VT.getVectorNumElements(); 3995 3996 unsigned Mask = 0; 3997 for (unsigned l = 0; l != NumElts; l += 8) { 3998 // 8 nodes per lane, but we only care about the last 4. 3999 for (unsigned i = 0; i < 4; ++i) { 4000 int Elt = N->getMaskElt(l+i+4); 4001 if (Elt < 0) continue; 4002 Elt &= 0x3; // only 2-bits. 4003 Mask |= Elt << (i * 2); 4004 } 4005 } 4006 4007 return Mask; 4008} 4009 4010/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4011/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4012static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 4013 EVT VT = N->getValueType(0); 4014 4015 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 4016 "Unsupported vector type for PSHUFHW"); 4017 4018 unsigned NumElts = VT.getVectorNumElements(); 4019 4020 unsigned Mask = 0; 4021 for (unsigned l = 0; l != NumElts; l += 8) { 4022 // 8 nodes per lane, but we only care about the first 4. 4023 for (unsigned i = 0; i < 4; ++i) { 4024 int Elt = N->getMaskElt(l+i); 4025 if (Elt < 0) continue; 4026 Elt &= 0x3; // only 2-bits 4027 Mask |= Elt << (i * 2); 4028 } 4029 } 4030 4031 return Mask; 4032} 4033 4034/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4035/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4036static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4037 EVT VT = SVOp->getValueType(0); 4038 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4039 4040 unsigned NumElts = VT.getVectorNumElements(); 4041 unsigned NumLanes = VT.getSizeInBits()/128; 4042 unsigned NumLaneElts = NumElts/NumLanes; 4043 4044 int Val = 0; 4045 unsigned i; 4046 for (i = 0; i != NumElts; ++i) { 4047 Val = SVOp->getMaskElt(i); 4048 if (Val >= 0) 4049 break; 4050 } 4051 if (Val >= (int)NumElts) 4052 Val -= NumElts - NumLaneElts; 4053 4054 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4055 return (Val - i) * EltSize; 4056} 4057 4058/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4059/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4060/// instructions. 4061unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4062 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4063 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4064 4065 uint64_t Index = 4066 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4067 4068 EVT VecVT = N->getOperand(0).getValueType(); 4069 EVT ElVT = VecVT.getVectorElementType(); 4070 4071 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4072 return Index / NumElemsPerChunk; 4073} 4074 4075/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4076/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4077/// instructions. 4078unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4079 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4080 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4081 4082 uint64_t Index = 4083 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4084 4085 EVT VecVT = N->getValueType(0); 4086 EVT ElVT = VecVT.getVectorElementType(); 4087 4088 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4089 return Index / NumElemsPerChunk; 4090} 4091 4092/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 4093/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 4094/// Handles 256-bit. 4095static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 4096 EVT VT = N->getValueType(0); 4097 4098 unsigned NumElts = VT.getVectorNumElements(); 4099 4100 assert((VT.is256BitVector() && NumElts == 4) && 4101 "Unsupported vector type for VPERMQ/VPERMPD"); 4102 4103 unsigned Mask = 0; 4104 for (unsigned i = 0; i != NumElts; ++i) { 4105 int Elt = N->getMaskElt(i); 4106 if (Elt < 0) 4107 continue; 4108 Mask |= Elt << (i*2); 4109 } 4110 4111 return Mask; 4112} 4113/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4114/// constant +0.0. 4115bool X86::isZeroNode(SDValue Elt) { 4116 return ((isa<ConstantSDNode>(Elt) && 4117 cast<ConstantSDNode>(Elt)->isNullValue()) || 4118 (isa<ConstantFPSDNode>(Elt) && 4119 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4120} 4121 4122/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4123/// their permute mask. 4124static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4125 SelectionDAG &DAG) { 4126 EVT VT = SVOp->getValueType(0); 4127 unsigned NumElems = VT.getVectorNumElements(); 4128 SmallVector<int, 8> MaskVec; 4129 4130 for (unsigned i = 0; i != NumElems; ++i) { 4131 int Idx = SVOp->getMaskElt(i); 4132 if (Idx >= 0) { 4133 if (Idx < (int)NumElems) 4134 Idx += NumElems; 4135 else 4136 Idx -= NumElems; 4137 } 4138 MaskVec.push_back(Idx); 4139 } 4140 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4141 SVOp->getOperand(0), &MaskVec[0]); 4142} 4143 4144/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4145/// match movhlps. The lower half elements should come from upper half of 4146/// V1 (and in order), and the upper half elements should come from the upper 4147/// half of V2 (and in order). 4148static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4149 if (VT.getSizeInBits() != 128) 4150 return false; 4151 if (VT.getVectorNumElements() != 4) 4152 return false; 4153 for (unsigned i = 0, e = 2; i != e; ++i) 4154 if (!isUndefOrEqual(Mask[i], i+2)) 4155 return false; 4156 for (unsigned i = 2; i != 4; ++i) 4157 if (!isUndefOrEqual(Mask[i], i+4)) 4158 return false; 4159 return true; 4160} 4161 4162/// isScalarLoadToVector - Returns true if the node is a scalar load that 4163/// is promoted to a vector. It also returns the LoadSDNode by reference if 4164/// required. 4165static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4166 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4167 return false; 4168 N = N->getOperand(0).getNode(); 4169 if (!ISD::isNON_EXTLoad(N)) 4170 return false; 4171 if (LD) 4172 *LD = cast<LoadSDNode>(N); 4173 return true; 4174} 4175 4176// Test whether the given value is a vector value which will be legalized 4177// into a load. 4178static bool WillBeConstantPoolLoad(SDNode *N) { 4179 if (N->getOpcode() != ISD::BUILD_VECTOR) 4180 return false; 4181 4182 // Check for any non-constant elements. 4183 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4184 switch (N->getOperand(i).getNode()->getOpcode()) { 4185 case ISD::UNDEF: 4186 case ISD::ConstantFP: 4187 case ISD::Constant: 4188 break; 4189 default: 4190 return false; 4191 } 4192 4193 // Vectors of all-zeros and all-ones are materialized with special 4194 // instructions rather than being loaded. 4195 return !ISD::isBuildVectorAllZeros(N) && 4196 !ISD::isBuildVectorAllOnes(N); 4197} 4198 4199/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4200/// match movlp{s|d}. The lower half elements should come from lower half of 4201/// V1 (and in order), and the upper half elements should come from the upper 4202/// half of V2 (and in order). And since V1 will become the source of the 4203/// MOVLP, it must be either a vector load or a scalar load to vector. 4204static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4205 ArrayRef<int> Mask, EVT VT) { 4206 if (VT.getSizeInBits() != 128) 4207 return false; 4208 4209 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4210 return false; 4211 // Is V2 is a vector load, don't do this transformation. We will try to use 4212 // load folding shufps op. 4213 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4214 return false; 4215 4216 unsigned NumElems = VT.getVectorNumElements(); 4217 4218 if (NumElems != 2 && NumElems != 4) 4219 return false; 4220 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4221 if (!isUndefOrEqual(Mask[i], i)) 4222 return false; 4223 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4224 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4225 return false; 4226 return true; 4227} 4228 4229/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4230/// all the same. 4231static bool isSplatVector(SDNode *N) { 4232 if (N->getOpcode() != ISD::BUILD_VECTOR) 4233 return false; 4234 4235 SDValue SplatValue = N->getOperand(0); 4236 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4237 if (N->getOperand(i) != SplatValue) 4238 return false; 4239 return true; 4240} 4241 4242/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4243/// to an zero vector. 4244/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4245static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4246 SDValue V1 = N->getOperand(0); 4247 SDValue V2 = N->getOperand(1); 4248 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4249 for (unsigned i = 0; i != NumElems; ++i) { 4250 int Idx = N->getMaskElt(i); 4251 if (Idx >= (int)NumElems) { 4252 unsigned Opc = V2.getOpcode(); 4253 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4254 continue; 4255 if (Opc != ISD::BUILD_VECTOR || 4256 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4257 return false; 4258 } else if (Idx >= 0) { 4259 unsigned Opc = V1.getOpcode(); 4260 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4261 continue; 4262 if (Opc != ISD::BUILD_VECTOR || 4263 !X86::isZeroNode(V1.getOperand(Idx))) 4264 return false; 4265 } 4266 } 4267 return true; 4268} 4269 4270/// getZeroVector - Returns a vector of specified type with all zero elements. 4271/// 4272static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4273 SelectionDAG &DAG, DebugLoc dl) { 4274 assert(VT.isVector() && "Expected a vector type"); 4275 unsigned Size = VT.getSizeInBits(); 4276 4277 // Always build SSE zero vectors as <4 x i32> bitcasted 4278 // to their dest type. This ensures they get CSE'd. 4279 SDValue Vec; 4280 if (Size == 128) { // SSE 4281 if (Subtarget->hasSSE2()) { // SSE2 4282 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4283 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4284 } else { // SSE1 4285 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4286 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4287 } 4288 } else if (Size == 256) { // AVX 4289 if (Subtarget->hasAVX2()) { // AVX2 4290 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4291 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4292 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4293 } else { 4294 // 256-bit logic and arithmetic instructions in AVX are all 4295 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4296 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4297 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4298 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4299 } 4300 } else 4301 llvm_unreachable("Unexpected vector type"); 4302 4303 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4304} 4305 4306/// getOnesVector - Returns a vector of specified type with all bits set. 4307/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4308/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4309/// Then bitcast to their original type, ensuring they get CSE'd. 4310static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4311 DebugLoc dl) { 4312 assert(VT.isVector() && "Expected a vector type"); 4313 unsigned Size = VT.getSizeInBits(); 4314 4315 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4316 SDValue Vec; 4317 if (Size == 256) { 4318 if (HasAVX2) { // AVX2 4319 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4320 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4321 } else { // AVX 4322 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4323 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4324 } 4325 } else if (Size == 128) { 4326 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4327 } else 4328 llvm_unreachable("Unexpected vector type"); 4329 4330 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4331} 4332 4333/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4334/// that point to V2 points to its first element. 4335static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4336 for (unsigned i = 0; i != NumElems; ++i) { 4337 if (Mask[i] > (int)NumElems) { 4338 Mask[i] = NumElems; 4339 } 4340 } 4341} 4342 4343/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4344/// operation of specified width. 4345static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4346 SDValue V2) { 4347 unsigned NumElems = VT.getVectorNumElements(); 4348 SmallVector<int, 8> Mask; 4349 Mask.push_back(NumElems); 4350 for (unsigned i = 1; i != NumElems; ++i) 4351 Mask.push_back(i); 4352 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4353} 4354 4355/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4356static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4357 SDValue V2) { 4358 unsigned NumElems = VT.getVectorNumElements(); 4359 SmallVector<int, 8> Mask; 4360 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4361 Mask.push_back(i); 4362 Mask.push_back(i + NumElems); 4363 } 4364 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4365} 4366 4367/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4368static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4369 SDValue V2) { 4370 unsigned NumElems = VT.getVectorNumElements(); 4371 SmallVector<int, 8> Mask; 4372 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4373 Mask.push_back(i + Half); 4374 Mask.push_back(i + NumElems + Half); 4375 } 4376 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4377} 4378 4379// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4380// a generic shuffle instruction because the target has no such instructions. 4381// Generate shuffles which repeat i16 and i8 several times until they can be 4382// represented by v4f32 and then be manipulated by target suported shuffles. 4383static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4384 EVT VT = V.getValueType(); 4385 int NumElems = VT.getVectorNumElements(); 4386 DebugLoc dl = V.getDebugLoc(); 4387 4388 while (NumElems > 4) { 4389 if (EltNo < NumElems/2) { 4390 V = getUnpackl(DAG, dl, VT, V, V); 4391 } else { 4392 V = getUnpackh(DAG, dl, VT, V, V); 4393 EltNo -= NumElems/2; 4394 } 4395 NumElems >>= 1; 4396 } 4397 return V; 4398} 4399 4400/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4401static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4402 EVT VT = V.getValueType(); 4403 DebugLoc dl = V.getDebugLoc(); 4404 unsigned Size = VT.getSizeInBits(); 4405 4406 if (Size == 128) { 4407 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4408 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4409 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4410 &SplatMask[0]); 4411 } else if (Size == 256) { 4412 // To use VPERMILPS to splat scalars, the second half of indicies must 4413 // refer to the higher part, which is a duplication of the lower one, 4414 // because VPERMILPS can only handle in-lane permutations. 4415 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4416 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4417 4418 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4419 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4420 &SplatMask[0]); 4421 } else 4422 llvm_unreachable("Vector size not supported"); 4423 4424 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4425} 4426 4427/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4428static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4429 EVT SrcVT = SV->getValueType(0); 4430 SDValue V1 = SV->getOperand(0); 4431 DebugLoc dl = SV->getDebugLoc(); 4432 4433 int EltNo = SV->getSplatIndex(); 4434 int NumElems = SrcVT.getVectorNumElements(); 4435 unsigned Size = SrcVT.getSizeInBits(); 4436 4437 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4438 "Unknown how to promote splat for type"); 4439 4440 // Extract the 128-bit part containing the splat element and update 4441 // the splat element index when it refers to the higher register. 4442 if (Size == 256) { 4443 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4444 if (EltNo >= NumElems/2) 4445 EltNo -= NumElems/2; 4446 } 4447 4448 // All i16 and i8 vector types can't be used directly by a generic shuffle 4449 // instruction because the target has no such instruction. Generate shuffles 4450 // which repeat i16 and i8 several times until they fit in i32, and then can 4451 // be manipulated by target suported shuffles. 4452 EVT EltVT = SrcVT.getVectorElementType(); 4453 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4454 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4455 4456 // Recreate the 256-bit vector and place the same 128-bit vector 4457 // into the low and high part. This is necessary because we want 4458 // to use VPERM* to shuffle the vectors 4459 if (Size == 256) { 4460 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4461 } 4462 4463 return getLegalSplat(DAG, V1, EltNo); 4464} 4465 4466/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4467/// vector of zero or undef vector. This produces a shuffle where the low 4468/// element of V2 is swizzled into the zero/undef vector, landing at element 4469/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4470static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4471 bool IsZero, 4472 const X86Subtarget *Subtarget, 4473 SelectionDAG &DAG) { 4474 EVT VT = V2.getValueType(); 4475 SDValue V1 = IsZero 4476 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4477 unsigned NumElems = VT.getVectorNumElements(); 4478 SmallVector<int, 16> MaskVec; 4479 for (unsigned i = 0; i != NumElems; ++i) 4480 // If this is the insertion idx, put the low elt of V2 here. 4481 MaskVec.push_back(i == Idx ? NumElems : i); 4482 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4483} 4484 4485/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4486/// target specific opcode. Returns true if the Mask could be calculated. 4487/// Sets IsUnary to true if only uses one source. 4488static bool getTargetShuffleMask(SDNode *N, MVT VT, 4489 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4490 unsigned NumElems = VT.getVectorNumElements(); 4491 SDValue ImmN; 4492 4493 IsUnary = false; 4494 switch(N->getOpcode()) { 4495 case X86ISD::SHUFP: 4496 ImmN = N->getOperand(N->getNumOperands()-1); 4497 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4498 break; 4499 case X86ISD::UNPCKH: 4500 DecodeUNPCKHMask(VT, Mask); 4501 break; 4502 case X86ISD::UNPCKL: 4503 DecodeUNPCKLMask(VT, Mask); 4504 break; 4505 case X86ISD::MOVHLPS: 4506 DecodeMOVHLPSMask(NumElems, Mask); 4507 break; 4508 case X86ISD::MOVLHPS: 4509 DecodeMOVLHPSMask(NumElems, Mask); 4510 break; 4511 case X86ISD::PSHUFD: 4512 case X86ISD::VPERMILP: 4513 ImmN = N->getOperand(N->getNumOperands()-1); 4514 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4515 IsUnary = true; 4516 break; 4517 case X86ISD::PSHUFHW: 4518 ImmN = N->getOperand(N->getNumOperands()-1); 4519 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4520 IsUnary = true; 4521 break; 4522 case X86ISD::PSHUFLW: 4523 ImmN = N->getOperand(N->getNumOperands()-1); 4524 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4525 IsUnary = true; 4526 break; 4527 case X86ISD::VPERMI: 4528 ImmN = N->getOperand(N->getNumOperands()-1); 4529 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4530 IsUnary = true; 4531 break; 4532 case X86ISD::MOVSS: 4533 case X86ISD::MOVSD: { 4534 // The index 0 always comes from the first element of the second source, 4535 // this is why MOVSS and MOVSD are used in the first place. The other 4536 // elements come from the other positions of the first source vector 4537 Mask.push_back(NumElems); 4538 for (unsigned i = 1; i != NumElems; ++i) { 4539 Mask.push_back(i); 4540 } 4541 break; 4542 } 4543 case X86ISD::VPERM2X128: 4544 ImmN = N->getOperand(N->getNumOperands()-1); 4545 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4546 if (Mask.empty()) return false; 4547 break; 4548 case X86ISD::MOVDDUP: 4549 case X86ISD::MOVLHPD: 4550 case X86ISD::MOVLPD: 4551 case X86ISD::MOVLPS: 4552 case X86ISD::MOVSHDUP: 4553 case X86ISD::MOVSLDUP: 4554 case X86ISD::PALIGN: 4555 // Not yet implemented 4556 return false; 4557 default: llvm_unreachable("unknown target shuffle node"); 4558 } 4559 4560 return true; 4561} 4562 4563/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4564/// element of the result of the vector shuffle. 4565static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4566 unsigned Depth) { 4567 if (Depth == 6) 4568 return SDValue(); // Limit search depth. 4569 4570 SDValue V = SDValue(N, 0); 4571 EVT VT = V.getValueType(); 4572 unsigned Opcode = V.getOpcode(); 4573 4574 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4575 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4576 int Elt = SV->getMaskElt(Index); 4577 4578 if (Elt < 0) 4579 return DAG.getUNDEF(VT.getVectorElementType()); 4580 4581 unsigned NumElems = VT.getVectorNumElements(); 4582 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4583 : SV->getOperand(1); 4584 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4585 } 4586 4587 // Recurse into target specific vector shuffles to find scalars. 4588 if (isTargetShuffle(Opcode)) { 4589 MVT ShufVT = V.getValueType().getSimpleVT(); 4590 unsigned NumElems = ShufVT.getVectorNumElements(); 4591 SmallVector<int, 16> ShuffleMask; 4592 SDValue ImmN; 4593 bool IsUnary; 4594 4595 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary)) 4596 return SDValue(); 4597 4598 int Elt = ShuffleMask[Index]; 4599 if (Elt < 0) 4600 return DAG.getUNDEF(ShufVT.getVectorElementType()); 4601 4602 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4603 : N->getOperand(1); 4604 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4605 Depth+1); 4606 } 4607 4608 // Actual nodes that may contain scalar elements 4609 if (Opcode == ISD::BITCAST) { 4610 V = V.getOperand(0); 4611 EVT SrcVT = V.getValueType(); 4612 unsigned NumElems = VT.getVectorNumElements(); 4613 4614 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4615 return SDValue(); 4616 } 4617 4618 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4619 return (Index == 0) ? V.getOperand(0) 4620 : DAG.getUNDEF(VT.getVectorElementType()); 4621 4622 if (V.getOpcode() == ISD::BUILD_VECTOR) 4623 return V.getOperand(Index); 4624 4625 return SDValue(); 4626} 4627 4628/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4629/// shuffle operation which come from a consecutively from a zero. The 4630/// search can start in two different directions, from left or right. 4631static 4632unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4633 bool ZerosFromLeft, SelectionDAG &DAG) { 4634 unsigned i; 4635 for (i = 0; i != NumElems; ++i) { 4636 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4637 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4638 if (!(Elt.getNode() && 4639 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4640 break; 4641 } 4642 4643 return i; 4644} 4645 4646/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4647/// correspond consecutively to elements from one of the vector operands, 4648/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4649static 4650bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4651 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4652 unsigned NumElems, unsigned &OpNum) { 4653 bool SeenV1 = false; 4654 bool SeenV2 = false; 4655 4656 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4657 int Idx = SVOp->getMaskElt(i); 4658 // Ignore undef indicies 4659 if (Idx < 0) 4660 continue; 4661 4662 if (Idx < (int)NumElems) 4663 SeenV1 = true; 4664 else 4665 SeenV2 = true; 4666 4667 // Only accept consecutive elements from the same vector 4668 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4669 return false; 4670 } 4671 4672 OpNum = SeenV1 ? 0 : 1; 4673 return true; 4674} 4675 4676/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4677/// logical left shift of a vector. 4678static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4679 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4680 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4681 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4682 false /* check zeros from right */, DAG); 4683 unsigned OpSrc; 4684 4685 if (!NumZeros) 4686 return false; 4687 4688 // Considering the elements in the mask that are not consecutive zeros, 4689 // check if they consecutively come from only one of the source vectors. 4690 // 4691 // V1 = {X, A, B, C} 0 4692 // \ \ \ / 4693 // vector_shuffle V1, V2 <1, 2, 3, X> 4694 // 4695 if (!isShuffleMaskConsecutive(SVOp, 4696 0, // Mask Start Index 4697 NumElems-NumZeros, // Mask End Index(exclusive) 4698 NumZeros, // Where to start looking in the src vector 4699 NumElems, // Number of elements in vector 4700 OpSrc)) // Which source operand ? 4701 return false; 4702 4703 isLeft = false; 4704 ShAmt = NumZeros; 4705 ShVal = SVOp->getOperand(OpSrc); 4706 return true; 4707} 4708 4709/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4710/// logical left shift of a vector. 4711static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4712 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4713 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4714 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4715 true /* check zeros from left */, DAG); 4716 unsigned OpSrc; 4717 4718 if (!NumZeros) 4719 return false; 4720 4721 // Considering the elements in the mask that are not consecutive zeros, 4722 // check if they consecutively come from only one of the source vectors. 4723 // 4724 // 0 { A, B, X, X } = V2 4725 // / \ / / 4726 // vector_shuffle V1, V2 <X, X, 4, 5> 4727 // 4728 if (!isShuffleMaskConsecutive(SVOp, 4729 NumZeros, // Mask Start Index 4730 NumElems, // Mask End Index(exclusive) 4731 0, // Where to start looking in the src vector 4732 NumElems, // Number of elements in vector 4733 OpSrc)) // Which source operand ? 4734 return false; 4735 4736 isLeft = true; 4737 ShAmt = NumZeros; 4738 ShVal = SVOp->getOperand(OpSrc); 4739 return true; 4740} 4741 4742/// isVectorShift - Returns true if the shuffle can be implemented as a 4743/// logical left or right shift of a vector. 4744static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4745 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4746 // Although the logic below support any bitwidth size, there are no 4747 // shift instructions which handle more than 128-bit vectors. 4748 if (SVOp->getValueType(0).getSizeInBits() > 128) 4749 return false; 4750 4751 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4752 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4753 return true; 4754 4755 return false; 4756} 4757 4758/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4759/// 4760static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4761 unsigned NumNonZero, unsigned NumZero, 4762 SelectionDAG &DAG, 4763 const X86Subtarget* Subtarget, 4764 const TargetLowering &TLI) { 4765 if (NumNonZero > 8) 4766 return SDValue(); 4767 4768 DebugLoc dl = Op.getDebugLoc(); 4769 SDValue V(0, 0); 4770 bool First = true; 4771 for (unsigned i = 0; i < 16; ++i) { 4772 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4773 if (ThisIsNonZero && First) { 4774 if (NumZero) 4775 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4776 else 4777 V = DAG.getUNDEF(MVT::v8i16); 4778 First = false; 4779 } 4780 4781 if ((i & 1) != 0) { 4782 SDValue ThisElt(0, 0), LastElt(0, 0); 4783 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4784 if (LastIsNonZero) { 4785 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4786 MVT::i16, Op.getOperand(i-1)); 4787 } 4788 if (ThisIsNonZero) { 4789 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4790 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4791 ThisElt, DAG.getConstant(8, MVT::i8)); 4792 if (LastIsNonZero) 4793 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4794 } else 4795 ThisElt = LastElt; 4796 4797 if (ThisElt.getNode()) 4798 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4799 DAG.getIntPtrConstant(i/2)); 4800 } 4801 } 4802 4803 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4804} 4805 4806/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4807/// 4808static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4809 unsigned NumNonZero, unsigned NumZero, 4810 SelectionDAG &DAG, 4811 const X86Subtarget* Subtarget, 4812 const TargetLowering &TLI) { 4813 if (NumNonZero > 4) 4814 return SDValue(); 4815 4816 DebugLoc dl = Op.getDebugLoc(); 4817 SDValue V(0, 0); 4818 bool First = true; 4819 for (unsigned i = 0; i < 8; ++i) { 4820 bool isNonZero = (NonZeros & (1 << i)) != 0; 4821 if (isNonZero) { 4822 if (First) { 4823 if (NumZero) 4824 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4825 else 4826 V = DAG.getUNDEF(MVT::v8i16); 4827 First = false; 4828 } 4829 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4830 MVT::v8i16, V, Op.getOperand(i), 4831 DAG.getIntPtrConstant(i)); 4832 } 4833 } 4834 4835 return V; 4836} 4837 4838/// getVShift - Return a vector logical shift node. 4839/// 4840static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4841 unsigned NumBits, SelectionDAG &DAG, 4842 const TargetLowering &TLI, DebugLoc dl) { 4843 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4844 EVT ShVT = MVT::v2i64; 4845 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4846 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4847 return DAG.getNode(ISD::BITCAST, dl, VT, 4848 DAG.getNode(Opc, dl, ShVT, SrcOp, 4849 DAG.getConstant(NumBits, 4850 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4851} 4852 4853SDValue 4854X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4855 SelectionDAG &DAG) const { 4856 4857 // Check if the scalar load can be widened into a vector load. And if 4858 // the address is "base + cst" see if the cst can be "absorbed" into 4859 // the shuffle mask. 4860 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4861 SDValue Ptr = LD->getBasePtr(); 4862 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4863 return SDValue(); 4864 EVT PVT = LD->getValueType(0); 4865 if (PVT != MVT::i32 && PVT != MVT::f32) 4866 return SDValue(); 4867 4868 int FI = -1; 4869 int64_t Offset = 0; 4870 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4871 FI = FINode->getIndex(); 4872 Offset = 0; 4873 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4874 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4875 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4876 Offset = Ptr.getConstantOperandVal(1); 4877 Ptr = Ptr.getOperand(0); 4878 } else { 4879 return SDValue(); 4880 } 4881 4882 // FIXME: 256-bit vector instructions don't require a strict alignment, 4883 // improve this code to support it better. 4884 unsigned RequiredAlign = VT.getSizeInBits()/8; 4885 SDValue Chain = LD->getChain(); 4886 // Make sure the stack object alignment is at least 16 or 32. 4887 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4888 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4889 if (MFI->isFixedObjectIndex(FI)) { 4890 // Can't change the alignment. FIXME: It's possible to compute 4891 // the exact stack offset and reference FI + adjust offset instead. 4892 // If someone *really* cares about this. That's the way to implement it. 4893 return SDValue(); 4894 } else { 4895 MFI->setObjectAlignment(FI, RequiredAlign); 4896 } 4897 } 4898 4899 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4900 // Ptr + (Offset & ~15). 4901 if (Offset < 0) 4902 return SDValue(); 4903 if ((Offset % RequiredAlign) & 3) 4904 return SDValue(); 4905 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4906 if (StartOffset) 4907 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4908 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4909 4910 int EltNo = (Offset - StartOffset) >> 2; 4911 unsigned NumElems = VT.getVectorNumElements(); 4912 4913 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4914 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4915 LD->getPointerInfo().getWithOffset(StartOffset), 4916 false, false, false, 0); 4917 4918 SmallVector<int, 8> Mask; 4919 for (unsigned i = 0; i != NumElems; ++i) 4920 Mask.push_back(EltNo); 4921 4922 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4923 } 4924 4925 return SDValue(); 4926} 4927 4928/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4929/// vector of type 'VT', see if the elements can be replaced by a single large 4930/// load which has the same value as a build_vector whose operands are 'elts'. 4931/// 4932/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4933/// 4934/// FIXME: we'd also like to handle the case where the last elements are zero 4935/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4936/// There's even a handy isZeroNode for that purpose. 4937static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4938 DebugLoc &DL, SelectionDAG &DAG) { 4939 EVT EltVT = VT.getVectorElementType(); 4940 unsigned NumElems = Elts.size(); 4941 4942 LoadSDNode *LDBase = NULL; 4943 unsigned LastLoadedElt = -1U; 4944 4945 // For each element in the initializer, see if we've found a load or an undef. 4946 // If we don't find an initial load element, or later load elements are 4947 // non-consecutive, bail out. 4948 for (unsigned i = 0; i < NumElems; ++i) { 4949 SDValue Elt = Elts[i]; 4950 4951 if (!Elt.getNode() || 4952 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4953 return SDValue(); 4954 if (!LDBase) { 4955 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4956 return SDValue(); 4957 LDBase = cast<LoadSDNode>(Elt.getNode()); 4958 LastLoadedElt = i; 4959 continue; 4960 } 4961 if (Elt.getOpcode() == ISD::UNDEF) 4962 continue; 4963 4964 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4965 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4966 return SDValue(); 4967 LastLoadedElt = i; 4968 } 4969 4970 // If we have found an entire vector of loads and undefs, then return a large 4971 // load of the entire vector width starting at the base pointer. If we found 4972 // consecutive loads for the low half, generate a vzext_load node. 4973 if (LastLoadedElt == NumElems - 1) { 4974 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4975 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4976 LDBase->getPointerInfo(), 4977 LDBase->isVolatile(), LDBase->isNonTemporal(), 4978 LDBase->isInvariant(), 0); 4979 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4980 LDBase->getPointerInfo(), 4981 LDBase->isVolatile(), LDBase->isNonTemporal(), 4982 LDBase->isInvariant(), LDBase->getAlignment()); 4983 } 4984 if (NumElems == 4 && LastLoadedElt == 1 && 4985 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4986 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4987 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4988 SDValue ResNode = 4989 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4990 LDBase->getPointerInfo(), 4991 LDBase->getAlignment(), 4992 false/*isVolatile*/, true/*ReadMem*/, 4993 false/*WriteMem*/); 4994 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4995 } 4996 return SDValue(); 4997} 4998 4999/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 5000/// to generate a splat value for the following cases: 5001/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 5002/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 5003/// a scalar load, or a constant. 5004/// The VBROADCAST node is returned when a pattern is found, 5005/// or SDValue() otherwise. 5006SDValue 5007X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 5008 if (!Subtarget->hasAVX()) 5009 return SDValue(); 5010 5011 EVT VT = Op.getValueType(); 5012 DebugLoc dl = Op.getDebugLoc(); 5013 5014 assert((VT.is128BitVector() || VT.is256BitVector()) && 5015 "Unsupported vector type for broadcast."); 5016 5017 SDValue Ld; 5018 bool ConstSplatVal; 5019 5020 switch (Op.getOpcode()) { 5021 default: 5022 // Unknown pattern found. 5023 return SDValue(); 5024 5025 case ISD::BUILD_VECTOR: { 5026 // The BUILD_VECTOR node must be a splat. 5027 if (!isSplatVector(Op.getNode())) 5028 return SDValue(); 5029 5030 Ld = Op.getOperand(0); 5031 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5032 Ld.getOpcode() == ISD::ConstantFP); 5033 5034 // The suspected load node has several users. Make sure that all 5035 // of its users are from the BUILD_VECTOR node. 5036 // Constants may have multiple users. 5037 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 5038 return SDValue(); 5039 break; 5040 } 5041 5042 case ISD::VECTOR_SHUFFLE: { 5043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5044 5045 // Shuffles must have a splat mask where the first element is 5046 // broadcasted. 5047 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 5048 return SDValue(); 5049 5050 SDValue Sc = Op.getOperand(0); 5051 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR && 5052 Sc.getOpcode() != ISD::BUILD_VECTOR) { 5053 5054 if (!Subtarget->hasAVX2()) 5055 return SDValue(); 5056 5057 // Use the register form of the broadcast instruction available on AVX2. 5058 if (VT.is256BitVector()) 5059 Sc = Extract128BitVector(Sc, 0, DAG, dl); 5060 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc); 5061 } 5062 5063 Ld = Sc.getOperand(0); 5064 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 5065 Ld.getOpcode() == ISD::ConstantFP); 5066 5067 // The scalar_to_vector node and the suspected 5068 // load node must have exactly one user. 5069 // Constants may have multiple users. 5070 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 5071 return SDValue(); 5072 break; 5073 } 5074 } 5075 5076 bool Is256 = VT.getSizeInBits() == 256; 5077 5078 // Handle the broadcasting a single constant scalar from the constant pool 5079 // into a vector. On Sandybridge it is still better to load a constant vector 5080 // from the constant pool and not to broadcast it from a scalar. 5081 if (ConstSplatVal && Subtarget->hasAVX2()) { 5082 EVT CVT = Ld.getValueType(); 5083 assert(!CVT.isVector() && "Must not broadcast a vector type"); 5084 unsigned ScalarSize = CVT.getSizeInBits(); 5085 5086 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) { 5087 const Constant *C = 0; 5088 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 5089 C = CI->getConstantIntValue(); 5090 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 5091 C = CF->getConstantFPValue(); 5092 5093 assert(C && "Invalid constant type"); 5094 5095 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 5096 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 5097 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 5098 MachinePointerInfo::getConstantPool(), 5099 false, false, false, Alignment); 5100 5101 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5102 } 5103 } 5104 5105 bool IsLoad = ISD::isNormalLoad(Ld.getNode()); 5106 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5107 5108 // Handle AVX2 in-register broadcasts. 5109 if (!IsLoad && Subtarget->hasAVX2() && 5110 (ScalarSize == 32 || (Is256 && ScalarSize == 64))) 5111 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5112 5113 // The scalar source must be a normal load. 5114 if (!IsLoad) 5115 return SDValue(); 5116 5117 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) 5118 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5119 5120 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5121 // double since there is no vbroadcastsd xmm 5122 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5123 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64) 5124 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5125 } 5126 5127 // Unsupported broadcast. 5128 return SDValue(); 5129} 5130 5131SDValue 5132X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5133 DebugLoc dl = Op.getDebugLoc(); 5134 5135 EVT VT = Op.getValueType(); 5136 EVT ExtVT = VT.getVectorElementType(); 5137 unsigned NumElems = Op.getNumOperands(); 5138 5139 // Vectors containing all zeros can be matched by pxor and xorps later 5140 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5141 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5142 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5143 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5144 return Op; 5145 5146 return getZeroVector(VT, Subtarget, DAG, dl); 5147 } 5148 5149 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5150 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5151 // vpcmpeqd on 256-bit vectors. 5152 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5153 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5154 return Op; 5155 5156 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5157 } 5158 5159 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5160 if (Broadcast.getNode()) 5161 return Broadcast; 5162 5163 unsigned EVTBits = ExtVT.getSizeInBits(); 5164 5165 unsigned NumZero = 0; 5166 unsigned NumNonZero = 0; 5167 unsigned NonZeros = 0; 5168 bool IsAllConstants = true; 5169 SmallSet<SDValue, 8> Values; 5170 for (unsigned i = 0; i < NumElems; ++i) { 5171 SDValue Elt = Op.getOperand(i); 5172 if (Elt.getOpcode() == ISD::UNDEF) 5173 continue; 5174 Values.insert(Elt); 5175 if (Elt.getOpcode() != ISD::Constant && 5176 Elt.getOpcode() != ISD::ConstantFP) 5177 IsAllConstants = false; 5178 if (X86::isZeroNode(Elt)) 5179 NumZero++; 5180 else { 5181 NonZeros |= (1 << i); 5182 NumNonZero++; 5183 } 5184 } 5185 5186 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5187 if (NumNonZero == 0) 5188 return DAG.getUNDEF(VT); 5189 5190 // Special case for single non-zero, non-undef, element. 5191 if (NumNonZero == 1) { 5192 unsigned Idx = CountTrailingZeros_32(NonZeros); 5193 SDValue Item = Op.getOperand(Idx); 5194 5195 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5196 // the value are obviously zero, truncate the value to i32 and do the 5197 // insertion that way. Only do this if the value is non-constant or if the 5198 // value is a constant being inserted into element 0. It is cheaper to do 5199 // a constant pool load than it is to do a movd + shuffle. 5200 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5201 (!IsAllConstants || Idx == 0)) { 5202 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5203 // Handle SSE only. 5204 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5205 EVT VecVT = MVT::v4i32; 5206 unsigned VecElts = 4; 5207 5208 // Truncate the value (which may itself be a constant) to i32, and 5209 // convert it to a vector with movd (S2V+shuffle to zero extend). 5210 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5211 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5212 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5213 5214 // Now we have our 32-bit value zero extended in the low element of 5215 // a vector. If Idx != 0, swizzle it into place. 5216 if (Idx != 0) { 5217 SmallVector<int, 4> Mask; 5218 Mask.push_back(Idx); 5219 for (unsigned i = 1; i != VecElts; ++i) 5220 Mask.push_back(i); 5221 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5222 &Mask[0]); 5223 } 5224 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5225 } 5226 } 5227 5228 // If we have a constant or non-constant insertion into the low element of 5229 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5230 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5231 // depending on what the source datatype is. 5232 if (Idx == 0) { 5233 if (NumZero == 0) 5234 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5235 5236 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5237 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5238 if (VT.getSizeInBits() == 256) { 5239 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5240 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5241 Item, DAG.getIntPtrConstant(0)); 5242 } 5243 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5244 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5245 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5246 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5247 } 5248 5249 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5250 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5251 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5252 if (VT.getSizeInBits() == 256) { 5253 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5254 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5255 } else { 5256 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5257 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5258 } 5259 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5260 } 5261 } 5262 5263 // Is it a vector logical left shift? 5264 if (NumElems == 2 && Idx == 1 && 5265 X86::isZeroNode(Op.getOperand(0)) && 5266 !X86::isZeroNode(Op.getOperand(1))) { 5267 unsigned NumBits = VT.getSizeInBits(); 5268 return getVShift(true, VT, 5269 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5270 VT, Op.getOperand(1)), 5271 NumBits/2, DAG, *this, dl); 5272 } 5273 5274 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5275 return SDValue(); 5276 5277 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5278 // is a non-constant being inserted into an element other than the low one, 5279 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5280 // movd/movss) to move this into the low element, then shuffle it into 5281 // place. 5282 if (EVTBits == 32) { 5283 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5284 5285 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5286 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5287 SmallVector<int, 8> MaskVec; 5288 for (unsigned i = 0; i != NumElems; ++i) 5289 MaskVec.push_back(i == Idx ? 0 : 1); 5290 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5291 } 5292 } 5293 5294 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5295 if (Values.size() == 1) { 5296 if (EVTBits == 32) { 5297 // Instead of a shuffle like this: 5298 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5299 // Check if it's possible to issue this instead. 5300 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5301 unsigned Idx = CountTrailingZeros_32(NonZeros); 5302 SDValue Item = Op.getOperand(Idx); 5303 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5304 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5305 } 5306 return SDValue(); 5307 } 5308 5309 // A vector full of immediates; various special cases are already 5310 // handled, so this is best done with a single constant-pool load. 5311 if (IsAllConstants) 5312 return SDValue(); 5313 5314 // For AVX-length vectors, build the individual 128-bit pieces and use 5315 // shuffles to put them in place. 5316 if (VT.getSizeInBits() == 256) { 5317 SmallVector<SDValue, 32> V; 5318 for (unsigned i = 0; i != NumElems; ++i) 5319 V.push_back(Op.getOperand(i)); 5320 5321 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5322 5323 // Build both the lower and upper subvector. 5324 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5325 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5326 NumElems/2); 5327 5328 // Recreate the wider vector with the lower and upper part. 5329 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5330 } 5331 5332 // Let legalizer expand 2-wide build_vectors. 5333 if (EVTBits == 64) { 5334 if (NumNonZero == 1) { 5335 // One half is zero or undef. 5336 unsigned Idx = CountTrailingZeros_32(NonZeros); 5337 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5338 Op.getOperand(Idx)); 5339 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5340 } 5341 return SDValue(); 5342 } 5343 5344 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5345 if (EVTBits == 8 && NumElems == 16) { 5346 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5347 Subtarget, *this); 5348 if (V.getNode()) return V; 5349 } 5350 5351 if (EVTBits == 16 && NumElems == 8) { 5352 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5353 Subtarget, *this); 5354 if (V.getNode()) return V; 5355 } 5356 5357 // If element VT is == 32 bits, turn it into a number of shuffles. 5358 SmallVector<SDValue, 8> V(NumElems); 5359 if (NumElems == 4 && NumZero > 0) { 5360 for (unsigned i = 0; i < 4; ++i) { 5361 bool isZero = !(NonZeros & (1 << i)); 5362 if (isZero) 5363 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5364 else 5365 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5366 } 5367 5368 for (unsigned i = 0; i < 2; ++i) { 5369 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5370 default: break; 5371 case 0: 5372 V[i] = V[i*2]; // Must be a zero vector. 5373 break; 5374 case 1: 5375 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5376 break; 5377 case 2: 5378 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5379 break; 5380 case 3: 5381 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5382 break; 5383 } 5384 } 5385 5386 bool Reverse1 = (NonZeros & 0x3) == 2; 5387 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5388 int MaskVec[] = { 5389 Reverse1 ? 1 : 0, 5390 Reverse1 ? 0 : 1, 5391 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5392 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5393 }; 5394 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5395 } 5396 5397 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5398 // Check for a build vector of consecutive loads. 5399 for (unsigned i = 0; i < NumElems; ++i) 5400 V[i] = Op.getOperand(i); 5401 5402 // Check for elements which are consecutive loads. 5403 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5404 if (LD.getNode()) 5405 return LD; 5406 5407 // For SSE 4.1, use insertps to put the high elements into the low element. 5408 if (getSubtarget()->hasSSE41()) { 5409 SDValue Result; 5410 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5411 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5412 else 5413 Result = DAG.getUNDEF(VT); 5414 5415 for (unsigned i = 1; i < NumElems; ++i) { 5416 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5417 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5418 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5419 } 5420 return Result; 5421 } 5422 5423 // Otherwise, expand into a number of unpckl*, start by extending each of 5424 // our (non-undef) elements to the full vector width with the element in the 5425 // bottom slot of the vector (which generates no code for SSE). 5426 for (unsigned i = 0; i < NumElems; ++i) { 5427 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5428 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5429 else 5430 V[i] = DAG.getUNDEF(VT); 5431 } 5432 5433 // Next, we iteratively mix elements, e.g. for v4f32: 5434 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5435 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5436 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5437 unsigned EltStride = NumElems >> 1; 5438 while (EltStride != 0) { 5439 for (unsigned i = 0; i < EltStride; ++i) { 5440 // If V[i+EltStride] is undef and this is the first round of mixing, 5441 // then it is safe to just drop this shuffle: V[i] is already in the 5442 // right place, the one element (since it's the first round) being 5443 // inserted as undef can be dropped. This isn't safe for successive 5444 // rounds because they will permute elements within both vectors. 5445 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5446 EltStride == NumElems/2) 5447 continue; 5448 5449 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5450 } 5451 EltStride >>= 1; 5452 } 5453 return V[0]; 5454 } 5455 return SDValue(); 5456} 5457 5458// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5459// them in a MMX register. This is better than doing a stack convert. 5460static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5461 DebugLoc dl = Op.getDebugLoc(); 5462 EVT ResVT = Op.getValueType(); 5463 5464 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5465 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5466 int Mask[2]; 5467 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5468 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5469 InVec = Op.getOperand(1); 5470 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5471 unsigned NumElts = ResVT.getVectorNumElements(); 5472 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5473 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5474 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5475 } else { 5476 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5477 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5478 Mask[0] = 0; Mask[1] = 2; 5479 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5480 } 5481 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5482} 5483 5484// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5485// to create 256-bit vectors from two other 128-bit ones. 5486static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5487 DebugLoc dl = Op.getDebugLoc(); 5488 EVT ResVT = Op.getValueType(); 5489 5490 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5491 5492 SDValue V1 = Op.getOperand(0); 5493 SDValue V2 = Op.getOperand(1); 5494 unsigned NumElems = ResVT.getVectorNumElements(); 5495 5496 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5497} 5498 5499SDValue 5500X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5501 EVT ResVT = Op.getValueType(); 5502 5503 assert(Op.getNumOperands() == 2); 5504 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5505 "Unsupported CONCAT_VECTORS for value type"); 5506 5507 // We support concatenate two MMX registers and place them in a MMX register. 5508 // This is better than doing a stack convert. 5509 if (ResVT.is128BitVector()) 5510 return LowerMMXCONCAT_VECTORS(Op, DAG); 5511 5512 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5513 // from two other 128-bit ones. 5514 return LowerAVXCONCAT_VECTORS(Op, DAG); 5515} 5516 5517// Try to lower a shuffle node into a simple blend instruction. 5518static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5519 const X86Subtarget *Subtarget, 5520 SelectionDAG &DAG) { 5521 SDValue V1 = SVOp->getOperand(0); 5522 SDValue V2 = SVOp->getOperand(1); 5523 DebugLoc dl = SVOp->getDebugLoc(); 5524 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5525 unsigned NumElems = VT.getVectorNumElements(); 5526 5527 if (!Subtarget->hasSSE41()) 5528 return SDValue(); 5529 5530 unsigned ISDNo = 0; 5531 MVT OpTy; 5532 5533 switch (VT.SimpleTy) { 5534 default: return SDValue(); 5535 case MVT::v8i16: 5536 ISDNo = X86ISD::BLENDPW; 5537 OpTy = MVT::v8i16; 5538 break; 5539 case MVT::v4i32: 5540 case MVT::v4f32: 5541 ISDNo = X86ISD::BLENDPS; 5542 OpTy = MVT::v4f32; 5543 break; 5544 case MVT::v2i64: 5545 case MVT::v2f64: 5546 ISDNo = X86ISD::BLENDPD; 5547 OpTy = MVT::v2f64; 5548 break; 5549 case MVT::v8i32: 5550 case MVT::v8f32: 5551 if (!Subtarget->hasAVX()) 5552 return SDValue(); 5553 ISDNo = X86ISD::BLENDPS; 5554 OpTy = MVT::v8f32; 5555 break; 5556 case MVT::v4i64: 5557 case MVT::v4f64: 5558 if (!Subtarget->hasAVX()) 5559 return SDValue(); 5560 ISDNo = X86ISD::BLENDPD; 5561 OpTy = MVT::v4f64; 5562 break; 5563 } 5564 assert(ISDNo && "Invalid Op Number"); 5565 5566 unsigned MaskVals = 0; 5567 5568 for (unsigned i = 0; i != NumElems; ++i) { 5569 int EltIdx = SVOp->getMaskElt(i); 5570 if (EltIdx == (int)i || EltIdx < 0) 5571 MaskVals |= (1<<i); 5572 else if (EltIdx == (int)(i + NumElems)) 5573 continue; // Bit is set to zero; 5574 else 5575 return SDValue(); 5576 } 5577 5578 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); 5579 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2); 5580 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2, 5581 DAG.getConstant(MaskVals, MVT::i32)); 5582 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5583} 5584 5585// v8i16 shuffles - Prefer shuffles in the following order: 5586// 1. [all] pshuflw, pshufhw, optional move 5587// 2. [ssse3] 1 x pshufb 5588// 3. [ssse3] 2 x pshufb + 1 x por 5589// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5590SDValue 5591X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5592 SelectionDAG &DAG) const { 5593 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5594 SDValue V1 = SVOp->getOperand(0); 5595 SDValue V2 = SVOp->getOperand(1); 5596 DebugLoc dl = SVOp->getDebugLoc(); 5597 SmallVector<int, 8> MaskVals; 5598 5599 // Determine if more than 1 of the words in each of the low and high quadwords 5600 // of the result come from the same quadword of one of the two inputs. Undef 5601 // mask values count as coming from any quadword, for better codegen. 5602 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5603 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5604 std::bitset<4> InputQuads; 5605 for (unsigned i = 0; i < 8; ++i) { 5606 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5607 int EltIdx = SVOp->getMaskElt(i); 5608 MaskVals.push_back(EltIdx); 5609 if (EltIdx < 0) { 5610 ++Quad[0]; 5611 ++Quad[1]; 5612 ++Quad[2]; 5613 ++Quad[3]; 5614 continue; 5615 } 5616 ++Quad[EltIdx / 4]; 5617 InputQuads.set(EltIdx / 4); 5618 } 5619 5620 int BestLoQuad = -1; 5621 unsigned MaxQuad = 1; 5622 for (unsigned i = 0; i < 4; ++i) { 5623 if (LoQuad[i] > MaxQuad) { 5624 BestLoQuad = i; 5625 MaxQuad = LoQuad[i]; 5626 } 5627 } 5628 5629 int BestHiQuad = -1; 5630 MaxQuad = 1; 5631 for (unsigned i = 0; i < 4; ++i) { 5632 if (HiQuad[i] > MaxQuad) { 5633 BestHiQuad = i; 5634 MaxQuad = HiQuad[i]; 5635 } 5636 } 5637 5638 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5639 // of the two input vectors, shuffle them into one input vector so only a 5640 // single pshufb instruction is necessary. If There are more than 2 input 5641 // quads, disable the next transformation since it does not help SSSE3. 5642 bool V1Used = InputQuads[0] || InputQuads[1]; 5643 bool V2Used = InputQuads[2] || InputQuads[3]; 5644 if (Subtarget->hasSSSE3()) { 5645 if (InputQuads.count() == 2 && V1Used && V2Used) { 5646 BestLoQuad = InputQuads[0] ? 0 : 1; 5647 BestHiQuad = InputQuads[2] ? 2 : 3; 5648 } 5649 if (InputQuads.count() > 2) { 5650 BestLoQuad = -1; 5651 BestHiQuad = -1; 5652 } 5653 } 5654 5655 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5656 // the shuffle mask. If a quad is scored as -1, that means that it contains 5657 // words from all 4 input quadwords. 5658 SDValue NewV; 5659 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5660 int MaskV[] = { 5661 BestLoQuad < 0 ? 0 : BestLoQuad, 5662 BestHiQuad < 0 ? 1 : BestHiQuad 5663 }; 5664 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5665 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5666 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5667 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5668 5669 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5670 // source words for the shuffle, to aid later transformations. 5671 bool AllWordsInNewV = true; 5672 bool InOrder[2] = { true, true }; 5673 for (unsigned i = 0; i != 8; ++i) { 5674 int idx = MaskVals[i]; 5675 if (idx != (int)i) 5676 InOrder[i/4] = false; 5677 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5678 continue; 5679 AllWordsInNewV = false; 5680 break; 5681 } 5682 5683 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5684 if (AllWordsInNewV) { 5685 for (int i = 0; i != 8; ++i) { 5686 int idx = MaskVals[i]; 5687 if (idx < 0) 5688 continue; 5689 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5690 if ((idx != i) && idx < 4) 5691 pshufhw = false; 5692 if ((idx != i) && idx > 3) 5693 pshuflw = false; 5694 } 5695 V1 = NewV; 5696 V2Used = false; 5697 BestLoQuad = 0; 5698 BestHiQuad = 1; 5699 } 5700 5701 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5702 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5703 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5704 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5705 unsigned TargetMask = 0; 5706 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5707 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5708 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5709 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5710 getShufflePSHUFLWImmediate(SVOp); 5711 V1 = NewV.getOperand(0); 5712 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5713 } 5714 } 5715 5716 // If we have SSSE3, and all words of the result are from 1 input vector, 5717 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5718 // is present, fall back to case 4. 5719 if (Subtarget->hasSSSE3()) { 5720 SmallVector<SDValue,16> pshufbMask; 5721 5722 // If we have elements from both input vectors, set the high bit of the 5723 // shuffle mask element to zero out elements that come from V2 in the V1 5724 // mask, and elements that come from V1 in the V2 mask, so that the two 5725 // results can be OR'd together. 5726 bool TwoInputs = V1Used && V2Used; 5727 for (unsigned i = 0; i != 8; ++i) { 5728 int EltIdx = MaskVals[i] * 2; 5729 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx; 5730 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1; 5731 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5732 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5733 } 5734 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5735 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5736 DAG.getNode(ISD::BUILD_VECTOR, dl, 5737 MVT::v16i8, &pshufbMask[0], 16)); 5738 if (!TwoInputs) 5739 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5740 5741 // Calculate the shuffle mask for the second input, shuffle it, and 5742 // OR it with the first shuffled input. 5743 pshufbMask.clear(); 5744 for (unsigned i = 0; i != 8; ++i) { 5745 int EltIdx = MaskVals[i] * 2; 5746 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16; 5747 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15; 5748 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8)); 5749 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8)); 5750 } 5751 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5752 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5753 DAG.getNode(ISD::BUILD_VECTOR, dl, 5754 MVT::v16i8, &pshufbMask[0], 16)); 5755 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5756 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5757 } 5758 5759 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5760 // and update MaskVals with new element order. 5761 std::bitset<8> InOrder; 5762 if (BestLoQuad >= 0) { 5763 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5764 for (int i = 0; i != 4; ++i) { 5765 int idx = MaskVals[i]; 5766 if (idx < 0) { 5767 InOrder.set(i); 5768 } else if ((idx / 4) == BestLoQuad) { 5769 MaskV[i] = idx & 3; 5770 InOrder.set(i); 5771 } 5772 } 5773 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5774 &MaskV[0]); 5775 5776 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5777 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5778 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5779 NewV.getOperand(0), 5780 getShufflePSHUFLWImmediate(SVOp), DAG); 5781 } 5782 } 5783 5784 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5785 // and update MaskVals with the new element order. 5786 if (BestHiQuad >= 0) { 5787 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5788 for (unsigned i = 4; i != 8; ++i) { 5789 int idx = MaskVals[i]; 5790 if (idx < 0) { 5791 InOrder.set(i); 5792 } else if ((idx / 4) == BestHiQuad) { 5793 MaskV[i] = (idx & 3) + 4; 5794 InOrder.set(i); 5795 } 5796 } 5797 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5798 &MaskV[0]); 5799 5800 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5801 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5802 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5803 NewV.getOperand(0), 5804 getShufflePSHUFHWImmediate(SVOp), DAG); 5805 } 5806 } 5807 5808 // In case BestHi & BestLo were both -1, which means each quadword has a word 5809 // from each of the four input quadwords, calculate the InOrder bitvector now 5810 // before falling through to the insert/extract cleanup. 5811 if (BestLoQuad == -1 && BestHiQuad == -1) { 5812 NewV = V1; 5813 for (int i = 0; i != 8; ++i) 5814 if (MaskVals[i] < 0 || MaskVals[i] == i) 5815 InOrder.set(i); 5816 } 5817 5818 // The other elements are put in the right place using pextrw and pinsrw. 5819 for (unsigned i = 0; i != 8; ++i) { 5820 if (InOrder[i]) 5821 continue; 5822 int EltIdx = MaskVals[i]; 5823 if (EltIdx < 0) 5824 continue; 5825 SDValue ExtOp = (EltIdx < 8) ? 5826 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5827 DAG.getIntPtrConstant(EltIdx)) : 5828 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5829 DAG.getIntPtrConstant(EltIdx - 8)); 5830 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5831 DAG.getIntPtrConstant(i)); 5832 } 5833 return NewV; 5834} 5835 5836// v16i8 shuffles - Prefer shuffles in the following order: 5837// 1. [ssse3] 1 x pshufb 5838// 2. [ssse3] 2 x pshufb + 1 x por 5839// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5840static 5841SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5842 SelectionDAG &DAG, 5843 const X86TargetLowering &TLI) { 5844 SDValue V1 = SVOp->getOperand(0); 5845 SDValue V2 = SVOp->getOperand(1); 5846 DebugLoc dl = SVOp->getDebugLoc(); 5847 ArrayRef<int> MaskVals = SVOp->getMask(); 5848 5849 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 5850 5851 // If we have SSSE3, case 1 is generated when all result bytes come from 5852 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5853 // present, fall back to case 3. 5854 5855 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5856 if (TLI.getSubtarget()->hasSSSE3()) { 5857 SmallVector<SDValue,16> pshufbMask; 5858 5859 // If all result elements are from one input vector, then only translate 5860 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5861 // 5862 // Otherwise, we have elements from both input vectors, and must zero out 5863 // elements that come from V2 in the first mask, and V1 in the second mask 5864 // so that we can OR them together. 5865 for (unsigned i = 0; i != 16; ++i) { 5866 int EltIdx = MaskVals[i]; 5867 if (EltIdx < 0 || EltIdx >= 16) 5868 EltIdx = 0x80; 5869 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5870 } 5871 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5872 DAG.getNode(ISD::BUILD_VECTOR, dl, 5873 MVT::v16i8, &pshufbMask[0], 16)); 5874 if (V2IsUndef) 5875 return V1; 5876 5877 // Calculate the shuffle mask for the second input, shuffle it, and 5878 // OR it with the first shuffled input. 5879 pshufbMask.clear(); 5880 for (unsigned i = 0; i != 16; ++i) { 5881 int EltIdx = MaskVals[i]; 5882 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16; 5883 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5884 } 5885 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5886 DAG.getNode(ISD::BUILD_VECTOR, dl, 5887 MVT::v16i8, &pshufbMask[0], 16)); 5888 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5889 } 5890 5891 // No SSSE3 - Calculate in place words and then fix all out of place words 5892 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5893 // the 16 different words that comprise the two doublequadword input vectors. 5894 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5895 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5896 SDValue NewV = V1; 5897 for (int i = 0; i != 8; ++i) { 5898 int Elt0 = MaskVals[i*2]; 5899 int Elt1 = MaskVals[i*2+1]; 5900 5901 // This word of the result is all undef, skip it. 5902 if (Elt0 < 0 && Elt1 < 0) 5903 continue; 5904 5905 // This word of the result is already in the correct place, skip it. 5906 if ((Elt0 == i*2) && (Elt1 == i*2+1)) 5907 continue; 5908 5909 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5910 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5911 SDValue InsElt; 5912 5913 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5914 // using a single extract together, load it and store it. 5915 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5916 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5917 DAG.getIntPtrConstant(Elt1 / 2)); 5918 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5919 DAG.getIntPtrConstant(i)); 5920 continue; 5921 } 5922 5923 // If Elt1 is defined, extract it from the appropriate source. If the 5924 // source byte is not also odd, shift the extracted word left 8 bits 5925 // otherwise clear the bottom 8 bits if we need to do an or. 5926 if (Elt1 >= 0) { 5927 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5928 DAG.getIntPtrConstant(Elt1 / 2)); 5929 if ((Elt1 & 1) == 0) 5930 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5931 DAG.getConstant(8, 5932 TLI.getShiftAmountTy(InsElt.getValueType()))); 5933 else if (Elt0 >= 0) 5934 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5935 DAG.getConstant(0xFF00, MVT::i16)); 5936 } 5937 // If Elt0 is defined, extract it from the appropriate source. If the 5938 // source byte is not also even, shift the extracted word right 8 bits. If 5939 // Elt1 was also defined, OR the extracted values together before 5940 // inserting them in the result. 5941 if (Elt0 >= 0) { 5942 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5943 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5944 if ((Elt0 & 1) != 0) 5945 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5946 DAG.getConstant(8, 5947 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5948 else if (Elt1 >= 0) 5949 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5950 DAG.getConstant(0x00FF, MVT::i16)); 5951 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5952 : InsElt0; 5953 } 5954 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5955 DAG.getIntPtrConstant(i)); 5956 } 5957 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5958} 5959 5960/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5961/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5962/// done when every pair / quad of shuffle mask elements point to elements in 5963/// the right sequence. e.g. 5964/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5965static 5966SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5967 SelectionDAG &DAG, DebugLoc dl) { 5968 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5969 unsigned NumElems = VT.getVectorNumElements(); 5970 MVT NewVT; 5971 unsigned Scale; 5972 switch (VT.SimpleTy) { 5973 default: llvm_unreachable("Unexpected!"); 5974 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 5975 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 5976 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 5977 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 5978 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 5979 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 5980 } 5981 5982 SmallVector<int, 8> MaskVec; 5983 for (unsigned i = 0; i != NumElems; i += Scale) { 5984 int StartIdx = -1; 5985 for (unsigned j = 0; j != Scale; ++j) { 5986 int EltIdx = SVOp->getMaskElt(i+j); 5987 if (EltIdx < 0) 5988 continue; 5989 if (StartIdx < 0) 5990 StartIdx = (EltIdx / Scale); 5991 if (EltIdx != (int)(StartIdx*Scale + j)) 5992 return SDValue(); 5993 } 5994 MaskVec.push_back(StartIdx); 5995 } 5996 5997 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 5998 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 5999 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 6000} 6001 6002/// getVZextMovL - Return a zero-extending vector move low node. 6003/// 6004static SDValue getVZextMovL(EVT VT, EVT OpVT, 6005 SDValue SrcOp, SelectionDAG &DAG, 6006 const X86Subtarget *Subtarget, DebugLoc dl) { 6007 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 6008 LoadSDNode *LD = NULL; 6009 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 6010 LD = dyn_cast<LoadSDNode>(SrcOp); 6011 if (!LD) { 6012 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 6013 // instead. 6014 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 6015 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 6016 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 6017 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 6018 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 6019 // PR2108 6020 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 6021 return DAG.getNode(ISD::BITCAST, dl, VT, 6022 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6023 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 6024 OpVT, 6025 SrcOp.getOperand(0) 6026 .getOperand(0)))); 6027 } 6028 } 6029 } 6030 6031 return DAG.getNode(ISD::BITCAST, dl, VT, 6032 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 6033 DAG.getNode(ISD::BITCAST, dl, 6034 OpVT, SrcOp))); 6035} 6036 6037/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6038/// which could not be matched by any known target speficic shuffle 6039static SDValue 6040LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6041 6042 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG); 6043 if (NewOp.getNode()) 6044 return NewOp; 6045 6046 EVT VT = SVOp->getValueType(0); 6047 6048 unsigned NumElems = VT.getVectorNumElements(); 6049 unsigned NumLaneElems = NumElems / 2; 6050 6051 DebugLoc dl = SVOp->getDebugLoc(); 6052 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 6053 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 6054 SDValue Output[2]; 6055 6056 SmallVector<int, 16> Mask; 6057 for (unsigned l = 0; l < 2; ++l) { 6058 // Build a shuffle mask for the output, discovering on the fly which 6059 // input vectors to use as shuffle operands (recorded in InputUsed). 6060 // If building a suitable shuffle vector proves too hard, then bail 6061 // out with UseBuildVector set. 6062 bool UseBuildVector = false; 6063 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 6064 unsigned LaneStart = l * NumLaneElems; 6065 for (unsigned i = 0; i != NumLaneElems; ++i) { 6066 // The mask element. This indexes into the input. 6067 int Idx = SVOp->getMaskElt(i+LaneStart); 6068 if (Idx < 0) { 6069 // the mask element does not index into any input vector. 6070 Mask.push_back(-1); 6071 continue; 6072 } 6073 6074 // The input vector this mask element indexes into. 6075 int Input = Idx / NumLaneElems; 6076 6077 // Turn the index into an offset from the start of the input vector. 6078 Idx -= Input * NumLaneElems; 6079 6080 // Find or create a shuffle vector operand to hold this input. 6081 unsigned OpNo; 6082 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6083 if (InputUsed[OpNo] == Input) 6084 // This input vector is already an operand. 6085 break; 6086 if (InputUsed[OpNo] < 0) { 6087 // Create a new operand for this input vector. 6088 InputUsed[OpNo] = Input; 6089 break; 6090 } 6091 } 6092 6093 if (OpNo >= array_lengthof(InputUsed)) { 6094 // More than two input vectors used! Give up on trying to create a 6095 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 6096 UseBuildVector = true; 6097 break; 6098 } 6099 6100 // Add the mask index for the new shuffle vector. 6101 Mask.push_back(Idx + OpNo * NumLaneElems); 6102 } 6103 6104 if (UseBuildVector) { 6105 SmallVector<SDValue, 16> SVOps; 6106 for (unsigned i = 0; i != NumLaneElems; ++i) { 6107 // The mask element. This indexes into the input. 6108 int Idx = SVOp->getMaskElt(i+LaneStart); 6109 if (Idx < 0) { 6110 SVOps.push_back(DAG.getUNDEF(EltVT)); 6111 continue; 6112 } 6113 6114 // The input vector this mask element indexes into. 6115 int Input = Idx / NumElems; 6116 6117 // Turn the index into an offset from the start of the input vector. 6118 Idx -= Input * NumElems; 6119 6120 // Extract the vector element by hand. 6121 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 6122 SVOp->getOperand(Input), 6123 DAG.getIntPtrConstant(Idx))); 6124 } 6125 6126 // Construct the output using a BUILD_VECTOR. 6127 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0], 6128 SVOps.size()); 6129 } else if (InputUsed[0] < 0) { 6130 // No input vectors were used! The result is undefined. 6131 Output[l] = DAG.getUNDEF(NVT); 6132 } else { 6133 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6134 (InputUsed[0] % 2) * NumLaneElems, 6135 DAG, dl); 6136 // If only one input was used, use an undefined vector for the other. 6137 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6138 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6139 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6140 // At least one input vector was used. Create a new shuffle vector. 6141 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6142 } 6143 6144 Mask.clear(); 6145 } 6146 6147 // Concatenate the result back 6148 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]); 6149} 6150 6151/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6152/// 4 elements, and match them with several different shuffle types. 6153static SDValue 6154LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6155 SDValue V1 = SVOp->getOperand(0); 6156 SDValue V2 = SVOp->getOperand(1); 6157 DebugLoc dl = SVOp->getDebugLoc(); 6158 EVT VT = SVOp->getValueType(0); 6159 6160 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6161 6162 std::pair<int, int> Locs[4]; 6163 int Mask1[] = { -1, -1, -1, -1 }; 6164 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6165 6166 unsigned NumHi = 0; 6167 unsigned NumLo = 0; 6168 for (unsigned i = 0; i != 4; ++i) { 6169 int Idx = PermMask[i]; 6170 if (Idx < 0) { 6171 Locs[i] = std::make_pair(-1, -1); 6172 } else { 6173 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6174 if (Idx < 4) { 6175 Locs[i] = std::make_pair(0, NumLo); 6176 Mask1[NumLo] = Idx; 6177 NumLo++; 6178 } else { 6179 Locs[i] = std::make_pair(1, NumHi); 6180 if (2+NumHi < 4) 6181 Mask1[2+NumHi] = Idx; 6182 NumHi++; 6183 } 6184 } 6185 } 6186 6187 if (NumLo <= 2 && NumHi <= 2) { 6188 // If no more than two elements come from either vector. This can be 6189 // implemented with two shuffles. First shuffle gather the elements. 6190 // The second shuffle, which takes the first shuffle as both of its 6191 // vector operands, put the elements into the right order. 6192 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6193 6194 int Mask2[] = { -1, -1, -1, -1 }; 6195 6196 for (unsigned i = 0; i != 4; ++i) 6197 if (Locs[i].first != -1) { 6198 unsigned Idx = (i < 2) ? 0 : 4; 6199 Idx += Locs[i].first * 2 + Locs[i].second; 6200 Mask2[i] = Idx; 6201 } 6202 6203 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6204 } 6205 6206 if (NumLo == 3 || NumHi == 3) { 6207 // Otherwise, we must have three elements from one vector, call it X, and 6208 // one element from the other, call it Y. First, use a shufps to build an 6209 // intermediate vector with the one element from Y and the element from X 6210 // that will be in the same half in the final destination (the indexes don't 6211 // matter). Then, use a shufps to build the final vector, taking the half 6212 // containing the element from Y from the intermediate, and the other half 6213 // from X. 6214 if (NumHi == 3) { 6215 // Normalize it so the 3 elements come from V1. 6216 CommuteVectorShuffleMask(PermMask, 4); 6217 std::swap(V1, V2); 6218 } 6219 6220 // Find the element from V2. 6221 unsigned HiIndex; 6222 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6223 int Val = PermMask[HiIndex]; 6224 if (Val < 0) 6225 continue; 6226 if (Val >= 4) 6227 break; 6228 } 6229 6230 Mask1[0] = PermMask[HiIndex]; 6231 Mask1[1] = -1; 6232 Mask1[2] = PermMask[HiIndex^1]; 6233 Mask1[3] = -1; 6234 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6235 6236 if (HiIndex >= 2) { 6237 Mask1[0] = PermMask[0]; 6238 Mask1[1] = PermMask[1]; 6239 Mask1[2] = HiIndex & 1 ? 6 : 4; 6240 Mask1[3] = HiIndex & 1 ? 4 : 6; 6241 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6242 } 6243 6244 Mask1[0] = HiIndex & 1 ? 2 : 0; 6245 Mask1[1] = HiIndex & 1 ? 0 : 2; 6246 Mask1[2] = PermMask[2]; 6247 Mask1[3] = PermMask[3]; 6248 if (Mask1[2] >= 0) 6249 Mask1[2] += 4; 6250 if (Mask1[3] >= 0) 6251 Mask1[3] += 4; 6252 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6253 } 6254 6255 // Break it into (shuffle shuffle_hi, shuffle_lo). 6256 int LoMask[] = { -1, -1, -1, -1 }; 6257 int HiMask[] = { -1, -1, -1, -1 }; 6258 6259 int *MaskPtr = LoMask; 6260 unsigned MaskIdx = 0; 6261 unsigned LoIdx = 0; 6262 unsigned HiIdx = 2; 6263 for (unsigned i = 0; i != 4; ++i) { 6264 if (i == 2) { 6265 MaskPtr = HiMask; 6266 MaskIdx = 1; 6267 LoIdx = 0; 6268 HiIdx = 2; 6269 } 6270 int Idx = PermMask[i]; 6271 if (Idx < 0) { 6272 Locs[i] = std::make_pair(-1, -1); 6273 } else if (Idx < 4) { 6274 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6275 MaskPtr[LoIdx] = Idx; 6276 LoIdx++; 6277 } else { 6278 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6279 MaskPtr[HiIdx] = Idx; 6280 HiIdx++; 6281 } 6282 } 6283 6284 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6285 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6286 int MaskOps[] = { -1, -1, -1, -1 }; 6287 for (unsigned i = 0; i != 4; ++i) 6288 if (Locs[i].first != -1) 6289 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6290 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6291} 6292 6293static bool MayFoldVectorLoad(SDValue V) { 6294 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6295 V = V.getOperand(0); 6296 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6297 V = V.getOperand(0); 6298 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6299 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6300 // BUILD_VECTOR (load), undef 6301 V = V.getOperand(0); 6302 if (MayFoldLoad(V)) 6303 return true; 6304 return false; 6305} 6306 6307// FIXME: the version above should always be used. Since there's 6308// a bug where several vector shuffles can't be folded because the 6309// DAG is not updated during lowering and a node claims to have two 6310// uses while it only has one, use this version, and let isel match 6311// another instruction if the load really happens to have more than 6312// one use. Remove this version after this bug get fixed. 6313// rdar://8434668, PR8156 6314static bool RelaxedMayFoldVectorLoad(SDValue V) { 6315 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6316 V = V.getOperand(0); 6317 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6318 V = V.getOperand(0); 6319 if (ISD::isNormalLoad(V.getNode())) 6320 return true; 6321 return false; 6322} 6323 6324static 6325SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6326 EVT VT = Op.getValueType(); 6327 6328 // Canonizalize to v2f64. 6329 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6330 return DAG.getNode(ISD::BITCAST, dl, VT, 6331 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6332 V1, DAG)); 6333} 6334 6335static 6336SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6337 bool HasSSE2) { 6338 SDValue V1 = Op.getOperand(0); 6339 SDValue V2 = Op.getOperand(1); 6340 EVT VT = Op.getValueType(); 6341 6342 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6343 6344 if (HasSSE2 && VT == MVT::v2f64) 6345 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6346 6347 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6348 return DAG.getNode(ISD::BITCAST, dl, VT, 6349 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6350 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6351 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6352} 6353 6354static 6355SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6356 SDValue V1 = Op.getOperand(0); 6357 SDValue V2 = Op.getOperand(1); 6358 EVT VT = Op.getValueType(); 6359 6360 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6361 "unsupported shuffle type"); 6362 6363 if (V2.getOpcode() == ISD::UNDEF) 6364 V2 = V1; 6365 6366 // v4i32 or v4f32 6367 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6368} 6369 6370static 6371SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6372 SDValue V1 = Op.getOperand(0); 6373 SDValue V2 = Op.getOperand(1); 6374 EVT VT = Op.getValueType(); 6375 unsigned NumElems = VT.getVectorNumElements(); 6376 6377 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6378 // operand of these instructions is only memory, so check if there's a 6379 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6380 // same masks. 6381 bool CanFoldLoad = false; 6382 6383 // Trivial case, when V2 comes from a load. 6384 if (MayFoldVectorLoad(V2)) 6385 CanFoldLoad = true; 6386 6387 // When V1 is a load, it can be folded later into a store in isel, example: 6388 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6389 // turns into: 6390 // (MOVLPSmr addr:$src1, VR128:$src2) 6391 // So, recognize this potential and also use MOVLPS or MOVLPD 6392 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6393 CanFoldLoad = true; 6394 6395 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6396 if (CanFoldLoad) { 6397 if (HasSSE2 && NumElems == 2) 6398 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6399 6400 if (NumElems == 4) 6401 // If we don't care about the second element, proceed to use movss. 6402 if (SVOp->getMaskElt(1) != -1) 6403 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6404 } 6405 6406 // movl and movlp will both match v2i64, but v2i64 is never matched by 6407 // movl earlier because we make it strict to avoid messing with the movlp load 6408 // folding logic (see the code above getMOVLP call). Match it here then, 6409 // this is horrible, but will stay like this until we move all shuffle 6410 // matching to x86 specific nodes. Note that for the 1st condition all 6411 // types are matched with movsd. 6412 if (HasSSE2) { 6413 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6414 // as to remove this logic from here, as much as possible 6415 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6416 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6417 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6418 } 6419 6420 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6421 6422 // Invert the operand order and use SHUFPS to match it. 6423 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6424 getShuffleSHUFImmediate(SVOp), DAG); 6425} 6426 6427SDValue 6428X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6430 EVT VT = Op.getValueType(); 6431 DebugLoc dl = Op.getDebugLoc(); 6432 SDValue V1 = Op.getOperand(0); 6433 SDValue V2 = Op.getOperand(1); 6434 6435 if (isZeroShuffle(SVOp)) 6436 return getZeroVector(VT, Subtarget, DAG, dl); 6437 6438 // Handle splat operations 6439 if (SVOp->isSplat()) { 6440 unsigned NumElem = VT.getVectorNumElements(); 6441 int Size = VT.getSizeInBits(); 6442 6443 // Use vbroadcast whenever the splat comes from a foldable load 6444 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6445 if (Broadcast.getNode()) 6446 return Broadcast; 6447 6448 // Handle splats by matching through known shuffle masks 6449 if ((Size == 128 && NumElem <= 4) || 6450 (Size == 256 && NumElem < 8)) 6451 return SDValue(); 6452 6453 // All remaning splats are promoted to target supported vector shuffles. 6454 return PromoteSplat(SVOp, DAG); 6455 } 6456 6457 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6458 // do it! 6459 if (VT == MVT::v8i16 || VT == MVT::v16i8 || 6460 VT == MVT::v16i16 || VT == MVT::v32i8) { 6461 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6462 if (NewOp.getNode()) 6463 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6464 } else if ((VT == MVT::v4i32 || 6465 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6466 // FIXME: Figure out a cleaner way to do this. 6467 // Try to make use of movq to zero out the top part. 6468 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6469 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6470 if (NewOp.getNode()) { 6471 EVT NewVT = NewOp.getValueType(); 6472 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6473 NewVT, true, false)) 6474 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6475 DAG, Subtarget, dl); 6476 } 6477 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6478 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6479 if (NewOp.getNode()) { 6480 EVT NewVT = NewOp.getValueType(); 6481 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6482 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6483 DAG, Subtarget, dl); 6484 } 6485 } 6486 } 6487 return SDValue(); 6488} 6489 6490SDValue 6491X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6493 SDValue V1 = Op.getOperand(0); 6494 SDValue V2 = Op.getOperand(1); 6495 EVT VT = Op.getValueType(); 6496 DebugLoc dl = Op.getDebugLoc(); 6497 unsigned NumElems = VT.getVectorNumElements(); 6498 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6499 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6500 bool V1IsSplat = false; 6501 bool V2IsSplat = false; 6502 bool HasSSE2 = Subtarget->hasSSE2(); 6503 bool HasAVX = Subtarget->hasAVX(); 6504 bool HasAVX2 = Subtarget->hasAVX2(); 6505 MachineFunction &MF = DAG.getMachineFunction(); 6506 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6507 6508 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6509 6510 if (V1IsUndef && V2IsUndef) 6511 return DAG.getUNDEF(VT); 6512 6513 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6514 6515 // Vector shuffle lowering takes 3 steps: 6516 // 6517 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6518 // narrowing and commutation of operands should be handled. 6519 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6520 // shuffle nodes. 6521 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6522 // so the shuffle can be broken into other shuffles and the legalizer can 6523 // try the lowering again. 6524 // 6525 // The general idea is that no vector_shuffle operation should be left to 6526 // be matched during isel, all of them must be converted to a target specific 6527 // node here. 6528 6529 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6530 // narrowing and commutation of operands should be handled. The actual code 6531 // doesn't include all of those, work in progress... 6532 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6533 if (NewOp.getNode()) 6534 return NewOp; 6535 6536 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6537 6538 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6539 // unpckh_undef). Only use pshufd if speed is more important than size. 6540 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6541 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6542 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6543 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6544 6545 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6546 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6547 return getMOVDDup(Op, dl, V1, DAG); 6548 6549 if (isMOVHLPS_v_undef_Mask(M, VT)) 6550 return getMOVHighToLow(Op, dl, DAG); 6551 6552 // Use to match splats 6553 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6554 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6555 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6556 6557 if (isPSHUFDMask(M, VT)) { 6558 // The actual implementation will match the mask in the if above and then 6559 // during isel it can match several different instructions, not only pshufd 6560 // as its name says, sad but true, emulate the behavior for now... 6561 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6562 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6563 6564 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6565 6566 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6567 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6568 6569 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6570 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6571 6572 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6573 TargetMask, DAG); 6574 } 6575 6576 // Check if this can be converted into a logical shift. 6577 bool isLeft = false; 6578 unsigned ShAmt = 0; 6579 SDValue ShVal; 6580 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6581 if (isShift && ShVal.hasOneUse()) { 6582 // If the shifted value has multiple uses, it may be cheaper to use 6583 // v_set0 + movlhps or movhlps, etc. 6584 EVT EltVT = VT.getVectorElementType(); 6585 ShAmt *= EltVT.getSizeInBits(); 6586 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6587 } 6588 6589 if (isMOVLMask(M, VT)) { 6590 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6591 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6592 if (!isMOVLPMask(M, VT)) { 6593 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6594 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6595 6596 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6597 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6598 } 6599 } 6600 6601 // FIXME: fold these into legal mask. 6602 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6603 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6604 6605 if (isMOVHLPSMask(M, VT)) 6606 return getMOVHighToLow(Op, dl, DAG); 6607 6608 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6609 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6610 6611 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6612 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6613 6614 if (isMOVLPMask(M, VT)) 6615 return getMOVLP(Op, dl, DAG, HasSSE2); 6616 6617 if (ShouldXformToMOVHLPS(M, VT) || 6618 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6619 return CommuteVectorShuffle(SVOp, DAG); 6620 6621 if (isShift) { 6622 // No better options. Use a vshldq / vsrldq. 6623 EVT EltVT = VT.getVectorElementType(); 6624 ShAmt *= EltVT.getSizeInBits(); 6625 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6626 } 6627 6628 bool Commuted = false; 6629 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6630 // 1,1,1,1 -> v8i16 though. 6631 V1IsSplat = isSplatVector(V1.getNode()); 6632 V2IsSplat = isSplatVector(V2.getNode()); 6633 6634 // Canonicalize the splat or undef, if present, to be on the RHS. 6635 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6636 CommuteVectorShuffleMask(M, NumElems); 6637 std::swap(V1, V2); 6638 std::swap(V1IsSplat, V2IsSplat); 6639 Commuted = true; 6640 } 6641 6642 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6643 // Shuffling low element of v1 into undef, just return v1. 6644 if (V2IsUndef) 6645 return V1; 6646 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6647 // the instruction selector will not match, so get a canonical MOVL with 6648 // swapped operands to undo the commute. 6649 return getMOVL(DAG, dl, VT, V2, V1); 6650 } 6651 6652 if (isUNPCKLMask(M, VT, HasAVX2)) 6653 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6654 6655 if (isUNPCKHMask(M, VT, HasAVX2)) 6656 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6657 6658 if (V2IsSplat) { 6659 // Normalize mask so all entries that point to V2 points to its first 6660 // element then try to match unpck{h|l} again. If match, return a 6661 // new vector_shuffle with the corrected mask.p 6662 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6663 NormalizeMask(NewMask, NumElems); 6664 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) 6665 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6666 if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) 6667 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6668 } 6669 6670 if (Commuted) { 6671 // Commute is back and try unpck* again. 6672 // FIXME: this seems wrong. 6673 CommuteVectorShuffleMask(M, NumElems); 6674 std::swap(V1, V2); 6675 std::swap(V1IsSplat, V2IsSplat); 6676 Commuted = false; 6677 6678 if (isUNPCKLMask(M, VT, HasAVX2)) 6679 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6680 6681 if (isUNPCKHMask(M, VT, HasAVX2)) 6682 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6683 } 6684 6685 // Normalize the node to match x86 shuffle ops if needed 6686 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6687 return CommuteVectorShuffle(SVOp, DAG); 6688 6689 // The checks below are all present in isShuffleMaskLegal, but they are 6690 // inlined here right now to enable us to directly emit target specific 6691 // nodes, and remove one by one until they don't return Op anymore. 6692 6693 if (isPALIGNRMask(M, VT, Subtarget)) 6694 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6695 getShufflePALIGNRImmediate(SVOp), 6696 DAG); 6697 6698 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6699 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6700 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6701 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6702 } 6703 6704 if (isPSHUFHWMask(M, VT, HasAVX2)) 6705 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6706 getShufflePSHUFHWImmediate(SVOp), 6707 DAG); 6708 6709 if (isPSHUFLWMask(M, VT, HasAVX2)) 6710 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6711 getShufflePSHUFLWImmediate(SVOp), 6712 DAG); 6713 6714 if (isSHUFPMask(M, VT, HasAVX)) 6715 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6716 getShuffleSHUFImmediate(SVOp), DAG); 6717 6718 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6719 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6720 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6721 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6722 6723 //===--------------------------------------------------------------------===// 6724 // Generate target specific nodes for 128 or 256-bit shuffles only 6725 // supported in the AVX instruction set. 6726 // 6727 6728 // Handle VMOVDDUPY permutations 6729 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6730 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6731 6732 // Handle VPERMILPS/D* permutations 6733 if (isVPERMILPMask(M, VT, HasAVX)) { 6734 if (HasAVX2 && VT == MVT::v8i32) 6735 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6736 getShuffleSHUFImmediate(SVOp), DAG); 6737 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6738 getShuffleSHUFImmediate(SVOp), DAG); 6739 } 6740 6741 // Handle VPERM2F128/VPERM2I128 permutations 6742 if (isVPERM2X128Mask(M, VT, HasAVX)) 6743 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6744 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6745 6746 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 6747 if (BlendOp.getNode()) 6748 return BlendOp; 6749 6750 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6751 SmallVector<SDValue, 8> permclMask; 6752 for (unsigned i = 0; i != 8; ++i) { 6753 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6754 } 6755 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6756 &permclMask[0], 8); 6757 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6758 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6759 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6760 } 6761 6762 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6763 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 6764 getShuffleCLImmediate(SVOp), DAG); 6765 6766 6767 //===--------------------------------------------------------------------===// 6768 // Since no target specific shuffle was selected for this generic one, 6769 // lower it into other known shuffles. FIXME: this isn't true yet, but 6770 // this is the plan. 6771 // 6772 6773 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6774 if (VT == MVT::v8i16) { 6775 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6776 if (NewOp.getNode()) 6777 return NewOp; 6778 } 6779 6780 if (VT == MVT::v16i8) { 6781 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6782 if (NewOp.getNode()) 6783 return NewOp; 6784 } 6785 6786 // Handle all 128-bit wide vectors with 4 elements, and match them with 6787 // several different shuffle types. 6788 if (NumElems == 4 && VT.getSizeInBits() == 128) 6789 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6790 6791 // Handle general 256-bit shuffles 6792 if (VT.is256BitVector()) 6793 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6794 6795 return SDValue(); 6796} 6797 6798SDValue 6799X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6800 SelectionDAG &DAG) const { 6801 EVT VT = Op.getValueType(); 6802 DebugLoc dl = Op.getDebugLoc(); 6803 6804 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6805 return SDValue(); 6806 6807 if (VT.getSizeInBits() == 8) { 6808 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6809 Op.getOperand(0), Op.getOperand(1)); 6810 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6811 DAG.getValueType(VT)); 6812 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6813 } 6814 6815 if (VT.getSizeInBits() == 16) { 6816 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6817 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6818 if (Idx == 0) 6819 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6820 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6821 DAG.getNode(ISD::BITCAST, dl, 6822 MVT::v4i32, 6823 Op.getOperand(0)), 6824 Op.getOperand(1))); 6825 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6826 Op.getOperand(0), Op.getOperand(1)); 6827 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6828 DAG.getValueType(VT)); 6829 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6830 } 6831 6832 if (VT == MVT::f32) { 6833 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6834 // the result back to FR32 register. It's only worth matching if the 6835 // result has a single use which is a store or a bitcast to i32. And in 6836 // the case of a store, it's not worth it if the index is a constant 0, 6837 // because a MOVSSmr can be used instead, which is smaller and faster. 6838 if (!Op.hasOneUse()) 6839 return SDValue(); 6840 SDNode *User = *Op.getNode()->use_begin(); 6841 if ((User->getOpcode() != ISD::STORE || 6842 (isa<ConstantSDNode>(Op.getOperand(1)) && 6843 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6844 (User->getOpcode() != ISD::BITCAST || 6845 User->getValueType(0) != MVT::i32)) 6846 return SDValue(); 6847 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6848 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6849 Op.getOperand(0)), 6850 Op.getOperand(1)); 6851 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6852 } 6853 6854 if (VT == MVT::i32 || VT == MVT::i64) { 6855 // ExtractPS/pextrq works with constant index. 6856 if (isa<ConstantSDNode>(Op.getOperand(1))) 6857 return Op; 6858 } 6859 return SDValue(); 6860} 6861 6862 6863SDValue 6864X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6865 SelectionDAG &DAG) const { 6866 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6867 return SDValue(); 6868 6869 SDValue Vec = Op.getOperand(0); 6870 EVT VecVT = Vec.getValueType(); 6871 6872 // If this is a 256-bit vector result, first extract the 128-bit vector and 6873 // then extract the element from the 128-bit vector. 6874 if (VecVT.getSizeInBits() == 256) { 6875 DebugLoc dl = Op.getNode()->getDebugLoc(); 6876 unsigned NumElems = VecVT.getVectorNumElements(); 6877 SDValue Idx = Op.getOperand(1); 6878 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6879 6880 // Get the 128-bit vector. 6881 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 6882 6883 if (IdxVal >= NumElems/2) 6884 IdxVal -= NumElems/2; 6885 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6886 DAG.getConstant(IdxVal, MVT::i32)); 6887 } 6888 6889 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6890 6891 if (Subtarget->hasSSE41()) { 6892 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6893 if (Res.getNode()) 6894 return Res; 6895 } 6896 6897 EVT VT = Op.getValueType(); 6898 DebugLoc dl = Op.getDebugLoc(); 6899 // TODO: handle v16i8. 6900 if (VT.getSizeInBits() == 16) { 6901 SDValue Vec = Op.getOperand(0); 6902 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6903 if (Idx == 0) 6904 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6905 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6906 DAG.getNode(ISD::BITCAST, dl, 6907 MVT::v4i32, Vec), 6908 Op.getOperand(1))); 6909 // Transform it so it match pextrw which produces a 32-bit result. 6910 EVT EltVT = MVT::i32; 6911 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6912 Op.getOperand(0), Op.getOperand(1)); 6913 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6914 DAG.getValueType(VT)); 6915 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6916 } 6917 6918 if (VT.getSizeInBits() == 32) { 6919 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6920 if (Idx == 0) 6921 return Op; 6922 6923 // SHUFPS the element to the lowest double word, then movss. 6924 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6925 EVT VVT = Op.getOperand(0).getValueType(); 6926 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6927 DAG.getUNDEF(VVT), Mask); 6928 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6929 DAG.getIntPtrConstant(0)); 6930 } 6931 6932 if (VT.getSizeInBits() == 64) { 6933 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6934 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6935 // to match extract_elt for f64. 6936 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6937 if (Idx == 0) 6938 return Op; 6939 6940 // UNPCKHPD the element to the lowest double word, then movsd. 6941 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6942 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6943 int Mask[2] = { 1, -1 }; 6944 EVT VVT = Op.getOperand(0).getValueType(); 6945 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6946 DAG.getUNDEF(VVT), Mask); 6947 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6948 DAG.getIntPtrConstant(0)); 6949 } 6950 6951 return SDValue(); 6952} 6953 6954SDValue 6955X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6956 SelectionDAG &DAG) const { 6957 EVT VT = Op.getValueType(); 6958 EVT EltVT = VT.getVectorElementType(); 6959 DebugLoc dl = Op.getDebugLoc(); 6960 6961 SDValue N0 = Op.getOperand(0); 6962 SDValue N1 = Op.getOperand(1); 6963 SDValue N2 = Op.getOperand(2); 6964 6965 if (VT.getSizeInBits() == 256) 6966 return SDValue(); 6967 6968 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6969 isa<ConstantSDNode>(N2)) { 6970 unsigned Opc; 6971 if (VT == MVT::v8i16) 6972 Opc = X86ISD::PINSRW; 6973 else if (VT == MVT::v16i8) 6974 Opc = X86ISD::PINSRB; 6975 else 6976 Opc = X86ISD::PINSRB; 6977 6978 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6979 // argument. 6980 if (N1.getValueType() != MVT::i32) 6981 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6982 if (N2.getValueType() != MVT::i32) 6983 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6984 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6985 } 6986 6987 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6988 // Bits [7:6] of the constant are the source select. This will always be 6989 // zero here. The DAG Combiner may combine an extract_elt index into these 6990 // bits. For example (insert (extract, 3), 2) could be matched by putting 6991 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6992 // Bits [5:4] of the constant are the destination select. This is the 6993 // value of the incoming immediate. 6994 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6995 // combine either bitwise AND or insert of float 0.0 to set these bits. 6996 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6997 // Create this as a scalar to vector.. 6998 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6999 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7000 } 7001 7002 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 7003 // PINSR* works with constant index. 7004 return Op; 7005 } 7006 return SDValue(); 7007} 7008 7009SDValue 7010X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7011 EVT VT = Op.getValueType(); 7012 EVT EltVT = VT.getVectorElementType(); 7013 7014 DebugLoc dl = Op.getDebugLoc(); 7015 SDValue N0 = Op.getOperand(0); 7016 SDValue N1 = Op.getOperand(1); 7017 SDValue N2 = Op.getOperand(2); 7018 7019 // If this is a 256-bit vector result, first extract the 128-bit vector, 7020 // insert the element into the extracted half and then place it back. 7021 if (VT.getSizeInBits() == 256) { 7022 if (!isa<ConstantSDNode>(N2)) 7023 return SDValue(); 7024 7025 // Get the desired 128-bit vector half. 7026 unsigned NumElems = VT.getVectorNumElements(); 7027 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7028 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 7029 7030 // Insert the element into the desired half. 7031 bool Upper = IdxVal >= NumElems/2; 7032 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 7033 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32)); 7034 7035 // Insert the changed part back to the 256-bit vector 7036 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 7037 } 7038 7039 if (Subtarget->hasSSE41()) 7040 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7041 7042 if (EltVT == MVT::i8) 7043 return SDValue(); 7044 7045 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7046 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7047 // as its second argument. 7048 if (N1.getValueType() != MVT::i32) 7049 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7050 if (N2.getValueType() != MVT::i32) 7051 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7052 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7053 } 7054 return SDValue(); 7055} 7056 7057SDValue 7058X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 7059 LLVMContext *Context = DAG.getContext(); 7060 DebugLoc dl = Op.getDebugLoc(); 7061 EVT OpVT = Op.getValueType(); 7062 7063 // If this is a 256-bit vector result, first insert into a 128-bit 7064 // vector and then insert into the 256-bit vector. 7065 if (OpVT.getSizeInBits() > 128) { 7066 // Insert into a 128-bit vector. 7067 EVT VT128 = EVT::getVectorVT(*Context, 7068 OpVT.getVectorElementType(), 7069 OpVT.getVectorNumElements() / 2); 7070 7071 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7072 7073 // Insert the 128-bit vector. 7074 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 7075 } 7076 7077 if (OpVT == MVT::v1i64 && 7078 Op.getOperand(0).getValueType() == MVT::i64) 7079 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7080 7081 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7082 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!"); 7083 return DAG.getNode(ISD::BITCAST, dl, OpVT, 7084 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7085} 7086 7087// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7088// a simple subregister reference or explicit instructions to grab 7089// upper bits of a vector. 7090SDValue 7091X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7092 if (Subtarget->hasAVX()) { 7093 DebugLoc dl = Op.getNode()->getDebugLoc(); 7094 SDValue Vec = Op.getNode()->getOperand(0); 7095 SDValue Idx = Op.getNode()->getOperand(1); 7096 7097 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 && 7098 Vec.getNode()->getValueType(0).getSizeInBits() == 256 && 7099 isa<ConstantSDNode>(Idx)) { 7100 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7101 return Extract128BitVector(Vec, IdxVal, DAG, dl); 7102 } 7103 } 7104 return SDValue(); 7105} 7106 7107// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7108// simple superregister reference or explicit instructions to insert 7109// the upper bits of a vector. 7110SDValue 7111X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7112 if (Subtarget->hasAVX()) { 7113 DebugLoc dl = Op.getNode()->getDebugLoc(); 7114 SDValue Vec = Op.getNode()->getOperand(0); 7115 SDValue SubVec = Op.getNode()->getOperand(1); 7116 SDValue Idx = Op.getNode()->getOperand(2); 7117 7118 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 && 7119 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 && 7120 isa<ConstantSDNode>(Idx)) { 7121 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7122 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7123 } 7124 } 7125 return SDValue(); 7126} 7127 7128// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7129// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7130// one of the above mentioned nodes. It has to be wrapped because otherwise 7131// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7132// be used to form addressing mode. These wrapped nodes will be selected 7133// into MOV32ri. 7134SDValue 7135X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7136 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7137 7138 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7139 // global base reg. 7140 unsigned char OpFlag = 0; 7141 unsigned WrapperKind = X86ISD::Wrapper; 7142 CodeModel::Model M = getTargetMachine().getCodeModel(); 7143 7144 if (Subtarget->isPICStyleRIPRel() && 7145 (M == CodeModel::Small || M == CodeModel::Kernel)) 7146 WrapperKind = X86ISD::WrapperRIP; 7147 else if (Subtarget->isPICStyleGOT()) 7148 OpFlag = X86II::MO_GOTOFF; 7149 else if (Subtarget->isPICStyleStubPIC()) 7150 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7151 7152 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7153 CP->getAlignment(), 7154 CP->getOffset(), OpFlag); 7155 DebugLoc DL = CP->getDebugLoc(); 7156 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7157 // With PIC, the address is actually $g + Offset. 7158 if (OpFlag) { 7159 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7160 DAG.getNode(X86ISD::GlobalBaseReg, 7161 DebugLoc(), getPointerTy()), 7162 Result); 7163 } 7164 7165 return Result; 7166} 7167 7168SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7169 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7170 7171 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7172 // global base reg. 7173 unsigned char OpFlag = 0; 7174 unsigned WrapperKind = X86ISD::Wrapper; 7175 CodeModel::Model M = getTargetMachine().getCodeModel(); 7176 7177 if (Subtarget->isPICStyleRIPRel() && 7178 (M == CodeModel::Small || M == CodeModel::Kernel)) 7179 WrapperKind = X86ISD::WrapperRIP; 7180 else if (Subtarget->isPICStyleGOT()) 7181 OpFlag = X86II::MO_GOTOFF; 7182 else if (Subtarget->isPICStyleStubPIC()) 7183 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7184 7185 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7186 OpFlag); 7187 DebugLoc DL = JT->getDebugLoc(); 7188 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7189 7190 // With PIC, the address is actually $g + Offset. 7191 if (OpFlag) 7192 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7193 DAG.getNode(X86ISD::GlobalBaseReg, 7194 DebugLoc(), getPointerTy()), 7195 Result); 7196 7197 return Result; 7198} 7199 7200SDValue 7201X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7202 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7203 7204 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7205 // global base reg. 7206 unsigned char OpFlag = 0; 7207 unsigned WrapperKind = X86ISD::Wrapper; 7208 CodeModel::Model M = getTargetMachine().getCodeModel(); 7209 7210 if (Subtarget->isPICStyleRIPRel() && 7211 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7212 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7213 OpFlag = X86II::MO_GOTPCREL; 7214 WrapperKind = X86ISD::WrapperRIP; 7215 } else if (Subtarget->isPICStyleGOT()) { 7216 OpFlag = X86II::MO_GOT; 7217 } else if (Subtarget->isPICStyleStubPIC()) { 7218 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7219 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7220 OpFlag = X86II::MO_DARWIN_NONLAZY; 7221 } 7222 7223 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7224 7225 DebugLoc DL = Op.getDebugLoc(); 7226 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7227 7228 7229 // With PIC, the address is actually $g + Offset. 7230 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7231 !Subtarget->is64Bit()) { 7232 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7233 DAG.getNode(X86ISD::GlobalBaseReg, 7234 DebugLoc(), getPointerTy()), 7235 Result); 7236 } 7237 7238 // For symbols that require a load from a stub to get the address, emit the 7239 // load. 7240 if (isGlobalStubReference(OpFlag)) 7241 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7242 MachinePointerInfo::getGOT(), false, false, false, 0); 7243 7244 return Result; 7245} 7246 7247SDValue 7248X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7249 // Create the TargetBlockAddressAddress node. 7250 unsigned char OpFlags = 7251 Subtarget->ClassifyBlockAddressReference(); 7252 CodeModel::Model M = getTargetMachine().getCodeModel(); 7253 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7254 DebugLoc dl = Op.getDebugLoc(); 7255 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7256 /*isTarget=*/true, OpFlags); 7257 7258 if (Subtarget->isPICStyleRIPRel() && 7259 (M == CodeModel::Small || M == CodeModel::Kernel)) 7260 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7261 else 7262 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7263 7264 // With PIC, the address is actually $g + Offset. 7265 if (isGlobalRelativeToPICBase(OpFlags)) { 7266 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7267 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7268 Result); 7269 } 7270 7271 return Result; 7272} 7273 7274SDValue 7275X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7276 int64_t Offset, 7277 SelectionDAG &DAG) const { 7278 // Create the TargetGlobalAddress node, folding in the constant 7279 // offset if it is legal. 7280 unsigned char OpFlags = 7281 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7282 CodeModel::Model M = getTargetMachine().getCodeModel(); 7283 SDValue Result; 7284 if (OpFlags == X86II::MO_NO_FLAG && 7285 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7286 // A direct static reference to a global. 7287 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7288 Offset = 0; 7289 } else { 7290 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7291 } 7292 7293 if (Subtarget->isPICStyleRIPRel() && 7294 (M == CodeModel::Small || M == CodeModel::Kernel)) 7295 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7296 else 7297 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7298 7299 // With PIC, the address is actually $g + Offset. 7300 if (isGlobalRelativeToPICBase(OpFlags)) { 7301 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7302 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7303 Result); 7304 } 7305 7306 // For globals that require a load from a stub to get the address, emit the 7307 // load. 7308 if (isGlobalStubReference(OpFlags)) 7309 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7310 MachinePointerInfo::getGOT(), false, false, false, 0); 7311 7312 // If there was a non-zero offset that we didn't fold, create an explicit 7313 // addition for it. 7314 if (Offset != 0) 7315 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7316 DAG.getConstant(Offset, getPointerTy())); 7317 7318 return Result; 7319} 7320 7321SDValue 7322X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7323 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7324 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7325 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7326} 7327 7328static SDValue 7329GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7330 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7331 unsigned char OperandFlags, bool LocalDynamic = false) { 7332 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7333 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7334 DebugLoc dl = GA->getDebugLoc(); 7335 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7336 GA->getValueType(0), 7337 GA->getOffset(), 7338 OperandFlags); 7339 7340 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR 7341 : X86ISD::TLSADDR; 7342 7343 if (InFlag) { 7344 SDValue Ops[] = { Chain, TGA, *InFlag }; 7345 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3); 7346 } else { 7347 SDValue Ops[] = { Chain, TGA }; 7348 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2); 7349 } 7350 7351 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7352 MFI->setAdjustsStack(true); 7353 7354 SDValue Flag = Chain.getValue(1); 7355 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7356} 7357 7358// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7359static SDValue 7360LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7361 const EVT PtrVT) { 7362 SDValue InFlag; 7363 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7364 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7365 DAG.getNode(X86ISD::GlobalBaseReg, 7366 DebugLoc(), PtrVT), InFlag); 7367 InFlag = Chain.getValue(1); 7368 7369 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7370} 7371 7372// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7373static SDValue 7374LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7375 const EVT PtrVT) { 7376 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7377 X86::RAX, X86II::MO_TLSGD); 7378} 7379 7380static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, 7381 SelectionDAG &DAG, 7382 const EVT PtrVT, 7383 bool is64Bit) { 7384 DebugLoc dl = GA->getDebugLoc(); 7385 7386 // Get the start address of the TLS block for this module. 7387 X86MachineFunctionInfo* MFI = DAG.getMachineFunction() 7388 .getInfo<X86MachineFunctionInfo>(); 7389 MFI->incNumLocalDynamicTLSAccesses(); 7390 7391 SDValue Base; 7392 if (is64Bit) { 7393 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX, 7394 X86II::MO_TLSLD, /*LocalDynamic=*/true); 7395 } else { 7396 SDValue InFlag; 7397 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7398 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag); 7399 InFlag = Chain.getValue(1); 7400 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, 7401 X86II::MO_TLSLDM, /*LocalDynamic=*/true); 7402 } 7403 7404 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations 7405 // of Base. 7406 7407 // Build x@dtpoff. 7408 unsigned char OperandFlags = X86II::MO_DTPOFF; 7409 unsigned WrapperKind = X86ISD::Wrapper; 7410 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7411 GA->getValueType(0), 7412 GA->getOffset(), OperandFlags); 7413 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7414 7415 // Add x@dtpoff with the base. 7416 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base); 7417} 7418 7419// Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model. 7420static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7421 const EVT PtrVT, TLSModel::Model model, 7422 bool is64Bit, bool isPIC) { 7423 DebugLoc dl = GA->getDebugLoc(); 7424 7425 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7426 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7427 is64Bit ? 257 : 256)); 7428 7429 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7430 DAG.getIntPtrConstant(0), 7431 MachinePointerInfo(Ptr), 7432 false, false, false, 0); 7433 7434 unsigned char OperandFlags = 0; 7435 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7436 // initialexec. 7437 unsigned WrapperKind = X86ISD::Wrapper; 7438 if (model == TLSModel::LocalExec) { 7439 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7440 } else if (model == TLSModel::InitialExec) { 7441 if (is64Bit) { 7442 OperandFlags = X86II::MO_GOTTPOFF; 7443 WrapperKind = X86ISD::WrapperRIP; 7444 } else { 7445 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF; 7446 } 7447 } else { 7448 llvm_unreachable("Unexpected model"); 7449 } 7450 7451 // emit "addl x@ntpoff,%eax" (local exec) 7452 // or "addl x@indntpoff,%eax" (initial exec) 7453 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic) 7454 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7455 GA->getValueType(0), 7456 GA->getOffset(), OperandFlags); 7457 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7458 7459 if (model == TLSModel::InitialExec) { 7460 if (isPIC && !is64Bit) { 7461 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, 7462 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), 7463 Offset); 7464 } 7465 7466 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7467 MachinePointerInfo::getGOT(), false, false, false, 7468 0); 7469 } 7470 7471 // The address of the thread local variable is the add of the thread 7472 // pointer with the offset of the variable. 7473 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7474} 7475 7476SDValue 7477X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7478 7479 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7480 const GlobalValue *GV = GA->getGlobal(); 7481 7482 if (Subtarget->isTargetELF()) { 7483 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7484 7485 switch (model) { 7486 case TLSModel::GeneralDynamic: 7487 if (Subtarget->is64Bit()) 7488 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7489 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7490 case TLSModel::LocalDynamic: 7491 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(), 7492 Subtarget->is64Bit()); 7493 case TLSModel::InitialExec: 7494 case TLSModel::LocalExec: 7495 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7496 Subtarget->is64Bit(), 7497 getTargetMachine().getRelocationModel() == Reloc::PIC_); 7498 } 7499 llvm_unreachable("Unknown TLS model."); 7500 } 7501 7502 if (Subtarget->isTargetDarwin()) { 7503 // Darwin only has one model of TLS. Lower to that. 7504 unsigned char OpFlag = 0; 7505 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7506 X86ISD::WrapperRIP : X86ISD::Wrapper; 7507 7508 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7509 // global base reg. 7510 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7511 !Subtarget->is64Bit(); 7512 if (PIC32) 7513 OpFlag = X86II::MO_TLVP_PIC_BASE; 7514 else 7515 OpFlag = X86II::MO_TLVP; 7516 DebugLoc DL = Op.getDebugLoc(); 7517 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7518 GA->getValueType(0), 7519 GA->getOffset(), OpFlag); 7520 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7521 7522 // With PIC32, the address is actually $g + Offset. 7523 if (PIC32) 7524 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7525 DAG.getNode(X86ISD::GlobalBaseReg, 7526 DebugLoc(), getPointerTy()), 7527 Offset); 7528 7529 // Lowering the machine isd will make sure everything is in the right 7530 // location. 7531 SDValue Chain = DAG.getEntryNode(); 7532 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7533 SDValue Args[] = { Chain, Offset }; 7534 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7535 7536 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7537 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7538 MFI->setAdjustsStack(true); 7539 7540 // And our return value (tls address) is in the standard call return value 7541 // location. 7542 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7543 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7544 Chain.getValue(1)); 7545 } 7546 7547 if (Subtarget->isTargetWindows()) { 7548 // Just use the implicit TLS architecture 7549 // Need to generate someting similar to: 7550 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7551 // ; from TEB 7552 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7553 // mov rcx, qword [rdx+rcx*8] 7554 // mov eax, .tls$:tlsvar 7555 // [rax+rcx] contains the address 7556 // Windows 64bit: gs:0x58 7557 // Windows 32bit: fs:__tls_array 7558 7559 // If GV is an alias then use the aliasee for determining 7560 // thread-localness. 7561 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7562 GV = GA->resolveAliasedGlobal(false); 7563 DebugLoc dl = GA->getDebugLoc(); 7564 SDValue Chain = DAG.getEntryNode(); 7565 7566 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7567 // %gs:0x58 (64-bit). 7568 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7569 ? Type::getInt8PtrTy(*DAG.getContext(), 7570 256) 7571 : Type::getInt32PtrTy(*DAG.getContext(), 7572 257)); 7573 7574 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7575 Subtarget->is64Bit() 7576 ? DAG.getIntPtrConstant(0x58) 7577 : DAG.getExternalSymbol("_tls_array", 7578 getPointerTy()), 7579 MachinePointerInfo(Ptr), 7580 false, false, false, 0); 7581 7582 // Load the _tls_index variable 7583 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7584 if (Subtarget->is64Bit()) 7585 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7586 IDX, MachinePointerInfo(), MVT::i32, 7587 false, false, 0); 7588 else 7589 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7590 false, false, false, 0); 7591 7592 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7593 getPointerTy()); 7594 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7595 7596 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7597 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7598 false, false, false, 0); 7599 7600 // Get the offset of start of .tls section 7601 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7602 GA->getValueType(0), 7603 GA->getOffset(), X86II::MO_SECREL); 7604 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7605 7606 // The address of the thread local variable is the add of the thread 7607 // pointer with the offset of the variable. 7608 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7609 } 7610 7611 llvm_unreachable("TLS not implemented for this target."); 7612} 7613 7614 7615/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7616/// and take a 2 x i32 value to shift plus a shift amount. 7617SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7618 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7619 EVT VT = Op.getValueType(); 7620 unsigned VTBits = VT.getSizeInBits(); 7621 DebugLoc dl = Op.getDebugLoc(); 7622 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7623 SDValue ShOpLo = Op.getOperand(0); 7624 SDValue ShOpHi = Op.getOperand(1); 7625 SDValue ShAmt = Op.getOperand(2); 7626 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7627 DAG.getConstant(VTBits - 1, MVT::i8)) 7628 : DAG.getConstant(0, VT); 7629 7630 SDValue Tmp2, Tmp3; 7631 if (Op.getOpcode() == ISD::SHL_PARTS) { 7632 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7633 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7634 } else { 7635 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7636 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7637 } 7638 7639 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7640 DAG.getConstant(VTBits, MVT::i8)); 7641 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7642 AndNode, DAG.getConstant(0, MVT::i8)); 7643 7644 SDValue Hi, Lo; 7645 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7646 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7647 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7648 7649 if (Op.getOpcode() == ISD::SHL_PARTS) { 7650 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7651 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7652 } else { 7653 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7654 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7655 } 7656 7657 SDValue Ops[2] = { Lo, Hi }; 7658 return DAG.getMergeValues(Ops, 2, dl); 7659} 7660 7661SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7662 SelectionDAG &DAG) const { 7663 EVT SrcVT = Op.getOperand(0).getValueType(); 7664 7665 if (SrcVT.isVector()) 7666 return SDValue(); 7667 7668 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7669 "Unknown SINT_TO_FP to lower!"); 7670 7671 // These are really Legal; return the operand so the caller accepts it as 7672 // Legal. 7673 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7674 return Op; 7675 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7676 Subtarget->is64Bit()) { 7677 return Op; 7678 } 7679 7680 DebugLoc dl = Op.getDebugLoc(); 7681 unsigned Size = SrcVT.getSizeInBits()/8; 7682 MachineFunction &MF = DAG.getMachineFunction(); 7683 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7684 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7685 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7686 StackSlot, 7687 MachinePointerInfo::getFixedStack(SSFI), 7688 false, false, 0); 7689 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7690} 7691 7692SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7693 SDValue StackSlot, 7694 SelectionDAG &DAG) const { 7695 // Build the FILD 7696 DebugLoc DL = Op.getDebugLoc(); 7697 SDVTList Tys; 7698 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7699 if (useSSE) 7700 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7701 else 7702 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7703 7704 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7705 7706 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7707 MachineMemOperand *MMO; 7708 if (FI) { 7709 int SSFI = FI->getIndex(); 7710 MMO = 7711 DAG.getMachineFunction() 7712 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7713 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7714 } else { 7715 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7716 StackSlot = StackSlot.getOperand(1); 7717 } 7718 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7719 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7720 X86ISD::FILD, DL, 7721 Tys, Ops, array_lengthof(Ops), 7722 SrcVT, MMO); 7723 7724 if (useSSE) { 7725 Chain = Result.getValue(1); 7726 SDValue InFlag = Result.getValue(2); 7727 7728 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7729 // shouldn't be necessary except that RFP cannot be live across 7730 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7731 MachineFunction &MF = DAG.getMachineFunction(); 7732 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7733 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7734 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7735 Tys = DAG.getVTList(MVT::Other); 7736 SDValue Ops[] = { 7737 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7738 }; 7739 MachineMemOperand *MMO = 7740 DAG.getMachineFunction() 7741 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7742 MachineMemOperand::MOStore, SSFISize, SSFISize); 7743 7744 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7745 Ops, array_lengthof(Ops), 7746 Op.getValueType(), MMO); 7747 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7748 MachinePointerInfo::getFixedStack(SSFI), 7749 false, false, false, 0); 7750 } 7751 7752 return Result; 7753} 7754 7755// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7756SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7757 SelectionDAG &DAG) const { 7758 // This algorithm is not obvious. Here it is what we're trying to output: 7759 /* 7760 movq %rax, %xmm0 7761 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7762 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7763 #ifdef __SSE3__ 7764 haddpd %xmm0, %xmm0 7765 #else 7766 pshufd $0x4e, %xmm0, %xmm1 7767 addpd %xmm1, %xmm0 7768 #endif 7769 */ 7770 7771 DebugLoc dl = Op.getDebugLoc(); 7772 LLVMContext *Context = DAG.getContext(); 7773 7774 // Build some magic constants. 7775 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7776 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7777 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7778 7779 SmallVector<Constant*,2> CV1; 7780 CV1.push_back( 7781 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7782 CV1.push_back( 7783 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7784 Constant *C1 = ConstantVector::get(CV1); 7785 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7786 7787 // Load the 64-bit value into an XMM register. 7788 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7789 Op.getOperand(0)); 7790 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7791 MachinePointerInfo::getConstantPool(), 7792 false, false, false, 16); 7793 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7794 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7795 CLod0); 7796 7797 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7798 MachinePointerInfo::getConstantPool(), 7799 false, false, false, 16); 7800 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7801 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7802 SDValue Result; 7803 7804 if (Subtarget->hasSSE3()) { 7805 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7806 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7807 } else { 7808 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7809 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7810 S2F, 0x4E, DAG); 7811 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7812 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7813 Sub); 7814 } 7815 7816 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7817 DAG.getIntPtrConstant(0)); 7818} 7819 7820// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7821SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7822 SelectionDAG &DAG) const { 7823 DebugLoc dl = Op.getDebugLoc(); 7824 // FP constant to bias correct the final result. 7825 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7826 MVT::f64); 7827 7828 // Load the 32-bit value into an XMM register. 7829 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7830 Op.getOperand(0)); 7831 7832 // Zero out the upper parts of the register. 7833 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7834 7835 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7836 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7837 DAG.getIntPtrConstant(0)); 7838 7839 // Or the load with the bias. 7840 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7841 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7842 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7843 MVT::v2f64, Load)), 7844 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7845 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7846 MVT::v2f64, Bias))); 7847 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7848 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7849 DAG.getIntPtrConstant(0)); 7850 7851 // Subtract the bias. 7852 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7853 7854 // Handle final rounding. 7855 EVT DestVT = Op.getValueType(); 7856 7857 if (DestVT.bitsLT(MVT::f64)) 7858 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7859 DAG.getIntPtrConstant(0)); 7860 if (DestVT.bitsGT(MVT::f64)) 7861 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7862 7863 // Handle final rounding. 7864 return Sub; 7865} 7866 7867SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7868 SelectionDAG &DAG) const { 7869 SDValue N0 = Op.getOperand(0); 7870 DebugLoc dl = Op.getDebugLoc(); 7871 7872 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7873 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7874 // the optimization here. 7875 if (DAG.SignBitIsZero(N0)) 7876 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7877 7878 EVT SrcVT = N0.getValueType(); 7879 EVT DstVT = Op.getValueType(); 7880 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7881 return LowerUINT_TO_FP_i64(Op, DAG); 7882 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7883 return LowerUINT_TO_FP_i32(Op, DAG); 7884 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 7885 return SDValue(); 7886 7887 // Make a 64-bit buffer, and use it to build an FILD. 7888 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7889 if (SrcVT == MVT::i32) { 7890 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7891 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7892 getPointerTy(), StackSlot, WordOff); 7893 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7894 StackSlot, MachinePointerInfo(), 7895 false, false, 0); 7896 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7897 OffsetSlot, MachinePointerInfo(), 7898 false, false, 0); 7899 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7900 return Fild; 7901 } 7902 7903 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7904 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7905 StackSlot, MachinePointerInfo(), 7906 false, false, 0); 7907 // For i64 source, we need to add the appropriate power of 2 if the input 7908 // was negative. This is the same as the optimization in 7909 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7910 // we must be careful to do the computation in x87 extended precision, not 7911 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7912 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7913 MachineMemOperand *MMO = 7914 DAG.getMachineFunction() 7915 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7916 MachineMemOperand::MOLoad, 8, 8); 7917 7918 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7919 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7920 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7921 MVT::i64, MMO); 7922 7923 APInt FF(32, 0x5F800000ULL); 7924 7925 // Check whether the sign bit is set. 7926 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7927 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7928 ISD::SETLT); 7929 7930 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7931 SDValue FudgePtr = DAG.getConstantPool( 7932 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7933 getPointerTy()); 7934 7935 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7936 SDValue Zero = DAG.getIntPtrConstant(0); 7937 SDValue Four = DAG.getIntPtrConstant(4); 7938 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7939 Zero, Four); 7940 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7941 7942 // Load the value out, extending it from f32 to f80. 7943 // FIXME: Avoid the extend by constructing the right constant pool? 7944 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7945 FudgePtr, MachinePointerInfo::getConstantPool(), 7946 MVT::f32, false, false, 4); 7947 // Extend everything to 80 bits to force it to be done on x87. 7948 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7949 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7950} 7951 7952std::pair<SDValue,SDValue> X86TargetLowering:: 7953FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7954 DebugLoc DL = Op.getDebugLoc(); 7955 7956 EVT DstTy = Op.getValueType(); 7957 7958 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7959 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7960 DstTy = MVT::i64; 7961 } 7962 7963 assert(DstTy.getSimpleVT() <= MVT::i64 && 7964 DstTy.getSimpleVT() >= MVT::i16 && 7965 "Unknown FP_TO_INT to lower!"); 7966 7967 // These are really Legal. 7968 if (DstTy == MVT::i32 && 7969 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7970 return std::make_pair(SDValue(), SDValue()); 7971 if (Subtarget->is64Bit() && 7972 DstTy == MVT::i64 && 7973 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7974 return std::make_pair(SDValue(), SDValue()); 7975 7976 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7977 // stack slot, or into the FTOL runtime function. 7978 MachineFunction &MF = DAG.getMachineFunction(); 7979 unsigned MemSize = DstTy.getSizeInBits()/8; 7980 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7981 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7982 7983 unsigned Opc; 7984 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7985 Opc = X86ISD::WIN_FTOL; 7986 else 7987 switch (DstTy.getSimpleVT().SimpleTy) { 7988 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7989 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7990 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7991 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7992 } 7993 7994 SDValue Chain = DAG.getEntryNode(); 7995 SDValue Value = Op.getOperand(0); 7996 EVT TheVT = Op.getOperand(0).getValueType(); 7997 // FIXME This causes a redundant load/store if the SSE-class value is already 7998 // in memory, such as if it is on the callstack. 7999 if (isScalarFPTypeInSSEReg(TheVT)) { 8000 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8001 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8002 MachinePointerInfo::getFixedStack(SSFI), 8003 false, false, 0); 8004 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8005 SDValue Ops[] = { 8006 Chain, StackSlot, DAG.getValueType(TheVT) 8007 }; 8008 8009 MachineMemOperand *MMO = 8010 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8011 MachineMemOperand::MOLoad, MemSize, MemSize); 8012 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 8013 DstTy, MMO); 8014 Chain = Value.getValue(1); 8015 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8016 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8017 } 8018 8019 MachineMemOperand *MMO = 8020 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8021 MachineMemOperand::MOStore, MemSize, MemSize); 8022 8023 if (Opc != X86ISD::WIN_FTOL) { 8024 // Build the FP_TO_INT*_IN_MEM 8025 SDValue Ops[] = { Chain, Value, StackSlot }; 8026 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8027 Ops, 3, DstTy, MMO); 8028 return std::make_pair(FIST, StackSlot); 8029 } else { 8030 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 8031 DAG.getVTList(MVT::Other, MVT::Glue), 8032 Chain, Value); 8033 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 8034 MVT::i32, ftol.getValue(1)); 8035 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 8036 MVT::i32, eax.getValue(2)); 8037 SDValue Ops[] = { eax, edx }; 8038 SDValue pair = IsReplace 8039 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 8040 : DAG.getMergeValues(Ops, 2, DL); 8041 return std::make_pair(pair, SDValue()); 8042 } 8043} 8044 8045SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 8046 SelectionDAG &DAG) const { 8047 if (Op.getValueType().isVector()) 8048 return SDValue(); 8049 8050 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8051 /*IsSigned=*/ true, /*IsReplace=*/ false); 8052 SDValue FIST = Vals.first, StackSlot = Vals.second; 8053 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 8054 if (FIST.getNode() == 0) return Op; 8055 8056 if (StackSlot.getNode()) 8057 // Load the result. 8058 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8059 FIST, StackSlot, MachinePointerInfo(), 8060 false, false, false, 0); 8061 8062 // The node is the result. 8063 return FIST; 8064} 8065 8066SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 8067 SelectionDAG &DAG) const { 8068 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 8069 /*IsSigned=*/ false, /*IsReplace=*/ false); 8070 SDValue FIST = Vals.first, StackSlot = Vals.second; 8071 assert(FIST.getNode() && "Unexpected failure"); 8072 8073 if (StackSlot.getNode()) 8074 // Load the result. 8075 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8076 FIST, StackSlot, MachinePointerInfo(), 8077 false, false, false, 0); 8078 8079 // The node is the result. 8080 return FIST; 8081} 8082 8083SDValue X86TargetLowering::LowerFABS(SDValue Op, 8084 SelectionDAG &DAG) const { 8085 LLVMContext *Context = DAG.getContext(); 8086 DebugLoc dl = Op.getDebugLoc(); 8087 EVT VT = Op.getValueType(); 8088 EVT EltVT = VT; 8089 if (VT.isVector()) 8090 EltVT = VT.getVectorElementType(); 8091 Constant *C; 8092 if (EltVT == MVT::f64) { 8093 C = ConstantVector::getSplat(2, 8094 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8095 } else { 8096 C = ConstantVector::getSplat(4, 8097 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8098 } 8099 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8100 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8101 MachinePointerInfo::getConstantPool(), 8102 false, false, false, 16); 8103 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8104} 8105 8106SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8107 LLVMContext *Context = DAG.getContext(); 8108 DebugLoc dl = Op.getDebugLoc(); 8109 EVT VT = Op.getValueType(); 8110 EVT EltVT = VT; 8111 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 8112 if (VT.isVector()) { 8113 EltVT = VT.getVectorElementType(); 8114 NumElts = VT.getVectorNumElements(); 8115 } 8116 Constant *C; 8117 if (EltVT == MVT::f64) 8118 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8119 else 8120 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8121 C = ConstantVector::getSplat(NumElts, C); 8122 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8123 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8124 MachinePointerInfo::getConstantPool(), 8125 false, false, false, 16); 8126 if (VT.isVector()) { 8127 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 8128 return DAG.getNode(ISD::BITCAST, dl, VT, 8129 DAG.getNode(ISD::XOR, dl, XORVT, 8130 DAG.getNode(ISD::BITCAST, dl, XORVT, 8131 Op.getOperand(0)), 8132 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 8133 } 8134 8135 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8136} 8137 8138SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8139 LLVMContext *Context = DAG.getContext(); 8140 SDValue Op0 = Op.getOperand(0); 8141 SDValue Op1 = Op.getOperand(1); 8142 DebugLoc dl = Op.getDebugLoc(); 8143 EVT VT = Op.getValueType(); 8144 EVT SrcVT = Op1.getValueType(); 8145 8146 // If second operand is smaller, extend it first. 8147 if (SrcVT.bitsLT(VT)) { 8148 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8149 SrcVT = VT; 8150 } 8151 // And if it is bigger, shrink it first. 8152 if (SrcVT.bitsGT(VT)) { 8153 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8154 SrcVT = VT; 8155 } 8156 8157 // At this point the operands and the result should have the same 8158 // type, and that won't be f80 since that is not custom lowered. 8159 8160 // First get the sign bit of second operand. 8161 SmallVector<Constant*,4> CV; 8162 if (SrcVT == MVT::f64) { 8163 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8164 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8165 } else { 8166 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8167 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8168 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8169 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8170 } 8171 Constant *C = ConstantVector::get(CV); 8172 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8173 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8174 MachinePointerInfo::getConstantPool(), 8175 false, false, false, 16); 8176 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8177 8178 // Shift sign bit right or left if the two operands have different types. 8179 if (SrcVT.bitsGT(VT)) { 8180 // Op0 is MVT::f32, Op1 is MVT::f64. 8181 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8182 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8183 DAG.getConstant(32, MVT::i32)); 8184 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8185 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8186 DAG.getIntPtrConstant(0)); 8187 } 8188 8189 // Clear first operand sign bit. 8190 CV.clear(); 8191 if (VT == MVT::f64) { 8192 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8193 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8194 } else { 8195 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8196 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8197 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8198 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8199 } 8200 C = ConstantVector::get(CV); 8201 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8202 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8203 MachinePointerInfo::getConstantPool(), 8204 false, false, false, 16); 8205 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8206 8207 // Or the value with the sign bit. 8208 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8209} 8210 8211SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8212 SDValue N0 = Op.getOperand(0); 8213 DebugLoc dl = Op.getDebugLoc(); 8214 EVT VT = Op.getValueType(); 8215 8216 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8217 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8218 DAG.getConstant(1, VT)); 8219 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8220} 8221 8222/// Emit nodes that will be selected as "test Op0,Op0", or something 8223/// equivalent. 8224SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8225 SelectionDAG &DAG) const { 8226 DebugLoc dl = Op.getDebugLoc(); 8227 8228 // CF and OF aren't always set the way we want. Determine which 8229 // of these we need. 8230 bool NeedCF = false; 8231 bool NeedOF = false; 8232 switch (X86CC) { 8233 default: break; 8234 case X86::COND_A: case X86::COND_AE: 8235 case X86::COND_B: case X86::COND_BE: 8236 NeedCF = true; 8237 break; 8238 case X86::COND_G: case X86::COND_GE: 8239 case X86::COND_L: case X86::COND_LE: 8240 case X86::COND_O: case X86::COND_NO: 8241 NeedOF = true; 8242 break; 8243 } 8244 8245 // See if we can use the EFLAGS value from the operand instead of 8246 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8247 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8248 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8249 // Emit a CMP with 0, which is the TEST pattern. 8250 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8251 DAG.getConstant(0, Op.getValueType())); 8252 8253 unsigned Opcode = 0; 8254 unsigned NumOperands = 0; 8255 switch (Op.getNode()->getOpcode()) { 8256 case ISD::ADD: 8257 // Due to an isel shortcoming, be conservative if this add is likely to be 8258 // selected as part of a load-modify-store instruction. When the root node 8259 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8260 // uses of other nodes in the match, such as the ADD in this case. This 8261 // leads to the ADD being left around and reselected, with the result being 8262 // two adds in the output. Alas, even if none our users are stores, that 8263 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8264 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8265 // climbing the DAG back to the root, and it doesn't seem to be worth the 8266 // effort. 8267 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8268 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8269 if (UI->getOpcode() != ISD::CopyToReg && 8270 UI->getOpcode() != ISD::SETCC && 8271 UI->getOpcode() != ISD::STORE) 8272 goto default_case; 8273 8274 if (ConstantSDNode *C = 8275 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8276 // An add of one will be selected as an INC. 8277 if (C->getAPIntValue() == 1) { 8278 Opcode = X86ISD::INC; 8279 NumOperands = 1; 8280 break; 8281 } 8282 8283 // An add of negative one (subtract of one) will be selected as a DEC. 8284 if (C->getAPIntValue().isAllOnesValue()) { 8285 Opcode = X86ISD::DEC; 8286 NumOperands = 1; 8287 break; 8288 } 8289 } 8290 8291 // Otherwise use a regular EFLAGS-setting add. 8292 Opcode = X86ISD::ADD; 8293 NumOperands = 2; 8294 break; 8295 case ISD::AND: { 8296 // If the primary and result isn't used, don't bother using X86ISD::AND, 8297 // because a TEST instruction will be better. 8298 bool NonFlagUse = false; 8299 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8300 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8301 SDNode *User = *UI; 8302 unsigned UOpNo = UI.getOperandNo(); 8303 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8304 // Look pass truncate. 8305 UOpNo = User->use_begin().getOperandNo(); 8306 User = *User->use_begin(); 8307 } 8308 8309 if (User->getOpcode() != ISD::BRCOND && 8310 User->getOpcode() != ISD::SETCC && 8311 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8312 NonFlagUse = true; 8313 break; 8314 } 8315 } 8316 8317 if (!NonFlagUse) 8318 break; 8319 } 8320 // FALL THROUGH 8321 case ISD::SUB: 8322 case ISD::OR: 8323 case ISD::XOR: 8324 // Due to the ISEL shortcoming noted above, be conservative if this op is 8325 // likely to be selected as part of a load-modify-store instruction. 8326 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8327 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8328 if (UI->getOpcode() == ISD::STORE) 8329 goto default_case; 8330 8331 // Otherwise use a regular EFLAGS-setting instruction. 8332 switch (Op.getNode()->getOpcode()) { 8333 default: llvm_unreachable("unexpected operator!"); 8334 case ISD::SUB: 8335 // If the only use of SUB is EFLAGS, use CMP instead. 8336 if (Op.hasOneUse()) 8337 Opcode = X86ISD::CMP; 8338 else 8339 Opcode = X86ISD::SUB; 8340 break; 8341 case ISD::OR: Opcode = X86ISD::OR; break; 8342 case ISD::XOR: Opcode = X86ISD::XOR; break; 8343 case ISD::AND: Opcode = X86ISD::AND; break; 8344 } 8345 8346 NumOperands = 2; 8347 break; 8348 case X86ISD::ADD: 8349 case X86ISD::SUB: 8350 case X86ISD::INC: 8351 case X86ISD::DEC: 8352 case X86ISD::OR: 8353 case X86ISD::XOR: 8354 case X86ISD::AND: 8355 return SDValue(Op.getNode(), 1); 8356 default: 8357 default_case: 8358 break; 8359 } 8360 8361 if (Opcode == 0) 8362 // Emit a CMP with 0, which is the TEST pattern. 8363 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8364 DAG.getConstant(0, Op.getValueType())); 8365 8366 if (Opcode == X86ISD::CMP) { 8367 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0), 8368 Op.getOperand(1)); 8369 // We can't replace usage of SUB with CMP. 8370 // The SUB node will be removed later because there is no use of it. 8371 return SDValue(New.getNode(), 0); 8372 } 8373 8374 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8375 SmallVector<SDValue, 4> Ops; 8376 for (unsigned i = 0; i != NumOperands; ++i) 8377 Ops.push_back(Op.getOperand(i)); 8378 8379 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8380 DAG.ReplaceAllUsesWith(Op, New); 8381 return SDValue(New.getNode(), 1); 8382} 8383 8384/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8385/// equivalent. 8386SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8387 SelectionDAG &DAG) const { 8388 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8389 if (C->getAPIntValue() == 0) 8390 return EmitTest(Op0, X86CC, DAG); 8391 8392 DebugLoc dl = Op0.getDebugLoc(); 8393 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8394} 8395 8396/// Convert a comparison if required by the subtarget. 8397SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 8398 SelectionDAG &DAG) const { 8399 // If the subtarget does not support the FUCOMI instruction, floating-point 8400 // comparisons have to be converted. 8401 if (Subtarget->hasCMov() || 8402 Cmp.getOpcode() != X86ISD::CMP || 8403 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 8404 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 8405 return Cmp; 8406 8407 // The instruction selector will select an FUCOM instruction instead of 8408 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 8409 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 8410 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 8411 DebugLoc dl = Cmp.getDebugLoc(); 8412 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 8413 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 8414 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 8415 DAG.getConstant(8, MVT::i8)); 8416 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 8417 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 8418} 8419 8420/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8421/// if it's possible. 8422SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8423 DebugLoc dl, SelectionDAG &DAG) const { 8424 SDValue Op0 = And.getOperand(0); 8425 SDValue Op1 = And.getOperand(1); 8426 if (Op0.getOpcode() == ISD::TRUNCATE) 8427 Op0 = Op0.getOperand(0); 8428 if (Op1.getOpcode() == ISD::TRUNCATE) 8429 Op1 = Op1.getOperand(0); 8430 8431 SDValue LHS, RHS; 8432 if (Op1.getOpcode() == ISD::SHL) 8433 std::swap(Op0, Op1); 8434 if (Op0.getOpcode() == ISD::SHL) { 8435 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8436 if (And00C->getZExtValue() == 1) { 8437 // If we looked past a truncate, check that it's only truncating away 8438 // known zeros. 8439 unsigned BitWidth = Op0.getValueSizeInBits(); 8440 unsigned AndBitWidth = And.getValueSizeInBits(); 8441 if (BitWidth > AndBitWidth) { 8442 APInt Zeros, Ones; 8443 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8444 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8445 return SDValue(); 8446 } 8447 LHS = Op1; 8448 RHS = Op0.getOperand(1); 8449 } 8450 } else if (Op1.getOpcode() == ISD::Constant) { 8451 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8452 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8453 SDValue AndLHS = Op0; 8454 8455 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8456 LHS = AndLHS.getOperand(0); 8457 RHS = AndLHS.getOperand(1); 8458 } 8459 8460 // Use BT if the immediate can't be encoded in a TEST instruction. 8461 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8462 LHS = AndLHS; 8463 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8464 } 8465 } 8466 8467 if (LHS.getNode()) { 8468 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8469 // instruction. Since the shift amount is in-range-or-undefined, we know 8470 // that doing a bittest on the i32 value is ok. We extend to i32 because 8471 // the encoding for the i16 version is larger than the i32 version. 8472 // Also promote i16 to i32 for performance / code size reason. 8473 if (LHS.getValueType() == MVT::i8 || 8474 LHS.getValueType() == MVT::i16) 8475 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8476 8477 // If the operand types disagree, extend the shift amount to match. Since 8478 // BT ignores high bits (like shifts) we can use anyextend. 8479 if (LHS.getValueType() != RHS.getValueType()) 8480 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8481 8482 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8483 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8484 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8485 DAG.getConstant(Cond, MVT::i8), BT); 8486 } 8487 8488 return SDValue(); 8489} 8490 8491SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8492 8493 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8494 8495 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8496 SDValue Op0 = Op.getOperand(0); 8497 SDValue Op1 = Op.getOperand(1); 8498 DebugLoc dl = Op.getDebugLoc(); 8499 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8500 8501 // Optimize to BT if possible. 8502 // Lower (X & (1 << N)) == 0 to BT(X, N). 8503 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8504 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8505 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8506 Op1.getOpcode() == ISD::Constant && 8507 cast<ConstantSDNode>(Op1)->isNullValue() && 8508 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8509 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8510 if (NewSetCC.getNode()) 8511 return NewSetCC; 8512 } 8513 8514 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8515 // these. 8516 if (Op1.getOpcode() == ISD::Constant && 8517 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8518 cast<ConstantSDNode>(Op1)->isNullValue()) && 8519 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8520 8521 // If the input is a setcc, then reuse the input setcc or use a new one with 8522 // the inverted condition. 8523 if (Op0.getOpcode() == X86ISD::SETCC) { 8524 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8525 bool Invert = (CC == ISD::SETNE) ^ 8526 cast<ConstantSDNode>(Op1)->isNullValue(); 8527 if (!Invert) return Op0; 8528 8529 CCode = X86::GetOppositeBranchCondition(CCode); 8530 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8531 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8532 } 8533 } 8534 8535 bool isFP = Op1.getValueType().isFloatingPoint(); 8536 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8537 if (X86CC == X86::COND_INVALID) 8538 return SDValue(); 8539 8540 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8541 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 8542 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8543 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8544} 8545 8546// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8547// ones, and then concatenate the result back. 8548static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8549 EVT VT = Op.getValueType(); 8550 8551 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8552 "Unsupported value type for operation"); 8553 8554 unsigned NumElems = VT.getVectorNumElements(); 8555 DebugLoc dl = Op.getDebugLoc(); 8556 SDValue CC = Op.getOperand(2); 8557 8558 // Extract the LHS vectors 8559 SDValue LHS = Op.getOperand(0); 8560 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 8561 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 8562 8563 // Extract the RHS vectors 8564 SDValue RHS = Op.getOperand(1); 8565 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 8566 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 8567 8568 // Issue the operation on the smaller types and concatenate the result back 8569 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8570 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8571 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8572 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8573 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8574} 8575 8576 8577SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8578 SDValue Cond; 8579 SDValue Op0 = Op.getOperand(0); 8580 SDValue Op1 = Op.getOperand(1); 8581 SDValue CC = Op.getOperand(2); 8582 EVT VT = Op.getValueType(); 8583 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8584 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8585 DebugLoc dl = Op.getDebugLoc(); 8586 8587 if (isFP) { 8588 unsigned SSECC = 8; 8589 EVT EltVT = Op0.getValueType().getVectorElementType(); 8590 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8591 8592 bool Swap = false; 8593 8594 // SSE Condition code mapping: 8595 // 0 - EQ 8596 // 1 - LT 8597 // 2 - LE 8598 // 3 - UNORD 8599 // 4 - NEQ 8600 // 5 - NLT 8601 // 6 - NLE 8602 // 7 - ORD 8603 switch (SetCCOpcode) { 8604 default: break; 8605 case ISD::SETOEQ: 8606 case ISD::SETEQ: SSECC = 0; break; 8607 case ISD::SETOGT: 8608 case ISD::SETGT: Swap = true; // Fallthrough 8609 case ISD::SETLT: 8610 case ISD::SETOLT: SSECC = 1; break; 8611 case ISD::SETOGE: 8612 case ISD::SETGE: Swap = true; // Fallthrough 8613 case ISD::SETLE: 8614 case ISD::SETOLE: SSECC = 2; break; 8615 case ISD::SETUO: SSECC = 3; break; 8616 case ISD::SETUNE: 8617 case ISD::SETNE: SSECC = 4; break; 8618 case ISD::SETULE: Swap = true; 8619 case ISD::SETUGE: SSECC = 5; break; 8620 case ISD::SETULT: Swap = true; 8621 case ISD::SETUGT: SSECC = 6; break; 8622 case ISD::SETO: SSECC = 7; break; 8623 } 8624 if (Swap) 8625 std::swap(Op0, Op1); 8626 8627 // In the two special cases we can't handle, emit two comparisons. 8628 if (SSECC == 8) { 8629 if (SetCCOpcode == ISD::SETUEQ) { 8630 SDValue UNORD, EQ; 8631 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8632 DAG.getConstant(3, MVT::i8)); 8633 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8634 DAG.getConstant(0, MVT::i8)); 8635 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8636 } 8637 if (SetCCOpcode == ISD::SETONE) { 8638 SDValue ORD, NEQ; 8639 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8640 DAG.getConstant(7, MVT::i8)); 8641 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8642 DAG.getConstant(4, MVT::i8)); 8643 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8644 } 8645 llvm_unreachable("Illegal FP comparison"); 8646 } 8647 // Handle all other FP comparisons here. 8648 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8649 DAG.getConstant(SSECC, MVT::i8)); 8650 } 8651 8652 // Break 256-bit integer vector compare into smaller ones. 8653 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8654 return Lower256IntVSETCC(Op, DAG); 8655 8656 // We are handling one of the integer comparisons here. Since SSE only has 8657 // GT and EQ comparisons for integer, swapping operands and multiple 8658 // operations may be required for some comparisons. 8659 unsigned Opc = 0; 8660 bool Swap = false, Invert = false, FlipSigns = false; 8661 8662 switch (SetCCOpcode) { 8663 default: break; 8664 case ISD::SETNE: Invert = true; 8665 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8666 case ISD::SETLT: Swap = true; 8667 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8668 case ISD::SETGE: Swap = true; 8669 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8670 case ISD::SETULT: Swap = true; 8671 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8672 case ISD::SETUGE: Swap = true; 8673 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8674 } 8675 if (Swap) 8676 std::swap(Op0, Op1); 8677 8678 // Check that the operation in question is available (most are plain SSE2, 8679 // but PCMPGTQ and PCMPEQQ have different requirements). 8680 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8681 return SDValue(); 8682 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8683 return SDValue(); 8684 8685 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8686 // bits of the inputs before performing those operations. 8687 if (FlipSigns) { 8688 EVT EltVT = VT.getVectorElementType(); 8689 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8690 EltVT); 8691 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8692 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8693 SignBits.size()); 8694 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8695 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8696 } 8697 8698 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8699 8700 // If the logical-not of the result is required, perform that now. 8701 if (Invert) 8702 Result = DAG.getNOT(dl, Result, VT); 8703 8704 return Result; 8705} 8706 8707// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8708static bool isX86LogicalCmp(SDValue Op) { 8709 unsigned Opc = Op.getNode()->getOpcode(); 8710 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 8711 Opc == X86ISD::SAHF) 8712 return true; 8713 if (Op.getResNo() == 1 && 8714 (Opc == X86ISD::ADD || 8715 Opc == X86ISD::SUB || 8716 Opc == X86ISD::ADC || 8717 Opc == X86ISD::SBB || 8718 Opc == X86ISD::SMUL || 8719 Opc == X86ISD::UMUL || 8720 Opc == X86ISD::INC || 8721 Opc == X86ISD::DEC || 8722 Opc == X86ISD::OR || 8723 Opc == X86ISD::XOR || 8724 Opc == X86ISD::AND)) 8725 return true; 8726 8727 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8728 return true; 8729 8730 return false; 8731} 8732 8733static bool isZero(SDValue V) { 8734 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8735 return C && C->isNullValue(); 8736} 8737 8738static bool isAllOnes(SDValue V) { 8739 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8740 return C && C->isAllOnesValue(); 8741} 8742 8743SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8744 bool addTest = true; 8745 SDValue Cond = Op.getOperand(0); 8746 SDValue Op1 = Op.getOperand(1); 8747 SDValue Op2 = Op.getOperand(2); 8748 DebugLoc DL = Op.getDebugLoc(); 8749 SDValue CC; 8750 8751 if (Cond.getOpcode() == ISD::SETCC) { 8752 SDValue NewCond = LowerSETCC(Cond, DAG); 8753 if (NewCond.getNode()) 8754 Cond = NewCond; 8755 } 8756 8757 // Handle the following cases related to max and min: 8758 // (a > b) ? (a-b) : 0 8759 // (a >= b) ? (a-b) : 0 8760 // (b < a) ? (a-b) : 0 8761 // (b <= a) ? (a-b) : 0 8762 // Comparison is removed to use EFLAGS from SUB. 8763 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2)) 8764 if (Cond.getOpcode() == X86ISD::SETCC && 8765 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8766 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) && 8767 C->getAPIntValue() == 0) { 8768 SDValue Cmp = Cond.getOperand(1); 8769 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8770 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) && 8771 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) && 8772 (CC == X86::COND_G || CC == X86::COND_GE || 8773 CC == X86::COND_A || CC == X86::COND_AE)) || 8774 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) && 8775 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) && 8776 (CC == X86::COND_L || CC == X86::COND_LE || 8777 CC == X86::COND_B || CC == X86::COND_BE))) { 8778 8779 if (Op1.getOpcode() == ISD::SUB) { 8780 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32); 8781 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs, 8782 Op1.getOperand(0), Op1.getOperand(1)); 8783 DAG.ReplaceAllUsesWith(Op1, New); 8784 Op1 = New; 8785 } 8786 8787 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8788 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE || 8789 CC == X86::COND_L || 8790 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE; 8791 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8), 8792 SDValue(Op1.getNode(), 1) }; 8793 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8794 } 8795 } 8796 8797 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8798 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8799 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8800 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8801 if (Cond.getOpcode() == X86ISD::SETCC && 8802 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8803 isZero(Cond.getOperand(1).getOperand(1))) { 8804 SDValue Cmp = Cond.getOperand(1); 8805 8806 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8807 8808 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8809 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8810 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8811 8812 SDValue CmpOp0 = Cmp.getOperand(0); 8813 // Apply further optimizations for special cases 8814 // (select (x != 0), -1, 0) -> neg & sbb 8815 // (select (x == 0), 0, -1) -> neg & sbb 8816 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 8817 if (YC->isNullValue() && 8818 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 8819 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 8820 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs, 8821 DAG.getConstant(0, CmpOp0.getValueType()), 8822 CmpOp0); 8823 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8824 DAG.getConstant(X86::COND_B, MVT::i8), 8825 SDValue(Neg.getNode(), 1)); 8826 return Res; 8827 } 8828 8829 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8830 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8831 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 8832 8833 SDValue Res = // Res = 0 or -1. 8834 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8835 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8836 8837 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8838 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8839 8840 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8841 if (N2C == 0 || !N2C->isNullValue()) 8842 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8843 return Res; 8844 } 8845 } 8846 8847 // Look past (and (setcc_carry (cmp ...)), 1). 8848 if (Cond.getOpcode() == ISD::AND && 8849 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8850 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8851 if (C && C->getAPIntValue() == 1) 8852 Cond = Cond.getOperand(0); 8853 } 8854 8855 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8856 // setting operand in place of the X86ISD::SETCC. 8857 unsigned CondOpcode = Cond.getOpcode(); 8858 if (CondOpcode == X86ISD::SETCC || 8859 CondOpcode == X86ISD::SETCC_CARRY) { 8860 CC = Cond.getOperand(0); 8861 8862 SDValue Cmp = Cond.getOperand(1); 8863 unsigned Opc = Cmp.getOpcode(); 8864 EVT VT = Op.getValueType(); 8865 8866 bool IllegalFPCMov = false; 8867 if (VT.isFloatingPoint() && !VT.isVector() && 8868 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8869 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8870 8871 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8872 Opc == X86ISD::BT) { // FIXME 8873 Cond = Cmp; 8874 addTest = false; 8875 } 8876 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8877 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8878 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8879 Cond.getOperand(0).getValueType() != MVT::i8)) { 8880 SDValue LHS = Cond.getOperand(0); 8881 SDValue RHS = Cond.getOperand(1); 8882 unsigned X86Opcode; 8883 unsigned X86Cond; 8884 SDVTList VTs; 8885 switch (CondOpcode) { 8886 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8887 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8888 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8889 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8890 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8891 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8892 default: llvm_unreachable("unexpected overflowing operator"); 8893 } 8894 if (CondOpcode == ISD::UMULO) 8895 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8896 MVT::i32); 8897 else 8898 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8899 8900 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8901 8902 if (CondOpcode == ISD::UMULO) 8903 Cond = X86Op.getValue(2); 8904 else 8905 Cond = X86Op.getValue(1); 8906 8907 CC = DAG.getConstant(X86Cond, MVT::i8); 8908 addTest = false; 8909 } 8910 8911 if (addTest) { 8912 // Look pass the truncate. 8913 if (Cond.getOpcode() == ISD::TRUNCATE) 8914 Cond = Cond.getOperand(0); 8915 8916 // We know the result of AND is compared against zero. Try to match 8917 // it to BT. 8918 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8919 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8920 if (NewSetCC.getNode()) { 8921 CC = NewSetCC.getOperand(0); 8922 Cond = NewSetCC.getOperand(1); 8923 addTest = false; 8924 } 8925 } 8926 } 8927 8928 if (addTest) { 8929 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8930 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8931 } 8932 8933 // a < b ? -1 : 0 -> RES = ~setcc_carry 8934 // a < b ? 0 : -1 -> RES = setcc_carry 8935 // a >= b ? -1 : 0 -> RES = setcc_carry 8936 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8937 if (Cond.getOpcode() == X86ISD::CMP) { 8938 Cond = ConvertCmpIfNecessary(Cond, DAG); 8939 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8940 8941 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8942 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8943 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8944 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8945 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8946 return DAG.getNOT(DL, Res, Res.getValueType()); 8947 return Res; 8948 } 8949 } 8950 8951 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8952 // condition is true. 8953 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8954 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8955 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8956} 8957 8958// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8959// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8960// from the AND / OR. 8961static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8962 Opc = Op.getOpcode(); 8963 if (Opc != ISD::OR && Opc != ISD::AND) 8964 return false; 8965 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8966 Op.getOperand(0).hasOneUse() && 8967 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8968 Op.getOperand(1).hasOneUse()); 8969} 8970 8971// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8972// 1 and that the SETCC node has a single use. 8973static bool isXor1OfSetCC(SDValue Op) { 8974 if (Op.getOpcode() != ISD::XOR) 8975 return false; 8976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8977 if (N1C && N1C->getAPIntValue() == 1) { 8978 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8979 Op.getOperand(0).hasOneUse(); 8980 } 8981 return false; 8982} 8983 8984SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8985 bool addTest = true; 8986 SDValue Chain = Op.getOperand(0); 8987 SDValue Cond = Op.getOperand(1); 8988 SDValue Dest = Op.getOperand(2); 8989 DebugLoc dl = Op.getDebugLoc(); 8990 SDValue CC; 8991 bool Inverted = false; 8992 8993 if (Cond.getOpcode() == ISD::SETCC) { 8994 // Check for setcc([su]{add,sub,mul}o == 0). 8995 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8996 isa<ConstantSDNode>(Cond.getOperand(1)) && 8997 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8998 Cond.getOperand(0).getResNo() == 1 && 8999 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 9000 Cond.getOperand(0).getOpcode() == ISD::UADDO || 9001 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 9002 Cond.getOperand(0).getOpcode() == ISD::USUBO || 9003 Cond.getOperand(0).getOpcode() == ISD::SMULO || 9004 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 9005 Inverted = true; 9006 Cond = Cond.getOperand(0); 9007 } else { 9008 SDValue NewCond = LowerSETCC(Cond, DAG); 9009 if (NewCond.getNode()) 9010 Cond = NewCond; 9011 } 9012 } 9013#if 0 9014 // FIXME: LowerXALUO doesn't handle these!! 9015 else if (Cond.getOpcode() == X86ISD::ADD || 9016 Cond.getOpcode() == X86ISD::SUB || 9017 Cond.getOpcode() == X86ISD::SMUL || 9018 Cond.getOpcode() == X86ISD::UMUL) 9019 Cond = LowerXALUO(Cond, DAG); 9020#endif 9021 9022 // Look pass (and (setcc_carry (cmp ...)), 1). 9023 if (Cond.getOpcode() == ISD::AND && 9024 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 9025 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 9026 if (C && C->getAPIntValue() == 1) 9027 Cond = Cond.getOperand(0); 9028 } 9029 9030 // If condition flag is set by a X86ISD::CMP, then use it as the condition 9031 // setting operand in place of the X86ISD::SETCC. 9032 unsigned CondOpcode = Cond.getOpcode(); 9033 if (CondOpcode == X86ISD::SETCC || 9034 CondOpcode == X86ISD::SETCC_CARRY) { 9035 CC = Cond.getOperand(0); 9036 9037 SDValue Cmp = Cond.getOperand(1); 9038 unsigned Opc = Cmp.getOpcode(); 9039 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 9040 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 9041 Cond = Cmp; 9042 addTest = false; 9043 } else { 9044 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 9045 default: break; 9046 case X86::COND_O: 9047 case X86::COND_B: 9048 // These can only come from an arithmetic instruction with overflow, 9049 // e.g. SADDO, UADDO. 9050 Cond = Cond.getNode()->getOperand(1); 9051 addTest = false; 9052 break; 9053 } 9054 } 9055 } 9056 CondOpcode = Cond.getOpcode(); 9057 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 9058 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 9059 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 9060 Cond.getOperand(0).getValueType() != MVT::i8)) { 9061 SDValue LHS = Cond.getOperand(0); 9062 SDValue RHS = Cond.getOperand(1); 9063 unsigned X86Opcode; 9064 unsigned X86Cond; 9065 SDVTList VTs; 9066 switch (CondOpcode) { 9067 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 9068 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 9069 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 9070 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 9071 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 9072 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 9073 default: llvm_unreachable("unexpected overflowing operator"); 9074 } 9075 if (Inverted) 9076 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 9077 if (CondOpcode == ISD::UMULO) 9078 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 9079 MVT::i32); 9080 else 9081 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 9082 9083 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 9084 9085 if (CondOpcode == ISD::UMULO) 9086 Cond = X86Op.getValue(2); 9087 else 9088 Cond = X86Op.getValue(1); 9089 9090 CC = DAG.getConstant(X86Cond, MVT::i8); 9091 addTest = false; 9092 } else { 9093 unsigned CondOpc; 9094 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 9095 SDValue Cmp = Cond.getOperand(0).getOperand(1); 9096 if (CondOpc == ISD::OR) { 9097 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 9098 // two branches instead of an explicit OR instruction with a 9099 // separate test. 9100 if (Cmp == Cond.getOperand(1).getOperand(1) && 9101 isX86LogicalCmp(Cmp)) { 9102 CC = Cond.getOperand(0).getOperand(0); 9103 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9104 Chain, Dest, CC, Cmp); 9105 CC = Cond.getOperand(1).getOperand(0); 9106 Cond = Cmp; 9107 addTest = false; 9108 } 9109 } else { // ISD::AND 9110 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 9111 // two branches instead of an explicit AND instruction with a 9112 // separate test. However, we only do this if this block doesn't 9113 // have a fall-through edge, because this requires an explicit 9114 // jmp when the condition is false. 9115 if (Cmp == Cond.getOperand(1).getOperand(1) && 9116 isX86LogicalCmp(Cmp) && 9117 Op.getNode()->hasOneUse()) { 9118 X86::CondCode CCode = 9119 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9120 CCode = X86::GetOppositeBranchCondition(CCode); 9121 CC = DAG.getConstant(CCode, MVT::i8); 9122 SDNode *User = *Op.getNode()->use_begin(); 9123 // Look for an unconditional branch following this conditional branch. 9124 // We need this because we need to reverse the successors in order 9125 // to implement FCMP_OEQ. 9126 if (User->getOpcode() == ISD::BR) { 9127 SDValue FalseBB = User->getOperand(1); 9128 SDNode *NewBR = 9129 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9130 assert(NewBR == User); 9131 (void)NewBR; 9132 Dest = FalseBB; 9133 9134 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9135 Chain, Dest, CC, Cmp); 9136 X86::CondCode CCode = 9137 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9138 CCode = X86::GetOppositeBranchCondition(CCode); 9139 CC = DAG.getConstant(CCode, MVT::i8); 9140 Cond = Cmp; 9141 addTest = false; 9142 } 9143 } 9144 } 9145 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9146 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9147 // It should be transformed during dag combiner except when the condition 9148 // is set by a arithmetics with overflow node. 9149 X86::CondCode CCode = 9150 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9151 CCode = X86::GetOppositeBranchCondition(CCode); 9152 CC = DAG.getConstant(CCode, MVT::i8); 9153 Cond = Cond.getOperand(0).getOperand(1); 9154 addTest = false; 9155 } else if (Cond.getOpcode() == ISD::SETCC && 9156 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9157 // For FCMP_OEQ, we can emit 9158 // two branches instead of an explicit AND instruction with a 9159 // separate test. However, we only do this if this block doesn't 9160 // have a fall-through edge, because this requires an explicit 9161 // jmp when the condition is false. 9162 if (Op.getNode()->hasOneUse()) { 9163 SDNode *User = *Op.getNode()->use_begin(); 9164 // Look for an unconditional branch following this conditional branch. 9165 // We need this because we need to reverse the successors in order 9166 // to implement FCMP_OEQ. 9167 if (User->getOpcode() == ISD::BR) { 9168 SDValue FalseBB = User->getOperand(1); 9169 SDNode *NewBR = 9170 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9171 assert(NewBR == User); 9172 (void)NewBR; 9173 Dest = FalseBB; 9174 9175 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9176 Cond.getOperand(0), Cond.getOperand(1)); 9177 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9178 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9179 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9180 Chain, Dest, CC, Cmp); 9181 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9182 Cond = Cmp; 9183 addTest = false; 9184 } 9185 } 9186 } else if (Cond.getOpcode() == ISD::SETCC && 9187 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9188 // For FCMP_UNE, we can emit 9189 // two branches instead of an explicit AND instruction with a 9190 // separate test. However, we only do this if this block doesn't 9191 // have a fall-through edge, because this requires an explicit 9192 // jmp when the condition is false. 9193 if (Op.getNode()->hasOneUse()) { 9194 SDNode *User = *Op.getNode()->use_begin(); 9195 // Look for an unconditional branch following this conditional branch. 9196 // We need this because we need to reverse the successors in order 9197 // to implement FCMP_UNE. 9198 if (User->getOpcode() == ISD::BR) { 9199 SDValue FalseBB = User->getOperand(1); 9200 SDNode *NewBR = 9201 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9202 assert(NewBR == User); 9203 (void)NewBR; 9204 9205 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9206 Cond.getOperand(0), Cond.getOperand(1)); 9207 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9208 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9209 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9210 Chain, Dest, CC, Cmp); 9211 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9212 Cond = Cmp; 9213 addTest = false; 9214 Dest = FalseBB; 9215 } 9216 } 9217 } 9218 } 9219 9220 if (addTest) { 9221 // Look pass the truncate. 9222 if (Cond.getOpcode() == ISD::TRUNCATE) 9223 Cond = Cond.getOperand(0); 9224 9225 // We know the result of AND is compared against zero. Try to match 9226 // it to BT. 9227 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9228 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9229 if (NewSetCC.getNode()) { 9230 CC = NewSetCC.getOperand(0); 9231 Cond = NewSetCC.getOperand(1); 9232 addTest = false; 9233 } 9234 } 9235 } 9236 9237 if (addTest) { 9238 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9239 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9240 } 9241 Cond = ConvertCmpIfNecessary(Cond, DAG); 9242 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9243 Chain, Dest, CC, Cond); 9244} 9245 9246 9247// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9248// Calls to _alloca is needed to probe the stack when allocating more than 4k 9249// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9250// that the guard pages used by the OS virtual memory manager are allocated in 9251// correct sequence. 9252SDValue 9253X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9254 SelectionDAG &DAG) const { 9255 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9256 getTargetMachine().Options.EnableSegmentedStacks) && 9257 "This should be used only on Windows targets or when segmented stacks " 9258 "are being used"); 9259 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9260 DebugLoc dl = Op.getDebugLoc(); 9261 9262 // Get the inputs. 9263 SDValue Chain = Op.getOperand(0); 9264 SDValue Size = Op.getOperand(1); 9265 // FIXME: Ensure alignment here 9266 9267 bool Is64Bit = Subtarget->is64Bit(); 9268 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9269 9270 if (getTargetMachine().Options.EnableSegmentedStacks) { 9271 MachineFunction &MF = DAG.getMachineFunction(); 9272 MachineRegisterInfo &MRI = MF.getRegInfo(); 9273 9274 if (Is64Bit) { 9275 // The 64 bit implementation of segmented stacks needs to clobber both r10 9276 // r11. This makes it impossible to use it along with nested parameters. 9277 const Function *F = MF.getFunction(); 9278 9279 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9280 I != E; ++I) 9281 if (I->hasNestAttr()) 9282 report_fatal_error("Cannot use segmented stacks with functions that " 9283 "have nested arguments."); 9284 } 9285 9286 const TargetRegisterClass *AddrRegClass = 9287 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9288 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9289 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9290 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9291 DAG.getRegister(Vreg, SPTy)); 9292 SDValue Ops1[2] = { Value, Chain }; 9293 return DAG.getMergeValues(Ops1, 2, dl); 9294 } else { 9295 SDValue Flag; 9296 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9297 9298 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9299 Flag = Chain.getValue(1); 9300 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9301 9302 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9303 Flag = Chain.getValue(1); 9304 9305 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9306 9307 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9308 return DAG.getMergeValues(Ops1, 2, dl); 9309 } 9310} 9311 9312SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9313 MachineFunction &MF = DAG.getMachineFunction(); 9314 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9315 9316 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9317 DebugLoc DL = Op.getDebugLoc(); 9318 9319 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9320 // vastart just stores the address of the VarArgsFrameIndex slot into the 9321 // memory location argument. 9322 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9323 getPointerTy()); 9324 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9325 MachinePointerInfo(SV), false, false, 0); 9326 } 9327 9328 // __va_list_tag: 9329 // gp_offset (0 - 6 * 8) 9330 // fp_offset (48 - 48 + 8 * 16) 9331 // overflow_arg_area (point to parameters coming in memory). 9332 // reg_save_area 9333 SmallVector<SDValue, 8> MemOps; 9334 SDValue FIN = Op.getOperand(1); 9335 // Store gp_offset 9336 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9337 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9338 MVT::i32), 9339 FIN, MachinePointerInfo(SV), false, false, 0); 9340 MemOps.push_back(Store); 9341 9342 // Store fp_offset 9343 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9344 FIN, DAG.getIntPtrConstant(4)); 9345 Store = DAG.getStore(Op.getOperand(0), DL, 9346 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9347 MVT::i32), 9348 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9349 MemOps.push_back(Store); 9350 9351 // Store ptr to overflow_arg_area 9352 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9353 FIN, DAG.getIntPtrConstant(4)); 9354 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9355 getPointerTy()); 9356 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9357 MachinePointerInfo(SV, 8), 9358 false, false, 0); 9359 MemOps.push_back(Store); 9360 9361 // Store ptr to reg_save_area. 9362 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9363 FIN, DAG.getIntPtrConstant(8)); 9364 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9365 getPointerTy()); 9366 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9367 MachinePointerInfo(SV, 16), false, false, 0); 9368 MemOps.push_back(Store); 9369 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9370 &MemOps[0], MemOps.size()); 9371} 9372 9373SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9374 assert(Subtarget->is64Bit() && 9375 "LowerVAARG only handles 64-bit va_arg!"); 9376 assert((Subtarget->isTargetLinux() || 9377 Subtarget->isTargetDarwin()) && 9378 "Unhandled target in LowerVAARG"); 9379 assert(Op.getNode()->getNumOperands() == 4); 9380 SDValue Chain = Op.getOperand(0); 9381 SDValue SrcPtr = Op.getOperand(1); 9382 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9383 unsigned Align = Op.getConstantOperandVal(3); 9384 DebugLoc dl = Op.getDebugLoc(); 9385 9386 EVT ArgVT = Op.getNode()->getValueType(0); 9387 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9388 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9389 uint8_t ArgMode; 9390 9391 // Decide which area this value should be read from. 9392 // TODO: Implement the AMD64 ABI in its entirety. This simple 9393 // selection mechanism works only for the basic types. 9394 if (ArgVT == MVT::f80) { 9395 llvm_unreachable("va_arg for f80 not yet implemented"); 9396 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9397 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9398 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9399 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9400 } else { 9401 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9402 } 9403 9404 if (ArgMode == 2) { 9405 // Sanity Check: Make sure using fp_offset makes sense. 9406 assert(!getTargetMachine().Options.UseSoftFloat && 9407 !(DAG.getMachineFunction() 9408 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9409 Subtarget->hasSSE1()); 9410 } 9411 9412 // Insert VAARG_64 node into the DAG 9413 // VAARG_64 returns two values: Variable Argument Address, Chain 9414 SmallVector<SDValue, 11> InstOps; 9415 InstOps.push_back(Chain); 9416 InstOps.push_back(SrcPtr); 9417 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9418 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9419 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9420 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9421 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9422 VTs, &InstOps[0], InstOps.size(), 9423 MVT::i64, 9424 MachinePointerInfo(SV), 9425 /*Align=*/0, 9426 /*Volatile=*/false, 9427 /*ReadMem=*/true, 9428 /*WriteMem=*/true); 9429 Chain = VAARG.getValue(1); 9430 9431 // Load the next argument and return it 9432 return DAG.getLoad(ArgVT, dl, 9433 Chain, 9434 VAARG, 9435 MachinePointerInfo(), 9436 false, false, false, 0); 9437} 9438 9439SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9440 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9441 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9442 SDValue Chain = Op.getOperand(0); 9443 SDValue DstPtr = Op.getOperand(1); 9444 SDValue SrcPtr = Op.getOperand(2); 9445 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9446 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9447 DebugLoc DL = Op.getDebugLoc(); 9448 9449 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9450 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9451 false, 9452 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9453} 9454 9455// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9456// may or may not be a constant. Takes immediate version of shift as input. 9457static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9458 SDValue SrcOp, SDValue ShAmt, 9459 SelectionDAG &DAG) { 9460 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9461 9462 if (isa<ConstantSDNode>(ShAmt)) { 9463 // Constant may be a TargetConstant. Use a regular constant. 9464 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 9465 switch (Opc) { 9466 default: llvm_unreachable("Unknown target vector shift node"); 9467 case X86ISD::VSHLI: 9468 case X86ISD::VSRLI: 9469 case X86ISD::VSRAI: 9470 return DAG.getNode(Opc, dl, VT, SrcOp, 9471 DAG.getConstant(ShiftAmt, MVT::i32)); 9472 } 9473 } 9474 9475 // Change opcode to non-immediate version 9476 switch (Opc) { 9477 default: llvm_unreachable("Unknown target vector shift node"); 9478 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9479 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9480 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9481 } 9482 9483 // Need to build a vector containing shift amount 9484 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9485 SDValue ShOps[4]; 9486 ShOps[0] = ShAmt; 9487 ShOps[1] = DAG.getConstant(0, MVT::i32); 9488 ShOps[2] = DAG.getUNDEF(MVT::i32); 9489 ShOps[3] = DAG.getUNDEF(MVT::i32); 9490 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9491 9492 // The return type has to be a 128-bit type with the same element 9493 // type as the input type. 9494 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9495 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); 9496 9497 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt); 9498 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9499} 9500 9501SDValue 9502X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9503 DebugLoc dl = Op.getDebugLoc(); 9504 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9505 switch (IntNo) { 9506 default: return SDValue(); // Don't custom lower most intrinsics. 9507 // Comparison intrinsics. 9508 case Intrinsic::x86_sse_comieq_ss: 9509 case Intrinsic::x86_sse_comilt_ss: 9510 case Intrinsic::x86_sse_comile_ss: 9511 case Intrinsic::x86_sse_comigt_ss: 9512 case Intrinsic::x86_sse_comige_ss: 9513 case Intrinsic::x86_sse_comineq_ss: 9514 case Intrinsic::x86_sse_ucomieq_ss: 9515 case Intrinsic::x86_sse_ucomilt_ss: 9516 case Intrinsic::x86_sse_ucomile_ss: 9517 case Intrinsic::x86_sse_ucomigt_ss: 9518 case Intrinsic::x86_sse_ucomige_ss: 9519 case Intrinsic::x86_sse_ucomineq_ss: 9520 case Intrinsic::x86_sse2_comieq_sd: 9521 case Intrinsic::x86_sse2_comilt_sd: 9522 case Intrinsic::x86_sse2_comile_sd: 9523 case Intrinsic::x86_sse2_comigt_sd: 9524 case Intrinsic::x86_sse2_comige_sd: 9525 case Intrinsic::x86_sse2_comineq_sd: 9526 case Intrinsic::x86_sse2_ucomieq_sd: 9527 case Intrinsic::x86_sse2_ucomilt_sd: 9528 case Intrinsic::x86_sse2_ucomile_sd: 9529 case Intrinsic::x86_sse2_ucomigt_sd: 9530 case Intrinsic::x86_sse2_ucomige_sd: 9531 case Intrinsic::x86_sse2_ucomineq_sd: { 9532 unsigned Opc = 0; 9533 ISD::CondCode CC = ISD::SETCC_INVALID; 9534 switch (IntNo) { 9535 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9536 case Intrinsic::x86_sse_comieq_ss: 9537 case Intrinsic::x86_sse2_comieq_sd: 9538 Opc = X86ISD::COMI; 9539 CC = ISD::SETEQ; 9540 break; 9541 case Intrinsic::x86_sse_comilt_ss: 9542 case Intrinsic::x86_sse2_comilt_sd: 9543 Opc = X86ISD::COMI; 9544 CC = ISD::SETLT; 9545 break; 9546 case Intrinsic::x86_sse_comile_ss: 9547 case Intrinsic::x86_sse2_comile_sd: 9548 Opc = X86ISD::COMI; 9549 CC = ISD::SETLE; 9550 break; 9551 case Intrinsic::x86_sse_comigt_ss: 9552 case Intrinsic::x86_sse2_comigt_sd: 9553 Opc = X86ISD::COMI; 9554 CC = ISD::SETGT; 9555 break; 9556 case Intrinsic::x86_sse_comige_ss: 9557 case Intrinsic::x86_sse2_comige_sd: 9558 Opc = X86ISD::COMI; 9559 CC = ISD::SETGE; 9560 break; 9561 case Intrinsic::x86_sse_comineq_ss: 9562 case Intrinsic::x86_sse2_comineq_sd: 9563 Opc = X86ISD::COMI; 9564 CC = ISD::SETNE; 9565 break; 9566 case Intrinsic::x86_sse_ucomieq_ss: 9567 case Intrinsic::x86_sse2_ucomieq_sd: 9568 Opc = X86ISD::UCOMI; 9569 CC = ISD::SETEQ; 9570 break; 9571 case Intrinsic::x86_sse_ucomilt_ss: 9572 case Intrinsic::x86_sse2_ucomilt_sd: 9573 Opc = X86ISD::UCOMI; 9574 CC = ISD::SETLT; 9575 break; 9576 case Intrinsic::x86_sse_ucomile_ss: 9577 case Intrinsic::x86_sse2_ucomile_sd: 9578 Opc = X86ISD::UCOMI; 9579 CC = ISD::SETLE; 9580 break; 9581 case Intrinsic::x86_sse_ucomigt_ss: 9582 case Intrinsic::x86_sse2_ucomigt_sd: 9583 Opc = X86ISD::UCOMI; 9584 CC = ISD::SETGT; 9585 break; 9586 case Intrinsic::x86_sse_ucomige_ss: 9587 case Intrinsic::x86_sse2_ucomige_sd: 9588 Opc = X86ISD::UCOMI; 9589 CC = ISD::SETGE; 9590 break; 9591 case Intrinsic::x86_sse_ucomineq_ss: 9592 case Intrinsic::x86_sse2_ucomineq_sd: 9593 Opc = X86ISD::UCOMI; 9594 CC = ISD::SETNE; 9595 break; 9596 } 9597 9598 SDValue LHS = Op.getOperand(1); 9599 SDValue RHS = Op.getOperand(2); 9600 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9601 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9602 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9603 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9604 DAG.getConstant(X86CC, MVT::i8), Cond); 9605 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9606 } 9607 // Arithmetic intrinsics. 9608 case Intrinsic::x86_sse2_pmulu_dq: 9609 case Intrinsic::x86_avx2_pmulu_dq: 9610 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9611 Op.getOperand(1), Op.getOperand(2)); 9612 case Intrinsic::x86_sse3_hadd_ps: 9613 case Intrinsic::x86_sse3_hadd_pd: 9614 case Intrinsic::x86_avx_hadd_ps_256: 9615 case Intrinsic::x86_avx_hadd_pd_256: 9616 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9617 Op.getOperand(1), Op.getOperand(2)); 9618 case Intrinsic::x86_sse3_hsub_ps: 9619 case Intrinsic::x86_sse3_hsub_pd: 9620 case Intrinsic::x86_avx_hsub_ps_256: 9621 case Intrinsic::x86_avx_hsub_pd_256: 9622 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9623 Op.getOperand(1), Op.getOperand(2)); 9624 case Intrinsic::x86_ssse3_phadd_w_128: 9625 case Intrinsic::x86_ssse3_phadd_d_128: 9626 case Intrinsic::x86_avx2_phadd_w: 9627 case Intrinsic::x86_avx2_phadd_d: 9628 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9629 Op.getOperand(1), Op.getOperand(2)); 9630 case Intrinsic::x86_ssse3_phsub_w_128: 9631 case Intrinsic::x86_ssse3_phsub_d_128: 9632 case Intrinsic::x86_avx2_phsub_w: 9633 case Intrinsic::x86_avx2_phsub_d: 9634 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9635 Op.getOperand(1), Op.getOperand(2)); 9636 case Intrinsic::x86_avx2_psllv_d: 9637 case Intrinsic::x86_avx2_psllv_q: 9638 case Intrinsic::x86_avx2_psllv_d_256: 9639 case Intrinsic::x86_avx2_psllv_q_256: 9640 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9641 Op.getOperand(1), Op.getOperand(2)); 9642 case Intrinsic::x86_avx2_psrlv_d: 9643 case Intrinsic::x86_avx2_psrlv_q: 9644 case Intrinsic::x86_avx2_psrlv_d_256: 9645 case Intrinsic::x86_avx2_psrlv_q_256: 9646 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9647 Op.getOperand(1), Op.getOperand(2)); 9648 case Intrinsic::x86_avx2_psrav_d: 9649 case Intrinsic::x86_avx2_psrav_d_256: 9650 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9651 Op.getOperand(1), Op.getOperand(2)); 9652 case Intrinsic::x86_ssse3_pshuf_b_128: 9653 case Intrinsic::x86_avx2_pshuf_b: 9654 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9655 Op.getOperand(1), Op.getOperand(2)); 9656 case Intrinsic::x86_ssse3_psign_b_128: 9657 case Intrinsic::x86_ssse3_psign_w_128: 9658 case Intrinsic::x86_ssse3_psign_d_128: 9659 case Intrinsic::x86_avx2_psign_b: 9660 case Intrinsic::x86_avx2_psign_w: 9661 case Intrinsic::x86_avx2_psign_d: 9662 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9663 Op.getOperand(1), Op.getOperand(2)); 9664 case Intrinsic::x86_sse41_insertps: 9665 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9666 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9667 case Intrinsic::x86_avx_vperm2f128_ps_256: 9668 case Intrinsic::x86_avx_vperm2f128_pd_256: 9669 case Intrinsic::x86_avx_vperm2f128_si_256: 9670 case Intrinsic::x86_avx2_vperm2i128: 9671 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9672 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9673 case Intrinsic::x86_avx2_permd: 9674 case Intrinsic::x86_avx2_permps: 9675 // Operands intentionally swapped. Mask is last operand to intrinsic, 9676 // but second operand for node/intruction. 9677 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 9678 Op.getOperand(2), Op.getOperand(1)); 9679 9680 // ptest and testp intrinsics. The intrinsic these come from are designed to 9681 // return an integer value, not just an instruction so lower it to the ptest 9682 // or testp pattern and a setcc for the result. 9683 case Intrinsic::x86_sse41_ptestz: 9684 case Intrinsic::x86_sse41_ptestc: 9685 case Intrinsic::x86_sse41_ptestnzc: 9686 case Intrinsic::x86_avx_ptestz_256: 9687 case Intrinsic::x86_avx_ptestc_256: 9688 case Intrinsic::x86_avx_ptestnzc_256: 9689 case Intrinsic::x86_avx_vtestz_ps: 9690 case Intrinsic::x86_avx_vtestc_ps: 9691 case Intrinsic::x86_avx_vtestnzc_ps: 9692 case Intrinsic::x86_avx_vtestz_pd: 9693 case Intrinsic::x86_avx_vtestc_pd: 9694 case Intrinsic::x86_avx_vtestnzc_pd: 9695 case Intrinsic::x86_avx_vtestz_ps_256: 9696 case Intrinsic::x86_avx_vtestc_ps_256: 9697 case Intrinsic::x86_avx_vtestnzc_ps_256: 9698 case Intrinsic::x86_avx_vtestz_pd_256: 9699 case Intrinsic::x86_avx_vtestc_pd_256: 9700 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9701 bool IsTestPacked = false; 9702 unsigned X86CC = 0; 9703 switch (IntNo) { 9704 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9705 case Intrinsic::x86_avx_vtestz_ps: 9706 case Intrinsic::x86_avx_vtestz_pd: 9707 case Intrinsic::x86_avx_vtestz_ps_256: 9708 case Intrinsic::x86_avx_vtestz_pd_256: 9709 IsTestPacked = true; // Fallthrough 9710 case Intrinsic::x86_sse41_ptestz: 9711 case Intrinsic::x86_avx_ptestz_256: 9712 // ZF = 1 9713 X86CC = X86::COND_E; 9714 break; 9715 case Intrinsic::x86_avx_vtestc_ps: 9716 case Intrinsic::x86_avx_vtestc_pd: 9717 case Intrinsic::x86_avx_vtestc_ps_256: 9718 case Intrinsic::x86_avx_vtestc_pd_256: 9719 IsTestPacked = true; // Fallthrough 9720 case Intrinsic::x86_sse41_ptestc: 9721 case Intrinsic::x86_avx_ptestc_256: 9722 // CF = 1 9723 X86CC = X86::COND_B; 9724 break; 9725 case Intrinsic::x86_avx_vtestnzc_ps: 9726 case Intrinsic::x86_avx_vtestnzc_pd: 9727 case Intrinsic::x86_avx_vtestnzc_ps_256: 9728 case Intrinsic::x86_avx_vtestnzc_pd_256: 9729 IsTestPacked = true; // Fallthrough 9730 case Intrinsic::x86_sse41_ptestnzc: 9731 case Intrinsic::x86_avx_ptestnzc_256: 9732 // ZF and CF = 0 9733 X86CC = X86::COND_A; 9734 break; 9735 } 9736 9737 SDValue LHS = Op.getOperand(1); 9738 SDValue RHS = Op.getOperand(2); 9739 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9740 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9741 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9742 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9743 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9744 } 9745 9746 // SSE/AVX shift intrinsics 9747 case Intrinsic::x86_sse2_psll_w: 9748 case Intrinsic::x86_sse2_psll_d: 9749 case Intrinsic::x86_sse2_psll_q: 9750 case Intrinsic::x86_avx2_psll_w: 9751 case Intrinsic::x86_avx2_psll_d: 9752 case Intrinsic::x86_avx2_psll_q: 9753 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9754 Op.getOperand(1), Op.getOperand(2)); 9755 case Intrinsic::x86_sse2_psrl_w: 9756 case Intrinsic::x86_sse2_psrl_d: 9757 case Intrinsic::x86_sse2_psrl_q: 9758 case Intrinsic::x86_avx2_psrl_w: 9759 case Intrinsic::x86_avx2_psrl_d: 9760 case Intrinsic::x86_avx2_psrl_q: 9761 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9762 Op.getOperand(1), Op.getOperand(2)); 9763 case Intrinsic::x86_sse2_psra_w: 9764 case Intrinsic::x86_sse2_psra_d: 9765 case Intrinsic::x86_avx2_psra_w: 9766 case Intrinsic::x86_avx2_psra_d: 9767 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9768 Op.getOperand(1), Op.getOperand(2)); 9769 case Intrinsic::x86_sse2_pslli_w: 9770 case Intrinsic::x86_sse2_pslli_d: 9771 case Intrinsic::x86_sse2_pslli_q: 9772 case Intrinsic::x86_avx2_pslli_w: 9773 case Intrinsic::x86_avx2_pslli_d: 9774 case Intrinsic::x86_avx2_pslli_q: 9775 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9776 Op.getOperand(1), Op.getOperand(2), DAG); 9777 case Intrinsic::x86_sse2_psrli_w: 9778 case Intrinsic::x86_sse2_psrli_d: 9779 case Intrinsic::x86_sse2_psrli_q: 9780 case Intrinsic::x86_avx2_psrli_w: 9781 case Intrinsic::x86_avx2_psrli_d: 9782 case Intrinsic::x86_avx2_psrli_q: 9783 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9784 Op.getOperand(1), Op.getOperand(2), DAG); 9785 case Intrinsic::x86_sse2_psrai_w: 9786 case Intrinsic::x86_sse2_psrai_d: 9787 case Intrinsic::x86_avx2_psrai_w: 9788 case Intrinsic::x86_avx2_psrai_d: 9789 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9790 Op.getOperand(1), Op.getOperand(2), DAG); 9791 // Fix vector shift instructions where the last operand is a non-immediate 9792 // i32 value. 9793 case Intrinsic::x86_mmx_pslli_w: 9794 case Intrinsic::x86_mmx_pslli_d: 9795 case Intrinsic::x86_mmx_pslli_q: 9796 case Intrinsic::x86_mmx_psrli_w: 9797 case Intrinsic::x86_mmx_psrli_d: 9798 case Intrinsic::x86_mmx_psrli_q: 9799 case Intrinsic::x86_mmx_psrai_w: 9800 case Intrinsic::x86_mmx_psrai_d: { 9801 SDValue ShAmt = Op.getOperand(2); 9802 if (isa<ConstantSDNode>(ShAmt)) 9803 return SDValue(); 9804 9805 unsigned NewIntNo = 0; 9806 switch (IntNo) { 9807 case Intrinsic::x86_mmx_pslli_w: 9808 NewIntNo = Intrinsic::x86_mmx_psll_w; 9809 break; 9810 case Intrinsic::x86_mmx_pslli_d: 9811 NewIntNo = Intrinsic::x86_mmx_psll_d; 9812 break; 9813 case Intrinsic::x86_mmx_pslli_q: 9814 NewIntNo = Intrinsic::x86_mmx_psll_q; 9815 break; 9816 case Intrinsic::x86_mmx_psrli_w: 9817 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9818 break; 9819 case Intrinsic::x86_mmx_psrli_d: 9820 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9821 break; 9822 case Intrinsic::x86_mmx_psrli_q: 9823 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9824 break; 9825 case Intrinsic::x86_mmx_psrai_w: 9826 NewIntNo = Intrinsic::x86_mmx_psra_w; 9827 break; 9828 case Intrinsic::x86_mmx_psrai_d: 9829 NewIntNo = Intrinsic::x86_mmx_psra_d; 9830 break; 9831 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9832 } 9833 9834 // The vector shift intrinsics with scalars uses 32b shift amounts but 9835 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9836 // to be zero. 9837 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9838 DAG.getConstant(0, MVT::i32)); 9839// FIXME this must be lowered to get rid of the invalid type. 9840 9841 EVT VT = Op.getValueType(); 9842 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9843 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9844 DAG.getConstant(NewIntNo, MVT::i32), 9845 Op.getOperand(1), ShAmt); 9846 } 9847 } 9848} 9849 9850SDValue 9851X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9852 DebugLoc dl = Op.getDebugLoc(); 9853 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 9854 switch (IntNo) { 9855 default: return SDValue(); // Don't custom lower most intrinsics. 9856 9857 // RDRAND intrinsics. 9858 case Intrinsic::x86_rdrand_16: 9859 case Intrinsic::x86_rdrand_32: 9860 case Intrinsic::x86_rdrand_64: { 9861 // Emit the node with the right value type. 9862 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other); 9863 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0)); 9864 9865 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise 9866 // return the value from Rand, which is always 0, casted to i32. 9867 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)), 9868 DAG.getConstant(1, Op->getValueType(1)), 9869 DAG.getConstant(X86::COND_B, MVT::i32), 9870 SDValue(Result.getNode(), 1) }; 9871 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, 9872 DAG.getVTList(Op->getValueType(1), MVT::Glue), 9873 Ops, 4); 9874 9875 // Return { result, isValid, chain }. 9876 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid, 9877 SDValue(Result.getNode(), 2)); 9878 } 9879 } 9880} 9881 9882SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9883 SelectionDAG &DAG) const { 9884 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9885 MFI->setReturnAddressIsTaken(true); 9886 9887 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9888 DebugLoc dl = Op.getDebugLoc(); 9889 9890 if (Depth > 0) { 9891 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9892 SDValue Offset = 9893 DAG.getConstant(TD->getPointerSize(), 9894 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9895 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9896 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9897 FrameAddr, Offset), 9898 MachinePointerInfo(), false, false, false, 0); 9899 } 9900 9901 // Just load the return address. 9902 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9903 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9904 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9905} 9906 9907SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9908 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9909 MFI->setFrameAddressIsTaken(true); 9910 9911 EVT VT = Op.getValueType(); 9912 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9913 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9914 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9915 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9916 while (Depth--) 9917 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9918 MachinePointerInfo(), 9919 false, false, false, 0); 9920 return FrameAddr; 9921} 9922 9923SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9924 SelectionDAG &DAG) const { 9925 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9926} 9927 9928SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9929 SDValue Chain = Op.getOperand(0); 9930 SDValue Offset = Op.getOperand(1); 9931 SDValue Handler = Op.getOperand(2); 9932 DebugLoc dl = Op.getDebugLoc(); 9933 9934 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9935 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9936 getPointerTy()); 9937 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9938 9939 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9940 DAG.getIntPtrConstant(TD->getPointerSize())); 9941 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9942 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9943 false, false, 0); 9944 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9945 9946 return DAG.getNode(X86ISD::EH_RETURN, dl, 9947 MVT::Other, 9948 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9949} 9950 9951SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9952 SelectionDAG &DAG) const { 9953 return Op.getOperand(0); 9954} 9955 9956SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9957 SelectionDAG &DAG) const { 9958 SDValue Root = Op.getOperand(0); 9959 SDValue Trmp = Op.getOperand(1); // trampoline 9960 SDValue FPtr = Op.getOperand(2); // nested function 9961 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9962 DebugLoc dl = Op.getDebugLoc(); 9963 9964 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9965 9966 if (Subtarget->is64Bit()) { 9967 SDValue OutChains[6]; 9968 9969 // Large code-model. 9970 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9971 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9972 9973 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9974 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9975 9976 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9977 9978 // Load the pointer to the nested function into R11. 9979 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9980 SDValue Addr = Trmp; 9981 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9982 Addr, MachinePointerInfo(TrmpAddr), 9983 false, false, 0); 9984 9985 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9986 DAG.getConstant(2, MVT::i64)); 9987 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9988 MachinePointerInfo(TrmpAddr, 2), 9989 false, false, 2); 9990 9991 // Load the 'nest' parameter value into R10. 9992 // R10 is specified in X86CallingConv.td 9993 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9994 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9995 DAG.getConstant(10, MVT::i64)); 9996 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9997 Addr, MachinePointerInfo(TrmpAddr, 10), 9998 false, false, 0); 9999 10000 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10001 DAG.getConstant(12, MVT::i64)); 10002 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 10003 MachinePointerInfo(TrmpAddr, 12), 10004 false, false, 2); 10005 10006 // Jump to the nested function. 10007 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 10008 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10009 DAG.getConstant(20, MVT::i64)); 10010 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10011 Addr, MachinePointerInfo(TrmpAddr, 20), 10012 false, false, 0); 10013 10014 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 10015 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10016 DAG.getConstant(22, MVT::i64)); 10017 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 10018 MachinePointerInfo(TrmpAddr, 22), 10019 false, false, 0); 10020 10021 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 10022 } else { 10023 const Function *Func = 10024 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 10025 CallingConv::ID CC = Func->getCallingConv(); 10026 unsigned NestReg; 10027 10028 switch (CC) { 10029 default: 10030 llvm_unreachable("Unsupported calling convention"); 10031 case CallingConv::C: 10032 case CallingConv::X86_StdCall: { 10033 // Pass 'nest' parameter in ECX. 10034 // Must be kept in sync with X86CallingConv.td 10035 NestReg = X86::ECX; 10036 10037 // Check that ECX wasn't needed by an 'inreg' parameter. 10038 FunctionType *FTy = Func->getFunctionType(); 10039 const AttrListPtr &Attrs = Func->getAttributes(); 10040 10041 if (!Attrs.isEmpty() && !Func->isVarArg()) { 10042 unsigned InRegCount = 0; 10043 unsigned Idx = 1; 10044 10045 for (FunctionType::param_iterator I = FTy->param_begin(), 10046 E = FTy->param_end(); I != E; ++I, ++Idx) 10047 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 10048 // FIXME: should only count parameters that are lowered to integers. 10049 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 10050 10051 if (InRegCount > 2) { 10052 report_fatal_error("Nest register in use - reduce number of inreg" 10053 " parameters!"); 10054 } 10055 } 10056 break; 10057 } 10058 case CallingConv::X86_FastCall: 10059 case CallingConv::X86_ThisCall: 10060 case CallingConv::Fast: 10061 // Pass 'nest' parameter in EAX. 10062 // Must be kept in sync with X86CallingConv.td 10063 NestReg = X86::EAX; 10064 break; 10065 } 10066 10067 SDValue OutChains[4]; 10068 SDValue Addr, Disp; 10069 10070 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10071 DAG.getConstant(10, MVT::i32)); 10072 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 10073 10074 // This is storing the opcode for MOV32ri. 10075 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 10076 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 10077 OutChains[0] = DAG.getStore(Root, dl, 10078 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 10079 Trmp, MachinePointerInfo(TrmpAddr), 10080 false, false, 0); 10081 10082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10083 DAG.getConstant(1, MVT::i32)); 10084 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 10085 MachinePointerInfo(TrmpAddr, 1), 10086 false, false, 1); 10087 10088 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 10089 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10090 DAG.getConstant(5, MVT::i32)); 10091 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 10092 MachinePointerInfo(TrmpAddr, 5), 10093 false, false, 1); 10094 10095 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10096 DAG.getConstant(6, MVT::i32)); 10097 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 10098 MachinePointerInfo(TrmpAddr, 6), 10099 false, false, 1); 10100 10101 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 10102 } 10103} 10104 10105SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10106 SelectionDAG &DAG) const { 10107 /* 10108 The rounding mode is in bits 11:10 of FPSR, and has the following 10109 settings: 10110 00 Round to nearest 10111 01 Round to -inf 10112 10 Round to +inf 10113 11 Round to 0 10114 10115 FLT_ROUNDS, on the other hand, expects the following: 10116 -1 Undefined 10117 0 Round to 0 10118 1 Round to nearest 10119 2 Round to +inf 10120 3 Round to -inf 10121 10122 To perform the conversion, we do: 10123 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10124 */ 10125 10126 MachineFunction &MF = DAG.getMachineFunction(); 10127 const TargetMachine &TM = MF.getTarget(); 10128 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10129 unsigned StackAlignment = TFI.getStackAlignment(); 10130 EVT VT = Op.getValueType(); 10131 DebugLoc DL = Op.getDebugLoc(); 10132 10133 // Save FP Control Word to stack slot 10134 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10135 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10136 10137 10138 MachineMemOperand *MMO = 10139 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10140 MachineMemOperand::MOStore, 2, 2); 10141 10142 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10143 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10144 DAG.getVTList(MVT::Other), 10145 Ops, 2, MVT::i16, MMO); 10146 10147 // Load FP Control Word from stack slot 10148 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10149 MachinePointerInfo(), false, false, false, 0); 10150 10151 // Transform as necessary 10152 SDValue CWD1 = 10153 DAG.getNode(ISD::SRL, DL, MVT::i16, 10154 DAG.getNode(ISD::AND, DL, MVT::i16, 10155 CWD, DAG.getConstant(0x800, MVT::i16)), 10156 DAG.getConstant(11, MVT::i8)); 10157 SDValue CWD2 = 10158 DAG.getNode(ISD::SRL, DL, MVT::i16, 10159 DAG.getNode(ISD::AND, DL, MVT::i16, 10160 CWD, DAG.getConstant(0x400, MVT::i16)), 10161 DAG.getConstant(9, MVT::i8)); 10162 10163 SDValue RetVal = 10164 DAG.getNode(ISD::AND, DL, MVT::i16, 10165 DAG.getNode(ISD::ADD, DL, MVT::i16, 10166 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10167 DAG.getConstant(1, MVT::i16)), 10168 DAG.getConstant(3, MVT::i16)); 10169 10170 10171 return DAG.getNode((VT.getSizeInBits() < 16 ? 10172 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10173} 10174 10175SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10176 EVT VT = Op.getValueType(); 10177 EVT OpVT = VT; 10178 unsigned NumBits = VT.getSizeInBits(); 10179 DebugLoc dl = Op.getDebugLoc(); 10180 10181 Op = Op.getOperand(0); 10182 if (VT == MVT::i8) { 10183 // Zero extend to i32 since there is not an i8 bsr. 10184 OpVT = MVT::i32; 10185 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10186 } 10187 10188 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10189 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10190 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10191 10192 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10193 SDValue Ops[] = { 10194 Op, 10195 DAG.getConstant(NumBits+NumBits-1, OpVT), 10196 DAG.getConstant(X86::COND_E, MVT::i8), 10197 Op.getValue(1) 10198 }; 10199 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10200 10201 // Finally xor with NumBits-1. 10202 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10203 10204 if (VT == MVT::i8) 10205 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10206 return Op; 10207} 10208 10209SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10210 SelectionDAG &DAG) const { 10211 EVT VT = Op.getValueType(); 10212 EVT OpVT = VT; 10213 unsigned NumBits = VT.getSizeInBits(); 10214 DebugLoc dl = Op.getDebugLoc(); 10215 10216 Op = Op.getOperand(0); 10217 if (VT == MVT::i8) { 10218 // Zero extend to i32 since there is not an i8 bsr. 10219 OpVT = MVT::i32; 10220 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10221 } 10222 10223 // Issue a bsr (scan bits in reverse). 10224 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10225 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10226 10227 // And xor with NumBits-1. 10228 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10229 10230 if (VT == MVT::i8) 10231 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10232 return Op; 10233} 10234 10235SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10236 EVT VT = Op.getValueType(); 10237 unsigned NumBits = VT.getSizeInBits(); 10238 DebugLoc dl = Op.getDebugLoc(); 10239 Op = Op.getOperand(0); 10240 10241 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10242 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10243 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10244 10245 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10246 SDValue Ops[] = { 10247 Op, 10248 DAG.getConstant(NumBits, VT), 10249 DAG.getConstant(X86::COND_E, MVT::i8), 10250 Op.getValue(1) 10251 }; 10252 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10253} 10254 10255// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10256// ones, and then concatenate the result back. 10257static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10258 EVT VT = Op.getValueType(); 10259 10260 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10261 "Unsupported value type for operation"); 10262 10263 unsigned NumElems = VT.getVectorNumElements(); 10264 DebugLoc dl = Op.getDebugLoc(); 10265 10266 // Extract the LHS vectors 10267 SDValue LHS = Op.getOperand(0); 10268 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10269 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10270 10271 // Extract the RHS vectors 10272 SDValue RHS = Op.getOperand(1); 10273 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 10274 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 10275 10276 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10277 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10278 10279 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10280 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10281 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10282} 10283 10284SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10285 assert(Op.getValueType().getSizeInBits() == 256 && 10286 Op.getValueType().isInteger() && 10287 "Only handle AVX 256-bit vector integer operation"); 10288 return Lower256IntArith(Op, DAG); 10289} 10290 10291SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10292 assert(Op.getValueType().getSizeInBits() == 256 && 10293 Op.getValueType().isInteger() && 10294 "Only handle AVX 256-bit vector integer operation"); 10295 return Lower256IntArith(Op, DAG); 10296} 10297 10298SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10299 EVT VT = Op.getValueType(); 10300 10301 // Decompose 256-bit ops into smaller 128-bit ops. 10302 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10303 return Lower256IntArith(Op, DAG); 10304 10305 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10306 "Only know how to lower V2I64/V4I64 multiply"); 10307 10308 DebugLoc dl = Op.getDebugLoc(); 10309 10310 // Ahi = psrlqi(a, 32); 10311 // Bhi = psrlqi(b, 32); 10312 // 10313 // AloBlo = pmuludq(a, b); 10314 // AloBhi = pmuludq(a, Bhi); 10315 // AhiBlo = pmuludq(Ahi, b); 10316 10317 // AloBhi = psllqi(AloBhi, 32); 10318 // AhiBlo = psllqi(AhiBlo, 32); 10319 // return AloBlo + AloBhi + AhiBlo; 10320 10321 SDValue A = Op.getOperand(0); 10322 SDValue B = Op.getOperand(1); 10323 10324 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10325 10326 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10327 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10328 10329 // Bit cast to 32-bit vectors for MULUDQ 10330 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10331 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10332 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10333 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10334 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10335 10336 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10337 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10338 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10339 10340 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10341 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10342 10343 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10344 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10345} 10346 10347SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10348 10349 EVT VT = Op.getValueType(); 10350 DebugLoc dl = Op.getDebugLoc(); 10351 SDValue R = Op.getOperand(0); 10352 SDValue Amt = Op.getOperand(1); 10353 LLVMContext *Context = DAG.getContext(); 10354 10355 if (!Subtarget->hasSSE2()) 10356 return SDValue(); 10357 10358 // Optimize shl/srl/sra with constant shift amount. 10359 if (isSplatVector(Amt.getNode())) { 10360 SDValue SclrAmt = Amt->getOperand(0); 10361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10362 uint64_t ShiftAmt = C->getZExtValue(); 10363 10364 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10365 (Subtarget->hasAVX2() && 10366 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10367 if (Op.getOpcode() == ISD::SHL) 10368 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10369 DAG.getConstant(ShiftAmt, MVT::i32)); 10370 if (Op.getOpcode() == ISD::SRL) 10371 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10372 DAG.getConstant(ShiftAmt, MVT::i32)); 10373 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10374 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10375 DAG.getConstant(ShiftAmt, MVT::i32)); 10376 } 10377 10378 if (VT == MVT::v16i8) { 10379 if (Op.getOpcode() == ISD::SHL) { 10380 // Make a large shift. 10381 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10382 DAG.getConstant(ShiftAmt, MVT::i32)); 10383 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10384 // Zero out the rightmost bits. 10385 SmallVector<SDValue, 16> V(16, 10386 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10387 MVT::i8)); 10388 return DAG.getNode(ISD::AND, dl, VT, SHL, 10389 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10390 } 10391 if (Op.getOpcode() == ISD::SRL) { 10392 // Make a large shift. 10393 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10394 DAG.getConstant(ShiftAmt, MVT::i32)); 10395 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10396 // Zero out the leftmost bits. 10397 SmallVector<SDValue, 16> V(16, 10398 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10399 MVT::i8)); 10400 return DAG.getNode(ISD::AND, dl, VT, SRL, 10401 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10402 } 10403 if (Op.getOpcode() == ISD::SRA) { 10404 if (ShiftAmt == 7) { 10405 // R s>> 7 === R s< 0 10406 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10407 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10408 } 10409 10410 // R s>> a === ((R u>> a) ^ m) - m 10411 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10412 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10413 MVT::i8)); 10414 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10415 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10416 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10417 return Res; 10418 } 10419 llvm_unreachable("Unknown shift opcode."); 10420 } 10421 10422 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10423 if (Op.getOpcode() == ISD::SHL) { 10424 // Make a large shift. 10425 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10426 DAG.getConstant(ShiftAmt, MVT::i32)); 10427 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10428 // Zero out the rightmost bits. 10429 SmallVector<SDValue, 32> V(32, 10430 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10431 MVT::i8)); 10432 return DAG.getNode(ISD::AND, dl, VT, SHL, 10433 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10434 } 10435 if (Op.getOpcode() == ISD::SRL) { 10436 // Make a large shift. 10437 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10438 DAG.getConstant(ShiftAmt, MVT::i32)); 10439 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10440 // Zero out the leftmost bits. 10441 SmallVector<SDValue, 32> V(32, 10442 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10443 MVT::i8)); 10444 return DAG.getNode(ISD::AND, dl, VT, SRL, 10445 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10446 } 10447 if (Op.getOpcode() == ISD::SRA) { 10448 if (ShiftAmt == 7) { 10449 // R s>> 7 === R s< 0 10450 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10451 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10452 } 10453 10454 // R s>> a === ((R u>> a) ^ m) - m 10455 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10456 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10457 MVT::i8)); 10458 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10459 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10460 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10461 return Res; 10462 } 10463 llvm_unreachable("Unknown shift opcode."); 10464 } 10465 } 10466 } 10467 10468 // Lower SHL with variable shift amount. 10469 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10470 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10471 DAG.getConstant(23, MVT::i32)); 10472 10473 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10474 Constant *C = ConstantDataVector::get(*Context, CV); 10475 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10476 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10477 MachinePointerInfo::getConstantPool(), 10478 false, false, false, 16); 10479 10480 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10481 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10482 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10483 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10484 } 10485 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10486 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10487 10488 // a = a << 5; 10489 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10490 DAG.getConstant(5, MVT::i32)); 10491 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10492 10493 // Turn 'a' into a mask suitable for VSELECT 10494 SDValue VSelM = DAG.getConstant(0x80, VT); 10495 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10496 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10497 10498 SDValue CM1 = DAG.getConstant(0x0f, VT); 10499 SDValue CM2 = DAG.getConstant(0x3f, VT); 10500 10501 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10502 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10503 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10504 DAG.getConstant(4, MVT::i32), DAG); 10505 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10506 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10507 10508 // a += a 10509 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10510 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10511 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10512 10513 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10514 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10515 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10516 DAG.getConstant(2, MVT::i32), DAG); 10517 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10518 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10519 10520 // a += a 10521 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10522 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10523 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10524 10525 // return VSELECT(r, r+r, a); 10526 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10527 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10528 return R; 10529 } 10530 10531 // Decompose 256-bit shifts into smaller 128-bit shifts. 10532 if (VT.getSizeInBits() == 256) { 10533 unsigned NumElems = VT.getVectorNumElements(); 10534 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10535 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10536 10537 // Extract the two vectors 10538 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 10539 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 10540 10541 // Recreate the shift amount vectors 10542 SDValue Amt1, Amt2; 10543 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10544 // Constant shift amount 10545 SmallVector<SDValue, 4> Amt1Csts; 10546 SmallVector<SDValue, 4> Amt2Csts; 10547 for (unsigned i = 0; i != NumElems/2; ++i) 10548 Amt1Csts.push_back(Amt->getOperand(i)); 10549 for (unsigned i = NumElems/2; i != NumElems; ++i) 10550 Amt2Csts.push_back(Amt->getOperand(i)); 10551 10552 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10553 &Amt1Csts[0], NumElems/2); 10554 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10555 &Amt2Csts[0], NumElems/2); 10556 } else { 10557 // Variable shift amount 10558 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 10559 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 10560 } 10561 10562 // Issue new vector shifts for the smaller types 10563 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10564 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10565 10566 // Concatenate the result back 10567 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10568 } 10569 10570 return SDValue(); 10571} 10572 10573SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10574 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10575 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10576 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10577 // has only one use. 10578 SDNode *N = Op.getNode(); 10579 SDValue LHS = N->getOperand(0); 10580 SDValue RHS = N->getOperand(1); 10581 unsigned BaseOp = 0; 10582 unsigned Cond = 0; 10583 DebugLoc DL = Op.getDebugLoc(); 10584 switch (Op.getOpcode()) { 10585 default: llvm_unreachable("Unknown ovf instruction!"); 10586 case ISD::SADDO: 10587 // A subtract of one will be selected as a INC. Note that INC doesn't 10588 // set CF, so we can't do this for UADDO. 10589 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10590 if (C->isOne()) { 10591 BaseOp = X86ISD::INC; 10592 Cond = X86::COND_O; 10593 break; 10594 } 10595 BaseOp = X86ISD::ADD; 10596 Cond = X86::COND_O; 10597 break; 10598 case ISD::UADDO: 10599 BaseOp = X86ISD::ADD; 10600 Cond = X86::COND_B; 10601 break; 10602 case ISD::SSUBO: 10603 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10604 // set CF, so we can't do this for USUBO. 10605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10606 if (C->isOne()) { 10607 BaseOp = X86ISD::DEC; 10608 Cond = X86::COND_O; 10609 break; 10610 } 10611 BaseOp = X86ISD::SUB; 10612 Cond = X86::COND_O; 10613 break; 10614 case ISD::USUBO: 10615 BaseOp = X86ISD::SUB; 10616 Cond = X86::COND_B; 10617 break; 10618 case ISD::SMULO: 10619 BaseOp = X86ISD::SMUL; 10620 Cond = X86::COND_O; 10621 break; 10622 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10623 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10624 MVT::i32); 10625 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10626 10627 SDValue SetCC = 10628 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10629 DAG.getConstant(X86::COND_O, MVT::i32), 10630 SDValue(Sum.getNode(), 2)); 10631 10632 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10633 } 10634 } 10635 10636 // Also sets EFLAGS. 10637 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10638 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10639 10640 SDValue SetCC = 10641 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10642 DAG.getConstant(Cond, MVT::i32), 10643 SDValue(Sum.getNode(), 1)); 10644 10645 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10646} 10647 10648SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10649 SelectionDAG &DAG) const { 10650 DebugLoc dl = Op.getDebugLoc(); 10651 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10652 EVT VT = Op.getValueType(); 10653 10654 if (!Subtarget->hasSSE2() || !VT.isVector()) 10655 return SDValue(); 10656 10657 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10658 ExtraVT.getScalarType().getSizeInBits(); 10659 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10660 10661 switch (VT.getSimpleVT().SimpleTy) { 10662 default: return SDValue(); 10663 case MVT::v8i32: 10664 case MVT::v16i16: 10665 if (!Subtarget->hasAVX()) 10666 return SDValue(); 10667 if (!Subtarget->hasAVX2()) { 10668 // needs to be split 10669 unsigned NumElems = VT.getVectorNumElements(); 10670 10671 // Extract the LHS vectors 10672 SDValue LHS = Op.getOperand(0); 10673 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10674 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10675 10676 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10677 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10678 10679 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10680 unsigned ExtraNumElems = ExtraVT.getVectorNumElements(); 10681 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10682 ExtraNumElems/2); 10683 SDValue Extra = DAG.getValueType(ExtraVT); 10684 10685 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10686 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10687 10688 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10689 } 10690 // fall through 10691 case MVT::v4i32: 10692 case MVT::v8i16: { 10693 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10694 Op.getOperand(0), ShAmt, DAG); 10695 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10696 } 10697 } 10698} 10699 10700 10701SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10702 DebugLoc dl = Op.getDebugLoc(); 10703 10704 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10705 // There isn't any reason to disable it if the target processor supports it. 10706 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10707 SDValue Chain = Op.getOperand(0); 10708 SDValue Zero = DAG.getConstant(0, MVT::i32); 10709 SDValue Ops[] = { 10710 DAG.getRegister(X86::ESP, MVT::i32), // Base 10711 DAG.getTargetConstant(1, MVT::i8), // Scale 10712 DAG.getRegister(0, MVT::i32), // Index 10713 DAG.getTargetConstant(0, MVT::i32), // Disp 10714 DAG.getRegister(0, MVT::i32), // Segment. 10715 Zero, 10716 Chain 10717 }; 10718 SDNode *Res = 10719 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10720 array_lengthof(Ops)); 10721 return SDValue(Res, 0); 10722 } 10723 10724 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10725 if (!isDev) 10726 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10727 10728 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10729 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10730 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10731 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10732 10733 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10734 if (!Op1 && !Op2 && !Op3 && Op4) 10735 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10736 10737 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10738 if (Op1 && !Op2 && !Op3 && !Op4) 10739 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10740 10741 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10742 // (MFENCE)>; 10743 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10744} 10745 10746SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10747 SelectionDAG &DAG) const { 10748 DebugLoc dl = Op.getDebugLoc(); 10749 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10750 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10751 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10752 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10753 10754 // The only fence that needs an instruction is a sequentially-consistent 10755 // cross-thread fence. 10756 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10757 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10758 // no-sse2). There isn't any reason to disable it if the target processor 10759 // supports it. 10760 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10761 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10762 10763 SDValue Chain = Op.getOperand(0); 10764 SDValue Zero = DAG.getConstant(0, MVT::i32); 10765 SDValue Ops[] = { 10766 DAG.getRegister(X86::ESP, MVT::i32), // Base 10767 DAG.getTargetConstant(1, MVT::i8), // Scale 10768 DAG.getRegister(0, MVT::i32), // Index 10769 DAG.getTargetConstant(0, MVT::i32), // Disp 10770 DAG.getRegister(0, MVT::i32), // Segment. 10771 Zero, 10772 Chain 10773 }; 10774 SDNode *Res = 10775 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10776 array_lengthof(Ops)); 10777 return SDValue(Res, 0); 10778 } 10779 10780 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10781 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10782} 10783 10784 10785SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10786 EVT T = Op.getValueType(); 10787 DebugLoc DL = Op.getDebugLoc(); 10788 unsigned Reg = 0; 10789 unsigned size = 0; 10790 switch(T.getSimpleVT().SimpleTy) { 10791 default: llvm_unreachable("Invalid value type!"); 10792 case MVT::i8: Reg = X86::AL; size = 1; break; 10793 case MVT::i16: Reg = X86::AX; size = 2; break; 10794 case MVT::i32: Reg = X86::EAX; size = 4; break; 10795 case MVT::i64: 10796 assert(Subtarget->is64Bit() && "Node not type legal!"); 10797 Reg = X86::RAX; size = 8; 10798 break; 10799 } 10800 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10801 Op.getOperand(2), SDValue()); 10802 SDValue Ops[] = { cpIn.getValue(0), 10803 Op.getOperand(1), 10804 Op.getOperand(3), 10805 DAG.getTargetConstant(size, MVT::i8), 10806 cpIn.getValue(1) }; 10807 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10808 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10809 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10810 Ops, 5, T, MMO); 10811 SDValue cpOut = 10812 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10813 return cpOut; 10814} 10815 10816SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10817 SelectionDAG &DAG) const { 10818 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10819 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10820 SDValue TheChain = Op.getOperand(0); 10821 DebugLoc dl = Op.getDebugLoc(); 10822 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10823 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10824 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10825 rax.getValue(2)); 10826 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10827 DAG.getConstant(32, MVT::i8)); 10828 SDValue Ops[] = { 10829 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10830 rdx.getValue(1) 10831 }; 10832 return DAG.getMergeValues(Ops, 2, dl); 10833} 10834 10835SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10836 SelectionDAG &DAG) const { 10837 EVT SrcVT = Op.getOperand(0).getValueType(); 10838 EVT DstVT = Op.getValueType(); 10839 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10840 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10841 assert((DstVT == MVT::i64 || 10842 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10843 "Unexpected custom BITCAST"); 10844 // i64 <=> MMX conversions are Legal. 10845 if (SrcVT==MVT::i64 && DstVT.isVector()) 10846 return Op; 10847 if (DstVT==MVT::i64 && SrcVT.isVector()) 10848 return Op; 10849 // MMX <=> MMX conversions are Legal. 10850 if (SrcVT.isVector() && DstVT.isVector()) 10851 return Op; 10852 // All other conversions need to be expanded. 10853 return SDValue(); 10854} 10855 10856SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10857 SDNode *Node = Op.getNode(); 10858 DebugLoc dl = Node->getDebugLoc(); 10859 EVT T = Node->getValueType(0); 10860 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10861 DAG.getConstant(0, T), Node->getOperand(2)); 10862 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10863 cast<AtomicSDNode>(Node)->getMemoryVT(), 10864 Node->getOperand(0), 10865 Node->getOperand(1), negOp, 10866 cast<AtomicSDNode>(Node)->getSrcValue(), 10867 cast<AtomicSDNode>(Node)->getAlignment(), 10868 cast<AtomicSDNode>(Node)->getOrdering(), 10869 cast<AtomicSDNode>(Node)->getSynchScope()); 10870} 10871 10872static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10873 SDNode *Node = Op.getNode(); 10874 DebugLoc dl = Node->getDebugLoc(); 10875 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10876 10877 // Convert seq_cst store -> xchg 10878 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10879 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10880 // (The only way to get a 16-byte store is cmpxchg16b) 10881 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10882 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10883 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10884 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10885 cast<AtomicSDNode>(Node)->getMemoryVT(), 10886 Node->getOperand(0), 10887 Node->getOperand(1), Node->getOperand(2), 10888 cast<AtomicSDNode>(Node)->getMemOperand(), 10889 cast<AtomicSDNode>(Node)->getOrdering(), 10890 cast<AtomicSDNode>(Node)->getSynchScope()); 10891 return Swap.getValue(1); 10892 } 10893 // Other atomic stores have a simple pattern. 10894 return Op; 10895} 10896 10897static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10898 EVT VT = Op.getNode()->getValueType(0); 10899 10900 // Let legalize expand this if it isn't a legal type yet. 10901 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10902 return SDValue(); 10903 10904 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10905 10906 unsigned Opc; 10907 bool ExtraOp = false; 10908 switch (Op.getOpcode()) { 10909 default: llvm_unreachable("Invalid code"); 10910 case ISD::ADDC: Opc = X86ISD::ADD; break; 10911 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10912 case ISD::SUBC: Opc = X86ISD::SUB; break; 10913 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10914 } 10915 10916 if (!ExtraOp) 10917 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10918 Op.getOperand(1)); 10919 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10920 Op.getOperand(1), Op.getOperand(2)); 10921} 10922 10923/// LowerOperation - Provide custom lowering hooks for some operations. 10924/// 10925SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10926 switch (Op.getOpcode()) { 10927 default: llvm_unreachable("Should not custom lower this!"); 10928 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10929 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10930 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10931 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10932 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10933 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10934 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10935 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10936 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10937 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10938 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10939 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10940 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10941 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10942 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10943 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10944 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10945 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10946 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10947 case ISD::SHL_PARTS: 10948 case ISD::SRA_PARTS: 10949 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10950 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10951 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10952 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10953 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10954 case ISD::FABS: return LowerFABS(Op, DAG); 10955 case ISD::FNEG: return LowerFNEG(Op, DAG); 10956 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10957 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10958 case ISD::SETCC: return LowerSETCC(Op, DAG); 10959 case ISD::SELECT: return LowerSELECT(Op, DAG); 10960 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10961 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10962 case ISD::VASTART: return LowerVASTART(Op, DAG); 10963 case ISD::VAARG: return LowerVAARG(Op, DAG); 10964 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10965 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10966 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG); 10967 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10968 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10969 case ISD::FRAME_TO_ARGS_OFFSET: 10970 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10971 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10972 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10973 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10974 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10975 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10976 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10977 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10978 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10979 case ISD::MUL: return LowerMUL(Op, DAG); 10980 case ISD::SRA: 10981 case ISD::SRL: 10982 case ISD::SHL: return LowerShift(Op, DAG); 10983 case ISD::SADDO: 10984 case ISD::UADDO: 10985 case ISD::SSUBO: 10986 case ISD::USUBO: 10987 case ISD::SMULO: 10988 case ISD::UMULO: return LowerXALUO(Op, DAG); 10989 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10990 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10991 case ISD::ADDC: 10992 case ISD::ADDE: 10993 case ISD::SUBC: 10994 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10995 case ISD::ADD: return LowerADD(Op, DAG); 10996 case ISD::SUB: return LowerSUB(Op, DAG); 10997 } 10998} 10999 11000static void ReplaceATOMIC_LOAD(SDNode *Node, 11001 SmallVectorImpl<SDValue> &Results, 11002 SelectionDAG &DAG) { 11003 DebugLoc dl = Node->getDebugLoc(); 11004 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 11005 11006 // Convert wide load -> cmpxchg8b/cmpxchg16b 11007 // FIXME: On 32-bit, load -> fild or movq would be more efficient 11008 // (The only way to get a 16-byte load is cmpxchg16b) 11009 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 11010 SDValue Zero = DAG.getConstant(0, VT); 11011 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 11012 Node->getOperand(0), 11013 Node->getOperand(1), Zero, Zero, 11014 cast<AtomicSDNode>(Node)->getMemOperand(), 11015 cast<AtomicSDNode>(Node)->getOrdering(), 11016 cast<AtomicSDNode>(Node)->getSynchScope()); 11017 Results.push_back(Swap.getValue(0)); 11018 Results.push_back(Swap.getValue(1)); 11019} 11020 11021void X86TargetLowering:: 11022ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 11023 SelectionDAG &DAG, unsigned NewOp) const { 11024 DebugLoc dl = Node->getDebugLoc(); 11025 assert (Node->getValueType(0) == MVT::i64 && 11026 "Only know how to expand i64 atomics"); 11027 11028 SDValue Chain = Node->getOperand(0); 11029 SDValue In1 = Node->getOperand(1); 11030 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11031 Node->getOperand(2), DAG.getIntPtrConstant(0)); 11032 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11033 Node->getOperand(2), DAG.getIntPtrConstant(1)); 11034 SDValue Ops[] = { Chain, In1, In2L, In2H }; 11035 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 11036 SDValue Result = 11037 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 11038 cast<MemSDNode>(Node)->getMemOperand()); 11039 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 11040 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 11041 Results.push_back(Result.getValue(2)); 11042} 11043 11044/// ReplaceNodeResults - Replace a node with an illegal result type 11045/// with a new node built out of custom code. 11046void X86TargetLowering::ReplaceNodeResults(SDNode *N, 11047 SmallVectorImpl<SDValue>&Results, 11048 SelectionDAG &DAG) const { 11049 DebugLoc dl = N->getDebugLoc(); 11050 switch (N->getOpcode()) { 11051 default: 11052 llvm_unreachable("Do not know how to custom type legalize this operation!"); 11053 case ISD::SIGN_EXTEND_INREG: 11054 case ISD::ADDC: 11055 case ISD::ADDE: 11056 case ISD::SUBC: 11057 case ISD::SUBE: 11058 // We don't want to expand or promote these. 11059 return; 11060 case ISD::FP_TO_SINT: 11061 case ISD::FP_TO_UINT: { 11062 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 11063 11064 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 11065 return; 11066 11067 std::pair<SDValue,SDValue> Vals = 11068 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 11069 SDValue FIST = Vals.first, StackSlot = Vals.second; 11070 if (FIST.getNode() != 0) { 11071 EVT VT = N->getValueType(0); 11072 // Return a load from the stack slot. 11073 if (StackSlot.getNode() != 0) 11074 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 11075 MachinePointerInfo(), 11076 false, false, false, 0)); 11077 else 11078 Results.push_back(FIST); 11079 } 11080 return; 11081 } 11082 case ISD::READCYCLECOUNTER: { 11083 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11084 SDValue TheChain = N->getOperand(0); 11085 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11086 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 11087 rd.getValue(1)); 11088 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 11089 eax.getValue(2)); 11090 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 11091 SDValue Ops[] = { eax, edx }; 11092 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 11093 Results.push_back(edx.getValue(1)); 11094 return; 11095 } 11096 case ISD::ATOMIC_CMP_SWAP: { 11097 EVT T = N->getValueType(0); 11098 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 11099 bool Regs64bit = T == MVT::i128; 11100 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11101 SDValue cpInL, cpInH; 11102 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11103 DAG.getConstant(0, HalfT)); 11104 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11105 DAG.getConstant(1, HalfT)); 11106 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11107 Regs64bit ? X86::RAX : X86::EAX, 11108 cpInL, SDValue()); 11109 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11110 Regs64bit ? X86::RDX : X86::EDX, 11111 cpInH, cpInL.getValue(1)); 11112 SDValue swapInL, swapInH; 11113 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11114 DAG.getConstant(0, HalfT)); 11115 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11116 DAG.getConstant(1, HalfT)); 11117 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11118 Regs64bit ? X86::RBX : X86::EBX, 11119 swapInL, cpInH.getValue(1)); 11120 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11121 Regs64bit ? X86::RCX : X86::ECX, 11122 swapInH, swapInL.getValue(1)); 11123 SDValue Ops[] = { swapInH.getValue(0), 11124 N->getOperand(1), 11125 swapInH.getValue(1) }; 11126 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11127 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11128 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11129 X86ISD::LCMPXCHG8_DAG; 11130 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11131 Ops, 3, T, MMO); 11132 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11133 Regs64bit ? X86::RAX : X86::EAX, 11134 HalfT, Result.getValue(1)); 11135 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11136 Regs64bit ? X86::RDX : X86::EDX, 11137 HalfT, cpOutL.getValue(2)); 11138 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11139 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11140 Results.push_back(cpOutH.getValue(1)); 11141 return; 11142 } 11143 case ISD::ATOMIC_LOAD_ADD: 11144 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 11145 return; 11146 case ISD::ATOMIC_LOAD_AND: 11147 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 11148 return; 11149 case ISD::ATOMIC_LOAD_NAND: 11150 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 11151 return; 11152 case ISD::ATOMIC_LOAD_OR: 11153 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 11154 return; 11155 case ISD::ATOMIC_LOAD_SUB: 11156 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 11157 return; 11158 case ISD::ATOMIC_LOAD_XOR: 11159 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11160 return; 11161 case ISD::ATOMIC_SWAP: 11162 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11163 return; 11164 case ISD::ATOMIC_LOAD: 11165 ReplaceATOMIC_LOAD(N, Results, DAG); 11166 } 11167} 11168 11169const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11170 switch (Opcode) { 11171 default: return NULL; 11172 case X86ISD::BSF: return "X86ISD::BSF"; 11173 case X86ISD::BSR: return "X86ISD::BSR"; 11174 case X86ISD::SHLD: return "X86ISD::SHLD"; 11175 case X86ISD::SHRD: return "X86ISD::SHRD"; 11176 case X86ISD::FAND: return "X86ISD::FAND"; 11177 case X86ISD::FOR: return "X86ISD::FOR"; 11178 case X86ISD::FXOR: return "X86ISD::FXOR"; 11179 case X86ISD::FSRL: return "X86ISD::FSRL"; 11180 case X86ISD::FILD: return "X86ISD::FILD"; 11181 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11182 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11183 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11184 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11185 case X86ISD::FLD: return "X86ISD::FLD"; 11186 case X86ISD::FST: return "X86ISD::FST"; 11187 case X86ISD::CALL: return "X86ISD::CALL"; 11188 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11189 case X86ISD::BT: return "X86ISD::BT"; 11190 case X86ISD::CMP: return "X86ISD::CMP"; 11191 case X86ISD::COMI: return "X86ISD::COMI"; 11192 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11193 case X86ISD::SETCC: return "X86ISD::SETCC"; 11194 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11195 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11196 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11197 case X86ISD::CMOV: return "X86ISD::CMOV"; 11198 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11199 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11200 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11201 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11202 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11203 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11204 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11205 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11206 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11207 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11208 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11209 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11210 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11211 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11212 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11213 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11214 case X86ISD::BLENDPW: return "X86ISD::BLENDPW"; 11215 case X86ISD::BLENDPS: return "X86ISD::BLENDPS"; 11216 case X86ISD::BLENDPD: return "X86ISD::BLENDPD"; 11217 case X86ISD::HADD: return "X86ISD::HADD"; 11218 case X86ISD::HSUB: return "X86ISD::HSUB"; 11219 case X86ISD::FHADD: return "X86ISD::FHADD"; 11220 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11221 case X86ISD::FMAX: return "X86ISD::FMAX"; 11222 case X86ISD::FMIN: return "X86ISD::FMIN"; 11223 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11224 case X86ISD::FRCP: return "X86ISD::FRCP"; 11225 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11226 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR"; 11227 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11228 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11229 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11230 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11231 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 11232 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11233 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11234 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11235 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11236 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11237 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11238 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11239 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11240 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11241 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11242 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11243 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11244 case X86ISD::VSHL: return "X86ISD::VSHL"; 11245 case X86ISD::VSRL: return "X86ISD::VSRL"; 11246 case X86ISD::VSRA: return "X86ISD::VSRA"; 11247 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11248 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11249 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11250 case X86ISD::CMPP: return "X86ISD::CMPP"; 11251 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11252 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11253 case X86ISD::ADD: return "X86ISD::ADD"; 11254 case X86ISD::SUB: return "X86ISD::SUB"; 11255 case X86ISD::ADC: return "X86ISD::ADC"; 11256 case X86ISD::SBB: return "X86ISD::SBB"; 11257 case X86ISD::SMUL: return "X86ISD::SMUL"; 11258 case X86ISD::UMUL: return "X86ISD::UMUL"; 11259 case X86ISD::INC: return "X86ISD::INC"; 11260 case X86ISD::DEC: return "X86ISD::DEC"; 11261 case X86ISD::OR: return "X86ISD::OR"; 11262 case X86ISD::XOR: return "X86ISD::XOR"; 11263 case X86ISD::AND: return "X86ISD::AND"; 11264 case X86ISD::ANDN: return "X86ISD::ANDN"; 11265 case X86ISD::BLSI: return "X86ISD::BLSI"; 11266 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11267 case X86ISD::BLSR: return "X86ISD::BLSR"; 11268 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11269 case X86ISD::PTEST: return "X86ISD::PTEST"; 11270 case X86ISD::TESTP: return "X86ISD::TESTP"; 11271 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11272 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11273 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11274 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11275 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11276 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11277 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11278 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11279 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11280 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11281 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11282 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11283 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11284 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11285 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11286 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11287 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11288 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11289 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11290 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11291 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 11292 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 11293 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11294 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11295 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11296 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11297 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11298 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11299 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11300 case X86ISD::SAHF: return "X86ISD::SAHF"; 11301 case X86ISD::RDRAND: return "X86ISD::RDRAND"; 11302 case X86ISD::FMADD: return "X86ISD::FMADD"; 11303 case X86ISD::FMSUB: return "X86ISD::FMSUB"; 11304 case X86ISD::FNMADD: return "X86ISD::FNMADD"; 11305 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; 11306 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB"; 11307 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD"; 11308 } 11309} 11310 11311// isLegalAddressingMode - Return true if the addressing mode represented 11312// by AM is legal for this target, for a load/store of the specified type. 11313bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11314 Type *Ty) const { 11315 // X86 supports extremely general addressing modes. 11316 CodeModel::Model M = getTargetMachine().getCodeModel(); 11317 Reloc::Model R = getTargetMachine().getRelocationModel(); 11318 11319 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11320 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11321 return false; 11322 11323 if (AM.BaseGV) { 11324 unsigned GVFlags = 11325 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11326 11327 // If a reference to this global requires an extra load, we can't fold it. 11328 if (isGlobalStubReference(GVFlags)) 11329 return false; 11330 11331 // If BaseGV requires a register for the PIC base, we cannot also have a 11332 // BaseReg specified. 11333 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11334 return false; 11335 11336 // If lower 4G is not available, then we must use rip-relative addressing. 11337 if ((M != CodeModel::Small || R != Reloc::Static) && 11338 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11339 return false; 11340 } 11341 11342 switch (AM.Scale) { 11343 case 0: 11344 case 1: 11345 case 2: 11346 case 4: 11347 case 8: 11348 // These scales always work. 11349 break; 11350 case 3: 11351 case 5: 11352 case 9: 11353 // These scales are formed with basereg+scalereg. Only accept if there is 11354 // no basereg yet. 11355 if (AM.HasBaseReg) 11356 return false; 11357 break; 11358 default: // Other stuff never works. 11359 return false; 11360 } 11361 11362 return true; 11363} 11364 11365 11366bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11367 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11368 return false; 11369 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11370 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11371 if (NumBits1 <= NumBits2) 11372 return false; 11373 return true; 11374} 11375 11376bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const { 11377 return Imm == (int32_t)Imm; 11378} 11379 11380bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const { 11381 // Can also use sub to handle negated immediates. 11382 return Imm == (int32_t)Imm; 11383} 11384 11385bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11386 if (!VT1.isInteger() || !VT2.isInteger()) 11387 return false; 11388 unsigned NumBits1 = VT1.getSizeInBits(); 11389 unsigned NumBits2 = VT2.getSizeInBits(); 11390 if (NumBits1 <= NumBits2) 11391 return false; 11392 return true; 11393} 11394 11395bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11396 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11397 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11398} 11399 11400bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11401 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11402 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11403} 11404 11405bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11406 // i16 instructions are longer (0x66 prefix) and potentially slower. 11407 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11408} 11409 11410/// isShuffleMaskLegal - Targets can use this to indicate that they only 11411/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11412/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11413/// are assumed to be legal. 11414bool 11415X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11416 EVT VT) const { 11417 // Very little shuffling can be done for 64-bit vectors right now. 11418 if (VT.getSizeInBits() == 64) 11419 return false; 11420 11421 // FIXME: pshufb, blends, shifts. 11422 return (VT.getVectorNumElements() == 2 || 11423 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11424 isMOVLMask(M, VT) || 11425 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11426 isPSHUFDMask(M, VT) || 11427 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) || 11428 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) || 11429 isPALIGNRMask(M, VT, Subtarget) || 11430 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11431 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11432 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11433 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11434} 11435 11436bool 11437X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11438 EVT VT) const { 11439 unsigned NumElts = VT.getVectorNumElements(); 11440 // FIXME: This collection of masks seems suspect. 11441 if (NumElts == 2) 11442 return true; 11443 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11444 return (isMOVLMask(Mask, VT) || 11445 isCommutedMOVLMask(Mask, VT, true) || 11446 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11447 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11448 } 11449 return false; 11450} 11451 11452//===----------------------------------------------------------------------===// 11453// X86 Scheduler Hooks 11454//===----------------------------------------------------------------------===// 11455 11456// private utility function 11457MachineBasicBlock * 11458X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11459 MachineBasicBlock *MBB, 11460 unsigned regOpc, 11461 unsigned immOpc, 11462 unsigned LoadOpc, 11463 unsigned CXchgOpc, 11464 unsigned notOpc, 11465 unsigned EAXreg, 11466 const TargetRegisterClass *RC, 11467 bool Invert) const { 11468 // For the atomic bitwise operator, we generate 11469 // thisMBB: 11470 // newMBB: 11471 // ld t1 = [bitinstr.addr] 11472 // op t2 = t1, [bitinstr.val] 11473 // not t3 = t2 (if Invert) 11474 // mov EAX = t1 11475 // lcs dest = [bitinstr.addr], t3 [EAX is implicit] 11476 // bz newMBB 11477 // fallthrough -->nextMBB 11478 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11479 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11480 MachineFunction::iterator MBBIter = MBB; 11481 ++MBBIter; 11482 11483 /// First build the CFG 11484 MachineFunction *F = MBB->getParent(); 11485 MachineBasicBlock *thisMBB = MBB; 11486 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11487 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11488 F->insert(MBBIter, newMBB); 11489 F->insert(MBBIter, nextMBB); 11490 11491 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11492 nextMBB->splice(nextMBB->begin(), thisMBB, 11493 llvm::next(MachineBasicBlock::iterator(bInstr)), 11494 thisMBB->end()); 11495 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11496 11497 // Update thisMBB to fall through to newMBB 11498 thisMBB->addSuccessor(newMBB); 11499 11500 // newMBB jumps to itself and fall through to nextMBB 11501 newMBB->addSuccessor(nextMBB); 11502 newMBB->addSuccessor(newMBB); 11503 11504 // Insert instructions into newMBB based on incoming instruction 11505 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11506 "unexpected number of operands"); 11507 DebugLoc dl = bInstr->getDebugLoc(); 11508 MachineOperand& destOper = bInstr->getOperand(0); 11509 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11510 int numArgs = bInstr->getNumOperands() - 1; 11511 for (int i=0; i < numArgs; ++i) 11512 argOpers[i] = &bInstr->getOperand(i+1); 11513 11514 // x86 address has 4 operands: base, index, scale, and displacement 11515 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11516 int valArgIndx = lastAddrIndx + 1; 11517 11518 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11519 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11520 for (int i=0; i <= lastAddrIndx; ++i) 11521 (*MIB).addOperand(*argOpers[i]); 11522 11523 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11524 assert((argOpers[valArgIndx]->isReg() || 11525 argOpers[valArgIndx]->isImm()) && 11526 "invalid operand"); 11527 if (argOpers[valArgIndx]->isReg()) 11528 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11529 else 11530 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11531 MIB.addReg(t1); 11532 (*MIB).addOperand(*argOpers[valArgIndx]); 11533 11534 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11535 if (Invert) { 11536 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2); 11537 } 11538 else 11539 t3 = t2; 11540 11541 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11542 MIB.addReg(t1); 11543 11544 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11545 for (int i=0; i <= lastAddrIndx; ++i) 11546 (*MIB).addOperand(*argOpers[i]); 11547 MIB.addReg(t3); 11548 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11549 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11550 bInstr->memoperands_end()); 11551 11552 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11553 MIB.addReg(EAXreg); 11554 11555 // insert branch 11556 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11557 11558 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11559 return nextMBB; 11560} 11561 11562// private utility function: 64 bit atomics on 32 bit host. 11563MachineBasicBlock * 11564X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11565 MachineBasicBlock *MBB, 11566 unsigned regOpcL, 11567 unsigned regOpcH, 11568 unsigned immOpcL, 11569 unsigned immOpcH, 11570 bool Invert) const { 11571 // For the atomic bitwise operator, we generate 11572 // thisMBB (instructions are in pairs, except cmpxchg8b) 11573 // ld t1,t2 = [bitinstr.addr] 11574 // newMBB: 11575 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11576 // op t5, t6 <- out1, out2, [bitinstr.val] 11577 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11578 // neg t7, t8 < t5, t6 (if Invert) 11579 // mov ECX, EBX <- t5, t6 11580 // mov EAX, EDX <- t1, t2 11581 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11582 // mov t3, t4 <- EAX, EDX 11583 // bz newMBB 11584 // result in out1, out2 11585 // fallthrough -->nextMBB 11586 11587 const TargetRegisterClass *RC = &X86::GR32RegClass; 11588 const unsigned LoadOpc = X86::MOV32rm; 11589 const unsigned NotOpc = X86::NOT32r; 11590 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11591 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11592 MachineFunction::iterator MBBIter = MBB; 11593 ++MBBIter; 11594 11595 /// First build the CFG 11596 MachineFunction *F = MBB->getParent(); 11597 MachineBasicBlock *thisMBB = MBB; 11598 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11599 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11600 F->insert(MBBIter, newMBB); 11601 F->insert(MBBIter, nextMBB); 11602 11603 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11604 nextMBB->splice(nextMBB->begin(), thisMBB, 11605 llvm::next(MachineBasicBlock::iterator(bInstr)), 11606 thisMBB->end()); 11607 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11608 11609 // Update thisMBB to fall through to newMBB 11610 thisMBB->addSuccessor(newMBB); 11611 11612 // newMBB jumps to itself and fall through to nextMBB 11613 newMBB->addSuccessor(nextMBB); 11614 newMBB->addSuccessor(newMBB); 11615 11616 DebugLoc dl = bInstr->getDebugLoc(); 11617 // Insert instructions into newMBB based on incoming instruction 11618 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11619 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11620 "unexpected number of operands"); 11621 MachineOperand& dest1Oper = bInstr->getOperand(0); 11622 MachineOperand& dest2Oper = bInstr->getOperand(1); 11623 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11624 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11625 argOpers[i] = &bInstr->getOperand(i+2); 11626 11627 // We use some of the operands multiple times, so conservatively just 11628 // clear any kill flags that might be present. 11629 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11630 argOpers[i]->setIsKill(false); 11631 } 11632 11633 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11634 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11635 11636 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11637 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11638 for (int i=0; i <= lastAddrIndx; ++i) 11639 (*MIB).addOperand(*argOpers[i]); 11640 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11641 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11642 // add 4 to displacement. 11643 for (int i=0; i <= lastAddrIndx-2; ++i) 11644 (*MIB).addOperand(*argOpers[i]); 11645 MachineOperand newOp3 = *(argOpers[3]); 11646 if (newOp3.isImm()) 11647 newOp3.setImm(newOp3.getImm()+4); 11648 else 11649 newOp3.setOffset(newOp3.getOffset()+4); 11650 (*MIB).addOperand(newOp3); 11651 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11652 11653 // t3/4 are defined later, at the bottom of the loop 11654 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11655 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11656 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11657 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11658 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11659 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11660 11661 // The subsequent operations should be using the destination registers of 11662 // the PHI instructions. 11663 t1 = dest1Oper.getReg(); 11664 t2 = dest2Oper.getReg(); 11665 11666 int valArgIndx = lastAddrIndx + 1; 11667 assert((argOpers[valArgIndx]->isReg() || 11668 argOpers[valArgIndx]->isImm()) && 11669 "invalid operand"); 11670 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11671 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11672 if (argOpers[valArgIndx]->isReg()) 11673 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11674 else 11675 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11676 if (regOpcL != X86::MOV32rr) 11677 MIB.addReg(t1); 11678 (*MIB).addOperand(*argOpers[valArgIndx]); 11679 assert(argOpers[valArgIndx + 1]->isReg() == 11680 argOpers[valArgIndx]->isReg()); 11681 assert(argOpers[valArgIndx + 1]->isImm() == 11682 argOpers[valArgIndx]->isImm()); 11683 if (argOpers[valArgIndx + 1]->isReg()) 11684 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11685 else 11686 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11687 if (regOpcH != X86::MOV32rr) 11688 MIB.addReg(t2); 11689 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11690 11691 unsigned t7, t8; 11692 if (Invert) { 11693 t7 = F->getRegInfo().createVirtualRegister(RC); 11694 t8 = F->getRegInfo().createVirtualRegister(RC); 11695 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5); 11696 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6); 11697 } else { 11698 t7 = t5; 11699 t8 = t6; 11700 } 11701 11702 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11703 MIB.addReg(t1); 11704 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11705 MIB.addReg(t2); 11706 11707 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11708 MIB.addReg(t7); 11709 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11710 MIB.addReg(t8); 11711 11712 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11713 for (int i=0; i <= lastAddrIndx; ++i) 11714 (*MIB).addOperand(*argOpers[i]); 11715 11716 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11717 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11718 bInstr->memoperands_end()); 11719 11720 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11721 MIB.addReg(X86::EAX); 11722 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11723 MIB.addReg(X86::EDX); 11724 11725 // insert branch 11726 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11727 11728 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11729 return nextMBB; 11730} 11731 11732// private utility function 11733MachineBasicBlock * 11734X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11735 MachineBasicBlock *MBB, 11736 unsigned cmovOpc) const { 11737 // For the atomic min/max operator, we generate 11738 // thisMBB: 11739 // newMBB: 11740 // ld t1 = [min/max.addr] 11741 // mov t2 = [min/max.val] 11742 // cmp t1, t2 11743 // cmov[cond] t2 = t1 11744 // mov EAX = t1 11745 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11746 // bz newMBB 11747 // fallthrough -->nextMBB 11748 // 11749 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11750 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11751 MachineFunction::iterator MBBIter = MBB; 11752 ++MBBIter; 11753 11754 /// First build the CFG 11755 MachineFunction *F = MBB->getParent(); 11756 MachineBasicBlock *thisMBB = MBB; 11757 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11758 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11759 F->insert(MBBIter, newMBB); 11760 F->insert(MBBIter, nextMBB); 11761 11762 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11763 nextMBB->splice(nextMBB->begin(), thisMBB, 11764 llvm::next(MachineBasicBlock::iterator(mInstr)), 11765 thisMBB->end()); 11766 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11767 11768 // Update thisMBB to fall through to newMBB 11769 thisMBB->addSuccessor(newMBB); 11770 11771 // newMBB jumps to newMBB and fall through to nextMBB 11772 newMBB->addSuccessor(nextMBB); 11773 newMBB->addSuccessor(newMBB); 11774 11775 DebugLoc dl = mInstr->getDebugLoc(); 11776 // Insert instructions into newMBB based on incoming instruction 11777 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11778 "unexpected number of operands"); 11779 MachineOperand& destOper = mInstr->getOperand(0); 11780 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11781 int numArgs = mInstr->getNumOperands() - 1; 11782 for (int i=0; i < numArgs; ++i) 11783 argOpers[i] = &mInstr->getOperand(i+1); 11784 11785 // x86 address has 4 operands: base, index, scale, and displacement 11786 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11787 int valArgIndx = lastAddrIndx + 1; 11788 11789 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11790 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11791 for (int i=0; i <= lastAddrIndx; ++i) 11792 (*MIB).addOperand(*argOpers[i]); 11793 11794 // We only support register and immediate values 11795 assert((argOpers[valArgIndx]->isReg() || 11796 argOpers[valArgIndx]->isImm()) && 11797 "invalid operand"); 11798 11799 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11800 if (argOpers[valArgIndx]->isReg()) 11801 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11802 else 11803 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11804 (*MIB).addOperand(*argOpers[valArgIndx]); 11805 11806 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11807 MIB.addReg(t1); 11808 11809 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11810 MIB.addReg(t1); 11811 MIB.addReg(t2); 11812 11813 // Generate movc 11814 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11815 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11816 MIB.addReg(t2); 11817 MIB.addReg(t1); 11818 11819 // Cmp and exchange if none has modified the memory location 11820 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11821 for (int i=0; i <= lastAddrIndx; ++i) 11822 (*MIB).addOperand(*argOpers[i]); 11823 MIB.addReg(t3); 11824 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11825 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11826 mInstr->memoperands_end()); 11827 11828 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11829 MIB.addReg(X86::EAX); 11830 11831 // insert branch 11832 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11833 11834 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11835 return nextMBB; 11836} 11837 11838// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11839// or XMM0_V32I8 in AVX all of this code can be replaced with that 11840// in the .td file. 11841MachineBasicBlock * 11842X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11843 unsigned numArgs, bool memArg) const { 11844 assert(Subtarget->hasSSE42() && 11845 "Target must have SSE4.2 or AVX features enabled"); 11846 11847 DebugLoc dl = MI->getDebugLoc(); 11848 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11849 unsigned Opc; 11850 if (!Subtarget->hasAVX()) { 11851 if (memArg) 11852 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11853 else 11854 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11855 } else { 11856 if (memArg) 11857 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11858 else 11859 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11860 } 11861 11862 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11863 for (unsigned i = 0; i < numArgs; ++i) { 11864 MachineOperand &Op = MI->getOperand(i+1); 11865 if (!(Op.isReg() && Op.isImplicit())) 11866 MIB.addOperand(Op); 11867 } 11868 BuildMI(*BB, MI, dl, 11869 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11870 MI->getOperand(0).getReg()) 11871 .addReg(X86::XMM0); 11872 11873 MI->eraseFromParent(); 11874 return BB; 11875} 11876 11877MachineBasicBlock * 11878X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11879 DebugLoc dl = MI->getDebugLoc(); 11880 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11881 11882 // Address into RAX/EAX, other two args into ECX, EDX. 11883 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11884 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11885 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11886 for (int i = 0; i < X86::AddrNumOperands; ++i) 11887 MIB.addOperand(MI->getOperand(i)); 11888 11889 unsigned ValOps = X86::AddrNumOperands; 11890 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11891 .addReg(MI->getOperand(ValOps).getReg()); 11892 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11893 .addReg(MI->getOperand(ValOps+1).getReg()); 11894 11895 // The instruction doesn't actually take any operands though. 11896 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11897 11898 MI->eraseFromParent(); // The pseudo is gone now. 11899 return BB; 11900} 11901 11902MachineBasicBlock * 11903X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11904 DebugLoc dl = MI->getDebugLoc(); 11905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11906 11907 // First arg in ECX, the second in EAX. 11908 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11909 .addReg(MI->getOperand(0).getReg()); 11910 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11911 .addReg(MI->getOperand(1).getReg()); 11912 11913 // The instruction doesn't actually take any operands though. 11914 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11915 11916 MI->eraseFromParent(); // The pseudo is gone now. 11917 return BB; 11918} 11919 11920MachineBasicBlock * 11921X86TargetLowering::EmitVAARG64WithCustomInserter( 11922 MachineInstr *MI, 11923 MachineBasicBlock *MBB) const { 11924 // Emit va_arg instruction on X86-64. 11925 11926 // Operands to this pseudo-instruction: 11927 // 0 ) Output : destination address (reg) 11928 // 1-5) Input : va_list address (addr, i64mem) 11929 // 6 ) ArgSize : Size (in bytes) of vararg type 11930 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11931 // 8 ) Align : Alignment of type 11932 // 9 ) EFLAGS (implicit-def) 11933 11934 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11935 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11936 11937 unsigned DestReg = MI->getOperand(0).getReg(); 11938 MachineOperand &Base = MI->getOperand(1); 11939 MachineOperand &Scale = MI->getOperand(2); 11940 MachineOperand &Index = MI->getOperand(3); 11941 MachineOperand &Disp = MI->getOperand(4); 11942 MachineOperand &Segment = MI->getOperand(5); 11943 unsigned ArgSize = MI->getOperand(6).getImm(); 11944 unsigned ArgMode = MI->getOperand(7).getImm(); 11945 unsigned Align = MI->getOperand(8).getImm(); 11946 11947 // Memory Reference 11948 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11949 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11950 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11951 11952 // Machine Information 11953 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11954 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11955 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11956 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11957 DebugLoc DL = MI->getDebugLoc(); 11958 11959 // struct va_list { 11960 // i32 gp_offset 11961 // i32 fp_offset 11962 // i64 overflow_area (address) 11963 // i64 reg_save_area (address) 11964 // } 11965 // sizeof(va_list) = 24 11966 // alignment(va_list) = 8 11967 11968 unsigned TotalNumIntRegs = 6; 11969 unsigned TotalNumXMMRegs = 8; 11970 bool UseGPOffset = (ArgMode == 1); 11971 bool UseFPOffset = (ArgMode == 2); 11972 unsigned MaxOffset = TotalNumIntRegs * 8 + 11973 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11974 11975 /* Align ArgSize to a multiple of 8 */ 11976 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11977 bool NeedsAlign = (Align > 8); 11978 11979 MachineBasicBlock *thisMBB = MBB; 11980 MachineBasicBlock *overflowMBB; 11981 MachineBasicBlock *offsetMBB; 11982 MachineBasicBlock *endMBB; 11983 11984 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11985 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11986 unsigned OffsetReg = 0; 11987 11988 if (!UseGPOffset && !UseFPOffset) { 11989 // If we only pull from the overflow region, we don't create a branch. 11990 // We don't need to alter control flow. 11991 OffsetDestReg = 0; // unused 11992 OverflowDestReg = DestReg; 11993 11994 offsetMBB = NULL; 11995 overflowMBB = thisMBB; 11996 endMBB = thisMBB; 11997 } else { 11998 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11999 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 12000 // If not, pull from overflow_area. (branch to overflowMBB) 12001 // 12002 // thisMBB 12003 // | . 12004 // | . 12005 // offsetMBB overflowMBB 12006 // | . 12007 // | . 12008 // endMBB 12009 12010 // Registers for the PHI in endMBB 12011 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 12012 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 12013 12014 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12015 MachineFunction *MF = MBB->getParent(); 12016 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12017 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12018 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12019 12020 MachineFunction::iterator MBBIter = MBB; 12021 ++MBBIter; 12022 12023 // Insert the new basic blocks 12024 MF->insert(MBBIter, offsetMBB); 12025 MF->insert(MBBIter, overflowMBB); 12026 MF->insert(MBBIter, endMBB); 12027 12028 // Transfer the remainder of MBB and its successor edges to endMBB. 12029 endMBB->splice(endMBB->begin(), thisMBB, 12030 llvm::next(MachineBasicBlock::iterator(MI)), 12031 thisMBB->end()); 12032 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 12033 12034 // Make offsetMBB and overflowMBB successors of thisMBB 12035 thisMBB->addSuccessor(offsetMBB); 12036 thisMBB->addSuccessor(overflowMBB); 12037 12038 // endMBB is a successor of both offsetMBB and overflowMBB 12039 offsetMBB->addSuccessor(endMBB); 12040 overflowMBB->addSuccessor(endMBB); 12041 12042 // Load the offset value into a register 12043 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12044 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 12045 .addOperand(Base) 12046 .addOperand(Scale) 12047 .addOperand(Index) 12048 .addDisp(Disp, UseFPOffset ? 4 : 0) 12049 .addOperand(Segment) 12050 .setMemRefs(MMOBegin, MMOEnd); 12051 12052 // Check if there is enough room left to pull this argument. 12053 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 12054 .addReg(OffsetReg) 12055 .addImm(MaxOffset + 8 - ArgSizeA8); 12056 12057 // Branch to "overflowMBB" if offset >= max 12058 // Fall through to "offsetMBB" otherwise 12059 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 12060 .addMBB(overflowMBB); 12061 } 12062 12063 // In offsetMBB, emit code to use the reg_save_area. 12064 if (offsetMBB) { 12065 assert(OffsetReg != 0); 12066 12067 // Read the reg_save_area address. 12068 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 12069 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 12070 .addOperand(Base) 12071 .addOperand(Scale) 12072 .addOperand(Index) 12073 .addDisp(Disp, 16) 12074 .addOperand(Segment) 12075 .setMemRefs(MMOBegin, MMOEnd); 12076 12077 // Zero-extend the offset 12078 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 12079 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 12080 .addImm(0) 12081 .addReg(OffsetReg) 12082 .addImm(X86::sub_32bit); 12083 12084 // Add the offset to the reg_save_area to get the final address. 12085 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 12086 .addReg(OffsetReg64) 12087 .addReg(RegSaveReg); 12088 12089 // Compute the offset for the next argument 12090 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12091 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 12092 .addReg(OffsetReg) 12093 .addImm(UseFPOffset ? 16 : 8); 12094 12095 // Store it back into the va_list. 12096 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 12097 .addOperand(Base) 12098 .addOperand(Scale) 12099 .addOperand(Index) 12100 .addDisp(Disp, UseFPOffset ? 4 : 0) 12101 .addOperand(Segment) 12102 .addReg(NextOffsetReg) 12103 .setMemRefs(MMOBegin, MMOEnd); 12104 12105 // Jump to endMBB 12106 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 12107 .addMBB(endMBB); 12108 } 12109 12110 // 12111 // Emit code to use overflow area 12112 // 12113 12114 // Load the overflow_area address into a register. 12115 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 12116 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 12117 .addOperand(Base) 12118 .addOperand(Scale) 12119 .addOperand(Index) 12120 .addDisp(Disp, 8) 12121 .addOperand(Segment) 12122 .setMemRefs(MMOBegin, MMOEnd); 12123 12124 // If we need to align it, do so. Otherwise, just copy the address 12125 // to OverflowDestReg. 12126 if (NeedsAlign) { 12127 // Align the overflow address 12128 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12129 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12130 12131 // aligned_addr = (addr + (align-1)) & ~(align-1) 12132 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12133 .addReg(OverflowAddrReg) 12134 .addImm(Align-1); 12135 12136 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12137 .addReg(TmpReg) 12138 .addImm(~(uint64_t)(Align-1)); 12139 } else { 12140 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12141 .addReg(OverflowAddrReg); 12142 } 12143 12144 // Compute the next overflow address after this argument. 12145 // (the overflow address should be kept 8-byte aligned) 12146 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12147 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12148 .addReg(OverflowDestReg) 12149 .addImm(ArgSizeA8); 12150 12151 // Store the new overflow address. 12152 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12153 .addOperand(Base) 12154 .addOperand(Scale) 12155 .addOperand(Index) 12156 .addDisp(Disp, 8) 12157 .addOperand(Segment) 12158 .addReg(NextAddrReg) 12159 .setMemRefs(MMOBegin, MMOEnd); 12160 12161 // If we branched, emit the PHI to the front of endMBB. 12162 if (offsetMBB) { 12163 BuildMI(*endMBB, endMBB->begin(), DL, 12164 TII->get(X86::PHI), DestReg) 12165 .addReg(OffsetDestReg).addMBB(offsetMBB) 12166 .addReg(OverflowDestReg).addMBB(overflowMBB); 12167 } 12168 12169 // Erase the pseudo instruction 12170 MI->eraseFromParent(); 12171 12172 return endMBB; 12173} 12174 12175MachineBasicBlock * 12176X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12177 MachineInstr *MI, 12178 MachineBasicBlock *MBB) const { 12179 // Emit code to save XMM registers to the stack. The ABI says that the 12180 // number of registers to save is given in %al, so it's theoretically 12181 // possible to do an indirect jump trick to avoid saving all of them, 12182 // however this code takes a simpler approach and just executes all 12183 // of the stores if %al is non-zero. It's less code, and it's probably 12184 // easier on the hardware branch predictor, and stores aren't all that 12185 // expensive anyway. 12186 12187 // Create the new basic blocks. One block contains all the XMM stores, 12188 // and one block is the final destination regardless of whether any 12189 // stores were performed. 12190 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12191 MachineFunction *F = MBB->getParent(); 12192 MachineFunction::iterator MBBIter = MBB; 12193 ++MBBIter; 12194 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12195 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12196 F->insert(MBBIter, XMMSaveMBB); 12197 F->insert(MBBIter, EndMBB); 12198 12199 // Transfer the remainder of MBB and its successor edges to EndMBB. 12200 EndMBB->splice(EndMBB->begin(), MBB, 12201 llvm::next(MachineBasicBlock::iterator(MI)), 12202 MBB->end()); 12203 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12204 12205 // The original block will now fall through to the XMM save block. 12206 MBB->addSuccessor(XMMSaveMBB); 12207 // The XMMSaveMBB will fall through to the end block. 12208 XMMSaveMBB->addSuccessor(EndMBB); 12209 12210 // Now add the instructions. 12211 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12212 DebugLoc DL = MI->getDebugLoc(); 12213 12214 unsigned CountReg = MI->getOperand(0).getReg(); 12215 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12216 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12217 12218 if (!Subtarget->isTargetWin64()) { 12219 // If %al is 0, branch around the XMM save block. 12220 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12221 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12222 MBB->addSuccessor(EndMBB); 12223 } 12224 12225 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12226 // In the XMM save block, save all the XMM argument registers. 12227 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12228 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12229 MachineMemOperand *MMO = 12230 F->getMachineMemOperand( 12231 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12232 MachineMemOperand::MOStore, 12233 /*Size=*/16, /*Align=*/16); 12234 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12235 .addFrameIndex(RegSaveFrameIndex) 12236 .addImm(/*Scale=*/1) 12237 .addReg(/*IndexReg=*/0) 12238 .addImm(/*Disp=*/Offset) 12239 .addReg(/*Segment=*/0) 12240 .addReg(MI->getOperand(i).getReg()) 12241 .addMemOperand(MMO); 12242 } 12243 12244 MI->eraseFromParent(); // The pseudo instruction is gone now. 12245 12246 return EndMBB; 12247} 12248 12249// The EFLAGS operand of SelectItr might be missing a kill marker 12250// because there were multiple uses of EFLAGS, and ISel didn't know 12251// which to mark. Figure out whether SelectItr should have had a 12252// kill marker, and set it if it should. Returns the correct kill 12253// marker value. 12254static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12255 MachineBasicBlock* BB, 12256 const TargetRegisterInfo* TRI) { 12257 // Scan forward through BB for a use/def of EFLAGS. 12258 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12259 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12260 const MachineInstr& mi = *miI; 12261 if (mi.readsRegister(X86::EFLAGS)) 12262 return false; 12263 if (mi.definesRegister(X86::EFLAGS)) 12264 break; // Should have kill-flag - update below. 12265 } 12266 12267 // If we hit the end of the block, check whether EFLAGS is live into a 12268 // successor. 12269 if (miI == BB->end()) { 12270 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12271 sEnd = BB->succ_end(); 12272 sItr != sEnd; ++sItr) { 12273 MachineBasicBlock* succ = *sItr; 12274 if (succ->isLiveIn(X86::EFLAGS)) 12275 return false; 12276 } 12277 } 12278 12279 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12280 // out. SelectMI should have a kill flag on EFLAGS. 12281 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12282 return true; 12283} 12284 12285MachineBasicBlock * 12286X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12287 MachineBasicBlock *BB) const { 12288 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12289 DebugLoc DL = MI->getDebugLoc(); 12290 12291 // To "insert" a SELECT_CC instruction, we actually have to insert the 12292 // diamond control-flow pattern. The incoming instruction knows the 12293 // destination vreg to set, the condition code register to branch on, the 12294 // true/false values to select between, and a branch opcode to use. 12295 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12296 MachineFunction::iterator It = BB; 12297 ++It; 12298 12299 // thisMBB: 12300 // ... 12301 // TrueVal = ... 12302 // cmpTY ccX, r1, r2 12303 // bCC copy1MBB 12304 // fallthrough --> copy0MBB 12305 MachineBasicBlock *thisMBB = BB; 12306 MachineFunction *F = BB->getParent(); 12307 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12308 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12309 F->insert(It, copy0MBB); 12310 F->insert(It, sinkMBB); 12311 12312 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12313 // live into the sink and copy blocks. 12314 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12315 if (!MI->killsRegister(X86::EFLAGS) && 12316 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12317 copy0MBB->addLiveIn(X86::EFLAGS); 12318 sinkMBB->addLiveIn(X86::EFLAGS); 12319 } 12320 12321 // Transfer the remainder of BB and its successor edges to sinkMBB. 12322 sinkMBB->splice(sinkMBB->begin(), BB, 12323 llvm::next(MachineBasicBlock::iterator(MI)), 12324 BB->end()); 12325 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12326 12327 // Add the true and fallthrough blocks as its successors. 12328 BB->addSuccessor(copy0MBB); 12329 BB->addSuccessor(sinkMBB); 12330 12331 // Create the conditional branch instruction. 12332 unsigned Opc = 12333 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12334 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12335 12336 // copy0MBB: 12337 // %FalseValue = ... 12338 // # fallthrough to sinkMBB 12339 copy0MBB->addSuccessor(sinkMBB); 12340 12341 // sinkMBB: 12342 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12343 // ... 12344 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12345 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12346 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12347 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12348 12349 MI->eraseFromParent(); // The pseudo instruction is gone now. 12350 return sinkMBB; 12351} 12352 12353MachineBasicBlock * 12354X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12355 bool Is64Bit) const { 12356 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12357 DebugLoc DL = MI->getDebugLoc(); 12358 MachineFunction *MF = BB->getParent(); 12359 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12360 12361 assert(getTargetMachine().Options.EnableSegmentedStacks); 12362 12363 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12364 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12365 12366 // BB: 12367 // ... [Till the alloca] 12368 // If stacklet is not large enough, jump to mallocMBB 12369 // 12370 // bumpMBB: 12371 // Allocate by subtracting from RSP 12372 // Jump to continueMBB 12373 // 12374 // mallocMBB: 12375 // Allocate by call to runtime 12376 // 12377 // continueMBB: 12378 // ... 12379 // [rest of original BB] 12380 // 12381 12382 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12383 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12384 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12385 12386 MachineRegisterInfo &MRI = MF->getRegInfo(); 12387 const TargetRegisterClass *AddrRegClass = 12388 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12389 12390 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12391 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12392 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12393 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12394 sizeVReg = MI->getOperand(1).getReg(), 12395 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12396 12397 MachineFunction::iterator MBBIter = BB; 12398 ++MBBIter; 12399 12400 MF->insert(MBBIter, bumpMBB); 12401 MF->insert(MBBIter, mallocMBB); 12402 MF->insert(MBBIter, continueMBB); 12403 12404 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12405 (MachineBasicBlock::iterator(MI)), BB->end()); 12406 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12407 12408 // Add code to the main basic block to check if the stack limit has been hit, 12409 // and if so, jump to mallocMBB otherwise to bumpMBB. 12410 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12411 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12412 .addReg(tmpSPVReg).addReg(sizeVReg); 12413 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12414 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12415 .addReg(SPLimitVReg); 12416 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12417 12418 // bumpMBB simply decreases the stack pointer, since we know the current 12419 // stacklet has enough space. 12420 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12421 .addReg(SPLimitVReg); 12422 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12423 .addReg(SPLimitVReg); 12424 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12425 12426 // Calls into a routine in libgcc to allocate more space from the heap. 12427 const uint32_t *RegMask = 12428 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12429 if (Is64Bit) { 12430 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12431 .addReg(sizeVReg); 12432 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12433 .addExternalSymbol("__morestack_allocate_stack_space") 12434 .addRegMask(RegMask) 12435 .addReg(X86::RDI, RegState::Implicit) 12436 .addReg(X86::RAX, RegState::ImplicitDefine); 12437 } else { 12438 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12439 .addImm(12); 12440 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12441 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12442 .addExternalSymbol("__morestack_allocate_stack_space") 12443 .addRegMask(RegMask) 12444 .addReg(X86::EAX, RegState::ImplicitDefine); 12445 } 12446 12447 if (!Is64Bit) 12448 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12449 .addImm(16); 12450 12451 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12452 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12453 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12454 12455 // Set up the CFG correctly. 12456 BB->addSuccessor(bumpMBB); 12457 BB->addSuccessor(mallocMBB); 12458 mallocMBB->addSuccessor(continueMBB); 12459 bumpMBB->addSuccessor(continueMBB); 12460 12461 // Take care of the PHI nodes. 12462 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12463 MI->getOperand(0).getReg()) 12464 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12465 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12466 12467 // Delete the original pseudo instruction. 12468 MI->eraseFromParent(); 12469 12470 // And we're done. 12471 return continueMBB; 12472} 12473 12474MachineBasicBlock * 12475X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12476 MachineBasicBlock *BB) const { 12477 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12478 DebugLoc DL = MI->getDebugLoc(); 12479 12480 assert(!Subtarget->isTargetEnvMacho()); 12481 12482 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12483 // non-trivial part is impdef of ESP. 12484 12485 if (Subtarget->isTargetWin64()) { 12486 if (Subtarget->isTargetCygMing()) { 12487 // ___chkstk(Mingw64): 12488 // Clobbers R10, R11, RAX and EFLAGS. 12489 // Updates RSP. 12490 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12491 .addExternalSymbol("___chkstk") 12492 .addReg(X86::RAX, RegState::Implicit) 12493 .addReg(X86::RSP, RegState::Implicit) 12494 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12495 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12496 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12497 } else { 12498 // __chkstk(MSVCRT): does not update stack pointer. 12499 // Clobbers R10, R11 and EFLAGS. 12500 // FIXME: RAX(allocated size) might be reused and not killed. 12501 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12502 .addExternalSymbol("__chkstk") 12503 .addReg(X86::RAX, RegState::Implicit) 12504 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12505 // RAX has the offset to subtracted from RSP. 12506 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12507 .addReg(X86::RSP) 12508 .addReg(X86::RAX); 12509 } 12510 } else { 12511 const char *StackProbeSymbol = 12512 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12513 12514 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12515 .addExternalSymbol(StackProbeSymbol) 12516 .addReg(X86::EAX, RegState::Implicit) 12517 .addReg(X86::ESP, RegState::Implicit) 12518 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12519 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12520 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12521 } 12522 12523 MI->eraseFromParent(); // The pseudo instruction is gone now. 12524 return BB; 12525} 12526 12527MachineBasicBlock * 12528X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12529 MachineBasicBlock *BB) const { 12530 // This is pretty easy. We're taking the value that we received from 12531 // our load from the relocation, sticking it in either RDI (x86-64) 12532 // or EAX and doing an indirect call. The return value will then 12533 // be in the normal return register. 12534 const X86InstrInfo *TII 12535 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12536 DebugLoc DL = MI->getDebugLoc(); 12537 MachineFunction *F = BB->getParent(); 12538 12539 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12540 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12541 12542 // Get a register mask for the lowered call. 12543 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12544 // proper register mask. 12545 const uint32_t *RegMask = 12546 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12547 if (Subtarget->is64Bit()) { 12548 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12549 TII->get(X86::MOV64rm), X86::RDI) 12550 .addReg(X86::RIP) 12551 .addImm(0).addReg(0) 12552 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12553 MI->getOperand(3).getTargetFlags()) 12554 .addReg(0); 12555 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12556 addDirectMem(MIB, X86::RDI); 12557 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12558 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12559 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12560 TII->get(X86::MOV32rm), X86::EAX) 12561 .addReg(0) 12562 .addImm(0).addReg(0) 12563 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12564 MI->getOperand(3).getTargetFlags()) 12565 .addReg(0); 12566 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12567 addDirectMem(MIB, X86::EAX); 12568 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12569 } else { 12570 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12571 TII->get(X86::MOV32rm), X86::EAX) 12572 .addReg(TII->getGlobalBaseReg(F)) 12573 .addImm(0).addReg(0) 12574 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12575 MI->getOperand(3).getTargetFlags()) 12576 .addReg(0); 12577 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12578 addDirectMem(MIB, X86::EAX); 12579 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12580 } 12581 12582 MI->eraseFromParent(); // The pseudo instruction is gone now. 12583 return BB; 12584} 12585 12586MachineBasicBlock * 12587X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12588 MachineBasicBlock *BB) const { 12589 switch (MI->getOpcode()) { 12590 default: llvm_unreachable("Unexpected instr type to insert"); 12591 case X86::TAILJMPd64: 12592 case X86::TAILJMPr64: 12593 case X86::TAILJMPm64: 12594 llvm_unreachable("TAILJMP64 would not be touched here."); 12595 case X86::TCRETURNdi64: 12596 case X86::TCRETURNri64: 12597 case X86::TCRETURNmi64: 12598 return BB; 12599 case X86::WIN_ALLOCA: 12600 return EmitLoweredWinAlloca(MI, BB); 12601 case X86::SEG_ALLOCA_32: 12602 return EmitLoweredSegAlloca(MI, BB, false); 12603 case X86::SEG_ALLOCA_64: 12604 return EmitLoweredSegAlloca(MI, BB, true); 12605 case X86::TLSCall_32: 12606 case X86::TLSCall_64: 12607 return EmitLoweredTLSCall(MI, BB); 12608 case X86::CMOV_GR8: 12609 case X86::CMOV_FR32: 12610 case X86::CMOV_FR64: 12611 case X86::CMOV_V4F32: 12612 case X86::CMOV_V2F64: 12613 case X86::CMOV_V2I64: 12614 case X86::CMOV_V8F32: 12615 case X86::CMOV_V4F64: 12616 case X86::CMOV_V4I64: 12617 case X86::CMOV_GR16: 12618 case X86::CMOV_GR32: 12619 case X86::CMOV_RFP32: 12620 case X86::CMOV_RFP64: 12621 case X86::CMOV_RFP80: 12622 return EmitLoweredSelect(MI, BB); 12623 12624 case X86::FP32_TO_INT16_IN_MEM: 12625 case X86::FP32_TO_INT32_IN_MEM: 12626 case X86::FP32_TO_INT64_IN_MEM: 12627 case X86::FP64_TO_INT16_IN_MEM: 12628 case X86::FP64_TO_INT32_IN_MEM: 12629 case X86::FP64_TO_INT64_IN_MEM: 12630 case X86::FP80_TO_INT16_IN_MEM: 12631 case X86::FP80_TO_INT32_IN_MEM: 12632 case X86::FP80_TO_INT64_IN_MEM: { 12633 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12634 DebugLoc DL = MI->getDebugLoc(); 12635 12636 // Change the floating point control register to use "round towards zero" 12637 // mode when truncating to an integer value. 12638 MachineFunction *F = BB->getParent(); 12639 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12640 addFrameReference(BuildMI(*BB, MI, DL, 12641 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12642 12643 // Load the old value of the high byte of the control word... 12644 unsigned OldCW = 12645 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 12646 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12647 CWFrameIdx); 12648 12649 // Set the high part to be round to zero... 12650 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12651 .addImm(0xC7F); 12652 12653 // Reload the modified control word now... 12654 addFrameReference(BuildMI(*BB, MI, DL, 12655 TII->get(X86::FLDCW16m)), CWFrameIdx); 12656 12657 // Restore the memory image of control word to original value 12658 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12659 .addReg(OldCW); 12660 12661 // Get the X86 opcode to use. 12662 unsigned Opc; 12663 switch (MI->getOpcode()) { 12664 default: llvm_unreachable("illegal opcode!"); 12665 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12666 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12667 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12668 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12669 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12670 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12671 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12672 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12673 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12674 } 12675 12676 X86AddressMode AM; 12677 MachineOperand &Op = MI->getOperand(0); 12678 if (Op.isReg()) { 12679 AM.BaseType = X86AddressMode::RegBase; 12680 AM.Base.Reg = Op.getReg(); 12681 } else { 12682 AM.BaseType = X86AddressMode::FrameIndexBase; 12683 AM.Base.FrameIndex = Op.getIndex(); 12684 } 12685 Op = MI->getOperand(1); 12686 if (Op.isImm()) 12687 AM.Scale = Op.getImm(); 12688 Op = MI->getOperand(2); 12689 if (Op.isImm()) 12690 AM.IndexReg = Op.getImm(); 12691 Op = MI->getOperand(3); 12692 if (Op.isGlobal()) { 12693 AM.GV = Op.getGlobal(); 12694 } else { 12695 AM.Disp = Op.getImm(); 12696 } 12697 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12698 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12699 12700 // Reload the original control word now. 12701 addFrameReference(BuildMI(*BB, MI, DL, 12702 TII->get(X86::FLDCW16m)), CWFrameIdx); 12703 12704 MI->eraseFromParent(); // The pseudo instruction is gone now. 12705 return BB; 12706 } 12707 // String/text processing lowering. 12708 case X86::PCMPISTRM128REG: 12709 case X86::VPCMPISTRM128REG: 12710 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12711 case X86::PCMPISTRM128MEM: 12712 case X86::VPCMPISTRM128MEM: 12713 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12714 case X86::PCMPESTRM128REG: 12715 case X86::VPCMPESTRM128REG: 12716 return EmitPCMP(MI, BB, 5, false /* in mem */); 12717 case X86::PCMPESTRM128MEM: 12718 case X86::VPCMPESTRM128MEM: 12719 return EmitPCMP(MI, BB, 5, true /* in mem */); 12720 12721 // Thread synchronization. 12722 case X86::MONITOR: 12723 return EmitMonitor(MI, BB); 12724 case X86::MWAIT: 12725 return EmitMwait(MI, BB); 12726 12727 // Atomic Lowering. 12728 case X86::ATOMAND32: 12729 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12730 X86::AND32ri, X86::MOV32rm, 12731 X86::LCMPXCHG32, 12732 X86::NOT32r, X86::EAX, 12733 &X86::GR32RegClass); 12734 case X86::ATOMOR32: 12735 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12736 X86::OR32ri, X86::MOV32rm, 12737 X86::LCMPXCHG32, 12738 X86::NOT32r, X86::EAX, 12739 &X86::GR32RegClass); 12740 case X86::ATOMXOR32: 12741 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12742 X86::XOR32ri, X86::MOV32rm, 12743 X86::LCMPXCHG32, 12744 X86::NOT32r, X86::EAX, 12745 &X86::GR32RegClass); 12746 case X86::ATOMNAND32: 12747 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12748 X86::AND32ri, X86::MOV32rm, 12749 X86::LCMPXCHG32, 12750 X86::NOT32r, X86::EAX, 12751 &X86::GR32RegClass, true); 12752 case X86::ATOMMIN32: 12753 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12754 case X86::ATOMMAX32: 12755 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12756 case X86::ATOMUMIN32: 12757 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12758 case X86::ATOMUMAX32: 12759 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12760 12761 case X86::ATOMAND16: 12762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12763 X86::AND16ri, X86::MOV16rm, 12764 X86::LCMPXCHG16, 12765 X86::NOT16r, X86::AX, 12766 &X86::GR16RegClass); 12767 case X86::ATOMOR16: 12768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12769 X86::OR16ri, X86::MOV16rm, 12770 X86::LCMPXCHG16, 12771 X86::NOT16r, X86::AX, 12772 &X86::GR16RegClass); 12773 case X86::ATOMXOR16: 12774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12775 X86::XOR16ri, X86::MOV16rm, 12776 X86::LCMPXCHG16, 12777 X86::NOT16r, X86::AX, 12778 &X86::GR16RegClass); 12779 case X86::ATOMNAND16: 12780 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12781 X86::AND16ri, X86::MOV16rm, 12782 X86::LCMPXCHG16, 12783 X86::NOT16r, X86::AX, 12784 &X86::GR16RegClass, true); 12785 case X86::ATOMMIN16: 12786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12787 case X86::ATOMMAX16: 12788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12789 case X86::ATOMUMIN16: 12790 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12791 case X86::ATOMUMAX16: 12792 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12793 12794 case X86::ATOMAND8: 12795 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12796 X86::AND8ri, X86::MOV8rm, 12797 X86::LCMPXCHG8, 12798 X86::NOT8r, X86::AL, 12799 &X86::GR8RegClass); 12800 case X86::ATOMOR8: 12801 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12802 X86::OR8ri, X86::MOV8rm, 12803 X86::LCMPXCHG8, 12804 X86::NOT8r, X86::AL, 12805 &X86::GR8RegClass); 12806 case X86::ATOMXOR8: 12807 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12808 X86::XOR8ri, X86::MOV8rm, 12809 X86::LCMPXCHG8, 12810 X86::NOT8r, X86::AL, 12811 &X86::GR8RegClass); 12812 case X86::ATOMNAND8: 12813 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12814 X86::AND8ri, X86::MOV8rm, 12815 X86::LCMPXCHG8, 12816 X86::NOT8r, X86::AL, 12817 &X86::GR8RegClass, true); 12818 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12819 // This group is for 64-bit host. 12820 case X86::ATOMAND64: 12821 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12822 X86::AND64ri32, X86::MOV64rm, 12823 X86::LCMPXCHG64, 12824 X86::NOT64r, X86::RAX, 12825 &X86::GR64RegClass); 12826 case X86::ATOMOR64: 12827 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12828 X86::OR64ri32, X86::MOV64rm, 12829 X86::LCMPXCHG64, 12830 X86::NOT64r, X86::RAX, 12831 &X86::GR64RegClass); 12832 case X86::ATOMXOR64: 12833 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12834 X86::XOR64ri32, X86::MOV64rm, 12835 X86::LCMPXCHG64, 12836 X86::NOT64r, X86::RAX, 12837 &X86::GR64RegClass); 12838 case X86::ATOMNAND64: 12839 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12840 X86::AND64ri32, X86::MOV64rm, 12841 X86::LCMPXCHG64, 12842 X86::NOT64r, X86::RAX, 12843 &X86::GR64RegClass, true); 12844 case X86::ATOMMIN64: 12845 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12846 case X86::ATOMMAX64: 12847 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12848 case X86::ATOMUMIN64: 12849 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12850 case X86::ATOMUMAX64: 12851 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12852 12853 // This group does 64-bit operations on a 32-bit host. 12854 case X86::ATOMAND6432: 12855 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12856 X86::AND32rr, X86::AND32rr, 12857 X86::AND32ri, X86::AND32ri, 12858 false); 12859 case X86::ATOMOR6432: 12860 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12861 X86::OR32rr, X86::OR32rr, 12862 X86::OR32ri, X86::OR32ri, 12863 false); 12864 case X86::ATOMXOR6432: 12865 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12866 X86::XOR32rr, X86::XOR32rr, 12867 X86::XOR32ri, X86::XOR32ri, 12868 false); 12869 case X86::ATOMNAND6432: 12870 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12871 X86::AND32rr, X86::AND32rr, 12872 X86::AND32ri, X86::AND32ri, 12873 true); 12874 case X86::ATOMADD6432: 12875 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12876 X86::ADD32rr, X86::ADC32rr, 12877 X86::ADD32ri, X86::ADC32ri, 12878 false); 12879 case X86::ATOMSUB6432: 12880 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12881 X86::SUB32rr, X86::SBB32rr, 12882 X86::SUB32ri, X86::SBB32ri, 12883 false); 12884 case X86::ATOMSWAP6432: 12885 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12886 X86::MOV32rr, X86::MOV32rr, 12887 X86::MOV32ri, X86::MOV32ri, 12888 false); 12889 case X86::VASTART_SAVE_XMM_REGS: 12890 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12891 12892 case X86::VAARG_64: 12893 return EmitVAARG64WithCustomInserter(MI, BB); 12894 } 12895} 12896 12897//===----------------------------------------------------------------------===// 12898// X86 Optimization Hooks 12899//===----------------------------------------------------------------------===// 12900 12901void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12902 APInt &KnownZero, 12903 APInt &KnownOne, 12904 const SelectionDAG &DAG, 12905 unsigned Depth) const { 12906 unsigned BitWidth = KnownZero.getBitWidth(); 12907 unsigned Opc = Op.getOpcode(); 12908 assert((Opc >= ISD::BUILTIN_OP_END || 12909 Opc == ISD::INTRINSIC_WO_CHAIN || 12910 Opc == ISD::INTRINSIC_W_CHAIN || 12911 Opc == ISD::INTRINSIC_VOID) && 12912 "Should use MaskedValueIsZero if you don't know whether Op" 12913 " is a target node!"); 12914 12915 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12916 switch (Opc) { 12917 default: break; 12918 case X86ISD::ADD: 12919 case X86ISD::SUB: 12920 case X86ISD::ADC: 12921 case X86ISD::SBB: 12922 case X86ISD::SMUL: 12923 case X86ISD::UMUL: 12924 case X86ISD::INC: 12925 case X86ISD::DEC: 12926 case X86ISD::OR: 12927 case X86ISD::XOR: 12928 case X86ISD::AND: 12929 // These nodes' second result is a boolean. 12930 if (Op.getResNo() == 0) 12931 break; 12932 // Fallthrough 12933 case X86ISD::SETCC: 12934 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12935 break; 12936 case ISD::INTRINSIC_WO_CHAIN: { 12937 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12938 unsigned NumLoBits = 0; 12939 switch (IntId) { 12940 default: break; 12941 case Intrinsic::x86_sse_movmsk_ps: 12942 case Intrinsic::x86_avx_movmsk_ps_256: 12943 case Intrinsic::x86_sse2_movmsk_pd: 12944 case Intrinsic::x86_avx_movmsk_pd_256: 12945 case Intrinsic::x86_mmx_pmovmskb: 12946 case Intrinsic::x86_sse2_pmovmskb_128: 12947 case Intrinsic::x86_avx2_pmovmskb: { 12948 // High bits of movmskp{s|d}, pmovmskb are known zero. 12949 switch (IntId) { 12950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12951 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12952 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12953 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12954 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12955 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12956 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12957 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12958 } 12959 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12960 break; 12961 } 12962 } 12963 break; 12964 } 12965 } 12966} 12967 12968unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12969 unsigned Depth) const { 12970 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12971 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12972 return Op.getValueType().getScalarType().getSizeInBits(); 12973 12974 // Fallback case. 12975 return 1; 12976} 12977 12978/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12979/// node is a GlobalAddress + offset. 12980bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12981 const GlobalValue* &GA, 12982 int64_t &Offset) const { 12983 if (N->getOpcode() == X86ISD::Wrapper) { 12984 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12985 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12986 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12987 return true; 12988 } 12989 } 12990 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12991} 12992 12993/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12994/// same as extracting the high 128-bit part of 256-bit vector and then 12995/// inserting the result into the low part of a new 256-bit vector 12996static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12997 EVT VT = SVOp->getValueType(0); 12998 unsigned NumElems = VT.getVectorNumElements(); 12999 13000 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13001 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 13002 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 13003 SVOp->getMaskElt(j) >= 0) 13004 return false; 13005 13006 return true; 13007} 13008 13009/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 13010/// same as extracting the low 128-bit part of 256-bit vector and then 13011/// inserting the result into the high part of a new 256-bit vector 13012static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 13013 EVT VT = SVOp->getValueType(0); 13014 unsigned NumElems = VT.getVectorNumElements(); 13015 13016 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13017 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 13018 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 13019 SVOp->getMaskElt(j) >= 0) 13020 return false; 13021 13022 return true; 13023} 13024 13025/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 13026static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 13027 TargetLowering::DAGCombinerInfo &DCI, 13028 const X86Subtarget* Subtarget) { 13029 DebugLoc dl = N->getDebugLoc(); 13030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 13031 SDValue V1 = SVOp->getOperand(0); 13032 SDValue V2 = SVOp->getOperand(1); 13033 EVT VT = SVOp->getValueType(0); 13034 unsigned NumElems = VT.getVectorNumElements(); 13035 13036 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 13037 V2.getOpcode() == ISD::CONCAT_VECTORS) { 13038 // 13039 // 0,0,0,... 13040 // | 13041 // V UNDEF BUILD_VECTOR UNDEF 13042 // \ / \ / 13043 // CONCAT_VECTOR CONCAT_VECTOR 13044 // \ / 13045 // \ / 13046 // RESULT: V + zero extended 13047 // 13048 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 13049 V2.getOperand(1).getOpcode() != ISD::UNDEF || 13050 V1.getOperand(1).getOpcode() != ISD::UNDEF) 13051 return SDValue(); 13052 13053 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 13054 return SDValue(); 13055 13056 // To match the shuffle mask, the first half of the mask should 13057 // be exactly the first vector, and all the rest a splat with the 13058 // first element of the second one. 13059 for (unsigned i = 0; i != NumElems/2; ++i) 13060 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 13061 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 13062 return SDValue(); 13063 13064 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 13065 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 13066 if (Ld->hasNUsesOfValue(1, 0)) { 13067 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 13068 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 13069 SDValue ResNode = 13070 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 13071 Ld->getMemoryVT(), 13072 Ld->getPointerInfo(), 13073 Ld->getAlignment(), 13074 false/*isVolatile*/, true/*ReadMem*/, 13075 false/*WriteMem*/); 13076 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 13077 } 13078 } 13079 13080 // Emit a zeroed vector and insert the desired subvector on its 13081 // first half. 13082 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 13083 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 13084 return DCI.CombineTo(N, InsV); 13085 } 13086 13087 //===--------------------------------------------------------------------===// 13088 // Combine some shuffles into subvector extracts and inserts: 13089 // 13090 13091 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13092 if (isShuffleHigh128VectorInsertLow(SVOp)) { 13093 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 13094 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 13095 return DCI.CombineTo(N, InsV); 13096 } 13097 13098 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13099 if (isShuffleLow128VectorInsertHigh(SVOp)) { 13100 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 13101 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 13102 return DCI.CombineTo(N, InsV); 13103 } 13104 13105 return SDValue(); 13106} 13107 13108/// PerformShuffleCombine - Performs several different shuffle combines. 13109static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 13110 TargetLowering::DAGCombinerInfo &DCI, 13111 const X86Subtarget *Subtarget) { 13112 DebugLoc dl = N->getDebugLoc(); 13113 EVT VT = N->getValueType(0); 13114 13115 // Don't create instructions with illegal types after legalize types has run. 13116 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13117 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13118 return SDValue(); 13119 13120 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13121 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 13122 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13123 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 13124 13125 // Only handle 128 wide vector from here on. 13126 if (VT.getSizeInBits() != 128) 13127 return SDValue(); 13128 13129 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13130 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13131 // consecutive, non-overlapping, and in the right order. 13132 SmallVector<SDValue, 16> Elts; 13133 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13134 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13135 13136 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13137} 13138 13139 13140/// DCI, PerformTruncateCombine - Converts truncate operation to 13141/// a sequence of vector shuffle operations. 13142/// It is possible when we truncate 256-bit vector to 128-bit vector 13143 13144SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 13145 DAGCombinerInfo &DCI) const { 13146 if (!DCI.isBeforeLegalizeOps()) 13147 return SDValue(); 13148 13149 if (!Subtarget->hasAVX()) 13150 return SDValue(); 13151 13152 EVT VT = N->getValueType(0); 13153 SDValue Op = N->getOperand(0); 13154 EVT OpVT = Op.getValueType(); 13155 DebugLoc dl = N->getDebugLoc(); 13156 13157 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 13158 13159 if (Subtarget->hasAVX2()) { 13160 // AVX2: v4i64 -> v4i32 13161 13162 // VPERMD 13163 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 13164 13165 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op); 13166 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32), 13167 ShufMask); 13168 13169 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, 13170 DAG.getIntPtrConstant(0)); 13171 } 13172 13173 // AVX: v4i64 -> v4i32 13174 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13175 DAG.getIntPtrConstant(0)); 13176 13177 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13178 DAG.getIntPtrConstant(2)); 13179 13180 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13181 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13182 13183 // PSHUFD 13184 static const int ShufMask1[] = {0, 2, 0, 0}; 13185 13186 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1); 13187 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1); 13188 13189 // MOVLHPS 13190 static const int ShufMask2[] = {0, 1, 4, 5}; 13191 13192 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 13193 } 13194 13195 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 13196 13197 if (Subtarget->hasAVX2()) { 13198 // AVX2: v8i32 -> v8i16 13199 13200 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op); 13201 13202 // PSHUFB 13203 SmallVector<SDValue,32> pshufbMask; 13204 for (unsigned i = 0; i < 2; ++i) { 13205 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 13206 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 13207 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 13208 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 13209 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 13210 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 13211 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 13212 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 13213 for (unsigned j = 0; j < 8; ++j) 13214 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 13215 } 13216 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, 13217 &pshufbMask[0], 32); 13218 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV); 13219 13220 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op); 13221 13222 static const int ShufMask[] = {0, 2, -1, -1}; 13223 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64), 13224 &ShufMask[0]); 13225 13226 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13227 DAG.getIntPtrConstant(0)); 13228 13229 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 13230 } 13231 13232 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13233 DAG.getIntPtrConstant(0)); 13234 13235 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13236 DAG.getIntPtrConstant(4)); 13237 13238 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13239 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13240 13241 // PSHUFB 13242 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13243 -1, -1, -1, -1, -1, -1, -1, -1}; 13244 13245 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8), 13246 ShufMask1); 13247 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8), 13248 ShufMask1); 13249 13250 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13251 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13252 13253 // MOVLHPS 13254 static const int ShufMask2[] = {0, 1, 4, 5}; 13255 13256 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13257 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13258 } 13259 13260 return SDValue(); 13261} 13262 13263/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13264/// specific shuffle of a load can be folded into a single element load. 13265/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13266/// shuffles have been customed lowered so we need to handle those here. 13267static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13268 TargetLowering::DAGCombinerInfo &DCI) { 13269 if (DCI.isBeforeLegalizeOps()) 13270 return SDValue(); 13271 13272 SDValue InVec = N->getOperand(0); 13273 SDValue EltNo = N->getOperand(1); 13274 13275 if (!isa<ConstantSDNode>(EltNo)) 13276 return SDValue(); 13277 13278 EVT VT = InVec.getValueType(); 13279 13280 bool HasShuffleIntoBitcast = false; 13281 if (InVec.getOpcode() == ISD::BITCAST) { 13282 // Don't duplicate a load with other uses. 13283 if (!InVec.hasOneUse()) 13284 return SDValue(); 13285 EVT BCVT = InVec.getOperand(0).getValueType(); 13286 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13287 return SDValue(); 13288 InVec = InVec.getOperand(0); 13289 HasShuffleIntoBitcast = true; 13290 } 13291 13292 if (!isTargetShuffle(InVec.getOpcode())) 13293 return SDValue(); 13294 13295 // Don't duplicate a load with other uses. 13296 if (!InVec.hasOneUse()) 13297 return SDValue(); 13298 13299 SmallVector<int, 16> ShuffleMask; 13300 bool UnaryShuffle; 13301 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask, 13302 UnaryShuffle)) 13303 return SDValue(); 13304 13305 // Select the input vector, guarding against out of range extract vector. 13306 unsigned NumElems = VT.getVectorNumElements(); 13307 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13308 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13309 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13310 : InVec.getOperand(1); 13311 13312 // If inputs to shuffle are the same for both ops, then allow 2 uses 13313 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13314 13315 if (LdNode.getOpcode() == ISD::BITCAST) { 13316 // Don't duplicate a load with other uses. 13317 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13318 return SDValue(); 13319 13320 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13321 LdNode = LdNode.getOperand(0); 13322 } 13323 13324 if (!ISD::isNormalLoad(LdNode.getNode())) 13325 return SDValue(); 13326 13327 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13328 13329 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13330 return SDValue(); 13331 13332 if (HasShuffleIntoBitcast) { 13333 // If there's a bitcast before the shuffle, check if the load type and 13334 // alignment is valid. 13335 unsigned Align = LN0->getAlignment(); 13336 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13337 unsigned NewAlign = TLI.getTargetData()-> 13338 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13339 13340 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13341 return SDValue(); 13342 } 13343 13344 // All checks match so transform back to vector_shuffle so that DAG combiner 13345 // can finish the job 13346 DebugLoc dl = N->getDebugLoc(); 13347 13348 // Create shuffle node taking into account the case that its a unary shuffle 13349 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13350 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13351 InVec.getOperand(0), Shuffle, 13352 &ShuffleMask[0]); 13353 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13354 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13355 EltNo); 13356} 13357 13358/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13359/// generation and convert it from being a bunch of shuffles and extracts 13360/// to a simple store and scalar loads to extract the elements. 13361static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13362 TargetLowering::DAGCombinerInfo &DCI) { 13363 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13364 if (NewOp.getNode()) 13365 return NewOp; 13366 13367 SDValue InputVector = N->getOperand(0); 13368 13369 // Only operate on vectors of 4 elements, where the alternative shuffling 13370 // gets to be more expensive. 13371 if (InputVector.getValueType() != MVT::v4i32) 13372 return SDValue(); 13373 13374 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13375 // single use which is a sign-extend or zero-extend, and all elements are 13376 // used. 13377 SmallVector<SDNode *, 4> Uses; 13378 unsigned ExtractedElements = 0; 13379 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13380 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13381 if (UI.getUse().getResNo() != InputVector.getResNo()) 13382 return SDValue(); 13383 13384 SDNode *Extract = *UI; 13385 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13386 return SDValue(); 13387 13388 if (Extract->getValueType(0) != MVT::i32) 13389 return SDValue(); 13390 if (!Extract->hasOneUse()) 13391 return SDValue(); 13392 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13393 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13394 return SDValue(); 13395 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13396 return SDValue(); 13397 13398 // Record which element was extracted. 13399 ExtractedElements |= 13400 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13401 13402 Uses.push_back(Extract); 13403 } 13404 13405 // If not all the elements were used, this may not be worthwhile. 13406 if (ExtractedElements != 15) 13407 return SDValue(); 13408 13409 // Ok, we've now decided to do the transformation. 13410 DebugLoc dl = InputVector.getDebugLoc(); 13411 13412 // Store the value to a temporary stack slot. 13413 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13414 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13415 MachinePointerInfo(), false, false, 0); 13416 13417 // Replace each use (extract) with a load of the appropriate element. 13418 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13419 UE = Uses.end(); UI != UE; ++UI) { 13420 SDNode *Extract = *UI; 13421 13422 // cOMpute the element's address. 13423 SDValue Idx = Extract->getOperand(1); 13424 unsigned EltSize = 13425 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13426 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13427 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13428 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13429 13430 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13431 StackPtr, OffsetVal); 13432 13433 // Load the scalar. 13434 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13435 ScalarAddr, MachinePointerInfo(), 13436 false, false, false, 0); 13437 13438 // Replace the exact with the load. 13439 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13440 } 13441 13442 // The replacement was made in place; don't return anything. 13443 return SDValue(); 13444} 13445 13446/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13447/// nodes. 13448static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13449 TargetLowering::DAGCombinerInfo &DCI, 13450 const X86Subtarget *Subtarget) { 13451 DebugLoc DL = N->getDebugLoc(); 13452 SDValue Cond = N->getOperand(0); 13453 // Get the LHS/RHS of the select. 13454 SDValue LHS = N->getOperand(1); 13455 SDValue RHS = N->getOperand(2); 13456 EVT VT = LHS.getValueType(); 13457 13458 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13459 // instructions match the semantics of the common C idiom x<y?x:y but not 13460 // x<=y?x:y, because of how they handle negative zero (which can be 13461 // ignored in unsafe-math mode). 13462 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13463 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13464 (Subtarget->hasSSE2() || 13465 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13466 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13467 13468 unsigned Opcode = 0; 13469 // Check for x CC y ? x : y. 13470 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13471 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13472 switch (CC) { 13473 default: break; 13474 case ISD::SETULT: 13475 // Converting this to a min would handle NaNs incorrectly, and swapping 13476 // the operands would cause it to handle comparisons between positive 13477 // and negative zero incorrectly. 13478 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13479 if (!DAG.getTarget().Options.UnsafeFPMath && 13480 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13481 break; 13482 std::swap(LHS, RHS); 13483 } 13484 Opcode = X86ISD::FMIN; 13485 break; 13486 case ISD::SETOLE: 13487 // Converting this to a min would handle comparisons between positive 13488 // and negative zero incorrectly. 13489 if (!DAG.getTarget().Options.UnsafeFPMath && 13490 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13491 break; 13492 Opcode = X86ISD::FMIN; 13493 break; 13494 case ISD::SETULE: 13495 // Converting this to a min would handle both negative zeros and NaNs 13496 // incorrectly, but we can swap the operands to fix both. 13497 std::swap(LHS, RHS); 13498 case ISD::SETOLT: 13499 case ISD::SETLT: 13500 case ISD::SETLE: 13501 Opcode = X86ISD::FMIN; 13502 break; 13503 13504 case ISD::SETOGE: 13505 // Converting this to a max would handle comparisons between positive 13506 // and negative zero incorrectly. 13507 if (!DAG.getTarget().Options.UnsafeFPMath && 13508 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13509 break; 13510 Opcode = X86ISD::FMAX; 13511 break; 13512 case ISD::SETUGT: 13513 // Converting this to a max would handle NaNs incorrectly, and swapping 13514 // the operands would cause it to handle comparisons between positive 13515 // and negative zero incorrectly. 13516 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13517 if (!DAG.getTarget().Options.UnsafeFPMath && 13518 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13519 break; 13520 std::swap(LHS, RHS); 13521 } 13522 Opcode = X86ISD::FMAX; 13523 break; 13524 case ISD::SETUGE: 13525 // Converting this to a max would handle both negative zeros and NaNs 13526 // incorrectly, but we can swap the operands to fix both. 13527 std::swap(LHS, RHS); 13528 case ISD::SETOGT: 13529 case ISD::SETGT: 13530 case ISD::SETGE: 13531 Opcode = X86ISD::FMAX; 13532 break; 13533 } 13534 // Check for x CC y ? y : x -- a min/max with reversed arms. 13535 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13536 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13537 switch (CC) { 13538 default: break; 13539 case ISD::SETOGE: 13540 // Converting this to a min would handle comparisons between positive 13541 // and negative zero incorrectly, and swapping the operands would 13542 // cause it to handle NaNs incorrectly. 13543 if (!DAG.getTarget().Options.UnsafeFPMath && 13544 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13545 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13546 break; 13547 std::swap(LHS, RHS); 13548 } 13549 Opcode = X86ISD::FMIN; 13550 break; 13551 case ISD::SETUGT: 13552 // Converting this to a min would handle NaNs incorrectly. 13553 if (!DAG.getTarget().Options.UnsafeFPMath && 13554 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13555 break; 13556 Opcode = X86ISD::FMIN; 13557 break; 13558 case ISD::SETUGE: 13559 // Converting this to a min would handle both negative zeros and NaNs 13560 // incorrectly, but we can swap the operands to fix both. 13561 std::swap(LHS, RHS); 13562 case ISD::SETOGT: 13563 case ISD::SETGT: 13564 case ISD::SETGE: 13565 Opcode = X86ISD::FMIN; 13566 break; 13567 13568 case ISD::SETULT: 13569 // Converting this to a max would handle NaNs incorrectly. 13570 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13571 break; 13572 Opcode = X86ISD::FMAX; 13573 break; 13574 case ISD::SETOLE: 13575 // Converting this to a max would handle comparisons between positive 13576 // and negative zero incorrectly, and swapping the operands would 13577 // cause it to handle NaNs incorrectly. 13578 if (!DAG.getTarget().Options.UnsafeFPMath && 13579 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13580 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13581 break; 13582 std::swap(LHS, RHS); 13583 } 13584 Opcode = X86ISD::FMAX; 13585 break; 13586 case ISD::SETULE: 13587 // Converting this to a max would handle both negative zeros and NaNs 13588 // incorrectly, but we can swap the operands to fix both. 13589 std::swap(LHS, RHS); 13590 case ISD::SETOLT: 13591 case ISD::SETLT: 13592 case ISD::SETLE: 13593 Opcode = X86ISD::FMAX; 13594 break; 13595 } 13596 } 13597 13598 if (Opcode) 13599 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13600 } 13601 13602 // If this is a select between two integer constants, try to do some 13603 // optimizations. 13604 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13605 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13606 // Don't do this for crazy integer types. 13607 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13608 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13609 // so that TrueC (the true value) is larger than FalseC. 13610 bool NeedsCondInvert = false; 13611 13612 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13613 // Efficiently invertible. 13614 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13615 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13616 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13617 NeedsCondInvert = true; 13618 std::swap(TrueC, FalseC); 13619 } 13620 13621 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13622 if (FalseC->getAPIntValue() == 0 && 13623 TrueC->getAPIntValue().isPowerOf2()) { 13624 if (NeedsCondInvert) // Invert the condition if needed. 13625 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13626 DAG.getConstant(1, Cond.getValueType())); 13627 13628 // Zero extend the condition if needed. 13629 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13630 13631 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13632 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13633 DAG.getConstant(ShAmt, MVT::i8)); 13634 } 13635 13636 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13637 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13638 if (NeedsCondInvert) // Invert the condition if needed. 13639 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13640 DAG.getConstant(1, Cond.getValueType())); 13641 13642 // Zero extend the condition if needed. 13643 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13644 FalseC->getValueType(0), Cond); 13645 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13646 SDValue(FalseC, 0)); 13647 } 13648 13649 // Optimize cases that will turn into an LEA instruction. This requires 13650 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13651 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13652 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13653 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13654 13655 bool isFastMultiplier = false; 13656 if (Diff < 10) { 13657 switch ((unsigned char)Diff) { 13658 default: break; 13659 case 1: // result = add base, cond 13660 case 2: // result = lea base( , cond*2) 13661 case 3: // result = lea base(cond, cond*2) 13662 case 4: // result = lea base( , cond*4) 13663 case 5: // result = lea base(cond, cond*4) 13664 case 8: // result = lea base( , cond*8) 13665 case 9: // result = lea base(cond, cond*8) 13666 isFastMultiplier = true; 13667 break; 13668 } 13669 } 13670 13671 if (isFastMultiplier) { 13672 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13673 if (NeedsCondInvert) // Invert the condition if needed. 13674 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13675 DAG.getConstant(1, Cond.getValueType())); 13676 13677 // Zero extend the condition if needed. 13678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13679 Cond); 13680 // Scale the condition by the difference. 13681 if (Diff != 1) 13682 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13683 DAG.getConstant(Diff, Cond.getValueType())); 13684 13685 // Add the base if non-zero. 13686 if (FalseC->getAPIntValue() != 0) 13687 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13688 SDValue(FalseC, 0)); 13689 return Cond; 13690 } 13691 } 13692 } 13693 } 13694 13695 // Canonicalize max and min: 13696 // (x > y) ? x : y -> (x >= y) ? x : y 13697 // (x < y) ? x : y -> (x <= y) ? x : y 13698 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13699 // the need for an extra compare 13700 // against zero. e.g. 13701 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13702 // subl %esi, %edi 13703 // testl %edi, %edi 13704 // movl $0, %eax 13705 // cmovgl %edi, %eax 13706 // => 13707 // xorl %eax, %eax 13708 // subl %esi, $edi 13709 // cmovsl %eax, %edi 13710 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13711 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13712 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13713 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13714 switch (CC) { 13715 default: break; 13716 case ISD::SETLT: 13717 case ISD::SETGT: { 13718 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13719 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13720 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13721 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13722 } 13723 } 13724 } 13725 13726 // If we know that this node is legal then we know that it is going to be 13727 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13728 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13729 // to simplify previous instructions. 13730 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13731 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13732 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) { 13733 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13734 13735 // Don't optimize vector selects that map to mask-registers. 13736 if (BitWidth == 1) 13737 return SDValue(); 13738 13739 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13740 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13741 13742 APInt KnownZero, KnownOne; 13743 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13744 DCI.isBeforeLegalizeOps()); 13745 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13746 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13747 DCI.CommitTargetLoweringOpt(TLO); 13748 } 13749 13750 return SDValue(); 13751} 13752 13753/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13754static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13755 TargetLowering::DAGCombinerInfo &DCI) { 13756 DebugLoc DL = N->getDebugLoc(); 13757 13758 // If the flag operand isn't dead, don't touch this CMOV. 13759 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13760 return SDValue(); 13761 13762 SDValue FalseOp = N->getOperand(0); 13763 SDValue TrueOp = N->getOperand(1); 13764 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13765 SDValue Cond = N->getOperand(3); 13766 if (CC == X86::COND_E || CC == X86::COND_NE) { 13767 switch (Cond.getOpcode()) { 13768 default: break; 13769 case X86ISD::BSR: 13770 case X86ISD::BSF: 13771 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13772 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13773 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13774 } 13775 } 13776 13777 // If this is a select between two integer constants, try to do some 13778 // optimizations. Note that the operands are ordered the opposite of SELECT 13779 // operands. 13780 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13781 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13782 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13783 // larger than FalseC (the false value). 13784 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13785 CC = X86::GetOppositeBranchCondition(CC); 13786 std::swap(TrueC, FalseC); 13787 } 13788 13789 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13790 // This is efficient for any integer data type (including i8/i16) and 13791 // shift amount. 13792 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13793 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13794 DAG.getConstant(CC, MVT::i8), Cond); 13795 13796 // Zero extend the condition if needed. 13797 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13798 13799 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13800 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13801 DAG.getConstant(ShAmt, MVT::i8)); 13802 if (N->getNumValues() == 2) // Dead flag value? 13803 return DCI.CombineTo(N, Cond, SDValue()); 13804 return Cond; 13805 } 13806 13807 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13808 // for any integer data type, including i8/i16. 13809 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13810 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13811 DAG.getConstant(CC, MVT::i8), Cond); 13812 13813 // Zero extend the condition if needed. 13814 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13815 FalseC->getValueType(0), Cond); 13816 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13817 SDValue(FalseC, 0)); 13818 13819 if (N->getNumValues() == 2) // Dead flag value? 13820 return DCI.CombineTo(N, Cond, SDValue()); 13821 return Cond; 13822 } 13823 13824 // Optimize cases that will turn into an LEA instruction. This requires 13825 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13826 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13827 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13828 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13829 13830 bool isFastMultiplier = false; 13831 if (Diff < 10) { 13832 switch ((unsigned char)Diff) { 13833 default: break; 13834 case 1: // result = add base, cond 13835 case 2: // result = lea base( , cond*2) 13836 case 3: // result = lea base(cond, cond*2) 13837 case 4: // result = lea base( , cond*4) 13838 case 5: // result = lea base(cond, cond*4) 13839 case 8: // result = lea base( , cond*8) 13840 case 9: // result = lea base(cond, cond*8) 13841 isFastMultiplier = true; 13842 break; 13843 } 13844 } 13845 13846 if (isFastMultiplier) { 13847 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13848 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13849 DAG.getConstant(CC, MVT::i8), Cond); 13850 // Zero extend the condition if needed. 13851 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13852 Cond); 13853 // Scale the condition by the difference. 13854 if (Diff != 1) 13855 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13856 DAG.getConstant(Diff, Cond.getValueType())); 13857 13858 // Add the base if non-zero. 13859 if (FalseC->getAPIntValue() != 0) 13860 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13861 SDValue(FalseC, 0)); 13862 if (N->getNumValues() == 2) // Dead flag value? 13863 return DCI.CombineTo(N, Cond, SDValue()); 13864 return Cond; 13865 } 13866 } 13867 } 13868 } 13869 return SDValue(); 13870} 13871 13872 13873/// PerformMulCombine - Optimize a single multiply with constant into two 13874/// in order to implement it with two cheaper instructions, e.g. 13875/// LEA + SHL, LEA + LEA. 13876static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13877 TargetLowering::DAGCombinerInfo &DCI) { 13878 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13879 return SDValue(); 13880 13881 EVT VT = N->getValueType(0); 13882 if (VT != MVT::i64) 13883 return SDValue(); 13884 13885 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13886 if (!C) 13887 return SDValue(); 13888 uint64_t MulAmt = C->getZExtValue(); 13889 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13890 return SDValue(); 13891 13892 uint64_t MulAmt1 = 0; 13893 uint64_t MulAmt2 = 0; 13894 if ((MulAmt % 9) == 0) { 13895 MulAmt1 = 9; 13896 MulAmt2 = MulAmt / 9; 13897 } else if ((MulAmt % 5) == 0) { 13898 MulAmt1 = 5; 13899 MulAmt2 = MulAmt / 5; 13900 } else if ((MulAmt % 3) == 0) { 13901 MulAmt1 = 3; 13902 MulAmt2 = MulAmt / 3; 13903 } 13904 if (MulAmt2 && 13905 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13906 DebugLoc DL = N->getDebugLoc(); 13907 13908 if (isPowerOf2_64(MulAmt2) && 13909 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13910 // If second multiplifer is pow2, issue it first. We want the multiply by 13911 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13912 // is an add. 13913 std::swap(MulAmt1, MulAmt2); 13914 13915 SDValue NewMul; 13916 if (isPowerOf2_64(MulAmt1)) 13917 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13918 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13919 else 13920 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13921 DAG.getConstant(MulAmt1, VT)); 13922 13923 if (isPowerOf2_64(MulAmt2)) 13924 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13925 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13926 else 13927 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13928 DAG.getConstant(MulAmt2, VT)); 13929 13930 // Do not add new nodes to DAG combiner worklist. 13931 DCI.CombineTo(N, NewMul, false); 13932 } 13933 return SDValue(); 13934} 13935 13936static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13937 SDValue N0 = N->getOperand(0); 13938 SDValue N1 = N->getOperand(1); 13939 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13940 EVT VT = N0.getValueType(); 13941 13942 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13943 // since the result of setcc_c is all zero's or all ones. 13944 if (VT.isInteger() && !VT.isVector() && 13945 N1C && N0.getOpcode() == ISD::AND && 13946 N0.getOperand(1).getOpcode() == ISD::Constant) { 13947 SDValue N00 = N0.getOperand(0); 13948 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13949 ((N00.getOpcode() == ISD::ANY_EXTEND || 13950 N00.getOpcode() == ISD::ZERO_EXTEND) && 13951 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13952 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13953 APInt ShAmt = N1C->getAPIntValue(); 13954 Mask = Mask.shl(ShAmt); 13955 if (Mask != 0) 13956 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13957 N00, DAG.getConstant(Mask, VT)); 13958 } 13959 } 13960 13961 13962 // Hardware support for vector shifts is sparse which makes us scalarize the 13963 // vector operations in many cases. Also, on sandybridge ADD is faster than 13964 // shl. 13965 // (shl V, 1) -> add V,V 13966 if (isSplatVector(N1.getNode())) { 13967 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13968 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13969 // We shift all of the values by one. In many cases we do not have 13970 // hardware support for this operation. This is better expressed as an ADD 13971 // of two values. 13972 if (N1C && (1 == N1C->getZExtValue())) { 13973 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13974 } 13975 } 13976 13977 return SDValue(); 13978} 13979 13980/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13981/// when possible. 13982static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13983 TargetLowering::DAGCombinerInfo &DCI, 13984 const X86Subtarget *Subtarget) { 13985 EVT VT = N->getValueType(0); 13986 if (N->getOpcode() == ISD::SHL) { 13987 SDValue V = PerformSHLCombine(N, DAG); 13988 if (V.getNode()) return V; 13989 } 13990 13991 // On X86 with SSE2 support, we can transform this to a vector shift if 13992 // all elements are shifted by the same amount. We can't do this in legalize 13993 // because the a constant vector is typically transformed to a constant pool 13994 // so we have no knowledge of the shift amount. 13995 if (!Subtarget->hasSSE2()) 13996 return SDValue(); 13997 13998 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13999 (!Subtarget->hasAVX2() || 14000 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 14001 return SDValue(); 14002 14003 SDValue ShAmtOp = N->getOperand(1); 14004 EVT EltVT = VT.getVectorElementType(); 14005 DebugLoc DL = N->getDebugLoc(); 14006 SDValue BaseShAmt = SDValue(); 14007 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 14008 unsigned NumElts = VT.getVectorNumElements(); 14009 unsigned i = 0; 14010 for (; i != NumElts; ++i) { 14011 SDValue Arg = ShAmtOp.getOperand(i); 14012 if (Arg.getOpcode() == ISD::UNDEF) continue; 14013 BaseShAmt = Arg; 14014 break; 14015 } 14016 // Handle the case where the build_vector is all undef 14017 // FIXME: Should DAG allow this? 14018 if (i == NumElts) 14019 return SDValue(); 14020 14021 for (; i != NumElts; ++i) { 14022 SDValue Arg = ShAmtOp.getOperand(i); 14023 if (Arg.getOpcode() == ISD::UNDEF) continue; 14024 if (Arg != BaseShAmt) { 14025 return SDValue(); 14026 } 14027 } 14028 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 14029 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 14030 SDValue InVec = ShAmtOp.getOperand(0); 14031 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 14032 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 14033 unsigned i = 0; 14034 for (; i != NumElts; ++i) { 14035 SDValue Arg = InVec.getOperand(i); 14036 if (Arg.getOpcode() == ISD::UNDEF) continue; 14037 BaseShAmt = Arg; 14038 break; 14039 } 14040 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 14041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 14042 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 14043 if (C->getZExtValue() == SplatIdx) 14044 BaseShAmt = InVec.getOperand(1); 14045 } 14046 } 14047 if (BaseShAmt.getNode() == 0) { 14048 // Don't create instructions with illegal types after legalize 14049 // types has run. 14050 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 14051 !DCI.isBeforeLegalize()) 14052 return SDValue(); 14053 14054 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 14055 DAG.getIntPtrConstant(0)); 14056 } 14057 } else 14058 return SDValue(); 14059 14060 // The shift amount is an i32. 14061 if (EltVT.bitsGT(MVT::i32)) 14062 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 14063 else if (EltVT.bitsLT(MVT::i32)) 14064 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 14065 14066 // The shift amount is identical so we can do a vector shift. 14067 SDValue ValOp = N->getOperand(0); 14068 switch (N->getOpcode()) { 14069 default: 14070 llvm_unreachable("Unknown shift opcode!"); 14071 case ISD::SHL: 14072 switch (VT.getSimpleVT().SimpleTy) { 14073 default: return SDValue(); 14074 case MVT::v2i64: 14075 case MVT::v4i32: 14076 case MVT::v8i16: 14077 case MVT::v4i64: 14078 case MVT::v8i32: 14079 case MVT::v16i16: 14080 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 14081 } 14082 case ISD::SRA: 14083 switch (VT.getSimpleVT().SimpleTy) { 14084 default: return SDValue(); 14085 case MVT::v4i32: 14086 case MVT::v8i16: 14087 case MVT::v8i32: 14088 case MVT::v16i16: 14089 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 14090 } 14091 case ISD::SRL: 14092 switch (VT.getSimpleVT().SimpleTy) { 14093 default: return SDValue(); 14094 case MVT::v2i64: 14095 case MVT::v4i32: 14096 case MVT::v8i16: 14097 case MVT::v4i64: 14098 case MVT::v8i32: 14099 case MVT::v16i16: 14100 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 14101 } 14102 } 14103} 14104 14105 14106// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 14107// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 14108// and friends. Likewise for OR -> CMPNEQSS. 14109static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 14110 TargetLowering::DAGCombinerInfo &DCI, 14111 const X86Subtarget *Subtarget) { 14112 unsigned opcode; 14113 14114 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 14115 // we're requiring SSE2 for both. 14116 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 14117 SDValue N0 = N->getOperand(0); 14118 SDValue N1 = N->getOperand(1); 14119 SDValue CMP0 = N0->getOperand(1); 14120 SDValue CMP1 = N1->getOperand(1); 14121 DebugLoc DL = N->getDebugLoc(); 14122 14123 // The SETCCs should both refer to the same CMP. 14124 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 14125 return SDValue(); 14126 14127 SDValue CMP00 = CMP0->getOperand(0); 14128 SDValue CMP01 = CMP0->getOperand(1); 14129 EVT VT = CMP00.getValueType(); 14130 14131 if (VT == MVT::f32 || VT == MVT::f64) { 14132 bool ExpectingFlags = false; 14133 // Check for any users that want flags: 14134 for (SDNode::use_iterator UI = N->use_begin(), 14135 UE = N->use_end(); 14136 !ExpectingFlags && UI != UE; ++UI) 14137 switch (UI->getOpcode()) { 14138 default: 14139 case ISD::BR_CC: 14140 case ISD::BRCOND: 14141 case ISD::SELECT: 14142 ExpectingFlags = true; 14143 break; 14144 case ISD::CopyToReg: 14145 case ISD::SIGN_EXTEND: 14146 case ISD::ZERO_EXTEND: 14147 case ISD::ANY_EXTEND: 14148 break; 14149 } 14150 14151 if (!ExpectingFlags) { 14152 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 14153 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 14154 14155 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 14156 X86::CondCode tmp = cc0; 14157 cc0 = cc1; 14158 cc1 = tmp; 14159 } 14160 14161 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 14162 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 14163 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 14164 X86ISD::NodeType NTOperator = is64BitFP ? 14165 X86ISD::FSETCCsd : X86ISD::FSETCCss; 14166 // FIXME: need symbolic constants for these magic numbers. 14167 // See X86ATTInstPrinter.cpp:printSSECC(). 14168 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 14169 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 14170 DAG.getConstant(x86cc, MVT::i8)); 14171 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 14172 OnesOrZeroesF); 14173 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 14174 DAG.getConstant(1, MVT::i32)); 14175 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 14176 return OneBitOfTruth; 14177 } 14178 } 14179 } 14180 } 14181 return SDValue(); 14182} 14183 14184/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 14185/// so it can be folded inside ANDNP. 14186static bool CanFoldXORWithAllOnes(const SDNode *N) { 14187 EVT VT = N->getValueType(0); 14188 14189 // Match direct AllOnes for 128 and 256-bit vectors 14190 if (ISD::isBuildVectorAllOnes(N)) 14191 return true; 14192 14193 // Look through a bit convert. 14194 if (N->getOpcode() == ISD::BITCAST) 14195 N = N->getOperand(0).getNode(); 14196 14197 // Sometimes the operand may come from a insert_subvector building a 256-bit 14198 // allones vector 14199 if (VT.getSizeInBits() == 256 && 14200 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 14201 SDValue V1 = N->getOperand(0); 14202 SDValue V2 = N->getOperand(1); 14203 14204 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 14205 V1.getOperand(0).getOpcode() == ISD::UNDEF && 14206 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 14207 ISD::isBuildVectorAllOnes(V2.getNode())) 14208 return true; 14209 } 14210 14211 return false; 14212} 14213 14214static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 14215 TargetLowering::DAGCombinerInfo &DCI, 14216 const X86Subtarget *Subtarget) { 14217 if (DCI.isBeforeLegalizeOps()) 14218 return SDValue(); 14219 14220 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14221 if (R.getNode()) 14222 return R; 14223 14224 EVT VT = N->getValueType(0); 14225 14226 // Create ANDN, BLSI, and BLSR instructions 14227 // BLSI is X & (-X) 14228 // BLSR is X & (X-1) 14229 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 14230 SDValue N0 = N->getOperand(0); 14231 SDValue N1 = N->getOperand(1); 14232 DebugLoc DL = N->getDebugLoc(); 14233 14234 // Check LHS for not 14235 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 14236 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 14237 // Check RHS for not 14238 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 14239 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14240 14241 // Check LHS for neg 14242 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14243 isZero(N0.getOperand(0))) 14244 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14245 14246 // Check RHS for neg 14247 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14248 isZero(N1.getOperand(0))) 14249 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14250 14251 // Check LHS for X-1 14252 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14253 isAllOnes(N0.getOperand(1))) 14254 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14255 14256 // Check RHS for X-1 14257 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14258 isAllOnes(N1.getOperand(1))) 14259 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14260 14261 return SDValue(); 14262 } 14263 14264 // Want to form ANDNP nodes: 14265 // 1) In the hopes of then easily combining them with OR and AND nodes 14266 // to form PBLEND/PSIGN. 14267 // 2) To match ANDN packed intrinsics 14268 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14269 return SDValue(); 14270 14271 SDValue N0 = N->getOperand(0); 14272 SDValue N1 = N->getOperand(1); 14273 DebugLoc DL = N->getDebugLoc(); 14274 14275 // Check LHS for vnot 14276 if (N0.getOpcode() == ISD::XOR && 14277 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14278 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14279 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14280 14281 // Check RHS for vnot 14282 if (N1.getOpcode() == ISD::XOR && 14283 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14284 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14285 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14286 14287 return SDValue(); 14288} 14289 14290static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14291 TargetLowering::DAGCombinerInfo &DCI, 14292 const X86Subtarget *Subtarget) { 14293 if (DCI.isBeforeLegalizeOps()) 14294 return SDValue(); 14295 14296 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14297 if (R.getNode()) 14298 return R; 14299 14300 EVT VT = N->getValueType(0); 14301 14302 SDValue N0 = N->getOperand(0); 14303 SDValue N1 = N->getOperand(1); 14304 14305 // look for psign/blend 14306 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14307 if (!Subtarget->hasSSSE3() || 14308 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14309 return SDValue(); 14310 14311 // Canonicalize pandn to RHS 14312 if (N0.getOpcode() == X86ISD::ANDNP) 14313 std::swap(N0, N1); 14314 // or (and (m, y), (pandn m, x)) 14315 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14316 SDValue Mask = N1.getOperand(0); 14317 SDValue X = N1.getOperand(1); 14318 SDValue Y; 14319 if (N0.getOperand(0) == Mask) 14320 Y = N0.getOperand(1); 14321 if (N0.getOperand(1) == Mask) 14322 Y = N0.getOperand(0); 14323 14324 // Check to see if the mask appeared in both the AND and ANDNP and 14325 if (!Y.getNode()) 14326 return SDValue(); 14327 14328 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14329 // Look through mask bitcast. 14330 if (Mask.getOpcode() == ISD::BITCAST) 14331 Mask = Mask.getOperand(0); 14332 if (X.getOpcode() == ISD::BITCAST) 14333 X = X.getOperand(0); 14334 if (Y.getOpcode() == ISD::BITCAST) 14335 Y = Y.getOperand(0); 14336 14337 EVT MaskVT = Mask.getValueType(); 14338 14339 // Validate that the Mask operand is a vector sra node. 14340 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14341 // there is no psrai.b 14342 if (Mask.getOpcode() != X86ISD::VSRAI) 14343 return SDValue(); 14344 14345 // Check that the SRA is all signbits. 14346 SDValue SraC = Mask.getOperand(1); 14347 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14348 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14349 if ((SraAmt + 1) != EltBits) 14350 return SDValue(); 14351 14352 DebugLoc DL = N->getDebugLoc(); 14353 14354 // Now we know we at least have a plendvb with the mask val. See if 14355 // we can form a psignb/w/d. 14356 // psign = x.type == y.type == mask.type && y = sub(0, x); 14357 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14358 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14359 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14360 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14361 "Unsupported VT for PSIGN"); 14362 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14363 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14364 } 14365 // PBLENDVB only available on SSE 4.1 14366 if (!Subtarget->hasSSE41()) 14367 return SDValue(); 14368 14369 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14370 14371 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14372 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14373 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14374 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14375 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14376 } 14377 } 14378 14379 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14380 return SDValue(); 14381 14382 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14383 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14384 std::swap(N0, N1); 14385 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14386 return SDValue(); 14387 if (!N0.hasOneUse() || !N1.hasOneUse()) 14388 return SDValue(); 14389 14390 SDValue ShAmt0 = N0.getOperand(1); 14391 if (ShAmt0.getValueType() != MVT::i8) 14392 return SDValue(); 14393 SDValue ShAmt1 = N1.getOperand(1); 14394 if (ShAmt1.getValueType() != MVT::i8) 14395 return SDValue(); 14396 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14397 ShAmt0 = ShAmt0.getOperand(0); 14398 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14399 ShAmt1 = ShAmt1.getOperand(0); 14400 14401 DebugLoc DL = N->getDebugLoc(); 14402 unsigned Opc = X86ISD::SHLD; 14403 SDValue Op0 = N0.getOperand(0); 14404 SDValue Op1 = N1.getOperand(0); 14405 if (ShAmt0.getOpcode() == ISD::SUB) { 14406 Opc = X86ISD::SHRD; 14407 std::swap(Op0, Op1); 14408 std::swap(ShAmt0, ShAmt1); 14409 } 14410 14411 unsigned Bits = VT.getSizeInBits(); 14412 if (ShAmt1.getOpcode() == ISD::SUB) { 14413 SDValue Sum = ShAmt1.getOperand(0); 14414 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14415 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14416 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14417 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14418 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14419 return DAG.getNode(Opc, DL, VT, 14420 Op0, Op1, 14421 DAG.getNode(ISD::TRUNCATE, DL, 14422 MVT::i8, ShAmt0)); 14423 } 14424 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14425 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14426 if (ShAmt0C && 14427 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14428 return DAG.getNode(Opc, DL, VT, 14429 N0.getOperand(0), N1.getOperand(0), 14430 DAG.getNode(ISD::TRUNCATE, DL, 14431 MVT::i8, ShAmt0)); 14432 } 14433 14434 return SDValue(); 14435} 14436 14437// Generate NEG and CMOV for integer abs. 14438static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 14439 EVT VT = N->getValueType(0); 14440 14441 // Since X86 does not have CMOV for 8-bit integer, we don't convert 14442 // 8-bit integer abs to NEG and CMOV. 14443 if (VT.isInteger() && VT.getSizeInBits() == 8) 14444 return SDValue(); 14445 14446 SDValue N0 = N->getOperand(0); 14447 SDValue N1 = N->getOperand(1); 14448 DebugLoc DL = N->getDebugLoc(); 14449 14450 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 14451 // and change it to SUB and CMOV. 14452 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 14453 N0.getOpcode() == ISD::ADD && 14454 N0.getOperand(1) == N1 && 14455 N1.getOpcode() == ISD::SRA && 14456 N1.getOperand(0) == N0.getOperand(0)) 14457 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 14458 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) { 14459 // Generate SUB & CMOV. 14460 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32), 14461 DAG.getConstant(0, VT), N0.getOperand(0)); 14462 14463 SDValue Ops[] = { N0.getOperand(0), Neg, 14464 DAG.getConstant(X86::COND_GE, MVT::i8), 14465 SDValue(Neg.getNode(), 1) }; 14466 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), 14467 Ops, array_lengthof(Ops)); 14468 } 14469 return SDValue(); 14470} 14471 14472// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14473static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14474 TargetLowering::DAGCombinerInfo &DCI, 14475 const X86Subtarget *Subtarget) { 14476 if (DCI.isBeforeLegalizeOps()) 14477 return SDValue(); 14478 14479 if (Subtarget->hasCMov()) { 14480 SDValue RV = performIntegerAbsCombine(N, DAG); 14481 if (RV.getNode()) 14482 return RV; 14483 } 14484 14485 // Try forming BMI if it is available. 14486 if (!Subtarget->hasBMI()) 14487 return SDValue(); 14488 14489 EVT VT = N->getValueType(0); 14490 14491 if (VT != MVT::i32 && VT != MVT::i64) 14492 return SDValue(); 14493 14494 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14495 14496 // Create BLSMSK instructions by finding X ^ (X-1) 14497 SDValue N0 = N->getOperand(0); 14498 SDValue N1 = N->getOperand(1); 14499 DebugLoc DL = N->getDebugLoc(); 14500 14501 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14502 isAllOnes(N0.getOperand(1))) 14503 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14504 14505 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14506 isAllOnes(N1.getOperand(1))) 14507 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14508 14509 return SDValue(); 14510} 14511 14512/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14513static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14514 TargetLowering::DAGCombinerInfo &DCI, 14515 const X86Subtarget *Subtarget) { 14516 LoadSDNode *Ld = cast<LoadSDNode>(N); 14517 EVT RegVT = Ld->getValueType(0); 14518 EVT MemVT = Ld->getMemoryVT(); 14519 DebugLoc dl = Ld->getDebugLoc(); 14520 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14521 14522 ISD::LoadExtType Ext = Ld->getExtensionType(); 14523 14524 // If this is a vector EXT Load then attempt to optimize it using a 14525 // shuffle. We need SSE4 for the shuffles. 14526 // TODO: It is possible to support ZExt by zeroing the undef values 14527 // during the shuffle phase or after the shuffle. 14528 if (RegVT.isVector() && RegVT.isInteger() && 14529 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14530 assert(MemVT != RegVT && "Cannot extend to the same type"); 14531 assert(MemVT.isVector() && "Must load a vector from memory"); 14532 14533 unsigned NumElems = RegVT.getVectorNumElements(); 14534 unsigned RegSz = RegVT.getSizeInBits(); 14535 unsigned MemSz = MemVT.getSizeInBits(); 14536 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14537 14538 // All sizes must be a power of two. 14539 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) 14540 return SDValue(); 14541 14542 // Attempt to load the original value using scalar loads. 14543 // Find the largest scalar type that divides the total loaded size. 14544 MVT SclrLoadTy = MVT::i8; 14545 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14546 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14547 MVT Tp = (MVT::SimpleValueType)tp; 14548 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { 14549 SclrLoadTy = Tp; 14550 } 14551 } 14552 14553 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 14554 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && 14555 (64 <= MemSz)) 14556 SclrLoadTy = MVT::f64; 14557 14558 // Calculate the number of scalar loads that we need to perform 14559 // in order to load our vector from memory. 14560 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits(); 14561 14562 // Represent our vector as a sequence of elements which are the 14563 // largest scalar that we can load. 14564 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14565 RegSz/SclrLoadTy.getSizeInBits()); 14566 14567 // Represent the data using the same element type that is stored in 14568 // memory. In practice, we ''widen'' MemVT. 14569 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14570 RegSz/MemVT.getScalarType().getSizeInBits()); 14571 14572 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && 14573 "Invalid vector type"); 14574 14575 // We can't shuffle using an illegal type. 14576 if (!TLI.isTypeLegal(WideVecVT)) 14577 return SDValue(); 14578 14579 SmallVector<SDValue, 8> Chains; 14580 SDValue Ptr = Ld->getBasePtr(); 14581 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8, 14582 TLI.getPointerTy()); 14583 SDValue Res = DAG.getUNDEF(LoadUnitVecVT); 14584 14585 for (unsigned i = 0; i < NumLoads; ++i) { 14586 // Perform a single load. 14587 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14588 Ptr, Ld->getPointerInfo(), 14589 Ld->isVolatile(), Ld->isNonTemporal(), 14590 Ld->isInvariant(), Ld->getAlignment()); 14591 Chains.push_back(ScalarLoad.getValue(1)); 14592 // Create the first element type using SCALAR_TO_VECTOR in order to avoid 14593 // another round of DAGCombining. 14594 if (i == 0) 14595 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad); 14596 else 14597 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res, 14598 ScalarLoad, DAG.getIntPtrConstant(i)); 14599 14600 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14601 } 14602 14603 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14604 Chains.size()); 14605 14606 // Bitcast the loaded value to a vector of the original element type, in 14607 // the size of the target vector type. 14608 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res); 14609 unsigned SizeRatio = RegSz/MemSz; 14610 14611 // Redistribute the loaded elements into the different locations. 14612 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14613 for (unsigned i = 0; i != NumElems; ++i) 14614 ShuffleVec[i*SizeRatio] = i; 14615 14616 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14617 DAG.getUNDEF(WideVecVT), 14618 &ShuffleVec[0]); 14619 14620 // Bitcast to the requested type. 14621 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14622 // Replace the original load with the new sequence 14623 // and return the new chain. 14624 return DCI.CombineTo(N, Shuff, TF, true); 14625 } 14626 14627 return SDValue(); 14628} 14629 14630/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14631static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14632 const X86Subtarget *Subtarget) { 14633 StoreSDNode *St = cast<StoreSDNode>(N); 14634 EVT VT = St->getValue().getValueType(); 14635 EVT StVT = St->getMemoryVT(); 14636 DebugLoc dl = St->getDebugLoc(); 14637 SDValue StoredVal = St->getOperand(1); 14638 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14639 14640 // If we are saving a concatenation of two XMM registers, perform two stores. 14641 // On Sandy Bridge, 256-bit memory operations are executed by two 14642 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit 14643 // memory operation. 14644 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() && 14645 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14646 StoredVal.getNumOperands() == 2) { 14647 SDValue Value0 = StoredVal.getOperand(0); 14648 SDValue Value1 = StoredVal.getOperand(1); 14649 14650 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14651 SDValue Ptr0 = St->getBasePtr(); 14652 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14653 14654 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14655 St->getPointerInfo(), St->isVolatile(), 14656 St->isNonTemporal(), St->getAlignment()); 14657 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14658 St->getPointerInfo(), St->isVolatile(), 14659 St->isNonTemporal(), St->getAlignment()); 14660 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14661 } 14662 14663 // Optimize trunc store (of multiple scalars) to shuffle and store. 14664 // First, pack all of the elements in one place. Next, store to memory 14665 // in fewer chunks. 14666 if (St->isTruncatingStore() && VT.isVector()) { 14667 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14668 unsigned NumElems = VT.getVectorNumElements(); 14669 assert(StVT != VT && "Cannot truncate to the same type"); 14670 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14671 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14672 14673 // From, To sizes and ElemCount must be pow of two 14674 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14675 // We are going to use the original vector elt for storing. 14676 // Accumulated smaller vector elements must be a multiple of the store size. 14677 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14678 14679 unsigned SizeRatio = FromSz / ToSz; 14680 14681 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14682 14683 // Create a type on which we perform the shuffle 14684 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14685 StVT.getScalarType(), NumElems*SizeRatio); 14686 14687 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14688 14689 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14690 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14691 for (unsigned i = 0; i != NumElems; ++i) 14692 ShuffleVec[i] = i * SizeRatio; 14693 14694 // Can't shuffle using an illegal type. 14695 if (!TLI.isTypeLegal(WideVecVT)) 14696 return SDValue(); 14697 14698 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14699 DAG.getUNDEF(WideVecVT), 14700 &ShuffleVec[0]); 14701 // At this point all of the data is stored at the bottom of the 14702 // register. We now need to save it to mem. 14703 14704 // Find the largest store unit 14705 MVT StoreType = MVT::i8; 14706 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14707 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14708 MVT Tp = (MVT::SimpleValueType)tp; 14709 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz) 14710 StoreType = Tp; 14711 } 14712 14713 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64. 14714 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 && 14715 (64 <= NumElems * ToSz)) 14716 StoreType = MVT::f64; 14717 14718 // Bitcast the original vector into a vector of store-size units 14719 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14720 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits()); 14721 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14722 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14723 SmallVector<SDValue, 8> Chains; 14724 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14725 TLI.getPointerTy()); 14726 SDValue Ptr = St->getBasePtr(); 14727 14728 // Perform one or more big stores into memory. 14729 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { 14730 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14731 StoreType, ShuffWide, 14732 DAG.getIntPtrConstant(i)); 14733 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14734 St->getPointerInfo(), St->isVolatile(), 14735 St->isNonTemporal(), St->getAlignment()); 14736 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14737 Chains.push_back(Ch); 14738 } 14739 14740 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14741 Chains.size()); 14742 } 14743 14744 14745 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14746 // the FP state in cases where an emms may be missing. 14747 // A preferable solution to the general problem is to figure out the right 14748 // places to insert EMMS. This qualifies as a quick hack. 14749 14750 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14751 if (VT.getSizeInBits() != 64) 14752 return SDValue(); 14753 14754 const Function *F = DAG.getMachineFunction().getFunction(); 14755 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14756 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14757 && Subtarget->hasSSE2(); 14758 if ((VT.isVector() || 14759 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14760 isa<LoadSDNode>(St->getValue()) && 14761 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14762 St->getChain().hasOneUse() && !St->isVolatile()) { 14763 SDNode* LdVal = St->getValue().getNode(); 14764 LoadSDNode *Ld = 0; 14765 int TokenFactorIndex = -1; 14766 SmallVector<SDValue, 8> Ops; 14767 SDNode* ChainVal = St->getChain().getNode(); 14768 // Must be a store of a load. We currently handle two cases: the load 14769 // is a direct child, and it's under an intervening TokenFactor. It is 14770 // possible to dig deeper under nested TokenFactors. 14771 if (ChainVal == LdVal) 14772 Ld = cast<LoadSDNode>(St->getChain()); 14773 else if (St->getValue().hasOneUse() && 14774 ChainVal->getOpcode() == ISD::TokenFactor) { 14775 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14776 if (ChainVal->getOperand(i).getNode() == LdVal) { 14777 TokenFactorIndex = i; 14778 Ld = cast<LoadSDNode>(St->getValue()); 14779 } else 14780 Ops.push_back(ChainVal->getOperand(i)); 14781 } 14782 } 14783 14784 if (!Ld || !ISD::isNormalLoad(Ld)) 14785 return SDValue(); 14786 14787 // If this is not the MMX case, i.e. we are just turning i64 load/store 14788 // into f64 load/store, avoid the transformation if there are multiple 14789 // uses of the loaded value. 14790 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14791 return SDValue(); 14792 14793 DebugLoc LdDL = Ld->getDebugLoc(); 14794 DebugLoc StDL = N->getDebugLoc(); 14795 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14796 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14797 // pair instead. 14798 if (Subtarget->is64Bit() || F64IsLegal) { 14799 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14800 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14801 Ld->getPointerInfo(), Ld->isVolatile(), 14802 Ld->isNonTemporal(), Ld->isInvariant(), 14803 Ld->getAlignment()); 14804 SDValue NewChain = NewLd.getValue(1); 14805 if (TokenFactorIndex != -1) { 14806 Ops.push_back(NewChain); 14807 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14808 Ops.size()); 14809 } 14810 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14811 St->getPointerInfo(), 14812 St->isVolatile(), St->isNonTemporal(), 14813 St->getAlignment()); 14814 } 14815 14816 // Otherwise, lower to two pairs of 32-bit loads / stores. 14817 SDValue LoAddr = Ld->getBasePtr(); 14818 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14819 DAG.getConstant(4, MVT::i32)); 14820 14821 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14822 Ld->getPointerInfo(), 14823 Ld->isVolatile(), Ld->isNonTemporal(), 14824 Ld->isInvariant(), Ld->getAlignment()); 14825 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14826 Ld->getPointerInfo().getWithOffset(4), 14827 Ld->isVolatile(), Ld->isNonTemporal(), 14828 Ld->isInvariant(), 14829 MinAlign(Ld->getAlignment(), 4)); 14830 14831 SDValue NewChain = LoLd.getValue(1); 14832 if (TokenFactorIndex != -1) { 14833 Ops.push_back(LoLd); 14834 Ops.push_back(HiLd); 14835 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14836 Ops.size()); 14837 } 14838 14839 LoAddr = St->getBasePtr(); 14840 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14841 DAG.getConstant(4, MVT::i32)); 14842 14843 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14844 St->getPointerInfo(), 14845 St->isVolatile(), St->isNonTemporal(), 14846 St->getAlignment()); 14847 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14848 St->getPointerInfo().getWithOffset(4), 14849 St->isVolatile(), 14850 St->isNonTemporal(), 14851 MinAlign(St->getAlignment(), 4)); 14852 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14853 } 14854 return SDValue(); 14855} 14856 14857/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14858/// and return the operands for the horizontal operation in LHS and RHS. A 14859/// horizontal operation performs the binary operation on successive elements 14860/// of its first operand, then on successive elements of its second operand, 14861/// returning the resulting values in a vector. For example, if 14862/// A = < float a0, float a1, float a2, float a3 > 14863/// and 14864/// B = < float b0, float b1, float b2, float b3 > 14865/// then the result of doing a horizontal operation on A and B is 14866/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14867/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14868/// A horizontal-op B, for some already available A and B, and if so then LHS is 14869/// set to A, RHS to B, and the routine returns 'true'. 14870/// Note that the binary operation should have the property that if one of the 14871/// operands is UNDEF then the result is UNDEF. 14872static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14873 // Look for the following pattern: if 14874 // A = < float a0, float a1, float a2, float a3 > 14875 // B = < float b0, float b1, float b2, float b3 > 14876 // and 14877 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14878 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14879 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14880 // which is A horizontal-op B. 14881 14882 // At least one of the operands should be a vector shuffle. 14883 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14884 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14885 return false; 14886 14887 EVT VT = LHS.getValueType(); 14888 14889 assert((VT.is128BitVector() || VT.is256BitVector()) && 14890 "Unsupported vector type for horizontal add/sub"); 14891 14892 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14893 // operate independently on 128-bit lanes. 14894 unsigned NumElts = VT.getVectorNumElements(); 14895 unsigned NumLanes = VT.getSizeInBits()/128; 14896 unsigned NumLaneElts = NumElts / NumLanes; 14897 assert((NumLaneElts % 2 == 0) && 14898 "Vector type should have an even number of elements in each lane"); 14899 unsigned HalfLaneElts = NumLaneElts/2; 14900 14901 // View LHS in the form 14902 // LHS = VECTOR_SHUFFLE A, B, LMask 14903 // If LHS is not a shuffle then pretend it is the shuffle 14904 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14905 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14906 // type VT. 14907 SDValue A, B; 14908 SmallVector<int, 16> LMask(NumElts); 14909 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14910 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14911 A = LHS.getOperand(0); 14912 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14913 B = LHS.getOperand(1); 14914 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14915 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14916 } else { 14917 if (LHS.getOpcode() != ISD::UNDEF) 14918 A = LHS; 14919 for (unsigned i = 0; i != NumElts; ++i) 14920 LMask[i] = i; 14921 } 14922 14923 // Likewise, view RHS in the form 14924 // RHS = VECTOR_SHUFFLE C, D, RMask 14925 SDValue C, D; 14926 SmallVector<int, 16> RMask(NumElts); 14927 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14928 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14929 C = RHS.getOperand(0); 14930 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14931 D = RHS.getOperand(1); 14932 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14933 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14934 } else { 14935 if (RHS.getOpcode() != ISD::UNDEF) 14936 C = RHS; 14937 for (unsigned i = 0; i != NumElts; ++i) 14938 RMask[i] = i; 14939 } 14940 14941 // Check that the shuffles are both shuffling the same vectors. 14942 if (!(A == C && B == D) && !(A == D && B == C)) 14943 return false; 14944 14945 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14946 if (!A.getNode() && !B.getNode()) 14947 return false; 14948 14949 // If A and B occur in reverse order in RHS, then "swap" them (which means 14950 // rewriting the mask). 14951 if (A != C) 14952 CommuteVectorShuffleMask(RMask, NumElts); 14953 14954 // At this point LHS and RHS are equivalent to 14955 // LHS = VECTOR_SHUFFLE A, B, LMask 14956 // RHS = VECTOR_SHUFFLE A, B, RMask 14957 // Check that the masks correspond to performing a horizontal operation. 14958 for (unsigned i = 0; i != NumElts; ++i) { 14959 int LIdx = LMask[i], RIdx = RMask[i]; 14960 14961 // Ignore any UNDEF components. 14962 if (LIdx < 0 || RIdx < 0 || 14963 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14964 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14965 continue; 14966 14967 // Check that successive elements are being operated on. If not, this is 14968 // not a horizontal operation. 14969 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14970 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14971 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14972 if (!(LIdx == Index && RIdx == Index + 1) && 14973 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14974 return false; 14975 } 14976 14977 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14978 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14979 return true; 14980} 14981 14982/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14983static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14984 const X86Subtarget *Subtarget) { 14985 EVT VT = N->getValueType(0); 14986 SDValue LHS = N->getOperand(0); 14987 SDValue RHS = N->getOperand(1); 14988 14989 // Try to synthesize horizontal adds from adds of shuffles. 14990 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14991 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14992 isHorizontalBinOp(LHS, RHS, true)) 14993 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14994 return SDValue(); 14995} 14996 14997/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14998static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14999 const X86Subtarget *Subtarget) { 15000 EVT VT = N->getValueType(0); 15001 SDValue LHS = N->getOperand(0); 15002 SDValue RHS = N->getOperand(1); 15003 15004 // Try to synthesize horizontal subs from subs of shuffles. 15005 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 15006 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 15007 isHorizontalBinOp(LHS, RHS, false)) 15008 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 15009 return SDValue(); 15010} 15011 15012/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 15013/// X86ISD::FXOR nodes. 15014static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 15015 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 15016 // F[X]OR(0.0, x) -> x 15017 // F[X]OR(x, 0.0) -> x 15018 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 15019 if (C->getValueAPF().isPosZero()) 15020 return N->getOperand(1); 15021 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 15022 if (C->getValueAPF().isPosZero()) 15023 return N->getOperand(0); 15024 return SDValue(); 15025} 15026 15027/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 15028static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 15029 // FAND(0.0, x) -> 0.0 15030 // FAND(x, 0.0) -> 0.0 15031 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 15032 if (C->getValueAPF().isPosZero()) 15033 return N->getOperand(0); 15034 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 15035 if (C->getValueAPF().isPosZero()) 15036 return N->getOperand(1); 15037 return SDValue(); 15038} 15039 15040static SDValue PerformBTCombine(SDNode *N, 15041 SelectionDAG &DAG, 15042 TargetLowering::DAGCombinerInfo &DCI) { 15043 // BT ignores high bits in the bit index operand. 15044 SDValue Op1 = N->getOperand(1); 15045 if (Op1.hasOneUse()) { 15046 unsigned BitWidth = Op1.getValueSizeInBits(); 15047 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 15048 APInt KnownZero, KnownOne; 15049 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 15050 !DCI.isBeforeLegalizeOps()); 15051 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 15052 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 15053 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 15054 DCI.CommitTargetLoweringOpt(TLO); 15055 } 15056 return SDValue(); 15057} 15058 15059static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 15060 SDValue Op = N->getOperand(0); 15061 if (Op.getOpcode() == ISD::BITCAST) 15062 Op = Op.getOperand(0); 15063 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 15064 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 15065 VT.getVectorElementType().getSizeInBits() == 15066 OpVT.getVectorElementType().getSizeInBits()) { 15067 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 15068 } 15069 return SDValue(); 15070} 15071 15072static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 15073 TargetLowering::DAGCombinerInfo &DCI, 15074 const X86Subtarget *Subtarget) { 15075 if (!DCI.isBeforeLegalizeOps()) 15076 return SDValue(); 15077 15078 if (!Subtarget->hasAVX()) 15079 return SDValue(); 15080 15081 EVT VT = N->getValueType(0); 15082 SDValue Op = N->getOperand(0); 15083 EVT OpVT = Op.getValueType(); 15084 DebugLoc dl = N->getDebugLoc(); 15085 15086 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 15087 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 15088 15089 if (Subtarget->hasAVX2()) 15090 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op); 15091 15092 // Optimize vectors in AVX mode 15093 // Sign extend v8i16 to v8i32 and 15094 // v4i32 to v4i64 15095 // 15096 // Divide input vector into two parts 15097 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 15098 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 15099 // concat the vectors to original VT 15100 15101 unsigned NumElems = OpVT.getVectorNumElements(); 15102 SmallVector<int,8> ShufMask1(NumElems, -1); 15103 for (unsigned i = 0; i != NumElems/2; ++i) 15104 ShufMask1[i] = i; 15105 15106 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 15107 &ShufMask1[0]); 15108 15109 SmallVector<int,8> ShufMask2(NumElems, -1); 15110 for (unsigned i = 0; i != NumElems/2; ++i) 15111 ShufMask2[i] = i + NumElems/2; 15112 15113 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 15114 &ShufMask2[0]); 15115 15116 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 15117 VT.getVectorNumElements()/2); 15118 15119 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 15120 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 15121 15122 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15123 } 15124 return SDValue(); 15125} 15126 15127static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG, 15128 const X86Subtarget* Subtarget) { 15129 DebugLoc dl = N->getDebugLoc(); 15130 EVT VT = N->getValueType(0); 15131 15132 EVT ScalarVT = VT.getScalarType(); 15133 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasFMA()) 15134 return SDValue(); 15135 15136 SDValue A = N->getOperand(0); 15137 SDValue B = N->getOperand(1); 15138 SDValue C = N->getOperand(2); 15139 15140 bool NegA = (A.getOpcode() == ISD::FNEG); 15141 bool NegB = (B.getOpcode() == ISD::FNEG); 15142 bool NegC = (C.getOpcode() == ISD::FNEG); 15143 15144 // Negative multiplication when NegA xor NegB 15145 bool NegMul = (NegA != NegB); 15146 if (NegA) 15147 A = A.getOperand(0); 15148 if (NegB) 15149 B = B.getOperand(0); 15150 if (NegC) 15151 C = C.getOperand(0); 15152 15153 unsigned Opcode; 15154 if (!NegMul) 15155 Opcode = (!NegC)? X86ISD::FMADD : X86ISD::FMSUB; 15156 else 15157 Opcode = (!NegC)? X86ISD::FNMADD : X86ISD::FNMSUB; 15158 return DAG.getNode(Opcode, dl, VT, A, B, C); 15159} 15160 15161static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 15162 TargetLowering::DAGCombinerInfo &DCI, 15163 const X86Subtarget *Subtarget) { 15164 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 15165 // (and (i32 x86isd::setcc_carry), 1) 15166 // This eliminates the zext. This transformation is necessary because 15167 // ISD::SETCC is always legalized to i8. 15168 DebugLoc dl = N->getDebugLoc(); 15169 SDValue N0 = N->getOperand(0); 15170 EVT VT = N->getValueType(0); 15171 EVT OpVT = N0.getValueType(); 15172 15173 if (N0.getOpcode() == ISD::AND && 15174 N0.hasOneUse() && 15175 N0.getOperand(0).hasOneUse()) { 15176 SDValue N00 = N0.getOperand(0); 15177 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 15178 return SDValue(); 15179 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 15180 if (!C || C->getZExtValue() != 1) 15181 return SDValue(); 15182 return DAG.getNode(ISD::AND, dl, VT, 15183 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 15184 N00.getOperand(0), N00.getOperand(1)), 15185 DAG.getConstant(1, VT)); 15186 } 15187 15188 // Optimize vectors in AVX mode: 15189 // 15190 // v8i16 -> v8i32 15191 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 15192 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 15193 // Concat upper and lower parts. 15194 // 15195 // v4i32 -> v4i64 15196 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 15197 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 15198 // Concat upper and lower parts. 15199 // 15200 if (!DCI.isBeforeLegalizeOps()) 15201 return SDValue(); 15202 15203 if (!Subtarget->hasAVX()) 15204 return SDValue(); 15205 15206 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 15207 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 15208 15209 if (Subtarget->hasAVX2()) 15210 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0); 15211 15212 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 15213 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec); 15214 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec); 15215 15216 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 15217 VT.getVectorNumElements()/2); 15218 15219 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 15220 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 15221 15222 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15223 } 15224 15225 return SDValue(); 15226} 15227 15228// Optimize x == -y --> x+y == 0 15229// x != -y --> x+y != 0 15230static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15231 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 15232 SDValue LHS = N->getOperand(0); 15233 SDValue RHS = N->getOperand(1); 15234 15235 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 15236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 15237 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 15238 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15239 LHS.getValueType(), RHS, LHS.getOperand(1)); 15240 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15241 addV, DAG.getConstant(0, addV.getValueType()), CC); 15242 } 15243 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 15244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 15245 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 15246 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15247 RHS.getValueType(), LHS, RHS.getOperand(1)); 15248 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15249 addV, DAG.getConstant(0, addV.getValueType()), CC); 15250 } 15251 return SDValue(); 15252} 15253 15254// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 15255static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15256 unsigned X86CC = N->getConstantOperandVal(0); 15257 SDValue EFLAG = N->getOperand(1); 15258 DebugLoc DL = N->getDebugLoc(); 15259 15260 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 15261 // a zext and produces an all-ones bit which is more useful than 0/1 in some 15262 // cases. 15263 if (X86CC == X86::COND_B) 15264 return DAG.getNode(ISD::AND, DL, MVT::i8, 15265 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 15266 DAG.getConstant(X86CC, MVT::i8), EFLAG), 15267 DAG.getConstant(1, MVT::i8)); 15268 15269 return SDValue(); 15270} 15271 15272static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) { 15273 SDValue Op0 = N->getOperand(0); 15274 EVT InVT = Op0->getValueType(0); 15275 15276 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) 15277 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15278 DebugLoc dl = N->getDebugLoc(); 15279 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15280 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); 15281 // Notice that we use SINT_TO_FP because we know that the high bits 15282 // are zero and SINT_TO_FP is better supported by the hardware. 15283 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15284 } 15285 15286 return SDValue(); 15287} 15288 15289static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 15290 const X86TargetLowering *XTLI) { 15291 SDValue Op0 = N->getOperand(0); 15292 EVT InVT = Op0->getValueType(0); 15293 15294 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 15295 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15296 DebugLoc dl = N->getDebugLoc(); 15297 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15298 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 15299 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15300 } 15301 15302 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 15303 // a 32-bit target where SSE doesn't support i64->FP operations. 15304 if (Op0.getOpcode() == ISD::LOAD) { 15305 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 15306 EVT VT = Ld->getValueType(0); 15307 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 15308 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 15309 !XTLI->getSubtarget()->is64Bit() && 15310 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 15311 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 15312 Ld->getChain(), Op0, DAG); 15313 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 15314 return FILDChain; 15315 } 15316 } 15317 return SDValue(); 15318} 15319 15320static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) { 15321 EVT VT = N->getValueType(0); 15322 15323 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT() 15324 if (VT == MVT::v8i8 || VT == MVT::v4i8) { 15325 DebugLoc dl = N->getDebugLoc(); 15326 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15327 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0)); 15328 return DAG.getNode(ISD::TRUNCATE, dl, VT, I); 15329 } 15330 15331 return SDValue(); 15332} 15333 15334// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 15335static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 15336 X86TargetLowering::DAGCombinerInfo &DCI) { 15337 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 15338 // the result is either zero or one (depending on the input carry bit). 15339 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 15340 if (X86::isZeroNode(N->getOperand(0)) && 15341 X86::isZeroNode(N->getOperand(1)) && 15342 // We don't have a good way to replace an EFLAGS use, so only do this when 15343 // dead right now. 15344 SDValue(N, 1).use_empty()) { 15345 DebugLoc DL = N->getDebugLoc(); 15346 EVT VT = N->getValueType(0); 15347 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 15348 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 15349 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 15350 DAG.getConstant(X86::COND_B,MVT::i8), 15351 N->getOperand(2)), 15352 DAG.getConstant(1, VT)); 15353 return DCI.CombineTo(N, Res1, CarryOut); 15354 } 15355 15356 return SDValue(); 15357} 15358 15359// fold (add Y, (sete X, 0)) -> adc 0, Y 15360// (add Y, (setne X, 0)) -> sbb -1, Y 15361// (sub (sete X, 0), Y) -> sbb 0, Y 15362// (sub (setne X, 0), Y) -> adc -1, Y 15363static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 15364 DebugLoc DL = N->getDebugLoc(); 15365 15366 // Look through ZExts. 15367 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 15368 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 15369 return SDValue(); 15370 15371 SDValue SetCC = Ext.getOperand(0); 15372 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 15373 return SDValue(); 15374 15375 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 15376 if (CC != X86::COND_E && CC != X86::COND_NE) 15377 return SDValue(); 15378 15379 SDValue Cmp = SetCC.getOperand(1); 15380 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 15381 !X86::isZeroNode(Cmp.getOperand(1)) || 15382 !Cmp.getOperand(0).getValueType().isInteger()) 15383 return SDValue(); 15384 15385 SDValue CmpOp0 = Cmp.getOperand(0); 15386 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 15387 DAG.getConstant(1, CmpOp0.getValueType())); 15388 15389 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 15390 if (CC == X86::COND_NE) 15391 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 15392 DL, OtherVal.getValueType(), OtherVal, 15393 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 15394 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 15395 DL, OtherVal.getValueType(), OtherVal, 15396 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 15397} 15398 15399/// PerformADDCombine - Do target-specific dag combines on integer adds. 15400static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 15401 const X86Subtarget *Subtarget) { 15402 EVT VT = N->getValueType(0); 15403 SDValue Op0 = N->getOperand(0); 15404 SDValue Op1 = N->getOperand(1); 15405 15406 // Try to synthesize horizontal adds from adds of shuffles. 15407 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15408 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15409 isHorizontalBinOp(Op0, Op1, true)) 15410 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 15411 15412 return OptimizeConditionalInDecrement(N, DAG); 15413} 15414 15415static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 15416 const X86Subtarget *Subtarget) { 15417 SDValue Op0 = N->getOperand(0); 15418 SDValue Op1 = N->getOperand(1); 15419 15420 // X86 can't encode an immediate LHS of a sub. See if we can push the 15421 // negation into a preceding instruction. 15422 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 15423 // If the RHS of the sub is a XOR with one use and a constant, invert the 15424 // immediate. Then add one to the LHS of the sub so we can turn 15425 // X-Y -> X+~Y+1, saving one register. 15426 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 15427 isa<ConstantSDNode>(Op1.getOperand(1))) { 15428 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 15429 EVT VT = Op0.getValueType(); 15430 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 15431 Op1.getOperand(0), 15432 DAG.getConstant(~XorC, VT)); 15433 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 15434 DAG.getConstant(C->getAPIntValue()+1, VT)); 15435 } 15436 } 15437 15438 // Try to synthesize horizontal adds from adds of shuffles. 15439 EVT VT = N->getValueType(0); 15440 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15441 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15442 isHorizontalBinOp(Op0, Op1, true)) 15443 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15444 15445 return OptimizeConditionalInDecrement(N, DAG); 15446} 15447 15448SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15449 DAGCombinerInfo &DCI) const { 15450 SelectionDAG &DAG = DCI.DAG; 15451 switch (N->getOpcode()) { 15452 default: break; 15453 case ISD::EXTRACT_VECTOR_ELT: 15454 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15455 case ISD::VSELECT: 15456 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15457 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15458 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15459 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15460 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15461 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15462 case ISD::SHL: 15463 case ISD::SRA: 15464 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15465 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15466 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15467 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15468 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); 15469 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15470 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG); 15471 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15472 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG); 15473 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15474 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15475 case X86ISD::FXOR: 15476 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15477 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15478 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15479 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15480 case ISD::ANY_EXTEND: 15481 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 15482 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15483 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15484 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 15485 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15486 case X86ISD::SHUFP: // Handle all target specific shuffles 15487 case X86ISD::PALIGN: 15488 case X86ISD::UNPCKH: 15489 case X86ISD::UNPCKL: 15490 case X86ISD::MOVHLPS: 15491 case X86ISD::MOVLHPS: 15492 case X86ISD::PSHUFD: 15493 case X86ISD::PSHUFHW: 15494 case X86ISD::PSHUFLW: 15495 case X86ISD::MOVSS: 15496 case X86ISD::MOVSD: 15497 case X86ISD::VPERMILP: 15498 case X86ISD::VPERM2X128: 15499 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15500 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget); 15501 } 15502 15503 return SDValue(); 15504} 15505 15506/// isTypeDesirableForOp - Return true if the target has native support for 15507/// the specified value type and it is 'desirable' to use the type for the 15508/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15509/// instruction encodings are longer and some i16 instructions are slow. 15510bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15511 if (!isTypeLegal(VT)) 15512 return false; 15513 if (VT != MVT::i16) 15514 return true; 15515 15516 switch (Opc) { 15517 default: 15518 return true; 15519 case ISD::LOAD: 15520 case ISD::SIGN_EXTEND: 15521 case ISD::ZERO_EXTEND: 15522 case ISD::ANY_EXTEND: 15523 case ISD::SHL: 15524 case ISD::SRL: 15525 case ISD::SUB: 15526 case ISD::ADD: 15527 case ISD::MUL: 15528 case ISD::AND: 15529 case ISD::OR: 15530 case ISD::XOR: 15531 return false; 15532 } 15533} 15534 15535/// IsDesirableToPromoteOp - This method query the target whether it is 15536/// beneficial for dag combiner to promote the specified node. If true, it 15537/// should return the desired promotion type by reference. 15538bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15539 EVT VT = Op.getValueType(); 15540 if (VT != MVT::i16) 15541 return false; 15542 15543 bool Promote = false; 15544 bool Commute = false; 15545 switch (Op.getOpcode()) { 15546 default: break; 15547 case ISD::LOAD: { 15548 LoadSDNode *LD = cast<LoadSDNode>(Op); 15549 // If the non-extending load has a single use and it's not live out, then it 15550 // might be folded. 15551 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15552 Op.hasOneUse()*/) { 15553 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15554 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15555 // The only case where we'd want to promote LOAD (rather then it being 15556 // promoted as an operand is when it's only use is liveout. 15557 if (UI->getOpcode() != ISD::CopyToReg) 15558 return false; 15559 } 15560 } 15561 Promote = true; 15562 break; 15563 } 15564 case ISD::SIGN_EXTEND: 15565 case ISD::ZERO_EXTEND: 15566 case ISD::ANY_EXTEND: 15567 Promote = true; 15568 break; 15569 case ISD::SHL: 15570 case ISD::SRL: { 15571 SDValue N0 = Op.getOperand(0); 15572 // Look out for (store (shl (load), x)). 15573 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15574 return false; 15575 Promote = true; 15576 break; 15577 } 15578 case ISD::ADD: 15579 case ISD::MUL: 15580 case ISD::AND: 15581 case ISD::OR: 15582 case ISD::XOR: 15583 Commute = true; 15584 // fallthrough 15585 case ISD::SUB: { 15586 SDValue N0 = Op.getOperand(0); 15587 SDValue N1 = Op.getOperand(1); 15588 if (!Commute && MayFoldLoad(N1)) 15589 return false; 15590 // Avoid disabling potential load folding opportunities. 15591 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15592 return false; 15593 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15594 return false; 15595 Promote = true; 15596 } 15597 } 15598 15599 PVT = MVT::i32; 15600 return Promote; 15601} 15602 15603//===----------------------------------------------------------------------===// 15604// X86 Inline Assembly Support 15605//===----------------------------------------------------------------------===// 15606 15607namespace { 15608 // Helper to match a string separated by whitespace. 15609 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15610 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15611 15612 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15613 StringRef piece(*args[i]); 15614 if (!s.startswith(piece)) // Check if the piece matches. 15615 return false; 15616 15617 s = s.substr(piece.size()); 15618 StringRef::size_type pos = s.find_first_not_of(" \t"); 15619 if (pos == 0) // We matched a prefix. 15620 return false; 15621 15622 s = s.substr(pos); 15623 } 15624 15625 return s.empty(); 15626 } 15627 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15628} 15629 15630bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15631 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15632 15633 std::string AsmStr = IA->getAsmString(); 15634 15635 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15636 if (!Ty || Ty->getBitWidth() % 16 != 0) 15637 return false; 15638 15639 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15640 SmallVector<StringRef, 4> AsmPieces; 15641 SplitString(AsmStr, AsmPieces, ";\n"); 15642 15643 switch (AsmPieces.size()) { 15644 default: return false; 15645 case 1: 15646 // FIXME: this should verify that we are targeting a 486 or better. If not, 15647 // we will turn this bswap into something that will be lowered to logical 15648 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15649 // lower so don't worry about this. 15650 // bswap $0 15651 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15652 matchAsm(AsmPieces[0], "bswapl", "$0") || 15653 matchAsm(AsmPieces[0], "bswapq", "$0") || 15654 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15655 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15656 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15657 // No need to check constraints, nothing other than the equivalent of 15658 // "=r,0" would be valid here. 15659 return IntrinsicLowering::LowerToByteSwap(CI); 15660 } 15661 15662 // rorw $$8, ${0:w} --> llvm.bswap.i16 15663 if (CI->getType()->isIntegerTy(16) && 15664 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15665 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15666 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15667 AsmPieces.clear(); 15668 const std::string &ConstraintsStr = IA->getConstraintString(); 15669 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15670 std::sort(AsmPieces.begin(), AsmPieces.end()); 15671 if (AsmPieces.size() == 4 && 15672 AsmPieces[0] == "~{cc}" && 15673 AsmPieces[1] == "~{dirflag}" && 15674 AsmPieces[2] == "~{flags}" && 15675 AsmPieces[3] == "~{fpsr}") 15676 return IntrinsicLowering::LowerToByteSwap(CI); 15677 } 15678 break; 15679 case 3: 15680 if (CI->getType()->isIntegerTy(32) && 15681 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15682 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15683 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15684 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15685 AsmPieces.clear(); 15686 const std::string &ConstraintsStr = IA->getConstraintString(); 15687 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15688 std::sort(AsmPieces.begin(), AsmPieces.end()); 15689 if (AsmPieces.size() == 4 && 15690 AsmPieces[0] == "~{cc}" && 15691 AsmPieces[1] == "~{dirflag}" && 15692 AsmPieces[2] == "~{flags}" && 15693 AsmPieces[3] == "~{fpsr}") 15694 return IntrinsicLowering::LowerToByteSwap(CI); 15695 } 15696 15697 if (CI->getType()->isIntegerTy(64)) { 15698 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15699 if (Constraints.size() >= 2 && 15700 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15701 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15702 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15703 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15704 matchAsm(AsmPieces[1], "bswap", "%edx") && 15705 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15706 return IntrinsicLowering::LowerToByteSwap(CI); 15707 } 15708 } 15709 break; 15710 } 15711 return false; 15712} 15713 15714 15715 15716/// getConstraintType - Given a constraint letter, return the type of 15717/// constraint it is for this target. 15718X86TargetLowering::ConstraintType 15719X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15720 if (Constraint.size() == 1) { 15721 switch (Constraint[0]) { 15722 case 'R': 15723 case 'q': 15724 case 'Q': 15725 case 'f': 15726 case 't': 15727 case 'u': 15728 case 'y': 15729 case 'x': 15730 case 'Y': 15731 case 'l': 15732 return C_RegisterClass; 15733 case 'a': 15734 case 'b': 15735 case 'c': 15736 case 'd': 15737 case 'S': 15738 case 'D': 15739 case 'A': 15740 return C_Register; 15741 case 'I': 15742 case 'J': 15743 case 'K': 15744 case 'L': 15745 case 'M': 15746 case 'N': 15747 case 'G': 15748 case 'C': 15749 case 'e': 15750 case 'Z': 15751 return C_Other; 15752 default: 15753 break; 15754 } 15755 } 15756 return TargetLowering::getConstraintType(Constraint); 15757} 15758 15759/// Examine constraint type and operand type and determine a weight value. 15760/// This object must already have been set up with the operand type 15761/// and the current alternative constraint selected. 15762TargetLowering::ConstraintWeight 15763 X86TargetLowering::getSingleConstraintMatchWeight( 15764 AsmOperandInfo &info, const char *constraint) const { 15765 ConstraintWeight weight = CW_Invalid; 15766 Value *CallOperandVal = info.CallOperandVal; 15767 // If we don't have a value, we can't do a match, 15768 // but allow it at the lowest weight. 15769 if (CallOperandVal == NULL) 15770 return CW_Default; 15771 Type *type = CallOperandVal->getType(); 15772 // Look at the constraint type. 15773 switch (*constraint) { 15774 default: 15775 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15776 case 'R': 15777 case 'q': 15778 case 'Q': 15779 case 'a': 15780 case 'b': 15781 case 'c': 15782 case 'd': 15783 case 'S': 15784 case 'D': 15785 case 'A': 15786 if (CallOperandVal->getType()->isIntegerTy()) 15787 weight = CW_SpecificReg; 15788 break; 15789 case 'f': 15790 case 't': 15791 case 'u': 15792 if (type->isFloatingPointTy()) 15793 weight = CW_SpecificReg; 15794 break; 15795 case 'y': 15796 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15797 weight = CW_SpecificReg; 15798 break; 15799 case 'x': 15800 case 'Y': 15801 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15802 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15803 weight = CW_Register; 15804 break; 15805 case 'I': 15806 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15807 if (C->getZExtValue() <= 31) 15808 weight = CW_Constant; 15809 } 15810 break; 15811 case 'J': 15812 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15813 if (C->getZExtValue() <= 63) 15814 weight = CW_Constant; 15815 } 15816 break; 15817 case 'K': 15818 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15819 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15820 weight = CW_Constant; 15821 } 15822 break; 15823 case 'L': 15824 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15825 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15826 weight = CW_Constant; 15827 } 15828 break; 15829 case 'M': 15830 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15831 if (C->getZExtValue() <= 3) 15832 weight = CW_Constant; 15833 } 15834 break; 15835 case 'N': 15836 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15837 if (C->getZExtValue() <= 0xff) 15838 weight = CW_Constant; 15839 } 15840 break; 15841 case 'G': 15842 case 'C': 15843 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15844 weight = CW_Constant; 15845 } 15846 break; 15847 case 'e': 15848 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15849 if ((C->getSExtValue() >= -0x80000000LL) && 15850 (C->getSExtValue() <= 0x7fffffffLL)) 15851 weight = CW_Constant; 15852 } 15853 break; 15854 case 'Z': 15855 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15856 if (C->getZExtValue() <= 0xffffffff) 15857 weight = CW_Constant; 15858 } 15859 break; 15860 } 15861 return weight; 15862} 15863 15864/// LowerXConstraint - try to replace an X constraint, which matches anything, 15865/// with another that has more specific requirements based on the type of the 15866/// corresponding operand. 15867const char *X86TargetLowering:: 15868LowerXConstraint(EVT ConstraintVT) const { 15869 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15870 // 'f' like normal targets. 15871 if (ConstraintVT.isFloatingPoint()) { 15872 if (Subtarget->hasSSE2()) 15873 return "Y"; 15874 if (Subtarget->hasSSE1()) 15875 return "x"; 15876 } 15877 15878 return TargetLowering::LowerXConstraint(ConstraintVT); 15879} 15880 15881/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15882/// vector. If it is invalid, don't add anything to Ops. 15883void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15884 std::string &Constraint, 15885 std::vector<SDValue>&Ops, 15886 SelectionDAG &DAG) const { 15887 SDValue Result(0, 0); 15888 15889 // Only support length 1 constraints for now. 15890 if (Constraint.length() > 1) return; 15891 15892 char ConstraintLetter = Constraint[0]; 15893 switch (ConstraintLetter) { 15894 default: break; 15895 case 'I': 15896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15897 if (C->getZExtValue() <= 31) { 15898 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15899 break; 15900 } 15901 } 15902 return; 15903 case 'J': 15904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15905 if (C->getZExtValue() <= 63) { 15906 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15907 break; 15908 } 15909 } 15910 return; 15911 case 'K': 15912 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15913 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15914 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15915 break; 15916 } 15917 } 15918 return; 15919 case 'N': 15920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15921 if (C->getZExtValue() <= 255) { 15922 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15923 break; 15924 } 15925 } 15926 return; 15927 case 'e': { 15928 // 32-bit signed value 15929 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15930 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15931 C->getSExtValue())) { 15932 // Widen to 64 bits here to get it sign extended. 15933 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15934 break; 15935 } 15936 // FIXME gcc accepts some relocatable values here too, but only in certain 15937 // memory models; it's complicated. 15938 } 15939 return; 15940 } 15941 case 'Z': { 15942 // 32-bit unsigned value 15943 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15944 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15945 C->getZExtValue())) { 15946 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15947 break; 15948 } 15949 } 15950 // FIXME gcc accepts some relocatable values here too, but only in certain 15951 // memory models; it's complicated. 15952 return; 15953 } 15954 case 'i': { 15955 // Literal immediates are always ok. 15956 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15957 // Widen to 64 bits here to get it sign extended. 15958 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15959 break; 15960 } 15961 15962 // In any sort of PIC mode addresses need to be computed at runtime by 15963 // adding in a register or some sort of table lookup. These can't 15964 // be used as immediates. 15965 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15966 return; 15967 15968 // If we are in non-pic codegen mode, we allow the address of a global (with 15969 // an optional displacement) to be used with 'i'. 15970 GlobalAddressSDNode *GA = 0; 15971 int64_t Offset = 0; 15972 15973 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15974 while (1) { 15975 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15976 Offset += GA->getOffset(); 15977 break; 15978 } else if (Op.getOpcode() == ISD::ADD) { 15979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15980 Offset += C->getZExtValue(); 15981 Op = Op.getOperand(0); 15982 continue; 15983 } 15984 } else if (Op.getOpcode() == ISD::SUB) { 15985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15986 Offset += -C->getZExtValue(); 15987 Op = Op.getOperand(0); 15988 continue; 15989 } 15990 } 15991 15992 // Otherwise, this isn't something we can handle, reject it. 15993 return; 15994 } 15995 15996 const GlobalValue *GV = GA->getGlobal(); 15997 // If we require an extra load to get this address, as in PIC mode, we 15998 // can't accept it. 15999 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 16000 getTargetMachine()))) 16001 return; 16002 16003 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 16004 GA->getValueType(0), Offset); 16005 break; 16006 } 16007 } 16008 16009 if (Result.getNode()) { 16010 Ops.push_back(Result); 16011 return; 16012 } 16013 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 16014} 16015 16016std::pair<unsigned, const TargetRegisterClass*> 16017X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 16018 EVT VT) const { 16019 // First, see if this is a constraint that directly corresponds to an LLVM 16020 // register class. 16021 if (Constraint.size() == 1) { 16022 // GCC Constraint Letters 16023 switch (Constraint[0]) { 16024 default: break; 16025 // TODO: Slight differences here in allocation order and leaving 16026 // RIP in the class. Do they matter any more here than they do 16027 // in the normal allocation? 16028 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 16029 if (Subtarget->is64Bit()) { 16030 if (VT == MVT::i32 || VT == MVT::f32) 16031 return std::make_pair(0U, &X86::GR32RegClass); 16032 if (VT == MVT::i16) 16033 return std::make_pair(0U, &X86::GR16RegClass); 16034 if (VT == MVT::i8 || VT == MVT::i1) 16035 return std::make_pair(0U, &X86::GR8RegClass); 16036 if (VT == MVT::i64 || VT == MVT::f64) 16037 return std::make_pair(0U, &X86::GR64RegClass); 16038 break; 16039 } 16040 // 32-bit fallthrough 16041 case 'Q': // Q_REGS 16042 if (VT == MVT::i32 || VT == MVT::f32) 16043 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 16044 if (VT == MVT::i16) 16045 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 16046 if (VT == MVT::i8 || VT == MVT::i1) 16047 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 16048 if (VT == MVT::i64) 16049 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 16050 break; 16051 case 'r': // GENERAL_REGS 16052 case 'l': // INDEX_REGS 16053 if (VT == MVT::i8 || VT == MVT::i1) 16054 return std::make_pair(0U, &X86::GR8RegClass); 16055 if (VT == MVT::i16) 16056 return std::make_pair(0U, &X86::GR16RegClass); 16057 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 16058 return std::make_pair(0U, &X86::GR32RegClass); 16059 return std::make_pair(0U, &X86::GR64RegClass); 16060 case 'R': // LEGACY_REGS 16061 if (VT == MVT::i8 || VT == MVT::i1) 16062 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 16063 if (VT == MVT::i16) 16064 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 16065 if (VT == MVT::i32 || !Subtarget->is64Bit()) 16066 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 16067 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 16068 case 'f': // FP Stack registers. 16069 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 16070 // value to the correct fpstack register class. 16071 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 16072 return std::make_pair(0U, &X86::RFP32RegClass); 16073 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 16074 return std::make_pair(0U, &X86::RFP64RegClass); 16075 return std::make_pair(0U, &X86::RFP80RegClass); 16076 case 'y': // MMX_REGS if MMX allowed. 16077 if (!Subtarget->hasMMX()) break; 16078 return std::make_pair(0U, &X86::VR64RegClass); 16079 case 'Y': // SSE_REGS if SSE2 allowed 16080 if (!Subtarget->hasSSE2()) break; 16081 // FALL THROUGH. 16082 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 16083 if (!Subtarget->hasSSE1()) break; 16084 16085 switch (VT.getSimpleVT().SimpleTy) { 16086 default: break; 16087 // Scalar SSE types. 16088 case MVT::f32: 16089 case MVT::i32: 16090 return std::make_pair(0U, &X86::FR32RegClass); 16091 case MVT::f64: 16092 case MVT::i64: 16093 return std::make_pair(0U, &X86::FR64RegClass); 16094 // Vector types. 16095 case MVT::v16i8: 16096 case MVT::v8i16: 16097 case MVT::v4i32: 16098 case MVT::v2i64: 16099 case MVT::v4f32: 16100 case MVT::v2f64: 16101 return std::make_pair(0U, &X86::VR128RegClass); 16102 // AVX types. 16103 case MVT::v32i8: 16104 case MVT::v16i16: 16105 case MVT::v8i32: 16106 case MVT::v4i64: 16107 case MVT::v8f32: 16108 case MVT::v4f64: 16109 return std::make_pair(0U, &X86::VR256RegClass); 16110 } 16111 break; 16112 } 16113 } 16114 16115 // Use the default implementation in TargetLowering to convert the register 16116 // constraint into a member of a register class. 16117 std::pair<unsigned, const TargetRegisterClass*> Res; 16118 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 16119 16120 // Not found as a standard register? 16121 if (Res.second == 0) { 16122 // Map st(0) -> st(7) -> ST0 16123 if (Constraint.size() == 7 && Constraint[0] == '{' && 16124 tolower(Constraint[1]) == 's' && 16125 tolower(Constraint[2]) == 't' && 16126 Constraint[3] == '(' && 16127 (Constraint[4] >= '0' && Constraint[4] <= '7') && 16128 Constraint[5] == ')' && 16129 Constraint[6] == '}') { 16130 16131 Res.first = X86::ST0+Constraint[4]-'0'; 16132 Res.second = &X86::RFP80RegClass; 16133 return Res; 16134 } 16135 16136 // GCC allows "st(0)" to be called just plain "st". 16137 if (StringRef("{st}").equals_lower(Constraint)) { 16138 Res.first = X86::ST0; 16139 Res.second = &X86::RFP80RegClass; 16140 return Res; 16141 } 16142 16143 // flags -> EFLAGS 16144 if (StringRef("{flags}").equals_lower(Constraint)) { 16145 Res.first = X86::EFLAGS; 16146 Res.second = &X86::CCRRegClass; 16147 return Res; 16148 } 16149 16150 // 'A' means EAX + EDX. 16151 if (Constraint == "A") { 16152 Res.first = X86::EAX; 16153 Res.second = &X86::GR32_ADRegClass; 16154 return Res; 16155 } 16156 return Res; 16157 } 16158 16159 // Otherwise, check to see if this is a register class of the wrong value 16160 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 16161 // turn into {ax},{dx}. 16162 if (Res.second->hasType(VT)) 16163 return Res; // Correct type already, nothing to do. 16164 16165 // All of the single-register GCC register classes map their values onto 16166 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 16167 // really want an 8-bit or 32-bit register, map to the appropriate register 16168 // class and return the appropriate register. 16169 if (Res.second == &X86::GR16RegClass) { 16170 if (VT == MVT::i8) { 16171 unsigned DestReg = 0; 16172 switch (Res.first) { 16173 default: break; 16174 case X86::AX: DestReg = X86::AL; break; 16175 case X86::DX: DestReg = X86::DL; break; 16176 case X86::CX: DestReg = X86::CL; break; 16177 case X86::BX: DestReg = X86::BL; break; 16178 } 16179 if (DestReg) { 16180 Res.first = DestReg; 16181 Res.second = &X86::GR8RegClass; 16182 } 16183 } else if (VT == MVT::i32) { 16184 unsigned DestReg = 0; 16185 switch (Res.first) { 16186 default: break; 16187 case X86::AX: DestReg = X86::EAX; break; 16188 case X86::DX: DestReg = X86::EDX; break; 16189 case X86::CX: DestReg = X86::ECX; break; 16190 case X86::BX: DestReg = X86::EBX; break; 16191 case X86::SI: DestReg = X86::ESI; break; 16192 case X86::DI: DestReg = X86::EDI; break; 16193 case X86::BP: DestReg = X86::EBP; break; 16194 case X86::SP: DestReg = X86::ESP; break; 16195 } 16196 if (DestReg) { 16197 Res.first = DestReg; 16198 Res.second = &X86::GR32RegClass; 16199 } 16200 } else if (VT == MVT::i64) { 16201 unsigned DestReg = 0; 16202 switch (Res.first) { 16203 default: break; 16204 case X86::AX: DestReg = X86::RAX; break; 16205 case X86::DX: DestReg = X86::RDX; break; 16206 case X86::CX: DestReg = X86::RCX; break; 16207 case X86::BX: DestReg = X86::RBX; break; 16208 case X86::SI: DestReg = X86::RSI; break; 16209 case X86::DI: DestReg = X86::RDI; break; 16210 case X86::BP: DestReg = X86::RBP; break; 16211 case X86::SP: DestReg = X86::RSP; break; 16212 } 16213 if (DestReg) { 16214 Res.first = DestReg; 16215 Res.second = &X86::GR64RegClass; 16216 } 16217 } 16218 } else if (Res.second == &X86::FR32RegClass || 16219 Res.second == &X86::FR64RegClass || 16220 Res.second == &X86::VR128RegClass) { 16221 // Handle references to XMM physical registers that got mapped into the 16222 // wrong class. This can happen with constraints like {xmm0} where the 16223 // target independent register mapper will just pick the first match it can 16224 // find, ignoring the required type. 16225 16226 if (VT == MVT::f32 || VT == MVT::i32) 16227 Res.second = &X86::FR32RegClass; 16228 else if (VT == MVT::f64 || VT == MVT::i64) 16229 Res.second = &X86::FR64RegClass; 16230 else if (X86::VR128RegClass.hasType(VT)) 16231 Res.second = &X86::VR128RegClass; 16232 else if (X86::VR256RegClass.hasType(VT)) 16233 Res.second = &X86::VR256RegClass; 16234 } 16235 16236 return Res; 16237} 16238