X86ISelLowering.cpp revision 1c39d4cfaa80addcf8ef4e298be63fc5831b8efe
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Function.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/ADT/BitVector.h" 27#include "llvm/ADT/VectorExtras.h" 28#include "llvm/CodeGen/CallingConvLower.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/CodeGen/PseudoSourceValue.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/ADT/SmallSet.h" 40#include "llvm/ADT/StringExtras.h" 41#include "llvm/Support/CommandLine.h" 42using namespace llvm; 43 44static cl::opt<bool> 45DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 46 47// Forward declarations. 48static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG); 49 50X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 51 : TargetLowering(TM) { 52 Subtarget = &TM.getSubtarget<X86Subtarget>(); 53 X86ScalarSSEf64 = Subtarget->hasSSE2(); 54 X86ScalarSSEf32 = Subtarget->hasSSE1(); 55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 56 57 bool Fast = false; 58 59 RegInfo = TM.getRegisterInfo(); 60 TD = getTargetData(); 61 62 // Set up the TargetLowering object. 63 64 // X86 is weird, it always uses i8 for shift amounts and setcc results. 65 setShiftAmountType(MVT::i8); 66 setBooleanContents(ZeroOrOneBooleanContent); 67 setSchedulingPreference(SchedulingForRegPressure); 68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 69 setStackPointerRegisterToSaveRestore(X86StackPtr); 70 71 if (Subtarget->isTargetDarwin()) { 72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(false); 74 setUseUnderscoreLongJmp(false); 75 } else if (Subtarget->isTargetMingw()) { 76 // MS runtime is weird: it exports _setjmp, but longjmp! 77 setUseUnderscoreSetJmp(true); 78 setUseUnderscoreLongJmp(false); 79 } else { 80 setUseUnderscoreSetJmp(true); 81 setUseUnderscoreLongJmp(true); 82 } 83 84 // Set up the register classes. 85 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 86 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 87 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 88 if (Subtarget->is64Bit()) 89 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 90 91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 92 93 // We don't accept any truncstore of integer registers. 94 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 95 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 97 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 99 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 100 101 // SETOEQ and SETUNE require checking two conditions. 102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 108 109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 110 // operation. 111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 114 115 if (Subtarget->is64Bit()) { 116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 118 } else { 119 if (X86ScalarSSEf64) { 120 // We have an impenetrably clever algorithm for ui64->double only. 121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 122 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. 123 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 124 } else 125 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 126 } 127 128 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 129 // this operation. 130 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 131 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 132 // SSE has no i16 to fp conversion, only i32 133 if (X86ScalarSSEf32) { 134 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 135 // f32 and f64 cases are Legal, f80 case is not 136 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 137 } else { 138 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 139 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 140 } 141 142 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 143 // are Legal, f80 is custom lowered. 144 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 145 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 146 147 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 148 // this operation. 149 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 150 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 151 152 if (X86ScalarSSEf32) { 153 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 154 // f32 and f64 cases are Legal, f80 case is not 155 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 156 } else { 157 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 158 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 159 } 160 161 // Handle FP_TO_UINT by promoting the destination to a larger signed 162 // conversion. 163 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 164 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 165 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 166 167 if (Subtarget->is64Bit()) { 168 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 169 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 170 } else { 171 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 172 // Expand FP_TO_UINT into a select. 173 // FIXME: We would like to use a Custom expander here eventually to do 174 // the optimal thing for SSE vs. the default expansion in the legalizer. 175 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 176 else 177 // With SSE3 we can use fisttpll to convert to a signed i64. 178 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 179 } 180 181 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 182 if (!X86ScalarSSEf64) { 183 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 184 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 185 } 186 187 // Scalar integer divide and remainder are lowered to use operations that 188 // produce two results, to match the available instructions. This exposes 189 // the two-result form to trivial CSE, which is able to combine x/y and x%y 190 // into a single instruction. 191 // 192 // Scalar integer multiply-high is also lowered to use two-result 193 // operations, to match the available instructions. However, plain multiply 194 // (low) operations are left as Legal, as there are single-result 195 // instructions for this in x86. Using the two-result multiply instructions 196 // when both high and low results are needed must be arranged by dagcombine. 197 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 198 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 199 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 200 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 201 setOperationAction(ISD::SREM , MVT::i8 , Expand); 202 setOperationAction(ISD::UREM , MVT::i8 , Expand); 203 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 204 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 205 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 206 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 207 setOperationAction(ISD::SREM , MVT::i16 , Expand); 208 setOperationAction(ISD::UREM , MVT::i16 , Expand); 209 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 210 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 211 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 212 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 213 setOperationAction(ISD::SREM , MVT::i32 , Expand); 214 setOperationAction(ISD::UREM , MVT::i32 , Expand); 215 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 216 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 217 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 218 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 219 setOperationAction(ISD::SREM , MVT::i64 , Expand); 220 setOperationAction(ISD::UREM , MVT::i64 , Expand); 221 222 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 223 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 224 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 225 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 226 if (Subtarget->is64Bit()) 227 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 231 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 232 setOperationAction(ISD::FREM , MVT::f32 , Expand); 233 setOperationAction(ISD::FREM , MVT::f64 , Expand); 234 setOperationAction(ISD::FREM , MVT::f80 , Expand); 235 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 236 237 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 238 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 239 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 240 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 241 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 242 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 243 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 244 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 245 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 246 if (Subtarget->is64Bit()) { 247 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 248 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 249 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 250 } 251 252 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 253 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 254 255 // These should be promoted to a larger select which is supported. 256 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 257 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 258 // X86 wants to expand cmov itself. 259 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 260 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 261 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 262 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 263 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 264 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 265 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 266 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 267 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 268 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 269 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 270 if (Subtarget->is64Bit()) { 271 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 272 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 273 } 274 // X86 ret instruction may pop stack. 275 setOperationAction(ISD::RET , MVT::Other, Custom); 276 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 277 278 // Darwin ABI issue. 279 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 280 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 281 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 282 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 283 if (Subtarget->is64Bit()) 284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 285 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 286 if (Subtarget->is64Bit()) { 287 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 288 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 289 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 290 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 291 } 292 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 293 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 294 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 295 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 296 if (Subtarget->is64Bit()) { 297 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 298 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 299 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 300 } 301 302 if (Subtarget->hasSSE1()) 303 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 304 305 if (!Subtarget->hasSSE2()) 306 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 307 308 // Expand certain atomics 309 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 313 314 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 318 319 if (!Subtarget->is64Bit()) { 320 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 321 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 322 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 323 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 324 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 325 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 326 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 327 } 328 329 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. 330 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 331 // FIXME - use subtarget debug flags 332 if (!Subtarget->isTargetDarwin() && 333 !Subtarget->isTargetELF() && 334 !Subtarget->isTargetCygMing()) { 335 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 336 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 337 } 338 339 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 340 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 341 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 342 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 343 if (Subtarget->is64Bit()) { 344 setExceptionPointerRegister(X86::RAX); 345 setExceptionSelectorRegister(X86::RDX); 346 } else { 347 setExceptionPointerRegister(X86::EAX); 348 setExceptionSelectorRegister(X86::EDX); 349 } 350 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 352 353 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 354 355 setOperationAction(ISD::TRAP, MVT::Other, Legal); 356 357 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 358 setOperationAction(ISD::VASTART , MVT::Other, Custom); 359 setOperationAction(ISD::VAEND , MVT::Other, Expand); 360 if (Subtarget->is64Bit()) { 361 setOperationAction(ISD::VAARG , MVT::Other, Custom); 362 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 363 } else { 364 setOperationAction(ISD::VAARG , MVT::Other, Expand); 365 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 366 } 367 368 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 369 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 370 if (Subtarget->is64Bit()) 371 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 372 if (Subtarget->isTargetCygMing()) 373 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 374 else 375 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 376 377 if (X86ScalarSSEf64) { 378 // f32 and f64 use SSE. 379 // Set up the FP register classes. 380 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 381 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 382 383 // Use ANDPD to simulate FABS. 384 setOperationAction(ISD::FABS , MVT::f64, Custom); 385 setOperationAction(ISD::FABS , MVT::f32, Custom); 386 387 // Use XORP to simulate FNEG. 388 setOperationAction(ISD::FNEG , MVT::f64, Custom); 389 setOperationAction(ISD::FNEG , MVT::f32, Custom); 390 391 // Use ANDPD and ORPD to simulate FCOPYSIGN. 392 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 393 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 394 395 // We don't support sin/cos/fmod 396 setOperationAction(ISD::FSIN , MVT::f64, Expand); 397 setOperationAction(ISD::FCOS , MVT::f64, Expand); 398 setOperationAction(ISD::FSIN , MVT::f32, Expand); 399 setOperationAction(ISD::FCOS , MVT::f32, Expand); 400 401 // Expand FP immediates into loads from the stack, except for the special 402 // cases we handle. 403 addLegalFPImmediate(APFloat(+0.0)); // xorpd 404 addLegalFPImmediate(APFloat(+0.0f)); // xorps 405 406 // Floating truncations from f80 and extensions to f80 go through memory. 407 // If optimizing, we lie about this though and handle it in 408 // InstructionSelectPreprocess so that dagcombine2 can hack on these. 409 if (Fast) { 410 setConvertAction(MVT::f32, MVT::f80, Expand); 411 setConvertAction(MVT::f64, MVT::f80, Expand); 412 setConvertAction(MVT::f80, MVT::f32, Expand); 413 setConvertAction(MVT::f80, MVT::f64, Expand); 414 } 415 } else if (X86ScalarSSEf32) { 416 // Use SSE for f32, x87 for f64. 417 // Set up the FP register classes. 418 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 419 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 420 421 // Use ANDPS to simulate FABS. 422 setOperationAction(ISD::FABS , MVT::f32, Custom); 423 424 // Use XORP to simulate FNEG. 425 setOperationAction(ISD::FNEG , MVT::f32, Custom); 426 427 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 428 429 // Use ANDPS and ORPS to simulate FCOPYSIGN. 430 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 431 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 432 433 // We don't support sin/cos/fmod 434 setOperationAction(ISD::FSIN , MVT::f32, Expand); 435 setOperationAction(ISD::FCOS , MVT::f32, Expand); 436 437 // Special cases we handle for FP constants. 438 addLegalFPImmediate(APFloat(+0.0f)); // xorps 439 addLegalFPImmediate(APFloat(+0.0)); // FLD0 440 addLegalFPImmediate(APFloat(+1.0)); // FLD1 441 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 442 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 443 444 // SSE <-> X87 conversions go through memory. If optimizing, we lie about 445 // this though and handle it in InstructionSelectPreprocess so that 446 // dagcombine2 can hack on these. 447 if (Fast) { 448 setConvertAction(MVT::f32, MVT::f64, Expand); 449 setConvertAction(MVT::f32, MVT::f80, Expand); 450 setConvertAction(MVT::f80, MVT::f32, Expand); 451 setConvertAction(MVT::f64, MVT::f32, Expand); 452 // And x87->x87 truncations also. 453 setConvertAction(MVT::f80, MVT::f64, Expand); 454 } 455 456 if (!UnsafeFPMath) { 457 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 458 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 459 } 460 } else { 461 // f32 and f64 in x87. 462 // Set up the FP register classes. 463 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 464 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 465 466 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 467 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 468 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 469 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 470 471 // Floating truncations go through memory. If optimizing, we lie about 472 // this though and handle it in InstructionSelectPreprocess so that 473 // dagcombine2 can hack on these. 474 if (Fast) { 475 setConvertAction(MVT::f80, MVT::f32, Expand); 476 setConvertAction(MVT::f64, MVT::f32, Expand); 477 setConvertAction(MVT::f80, MVT::f64, Expand); 478 } 479 480 if (!UnsafeFPMath) { 481 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 482 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 483 } 484 addLegalFPImmediate(APFloat(+0.0)); // FLD0 485 addLegalFPImmediate(APFloat(+1.0)); // FLD1 486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 488 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 489 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 490 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 491 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 492 } 493 494 // Long double always uses X87. 495 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 496 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 497 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 498 { 499 bool ignored; 500 APFloat TmpFlt(+0.0); 501 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 502 &ignored); 503 addLegalFPImmediate(TmpFlt); // FLD0 504 TmpFlt.changeSign(); 505 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 506 APFloat TmpFlt2(+1.0); 507 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 508 &ignored); 509 addLegalFPImmediate(TmpFlt2); // FLD1 510 TmpFlt2.changeSign(); 511 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 512 } 513 514 if (!UnsafeFPMath) { 515 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 516 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 517 } 518 519 // Always use a library call for pow. 520 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 521 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 522 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 523 524 setOperationAction(ISD::FLOG, MVT::f80, Expand); 525 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 526 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 527 setOperationAction(ISD::FEXP, MVT::f80, Expand); 528 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 529 530 // First set operation action for all vector types to either promote 531 // (for widening) or expand (for scalarization). Then we will selectively 532 // turn on ones that can be effectively codegen'd. 533 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 534 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 535 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 538 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 539 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 540 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 541 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 542 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 543 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 546 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 547 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 548 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 549 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 550 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 551 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 578 } 579 580 if (!DisableMMX && Subtarget->hasMMX()) { 581 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 582 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 583 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 584 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 585 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 586 587 // FIXME: add MMX packed arithmetics 588 589 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 590 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 591 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 592 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 593 594 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 595 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 596 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 597 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 598 599 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 600 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 601 602 setOperationAction(ISD::AND, MVT::v8i8, Promote); 603 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 604 setOperationAction(ISD::AND, MVT::v4i16, Promote); 605 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 606 setOperationAction(ISD::AND, MVT::v2i32, Promote); 607 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 608 setOperationAction(ISD::AND, MVT::v1i64, Legal); 609 610 setOperationAction(ISD::OR, MVT::v8i8, Promote); 611 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 612 setOperationAction(ISD::OR, MVT::v4i16, Promote); 613 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 614 setOperationAction(ISD::OR, MVT::v2i32, Promote); 615 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 616 setOperationAction(ISD::OR, MVT::v1i64, Legal); 617 618 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 619 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 620 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 621 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 622 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 623 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 624 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 625 626 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 627 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 628 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 629 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 630 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 631 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 632 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 633 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 634 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 635 636 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 637 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 638 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 640 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 641 642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 646 647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 651 652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 653 654 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); 655 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); 656 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 657 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 658 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 659 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 660 } 661 662 if (Subtarget->hasSSE1()) { 663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 664 665 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 677 } 678 679 if (Subtarget->hasSSE2()) { 680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 681 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 682 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 683 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 684 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 685 686 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 687 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 688 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 689 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 690 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 691 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 692 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 693 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 694 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 695 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 696 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 697 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 698 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 699 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 700 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 701 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 702 703 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 704 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 705 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 706 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 707 708 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 710 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 713 714 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 715 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 716 MVT VT = (MVT::SimpleValueType)i; 717 // Do not attempt to custom lower non-power-of-2 vectors 718 if (!isPowerOf2_32(VT.getVectorNumElements())) 719 continue; 720 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 721 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 723 } 724 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 725 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 726 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 727 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 728 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 729 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 730 if (Subtarget->is64Bit()) { 731 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 732 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 733 } 734 735 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 736 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 737 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote); 738 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64); 739 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote); 740 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64); 741 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote); 742 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64); 743 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote); 744 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64); 745 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote); 746 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64); 747 } 748 749 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 750 751 // Custom lower v2i64 and v2f64 selects. 752 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 753 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 754 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 755 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 756 757 } 758 759 if (Subtarget->hasSSE41()) { 760 // FIXME: Do we need to handle scalar-to-vector here? 761 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 762 763 // i8 and i16 vectors are custom , because the source register and source 764 // source memory operand types are not the same width. f32 vectors are 765 // custom since the immediate controlling the insert encodes additional 766 // information. 767 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); 770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 771 772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); 775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 776 777 if (Subtarget->is64Bit()) { 778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 780 } 781 } 782 783 if (Subtarget->hasSSE42()) { 784 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 785 } 786 787 // We want to custom lower some of our intrinsics. 788 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 789 790 // Add/Sub/Mul with overflow operations are custom lowered. 791 setOperationAction(ISD::SADDO, MVT::i32, Custom); 792 setOperationAction(ISD::SADDO, MVT::i64, Custom); 793 setOperationAction(ISD::UADDO, MVT::i32, Custom); 794 setOperationAction(ISD::UADDO, MVT::i64, Custom); 795 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 796 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 797 setOperationAction(ISD::USUBO, MVT::i32, Custom); 798 setOperationAction(ISD::USUBO, MVT::i64, Custom); 799 setOperationAction(ISD::SMULO, MVT::i32, Custom); 800 setOperationAction(ISD::SMULO, MVT::i64, Custom); 801 setOperationAction(ISD::UMULO, MVT::i32, Custom); 802 setOperationAction(ISD::UMULO, MVT::i64, Custom); 803 804 // We have target-specific dag combine patterns for the following nodes: 805 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 806 setTargetDAGCombine(ISD::BUILD_VECTOR); 807 setTargetDAGCombine(ISD::SELECT); 808 setTargetDAGCombine(ISD::STORE); 809 810 computeRegisterProperties(); 811 812 // FIXME: These should be based on subtarget info. Plus, the values should 813 // be smaller when we are in optimizing for size mode. 814 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 815 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 816 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 817 allowUnalignedMemoryAccesses = true; // x86 supports it! 818 setPrefLoopAlignment(16); 819} 820 821 822MVT X86TargetLowering::getSetCCResultType(const SDValue &) const { 823 return MVT::i8; 824} 825 826 827/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 828/// the desired ByVal argument alignment. 829static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 830 if (MaxAlign == 16) 831 return; 832 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 833 if (VTy->getBitWidth() == 128) 834 MaxAlign = 16; 835 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 836 unsigned EltAlign = 0; 837 getMaxByValAlign(ATy->getElementType(), EltAlign); 838 if (EltAlign > MaxAlign) 839 MaxAlign = EltAlign; 840 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 841 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 842 unsigned EltAlign = 0; 843 getMaxByValAlign(STy->getElementType(i), EltAlign); 844 if (EltAlign > MaxAlign) 845 MaxAlign = EltAlign; 846 if (MaxAlign == 16) 847 break; 848 } 849 } 850 return; 851} 852 853/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 854/// function arguments in the caller parameter area. For X86, aggregates 855/// that contain SSE vectors are placed at 16-byte boundaries while the rest 856/// are at 4-byte boundaries. 857unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 858 if (Subtarget->is64Bit()) { 859 // Max of 8 and alignment of type. 860 unsigned TyAlign = TD->getABITypeAlignment(Ty); 861 if (TyAlign > 8) 862 return TyAlign; 863 return 8; 864 } 865 866 unsigned Align = 4; 867 if (Subtarget->hasSSE1()) 868 getMaxByValAlign(Ty, Align); 869 return Align; 870} 871 872/// getOptimalMemOpType - Returns the target specific optimal type for load 873/// and store operations as a result of memset, memcpy, and memmove 874/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 875/// determining it. 876MVT 877X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 878 bool isSrcConst, bool isSrcStr) const { 879 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 880 // linux. This is because the stack realignment code can't handle certain 881 // cases like PR2962. This should be removed when PR2962 is fixed. 882 if (Subtarget->getStackAlignment() >= 16) { 883 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 884 return MVT::v4i32; 885 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 886 return MVT::v4f32; 887 } 888 if (Subtarget->is64Bit() && Size >= 8) 889 return MVT::i64; 890 return MVT::i32; 891} 892 893 894/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 895/// jumptable. 896SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 897 SelectionDAG &DAG) const { 898 if (usesGlobalOffsetTable()) 899 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 900 if (!Subtarget->isPICStyleRIPRel()) 901 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()); 902 return Table; 903} 904 905//===----------------------------------------------------------------------===// 906// Return Value Calling Convention Implementation 907//===----------------------------------------------------------------------===// 908 909#include "X86GenCallingConv.inc" 910 911/// LowerRET - Lower an ISD::RET node. 912SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 913 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 914 915 SmallVector<CCValAssign, 16> RVLocs; 916 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 917 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 918 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 919 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86); 920 921 // If this is the first return lowered for this function, add the regs to the 922 // liveout set for the function. 923 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 924 for (unsigned i = 0; i != RVLocs.size(); ++i) 925 if (RVLocs[i].isRegLoc()) 926 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 927 } 928 SDValue Chain = Op.getOperand(0); 929 930 // Handle tail call return. 931 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); 932 if (Chain.getOpcode() == X86ISD::TAILCALL) { 933 SDValue TailCall = Chain; 934 SDValue TargetAddress = TailCall.getOperand(1); 935 SDValue StackAdjustment = TailCall.getOperand(2); 936 assert(((TargetAddress.getOpcode() == ISD::Register && 937 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX || 938 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || 939 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 940 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 941 "Expecting an global address, external symbol, or register"); 942 assert(StackAdjustment.getOpcode() == ISD::Constant && 943 "Expecting a const value"); 944 945 SmallVector<SDValue,8> Operands; 946 Operands.push_back(Chain.getOperand(0)); 947 Operands.push_back(TargetAddress); 948 Operands.push_back(StackAdjustment); 949 // Copy registers used by the call. Last operand is a flag so it is not 950 // copied. 951 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 952 Operands.push_back(Chain.getOperand(i)); 953 } 954 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0], 955 Operands.size()); 956 } 957 958 // Regular return. 959 SDValue Flag; 960 961 SmallVector<SDValue, 6> RetOps; 962 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 963 // Operand #1 = Bytes To Pop 964 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 965 966 // Copy the result values into the output registers. 967 for (unsigned i = 0; i != RVLocs.size(); ++i) { 968 CCValAssign &VA = RVLocs[i]; 969 assert(VA.isRegLoc() && "Can only return in registers!"); 970 SDValue ValToCopy = Op.getOperand(i*2+1); 971 972 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 973 // the RET instruction and handled by the FP Stackifier. 974 if (RVLocs[i].getLocReg() == X86::ST0 || 975 RVLocs[i].getLocReg() == X86::ST1) { 976 // If this is a copy from an xmm register to ST(0), use an FPExtend to 977 // change the value to the FP stack register class. 978 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) 979 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy); 980 RetOps.push_back(ValToCopy); 981 // Don't emit a copytoreg. 982 continue; 983 } 984 985 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag); 986 Flag = Chain.getValue(1); 987 } 988 989 // The x86-64 ABI for returning structs by value requires that we copy 990 // the sret argument into %rax for the return. We saved the argument into 991 // a virtual register in the entry block, so now we copy the value out 992 // and into %rax. 993 if (Subtarget->is64Bit() && 994 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 995 MachineFunction &MF = DAG.getMachineFunction(); 996 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 997 unsigned Reg = FuncInfo->getSRetReturnReg(); 998 if (!Reg) { 999 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1000 FuncInfo->setSRetReturnReg(Reg); 1001 } 1002 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); 1003 1004 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag); 1005 Flag = Chain.getValue(1); 1006 } 1007 1008 RetOps[0] = Chain; // Update chain. 1009 1010 // Add the flag if we have it. 1011 if (Flag.getNode()) 1012 RetOps.push_back(Flag); 1013 1014 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size()); 1015} 1016 1017 1018/// LowerCallResult - Lower the result values of an ISD::CALL into the 1019/// appropriate copies out of appropriate physical registers. This assumes that 1020/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 1021/// being lowered. The returns a SDNode with the same number of values as the 1022/// ISD::CALL. 1023SDNode *X86TargetLowering:: 1024LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 1025 unsigned CallingConv, SelectionDAG &DAG) { 1026 1027 // Assign locations to each value returned by this call. 1028 SmallVector<CCValAssign, 16> RVLocs; 1029 bool isVarArg = TheCall->isVarArg(); 1030 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 1031 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); 1032 1033 SmallVector<SDValue, 8> ResultVals; 1034 1035 // Copy all of the result registers out of their specified physreg. 1036 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1037 MVT CopyVT = RVLocs[i].getValVT(); 1038 1039 // If this is a call to a function that returns an fp value on the floating 1040 // point stack, but where we prefer to use the value in xmm registers, copy 1041 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1042 if ((RVLocs[i].getLocReg() == X86::ST0 || 1043 RVLocs[i].getLocReg() == X86::ST1) && 1044 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 1045 CopyVT = MVT::f80; 1046 } 1047 1048 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 1049 CopyVT, InFlag).getValue(1); 1050 SDValue Val = Chain.getValue(0); 1051 InFlag = Chain.getValue(2); 1052 1053 if (CopyVT != RVLocs[i].getValVT()) { 1054 // Round the F80 the right size, which also moves to the appropriate xmm 1055 // register. 1056 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val, 1057 // This truncation won't change the value. 1058 DAG.getIntPtrConstant(1)); 1059 } 1060 1061 ResultVals.push_back(Val); 1062 } 1063 1064 // Merge everything together with a MERGE_VALUES node. 1065 ResultVals.push_back(Chain); 1066 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0], 1067 ResultVals.size()).getNode(); 1068} 1069 1070 1071//===----------------------------------------------------------------------===// 1072// C & StdCall & Fast Calling Convention implementation 1073//===----------------------------------------------------------------------===// 1074// StdCall calling convention seems to be standard for many Windows' API 1075// routines and around. It differs from C calling convention just a little: 1076// callee should clean up the stack, not caller. Symbols should be also 1077// decorated in some fancy way :) It doesn't support any vector arguments. 1078// For info on fast calling convention see Fast Calling Convention (tail call) 1079// implementation LowerX86_32FastCCCallTo. 1080 1081/// AddLiveIn - This helper function adds the specified physical register to the 1082/// MachineFunction as a live in value. It also creates a corresponding virtual 1083/// register for it. 1084static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 1085 const TargetRegisterClass *RC) { 1086 assert(RC->contains(PReg) && "Not the correct regclass!"); 1087 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1088 MF.getRegInfo().addLiveIn(PReg, VReg); 1089 return VReg; 1090} 1091 1092/// CallIsStructReturn - Determines whether a CALL node uses struct return 1093/// semantics. 1094static bool CallIsStructReturn(CallSDNode *TheCall) { 1095 unsigned NumOps = TheCall->getNumArgs(); 1096 if (!NumOps) 1097 return false; 1098 1099 return TheCall->getArgFlags(0).isSRet(); 1100} 1101 1102/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct 1103/// return semantics. 1104static bool ArgsAreStructReturn(SDValue Op) { 1105 unsigned NumArgs = Op.getNode()->getNumValues() - 1; 1106 if (!NumArgs) 1107 return false; 1108 1109 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); 1110} 1111 1112/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires 1113/// the callee to pop its own arguments. Callee pop is necessary to support tail 1114/// calls. 1115bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) { 1116 if (IsVarArg) 1117 return false; 1118 1119 switch (CallingConv) { 1120 default: 1121 return false; 1122 case CallingConv::X86_StdCall: 1123 return !Subtarget->is64Bit(); 1124 case CallingConv::X86_FastCall: 1125 return !Subtarget->is64Bit(); 1126 case CallingConv::Fast: 1127 return PerformTailCallOpt; 1128 } 1129} 1130 1131/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1132/// given CallingConvention value. 1133CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const { 1134 if (Subtarget->is64Bit()) { 1135 if (Subtarget->isTargetWin64()) 1136 return CC_X86_Win64_C; 1137 else if (CC == CallingConv::Fast && PerformTailCallOpt) 1138 return CC_X86_64_TailCall; 1139 else 1140 return CC_X86_64_C; 1141 } 1142 1143 if (CC == CallingConv::X86_FastCall) 1144 return CC_X86_32_FastCall; 1145 else if (CC == CallingConv::Fast) 1146 return CC_X86_32_FastCC; 1147 else 1148 return CC_X86_32_C; 1149} 1150 1151/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to 1152/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. 1153NameDecorationStyle 1154X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) { 1155 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 1156 if (CC == CallingConv::X86_FastCall) 1157 return FastCall; 1158 else if (CC == CallingConv::X86_StdCall) 1159 return StdCall; 1160 return None; 1161} 1162 1163 1164/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer 1165/// in a register before calling. 1166bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { 1167 return !IsTailCall && !Is64Bit && 1168 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1169 Subtarget->isPICStyleGOT(); 1170} 1171 1172/// CallRequiresFnAddressInReg - Check whether the call requires the function 1173/// address to be loaded in a register. 1174bool 1175X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { 1176 return !Is64Bit && IsTailCall && 1177 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1178 Subtarget->isPICStyleGOT(); 1179} 1180 1181/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1182/// by "Src" to address "Dst" with size and alignment information specified by 1183/// the specific parameter attribute. The copy will be passed as a byval 1184/// function parameter. 1185static SDValue 1186CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1187 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { 1188 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1189 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), 1190 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1191} 1192 1193SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG, 1194 const CCValAssign &VA, 1195 MachineFrameInfo *MFI, 1196 unsigned CC, 1197 SDValue Root, unsigned i) { 1198 // Create the nodes corresponding to a load from this parameter slot. 1199 ISD::ArgFlagsTy Flags = 1200 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); 1201 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; 1202 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1203 1204 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1205 // changed with more analysis. 1206 // In case of tail call optimization mark all arguments mutable. Since they 1207 // could be overwritten by lowering of arguments in case of a tail call. 1208 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1209 VA.getLocMemOffset(), isImmutable); 1210 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1211 if (Flags.isByVal()) 1212 return FIN; 1213 return DAG.getLoad(VA.getValVT(), Root, FIN, 1214 PseudoSourceValue::getFixedStack(FI), 0); 1215} 1216 1217SDValue 1218X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 1219 MachineFunction &MF = DAG.getMachineFunction(); 1220 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1221 1222 const Function* Fn = MF.getFunction(); 1223 if (Fn->hasExternalLinkage() && 1224 Subtarget->isTargetCygMing() && 1225 Fn->getName() == "main") 1226 FuncInfo->setForceFramePointer(true); 1227 1228 // Decorate the function name. 1229 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); 1230 1231 MachineFrameInfo *MFI = MF.getFrameInfo(); 1232 SDValue Root = Op.getOperand(0); 1233 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1234 unsigned CC = MF.getFunction()->getCallingConv(); 1235 bool Is64Bit = Subtarget->is64Bit(); 1236 bool IsWin64 = Subtarget->isTargetWin64(); 1237 1238 assert(!(isVarArg && CC == CallingConv::Fast) && 1239 "Var args not supported with calling convention fastcc"); 1240 1241 // Assign locations to all of the incoming arguments. 1242 SmallVector<CCValAssign, 16> ArgLocs; 1243 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1244 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC)); 1245 1246 SmallVector<SDValue, 8> ArgValues; 1247 unsigned LastVal = ~0U; 1248 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1249 CCValAssign &VA = ArgLocs[i]; 1250 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1251 // places. 1252 assert(VA.getValNo() != LastVal && 1253 "Don't support value assigned to multiple locs yet"); 1254 LastVal = VA.getValNo(); 1255 1256 if (VA.isRegLoc()) { 1257 MVT RegVT = VA.getLocVT(); 1258 TargetRegisterClass *RC; 1259 if (RegVT == MVT::i32) 1260 RC = X86::GR32RegisterClass; 1261 else if (Is64Bit && RegVT == MVT::i64) 1262 RC = X86::GR64RegisterClass; 1263 else if (RegVT == MVT::f32) 1264 RC = X86::FR32RegisterClass; 1265 else if (RegVT == MVT::f64) 1266 RC = X86::FR64RegisterClass; 1267 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1268 RC = X86::VR128RegisterClass; 1269 else if (RegVT.isVector()) { 1270 assert(RegVT.getSizeInBits() == 64); 1271 if (!Is64Bit) 1272 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. 1273 else { 1274 // Darwin calling convention passes MMX values in either GPRs or 1275 // XMMs in x86-64. Other targets pass them in memory. 1276 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { 1277 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. 1278 RegVT = MVT::v2i64; 1279 } else { 1280 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. 1281 RegVT = MVT::i64; 1282 } 1283 } 1284 } else { 1285 assert(0 && "Unknown argument type!"); 1286 } 1287 1288 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 1289 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 1290 1291 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1292 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1293 // right size. 1294 if (VA.getLocInfo() == CCValAssign::SExt) 1295 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 1296 DAG.getValueType(VA.getValVT())); 1297 else if (VA.getLocInfo() == CCValAssign::ZExt) 1298 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 1299 DAG.getValueType(VA.getValVT())); 1300 1301 if (VA.getLocInfo() != CCValAssign::Full) 1302 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 1303 1304 // Handle MMX values passed in GPRs. 1305 if (Is64Bit && RegVT != VA.getLocVT()) { 1306 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) 1307 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1308 else if (RC == X86::VR128RegisterClass) { 1309 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, 1310 DAG.getConstant(0, MVT::i64)); 1311 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1312 } 1313 } 1314 1315 ArgValues.push_back(ArgValue); 1316 } else { 1317 assert(VA.isMemLoc()); 1318 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); 1319 } 1320 } 1321 1322 // The x86-64 ABI for returning structs by value requires that we copy 1323 // the sret argument into %rax for the return. Save the argument into 1324 // a virtual register so that we can access it from the return points. 1325 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1326 MachineFunction &MF = DAG.getMachineFunction(); 1327 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1328 unsigned Reg = FuncInfo->getSRetReturnReg(); 1329 if (!Reg) { 1330 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1331 FuncInfo->setSRetReturnReg(Reg); 1332 } 1333 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); 1334 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); 1335 } 1336 1337 unsigned StackSize = CCInfo.getNextStackOffset(); 1338 // align stack specially for tail calls 1339 if (PerformTailCallOpt && CC == CallingConv::Fast) 1340 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1341 1342 // If the function takes variable number of arguments, make a frame index for 1343 // the start of the first vararg value... for expansion of llvm.va_start. 1344 if (isVarArg) { 1345 if (Is64Bit || CC != CallingConv::X86_FastCall) { 1346 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1347 } 1348 if (Is64Bit) { 1349 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1350 1351 // FIXME: We should really autogenerate these arrays 1352 static const unsigned GPR64ArgRegsWin64[] = { 1353 X86::RCX, X86::RDX, X86::R8, X86::R9 1354 }; 1355 static const unsigned XMMArgRegsWin64[] = { 1356 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1357 }; 1358 static const unsigned GPR64ArgRegs64Bit[] = { 1359 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1360 }; 1361 static const unsigned XMMArgRegs64Bit[] = { 1362 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1363 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1364 }; 1365 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1366 1367 if (IsWin64) { 1368 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1369 GPR64ArgRegs = GPR64ArgRegsWin64; 1370 XMMArgRegs = XMMArgRegsWin64; 1371 } else { 1372 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1373 GPR64ArgRegs = GPR64ArgRegs64Bit; 1374 XMMArgRegs = XMMArgRegs64Bit; 1375 } 1376 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1377 TotalNumIntRegs); 1378 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1379 TotalNumXMMRegs); 1380 1381 // For X86-64, if there are vararg parameters that are passed via 1382 // registers, then we must store them to their spots on the stack so they 1383 // may be loaded by deferencing the result of va_next. 1384 VarArgsGPOffset = NumIntRegs * 8; 1385 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1386 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1387 TotalNumXMMRegs * 16, 16); 1388 1389 // Store the integer parameter registers. 1390 SmallVector<SDValue, 8> MemOps; 1391 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1392 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1393 DAG.getIntPtrConstant(VarArgsGPOffset)); 1394 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1395 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1396 X86::GR64RegisterClass); 1397 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1398 SDValue Store = 1399 DAG.getStore(Val.getValue(1), Val, FIN, 1400 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1401 MemOps.push_back(Store); 1402 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1403 DAG.getIntPtrConstant(8)); 1404 } 1405 1406 // Now store the XMM (fp + vector) parameter registers. 1407 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1408 DAG.getIntPtrConstant(VarArgsFPOffset)); 1409 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1410 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1411 X86::VR128RegisterClass); 1412 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1413 SDValue Store = 1414 DAG.getStore(Val.getValue(1), Val, FIN, 1415 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1416 MemOps.push_back(Store); 1417 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1418 DAG.getIntPtrConstant(16)); 1419 } 1420 if (!MemOps.empty()) 1421 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1422 &MemOps[0], MemOps.size()); 1423 } 1424 } 1425 1426 ArgValues.push_back(Root); 1427 1428 // Some CCs need callee pop. 1429 if (IsCalleePop(isVarArg, CC)) { 1430 BytesToPopOnReturn = StackSize; // Callee pops everything. 1431 BytesCallerReserves = 0; 1432 } else { 1433 BytesToPopOnReturn = 0; // Callee pops nothing. 1434 // If this is an sret function, the return should pop the hidden pointer. 1435 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op)) 1436 BytesToPopOnReturn = 4; 1437 BytesCallerReserves = StackSize; 1438 } 1439 1440 if (!Is64Bit) { 1441 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1442 if (CC == CallingConv::X86_FastCall) 1443 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1444 } 1445 1446 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1447 1448 // Return the new list of results. 1449 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), 1450 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 1451} 1452 1453SDValue 1454X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 1455 const SDValue &StackPtr, 1456 const CCValAssign &VA, 1457 SDValue Chain, 1458 SDValue Arg, ISD::ArgFlagsTy Flags) { 1459 unsigned LocMemOffset = VA.getLocMemOffset(); 1460 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1461 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1462 if (Flags.isByVal()) { 1463 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); 1464 } 1465 return DAG.getStore(Chain, Arg, PtrOff, 1466 PseudoSourceValue::getStack(), LocMemOffset); 1467} 1468 1469/// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call 1470/// optimization is performed and it is required. 1471SDValue 1472X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1473 SDValue &OutRetAddr, 1474 SDValue Chain, 1475 bool IsTailCall, 1476 bool Is64Bit, 1477 int FPDiff) { 1478 if (!IsTailCall || FPDiff==0) return Chain; 1479 1480 // Adjust the Return address stack slot. 1481 MVT VT = getPointerTy(); 1482 OutRetAddr = getReturnAddressFrameIndex(DAG); 1483 // Load the "old" Return address. 1484 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0); 1485 return SDValue(OutRetAddr.getNode(), 1); 1486} 1487 1488/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1489/// optimization is performed and it is required (FPDiff!=0). 1490static SDValue 1491EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1492 SDValue Chain, SDValue RetAddrFrIdx, 1493 bool Is64Bit, int FPDiff) { 1494 // Store the return address to the appropriate stack slot. 1495 if (!FPDiff) return Chain; 1496 // Calculate the new stack slot for the return address. 1497 int SlotSize = Is64Bit ? 8 : 4; 1498 int NewReturnAddrFI = 1499 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1500 MVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1501 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1502 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, 1503 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1504 return Chain; 1505} 1506 1507SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 1508 MachineFunction &MF = DAG.getMachineFunction(); 1509 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 1510 SDValue Chain = TheCall->getChain(); 1511 unsigned CC = TheCall->getCallingConv(); 1512 bool isVarArg = TheCall->isVarArg(); 1513 bool IsTailCall = TheCall->isTailCall() && 1514 CC == CallingConv::Fast && PerformTailCallOpt; 1515 SDValue Callee = TheCall->getCallee(); 1516 bool Is64Bit = Subtarget->is64Bit(); 1517 bool IsStructRet = CallIsStructReturn(TheCall); 1518 1519 assert(!(isVarArg && CC == CallingConv::Fast) && 1520 "Var args not supported with calling convention fastcc"); 1521 1522 // Analyze operands of the call, assigning locations to each operand. 1523 SmallVector<CCValAssign, 16> ArgLocs; 1524 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1525 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC)); 1526 1527 // Get a count of how many bytes are to be pushed on the stack. 1528 unsigned NumBytes = CCInfo.getNextStackOffset(); 1529 if (PerformTailCallOpt && CC == CallingConv::Fast) 1530 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1531 1532 int FPDiff = 0; 1533 if (IsTailCall) { 1534 // Lower arguments at fp - stackoffset + fpdiff. 1535 unsigned NumBytesCallerPushed = 1536 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1537 FPDiff = NumBytesCallerPushed - NumBytes; 1538 1539 // Set the delta of movement of the returnaddr stackslot. 1540 // But only set if delta is greater than previous delta. 1541 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1542 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1543 } 1544 1545 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1546 1547 SDValue RetAddrFrIdx; 1548 // Load return adress for tail calls. 1549 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, 1550 FPDiff); 1551 1552 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1553 SmallVector<SDValue, 8> MemOpChains; 1554 SDValue StackPtr; 1555 1556 // Walk the register/memloc assignments, inserting copies/loads. In the case 1557 // of tail call optimization arguments are handle later. 1558 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1559 CCValAssign &VA = ArgLocs[i]; 1560 SDValue Arg = TheCall->getArg(i); 1561 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1562 bool isByVal = Flags.isByVal(); 1563 1564 // Promote the value if needed. 1565 switch (VA.getLocInfo()) { 1566 default: assert(0 && "Unknown loc info!"); 1567 case CCValAssign::Full: break; 1568 case CCValAssign::SExt: 1569 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 1570 break; 1571 case CCValAssign::ZExt: 1572 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 1573 break; 1574 case CCValAssign::AExt: 1575 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 1576 break; 1577 } 1578 1579 if (VA.isRegLoc()) { 1580 if (Is64Bit) { 1581 MVT RegVT = VA.getLocVT(); 1582 if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1583 switch (VA.getLocReg()) { 1584 default: 1585 break; 1586 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: 1587 case X86::R8: { 1588 // Special case: passing MMX values in GPR registers. 1589 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); 1590 break; 1591 } 1592 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: 1593 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { 1594 // Special case: passing MMX values in XMM registers. 1595 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); 1596 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg); 1597 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 1598 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg, 1599 getMOVLMask(2, DAG)); 1600 break; 1601 } 1602 } 1603 } 1604 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1605 } else { 1606 if (!IsTailCall || (IsTailCall && isByVal)) { 1607 assert(VA.isMemLoc()); 1608 if (StackPtr.getNode() == 0) 1609 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1610 1611 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, 1612 Chain, Arg, Flags)); 1613 } 1614 } 1615 } 1616 1617 if (!MemOpChains.empty()) 1618 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1619 &MemOpChains[0], MemOpChains.size()); 1620 1621 // Build a sequence of copy-to-reg nodes chained together with token chain 1622 // and flag operands which copy the outgoing args into registers. 1623 SDValue InFlag; 1624 // Tail call byval lowering might overwrite argument registers so in case of 1625 // tail call optimization the copies to registers are lowered later. 1626 if (!IsTailCall) 1627 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1628 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1629 InFlag); 1630 InFlag = Chain.getValue(1); 1631 } 1632 1633 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1634 // GOT pointer. 1635 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { 1636 Chain = DAG.getCopyToReg(Chain, X86::EBX, 1637 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 1638 InFlag); 1639 InFlag = Chain.getValue(1); 1640 } 1641 // If we are tail calling and generating PIC/GOT style code load the address 1642 // of the callee into ecx. The value in ecx is used as target of the tail 1643 // jump. This is done to circumvent the ebx/callee-saved problem for tail 1644 // calls on PIC/GOT architectures. Normally we would just put the address of 1645 // GOT into ebx and then call target@PLT. But for tail callss ebx would be 1646 // restored (since ebx is callee saved) before jumping to the target@PLT. 1647 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { 1648 // Note: The actual moving to ecx is done further down. 1649 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1650 if (G && !G->getGlobal()->hasHiddenVisibility() && 1651 !G->getGlobal()->hasProtectedVisibility()) 1652 Callee = LowerGlobalAddress(Callee, DAG); 1653 else if (isa<ExternalSymbolSDNode>(Callee)) 1654 Callee = LowerExternalSymbol(Callee,DAG); 1655 } 1656 1657 if (Is64Bit && isVarArg) { 1658 // From AMD64 ABI document: 1659 // For calls that may call functions that use varargs or stdargs 1660 // (prototype-less calls or calls to functions containing ellipsis (...) in 1661 // the declaration) %al is used as hidden argument to specify the number 1662 // of SSE registers used. The contents of %al do not need to match exactly 1663 // the number of registers, but must be an ubound on the number of SSE 1664 // registers used and is in the range 0 - 8 inclusive. 1665 1666 // FIXME: Verify this on Win64 1667 // Count the number of XMM registers allocated. 1668 static const unsigned XMMArgRegs[] = { 1669 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1670 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1671 }; 1672 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1673 1674 Chain = DAG.getCopyToReg(Chain, X86::AL, 1675 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1676 InFlag = Chain.getValue(1); 1677 } 1678 1679 1680 // For tail calls lower the arguments to the 'real' stack slot. 1681 if (IsTailCall) { 1682 SmallVector<SDValue, 8> MemOpChains2; 1683 SDValue FIN; 1684 int FI = 0; 1685 // Do not flag preceeding copytoreg stuff together with the following stuff. 1686 InFlag = SDValue(); 1687 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1688 CCValAssign &VA = ArgLocs[i]; 1689 if (!VA.isRegLoc()) { 1690 assert(VA.isMemLoc()); 1691 SDValue Arg = TheCall->getArg(i); 1692 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1693 // Create frame index. 1694 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1695 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1696 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1697 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1698 1699 if (Flags.isByVal()) { 1700 // Copy relative to framepointer. 1701 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1702 if (StackPtr.getNode() == 0) 1703 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1704 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source); 1705 1706 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, 1707 Flags, DAG)); 1708 } else { 1709 // Store relative to framepointer. 1710 MemOpChains2.push_back( 1711 DAG.getStore(Chain, Arg, FIN, 1712 PseudoSourceValue::getFixedStack(FI), 0)); 1713 } 1714 } 1715 } 1716 1717 if (!MemOpChains2.empty()) 1718 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1719 &MemOpChains2[0], MemOpChains2.size()); 1720 1721 // Copy arguments to their registers. 1722 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1723 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1724 InFlag); 1725 InFlag = Chain.getValue(1); 1726 } 1727 InFlag =SDValue(); 1728 1729 // Store the return address to the appropriate stack slot. 1730 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1731 FPDiff); 1732 } 1733 1734 // If the callee is a GlobalAddress node (quite common, every direct call is) 1735 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1736 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1737 // We should use extra load for direct calls to dllimported functions in 1738 // non-JIT mode. 1739 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1740 getTargetMachine(), true)) 1741 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(), 1742 G->getOffset()); 1743 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1744 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1745 } else if (IsTailCall) { 1746 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX; 1747 1748 Chain = DAG.getCopyToReg(Chain, 1749 DAG.getRegister(Opc, getPointerTy()), 1750 Callee,InFlag); 1751 Callee = DAG.getRegister(Opc, getPointerTy()); 1752 // Add register as live out. 1753 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); 1754 } 1755 1756 // Returns a chain & a flag for retval copy to use. 1757 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1758 SmallVector<SDValue, 8> Ops; 1759 1760 if (IsTailCall) { 1761 Ops.push_back(Chain); 1762 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true)); 1763 Ops.push_back(DAG.getIntPtrConstant(0, true)); 1764 if (InFlag.getNode()) 1765 Ops.push_back(InFlag); 1766 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1767 InFlag = Chain.getValue(1); 1768 1769 // Returns a chain & a flag for retval copy to use. 1770 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1771 Ops.clear(); 1772 } 1773 1774 Ops.push_back(Chain); 1775 Ops.push_back(Callee); 1776 1777 if (IsTailCall) 1778 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1779 1780 // Add argument registers to the end of the list so that they are known live 1781 // into the call. 1782 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1783 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1784 RegsToPass[i].second.getValueType())); 1785 1786 // Add an implicit use GOT pointer in EBX. 1787 if (!IsTailCall && !Is64Bit && 1788 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1789 Subtarget->isPICStyleGOT()) 1790 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1791 1792 // Add an implicit use of AL for x86 vararg functions. 1793 if (Is64Bit && isVarArg) 1794 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1795 1796 if (InFlag.getNode()) 1797 Ops.push_back(InFlag); 1798 1799 if (IsTailCall) { 1800 assert(InFlag.getNode() && 1801 "Flag must be set. Depend on flag being set in LowerRET"); 1802 Chain = DAG.getNode(X86ISD::TAILCALL, 1803 TheCall->getVTList(), &Ops[0], Ops.size()); 1804 1805 return SDValue(Chain.getNode(), Op.getResNo()); 1806 } 1807 1808 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); 1809 InFlag = Chain.getValue(1); 1810 1811 // Create the CALLSEQ_END node. 1812 unsigned NumBytesForCalleeToPush; 1813 if (IsCalleePop(isVarArg, CC)) 1814 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 1815 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet) 1816 // If this is is a call to a struct-return function, the callee 1817 // pops the hidden struct pointer, so we have to push it back. 1818 // This is common for Darwin/X86, Linux & Mingw32 targets. 1819 NumBytesForCalleeToPush = 4; 1820 else 1821 NumBytesForCalleeToPush = 0; // Callee pops nothing. 1822 1823 // Returns a flag for retval copy to use. 1824 Chain = DAG.getCALLSEQ_END(Chain, 1825 DAG.getIntPtrConstant(NumBytes, true), 1826 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 1827 true), 1828 InFlag); 1829 InFlag = Chain.getValue(1); 1830 1831 // Handle result values, copying them out of physregs into vregs that we 1832 // return. 1833 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 1834 Op.getResNo()); 1835} 1836 1837 1838//===----------------------------------------------------------------------===// 1839// Fast Calling Convention (tail call) implementation 1840//===----------------------------------------------------------------------===// 1841 1842// Like std call, callee cleans arguments, convention except that ECX is 1843// reserved for storing the tail called function address. Only 2 registers are 1844// free for argument passing (inreg). Tail call optimization is performed 1845// provided: 1846// * tailcallopt is enabled 1847// * caller/callee are fastcc 1848// On X86_64 architecture with GOT-style position independent code only local 1849// (within module) calls are supported at the moment. 1850// To keep the stack aligned according to platform abi the function 1851// GetAlignedArgumentStackSize ensures that argument delta is always multiples 1852// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 1853// If a tail called function callee has more arguments than the caller the 1854// caller needs to make sure that there is room to move the RETADDR to. This is 1855// achieved by reserving an area the size of the argument delta right after the 1856// original REtADDR, but before the saved framepointer or the spilled registers 1857// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 1858// stack layout: 1859// arg1 1860// arg2 1861// RETADDR 1862// [ new RETADDR 1863// move area ] 1864// (possible EBP) 1865// ESI 1866// EDI 1867// local1 .. 1868 1869/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 1870/// for a 16 byte align requirement. 1871unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 1872 SelectionDAG& DAG) { 1873 MachineFunction &MF = DAG.getMachineFunction(); 1874 const TargetMachine &TM = MF.getTarget(); 1875 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 1876 unsigned StackAlignment = TFI.getStackAlignment(); 1877 uint64_t AlignMask = StackAlignment - 1; 1878 int64_t Offset = StackSize; 1879 uint64_t SlotSize = TD->getPointerSize(); 1880 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 1881 // Number smaller than 12 so just add the difference. 1882 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 1883 } else { 1884 // Mask out lower bits, add stackalignment once plus the 12 bytes. 1885 Offset = ((~AlignMask) & Offset) + StackAlignment + 1886 (StackAlignment-SlotSize); 1887 } 1888 return Offset; 1889} 1890 1891/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1892/// following the call is a return. A function is eligible if caller/callee 1893/// calling conventions match, currently only fastcc supports tail calls, and 1894/// the function CALL is immediatly followed by a RET. 1895bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall, 1896 SDValue Ret, 1897 SelectionDAG& DAG) const { 1898 if (!PerformTailCallOpt) 1899 return false; 1900 1901 if (CheckTailCallReturnConstraints(TheCall, Ret)) { 1902 MachineFunction &MF = DAG.getMachineFunction(); 1903 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1904 unsigned CalleeCC= TheCall->getCallingConv(); 1905 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1906 SDValue Callee = TheCall->getCallee(); 1907 // On x86/32Bit PIC/GOT tail calls are supported. 1908 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || 1909 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) 1910 return true; 1911 1912 // Can only do local tail calls (in same module, hidden or protected) on 1913 // x86_64 PIC/GOT at the moment. 1914 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1915 return G->getGlobal()->hasHiddenVisibility() 1916 || G->getGlobal()->hasProtectedVisibility(); 1917 } 1918 } 1919 1920 return false; 1921} 1922 1923FastISel * 1924X86TargetLowering::createFastISel(MachineFunction &mf, 1925 MachineModuleInfo *mmo, 1926 DenseMap<const Value *, unsigned> &vm, 1927 DenseMap<const BasicBlock *, 1928 MachineBasicBlock *> &bm, 1929 DenseMap<const AllocaInst *, int> &am 1930#ifndef NDEBUG 1931 , SmallSet<Instruction*, 8> &cil 1932#endif 1933 ) { 1934 return X86::createFastISel(mf, mmo, vm, bm, am 1935#ifndef NDEBUG 1936 , cil 1937#endif 1938 ); 1939} 1940 1941 1942//===----------------------------------------------------------------------===// 1943// Other Lowering Hooks 1944//===----------------------------------------------------------------------===// 1945 1946 1947SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1948 MachineFunction &MF = DAG.getMachineFunction(); 1949 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1950 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1951 uint64_t SlotSize = TD->getPointerSize(); 1952 1953 if (ReturnAddrIndex == 0) { 1954 // Set up a frame object for the return address. 1955 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize); 1956 FuncInfo->setRAIndex(ReturnAddrIndex); 1957 } 1958 1959 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1960} 1961 1962 1963/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 1964/// specific condition code, returning the condition code and the LHS/RHS of the 1965/// comparison to make. 1966static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 1967 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 1968 if (!isFP) { 1969 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1970 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 1971 // X > -1 -> X == 0, jump !sign. 1972 RHS = DAG.getConstant(0, RHS.getValueType()); 1973 return X86::COND_NS; 1974 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 1975 // X < 0 -> X == 0, jump on sign. 1976 return X86::COND_S; 1977 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 1978 // X < 1 -> X <= 0 1979 RHS = DAG.getConstant(0, RHS.getValueType()); 1980 return X86::COND_LE; 1981 } 1982 } 1983 1984 switch (SetCCOpcode) { 1985 default: assert(0 && "Invalid integer condition!"); 1986 case ISD::SETEQ: return X86::COND_E; 1987 case ISD::SETGT: return X86::COND_G; 1988 case ISD::SETGE: return X86::COND_GE; 1989 case ISD::SETLT: return X86::COND_L; 1990 case ISD::SETLE: return X86::COND_LE; 1991 case ISD::SETNE: return X86::COND_NE; 1992 case ISD::SETULT: return X86::COND_B; 1993 case ISD::SETUGT: return X86::COND_A; 1994 case ISD::SETULE: return X86::COND_BE; 1995 case ISD::SETUGE: return X86::COND_AE; 1996 } 1997 } 1998 1999 // First determine if it is required or is profitable to flip the operands. 2000 2001 // If LHS is a foldable load, but RHS is not, flip the condition. 2002 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2003 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2004 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2005 std::swap(LHS, RHS); 2006 } 2007 2008 switch (SetCCOpcode) { 2009 default: break; 2010 case ISD::SETOLT: 2011 case ISD::SETOLE: 2012 case ISD::SETUGT: 2013 case ISD::SETUGE: 2014 std::swap(LHS, RHS); 2015 break; 2016 } 2017 2018 // On a floating point condition, the flags are set as follows: 2019 // ZF PF CF op 2020 // 0 | 0 | 0 | X > Y 2021 // 0 | 0 | 1 | X < Y 2022 // 1 | 0 | 0 | X == Y 2023 // 1 | 1 | 1 | unordered 2024 switch (SetCCOpcode) { 2025 default: assert(0 && "Condcode should be pre-legalized away"); 2026 case ISD::SETUEQ: 2027 case ISD::SETEQ: return X86::COND_E; 2028 case ISD::SETOLT: // flipped 2029 case ISD::SETOGT: 2030 case ISD::SETGT: return X86::COND_A; 2031 case ISD::SETOLE: // flipped 2032 case ISD::SETOGE: 2033 case ISD::SETGE: return X86::COND_AE; 2034 case ISD::SETUGT: // flipped 2035 case ISD::SETULT: 2036 case ISD::SETLT: return X86::COND_B; 2037 case ISD::SETUGE: // flipped 2038 case ISD::SETULE: 2039 case ISD::SETLE: return X86::COND_BE; 2040 case ISD::SETONE: 2041 case ISD::SETNE: return X86::COND_NE; 2042 case ISD::SETUO: return X86::COND_P; 2043 case ISD::SETO: return X86::COND_NP; 2044 } 2045} 2046 2047/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2048/// code. Current x86 isa includes the following FP cmov instructions: 2049/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2050static bool hasFPCMov(unsigned X86CC) { 2051 switch (X86CC) { 2052 default: 2053 return false; 2054 case X86::COND_B: 2055 case X86::COND_BE: 2056 case X86::COND_E: 2057 case X86::COND_P: 2058 case X86::COND_A: 2059 case X86::COND_AE: 2060 case X86::COND_NE: 2061 case X86::COND_NP: 2062 return true; 2063 } 2064} 2065 2066/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 2067/// true if Op is undef or if its value falls within the specified range (L, H]. 2068static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) { 2069 if (Op.getOpcode() == ISD::UNDEF) 2070 return true; 2071 2072 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue(); 2073 return (Val >= Low && Val < Hi); 2074} 2075 2076/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 2077/// true if Op is undef or if its value equal to the specified value. 2078static bool isUndefOrEqual(SDValue Op, unsigned Val) { 2079 if (Op.getOpcode() == ISD::UNDEF) 2080 return true; 2081 return cast<ConstantSDNode>(Op)->getZExtValue() == Val; 2082} 2083 2084/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 2085/// specifies a shuffle of elements that is suitable for input to PSHUFD. 2086bool X86::isPSHUFDMask(SDNode *N) { 2087 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2088 2089 if (N->getNumOperands() != 2 && N->getNumOperands() != 4) 2090 return false; 2091 2092 // Check if the value doesn't reference the second vector. 2093 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2094 SDValue Arg = N->getOperand(i); 2095 if (Arg.getOpcode() == ISD::UNDEF) continue; 2096 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2097 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e) 2098 return false; 2099 } 2100 2101 return true; 2102} 2103 2104/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 2105/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 2106bool X86::isPSHUFHWMask(SDNode *N) { 2107 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2108 2109 if (N->getNumOperands() != 8) 2110 return false; 2111 2112 // Lower quadword copied in order. 2113 for (unsigned i = 0; i != 4; ++i) { 2114 SDValue Arg = N->getOperand(i); 2115 if (Arg.getOpcode() == ISD::UNDEF) continue; 2116 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2117 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i) 2118 return false; 2119 } 2120 2121 // Upper quadword shuffled. 2122 for (unsigned i = 4; i != 8; ++i) { 2123 SDValue Arg = N->getOperand(i); 2124 if (Arg.getOpcode() == ISD::UNDEF) continue; 2125 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2126 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2127 if (Val < 4 || Val > 7) 2128 return false; 2129 } 2130 2131 return true; 2132} 2133 2134/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 2135/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 2136bool X86::isPSHUFLWMask(SDNode *N) { 2137 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2138 2139 if (N->getNumOperands() != 8) 2140 return false; 2141 2142 // Upper quadword copied in order. 2143 for (unsigned i = 4; i != 8; ++i) 2144 if (!isUndefOrEqual(N->getOperand(i), i)) 2145 return false; 2146 2147 // Lower quadword shuffled. 2148 for (unsigned i = 0; i != 4; ++i) 2149 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 2150 return false; 2151 2152 return true; 2153} 2154 2155/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2156/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2157static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) { 2158 if (NumElems != 2 && NumElems != 4) return false; 2159 2160 unsigned Half = NumElems / 2; 2161 for (unsigned i = 0; i < Half; ++i) 2162 if (!isUndefOrInRange(Elems[i], 0, NumElems)) 2163 return false; 2164 for (unsigned i = Half; i < NumElems; ++i) 2165 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) 2166 return false; 2167 2168 return true; 2169} 2170 2171bool X86::isSHUFPMask(SDNode *N) { 2172 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2173 return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); 2174} 2175 2176/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2177/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2178/// half elements to come from vector 1 (which would equal the dest.) and 2179/// the upper half to come from vector 2. 2180static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) { 2181 if (NumOps != 2 && NumOps != 4) return false; 2182 2183 unsigned Half = NumOps / 2; 2184 for (unsigned i = 0; i < Half; ++i) 2185 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) 2186 return false; 2187 for (unsigned i = Half; i < NumOps; ++i) 2188 if (!isUndefOrInRange(Ops[i], 0, NumOps)) 2189 return false; 2190 return true; 2191} 2192 2193static bool isCommutedSHUFP(SDNode *N) { 2194 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2195 return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); 2196} 2197 2198/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2199/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2200bool X86::isMOVHLPSMask(SDNode *N) { 2201 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2202 2203 if (N->getNumOperands() != 4) 2204 return false; 2205 2206 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2207 return isUndefOrEqual(N->getOperand(0), 6) && 2208 isUndefOrEqual(N->getOperand(1), 7) && 2209 isUndefOrEqual(N->getOperand(2), 2) && 2210 isUndefOrEqual(N->getOperand(3), 3); 2211} 2212 2213/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2214/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2215/// <2, 3, 2, 3> 2216bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 2217 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2218 2219 if (N->getNumOperands() != 4) 2220 return false; 2221 2222 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 2223 return isUndefOrEqual(N->getOperand(0), 2) && 2224 isUndefOrEqual(N->getOperand(1), 3) && 2225 isUndefOrEqual(N->getOperand(2), 2) && 2226 isUndefOrEqual(N->getOperand(3), 3); 2227} 2228 2229/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2230/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2231bool X86::isMOVLPMask(SDNode *N) { 2232 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2233 2234 unsigned NumElems = N->getNumOperands(); 2235 if (NumElems != 2 && NumElems != 4) 2236 return false; 2237 2238 for (unsigned i = 0; i < NumElems/2; ++i) 2239 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2240 return false; 2241 2242 for (unsigned i = NumElems/2; i < NumElems; ++i) 2243 if (!isUndefOrEqual(N->getOperand(i), i)) 2244 return false; 2245 2246 return true; 2247} 2248 2249/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2250/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2251/// and MOVLHPS. 2252bool X86::isMOVHPMask(SDNode *N) { 2253 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2254 2255 unsigned NumElems = N->getNumOperands(); 2256 if (NumElems != 2 && NumElems != 4) 2257 return false; 2258 2259 for (unsigned i = 0; i < NumElems/2; ++i) 2260 if (!isUndefOrEqual(N->getOperand(i), i)) 2261 return false; 2262 2263 for (unsigned i = 0; i < NumElems/2; ++i) { 2264 SDValue Arg = N->getOperand(i + NumElems/2); 2265 if (!isUndefOrEqual(Arg, i + NumElems)) 2266 return false; 2267 } 2268 2269 return true; 2270} 2271 2272/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2273/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2274bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts, 2275 bool V2IsSplat = false) { 2276 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2277 return false; 2278 2279 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2280 SDValue BitI = Elts[i]; 2281 SDValue BitI1 = Elts[i+1]; 2282 if (!isUndefOrEqual(BitI, j)) 2283 return false; 2284 if (V2IsSplat) { 2285 if (isUndefOrEqual(BitI1, NumElts)) 2286 return false; 2287 } else { 2288 if (!isUndefOrEqual(BitI1, j + NumElts)) 2289 return false; 2290 } 2291 } 2292 2293 return true; 2294} 2295 2296bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2297 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2298 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2299} 2300 2301/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2302/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2303bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts, 2304 bool V2IsSplat = false) { 2305 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2306 return false; 2307 2308 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2309 SDValue BitI = Elts[i]; 2310 SDValue BitI1 = Elts[i+1]; 2311 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2312 return false; 2313 if (V2IsSplat) { 2314 if (isUndefOrEqual(BitI1, NumElts)) 2315 return false; 2316 } else { 2317 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2318 return false; 2319 } 2320 } 2321 2322 return true; 2323} 2324 2325bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2326 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2327 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2328} 2329 2330/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2331/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2332/// <0, 0, 1, 1> 2333bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2334 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2335 2336 unsigned NumElems = N->getNumOperands(); 2337 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2338 return false; 2339 2340 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2341 SDValue BitI = N->getOperand(i); 2342 SDValue BitI1 = N->getOperand(i+1); 2343 2344 if (!isUndefOrEqual(BitI, j)) 2345 return false; 2346 if (!isUndefOrEqual(BitI1, j)) 2347 return false; 2348 } 2349 2350 return true; 2351} 2352 2353/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2354/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2355/// <2, 2, 3, 3> 2356bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { 2357 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2358 2359 unsigned NumElems = N->getNumOperands(); 2360 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2361 return false; 2362 2363 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2364 SDValue BitI = N->getOperand(i); 2365 SDValue BitI1 = N->getOperand(i + 1); 2366 2367 if (!isUndefOrEqual(BitI, j)) 2368 return false; 2369 if (!isUndefOrEqual(BitI1, j)) 2370 return false; 2371 } 2372 2373 return true; 2374} 2375 2376/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2377/// specifies a shuffle of elements that is suitable for input to MOVSS, 2378/// MOVSD, and MOVD, i.e. setting the lowest element. 2379static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) { 2380 if (NumElts != 2 && NumElts != 4) 2381 return false; 2382 2383 if (!isUndefOrEqual(Elts[0], NumElts)) 2384 return false; 2385 2386 for (unsigned i = 1; i < NumElts; ++i) { 2387 if (!isUndefOrEqual(Elts[i], i)) 2388 return false; 2389 } 2390 2391 return true; 2392} 2393 2394bool X86::isMOVLMask(SDNode *N) { 2395 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2396 return ::isMOVLMask(N->op_begin(), N->getNumOperands()); 2397} 2398 2399/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2400/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2401/// element of vector 2 and the other elements to come from vector 1 in order. 2402static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps, 2403 bool V2IsSplat = false, 2404 bool V2IsUndef = false) { 2405 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2406 return false; 2407 2408 if (!isUndefOrEqual(Ops[0], 0)) 2409 return false; 2410 2411 for (unsigned i = 1; i < NumOps; ++i) { 2412 SDValue Arg = Ops[i]; 2413 if (!(isUndefOrEqual(Arg, i+NumOps) || 2414 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || 2415 (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) 2416 return false; 2417 } 2418 2419 return true; 2420} 2421 2422static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2423 bool V2IsUndef = false) { 2424 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2425 return isCommutedMOVL(N->op_begin(), N->getNumOperands(), 2426 V2IsSplat, V2IsUndef); 2427} 2428 2429/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2430/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2431bool X86::isMOVSHDUPMask(SDNode *N) { 2432 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2433 2434 if (N->getNumOperands() != 4) 2435 return false; 2436 2437 // Expect 1, 1, 3, 3 2438 for (unsigned i = 0; i < 2; ++i) { 2439 SDValue Arg = N->getOperand(i); 2440 if (Arg.getOpcode() == ISD::UNDEF) continue; 2441 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2442 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2443 if (Val != 1) return false; 2444 } 2445 2446 bool HasHi = false; 2447 for (unsigned i = 2; i < 4; ++i) { 2448 SDValue Arg = N->getOperand(i); 2449 if (Arg.getOpcode() == ISD::UNDEF) continue; 2450 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2451 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2452 if (Val != 3) return false; 2453 HasHi = true; 2454 } 2455 2456 // Don't use movshdup if it can be done with a shufps. 2457 return HasHi; 2458} 2459 2460/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2461/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2462bool X86::isMOVSLDUPMask(SDNode *N) { 2463 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2464 2465 if (N->getNumOperands() != 4) 2466 return false; 2467 2468 // Expect 0, 0, 2, 2 2469 for (unsigned i = 0; i < 2; ++i) { 2470 SDValue Arg = N->getOperand(i); 2471 if (Arg.getOpcode() == ISD::UNDEF) continue; 2472 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2473 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2474 if (Val != 0) return false; 2475 } 2476 2477 bool HasHi = false; 2478 for (unsigned i = 2; i < 4; ++i) { 2479 SDValue Arg = N->getOperand(i); 2480 if (Arg.getOpcode() == ISD::UNDEF) continue; 2481 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2482 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2483 if (Val != 2) return false; 2484 HasHi = true; 2485 } 2486 2487 // Don't use movshdup if it can be done with a shufps. 2488 return HasHi; 2489} 2490 2491/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand 2492/// specifies a identity operation on the LHS or RHS. 2493static bool isIdentityMask(SDNode *N, bool RHS = false) { 2494 unsigned NumElems = N->getNumOperands(); 2495 for (unsigned i = 0; i < NumElems; ++i) 2496 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0))) 2497 return false; 2498 return true; 2499} 2500 2501/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2502/// a splat of a single element. 2503static bool isSplatMask(SDNode *N) { 2504 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2505 2506 // This is a splat operation if each element of the permute is the same, and 2507 // if the value doesn't reference the second vector. 2508 unsigned NumElems = N->getNumOperands(); 2509 SDValue ElementBase; 2510 unsigned i = 0; 2511 for (; i != NumElems; ++i) { 2512 SDValue Elt = N->getOperand(i); 2513 if (isa<ConstantSDNode>(Elt)) { 2514 ElementBase = Elt; 2515 break; 2516 } 2517 } 2518 2519 if (!ElementBase.getNode()) 2520 return false; 2521 2522 for (; i != NumElems; ++i) { 2523 SDValue Arg = N->getOperand(i); 2524 if (Arg.getOpcode() == ISD::UNDEF) continue; 2525 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2526 if (Arg != ElementBase) return false; 2527 } 2528 2529 // Make sure it is a splat of the first vector operand. 2530 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems; 2531} 2532 2533/// getSplatMaskEltNo - Given a splat mask, return the index to the element 2534/// we want to splat. 2535static SDValue getSplatMaskEltNo(SDNode *N) { 2536 assert(isSplatMask(N) && "Not a splat mask"); 2537 unsigned NumElems = N->getNumOperands(); 2538 SDValue ElementBase; 2539 unsigned i = 0; 2540 for (; i != NumElems; ++i) { 2541 SDValue Elt = N->getOperand(i); 2542 if (isa<ConstantSDNode>(Elt)) 2543 return Elt; 2544 } 2545 assert(0 && " No splat value found!"); 2546 return SDValue(); 2547} 2548 2549 2550/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2551/// a splat of a single element and it's a 2 or 4 element mask. 2552bool X86::isSplatMask(SDNode *N) { 2553 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2554 2555 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2556 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2557 return false; 2558 return ::isSplatMask(N); 2559} 2560 2561/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 2562/// specifies a splat of zero element. 2563bool X86::isSplatLoMask(SDNode *N) { 2564 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2565 2566 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 2567 if (!isUndefOrEqual(N->getOperand(i), 0)) 2568 return false; 2569 return true; 2570} 2571 2572/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2573/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2574bool X86::isMOVDDUPMask(SDNode *N) { 2575 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2576 2577 unsigned e = N->getNumOperands() / 2; 2578 for (unsigned i = 0; i < e; ++i) 2579 if (!isUndefOrEqual(N->getOperand(i), i)) 2580 return false; 2581 for (unsigned i = 0; i < e; ++i) 2582 if (!isUndefOrEqual(N->getOperand(e+i), i)) 2583 return false; 2584 return true; 2585} 2586 2587/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2588/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2589/// instructions. 2590unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2591 unsigned NumOperands = N->getNumOperands(); 2592 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2593 unsigned Mask = 0; 2594 for (unsigned i = 0; i < NumOperands; ++i) { 2595 unsigned Val = 0; 2596 SDValue Arg = N->getOperand(NumOperands-i-1); 2597 if (Arg.getOpcode() != ISD::UNDEF) 2598 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2599 if (Val >= NumOperands) Val -= NumOperands; 2600 Mask |= Val; 2601 if (i != NumOperands - 1) 2602 Mask <<= Shift; 2603 } 2604 2605 return Mask; 2606} 2607 2608/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2609/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2610/// instructions. 2611unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2612 unsigned Mask = 0; 2613 // 8 nodes, but we only care about the last 4. 2614 for (unsigned i = 7; i >= 4; --i) { 2615 unsigned Val = 0; 2616 SDValue Arg = N->getOperand(i); 2617 if (Arg.getOpcode() != ISD::UNDEF) 2618 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2619 Mask |= (Val - 4); 2620 if (i != 4) 2621 Mask <<= 2; 2622 } 2623 2624 return Mask; 2625} 2626 2627/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2628/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2629/// instructions. 2630unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2631 unsigned Mask = 0; 2632 // 8 nodes, but we only care about the first 4. 2633 for (int i = 3; i >= 0; --i) { 2634 unsigned Val = 0; 2635 SDValue Arg = N->getOperand(i); 2636 if (Arg.getOpcode() != ISD::UNDEF) 2637 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2638 Mask |= Val; 2639 if (i != 0) 2640 Mask <<= 2; 2641 } 2642 2643 return Mask; 2644} 2645 2646/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2647/// specifies a 8 element shuffle that can be broken into a pair of 2648/// PSHUFHW and PSHUFLW. 2649static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2650 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2651 2652 if (N->getNumOperands() != 8) 2653 return false; 2654 2655 // Lower quadword shuffled. 2656 for (unsigned i = 0; i != 4; ++i) { 2657 SDValue Arg = N->getOperand(i); 2658 if (Arg.getOpcode() == ISD::UNDEF) continue; 2659 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2660 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2661 if (Val >= 4) 2662 return false; 2663 } 2664 2665 // Upper quadword shuffled. 2666 for (unsigned i = 4; i != 8; ++i) { 2667 SDValue Arg = N->getOperand(i); 2668 if (Arg.getOpcode() == ISD::UNDEF) continue; 2669 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2670 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2671 if (Val < 4 || Val > 7) 2672 return false; 2673 } 2674 2675 return true; 2676} 2677 2678/// CommuteVectorShuffle - Swap vector_shuffle operands as well as 2679/// values in ther permute mask. 2680static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1, 2681 SDValue &V2, SDValue &Mask, 2682 SelectionDAG &DAG) { 2683 MVT VT = Op.getValueType(); 2684 MVT MaskVT = Mask.getValueType(); 2685 MVT EltVT = MaskVT.getVectorElementType(); 2686 unsigned NumElems = Mask.getNumOperands(); 2687 SmallVector<SDValue, 8> MaskVec; 2688 2689 for (unsigned i = 0; i != NumElems; ++i) { 2690 SDValue Arg = Mask.getOperand(i); 2691 if (Arg.getOpcode() == ISD::UNDEF) { 2692 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2693 continue; 2694 } 2695 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2696 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2697 if (Val < NumElems) 2698 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2699 else 2700 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2701 } 2702 2703 std::swap(V1, V2); 2704 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2705 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2706} 2707 2708/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2709/// the two vector operands have swapped position. 2710static 2711SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) { 2712 MVT MaskVT = Mask.getValueType(); 2713 MVT EltVT = MaskVT.getVectorElementType(); 2714 unsigned NumElems = Mask.getNumOperands(); 2715 SmallVector<SDValue, 8> MaskVec; 2716 for (unsigned i = 0; i != NumElems; ++i) { 2717 SDValue Arg = Mask.getOperand(i); 2718 if (Arg.getOpcode() == ISD::UNDEF) { 2719 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2720 continue; 2721 } 2722 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2723 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2724 if (Val < NumElems) 2725 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2726 else 2727 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2728 } 2729 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2730} 2731 2732 2733/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2734/// match movhlps. The lower half elements should come from upper half of 2735/// V1 (and in order), and the upper half elements should come from the upper 2736/// half of V2 (and in order). 2737static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2738 unsigned NumElems = Mask->getNumOperands(); 2739 if (NumElems != 4) 2740 return false; 2741 for (unsigned i = 0, e = 2; i != e; ++i) 2742 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2743 return false; 2744 for (unsigned i = 2; i != 4; ++i) 2745 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2746 return false; 2747 return true; 2748} 2749 2750/// isScalarLoadToVector - Returns true if the node is a scalar load that 2751/// is promoted to a vector. It also returns the LoadSDNode by reference if 2752/// required. 2753static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2754 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 2755 return false; 2756 N = N->getOperand(0).getNode(); 2757 if (!ISD::isNON_EXTLoad(N)) 2758 return false; 2759 if (LD) 2760 *LD = cast<LoadSDNode>(N); 2761 return true; 2762} 2763 2764/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2765/// match movlp{s|d}. The lower half elements should come from lower half of 2766/// V1 (and in order), and the upper half elements should come from the upper 2767/// half of V2 (and in order). And since V1 will become the source of the 2768/// MOVLP, it must be either a vector load or a scalar load to vector. 2769static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2770 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2771 return false; 2772 // Is V2 is a vector load, don't do this transformation. We will try to use 2773 // load folding shufps op. 2774 if (ISD::isNON_EXTLoad(V2)) 2775 return false; 2776 2777 unsigned NumElems = Mask->getNumOperands(); 2778 if (NumElems != 2 && NumElems != 4) 2779 return false; 2780 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2781 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2782 return false; 2783 for (unsigned i = NumElems/2; i != NumElems; ++i) 2784 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2785 return false; 2786 return true; 2787} 2788 2789/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2790/// all the same. 2791static bool isSplatVector(SDNode *N) { 2792 if (N->getOpcode() != ISD::BUILD_VECTOR) 2793 return false; 2794 2795 SDValue SplatValue = N->getOperand(0); 2796 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2797 if (N->getOperand(i) != SplatValue) 2798 return false; 2799 return true; 2800} 2801 2802/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2803/// to an undef. 2804static bool isUndefShuffle(SDNode *N) { 2805 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2806 return false; 2807 2808 SDValue V1 = N->getOperand(0); 2809 SDValue V2 = N->getOperand(1); 2810 SDValue Mask = N->getOperand(2); 2811 unsigned NumElems = Mask.getNumOperands(); 2812 for (unsigned i = 0; i != NumElems; ++i) { 2813 SDValue Arg = Mask.getOperand(i); 2814 if (Arg.getOpcode() != ISD::UNDEF) { 2815 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2816 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2817 return false; 2818 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2819 return false; 2820 } 2821 } 2822 return true; 2823} 2824 2825/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2826/// constant +0.0. 2827static inline bool isZeroNode(SDValue Elt) { 2828 return ((isa<ConstantSDNode>(Elt) && 2829 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 2830 (isa<ConstantFPSDNode>(Elt) && 2831 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2832} 2833 2834/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2835/// to an zero vector. 2836static bool isZeroShuffle(SDNode *N) { 2837 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2838 return false; 2839 2840 SDValue V1 = N->getOperand(0); 2841 SDValue V2 = N->getOperand(1); 2842 SDValue Mask = N->getOperand(2); 2843 unsigned NumElems = Mask.getNumOperands(); 2844 for (unsigned i = 0; i != NumElems; ++i) { 2845 SDValue Arg = Mask.getOperand(i); 2846 if (Arg.getOpcode() == ISD::UNDEF) 2847 continue; 2848 2849 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 2850 if (Idx < NumElems) { 2851 unsigned Opc = V1.getNode()->getOpcode(); 2852 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 2853 continue; 2854 if (Opc != ISD::BUILD_VECTOR || 2855 !isZeroNode(V1.getNode()->getOperand(Idx))) 2856 return false; 2857 } else if (Idx >= NumElems) { 2858 unsigned Opc = V2.getNode()->getOpcode(); 2859 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 2860 continue; 2861 if (Opc != ISD::BUILD_VECTOR || 2862 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems))) 2863 return false; 2864 } 2865 } 2866 return true; 2867} 2868 2869/// getZeroVector - Returns a vector of specified type with all zero elements. 2870/// 2871static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { 2872 assert(VT.isVector() && "Expected a vector type"); 2873 2874 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2875 // type. This ensures they get CSE'd. 2876 SDValue Vec; 2877 if (VT.getSizeInBits() == 64) { // MMX 2878 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2879 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2880 } else if (HasSSE2) { // SSE2 2881 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2882 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2883 } else { // SSE1 2884 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2885 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst); 2886 } 2887 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2888} 2889 2890/// getOnesVector - Returns a vector of specified type with all bits set. 2891/// 2892static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) { 2893 assert(VT.isVector() && "Expected a vector type"); 2894 2895 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2896 // type. This ensures they get CSE'd. 2897 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2898 SDValue Vec; 2899 if (VT.getSizeInBits() == 64) // MMX 2900 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2901 else // SSE 2902 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2903 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2904} 2905 2906 2907/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2908/// that point to V2 points to its first element. 2909static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) { 2910 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2911 2912 bool Changed = false; 2913 SmallVector<SDValue, 8> MaskVec; 2914 unsigned NumElems = Mask.getNumOperands(); 2915 for (unsigned i = 0; i != NumElems; ++i) { 2916 SDValue Arg = Mask.getOperand(i); 2917 if (Arg.getOpcode() != ISD::UNDEF) { 2918 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2919 if (Val > NumElems) { 2920 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2921 Changed = true; 2922 } 2923 } 2924 MaskVec.push_back(Arg); 2925 } 2926 2927 if (Changed) 2928 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 2929 &MaskVec[0], MaskVec.size()); 2930 return Mask; 2931} 2932 2933/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2934/// operation of specified width. 2935static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 2936 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2937 MVT BaseVT = MaskVT.getVectorElementType(); 2938 2939 SmallVector<SDValue, 8> MaskVec; 2940 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2941 for (unsigned i = 1; i != NumElems; ++i) 2942 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2943 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2944} 2945 2946/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2947/// of specified width. 2948static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 2949 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2950 MVT BaseVT = MaskVT.getVectorElementType(); 2951 SmallVector<SDValue, 8> MaskVec; 2952 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2953 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2954 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 2955 } 2956 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2957} 2958 2959/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 2960/// of specified width. 2961static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 2962 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2963 MVT BaseVT = MaskVT.getVectorElementType(); 2964 unsigned Half = NumElems/2; 2965 SmallVector<SDValue, 8> MaskVec; 2966 for (unsigned i = 0; i != Half; ++i) { 2967 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 2968 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 2969 } 2970 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2971} 2972 2973/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps 2974/// element #0 of a vector with the specified index, leaving the rest of the 2975/// elements in place. 2976static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, 2977 SelectionDAG &DAG) { 2978 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2979 MVT BaseVT = MaskVT.getVectorElementType(); 2980 SmallVector<SDValue, 8> MaskVec; 2981 // Element #0 of the result gets the elt we are replacing. 2982 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); 2983 for (unsigned i = 1; i != NumElems; ++i) 2984 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); 2985 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2986} 2987 2988/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 2989static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) { 2990 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; 2991 MVT VT = Op.getValueType(); 2992 if (PVT == VT) 2993 return Op; 2994 SDValue V1 = Op.getOperand(0); 2995 SDValue Mask = Op.getOperand(2); 2996 unsigned MaskNumElems = Mask.getNumOperands(); 2997 unsigned NumElems = MaskNumElems; 2998 // Special handling of v4f32 -> v4i32. 2999 if (VT != MVT::v4f32) { 3000 // Find which element we want to splat. 3001 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode(); 3002 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue(); 3003 // unpack elements to the correct location 3004 while (NumElems > 4) { 3005 if (EltNo < NumElems/2) { 3006 Mask = getUnpacklMask(MaskNumElems, DAG); 3007 } else { 3008 Mask = getUnpackhMask(MaskNumElems, DAG); 3009 EltNo -= NumElems/2; 3010 } 3011 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 3012 NumElems >>= 1; 3013 } 3014 SDValue Cst = DAG.getConstant(EltNo, MVT::i32); 3015 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 3016 } 3017 3018 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); 3019 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, 3020 DAG.getNode(ISD::UNDEF, PVT), Mask); 3021 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 3022} 3023 3024/// isVectorLoad - Returns true if the node is a vector load, a scalar 3025/// load that's promoted to vector, or a load bitcasted. 3026static bool isVectorLoad(SDValue Op) { 3027 assert(Op.getValueType().isVector() && "Expected a vector type"); 3028 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR || 3029 Op.getOpcode() == ISD::BIT_CONVERT) { 3030 return isa<LoadSDNode>(Op.getOperand(0)); 3031 } 3032 return isa<LoadSDNode>(Op); 3033} 3034 3035 3036/// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64. 3037/// 3038static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask, 3039 SelectionDAG &DAG, bool HasSSE3) { 3040 // If we have sse3 and shuffle has more than one use or input is a load, then 3041 // use movddup. Otherwise, use movlhps. 3042 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1)); 3043 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32; 3044 MVT VT = Op.getValueType(); 3045 if (VT == PVT) 3046 return Op; 3047 unsigned NumElems = PVT.getVectorNumElements(); 3048 if (NumElems == 2) { 3049 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3050 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 3051 } else { 3052 assert(NumElems == 4); 3053 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32); 3054 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32); 3055 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1); 3056 } 3057 3058 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); 3059 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, 3060 DAG.getNode(ISD::UNDEF, PVT), Mask); 3061 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 3062} 3063 3064/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3065/// vector of zero or undef vector. This produces a shuffle where the low 3066/// element of V2 is swizzled into the zero/undef vector, landing at element 3067/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3068static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3069 bool isZero, bool HasSSE2, 3070 SelectionDAG &DAG) { 3071 MVT VT = V2.getValueType(); 3072 SDValue V1 = isZero 3073 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT); 3074 unsigned NumElems = V2.getValueType().getVectorNumElements(); 3075 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3076 MVT EVT = MaskVT.getVectorElementType(); 3077 SmallVector<SDValue, 16> MaskVec; 3078 for (unsigned i = 0; i != NumElems; ++i) 3079 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. 3080 MaskVec.push_back(DAG.getConstant(NumElems, EVT)); 3081 else 3082 MaskVec.push_back(DAG.getConstant(i, EVT)); 3083 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3084 &MaskVec[0], MaskVec.size()); 3085 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 3086} 3087 3088/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3089/// a shuffle that is zero. 3090static 3091unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask, 3092 unsigned NumElems, bool Low, 3093 SelectionDAG &DAG) { 3094 unsigned NumZeros = 0; 3095 for (unsigned i = 0; i < NumElems; ++i) { 3096 unsigned Index = Low ? i : NumElems-i-1; 3097 SDValue Idx = Mask.getOperand(Index); 3098 if (Idx.getOpcode() == ISD::UNDEF) { 3099 ++NumZeros; 3100 continue; 3101 } 3102 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index); 3103 if (Elt.getNode() && isZeroNode(Elt)) 3104 ++NumZeros; 3105 else 3106 break; 3107 } 3108 return NumZeros; 3109} 3110 3111/// isVectorShift - Returns true if the shuffle can be implemented as a 3112/// logical left or right shift of a vector. 3113static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG, 3114 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3115 unsigned NumElems = Mask.getNumOperands(); 3116 3117 isLeft = true; 3118 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG); 3119 if (!NumZeros) { 3120 isLeft = false; 3121 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG); 3122 if (!NumZeros) 3123 return false; 3124 } 3125 3126 bool SeenV1 = false; 3127 bool SeenV2 = false; 3128 for (unsigned i = NumZeros; i < NumElems; ++i) { 3129 unsigned Val = isLeft ? (i - NumZeros) : i; 3130 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros)); 3131 if (Idx.getOpcode() == ISD::UNDEF) 3132 continue; 3133 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 3134 if (Index < NumElems) 3135 SeenV1 = true; 3136 else { 3137 Index -= NumElems; 3138 SeenV2 = true; 3139 } 3140 if (Index != Val) 3141 return false; 3142 } 3143 if (SeenV1 && SeenV2) 3144 return false; 3145 3146 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1); 3147 ShAmt = NumZeros; 3148 return true; 3149} 3150 3151 3152/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3153/// 3154static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3155 unsigned NumNonZero, unsigned NumZero, 3156 SelectionDAG &DAG, TargetLowering &TLI) { 3157 if (NumNonZero > 8) 3158 return SDValue(); 3159 3160 SDValue V(0, 0); 3161 bool First = true; 3162 for (unsigned i = 0; i < 16; ++i) { 3163 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3164 if (ThisIsNonZero && First) { 3165 if (NumZero) 3166 V = getZeroVector(MVT::v8i16, true, DAG); 3167 else 3168 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3169 First = false; 3170 } 3171 3172 if ((i & 1) != 0) { 3173 SDValue ThisElt(0, 0), LastElt(0, 0); 3174 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3175 if (LastIsNonZero) { 3176 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 3177 } 3178 if (ThisIsNonZero) { 3179 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 3180 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 3181 ThisElt, DAG.getConstant(8, MVT::i8)); 3182 if (LastIsNonZero) 3183 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 3184 } else 3185 ThisElt = LastElt; 3186 3187 if (ThisElt.getNode()) 3188 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 3189 DAG.getIntPtrConstant(i/2)); 3190 } 3191 } 3192 3193 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 3194} 3195 3196/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3197/// 3198static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3199 unsigned NumNonZero, unsigned NumZero, 3200 SelectionDAG &DAG, TargetLowering &TLI) { 3201 if (NumNonZero > 4) 3202 return SDValue(); 3203 3204 SDValue V(0, 0); 3205 bool First = true; 3206 for (unsigned i = 0; i < 8; ++i) { 3207 bool isNonZero = (NonZeros & (1 << i)) != 0; 3208 if (isNonZero) { 3209 if (First) { 3210 if (NumZero) 3211 V = getZeroVector(MVT::v8i16, true, DAG); 3212 else 3213 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3214 First = false; 3215 } 3216 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 3217 DAG.getIntPtrConstant(i)); 3218 } 3219 } 3220 3221 return V; 3222} 3223 3224/// getVShift - Return a vector logical shift node. 3225/// 3226static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, 3227 unsigned NumBits, SelectionDAG &DAG, 3228 const TargetLowering &TLI) { 3229 bool isMMX = VT.getSizeInBits() == 64; 3230 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3231 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3232 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp); 3233 return DAG.getNode(ISD::BIT_CONVERT, VT, 3234 DAG.getNode(Opc, ShVT, SrcOp, 3235 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3236} 3237 3238SDValue 3239X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3240 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3241 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3242 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3243 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3244 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3245 // eliminated on x86-32 hosts. 3246 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3247 return Op; 3248 3249 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3250 return getOnesVector(Op.getValueType(), DAG); 3251 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG); 3252 } 3253 3254 MVT VT = Op.getValueType(); 3255 MVT EVT = VT.getVectorElementType(); 3256 unsigned EVTBits = EVT.getSizeInBits(); 3257 3258 unsigned NumElems = Op.getNumOperands(); 3259 unsigned NumZero = 0; 3260 unsigned NumNonZero = 0; 3261 unsigned NonZeros = 0; 3262 bool IsAllConstants = true; 3263 SmallSet<SDValue, 8> Values; 3264 for (unsigned i = 0; i < NumElems; ++i) { 3265 SDValue Elt = Op.getOperand(i); 3266 if (Elt.getOpcode() == ISD::UNDEF) 3267 continue; 3268 Values.insert(Elt); 3269 if (Elt.getOpcode() != ISD::Constant && 3270 Elt.getOpcode() != ISD::ConstantFP) 3271 IsAllConstants = false; 3272 if (isZeroNode(Elt)) 3273 NumZero++; 3274 else { 3275 NonZeros |= (1 << i); 3276 NumNonZero++; 3277 } 3278 } 3279 3280 if (NumNonZero == 0) { 3281 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3282 return DAG.getNode(ISD::UNDEF, VT); 3283 } 3284 3285 // Special case for single non-zero, non-undef, element. 3286 if (NumNonZero == 1 && NumElems <= 4) { 3287 unsigned Idx = CountTrailingZeros_32(NonZeros); 3288 SDValue Item = Op.getOperand(Idx); 3289 3290 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3291 // the value are obviously zero, truncate the value to i32 and do the 3292 // insertion that way. Only do this if the value is non-constant or if the 3293 // value is a constant being inserted into element 0. It is cheaper to do 3294 // a constant pool load than it is to do a movd + shuffle. 3295 if (EVT == MVT::i64 && !Subtarget->is64Bit() && 3296 (!IsAllConstants || Idx == 0)) { 3297 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3298 // Handle MMX and SSE both. 3299 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3300 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3301 3302 // Truncate the value (which may itself be a constant) to i32, and 3303 // convert it to a vector with movd (S2V+shuffle to zero extend). 3304 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item); 3305 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item); 3306 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3307 Subtarget->hasSSE2(), DAG); 3308 3309 // Now we have our 32-bit value zero extended in the low element of 3310 // a vector. If Idx != 0, swizzle it into place. 3311 if (Idx != 0) { 3312 SDValue Ops[] = { 3313 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), 3314 getSwapEltZeroMask(VecElts, Idx, DAG) 3315 }; 3316 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3); 3317 } 3318 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item); 3319 } 3320 } 3321 3322 // If we have a constant or non-constant insertion into the low element of 3323 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3324 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3325 // depending on what the source datatype is. Because we can only get here 3326 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64. 3327 if (Idx == 0 && 3328 // Don't do this for i64 values on x86-32. 3329 (EVT != MVT::i64 || Subtarget->is64Bit())) { 3330 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3331 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3332 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3333 Subtarget->hasSSE2(), DAG); 3334 } 3335 3336 // Is it a vector logical left shift? 3337 if (NumElems == 2 && Idx == 1 && 3338 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) { 3339 unsigned NumBits = VT.getSizeInBits(); 3340 return getVShift(true, VT, 3341 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)), 3342 NumBits/2, DAG, *this); 3343 } 3344 3345 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3346 return SDValue(); 3347 3348 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3349 // is a non-constant being inserted into an element other than the low one, 3350 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3351 // movd/movss) to move this into the low element, then shuffle it into 3352 // place. 3353 if (EVTBits == 32) { 3354 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3355 3356 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3357 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3358 Subtarget->hasSSE2(), DAG); 3359 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3360 MVT MaskEVT = MaskVT.getVectorElementType(); 3361 SmallVector<SDValue, 8> MaskVec; 3362 for (unsigned i = 0; i < NumElems; i++) 3363 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 3364 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3365 &MaskVec[0], MaskVec.size()); 3366 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 3367 DAG.getNode(ISD::UNDEF, VT), Mask); 3368 } 3369 } 3370 3371 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3372 if (Values.size() == 1) 3373 return SDValue(); 3374 3375 // A vector full of immediates; various special cases are already 3376 // handled, so this is best done with a single constant-pool load. 3377 if (IsAllConstants) 3378 return SDValue(); 3379 3380 // Let legalizer expand 2-wide build_vectors. 3381 if (EVTBits == 64) { 3382 if (NumNonZero == 1) { 3383 // One half is zero or undef. 3384 unsigned Idx = CountTrailingZeros_32(NonZeros); 3385 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, 3386 Op.getOperand(Idx)); 3387 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3388 Subtarget->hasSSE2(), DAG); 3389 } 3390 return SDValue(); 3391 } 3392 3393 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3394 if (EVTBits == 8 && NumElems == 16) { 3395 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3396 *this); 3397 if (V.getNode()) return V; 3398 } 3399 3400 if (EVTBits == 16 && NumElems == 8) { 3401 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3402 *this); 3403 if (V.getNode()) return V; 3404 } 3405 3406 // If element VT is == 32 bits, turn it into a number of shuffles. 3407 SmallVector<SDValue, 8> V; 3408 V.resize(NumElems); 3409 if (NumElems == 4 && NumZero > 0) { 3410 for (unsigned i = 0; i < 4; ++i) { 3411 bool isZero = !(NonZeros & (1 << i)); 3412 if (isZero) 3413 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG); 3414 else 3415 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3416 } 3417 3418 for (unsigned i = 0; i < 2; ++i) { 3419 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3420 default: break; 3421 case 0: 3422 V[i] = V[i*2]; // Must be a zero vector. 3423 break; 3424 case 1: 3425 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 3426 getMOVLMask(NumElems, DAG)); 3427 break; 3428 case 2: 3429 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3430 getMOVLMask(NumElems, DAG)); 3431 break; 3432 case 3: 3433 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3434 getUnpacklMask(NumElems, DAG)); 3435 break; 3436 } 3437 } 3438 3439 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3440 MVT EVT = MaskVT.getVectorElementType(); 3441 SmallVector<SDValue, 8> MaskVec; 3442 bool Reverse = (NonZeros & 0x3) == 2; 3443 for (unsigned i = 0; i < 2; ++i) 3444 if (Reverse) 3445 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3446 else 3447 MaskVec.push_back(DAG.getConstant(i, EVT)); 3448 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3449 for (unsigned i = 0; i < 2; ++i) 3450 if (Reverse) 3451 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3452 else 3453 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3454 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3455 &MaskVec[0], MaskVec.size()); 3456 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 3457 } 3458 3459 if (Values.size() > 2) { 3460 // Expand into a number of unpckl*. 3461 // e.g. for v4f32 3462 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3463 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3464 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3465 SDValue UnpckMask = getUnpacklMask(NumElems, DAG); 3466 for (unsigned i = 0; i < NumElems; ++i) 3467 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3468 NumElems >>= 1; 3469 while (NumElems != 0) { 3470 for (unsigned i = 0; i < NumElems; ++i) 3471 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 3472 UnpckMask); 3473 NumElems >>= 1; 3474 } 3475 return V[0]; 3476 } 3477 3478 return SDValue(); 3479} 3480 3481static 3482SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, 3483 SDValue PermMask, SelectionDAG &DAG, 3484 TargetLowering &TLI) { 3485 SDValue NewV; 3486 MVT MaskVT = MVT::getIntVectorWithNumElements(8); 3487 MVT MaskEVT = MaskVT.getVectorElementType(); 3488 MVT PtrVT = TLI.getPointerTy(); 3489 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(), 3490 PermMask.getNode()->op_end()); 3491 3492 // First record which half of which vector the low elements come from. 3493 SmallVector<unsigned, 4> LowQuad(4); 3494 for (unsigned i = 0; i < 4; ++i) { 3495 SDValue Elt = MaskElts[i]; 3496 if (Elt.getOpcode() == ISD::UNDEF) 3497 continue; 3498 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3499 int QuadIdx = EltIdx / 4; 3500 ++LowQuad[QuadIdx]; 3501 } 3502 3503 int BestLowQuad = -1; 3504 unsigned MaxQuad = 1; 3505 for (unsigned i = 0; i < 4; ++i) { 3506 if (LowQuad[i] > MaxQuad) { 3507 BestLowQuad = i; 3508 MaxQuad = LowQuad[i]; 3509 } 3510 } 3511 3512 // Record which half of which vector the high elements come from. 3513 SmallVector<unsigned, 4> HighQuad(4); 3514 for (unsigned i = 4; i < 8; ++i) { 3515 SDValue Elt = MaskElts[i]; 3516 if (Elt.getOpcode() == ISD::UNDEF) 3517 continue; 3518 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3519 int QuadIdx = EltIdx / 4; 3520 ++HighQuad[QuadIdx]; 3521 } 3522 3523 int BestHighQuad = -1; 3524 MaxQuad = 1; 3525 for (unsigned i = 0; i < 4; ++i) { 3526 if (HighQuad[i] > MaxQuad) { 3527 BestHighQuad = i; 3528 MaxQuad = HighQuad[i]; 3529 } 3530 } 3531 3532 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it. 3533 if (BestLowQuad != -1 || BestHighQuad != -1) { 3534 // First sort the 4 chunks in order using shufpd. 3535 SmallVector<SDValue, 8> MaskVec; 3536 3537 if (BestLowQuad != -1) 3538 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32)); 3539 else 3540 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 3541 3542 if (BestHighQuad != -1) 3543 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32)); 3544 else 3545 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 3546 3547 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); 3548 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 3549 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), 3550 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); 3551 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV); 3552 3553 // Now sort high and low parts separately. 3554 BitVector InOrder(8); 3555 if (BestLowQuad != -1) { 3556 // Sort lower half in order using PSHUFLW. 3557 MaskVec.clear(); 3558 bool AnyOutOrder = false; 3559 3560 for (unsigned i = 0; i != 4; ++i) { 3561 SDValue Elt = MaskElts[i]; 3562 if (Elt.getOpcode() == ISD::UNDEF) { 3563 MaskVec.push_back(Elt); 3564 InOrder.set(i); 3565 } else { 3566 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3567 if (EltIdx != i) 3568 AnyOutOrder = true; 3569 3570 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT)); 3571 3572 // If this element is in the right place after this shuffle, then 3573 // remember it. 3574 if ((int)(EltIdx / 4) == BestLowQuad) 3575 InOrder.set(i); 3576 } 3577 } 3578 if (AnyOutOrder) { 3579 for (unsigned i = 4; i != 8; ++i) 3580 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3581 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3582 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3583 } 3584 } 3585 3586 if (BestHighQuad != -1) { 3587 // Sort high half in order using PSHUFHW if possible. 3588 MaskVec.clear(); 3589 3590 for (unsigned i = 0; i != 4; ++i) 3591 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3592 3593 bool AnyOutOrder = false; 3594 for (unsigned i = 4; i != 8; ++i) { 3595 SDValue Elt = MaskElts[i]; 3596 if (Elt.getOpcode() == ISD::UNDEF) { 3597 MaskVec.push_back(Elt); 3598 InOrder.set(i); 3599 } else { 3600 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3601 if (EltIdx != i) 3602 AnyOutOrder = true; 3603 3604 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT)); 3605 3606 // If this element is in the right place after this shuffle, then 3607 // remember it. 3608 if ((int)(EltIdx / 4) == BestHighQuad) 3609 InOrder.set(i); 3610 } 3611 } 3612 3613 if (AnyOutOrder) { 3614 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3615 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3616 } 3617 } 3618 3619 // The other elements are put in the right place using pextrw and pinsrw. 3620 for (unsigned i = 0; i != 8; ++i) { 3621 if (InOrder[i]) 3622 continue; 3623 SDValue Elt = MaskElts[i]; 3624 if (Elt.getOpcode() == ISD::UNDEF) 3625 continue; 3626 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3627 SDValue ExtOp = (EltIdx < 8) 3628 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3629 DAG.getConstant(EltIdx, PtrVT)) 3630 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3631 DAG.getConstant(EltIdx - 8, PtrVT)); 3632 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3633 DAG.getConstant(i, PtrVT)); 3634 } 3635 3636 return NewV; 3637 } 3638 3639 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as 3640 // few as possible. First, let's find out how many elements are already in the 3641 // right order. 3642 unsigned V1InOrder = 0; 3643 unsigned V1FromV1 = 0; 3644 unsigned V2InOrder = 0; 3645 unsigned V2FromV2 = 0; 3646 SmallVector<SDValue, 8> V1Elts; 3647 SmallVector<SDValue, 8> V2Elts; 3648 for (unsigned i = 0; i < 8; ++i) { 3649 SDValue Elt = MaskElts[i]; 3650 if (Elt.getOpcode() == ISD::UNDEF) { 3651 V1Elts.push_back(Elt); 3652 V2Elts.push_back(Elt); 3653 ++V1InOrder; 3654 ++V2InOrder; 3655 continue; 3656 } 3657 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3658 if (EltIdx == i) { 3659 V1Elts.push_back(Elt); 3660 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT)); 3661 ++V1InOrder; 3662 } else if (EltIdx == i+8) { 3663 V1Elts.push_back(Elt); 3664 V2Elts.push_back(DAG.getConstant(i, MaskEVT)); 3665 ++V2InOrder; 3666 } else if (EltIdx < 8) { 3667 V1Elts.push_back(Elt); 3668 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT)); 3669 ++V1FromV1; 3670 } else { 3671 V1Elts.push_back(Elt); 3672 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT)); 3673 ++V2FromV2; 3674 } 3675 } 3676 3677 if (V2InOrder > V1InOrder) { 3678 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3679 std::swap(V1, V2); 3680 std::swap(V1Elts, V2Elts); 3681 std::swap(V1FromV1, V2FromV2); 3682 } 3683 3684 if ((V1FromV1 + V1InOrder) != 8) { 3685 // Some elements are from V2. 3686 if (V1FromV1) { 3687 // If there are elements that are from V1 but out of place, 3688 // then first sort them in place 3689 SmallVector<SDValue, 8> MaskVec; 3690 for (unsigned i = 0; i < 8; ++i) { 3691 SDValue Elt = V1Elts[i]; 3692 if (Elt.getOpcode() == ISD::UNDEF) { 3693 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3694 continue; 3695 } 3696 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3697 if (EltIdx >= 8) 3698 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3699 else 3700 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); 3701 } 3702 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3703 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); 3704 } 3705 3706 NewV = V1; 3707 for (unsigned i = 0; i < 8; ++i) { 3708 SDValue Elt = V1Elts[i]; 3709 if (Elt.getOpcode() == ISD::UNDEF) 3710 continue; 3711 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3712 if (EltIdx < 8) 3713 continue; 3714 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3715 DAG.getConstant(EltIdx - 8, PtrVT)); 3716 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3717 DAG.getConstant(i, PtrVT)); 3718 } 3719 return NewV; 3720 } else { 3721 // All elements are from V1. 3722 NewV = V1; 3723 for (unsigned i = 0; i < 8; ++i) { 3724 SDValue Elt = V1Elts[i]; 3725 if (Elt.getOpcode() == ISD::UNDEF) 3726 continue; 3727 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3728 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3729 DAG.getConstant(EltIdx, PtrVT)); 3730 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3731 DAG.getConstant(i, PtrVT)); 3732 } 3733 return NewV; 3734 } 3735} 3736 3737/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3738/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3739/// done when every pair / quad of shuffle mask elements point to elements in 3740/// the right sequence. e.g. 3741/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3742static 3743SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2, 3744 MVT VT, 3745 SDValue PermMask, SelectionDAG &DAG, 3746 TargetLowering &TLI) { 3747 unsigned NumElems = PermMask.getNumOperands(); 3748 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3749 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3750 MVT MaskEltVT = MaskVT.getVectorElementType(); 3751 MVT NewVT = MaskVT; 3752 switch (VT.getSimpleVT()) { 3753 default: assert(false && "Unexpected!"); 3754 case MVT::v4f32: NewVT = MVT::v2f64; break; 3755 case MVT::v4i32: NewVT = MVT::v2i64; break; 3756 case MVT::v8i16: NewVT = MVT::v4i32; break; 3757 case MVT::v16i8: NewVT = MVT::v4i32; break; 3758 } 3759 3760 if (NewWidth == 2) { 3761 if (VT.isInteger()) 3762 NewVT = MVT::v2i64; 3763 else 3764 NewVT = MVT::v2f64; 3765 } 3766 unsigned Scale = NumElems / NewWidth; 3767 SmallVector<SDValue, 8> MaskVec; 3768 for (unsigned i = 0; i < NumElems; i += Scale) { 3769 unsigned StartIdx = ~0U; 3770 for (unsigned j = 0; j < Scale; ++j) { 3771 SDValue Elt = PermMask.getOperand(i+j); 3772 if (Elt.getOpcode() == ISD::UNDEF) 3773 continue; 3774 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3775 if (StartIdx == ~0U) 3776 StartIdx = EltIdx - (EltIdx % Scale); 3777 if (EltIdx != StartIdx + j) 3778 return SDValue(); 3779 } 3780 if (StartIdx == ~0U) 3781 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT)); 3782 else 3783 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT)); 3784 } 3785 3786 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1); 3787 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2); 3788 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2, 3789 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3790 &MaskVec[0], MaskVec.size())); 3791} 3792 3793/// getVZextMovL - Return a zero-extending vector move low node. 3794/// 3795static SDValue getVZextMovL(MVT VT, MVT OpVT, 3796 SDValue SrcOp, SelectionDAG &DAG, 3797 const X86Subtarget *Subtarget) { 3798 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3799 LoadSDNode *LD = NULL; 3800 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 3801 LD = dyn_cast<LoadSDNode>(SrcOp); 3802 if (!LD) { 3803 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3804 // instead. 3805 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3806 if ((EVT != MVT::i64 || Subtarget->is64Bit()) && 3807 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 3808 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 3809 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { 3810 // PR2108 3811 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 3812 return DAG.getNode(ISD::BIT_CONVERT, VT, 3813 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, 3814 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT, 3815 SrcOp.getOperand(0) 3816 .getOperand(0)))); 3817 } 3818 } 3819 } 3820 3821 return DAG.getNode(ISD::BIT_CONVERT, VT, 3822 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, 3823 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp))); 3824} 3825 3826/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 3827/// shuffles. 3828static SDValue 3829LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2, 3830 SDValue PermMask, MVT VT, SelectionDAG &DAG) { 3831 MVT MaskVT = PermMask.getValueType(); 3832 MVT MaskEVT = MaskVT.getVectorElementType(); 3833 SmallVector<std::pair<int, int>, 8> Locs; 3834 Locs.resize(4); 3835 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3836 unsigned NumHi = 0; 3837 unsigned NumLo = 0; 3838 for (unsigned i = 0; i != 4; ++i) { 3839 SDValue Elt = PermMask.getOperand(i); 3840 if (Elt.getOpcode() == ISD::UNDEF) { 3841 Locs[i] = std::make_pair(-1, -1); 3842 } else { 3843 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue(); 3844 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!"); 3845 if (Val < 4) { 3846 Locs[i] = std::make_pair(0, NumLo); 3847 Mask1[NumLo] = Elt; 3848 NumLo++; 3849 } else { 3850 Locs[i] = std::make_pair(1, NumHi); 3851 if (2+NumHi < 4) 3852 Mask1[2+NumHi] = Elt; 3853 NumHi++; 3854 } 3855 } 3856 } 3857 3858 if (NumLo <= 2 && NumHi <= 2) { 3859 // If no more than two elements come from either vector. This can be 3860 // implemented with two shuffles. First shuffle gather the elements. 3861 // The second shuffle, which takes the first shuffle as both of its 3862 // vector operands, put the elements into the right order. 3863 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3864 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3865 &Mask1[0], Mask1.size())); 3866 3867 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3868 for (unsigned i = 0; i != 4; ++i) { 3869 if (Locs[i].first == -1) 3870 continue; 3871 else { 3872 unsigned Idx = (i < 2) ? 0 : 4; 3873 Idx += Locs[i].first * 2 + Locs[i].second; 3874 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 3875 } 3876 } 3877 3878 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 3879 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3880 &Mask2[0], Mask2.size())); 3881 } else if (NumLo == 3 || NumHi == 3) { 3882 // Otherwise, we must have three elements from one vector, call it X, and 3883 // one element from the other, call it Y. First, use a shufps to build an 3884 // intermediate vector with the one element from Y and the element from X 3885 // that will be in the same half in the final destination (the indexes don't 3886 // matter). Then, use a shufps to build the final vector, taking the half 3887 // containing the element from Y from the intermediate, and the other half 3888 // from X. 3889 if (NumHi == 3) { 3890 // Normalize it so the 3 elements come from V1. 3891 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3892 std::swap(V1, V2); 3893 } 3894 3895 // Find the element from V2. 3896 unsigned HiIndex; 3897 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 3898 SDValue Elt = PermMask.getOperand(HiIndex); 3899 if (Elt.getOpcode() == ISD::UNDEF) 3900 continue; 3901 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue(); 3902 if (Val >= 4) 3903 break; 3904 } 3905 3906 Mask1[0] = PermMask.getOperand(HiIndex); 3907 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT); 3908 Mask1[2] = PermMask.getOperand(HiIndex^1); 3909 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT); 3910 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3911 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3912 3913 if (HiIndex >= 2) { 3914 Mask1[0] = PermMask.getOperand(0); 3915 Mask1[1] = PermMask.getOperand(1); 3916 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT); 3917 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT); 3918 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3919 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3920 } else { 3921 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT); 3922 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT); 3923 Mask1[2] = PermMask.getOperand(2); 3924 Mask1[3] = PermMask.getOperand(3); 3925 if (Mask1[2].getOpcode() != ISD::UNDEF) 3926 Mask1[2] = 3927 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4, 3928 MaskEVT); 3929 if (Mask1[3].getOpcode() != ISD::UNDEF) 3930 Mask1[3] = 3931 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4, 3932 MaskEVT); 3933 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, 3934 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3935 } 3936 } 3937 3938 // Break it into (shuffle shuffle_hi, shuffle_lo). 3939 Locs.clear(); 3940 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3941 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3942 SmallVector<SDValue,8> *MaskPtr = &LoMask; 3943 unsigned MaskIdx = 0; 3944 unsigned LoIdx = 0; 3945 unsigned HiIdx = 2; 3946 for (unsigned i = 0; i != 4; ++i) { 3947 if (i == 2) { 3948 MaskPtr = &HiMask; 3949 MaskIdx = 1; 3950 LoIdx = 0; 3951 HiIdx = 2; 3952 } 3953 SDValue Elt = PermMask.getOperand(i); 3954 if (Elt.getOpcode() == ISD::UNDEF) { 3955 Locs[i] = std::make_pair(-1, -1); 3956 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) { 3957 Locs[i] = std::make_pair(MaskIdx, LoIdx); 3958 (*MaskPtr)[LoIdx] = Elt; 3959 LoIdx++; 3960 } else { 3961 Locs[i] = std::make_pair(MaskIdx, HiIdx); 3962 (*MaskPtr)[HiIdx] = Elt; 3963 HiIdx++; 3964 } 3965 } 3966 3967 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3968 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3969 &LoMask[0], LoMask.size())); 3970 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3971 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3972 &HiMask[0], HiMask.size())); 3973 SmallVector<SDValue, 8> MaskOps; 3974 for (unsigned i = 0; i != 4; ++i) { 3975 if (Locs[i].first == -1) { 3976 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3977 } else { 3978 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 3979 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 3980 } 3981 } 3982 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 3983 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3984 &MaskOps[0], MaskOps.size())); 3985} 3986 3987SDValue 3988X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 3989 SDValue V1 = Op.getOperand(0); 3990 SDValue V2 = Op.getOperand(1); 3991 SDValue PermMask = Op.getOperand(2); 3992 MVT VT = Op.getValueType(); 3993 unsigned NumElems = PermMask.getNumOperands(); 3994 bool isMMX = VT.getSizeInBits() == 64; 3995 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 3996 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 3997 bool V1IsSplat = false; 3998 bool V2IsSplat = false; 3999 4000 if (isUndefShuffle(Op.getNode())) 4001 return DAG.getNode(ISD::UNDEF, VT); 4002 4003 if (isZeroShuffle(Op.getNode())) 4004 return getZeroVector(VT, Subtarget->hasSSE2(), DAG); 4005 4006 if (isIdentityMask(PermMask.getNode())) 4007 return V1; 4008 else if (isIdentityMask(PermMask.getNode(), true)) 4009 return V2; 4010 4011 // Canonicalize movddup shuffles. 4012 if (V2IsUndef && Subtarget->hasSSE2() && 4013 VT.getSizeInBits() == 128 && 4014 X86::isMOVDDUPMask(PermMask.getNode())) 4015 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3()); 4016 4017 if (isSplatMask(PermMask.getNode())) { 4018 if (isMMX || NumElems < 4) return Op; 4019 // Promote it to a v4{if}32 splat. 4020 return PromoteSplat(Op, DAG, Subtarget->hasSSE2()); 4021 } 4022 4023 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4024 // do it! 4025 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4026 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); 4027 if (NewOp.getNode()) 4028 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); 4029 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4030 // FIXME: Figure out a cleaner way to do this. 4031 // Try to make use of movq to zero out the top part. 4032 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4033 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 4034 DAG, *this); 4035 if (NewOp.getNode()) { 4036 SDValue NewV1 = NewOp.getOperand(0); 4037 SDValue NewV2 = NewOp.getOperand(1); 4038 SDValue NewMask = NewOp.getOperand(2); 4039 if (isCommutedMOVL(NewMask.getNode(), true, false)) { 4040 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); 4041 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget); 4042 } 4043 } 4044 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4045 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 4046 DAG, *this); 4047 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode())) 4048 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4049 DAG, Subtarget); 4050 } 4051 } 4052 4053 // Check if this can be converted into a logical shift. 4054 bool isLeft = false; 4055 unsigned ShAmt = 0; 4056 SDValue ShVal; 4057 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt); 4058 if (isShift && ShVal.hasOneUse()) { 4059 // If the shifted value has multiple uses, it may be cheaper to use 4060 // v_set0 + movlhps or movhlps, etc. 4061 MVT EVT = VT.getVectorElementType(); 4062 ShAmt *= EVT.getSizeInBits(); 4063 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); 4064 } 4065 4066 if (X86::isMOVLMask(PermMask.getNode())) { 4067 if (V1IsUndef) 4068 return V2; 4069 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4070 return getVZextMovL(VT, VT, V2, DAG, Subtarget); 4071 if (!isMMX) 4072 return Op; 4073 } 4074 4075 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) || 4076 X86::isMOVSLDUPMask(PermMask.getNode()) || 4077 X86::isMOVHLPSMask(PermMask.getNode()) || 4078 X86::isMOVHPMask(PermMask.getNode()) || 4079 X86::isMOVLPMask(PermMask.getNode()))) 4080 return Op; 4081 4082 if (ShouldXformToMOVHLPS(PermMask.getNode()) || 4083 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode())) 4084 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4085 4086 if (isShift) { 4087 // No better options. Use a vshl / vsrl. 4088 MVT EVT = VT.getVectorElementType(); 4089 ShAmt *= EVT.getSizeInBits(); 4090 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); 4091 } 4092 4093 bool Commuted = false; 4094 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4095 // 1,1,1,1 -> v8i16 though. 4096 V1IsSplat = isSplatVector(V1.getNode()); 4097 V2IsSplat = isSplatVector(V2.getNode()); 4098 4099 // Canonicalize the splat or undef, if present, to be on the RHS. 4100 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4101 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4102 std::swap(V1IsSplat, V2IsSplat); 4103 std::swap(V1IsUndef, V2IsUndef); 4104 Commuted = true; 4105 } 4106 4107 // FIXME: Figure out a cleaner way to do this. 4108 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) { 4109 if (V2IsUndef) return V1; 4110 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4111 if (V2IsSplat) { 4112 // V2 is a splat, so the mask may be malformed. That is, it may point 4113 // to any V2 element. The instruction selectior won't like this. Get 4114 // a corrected mask and commute to form a proper MOVS{S|D}. 4115 SDValue NewMask = getMOVLMask(NumElems, DAG); 4116 if (NewMask.getNode() != PermMask.getNode()) 4117 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 4118 } 4119 return Op; 4120 } 4121 4122 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) || 4123 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) || 4124 X86::isUNPCKLMask(PermMask.getNode()) || 4125 X86::isUNPCKHMask(PermMask.getNode())) 4126 return Op; 4127 4128 if (V2IsSplat) { 4129 // Normalize mask so all entries that point to V2 points to its first 4130 // element then try to match unpck{h|l} again. If match, return a 4131 // new vector_shuffle with the corrected mask. 4132 SDValue NewMask = NormalizeMask(PermMask, DAG); 4133 if (NewMask.getNode() != PermMask.getNode()) { 4134 if (X86::isUNPCKLMask(PermMask.getNode(), true)) { 4135 SDValue NewMask = getUnpacklMask(NumElems, DAG); 4136 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 4137 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) { 4138 SDValue NewMask = getUnpackhMask(NumElems, DAG); 4139 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 4140 } 4141 } 4142 } 4143 4144 // Normalize the node to match x86 shuffle ops if needed 4145 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode())) 4146 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4147 4148 if (Commuted) { 4149 // Commute is back and try unpck* again. 4150 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4151 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) || 4152 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) || 4153 X86::isUNPCKLMask(PermMask.getNode()) || 4154 X86::isUNPCKHMask(PermMask.getNode())) 4155 return Op; 4156 } 4157 4158 // Try PSHUF* first, then SHUFP*. 4159 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically 4160 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. 4161 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) { 4162 if (V2.getOpcode() != ISD::UNDEF) 4163 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 4164 DAG.getNode(ISD::UNDEF, VT), PermMask); 4165 return Op; 4166 } 4167 4168 if (!isMMX) { 4169 if (Subtarget->hasSSE2() && 4170 (X86::isPSHUFDMask(PermMask.getNode()) || 4171 X86::isPSHUFHWMask(PermMask.getNode()) || 4172 X86::isPSHUFLWMask(PermMask.getNode()))) { 4173 MVT RVT = VT; 4174 if (VT == MVT::v4f32) { 4175 RVT = MVT::v4i32; 4176 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, 4177 DAG.getNode(ISD::BIT_CONVERT, RVT, V1), 4178 DAG.getNode(ISD::UNDEF, RVT), PermMask); 4179 } else if (V2.getOpcode() != ISD::UNDEF) 4180 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1, 4181 DAG.getNode(ISD::UNDEF, RVT), PermMask); 4182 if (RVT != VT) 4183 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op); 4184 return Op; 4185 } 4186 4187 // Binary or unary shufps. 4188 if (X86::isSHUFPMask(PermMask.getNode()) || 4189 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode()))) 4190 return Op; 4191 } 4192 4193 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4194 if (VT == MVT::v8i16) { 4195 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); 4196 if (NewOp.getNode()) 4197 return NewOp; 4198 } 4199 4200 // Handle all 4 wide cases with a number of shuffles except for MMX. 4201 if (NumElems == 4 && !isMMX) 4202 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG); 4203 4204 return SDValue(); 4205} 4206 4207SDValue 4208X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4209 SelectionDAG &DAG) { 4210 MVT VT = Op.getValueType(); 4211 if (VT.getSizeInBits() == 8) { 4212 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, 4213 Op.getOperand(0), Op.getOperand(1)); 4214 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 4215 DAG.getValueType(VT)); 4216 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4217 } else if (VT.getSizeInBits() == 16) { 4218 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, 4219 Op.getOperand(0), Op.getOperand(1)); 4220 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 4221 DAG.getValueType(VT)); 4222 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4223 } else if (VT == MVT::f32) { 4224 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4225 // the result back to FR32 register. It's only worth matching if the 4226 // result has a single use which is a store or a bitcast to i32. And in 4227 // the case of a store, it's not worth it if the index is a constant 0, 4228 // because a MOVSSmr can be used instead, which is smaller and faster. 4229 if (!Op.hasOneUse()) 4230 return SDValue(); 4231 SDNode *User = *Op.getNode()->use_begin(); 4232 if ((User->getOpcode() != ISD::STORE || 4233 (isa<ConstantSDNode>(Op.getOperand(1)) && 4234 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4235 (User->getOpcode() != ISD::BIT_CONVERT || 4236 User->getValueType(0) != MVT::i32)) 4237 return SDValue(); 4238 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4239 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), 4240 Op.getOperand(1)); 4241 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); 4242 } 4243 return SDValue(); 4244} 4245 4246 4247SDValue 4248X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4249 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4250 return SDValue(); 4251 4252 if (Subtarget->hasSSE41()) { 4253 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4254 if (Res.getNode()) 4255 return Res; 4256 } 4257 4258 MVT VT = Op.getValueType(); 4259 // TODO: handle v16i8. 4260 if (VT.getSizeInBits() == 16) { 4261 SDValue Vec = Op.getOperand(0); 4262 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4263 if (Idx == 0) 4264 return DAG.getNode(ISD::TRUNCATE, MVT::i16, 4265 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4266 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), 4267 Op.getOperand(1))); 4268 // Transform it so it match pextrw which produces a 32-bit result. 4269 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); 4270 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 4271 Op.getOperand(0), Op.getOperand(1)); 4272 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 4273 DAG.getValueType(VT)); 4274 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4275 } else if (VT.getSizeInBits() == 32) { 4276 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4277 if (Idx == 0) 4278 return Op; 4279 // SHUFPS the element to the lowest double word, then movss. 4280 MVT MaskVT = MVT::getIntVectorWithNumElements(4); 4281 SmallVector<SDValue, 8> IdxVec; 4282 IdxVec. 4283 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); 4284 IdxVec. 4285 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4286 IdxVec. 4287 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4288 IdxVec. 4289 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4290 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4291 &IdxVec[0], IdxVec.size()); 4292 SDValue Vec = Op.getOperand(0); 4293 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 4294 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 4295 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 4296 DAG.getIntPtrConstant(0)); 4297 } else if (VT.getSizeInBits() == 64) { 4298 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4299 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4300 // to match extract_elt for f64. 4301 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4302 if (Idx == 0) 4303 return Op; 4304 4305 // UNPCKHPD the element to the lowest double word, then movsd. 4306 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4307 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4308 MVT MaskVT = MVT::getIntVectorWithNumElements(2); 4309 SmallVector<SDValue, 8> IdxVec; 4310 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); 4311 IdxVec. 4312 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4313 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4314 &IdxVec[0], IdxVec.size()); 4315 SDValue Vec = Op.getOperand(0); 4316 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 4317 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 4318 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 4319 DAG.getIntPtrConstant(0)); 4320 } 4321 4322 return SDValue(); 4323} 4324 4325SDValue 4326X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4327 MVT VT = Op.getValueType(); 4328 MVT EVT = VT.getVectorElementType(); 4329 4330 SDValue N0 = Op.getOperand(0); 4331 SDValue N1 = Op.getOperand(1); 4332 SDValue N2 = Op.getOperand(2); 4333 4334 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4335 isa<ConstantSDNode>(N2)) { 4336 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4337 : X86ISD::PINSRW; 4338 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4339 // argument. 4340 if (N1.getValueType() != MVT::i32) 4341 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 4342 if (N2.getValueType() != MVT::i32) 4343 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4344 return DAG.getNode(Opc, VT, N0, N1, N2); 4345 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4346 // Bits [7:6] of the constant are the source select. This will always be 4347 // zero here. The DAG Combiner may combine an extract_elt index into these 4348 // bits. For example (insert (extract, 3), 2) could be matched by putting 4349 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4350 // Bits [5:4] of the constant are the destination select. This is the 4351 // value of the incoming immediate. 4352 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4353 // combine either bitwise AND or insert of float 0.0 to set these bits. 4354 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4355 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); 4356 } 4357 return SDValue(); 4358} 4359 4360SDValue 4361X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4362 MVT VT = Op.getValueType(); 4363 MVT EVT = VT.getVectorElementType(); 4364 4365 if (Subtarget->hasSSE41()) 4366 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4367 4368 if (EVT == MVT::i8) 4369 return SDValue(); 4370 4371 SDValue N0 = Op.getOperand(0); 4372 SDValue N1 = Op.getOperand(1); 4373 SDValue N2 = Op.getOperand(2); 4374 4375 if (EVT.getSizeInBits() == 16) { 4376 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4377 // as its second argument. 4378 if (N1.getValueType() != MVT::i32) 4379 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 4380 if (N2.getValueType() != MVT::i32) 4381 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4382 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 4383 } 4384 return SDValue(); 4385} 4386 4387SDValue 4388X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4389 if (Op.getValueType() == MVT::v2f32) 4390 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32, 4391 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32, 4392 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, 4393 Op.getOperand(0)))); 4394 4395 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 4396 MVT VT = MVT::v2i32; 4397 switch (Op.getValueType().getSimpleVT()) { 4398 default: break; 4399 case MVT::v16i8: 4400 case MVT::v8i16: 4401 VT = MVT::v4i32; 4402 break; 4403 } 4404 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), 4405 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt)); 4406} 4407 4408// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4409// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4410// one of the above mentioned nodes. It has to be wrapped because otherwise 4411// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4412// be used to form addressing mode. These wrapped nodes will be selected 4413// into MOV32ri. 4414SDValue 4415X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4416 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4417 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), 4418 getPointerTy(), 4419 CP->getAlignment()); 4420 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4421 // With PIC, the address is actually $g + Offset. 4422 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4423 !Subtarget->isPICStyleRIPRel()) { 4424 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4425 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4426 Result); 4427 } 4428 4429 return Result; 4430} 4431 4432SDValue 4433X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, 4434 int64_t Offset, 4435 SelectionDAG &DAG) const { 4436 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 4437 bool ExtraLoadRequired = 4438 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false); 4439 4440 // Create the TargetGlobalAddress node, folding in the constant 4441 // offset if it is legal. 4442 SDValue Result; 4443 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) { 4444 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 4445 Offset = 0; 4446 } else 4447 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0); 4448 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4449 4450 // With PIC, the address is actually $g + Offset. 4451 if (IsPic && !Subtarget->isPICStyleRIPRel()) { 4452 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4453 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4454 Result); 4455 } 4456 4457 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 4458 // load the value at address GV, not the value of GV itself. This means that 4459 // the GlobalAddress must be in the base or index register of the address, not 4460 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 4461 // The same applies for external symbols during PIC codegen 4462 if (ExtraLoadRequired) 4463 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, 4464 PseudoSourceValue::getGOT(), 0); 4465 4466 // If there was a non-zero offset that we didn't fold, create an explicit 4467 // addition for it. 4468 if (Offset != 0) 4469 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result, 4470 DAG.getConstant(Offset, getPointerTy())); 4471 4472 return Result; 4473} 4474 4475SDValue 4476X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4477 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4478 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 4479 return LowerGlobalAddress(GV, Offset, DAG); 4480} 4481 4482// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4483static SDValue 4484LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4485 const MVT PtrVT) { 4486 SDValue InFlag; 4487 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, 4488 DAG.getNode(X86ISD::GlobalBaseReg, 4489 PtrVT), InFlag); 4490 InFlag = Chain.getValue(1); 4491 4492 // emit leal symbol@TLSGD(,%ebx,1), %eax 4493 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4494 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4495 GA->getValueType(0), 4496 GA->getOffset()); 4497 SDValue Ops[] = { Chain, TGA, InFlag }; 4498 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); 4499 InFlag = Result.getValue(2); 4500 Chain = Result.getValue(1); 4501 4502 // call ___tls_get_addr. This function receives its argument in 4503 // the register EAX. 4504 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag); 4505 InFlag = Chain.getValue(1); 4506 4507 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4508 SDValue Ops1[] = { Chain, 4509 DAG.getTargetExternalSymbol("___tls_get_addr", 4510 PtrVT), 4511 DAG.getRegister(X86::EAX, PtrVT), 4512 DAG.getRegister(X86::EBX, PtrVT), 4513 InFlag }; 4514 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5); 4515 InFlag = Chain.getValue(1); 4516 4517 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag); 4518} 4519 4520// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4521static SDValue 4522LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4523 const MVT PtrVT) { 4524 SDValue InFlag, Chain; 4525 4526 // emit leaq symbol@TLSGD(%rip), %rdi 4527 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4528 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4529 GA->getValueType(0), 4530 GA->getOffset()); 4531 SDValue Ops[] = { DAG.getEntryNode(), TGA}; 4532 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2); 4533 Chain = Result.getValue(1); 4534 InFlag = Result.getValue(2); 4535 4536 // call __tls_get_addr. This function receives its argument in 4537 // the register RDI. 4538 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag); 4539 InFlag = Chain.getValue(1); 4540 4541 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4542 SDValue Ops1[] = { Chain, 4543 DAG.getTargetExternalSymbol("__tls_get_addr", 4544 PtrVT), 4545 DAG.getRegister(X86::RDI, PtrVT), 4546 InFlag }; 4547 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4); 4548 InFlag = Chain.getValue(1); 4549 4550 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag); 4551} 4552 4553// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4554// "local exec" model. 4555static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4556 const MVT PtrVT) { 4557 // Get the Thread Pointer 4558 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); 4559 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4560 // exec) 4561 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4562 GA->getValueType(0), 4563 GA->getOffset()); 4564 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); 4565 4566 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model 4567 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, 4568 PseudoSourceValue::getGOT(), 0); 4569 4570 // The address of the thread local variable is the add of the thread 4571 // pointer with the offset of the variable. 4572 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 4573} 4574 4575SDValue 4576X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4577 // TODO: implement the "local dynamic" model 4578 // TODO: implement the "initial exec"model for pic executables 4579 assert(Subtarget->isTargetELF() && 4580 "TLS not implemented for non-ELF targets"); 4581 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4582 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 4583 // otherwise use the "Local Exec"TLS Model 4584 if (Subtarget->is64Bit()) { 4585 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4586 } else { 4587 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 4588 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4589 else 4590 return LowerToTLSExecModel(GA, DAG, getPointerTy()); 4591 } 4592} 4593 4594SDValue 4595X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4596 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4597 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 4598 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4599 // With PIC, the address is actually $g + Offset. 4600 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4601 !Subtarget->isPICStyleRIPRel()) { 4602 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4603 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4604 Result); 4605 } 4606 4607 return Result; 4608} 4609 4610SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4611 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4612 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 4613 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4614 // With PIC, the address is actually $g + Offset. 4615 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4616 !Subtarget->isPICStyleRIPRel()) { 4617 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4618 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4619 Result); 4620 } 4621 4622 return Result; 4623} 4624 4625/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4626/// take a 2 x i32 value to shift plus a shift amount. 4627SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4628 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4629 MVT VT = Op.getValueType(); 4630 unsigned VTBits = VT.getSizeInBits(); 4631 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4632 SDValue ShOpLo = Op.getOperand(0); 4633 SDValue ShOpHi = Op.getOperand(1); 4634 SDValue ShAmt = Op.getOperand(2); 4635 SDValue Tmp1 = isSRA ? 4636 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : 4637 DAG.getConstant(0, VT); 4638 4639 SDValue Tmp2, Tmp3; 4640 if (Op.getOpcode() == ISD::SHL_PARTS) { 4641 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); 4642 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); 4643 } else { 4644 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); 4645 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); 4646 } 4647 4648 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 4649 DAG.getConstant(VTBits, MVT::i8)); 4650 SDValue Cond = DAG.getNode(X86ISD::CMP, VT, 4651 AndNode, DAG.getConstant(0, MVT::i8)); 4652 4653 SDValue Hi, Lo; 4654 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4655 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4656 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4657 4658 if (Op.getOpcode() == ISD::SHL_PARTS) { 4659 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); 4660 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); 4661 } else { 4662 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); 4663 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); 4664 } 4665 4666 SDValue Ops[2] = { Lo, Hi }; 4667 return DAG.getMergeValues(Ops, 2); 4668} 4669 4670SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4671 MVT SrcVT = Op.getOperand(0).getValueType(); 4672 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4673 "Unknown SINT_TO_FP to lower!"); 4674 4675 // These are really Legal; caller falls through into that case. 4676 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4677 return SDValue(); 4678 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && 4679 Subtarget->is64Bit()) 4680 return SDValue(); 4681 4682 unsigned Size = SrcVT.getSizeInBits()/8; 4683 MachineFunction &MF = DAG.getMachineFunction(); 4684 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4685 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4686 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), 4687 StackSlot, 4688 PseudoSourceValue::getFixedStack(SSFI), 0); 4689 4690 // Build the FILD 4691 SDVTList Tys; 4692 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4693 if (useSSE) 4694 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4695 else 4696 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4697 SmallVector<SDValue, 8> Ops; 4698 Ops.push_back(Chain); 4699 Ops.push_back(StackSlot); 4700 Ops.push_back(DAG.getValueType(SrcVT)); 4701 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, 4702 Tys, &Ops[0], Ops.size()); 4703 4704 if (useSSE) { 4705 Chain = Result.getValue(1); 4706 SDValue InFlag = Result.getValue(2); 4707 4708 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4709 // shouldn't be necessary except that RFP cannot be live across 4710 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4711 MachineFunction &MF = DAG.getMachineFunction(); 4712 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4713 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4714 Tys = DAG.getVTList(MVT::Other); 4715 SmallVector<SDValue, 8> Ops; 4716 Ops.push_back(Chain); 4717 Ops.push_back(Result); 4718 Ops.push_back(StackSlot); 4719 Ops.push_back(DAG.getValueType(Op.getValueType())); 4720 Ops.push_back(InFlag); 4721 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 4722 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, 4723 PseudoSourceValue::getFixedStack(SSFI), 0); 4724 } 4725 4726 return Result; 4727} 4728 4729SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4730 MVT SrcVT = Op.getOperand(0).getValueType(); 4731 assert(SrcVT.getSimpleVT() == MVT::i64 && "Unknown UINT_TO_FP to lower!"); 4732 4733 // We only handle SSE2 f64 target here; caller can handle the rest. 4734 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 4735 return SDValue(); 4736 4737 // This algorithm is not obvious. Here it is in C code, more or less: 4738/* 4739 double uint64_to_double( uint32_t hi, uint32_t lo ) 4740 { 4741 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 4742 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 4743 4744 // copy ints to xmm registers 4745 __m128i xh = _mm_cvtsi32_si128( hi ); 4746 __m128i xl = _mm_cvtsi32_si128( lo ); 4747 4748 // combine into low half of a single xmm register 4749 __m128i x = _mm_unpacklo_epi32( xh, xl ); 4750 __m128d d; 4751 double sd; 4752 4753 // merge in appropriate exponents to give the integer bits the 4754 // right magnitude 4755 x = _mm_unpacklo_epi32( x, exp ); 4756 4757 // subtract away the biases to deal with the IEEE-754 double precision 4758 // implicit 1 4759 d = _mm_sub_pd( (__m128d) x, bias ); 4760 4761 // All conversions up to here are exact. The correctly rounded result is 4762 // calculated using the 4763 // current rounding mode using the following horizontal add. 4764 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 4765 _mm_store_sd( &sd, d ); //since we are returning doubles in XMM, this 4766 // store doesn't really need to be here (except maybe to zero the other 4767 // double) 4768 return sd; 4769 } 4770*/ 4771 4772 // Build some magic constants. 4773 std::vector<Constant*>CV0; 4774 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000))); 4775 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000))); 4776 CV0.push_back(ConstantInt::get(APInt(32, 0))); 4777 CV0.push_back(ConstantInt::get(APInt(32, 0))); 4778 Constant *C0 = ConstantVector::get(CV0); 4779 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4); 4780 4781 std::vector<Constant*>CV1; 4782 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL)))); 4783 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL)))); 4784 Constant *C1 = ConstantVector::get(CV1); 4785 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4); 4786 4787 SmallVector<SDValue, 4> MaskVec; 4788 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 4789 MaskVec.push_back(DAG.getConstant(4, MVT::i32)); 4790 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 4791 MaskVec.push_back(DAG.getConstant(5, MVT::i32)); 4792 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0], 4793 MaskVec.size()); 4794 SmallVector<SDValue, 4> MaskVec2; 4795 MaskVec2.push_back(DAG.getConstant(1, MVT::i32)); 4796 MaskVec2.push_back(DAG.getConstant(0, MVT::i32)); 4797 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0], 4798 MaskVec2.size()); 4799 4800 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, 4801 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 4802 Op.getOperand(0), 4803 DAG.getIntPtrConstant(1))); 4804 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32, 4805 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 4806 Op.getOperand(0), 4807 DAG.getIntPtrConstant(0))); 4808 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, 4809 XR1, XR2, UnpcklMask); 4810 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0, 4811 PseudoSourceValue::getConstantPool(), 0, false, 16); 4812 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, 4813 Unpck1, CLod0, UnpcklMask); 4814 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2); 4815 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1, 4816 PseudoSourceValue::getConstantPool(), 0, false, 16); 4817 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1); 4818 // Add the halves; easiest way is to swap them into another reg first. 4819 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64, 4820 Sub, Sub, ShufMask); 4821 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub); 4822 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add, 4823 DAG.getIntPtrConstant(0)); 4824} 4825 4826std::pair<SDValue,SDValue> X86TargetLowering:: 4827FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) { 4828 assert(Op.getValueType().getSimpleVT() <= MVT::i64 && 4829 Op.getValueType().getSimpleVT() >= MVT::i16 && 4830 "Unknown FP_TO_SINT to lower!"); 4831 4832 // These are really Legal. 4833 if (Op.getValueType() == MVT::i32 && 4834 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 4835 return std::make_pair(SDValue(), SDValue()); 4836 if (Subtarget->is64Bit() && 4837 Op.getValueType() == MVT::i64 && 4838 Op.getOperand(0).getValueType() != MVT::f80) 4839 return std::make_pair(SDValue(), SDValue()); 4840 4841 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 4842 // stack slot. 4843 MachineFunction &MF = DAG.getMachineFunction(); 4844 unsigned MemSize = Op.getValueType().getSizeInBits()/8; 4845 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4846 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4847 unsigned Opc; 4848 switch (Op.getValueType().getSimpleVT()) { 4849 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 4850 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 4851 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 4852 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 4853 } 4854 4855 SDValue Chain = DAG.getEntryNode(); 4856 SDValue Value = Op.getOperand(0); 4857 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 4858 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 4859 Chain = DAG.getStore(Chain, Value, StackSlot, 4860 PseudoSourceValue::getFixedStack(SSFI), 0); 4861 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 4862 SDValue Ops[] = { 4863 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 4864 }; 4865 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 4866 Chain = Value.getValue(1); 4867 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4868 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4869 } 4870 4871 // Build the FP_TO_INT*_IN_MEM 4872 SDValue Ops[] = { Chain, Value, StackSlot }; 4873 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); 4874 4875 return std::make_pair(FIST, StackSlot); 4876} 4877 4878SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 4879 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG); 4880 SDValue FIST = Vals.first, StackSlot = Vals.second; 4881 if (FIST.getNode() == 0) return SDValue(); 4882 4883 // Load the result. 4884 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); 4885} 4886 4887SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 4888 MVT VT = Op.getValueType(); 4889 MVT EltVT = VT; 4890 if (VT.isVector()) 4891 EltVT = VT.getVectorElementType(); 4892 std::vector<Constant*> CV; 4893 if (EltVT == MVT::f64) { 4894 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); 4895 CV.push_back(C); 4896 CV.push_back(C); 4897 } else { 4898 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))); 4899 CV.push_back(C); 4900 CV.push_back(C); 4901 CV.push_back(C); 4902 CV.push_back(C); 4903 } 4904 Constant *C = ConstantVector::get(CV); 4905 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4906 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4907 PseudoSourceValue::getConstantPool(), 0, 4908 false, 16); 4909 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 4910} 4911 4912SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 4913 MVT VT = Op.getValueType(); 4914 MVT EltVT = VT; 4915 unsigned EltNum = 1; 4916 if (VT.isVector()) { 4917 EltVT = VT.getVectorElementType(); 4918 EltNum = VT.getVectorNumElements(); 4919 } 4920 std::vector<Constant*> CV; 4921 if (EltVT == MVT::f64) { 4922 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63))); 4923 CV.push_back(C); 4924 CV.push_back(C); 4925 } else { 4926 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31))); 4927 CV.push_back(C); 4928 CV.push_back(C); 4929 CV.push_back(C); 4930 CV.push_back(C); 4931 } 4932 Constant *C = ConstantVector::get(CV); 4933 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4934 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4935 PseudoSourceValue::getConstantPool(), 0, 4936 false, 16); 4937 if (VT.isVector()) { 4938 return DAG.getNode(ISD::BIT_CONVERT, VT, 4939 DAG.getNode(ISD::XOR, MVT::v2i64, 4940 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), 4941 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask))); 4942 } else { 4943 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 4944 } 4945} 4946 4947SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 4948 SDValue Op0 = Op.getOperand(0); 4949 SDValue Op1 = Op.getOperand(1); 4950 MVT VT = Op.getValueType(); 4951 MVT SrcVT = Op1.getValueType(); 4952 4953 // If second operand is smaller, extend it first. 4954 if (SrcVT.bitsLT(VT)) { 4955 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); 4956 SrcVT = VT; 4957 } 4958 // And if it is bigger, shrink it first. 4959 if (SrcVT.bitsGT(VT)) { 4960 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); 4961 SrcVT = VT; 4962 } 4963 4964 // At this point the operands and the result should have the same 4965 // type, and that won't be f80 since that is not custom lowered. 4966 4967 // First get the sign bit of second operand. 4968 std::vector<Constant*> CV; 4969 if (SrcVT == MVT::f64) { 4970 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63)))); 4971 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 4972 } else { 4973 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31)))); 4974 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4975 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4976 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4977 } 4978 Constant *C = ConstantVector::get(CV); 4979 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4980 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, 4981 PseudoSourceValue::getConstantPool(), 0, 4982 false, 16); 4983 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); 4984 4985 // Shift sign bit right or left if the two operands have different types. 4986 if (SrcVT.bitsGT(VT)) { 4987 // Op0 is MVT::f32, Op1 is MVT::f64. 4988 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); 4989 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, 4990 DAG.getConstant(32, MVT::i32)); 4991 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); 4992 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, 4993 DAG.getIntPtrConstant(0)); 4994 } 4995 4996 // Clear first operand sign bit. 4997 CV.clear(); 4998 if (VT == MVT::f64) { 4999 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))))); 5000 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5001 } else { 5002 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31))))); 5003 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5004 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5005 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5006 } 5007 C = ConstantVector::get(CV); 5008 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5009 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5010 PseudoSourceValue::getConstantPool(), 0, 5011 false, 16); 5012 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); 5013 5014 // Or the value with the sign bit. 5015 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); 5016} 5017 5018SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5019 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5020 SDValue Cond; 5021 SDValue Op0 = Op.getOperand(0); 5022 SDValue Op1 = Op.getOperand(1); 5023 SDValue CC = Op.getOperand(2); 5024 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5025 5026 unsigned X86CC = TranslateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, 5027 Op0, Op1, DAG); 5028 5029 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); 5030 return DAG.getNode(X86ISD::SETCC, MVT::i8, 5031 DAG.getConstant(X86CC, MVT::i8), Cond); 5032} 5033 5034SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5035 SDValue Cond; 5036 SDValue Op0 = Op.getOperand(0); 5037 SDValue Op1 = Op.getOperand(1); 5038 SDValue CC = Op.getOperand(2); 5039 MVT VT = Op.getValueType(); 5040 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5041 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5042 5043 if (isFP) { 5044 unsigned SSECC = 8; 5045 MVT VT0 = Op0.getValueType(); 5046 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5047 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5048 bool Swap = false; 5049 5050 switch (SetCCOpcode) { 5051 default: break; 5052 case ISD::SETOEQ: 5053 case ISD::SETEQ: SSECC = 0; break; 5054 case ISD::SETOGT: 5055 case ISD::SETGT: Swap = true; // Fallthrough 5056 case ISD::SETLT: 5057 case ISD::SETOLT: SSECC = 1; break; 5058 case ISD::SETOGE: 5059 case ISD::SETGE: Swap = true; // Fallthrough 5060 case ISD::SETLE: 5061 case ISD::SETOLE: SSECC = 2; break; 5062 case ISD::SETUO: SSECC = 3; break; 5063 case ISD::SETUNE: 5064 case ISD::SETNE: SSECC = 4; break; 5065 case ISD::SETULE: Swap = true; 5066 case ISD::SETUGE: SSECC = 5; break; 5067 case ISD::SETULT: Swap = true; 5068 case ISD::SETUGT: SSECC = 6; break; 5069 case ISD::SETO: SSECC = 7; break; 5070 } 5071 if (Swap) 5072 std::swap(Op0, Op1); 5073 5074 // In the two special cases we can't handle, emit two comparisons. 5075 if (SSECC == 8) { 5076 if (SetCCOpcode == ISD::SETUEQ) { 5077 SDValue UNORD, EQ; 5078 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 5079 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 5080 return DAG.getNode(ISD::OR, VT, UNORD, EQ); 5081 } 5082 else if (SetCCOpcode == ISD::SETONE) { 5083 SDValue ORD, NEQ; 5084 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 5085 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 5086 return DAG.getNode(ISD::AND, VT, ORD, NEQ); 5087 } 5088 assert(0 && "Illegal FP comparison"); 5089 } 5090 // Handle all other FP comparisons here. 5091 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 5092 } 5093 5094 // We are handling one of the integer comparisons here. Since SSE only has 5095 // GT and EQ comparisons for integer, swapping operands and multiple 5096 // operations may be required for some comparisons. 5097 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 5098 bool Swap = false, Invert = false, FlipSigns = false; 5099 5100 switch (VT.getSimpleVT()) { 5101 default: break; 5102 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 5103 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 5104 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 5105 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 5106 } 5107 5108 switch (SetCCOpcode) { 5109 default: break; 5110 case ISD::SETNE: Invert = true; 5111 case ISD::SETEQ: Opc = EQOpc; break; 5112 case ISD::SETLT: Swap = true; 5113 case ISD::SETGT: Opc = GTOpc; break; 5114 case ISD::SETGE: Swap = true; 5115 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 5116 case ISD::SETULT: Swap = true; 5117 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 5118 case ISD::SETUGE: Swap = true; 5119 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 5120 } 5121 if (Swap) 5122 std::swap(Op0, Op1); 5123 5124 // Since SSE has no unsigned integer comparisons, we need to flip the sign 5125 // bits of the inputs before performing those operations. 5126 if (FlipSigns) { 5127 MVT EltVT = VT.getVectorElementType(); 5128 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT); 5129 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 5130 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0], 5131 SignBits.size()); 5132 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec); 5133 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec); 5134 } 5135 5136 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1); 5137 5138 // If the logical-not of the result is required, perform that now. 5139 if (Invert) { 5140 MVT EltVT = VT.getVectorElementType(); 5141 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT); 5142 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne); 5143 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], 5144 NegOnes.size()); 5145 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV); 5146 } 5147 return Result; 5148} 5149 5150// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 5151static bool isX86LogicalCmp(unsigned Opc) { 5152 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI; 5153} 5154 5155SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 5156 bool addTest = true; 5157 SDValue Cond = Op.getOperand(0); 5158 SDValue CC; 5159 5160 if (Cond.getOpcode() == ISD::SETCC) 5161 Cond = LowerSETCC(Cond, DAG); 5162 5163 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5164 // setting operand in place of the X86ISD::SETCC. 5165 if (Cond.getOpcode() == X86ISD::SETCC) { 5166 CC = Cond.getOperand(0); 5167 5168 SDValue Cmp = Cond.getOperand(1); 5169 unsigned Opc = Cmp.getOpcode(); 5170 MVT VT = Op.getValueType(); 5171 5172 bool IllegalFPCMov = false; 5173 if (VT.isFloatingPoint() && !VT.isVector() && 5174 !isScalarFPTypeInSSEReg(VT)) // FPStack? 5175 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 5176 5177 if (isX86LogicalCmp(Opc) && !IllegalFPCMov) { 5178 Cond = Cmp; 5179 addTest = false; 5180 } 5181 } 5182 5183 if (addTest) { 5184 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5185 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 5186 } 5187 5188 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), 5189 MVT::Flag); 5190 SmallVector<SDValue, 4> Ops; 5191 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 5192 // condition is true. 5193 Ops.push_back(Op.getOperand(2)); 5194 Ops.push_back(Op.getOperand(1)); 5195 Ops.push_back(CC); 5196 Ops.push_back(Cond); 5197 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 5198} 5199 5200// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 5201// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 5202// from the AND / OR. 5203static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 5204 Opc = Op.getOpcode(); 5205 if (Opc != ISD::OR && Opc != ISD::AND) 5206 return false; 5207 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5208 Op.getOperand(0).hasOneUse() && 5209 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 5210 Op.getOperand(1).hasOneUse()); 5211} 5212 5213SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 5214 bool addTest = true; 5215 SDValue Chain = Op.getOperand(0); 5216 SDValue Cond = Op.getOperand(1); 5217 SDValue Dest = Op.getOperand(2); 5218 SDValue CC; 5219 5220 if (Cond.getOpcode() == ISD::SETCC) 5221 Cond = LowerSETCC(Cond, DAG); 5222 else if (Cond.getOpcode() == X86ISD::ADD || 5223 Cond.getOpcode() == X86ISD::SUB || 5224 Cond.getOpcode() == X86ISD::SMUL || 5225 Cond.getOpcode() == X86ISD::UMUL) 5226 Cond = LowerXALUO(Cond, DAG); 5227 5228 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5229 // setting operand in place of the X86ISD::SETCC. 5230 if (Cond.getOpcode() == X86ISD::SETCC) { 5231 CC = Cond.getOperand(0); 5232 5233 SDValue Cmp = Cond.getOperand(1); 5234 unsigned Opc = Cmp.getOpcode(); 5235 if (isX86LogicalCmp(Opc)) { 5236 Cond = Cmp; 5237 addTest = false; 5238 } else { 5239 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 5240 default: break; 5241 case X86::COND_O: 5242 case X86::COND_C: 5243 // These can only come from an arithmetic instruction with overflow, e.g. 5244 // SADDO, UADDO. 5245 Cond = Cond.getNode()->getOperand(1); 5246 addTest = false; 5247 break; 5248 } 5249 } 5250 } else { 5251 unsigned CondOpc; 5252 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 5253 SDValue Cmp = Cond.getOperand(0).getOperand(1); 5254 unsigned Opc = Cmp.getOpcode(); 5255 if (CondOpc == ISD::OR) { 5256 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 5257 // two branches instead of an explicit OR instruction with a 5258 // separate test. 5259 if (Cmp == Cond.getOperand(1).getOperand(1) && 5260 isX86LogicalCmp(Opc)) { 5261 CC = Cond.getOperand(0).getOperand(0); 5262 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 5263 Chain, Dest, CC, Cmp); 5264 CC = Cond.getOperand(1).getOperand(0); 5265 Cond = Cmp; 5266 addTest = false; 5267 } 5268 } else { // ISD::AND 5269 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 5270 // two branches instead of an explicit AND instruction with a 5271 // separate test. However, we only do this if this block doesn't 5272 // have a fall-through edge, because this requires an explicit 5273 // jmp when the condition is false. 5274 if (Cmp == Cond.getOperand(1).getOperand(1) && 5275 isX86LogicalCmp(Opc) && 5276 Op.getNode()->hasOneUse()) { 5277 X86::CondCode CCode = 5278 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5279 CCode = X86::GetOppositeBranchCondition(CCode); 5280 CC = DAG.getConstant(CCode, MVT::i8); 5281 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 5282 // Look for an unconditional branch following this conditional branch. 5283 // We need this because we need to reverse the successors in order 5284 // to implement FCMP_OEQ. 5285 if (User.getOpcode() == ISD::BR) { 5286 SDValue FalseBB = User.getOperand(1); 5287 SDValue NewBR = 5288 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 5289 assert(NewBR == User); 5290 Dest = FalseBB; 5291 5292 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 5293 Chain, Dest, CC, Cmp); 5294 X86::CondCode CCode = 5295 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 5296 CCode = X86::GetOppositeBranchCondition(CCode); 5297 CC = DAG.getConstant(CCode, MVT::i8); 5298 Cond = Cmp; 5299 addTest = false; 5300 } 5301 } 5302 } 5303 } 5304 } 5305 5306 if (addTest) { 5307 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5308 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 5309 } 5310 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 5311 Chain, Dest, CC, Cond); 5312} 5313 5314 5315// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 5316// Calls to _alloca is needed to probe the stack when allocating more than 4k 5317// bytes in one go. Touching the stack at 4K increments is necessary to ensure 5318// that the guard pages used by the OS virtual memory manager are allocated in 5319// correct sequence. 5320SDValue 5321X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5322 SelectionDAG &DAG) { 5323 assert(Subtarget->isTargetCygMing() && 5324 "This should be used only on Cygwin/Mingw targets"); 5325 5326 // Get the inputs. 5327 SDValue Chain = Op.getOperand(0); 5328 SDValue Size = Op.getOperand(1); 5329 // FIXME: Ensure alignment here 5330 5331 SDValue Flag; 5332 5333 MVT IntPtr = getPointerTy(); 5334 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5335 5336 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 5337 5338 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); 5339 Flag = Chain.getValue(1); 5340 5341 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5342 SDValue Ops[] = { Chain, 5343 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5344 DAG.getRegister(X86::EAX, IntPtr), 5345 DAG.getRegister(X86StackPtr, SPTy), 5346 Flag }; 5347 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5); 5348 Flag = Chain.getValue(1); 5349 5350 Chain = DAG.getCALLSEQ_END(Chain, 5351 DAG.getIntPtrConstant(0, true), 5352 DAG.getIntPtrConstant(0, true), 5353 Flag); 5354 5355 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); 5356 5357 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5358 return DAG.getMergeValues(Ops1, 2); 5359} 5360 5361SDValue 5362X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, 5363 SDValue Chain, 5364 SDValue Dst, SDValue Src, 5365 SDValue Size, unsigned Align, 5366 const Value *DstSV, 5367 uint64_t DstSVOff) { 5368 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5369 5370 // If not DWORD aligned or size is more than the threshold, call the library. 5371 // The libc version is likely to be faster for these cases. It can use the 5372 // address value and run time information about the CPU. 5373 if ((Align & 3) != 0 || 5374 !ConstantSize || 5375 ConstantSize->getZExtValue() > 5376 getSubtarget()->getMaxInlineSizeThreshold()) { 5377 SDValue InFlag(0, 0); 5378 5379 // Check to see if there is a specialized entry-point for memory zeroing. 5380 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5381 5382 if (const char *bzeroEntry = V && 5383 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5384 MVT IntPtr = getPointerTy(); 5385 const Type *IntPtrTy = TD->getIntPtrType(); 5386 TargetLowering::ArgListTy Args; 5387 TargetLowering::ArgListEntry Entry; 5388 Entry.Node = Dst; 5389 Entry.Ty = IntPtrTy; 5390 Args.push_back(Entry); 5391 Entry.Node = Size; 5392 Args.push_back(Entry); 5393 std::pair<SDValue,SDValue> CallResult = 5394 LowerCallTo(Chain, Type::VoidTy, false, false, false, false, 5395 CallingConv::C, false, 5396 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG); 5397 return CallResult.second; 5398 } 5399 5400 // Otherwise have the target-independent code call memset. 5401 return SDValue(); 5402 } 5403 5404 uint64_t SizeVal = ConstantSize->getZExtValue(); 5405 SDValue InFlag(0, 0); 5406 MVT AVT; 5407 SDValue Count; 5408 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5409 unsigned BytesLeft = 0; 5410 bool TwoRepStos = false; 5411 if (ValC) { 5412 unsigned ValReg; 5413 uint64_t Val = ValC->getZExtValue() & 255; 5414 5415 // If the value is a constant, then we can potentially use larger sets. 5416 switch (Align & 3) { 5417 case 2: // WORD aligned 5418 AVT = MVT::i16; 5419 ValReg = X86::AX; 5420 Val = (Val << 8) | Val; 5421 break; 5422 case 0: // DWORD aligned 5423 AVT = MVT::i32; 5424 ValReg = X86::EAX; 5425 Val = (Val << 8) | Val; 5426 Val = (Val << 16) | Val; 5427 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5428 AVT = MVT::i64; 5429 ValReg = X86::RAX; 5430 Val = (Val << 32) | Val; 5431 } 5432 break; 5433 default: // Byte aligned 5434 AVT = MVT::i8; 5435 ValReg = X86::AL; 5436 Count = DAG.getIntPtrConstant(SizeVal); 5437 break; 5438 } 5439 5440 if (AVT.bitsGT(MVT::i8)) { 5441 unsigned UBytes = AVT.getSizeInBits() / 8; 5442 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5443 BytesLeft = SizeVal % UBytes; 5444 } 5445 5446 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 5447 InFlag); 5448 InFlag = Chain.getValue(1); 5449 } else { 5450 AVT = MVT::i8; 5451 Count = DAG.getIntPtrConstant(SizeVal); 5452 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag); 5453 InFlag = Chain.getValue(1); 5454 } 5455 5456 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 5457 Count, InFlag); 5458 InFlag = Chain.getValue(1); 5459 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 5460 Dst, InFlag); 5461 InFlag = Chain.getValue(1); 5462 5463 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5464 SmallVector<SDValue, 8> Ops; 5465 Ops.push_back(Chain); 5466 Ops.push_back(DAG.getValueType(AVT)); 5467 Ops.push_back(InFlag); 5468 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 5469 5470 if (TwoRepStos) { 5471 InFlag = Chain.getValue(1); 5472 Count = Size; 5473 MVT CVT = Count.getValueType(); 5474 SDValue Left = DAG.getNode(ISD::AND, CVT, Count, 5475 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5476 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 5477 Left, InFlag); 5478 InFlag = Chain.getValue(1); 5479 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5480 Ops.clear(); 5481 Ops.push_back(Chain); 5482 Ops.push_back(DAG.getValueType(MVT::i8)); 5483 Ops.push_back(InFlag); 5484 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 5485 } else if (BytesLeft) { 5486 // Handle the last 1 - 7 bytes. 5487 unsigned Offset = SizeVal - BytesLeft; 5488 MVT AddrVT = Dst.getValueType(); 5489 MVT SizeVT = Size.getValueType(); 5490 5491 Chain = DAG.getMemset(Chain, 5492 DAG.getNode(ISD::ADD, AddrVT, Dst, 5493 DAG.getConstant(Offset, AddrVT)), 5494 Src, 5495 DAG.getConstant(BytesLeft, SizeVT), 5496 Align, DstSV, DstSVOff + Offset); 5497 } 5498 5499 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 5500 return Chain; 5501} 5502 5503SDValue 5504X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, 5505 SDValue Chain, SDValue Dst, SDValue Src, 5506 SDValue Size, unsigned Align, 5507 bool AlwaysInline, 5508 const Value *DstSV, uint64_t DstSVOff, 5509 const Value *SrcSV, uint64_t SrcSVOff) { 5510 // This requires the copy size to be a constant, preferrably 5511 // within a subtarget-specific limit. 5512 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5513 if (!ConstantSize) 5514 return SDValue(); 5515 uint64_t SizeVal = ConstantSize->getZExtValue(); 5516 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 5517 return SDValue(); 5518 5519 /// If not DWORD aligned, call the library. 5520 if ((Align & 3) != 0) 5521 return SDValue(); 5522 5523 // DWORD aligned 5524 MVT AVT = MVT::i32; 5525 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 5526 AVT = MVT::i64; 5527 5528 unsigned UBytes = AVT.getSizeInBits() / 8; 5529 unsigned CountVal = SizeVal / UBytes; 5530 SDValue Count = DAG.getIntPtrConstant(CountVal); 5531 unsigned BytesLeft = SizeVal % UBytes; 5532 5533 SDValue InFlag(0, 0); 5534 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 5535 Count, InFlag); 5536 InFlag = Chain.getValue(1); 5537 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 5538 Dst, InFlag); 5539 InFlag = Chain.getValue(1); 5540 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 5541 Src, InFlag); 5542 InFlag = Chain.getValue(1); 5543 5544 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5545 SmallVector<SDValue, 8> Ops; 5546 Ops.push_back(Chain); 5547 Ops.push_back(DAG.getValueType(AVT)); 5548 Ops.push_back(InFlag); 5549 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 5550 5551 SmallVector<SDValue, 4> Results; 5552 Results.push_back(RepMovs); 5553 if (BytesLeft) { 5554 // Handle the last 1 - 7 bytes. 5555 unsigned Offset = SizeVal - BytesLeft; 5556 MVT DstVT = Dst.getValueType(); 5557 MVT SrcVT = Src.getValueType(); 5558 MVT SizeVT = Size.getValueType(); 5559 Results.push_back(DAG.getMemcpy(Chain, 5560 DAG.getNode(ISD::ADD, DstVT, Dst, 5561 DAG.getConstant(Offset, DstVT)), 5562 DAG.getNode(ISD::ADD, SrcVT, Src, 5563 DAG.getConstant(Offset, SrcVT)), 5564 DAG.getConstant(BytesLeft, SizeVT), 5565 Align, AlwaysInline, 5566 DstSV, DstSVOff + Offset, 5567 SrcSV, SrcSVOff + Offset)); 5568 } 5569 5570 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size()); 5571} 5572 5573SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 5574 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 5575 5576 if (!Subtarget->is64Bit()) { 5577 // vastart just stores the address of the VarArgsFrameIndex slot into the 5578 // memory location argument. 5579 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 5580 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); 5581 } 5582 5583 // __va_list_tag: 5584 // gp_offset (0 - 6 * 8) 5585 // fp_offset (48 - 48 + 8 * 16) 5586 // overflow_arg_area (point to parameters coming in memory). 5587 // reg_save_area 5588 SmallVector<SDValue, 8> MemOps; 5589 SDValue FIN = Op.getOperand(1); 5590 // Store gp_offset 5591 SDValue Store = DAG.getStore(Op.getOperand(0), 5592 DAG.getConstant(VarArgsGPOffset, MVT::i32), 5593 FIN, SV, 0); 5594 MemOps.push_back(Store); 5595 5596 // Store fp_offset 5597 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 5598 Store = DAG.getStore(Op.getOperand(0), 5599 DAG.getConstant(VarArgsFPOffset, MVT::i32), 5600 FIN, SV, 0); 5601 MemOps.push_back(Store); 5602 5603 // Store ptr to overflow_arg_area 5604 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 5605 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 5606 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); 5607 MemOps.push_back(Store); 5608 5609 // Store ptr to reg_save_area. 5610 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); 5611 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 5612 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); 5613 MemOps.push_back(Store); 5614 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 5615} 5616 5617SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 5618 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 5619 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 5620 SDValue Chain = Op.getOperand(0); 5621 SDValue SrcPtr = Op.getOperand(1); 5622 SDValue SrcSV = Op.getOperand(2); 5623 5624 assert(0 && "VAArgInst is not yet implemented for x86-64!"); 5625 abort(); 5626 return SDValue(); 5627} 5628 5629SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 5630 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 5631 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 5632 SDValue Chain = Op.getOperand(0); 5633 SDValue DstPtr = Op.getOperand(1); 5634 SDValue SrcPtr = Op.getOperand(2); 5635 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 5636 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 5637 5638 return DAG.getMemcpy(Chain, DstPtr, SrcPtr, 5639 DAG.getIntPtrConstant(24), 8, false, 5640 DstSV, 0, SrcSV, 0); 5641} 5642 5643SDValue 5644X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 5645 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5646 switch (IntNo) { 5647 default: return SDValue(); // Don't custom lower most intrinsics. 5648 // Comparison intrinsics. 5649 case Intrinsic::x86_sse_comieq_ss: 5650 case Intrinsic::x86_sse_comilt_ss: 5651 case Intrinsic::x86_sse_comile_ss: 5652 case Intrinsic::x86_sse_comigt_ss: 5653 case Intrinsic::x86_sse_comige_ss: 5654 case Intrinsic::x86_sse_comineq_ss: 5655 case Intrinsic::x86_sse_ucomieq_ss: 5656 case Intrinsic::x86_sse_ucomilt_ss: 5657 case Intrinsic::x86_sse_ucomile_ss: 5658 case Intrinsic::x86_sse_ucomigt_ss: 5659 case Intrinsic::x86_sse_ucomige_ss: 5660 case Intrinsic::x86_sse_ucomineq_ss: 5661 case Intrinsic::x86_sse2_comieq_sd: 5662 case Intrinsic::x86_sse2_comilt_sd: 5663 case Intrinsic::x86_sse2_comile_sd: 5664 case Intrinsic::x86_sse2_comigt_sd: 5665 case Intrinsic::x86_sse2_comige_sd: 5666 case Intrinsic::x86_sse2_comineq_sd: 5667 case Intrinsic::x86_sse2_ucomieq_sd: 5668 case Intrinsic::x86_sse2_ucomilt_sd: 5669 case Intrinsic::x86_sse2_ucomile_sd: 5670 case Intrinsic::x86_sse2_ucomigt_sd: 5671 case Intrinsic::x86_sse2_ucomige_sd: 5672 case Intrinsic::x86_sse2_ucomineq_sd: { 5673 unsigned Opc = 0; 5674 ISD::CondCode CC = ISD::SETCC_INVALID; 5675 switch (IntNo) { 5676 default: break; 5677 case Intrinsic::x86_sse_comieq_ss: 5678 case Intrinsic::x86_sse2_comieq_sd: 5679 Opc = X86ISD::COMI; 5680 CC = ISD::SETEQ; 5681 break; 5682 case Intrinsic::x86_sse_comilt_ss: 5683 case Intrinsic::x86_sse2_comilt_sd: 5684 Opc = X86ISD::COMI; 5685 CC = ISD::SETLT; 5686 break; 5687 case Intrinsic::x86_sse_comile_ss: 5688 case Intrinsic::x86_sse2_comile_sd: 5689 Opc = X86ISD::COMI; 5690 CC = ISD::SETLE; 5691 break; 5692 case Intrinsic::x86_sse_comigt_ss: 5693 case Intrinsic::x86_sse2_comigt_sd: 5694 Opc = X86ISD::COMI; 5695 CC = ISD::SETGT; 5696 break; 5697 case Intrinsic::x86_sse_comige_ss: 5698 case Intrinsic::x86_sse2_comige_sd: 5699 Opc = X86ISD::COMI; 5700 CC = ISD::SETGE; 5701 break; 5702 case Intrinsic::x86_sse_comineq_ss: 5703 case Intrinsic::x86_sse2_comineq_sd: 5704 Opc = X86ISD::COMI; 5705 CC = ISD::SETNE; 5706 break; 5707 case Intrinsic::x86_sse_ucomieq_ss: 5708 case Intrinsic::x86_sse2_ucomieq_sd: 5709 Opc = X86ISD::UCOMI; 5710 CC = ISD::SETEQ; 5711 break; 5712 case Intrinsic::x86_sse_ucomilt_ss: 5713 case Intrinsic::x86_sse2_ucomilt_sd: 5714 Opc = X86ISD::UCOMI; 5715 CC = ISD::SETLT; 5716 break; 5717 case Intrinsic::x86_sse_ucomile_ss: 5718 case Intrinsic::x86_sse2_ucomile_sd: 5719 Opc = X86ISD::UCOMI; 5720 CC = ISD::SETLE; 5721 break; 5722 case Intrinsic::x86_sse_ucomigt_ss: 5723 case Intrinsic::x86_sse2_ucomigt_sd: 5724 Opc = X86ISD::UCOMI; 5725 CC = ISD::SETGT; 5726 break; 5727 case Intrinsic::x86_sse_ucomige_ss: 5728 case Intrinsic::x86_sse2_ucomige_sd: 5729 Opc = X86ISD::UCOMI; 5730 CC = ISD::SETGE; 5731 break; 5732 case Intrinsic::x86_sse_ucomineq_ss: 5733 case Intrinsic::x86_sse2_ucomineq_sd: 5734 Opc = X86ISD::UCOMI; 5735 CC = ISD::SETNE; 5736 break; 5737 } 5738 5739 SDValue LHS = Op.getOperand(1); 5740 SDValue RHS = Op.getOperand(2); 5741 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 5742 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); 5743 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, 5744 DAG.getConstant(X86CC, MVT::i8), Cond); 5745 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC); 5746 } 5747 5748 // Fix vector shift instructions where the last operand is a non-immediate 5749 // i32 value. 5750 case Intrinsic::x86_sse2_pslli_w: 5751 case Intrinsic::x86_sse2_pslli_d: 5752 case Intrinsic::x86_sse2_pslli_q: 5753 case Intrinsic::x86_sse2_psrli_w: 5754 case Intrinsic::x86_sse2_psrli_d: 5755 case Intrinsic::x86_sse2_psrli_q: 5756 case Intrinsic::x86_sse2_psrai_w: 5757 case Intrinsic::x86_sse2_psrai_d: 5758 case Intrinsic::x86_mmx_pslli_w: 5759 case Intrinsic::x86_mmx_pslli_d: 5760 case Intrinsic::x86_mmx_pslli_q: 5761 case Intrinsic::x86_mmx_psrli_w: 5762 case Intrinsic::x86_mmx_psrli_d: 5763 case Intrinsic::x86_mmx_psrli_q: 5764 case Intrinsic::x86_mmx_psrai_w: 5765 case Intrinsic::x86_mmx_psrai_d: { 5766 SDValue ShAmt = Op.getOperand(2); 5767 if (isa<ConstantSDNode>(ShAmt)) 5768 return SDValue(); 5769 5770 unsigned NewIntNo = 0; 5771 MVT ShAmtVT = MVT::v4i32; 5772 switch (IntNo) { 5773 case Intrinsic::x86_sse2_pslli_w: 5774 NewIntNo = Intrinsic::x86_sse2_psll_w; 5775 break; 5776 case Intrinsic::x86_sse2_pslli_d: 5777 NewIntNo = Intrinsic::x86_sse2_psll_d; 5778 break; 5779 case Intrinsic::x86_sse2_pslli_q: 5780 NewIntNo = Intrinsic::x86_sse2_psll_q; 5781 break; 5782 case Intrinsic::x86_sse2_psrli_w: 5783 NewIntNo = Intrinsic::x86_sse2_psrl_w; 5784 break; 5785 case Intrinsic::x86_sse2_psrli_d: 5786 NewIntNo = Intrinsic::x86_sse2_psrl_d; 5787 break; 5788 case Intrinsic::x86_sse2_psrli_q: 5789 NewIntNo = Intrinsic::x86_sse2_psrl_q; 5790 break; 5791 case Intrinsic::x86_sse2_psrai_w: 5792 NewIntNo = Intrinsic::x86_sse2_psra_w; 5793 break; 5794 case Intrinsic::x86_sse2_psrai_d: 5795 NewIntNo = Intrinsic::x86_sse2_psra_d; 5796 break; 5797 default: { 5798 ShAmtVT = MVT::v2i32; 5799 switch (IntNo) { 5800 case Intrinsic::x86_mmx_pslli_w: 5801 NewIntNo = Intrinsic::x86_mmx_psll_w; 5802 break; 5803 case Intrinsic::x86_mmx_pslli_d: 5804 NewIntNo = Intrinsic::x86_mmx_psll_d; 5805 break; 5806 case Intrinsic::x86_mmx_pslli_q: 5807 NewIntNo = Intrinsic::x86_mmx_psll_q; 5808 break; 5809 case Intrinsic::x86_mmx_psrli_w: 5810 NewIntNo = Intrinsic::x86_mmx_psrl_w; 5811 break; 5812 case Intrinsic::x86_mmx_psrli_d: 5813 NewIntNo = Intrinsic::x86_mmx_psrl_d; 5814 break; 5815 case Intrinsic::x86_mmx_psrli_q: 5816 NewIntNo = Intrinsic::x86_mmx_psrl_q; 5817 break; 5818 case Intrinsic::x86_mmx_psrai_w: 5819 NewIntNo = Intrinsic::x86_mmx_psra_w; 5820 break; 5821 case Intrinsic::x86_mmx_psrai_d: 5822 NewIntNo = Intrinsic::x86_mmx_psra_d; 5823 break; 5824 default: abort(); // Can't reach here. 5825 } 5826 break; 5827 } 5828 } 5829 MVT VT = Op.getValueType(); 5830 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT, 5831 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt)); 5832 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 5833 DAG.getConstant(NewIntNo, MVT::i32), 5834 Op.getOperand(1), ShAmt); 5835 } 5836 } 5837} 5838 5839SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 5840 // Depths > 0 not supported yet! 5841 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 5842 return SDValue(); 5843 5844 // Just load the return address 5845 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 5846 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 5847} 5848 5849SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 5850 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5851 MFI->setFrameAddressIsTaken(true); 5852 MVT VT = Op.getValueType(); 5853 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5854 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 5855 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT); 5856 while (Depth--) 5857 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0); 5858 return FrameAddr; 5859} 5860 5861SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 5862 SelectionDAG &DAG) { 5863 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 5864} 5865 5866SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 5867{ 5868 MachineFunction &MF = DAG.getMachineFunction(); 5869 SDValue Chain = Op.getOperand(0); 5870 SDValue Offset = Op.getOperand(1); 5871 SDValue Handler = Op.getOperand(2); 5872 5873 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 5874 getPointerTy()); 5875 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 5876 5877 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, 5878 DAG.getIntPtrConstant(-TD->getPointerSize())); 5879 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); 5880 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); 5881 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr); 5882 MF.getRegInfo().addLiveOut(StoreAddrReg); 5883 5884 return DAG.getNode(X86ISD::EH_RETURN, 5885 MVT::Other, 5886 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 5887} 5888 5889SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 5890 SelectionDAG &DAG) { 5891 SDValue Root = Op.getOperand(0); 5892 SDValue Trmp = Op.getOperand(1); // trampoline 5893 SDValue FPtr = Op.getOperand(2); // nested function 5894 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 5895 5896 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 5897 5898 const X86InstrInfo *TII = 5899 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 5900 5901 if (Subtarget->is64Bit()) { 5902 SDValue OutChains[6]; 5903 5904 // Large code-model. 5905 5906 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 5907 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 5908 5909 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 5910 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 5911 5912 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 5913 5914 // Load the pointer to the nested function into R11. 5915 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 5916 SDValue Addr = Trmp; 5917 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5918 TrmpAddr, 0); 5919 5920 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); 5921 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); 5922 5923 // Load the 'nest' parameter value into R10. 5924 // R10 is specified in X86CallingConv.td 5925 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 5926 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); 5927 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5928 TrmpAddr, 10); 5929 5930 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); 5931 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); 5932 5933 // Jump to the nested function. 5934 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 5935 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); 5936 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5937 TrmpAddr, 20); 5938 5939 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 5940 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); 5941 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, 5942 TrmpAddr, 22); 5943 5944 SDValue Ops[] = 5945 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; 5946 return DAG.getMergeValues(Ops, 2); 5947 } else { 5948 const Function *Func = 5949 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 5950 unsigned CC = Func->getCallingConv(); 5951 unsigned NestReg; 5952 5953 switch (CC) { 5954 default: 5955 assert(0 && "Unsupported calling convention"); 5956 case CallingConv::C: 5957 case CallingConv::X86_StdCall: { 5958 // Pass 'nest' parameter in ECX. 5959 // Must be kept in sync with X86CallingConv.td 5960 NestReg = X86::ECX; 5961 5962 // Check that ECX wasn't needed by an 'inreg' parameter. 5963 const FunctionType *FTy = Func->getFunctionType(); 5964 const AttrListPtr &Attrs = Func->getAttributes(); 5965 5966 if (!Attrs.isEmpty() && !Func->isVarArg()) { 5967 unsigned InRegCount = 0; 5968 unsigned Idx = 1; 5969 5970 for (FunctionType::param_iterator I = FTy->param_begin(), 5971 E = FTy->param_end(); I != E; ++I, ++Idx) 5972 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 5973 // FIXME: should only count parameters that are lowered to integers. 5974 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 5975 5976 if (InRegCount > 2) { 5977 cerr << "Nest register in use - reduce number of inreg parameters!\n"; 5978 abort(); 5979 } 5980 } 5981 break; 5982 } 5983 case CallingConv::X86_FastCall: 5984 case CallingConv::Fast: 5985 // Pass 'nest' parameter in EAX. 5986 // Must be kept in sync with X86CallingConv.td 5987 NestReg = X86::EAX; 5988 break; 5989 } 5990 5991 SDValue OutChains[4]; 5992 SDValue Addr, Disp; 5993 5994 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); 5995 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); 5996 5997 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 5998 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 5999 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 6000 Trmp, TrmpAddr, 0); 6001 6002 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); 6003 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); 6004 6005 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 6006 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); 6007 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, 6008 TrmpAddr, 5, false, 1); 6009 6010 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); 6011 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); 6012 6013 SDValue Ops[] = 6014 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; 6015 return DAG.getMergeValues(Ops, 2); 6016 } 6017} 6018 6019SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 6020 /* 6021 The rounding mode is in bits 11:10 of FPSR, and has the following 6022 settings: 6023 00 Round to nearest 6024 01 Round to -inf 6025 10 Round to +inf 6026 11 Round to 0 6027 6028 FLT_ROUNDS, on the other hand, expects the following: 6029 -1 Undefined 6030 0 Round to 0 6031 1 Round to nearest 6032 2 Round to +inf 6033 3 Round to -inf 6034 6035 To perform the conversion, we do: 6036 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 6037 */ 6038 6039 MachineFunction &MF = DAG.getMachineFunction(); 6040 const TargetMachine &TM = MF.getTarget(); 6041 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 6042 unsigned StackAlignment = TFI.getStackAlignment(); 6043 MVT VT = Op.getValueType(); 6044 6045 // Save FP Control Word to stack slot 6046 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 6047 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6048 6049 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, 6050 DAG.getEntryNode(), StackSlot); 6051 6052 // Load FP Control Word from stack slot 6053 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); 6054 6055 // Transform as necessary 6056 SDValue CWD1 = 6057 DAG.getNode(ISD::SRL, MVT::i16, 6058 DAG.getNode(ISD::AND, MVT::i16, 6059 CWD, DAG.getConstant(0x800, MVT::i16)), 6060 DAG.getConstant(11, MVT::i8)); 6061 SDValue CWD2 = 6062 DAG.getNode(ISD::SRL, MVT::i16, 6063 DAG.getNode(ISD::AND, MVT::i16, 6064 CWD, DAG.getConstant(0x400, MVT::i16)), 6065 DAG.getConstant(9, MVT::i8)); 6066 6067 SDValue RetVal = 6068 DAG.getNode(ISD::AND, MVT::i16, 6069 DAG.getNode(ISD::ADD, MVT::i16, 6070 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), 6071 DAG.getConstant(1, MVT::i16)), 6072 DAG.getConstant(3, MVT::i16)); 6073 6074 6075 return DAG.getNode((VT.getSizeInBits() < 16 ? 6076 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 6077} 6078 6079SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 6080 MVT VT = Op.getValueType(); 6081 MVT OpVT = VT; 6082 unsigned NumBits = VT.getSizeInBits(); 6083 6084 Op = Op.getOperand(0); 6085 if (VT == MVT::i8) { 6086 // Zero extend to i32 since there is not an i8 bsr. 6087 OpVT = MVT::i32; 6088 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 6089 } 6090 6091 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 6092 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6093 Op = DAG.getNode(X86ISD::BSR, VTs, Op); 6094 6095 // If src is zero (i.e. bsr sets ZF), returns NumBits. 6096 SmallVector<SDValue, 4> Ops; 6097 Ops.push_back(Op); 6098 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 6099 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6100 Ops.push_back(Op.getValue(1)); 6101 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 6102 6103 // Finally xor with NumBits-1. 6104 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 6105 6106 if (VT == MVT::i8) 6107 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 6108 return Op; 6109} 6110 6111SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 6112 MVT VT = Op.getValueType(); 6113 MVT OpVT = VT; 6114 unsigned NumBits = VT.getSizeInBits(); 6115 6116 Op = Op.getOperand(0); 6117 if (VT == MVT::i8) { 6118 OpVT = MVT::i32; 6119 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 6120 } 6121 6122 // Issue a bsf (scan bits forward) which also sets EFLAGS. 6123 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6124 Op = DAG.getNode(X86ISD::BSF, VTs, Op); 6125 6126 // If src is zero (i.e. bsf sets ZF), returns NumBits. 6127 SmallVector<SDValue, 4> Ops; 6128 Ops.push_back(Op); 6129 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 6130 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6131 Ops.push_back(Op.getValue(1)); 6132 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 6133 6134 if (VT == MVT::i8) 6135 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 6136 return Op; 6137} 6138 6139SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 6140 MVT VT = Op.getValueType(); 6141 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 6142 6143 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 6144 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 6145 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 6146 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 6147 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 6148 // 6149 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 6150 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 6151 // return AloBlo + AloBhi + AhiBlo; 6152 6153 SDValue A = Op.getOperand(0); 6154 SDValue B = Op.getOperand(1); 6155 6156 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6157 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6158 A, DAG.getConstant(32, MVT::i32)); 6159 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6160 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6161 B, DAG.getConstant(32, MVT::i32)); 6162 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6163 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6164 A, B); 6165 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6166 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6167 A, Bhi); 6168 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6169 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6170 Ahi, B); 6171 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6172 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6173 AloBhi, DAG.getConstant(32, MVT::i32)); 6174 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 6175 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6176 AhiBlo, DAG.getConstant(32, MVT::i32)); 6177 SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi); 6178 Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo); 6179 return Res; 6180} 6181 6182 6183SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 6184 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 6185 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 6186 // looks for this combo and may remove the "setcc" instruction if the "setcc" 6187 // has only one use. 6188 SDNode *N = Op.getNode(); 6189 SDValue LHS = N->getOperand(0); 6190 SDValue RHS = N->getOperand(1); 6191 unsigned BaseOp = 0; 6192 unsigned Cond = 0; 6193 6194 switch (Op.getOpcode()) { 6195 default: assert(0 && "Unknown ovf instruction!"); 6196 case ISD::SADDO: 6197 BaseOp = X86ISD::ADD; 6198 Cond = X86::COND_O; 6199 break; 6200 case ISD::UADDO: 6201 BaseOp = X86ISD::ADD; 6202 Cond = X86::COND_C; 6203 break; 6204 case ISD::SSUBO: 6205 BaseOp = X86ISD::SUB; 6206 Cond = X86::COND_O; 6207 break; 6208 case ISD::USUBO: 6209 BaseOp = X86ISD::SUB; 6210 Cond = X86::COND_C; 6211 break; 6212 case ISD::SMULO: 6213 BaseOp = X86ISD::SMUL; 6214 Cond = X86::COND_O; 6215 break; 6216 case ISD::UMULO: 6217 BaseOp = X86ISD::UMUL; 6218 Cond = X86::COND_C; 6219 break; 6220 } 6221 6222 // Also sets EFLAGS. 6223 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 6224 SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS); 6225 6226 SDValue SetCC = 6227 DAG.getNode(X86ISD::SETCC, N->getValueType(1), 6228 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 6229 6230 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 6231 return Sum; 6232} 6233 6234SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 6235 MVT T = Op.getValueType(); 6236 unsigned Reg = 0; 6237 unsigned size = 0; 6238 switch(T.getSimpleVT()) { 6239 default: 6240 assert(false && "Invalid value type!"); 6241 case MVT::i8: Reg = X86::AL; size = 1; break; 6242 case MVT::i16: Reg = X86::AX; size = 2; break; 6243 case MVT::i32: Reg = X86::EAX; size = 4; break; 6244 case MVT::i64: 6245 assert(Subtarget->is64Bit() && "Node not type legal!"); 6246 Reg = X86::RAX; size = 8; 6247 break; 6248 } 6249 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, 6250 Op.getOperand(2), SDValue()); 6251 SDValue Ops[] = { cpIn.getValue(0), 6252 Op.getOperand(1), 6253 Op.getOperand(3), 6254 DAG.getTargetConstant(size, MVT::i8), 6255 cpIn.getValue(1) }; 6256 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6257 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); 6258 SDValue cpOut = 6259 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); 6260 return cpOut; 6261} 6262 6263SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 6264 SelectionDAG &DAG) { 6265 assert(Subtarget->is64Bit() && "Result not type legalized?"); 6266 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6267 SDValue TheChain = Op.getOperand(0); 6268 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); 6269 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); 6270 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64, 6271 rax.getValue(2)); 6272 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, 6273 DAG.getConstant(32, MVT::i8)); 6274 SDValue Ops[] = { 6275 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), 6276 rdx.getValue(1) 6277 }; 6278 return DAG.getMergeValues(Ops, 2); 6279} 6280 6281SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 6282 SDNode *Node = Op.getNode(); 6283 MVT T = Node->getValueType(0); 6284 SDValue negOp = DAG.getNode(ISD::SUB, T, 6285 DAG.getConstant(0, T), Node->getOperand(2)); 6286 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, 6287 cast<AtomicSDNode>(Node)->getMemoryVT(), 6288 Node->getOperand(0), 6289 Node->getOperand(1), negOp, 6290 cast<AtomicSDNode>(Node)->getSrcValue(), 6291 cast<AtomicSDNode>(Node)->getAlignment()); 6292} 6293 6294/// LowerOperation - Provide custom lowering hooks for some operations. 6295/// 6296SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 6297 switch (Op.getOpcode()) { 6298 default: assert(0 && "Should not custom lower this!"); 6299 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 6300 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 6301 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 6302 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 6303 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 6304 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 6305 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 6306 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 6307 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 6308 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 6309 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 6310 case ISD::SHL_PARTS: 6311 case ISD::SRA_PARTS: 6312 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 6313 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 6314 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 6315 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 6316 case ISD::FABS: return LowerFABS(Op, DAG); 6317 case ISD::FNEG: return LowerFNEG(Op, DAG); 6318 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 6319 case ISD::SETCC: return LowerSETCC(Op, DAG); 6320 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 6321 case ISD::SELECT: return LowerSELECT(Op, DAG); 6322 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 6323 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 6324 case ISD::CALL: return LowerCALL(Op, DAG); 6325 case ISD::RET: return LowerRET(Op, DAG); 6326 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 6327 case ISD::VASTART: return LowerVASTART(Op, DAG); 6328 case ISD::VAARG: return LowerVAARG(Op, DAG); 6329 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 6330 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 6331 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 6332 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 6333 case ISD::FRAME_TO_ARGS_OFFSET: 6334 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 6335 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 6336 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 6337 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 6338 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 6339 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 6340 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 6341 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 6342 case ISD::SADDO: 6343 case ISD::UADDO: 6344 case ISD::SSUBO: 6345 case ISD::USUBO: 6346 case ISD::SMULO: 6347 case ISD::UMULO: return LowerXALUO(Op, DAG); 6348 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 6349 } 6350} 6351 6352void X86TargetLowering:: 6353ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 6354 SelectionDAG &DAG, unsigned NewOp) { 6355 MVT T = Node->getValueType(0); 6356 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 6357 6358 SDValue Chain = Node->getOperand(0); 6359 SDValue In1 = Node->getOperand(1); 6360 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 6361 Node->getOperand(2), DAG.getIntPtrConstant(0)); 6362 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 6363 Node->getOperand(2), DAG.getIntPtrConstant(1)); 6364 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't 6365 // have a MemOperand. Pass the info through as a normal operand. 6366 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); 6367 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; 6368 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 6369 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5); 6370 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 6371 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2)); 6372 Results.push_back(Result.getValue(2)); 6373} 6374 6375/// ReplaceNodeResults - Replace a node with an illegal result type 6376/// with a new node built out of custom code. 6377void X86TargetLowering::ReplaceNodeResults(SDNode *N, 6378 SmallVectorImpl<SDValue>&Results, 6379 SelectionDAG &DAG) { 6380 switch (N->getOpcode()) { 6381 default: 6382 assert(false && "Do not know how to custom type legalize this operation!"); 6383 return; 6384 case ISD::FP_TO_SINT: { 6385 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG); 6386 SDValue FIST = Vals.first, StackSlot = Vals.second; 6387 if (FIST.getNode() != 0) { 6388 MVT VT = N->getValueType(0); 6389 // Return a load from the stack slot. 6390 Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0)); 6391 } 6392 return; 6393 } 6394 case ISD::READCYCLECOUNTER: { 6395 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6396 SDValue TheChain = N->getOperand(0); 6397 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); 6398 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); 6399 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32, 6400 eax.getValue(2)); 6401 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 6402 SDValue Ops[] = { eax, edx }; 6403 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2)); 6404 Results.push_back(edx.getValue(1)); 6405 return; 6406 } 6407 case ISD::ATOMIC_CMP_SWAP: { 6408 MVT T = N->getValueType(0); 6409 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 6410 SDValue cpInL, cpInH; 6411 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2), 6412 DAG.getConstant(0, MVT::i32)); 6413 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2), 6414 DAG.getConstant(1, MVT::i32)); 6415 cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue()); 6416 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH, 6417 cpInL.getValue(1)); 6418 SDValue swapInL, swapInH; 6419 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3), 6420 DAG.getConstant(0, MVT::i32)); 6421 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3), 6422 DAG.getConstant(1, MVT::i32)); 6423 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL, 6424 cpInH.getValue(1)); 6425 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH, 6426 swapInL.getValue(1)); 6427 SDValue Ops[] = { swapInH.getValue(0), 6428 N->getOperand(1), 6429 swapInH.getValue(1) }; 6430 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6431 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); 6432 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, 6433 Result.getValue(1)); 6434 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, 6435 cpOutL.getValue(2)); 6436 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 6437 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2)); 6438 Results.push_back(cpOutH.getValue(1)); 6439 return; 6440 } 6441 case ISD::ATOMIC_LOAD_ADD: 6442 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 6443 return; 6444 case ISD::ATOMIC_LOAD_AND: 6445 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 6446 return; 6447 case ISD::ATOMIC_LOAD_NAND: 6448 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 6449 return; 6450 case ISD::ATOMIC_LOAD_OR: 6451 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 6452 return; 6453 case ISD::ATOMIC_LOAD_SUB: 6454 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 6455 return; 6456 case ISD::ATOMIC_LOAD_XOR: 6457 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 6458 return; 6459 case ISD::ATOMIC_SWAP: 6460 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 6461 return; 6462 } 6463} 6464 6465const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 6466 switch (Opcode) { 6467 default: return NULL; 6468 case X86ISD::BSF: return "X86ISD::BSF"; 6469 case X86ISD::BSR: return "X86ISD::BSR"; 6470 case X86ISD::SHLD: return "X86ISD::SHLD"; 6471 case X86ISD::SHRD: return "X86ISD::SHRD"; 6472 case X86ISD::FAND: return "X86ISD::FAND"; 6473 case X86ISD::FOR: return "X86ISD::FOR"; 6474 case X86ISD::FXOR: return "X86ISD::FXOR"; 6475 case X86ISD::FSRL: return "X86ISD::FSRL"; 6476 case X86ISD::FILD: return "X86ISD::FILD"; 6477 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 6478 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 6479 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 6480 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 6481 case X86ISD::FLD: return "X86ISD::FLD"; 6482 case X86ISD::FST: return "X86ISD::FST"; 6483 case X86ISD::CALL: return "X86ISD::CALL"; 6484 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 6485 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 6486 case X86ISD::BT: return "X86ISD::BT"; 6487 case X86ISD::CMP: return "X86ISD::CMP"; 6488 case X86ISD::COMI: return "X86ISD::COMI"; 6489 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 6490 case X86ISD::SETCC: return "X86ISD::SETCC"; 6491 case X86ISD::CMOV: return "X86ISD::CMOV"; 6492 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 6493 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 6494 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 6495 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 6496 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 6497 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 6498 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 6499 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 6500 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 6501 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 6502 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 6503 case X86ISD::FMAX: return "X86ISD::FMAX"; 6504 case X86ISD::FMIN: return "X86ISD::FMIN"; 6505 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 6506 case X86ISD::FRCP: return "X86ISD::FRCP"; 6507 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 6508 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; 6509 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 6510 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 6511 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 6512 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 6513 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 6514 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 6515 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 6516 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 6517 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 6518 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 6519 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 6520 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 6521 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 6522 case X86ISD::VSHL: return "X86ISD::VSHL"; 6523 case X86ISD::VSRL: return "X86ISD::VSRL"; 6524 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 6525 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 6526 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 6527 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 6528 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 6529 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 6530 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 6531 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 6532 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 6533 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 6534 case X86ISD::ADD: return "X86ISD::ADD"; 6535 case X86ISD::SUB: return "X86ISD::SUB"; 6536 case X86ISD::SMUL: return "X86ISD::SMUL"; 6537 case X86ISD::UMUL: return "X86ISD::UMUL"; 6538 } 6539} 6540 6541// isLegalAddressingMode - Return true if the addressing mode represented 6542// by AM is legal for this target, for a load/store of the specified type. 6543bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 6544 const Type *Ty) const { 6545 // X86 supports extremely general addressing modes. 6546 6547 // X86 allows a sign-extended 32-bit immediate field as a displacement. 6548 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) 6549 return false; 6550 6551 if (AM.BaseGV) { 6552 // We can only fold this if we don't need an extra load. 6553 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) 6554 return false; 6555 // If BaseGV requires a register, we cannot also have a BaseReg. 6556 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) && 6557 AM.HasBaseReg) 6558 return false; 6559 6560 // X86-64 only supports addr of globals in small code model. 6561 if (Subtarget->is64Bit()) { 6562 if (getTargetMachine().getCodeModel() != CodeModel::Small) 6563 return false; 6564 // If lower 4G is not available, then we must use rip-relative addressing. 6565 if (AM.BaseOffs || AM.Scale > 1) 6566 return false; 6567 } 6568 } 6569 6570 switch (AM.Scale) { 6571 case 0: 6572 case 1: 6573 case 2: 6574 case 4: 6575 case 8: 6576 // These scales always work. 6577 break; 6578 case 3: 6579 case 5: 6580 case 9: 6581 // These scales are formed with basereg+scalereg. Only accept if there is 6582 // no basereg yet. 6583 if (AM.HasBaseReg) 6584 return false; 6585 break; 6586 default: // Other stuff never works. 6587 return false; 6588 } 6589 6590 return true; 6591} 6592 6593 6594bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 6595 if (!Ty1->isInteger() || !Ty2->isInteger()) 6596 return false; 6597 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6598 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6599 if (NumBits1 <= NumBits2) 6600 return false; 6601 return Subtarget->is64Bit() || NumBits1 < 64; 6602} 6603 6604bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { 6605 if (!VT1.isInteger() || !VT2.isInteger()) 6606 return false; 6607 unsigned NumBits1 = VT1.getSizeInBits(); 6608 unsigned NumBits2 = VT2.getSizeInBits(); 6609 if (NumBits1 <= NumBits2) 6610 return false; 6611 return Subtarget->is64Bit() || NumBits1 < 64; 6612} 6613 6614/// isShuffleMaskLegal - Targets can use this to indicate that they only 6615/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 6616/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 6617/// are assumed to be legal. 6618bool 6619X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const { 6620 // Only do shuffles on 128-bit vector types for now. 6621 if (VT.getSizeInBits() == 64) return false; 6622 return (Mask.getNode()->getNumOperands() <= 4 || 6623 isIdentityMask(Mask.getNode()) || 6624 isIdentityMask(Mask.getNode(), true) || 6625 isSplatMask(Mask.getNode()) || 6626 isPSHUFHW_PSHUFLWMask(Mask.getNode()) || 6627 X86::isUNPCKLMask(Mask.getNode()) || 6628 X86::isUNPCKHMask(Mask.getNode()) || 6629 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) || 6630 X86::isUNPCKH_v_undef_Mask(Mask.getNode())); 6631} 6632 6633bool 6634X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 6635 MVT EVT, SelectionDAG &DAG) const { 6636 unsigned NumElts = BVOps.size(); 6637 // Only do shuffles on 128-bit vector types for now. 6638 if (EVT.getSizeInBits() * NumElts == 64) return false; 6639 if (NumElts == 2) return true; 6640 if (NumElts == 4) { 6641 return (isMOVLMask(&BVOps[0], 4) || 6642 isCommutedMOVL(&BVOps[0], 4, true) || 6643 isSHUFPMask(&BVOps[0], 4) || 6644 isCommutedSHUFP(&BVOps[0], 4)); 6645 } 6646 return false; 6647} 6648 6649//===----------------------------------------------------------------------===// 6650// X86 Scheduler Hooks 6651//===----------------------------------------------------------------------===// 6652 6653// private utility function 6654MachineBasicBlock * 6655X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 6656 MachineBasicBlock *MBB, 6657 unsigned regOpc, 6658 unsigned immOpc, 6659 unsigned LoadOpc, 6660 unsigned CXchgOpc, 6661 unsigned copyOpc, 6662 unsigned notOpc, 6663 unsigned EAXreg, 6664 TargetRegisterClass *RC, 6665 bool invSrc) { 6666 // For the atomic bitwise operator, we generate 6667 // thisMBB: 6668 // newMBB: 6669 // ld t1 = [bitinstr.addr] 6670 // op t2 = t1, [bitinstr.val] 6671 // mov EAX = t1 6672 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 6673 // bz newMBB 6674 // fallthrough -->nextMBB 6675 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6676 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6677 MachineFunction::iterator MBBIter = MBB; 6678 ++MBBIter; 6679 6680 /// First build the CFG 6681 MachineFunction *F = MBB->getParent(); 6682 MachineBasicBlock *thisMBB = MBB; 6683 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6684 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6685 F->insert(MBBIter, newMBB); 6686 F->insert(MBBIter, nextMBB); 6687 6688 // Move all successors to thisMBB to nextMBB 6689 nextMBB->transferSuccessors(thisMBB); 6690 6691 // Update thisMBB to fall through to newMBB 6692 thisMBB->addSuccessor(newMBB); 6693 6694 // newMBB jumps to itself and fall through to nextMBB 6695 newMBB->addSuccessor(nextMBB); 6696 newMBB->addSuccessor(newMBB); 6697 6698 // Insert instructions into newMBB based on incoming instruction 6699 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands"); 6700 MachineOperand& destOper = bInstr->getOperand(0); 6701 MachineOperand* argOpers[6]; 6702 int numArgs = bInstr->getNumOperands() - 1; 6703 for (int i=0; i < numArgs; ++i) 6704 argOpers[i] = &bInstr->getOperand(i+1); 6705 6706 // x86 address has 4 operands: base, index, scale, and displacement 6707 int lastAddrIndx = 3; // [0,3] 6708 int valArgIndx = 4; 6709 6710 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 6711 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1); 6712 for (int i=0; i <= lastAddrIndx; ++i) 6713 (*MIB).addOperand(*argOpers[i]); 6714 6715 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 6716 if (invSrc) { 6717 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1); 6718 } 6719 else 6720 tt = t1; 6721 6722 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 6723 assert((argOpers[valArgIndx]->isReg() || 6724 argOpers[valArgIndx]->isImm()) && 6725 "invalid operand"); 6726 if (argOpers[valArgIndx]->isReg()) 6727 MIB = BuildMI(newMBB, TII->get(regOpc), t2); 6728 else 6729 MIB = BuildMI(newMBB, TII->get(immOpc), t2); 6730 MIB.addReg(tt); 6731 (*MIB).addOperand(*argOpers[valArgIndx]); 6732 6733 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg); 6734 MIB.addReg(t1); 6735 6736 MIB = BuildMI(newMBB, TII->get(CXchgOpc)); 6737 for (int i=0; i <= lastAddrIndx; ++i) 6738 (*MIB).addOperand(*argOpers[i]); 6739 MIB.addReg(t2); 6740 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 6741 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 6742 6743 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg()); 6744 MIB.addReg(EAXreg); 6745 6746 // insert branch 6747 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 6748 6749 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 6750 return nextMBB; 6751} 6752 6753// private utility function: 64 bit atomics on 32 bit host. 6754MachineBasicBlock * 6755X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 6756 MachineBasicBlock *MBB, 6757 unsigned regOpcL, 6758 unsigned regOpcH, 6759 unsigned immOpcL, 6760 unsigned immOpcH, 6761 bool invSrc) { 6762 // For the atomic bitwise operator, we generate 6763 // thisMBB (instructions are in pairs, except cmpxchg8b) 6764 // ld t1,t2 = [bitinstr.addr] 6765 // newMBB: 6766 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 6767 // op t5, t6 <- out1, out2, [bitinstr.val] 6768 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 6769 // mov ECX, EBX <- t5, t6 6770 // mov EAX, EDX <- t1, t2 6771 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 6772 // mov t3, t4 <- EAX, EDX 6773 // bz newMBB 6774 // result in out1, out2 6775 // fallthrough -->nextMBB 6776 6777 const TargetRegisterClass *RC = X86::GR32RegisterClass; 6778 const unsigned LoadOpc = X86::MOV32rm; 6779 const unsigned copyOpc = X86::MOV32rr; 6780 const unsigned NotOpc = X86::NOT32r; 6781 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6782 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6783 MachineFunction::iterator MBBIter = MBB; 6784 ++MBBIter; 6785 6786 /// First build the CFG 6787 MachineFunction *F = MBB->getParent(); 6788 MachineBasicBlock *thisMBB = MBB; 6789 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6790 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6791 F->insert(MBBIter, newMBB); 6792 F->insert(MBBIter, nextMBB); 6793 6794 // Move all successors to thisMBB to nextMBB 6795 nextMBB->transferSuccessors(thisMBB); 6796 6797 // Update thisMBB to fall through to newMBB 6798 thisMBB->addSuccessor(newMBB); 6799 6800 // newMBB jumps to itself and fall through to nextMBB 6801 newMBB->addSuccessor(nextMBB); 6802 newMBB->addSuccessor(newMBB); 6803 6804 // Insert instructions into newMBB based on incoming instruction 6805 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 6806 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands"); 6807 MachineOperand& dest1Oper = bInstr->getOperand(0); 6808 MachineOperand& dest2Oper = bInstr->getOperand(1); 6809 MachineOperand* argOpers[6]; 6810 for (int i=0; i < 6; ++i) 6811 argOpers[i] = &bInstr->getOperand(i+2); 6812 6813 // x86 address has 4 operands: base, index, scale, and displacement 6814 int lastAddrIndx = 3; // [0,3] 6815 6816 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 6817 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1); 6818 for (int i=0; i <= lastAddrIndx; ++i) 6819 (*MIB).addOperand(*argOpers[i]); 6820 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 6821 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2); 6822 // add 4 to displacement. 6823 for (int i=0; i <= lastAddrIndx-1; ++i) 6824 (*MIB).addOperand(*argOpers[i]); 6825 MachineOperand newOp3 = *(argOpers[3]); 6826 if (newOp3.isImm()) 6827 newOp3.setImm(newOp3.getImm()+4); 6828 else 6829 newOp3.setOffset(newOp3.getOffset()+4); 6830 (*MIB).addOperand(newOp3); 6831 6832 // t3/4 are defined later, at the bottom of the loop 6833 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 6834 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 6835 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg()) 6836 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 6837 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg()) 6838 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 6839 6840 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); 6841 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); 6842 if (invSrc) { 6843 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1); 6844 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2); 6845 } else { 6846 tt1 = t1; 6847 tt2 = t2; 6848 } 6849 6850 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) && 6851 "invalid operand"); 6852 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 6853 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 6854 if (argOpers[4]->isReg()) 6855 MIB = BuildMI(newMBB, TII->get(regOpcL), t5); 6856 else 6857 MIB = BuildMI(newMBB, TII->get(immOpcL), t5); 6858 if (regOpcL != X86::MOV32rr) 6859 MIB.addReg(tt1); 6860 (*MIB).addOperand(*argOpers[4]); 6861 assert(argOpers[5]->isReg() == argOpers[4]->isReg()); 6862 assert(argOpers[5]->isImm() == argOpers[4]->isImm()); 6863 if (argOpers[5]->isReg()) 6864 MIB = BuildMI(newMBB, TII->get(regOpcH), t6); 6865 else 6866 MIB = BuildMI(newMBB, TII->get(immOpcH), t6); 6867 if (regOpcH != X86::MOV32rr) 6868 MIB.addReg(tt2); 6869 (*MIB).addOperand(*argOpers[5]); 6870 6871 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX); 6872 MIB.addReg(t1); 6873 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX); 6874 MIB.addReg(t2); 6875 6876 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX); 6877 MIB.addReg(t5); 6878 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX); 6879 MIB.addReg(t6); 6880 6881 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B)); 6882 for (int i=0; i <= lastAddrIndx; ++i) 6883 (*MIB).addOperand(*argOpers[i]); 6884 6885 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 6886 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 6887 6888 MIB = BuildMI(newMBB, TII->get(copyOpc), t3); 6889 MIB.addReg(X86::EAX); 6890 MIB = BuildMI(newMBB, TII->get(copyOpc), t4); 6891 MIB.addReg(X86::EDX); 6892 6893 // insert branch 6894 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 6895 6896 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 6897 return nextMBB; 6898} 6899 6900// private utility function 6901MachineBasicBlock * 6902X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 6903 MachineBasicBlock *MBB, 6904 unsigned cmovOpc) { 6905 // For the atomic min/max operator, we generate 6906 // thisMBB: 6907 // newMBB: 6908 // ld t1 = [min/max.addr] 6909 // mov t2 = [min/max.val] 6910 // cmp t1, t2 6911 // cmov[cond] t2 = t1 6912 // mov EAX = t1 6913 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 6914 // bz newMBB 6915 // fallthrough -->nextMBB 6916 // 6917 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6918 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6919 MachineFunction::iterator MBBIter = MBB; 6920 ++MBBIter; 6921 6922 /// First build the CFG 6923 MachineFunction *F = MBB->getParent(); 6924 MachineBasicBlock *thisMBB = MBB; 6925 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6926 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6927 F->insert(MBBIter, newMBB); 6928 F->insert(MBBIter, nextMBB); 6929 6930 // Move all successors to thisMBB to nextMBB 6931 nextMBB->transferSuccessors(thisMBB); 6932 6933 // Update thisMBB to fall through to newMBB 6934 thisMBB->addSuccessor(newMBB); 6935 6936 // newMBB jumps to newMBB and fall through to nextMBB 6937 newMBB->addSuccessor(nextMBB); 6938 newMBB->addSuccessor(newMBB); 6939 6940 // Insert instructions into newMBB based on incoming instruction 6941 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands"); 6942 MachineOperand& destOper = mInstr->getOperand(0); 6943 MachineOperand* argOpers[6]; 6944 int numArgs = mInstr->getNumOperands() - 1; 6945 for (int i=0; i < numArgs; ++i) 6946 argOpers[i] = &mInstr->getOperand(i+1); 6947 6948 // x86 address has 4 operands: base, index, scale, and displacement 6949 int lastAddrIndx = 3; // [0,3] 6950 int valArgIndx = 4; 6951 6952 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 6953 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1); 6954 for (int i=0; i <= lastAddrIndx; ++i) 6955 (*MIB).addOperand(*argOpers[i]); 6956 6957 // We only support register and immediate values 6958 assert((argOpers[valArgIndx]->isReg() || 6959 argOpers[valArgIndx]->isImm()) && 6960 "invalid operand"); 6961 6962 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 6963 if (argOpers[valArgIndx]->isReg()) 6964 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); 6965 else 6966 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); 6967 (*MIB).addOperand(*argOpers[valArgIndx]); 6968 6969 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX); 6970 MIB.addReg(t1); 6971 6972 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr)); 6973 MIB.addReg(t1); 6974 MIB.addReg(t2); 6975 6976 // Generate movc 6977 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 6978 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3); 6979 MIB.addReg(t2); 6980 MIB.addReg(t1); 6981 6982 // Cmp and exchange if none has modified the memory location 6983 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32)); 6984 for (int i=0; i <= lastAddrIndx; ++i) 6985 (*MIB).addOperand(*argOpers[i]); 6986 MIB.addReg(t3); 6987 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 6988 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 6989 6990 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); 6991 MIB.addReg(X86::EAX); 6992 6993 // insert branch 6994 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 6995 6996 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 6997 return nextMBB; 6998} 6999 7000 7001MachineBasicBlock * 7002X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 7003 MachineBasicBlock *BB) { 7004 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7005 switch (MI->getOpcode()) { 7006 default: assert(false && "Unexpected instr type to insert"); 7007 case X86::CMOV_V1I64: 7008 case X86::CMOV_FR32: 7009 case X86::CMOV_FR64: 7010 case X86::CMOV_V4F32: 7011 case X86::CMOV_V2F64: 7012 case X86::CMOV_V2I64: { 7013 // To "insert" a SELECT_CC instruction, we actually have to insert the 7014 // diamond control-flow pattern. The incoming instruction knows the 7015 // destination vreg to set, the condition code register to branch on, the 7016 // true/false values to select between, and a branch opcode to use. 7017 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 7018 MachineFunction::iterator It = BB; 7019 ++It; 7020 7021 // thisMBB: 7022 // ... 7023 // TrueVal = ... 7024 // cmpTY ccX, r1, r2 7025 // bCC copy1MBB 7026 // fallthrough --> copy0MBB 7027 MachineBasicBlock *thisMBB = BB; 7028 MachineFunction *F = BB->getParent(); 7029 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 7030 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 7031 unsigned Opc = 7032 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 7033 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 7034 F->insert(It, copy0MBB); 7035 F->insert(It, sinkMBB); 7036 // Update machine-CFG edges by transferring all successors of the current 7037 // block to the new block which will contain the Phi node for the select. 7038 sinkMBB->transferSuccessors(BB); 7039 7040 // Add the true and fallthrough blocks as its successors. 7041 BB->addSuccessor(copy0MBB); 7042 BB->addSuccessor(sinkMBB); 7043 7044 // copy0MBB: 7045 // %FalseValue = ... 7046 // # fallthrough to sinkMBB 7047 BB = copy0MBB; 7048 7049 // Update machine-CFG edges 7050 BB->addSuccessor(sinkMBB); 7051 7052 // sinkMBB: 7053 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 7054 // ... 7055 BB = sinkMBB; 7056 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) 7057 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 7058 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 7059 7060 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7061 return BB; 7062 } 7063 7064 case X86::FP32_TO_INT16_IN_MEM: 7065 case X86::FP32_TO_INT32_IN_MEM: 7066 case X86::FP32_TO_INT64_IN_MEM: 7067 case X86::FP64_TO_INT16_IN_MEM: 7068 case X86::FP64_TO_INT32_IN_MEM: 7069 case X86::FP64_TO_INT64_IN_MEM: 7070 case X86::FP80_TO_INT16_IN_MEM: 7071 case X86::FP80_TO_INT32_IN_MEM: 7072 case X86::FP80_TO_INT64_IN_MEM: { 7073 // Change the floating point control register to use "round towards zero" 7074 // mode when truncating to an integer value. 7075 MachineFunction *F = BB->getParent(); 7076 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 7077 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); 7078 7079 // Load the old value of the high byte of the control word... 7080 unsigned OldCW = 7081 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 7082 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); 7083 7084 // Set the high part to be round to zero... 7085 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) 7086 .addImm(0xC7F); 7087 7088 // Reload the modified control word now... 7089 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 7090 7091 // Restore the memory image of control word to original value 7092 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) 7093 .addReg(OldCW); 7094 7095 // Get the X86 opcode to use. 7096 unsigned Opc; 7097 switch (MI->getOpcode()) { 7098 default: assert(0 && "illegal opcode!"); 7099 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 7100 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 7101 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 7102 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 7103 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 7104 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 7105 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 7106 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 7107 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 7108 } 7109 7110 X86AddressMode AM; 7111 MachineOperand &Op = MI->getOperand(0); 7112 if (Op.isReg()) { 7113 AM.BaseType = X86AddressMode::RegBase; 7114 AM.Base.Reg = Op.getReg(); 7115 } else { 7116 AM.BaseType = X86AddressMode::FrameIndexBase; 7117 AM.Base.FrameIndex = Op.getIndex(); 7118 } 7119 Op = MI->getOperand(1); 7120 if (Op.isImm()) 7121 AM.Scale = Op.getImm(); 7122 Op = MI->getOperand(2); 7123 if (Op.isImm()) 7124 AM.IndexReg = Op.getImm(); 7125 Op = MI->getOperand(3); 7126 if (Op.isGlobal()) { 7127 AM.GV = Op.getGlobal(); 7128 } else { 7129 AM.Disp = Op.getImm(); 7130 } 7131 addFullAddress(BuildMI(BB, TII->get(Opc)), AM) 7132 .addReg(MI->getOperand(4).getReg()); 7133 7134 // Reload the original control word now. 7135 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 7136 7137 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7138 return BB; 7139 } 7140 case X86::ATOMAND32: 7141 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7142 X86::AND32ri, X86::MOV32rm, 7143 X86::LCMPXCHG32, X86::MOV32rr, 7144 X86::NOT32r, X86::EAX, 7145 X86::GR32RegisterClass); 7146 case X86::ATOMOR32: 7147 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 7148 X86::OR32ri, X86::MOV32rm, 7149 X86::LCMPXCHG32, X86::MOV32rr, 7150 X86::NOT32r, X86::EAX, 7151 X86::GR32RegisterClass); 7152 case X86::ATOMXOR32: 7153 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 7154 X86::XOR32ri, X86::MOV32rm, 7155 X86::LCMPXCHG32, X86::MOV32rr, 7156 X86::NOT32r, X86::EAX, 7157 X86::GR32RegisterClass); 7158 case X86::ATOMNAND32: 7159 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7160 X86::AND32ri, X86::MOV32rm, 7161 X86::LCMPXCHG32, X86::MOV32rr, 7162 X86::NOT32r, X86::EAX, 7163 X86::GR32RegisterClass, true); 7164 case X86::ATOMMIN32: 7165 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 7166 case X86::ATOMMAX32: 7167 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 7168 case X86::ATOMUMIN32: 7169 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 7170 case X86::ATOMUMAX32: 7171 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 7172 7173 case X86::ATOMAND16: 7174 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7175 X86::AND16ri, X86::MOV16rm, 7176 X86::LCMPXCHG16, X86::MOV16rr, 7177 X86::NOT16r, X86::AX, 7178 X86::GR16RegisterClass); 7179 case X86::ATOMOR16: 7180 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 7181 X86::OR16ri, X86::MOV16rm, 7182 X86::LCMPXCHG16, X86::MOV16rr, 7183 X86::NOT16r, X86::AX, 7184 X86::GR16RegisterClass); 7185 case X86::ATOMXOR16: 7186 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 7187 X86::XOR16ri, X86::MOV16rm, 7188 X86::LCMPXCHG16, X86::MOV16rr, 7189 X86::NOT16r, X86::AX, 7190 X86::GR16RegisterClass); 7191 case X86::ATOMNAND16: 7192 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7193 X86::AND16ri, X86::MOV16rm, 7194 X86::LCMPXCHG16, X86::MOV16rr, 7195 X86::NOT16r, X86::AX, 7196 X86::GR16RegisterClass, true); 7197 case X86::ATOMMIN16: 7198 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 7199 case X86::ATOMMAX16: 7200 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 7201 case X86::ATOMUMIN16: 7202 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 7203 case X86::ATOMUMAX16: 7204 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 7205 7206 case X86::ATOMAND8: 7207 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7208 X86::AND8ri, X86::MOV8rm, 7209 X86::LCMPXCHG8, X86::MOV8rr, 7210 X86::NOT8r, X86::AL, 7211 X86::GR8RegisterClass); 7212 case X86::ATOMOR8: 7213 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 7214 X86::OR8ri, X86::MOV8rm, 7215 X86::LCMPXCHG8, X86::MOV8rr, 7216 X86::NOT8r, X86::AL, 7217 X86::GR8RegisterClass); 7218 case X86::ATOMXOR8: 7219 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 7220 X86::XOR8ri, X86::MOV8rm, 7221 X86::LCMPXCHG8, X86::MOV8rr, 7222 X86::NOT8r, X86::AL, 7223 X86::GR8RegisterClass); 7224 case X86::ATOMNAND8: 7225 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7226 X86::AND8ri, X86::MOV8rm, 7227 X86::LCMPXCHG8, X86::MOV8rr, 7228 X86::NOT8r, X86::AL, 7229 X86::GR8RegisterClass, true); 7230 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 7231 // This group is for 64-bit host. 7232 case X86::ATOMAND64: 7233 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7234 X86::AND64ri32, X86::MOV64rm, 7235 X86::LCMPXCHG64, X86::MOV64rr, 7236 X86::NOT64r, X86::RAX, 7237 X86::GR64RegisterClass); 7238 case X86::ATOMOR64: 7239 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 7240 X86::OR64ri32, X86::MOV64rm, 7241 X86::LCMPXCHG64, X86::MOV64rr, 7242 X86::NOT64r, X86::RAX, 7243 X86::GR64RegisterClass); 7244 case X86::ATOMXOR64: 7245 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 7246 X86::XOR64ri32, X86::MOV64rm, 7247 X86::LCMPXCHG64, X86::MOV64rr, 7248 X86::NOT64r, X86::RAX, 7249 X86::GR64RegisterClass); 7250 case X86::ATOMNAND64: 7251 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7252 X86::AND64ri32, X86::MOV64rm, 7253 X86::LCMPXCHG64, X86::MOV64rr, 7254 X86::NOT64r, X86::RAX, 7255 X86::GR64RegisterClass, true); 7256 case X86::ATOMMIN64: 7257 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 7258 case X86::ATOMMAX64: 7259 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 7260 case X86::ATOMUMIN64: 7261 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 7262 case X86::ATOMUMAX64: 7263 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 7264 7265 // This group does 64-bit operations on a 32-bit host. 7266 case X86::ATOMAND6432: 7267 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7268 X86::AND32rr, X86::AND32rr, 7269 X86::AND32ri, X86::AND32ri, 7270 false); 7271 case X86::ATOMOR6432: 7272 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7273 X86::OR32rr, X86::OR32rr, 7274 X86::OR32ri, X86::OR32ri, 7275 false); 7276 case X86::ATOMXOR6432: 7277 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7278 X86::XOR32rr, X86::XOR32rr, 7279 X86::XOR32ri, X86::XOR32ri, 7280 false); 7281 case X86::ATOMNAND6432: 7282 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7283 X86::AND32rr, X86::AND32rr, 7284 X86::AND32ri, X86::AND32ri, 7285 true); 7286 case X86::ATOMADD6432: 7287 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7288 X86::ADD32rr, X86::ADC32rr, 7289 X86::ADD32ri, X86::ADC32ri, 7290 false); 7291 case X86::ATOMSUB6432: 7292 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7293 X86::SUB32rr, X86::SBB32rr, 7294 X86::SUB32ri, X86::SBB32ri, 7295 false); 7296 case X86::ATOMSWAP6432: 7297 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7298 X86::MOV32rr, X86::MOV32rr, 7299 X86::MOV32ri, X86::MOV32ri, 7300 false); 7301 } 7302} 7303 7304//===----------------------------------------------------------------------===// 7305// X86 Optimization Hooks 7306//===----------------------------------------------------------------------===// 7307 7308void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7309 const APInt &Mask, 7310 APInt &KnownZero, 7311 APInt &KnownOne, 7312 const SelectionDAG &DAG, 7313 unsigned Depth) const { 7314 unsigned Opc = Op.getOpcode(); 7315 assert((Opc >= ISD::BUILTIN_OP_END || 7316 Opc == ISD::INTRINSIC_WO_CHAIN || 7317 Opc == ISD::INTRINSIC_W_CHAIN || 7318 Opc == ISD::INTRINSIC_VOID) && 7319 "Should use MaskedValueIsZero if you don't know whether Op" 7320 " is a target node!"); 7321 7322 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 7323 switch (Opc) { 7324 default: break; 7325 case X86ISD::SETCC: 7326 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 7327 Mask.getBitWidth() - 1); 7328 break; 7329 } 7330} 7331 7332/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 7333/// node is a GlobalAddress + offset. 7334bool X86TargetLowering::isGAPlusOffset(SDNode *N, 7335 GlobalValue* &GA, int64_t &Offset) const{ 7336 if (N->getOpcode() == X86ISD::Wrapper) { 7337 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 7338 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 7339 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 7340 return true; 7341 } 7342 } 7343 return TargetLowering::isGAPlusOffset(N, GA, Offset); 7344} 7345 7346static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 7347 const TargetLowering &TLI) { 7348 GlobalValue *GV; 7349 int64_t Offset = 0; 7350 if (TLI.isGAPlusOffset(Base, GV, Offset)) 7351 return (GV->getAlignment() >= N && (Offset % N) == 0); 7352 // DAG combine handles the stack object case. 7353 return false; 7354} 7355 7356static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask, 7357 unsigned NumElems, MVT EVT, 7358 SDNode *&Base, 7359 SelectionDAG &DAG, MachineFrameInfo *MFI, 7360 const TargetLowering &TLI) { 7361 Base = NULL; 7362 for (unsigned i = 0; i < NumElems; ++i) { 7363 SDValue Idx = PermMask.getOperand(i); 7364 if (Idx.getOpcode() == ISD::UNDEF) { 7365 if (!Base) 7366 return false; 7367 continue; 7368 } 7369 7370 SDValue Elt = DAG.getShuffleScalarElt(N, i); 7371 if (!Elt.getNode() || 7372 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 7373 return false; 7374 if (!Base) { 7375 Base = Elt.getNode(); 7376 if (Base->getOpcode() == ISD::UNDEF) 7377 return false; 7378 continue; 7379 } 7380 if (Elt.getOpcode() == ISD::UNDEF) 7381 continue; 7382 7383 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base, 7384 EVT.getSizeInBits()/8, i, MFI)) 7385 return false; 7386 } 7387 return true; 7388} 7389 7390/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 7391/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 7392/// if the load addresses are consecutive, non-overlapping, and in the right 7393/// order. 7394static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 7395 const TargetLowering &TLI) { 7396 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7397 MVT VT = N->getValueType(0); 7398 MVT EVT = VT.getVectorElementType(); 7399 SDValue PermMask = N->getOperand(2); 7400 unsigned NumElems = PermMask.getNumOperands(); 7401 SDNode *Base = NULL; 7402 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base, 7403 DAG, MFI, TLI)) 7404 return SDValue(); 7405 7406 LoadSDNode *LD = cast<LoadSDNode>(Base); 7407 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI)) 7408 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 7409 LD->getSrcValueOffset(), LD->isVolatile()); 7410 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 7411 LD->getSrcValueOffset(), LD->isVolatile(), 7412 LD->getAlignment()); 7413} 7414 7415/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. 7416static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, 7417 const X86Subtarget *Subtarget, 7418 const TargetLowering &TLI) { 7419 unsigned NumOps = N->getNumOperands(); 7420 7421 // Ignore single operand BUILD_VECTOR. 7422 if (NumOps == 1) 7423 return SDValue(); 7424 7425 MVT VT = N->getValueType(0); 7426 MVT EVT = VT.getVectorElementType(); 7427 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit()) 7428 // We are looking for load i64 and zero extend. We want to transform 7429 // it before legalizer has a chance to expand it. Also look for i64 7430 // BUILD_PAIR bit casted to f64. 7431 return SDValue(); 7432 // This must be an insertion into a zero vector. 7433 SDValue HighElt = N->getOperand(1); 7434 if (!isZeroNode(HighElt)) 7435 return SDValue(); 7436 7437 // Value must be a load. 7438 SDNode *Base = N->getOperand(0).getNode(); 7439 if (!isa<LoadSDNode>(Base)) { 7440 if (Base->getOpcode() != ISD::BIT_CONVERT) 7441 return SDValue(); 7442 Base = Base->getOperand(0).getNode(); 7443 if (!isa<LoadSDNode>(Base)) 7444 return SDValue(); 7445 } 7446 7447 // Transform it into VZEXT_LOAD addr. 7448 LoadSDNode *LD = cast<LoadSDNode>(Base); 7449 7450 // Load must not be an extload. 7451 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 7452 return SDValue(); 7453 7454 SDVTList Tys = DAG.getVTList(VT, MVT::Other); 7455 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 7456 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2); 7457 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1)); 7458 return ResNode; 7459} 7460 7461/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 7462static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 7463 const X86Subtarget *Subtarget) { 7464 SDValue Cond = N->getOperand(0); 7465 7466 // If we have SSE[12] support, try to form min/max nodes. 7467 if (Subtarget->hasSSE2() && 7468 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 7469 if (Cond.getOpcode() == ISD::SETCC) { 7470 // Get the LHS/RHS of the select. 7471 SDValue LHS = N->getOperand(1); 7472 SDValue RHS = N->getOperand(2); 7473 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 7474 7475 unsigned Opcode = 0; 7476 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 7477 switch (CC) { 7478 default: break; 7479 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 7480 case ISD::SETULE: 7481 case ISD::SETLE: 7482 if (!UnsafeFPMath) break; 7483 // FALL THROUGH. 7484 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 7485 case ISD::SETLT: 7486 Opcode = X86ISD::FMIN; 7487 break; 7488 7489 case ISD::SETOGT: // (X > Y) ? X : Y -> max 7490 case ISD::SETUGT: 7491 case ISD::SETGT: 7492 if (!UnsafeFPMath) break; 7493 // FALL THROUGH. 7494 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 7495 case ISD::SETGE: 7496 Opcode = X86ISD::FMAX; 7497 break; 7498 } 7499 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 7500 switch (CC) { 7501 default: break; 7502 case ISD::SETOGT: // (X > Y) ? Y : X -> min 7503 case ISD::SETUGT: 7504 case ISD::SETGT: 7505 if (!UnsafeFPMath) break; 7506 // FALL THROUGH. 7507 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 7508 case ISD::SETGE: 7509 Opcode = X86ISD::FMIN; 7510 break; 7511 7512 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 7513 case ISD::SETULE: 7514 case ISD::SETLE: 7515 if (!UnsafeFPMath) break; 7516 // FALL THROUGH. 7517 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 7518 case ISD::SETLT: 7519 Opcode = X86ISD::FMAX; 7520 break; 7521 } 7522 } 7523 7524 if (Opcode) 7525 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); 7526 } 7527 7528 } 7529 7530 return SDValue(); 7531} 7532 7533/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 7534static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 7535 const X86Subtarget *Subtarget) { 7536 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 7537 // the FP state in cases where an emms may be missing. 7538 // A preferable solution to the general problem is to figure out the right 7539 // places to insert EMMS. This qualifies as a quick hack. 7540 StoreSDNode *St = cast<StoreSDNode>(N); 7541 if (St->getValue().getValueType().isVector() && 7542 St->getValue().getValueType().getSizeInBits() == 64 && 7543 isa<LoadSDNode>(St->getValue()) && 7544 !cast<LoadSDNode>(St->getValue())->isVolatile() && 7545 St->getChain().hasOneUse() && !St->isVolatile()) { 7546 SDNode* LdVal = St->getValue().getNode(); 7547 LoadSDNode *Ld = 0; 7548 int TokenFactorIndex = -1; 7549 SmallVector<SDValue, 8> Ops; 7550 SDNode* ChainVal = St->getChain().getNode(); 7551 // Must be a store of a load. We currently handle two cases: the load 7552 // is a direct child, and it's under an intervening TokenFactor. It is 7553 // possible to dig deeper under nested TokenFactors. 7554 if (ChainVal == LdVal) 7555 Ld = cast<LoadSDNode>(St->getChain()); 7556 else if (St->getValue().hasOneUse() && 7557 ChainVal->getOpcode() == ISD::TokenFactor) { 7558 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 7559 if (ChainVal->getOperand(i).getNode() == LdVal) { 7560 TokenFactorIndex = i; 7561 Ld = cast<LoadSDNode>(St->getValue()); 7562 } else 7563 Ops.push_back(ChainVal->getOperand(i)); 7564 } 7565 } 7566 if (Ld) { 7567 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 7568 if (Subtarget->is64Bit()) { 7569 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), 7570 Ld->getBasePtr(), Ld->getSrcValue(), 7571 Ld->getSrcValueOffset(), Ld->isVolatile(), 7572 Ld->getAlignment()); 7573 SDValue NewChain = NewLd.getValue(1); 7574 if (TokenFactorIndex != -1) { 7575 Ops.push_back(NewChain); 7576 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 7577 Ops.size()); 7578 } 7579 return DAG.getStore(NewChain, NewLd, St->getBasePtr(), 7580 St->getSrcValue(), St->getSrcValueOffset(), 7581 St->isVolatile(), St->getAlignment()); 7582 } 7583 7584 // Otherwise, lower to two 32-bit copies. 7585 SDValue LoAddr = Ld->getBasePtr(); 7586 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 7587 DAG.getConstant(4, MVT::i32)); 7588 7589 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, 7590 Ld->getSrcValue(), Ld->getSrcValueOffset(), 7591 Ld->isVolatile(), Ld->getAlignment()); 7592 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, 7593 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 7594 Ld->isVolatile(), 7595 MinAlign(Ld->getAlignment(), 4)); 7596 7597 SDValue NewChain = LoLd.getValue(1); 7598 if (TokenFactorIndex != -1) { 7599 Ops.push_back(LoLd); 7600 Ops.push_back(HiLd); 7601 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 7602 Ops.size()); 7603 } 7604 7605 LoAddr = St->getBasePtr(); 7606 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 7607 DAG.getConstant(4, MVT::i32)); 7608 7609 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr, 7610 St->getSrcValue(), St->getSrcValueOffset(), 7611 St->isVolatile(), St->getAlignment()); 7612 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr, 7613 St->getSrcValue(), 7614 St->getSrcValueOffset() + 4, 7615 St->isVolatile(), 7616 MinAlign(St->getAlignment(), 4)); 7617 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); 7618 } 7619 } 7620 return SDValue(); 7621} 7622 7623/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 7624/// X86ISD::FXOR nodes. 7625static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 7626 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 7627 // F[X]OR(0.0, x) -> x 7628 // F[X]OR(x, 0.0) -> x 7629 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 7630 if (C->getValueAPF().isPosZero()) 7631 return N->getOperand(1); 7632 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 7633 if (C->getValueAPF().isPosZero()) 7634 return N->getOperand(0); 7635 return SDValue(); 7636} 7637 7638/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 7639static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 7640 // FAND(0.0, x) -> 0.0 7641 // FAND(x, 0.0) -> 0.0 7642 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 7643 if (C->getValueAPF().isPosZero()) 7644 return N->getOperand(0); 7645 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 7646 if (C->getValueAPF().isPosZero()) 7647 return N->getOperand(1); 7648 return SDValue(); 7649} 7650 7651 7652SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 7653 DAGCombinerInfo &DCI) const { 7654 SelectionDAG &DAG = DCI.DAG; 7655 switch (N->getOpcode()) { 7656 default: break; 7657 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 7658 case ISD::BUILD_VECTOR: 7659 return PerformBuildVectorCombine(N, DAG, Subtarget, *this); 7660 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 7661 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 7662 case X86ISD::FXOR: 7663 case X86ISD::FOR: return PerformFORCombine(N, DAG); 7664 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 7665 } 7666 7667 return SDValue(); 7668} 7669 7670//===----------------------------------------------------------------------===// 7671// X86 Inline Assembly Support 7672//===----------------------------------------------------------------------===// 7673 7674/// getConstraintType - Given a constraint letter, return the type of 7675/// constraint it is for this target. 7676X86TargetLowering::ConstraintType 7677X86TargetLowering::getConstraintType(const std::string &Constraint) const { 7678 if (Constraint.size() == 1) { 7679 switch (Constraint[0]) { 7680 case 'A': 7681 return C_Register; 7682 case 'f': 7683 case 'r': 7684 case 'R': 7685 case 'l': 7686 case 'q': 7687 case 'Q': 7688 case 'x': 7689 case 'y': 7690 case 'Y': 7691 return C_RegisterClass; 7692 default: 7693 break; 7694 } 7695 } 7696 return TargetLowering::getConstraintType(Constraint); 7697} 7698 7699/// LowerXConstraint - try to replace an X constraint, which matches anything, 7700/// with another that has more specific requirements based on the type of the 7701/// corresponding operand. 7702const char *X86TargetLowering:: 7703LowerXConstraint(MVT ConstraintVT) const { 7704 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 7705 // 'f' like normal targets. 7706 if (ConstraintVT.isFloatingPoint()) { 7707 if (Subtarget->hasSSE2()) 7708 return "Y"; 7709 if (Subtarget->hasSSE1()) 7710 return "x"; 7711 } 7712 7713 return TargetLowering::LowerXConstraint(ConstraintVT); 7714} 7715 7716/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 7717/// vector. If it is invalid, don't add anything to Ops. 7718void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 7719 char Constraint, 7720 bool hasMemory, 7721 std::vector<SDValue>&Ops, 7722 SelectionDAG &DAG) const { 7723 SDValue Result(0, 0); 7724 7725 switch (Constraint) { 7726 default: break; 7727 case 'I': 7728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 7729 if (C->getZExtValue() <= 31) { 7730 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 7731 break; 7732 } 7733 } 7734 return; 7735 case 'J': 7736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 7737 if (C->getZExtValue() <= 63) { 7738 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 7739 break; 7740 } 7741 } 7742 return; 7743 case 'N': 7744 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 7745 if (C->getZExtValue() <= 255) { 7746 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 7747 break; 7748 } 7749 } 7750 return; 7751 case 'i': { 7752 // Literal immediates are always ok. 7753 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 7754 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType()); 7755 break; 7756 } 7757 7758 // If we are in non-pic codegen mode, we allow the address of a global (with 7759 // an optional displacement) to be used with 'i'. 7760 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 7761 int64_t Offset = 0; 7762 7763 // Match either (GA) or (GA+C) 7764 if (GA) { 7765 Offset = GA->getOffset(); 7766 } else if (Op.getOpcode() == ISD::ADD) { 7767 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7768 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 7769 if (C && GA) { 7770 Offset = GA->getOffset()+C->getZExtValue(); 7771 } else { 7772 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7773 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 7774 if (C && GA) 7775 Offset = GA->getOffset()+C->getZExtValue(); 7776 else 7777 C = 0, GA = 0; 7778 } 7779 } 7780 7781 if (GA) { 7782 if (hasMemory) 7783 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG); 7784 else 7785 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 7786 Offset); 7787 Result = Op; 7788 break; 7789 } 7790 7791 // Otherwise, not valid for this mode. 7792 return; 7793 } 7794 } 7795 7796 if (Result.getNode()) { 7797 Ops.push_back(Result); 7798 return; 7799 } 7800 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 7801 Ops, DAG); 7802} 7803 7804std::vector<unsigned> X86TargetLowering:: 7805getRegClassForInlineAsmConstraint(const std::string &Constraint, 7806 MVT VT) const { 7807 if (Constraint.size() == 1) { 7808 // FIXME: not handling fp-stack yet! 7809 switch (Constraint[0]) { // GCC X86 Constraint Letters 7810 default: break; // Unknown constraint letter 7811 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 7812 case 'Q': // Q_REGS 7813 if (VT == MVT::i32) 7814 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 7815 else if (VT == MVT::i16) 7816 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 7817 else if (VT == MVT::i8) 7818 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 7819 else if (VT == MVT::i64) 7820 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 7821 break; 7822 } 7823 } 7824 7825 return std::vector<unsigned>(); 7826} 7827 7828std::pair<unsigned, const TargetRegisterClass*> 7829X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 7830 MVT VT) const { 7831 // First, see if this is a constraint that directly corresponds to an LLVM 7832 // register class. 7833 if (Constraint.size() == 1) { 7834 // GCC Constraint Letters 7835 switch (Constraint[0]) { 7836 default: break; 7837 case 'r': // GENERAL_REGS 7838 case 'R': // LEGACY_REGS 7839 case 'l': // INDEX_REGS 7840 if (VT == MVT::i8) 7841 return std::make_pair(0U, X86::GR8RegisterClass); 7842 if (VT == MVT::i16) 7843 return std::make_pair(0U, X86::GR16RegisterClass); 7844 if (VT == MVT::i32 || !Subtarget->is64Bit()) 7845 return std::make_pair(0U, X86::GR32RegisterClass); 7846 return std::make_pair(0U, X86::GR64RegisterClass); 7847 case 'f': // FP Stack registers. 7848 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 7849 // value to the correct fpstack register class. 7850 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 7851 return std::make_pair(0U, X86::RFP32RegisterClass); 7852 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 7853 return std::make_pair(0U, X86::RFP64RegisterClass); 7854 return std::make_pair(0U, X86::RFP80RegisterClass); 7855 case 'y': // MMX_REGS if MMX allowed. 7856 if (!Subtarget->hasMMX()) break; 7857 return std::make_pair(0U, X86::VR64RegisterClass); 7858 case 'Y': // SSE_REGS if SSE2 allowed 7859 if (!Subtarget->hasSSE2()) break; 7860 // FALL THROUGH. 7861 case 'x': // SSE_REGS if SSE1 allowed 7862 if (!Subtarget->hasSSE1()) break; 7863 7864 switch (VT.getSimpleVT()) { 7865 default: break; 7866 // Scalar SSE types. 7867 case MVT::f32: 7868 case MVT::i32: 7869 return std::make_pair(0U, X86::FR32RegisterClass); 7870 case MVT::f64: 7871 case MVT::i64: 7872 return std::make_pair(0U, X86::FR64RegisterClass); 7873 // Vector types. 7874 case MVT::v16i8: 7875 case MVT::v8i16: 7876 case MVT::v4i32: 7877 case MVT::v2i64: 7878 case MVT::v4f32: 7879 case MVT::v2f64: 7880 return std::make_pair(0U, X86::VR128RegisterClass); 7881 } 7882 break; 7883 } 7884 } 7885 7886 // Use the default implementation in TargetLowering to convert the register 7887 // constraint into a member of a register class. 7888 std::pair<unsigned, const TargetRegisterClass*> Res; 7889 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 7890 7891 // Not found as a standard register? 7892 if (Res.second == 0) { 7893 // GCC calls "st(0)" just plain "st". 7894 if (StringsEqualNoCase("{st}", Constraint)) { 7895 Res.first = X86::ST0; 7896 Res.second = X86::RFP80RegisterClass; 7897 } 7898 // 'A' means EAX + EDX. 7899 if (Constraint == "A") { 7900 Res.first = X86::EAX; 7901 Res.second = X86::GRADRegisterClass; 7902 } 7903 return Res; 7904 } 7905 7906 // Otherwise, check to see if this is a register class of the wrong value 7907 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 7908 // turn into {ax},{dx}. 7909 if (Res.second->hasType(VT)) 7910 return Res; // Correct type already, nothing to do. 7911 7912 // All of the single-register GCC register classes map their values onto 7913 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 7914 // really want an 8-bit or 32-bit register, map to the appropriate register 7915 // class and return the appropriate register. 7916 if (Res.second == X86::GR16RegisterClass) { 7917 if (VT == MVT::i8) { 7918 unsigned DestReg = 0; 7919 switch (Res.first) { 7920 default: break; 7921 case X86::AX: DestReg = X86::AL; break; 7922 case X86::DX: DestReg = X86::DL; break; 7923 case X86::CX: DestReg = X86::CL; break; 7924 case X86::BX: DestReg = X86::BL; break; 7925 } 7926 if (DestReg) { 7927 Res.first = DestReg; 7928 Res.second = Res.second = X86::GR8RegisterClass; 7929 } 7930 } else if (VT == MVT::i32) { 7931 unsigned DestReg = 0; 7932 switch (Res.first) { 7933 default: break; 7934 case X86::AX: DestReg = X86::EAX; break; 7935 case X86::DX: DestReg = X86::EDX; break; 7936 case X86::CX: DestReg = X86::ECX; break; 7937 case X86::BX: DestReg = X86::EBX; break; 7938 case X86::SI: DestReg = X86::ESI; break; 7939 case X86::DI: DestReg = X86::EDI; break; 7940 case X86::BP: DestReg = X86::EBP; break; 7941 case X86::SP: DestReg = X86::ESP; break; 7942 } 7943 if (DestReg) { 7944 Res.first = DestReg; 7945 Res.second = Res.second = X86::GR32RegisterClass; 7946 } 7947 } else if (VT == MVT::i64) { 7948 unsigned DestReg = 0; 7949 switch (Res.first) { 7950 default: break; 7951 case X86::AX: DestReg = X86::RAX; break; 7952 case X86::DX: DestReg = X86::RDX; break; 7953 case X86::CX: DestReg = X86::RCX; break; 7954 case X86::BX: DestReg = X86::RBX; break; 7955 case X86::SI: DestReg = X86::RSI; break; 7956 case X86::DI: DestReg = X86::RDI; break; 7957 case X86::BP: DestReg = X86::RBP; break; 7958 case X86::SP: DestReg = X86::RSP; break; 7959 } 7960 if (DestReg) { 7961 Res.first = DestReg; 7962 Res.second = Res.second = X86::GR64RegisterClass; 7963 } 7964 } 7965 } else if (Res.second == X86::FR32RegisterClass || 7966 Res.second == X86::FR64RegisterClass || 7967 Res.second == X86::VR128RegisterClass) { 7968 // Handle references to XMM physical registers that got mapped into the 7969 // wrong class. This can happen with constraints like {xmm0} where the 7970 // target independent register mapper will just pick the first match it can 7971 // find, ignoring the required type. 7972 if (VT == MVT::f32) 7973 Res.second = X86::FR32RegisterClass; 7974 else if (VT == MVT::f64) 7975 Res.second = X86::FR64RegisterClass; 7976 else if (X86::VR128RegisterClass->hasType(VT)) 7977 Res.second = X86::VR128RegisterClass; 7978 } 7979 7980 return Res; 7981} 7982 7983//===----------------------------------------------------------------------===// 7984// X86 Widen vector type 7985//===----------------------------------------------------------------------===// 7986 7987/// getWidenVectorType: given a vector type, returns the type to widen 7988/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 7989/// If there is no vector type that we want to widen to, returns MVT::Other 7990/// When and where to widen is target dependent based on the cost of 7991/// scalarizing vs using the wider vector type. 7992 7993MVT X86TargetLowering::getWidenVectorType(MVT VT) { 7994 assert(VT.isVector()); 7995 if (isTypeLegal(VT)) 7996 return VT; 7997 7998 // TODO: In computeRegisterProperty, we can compute the list of legal vector 7999 // type based on element type. This would speed up our search (though 8000 // it may not be worth it since the size of the list is relatively 8001 // small). 8002 MVT EltVT = VT.getVectorElementType(); 8003 unsigned NElts = VT.getVectorNumElements(); 8004 8005 // On X86, it make sense to widen any vector wider than 1 8006 if (NElts <= 1) 8007 return MVT::Other; 8008 8009 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 8010 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 8011 MVT SVT = (MVT::SimpleValueType)nVT; 8012 8013 if (isTypeLegal(SVT) && 8014 SVT.getVectorElementType() == EltVT && 8015 SVT.getVectorNumElements() > NElts) 8016 return SVT; 8017 } 8018 return MVT::Other; 8019} 8020