X86ISelLowering.cpp revision 228756c744a1f877f7150c8fc91e074ff58c9d66
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 66 SelectionDAG &DAG, DebugLoc dl) { 67 EVT VT = Vec.getValueType(); 68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 69 EVT ElVT = VT.getVectorElementType(); 70 unsigned Factor = VT.getSizeInBits()/128; 71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 72 VT.getVectorNumElements()/Factor); 73 74 // Extract from UNDEF is UNDEF. 75 if (Vec.getOpcode() == ISD::UNDEF) 76 return DAG.getUNDEF(ResultVT); 77 78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 79 // we can match to VEXTRACTF128. 80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 81 82 // This is the index of the first element of the 128-bit chunk 83 // we want. 84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 85 * ElemsPerChunk); 86 87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 89 VecIdx); 90 91 return Result; 92} 93 94/// Generate a DAG to put 128-bits into a vector > 128 bits. This 95/// sets things up to match to an AVX VINSERTF128 instruction or a 96/// simple superregister reference. Idx is an index in the 128 bits 97/// we want. It need not be aligned to a 128-bit bounday. That makes 98/// lowering INSERT_VECTOR_ELT operations easier. 99static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 100 unsigned IdxVal, SelectionDAG &DAG, 101 DebugLoc dl) { 102 EVT VT = Vec.getValueType(); 103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 104 105 EVT ElVT = VT.getVectorElementType(); 106 EVT ResultVT = Result.getValueType(); 107 108 // Insert the relevant 128 bits. 109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 110 111 // This is the index of the first element of the 128-bit chunk 112 // we want. 113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 114 * ElemsPerChunk); 115 116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 118 VecIdx); 119 return Result; 120} 121 122/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 123/// instructions. This is used because creating CONCAT_VECTOR nodes of 124/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 125/// large BUILD_VECTORS. 126static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 127 unsigned NumElems, SelectionDAG &DAG, 128 DebugLoc dl) { 129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 131} 132 133static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 135 bool is64Bit = Subtarget->is64Bit(); 136 137 if (Subtarget->isTargetEnvMacho()) { 138 if (is64Bit) 139 return new X8664_MachoTargetObjectFile(); 140 return new TargetLoweringObjectFileMachO(); 141 } 142 143 if (Subtarget->isTargetELF()) 144 return new TargetLoweringObjectFileELF(); 145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 146 return new TargetLoweringObjectFileCOFF(); 147 llvm_unreachable("unknown subtarget type"); 148} 149 150X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 151 : TargetLowering(TM, createTLOF(TM)) { 152 Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 X86ScalarSSEf64 = Subtarget->hasSSE2(); 154 X86ScalarSSEf32 = Subtarget->hasSSE1(); 155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 156 157 RegInfo = TM.getRegisterInfo(); 158 TD = getTargetData(); 159 160 // Set up the TargetLowering object. 161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 162 163 // X86 is weird, it always uses i8 for shift amounts and setcc results. 164 setBooleanContents(ZeroOrOneBooleanContent); 165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 167 168 // For 64-bit since we have so many registers use the ILP scheduler, for 169 // 32-bit code use the register pressure specific scheduling. 170 // For Atom, always use ILP scheduling. 171 if (Subtarget->isAtom()) 172 setSchedulingPreference(Sched::ILP); 173 else if (Subtarget->is64Bit()) 174 setSchedulingPreference(Sched::ILP); 175 else 176 setSchedulingPreference(Sched::RegPressure); 177 setStackPointerRegisterToSaveRestore(X86StackPtr); 178 179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 180 // Setup Windows compiler runtime calls. 181 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 183 setLibcallName(RTLIB::SREM_I64, "_allrem"); 184 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 185 setLibcallName(RTLIB::MUL_I64, "_allmul"); 186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 191 192 // The _ftol2 runtime function has an unusual calling conv, which 193 // is modeled by a special pseudo-instruction. 194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 198 } 199 200 if (Subtarget->isTargetDarwin()) { 201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 202 setUseUnderscoreSetJmp(false); 203 setUseUnderscoreLongJmp(false); 204 } else if (Subtarget->isTargetMingw()) { 205 // MS runtime is weird: it exports _setjmp, but longjmp! 206 setUseUnderscoreSetJmp(true); 207 setUseUnderscoreLongJmp(false); 208 } else { 209 setUseUnderscoreSetJmp(true); 210 setUseUnderscoreLongJmp(true); 211 } 212 213 // Set up the register classes. 214 addRegisterClass(MVT::i8, &X86::GR8RegClass); 215 addRegisterClass(MVT::i16, &X86::GR16RegClass); 216 addRegisterClass(MVT::i32, &X86::GR32RegClass); 217 if (Subtarget->is64Bit()) 218 addRegisterClass(MVT::i64, &X86::GR64RegClass); 219 220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 221 222 // We don't accept any truncstore of integer registers. 223 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 224 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 226 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 228 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 229 230 // SETOEQ and SETUNE require checking two conditions. 231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 237 238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 239 // operation. 240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 243 244 if (Subtarget->is64Bit()) { 245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 247 } else if (!TM.Options.UseSoftFloat) { 248 // We have an algorithm for SSE2->double, and we turn this into a 249 // 64-bit FILD followed by conditional FADD for other targets. 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 // We have an algorithm for SSE2, and we turn this into a 64-bit 252 // FILD for other targets. 253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 254 } 255 256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 257 // this operation. 258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 260 261 if (!TM.Options.UseSoftFloat) { 262 // SSE has no i16 to fp conversion, only i32 263 if (X86ScalarSSEf32) { 264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 265 // f32 and f64 cases are Legal, f80 case is not 266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 267 } else { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 270 } 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 274 } 275 276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 277 // are Legal, f80 is custom lowered. 278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 280 281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 282 // this operation. 283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 285 286 if (X86ScalarSSEf32) { 287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 288 // f32 and f64 cases are Legal, f80 case is not 289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 290 } else { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 293 } 294 295 // Handle FP_TO_UINT by promoting the destination to a larger signed 296 // conversion. 297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 300 301 if (Subtarget->is64Bit()) { 302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 304 } else if (!TM.Options.UseSoftFloat) { 305 // Since AVX is a superset of SSE3, only check for SSE here. 306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 307 // Expand FP_TO_UINT into a select. 308 // FIXME: We would like to use a Custom expander here eventually to do 309 // the optimal thing for SSE vs. the default expansion in the legalizer. 310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 311 else 312 // With SSE3 we can use fisttpll to convert to a signed i64; without 313 // SSE, we're stuck with a fistpll. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 315 } 316 317 if (isTargetFTOL()) { 318 // Use the _ftol2 runtime function, which has a pseudo-instruction 319 // to handle its weird calling convention. 320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 321 } 322 323 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 324 if (!X86ScalarSSEf64) { 325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 327 if (Subtarget->is64Bit()) { 328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 329 // Without SSE, i64->f64 goes through memory. 330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 331 } 332 } 333 334 // Scalar integer divide and remainder are lowered to use operations that 335 // produce two results, to match the available instructions. This exposes 336 // the two-result form to trivial CSE, which is able to combine x/y and x%y 337 // into a single instruction. 338 // 339 // Scalar integer multiply-high is also lowered to use two-result 340 // operations, to match the available instructions. However, plain multiply 341 // (low) operations are left as Legal, as there are single-result 342 // instructions for this in x86. Using the two-result multiply instructions 343 // when both high and low results are needed must be arranged by dagcombine. 344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 345 MVT VT = IntVTs[i]; 346 setOperationAction(ISD::MULHS, VT, Expand); 347 setOperationAction(ISD::MULHU, VT, Expand); 348 setOperationAction(ISD::SDIV, VT, Expand); 349 setOperationAction(ISD::UDIV, VT, Expand); 350 setOperationAction(ISD::SREM, VT, Expand); 351 setOperationAction(ISD::UREM, VT, Expand); 352 353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 354 setOperationAction(ISD::ADDC, VT, Custom); 355 setOperationAction(ISD::ADDE, VT, Custom); 356 setOperationAction(ISD::SUBC, VT, Custom); 357 setOperationAction(ISD::SUBE, VT, Custom); 358 } 359 360 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 361 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 362 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 364 if (Subtarget->is64Bit()) 365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 370 setOperationAction(ISD::FREM , MVT::f32 , Expand); 371 setOperationAction(ISD::FREM , MVT::f64 , Expand); 372 setOperationAction(ISD::FREM , MVT::f80 , Expand); 373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 374 375 // Promote the i8 variants and force them on up to i32 which has a shorter 376 // encoding. 377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 381 if (Subtarget->hasBMI()) { 382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 384 if (Subtarget->is64Bit()) 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 386 } else { 387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 389 if (Subtarget->is64Bit()) 390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 391 } 392 393 if (Subtarget->hasLZCNT()) { 394 // When promoting the i8 variants, force them to i32 for a shorter 395 // encoding. 396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 402 if (Subtarget->is64Bit()) 403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 404 } else { 405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 411 if (Subtarget->is64Bit()) { 412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 414 } 415 } 416 417 if (Subtarget->hasPOPCNT()) { 418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 419 } else { 420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 423 if (Subtarget->is64Bit()) 424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 425 } 426 427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 429 430 // These should be promoted to a larger select which is supported. 431 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 432 // X86 wants to expand cmov itself. 433 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 434 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 435 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 436 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 437 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 438 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 439 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 440 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 441 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 442 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 443 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 444 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 445 if (Subtarget->is64Bit()) { 446 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 448 } 449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 450 451 // Darwin ABI issue. 452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 456 if (Subtarget->is64Bit()) 457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) { 461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 466 } 467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 471 if (Subtarget->is64Bit()) { 472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 475 } 476 477 if (Subtarget->hasSSE1()) 478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 479 480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 482 483 // On X86 and X86-64, atomic operations are lowered to locked instructions. 484 // Locked instructions, in turn, have implicit fence semantics (all memory 485 // operations are flushed before issuing the locked instruction, and they 486 // are not buffered), so we can fold away the common pattern of 487 // fence-atomic-fence. 488 setShouldFoldAtomicFences(true); 489 490 // Expand certain atomics 491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 492 MVT VT = IntVTs[i]; 493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 496 } 497 498 if (!Subtarget->is64Bit()) { 499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 507 } 508 509 if (Subtarget->hasCmpxchg16b()) { 510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 511 } 512 513 // FIXME - use subtarget debug flags 514 if (!Subtarget->isTargetDarwin() && 515 !Subtarget->isTargetELF() && 516 !Subtarget->isTargetCygMing()) { 517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 518 } 519 520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 524 if (Subtarget->is64Bit()) { 525 setExceptionPointerRegister(X86::RAX); 526 setExceptionSelectorRegister(X86::RDX); 527 } else { 528 setExceptionPointerRegister(X86::EAX); 529 setExceptionSelectorRegister(X86::EDX); 530 } 531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 533 534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 536 537 setOperationAction(ISD::TRAP, MVT::Other, Legal); 538 539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 540 setOperationAction(ISD::VASTART , MVT::Other, Custom); 541 setOperationAction(ISD::VAEND , MVT::Other, Expand); 542 if (Subtarget->is64Bit()) { 543 setOperationAction(ISD::VAARG , MVT::Other, Custom); 544 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 545 } else { 546 setOperationAction(ISD::VAARG , MVT::Other, Expand); 547 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 548 } 549 550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 552 553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 555 MVT::i64 : MVT::i32, Custom); 556 else if (TM.Options.EnableSegmentedStacks) 557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 558 MVT::i64 : MVT::i32, Custom); 559 else 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Expand); 562 563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 564 // f32 and f64 use SSE. 565 // Set up the FP register classes. 566 addRegisterClass(MVT::f32, &X86::FR32RegClass); 567 addRegisterClass(MVT::f64, &X86::FR64RegClass); 568 569 // Use ANDPD to simulate FABS. 570 setOperationAction(ISD::FABS , MVT::f64, Custom); 571 setOperationAction(ISD::FABS , MVT::f32, Custom); 572 573 // Use XORP to simulate FNEG. 574 setOperationAction(ISD::FNEG , MVT::f64, Custom); 575 setOperationAction(ISD::FNEG , MVT::f32, Custom); 576 577 // Use ANDPD and ORPD to simulate FCOPYSIGN. 578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 580 581 // Lower this to FGETSIGNx86 plus an AND. 582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 584 585 // We don't support sin/cos/fmod 586 setOperationAction(ISD::FSIN , MVT::f64, Expand); 587 setOperationAction(ISD::FCOS , MVT::f64, Expand); 588 setOperationAction(ISD::FSIN , MVT::f32, Expand); 589 setOperationAction(ISD::FCOS , MVT::f32, Expand); 590 591 // Expand FP immediates into loads from the stack, except for the special 592 // cases we handle. 593 addLegalFPImmediate(APFloat(+0.0)); // xorpd 594 addLegalFPImmediate(APFloat(+0.0f)); // xorps 595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 596 // Use SSE for f32, x87 for f64. 597 // Set up the FP register classes. 598 addRegisterClass(MVT::f32, &X86::FR32RegClass); 599 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 600 601 // Use ANDPS to simulate FABS. 602 setOperationAction(ISD::FABS , MVT::f32, Custom); 603 604 // Use XORP to simulate FNEG. 605 setOperationAction(ISD::FNEG , MVT::f32, Custom); 606 607 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 608 609 // Use ANDPS and ORPS to simulate FCOPYSIGN. 610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 612 613 // We don't support sin/cos/fmod 614 setOperationAction(ISD::FSIN , MVT::f32, Expand); 615 setOperationAction(ISD::FCOS , MVT::f32, Expand); 616 617 // Special cases we handle for FP constants. 618 addLegalFPImmediate(APFloat(+0.0f)); // xorps 619 addLegalFPImmediate(APFloat(+0.0)); // FLD0 620 addLegalFPImmediate(APFloat(+1.0)); // FLD1 621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 623 624 if (!TM.Options.UnsafeFPMath) { 625 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 626 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 627 } 628 } else if (!TM.Options.UseSoftFloat) { 629 // f32 and f64 in x87. 630 // Set up the FP register classes. 631 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 632 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 633 634 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 635 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 638 639 if (!TM.Options.UnsafeFPMath) { 640 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 641 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 642 } 643 addLegalFPImmediate(APFloat(+0.0)); // FLD0 644 addLegalFPImmediate(APFloat(+1.0)); // FLD1 645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 651 } 652 653 // We don't support FMA. 654 setOperationAction(ISD::FMA, MVT::f64, Expand); 655 setOperationAction(ISD::FMA, MVT::f32, Expand); 656 657 // Long double always uses X87. 658 if (!TM.Options.UseSoftFloat) { 659 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 660 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 662 { 663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 664 addLegalFPImmediate(TmpFlt); // FLD0 665 TmpFlt.changeSign(); 666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 667 668 bool ignored; 669 APFloat TmpFlt2(+1.0); 670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 671 &ignored); 672 addLegalFPImmediate(TmpFlt2); // FLD1 673 TmpFlt2.changeSign(); 674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 675 } 676 677 if (!TM.Options.UnsafeFPMath) { 678 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 679 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 680 } 681 682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 683 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 685 setOperationAction(ISD::FRINT, MVT::f80, Expand); 686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 687 setOperationAction(ISD::FMA, MVT::f80, Expand); 688 } 689 690 // Always use a library call for pow. 691 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 692 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 693 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 694 695 setOperationAction(ISD::FLOG, MVT::f80, Expand); 696 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 697 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 698 setOperationAction(ISD::FEXP, MVT::f80, Expand); 699 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 700 701 // First set operation action for all vector types to either promote 702 // (for widening) or expand (for scalarization). Then we will selectively 703 // turn on ones that can be effectively codegen'd. 704 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 705 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) { 706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 763 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE; 764 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 765 setTruncStoreAction((MVT::SimpleValueType)VT, 766 (MVT::SimpleValueType)InnerVT, Expand); 767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 770 } 771 772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 773 // with -msoft-float, disable use of MMX as well. 774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 776 // No operations on x86mmx supported, everything uses intrinsics. 777 } 778 779 // MMX-sized vectors (other than x86mmx) are expected to be expanded 780 // into smaller operations. 781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 785 setOperationAction(ISD::AND, MVT::v8i8, Expand); 786 setOperationAction(ISD::AND, MVT::v4i16, Expand); 787 setOperationAction(ISD::AND, MVT::v2i32, Expand); 788 setOperationAction(ISD::AND, MVT::v1i64, Expand); 789 setOperationAction(ISD::OR, MVT::v8i8, Expand); 790 setOperationAction(ISD::OR, MVT::v4i16, Expand); 791 setOperationAction(ISD::OR, MVT::v2i32, Expand); 792 setOperationAction(ISD::OR, MVT::v1i64, Expand); 793 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 794 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 795 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 796 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 810 811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 813 814 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 826 } 827 828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 830 831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 832 // registers cannot be used even for integer operations. 833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 837 838 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 839 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 840 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 841 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 842 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 843 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 844 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 845 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 846 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 847 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 848 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 854 855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 859 860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 865 866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 871 872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 874 EVT VT = (MVT::SimpleValueType)i; 875 // Do not attempt to custom lower non-power-of-2 vectors 876 if (!isPowerOf2_32(VT.getVectorNumElements())) 877 continue; 878 // Do not attempt to custom lower non-128-bit vectors 879 if (!VT.is128BitVector()) 880 continue; 881 setOperationAction(ISD::BUILD_VECTOR, 882 VT.getSimpleVT().SimpleTy, Custom); 883 setOperationAction(ISD::VECTOR_SHUFFLE, 884 VT.getSimpleVT().SimpleTy, Custom); 885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 886 VT.getSimpleVT().SimpleTy, Custom); 887 } 888 889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 895 896 if (Subtarget->is64Bit()) { 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 899 } 900 901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 902 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) { 903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 904 EVT VT = SVT; 905 906 // Do not attempt to promote non-128-bit vectors 907 if (!VT.is128BitVector()) 908 continue; 909 910 setOperationAction(ISD::AND, SVT, Promote); 911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 912 setOperationAction(ISD::OR, SVT, Promote); 913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 914 setOperationAction(ISD::XOR, SVT, Promote); 915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 916 setOperationAction(ISD::LOAD, SVT, Promote); 917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 918 setOperationAction(ISD::SELECT, SVT, Promote); 919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 920 } 921 922 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 923 924 // Custom lower v2i64 and v2f64 selects. 925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 929 930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 932 } 933 934 if (Subtarget->hasSSE41()) { 935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 936 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 938 setOperationAction(ISD::FRINT, MVT::f32, Legal); 939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 941 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 943 setOperationAction(ISD::FRINT, MVT::f64, Legal); 944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 945 946 // FIXME: Do we need to handle scalar-to-vector here? 947 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 948 949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 954 955 // i8 and i16 vectors are custom , because the source register and source 956 // source memory operand types are not the same width. f32 vectors are 957 // custom since the immediate controlling the insert encodes additional 958 // information. 959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 963 964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 968 969 // FIXME: these should be Legal but thats only for the case where 970 // the index is constant. For now custom expand to deal with that. 971 if (Subtarget->is64Bit()) { 972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 974 } 975 } 976 977 if (Subtarget->hasSSE2()) { 978 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 979 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 980 981 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 982 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 983 984 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 986 987 if (Subtarget->hasAVX2()) { 988 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 989 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 990 991 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 992 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 993 994 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 995 } else { 996 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 997 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 998 999 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1001 1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1003 } 1004 } 1005 1006 if (Subtarget->hasSSE42()) 1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1008 1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1016 1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1020 1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1027 1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1034 1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1038 1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1045 1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1048 1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1051 1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1059 1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1063 1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1068 1069 if (Subtarget->hasAVX2()) { 1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1074 1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1079 1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1083 // Don't lower v32i8 because there is no 128-bit byte mul 1084 1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1086 1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1089 1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1092 1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1094 } else { 1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1099 1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1104 1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1108 // Don't lower v32i8 because there is no 128-bit byte mul 1109 1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1112 1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1115 1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1117 } 1118 1119 // Custom lower several nodes for 256-bit types. 1120 for (int i = MVT::FIRST_VECTOR_VALUETYPE; 1121 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1123 EVT VT = SVT; 1124 1125 // Extract subvector is special because the value type 1126 // (result) is 128-bit but the source is 256-bit wide. 1127 if (VT.is128BitVector()) 1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1129 1130 // Do not attempt to custom lower other non-256-bit vectors 1131 if (!VT.is256BitVector()) 1132 continue; 1133 1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1140 } 1141 1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1143 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) { 1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1145 EVT VT = SVT; 1146 1147 // Do not attempt to promote non-256-bit vectors 1148 if (!VT.is256BitVector()) 1149 continue; 1150 1151 setOperationAction(ISD::AND, SVT, Promote); 1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1153 setOperationAction(ISD::OR, SVT, Promote); 1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1155 setOperationAction(ISD::XOR, SVT, Promote); 1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1157 setOperationAction(ISD::LOAD, SVT, Promote); 1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1159 setOperationAction(ISD::SELECT, SVT, Promote); 1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1161 } 1162 } 1163 1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1165 // of this type with custom code. 1166 for (int VT = MVT::FIRST_VECTOR_VALUETYPE; 1167 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) { 1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1169 Custom); 1170 } 1171 1172 // We want to custom lower some of our intrinsics. 1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1174 1175 1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1177 // handle type legalization for these operations here. 1178 // 1179 // FIXME: We really should do custom legalization for addition and 1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1181 // than generic legalization for 64-bit multiplication-with-overflow, though. 1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1183 // Add/Sub/Mul with overflow operations are custom lowered. 1184 MVT VT = IntVTs[i]; 1185 setOperationAction(ISD::SADDO, VT, Custom); 1186 setOperationAction(ISD::UADDO, VT, Custom); 1187 setOperationAction(ISD::SSUBO, VT, Custom); 1188 setOperationAction(ISD::USUBO, VT, Custom); 1189 setOperationAction(ISD::SMULO, VT, Custom); 1190 setOperationAction(ISD::UMULO, VT, Custom); 1191 } 1192 1193 // There are no 8-bit 3-address imul/mul instructions 1194 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1195 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1196 1197 if (!Subtarget->is64Bit()) { 1198 // These libcalls are not available in 32-bit. 1199 setLibcallName(RTLIB::SHL_I128, 0); 1200 setLibcallName(RTLIB::SRL_I128, 0); 1201 setLibcallName(RTLIB::SRA_I128, 0); 1202 } 1203 1204 // We have target-specific dag combine patterns for the following nodes: 1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1207 setTargetDAGCombine(ISD::VSELECT); 1208 setTargetDAGCombine(ISD::SELECT); 1209 setTargetDAGCombine(ISD::SHL); 1210 setTargetDAGCombine(ISD::SRA); 1211 setTargetDAGCombine(ISD::SRL); 1212 setTargetDAGCombine(ISD::OR); 1213 setTargetDAGCombine(ISD::AND); 1214 setTargetDAGCombine(ISD::ADD); 1215 setTargetDAGCombine(ISD::FADD); 1216 setTargetDAGCombine(ISD::FSUB); 1217 setTargetDAGCombine(ISD::SUB); 1218 setTargetDAGCombine(ISD::LOAD); 1219 setTargetDAGCombine(ISD::STORE); 1220 setTargetDAGCombine(ISD::ZERO_EXTEND); 1221 setTargetDAGCombine(ISD::ANY_EXTEND); 1222 setTargetDAGCombine(ISD::SIGN_EXTEND); 1223 setTargetDAGCombine(ISD::TRUNCATE); 1224 setTargetDAGCombine(ISD::UINT_TO_FP); 1225 setTargetDAGCombine(ISD::SINT_TO_FP); 1226 setTargetDAGCombine(ISD::SETCC); 1227 setTargetDAGCombine(ISD::FP_TO_SINT); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 // Predictable cmov don't hurt on atom because it's in-order. 1247 predictableSelectIsExpensive = !Subtarget->isAtom(); 1248 1249 setPrefFunctionAlignment(4); // 2^4 bytes. 1250} 1251 1252 1253EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1254 if (!VT.isVector()) return MVT::i8; 1255 return VT.changeVectorElementTypeToInteger(); 1256} 1257 1258 1259/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1260/// the desired ByVal argument alignment. 1261static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1262 if (MaxAlign == 16) 1263 return; 1264 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1265 if (VTy->getBitWidth() == 128) 1266 MaxAlign = 16; 1267 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1268 unsigned EltAlign = 0; 1269 getMaxByValAlign(ATy->getElementType(), EltAlign); 1270 if (EltAlign > MaxAlign) 1271 MaxAlign = EltAlign; 1272 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1273 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1274 unsigned EltAlign = 0; 1275 getMaxByValAlign(STy->getElementType(i), EltAlign); 1276 if (EltAlign > MaxAlign) 1277 MaxAlign = EltAlign; 1278 if (MaxAlign == 16) 1279 break; 1280 } 1281 } 1282} 1283 1284/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1285/// function arguments in the caller parameter area. For X86, aggregates 1286/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1287/// are at 4-byte boundaries. 1288unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1289 if (Subtarget->is64Bit()) { 1290 // Max of 8 and alignment of type. 1291 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1292 if (TyAlign > 8) 1293 return TyAlign; 1294 return 8; 1295 } 1296 1297 unsigned Align = 4; 1298 if (Subtarget->hasSSE1()) 1299 getMaxByValAlign(Ty, Align); 1300 return Align; 1301} 1302 1303/// getOptimalMemOpType - Returns the target specific optimal type for load 1304/// and store operations as a result of memset, memcpy, and memmove 1305/// lowering. If DstAlign is zero that means it's safe to destination 1306/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1307/// means there isn't a need to check it against alignment requirement, 1308/// probably because the source does not need to be loaded. If 1309/// 'IsZeroVal' is true, that means it's safe to return a 1310/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1311/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1312/// constant so it does not need to be loaded. 1313/// It returns EVT::Other if the type should be determined using generic 1314/// target-independent logic. 1315EVT 1316X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1317 unsigned DstAlign, unsigned SrcAlign, 1318 bool IsZeroVal, 1319 bool MemcpyStrSrc, 1320 MachineFunction &MF) const { 1321 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1322 // linux. This is because the stack realignment code can't handle certain 1323 // cases like PR2962. This should be removed when PR2962 is fixed. 1324 const Function *F = MF.getFunction(); 1325 if (IsZeroVal && 1326 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1327 if (Size >= 16 && 1328 (Subtarget->isUnalignedMemAccessFast() || 1329 ((DstAlign == 0 || DstAlign >= 16) && 1330 (SrcAlign == 0 || SrcAlign >= 16))) && 1331 Subtarget->getStackAlignment() >= 16) { 1332 if (Subtarget->getStackAlignment() >= 32) { 1333 if (Subtarget->hasAVX2()) 1334 return MVT::v8i32; 1335 if (Subtarget->hasAVX()) 1336 return MVT::v8f32; 1337 } 1338 if (Subtarget->hasSSE2()) 1339 return MVT::v4i32; 1340 if (Subtarget->hasSSE1()) 1341 return MVT::v4f32; 1342 } else if (!MemcpyStrSrc && Size >= 8 && 1343 !Subtarget->is64Bit() && 1344 Subtarget->getStackAlignment() >= 8 && 1345 Subtarget->hasSSE2()) { 1346 // Do not use f64 to lower memcpy if source is string constant. It's 1347 // better to use i32 to avoid the loads. 1348 return MVT::f64; 1349 } 1350 } 1351 if (Subtarget->is64Bit() && Size >= 8) 1352 return MVT::i64; 1353 return MVT::i32; 1354} 1355 1356/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1357/// current function. The returned value is a member of the 1358/// MachineJumpTableInfo::JTEntryKind enum. 1359unsigned X86TargetLowering::getJumpTableEncoding() const { 1360 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1361 // symbol. 1362 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1363 Subtarget->isPICStyleGOT()) 1364 return MachineJumpTableInfo::EK_Custom32; 1365 1366 // Otherwise, use the normal jump table encoding heuristics. 1367 return TargetLowering::getJumpTableEncoding(); 1368} 1369 1370const MCExpr * 1371X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1372 const MachineBasicBlock *MBB, 1373 unsigned uid,MCContext &Ctx) const{ 1374 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1375 Subtarget->isPICStyleGOT()); 1376 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1377 // entries. 1378 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1379 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1380} 1381 1382/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1383/// jumptable. 1384SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1385 SelectionDAG &DAG) const { 1386 if (!Subtarget->is64Bit()) 1387 // This doesn't have DebugLoc associated with it, but is not really the 1388 // same as a Register. 1389 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1390 return Table; 1391} 1392 1393/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1394/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1395/// MCExpr. 1396const MCExpr *X86TargetLowering:: 1397getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1398 MCContext &Ctx) const { 1399 // X86-64 uses RIP relative addressing based on the jump table label. 1400 if (Subtarget->isPICStyleRIPRel()) 1401 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1402 1403 // Otherwise, the reference is relative to the PIC base. 1404 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1405} 1406 1407// FIXME: Why this routine is here? Move to RegInfo! 1408std::pair<const TargetRegisterClass*, uint8_t> 1409X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1410 const TargetRegisterClass *RRC = 0; 1411 uint8_t Cost = 1; 1412 switch (VT.getSimpleVT().SimpleTy) { 1413 default: 1414 return TargetLowering::findRepresentativeClass(VT); 1415 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1416 RRC = Subtarget->is64Bit() ? 1417 (const TargetRegisterClass*)&X86::GR64RegClass : 1418 (const TargetRegisterClass*)&X86::GR32RegClass; 1419 break; 1420 case MVT::x86mmx: 1421 RRC = &X86::VR64RegClass; 1422 break; 1423 case MVT::f32: case MVT::f64: 1424 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1425 case MVT::v4f32: case MVT::v2f64: 1426 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1427 case MVT::v4f64: 1428 RRC = &X86::VR128RegClass; 1429 break; 1430 } 1431 return std::make_pair(RRC, Cost); 1432} 1433 1434bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1435 unsigned &Offset) const { 1436 if (!Subtarget->isTargetLinux()) 1437 return false; 1438 1439 if (Subtarget->is64Bit()) { 1440 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1441 Offset = 0x28; 1442 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1443 AddressSpace = 256; 1444 else 1445 AddressSpace = 257; 1446 } else { 1447 // %gs:0x14 on i386 1448 Offset = 0x14; 1449 AddressSpace = 256; 1450 } 1451 return true; 1452} 1453 1454 1455//===----------------------------------------------------------------------===// 1456// Return Value Calling Convention Implementation 1457//===----------------------------------------------------------------------===// 1458 1459#include "X86GenCallingConv.inc" 1460 1461bool 1462X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1463 MachineFunction &MF, bool isVarArg, 1464 const SmallVectorImpl<ISD::OutputArg> &Outs, 1465 LLVMContext &Context) const { 1466 SmallVector<CCValAssign, 16> RVLocs; 1467 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1468 RVLocs, Context); 1469 return CCInfo.CheckReturn(Outs, RetCC_X86); 1470} 1471 1472SDValue 1473X86TargetLowering::LowerReturn(SDValue Chain, 1474 CallingConv::ID CallConv, bool isVarArg, 1475 const SmallVectorImpl<ISD::OutputArg> &Outs, 1476 const SmallVectorImpl<SDValue> &OutVals, 1477 DebugLoc dl, SelectionDAG &DAG) const { 1478 MachineFunction &MF = DAG.getMachineFunction(); 1479 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1480 1481 SmallVector<CCValAssign, 16> RVLocs; 1482 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1483 RVLocs, *DAG.getContext()); 1484 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1485 1486 // Add the regs to the liveout set for the function. 1487 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1488 for (unsigned i = 0; i != RVLocs.size(); ++i) 1489 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1490 MRI.addLiveOut(RVLocs[i].getLocReg()); 1491 1492 SDValue Flag; 1493 1494 SmallVector<SDValue, 6> RetOps; 1495 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1496 // Operand #1 = Bytes To Pop 1497 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1498 MVT::i16)); 1499 1500 // Copy the result values into the output registers. 1501 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1502 CCValAssign &VA = RVLocs[i]; 1503 assert(VA.isRegLoc() && "Can only return in registers!"); 1504 SDValue ValToCopy = OutVals[i]; 1505 EVT ValVT = ValToCopy.getValueType(); 1506 1507 // If this is x86-64, and we disabled SSE, we can't return FP values, 1508 // or SSE or MMX vectors. 1509 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1510 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1511 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1512 report_fatal_error("SSE register return with SSE disabled"); 1513 } 1514 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1515 // llvm-gcc has never done it right and no one has noticed, so this 1516 // should be OK for now. 1517 if (ValVT == MVT::f64 && 1518 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1519 report_fatal_error("SSE2 register return with SSE2 disabled"); 1520 1521 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1522 // the RET instruction and handled by the FP Stackifier. 1523 if (VA.getLocReg() == X86::ST0 || 1524 VA.getLocReg() == X86::ST1) { 1525 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1526 // change the value to the FP stack register class. 1527 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1528 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1529 RetOps.push_back(ValToCopy); 1530 // Don't emit a copytoreg. 1531 continue; 1532 } 1533 1534 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1535 // which is returned in RAX / RDX. 1536 if (Subtarget->is64Bit()) { 1537 if (ValVT == MVT::x86mmx) { 1538 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1539 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1540 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1541 ValToCopy); 1542 // If we don't have SSE2 available, convert to v4f32 so the generated 1543 // register is legal. 1544 if (!Subtarget->hasSSE2()) 1545 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1546 } 1547 } 1548 } 1549 1550 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1551 Flag = Chain.getValue(1); 1552 } 1553 1554 // The x86-64 ABI for returning structs by value requires that we copy 1555 // the sret argument into %rax for the return. We saved the argument into 1556 // a virtual register in the entry block, so now we copy the value out 1557 // and into %rax. 1558 if (Subtarget->is64Bit() && 1559 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1560 MachineFunction &MF = DAG.getMachineFunction(); 1561 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1562 unsigned Reg = FuncInfo->getSRetReturnReg(); 1563 assert(Reg && 1564 "SRetReturnReg should have been set in LowerFormalArguments()."); 1565 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1566 1567 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1568 Flag = Chain.getValue(1); 1569 1570 // RAX now acts like a return value. 1571 MRI.addLiveOut(X86::RAX); 1572 } 1573 1574 RetOps[0] = Chain; // Update chain. 1575 1576 // Add the flag if we have it. 1577 if (Flag.getNode()) 1578 RetOps.push_back(Flag); 1579 1580 return DAG.getNode(X86ISD::RET_FLAG, dl, 1581 MVT::Other, &RetOps[0], RetOps.size()); 1582} 1583 1584bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1585 if (N->getNumValues() != 1) 1586 return false; 1587 if (!N->hasNUsesOfValue(1, 0)) 1588 return false; 1589 1590 SDValue TCChain = Chain; 1591 SDNode *Copy = *N->use_begin(); 1592 if (Copy->getOpcode() == ISD::CopyToReg) { 1593 // If the copy has a glue operand, we conservatively assume it isn't safe to 1594 // perform a tail call. 1595 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1596 return false; 1597 TCChain = Copy->getOperand(0); 1598 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1599 return false; 1600 1601 bool HasRet = false; 1602 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1603 UI != UE; ++UI) { 1604 if (UI->getOpcode() != X86ISD::RET_FLAG) 1605 return false; 1606 HasRet = true; 1607 } 1608 1609 if (!HasRet) 1610 return false; 1611 1612 Chain = TCChain; 1613 return true; 1614} 1615 1616EVT 1617X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1618 ISD::NodeType ExtendKind) const { 1619 MVT ReturnMVT; 1620 // TODO: Is this also valid on 32-bit? 1621 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1622 ReturnMVT = MVT::i8; 1623 else 1624 ReturnMVT = MVT::i32; 1625 1626 EVT MinVT = getRegisterType(Context, ReturnMVT); 1627 return VT.bitsLT(MinVT) ? MinVT : VT; 1628} 1629 1630/// LowerCallResult - Lower the result values of a call into the 1631/// appropriate copies out of appropriate physical registers. 1632/// 1633SDValue 1634X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1635 CallingConv::ID CallConv, bool isVarArg, 1636 const SmallVectorImpl<ISD::InputArg> &Ins, 1637 DebugLoc dl, SelectionDAG &DAG, 1638 SmallVectorImpl<SDValue> &InVals) const { 1639 1640 // Assign locations to each value returned by this call. 1641 SmallVector<CCValAssign, 16> RVLocs; 1642 bool Is64Bit = Subtarget->is64Bit(); 1643 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1644 getTargetMachine(), RVLocs, *DAG.getContext()); 1645 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1646 1647 // Copy all of the result registers out of their specified physreg. 1648 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1649 CCValAssign &VA = RVLocs[i]; 1650 EVT CopyVT = VA.getValVT(); 1651 1652 // If this is x86-64, and we disabled SSE, we can't return FP values 1653 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1654 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1655 report_fatal_error("SSE register return with SSE disabled"); 1656 } 1657 1658 SDValue Val; 1659 1660 // If this is a call to a function that returns an fp value on the floating 1661 // point stack, we must guarantee the the value is popped from the stack, so 1662 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1663 // if the return value is not used. We use the FpPOP_RETVAL instruction 1664 // instead. 1665 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1666 // If we prefer to use the value in xmm registers, copy it out as f80 and 1667 // use a truncate to move it from fp stack reg to xmm reg. 1668 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1669 SDValue Ops[] = { Chain, InFlag }; 1670 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1671 MVT::Other, MVT::Glue, Ops, 2), 1); 1672 Val = Chain.getValue(0); 1673 1674 // Round the f80 to the right size, which also moves it to the appropriate 1675 // xmm register. 1676 if (CopyVT != VA.getValVT()) 1677 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1678 // This truncation won't change the value. 1679 DAG.getIntPtrConstant(1)); 1680 } else { 1681 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1682 CopyVT, InFlag).getValue(1); 1683 Val = Chain.getValue(0); 1684 } 1685 InFlag = Chain.getValue(2); 1686 InVals.push_back(Val); 1687 } 1688 1689 return Chain; 1690} 1691 1692 1693//===----------------------------------------------------------------------===// 1694// C & StdCall & Fast Calling Convention implementation 1695//===----------------------------------------------------------------------===// 1696// StdCall calling convention seems to be standard for many Windows' API 1697// routines and around. It differs from C calling convention just a little: 1698// callee should clean up the stack, not caller. Symbols should be also 1699// decorated in some fancy way :) It doesn't support any vector arguments. 1700// For info on fast calling convention see Fast Calling Convention (tail call) 1701// implementation LowerX86_32FastCCCallTo. 1702 1703/// CallIsStructReturn - Determines whether a call uses struct return 1704/// semantics. 1705static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1706 if (Outs.empty()) 1707 return false; 1708 1709 return Outs[0].Flags.isSRet(); 1710} 1711 1712/// ArgsAreStructReturn - Determines whether a function uses struct 1713/// return semantics. 1714static bool 1715ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1716 if (Ins.empty()) 1717 return false; 1718 1719 return Ins[0].Flags.isSRet(); 1720} 1721 1722/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1723/// by "Src" to address "Dst" with size and alignment information specified by 1724/// the specific parameter attribute. The copy will be passed as a byval 1725/// function parameter. 1726static SDValue 1727CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1728 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1729 DebugLoc dl) { 1730 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1731 1732 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1733 /*isVolatile*/false, /*AlwaysInline=*/true, 1734 MachinePointerInfo(), MachinePointerInfo()); 1735} 1736 1737/// IsTailCallConvention - Return true if the calling convention is one that 1738/// supports tail call optimization. 1739static bool IsTailCallConvention(CallingConv::ID CC) { 1740 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1741} 1742 1743bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1744 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1745 return false; 1746 1747 CallSite CS(CI); 1748 CallingConv::ID CalleeCC = CS.getCallingConv(); 1749 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1750 return false; 1751 1752 return true; 1753} 1754 1755/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1756/// a tailcall target by changing its ABI. 1757static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1758 bool GuaranteedTailCallOpt) { 1759 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1760} 1761 1762SDValue 1763X86TargetLowering::LowerMemArgument(SDValue Chain, 1764 CallingConv::ID CallConv, 1765 const SmallVectorImpl<ISD::InputArg> &Ins, 1766 DebugLoc dl, SelectionDAG &DAG, 1767 const CCValAssign &VA, 1768 MachineFrameInfo *MFI, 1769 unsigned i) const { 1770 // Create the nodes corresponding to a load from this parameter slot. 1771 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1772 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1773 getTargetMachine().Options.GuaranteedTailCallOpt); 1774 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1775 EVT ValVT; 1776 1777 // If value is passed by pointer we have address passed instead of the value 1778 // itself. 1779 if (VA.getLocInfo() == CCValAssign::Indirect) 1780 ValVT = VA.getLocVT(); 1781 else 1782 ValVT = VA.getValVT(); 1783 1784 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1785 // changed with more analysis. 1786 // In case of tail call optimization mark all arguments mutable. Since they 1787 // could be overwritten by lowering of arguments in case of a tail call. 1788 if (Flags.isByVal()) { 1789 unsigned Bytes = Flags.getByValSize(); 1790 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1791 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1792 return DAG.getFrameIndex(FI, getPointerTy()); 1793 } else { 1794 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1795 VA.getLocMemOffset(), isImmutable); 1796 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1797 return DAG.getLoad(ValVT, dl, Chain, FIN, 1798 MachinePointerInfo::getFixedStack(FI), 1799 false, false, false, 0); 1800 } 1801} 1802 1803SDValue 1804X86TargetLowering::LowerFormalArguments(SDValue Chain, 1805 CallingConv::ID CallConv, 1806 bool isVarArg, 1807 const SmallVectorImpl<ISD::InputArg> &Ins, 1808 DebugLoc dl, 1809 SelectionDAG &DAG, 1810 SmallVectorImpl<SDValue> &InVals) 1811 const { 1812 MachineFunction &MF = DAG.getMachineFunction(); 1813 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1814 1815 const Function* Fn = MF.getFunction(); 1816 if (Fn->hasExternalLinkage() && 1817 Subtarget->isTargetCygMing() && 1818 Fn->getName() == "main") 1819 FuncInfo->setForceFramePointer(true); 1820 1821 MachineFrameInfo *MFI = MF.getFrameInfo(); 1822 bool Is64Bit = Subtarget->is64Bit(); 1823 bool IsWindows = Subtarget->isTargetWindows(); 1824 bool IsWin64 = Subtarget->isTargetWin64(); 1825 1826 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1827 "Var args not supported with calling convention fastcc or ghc"); 1828 1829 // Assign locations to all of the incoming arguments. 1830 SmallVector<CCValAssign, 16> ArgLocs; 1831 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1832 ArgLocs, *DAG.getContext()); 1833 1834 // Allocate shadow area for Win64 1835 if (IsWin64) { 1836 CCInfo.AllocateStack(32, 8); 1837 } 1838 1839 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1840 1841 unsigned LastVal = ~0U; 1842 SDValue ArgValue; 1843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1844 CCValAssign &VA = ArgLocs[i]; 1845 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1846 // places. 1847 assert(VA.getValNo() != LastVal && 1848 "Don't support value assigned to multiple locs yet"); 1849 (void)LastVal; 1850 LastVal = VA.getValNo(); 1851 1852 if (VA.isRegLoc()) { 1853 EVT RegVT = VA.getLocVT(); 1854 const TargetRegisterClass *RC; 1855 if (RegVT == MVT::i32) 1856 RC = &X86::GR32RegClass; 1857 else if (Is64Bit && RegVT == MVT::i64) 1858 RC = &X86::GR64RegClass; 1859 else if (RegVT == MVT::f32) 1860 RC = &X86::FR32RegClass; 1861 else if (RegVT == MVT::f64) 1862 RC = &X86::FR64RegClass; 1863 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1864 RC = &X86::VR256RegClass; 1865 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1866 RC = &X86::VR128RegClass; 1867 else if (RegVT == MVT::x86mmx) 1868 RC = &X86::VR64RegClass; 1869 else 1870 llvm_unreachable("Unknown argument type!"); 1871 1872 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1873 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1874 1875 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1876 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1877 // right size. 1878 if (VA.getLocInfo() == CCValAssign::SExt) 1879 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1880 DAG.getValueType(VA.getValVT())); 1881 else if (VA.getLocInfo() == CCValAssign::ZExt) 1882 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1883 DAG.getValueType(VA.getValVT())); 1884 else if (VA.getLocInfo() == CCValAssign::BCvt) 1885 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1886 1887 if (VA.isExtInLoc()) { 1888 // Handle MMX values passed in XMM regs. 1889 if (RegVT.isVector()) { 1890 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1891 ArgValue); 1892 } else 1893 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1894 } 1895 } else { 1896 assert(VA.isMemLoc()); 1897 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1898 } 1899 1900 // If value is passed via pointer - do a load. 1901 if (VA.getLocInfo() == CCValAssign::Indirect) 1902 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1903 MachinePointerInfo(), false, false, false, 0); 1904 1905 InVals.push_back(ArgValue); 1906 } 1907 1908 // The x86-64 ABI for returning structs by value requires that we copy 1909 // the sret argument into %rax for the return. Save the argument into 1910 // a virtual register so that we can access it from the return points. 1911 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1912 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1913 unsigned Reg = FuncInfo->getSRetReturnReg(); 1914 if (!Reg) { 1915 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1916 FuncInfo->setSRetReturnReg(Reg); 1917 } 1918 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1919 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1920 } 1921 1922 unsigned StackSize = CCInfo.getNextStackOffset(); 1923 // Align stack specially for tail calls. 1924 if (FuncIsMadeTailCallSafe(CallConv, 1925 MF.getTarget().Options.GuaranteedTailCallOpt)) 1926 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1927 1928 // If the function takes variable number of arguments, make a frame index for 1929 // the start of the first vararg value... for expansion of llvm.va_start. 1930 if (isVarArg) { 1931 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1932 CallConv != CallingConv::X86_ThisCall)) { 1933 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1934 } 1935 if (Is64Bit) { 1936 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1937 1938 // FIXME: We should really autogenerate these arrays 1939 static const uint16_t GPR64ArgRegsWin64[] = { 1940 X86::RCX, X86::RDX, X86::R8, X86::R9 1941 }; 1942 static const uint16_t GPR64ArgRegs64Bit[] = { 1943 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1944 }; 1945 static const uint16_t XMMArgRegs64Bit[] = { 1946 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1947 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1948 }; 1949 const uint16_t *GPR64ArgRegs; 1950 unsigned NumXMMRegs = 0; 1951 1952 if (IsWin64) { 1953 // The XMM registers which might contain var arg parameters are shadowed 1954 // in their paired GPR. So we only need to save the GPR to their home 1955 // slots. 1956 TotalNumIntRegs = 4; 1957 GPR64ArgRegs = GPR64ArgRegsWin64; 1958 } else { 1959 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1960 GPR64ArgRegs = GPR64ArgRegs64Bit; 1961 1962 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1963 TotalNumXMMRegs); 1964 } 1965 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1966 TotalNumIntRegs); 1967 1968 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1969 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1970 "SSE register cannot be used when SSE is disabled!"); 1971 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1972 NoImplicitFloatOps) && 1973 "SSE register cannot be used when SSE is disabled!"); 1974 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1975 !Subtarget->hasSSE1()) 1976 // Kernel mode asks for SSE to be disabled, so don't push them 1977 // on the stack. 1978 TotalNumXMMRegs = 0; 1979 1980 if (IsWin64) { 1981 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1982 // Get to the caller-allocated home save location. Add 8 to account 1983 // for the return address. 1984 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1985 FuncInfo->setRegSaveFrameIndex( 1986 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1987 // Fixup to set vararg frame on shadow area (4 x i64). 1988 if (NumIntRegs < 4) 1989 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1990 } else { 1991 // For X86-64, if there are vararg parameters that are passed via 1992 // registers, then we must store them to their spots on the stack so 1993 // they may be loaded by deferencing the result of va_next. 1994 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1995 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1996 FuncInfo->setRegSaveFrameIndex( 1997 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1998 false)); 1999 } 2000 2001 // Store the integer parameter registers. 2002 SmallVector<SDValue, 8> MemOps; 2003 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2004 getPointerTy()); 2005 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2006 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2007 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2008 DAG.getIntPtrConstant(Offset)); 2009 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2010 &X86::GR64RegClass); 2011 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2012 SDValue Store = 2013 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2014 MachinePointerInfo::getFixedStack( 2015 FuncInfo->getRegSaveFrameIndex(), Offset), 2016 false, false, 0); 2017 MemOps.push_back(Store); 2018 Offset += 8; 2019 } 2020 2021 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2022 // Now store the XMM (fp + vector) parameter registers. 2023 SmallVector<SDValue, 11> SaveXMMOps; 2024 SaveXMMOps.push_back(Chain); 2025 2026 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2027 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2028 SaveXMMOps.push_back(ALVal); 2029 2030 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2031 FuncInfo->getRegSaveFrameIndex())); 2032 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2033 FuncInfo->getVarArgsFPOffset())); 2034 2035 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2036 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2037 &X86::VR128RegClass); 2038 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2039 SaveXMMOps.push_back(Val); 2040 } 2041 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2042 MVT::Other, 2043 &SaveXMMOps[0], SaveXMMOps.size())); 2044 } 2045 2046 if (!MemOps.empty()) 2047 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2048 &MemOps[0], MemOps.size()); 2049 } 2050 } 2051 2052 // Some CCs need callee pop. 2053 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2054 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2055 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2056 } else { 2057 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2058 // If this is an sret function, the return should pop the hidden pointer. 2059 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2060 ArgsAreStructReturn(Ins)) 2061 FuncInfo->setBytesToPopOnReturn(4); 2062 } 2063 2064 if (!Is64Bit) { 2065 // RegSaveFrameIndex is X86-64 only. 2066 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2067 if (CallConv == CallingConv::X86_FastCall || 2068 CallConv == CallingConv::X86_ThisCall) 2069 // fastcc functions can't have varargs. 2070 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2071 } 2072 2073 FuncInfo->setArgumentStackSize(StackSize); 2074 2075 return Chain; 2076} 2077 2078SDValue 2079X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2080 SDValue StackPtr, SDValue Arg, 2081 DebugLoc dl, SelectionDAG &DAG, 2082 const CCValAssign &VA, 2083 ISD::ArgFlagsTy Flags) const { 2084 unsigned LocMemOffset = VA.getLocMemOffset(); 2085 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2086 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2087 if (Flags.isByVal()) 2088 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2089 2090 return DAG.getStore(Chain, dl, Arg, PtrOff, 2091 MachinePointerInfo::getStack(LocMemOffset), 2092 false, false, 0); 2093} 2094 2095/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2096/// optimization is performed and it is required. 2097SDValue 2098X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2099 SDValue &OutRetAddr, SDValue Chain, 2100 bool IsTailCall, bool Is64Bit, 2101 int FPDiff, DebugLoc dl) const { 2102 // Adjust the Return address stack slot. 2103 EVT VT = getPointerTy(); 2104 OutRetAddr = getReturnAddressFrameIndex(DAG); 2105 2106 // Load the "old" Return address. 2107 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2108 false, false, false, 0); 2109 return SDValue(OutRetAddr.getNode(), 1); 2110} 2111 2112/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2113/// optimization is performed and it is required (FPDiff!=0). 2114static SDValue 2115EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2116 SDValue Chain, SDValue RetAddrFrIdx, 2117 bool Is64Bit, int FPDiff, DebugLoc dl) { 2118 // Store the return address to the appropriate stack slot. 2119 if (!FPDiff) return Chain; 2120 // Calculate the new stack slot for the return address. 2121 int SlotSize = Is64Bit ? 8 : 4; 2122 int NewReturnAddrFI = 2123 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2124 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2125 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2126 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2127 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2128 false, false, 0); 2129 return Chain; 2130} 2131 2132SDValue 2133X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2134 CallingConv::ID CallConv, bool isVarArg, 2135 bool doesNotRet, bool &isTailCall, 2136 const SmallVectorImpl<ISD::OutputArg> &Outs, 2137 const SmallVectorImpl<SDValue> &OutVals, 2138 const SmallVectorImpl<ISD::InputArg> &Ins, 2139 DebugLoc dl, SelectionDAG &DAG, 2140 SmallVectorImpl<SDValue> &InVals) const { 2141 MachineFunction &MF = DAG.getMachineFunction(); 2142 bool Is64Bit = Subtarget->is64Bit(); 2143 bool IsWin64 = Subtarget->isTargetWin64(); 2144 bool IsWindows = Subtarget->isTargetWindows(); 2145 bool IsStructRet = CallIsStructReturn(Outs); 2146 bool IsSibcall = false; 2147 2148 if (MF.getTarget().Options.DisableTailCalls) 2149 isTailCall = false; 2150 2151 if (isTailCall) { 2152 // Check if it's really possible to do a tail call. 2153 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2154 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2155 Outs, OutVals, Ins, DAG); 2156 2157 // Sibcalls are automatically detected tailcalls which do not require 2158 // ABI changes. 2159 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2160 IsSibcall = true; 2161 2162 if (isTailCall) 2163 ++NumTailCalls; 2164 } 2165 2166 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2167 "Var args not supported with calling convention fastcc or ghc"); 2168 2169 // Analyze operands of the call, assigning locations to each operand. 2170 SmallVector<CCValAssign, 16> ArgLocs; 2171 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2172 ArgLocs, *DAG.getContext()); 2173 2174 // Allocate shadow area for Win64 2175 if (IsWin64) { 2176 CCInfo.AllocateStack(32, 8); 2177 } 2178 2179 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2180 2181 // Get a count of how many bytes are to be pushed on the stack. 2182 unsigned NumBytes = CCInfo.getNextStackOffset(); 2183 if (IsSibcall) 2184 // This is a sibcall. The memory operands are available in caller's 2185 // own caller's stack. 2186 NumBytes = 0; 2187 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2188 IsTailCallConvention(CallConv)) 2189 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2190 2191 int FPDiff = 0; 2192 if (isTailCall && !IsSibcall) { 2193 // Lower arguments at fp - stackoffset + fpdiff. 2194 unsigned NumBytesCallerPushed = 2195 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2196 FPDiff = NumBytesCallerPushed - NumBytes; 2197 2198 // Set the delta of movement of the returnaddr stackslot. 2199 // But only set if delta is greater than previous delta. 2200 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2201 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2202 } 2203 2204 if (!IsSibcall) 2205 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2206 2207 SDValue RetAddrFrIdx; 2208 // Load return address for tail calls. 2209 if (isTailCall && FPDiff) 2210 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2211 Is64Bit, FPDiff, dl); 2212 2213 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2214 SmallVector<SDValue, 8> MemOpChains; 2215 SDValue StackPtr; 2216 2217 // Walk the register/memloc assignments, inserting copies/loads. In the case 2218 // of tail call optimization arguments are handle later. 2219 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2220 CCValAssign &VA = ArgLocs[i]; 2221 EVT RegVT = VA.getLocVT(); 2222 SDValue Arg = OutVals[i]; 2223 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2224 bool isByVal = Flags.isByVal(); 2225 2226 // Promote the value if needed. 2227 switch (VA.getLocInfo()) { 2228 default: llvm_unreachable("Unknown loc info!"); 2229 case CCValAssign::Full: break; 2230 case CCValAssign::SExt: 2231 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2232 break; 2233 case CCValAssign::ZExt: 2234 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2235 break; 2236 case CCValAssign::AExt: 2237 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2238 // Special case: passing MMX values in XMM registers. 2239 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2240 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2241 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2242 } else 2243 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2244 break; 2245 case CCValAssign::BCvt: 2246 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2247 break; 2248 case CCValAssign::Indirect: { 2249 // Store the argument. 2250 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2251 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2252 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2253 MachinePointerInfo::getFixedStack(FI), 2254 false, false, 0); 2255 Arg = SpillSlot; 2256 break; 2257 } 2258 } 2259 2260 if (VA.isRegLoc()) { 2261 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2262 if (isVarArg && IsWin64) { 2263 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2264 // shadow reg if callee is a varargs function. 2265 unsigned ShadowReg = 0; 2266 switch (VA.getLocReg()) { 2267 case X86::XMM0: ShadowReg = X86::RCX; break; 2268 case X86::XMM1: ShadowReg = X86::RDX; break; 2269 case X86::XMM2: ShadowReg = X86::R8; break; 2270 case X86::XMM3: ShadowReg = X86::R9; break; 2271 } 2272 if (ShadowReg) 2273 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2274 } 2275 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2276 assert(VA.isMemLoc()); 2277 if (StackPtr.getNode() == 0) 2278 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2279 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2280 dl, DAG, VA, Flags)); 2281 } 2282 } 2283 2284 if (!MemOpChains.empty()) 2285 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2286 &MemOpChains[0], MemOpChains.size()); 2287 2288 // Build a sequence of copy-to-reg nodes chained together with token chain 2289 // and flag operands which copy the outgoing args into registers. 2290 SDValue InFlag; 2291 // Tail call byval lowering might overwrite argument registers so in case of 2292 // tail call optimization the copies to registers are lowered later. 2293 if (!isTailCall) 2294 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2295 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2296 RegsToPass[i].second, InFlag); 2297 InFlag = Chain.getValue(1); 2298 } 2299 2300 if (Subtarget->isPICStyleGOT()) { 2301 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2302 // GOT pointer. 2303 if (!isTailCall) { 2304 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2305 DAG.getNode(X86ISD::GlobalBaseReg, 2306 DebugLoc(), getPointerTy()), 2307 InFlag); 2308 InFlag = Chain.getValue(1); 2309 } else { 2310 // If we are tail calling and generating PIC/GOT style code load the 2311 // address of the callee into ECX. The value in ecx is used as target of 2312 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2313 // for tail calls on PIC/GOT architectures. Normally we would just put the 2314 // address of GOT into ebx and then call target@PLT. But for tail calls 2315 // ebx would be restored (since ebx is callee saved) before jumping to the 2316 // target@PLT. 2317 2318 // Note: The actual moving to ECX is done further down. 2319 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2320 if (G && !G->getGlobal()->hasHiddenVisibility() && 2321 !G->getGlobal()->hasProtectedVisibility()) 2322 Callee = LowerGlobalAddress(Callee, DAG); 2323 else if (isa<ExternalSymbolSDNode>(Callee)) 2324 Callee = LowerExternalSymbol(Callee, DAG); 2325 } 2326 } 2327 2328 if (Is64Bit && isVarArg && !IsWin64) { 2329 // From AMD64 ABI document: 2330 // For calls that may call functions that use varargs or stdargs 2331 // (prototype-less calls or calls to functions containing ellipsis (...) in 2332 // the declaration) %al is used as hidden argument to specify the number 2333 // of SSE registers used. The contents of %al do not need to match exactly 2334 // the number of registers, but must be an ubound on the number of SSE 2335 // registers used and is in the range 0 - 8 inclusive. 2336 2337 // Count the number of XMM registers allocated. 2338 static const uint16_t XMMArgRegs[] = { 2339 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2340 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2341 }; 2342 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2343 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2344 && "SSE registers cannot be used when SSE is disabled"); 2345 2346 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2347 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2348 InFlag = Chain.getValue(1); 2349 } 2350 2351 2352 // For tail calls lower the arguments to the 'real' stack slot. 2353 if (isTailCall) { 2354 // Force all the incoming stack arguments to be loaded from the stack 2355 // before any new outgoing arguments are stored to the stack, because the 2356 // outgoing stack slots may alias the incoming argument stack slots, and 2357 // the alias isn't otherwise explicit. This is slightly more conservative 2358 // than necessary, because it means that each store effectively depends 2359 // on every argument instead of just those arguments it would clobber. 2360 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2361 2362 SmallVector<SDValue, 8> MemOpChains2; 2363 SDValue FIN; 2364 int FI = 0; 2365 // Do not flag preceding copytoreg stuff together with the following stuff. 2366 InFlag = SDValue(); 2367 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2368 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2369 CCValAssign &VA = ArgLocs[i]; 2370 if (VA.isRegLoc()) 2371 continue; 2372 assert(VA.isMemLoc()); 2373 SDValue Arg = OutVals[i]; 2374 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2375 // Create frame index. 2376 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2377 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2378 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2379 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2380 2381 if (Flags.isByVal()) { 2382 // Copy relative to framepointer. 2383 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2384 if (StackPtr.getNode() == 0) 2385 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2386 getPointerTy()); 2387 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2388 2389 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2390 ArgChain, 2391 Flags, DAG, dl)); 2392 } else { 2393 // Store relative to framepointer. 2394 MemOpChains2.push_back( 2395 DAG.getStore(ArgChain, dl, Arg, FIN, 2396 MachinePointerInfo::getFixedStack(FI), 2397 false, false, 0)); 2398 } 2399 } 2400 } 2401 2402 if (!MemOpChains2.empty()) 2403 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2404 &MemOpChains2[0], MemOpChains2.size()); 2405 2406 // Copy arguments to their registers. 2407 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2408 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2409 RegsToPass[i].second, InFlag); 2410 InFlag = Chain.getValue(1); 2411 } 2412 InFlag =SDValue(); 2413 2414 // Store the return address to the appropriate stack slot. 2415 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2416 FPDiff, dl); 2417 } 2418 2419 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2420 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2421 // In the 64-bit large code model, we have to make all calls 2422 // through a register, since the call instruction's 32-bit 2423 // pc-relative offset may not be large enough to hold the whole 2424 // address. 2425 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2426 // If the callee is a GlobalAddress node (quite common, every direct call 2427 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2428 // it. 2429 2430 // We should use extra load for direct calls to dllimported functions in 2431 // non-JIT mode. 2432 const GlobalValue *GV = G->getGlobal(); 2433 if (!GV->hasDLLImportLinkage()) { 2434 unsigned char OpFlags = 0; 2435 bool ExtraLoad = false; 2436 unsigned WrapperKind = ISD::DELETED_NODE; 2437 2438 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2439 // external symbols most go through the PLT in PIC mode. If the symbol 2440 // has hidden or protected visibility, or if it is static or local, then 2441 // we don't need to use the PLT - we can directly call it. 2442 if (Subtarget->isTargetELF() && 2443 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2444 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2445 OpFlags = X86II::MO_PLT; 2446 } else if (Subtarget->isPICStyleStubAny() && 2447 (GV->isDeclaration() || GV->isWeakForLinker()) && 2448 (!Subtarget->getTargetTriple().isMacOSX() || 2449 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2450 // PC-relative references to external symbols should go through $stub, 2451 // unless we're building with the leopard linker or later, which 2452 // automatically synthesizes these stubs. 2453 OpFlags = X86II::MO_DARWIN_STUB; 2454 } else if (Subtarget->isPICStyleRIPRel() && 2455 isa<Function>(GV) && 2456 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2457 // If the function is marked as non-lazy, generate an indirect call 2458 // which loads from the GOT directly. This avoids runtime overhead 2459 // at the cost of eager binding (and one extra byte of encoding). 2460 OpFlags = X86II::MO_GOTPCREL; 2461 WrapperKind = X86ISD::WrapperRIP; 2462 ExtraLoad = true; 2463 } 2464 2465 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2466 G->getOffset(), OpFlags); 2467 2468 // Add a wrapper if needed. 2469 if (WrapperKind != ISD::DELETED_NODE) 2470 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2471 // Add extra indirection if needed. 2472 if (ExtraLoad) 2473 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2474 MachinePointerInfo::getGOT(), 2475 false, false, false, 0); 2476 } 2477 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2478 unsigned char OpFlags = 0; 2479 2480 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2481 // external symbols should go through the PLT. 2482 if (Subtarget->isTargetELF() && 2483 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2484 OpFlags = X86II::MO_PLT; 2485 } else if (Subtarget->isPICStyleStubAny() && 2486 (!Subtarget->getTargetTriple().isMacOSX() || 2487 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2488 // PC-relative references to external symbols should go through $stub, 2489 // unless we're building with the leopard linker or later, which 2490 // automatically synthesizes these stubs. 2491 OpFlags = X86II::MO_DARWIN_STUB; 2492 } 2493 2494 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2495 OpFlags); 2496 } 2497 2498 // Returns a chain & a flag for retval copy to use. 2499 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2500 SmallVector<SDValue, 8> Ops; 2501 2502 if (!IsSibcall && isTailCall) { 2503 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2504 DAG.getIntPtrConstant(0, true), InFlag); 2505 InFlag = Chain.getValue(1); 2506 } 2507 2508 Ops.push_back(Chain); 2509 Ops.push_back(Callee); 2510 2511 if (isTailCall) 2512 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2513 2514 // Add argument registers to the end of the list so that they are known live 2515 // into the call. 2516 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2517 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2518 RegsToPass[i].second.getValueType())); 2519 2520 // Add an implicit use GOT pointer in EBX. 2521 if (!isTailCall && Subtarget->isPICStyleGOT()) 2522 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2523 2524 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2525 if (Is64Bit && isVarArg && !IsWin64) 2526 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2527 2528 // Add a register mask operand representing the call-preserved registers. 2529 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2530 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2531 assert(Mask && "Missing call preserved mask for calling convention"); 2532 Ops.push_back(DAG.getRegisterMask(Mask)); 2533 2534 if (InFlag.getNode()) 2535 Ops.push_back(InFlag); 2536 2537 if (isTailCall) { 2538 // We used to do: 2539 //// If this is the first return lowered for this function, add the regs 2540 //// to the liveout set for the function. 2541 // This isn't right, although it's probably harmless on x86; liveouts 2542 // should be computed from returns not tail calls. Consider a void 2543 // function making a tail call to a function returning int. 2544 return DAG.getNode(X86ISD::TC_RETURN, dl, 2545 NodeTys, &Ops[0], Ops.size()); 2546 } 2547 2548 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2549 InFlag = Chain.getValue(1); 2550 2551 // Create the CALLSEQ_END node. 2552 unsigned NumBytesForCalleeToPush; 2553 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2554 getTargetMachine().Options.GuaranteedTailCallOpt)) 2555 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2556 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2557 IsStructRet) 2558 // If this is a call to a struct-return function, the callee 2559 // pops the hidden struct pointer, so we have to push it back. 2560 // This is common for Darwin/X86, Linux & Mingw32 targets. 2561 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2562 NumBytesForCalleeToPush = 4; 2563 else 2564 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2565 2566 // Returns a flag for retval copy to use. 2567 if (!IsSibcall) { 2568 Chain = DAG.getCALLSEQ_END(Chain, 2569 DAG.getIntPtrConstant(NumBytes, true), 2570 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2571 true), 2572 InFlag); 2573 InFlag = Chain.getValue(1); 2574 } 2575 2576 // Handle result values, copying them out of physregs into vregs that we 2577 // return. 2578 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2579 Ins, dl, DAG, InVals); 2580} 2581 2582 2583//===----------------------------------------------------------------------===// 2584// Fast Calling Convention (tail call) implementation 2585//===----------------------------------------------------------------------===// 2586 2587// Like std call, callee cleans arguments, convention except that ECX is 2588// reserved for storing the tail called function address. Only 2 registers are 2589// free for argument passing (inreg). Tail call optimization is performed 2590// provided: 2591// * tailcallopt is enabled 2592// * caller/callee are fastcc 2593// On X86_64 architecture with GOT-style position independent code only local 2594// (within module) calls are supported at the moment. 2595// To keep the stack aligned according to platform abi the function 2596// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2597// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2598// If a tail called function callee has more arguments than the caller the 2599// caller needs to make sure that there is room to move the RETADDR to. This is 2600// achieved by reserving an area the size of the argument delta right after the 2601// original REtADDR, but before the saved framepointer or the spilled registers 2602// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2603// stack layout: 2604// arg1 2605// arg2 2606// RETADDR 2607// [ new RETADDR 2608// move area ] 2609// (possible EBP) 2610// ESI 2611// EDI 2612// local1 .. 2613 2614/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2615/// for a 16 byte align requirement. 2616unsigned 2617X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2618 SelectionDAG& DAG) const { 2619 MachineFunction &MF = DAG.getMachineFunction(); 2620 const TargetMachine &TM = MF.getTarget(); 2621 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2622 unsigned StackAlignment = TFI.getStackAlignment(); 2623 uint64_t AlignMask = StackAlignment - 1; 2624 int64_t Offset = StackSize; 2625 uint64_t SlotSize = TD->getPointerSize(); 2626 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2627 // Number smaller than 12 so just add the difference. 2628 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2629 } else { 2630 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2631 Offset = ((~AlignMask) & Offset) + StackAlignment + 2632 (StackAlignment-SlotSize); 2633 } 2634 return Offset; 2635} 2636 2637/// MatchingStackOffset - Return true if the given stack call argument is 2638/// already available in the same position (relatively) of the caller's 2639/// incoming argument stack. 2640static 2641bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2642 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2643 const X86InstrInfo *TII) { 2644 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2645 int FI = INT_MAX; 2646 if (Arg.getOpcode() == ISD::CopyFromReg) { 2647 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2648 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2649 return false; 2650 MachineInstr *Def = MRI->getVRegDef(VR); 2651 if (!Def) 2652 return false; 2653 if (!Flags.isByVal()) { 2654 if (!TII->isLoadFromStackSlot(Def, FI)) 2655 return false; 2656 } else { 2657 unsigned Opcode = Def->getOpcode(); 2658 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2659 Def->getOperand(1).isFI()) { 2660 FI = Def->getOperand(1).getIndex(); 2661 Bytes = Flags.getByValSize(); 2662 } else 2663 return false; 2664 } 2665 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2666 if (Flags.isByVal()) 2667 // ByVal argument is passed in as a pointer but it's now being 2668 // dereferenced. e.g. 2669 // define @foo(%struct.X* %A) { 2670 // tail call @bar(%struct.X* byval %A) 2671 // } 2672 return false; 2673 SDValue Ptr = Ld->getBasePtr(); 2674 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2675 if (!FINode) 2676 return false; 2677 FI = FINode->getIndex(); 2678 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2679 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2680 FI = FINode->getIndex(); 2681 Bytes = Flags.getByValSize(); 2682 } else 2683 return false; 2684 2685 assert(FI != INT_MAX); 2686 if (!MFI->isFixedObjectIndex(FI)) 2687 return false; 2688 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2689} 2690 2691/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2692/// for tail call optimization. Targets which want to do tail call 2693/// optimization should implement this function. 2694bool 2695X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2696 CallingConv::ID CalleeCC, 2697 bool isVarArg, 2698 bool isCalleeStructRet, 2699 bool isCallerStructRet, 2700 const SmallVectorImpl<ISD::OutputArg> &Outs, 2701 const SmallVectorImpl<SDValue> &OutVals, 2702 const SmallVectorImpl<ISD::InputArg> &Ins, 2703 SelectionDAG& DAG) const { 2704 if (!IsTailCallConvention(CalleeCC) && 2705 CalleeCC != CallingConv::C) 2706 return false; 2707 2708 // If -tailcallopt is specified, make fastcc functions tail-callable. 2709 const MachineFunction &MF = DAG.getMachineFunction(); 2710 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2711 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2712 bool CCMatch = CallerCC == CalleeCC; 2713 2714 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2715 if (IsTailCallConvention(CalleeCC) && CCMatch) 2716 return true; 2717 return false; 2718 } 2719 2720 // Look for obvious safe cases to perform tail call optimization that do not 2721 // require ABI changes. This is what gcc calls sibcall. 2722 2723 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2724 // emit a special epilogue. 2725 if (RegInfo->needsStackRealignment(MF)) 2726 return false; 2727 2728 // Also avoid sibcall optimization if either caller or callee uses struct 2729 // return semantics. 2730 if (isCalleeStructRet || isCallerStructRet) 2731 return false; 2732 2733 // An stdcall caller is expected to clean up its arguments; the callee 2734 // isn't going to do that. 2735 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2736 return false; 2737 2738 // Do not sibcall optimize vararg calls unless all arguments are passed via 2739 // registers. 2740 if (isVarArg && !Outs.empty()) { 2741 2742 // Optimizing for varargs on Win64 is unlikely to be safe without 2743 // additional testing. 2744 if (Subtarget->isTargetWin64()) 2745 return false; 2746 2747 SmallVector<CCValAssign, 16> ArgLocs; 2748 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2749 getTargetMachine(), ArgLocs, *DAG.getContext()); 2750 2751 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2752 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2753 if (!ArgLocs[i].isRegLoc()) 2754 return false; 2755 } 2756 2757 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2758 // stack. Therefore, if it's not used by the call it is not safe to optimize 2759 // this into a sibcall. 2760 bool Unused = false; 2761 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2762 if (!Ins[i].Used) { 2763 Unused = true; 2764 break; 2765 } 2766 } 2767 if (Unused) { 2768 SmallVector<CCValAssign, 16> RVLocs; 2769 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2770 getTargetMachine(), RVLocs, *DAG.getContext()); 2771 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2772 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2773 CCValAssign &VA = RVLocs[i]; 2774 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2775 return false; 2776 } 2777 } 2778 2779 // If the calling conventions do not match, then we'd better make sure the 2780 // results are returned in the same way as what the caller expects. 2781 if (!CCMatch) { 2782 SmallVector<CCValAssign, 16> RVLocs1; 2783 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2784 getTargetMachine(), RVLocs1, *DAG.getContext()); 2785 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2786 2787 SmallVector<CCValAssign, 16> RVLocs2; 2788 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2789 getTargetMachine(), RVLocs2, *DAG.getContext()); 2790 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2791 2792 if (RVLocs1.size() != RVLocs2.size()) 2793 return false; 2794 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2795 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2796 return false; 2797 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2798 return false; 2799 if (RVLocs1[i].isRegLoc()) { 2800 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2801 return false; 2802 } else { 2803 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2804 return false; 2805 } 2806 } 2807 } 2808 2809 // If the callee takes no arguments then go on to check the results of the 2810 // call. 2811 if (!Outs.empty()) { 2812 // Check if stack adjustment is needed. For now, do not do this if any 2813 // argument is passed on the stack. 2814 SmallVector<CCValAssign, 16> ArgLocs; 2815 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2816 getTargetMachine(), ArgLocs, *DAG.getContext()); 2817 2818 // Allocate shadow area for Win64 2819 if (Subtarget->isTargetWin64()) { 2820 CCInfo.AllocateStack(32, 8); 2821 } 2822 2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2824 if (CCInfo.getNextStackOffset()) { 2825 MachineFunction &MF = DAG.getMachineFunction(); 2826 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2827 return false; 2828 2829 // Check if the arguments are already laid out in the right way as 2830 // the caller's fixed stack objects. 2831 MachineFrameInfo *MFI = MF.getFrameInfo(); 2832 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2833 const X86InstrInfo *TII = 2834 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2835 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2836 CCValAssign &VA = ArgLocs[i]; 2837 SDValue Arg = OutVals[i]; 2838 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2839 if (VA.getLocInfo() == CCValAssign::Indirect) 2840 return false; 2841 if (!VA.isRegLoc()) { 2842 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2843 MFI, MRI, TII)) 2844 return false; 2845 } 2846 } 2847 } 2848 2849 // If the tailcall address may be in a register, then make sure it's 2850 // possible to register allocate for it. In 32-bit, the call address can 2851 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2852 // callee-saved registers are restored. These happen to be the same 2853 // registers used to pass 'inreg' arguments so watch out for those. 2854 if (!Subtarget->is64Bit() && 2855 !isa<GlobalAddressSDNode>(Callee) && 2856 !isa<ExternalSymbolSDNode>(Callee)) { 2857 unsigned NumInRegs = 0; 2858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2859 CCValAssign &VA = ArgLocs[i]; 2860 if (!VA.isRegLoc()) 2861 continue; 2862 unsigned Reg = VA.getLocReg(); 2863 switch (Reg) { 2864 default: break; 2865 case X86::EAX: case X86::EDX: case X86::ECX: 2866 if (++NumInRegs == 3) 2867 return false; 2868 break; 2869 } 2870 } 2871 } 2872 } 2873 2874 return true; 2875} 2876 2877FastISel * 2878X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2879 return X86::createFastISel(funcInfo); 2880} 2881 2882 2883//===----------------------------------------------------------------------===// 2884// Other Lowering Hooks 2885//===----------------------------------------------------------------------===// 2886 2887static bool MayFoldLoad(SDValue Op) { 2888 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2889} 2890 2891static bool MayFoldIntoStore(SDValue Op) { 2892 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2893} 2894 2895static bool isTargetShuffle(unsigned Opcode) { 2896 switch(Opcode) { 2897 default: return false; 2898 case X86ISD::PSHUFD: 2899 case X86ISD::PSHUFHW: 2900 case X86ISD::PSHUFLW: 2901 case X86ISD::SHUFP: 2902 case X86ISD::PALIGN: 2903 case X86ISD::MOVLHPS: 2904 case X86ISD::MOVLHPD: 2905 case X86ISD::MOVHLPS: 2906 case X86ISD::MOVLPS: 2907 case X86ISD::MOVLPD: 2908 case X86ISD::MOVSHDUP: 2909 case X86ISD::MOVSLDUP: 2910 case X86ISD::MOVDDUP: 2911 case X86ISD::MOVSS: 2912 case X86ISD::MOVSD: 2913 case X86ISD::UNPCKL: 2914 case X86ISD::UNPCKH: 2915 case X86ISD::VPERMILP: 2916 case X86ISD::VPERM2X128: 2917 case X86ISD::VPERMI: 2918 return true; 2919 } 2920} 2921 2922static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2923 SDValue V1, SelectionDAG &DAG) { 2924 switch(Opc) { 2925 default: llvm_unreachable("Unknown x86 shuffle node"); 2926 case X86ISD::MOVSHDUP: 2927 case X86ISD::MOVSLDUP: 2928 case X86ISD::MOVDDUP: 2929 return DAG.getNode(Opc, dl, VT, V1); 2930 } 2931} 2932 2933static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2934 SDValue V1, unsigned TargetMask, 2935 SelectionDAG &DAG) { 2936 switch(Opc) { 2937 default: llvm_unreachable("Unknown x86 shuffle node"); 2938 case X86ISD::PSHUFD: 2939 case X86ISD::PSHUFHW: 2940 case X86ISD::PSHUFLW: 2941 case X86ISD::VPERMILP: 2942 case X86ISD::VPERMI: 2943 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2944 } 2945} 2946 2947static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2948 SDValue V1, SDValue V2, unsigned TargetMask, 2949 SelectionDAG &DAG) { 2950 switch(Opc) { 2951 default: llvm_unreachable("Unknown x86 shuffle node"); 2952 case X86ISD::PALIGN: 2953 case X86ISD::SHUFP: 2954 case X86ISD::VPERM2X128: 2955 return DAG.getNode(Opc, dl, VT, V1, V2, 2956 DAG.getConstant(TargetMask, MVT::i8)); 2957 } 2958} 2959 2960static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2961 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2962 switch(Opc) { 2963 default: llvm_unreachable("Unknown x86 shuffle node"); 2964 case X86ISD::MOVLHPS: 2965 case X86ISD::MOVLHPD: 2966 case X86ISD::MOVHLPS: 2967 case X86ISD::MOVLPS: 2968 case X86ISD::MOVLPD: 2969 case X86ISD::MOVSS: 2970 case X86ISD::MOVSD: 2971 case X86ISD::UNPCKL: 2972 case X86ISD::UNPCKH: 2973 return DAG.getNode(Opc, dl, VT, V1, V2); 2974 } 2975} 2976 2977SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2978 MachineFunction &MF = DAG.getMachineFunction(); 2979 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2980 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2981 2982 if (ReturnAddrIndex == 0) { 2983 // Set up a frame object for the return address. 2984 uint64_t SlotSize = TD->getPointerSize(); 2985 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2986 false); 2987 FuncInfo->setRAIndex(ReturnAddrIndex); 2988 } 2989 2990 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2991} 2992 2993 2994bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2995 bool hasSymbolicDisplacement) { 2996 // Offset should fit into 32 bit immediate field. 2997 if (!isInt<32>(Offset)) 2998 return false; 2999 3000 // If we don't have a symbolic displacement - we don't have any extra 3001 // restrictions. 3002 if (!hasSymbolicDisplacement) 3003 return true; 3004 3005 // FIXME: Some tweaks might be needed for medium code model. 3006 if (M != CodeModel::Small && M != CodeModel::Kernel) 3007 return false; 3008 3009 // For small code model we assume that latest object is 16MB before end of 31 3010 // bits boundary. We may also accept pretty large negative constants knowing 3011 // that all objects are in the positive half of address space. 3012 if (M == CodeModel::Small && Offset < 16*1024*1024) 3013 return true; 3014 3015 // For kernel code model we know that all object resist in the negative half 3016 // of 32bits address space. We may not accept negative offsets, since they may 3017 // be just off and we may accept pretty large positive ones. 3018 if (M == CodeModel::Kernel && Offset > 0) 3019 return true; 3020 3021 return false; 3022} 3023 3024/// isCalleePop - Determines whether the callee is required to pop its 3025/// own arguments. Callee pop is necessary to support tail calls. 3026bool X86::isCalleePop(CallingConv::ID CallingConv, 3027 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3028 if (IsVarArg) 3029 return false; 3030 3031 switch (CallingConv) { 3032 default: 3033 return false; 3034 case CallingConv::X86_StdCall: 3035 return !is64Bit; 3036 case CallingConv::X86_FastCall: 3037 return !is64Bit; 3038 case CallingConv::X86_ThisCall: 3039 return !is64Bit; 3040 case CallingConv::Fast: 3041 return TailCallOpt; 3042 case CallingConv::GHC: 3043 return TailCallOpt; 3044 } 3045} 3046 3047/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3048/// specific condition code, returning the condition code and the LHS/RHS of the 3049/// comparison to make. 3050static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3051 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3052 if (!isFP) { 3053 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3054 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3055 // X > -1 -> X == 0, jump !sign. 3056 RHS = DAG.getConstant(0, RHS.getValueType()); 3057 return X86::COND_NS; 3058 } 3059 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3060 // X < 0 -> X == 0, jump on sign. 3061 return X86::COND_S; 3062 } 3063 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3064 // X < 1 -> X <= 0 3065 RHS = DAG.getConstant(0, RHS.getValueType()); 3066 return X86::COND_LE; 3067 } 3068 } 3069 3070 switch (SetCCOpcode) { 3071 default: llvm_unreachable("Invalid integer condition!"); 3072 case ISD::SETEQ: return X86::COND_E; 3073 case ISD::SETGT: return X86::COND_G; 3074 case ISD::SETGE: return X86::COND_GE; 3075 case ISD::SETLT: return X86::COND_L; 3076 case ISD::SETLE: return X86::COND_LE; 3077 case ISD::SETNE: return X86::COND_NE; 3078 case ISD::SETULT: return X86::COND_B; 3079 case ISD::SETUGT: return X86::COND_A; 3080 case ISD::SETULE: return X86::COND_BE; 3081 case ISD::SETUGE: return X86::COND_AE; 3082 } 3083 } 3084 3085 // First determine if it is required or is profitable to flip the operands. 3086 3087 // If LHS is a foldable load, but RHS is not, flip the condition. 3088 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3089 !ISD::isNON_EXTLoad(RHS.getNode())) { 3090 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3091 std::swap(LHS, RHS); 3092 } 3093 3094 switch (SetCCOpcode) { 3095 default: break; 3096 case ISD::SETOLT: 3097 case ISD::SETOLE: 3098 case ISD::SETUGT: 3099 case ISD::SETUGE: 3100 std::swap(LHS, RHS); 3101 break; 3102 } 3103 3104 // On a floating point condition, the flags are set as follows: 3105 // ZF PF CF op 3106 // 0 | 0 | 0 | X > Y 3107 // 0 | 0 | 1 | X < Y 3108 // 1 | 0 | 0 | X == Y 3109 // 1 | 1 | 1 | unordered 3110 switch (SetCCOpcode) { 3111 default: llvm_unreachable("Condcode should be pre-legalized away"); 3112 case ISD::SETUEQ: 3113 case ISD::SETEQ: return X86::COND_E; 3114 case ISD::SETOLT: // flipped 3115 case ISD::SETOGT: 3116 case ISD::SETGT: return X86::COND_A; 3117 case ISD::SETOLE: // flipped 3118 case ISD::SETOGE: 3119 case ISD::SETGE: return X86::COND_AE; 3120 case ISD::SETUGT: // flipped 3121 case ISD::SETULT: 3122 case ISD::SETLT: return X86::COND_B; 3123 case ISD::SETUGE: // flipped 3124 case ISD::SETULE: 3125 case ISD::SETLE: return X86::COND_BE; 3126 case ISD::SETONE: 3127 case ISD::SETNE: return X86::COND_NE; 3128 case ISD::SETUO: return X86::COND_P; 3129 case ISD::SETO: return X86::COND_NP; 3130 case ISD::SETOEQ: 3131 case ISD::SETUNE: return X86::COND_INVALID; 3132 } 3133} 3134 3135/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3136/// code. Current x86 isa includes the following FP cmov instructions: 3137/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3138static bool hasFPCMov(unsigned X86CC) { 3139 switch (X86CC) { 3140 default: 3141 return false; 3142 case X86::COND_B: 3143 case X86::COND_BE: 3144 case X86::COND_E: 3145 case X86::COND_P: 3146 case X86::COND_A: 3147 case X86::COND_AE: 3148 case X86::COND_NE: 3149 case X86::COND_NP: 3150 return true; 3151 } 3152} 3153 3154/// isFPImmLegal - Returns true if the target can instruction select the 3155/// specified FP immediate natively. If false, the legalizer will 3156/// materialize the FP immediate as a load from a constant pool. 3157bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3158 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3159 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3160 return true; 3161 } 3162 return false; 3163} 3164 3165/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3166/// the specified range (L, H]. 3167static bool isUndefOrInRange(int Val, int Low, int Hi) { 3168 return (Val < 0) || (Val >= Low && Val < Hi); 3169} 3170 3171/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3172/// specified value. 3173static bool isUndefOrEqual(int Val, int CmpVal) { 3174 if (Val < 0 || Val == CmpVal) 3175 return true; 3176 return false; 3177} 3178 3179/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3180/// from position Pos and ending in Pos+Size, falls within the specified 3181/// sequential range (L, L+Pos]. or is undef. 3182static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3183 unsigned Pos, unsigned Size, int Low) { 3184 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3185 if (!isUndefOrEqual(Mask[i], Low)) 3186 return false; 3187 return true; 3188} 3189 3190/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3191/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3192/// the second operand. 3193static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3194 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3195 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3196 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3197 return (Mask[0] < 2 && Mask[1] < 2); 3198 return false; 3199} 3200 3201/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3202/// is suitable for input to PSHUFHW. 3203static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3204 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3205 return false; 3206 3207 // Lower quadword copied in order or undef. 3208 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3209 return false; 3210 3211 // Upper quadword shuffled. 3212 for (unsigned i = 4; i != 8; ++i) 3213 if (!isUndefOrInRange(Mask[i], 4, 8)) 3214 return false; 3215 3216 if (VT == MVT::v16i16) { 3217 // Lower quadword copied in order or undef. 3218 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8)) 3219 return false; 3220 3221 // Upper quadword shuffled. 3222 for (unsigned i = 12; i != 16; ++i) 3223 if (!isUndefOrInRange(Mask[i], 12, 16)) 3224 return false; 3225 } 3226 3227 return true; 3228} 3229 3230/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3231/// is suitable for input to PSHUFLW. 3232static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3233 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16)) 3234 return false; 3235 3236 // Upper quadword copied in order. 3237 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3238 return false; 3239 3240 // Lower quadword shuffled. 3241 for (unsigned i = 0; i != 4; ++i) 3242 if (!isUndefOrInRange(Mask[i], 0, 4)) 3243 return false; 3244 3245 if (VT == MVT::v16i16) { 3246 // Upper quadword copied in order. 3247 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12)) 3248 return false; 3249 3250 // Lower quadword shuffled. 3251 for (unsigned i = 8; i != 12; ++i) 3252 if (!isUndefOrInRange(Mask[i], 8, 12)) 3253 return false; 3254 } 3255 3256 return true; 3257} 3258 3259/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3260/// is suitable for input to PALIGNR. 3261static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3262 const X86Subtarget *Subtarget) { 3263 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3264 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3265 return false; 3266 3267 unsigned NumElts = VT.getVectorNumElements(); 3268 unsigned NumLanes = VT.getSizeInBits()/128; 3269 unsigned NumLaneElts = NumElts/NumLanes; 3270 3271 // Do not handle 64-bit element shuffles with palignr. 3272 if (NumLaneElts == 2) 3273 return false; 3274 3275 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3276 unsigned i; 3277 for (i = 0; i != NumLaneElts; ++i) { 3278 if (Mask[i+l] >= 0) 3279 break; 3280 } 3281 3282 // Lane is all undef, go to next lane 3283 if (i == NumLaneElts) 3284 continue; 3285 3286 int Start = Mask[i+l]; 3287 3288 // Make sure its in this lane in one of the sources 3289 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3290 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3291 return false; 3292 3293 // If not lane 0, then we must match lane 0 3294 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3295 return false; 3296 3297 // Correct second source to be contiguous with first source 3298 if (Start >= (int)NumElts) 3299 Start -= NumElts - NumLaneElts; 3300 3301 // Make sure we're shifting in the right direction. 3302 if (Start <= (int)(i+l)) 3303 return false; 3304 3305 Start -= i; 3306 3307 // Check the rest of the elements to see if they are consecutive. 3308 for (++i; i != NumLaneElts; ++i) { 3309 int Idx = Mask[i+l]; 3310 3311 // Make sure its in this lane 3312 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3313 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3314 return false; 3315 3316 // If not lane 0, then we must match lane 0 3317 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3318 return false; 3319 3320 if (Idx >= (int)NumElts) 3321 Idx -= NumElts - NumLaneElts; 3322 3323 if (!isUndefOrEqual(Idx, Start+i)) 3324 return false; 3325 3326 } 3327 } 3328 3329 return true; 3330} 3331 3332/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3333/// the two vector operands have swapped position. 3334static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3335 unsigned NumElems) { 3336 for (unsigned i = 0; i != NumElems; ++i) { 3337 int idx = Mask[i]; 3338 if (idx < 0) 3339 continue; 3340 else if (idx < (int)NumElems) 3341 Mask[i] = idx + NumElems; 3342 else 3343 Mask[i] = idx - NumElems; 3344 } 3345} 3346 3347/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3348/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3349/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3350/// reverse of what x86 shuffles want. 3351static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3352 bool Commuted = false) { 3353 if (!HasAVX && VT.getSizeInBits() == 256) 3354 return false; 3355 3356 unsigned NumElems = VT.getVectorNumElements(); 3357 unsigned NumLanes = VT.getSizeInBits()/128; 3358 unsigned NumLaneElems = NumElems/NumLanes; 3359 3360 if (NumLaneElems != 2 && NumLaneElems != 4) 3361 return false; 3362 3363 // VSHUFPSY divides the resulting vector into 4 chunks. 3364 // The sources are also splitted into 4 chunks, and each destination 3365 // chunk must come from a different source chunk. 3366 // 3367 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3368 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3369 // 3370 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3371 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3372 // 3373 // VSHUFPDY divides the resulting vector into 4 chunks. 3374 // The sources are also splitted into 4 chunks, and each destination 3375 // chunk must come from a different source chunk. 3376 // 3377 // SRC1 => X3 X2 X1 X0 3378 // SRC2 => Y3 Y2 Y1 Y0 3379 // 3380 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3381 // 3382 unsigned HalfLaneElems = NumLaneElems/2; 3383 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3384 for (unsigned i = 0; i != NumLaneElems; ++i) { 3385 int Idx = Mask[i+l]; 3386 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3387 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3388 return false; 3389 // For VSHUFPSY, the mask of the second half must be the same as the 3390 // first but with the appropriate offsets. This works in the same way as 3391 // VPERMILPS works with masks. 3392 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3393 continue; 3394 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3395 return false; 3396 } 3397 } 3398 3399 return true; 3400} 3401 3402/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3403/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3404static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3405 unsigned NumElems = VT.getVectorNumElements(); 3406 3407 if (VT.getSizeInBits() != 128) 3408 return false; 3409 3410 if (NumElems != 4) 3411 return false; 3412 3413 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3414 return isUndefOrEqual(Mask[0], 6) && 3415 isUndefOrEqual(Mask[1], 7) && 3416 isUndefOrEqual(Mask[2], 2) && 3417 isUndefOrEqual(Mask[3], 3); 3418} 3419 3420/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3421/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3422/// <2, 3, 2, 3> 3423static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3424 unsigned NumElems = VT.getVectorNumElements(); 3425 3426 if (VT.getSizeInBits() != 128) 3427 return false; 3428 3429 if (NumElems != 4) 3430 return false; 3431 3432 return isUndefOrEqual(Mask[0], 2) && 3433 isUndefOrEqual(Mask[1], 3) && 3434 isUndefOrEqual(Mask[2], 2) && 3435 isUndefOrEqual(Mask[3], 3); 3436} 3437 3438/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3439/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3440static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3441 if (VT.getSizeInBits() != 128) 3442 return false; 3443 3444 unsigned NumElems = VT.getVectorNumElements(); 3445 3446 if (NumElems != 2 && NumElems != 4) 3447 return false; 3448 3449 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3450 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3451 return false; 3452 3453 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 3454 if (!isUndefOrEqual(Mask[i], i)) 3455 return false; 3456 3457 return true; 3458} 3459 3460/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3461/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3462static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3463 unsigned NumElems = VT.getVectorNumElements(); 3464 3465 if ((NumElems != 2 && NumElems != 4) 3466 || VT.getSizeInBits() > 128) 3467 return false; 3468 3469 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3470 if (!isUndefOrEqual(Mask[i], i)) 3471 return false; 3472 3473 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3474 if (!isUndefOrEqual(Mask[i + e], i + NumElems)) 3475 return false; 3476 3477 return true; 3478} 3479 3480/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3481/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3482static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3483 bool HasAVX2, bool V2IsSplat = false) { 3484 unsigned NumElts = VT.getVectorNumElements(); 3485 3486 assert((VT.is128BitVector() || VT.is256BitVector()) && 3487 "Unsupported vector type for unpckh"); 3488 3489 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3490 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3491 return false; 3492 3493 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3494 // independently on 128-bit lanes. 3495 unsigned NumLanes = VT.getSizeInBits()/128; 3496 unsigned NumLaneElts = NumElts/NumLanes; 3497 3498 for (unsigned l = 0; l != NumLanes; ++l) { 3499 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3500 i != (l+1)*NumLaneElts; 3501 i += 2, ++j) { 3502 int BitI = Mask[i]; 3503 int BitI1 = Mask[i+1]; 3504 if (!isUndefOrEqual(BitI, j)) 3505 return false; 3506 if (V2IsSplat) { 3507 if (!isUndefOrEqual(BitI1, NumElts)) 3508 return false; 3509 } else { 3510 if (!isUndefOrEqual(BitI1, j + NumElts)) 3511 return false; 3512 } 3513 } 3514 } 3515 3516 return true; 3517} 3518 3519/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3520/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3521static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3522 bool HasAVX2, bool V2IsSplat = false) { 3523 unsigned NumElts = VT.getVectorNumElements(); 3524 3525 assert((VT.is128BitVector() || VT.is256BitVector()) && 3526 "Unsupported vector type for unpckh"); 3527 3528 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3529 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3530 return false; 3531 3532 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3533 // independently on 128-bit lanes. 3534 unsigned NumLanes = VT.getSizeInBits()/128; 3535 unsigned NumLaneElts = NumElts/NumLanes; 3536 3537 for (unsigned l = 0; l != NumLanes; ++l) { 3538 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3539 i != (l+1)*NumLaneElts; i += 2, ++j) { 3540 int BitI = Mask[i]; 3541 int BitI1 = Mask[i+1]; 3542 if (!isUndefOrEqual(BitI, j)) 3543 return false; 3544 if (V2IsSplat) { 3545 if (isUndefOrEqual(BitI1, NumElts)) 3546 return false; 3547 } else { 3548 if (!isUndefOrEqual(BitI1, j+NumElts)) 3549 return false; 3550 } 3551 } 3552 } 3553 return true; 3554} 3555 3556/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3557/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3558/// <0, 0, 1, 1> 3559static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3560 bool HasAVX2) { 3561 unsigned NumElts = VT.getVectorNumElements(); 3562 3563 assert((VT.is128BitVector() || VT.is256BitVector()) && 3564 "Unsupported vector type for unpckh"); 3565 3566 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3567 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3568 return false; 3569 3570 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3571 // FIXME: Need a better way to get rid of this, there's no latency difference 3572 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3573 // the former later. We should also remove the "_undef" special mask. 3574 if (NumElts == 4 && VT.getSizeInBits() == 256) 3575 return false; 3576 3577 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3578 // independently on 128-bit lanes. 3579 unsigned NumLanes = VT.getSizeInBits()/128; 3580 unsigned NumLaneElts = NumElts/NumLanes; 3581 3582 for (unsigned l = 0; l != NumLanes; ++l) { 3583 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3584 i != (l+1)*NumLaneElts; 3585 i += 2, ++j) { 3586 int BitI = Mask[i]; 3587 int BitI1 = Mask[i+1]; 3588 3589 if (!isUndefOrEqual(BitI, j)) 3590 return false; 3591 if (!isUndefOrEqual(BitI1, j)) 3592 return false; 3593 } 3594 } 3595 3596 return true; 3597} 3598 3599/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3600/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3601/// <2, 2, 3, 3> 3602static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3603 unsigned NumElts = VT.getVectorNumElements(); 3604 3605 assert((VT.is128BitVector() || VT.is256BitVector()) && 3606 "Unsupported vector type for unpckh"); 3607 3608 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3609 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3610 return false; 3611 3612 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3613 // independently on 128-bit lanes. 3614 unsigned NumLanes = VT.getSizeInBits()/128; 3615 unsigned NumLaneElts = NumElts/NumLanes; 3616 3617 for (unsigned l = 0; l != NumLanes; ++l) { 3618 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3619 i != (l+1)*NumLaneElts; i += 2, ++j) { 3620 int BitI = Mask[i]; 3621 int BitI1 = Mask[i+1]; 3622 if (!isUndefOrEqual(BitI, j)) 3623 return false; 3624 if (!isUndefOrEqual(BitI1, j)) 3625 return false; 3626 } 3627 } 3628 return true; 3629} 3630 3631/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3632/// specifies a shuffle of elements that is suitable for input to MOVSS, 3633/// MOVSD, and MOVD, i.e. setting the lowest element. 3634static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3635 if (VT.getVectorElementType().getSizeInBits() < 32) 3636 return false; 3637 if (VT.getSizeInBits() == 256) 3638 return false; 3639 3640 unsigned NumElts = VT.getVectorNumElements(); 3641 3642 if (!isUndefOrEqual(Mask[0], NumElts)) 3643 return false; 3644 3645 for (unsigned i = 1; i != NumElts; ++i) 3646 if (!isUndefOrEqual(Mask[i], i)) 3647 return false; 3648 3649 return true; 3650} 3651 3652/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3653/// as permutations between 128-bit chunks or halves. As an example: this 3654/// shuffle bellow: 3655/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3656/// The first half comes from the second half of V1 and the second half from the 3657/// the second half of V2. 3658static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3659 if (!HasAVX || VT.getSizeInBits() != 256) 3660 return false; 3661 3662 // The shuffle result is divided into half A and half B. In total the two 3663 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3664 // B must come from C, D, E or F. 3665 unsigned HalfSize = VT.getVectorNumElements()/2; 3666 bool MatchA = false, MatchB = false; 3667 3668 // Check if A comes from one of C, D, E, F. 3669 for (unsigned Half = 0; Half != 4; ++Half) { 3670 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3671 MatchA = true; 3672 break; 3673 } 3674 } 3675 3676 // Check if B comes from one of C, D, E, F. 3677 for (unsigned Half = 0; Half != 4; ++Half) { 3678 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3679 MatchB = true; 3680 break; 3681 } 3682 } 3683 3684 return MatchA && MatchB; 3685} 3686 3687/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3688/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3689static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3690 EVT VT = SVOp->getValueType(0); 3691 3692 unsigned HalfSize = VT.getVectorNumElements()/2; 3693 3694 unsigned FstHalf = 0, SndHalf = 0; 3695 for (unsigned i = 0; i < HalfSize; ++i) { 3696 if (SVOp->getMaskElt(i) > 0) { 3697 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3698 break; 3699 } 3700 } 3701 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3702 if (SVOp->getMaskElt(i) > 0) { 3703 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3704 break; 3705 } 3706 } 3707 3708 return (FstHalf | (SndHalf << 4)); 3709} 3710 3711/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3712/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3713/// Note that VPERMIL mask matching is different depending whether theunderlying 3714/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3715/// to the same elements of the low, but to the higher half of the source. 3716/// In VPERMILPD the two lanes could be shuffled independently of each other 3717/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3718static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3719 if (!HasAVX) 3720 return false; 3721 3722 unsigned NumElts = VT.getVectorNumElements(); 3723 // Only match 256-bit with 32/64-bit types 3724 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3725 return false; 3726 3727 unsigned NumLanes = VT.getSizeInBits()/128; 3728 unsigned LaneSize = NumElts/NumLanes; 3729 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3730 for (unsigned i = 0; i != LaneSize; ++i) { 3731 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3732 return false; 3733 if (NumElts != 8 || l == 0) 3734 continue; 3735 // VPERMILPS handling 3736 if (Mask[i] < 0) 3737 continue; 3738 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3739 return false; 3740 } 3741 } 3742 3743 return true; 3744} 3745 3746/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3747/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3748/// element of vector 2 and the other elements to come from vector 1 in order. 3749static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3750 bool V2IsSplat = false, bool V2IsUndef = false) { 3751 unsigned NumOps = VT.getVectorNumElements(); 3752 if (VT.getSizeInBits() == 256) 3753 return false; 3754 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3755 return false; 3756 3757 if (!isUndefOrEqual(Mask[0], 0)) 3758 return false; 3759 3760 for (unsigned i = 1; i != NumOps; ++i) 3761 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3762 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3763 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3764 return false; 3765 3766 return true; 3767} 3768 3769/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3770/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3771/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3772static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3773 const X86Subtarget *Subtarget) { 3774 if (!Subtarget->hasSSE3()) 3775 return false; 3776 3777 unsigned NumElems = VT.getVectorNumElements(); 3778 3779 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3780 (VT.getSizeInBits() == 256 && NumElems != 8)) 3781 return false; 3782 3783 // "i+1" is the value the indexed mask element must have 3784 for (unsigned i = 0; i != NumElems; i += 2) 3785 if (!isUndefOrEqual(Mask[i], i+1) || 3786 !isUndefOrEqual(Mask[i+1], i+1)) 3787 return false; 3788 3789 return true; 3790} 3791 3792/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3793/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3794/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3795static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3796 const X86Subtarget *Subtarget) { 3797 if (!Subtarget->hasSSE3()) 3798 return false; 3799 3800 unsigned NumElems = VT.getVectorNumElements(); 3801 3802 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3803 (VT.getSizeInBits() == 256 && NumElems != 8)) 3804 return false; 3805 3806 // "i" is the value the indexed mask element must have 3807 for (unsigned i = 0; i != NumElems; i += 2) 3808 if (!isUndefOrEqual(Mask[i], i) || 3809 !isUndefOrEqual(Mask[i+1], i)) 3810 return false; 3811 3812 return true; 3813} 3814 3815/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3816/// specifies a shuffle of elements that is suitable for input to 256-bit 3817/// version of MOVDDUP. 3818static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3819 unsigned NumElts = VT.getVectorNumElements(); 3820 3821 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3822 return false; 3823 3824 for (unsigned i = 0; i != NumElts/2; ++i) 3825 if (!isUndefOrEqual(Mask[i], 0)) 3826 return false; 3827 for (unsigned i = NumElts/2; i != NumElts; ++i) 3828 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3829 return false; 3830 return true; 3831} 3832 3833/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3834/// specifies a shuffle of elements that is suitable for input to 128-bit 3835/// version of MOVDDUP. 3836static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3837 if (VT.getSizeInBits() != 128) 3838 return false; 3839 3840 unsigned e = VT.getVectorNumElements() / 2; 3841 for (unsigned i = 0; i != e; ++i) 3842 if (!isUndefOrEqual(Mask[i], i)) 3843 return false; 3844 for (unsigned i = 0; i != e; ++i) 3845 if (!isUndefOrEqual(Mask[e+i], i)) 3846 return false; 3847 return true; 3848} 3849 3850/// isVEXTRACTF128Index - Return true if the specified 3851/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3852/// suitable for input to VEXTRACTF128. 3853bool X86::isVEXTRACTF128Index(SDNode *N) { 3854 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3855 return false; 3856 3857 // The index should be aligned on a 128-bit boundary. 3858 uint64_t Index = 3859 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3860 3861 unsigned VL = N->getValueType(0).getVectorNumElements(); 3862 unsigned VBits = N->getValueType(0).getSizeInBits(); 3863 unsigned ElSize = VBits / VL; 3864 bool Result = (Index * ElSize) % 128 == 0; 3865 3866 return Result; 3867} 3868 3869/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3870/// operand specifies a subvector insert that is suitable for input to 3871/// VINSERTF128. 3872bool X86::isVINSERTF128Index(SDNode *N) { 3873 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3874 return false; 3875 3876 // The index should be aligned on a 128-bit boundary. 3877 uint64_t Index = 3878 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3879 3880 unsigned VL = N->getValueType(0).getVectorNumElements(); 3881 unsigned VBits = N->getValueType(0).getSizeInBits(); 3882 unsigned ElSize = VBits / VL; 3883 bool Result = (Index * ElSize) % 128 == 0; 3884 3885 return Result; 3886} 3887 3888/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3889/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3890/// Handles 128-bit and 256-bit. 3891static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3892 EVT VT = N->getValueType(0); 3893 3894 assert((VT.is128BitVector() || VT.is256BitVector()) && 3895 "Unsupported vector type for PSHUF/SHUFP"); 3896 3897 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3898 // independently on 128-bit lanes. 3899 unsigned NumElts = VT.getVectorNumElements(); 3900 unsigned NumLanes = VT.getSizeInBits()/128; 3901 unsigned NumLaneElts = NumElts/NumLanes; 3902 3903 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3904 "Only supports 2 or 4 elements per lane"); 3905 3906 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3907 unsigned Mask = 0; 3908 for (unsigned i = 0; i != NumElts; ++i) { 3909 int Elt = N->getMaskElt(i); 3910 if (Elt < 0) continue; 3911 Elt &= NumLaneElts - 1; 3912 unsigned ShAmt = (i << Shift) % 8; 3913 Mask |= Elt << ShAmt; 3914 } 3915 3916 return Mask; 3917} 3918 3919/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3920/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3921static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3922 EVT VT = N->getValueType(0); 3923 3924 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 3925 "Unsupported vector type for PSHUFHW"); 3926 3927 unsigned NumElts = VT.getVectorNumElements(); 3928 3929 unsigned Mask = 0; 3930 for (unsigned l = 0; l != NumElts; l += 8) { 3931 // 8 nodes per lane, but we only care about the last 4. 3932 for (unsigned i = 0; i < 4; ++i) { 3933 int Elt = N->getMaskElt(l+i+4); 3934 if (Elt < 0) continue; 3935 Elt &= 0x3; // only 2-bits. 3936 Mask |= Elt << (i * 2); 3937 } 3938 } 3939 3940 return Mask; 3941} 3942 3943/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3944/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3945static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3946 EVT VT = N->getValueType(0); 3947 3948 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && 3949 "Unsupported vector type for PSHUFHW"); 3950 3951 unsigned NumElts = VT.getVectorNumElements(); 3952 3953 unsigned Mask = 0; 3954 for (unsigned l = 0; l != NumElts; l += 8) { 3955 // 8 nodes per lane, but we only care about the first 4. 3956 for (unsigned i = 0; i < 4; ++i) { 3957 int Elt = N->getMaskElt(l+i); 3958 if (Elt < 0) continue; 3959 Elt &= 0x3; // only 2-bits 3960 Mask |= Elt << (i * 2); 3961 } 3962 } 3963 3964 return Mask; 3965} 3966 3967/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3968/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3969static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3970 EVT VT = SVOp->getValueType(0); 3971 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3972 3973 unsigned NumElts = VT.getVectorNumElements(); 3974 unsigned NumLanes = VT.getSizeInBits()/128; 3975 unsigned NumLaneElts = NumElts/NumLanes; 3976 3977 int Val = 0; 3978 unsigned i; 3979 for (i = 0; i != NumElts; ++i) { 3980 Val = SVOp->getMaskElt(i); 3981 if (Val >= 0) 3982 break; 3983 } 3984 if (Val >= (int)NumElts) 3985 Val -= NumElts - NumLaneElts; 3986 3987 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3988 return (Val - i) * EltSize; 3989} 3990 3991/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3992/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3993/// instructions. 3994unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3995 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3996 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3997 3998 uint64_t Index = 3999 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4000 4001 EVT VecVT = N->getOperand(0).getValueType(); 4002 EVT ElVT = VecVT.getVectorElementType(); 4003 4004 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4005 return Index / NumElemsPerChunk; 4006} 4007 4008/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4009/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4010/// instructions. 4011unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4012 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4013 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4014 4015 uint64_t Index = 4016 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4017 4018 EVT VecVT = N->getValueType(0); 4019 EVT ElVT = VecVT.getVectorElementType(); 4020 4021 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4022 return Index / NumElemsPerChunk; 4023} 4024 4025/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 4026/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 4027/// Handles 256-bit. 4028static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 4029 EVT VT = N->getValueType(0); 4030 4031 unsigned NumElts = VT.getVectorNumElements(); 4032 4033 assert((VT.is256BitVector() && NumElts == 4) && 4034 "Unsupported vector type for VPERMQ/VPERMPD"); 4035 4036 unsigned Mask = 0; 4037 for (unsigned i = 0; i != NumElts; ++i) { 4038 int Elt = N->getMaskElt(i); 4039 if (Elt < 0) 4040 continue; 4041 Mask |= Elt << (i*2); 4042 } 4043 4044 return Mask; 4045} 4046/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4047/// constant +0.0. 4048bool X86::isZeroNode(SDValue Elt) { 4049 return ((isa<ConstantSDNode>(Elt) && 4050 cast<ConstantSDNode>(Elt)->isNullValue()) || 4051 (isa<ConstantFPSDNode>(Elt) && 4052 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4053} 4054 4055/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4056/// their permute mask. 4057static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4058 SelectionDAG &DAG) { 4059 EVT VT = SVOp->getValueType(0); 4060 unsigned NumElems = VT.getVectorNumElements(); 4061 SmallVector<int, 8> MaskVec; 4062 4063 for (unsigned i = 0; i != NumElems; ++i) { 4064 int idx = SVOp->getMaskElt(i); 4065 if (idx < 0) 4066 MaskVec.push_back(idx); 4067 else if (idx < (int)NumElems) 4068 MaskVec.push_back(idx + NumElems); 4069 else 4070 MaskVec.push_back(idx - NumElems); 4071 } 4072 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4073 SVOp->getOperand(0), &MaskVec[0]); 4074} 4075 4076/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4077/// match movhlps. The lower half elements should come from upper half of 4078/// V1 (and in order), and the upper half elements should come from the upper 4079/// half of V2 (and in order). 4080static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4081 if (VT.getSizeInBits() != 128) 4082 return false; 4083 if (VT.getVectorNumElements() != 4) 4084 return false; 4085 for (unsigned i = 0, e = 2; i != e; ++i) 4086 if (!isUndefOrEqual(Mask[i], i+2)) 4087 return false; 4088 for (unsigned i = 2; i != 4; ++i) 4089 if (!isUndefOrEqual(Mask[i], i+4)) 4090 return false; 4091 return true; 4092} 4093 4094/// isScalarLoadToVector - Returns true if the node is a scalar load that 4095/// is promoted to a vector. It also returns the LoadSDNode by reference if 4096/// required. 4097static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4098 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4099 return false; 4100 N = N->getOperand(0).getNode(); 4101 if (!ISD::isNON_EXTLoad(N)) 4102 return false; 4103 if (LD) 4104 *LD = cast<LoadSDNode>(N); 4105 return true; 4106} 4107 4108// Test whether the given value is a vector value which will be legalized 4109// into a load. 4110static bool WillBeConstantPoolLoad(SDNode *N) { 4111 if (N->getOpcode() != ISD::BUILD_VECTOR) 4112 return false; 4113 4114 // Check for any non-constant elements. 4115 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4116 switch (N->getOperand(i).getNode()->getOpcode()) { 4117 case ISD::UNDEF: 4118 case ISD::ConstantFP: 4119 case ISD::Constant: 4120 break; 4121 default: 4122 return false; 4123 } 4124 4125 // Vectors of all-zeros and all-ones are materialized with special 4126 // instructions rather than being loaded. 4127 return !ISD::isBuildVectorAllZeros(N) && 4128 !ISD::isBuildVectorAllOnes(N); 4129} 4130 4131/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4132/// match movlp{s|d}. The lower half elements should come from lower half of 4133/// V1 (and in order), and the upper half elements should come from the upper 4134/// half of V2 (and in order). And since V1 will become the source of the 4135/// MOVLP, it must be either a vector load or a scalar load to vector. 4136static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4137 ArrayRef<int> Mask, EVT VT) { 4138 if (VT.getSizeInBits() != 128) 4139 return false; 4140 4141 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4142 return false; 4143 // Is V2 is a vector load, don't do this transformation. We will try to use 4144 // load folding shufps op. 4145 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4146 return false; 4147 4148 unsigned NumElems = VT.getVectorNumElements(); 4149 4150 if (NumElems != 2 && NumElems != 4) 4151 return false; 4152 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4153 if (!isUndefOrEqual(Mask[i], i)) 4154 return false; 4155 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i) 4156 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4157 return false; 4158 return true; 4159} 4160 4161/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4162/// all the same. 4163static bool isSplatVector(SDNode *N) { 4164 if (N->getOpcode() != ISD::BUILD_VECTOR) 4165 return false; 4166 4167 SDValue SplatValue = N->getOperand(0); 4168 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4169 if (N->getOperand(i) != SplatValue) 4170 return false; 4171 return true; 4172} 4173 4174/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4175/// to an zero vector. 4176/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4177static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4178 SDValue V1 = N->getOperand(0); 4179 SDValue V2 = N->getOperand(1); 4180 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4181 for (unsigned i = 0; i != NumElems; ++i) { 4182 int Idx = N->getMaskElt(i); 4183 if (Idx >= (int)NumElems) { 4184 unsigned Opc = V2.getOpcode(); 4185 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4186 continue; 4187 if (Opc != ISD::BUILD_VECTOR || 4188 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4189 return false; 4190 } else if (Idx >= 0) { 4191 unsigned Opc = V1.getOpcode(); 4192 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4193 continue; 4194 if (Opc != ISD::BUILD_VECTOR || 4195 !X86::isZeroNode(V1.getOperand(Idx))) 4196 return false; 4197 } 4198 } 4199 return true; 4200} 4201 4202/// getZeroVector - Returns a vector of specified type with all zero elements. 4203/// 4204static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4205 SelectionDAG &DAG, DebugLoc dl) { 4206 assert(VT.isVector() && "Expected a vector type"); 4207 unsigned Size = VT.getSizeInBits(); 4208 4209 // Always build SSE zero vectors as <4 x i32> bitcasted 4210 // to their dest type. This ensures they get CSE'd. 4211 SDValue Vec; 4212 if (Size == 128) { // SSE 4213 if (Subtarget->hasSSE2()) { // SSE2 4214 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4216 } else { // SSE1 4217 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4218 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4219 } 4220 } else if (Size == 256) { // AVX 4221 if (Subtarget->hasAVX2()) { // AVX2 4222 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4223 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4224 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4225 } else { 4226 // 256-bit logic and arithmetic instructions in AVX are all 4227 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4228 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4229 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4231 } 4232 } else 4233 llvm_unreachable("Unexpected vector type"); 4234 4235 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4236} 4237 4238/// getOnesVector - Returns a vector of specified type with all bits set. 4239/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4240/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4241/// Then bitcast to their original type, ensuring they get CSE'd. 4242static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4243 DebugLoc dl) { 4244 assert(VT.isVector() && "Expected a vector type"); 4245 unsigned Size = VT.getSizeInBits(); 4246 4247 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4248 SDValue Vec; 4249 if (Size == 256) { 4250 if (HasAVX2) { // AVX2 4251 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4253 } else { // AVX 4254 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4255 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4256 } 4257 } else if (Size == 128) { 4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4259 } else 4260 llvm_unreachable("Unexpected vector type"); 4261 4262 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4263} 4264 4265/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4266/// that point to V2 points to its first element. 4267static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4268 for (unsigned i = 0; i != NumElems; ++i) { 4269 if (Mask[i] > (int)NumElems) { 4270 Mask[i] = NumElems; 4271 } 4272 } 4273} 4274 4275/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4276/// operation of specified width. 4277static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4278 SDValue V2) { 4279 unsigned NumElems = VT.getVectorNumElements(); 4280 SmallVector<int, 8> Mask; 4281 Mask.push_back(NumElems); 4282 for (unsigned i = 1; i != NumElems; ++i) 4283 Mask.push_back(i); 4284 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4285} 4286 4287/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4288static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4289 SDValue V2) { 4290 unsigned NumElems = VT.getVectorNumElements(); 4291 SmallVector<int, 8> Mask; 4292 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4293 Mask.push_back(i); 4294 Mask.push_back(i + NumElems); 4295 } 4296 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4297} 4298 4299/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4300static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4301 SDValue V2) { 4302 unsigned NumElems = VT.getVectorNumElements(); 4303 SmallVector<int, 8> Mask; 4304 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) { 4305 Mask.push_back(i + Half); 4306 Mask.push_back(i + NumElems + Half); 4307 } 4308 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4309} 4310 4311// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4312// a generic shuffle instruction because the target has no such instructions. 4313// Generate shuffles which repeat i16 and i8 several times until they can be 4314// represented by v4f32 and then be manipulated by target suported shuffles. 4315static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4316 EVT VT = V.getValueType(); 4317 int NumElems = VT.getVectorNumElements(); 4318 DebugLoc dl = V.getDebugLoc(); 4319 4320 while (NumElems > 4) { 4321 if (EltNo < NumElems/2) { 4322 V = getUnpackl(DAG, dl, VT, V, V); 4323 } else { 4324 V = getUnpackh(DAG, dl, VT, V, V); 4325 EltNo -= NumElems/2; 4326 } 4327 NumElems >>= 1; 4328 } 4329 return V; 4330} 4331 4332/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4333static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4334 EVT VT = V.getValueType(); 4335 DebugLoc dl = V.getDebugLoc(); 4336 unsigned Size = VT.getSizeInBits(); 4337 4338 if (Size == 128) { 4339 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4340 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4341 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4342 &SplatMask[0]); 4343 } else if (Size == 256) { 4344 // To use VPERMILPS to splat scalars, the second half of indicies must 4345 // refer to the higher part, which is a duplication of the lower one, 4346 // because VPERMILPS can only handle in-lane permutations. 4347 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4348 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4349 4350 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4351 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4352 &SplatMask[0]); 4353 } else 4354 llvm_unreachable("Vector size not supported"); 4355 4356 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4357} 4358 4359/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4360static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4361 EVT SrcVT = SV->getValueType(0); 4362 SDValue V1 = SV->getOperand(0); 4363 DebugLoc dl = SV->getDebugLoc(); 4364 4365 int EltNo = SV->getSplatIndex(); 4366 int NumElems = SrcVT.getVectorNumElements(); 4367 unsigned Size = SrcVT.getSizeInBits(); 4368 4369 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4370 "Unknown how to promote splat for type"); 4371 4372 // Extract the 128-bit part containing the splat element and update 4373 // the splat element index when it refers to the higher register. 4374 if (Size == 256) { 4375 V1 = Extract128BitVector(V1, EltNo, DAG, dl); 4376 if (EltNo >= NumElems/2) 4377 EltNo -= NumElems/2; 4378 } 4379 4380 // All i16 and i8 vector types can't be used directly by a generic shuffle 4381 // instruction because the target has no such instruction. Generate shuffles 4382 // which repeat i16 and i8 several times until they fit in i32, and then can 4383 // be manipulated by target suported shuffles. 4384 EVT EltVT = SrcVT.getVectorElementType(); 4385 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4386 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4387 4388 // Recreate the 256-bit vector and place the same 128-bit vector 4389 // into the low and high part. This is necessary because we want 4390 // to use VPERM* to shuffle the vectors 4391 if (Size == 256) { 4392 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4393 } 4394 4395 return getLegalSplat(DAG, V1, EltNo); 4396} 4397 4398/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4399/// vector of zero or undef vector. This produces a shuffle where the low 4400/// element of V2 is swizzled into the zero/undef vector, landing at element 4401/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4402static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4403 bool IsZero, 4404 const X86Subtarget *Subtarget, 4405 SelectionDAG &DAG) { 4406 EVT VT = V2.getValueType(); 4407 SDValue V1 = IsZero 4408 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4409 unsigned NumElems = VT.getVectorNumElements(); 4410 SmallVector<int, 16> MaskVec; 4411 for (unsigned i = 0; i != NumElems; ++i) 4412 // If this is the insertion idx, put the low elt of V2 here. 4413 MaskVec.push_back(i == Idx ? NumElems : i); 4414 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4415} 4416 4417/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4418/// target specific opcode. Returns true if the Mask could be calculated. 4419/// Sets IsUnary to true if only uses one source. 4420static bool getTargetShuffleMask(SDNode *N, MVT VT, 4421 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4422 unsigned NumElems = VT.getVectorNumElements(); 4423 SDValue ImmN; 4424 4425 IsUnary = false; 4426 switch(N->getOpcode()) { 4427 case X86ISD::SHUFP: 4428 ImmN = N->getOperand(N->getNumOperands()-1); 4429 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4430 break; 4431 case X86ISD::UNPCKH: 4432 DecodeUNPCKHMask(VT, Mask); 4433 break; 4434 case X86ISD::UNPCKL: 4435 DecodeUNPCKLMask(VT, Mask); 4436 break; 4437 case X86ISD::MOVHLPS: 4438 DecodeMOVHLPSMask(NumElems, Mask); 4439 break; 4440 case X86ISD::MOVLHPS: 4441 DecodeMOVLHPSMask(NumElems, Mask); 4442 break; 4443 case X86ISD::PSHUFD: 4444 case X86ISD::VPERMILP: 4445 ImmN = N->getOperand(N->getNumOperands()-1); 4446 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4447 IsUnary = true; 4448 break; 4449 case X86ISD::PSHUFHW: 4450 ImmN = N->getOperand(N->getNumOperands()-1); 4451 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4452 IsUnary = true; 4453 break; 4454 case X86ISD::PSHUFLW: 4455 ImmN = N->getOperand(N->getNumOperands()-1); 4456 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4457 IsUnary = true; 4458 break; 4459 case X86ISD::VPERMI: 4460 ImmN = N->getOperand(N->getNumOperands()-1); 4461 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4462 IsUnary = true; 4463 break; 4464 case X86ISD::MOVSS: 4465 case X86ISD::MOVSD: { 4466 // The index 0 always comes from the first element of the second source, 4467 // this is why MOVSS and MOVSD are used in the first place. The other 4468 // elements come from the other positions of the first source vector 4469 Mask.push_back(NumElems); 4470 for (unsigned i = 1; i != NumElems; ++i) { 4471 Mask.push_back(i); 4472 } 4473 break; 4474 } 4475 case X86ISD::VPERM2X128: 4476 ImmN = N->getOperand(N->getNumOperands()-1); 4477 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4478 if (Mask.empty()) return false; 4479 break; 4480 case X86ISD::MOVDDUP: 4481 case X86ISD::MOVLHPD: 4482 case X86ISD::MOVLPD: 4483 case X86ISD::MOVLPS: 4484 case X86ISD::MOVSHDUP: 4485 case X86ISD::MOVSLDUP: 4486 case X86ISD::PALIGN: 4487 // Not yet implemented 4488 return false; 4489 default: llvm_unreachable("unknown target shuffle node"); 4490 } 4491 4492 return true; 4493} 4494 4495/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4496/// element of the result of the vector shuffle. 4497static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4498 unsigned Depth) { 4499 if (Depth == 6) 4500 return SDValue(); // Limit search depth. 4501 4502 SDValue V = SDValue(N, 0); 4503 EVT VT = V.getValueType(); 4504 unsigned Opcode = V.getOpcode(); 4505 4506 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4507 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4508 int Elt = SV->getMaskElt(Index); 4509 4510 if (Elt < 0) 4511 return DAG.getUNDEF(VT.getVectorElementType()); 4512 4513 unsigned NumElems = VT.getVectorNumElements(); 4514 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4515 : SV->getOperand(1); 4516 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4517 } 4518 4519 // Recurse into target specific vector shuffles to find scalars. 4520 if (isTargetShuffle(Opcode)) { 4521 MVT ShufVT = V.getValueType().getSimpleVT(); 4522 unsigned NumElems = ShufVT.getVectorNumElements(); 4523 SmallVector<int, 16> ShuffleMask; 4524 SDValue ImmN; 4525 bool IsUnary; 4526 4527 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary)) 4528 return SDValue(); 4529 4530 int Elt = ShuffleMask[Index]; 4531 if (Elt < 0) 4532 return DAG.getUNDEF(ShufVT.getVectorElementType()); 4533 4534 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4535 : N->getOperand(1); 4536 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4537 Depth+1); 4538 } 4539 4540 // Actual nodes that may contain scalar elements 4541 if (Opcode == ISD::BITCAST) { 4542 V = V.getOperand(0); 4543 EVT SrcVT = V.getValueType(); 4544 unsigned NumElems = VT.getVectorNumElements(); 4545 4546 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4547 return SDValue(); 4548 } 4549 4550 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4551 return (Index == 0) ? V.getOperand(0) 4552 : DAG.getUNDEF(VT.getVectorElementType()); 4553 4554 if (V.getOpcode() == ISD::BUILD_VECTOR) 4555 return V.getOperand(Index); 4556 4557 return SDValue(); 4558} 4559 4560/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4561/// shuffle operation which come from a consecutively from a zero. The 4562/// search can start in two different directions, from left or right. 4563static 4564unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4565 bool ZerosFromLeft, SelectionDAG &DAG) { 4566 unsigned i; 4567 for (i = 0; i != NumElems; ++i) { 4568 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4569 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4570 if (!(Elt.getNode() && 4571 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4572 break; 4573 } 4574 4575 return i; 4576} 4577 4578/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4579/// correspond consecutively to elements from one of the vector operands, 4580/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4581static 4582bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4583 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4584 unsigned NumElems, unsigned &OpNum) { 4585 bool SeenV1 = false; 4586 bool SeenV2 = false; 4587 4588 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4589 int Idx = SVOp->getMaskElt(i); 4590 // Ignore undef indicies 4591 if (Idx < 0) 4592 continue; 4593 4594 if (Idx < (int)NumElems) 4595 SeenV1 = true; 4596 else 4597 SeenV2 = true; 4598 4599 // Only accept consecutive elements from the same vector 4600 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4601 return false; 4602 } 4603 4604 OpNum = SeenV1 ? 0 : 1; 4605 return true; 4606} 4607 4608/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4609/// logical left shift of a vector. 4610static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4611 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4612 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4613 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4614 false /* check zeros from right */, DAG); 4615 unsigned OpSrc; 4616 4617 if (!NumZeros) 4618 return false; 4619 4620 // Considering the elements in the mask that are not consecutive zeros, 4621 // check if they consecutively come from only one of the source vectors. 4622 // 4623 // V1 = {X, A, B, C} 0 4624 // \ \ \ / 4625 // vector_shuffle V1, V2 <1, 2, 3, X> 4626 // 4627 if (!isShuffleMaskConsecutive(SVOp, 4628 0, // Mask Start Index 4629 NumElems-NumZeros, // Mask End Index(exclusive) 4630 NumZeros, // Where to start looking in the src vector 4631 NumElems, // Number of elements in vector 4632 OpSrc)) // Which source operand ? 4633 return false; 4634 4635 isLeft = false; 4636 ShAmt = NumZeros; 4637 ShVal = SVOp->getOperand(OpSrc); 4638 return true; 4639} 4640 4641/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4642/// logical left shift of a vector. 4643static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4645 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4646 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4647 true /* check zeros from left */, DAG); 4648 unsigned OpSrc; 4649 4650 if (!NumZeros) 4651 return false; 4652 4653 // Considering the elements in the mask that are not consecutive zeros, 4654 // check if they consecutively come from only one of the source vectors. 4655 // 4656 // 0 { A, B, X, X } = V2 4657 // / \ / / 4658 // vector_shuffle V1, V2 <X, X, 4, 5> 4659 // 4660 if (!isShuffleMaskConsecutive(SVOp, 4661 NumZeros, // Mask Start Index 4662 NumElems, // Mask End Index(exclusive) 4663 0, // Where to start looking in the src vector 4664 NumElems, // Number of elements in vector 4665 OpSrc)) // Which source operand ? 4666 return false; 4667 4668 isLeft = true; 4669 ShAmt = NumZeros; 4670 ShVal = SVOp->getOperand(OpSrc); 4671 return true; 4672} 4673 4674/// isVectorShift - Returns true if the shuffle can be implemented as a 4675/// logical left or right shift of a vector. 4676static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4677 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4678 // Although the logic below support any bitwidth size, there are no 4679 // shift instructions which handle more than 128-bit vectors. 4680 if (SVOp->getValueType(0).getSizeInBits() > 128) 4681 return false; 4682 4683 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4684 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4685 return true; 4686 4687 return false; 4688} 4689 4690/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4691/// 4692static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4693 unsigned NumNonZero, unsigned NumZero, 4694 SelectionDAG &DAG, 4695 const X86Subtarget* Subtarget, 4696 const TargetLowering &TLI) { 4697 if (NumNonZero > 8) 4698 return SDValue(); 4699 4700 DebugLoc dl = Op.getDebugLoc(); 4701 SDValue V(0, 0); 4702 bool First = true; 4703 for (unsigned i = 0; i < 16; ++i) { 4704 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4705 if (ThisIsNonZero && First) { 4706 if (NumZero) 4707 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4708 else 4709 V = DAG.getUNDEF(MVT::v8i16); 4710 First = false; 4711 } 4712 4713 if ((i & 1) != 0) { 4714 SDValue ThisElt(0, 0), LastElt(0, 0); 4715 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4716 if (LastIsNonZero) { 4717 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4718 MVT::i16, Op.getOperand(i-1)); 4719 } 4720 if (ThisIsNonZero) { 4721 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4722 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4723 ThisElt, DAG.getConstant(8, MVT::i8)); 4724 if (LastIsNonZero) 4725 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4726 } else 4727 ThisElt = LastElt; 4728 4729 if (ThisElt.getNode()) 4730 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4731 DAG.getIntPtrConstant(i/2)); 4732 } 4733 } 4734 4735 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4736} 4737 4738/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4739/// 4740static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4741 unsigned NumNonZero, unsigned NumZero, 4742 SelectionDAG &DAG, 4743 const X86Subtarget* Subtarget, 4744 const TargetLowering &TLI) { 4745 if (NumNonZero > 4) 4746 return SDValue(); 4747 4748 DebugLoc dl = Op.getDebugLoc(); 4749 SDValue V(0, 0); 4750 bool First = true; 4751 for (unsigned i = 0; i < 8; ++i) { 4752 bool isNonZero = (NonZeros & (1 << i)) != 0; 4753 if (isNonZero) { 4754 if (First) { 4755 if (NumZero) 4756 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4757 else 4758 V = DAG.getUNDEF(MVT::v8i16); 4759 First = false; 4760 } 4761 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4762 MVT::v8i16, V, Op.getOperand(i), 4763 DAG.getIntPtrConstant(i)); 4764 } 4765 } 4766 4767 return V; 4768} 4769 4770/// getVShift - Return a vector logical shift node. 4771/// 4772static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4773 unsigned NumBits, SelectionDAG &DAG, 4774 const TargetLowering &TLI, DebugLoc dl) { 4775 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4776 EVT ShVT = MVT::v2i64; 4777 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4778 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4779 return DAG.getNode(ISD::BITCAST, dl, VT, 4780 DAG.getNode(Opc, dl, ShVT, SrcOp, 4781 DAG.getConstant(NumBits, 4782 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4783} 4784 4785SDValue 4786X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4787 SelectionDAG &DAG) const { 4788 4789 // Check if the scalar load can be widened into a vector load. And if 4790 // the address is "base + cst" see if the cst can be "absorbed" into 4791 // the shuffle mask. 4792 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4793 SDValue Ptr = LD->getBasePtr(); 4794 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4795 return SDValue(); 4796 EVT PVT = LD->getValueType(0); 4797 if (PVT != MVT::i32 && PVT != MVT::f32) 4798 return SDValue(); 4799 4800 int FI = -1; 4801 int64_t Offset = 0; 4802 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4803 FI = FINode->getIndex(); 4804 Offset = 0; 4805 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4806 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4807 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4808 Offset = Ptr.getConstantOperandVal(1); 4809 Ptr = Ptr.getOperand(0); 4810 } else { 4811 return SDValue(); 4812 } 4813 4814 // FIXME: 256-bit vector instructions don't require a strict alignment, 4815 // improve this code to support it better. 4816 unsigned RequiredAlign = VT.getSizeInBits()/8; 4817 SDValue Chain = LD->getChain(); 4818 // Make sure the stack object alignment is at least 16 or 32. 4819 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4820 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4821 if (MFI->isFixedObjectIndex(FI)) { 4822 // Can't change the alignment. FIXME: It's possible to compute 4823 // the exact stack offset and reference FI + adjust offset instead. 4824 // If someone *really* cares about this. That's the way to implement it. 4825 return SDValue(); 4826 } else { 4827 MFI->setObjectAlignment(FI, RequiredAlign); 4828 } 4829 } 4830 4831 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4832 // Ptr + (Offset & ~15). 4833 if (Offset < 0) 4834 return SDValue(); 4835 if ((Offset % RequiredAlign) & 3) 4836 return SDValue(); 4837 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4838 if (StartOffset) 4839 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4840 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4841 4842 int EltNo = (Offset - StartOffset) >> 2; 4843 unsigned NumElems = VT.getVectorNumElements(); 4844 4845 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4846 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4847 LD->getPointerInfo().getWithOffset(StartOffset), 4848 false, false, false, 0); 4849 4850 SmallVector<int, 8> Mask; 4851 for (unsigned i = 0; i != NumElems; ++i) 4852 Mask.push_back(EltNo); 4853 4854 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4855 } 4856 4857 return SDValue(); 4858} 4859 4860/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4861/// vector of type 'VT', see if the elements can be replaced by a single large 4862/// load which has the same value as a build_vector whose operands are 'elts'. 4863/// 4864/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4865/// 4866/// FIXME: we'd also like to handle the case where the last elements are zero 4867/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4868/// There's even a handy isZeroNode for that purpose. 4869static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4870 DebugLoc &DL, SelectionDAG &DAG) { 4871 EVT EltVT = VT.getVectorElementType(); 4872 unsigned NumElems = Elts.size(); 4873 4874 LoadSDNode *LDBase = NULL; 4875 unsigned LastLoadedElt = -1U; 4876 4877 // For each element in the initializer, see if we've found a load or an undef. 4878 // If we don't find an initial load element, or later load elements are 4879 // non-consecutive, bail out. 4880 for (unsigned i = 0; i < NumElems; ++i) { 4881 SDValue Elt = Elts[i]; 4882 4883 if (!Elt.getNode() || 4884 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4885 return SDValue(); 4886 if (!LDBase) { 4887 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4888 return SDValue(); 4889 LDBase = cast<LoadSDNode>(Elt.getNode()); 4890 LastLoadedElt = i; 4891 continue; 4892 } 4893 if (Elt.getOpcode() == ISD::UNDEF) 4894 continue; 4895 4896 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4897 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4898 return SDValue(); 4899 LastLoadedElt = i; 4900 } 4901 4902 // If we have found an entire vector of loads and undefs, then return a large 4903 // load of the entire vector width starting at the base pointer. If we found 4904 // consecutive loads for the low half, generate a vzext_load node. 4905 if (LastLoadedElt == NumElems - 1) { 4906 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4907 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4908 LDBase->getPointerInfo(), 4909 LDBase->isVolatile(), LDBase->isNonTemporal(), 4910 LDBase->isInvariant(), 0); 4911 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4912 LDBase->getPointerInfo(), 4913 LDBase->isVolatile(), LDBase->isNonTemporal(), 4914 LDBase->isInvariant(), LDBase->getAlignment()); 4915 } 4916 if (NumElems == 4 && LastLoadedElt == 1 && 4917 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4918 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4919 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4920 SDValue ResNode = 4921 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4922 LDBase->getPointerInfo(), 4923 LDBase->getAlignment(), 4924 false/*isVolatile*/, true/*ReadMem*/, 4925 false/*WriteMem*/); 4926 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4927 } 4928 return SDValue(); 4929} 4930 4931/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 4932/// to generate a splat value for the following cases: 4933/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 4934/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4935/// a scalar load, or a constant. 4936/// The VBROADCAST node is returned when a pattern is found, 4937/// or SDValue() otherwise. 4938SDValue 4939X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 4940 if (!Subtarget->hasAVX()) 4941 return SDValue(); 4942 4943 EVT VT = Op.getValueType(); 4944 DebugLoc dl = Op.getDebugLoc(); 4945 4946 assert((VT.is128BitVector() || VT.is256BitVector()) && 4947 "Unsupported vector type for broadcast."); 4948 4949 SDValue Ld; 4950 bool ConstSplatVal; 4951 4952 switch (Op.getOpcode()) { 4953 default: 4954 // Unknown pattern found. 4955 return SDValue(); 4956 4957 case ISD::BUILD_VECTOR: { 4958 // The BUILD_VECTOR node must be a splat. 4959 if (!isSplatVector(Op.getNode())) 4960 return SDValue(); 4961 4962 Ld = Op.getOperand(0); 4963 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4964 Ld.getOpcode() == ISD::ConstantFP); 4965 4966 // The suspected load node has several users. Make sure that all 4967 // of its users are from the BUILD_VECTOR node. 4968 // Constants may have multiple users. 4969 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4970 return SDValue(); 4971 break; 4972 } 4973 4974 case ISD::VECTOR_SHUFFLE: { 4975 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4976 4977 // Shuffles must have a splat mask where the first element is 4978 // broadcasted. 4979 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4980 return SDValue(); 4981 4982 SDValue Sc = Op.getOperand(0); 4983 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR && 4984 Sc.getOpcode() != ISD::BUILD_VECTOR) 4985 return SDValue(); 4986 4987 Ld = Sc.getOperand(0); 4988 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4989 Ld.getOpcode() == ISD::ConstantFP); 4990 4991 // The scalar_to_vector node and the suspected 4992 // load node must have exactly one user. 4993 // Constants may have multiple users. 4994 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 4995 return SDValue(); 4996 break; 4997 } 4998 } 4999 5000 bool Is256 = VT.getSizeInBits() == 256; 5001 5002 // Handle the broadcasting a single constant scalar from the constant pool 5003 // into a vector. On Sandybridge it is still better to load a constant vector 5004 // from the constant pool and not to broadcast it from a scalar. 5005 if (ConstSplatVal && Subtarget->hasAVX2()) { 5006 EVT CVT = Ld.getValueType(); 5007 assert(!CVT.isVector() && "Must not broadcast a vector type"); 5008 unsigned ScalarSize = CVT.getSizeInBits(); 5009 5010 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) { 5011 const Constant *C = 0; 5012 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 5013 C = CI->getConstantIntValue(); 5014 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 5015 C = CF->getConstantFPValue(); 5016 5017 assert(C && "Invalid constant type"); 5018 5019 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 5020 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 5021 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 5022 MachinePointerInfo::getConstantPool(), 5023 false, false, false, Alignment); 5024 5025 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5026 } 5027 } 5028 5029 // The scalar source must be a normal load. 5030 if (!ISD::isNormalLoad(Ld.getNode())) 5031 return SDValue(); 5032 5033 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5034 5035 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) 5036 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5037 5038 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5039 // double since there is no vbroadcastsd xmm 5040 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5041 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64) 5042 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5043 } 5044 5045 // Unsupported broadcast. 5046 return SDValue(); 5047} 5048 5049SDValue 5050X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5051 DebugLoc dl = Op.getDebugLoc(); 5052 5053 EVT VT = Op.getValueType(); 5054 EVT ExtVT = VT.getVectorElementType(); 5055 unsigned NumElems = Op.getNumOperands(); 5056 5057 // Vectors containing all zeros can be matched by pxor and xorps later 5058 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5059 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5060 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5061 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5062 return Op; 5063 5064 return getZeroVector(VT, Subtarget, DAG, dl); 5065 } 5066 5067 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5068 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5069 // vpcmpeqd on 256-bit vectors. 5070 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5071 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5072 return Op; 5073 5074 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5075 } 5076 5077 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5078 if (Broadcast.getNode()) 5079 return Broadcast; 5080 5081 unsigned EVTBits = ExtVT.getSizeInBits(); 5082 5083 unsigned NumZero = 0; 5084 unsigned NumNonZero = 0; 5085 unsigned NonZeros = 0; 5086 bool IsAllConstants = true; 5087 SmallSet<SDValue, 8> Values; 5088 for (unsigned i = 0; i < NumElems; ++i) { 5089 SDValue Elt = Op.getOperand(i); 5090 if (Elt.getOpcode() == ISD::UNDEF) 5091 continue; 5092 Values.insert(Elt); 5093 if (Elt.getOpcode() != ISD::Constant && 5094 Elt.getOpcode() != ISD::ConstantFP) 5095 IsAllConstants = false; 5096 if (X86::isZeroNode(Elt)) 5097 NumZero++; 5098 else { 5099 NonZeros |= (1 << i); 5100 NumNonZero++; 5101 } 5102 } 5103 5104 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5105 if (NumNonZero == 0) 5106 return DAG.getUNDEF(VT); 5107 5108 // Special case for single non-zero, non-undef, element. 5109 if (NumNonZero == 1) { 5110 unsigned Idx = CountTrailingZeros_32(NonZeros); 5111 SDValue Item = Op.getOperand(Idx); 5112 5113 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5114 // the value are obviously zero, truncate the value to i32 and do the 5115 // insertion that way. Only do this if the value is non-constant or if the 5116 // value is a constant being inserted into element 0. It is cheaper to do 5117 // a constant pool load than it is to do a movd + shuffle. 5118 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5119 (!IsAllConstants || Idx == 0)) { 5120 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5121 // Handle SSE only. 5122 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5123 EVT VecVT = MVT::v4i32; 5124 unsigned VecElts = 4; 5125 5126 // Truncate the value (which may itself be a constant) to i32, and 5127 // convert it to a vector with movd (S2V+shuffle to zero extend). 5128 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5129 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5130 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5131 5132 // Now we have our 32-bit value zero extended in the low element of 5133 // a vector. If Idx != 0, swizzle it into place. 5134 if (Idx != 0) { 5135 SmallVector<int, 4> Mask; 5136 Mask.push_back(Idx); 5137 for (unsigned i = 1; i != VecElts; ++i) 5138 Mask.push_back(i); 5139 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5140 &Mask[0]); 5141 } 5142 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5143 } 5144 } 5145 5146 // If we have a constant or non-constant insertion into the low element of 5147 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5148 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5149 // depending on what the source datatype is. 5150 if (Idx == 0) { 5151 if (NumZero == 0) 5152 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5153 5154 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5155 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5156 if (VT.getSizeInBits() == 256) { 5157 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5158 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5159 Item, DAG.getIntPtrConstant(0)); 5160 } 5161 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5162 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5163 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5164 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5165 } 5166 5167 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5168 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5169 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5170 if (VT.getSizeInBits() == 256) { 5171 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5172 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5173 } else { 5174 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5175 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5176 } 5177 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5178 } 5179 } 5180 5181 // Is it a vector logical left shift? 5182 if (NumElems == 2 && Idx == 1 && 5183 X86::isZeroNode(Op.getOperand(0)) && 5184 !X86::isZeroNode(Op.getOperand(1))) { 5185 unsigned NumBits = VT.getSizeInBits(); 5186 return getVShift(true, VT, 5187 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5188 VT, Op.getOperand(1)), 5189 NumBits/2, DAG, *this, dl); 5190 } 5191 5192 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5193 return SDValue(); 5194 5195 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5196 // is a non-constant being inserted into an element other than the low one, 5197 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5198 // movd/movss) to move this into the low element, then shuffle it into 5199 // place. 5200 if (EVTBits == 32) { 5201 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5202 5203 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5204 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5205 SmallVector<int, 8> MaskVec; 5206 for (unsigned i = 0; i != NumElems; ++i) 5207 MaskVec.push_back(i == Idx ? 0 : 1); 5208 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5209 } 5210 } 5211 5212 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5213 if (Values.size() == 1) { 5214 if (EVTBits == 32) { 5215 // Instead of a shuffle like this: 5216 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5217 // Check if it's possible to issue this instead. 5218 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5219 unsigned Idx = CountTrailingZeros_32(NonZeros); 5220 SDValue Item = Op.getOperand(Idx); 5221 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5222 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5223 } 5224 return SDValue(); 5225 } 5226 5227 // A vector full of immediates; various special cases are already 5228 // handled, so this is best done with a single constant-pool load. 5229 if (IsAllConstants) 5230 return SDValue(); 5231 5232 // For AVX-length vectors, build the individual 128-bit pieces and use 5233 // shuffles to put them in place. 5234 if (VT.getSizeInBits() == 256) { 5235 SmallVector<SDValue, 32> V; 5236 for (unsigned i = 0; i != NumElems; ++i) 5237 V.push_back(Op.getOperand(i)); 5238 5239 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5240 5241 // Build both the lower and upper subvector. 5242 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5243 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5244 NumElems/2); 5245 5246 // Recreate the wider vector with the lower and upper part. 5247 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5248 } 5249 5250 // Let legalizer expand 2-wide build_vectors. 5251 if (EVTBits == 64) { 5252 if (NumNonZero == 1) { 5253 // One half is zero or undef. 5254 unsigned Idx = CountTrailingZeros_32(NonZeros); 5255 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5256 Op.getOperand(Idx)); 5257 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5258 } 5259 return SDValue(); 5260 } 5261 5262 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5263 if (EVTBits == 8 && NumElems == 16) { 5264 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5265 Subtarget, *this); 5266 if (V.getNode()) return V; 5267 } 5268 5269 if (EVTBits == 16 && NumElems == 8) { 5270 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5271 Subtarget, *this); 5272 if (V.getNode()) return V; 5273 } 5274 5275 // If element VT is == 32 bits, turn it into a number of shuffles. 5276 SmallVector<SDValue, 8> V(NumElems); 5277 if (NumElems == 4 && NumZero > 0) { 5278 for (unsigned i = 0; i < 4; ++i) { 5279 bool isZero = !(NonZeros & (1 << i)); 5280 if (isZero) 5281 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5282 else 5283 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5284 } 5285 5286 for (unsigned i = 0; i < 2; ++i) { 5287 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5288 default: break; 5289 case 0: 5290 V[i] = V[i*2]; // Must be a zero vector. 5291 break; 5292 case 1: 5293 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5294 break; 5295 case 2: 5296 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5297 break; 5298 case 3: 5299 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5300 break; 5301 } 5302 } 5303 5304 bool Reverse1 = (NonZeros & 0x3) == 2; 5305 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5306 int MaskVec[] = { 5307 Reverse1 ? 1 : 0, 5308 Reverse1 ? 0 : 1, 5309 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5310 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5311 }; 5312 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5313 } 5314 5315 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5316 // Check for a build vector of consecutive loads. 5317 for (unsigned i = 0; i < NumElems; ++i) 5318 V[i] = Op.getOperand(i); 5319 5320 // Check for elements which are consecutive loads. 5321 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5322 if (LD.getNode()) 5323 return LD; 5324 5325 // For SSE 4.1, use insertps to put the high elements into the low element. 5326 if (getSubtarget()->hasSSE41()) { 5327 SDValue Result; 5328 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5329 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5330 else 5331 Result = DAG.getUNDEF(VT); 5332 5333 for (unsigned i = 1; i < NumElems; ++i) { 5334 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5335 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5336 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5337 } 5338 return Result; 5339 } 5340 5341 // Otherwise, expand into a number of unpckl*, start by extending each of 5342 // our (non-undef) elements to the full vector width with the element in the 5343 // bottom slot of the vector (which generates no code for SSE). 5344 for (unsigned i = 0; i < NumElems; ++i) { 5345 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5346 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5347 else 5348 V[i] = DAG.getUNDEF(VT); 5349 } 5350 5351 // Next, we iteratively mix elements, e.g. for v4f32: 5352 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5353 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5354 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5355 unsigned EltStride = NumElems >> 1; 5356 while (EltStride != 0) { 5357 for (unsigned i = 0; i < EltStride; ++i) { 5358 // If V[i+EltStride] is undef and this is the first round of mixing, 5359 // then it is safe to just drop this shuffle: V[i] is already in the 5360 // right place, the one element (since it's the first round) being 5361 // inserted as undef can be dropped. This isn't safe for successive 5362 // rounds because they will permute elements within both vectors. 5363 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5364 EltStride == NumElems/2) 5365 continue; 5366 5367 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5368 } 5369 EltStride >>= 1; 5370 } 5371 return V[0]; 5372 } 5373 return SDValue(); 5374} 5375 5376// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5377// them in a MMX register. This is better than doing a stack convert. 5378static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5379 DebugLoc dl = Op.getDebugLoc(); 5380 EVT ResVT = Op.getValueType(); 5381 5382 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5383 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5384 int Mask[2]; 5385 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5386 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5387 InVec = Op.getOperand(1); 5388 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5389 unsigned NumElts = ResVT.getVectorNumElements(); 5390 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5391 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5392 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5393 } else { 5394 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5395 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5396 Mask[0] = 0; Mask[1] = 2; 5397 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5398 } 5399 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5400} 5401 5402// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5403// to create 256-bit vectors from two other 128-bit ones. 5404static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5405 DebugLoc dl = Op.getDebugLoc(); 5406 EVT ResVT = Op.getValueType(); 5407 5408 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5409 5410 SDValue V1 = Op.getOperand(0); 5411 SDValue V2 = Op.getOperand(1); 5412 unsigned NumElems = ResVT.getVectorNumElements(); 5413 5414 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5415} 5416 5417SDValue 5418X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5419 EVT ResVT = Op.getValueType(); 5420 5421 assert(Op.getNumOperands() == 2); 5422 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5423 "Unsupported CONCAT_VECTORS for value type"); 5424 5425 // We support concatenate two MMX registers and place them in a MMX register. 5426 // This is better than doing a stack convert. 5427 if (ResVT.is128BitVector()) 5428 return LowerMMXCONCAT_VECTORS(Op, DAG); 5429 5430 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5431 // from two other 128-bit ones. 5432 return LowerAVXCONCAT_VECTORS(Op, DAG); 5433} 5434 5435// Try to lower a shuffle node into a simple blend instruction. 5436static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5437 const X86Subtarget *Subtarget, 5438 SelectionDAG &DAG) { 5439 SDValue V1 = SVOp->getOperand(0); 5440 SDValue V2 = SVOp->getOperand(1); 5441 DebugLoc dl = SVOp->getDebugLoc(); 5442 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5443 unsigned NumElems = VT.getVectorNumElements(); 5444 5445 if (!Subtarget->hasSSE41()) 5446 return SDValue(); 5447 5448 unsigned ISDNo = 0; 5449 MVT OpTy; 5450 5451 switch (VT.SimpleTy) { 5452 default: return SDValue(); 5453 case MVT::v8i16: 5454 ISDNo = X86ISD::BLENDPW; 5455 OpTy = MVT::v8i16; 5456 break; 5457 case MVT::v4i32: 5458 case MVT::v4f32: 5459 ISDNo = X86ISD::BLENDPS; 5460 OpTy = MVT::v4f32; 5461 break; 5462 case MVT::v2i64: 5463 case MVT::v2f64: 5464 ISDNo = X86ISD::BLENDPD; 5465 OpTy = MVT::v2f64; 5466 break; 5467 case MVT::v8i32: 5468 case MVT::v8f32: 5469 if (!Subtarget->hasAVX()) 5470 return SDValue(); 5471 ISDNo = X86ISD::BLENDPS; 5472 OpTy = MVT::v8f32; 5473 break; 5474 case MVT::v4i64: 5475 case MVT::v4f64: 5476 if (!Subtarget->hasAVX()) 5477 return SDValue(); 5478 ISDNo = X86ISD::BLENDPD; 5479 OpTy = MVT::v4f64; 5480 break; 5481 } 5482 assert(ISDNo && "Invalid Op Number"); 5483 5484 unsigned MaskVals = 0; 5485 5486 for (unsigned i = 0; i != NumElems; ++i) { 5487 int EltIdx = SVOp->getMaskElt(i); 5488 if (EltIdx == (int)i || EltIdx < 0) 5489 MaskVals |= (1<<i); 5490 else if (EltIdx == (int)(i + NumElems)) 5491 continue; // Bit is set to zero; 5492 else 5493 return SDValue(); 5494 } 5495 5496 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); 5497 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2); 5498 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2, 5499 DAG.getConstant(MaskVals, MVT::i32)); 5500 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5501} 5502 5503// v8i16 shuffles - Prefer shuffles in the following order: 5504// 1. [all] pshuflw, pshufhw, optional move 5505// 2. [ssse3] 1 x pshufb 5506// 3. [ssse3] 2 x pshufb + 1 x por 5507// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5508SDValue 5509X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5510 SelectionDAG &DAG) const { 5511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5512 SDValue V1 = SVOp->getOperand(0); 5513 SDValue V2 = SVOp->getOperand(1); 5514 DebugLoc dl = SVOp->getDebugLoc(); 5515 SmallVector<int, 8> MaskVals; 5516 5517 // Determine if more than 1 of the words in each of the low and high quadwords 5518 // of the result come from the same quadword of one of the two inputs. Undef 5519 // mask values count as coming from any quadword, for better codegen. 5520 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5521 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5522 std::bitset<4> InputQuads; 5523 for (unsigned i = 0; i < 8; ++i) { 5524 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5525 int EltIdx = SVOp->getMaskElt(i); 5526 MaskVals.push_back(EltIdx); 5527 if (EltIdx < 0) { 5528 ++Quad[0]; 5529 ++Quad[1]; 5530 ++Quad[2]; 5531 ++Quad[3]; 5532 continue; 5533 } 5534 ++Quad[EltIdx / 4]; 5535 InputQuads.set(EltIdx / 4); 5536 } 5537 5538 int BestLoQuad = -1; 5539 unsigned MaxQuad = 1; 5540 for (unsigned i = 0; i < 4; ++i) { 5541 if (LoQuad[i] > MaxQuad) { 5542 BestLoQuad = i; 5543 MaxQuad = LoQuad[i]; 5544 } 5545 } 5546 5547 int BestHiQuad = -1; 5548 MaxQuad = 1; 5549 for (unsigned i = 0; i < 4; ++i) { 5550 if (HiQuad[i] > MaxQuad) { 5551 BestHiQuad = i; 5552 MaxQuad = HiQuad[i]; 5553 } 5554 } 5555 5556 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5557 // of the two input vectors, shuffle them into one input vector so only a 5558 // single pshufb instruction is necessary. If There are more than 2 input 5559 // quads, disable the next transformation since it does not help SSSE3. 5560 bool V1Used = InputQuads[0] || InputQuads[1]; 5561 bool V2Used = InputQuads[2] || InputQuads[3]; 5562 if (Subtarget->hasSSSE3()) { 5563 if (InputQuads.count() == 2 && V1Used && V2Used) { 5564 BestLoQuad = InputQuads[0] ? 0 : 1; 5565 BestHiQuad = InputQuads[2] ? 2 : 3; 5566 } 5567 if (InputQuads.count() > 2) { 5568 BestLoQuad = -1; 5569 BestHiQuad = -1; 5570 } 5571 } 5572 5573 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5574 // the shuffle mask. If a quad is scored as -1, that means that it contains 5575 // words from all 4 input quadwords. 5576 SDValue NewV; 5577 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5578 int MaskV[] = { 5579 BestLoQuad < 0 ? 0 : BestLoQuad, 5580 BestHiQuad < 0 ? 1 : BestHiQuad 5581 }; 5582 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5583 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5584 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5585 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5586 5587 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5588 // source words for the shuffle, to aid later transformations. 5589 bool AllWordsInNewV = true; 5590 bool InOrder[2] = { true, true }; 5591 for (unsigned i = 0; i != 8; ++i) { 5592 int idx = MaskVals[i]; 5593 if (idx != (int)i) 5594 InOrder[i/4] = false; 5595 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5596 continue; 5597 AllWordsInNewV = false; 5598 break; 5599 } 5600 5601 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5602 if (AllWordsInNewV) { 5603 for (int i = 0; i != 8; ++i) { 5604 int idx = MaskVals[i]; 5605 if (idx < 0) 5606 continue; 5607 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5608 if ((idx != i) && idx < 4) 5609 pshufhw = false; 5610 if ((idx != i) && idx > 3) 5611 pshuflw = false; 5612 } 5613 V1 = NewV; 5614 V2Used = false; 5615 BestLoQuad = 0; 5616 BestHiQuad = 1; 5617 } 5618 5619 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5620 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5621 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5622 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5623 unsigned TargetMask = 0; 5624 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5625 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5626 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5627 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5628 getShufflePSHUFLWImmediate(SVOp); 5629 V1 = NewV.getOperand(0); 5630 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5631 } 5632 } 5633 5634 // If we have SSSE3, and all words of the result are from 1 input vector, 5635 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5636 // is present, fall back to case 4. 5637 if (Subtarget->hasSSSE3()) { 5638 SmallVector<SDValue,16> pshufbMask; 5639 5640 // If we have elements from both input vectors, set the high bit of the 5641 // shuffle mask element to zero out elements that come from V2 in the V1 5642 // mask, and elements that come from V1 in the V2 mask, so that the two 5643 // results can be OR'd together. 5644 bool TwoInputs = V1Used && V2Used; 5645 for (unsigned i = 0; i != 8; ++i) { 5646 int EltIdx = MaskVals[i] * 2; 5647 if (TwoInputs && (EltIdx >= 16)) { 5648 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5649 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5650 continue; 5651 } 5652 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5653 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5654 } 5655 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5656 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5657 DAG.getNode(ISD::BUILD_VECTOR, dl, 5658 MVT::v16i8, &pshufbMask[0], 16)); 5659 if (!TwoInputs) 5660 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5661 5662 // Calculate the shuffle mask for the second input, shuffle it, and 5663 // OR it with the first shuffled input. 5664 pshufbMask.clear(); 5665 for (unsigned i = 0; i != 8; ++i) { 5666 int EltIdx = MaskVals[i] * 2; 5667 if (EltIdx < 16) { 5668 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5669 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5670 continue; 5671 } 5672 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5673 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5674 } 5675 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5676 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5677 DAG.getNode(ISD::BUILD_VECTOR, dl, 5678 MVT::v16i8, &pshufbMask[0], 16)); 5679 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5680 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5681 } 5682 5683 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5684 // and update MaskVals with new element order. 5685 std::bitset<8> InOrder; 5686 if (BestLoQuad >= 0) { 5687 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5688 for (int i = 0; i != 4; ++i) { 5689 int idx = MaskVals[i]; 5690 if (idx < 0) { 5691 InOrder.set(i); 5692 } else if ((idx / 4) == BestLoQuad) { 5693 MaskV[i] = idx & 3; 5694 InOrder.set(i); 5695 } 5696 } 5697 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5698 &MaskV[0]); 5699 5700 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5701 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5702 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5703 NewV.getOperand(0), 5704 getShufflePSHUFLWImmediate(SVOp), DAG); 5705 } 5706 } 5707 5708 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5709 // and update MaskVals with the new element order. 5710 if (BestHiQuad >= 0) { 5711 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5712 for (unsigned i = 4; i != 8; ++i) { 5713 int idx = MaskVals[i]; 5714 if (idx < 0) { 5715 InOrder.set(i); 5716 } else if ((idx / 4) == BestHiQuad) { 5717 MaskV[i] = (idx & 3) + 4; 5718 InOrder.set(i); 5719 } 5720 } 5721 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5722 &MaskV[0]); 5723 5724 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5726 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5727 NewV.getOperand(0), 5728 getShufflePSHUFHWImmediate(SVOp), DAG); 5729 } 5730 } 5731 5732 // In case BestHi & BestLo were both -1, which means each quadword has a word 5733 // from each of the four input quadwords, calculate the InOrder bitvector now 5734 // before falling through to the insert/extract cleanup. 5735 if (BestLoQuad == -1 && BestHiQuad == -1) { 5736 NewV = V1; 5737 for (int i = 0; i != 8; ++i) 5738 if (MaskVals[i] < 0 || MaskVals[i] == i) 5739 InOrder.set(i); 5740 } 5741 5742 // The other elements are put in the right place using pextrw and pinsrw. 5743 for (unsigned i = 0; i != 8; ++i) { 5744 if (InOrder[i]) 5745 continue; 5746 int EltIdx = MaskVals[i]; 5747 if (EltIdx < 0) 5748 continue; 5749 SDValue ExtOp = (EltIdx < 8) ? 5750 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5751 DAG.getIntPtrConstant(EltIdx)) : 5752 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5753 DAG.getIntPtrConstant(EltIdx - 8)); 5754 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5755 DAG.getIntPtrConstant(i)); 5756 } 5757 return NewV; 5758} 5759 5760// v16i8 shuffles - Prefer shuffles in the following order: 5761// 1. [ssse3] 1 x pshufb 5762// 2. [ssse3] 2 x pshufb + 1 x por 5763// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5764static 5765SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5766 SelectionDAG &DAG, 5767 const X86TargetLowering &TLI) { 5768 SDValue V1 = SVOp->getOperand(0); 5769 SDValue V2 = SVOp->getOperand(1); 5770 DebugLoc dl = SVOp->getDebugLoc(); 5771 ArrayRef<int> MaskVals = SVOp->getMask(); 5772 5773 // If we have SSSE3, case 1 is generated when all result bytes come from 5774 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5775 // present, fall back to case 3. 5776 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5777 bool V1Only = true; 5778 bool V2Only = true; 5779 for (unsigned i = 0; i < 16; ++i) { 5780 int EltIdx = MaskVals[i]; 5781 if (EltIdx < 0) 5782 continue; 5783 if (EltIdx < 16) 5784 V2Only = false; 5785 else 5786 V1Only = false; 5787 } 5788 5789 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5790 if (TLI.getSubtarget()->hasSSSE3()) { 5791 SmallVector<SDValue,16> pshufbMask; 5792 5793 // If all result elements are from one input vector, then only translate 5794 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5795 // 5796 // Otherwise, we have elements from both input vectors, and must zero out 5797 // elements that come from V2 in the first mask, and V1 in the second mask 5798 // so that we can OR them together. 5799 bool TwoInputs = !(V1Only || V2Only); 5800 for (unsigned i = 0; i != 16; ++i) { 5801 int EltIdx = MaskVals[i]; 5802 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5803 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5804 continue; 5805 } 5806 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5807 } 5808 // If all the elements are from V2, assign it to V1 and return after 5809 // building the first pshufb. 5810 if (V2Only) 5811 V1 = V2; 5812 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5813 DAG.getNode(ISD::BUILD_VECTOR, dl, 5814 MVT::v16i8, &pshufbMask[0], 16)); 5815 if (!TwoInputs) 5816 return V1; 5817 5818 // Calculate the shuffle mask for the second input, shuffle it, and 5819 // OR it with the first shuffled input. 5820 pshufbMask.clear(); 5821 for (unsigned i = 0; i != 16; ++i) { 5822 int EltIdx = MaskVals[i]; 5823 if (EltIdx < 16) { 5824 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5825 continue; 5826 } 5827 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5828 } 5829 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5830 DAG.getNode(ISD::BUILD_VECTOR, dl, 5831 MVT::v16i8, &pshufbMask[0], 16)); 5832 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5833 } 5834 5835 // No SSSE3 - Calculate in place words and then fix all out of place words 5836 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5837 // the 16 different words that comprise the two doublequadword input vectors. 5838 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5839 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5840 SDValue NewV = V2Only ? V2 : V1; 5841 for (int i = 0; i != 8; ++i) { 5842 int Elt0 = MaskVals[i*2]; 5843 int Elt1 = MaskVals[i*2+1]; 5844 5845 // This word of the result is all undef, skip it. 5846 if (Elt0 < 0 && Elt1 < 0) 5847 continue; 5848 5849 // This word of the result is already in the correct place, skip it. 5850 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5851 continue; 5852 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5853 continue; 5854 5855 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5856 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5857 SDValue InsElt; 5858 5859 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5860 // using a single extract together, load it and store it. 5861 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5862 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5863 DAG.getIntPtrConstant(Elt1 / 2)); 5864 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5865 DAG.getIntPtrConstant(i)); 5866 continue; 5867 } 5868 5869 // If Elt1 is defined, extract it from the appropriate source. If the 5870 // source byte is not also odd, shift the extracted word left 8 bits 5871 // otherwise clear the bottom 8 bits if we need to do an or. 5872 if (Elt1 >= 0) { 5873 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5874 DAG.getIntPtrConstant(Elt1 / 2)); 5875 if ((Elt1 & 1) == 0) 5876 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5877 DAG.getConstant(8, 5878 TLI.getShiftAmountTy(InsElt.getValueType()))); 5879 else if (Elt0 >= 0) 5880 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5881 DAG.getConstant(0xFF00, MVT::i16)); 5882 } 5883 // If Elt0 is defined, extract it from the appropriate source. If the 5884 // source byte is not also even, shift the extracted word right 8 bits. If 5885 // Elt1 was also defined, OR the extracted values together before 5886 // inserting them in the result. 5887 if (Elt0 >= 0) { 5888 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5889 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5890 if ((Elt0 & 1) != 0) 5891 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5892 DAG.getConstant(8, 5893 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5894 else if (Elt1 >= 0) 5895 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5896 DAG.getConstant(0x00FF, MVT::i16)); 5897 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5898 : InsElt0; 5899 } 5900 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5901 DAG.getIntPtrConstant(i)); 5902 } 5903 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5904} 5905 5906/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5907/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5908/// done when every pair / quad of shuffle mask elements point to elements in 5909/// the right sequence. e.g. 5910/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5911static 5912SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5913 SelectionDAG &DAG, DebugLoc dl) { 5914 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5915 unsigned NumElems = VT.getVectorNumElements(); 5916 MVT NewVT; 5917 unsigned Scale; 5918 switch (VT.SimpleTy) { 5919 default: llvm_unreachable("Unexpected!"); 5920 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break; 5921 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break; 5922 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break; 5923 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break; 5924 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; 5925 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break; 5926 } 5927 5928 SmallVector<int, 8> MaskVec; 5929 for (unsigned i = 0; i != NumElems; i += Scale) { 5930 int StartIdx = -1; 5931 for (unsigned j = 0; j != Scale; ++j) { 5932 int EltIdx = SVOp->getMaskElt(i+j); 5933 if (EltIdx < 0) 5934 continue; 5935 if (StartIdx < 0) 5936 StartIdx = (EltIdx / Scale); 5937 if (EltIdx != (int)(StartIdx*Scale + j)) 5938 return SDValue(); 5939 } 5940 MaskVec.push_back(StartIdx); 5941 } 5942 5943 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0)); 5944 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1)); 5945 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5946} 5947 5948/// getVZextMovL - Return a zero-extending vector move low node. 5949/// 5950static SDValue getVZextMovL(EVT VT, EVT OpVT, 5951 SDValue SrcOp, SelectionDAG &DAG, 5952 const X86Subtarget *Subtarget, DebugLoc dl) { 5953 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5954 LoadSDNode *LD = NULL; 5955 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5956 LD = dyn_cast<LoadSDNode>(SrcOp); 5957 if (!LD) { 5958 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5959 // instead. 5960 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5961 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5962 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5963 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5964 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5965 // PR2108 5966 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5967 return DAG.getNode(ISD::BITCAST, dl, VT, 5968 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5969 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5970 OpVT, 5971 SrcOp.getOperand(0) 5972 .getOperand(0)))); 5973 } 5974 } 5975 } 5976 5977 return DAG.getNode(ISD::BITCAST, dl, VT, 5978 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5979 DAG.getNode(ISD::BITCAST, dl, 5980 OpVT, SrcOp))); 5981} 5982 5983/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5984/// which could not be matched by any known target speficic shuffle 5985static SDValue 5986LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5987 EVT VT = SVOp->getValueType(0); 5988 5989 unsigned NumElems = VT.getVectorNumElements(); 5990 unsigned NumLaneElems = NumElems / 2; 5991 5992 DebugLoc dl = SVOp->getDebugLoc(); 5993 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5994 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 5995 SDValue Shufs[2]; 5996 5997 SmallVector<int, 16> Mask; 5998 for (unsigned l = 0; l < 2; ++l) { 5999 // Build a shuffle mask for the output, discovering on the fly which 6000 // input vectors to use as shuffle operands (recorded in InputUsed). 6001 // If building a suitable shuffle vector proves too hard, then bail 6002 // out with useBuildVector set. 6003 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 6004 unsigned LaneStart = l * NumLaneElems; 6005 for (unsigned i = 0; i != NumLaneElems; ++i) { 6006 // The mask element. This indexes into the input. 6007 int Idx = SVOp->getMaskElt(i+LaneStart); 6008 if (Idx < 0) { 6009 // the mask element does not index into any input vector. 6010 Mask.push_back(-1); 6011 continue; 6012 } 6013 6014 // The input vector this mask element indexes into. 6015 int Input = Idx / NumLaneElems; 6016 6017 // Turn the index into an offset from the start of the input vector. 6018 Idx -= Input * NumLaneElems; 6019 6020 // Find or create a shuffle vector operand to hold this input. 6021 unsigned OpNo; 6022 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6023 if (InputUsed[OpNo] == Input) 6024 // This input vector is already an operand. 6025 break; 6026 if (InputUsed[OpNo] < 0) { 6027 // Create a new operand for this input vector. 6028 InputUsed[OpNo] = Input; 6029 break; 6030 } 6031 } 6032 6033 if (OpNo >= array_lengthof(InputUsed)) { 6034 // More than two input vectors used! Give up. 6035 return SDValue(); 6036 } 6037 6038 // Add the mask index for the new shuffle vector. 6039 Mask.push_back(Idx + OpNo * NumLaneElems); 6040 } 6041 6042 if (InputUsed[0] < 0) { 6043 // No input vectors were used! The result is undefined. 6044 Shufs[l] = DAG.getUNDEF(NVT); 6045 } else { 6046 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6047 (InputUsed[0] % 2) * NumLaneElems, 6048 DAG, dl); 6049 // If only one input was used, use an undefined vector for the other. 6050 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6051 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6052 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6053 // At least one input vector was used. Create a new shuffle vector. 6054 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6055 } 6056 6057 Mask.clear(); 6058 } 6059 6060 // Concatenate the result back 6061 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]); 6062} 6063 6064/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6065/// 4 elements, and match them with several different shuffle types. 6066static SDValue 6067LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6068 SDValue V1 = SVOp->getOperand(0); 6069 SDValue V2 = SVOp->getOperand(1); 6070 DebugLoc dl = SVOp->getDebugLoc(); 6071 EVT VT = SVOp->getValueType(0); 6072 6073 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6074 6075 std::pair<int, int> Locs[4]; 6076 int Mask1[] = { -1, -1, -1, -1 }; 6077 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6078 6079 unsigned NumHi = 0; 6080 unsigned NumLo = 0; 6081 for (unsigned i = 0; i != 4; ++i) { 6082 int Idx = PermMask[i]; 6083 if (Idx < 0) { 6084 Locs[i] = std::make_pair(-1, -1); 6085 } else { 6086 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6087 if (Idx < 4) { 6088 Locs[i] = std::make_pair(0, NumLo); 6089 Mask1[NumLo] = Idx; 6090 NumLo++; 6091 } else { 6092 Locs[i] = std::make_pair(1, NumHi); 6093 if (2+NumHi < 4) 6094 Mask1[2+NumHi] = Idx; 6095 NumHi++; 6096 } 6097 } 6098 } 6099 6100 if (NumLo <= 2 && NumHi <= 2) { 6101 // If no more than two elements come from either vector. This can be 6102 // implemented with two shuffles. First shuffle gather the elements. 6103 // The second shuffle, which takes the first shuffle as both of its 6104 // vector operands, put the elements into the right order. 6105 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6106 6107 int Mask2[] = { -1, -1, -1, -1 }; 6108 6109 for (unsigned i = 0; i != 4; ++i) 6110 if (Locs[i].first != -1) { 6111 unsigned Idx = (i < 2) ? 0 : 4; 6112 Idx += Locs[i].first * 2 + Locs[i].second; 6113 Mask2[i] = Idx; 6114 } 6115 6116 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6117 } 6118 6119 if (NumLo == 3 || NumHi == 3) { 6120 // Otherwise, we must have three elements from one vector, call it X, and 6121 // one element from the other, call it Y. First, use a shufps to build an 6122 // intermediate vector with the one element from Y and the element from X 6123 // that will be in the same half in the final destination (the indexes don't 6124 // matter). Then, use a shufps to build the final vector, taking the half 6125 // containing the element from Y from the intermediate, and the other half 6126 // from X. 6127 if (NumHi == 3) { 6128 // Normalize it so the 3 elements come from V1. 6129 CommuteVectorShuffleMask(PermMask, 4); 6130 std::swap(V1, V2); 6131 } 6132 6133 // Find the element from V2. 6134 unsigned HiIndex; 6135 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6136 int Val = PermMask[HiIndex]; 6137 if (Val < 0) 6138 continue; 6139 if (Val >= 4) 6140 break; 6141 } 6142 6143 Mask1[0] = PermMask[HiIndex]; 6144 Mask1[1] = -1; 6145 Mask1[2] = PermMask[HiIndex^1]; 6146 Mask1[3] = -1; 6147 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6148 6149 if (HiIndex >= 2) { 6150 Mask1[0] = PermMask[0]; 6151 Mask1[1] = PermMask[1]; 6152 Mask1[2] = HiIndex & 1 ? 6 : 4; 6153 Mask1[3] = HiIndex & 1 ? 4 : 6; 6154 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6155 } 6156 6157 Mask1[0] = HiIndex & 1 ? 2 : 0; 6158 Mask1[1] = HiIndex & 1 ? 0 : 2; 6159 Mask1[2] = PermMask[2]; 6160 Mask1[3] = PermMask[3]; 6161 if (Mask1[2] >= 0) 6162 Mask1[2] += 4; 6163 if (Mask1[3] >= 0) 6164 Mask1[3] += 4; 6165 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6166 } 6167 6168 // Break it into (shuffle shuffle_hi, shuffle_lo). 6169 int LoMask[] = { -1, -1, -1, -1 }; 6170 int HiMask[] = { -1, -1, -1, -1 }; 6171 6172 int *MaskPtr = LoMask; 6173 unsigned MaskIdx = 0; 6174 unsigned LoIdx = 0; 6175 unsigned HiIdx = 2; 6176 for (unsigned i = 0; i != 4; ++i) { 6177 if (i == 2) { 6178 MaskPtr = HiMask; 6179 MaskIdx = 1; 6180 LoIdx = 0; 6181 HiIdx = 2; 6182 } 6183 int Idx = PermMask[i]; 6184 if (Idx < 0) { 6185 Locs[i] = std::make_pair(-1, -1); 6186 } else if (Idx < 4) { 6187 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6188 MaskPtr[LoIdx] = Idx; 6189 LoIdx++; 6190 } else { 6191 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6192 MaskPtr[HiIdx] = Idx; 6193 HiIdx++; 6194 } 6195 } 6196 6197 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6198 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6199 int MaskOps[] = { -1, -1, -1, -1 }; 6200 for (unsigned i = 0; i != 4; ++i) 6201 if (Locs[i].first != -1) 6202 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6203 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6204} 6205 6206static bool MayFoldVectorLoad(SDValue V) { 6207 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6208 V = V.getOperand(0); 6209 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6210 V = V.getOperand(0); 6211 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6212 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6213 // BUILD_VECTOR (load), undef 6214 V = V.getOperand(0); 6215 if (MayFoldLoad(V)) 6216 return true; 6217 return false; 6218} 6219 6220// FIXME: the version above should always be used. Since there's 6221// a bug where several vector shuffles can't be folded because the 6222// DAG is not updated during lowering and a node claims to have two 6223// uses while it only has one, use this version, and let isel match 6224// another instruction if the load really happens to have more than 6225// one use. Remove this version after this bug get fixed. 6226// rdar://8434668, PR8156 6227static bool RelaxedMayFoldVectorLoad(SDValue V) { 6228 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6229 V = V.getOperand(0); 6230 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6231 V = V.getOperand(0); 6232 if (ISD::isNormalLoad(V.getNode())) 6233 return true; 6234 return false; 6235} 6236 6237static 6238SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6239 EVT VT = Op.getValueType(); 6240 6241 // Canonizalize to v2f64. 6242 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6243 return DAG.getNode(ISD::BITCAST, dl, VT, 6244 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6245 V1, DAG)); 6246} 6247 6248static 6249SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6250 bool HasSSE2) { 6251 SDValue V1 = Op.getOperand(0); 6252 SDValue V2 = Op.getOperand(1); 6253 EVT VT = Op.getValueType(); 6254 6255 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6256 6257 if (HasSSE2 && VT == MVT::v2f64) 6258 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6259 6260 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6261 return DAG.getNode(ISD::BITCAST, dl, VT, 6262 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6263 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6264 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6265} 6266 6267static 6268SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6269 SDValue V1 = Op.getOperand(0); 6270 SDValue V2 = Op.getOperand(1); 6271 EVT VT = Op.getValueType(); 6272 6273 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6274 "unsupported shuffle type"); 6275 6276 if (V2.getOpcode() == ISD::UNDEF) 6277 V2 = V1; 6278 6279 // v4i32 or v4f32 6280 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6281} 6282 6283static 6284SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6285 SDValue V1 = Op.getOperand(0); 6286 SDValue V2 = Op.getOperand(1); 6287 EVT VT = Op.getValueType(); 6288 unsigned NumElems = VT.getVectorNumElements(); 6289 6290 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6291 // operand of these instructions is only memory, so check if there's a 6292 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6293 // same masks. 6294 bool CanFoldLoad = false; 6295 6296 // Trivial case, when V2 comes from a load. 6297 if (MayFoldVectorLoad(V2)) 6298 CanFoldLoad = true; 6299 6300 // When V1 is a load, it can be folded later into a store in isel, example: 6301 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6302 // turns into: 6303 // (MOVLPSmr addr:$src1, VR128:$src2) 6304 // So, recognize this potential and also use MOVLPS or MOVLPD 6305 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6306 CanFoldLoad = true; 6307 6308 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6309 if (CanFoldLoad) { 6310 if (HasSSE2 && NumElems == 2) 6311 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6312 6313 if (NumElems == 4) 6314 // If we don't care about the second element, procede to use movss. 6315 if (SVOp->getMaskElt(1) != -1) 6316 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6317 } 6318 6319 // movl and movlp will both match v2i64, but v2i64 is never matched by 6320 // movl earlier because we make it strict to avoid messing with the movlp load 6321 // folding logic (see the code above getMOVLP call). Match it here then, 6322 // this is horrible, but will stay like this until we move all shuffle 6323 // matching to x86 specific nodes. Note that for the 1st condition all 6324 // types are matched with movsd. 6325 if (HasSSE2) { 6326 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6327 // as to remove this logic from here, as much as possible 6328 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6329 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6330 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6331 } 6332 6333 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6334 6335 // Invert the operand order and use SHUFPS to match it. 6336 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6337 getShuffleSHUFImmediate(SVOp), DAG); 6338} 6339 6340SDValue 6341X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6343 EVT VT = Op.getValueType(); 6344 DebugLoc dl = Op.getDebugLoc(); 6345 SDValue V1 = Op.getOperand(0); 6346 SDValue V2 = Op.getOperand(1); 6347 6348 if (isZeroShuffle(SVOp)) 6349 return getZeroVector(VT, Subtarget, DAG, dl); 6350 6351 // Handle splat operations 6352 if (SVOp->isSplat()) { 6353 unsigned NumElem = VT.getVectorNumElements(); 6354 int Size = VT.getSizeInBits(); 6355 6356 // Use vbroadcast whenever the splat comes from a foldable load 6357 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6358 if (Broadcast.getNode()) 6359 return Broadcast; 6360 6361 // Handle splats by matching through known shuffle masks 6362 if ((Size == 128 && NumElem <= 4) || 6363 (Size == 256 && NumElem < 8)) 6364 return SDValue(); 6365 6366 // All remaning splats are promoted to target supported vector shuffles. 6367 return PromoteSplat(SVOp, DAG); 6368 } 6369 6370 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6371 // do it! 6372 if (VT == MVT::v8i16 || VT == MVT::v16i8 || 6373 VT == MVT::v16i16 || VT == MVT::v32i8) { 6374 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6375 if (NewOp.getNode()) 6376 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6377 } else if ((VT == MVT::v4i32 || 6378 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6379 // FIXME: Figure out a cleaner way to do this. 6380 // Try to make use of movq to zero out the top part. 6381 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6382 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6383 if (NewOp.getNode()) { 6384 EVT NewVT = NewOp.getValueType(); 6385 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6386 NewVT, true, false)) 6387 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6388 DAG, Subtarget, dl); 6389 } 6390 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6391 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6392 if (NewOp.getNode()) { 6393 EVT NewVT = NewOp.getValueType(); 6394 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6395 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6396 DAG, Subtarget, dl); 6397 } 6398 } 6399 } 6400 return SDValue(); 6401} 6402 6403SDValue 6404X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6406 SDValue V1 = Op.getOperand(0); 6407 SDValue V2 = Op.getOperand(1); 6408 EVT VT = Op.getValueType(); 6409 DebugLoc dl = Op.getDebugLoc(); 6410 unsigned NumElems = VT.getVectorNumElements(); 6411 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6412 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6413 bool V1IsSplat = false; 6414 bool V2IsSplat = false; 6415 bool HasSSE2 = Subtarget->hasSSE2(); 6416 bool HasAVX = Subtarget->hasAVX(); 6417 bool HasAVX2 = Subtarget->hasAVX2(); 6418 MachineFunction &MF = DAG.getMachineFunction(); 6419 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6420 6421 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6422 6423 if (V1IsUndef && V2IsUndef) 6424 return DAG.getUNDEF(VT); 6425 6426 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6427 6428 // Vector shuffle lowering takes 3 steps: 6429 // 6430 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6431 // narrowing and commutation of operands should be handled. 6432 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6433 // shuffle nodes. 6434 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6435 // so the shuffle can be broken into other shuffles and the legalizer can 6436 // try the lowering again. 6437 // 6438 // The general idea is that no vector_shuffle operation should be left to 6439 // be matched during isel, all of them must be converted to a target specific 6440 // node here. 6441 6442 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6443 // narrowing and commutation of operands should be handled. The actual code 6444 // doesn't include all of those, work in progress... 6445 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6446 if (NewOp.getNode()) 6447 return NewOp; 6448 6449 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6450 6451 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6452 // unpckh_undef). Only use pshufd if speed is more important than size. 6453 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6454 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6455 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6456 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6457 6458 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6459 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6460 return getMOVDDup(Op, dl, V1, DAG); 6461 6462 if (isMOVHLPS_v_undef_Mask(M, VT)) 6463 return getMOVHighToLow(Op, dl, DAG); 6464 6465 // Use to match splats 6466 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6467 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6468 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6469 6470 if (isPSHUFDMask(M, VT)) { 6471 // The actual implementation will match the mask in the if above and then 6472 // during isel it can match several different instructions, not only pshufd 6473 // as its name says, sad but true, emulate the behavior for now... 6474 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6475 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6476 6477 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6478 6479 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6480 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6481 6482 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6483 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6484 6485 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6486 TargetMask, DAG); 6487 } 6488 6489 // Check if this can be converted into a logical shift. 6490 bool isLeft = false; 6491 unsigned ShAmt = 0; 6492 SDValue ShVal; 6493 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6494 if (isShift && ShVal.hasOneUse()) { 6495 // If the shifted value has multiple uses, it may be cheaper to use 6496 // v_set0 + movlhps or movhlps, etc. 6497 EVT EltVT = VT.getVectorElementType(); 6498 ShAmt *= EltVT.getSizeInBits(); 6499 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6500 } 6501 6502 if (isMOVLMask(M, VT)) { 6503 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6504 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6505 if (!isMOVLPMask(M, VT)) { 6506 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6507 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6508 6509 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6510 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6511 } 6512 } 6513 6514 // FIXME: fold these into legal mask. 6515 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6516 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6517 6518 if (isMOVHLPSMask(M, VT)) 6519 return getMOVHighToLow(Op, dl, DAG); 6520 6521 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6522 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6523 6524 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6525 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6526 6527 if (isMOVLPMask(M, VT)) 6528 return getMOVLP(Op, dl, DAG, HasSSE2); 6529 6530 if (ShouldXformToMOVHLPS(M, VT) || 6531 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6532 return CommuteVectorShuffle(SVOp, DAG); 6533 6534 if (isShift) { 6535 // No better options. Use a vshldq / vsrldq. 6536 EVT EltVT = VT.getVectorElementType(); 6537 ShAmt *= EltVT.getSizeInBits(); 6538 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6539 } 6540 6541 bool Commuted = false; 6542 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6543 // 1,1,1,1 -> v8i16 though. 6544 V1IsSplat = isSplatVector(V1.getNode()); 6545 V2IsSplat = isSplatVector(V2.getNode()); 6546 6547 // Canonicalize the splat or undef, if present, to be on the RHS. 6548 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6549 CommuteVectorShuffleMask(M, NumElems); 6550 std::swap(V1, V2); 6551 std::swap(V1IsSplat, V2IsSplat); 6552 Commuted = true; 6553 } 6554 6555 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6556 // Shuffling low element of v1 into undef, just return v1. 6557 if (V2IsUndef) 6558 return V1; 6559 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6560 // the instruction selector will not match, so get a canonical MOVL with 6561 // swapped operands to undo the commute. 6562 return getMOVL(DAG, dl, VT, V2, V1); 6563 } 6564 6565 if (isUNPCKLMask(M, VT, HasAVX2)) 6566 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6567 6568 if (isUNPCKHMask(M, VT, HasAVX2)) 6569 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6570 6571 if (V2IsSplat) { 6572 // Normalize mask so all entries that point to V2 points to its first 6573 // element then try to match unpck{h|l} again. If match, return a 6574 // new vector_shuffle with the corrected mask.p 6575 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6576 NormalizeMask(NewMask, NumElems); 6577 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) 6578 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6579 if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) 6580 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6581 } 6582 6583 if (Commuted) { 6584 // Commute is back and try unpck* again. 6585 // FIXME: this seems wrong. 6586 CommuteVectorShuffleMask(M, NumElems); 6587 std::swap(V1, V2); 6588 std::swap(V1IsSplat, V2IsSplat); 6589 Commuted = false; 6590 6591 if (isUNPCKLMask(M, VT, HasAVX2)) 6592 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6593 6594 if (isUNPCKHMask(M, VT, HasAVX2)) 6595 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6596 } 6597 6598 // Normalize the node to match x86 shuffle ops if needed 6599 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6600 return CommuteVectorShuffle(SVOp, DAG); 6601 6602 // The checks below are all present in isShuffleMaskLegal, but they are 6603 // inlined here right now to enable us to directly emit target specific 6604 // nodes, and remove one by one until they don't return Op anymore. 6605 6606 if (isPALIGNRMask(M, VT, Subtarget)) 6607 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6608 getShufflePALIGNRImmediate(SVOp), 6609 DAG); 6610 6611 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6612 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6613 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6614 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6615 } 6616 6617 if (isPSHUFHWMask(M, VT, HasAVX2)) 6618 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6619 getShufflePSHUFHWImmediate(SVOp), 6620 DAG); 6621 6622 if (isPSHUFLWMask(M, VT, HasAVX2)) 6623 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6624 getShufflePSHUFLWImmediate(SVOp), 6625 DAG); 6626 6627 if (isSHUFPMask(M, VT, HasAVX)) 6628 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6629 getShuffleSHUFImmediate(SVOp), DAG); 6630 6631 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6632 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6633 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6634 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6635 6636 //===--------------------------------------------------------------------===// 6637 // Generate target specific nodes for 128 or 256-bit shuffles only 6638 // supported in the AVX instruction set. 6639 // 6640 6641 // Handle VMOVDDUPY permutations 6642 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6643 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6644 6645 // Handle VPERMILPS/D* permutations 6646 if (isVPERMILPMask(M, VT, HasAVX)) { 6647 if (HasAVX2 && VT == MVT::v8i32) 6648 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6649 getShuffleSHUFImmediate(SVOp), DAG); 6650 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6651 getShuffleSHUFImmediate(SVOp), DAG); 6652 } 6653 6654 // Handle VPERM2F128/VPERM2I128 permutations 6655 if (isVPERM2X128Mask(M, VT, HasAVX)) 6656 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6657 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6658 6659 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 6660 if (BlendOp.getNode()) 6661 return BlendOp; 6662 6663 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6664 SmallVector<SDValue, 8> permclMask; 6665 for (unsigned i = 0; i != 8; ++i) { 6666 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6667 } 6668 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6669 &permclMask[0], 8); 6670 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6671 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6672 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6673 } 6674 6675 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6676 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 6677 getShuffleCLImmediate(SVOp), DAG); 6678 6679 6680 //===--------------------------------------------------------------------===// 6681 // Since no target specific shuffle was selected for this generic one, 6682 // lower it into other known shuffles. FIXME: this isn't true yet, but 6683 // this is the plan. 6684 // 6685 6686 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6687 if (VT == MVT::v8i16) { 6688 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6689 if (NewOp.getNode()) 6690 return NewOp; 6691 } 6692 6693 if (VT == MVT::v16i8) { 6694 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6695 if (NewOp.getNode()) 6696 return NewOp; 6697 } 6698 6699 // Handle all 128-bit wide vectors with 4 elements, and match them with 6700 // several different shuffle types. 6701 if (NumElems == 4 && VT.getSizeInBits() == 128) 6702 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6703 6704 // Handle general 256-bit shuffles 6705 if (VT.is256BitVector()) 6706 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6707 6708 return SDValue(); 6709} 6710 6711SDValue 6712X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6713 SelectionDAG &DAG) const { 6714 EVT VT = Op.getValueType(); 6715 DebugLoc dl = Op.getDebugLoc(); 6716 6717 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6718 return SDValue(); 6719 6720 if (VT.getSizeInBits() == 8) { 6721 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6722 Op.getOperand(0), Op.getOperand(1)); 6723 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6724 DAG.getValueType(VT)); 6725 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6726 } 6727 6728 if (VT.getSizeInBits() == 16) { 6729 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6730 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6731 if (Idx == 0) 6732 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6733 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6734 DAG.getNode(ISD::BITCAST, dl, 6735 MVT::v4i32, 6736 Op.getOperand(0)), 6737 Op.getOperand(1))); 6738 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6739 Op.getOperand(0), Op.getOperand(1)); 6740 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6741 DAG.getValueType(VT)); 6742 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6743 } 6744 6745 if (VT == MVT::f32) { 6746 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6747 // the result back to FR32 register. It's only worth matching if the 6748 // result has a single use which is a store or a bitcast to i32. And in 6749 // the case of a store, it's not worth it if the index is a constant 0, 6750 // because a MOVSSmr can be used instead, which is smaller and faster. 6751 if (!Op.hasOneUse()) 6752 return SDValue(); 6753 SDNode *User = *Op.getNode()->use_begin(); 6754 if ((User->getOpcode() != ISD::STORE || 6755 (isa<ConstantSDNode>(Op.getOperand(1)) && 6756 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6757 (User->getOpcode() != ISD::BITCAST || 6758 User->getValueType(0) != MVT::i32)) 6759 return SDValue(); 6760 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6761 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6762 Op.getOperand(0)), 6763 Op.getOperand(1)); 6764 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6765 } 6766 6767 if (VT == MVT::i32 || VT == MVT::i64) { 6768 // ExtractPS/pextrq works with constant index. 6769 if (isa<ConstantSDNode>(Op.getOperand(1))) 6770 return Op; 6771 } 6772 return SDValue(); 6773} 6774 6775 6776SDValue 6777X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6778 SelectionDAG &DAG) const { 6779 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6780 return SDValue(); 6781 6782 SDValue Vec = Op.getOperand(0); 6783 EVT VecVT = Vec.getValueType(); 6784 6785 // If this is a 256-bit vector result, first extract the 128-bit vector and 6786 // then extract the element from the 128-bit vector. 6787 if (VecVT.getSizeInBits() == 256) { 6788 DebugLoc dl = Op.getNode()->getDebugLoc(); 6789 unsigned NumElems = VecVT.getVectorNumElements(); 6790 SDValue Idx = Op.getOperand(1); 6791 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6792 6793 // Get the 128-bit vector. 6794 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl); 6795 6796 if (IdxVal >= NumElems/2) 6797 IdxVal -= NumElems/2; 6798 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6799 DAG.getConstant(IdxVal, MVT::i32)); 6800 } 6801 6802 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6803 6804 if (Subtarget->hasSSE41()) { 6805 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6806 if (Res.getNode()) 6807 return Res; 6808 } 6809 6810 EVT VT = Op.getValueType(); 6811 DebugLoc dl = Op.getDebugLoc(); 6812 // TODO: handle v16i8. 6813 if (VT.getSizeInBits() == 16) { 6814 SDValue Vec = Op.getOperand(0); 6815 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6816 if (Idx == 0) 6817 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6818 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6819 DAG.getNode(ISD::BITCAST, dl, 6820 MVT::v4i32, Vec), 6821 Op.getOperand(1))); 6822 // Transform it so it match pextrw which produces a 32-bit result. 6823 EVT EltVT = MVT::i32; 6824 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6825 Op.getOperand(0), Op.getOperand(1)); 6826 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6827 DAG.getValueType(VT)); 6828 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6829 } 6830 6831 if (VT.getSizeInBits() == 32) { 6832 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6833 if (Idx == 0) 6834 return Op; 6835 6836 // SHUFPS the element to the lowest double word, then movss. 6837 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6838 EVT VVT = Op.getOperand(0).getValueType(); 6839 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6840 DAG.getUNDEF(VVT), Mask); 6841 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6842 DAG.getIntPtrConstant(0)); 6843 } 6844 6845 if (VT.getSizeInBits() == 64) { 6846 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6847 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6848 // to match extract_elt for f64. 6849 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6850 if (Idx == 0) 6851 return Op; 6852 6853 // UNPCKHPD the element to the lowest double word, then movsd. 6854 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6855 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6856 int Mask[2] = { 1, -1 }; 6857 EVT VVT = Op.getOperand(0).getValueType(); 6858 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6859 DAG.getUNDEF(VVT), Mask); 6860 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6861 DAG.getIntPtrConstant(0)); 6862 } 6863 6864 return SDValue(); 6865} 6866 6867SDValue 6868X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6869 SelectionDAG &DAG) const { 6870 EVT VT = Op.getValueType(); 6871 EVT EltVT = VT.getVectorElementType(); 6872 DebugLoc dl = Op.getDebugLoc(); 6873 6874 SDValue N0 = Op.getOperand(0); 6875 SDValue N1 = Op.getOperand(1); 6876 SDValue N2 = Op.getOperand(2); 6877 6878 if (VT.getSizeInBits() == 256) 6879 return SDValue(); 6880 6881 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6882 isa<ConstantSDNode>(N2)) { 6883 unsigned Opc; 6884 if (VT == MVT::v8i16) 6885 Opc = X86ISD::PINSRW; 6886 else if (VT == MVT::v16i8) 6887 Opc = X86ISD::PINSRB; 6888 else 6889 Opc = X86ISD::PINSRB; 6890 6891 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6892 // argument. 6893 if (N1.getValueType() != MVT::i32) 6894 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6895 if (N2.getValueType() != MVT::i32) 6896 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6897 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6898 } 6899 6900 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6901 // Bits [7:6] of the constant are the source select. This will always be 6902 // zero here. The DAG Combiner may combine an extract_elt index into these 6903 // bits. For example (insert (extract, 3), 2) could be matched by putting 6904 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6905 // Bits [5:4] of the constant are the destination select. This is the 6906 // value of the incoming immediate. 6907 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6908 // combine either bitwise AND or insert of float 0.0 to set these bits. 6909 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6910 // Create this as a scalar to vector.. 6911 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6912 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6913 } 6914 6915 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 6916 // PINSR* works with constant index. 6917 return Op; 6918 } 6919 return SDValue(); 6920} 6921 6922SDValue 6923X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6924 EVT VT = Op.getValueType(); 6925 EVT EltVT = VT.getVectorElementType(); 6926 6927 DebugLoc dl = Op.getDebugLoc(); 6928 SDValue N0 = Op.getOperand(0); 6929 SDValue N1 = Op.getOperand(1); 6930 SDValue N2 = Op.getOperand(2); 6931 6932 // If this is a 256-bit vector result, first extract the 128-bit vector, 6933 // insert the element into the extracted half and then place it back. 6934 if (VT.getSizeInBits() == 256) { 6935 if (!isa<ConstantSDNode>(N2)) 6936 return SDValue(); 6937 6938 // Get the desired 128-bit vector half. 6939 unsigned NumElems = VT.getVectorNumElements(); 6940 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6941 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl); 6942 6943 // Insert the element into the desired half. 6944 bool Upper = IdxVal >= NumElems/2; 6945 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1, 6946 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32)); 6947 6948 // Insert the changed part back to the 256-bit vector 6949 return Insert128BitVector(N0, V, IdxVal, DAG, dl); 6950 } 6951 6952 if (Subtarget->hasSSE41()) 6953 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6954 6955 if (EltVT == MVT::i8) 6956 return SDValue(); 6957 6958 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6959 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6960 // as its second argument. 6961 if (N1.getValueType() != MVT::i32) 6962 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6963 if (N2.getValueType() != MVT::i32) 6964 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6965 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6966 } 6967 return SDValue(); 6968} 6969 6970SDValue 6971X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6972 LLVMContext *Context = DAG.getContext(); 6973 DebugLoc dl = Op.getDebugLoc(); 6974 EVT OpVT = Op.getValueType(); 6975 6976 // If this is a 256-bit vector result, first insert into a 128-bit 6977 // vector and then insert into the 256-bit vector. 6978 if (OpVT.getSizeInBits() > 128) { 6979 // Insert into a 128-bit vector. 6980 EVT VT128 = EVT::getVectorVT(*Context, 6981 OpVT.getVectorElementType(), 6982 OpVT.getVectorNumElements() / 2); 6983 6984 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6985 6986 // Insert the 128-bit vector. 6987 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 6988 } 6989 6990 if (OpVT == MVT::v1i64 && 6991 Op.getOperand(0).getValueType() == MVT::i64) 6992 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6993 6994 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6995 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!"); 6996 return DAG.getNode(ISD::BITCAST, dl, OpVT, 6997 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6998} 6999 7000// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7001// a simple subregister reference or explicit instructions to grab 7002// upper bits of a vector. 7003SDValue 7004X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7005 if (Subtarget->hasAVX()) { 7006 DebugLoc dl = Op.getNode()->getDebugLoc(); 7007 SDValue Vec = Op.getNode()->getOperand(0); 7008 SDValue Idx = Op.getNode()->getOperand(1); 7009 7010 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 && 7011 Vec.getNode()->getValueType(0).getSizeInBits() == 256 && 7012 isa<ConstantSDNode>(Idx)) { 7013 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7014 return Extract128BitVector(Vec, IdxVal, DAG, dl); 7015 } 7016 } 7017 return SDValue(); 7018} 7019 7020// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7021// simple superregister reference or explicit instructions to insert 7022// the upper bits of a vector. 7023SDValue 7024X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7025 if (Subtarget->hasAVX()) { 7026 DebugLoc dl = Op.getNode()->getDebugLoc(); 7027 SDValue Vec = Op.getNode()->getOperand(0); 7028 SDValue SubVec = Op.getNode()->getOperand(1); 7029 SDValue Idx = Op.getNode()->getOperand(2); 7030 7031 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 && 7032 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 && 7033 isa<ConstantSDNode>(Idx)) { 7034 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7035 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7036 } 7037 } 7038 return SDValue(); 7039} 7040 7041// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7042// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7043// one of the above mentioned nodes. It has to be wrapped because otherwise 7044// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7045// be used to form addressing mode. These wrapped nodes will be selected 7046// into MOV32ri. 7047SDValue 7048X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7049 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7050 7051 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7052 // global base reg. 7053 unsigned char OpFlag = 0; 7054 unsigned WrapperKind = X86ISD::Wrapper; 7055 CodeModel::Model M = getTargetMachine().getCodeModel(); 7056 7057 if (Subtarget->isPICStyleRIPRel() && 7058 (M == CodeModel::Small || M == CodeModel::Kernel)) 7059 WrapperKind = X86ISD::WrapperRIP; 7060 else if (Subtarget->isPICStyleGOT()) 7061 OpFlag = X86II::MO_GOTOFF; 7062 else if (Subtarget->isPICStyleStubPIC()) 7063 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7064 7065 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7066 CP->getAlignment(), 7067 CP->getOffset(), OpFlag); 7068 DebugLoc DL = CP->getDebugLoc(); 7069 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7070 // With PIC, the address is actually $g + Offset. 7071 if (OpFlag) { 7072 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7073 DAG.getNode(X86ISD::GlobalBaseReg, 7074 DebugLoc(), getPointerTy()), 7075 Result); 7076 } 7077 7078 return Result; 7079} 7080 7081SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7082 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7083 7084 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7085 // global base reg. 7086 unsigned char OpFlag = 0; 7087 unsigned WrapperKind = X86ISD::Wrapper; 7088 CodeModel::Model M = getTargetMachine().getCodeModel(); 7089 7090 if (Subtarget->isPICStyleRIPRel() && 7091 (M == CodeModel::Small || M == CodeModel::Kernel)) 7092 WrapperKind = X86ISD::WrapperRIP; 7093 else if (Subtarget->isPICStyleGOT()) 7094 OpFlag = X86II::MO_GOTOFF; 7095 else if (Subtarget->isPICStyleStubPIC()) 7096 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7097 7098 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7099 OpFlag); 7100 DebugLoc DL = JT->getDebugLoc(); 7101 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7102 7103 // With PIC, the address is actually $g + Offset. 7104 if (OpFlag) 7105 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7106 DAG.getNode(X86ISD::GlobalBaseReg, 7107 DebugLoc(), getPointerTy()), 7108 Result); 7109 7110 return Result; 7111} 7112 7113SDValue 7114X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7115 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7116 7117 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7118 // global base reg. 7119 unsigned char OpFlag = 0; 7120 unsigned WrapperKind = X86ISD::Wrapper; 7121 CodeModel::Model M = getTargetMachine().getCodeModel(); 7122 7123 if (Subtarget->isPICStyleRIPRel() && 7124 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7125 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7126 OpFlag = X86II::MO_GOTPCREL; 7127 WrapperKind = X86ISD::WrapperRIP; 7128 } else if (Subtarget->isPICStyleGOT()) { 7129 OpFlag = X86II::MO_GOT; 7130 } else if (Subtarget->isPICStyleStubPIC()) { 7131 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7132 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7133 OpFlag = X86II::MO_DARWIN_NONLAZY; 7134 } 7135 7136 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7137 7138 DebugLoc DL = Op.getDebugLoc(); 7139 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7140 7141 7142 // With PIC, the address is actually $g + Offset. 7143 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7144 !Subtarget->is64Bit()) { 7145 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7146 DAG.getNode(X86ISD::GlobalBaseReg, 7147 DebugLoc(), getPointerTy()), 7148 Result); 7149 } 7150 7151 // For symbols that require a load from a stub to get the address, emit the 7152 // load. 7153 if (isGlobalStubReference(OpFlag)) 7154 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7155 MachinePointerInfo::getGOT(), false, false, false, 0); 7156 7157 return Result; 7158} 7159 7160SDValue 7161X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7162 // Create the TargetBlockAddressAddress node. 7163 unsigned char OpFlags = 7164 Subtarget->ClassifyBlockAddressReference(); 7165 CodeModel::Model M = getTargetMachine().getCodeModel(); 7166 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7167 DebugLoc dl = Op.getDebugLoc(); 7168 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7169 /*isTarget=*/true, OpFlags); 7170 7171 if (Subtarget->isPICStyleRIPRel() && 7172 (M == CodeModel::Small || M == CodeModel::Kernel)) 7173 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7174 else 7175 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7176 7177 // With PIC, the address is actually $g + Offset. 7178 if (isGlobalRelativeToPICBase(OpFlags)) { 7179 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7180 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7181 Result); 7182 } 7183 7184 return Result; 7185} 7186 7187SDValue 7188X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7189 int64_t Offset, 7190 SelectionDAG &DAG) const { 7191 // Create the TargetGlobalAddress node, folding in the constant 7192 // offset if it is legal. 7193 unsigned char OpFlags = 7194 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7195 CodeModel::Model M = getTargetMachine().getCodeModel(); 7196 SDValue Result; 7197 if (OpFlags == X86II::MO_NO_FLAG && 7198 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7199 // A direct static reference to a global. 7200 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7201 Offset = 0; 7202 } else { 7203 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7204 } 7205 7206 if (Subtarget->isPICStyleRIPRel() && 7207 (M == CodeModel::Small || M == CodeModel::Kernel)) 7208 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7209 else 7210 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7211 7212 // With PIC, the address is actually $g + Offset. 7213 if (isGlobalRelativeToPICBase(OpFlags)) { 7214 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7215 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7216 Result); 7217 } 7218 7219 // For globals that require a load from a stub to get the address, emit the 7220 // load. 7221 if (isGlobalStubReference(OpFlags)) 7222 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7223 MachinePointerInfo::getGOT(), false, false, false, 0); 7224 7225 // If there was a non-zero offset that we didn't fold, create an explicit 7226 // addition for it. 7227 if (Offset != 0) 7228 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7229 DAG.getConstant(Offset, getPointerTy())); 7230 7231 return Result; 7232} 7233 7234SDValue 7235X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7236 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7237 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7238 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7239} 7240 7241static SDValue 7242GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7243 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7244 unsigned char OperandFlags) { 7245 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7246 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7247 DebugLoc dl = GA->getDebugLoc(); 7248 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7249 GA->getValueType(0), 7250 GA->getOffset(), 7251 OperandFlags); 7252 if (InFlag) { 7253 SDValue Ops[] = { Chain, TGA, *InFlag }; 7254 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7255 } else { 7256 SDValue Ops[] = { Chain, TGA }; 7257 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7258 } 7259 7260 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7261 MFI->setAdjustsStack(true); 7262 7263 SDValue Flag = Chain.getValue(1); 7264 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7265} 7266 7267// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7268static SDValue 7269LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7270 const EVT PtrVT) { 7271 SDValue InFlag; 7272 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7273 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7274 DAG.getNode(X86ISD::GlobalBaseReg, 7275 DebugLoc(), PtrVT), InFlag); 7276 InFlag = Chain.getValue(1); 7277 7278 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7279} 7280 7281// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7282static SDValue 7283LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7284 const EVT PtrVT) { 7285 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7286 X86::RAX, X86II::MO_TLSGD); 7287} 7288 7289// Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model. 7290static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7291 const EVT PtrVT, TLSModel::Model model, 7292 bool is64Bit, bool isPIC) { 7293 DebugLoc dl = GA->getDebugLoc(); 7294 7295 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7296 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7297 is64Bit ? 257 : 256)); 7298 7299 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7300 DAG.getIntPtrConstant(0), 7301 MachinePointerInfo(Ptr), 7302 false, false, false, 0); 7303 7304 unsigned char OperandFlags = 0; 7305 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7306 // initialexec. 7307 unsigned WrapperKind = X86ISD::Wrapper; 7308 if (model == TLSModel::LocalExec) { 7309 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7310 } else if (model == TLSModel::InitialExec) { 7311 if (is64Bit) { 7312 OperandFlags = X86II::MO_GOTTPOFF; 7313 WrapperKind = X86ISD::WrapperRIP; 7314 } else { 7315 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF; 7316 } 7317 } else { 7318 llvm_unreachable("Unexpected model"); 7319 } 7320 7321 // emit "addl x@ntpoff,%eax" (local exec) 7322 // or "addl x@indntpoff,%eax" (initial exec) 7323 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic) 7324 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7325 GA->getValueType(0), 7326 GA->getOffset(), OperandFlags); 7327 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7328 7329 if (model == TLSModel::InitialExec) { 7330 if (isPIC && !is64Bit) { 7331 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, 7332 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), 7333 Offset); 7334 } else { 7335 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7336 MachinePointerInfo::getGOT(), false, false, false, 7337 0); 7338 } 7339 } 7340 7341 // The address of the thread local variable is the add of the thread 7342 // pointer with the offset of the variable. 7343 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7344} 7345 7346SDValue 7347X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7348 7349 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7350 const GlobalValue *GV = GA->getGlobal(); 7351 7352 if (Subtarget->isTargetELF()) { 7353 // TODO: implement the "local dynamic" model 7354 7355 // If GV is an alias then use the aliasee for determining 7356 // thread-localness. 7357 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7358 GV = GA->resolveAliasedGlobal(false); 7359 7360 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7361 7362 switch (model) { 7363 case TLSModel::GeneralDynamic: 7364 case TLSModel::LocalDynamic: // not implemented 7365 if (Subtarget->is64Bit()) 7366 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7367 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7368 7369 case TLSModel::InitialExec: 7370 case TLSModel::LocalExec: 7371 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7372 Subtarget->is64Bit(), 7373 getTargetMachine().getRelocationModel() == Reloc::PIC_); 7374 } 7375 llvm_unreachable("Unknown TLS model."); 7376 } 7377 7378 if (Subtarget->isTargetDarwin()) { 7379 // Darwin only has one model of TLS. Lower to that. 7380 unsigned char OpFlag = 0; 7381 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7382 X86ISD::WrapperRIP : X86ISD::Wrapper; 7383 7384 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7385 // global base reg. 7386 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7387 !Subtarget->is64Bit(); 7388 if (PIC32) 7389 OpFlag = X86II::MO_TLVP_PIC_BASE; 7390 else 7391 OpFlag = X86II::MO_TLVP; 7392 DebugLoc DL = Op.getDebugLoc(); 7393 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7394 GA->getValueType(0), 7395 GA->getOffset(), OpFlag); 7396 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7397 7398 // With PIC32, the address is actually $g + Offset. 7399 if (PIC32) 7400 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7401 DAG.getNode(X86ISD::GlobalBaseReg, 7402 DebugLoc(), getPointerTy()), 7403 Offset); 7404 7405 // Lowering the machine isd will make sure everything is in the right 7406 // location. 7407 SDValue Chain = DAG.getEntryNode(); 7408 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7409 SDValue Args[] = { Chain, Offset }; 7410 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7411 7412 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7413 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7414 MFI->setAdjustsStack(true); 7415 7416 // And our return value (tls address) is in the standard call return value 7417 // location. 7418 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7419 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7420 Chain.getValue(1)); 7421 } 7422 7423 if (Subtarget->isTargetWindows()) { 7424 // Just use the implicit TLS architecture 7425 // Need to generate someting similar to: 7426 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7427 // ; from TEB 7428 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7429 // mov rcx, qword [rdx+rcx*8] 7430 // mov eax, .tls$:tlsvar 7431 // [rax+rcx] contains the address 7432 // Windows 64bit: gs:0x58 7433 // Windows 32bit: fs:__tls_array 7434 7435 // If GV is an alias then use the aliasee for determining 7436 // thread-localness. 7437 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7438 GV = GA->resolveAliasedGlobal(false); 7439 DebugLoc dl = GA->getDebugLoc(); 7440 SDValue Chain = DAG.getEntryNode(); 7441 7442 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7443 // %gs:0x58 (64-bit). 7444 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7445 ? Type::getInt8PtrTy(*DAG.getContext(), 7446 256) 7447 : Type::getInt32PtrTy(*DAG.getContext(), 7448 257)); 7449 7450 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7451 Subtarget->is64Bit() 7452 ? DAG.getIntPtrConstant(0x58) 7453 : DAG.getExternalSymbol("_tls_array", 7454 getPointerTy()), 7455 MachinePointerInfo(Ptr), 7456 false, false, false, 0); 7457 7458 // Load the _tls_index variable 7459 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7460 if (Subtarget->is64Bit()) 7461 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7462 IDX, MachinePointerInfo(), MVT::i32, 7463 false, false, 0); 7464 else 7465 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7466 false, false, false, 0); 7467 7468 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7469 getPointerTy()); 7470 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7471 7472 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7473 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7474 false, false, false, 0); 7475 7476 // Get the offset of start of .tls section 7477 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7478 GA->getValueType(0), 7479 GA->getOffset(), X86II::MO_SECREL); 7480 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7481 7482 // The address of the thread local variable is the add of the thread 7483 // pointer with the offset of the variable. 7484 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7485 } 7486 7487 llvm_unreachable("TLS not implemented for this target."); 7488} 7489 7490 7491/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7492/// and take a 2 x i32 value to shift plus a shift amount. 7493SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7494 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7495 EVT VT = Op.getValueType(); 7496 unsigned VTBits = VT.getSizeInBits(); 7497 DebugLoc dl = Op.getDebugLoc(); 7498 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7499 SDValue ShOpLo = Op.getOperand(0); 7500 SDValue ShOpHi = Op.getOperand(1); 7501 SDValue ShAmt = Op.getOperand(2); 7502 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7503 DAG.getConstant(VTBits - 1, MVT::i8)) 7504 : DAG.getConstant(0, VT); 7505 7506 SDValue Tmp2, Tmp3; 7507 if (Op.getOpcode() == ISD::SHL_PARTS) { 7508 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7509 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7510 } else { 7511 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7512 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7513 } 7514 7515 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7516 DAG.getConstant(VTBits, MVT::i8)); 7517 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7518 AndNode, DAG.getConstant(0, MVT::i8)); 7519 7520 SDValue Hi, Lo; 7521 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7522 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7523 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7524 7525 if (Op.getOpcode() == ISD::SHL_PARTS) { 7526 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7527 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7528 } else { 7529 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7530 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7531 } 7532 7533 SDValue Ops[2] = { Lo, Hi }; 7534 return DAG.getMergeValues(Ops, 2, dl); 7535} 7536 7537SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7538 SelectionDAG &DAG) const { 7539 EVT SrcVT = Op.getOperand(0).getValueType(); 7540 7541 if (SrcVT.isVector()) 7542 return SDValue(); 7543 7544 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7545 "Unknown SINT_TO_FP to lower!"); 7546 7547 // These are really Legal; return the operand so the caller accepts it as 7548 // Legal. 7549 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7550 return Op; 7551 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7552 Subtarget->is64Bit()) { 7553 return Op; 7554 } 7555 7556 DebugLoc dl = Op.getDebugLoc(); 7557 unsigned Size = SrcVT.getSizeInBits()/8; 7558 MachineFunction &MF = DAG.getMachineFunction(); 7559 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7560 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7561 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7562 StackSlot, 7563 MachinePointerInfo::getFixedStack(SSFI), 7564 false, false, 0); 7565 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7566} 7567 7568SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7569 SDValue StackSlot, 7570 SelectionDAG &DAG) const { 7571 // Build the FILD 7572 DebugLoc DL = Op.getDebugLoc(); 7573 SDVTList Tys; 7574 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7575 if (useSSE) 7576 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7577 else 7578 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7579 7580 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7581 7582 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7583 MachineMemOperand *MMO; 7584 if (FI) { 7585 int SSFI = FI->getIndex(); 7586 MMO = 7587 DAG.getMachineFunction() 7588 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7589 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7590 } else { 7591 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7592 StackSlot = StackSlot.getOperand(1); 7593 } 7594 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7595 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7596 X86ISD::FILD, DL, 7597 Tys, Ops, array_lengthof(Ops), 7598 SrcVT, MMO); 7599 7600 if (useSSE) { 7601 Chain = Result.getValue(1); 7602 SDValue InFlag = Result.getValue(2); 7603 7604 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7605 // shouldn't be necessary except that RFP cannot be live across 7606 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7607 MachineFunction &MF = DAG.getMachineFunction(); 7608 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7609 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7610 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7611 Tys = DAG.getVTList(MVT::Other); 7612 SDValue Ops[] = { 7613 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7614 }; 7615 MachineMemOperand *MMO = 7616 DAG.getMachineFunction() 7617 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7618 MachineMemOperand::MOStore, SSFISize, SSFISize); 7619 7620 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7621 Ops, array_lengthof(Ops), 7622 Op.getValueType(), MMO); 7623 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7624 MachinePointerInfo::getFixedStack(SSFI), 7625 false, false, false, 0); 7626 } 7627 7628 return Result; 7629} 7630 7631// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7632SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7633 SelectionDAG &DAG) const { 7634 // This algorithm is not obvious. Here it is what we're trying to output: 7635 /* 7636 movq %rax, %xmm0 7637 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7638 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7639 #ifdef __SSE3__ 7640 haddpd %xmm0, %xmm0 7641 #else 7642 pshufd $0x4e, %xmm0, %xmm1 7643 addpd %xmm1, %xmm0 7644 #endif 7645 */ 7646 7647 DebugLoc dl = Op.getDebugLoc(); 7648 LLVMContext *Context = DAG.getContext(); 7649 7650 // Build some magic constants. 7651 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7652 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7653 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7654 7655 SmallVector<Constant*,2> CV1; 7656 CV1.push_back( 7657 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7658 CV1.push_back( 7659 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7660 Constant *C1 = ConstantVector::get(CV1); 7661 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7662 7663 // Load the 64-bit value into an XMM register. 7664 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7665 Op.getOperand(0)); 7666 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7667 MachinePointerInfo::getConstantPool(), 7668 false, false, false, 16); 7669 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7670 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7671 CLod0); 7672 7673 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7674 MachinePointerInfo::getConstantPool(), 7675 false, false, false, 16); 7676 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7677 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7678 SDValue Result; 7679 7680 if (Subtarget->hasSSE3()) { 7681 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7682 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7683 } else { 7684 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7685 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7686 S2F, 0x4E, DAG); 7687 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7688 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7689 Sub); 7690 } 7691 7692 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7693 DAG.getIntPtrConstant(0)); 7694} 7695 7696// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7697SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7698 SelectionDAG &DAG) const { 7699 DebugLoc dl = Op.getDebugLoc(); 7700 // FP constant to bias correct the final result. 7701 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7702 MVT::f64); 7703 7704 // Load the 32-bit value into an XMM register. 7705 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7706 Op.getOperand(0)); 7707 7708 // Zero out the upper parts of the register. 7709 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7710 7711 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7712 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7713 DAG.getIntPtrConstant(0)); 7714 7715 // Or the load with the bias. 7716 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7717 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7718 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7719 MVT::v2f64, Load)), 7720 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7721 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7722 MVT::v2f64, Bias))); 7723 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7724 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7725 DAG.getIntPtrConstant(0)); 7726 7727 // Subtract the bias. 7728 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7729 7730 // Handle final rounding. 7731 EVT DestVT = Op.getValueType(); 7732 7733 if (DestVT.bitsLT(MVT::f64)) 7734 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7735 DAG.getIntPtrConstant(0)); 7736 if (DestVT.bitsGT(MVT::f64)) 7737 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7738 7739 // Handle final rounding. 7740 return Sub; 7741} 7742 7743SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7744 SelectionDAG &DAG) const { 7745 SDValue N0 = Op.getOperand(0); 7746 DebugLoc dl = Op.getDebugLoc(); 7747 7748 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7749 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7750 // the optimization here. 7751 if (DAG.SignBitIsZero(N0)) 7752 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7753 7754 EVT SrcVT = N0.getValueType(); 7755 EVT DstVT = Op.getValueType(); 7756 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7757 return LowerUINT_TO_FP_i64(Op, DAG); 7758 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7759 return LowerUINT_TO_FP_i32(Op, DAG); 7760 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 7761 return SDValue(); 7762 7763 // Make a 64-bit buffer, and use it to build an FILD. 7764 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7765 if (SrcVT == MVT::i32) { 7766 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7767 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7768 getPointerTy(), StackSlot, WordOff); 7769 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7770 StackSlot, MachinePointerInfo(), 7771 false, false, 0); 7772 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7773 OffsetSlot, MachinePointerInfo(), 7774 false, false, 0); 7775 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7776 return Fild; 7777 } 7778 7779 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7780 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7781 StackSlot, MachinePointerInfo(), 7782 false, false, 0); 7783 // For i64 source, we need to add the appropriate power of 2 if the input 7784 // was negative. This is the same as the optimization in 7785 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7786 // we must be careful to do the computation in x87 extended precision, not 7787 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7788 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7789 MachineMemOperand *MMO = 7790 DAG.getMachineFunction() 7791 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7792 MachineMemOperand::MOLoad, 8, 8); 7793 7794 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7795 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7796 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7797 MVT::i64, MMO); 7798 7799 APInt FF(32, 0x5F800000ULL); 7800 7801 // Check whether the sign bit is set. 7802 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7803 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7804 ISD::SETLT); 7805 7806 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7807 SDValue FudgePtr = DAG.getConstantPool( 7808 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7809 getPointerTy()); 7810 7811 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7812 SDValue Zero = DAG.getIntPtrConstant(0); 7813 SDValue Four = DAG.getIntPtrConstant(4); 7814 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7815 Zero, Four); 7816 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7817 7818 // Load the value out, extending it from f32 to f80. 7819 // FIXME: Avoid the extend by constructing the right constant pool? 7820 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7821 FudgePtr, MachinePointerInfo::getConstantPool(), 7822 MVT::f32, false, false, 4); 7823 // Extend everything to 80 bits to force it to be done on x87. 7824 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7825 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7826} 7827 7828std::pair<SDValue,SDValue> X86TargetLowering:: 7829FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7830 DebugLoc DL = Op.getDebugLoc(); 7831 7832 EVT DstTy = Op.getValueType(); 7833 7834 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7835 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7836 DstTy = MVT::i64; 7837 } 7838 7839 assert(DstTy.getSimpleVT() <= MVT::i64 && 7840 DstTy.getSimpleVT() >= MVT::i16 && 7841 "Unknown FP_TO_INT to lower!"); 7842 7843 // These are really Legal. 7844 if (DstTy == MVT::i32 && 7845 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7846 return std::make_pair(SDValue(), SDValue()); 7847 if (Subtarget->is64Bit() && 7848 DstTy == MVT::i64 && 7849 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7850 return std::make_pair(SDValue(), SDValue()); 7851 7852 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7853 // stack slot, or into the FTOL runtime function. 7854 MachineFunction &MF = DAG.getMachineFunction(); 7855 unsigned MemSize = DstTy.getSizeInBits()/8; 7856 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7857 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7858 7859 unsigned Opc; 7860 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7861 Opc = X86ISD::WIN_FTOL; 7862 else 7863 switch (DstTy.getSimpleVT().SimpleTy) { 7864 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7865 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7866 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7867 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7868 } 7869 7870 SDValue Chain = DAG.getEntryNode(); 7871 SDValue Value = Op.getOperand(0); 7872 EVT TheVT = Op.getOperand(0).getValueType(); 7873 // FIXME This causes a redundant load/store if the SSE-class value is already 7874 // in memory, such as if it is on the callstack. 7875 if (isScalarFPTypeInSSEReg(TheVT)) { 7876 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7877 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7878 MachinePointerInfo::getFixedStack(SSFI), 7879 false, false, 0); 7880 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7881 SDValue Ops[] = { 7882 Chain, StackSlot, DAG.getValueType(TheVT) 7883 }; 7884 7885 MachineMemOperand *MMO = 7886 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7887 MachineMemOperand::MOLoad, MemSize, MemSize); 7888 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7889 DstTy, MMO); 7890 Chain = Value.getValue(1); 7891 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7892 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7893 } 7894 7895 MachineMemOperand *MMO = 7896 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7897 MachineMemOperand::MOStore, MemSize, MemSize); 7898 7899 if (Opc != X86ISD::WIN_FTOL) { 7900 // Build the FP_TO_INT*_IN_MEM 7901 SDValue Ops[] = { Chain, Value, StackSlot }; 7902 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7903 Ops, 3, DstTy, MMO); 7904 return std::make_pair(FIST, StackSlot); 7905 } else { 7906 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7907 DAG.getVTList(MVT::Other, MVT::Glue), 7908 Chain, Value); 7909 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7910 MVT::i32, ftol.getValue(1)); 7911 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7912 MVT::i32, eax.getValue(2)); 7913 SDValue Ops[] = { eax, edx }; 7914 SDValue pair = IsReplace 7915 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7916 : DAG.getMergeValues(Ops, 2, DL); 7917 return std::make_pair(pair, SDValue()); 7918 } 7919} 7920 7921SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7922 SelectionDAG &DAG) const { 7923 if (Op.getValueType().isVector()) 7924 return SDValue(); 7925 7926 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7927 /*IsSigned=*/ true, /*IsReplace=*/ false); 7928 SDValue FIST = Vals.first, StackSlot = Vals.second; 7929 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7930 if (FIST.getNode() == 0) return Op; 7931 7932 if (StackSlot.getNode()) 7933 // Load the result. 7934 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7935 FIST, StackSlot, MachinePointerInfo(), 7936 false, false, false, 0); 7937 7938 // The node is the result. 7939 return FIST; 7940} 7941 7942SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7943 SelectionDAG &DAG) const { 7944 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7945 /*IsSigned=*/ false, /*IsReplace=*/ false); 7946 SDValue FIST = Vals.first, StackSlot = Vals.second; 7947 assert(FIST.getNode() && "Unexpected failure"); 7948 7949 if (StackSlot.getNode()) 7950 // Load the result. 7951 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7952 FIST, StackSlot, MachinePointerInfo(), 7953 false, false, false, 0); 7954 7955 // The node is the result. 7956 return FIST; 7957} 7958 7959SDValue X86TargetLowering::LowerFABS(SDValue Op, 7960 SelectionDAG &DAG) const { 7961 LLVMContext *Context = DAG.getContext(); 7962 DebugLoc dl = Op.getDebugLoc(); 7963 EVT VT = Op.getValueType(); 7964 EVT EltVT = VT; 7965 if (VT.isVector()) 7966 EltVT = VT.getVectorElementType(); 7967 Constant *C; 7968 if (EltVT == MVT::f64) { 7969 C = ConstantVector::getSplat(2, 7970 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7971 } else { 7972 C = ConstantVector::getSplat(4, 7973 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7974 } 7975 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7976 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7977 MachinePointerInfo::getConstantPool(), 7978 false, false, false, 16); 7979 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7980} 7981 7982SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7983 LLVMContext *Context = DAG.getContext(); 7984 DebugLoc dl = Op.getDebugLoc(); 7985 EVT VT = Op.getValueType(); 7986 EVT EltVT = VT; 7987 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7988 if (VT.isVector()) { 7989 EltVT = VT.getVectorElementType(); 7990 NumElts = VT.getVectorNumElements(); 7991 } 7992 Constant *C; 7993 if (EltVT == MVT::f64) 7994 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7995 else 7996 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7997 C = ConstantVector::getSplat(NumElts, C); 7998 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7999 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8000 MachinePointerInfo::getConstantPool(), 8001 false, false, false, 16); 8002 if (VT.isVector()) { 8003 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 8004 return DAG.getNode(ISD::BITCAST, dl, VT, 8005 DAG.getNode(ISD::XOR, dl, XORVT, 8006 DAG.getNode(ISD::BITCAST, dl, XORVT, 8007 Op.getOperand(0)), 8008 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 8009 } 8010 8011 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8012} 8013 8014SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8015 LLVMContext *Context = DAG.getContext(); 8016 SDValue Op0 = Op.getOperand(0); 8017 SDValue Op1 = Op.getOperand(1); 8018 DebugLoc dl = Op.getDebugLoc(); 8019 EVT VT = Op.getValueType(); 8020 EVT SrcVT = Op1.getValueType(); 8021 8022 // If second operand is smaller, extend it first. 8023 if (SrcVT.bitsLT(VT)) { 8024 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8025 SrcVT = VT; 8026 } 8027 // And if it is bigger, shrink it first. 8028 if (SrcVT.bitsGT(VT)) { 8029 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8030 SrcVT = VT; 8031 } 8032 8033 // At this point the operands and the result should have the same 8034 // type, and that won't be f80 since that is not custom lowered. 8035 8036 // First get the sign bit of second operand. 8037 SmallVector<Constant*,4> CV; 8038 if (SrcVT == MVT::f64) { 8039 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8040 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8041 } else { 8042 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8043 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8044 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8045 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8046 } 8047 Constant *C = ConstantVector::get(CV); 8048 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8049 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8050 MachinePointerInfo::getConstantPool(), 8051 false, false, false, 16); 8052 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8053 8054 // Shift sign bit right or left if the two operands have different types. 8055 if (SrcVT.bitsGT(VT)) { 8056 // Op0 is MVT::f32, Op1 is MVT::f64. 8057 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8058 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8059 DAG.getConstant(32, MVT::i32)); 8060 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8061 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8062 DAG.getIntPtrConstant(0)); 8063 } 8064 8065 // Clear first operand sign bit. 8066 CV.clear(); 8067 if (VT == MVT::f64) { 8068 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8069 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8070 } else { 8071 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8072 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8073 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8074 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8075 } 8076 C = ConstantVector::get(CV); 8077 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8078 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8079 MachinePointerInfo::getConstantPool(), 8080 false, false, false, 16); 8081 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8082 8083 // Or the value with the sign bit. 8084 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8085} 8086 8087SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8088 SDValue N0 = Op.getOperand(0); 8089 DebugLoc dl = Op.getDebugLoc(); 8090 EVT VT = Op.getValueType(); 8091 8092 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8093 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8094 DAG.getConstant(1, VT)); 8095 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8096} 8097 8098/// Emit nodes that will be selected as "test Op0,Op0", or something 8099/// equivalent. 8100SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8101 SelectionDAG &DAG) const { 8102 DebugLoc dl = Op.getDebugLoc(); 8103 8104 // CF and OF aren't always set the way we want. Determine which 8105 // of these we need. 8106 bool NeedCF = false; 8107 bool NeedOF = false; 8108 switch (X86CC) { 8109 default: break; 8110 case X86::COND_A: case X86::COND_AE: 8111 case X86::COND_B: case X86::COND_BE: 8112 NeedCF = true; 8113 break; 8114 case X86::COND_G: case X86::COND_GE: 8115 case X86::COND_L: case X86::COND_LE: 8116 case X86::COND_O: case X86::COND_NO: 8117 NeedOF = true; 8118 break; 8119 } 8120 8121 // See if we can use the EFLAGS value from the operand instead of 8122 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8123 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8124 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8125 // Emit a CMP with 0, which is the TEST pattern. 8126 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8127 DAG.getConstant(0, Op.getValueType())); 8128 8129 unsigned Opcode = 0; 8130 unsigned NumOperands = 0; 8131 switch (Op.getNode()->getOpcode()) { 8132 case ISD::ADD: 8133 // Due to an isel shortcoming, be conservative if this add is likely to be 8134 // selected as part of a load-modify-store instruction. When the root node 8135 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8136 // uses of other nodes in the match, such as the ADD in this case. This 8137 // leads to the ADD being left around and reselected, with the result being 8138 // two adds in the output. Alas, even if none our users are stores, that 8139 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8140 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8141 // climbing the DAG back to the root, and it doesn't seem to be worth the 8142 // effort. 8143 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8144 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8145 if (UI->getOpcode() != ISD::CopyToReg && 8146 UI->getOpcode() != ISD::SETCC && 8147 UI->getOpcode() != ISD::STORE) 8148 goto default_case; 8149 8150 if (ConstantSDNode *C = 8151 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8152 // An add of one will be selected as an INC. 8153 if (C->getAPIntValue() == 1) { 8154 Opcode = X86ISD::INC; 8155 NumOperands = 1; 8156 break; 8157 } 8158 8159 // An add of negative one (subtract of one) will be selected as a DEC. 8160 if (C->getAPIntValue().isAllOnesValue()) { 8161 Opcode = X86ISD::DEC; 8162 NumOperands = 1; 8163 break; 8164 } 8165 } 8166 8167 // Otherwise use a regular EFLAGS-setting add. 8168 Opcode = X86ISD::ADD; 8169 NumOperands = 2; 8170 break; 8171 case ISD::AND: { 8172 // If the primary and result isn't used, don't bother using X86ISD::AND, 8173 // because a TEST instruction will be better. 8174 bool NonFlagUse = false; 8175 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8176 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8177 SDNode *User = *UI; 8178 unsigned UOpNo = UI.getOperandNo(); 8179 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8180 // Look pass truncate. 8181 UOpNo = User->use_begin().getOperandNo(); 8182 User = *User->use_begin(); 8183 } 8184 8185 if (User->getOpcode() != ISD::BRCOND && 8186 User->getOpcode() != ISD::SETCC && 8187 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8188 NonFlagUse = true; 8189 break; 8190 } 8191 } 8192 8193 if (!NonFlagUse) 8194 break; 8195 } 8196 // FALL THROUGH 8197 case ISD::SUB: 8198 case ISD::OR: 8199 case ISD::XOR: 8200 // Due to the ISEL shortcoming noted above, be conservative if this op is 8201 // likely to be selected as part of a load-modify-store instruction. 8202 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8203 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8204 if (UI->getOpcode() == ISD::STORE) 8205 goto default_case; 8206 8207 // Otherwise use a regular EFLAGS-setting instruction. 8208 switch (Op.getNode()->getOpcode()) { 8209 default: llvm_unreachable("unexpected operator!"); 8210 case ISD::SUB: Opcode = X86ISD::SUB; break; 8211 case ISD::OR: Opcode = X86ISD::OR; break; 8212 case ISD::XOR: Opcode = X86ISD::XOR; break; 8213 case ISD::AND: Opcode = X86ISD::AND; break; 8214 } 8215 8216 NumOperands = 2; 8217 break; 8218 case X86ISD::ADD: 8219 case X86ISD::SUB: 8220 case X86ISD::INC: 8221 case X86ISD::DEC: 8222 case X86ISD::OR: 8223 case X86ISD::XOR: 8224 case X86ISD::AND: 8225 return SDValue(Op.getNode(), 1); 8226 default: 8227 default_case: 8228 break; 8229 } 8230 8231 if (Opcode == 0) 8232 // Emit a CMP with 0, which is the TEST pattern. 8233 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8234 DAG.getConstant(0, Op.getValueType())); 8235 8236 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8237 SmallVector<SDValue, 4> Ops; 8238 for (unsigned i = 0; i != NumOperands; ++i) 8239 Ops.push_back(Op.getOperand(i)); 8240 8241 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8242 DAG.ReplaceAllUsesWith(Op, New); 8243 return SDValue(New.getNode(), 1); 8244} 8245 8246/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8247/// equivalent. 8248SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8249 SelectionDAG &DAG) const { 8250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8251 if (C->getAPIntValue() == 0) 8252 return EmitTest(Op0, X86CC, DAG); 8253 8254 DebugLoc dl = Op0.getDebugLoc(); 8255 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8256} 8257 8258/// Convert a comparison if required by the subtarget. 8259SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 8260 SelectionDAG &DAG) const { 8261 // If the subtarget does not support the FUCOMI instruction, floating-point 8262 // comparisons have to be converted. 8263 if (Subtarget->hasCMov() || 8264 Cmp.getOpcode() != X86ISD::CMP || 8265 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 8266 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 8267 return Cmp; 8268 8269 // The instruction selector will select an FUCOM instruction instead of 8270 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 8271 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 8272 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 8273 DebugLoc dl = Cmp.getDebugLoc(); 8274 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 8275 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 8276 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 8277 DAG.getConstant(8, MVT::i8)); 8278 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 8279 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 8280} 8281 8282/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8283/// if it's possible. 8284SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8285 DebugLoc dl, SelectionDAG &DAG) const { 8286 SDValue Op0 = And.getOperand(0); 8287 SDValue Op1 = And.getOperand(1); 8288 if (Op0.getOpcode() == ISD::TRUNCATE) 8289 Op0 = Op0.getOperand(0); 8290 if (Op1.getOpcode() == ISD::TRUNCATE) 8291 Op1 = Op1.getOperand(0); 8292 8293 SDValue LHS, RHS; 8294 if (Op1.getOpcode() == ISD::SHL) 8295 std::swap(Op0, Op1); 8296 if (Op0.getOpcode() == ISD::SHL) { 8297 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8298 if (And00C->getZExtValue() == 1) { 8299 // If we looked past a truncate, check that it's only truncating away 8300 // known zeros. 8301 unsigned BitWidth = Op0.getValueSizeInBits(); 8302 unsigned AndBitWidth = And.getValueSizeInBits(); 8303 if (BitWidth > AndBitWidth) { 8304 APInt Zeros, Ones; 8305 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8306 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8307 return SDValue(); 8308 } 8309 LHS = Op1; 8310 RHS = Op0.getOperand(1); 8311 } 8312 } else if (Op1.getOpcode() == ISD::Constant) { 8313 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8314 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8315 SDValue AndLHS = Op0; 8316 8317 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8318 LHS = AndLHS.getOperand(0); 8319 RHS = AndLHS.getOperand(1); 8320 } 8321 8322 // Use BT if the immediate can't be encoded in a TEST instruction. 8323 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8324 LHS = AndLHS; 8325 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8326 } 8327 } 8328 8329 if (LHS.getNode()) { 8330 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8331 // instruction. Since the shift amount is in-range-or-undefined, we know 8332 // that doing a bittest on the i32 value is ok. We extend to i32 because 8333 // the encoding for the i16 version is larger than the i32 version. 8334 // Also promote i16 to i32 for performance / code size reason. 8335 if (LHS.getValueType() == MVT::i8 || 8336 LHS.getValueType() == MVT::i16) 8337 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8338 8339 // If the operand types disagree, extend the shift amount to match. Since 8340 // BT ignores high bits (like shifts) we can use anyextend. 8341 if (LHS.getValueType() != RHS.getValueType()) 8342 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8343 8344 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8345 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8346 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8347 DAG.getConstant(Cond, MVT::i8), BT); 8348 } 8349 8350 return SDValue(); 8351} 8352 8353SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8354 8355 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8356 8357 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8358 SDValue Op0 = Op.getOperand(0); 8359 SDValue Op1 = Op.getOperand(1); 8360 DebugLoc dl = Op.getDebugLoc(); 8361 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8362 8363 // Optimize to BT if possible. 8364 // Lower (X & (1 << N)) == 0 to BT(X, N). 8365 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8366 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8367 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8368 Op1.getOpcode() == ISD::Constant && 8369 cast<ConstantSDNode>(Op1)->isNullValue() && 8370 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8371 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8372 if (NewSetCC.getNode()) 8373 return NewSetCC; 8374 } 8375 8376 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8377 // these. 8378 if (Op1.getOpcode() == ISD::Constant && 8379 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8380 cast<ConstantSDNode>(Op1)->isNullValue()) && 8381 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8382 8383 // If the input is a setcc, then reuse the input setcc or use a new one with 8384 // the inverted condition. 8385 if (Op0.getOpcode() == X86ISD::SETCC) { 8386 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8387 bool Invert = (CC == ISD::SETNE) ^ 8388 cast<ConstantSDNode>(Op1)->isNullValue(); 8389 if (!Invert) return Op0; 8390 8391 CCode = X86::GetOppositeBranchCondition(CCode); 8392 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8393 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8394 } 8395 } 8396 8397 bool isFP = Op1.getValueType().isFloatingPoint(); 8398 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8399 if (X86CC == X86::COND_INVALID) 8400 return SDValue(); 8401 8402 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8403 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 8404 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8405 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8406} 8407 8408// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8409// ones, and then concatenate the result back. 8410static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8411 EVT VT = Op.getValueType(); 8412 8413 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8414 "Unsupported value type for operation"); 8415 8416 unsigned NumElems = VT.getVectorNumElements(); 8417 DebugLoc dl = Op.getDebugLoc(); 8418 SDValue CC = Op.getOperand(2); 8419 8420 // Extract the LHS vectors 8421 SDValue LHS = Op.getOperand(0); 8422 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 8423 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 8424 8425 // Extract the RHS vectors 8426 SDValue RHS = Op.getOperand(1); 8427 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 8428 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 8429 8430 // Issue the operation on the smaller types and concatenate the result back 8431 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8432 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8433 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8434 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8435 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8436} 8437 8438 8439SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8440 SDValue Cond; 8441 SDValue Op0 = Op.getOperand(0); 8442 SDValue Op1 = Op.getOperand(1); 8443 SDValue CC = Op.getOperand(2); 8444 EVT VT = Op.getValueType(); 8445 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8446 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8447 DebugLoc dl = Op.getDebugLoc(); 8448 8449 if (isFP) { 8450 unsigned SSECC = 8; 8451 EVT EltVT = Op0.getValueType().getVectorElementType(); 8452 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8453 8454 bool Swap = false; 8455 8456 // SSE Condition code mapping: 8457 // 0 - EQ 8458 // 1 - LT 8459 // 2 - LE 8460 // 3 - UNORD 8461 // 4 - NEQ 8462 // 5 - NLT 8463 // 6 - NLE 8464 // 7 - ORD 8465 switch (SetCCOpcode) { 8466 default: break; 8467 case ISD::SETOEQ: 8468 case ISD::SETEQ: SSECC = 0; break; 8469 case ISD::SETOGT: 8470 case ISD::SETGT: Swap = true; // Fallthrough 8471 case ISD::SETLT: 8472 case ISD::SETOLT: SSECC = 1; break; 8473 case ISD::SETOGE: 8474 case ISD::SETGE: Swap = true; // Fallthrough 8475 case ISD::SETLE: 8476 case ISD::SETOLE: SSECC = 2; break; 8477 case ISD::SETUO: SSECC = 3; break; 8478 case ISD::SETUNE: 8479 case ISD::SETNE: SSECC = 4; break; 8480 case ISD::SETULE: Swap = true; 8481 case ISD::SETUGE: SSECC = 5; break; 8482 case ISD::SETULT: Swap = true; 8483 case ISD::SETUGT: SSECC = 6; break; 8484 case ISD::SETO: SSECC = 7; break; 8485 } 8486 if (Swap) 8487 std::swap(Op0, Op1); 8488 8489 // In the two special cases we can't handle, emit two comparisons. 8490 if (SSECC == 8) { 8491 if (SetCCOpcode == ISD::SETUEQ) { 8492 SDValue UNORD, EQ; 8493 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8494 DAG.getConstant(3, MVT::i8)); 8495 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8496 DAG.getConstant(0, MVT::i8)); 8497 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8498 } 8499 if (SetCCOpcode == ISD::SETONE) { 8500 SDValue ORD, NEQ; 8501 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8502 DAG.getConstant(7, MVT::i8)); 8503 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8504 DAG.getConstant(4, MVT::i8)); 8505 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8506 } 8507 llvm_unreachable("Illegal FP comparison"); 8508 } 8509 // Handle all other FP comparisons here. 8510 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8511 DAG.getConstant(SSECC, MVT::i8)); 8512 } 8513 8514 // Break 256-bit integer vector compare into smaller ones. 8515 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8516 return Lower256IntVSETCC(Op, DAG); 8517 8518 // We are handling one of the integer comparisons here. Since SSE only has 8519 // GT and EQ comparisons for integer, swapping operands and multiple 8520 // operations may be required for some comparisons. 8521 unsigned Opc = 0; 8522 bool Swap = false, Invert = false, FlipSigns = false; 8523 8524 switch (SetCCOpcode) { 8525 default: break; 8526 case ISD::SETNE: Invert = true; 8527 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8528 case ISD::SETLT: Swap = true; 8529 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8530 case ISD::SETGE: Swap = true; 8531 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8532 case ISD::SETULT: Swap = true; 8533 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8534 case ISD::SETUGE: Swap = true; 8535 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8536 } 8537 if (Swap) 8538 std::swap(Op0, Op1); 8539 8540 // Check that the operation in question is available (most are plain SSE2, 8541 // but PCMPGTQ and PCMPEQQ have different requirements). 8542 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8543 return SDValue(); 8544 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8545 return SDValue(); 8546 8547 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8548 // bits of the inputs before performing those operations. 8549 if (FlipSigns) { 8550 EVT EltVT = VT.getVectorElementType(); 8551 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8552 EltVT); 8553 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8554 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8555 SignBits.size()); 8556 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8557 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8558 } 8559 8560 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8561 8562 // If the logical-not of the result is required, perform that now. 8563 if (Invert) 8564 Result = DAG.getNOT(dl, Result, VT); 8565 8566 return Result; 8567} 8568 8569// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8570static bool isX86LogicalCmp(SDValue Op) { 8571 unsigned Opc = Op.getNode()->getOpcode(); 8572 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 8573 Opc == X86ISD::SAHF) 8574 return true; 8575 if (Op.getResNo() == 1 && 8576 (Opc == X86ISD::ADD || 8577 Opc == X86ISD::SUB || 8578 Opc == X86ISD::ADC || 8579 Opc == X86ISD::SBB || 8580 Opc == X86ISD::SMUL || 8581 Opc == X86ISD::UMUL || 8582 Opc == X86ISD::INC || 8583 Opc == X86ISD::DEC || 8584 Opc == X86ISD::OR || 8585 Opc == X86ISD::XOR || 8586 Opc == X86ISD::AND)) 8587 return true; 8588 8589 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8590 return true; 8591 8592 return false; 8593} 8594 8595static bool isZero(SDValue V) { 8596 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8597 return C && C->isNullValue(); 8598} 8599 8600static bool isAllOnes(SDValue V) { 8601 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8602 return C && C->isAllOnesValue(); 8603} 8604 8605SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8606 bool addTest = true; 8607 SDValue Cond = Op.getOperand(0); 8608 SDValue Op1 = Op.getOperand(1); 8609 SDValue Op2 = Op.getOperand(2); 8610 DebugLoc DL = Op.getDebugLoc(); 8611 SDValue CC; 8612 8613 if (Cond.getOpcode() == ISD::SETCC) { 8614 SDValue NewCond = LowerSETCC(Cond, DAG); 8615 if (NewCond.getNode()) 8616 Cond = NewCond; 8617 } 8618 8619 // Handle the following cases related to max and min: 8620 // (a > b) ? (a-b) : 0 8621 // (a >= b) ? (a-b) : 0 8622 // (b < a) ? (a-b) : 0 8623 // (b <= a) ? (a-b) : 0 8624 // Comparison is removed to use EFLAGS from SUB. 8625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2)) 8626 if (Cond.getOpcode() == X86ISD::SETCC && 8627 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8628 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) && 8629 C->getAPIntValue() == 0) { 8630 SDValue Cmp = Cond.getOperand(1); 8631 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8632 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) && 8633 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) && 8634 (CC == X86::COND_G || CC == X86::COND_GE || 8635 CC == X86::COND_A || CC == X86::COND_AE)) || 8636 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) && 8637 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) && 8638 (CC == X86::COND_L || CC == X86::COND_LE || 8639 CC == X86::COND_B || CC == X86::COND_BE))) { 8640 8641 if (Op1.getOpcode() == ISD::SUB) { 8642 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32); 8643 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs, 8644 Op1.getOperand(0), Op1.getOperand(1)); 8645 DAG.ReplaceAllUsesWith(Op1, New); 8646 Op1 = New; 8647 } 8648 8649 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8650 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE || 8651 CC == X86::COND_L || 8652 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE; 8653 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8), 8654 SDValue(Op1.getNode(), 1) }; 8655 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8656 } 8657 } 8658 8659 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8660 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8661 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8662 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8663 if (Cond.getOpcode() == X86ISD::SETCC && 8664 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8665 isZero(Cond.getOperand(1).getOperand(1))) { 8666 SDValue Cmp = Cond.getOperand(1); 8667 8668 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8669 8670 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8671 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8672 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8673 8674 SDValue CmpOp0 = Cmp.getOperand(0); 8675 // Apply further optimizations for special cases 8676 // (select (x != 0), -1, 0) -> neg & sbb 8677 // (select (x == 0), 0, -1) -> neg & sbb 8678 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y)) 8679 if (YC->isNullValue() && 8680 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { 8681 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32); 8682 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs, 8683 DAG.getConstant(0, CmpOp0.getValueType()), 8684 CmpOp0); 8685 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8686 DAG.getConstant(X86::COND_B, MVT::i8), 8687 SDValue(Neg.getNode(), 1)); 8688 return Res; 8689 } 8690 8691 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8692 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8693 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 8694 8695 SDValue Res = // Res = 0 or -1. 8696 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8697 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8698 8699 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8700 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8701 8702 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8703 if (N2C == 0 || !N2C->isNullValue()) 8704 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8705 return Res; 8706 } 8707 } 8708 8709 // Look past (and (setcc_carry (cmp ...)), 1). 8710 if (Cond.getOpcode() == ISD::AND && 8711 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8712 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8713 if (C && C->getAPIntValue() == 1) 8714 Cond = Cond.getOperand(0); 8715 } 8716 8717 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8718 // setting operand in place of the X86ISD::SETCC. 8719 unsigned CondOpcode = Cond.getOpcode(); 8720 if (CondOpcode == X86ISD::SETCC || 8721 CondOpcode == X86ISD::SETCC_CARRY) { 8722 CC = Cond.getOperand(0); 8723 8724 SDValue Cmp = Cond.getOperand(1); 8725 unsigned Opc = Cmp.getOpcode(); 8726 EVT VT = Op.getValueType(); 8727 8728 bool IllegalFPCMov = false; 8729 if (VT.isFloatingPoint() && !VT.isVector() && 8730 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8731 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8732 8733 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8734 Opc == X86ISD::BT) { // FIXME 8735 Cond = Cmp; 8736 addTest = false; 8737 } 8738 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8739 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8740 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8741 Cond.getOperand(0).getValueType() != MVT::i8)) { 8742 SDValue LHS = Cond.getOperand(0); 8743 SDValue RHS = Cond.getOperand(1); 8744 unsigned X86Opcode; 8745 unsigned X86Cond; 8746 SDVTList VTs; 8747 switch (CondOpcode) { 8748 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8749 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8750 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8751 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8752 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8753 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8754 default: llvm_unreachable("unexpected overflowing operator"); 8755 } 8756 if (CondOpcode == ISD::UMULO) 8757 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8758 MVT::i32); 8759 else 8760 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8761 8762 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8763 8764 if (CondOpcode == ISD::UMULO) 8765 Cond = X86Op.getValue(2); 8766 else 8767 Cond = X86Op.getValue(1); 8768 8769 CC = DAG.getConstant(X86Cond, MVT::i8); 8770 addTest = false; 8771 } 8772 8773 if (addTest) { 8774 // Look pass the truncate. 8775 if (Cond.getOpcode() == ISD::TRUNCATE) 8776 Cond = Cond.getOperand(0); 8777 8778 // We know the result of AND is compared against zero. Try to match 8779 // it to BT. 8780 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8781 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8782 if (NewSetCC.getNode()) { 8783 CC = NewSetCC.getOperand(0); 8784 Cond = NewSetCC.getOperand(1); 8785 addTest = false; 8786 } 8787 } 8788 } 8789 8790 if (addTest) { 8791 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8792 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8793 } 8794 8795 // a < b ? -1 : 0 -> RES = ~setcc_carry 8796 // a < b ? 0 : -1 -> RES = setcc_carry 8797 // a >= b ? -1 : 0 -> RES = setcc_carry 8798 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8799 if (Cond.getOpcode() == X86ISD::CMP) { 8800 Cond = ConvertCmpIfNecessary(Cond, DAG); 8801 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8802 8803 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8804 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8805 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8806 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8807 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8808 return DAG.getNOT(DL, Res, Res.getValueType()); 8809 return Res; 8810 } 8811 } 8812 8813 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8814 // condition is true. 8815 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8816 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8817 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8818} 8819 8820// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8821// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8822// from the AND / OR. 8823static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8824 Opc = Op.getOpcode(); 8825 if (Opc != ISD::OR && Opc != ISD::AND) 8826 return false; 8827 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8828 Op.getOperand(0).hasOneUse() && 8829 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8830 Op.getOperand(1).hasOneUse()); 8831} 8832 8833// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8834// 1 and that the SETCC node has a single use. 8835static bool isXor1OfSetCC(SDValue Op) { 8836 if (Op.getOpcode() != ISD::XOR) 8837 return false; 8838 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8839 if (N1C && N1C->getAPIntValue() == 1) { 8840 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8841 Op.getOperand(0).hasOneUse(); 8842 } 8843 return false; 8844} 8845 8846SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8847 bool addTest = true; 8848 SDValue Chain = Op.getOperand(0); 8849 SDValue Cond = Op.getOperand(1); 8850 SDValue Dest = Op.getOperand(2); 8851 DebugLoc dl = Op.getDebugLoc(); 8852 SDValue CC; 8853 bool Inverted = false; 8854 8855 if (Cond.getOpcode() == ISD::SETCC) { 8856 // Check for setcc([su]{add,sub,mul}o == 0). 8857 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8858 isa<ConstantSDNode>(Cond.getOperand(1)) && 8859 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8860 Cond.getOperand(0).getResNo() == 1 && 8861 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8862 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8863 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8864 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8865 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8866 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8867 Inverted = true; 8868 Cond = Cond.getOperand(0); 8869 } else { 8870 SDValue NewCond = LowerSETCC(Cond, DAG); 8871 if (NewCond.getNode()) 8872 Cond = NewCond; 8873 } 8874 } 8875#if 0 8876 // FIXME: LowerXALUO doesn't handle these!! 8877 else if (Cond.getOpcode() == X86ISD::ADD || 8878 Cond.getOpcode() == X86ISD::SUB || 8879 Cond.getOpcode() == X86ISD::SMUL || 8880 Cond.getOpcode() == X86ISD::UMUL) 8881 Cond = LowerXALUO(Cond, DAG); 8882#endif 8883 8884 // Look pass (and (setcc_carry (cmp ...)), 1). 8885 if (Cond.getOpcode() == ISD::AND && 8886 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8888 if (C && C->getAPIntValue() == 1) 8889 Cond = Cond.getOperand(0); 8890 } 8891 8892 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8893 // setting operand in place of the X86ISD::SETCC. 8894 unsigned CondOpcode = Cond.getOpcode(); 8895 if (CondOpcode == X86ISD::SETCC || 8896 CondOpcode == X86ISD::SETCC_CARRY) { 8897 CC = Cond.getOperand(0); 8898 8899 SDValue Cmp = Cond.getOperand(1); 8900 unsigned Opc = Cmp.getOpcode(); 8901 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8902 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8903 Cond = Cmp; 8904 addTest = false; 8905 } else { 8906 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8907 default: break; 8908 case X86::COND_O: 8909 case X86::COND_B: 8910 // These can only come from an arithmetic instruction with overflow, 8911 // e.g. SADDO, UADDO. 8912 Cond = Cond.getNode()->getOperand(1); 8913 addTest = false; 8914 break; 8915 } 8916 } 8917 } 8918 CondOpcode = Cond.getOpcode(); 8919 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8920 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8921 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8922 Cond.getOperand(0).getValueType() != MVT::i8)) { 8923 SDValue LHS = Cond.getOperand(0); 8924 SDValue RHS = Cond.getOperand(1); 8925 unsigned X86Opcode; 8926 unsigned X86Cond; 8927 SDVTList VTs; 8928 switch (CondOpcode) { 8929 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8930 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8931 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8932 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8933 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8934 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8935 default: llvm_unreachable("unexpected overflowing operator"); 8936 } 8937 if (Inverted) 8938 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8939 if (CondOpcode == ISD::UMULO) 8940 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8941 MVT::i32); 8942 else 8943 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8944 8945 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8946 8947 if (CondOpcode == ISD::UMULO) 8948 Cond = X86Op.getValue(2); 8949 else 8950 Cond = X86Op.getValue(1); 8951 8952 CC = DAG.getConstant(X86Cond, MVT::i8); 8953 addTest = false; 8954 } else { 8955 unsigned CondOpc; 8956 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8957 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8958 if (CondOpc == ISD::OR) { 8959 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8960 // two branches instead of an explicit OR instruction with a 8961 // separate test. 8962 if (Cmp == Cond.getOperand(1).getOperand(1) && 8963 isX86LogicalCmp(Cmp)) { 8964 CC = Cond.getOperand(0).getOperand(0); 8965 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8966 Chain, Dest, CC, Cmp); 8967 CC = Cond.getOperand(1).getOperand(0); 8968 Cond = Cmp; 8969 addTest = false; 8970 } 8971 } else { // ISD::AND 8972 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8973 // two branches instead of an explicit AND instruction with a 8974 // separate test. However, we only do this if this block doesn't 8975 // have a fall-through edge, because this requires an explicit 8976 // jmp when the condition is false. 8977 if (Cmp == Cond.getOperand(1).getOperand(1) && 8978 isX86LogicalCmp(Cmp) && 8979 Op.getNode()->hasOneUse()) { 8980 X86::CondCode CCode = 8981 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8982 CCode = X86::GetOppositeBranchCondition(CCode); 8983 CC = DAG.getConstant(CCode, MVT::i8); 8984 SDNode *User = *Op.getNode()->use_begin(); 8985 // Look for an unconditional branch following this conditional branch. 8986 // We need this because we need to reverse the successors in order 8987 // to implement FCMP_OEQ. 8988 if (User->getOpcode() == ISD::BR) { 8989 SDValue FalseBB = User->getOperand(1); 8990 SDNode *NewBR = 8991 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8992 assert(NewBR == User); 8993 (void)NewBR; 8994 Dest = FalseBB; 8995 8996 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8997 Chain, Dest, CC, Cmp); 8998 X86::CondCode CCode = 8999 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9000 CCode = X86::GetOppositeBranchCondition(CCode); 9001 CC = DAG.getConstant(CCode, MVT::i8); 9002 Cond = Cmp; 9003 addTest = false; 9004 } 9005 } 9006 } 9007 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9008 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9009 // It should be transformed during dag combiner except when the condition 9010 // is set by a arithmetics with overflow node. 9011 X86::CondCode CCode = 9012 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9013 CCode = X86::GetOppositeBranchCondition(CCode); 9014 CC = DAG.getConstant(CCode, MVT::i8); 9015 Cond = Cond.getOperand(0).getOperand(1); 9016 addTest = false; 9017 } else if (Cond.getOpcode() == ISD::SETCC && 9018 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9019 // For FCMP_OEQ, we can emit 9020 // two branches instead of an explicit AND instruction with a 9021 // separate test. However, we only do this if this block doesn't 9022 // have a fall-through edge, because this requires an explicit 9023 // jmp when the condition is false. 9024 if (Op.getNode()->hasOneUse()) { 9025 SDNode *User = *Op.getNode()->use_begin(); 9026 // Look for an unconditional branch following this conditional branch. 9027 // We need this because we need to reverse the successors in order 9028 // to implement FCMP_OEQ. 9029 if (User->getOpcode() == ISD::BR) { 9030 SDValue FalseBB = User->getOperand(1); 9031 SDNode *NewBR = 9032 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9033 assert(NewBR == User); 9034 (void)NewBR; 9035 Dest = FalseBB; 9036 9037 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9038 Cond.getOperand(0), Cond.getOperand(1)); 9039 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9040 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9041 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9042 Chain, Dest, CC, Cmp); 9043 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9044 Cond = Cmp; 9045 addTest = false; 9046 } 9047 } 9048 } else if (Cond.getOpcode() == ISD::SETCC && 9049 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9050 // For FCMP_UNE, we can emit 9051 // two branches instead of an explicit AND instruction with a 9052 // separate test. However, we only do this if this block doesn't 9053 // have a fall-through edge, because this requires an explicit 9054 // jmp when the condition is false. 9055 if (Op.getNode()->hasOneUse()) { 9056 SDNode *User = *Op.getNode()->use_begin(); 9057 // Look for an unconditional branch following this conditional branch. 9058 // We need this because we need to reverse the successors in order 9059 // to implement FCMP_UNE. 9060 if (User->getOpcode() == ISD::BR) { 9061 SDValue FalseBB = User->getOperand(1); 9062 SDNode *NewBR = 9063 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9064 assert(NewBR == User); 9065 (void)NewBR; 9066 9067 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9068 Cond.getOperand(0), Cond.getOperand(1)); 9069 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 9070 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9071 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9072 Chain, Dest, CC, Cmp); 9073 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9074 Cond = Cmp; 9075 addTest = false; 9076 Dest = FalseBB; 9077 } 9078 } 9079 } 9080 } 9081 9082 if (addTest) { 9083 // Look pass the truncate. 9084 if (Cond.getOpcode() == ISD::TRUNCATE) 9085 Cond = Cond.getOperand(0); 9086 9087 // We know the result of AND is compared against zero. Try to match 9088 // it to BT. 9089 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9090 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9091 if (NewSetCC.getNode()) { 9092 CC = NewSetCC.getOperand(0); 9093 Cond = NewSetCC.getOperand(1); 9094 addTest = false; 9095 } 9096 } 9097 } 9098 9099 if (addTest) { 9100 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9101 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9102 } 9103 Cond = ConvertCmpIfNecessary(Cond, DAG); 9104 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9105 Chain, Dest, CC, Cond); 9106} 9107 9108 9109// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9110// Calls to _alloca is needed to probe the stack when allocating more than 4k 9111// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9112// that the guard pages used by the OS virtual memory manager are allocated in 9113// correct sequence. 9114SDValue 9115X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9116 SelectionDAG &DAG) const { 9117 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9118 getTargetMachine().Options.EnableSegmentedStacks) && 9119 "This should be used only on Windows targets or when segmented stacks " 9120 "are being used"); 9121 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9122 DebugLoc dl = Op.getDebugLoc(); 9123 9124 // Get the inputs. 9125 SDValue Chain = Op.getOperand(0); 9126 SDValue Size = Op.getOperand(1); 9127 // FIXME: Ensure alignment here 9128 9129 bool Is64Bit = Subtarget->is64Bit(); 9130 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9131 9132 if (getTargetMachine().Options.EnableSegmentedStacks) { 9133 MachineFunction &MF = DAG.getMachineFunction(); 9134 MachineRegisterInfo &MRI = MF.getRegInfo(); 9135 9136 if (Is64Bit) { 9137 // The 64 bit implementation of segmented stacks needs to clobber both r10 9138 // r11. This makes it impossible to use it along with nested parameters. 9139 const Function *F = MF.getFunction(); 9140 9141 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9142 I != E; ++I) 9143 if (I->hasNestAttr()) 9144 report_fatal_error("Cannot use segmented stacks with functions that " 9145 "have nested arguments."); 9146 } 9147 9148 const TargetRegisterClass *AddrRegClass = 9149 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9150 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9151 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9152 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9153 DAG.getRegister(Vreg, SPTy)); 9154 SDValue Ops1[2] = { Value, Chain }; 9155 return DAG.getMergeValues(Ops1, 2, dl); 9156 } else { 9157 SDValue Flag; 9158 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9159 9160 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9161 Flag = Chain.getValue(1); 9162 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9163 9164 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9165 Flag = Chain.getValue(1); 9166 9167 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9168 9169 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9170 return DAG.getMergeValues(Ops1, 2, dl); 9171 } 9172} 9173 9174SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9175 MachineFunction &MF = DAG.getMachineFunction(); 9176 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9177 9178 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9179 DebugLoc DL = Op.getDebugLoc(); 9180 9181 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9182 // vastart just stores the address of the VarArgsFrameIndex slot into the 9183 // memory location argument. 9184 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9185 getPointerTy()); 9186 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9187 MachinePointerInfo(SV), false, false, 0); 9188 } 9189 9190 // __va_list_tag: 9191 // gp_offset (0 - 6 * 8) 9192 // fp_offset (48 - 48 + 8 * 16) 9193 // overflow_arg_area (point to parameters coming in memory). 9194 // reg_save_area 9195 SmallVector<SDValue, 8> MemOps; 9196 SDValue FIN = Op.getOperand(1); 9197 // Store gp_offset 9198 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9199 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9200 MVT::i32), 9201 FIN, MachinePointerInfo(SV), false, false, 0); 9202 MemOps.push_back(Store); 9203 9204 // Store fp_offset 9205 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9206 FIN, DAG.getIntPtrConstant(4)); 9207 Store = DAG.getStore(Op.getOperand(0), DL, 9208 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9209 MVT::i32), 9210 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9211 MemOps.push_back(Store); 9212 9213 // Store ptr to overflow_arg_area 9214 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9215 FIN, DAG.getIntPtrConstant(4)); 9216 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9217 getPointerTy()); 9218 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9219 MachinePointerInfo(SV, 8), 9220 false, false, 0); 9221 MemOps.push_back(Store); 9222 9223 // Store ptr to reg_save_area. 9224 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9225 FIN, DAG.getIntPtrConstant(8)); 9226 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9227 getPointerTy()); 9228 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9229 MachinePointerInfo(SV, 16), false, false, 0); 9230 MemOps.push_back(Store); 9231 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9232 &MemOps[0], MemOps.size()); 9233} 9234 9235SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9236 assert(Subtarget->is64Bit() && 9237 "LowerVAARG only handles 64-bit va_arg!"); 9238 assert((Subtarget->isTargetLinux() || 9239 Subtarget->isTargetDarwin()) && 9240 "Unhandled target in LowerVAARG"); 9241 assert(Op.getNode()->getNumOperands() == 4); 9242 SDValue Chain = Op.getOperand(0); 9243 SDValue SrcPtr = Op.getOperand(1); 9244 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9245 unsigned Align = Op.getConstantOperandVal(3); 9246 DebugLoc dl = Op.getDebugLoc(); 9247 9248 EVT ArgVT = Op.getNode()->getValueType(0); 9249 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9250 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9251 uint8_t ArgMode; 9252 9253 // Decide which area this value should be read from. 9254 // TODO: Implement the AMD64 ABI in its entirety. This simple 9255 // selection mechanism works only for the basic types. 9256 if (ArgVT == MVT::f80) { 9257 llvm_unreachable("va_arg for f80 not yet implemented"); 9258 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9259 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9260 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9261 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9262 } else { 9263 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9264 } 9265 9266 if (ArgMode == 2) { 9267 // Sanity Check: Make sure using fp_offset makes sense. 9268 assert(!getTargetMachine().Options.UseSoftFloat && 9269 !(DAG.getMachineFunction() 9270 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9271 Subtarget->hasSSE1()); 9272 } 9273 9274 // Insert VAARG_64 node into the DAG 9275 // VAARG_64 returns two values: Variable Argument Address, Chain 9276 SmallVector<SDValue, 11> InstOps; 9277 InstOps.push_back(Chain); 9278 InstOps.push_back(SrcPtr); 9279 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9280 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9281 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9282 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9283 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9284 VTs, &InstOps[0], InstOps.size(), 9285 MVT::i64, 9286 MachinePointerInfo(SV), 9287 /*Align=*/0, 9288 /*Volatile=*/false, 9289 /*ReadMem=*/true, 9290 /*WriteMem=*/true); 9291 Chain = VAARG.getValue(1); 9292 9293 // Load the next argument and return it 9294 return DAG.getLoad(ArgVT, dl, 9295 Chain, 9296 VAARG, 9297 MachinePointerInfo(), 9298 false, false, false, 0); 9299} 9300 9301SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9302 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9303 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9304 SDValue Chain = Op.getOperand(0); 9305 SDValue DstPtr = Op.getOperand(1); 9306 SDValue SrcPtr = Op.getOperand(2); 9307 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9308 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9309 DebugLoc DL = Op.getDebugLoc(); 9310 9311 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9312 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9313 false, 9314 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9315} 9316 9317// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9318// may or may not be a constant. Takes immediate version of shift as input. 9319static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9320 SDValue SrcOp, SDValue ShAmt, 9321 SelectionDAG &DAG) { 9322 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9323 9324 if (isa<ConstantSDNode>(ShAmt)) { 9325 switch (Opc) { 9326 default: llvm_unreachable("Unknown target vector shift node"); 9327 case X86ISD::VSHLI: 9328 case X86ISD::VSRLI: 9329 case X86ISD::VSRAI: 9330 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9331 } 9332 } 9333 9334 // Change opcode to non-immediate version 9335 switch (Opc) { 9336 default: llvm_unreachable("Unknown target vector shift node"); 9337 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9338 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9339 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9340 } 9341 9342 // Need to build a vector containing shift amount 9343 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9344 SDValue ShOps[4]; 9345 ShOps[0] = ShAmt; 9346 ShOps[1] = DAG.getConstant(0, MVT::i32); 9347 ShOps[2] = DAG.getUNDEF(MVT::i32); 9348 ShOps[3] = DAG.getUNDEF(MVT::i32); 9349 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9350 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9351 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9352} 9353 9354SDValue 9355X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9356 DebugLoc dl = Op.getDebugLoc(); 9357 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9358 switch (IntNo) { 9359 default: return SDValue(); // Don't custom lower most intrinsics. 9360 // Comparison intrinsics. 9361 case Intrinsic::x86_sse_comieq_ss: 9362 case Intrinsic::x86_sse_comilt_ss: 9363 case Intrinsic::x86_sse_comile_ss: 9364 case Intrinsic::x86_sse_comigt_ss: 9365 case Intrinsic::x86_sse_comige_ss: 9366 case Intrinsic::x86_sse_comineq_ss: 9367 case Intrinsic::x86_sse_ucomieq_ss: 9368 case Intrinsic::x86_sse_ucomilt_ss: 9369 case Intrinsic::x86_sse_ucomile_ss: 9370 case Intrinsic::x86_sse_ucomigt_ss: 9371 case Intrinsic::x86_sse_ucomige_ss: 9372 case Intrinsic::x86_sse_ucomineq_ss: 9373 case Intrinsic::x86_sse2_comieq_sd: 9374 case Intrinsic::x86_sse2_comilt_sd: 9375 case Intrinsic::x86_sse2_comile_sd: 9376 case Intrinsic::x86_sse2_comigt_sd: 9377 case Intrinsic::x86_sse2_comige_sd: 9378 case Intrinsic::x86_sse2_comineq_sd: 9379 case Intrinsic::x86_sse2_ucomieq_sd: 9380 case Intrinsic::x86_sse2_ucomilt_sd: 9381 case Intrinsic::x86_sse2_ucomile_sd: 9382 case Intrinsic::x86_sse2_ucomigt_sd: 9383 case Intrinsic::x86_sse2_ucomige_sd: 9384 case Intrinsic::x86_sse2_ucomineq_sd: { 9385 unsigned Opc = 0; 9386 ISD::CondCode CC = ISD::SETCC_INVALID; 9387 switch (IntNo) { 9388 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9389 case Intrinsic::x86_sse_comieq_ss: 9390 case Intrinsic::x86_sse2_comieq_sd: 9391 Opc = X86ISD::COMI; 9392 CC = ISD::SETEQ; 9393 break; 9394 case Intrinsic::x86_sse_comilt_ss: 9395 case Intrinsic::x86_sse2_comilt_sd: 9396 Opc = X86ISD::COMI; 9397 CC = ISD::SETLT; 9398 break; 9399 case Intrinsic::x86_sse_comile_ss: 9400 case Intrinsic::x86_sse2_comile_sd: 9401 Opc = X86ISD::COMI; 9402 CC = ISD::SETLE; 9403 break; 9404 case Intrinsic::x86_sse_comigt_ss: 9405 case Intrinsic::x86_sse2_comigt_sd: 9406 Opc = X86ISD::COMI; 9407 CC = ISD::SETGT; 9408 break; 9409 case Intrinsic::x86_sse_comige_ss: 9410 case Intrinsic::x86_sse2_comige_sd: 9411 Opc = X86ISD::COMI; 9412 CC = ISD::SETGE; 9413 break; 9414 case Intrinsic::x86_sse_comineq_ss: 9415 case Intrinsic::x86_sse2_comineq_sd: 9416 Opc = X86ISD::COMI; 9417 CC = ISD::SETNE; 9418 break; 9419 case Intrinsic::x86_sse_ucomieq_ss: 9420 case Intrinsic::x86_sse2_ucomieq_sd: 9421 Opc = X86ISD::UCOMI; 9422 CC = ISD::SETEQ; 9423 break; 9424 case Intrinsic::x86_sse_ucomilt_ss: 9425 case Intrinsic::x86_sse2_ucomilt_sd: 9426 Opc = X86ISD::UCOMI; 9427 CC = ISD::SETLT; 9428 break; 9429 case Intrinsic::x86_sse_ucomile_ss: 9430 case Intrinsic::x86_sse2_ucomile_sd: 9431 Opc = X86ISD::UCOMI; 9432 CC = ISD::SETLE; 9433 break; 9434 case Intrinsic::x86_sse_ucomigt_ss: 9435 case Intrinsic::x86_sse2_ucomigt_sd: 9436 Opc = X86ISD::UCOMI; 9437 CC = ISD::SETGT; 9438 break; 9439 case Intrinsic::x86_sse_ucomige_ss: 9440 case Intrinsic::x86_sse2_ucomige_sd: 9441 Opc = X86ISD::UCOMI; 9442 CC = ISD::SETGE; 9443 break; 9444 case Intrinsic::x86_sse_ucomineq_ss: 9445 case Intrinsic::x86_sse2_ucomineq_sd: 9446 Opc = X86ISD::UCOMI; 9447 CC = ISD::SETNE; 9448 break; 9449 } 9450 9451 SDValue LHS = Op.getOperand(1); 9452 SDValue RHS = Op.getOperand(2); 9453 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9454 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9455 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9456 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9457 DAG.getConstant(X86CC, MVT::i8), Cond); 9458 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9459 } 9460 // XOP comparison intrinsics 9461 case Intrinsic::x86_xop_vpcomltb: 9462 case Intrinsic::x86_xop_vpcomltw: 9463 case Intrinsic::x86_xop_vpcomltd: 9464 case Intrinsic::x86_xop_vpcomltq: 9465 case Intrinsic::x86_xop_vpcomltub: 9466 case Intrinsic::x86_xop_vpcomltuw: 9467 case Intrinsic::x86_xop_vpcomltud: 9468 case Intrinsic::x86_xop_vpcomltuq: 9469 case Intrinsic::x86_xop_vpcomleb: 9470 case Intrinsic::x86_xop_vpcomlew: 9471 case Intrinsic::x86_xop_vpcomled: 9472 case Intrinsic::x86_xop_vpcomleq: 9473 case Intrinsic::x86_xop_vpcomleub: 9474 case Intrinsic::x86_xop_vpcomleuw: 9475 case Intrinsic::x86_xop_vpcomleud: 9476 case Intrinsic::x86_xop_vpcomleuq: 9477 case Intrinsic::x86_xop_vpcomgtb: 9478 case Intrinsic::x86_xop_vpcomgtw: 9479 case Intrinsic::x86_xop_vpcomgtd: 9480 case Intrinsic::x86_xop_vpcomgtq: 9481 case Intrinsic::x86_xop_vpcomgtub: 9482 case Intrinsic::x86_xop_vpcomgtuw: 9483 case Intrinsic::x86_xop_vpcomgtud: 9484 case Intrinsic::x86_xop_vpcomgtuq: 9485 case Intrinsic::x86_xop_vpcomgeb: 9486 case Intrinsic::x86_xop_vpcomgew: 9487 case Intrinsic::x86_xop_vpcomged: 9488 case Intrinsic::x86_xop_vpcomgeq: 9489 case Intrinsic::x86_xop_vpcomgeub: 9490 case Intrinsic::x86_xop_vpcomgeuw: 9491 case Intrinsic::x86_xop_vpcomgeud: 9492 case Intrinsic::x86_xop_vpcomgeuq: 9493 case Intrinsic::x86_xop_vpcomeqb: 9494 case Intrinsic::x86_xop_vpcomeqw: 9495 case Intrinsic::x86_xop_vpcomeqd: 9496 case Intrinsic::x86_xop_vpcomeqq: 9497 case Intrinsic::x86_xop_vpcomequb: 9498 case Intrinsic::x86_xop_vpcomequw: 9499 case Intrinsic::x86_xop_vpcomequd: 9500 case Intrinsic::x86_xop_vpcomequq: 9501 case Intrinsic::x86_xop_vpcomneb: 9502 case Intrinsic::x86_xop_vpcomnew: 9503 case Intrinsic::x86_xop_vpcomned: 9504 case Intrinsic::x86_xop_vpcomneq: 9505 case Intrinsic::x86_xop_vpcomneub: 9506 case Intrinsic::x86_xop_vpcomneuw: 9507 case Intrinsic::x86_xop_vpcomneud: 9508 case Intrinsic::x86_xop_vpcomneuq: 9509 case Intrinsic::x86_xop_vpcomfalseb: 9510 case Intrinsic::x86_xop_vpcomfalsew: 9511 case Intrinsic::x86_xop_vpcomfalsed: 9512 case Intrinsic::x86_xop_vpcomfalseq: 9513 case Intrinsic::x86_xop_vpcomfalseub: 9514 case Intrinsic::x86_xop_vpcomfalseuw: 9515 case Intrinsic::x86_xop_vpcomfalseud: 9516 case Intrinsic::x86_xop_vpcomfalseuq: 9517 case Intrinsic::x86_xop_vpcomtrueb: 9518 case Intrinsic::x86_xop_vpcomtruew: 9519 case Intrinsic::x86_xop_vpcomtrued: 9520 case Intrinsic::x86_xop_vpcomtrueq: 9521 case Intrinsic::x86_xop_vpcomtrueub: 9522 case Intrinsic::x86_xop_vpcomtrueuw: 9523 case Intrinsic::x86_xop_vpcomtrueud: 9524 case Intrinsic::x86_xop_vpcomtrueuq: { 9525 unsigned CC = 0; 9526 unsigned Opc = 0; 9527 9528 switch (IntNo) { 9529 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9530 case Intrinsic::x86_xop_vpcomltb: 9531 case Intrinsic::x86_xop_vpcomltw: 9532 case Intrinsic::x86_xop_vpcomltd: 9533 case Intrinsic::x86_xop_vpcomltq: 9534 CC = 0; 9535 Opc = X86ISD::VPCOM; 9536 break; 9537 case Intrinsic::x86_xop_vpcomltub: 9538 case Intrinsic::x86_xop_vpcomltuw: 9539 case Intrinsic::x86_xop_vpcomltud: 9540 case Intrinsic::x86_xop_vpcomltuq: 9541 CC = 0; 9542 Opc = X86ISD::VPCOMU; 9543 break; 9544 case Intrinsic::x86_xop_vpcomleb: 9545 case Intrinsic::x86_xop_vpcomlew: 9546 case Intrinsic::x86_xop_vpcomled: 9547 case Intrinsic::x86_xop_vpcomleq: 9548 CC = 1; 9549 Opc = X86ISD::VPCOM; 9550 break; 9551 case Intrinsic::x86_xop_vpcomleub: 9552 case Intrinsic::x86_xop_vpcomleuw: 9553 case Intrinsic::x86_xop_vpcomleud: 9554 case Intrinsic::x86_xop_vpcomleuq: 9555 CC = 1; 9556 Opc = X86ISD::VPCOMU; 9557 break; 9558 case Intrinsic::x86_xop_vpcomgtb: 9559 case Intrinsic::x86_xop_vpcomgtw: 9560 case Intrinsic::x86_xop_vpcomgtd: 9561 case Intrinsic::x86_xop_vpcomgtq: 9562 CC = 2; 9563 Opc = X86ISD::VPCOM; 9564 break; 9565 case Intrinsic::x86_xop_vpcomgtub: 9566 case Intrinsic::x86_xop_vpcomgtuw: 9567 case Intrinsic::x86_xop_vpcomgtud: 9568 case Intrinsic::x86_xop_vpcomgtuq: 9569 CC = 2; 9570 Opc = X86ISD::VPCOMU; 9571 break; 9572 case Intrinsic::x86_xop_vpcomgeb: 9573 case Intrinsic::x86_xop_vpcomgew: 9574 case Intrinsic::x86_xop_vpcomged: 9575 case Intrinsic::x86_xop_vpcomgeq: 9576 CC = 3; 9577 Opc = X86ISD::VPCOM; 9578 break; 9579 case Intrinsic::x86_xop_vpcomgeub: 9580 case Intrinsic::x86_xop_vpcomgeuw: 9581 case Intrinsic::x86_xop_vpcomgeud: 9582 case Intrinsic::x86_xop_vpcomgeuq: 9583 CC = 3; 9584 Opc = X86ISD::VPCOMU; 9585 break; 9586 case Intrinsic::x86_xop_vpcomeqb: 9587 case Intrinsic::x86_xop_vpcomeqw: 9588 case Intrinsic::x86_xop_vpcomeqd: 9589 case Intrinsic::x86_xop_vpcomeqq: 9590 CC = 4; 9591 Opc = X86ISD::VPCOM; 9592 break; 9593 case Intrinsic::x86_xop_vpcomequb: 9594 case Intrinsic::x86_xop_vpcomequw: 9595 case Intrinsic::x86_xop_vpcomequd: 9596 case Intrinsic::x86_xop_vpcomequq: 9597 CC = 4; 9598 Opc = X86ISD::VPCOMU; 9599 break; 9600 case Intrinsic::x86_xop_vpcomneb: 9601 case Intrinsic::x86_xop_vpcomnew: 9602 case Intrinsic::x86_xop_vpcomned: 9603 case Intrinsic::x86_xop_vpcomneq: 9604 CC = 5; 9605 Opc = X86ISD::VPCOM; 9606 break; 9607 case Intrinsic::x86_xop_vpcomneub: 9608 case Intrinsic::x86_xop_vpcomneuw: 9609 case Intrinsic::x86_xop_vpcomneud: 9610 case Intrinsic::x86_xop_vpcomneuq: 9611 CC = 5; 9612 Opc = X86ISD::VPCOMU; 9613 break; 9614 case Intrinsic::x86_xop_vpcomfalseb: 9615 case Intrinsic::x86_xop_vpcomfalsew: 9616 case Intrinsic::x86_xop_vpcomfalsed: 9617 case Intrinsic::x86_xop_vpcomfalseq: 9618 CC = 6; 9619 Opc = X86ISD::VPCOM; 9620 break; 9621 case Intrinsic::x86_xop_vpcomfalseub: 9622 case Intrinsic::x86_xop_vpcomfalseuw: 9623 case Intrinsic::x86_xop_vpcomfalseud: 9624 case Intrinsic::x86_xop_vpcomfalseuq: 9625 CC = 6; 9626 Opc = X86ISD::VPCOMU; 9627 break; 9628 case Intrinsic::x86_xop_vpcomtrueb: 9629 case Intrinsic::x86_xop_vpcomtruew: 9630 case Intrinsic::x86_xop_vpcomtrued: 9631 case Intrinsic::x86_xop_vpcomtrueq: 9632 CC = 7; 9633 Opc = X86ISD::VPCOM; 9634 break; 9635 case Intrinsic::x86_xop_vpcomtrueub: 9636 case Intrinsic::x86_xop_vpcomtrueuw: 9637 case Intrinsic::x86_xop_vpcomtrueud: 9638 case Intrinsic::x86_xop_vpcomtrueuq: 9639 CC = 7; 9640 Opc = X86ISD::VPCOMU; 9641 break; 9642 } 9643 9644 SDValue LHS = Op.getOperand(1); 9645 SDValue RHS = Op.getOperand(2); 9646 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9647 DAG.getConstant(CC, MVT::i8)); 9648 } 9649 9650 // Arithmetic intrinsics. 9651 case Intrinsic::x86_sse2_pmulu_dq: 9652 case Intrinsic::x86_avx2_pmulu_dq: 9653 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9654 Op.getOperand(1), Op.getOperand(2)); 9655 case Intrinsic::x86_sse3_hadd_ps: 9656 case Intrinsic::x86_sse3_hadd_pd: 9657 case Intrinsic::x86_avx_hadd_ps_256: 9658 case Intrinsic::x86_avx_hadd_pd_256: 9659 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9660 Op.getOperand(1), Op.getOperand(2)); 9661 case Intrinsic::x86_sse3_hsub_ps: 9662 case Intrinsic::x86_sse3_hsub_pd: 9663 case Intrinsic::x86_avx_hsub_ps_256: 9664 case Intrinsic::x86_avx_hsub_pd_256: 9665 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9666 Op.getOperand(1), Op.getOperand(2)); 9667 case Intrinsic::x86_ssse3_phadd_w_128: 9668 case Intrinsic::x86_ssse3_phadd_d_128: 9669 case Intrinsic::x86_avx2_phadd_w: 9670 case Intrinsic::x86_avx2_phadd_d: 9671 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9672 Op.getOperand(1), Op.getOperand(2)); 9673 case Intrinsic::x86_ssse3_phsub_w_128: 9674 case Intrinsic::x86_ssse3_phsub_d_128: 9675 case Intrinsic::x86_avx2_phsub_w: 9676 case Intrinsic::x86_avx2_phsub_d: 9677 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9678 Op.getOperand(1), Op.getOperand(2)); 9679 case Intrinsic::x86_avx2_psllv_d: 9680 case Intrinsic::x86_avx2_psllv_q: 9681 case Intrinsic::x86_avx2_psllv_d_256: 9682 case Intrinsic::x86_avx2_psllv_q_256: 9683 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9684 Op.getOperand(1), Op.getOperand(2)); 9685 case Intrinsic::x86_avx2_psrlv_d: 9686 case Intrinsic::x86_avx2_psrlv_q: 9687 case Intrinsic::x86_avx2_psrlv_d_256: 9688 case Intrinsic::x86_avx2_psrlv_q_256: 9689 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9690 Op.getOperand(1), Op.getOperand(2)); 9691 case Intrinsic::x86_avx2_psrav_d: 9692 case Intrinsic::x86_avx2_psrav_d_256: 9693 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9694 Op.getOperand(1), Op.getOperand(2)); 9695 case Intrinsic::x86_ssse3_pshuf_b_128: 9696 case Intrinsic::x86_avx2_pshuf_b: 9697 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9698 Op.getOperand(1), Op.getOperand(2)); 9699 case Intrinsic::x86_ssse3_psign_b_128: 9700 case Intrinsic::x86_ssse3_psign_w_128: 9701 case Intrinsic::x86_ssse3_psign_d_128: 9702 case Intrinsic::x86_avx2_psign_b: 9703 case Intrinsic::x86_avx2_psign_w: 9704 case Intrinsic::x86_avx2_psign_d: 9705 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9706 Op.getOperand(1), Op.getOperand(2)); 9707 case Intrinsic::x86_sse41_insertps: 9708 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9709 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9710 case Intrinsic::x86_avx_vperm2f128_ps_256: 9711 case Intrinsic::x86_avx_vperm2f128_pd_256: 9712 case Intrinsic::x86_avx_vperm2f128_si_256: 9713 case Intrinsic::x86_avx2_vperm2i128: 9714 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9715 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9716 case Intrinsic::x86_avx2_permd: 9717 case Intrinsic::x86_avx2_permps: 9718 // Operands intentionally swapped. Mask is last operand to intrinsic, 9719 // but second operand for node/intruction. 9720 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 9721 Op.getOperand(2), Op.getOperand(1)); 9722 9723 // ptest and testp intrinsics. The intrinsic these come from are designed to 9724 // return an integer value, not just an instruction so lower it to the ptest 9725 // or testp pattern and a setcc for the result. 9726 case Intrinsic::x86_sse41_ptestz: 9727 case Intrinsic::x86_sse41_ptestc: 9728 case Intrinsic::x86_sse41_ptestnzc: 9729 case Intrinsic::x86_avx_ptestz_256: 9730 case Intrinsic::x86_avx_ptestc_256: 9731 case Intrinsic::x86_avx_ptestnzc_256: 9732 case Intrinsic::x86_avx_vtestz_ps: 9733 case Intrinsic::x86_avx_vtestc_ps: 9734 case Intrinsic::x86_avx_vtestnzc_ps: 9735 case Intrinsic::x86_avx_vtestz_pd: 9736 case Intrinsic::x86_avx_vtestc_pd: 9737 case Intrinsic::x86_avx_vtestnzc_pd: 9738 case Intrinsic::x86_avx_vtestz_ps_256: 9739 case Intrinsic::x86_avx_vtestc_ps_256: 9740 case Intrinsic::x86_avx_vtestnzc_ps_256: 9741 case Intrinsic::x86_avx_vtestz_pd_256: 9742 case Intrinsic::x86_avx_vtestc_pd_256: 9743 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9744 bool IsTestPacked = false; 9745 unsigned X86CC = 0; 9746 switch (IntNo) { 9747 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9748 case Intrinsic::x86_avx_vtestz_ps: 9749 case Intrinsic::x86_avx_vtestz_pd: 9750 case Intrinsic::x86_avx_vtestz_ps_256: 9751 case Intrinsic::x86_avx_vtestz_pd_256: 9752 IsTestPacked = true; // Fallthrough 9753 case Intrinsic::x86_sse41_ptestz: 9754 case Intrinsic::x86_avx_ptestz_256: 9755 // ZF = 1 9756 X86CC = X86::COND_E; 9757 break; 9758 case Intrinsic::x86_avx_vtestc_ps: 9759 case Intrinsic::x86_avx_vtestc_pd: 9760 case Intrinsic::x86_avx_vtestc_ps_256: 9761 case Intrinsic::x86_avx_vtestc_pd_256: 9762 IsTestPacked = true; // Fallthrough 9763 case Intrinsic::x86_sse41_ptestc: 9764 case Intrinsic::x86_avx_ptestc_256: 9765 // CF = 1 9766 X86CC = X86::COND_B; 9767 break; 9768 case Intrinsic::x86_avx_vtestnzc_ps: 9769 case Intrinsic::x86_avx_vtestnzc_pd: 9770 case Intrinsic::x86_avx_vtestnzc_ps_256: 9771 case Intrinsic::x86_avx_vtestnzc_pd_256: 9772 IsTestPacked = true; // Fallthrough 9773 case Intrinsic::x86_sse41_ptestnzc: 9774 case Intrinsic::x86_avx_ptestnzc_256: 9775 // ZF and CF = 0 9776 X86CC = X86::COND_A; 9777 break; 9778 } 9779 9780 SDValue LHS = Op.getOperand(1); 9781 SDValue RHS = Op.getOperand(2); 9782 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9783 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9784 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9785 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9786 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9787 } 9788 9789 // SSE/AVX shift intrinsics 9790 case Intrinsic::x86_sse2_psll_w: 9791 case Intrinsic::x86_sse2_psll_d: 9792 case Intrinsic::x86_sse2_psll_q: 9793 case Intrinsic::x86_avx2_psll_w: 9794 case Intrinsic::x86_avx2_psll_d: 9795 case Intrinsic::x86_avx2_psll_q: 9796 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9797 Op.getOperand(1), Op.getOperand(2)); 9798 case Intrinsic::x86_sse2_psrl_w: 9799 case Intrinsic::x86_sse2_psrl_d: 9800 case Intrinsic::x86_sse2_psrl_q: 9801 case Intrinsic::x86_avx2_psrl_w: 9802 case Intrinsic::x86_avx2_psrl_d: 9803 case Intrinsic::x86_avx2_psrl_q: 9804 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9805 Op.getOperand(1), Op.getOperand(2)); 9806 case Intrinsic::x86_sse2_psra_w: 9807 case Intrinsic::x86_sse2_psra_d: 9808 case Intrinsic::x86_avx2_psra_w: 9809 case Intrinsic::x86_avx2_psra_d: 9810 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9811 Op.getOperand(1), Op.getOperand(2)); 9812 case Intrinsic::x86_sse2_pslli_w: 9813 case Intrinsic::x86_sse2_pslli_d: 9814 case Intrinsic::x86_sse2_pslli_q: 9815 case Intrinsic::x86_avx2_pslli_w: 9816 case Intrinsic::x86_avx2_pslli_d: 9817 case Intrinsic::x86_avx2_pslli_q: 9818 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9819 Op.getOperand(1), Op.getOperand(2), DAG); 9820 case Intrinsic::x86_sse2_psrli_w: 9821 case Intrinsic::x86_sse2_psrli_d: 9822 case Intrinsic::x86_sse2_psrli_q: 9823 case Intrinsic::x86_avx2_psrli_w: 9824 case Intrinsic::x86_avx2_psrli_d: 9825 case Intrinsic::x86_avx2_psrli_q: 9826 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9827 Op.getOperand(1), Op.getOperand(2), DAG); 9828 case Intrinsic::x86_sse2_psrai_w: 9829 case Intrinsic::x86_sse2_psrai_d: 9830 case Intrinsic::x86_avx2_psrai_w: 9831 case Intrinsic::x86_avx2_psrai_d: 9832 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9833 Op.getOperand(1), Op.getOperand(2), DAG); 9834 // Fix vector shift instructions where the last operand is a non-immediate 9835 // i32 value. 9836 case Intrinsic::x86_mmx_pslli_w: 9837 case Intrinsic::x86_mmx_pslli_d: 9838 case Intrinsic::x86_mmx_pslli_q: 9839 case Intrinsic::x86_mmx_psrli_w: 9840 case Intrinsic::x86_mmx_psrli_d: 9841 case Intrinsic::x86_mmx_psrli_q: 9842 case Intrinsic::x86_mmx_psrai_w: 9843 case Intrinsic::x86_mmx_psrai_d: { 9844 SDValue ShAmt = Op.getOperand(2); 9845 if (isa<ConstantSDNode>(ShAmt)) 9846 return SDValue(); 9847 9848 unsigned NewIntNo = 0; 9849 switch (IntNo) { 9850 case Intrinsic::x86_mmx_pslli_w: 9851 NewIntNo = Intrinsic::x86_mmx_psll_w; 9852 break; 9853 case Intrinsic::x86_mmx_pslli_d: 9854 NewIntNo = Intrinsic::x86_mmx_psll_d; 9855 break; 9856 case Intrinsic::x86_mmx_pslli_q: 9857 NewIntNo = Intrinsic::x86_mmx_psll_q; 9858 break; 9859 case Intrinsic::x86_mmx_psrli_w: 9860 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9861 break; 9862 case Intrinsic::x86_mmx_psrli_d: 9863 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9864 break; 9865 case Intrinsic::x86_mmx_psrli_q: 9866 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9867 break; 9868 case Intrinsic::x86_mmx_psrai_w: 9869 NewIntNo = Intrinsic::x86_mmx_psra_w; 9870 break; 9871 case Intrinsic::x86_mmx_psrai_d: 9872 NewIntNo = Intrinsic::x86_mmx_psra_d; 9873 break; 9874 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9875 } 9876 9877 // The vector shift intrinsics with scalars uses 32b shift amounts but 9878 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9879 // to be zero. 9880 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9881 DAG.getConstant(0, MVT::i32)); 9882// FIXME this must be lowered to get rid of the invalid type. 9883 9884 EVT VT = Op.getValueType(); 9885 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9886 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9887 DAG.getConstant(NewIntNo, MVT::i32), 9888 Op.getOperand(1), ShAmt); 9889 } 9890 } 9891} 9892 9893SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9894 SelectionDAG &DAG) const { 9895 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9896 MFI->setReturnAddressIsTaken(true); 9897 9898 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9899 DebugLoc dl = Op.getDebugLoc(); 9900 9901 if (Depth > 0) { 9902 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9903 SDValue Offset = 9904 DAG.getConstant(TD->getPointerSize(), 9905 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9906 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9907 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9908 FrameAddr, Offset), 9909 MachinePointerInfo(), false, false, false, 0); 9910 } 9911 9912 // Just load the return address. 9913 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9914 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9915 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9916} 9917 9918SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9919 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9920 MFI->setFrameAddressIsTaken(true); 9921 9922 EVT VT = Op.getValueType(); 9923 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9924 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9925 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9926 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9927 while (Depth--) 9928 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9929 MachinePointerInfo(), 9930 false, false, false, 0); 9931 return FrameAddr; 9932} 9933 9934SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9935 SelectionDAG &DAG) const { 9936 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9937} 9938 9939SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9940 MachineFunction &MF = DAG.getMachineFunction(); 9941 SDValue Chain = Op.getOperand(0); 9942 SDValue Offset = Op.getOperand(1); 9943 SDValue Handler = Op.getOperand(2); 9944 DebugLoc dl = Op.getDebugLoc(); 9945 9946 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9947 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9948 getPointerTy()); 9949 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9950 9951 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9952 DAG.getIntPtrConstant(TD->getPointerSize())); 9953 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9954 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9955 false, false, 0); 9956 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9957 MF.getRegInfo().addLiveOut(StoreAddrReg); 9958 9959 return DAG.getNode(X86ISD::EH_RETURN, dl, 9960 MVT::Other, 9961 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9962} 9963 9964SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9965 SelectionDAG &DAG) const { 9966 return Op.getOperand(0); 9967} 9968 9969SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9970 SelectionDAG &DAG) const { 9971 SDValue Root = Op.getOperand(0); 9972 SDValue Trmp = Op.getOperand(1); // trampoline 9973 SDValue FPtr = Op.getOperand(2); // nested function 9974 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9975 DebugLoc dl = Op.getDebugLoc(); 9976 9977 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9978 9979 if (Subtarget->is64Bit()) { 9980 SDValue OutChains[6]; 9981 9982 // Large code-model. 9983 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9984 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9985 9986 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9987 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9988 9989 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9990 9991 // Load the pointer to the nested function into R11. 9992 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9993 SDValue Addr = Trmp; 9994 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9995 Addr, MachinePointerInfo(TrmpAddr), 9996 false, false, 0); 9997 9998 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9999 DAG.getConstant(2, MVT::i64)); 10000 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 10001 MachinePointerInfo(TrmpAddr, 2), 10002 false, false, 2); 10003 10004 // Load the 'nest' parameter value into R10. 10005 // R10 is specified in X86CallingConv.td 10006 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 10007 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10008 DAG.getConstant(10, MVT::i64)); 10009 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10010 Addr, MachinePointerInfo(TrmpAddr, 10), 10011 false, false, 0); 10012 10013 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10014 DAG.getConstant(12, MVT::i64)); 10015 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 10016 MachinePointerInfo(TrmpAddr, 12), 10017 false, false, 2); 10018 10019 // Jump to the nested function. 10020 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 10021 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10022 DAG.getConstant(20, MVT::i64)); 10023 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 10024 Addr, MachinePointerInfo(TrmpAddr, 20), 10025 false, false, 0); 10026 10027 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 10028 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 10029 DAG.getConstant(22, MVT::i64)); 10030 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 10031 MachinePointerInfo(TrmpAddr, 22), 10032 false, false, 0); 10033 10034 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 10035 } else { 10036 const Function *Func = 10037 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 10038 CallingConv::ID CC = Func->getCallingConv(); 10039 unsigned NestReg; 10040 10041 switch (CC) { 10042 default: 10043 llvm_unreachable("Unsupported calling convention"); 10044 case CallingConv::C: 10045 case CallingConv::X86_StdCall: { 10046 // Pass 'nest' parameter in ECX. 10047 // Must be kept in sync with X86CallingConv.td 10048 NestReg = X86::ECX; 10049 10050 // Check that ECX wasn't needed by an 'inreg' parameter. 10051 FunctionType *FTy = Func->getFunctionType(); 10052 const AttrListPtr &Attrs = Func->getAttributes(); 10053 10054 if (!Attrs.isEmpty() && !Func->isVarArg()) { 10055 unsigned InRegCount = 0; 10056 unsigned Idx = 1; 10057 10058 for (FunctionType::param_iterator I = FTy->param_begin(), 10059 E = FTy->param_end(); I != E; ++I, ++Idx) 10060 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 10061 // FIXME: should only count parameters that are lowered to integers. 10062 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 10063 10064 if (InRegCount > 2) { 10065 report_fatal_error("Nest register in use - reduce number of inreg" 10066 " parameters!"); 10067 } 10068 } 10069 break; 10070 } 10071 case CallingConv::X86_FastCall: 10072 case CallingConv::X86_ThisCall: 10073 case CallingConv::Fast: 10074 // Pass 'nest' parameter in EAX. 10075 // Must be kept in sync with X86CallingConv.td 10076 NestReg = X86::EAX; 10077 break; 10078 } 10079 10080 SDValue OutChains[4]; 10081 SDValue Addr, Disp; 10082 10083 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10084 DAG.getConstant(10, MVT::i32)); 10085 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 10086 10087 // This is storing the opcode for MOV32ri. 10088 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 10089 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 10090 OutChains[0] = DAG.getStore(Root, dl, 10091 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 10092 Trmp, MachinePointerInfo(TrmpAddr), 10093 false, false, 0); 10094 10095 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10096 DAG.getConstant(1, MVT::i32)); 10097 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 10098 MachinePointerInfo(TrmpAddr, 1), 10099 false, false, 1); 10100 10101 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 10102 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10103 DAG.getConstant(5, MVT::i32)); 10104 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 10105 MachinePointerInfo(TrmpAddr, 5), 10106 false, false, 1); 10107 10108 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10109 DAG.getConstant(6, MVT::i32)); 10110 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 10111 MachinePointerInfo(TrmpAddr, 6), 10112 false, false, 1); 10113 10114 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 10115 } 10116} 10117 10118SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10119 SelectionDAG &DAG) const { 10120 /* 10121 The rounding mode is in bits 11:10 of FPSR, and has the following 10122 settings: 10123 00 Round to nearest 10124 01 Round to -inf 10125 10 Round to +inf 10126 11 Round to 0 10127 10128 FLT_ROUNDS, on the other hand, expects the following: 10129 -1 Undefined 10130 0 Round to 0 10131 1 Round to nearest 10132 2 Round to +inf 10133 3 Round to -inf 10134 10135 To perform the conversion, we do: 10136 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10137 */ 10138 10139 MachineFunction &MF = DAG.getMachineFunction(); 10140 const TargetMachine &TM = MF.getTarget(); 10141 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10142 unsigned StackAlignment = TFI.getStackAlignment(); 10143 EVT VT = Op.getValueType(); 10144 DebugLoc DL = Op.getDebugLoc(); 10145 10146 // Save FP Control Word to stack slot 10147 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10148 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10149 10150 10151 MachineMemOperand *MMO = 10152 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10153 MachineMemOperand::MOStore, 2, 2); 10154 10155 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10156 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10157 DAG.getVTList(MVT::Other), 10158 Ops, 2, MVT::i16, MMO); 10159 10160 // Load FP Control Word from stack slot 10161 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10162 MachinePointerInfo(), false, false, false, 0); 10163 10164 // Transform as necessary 10165 SDValue CWD1 = 10166 DAG.getNode(ISD::SRL, DL, MVT::i16, 10167 DAG.getNode(ISD::AND, DL, MVT::i16, 10168 CWD, DAG.getConstant(0x800, MVT::i16)), 10169 DAG.getConstant(11, MVT::i8)); 10170 SDValue CWD2 = 10171 DAG.getNode(ISD::SRL, DL, MVT::i16, 10172 DAG.getNode(ISD::AND, DL, MVT::i16, 10173 CWD, DAG.getConstant(0x400, MVT::i16)), 10174 DAG.getConstant(9, MVT::i8)); 10175 10176 SDValue RetVal = 10177 DAG.getNode(ISD::AND, DL, MVT::i16, 10178 DAG.getNode(ISD::ADD, DL, MVT::i16, 10179 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10180 DAG.getConstant(1, MVT::i16)), 10181 DAG.getConstant(3, MVT::i16)); 10182 10183 10184 return DAG.getNode((VT.getSizeInBits() < 16 ? 10185 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10186} 10187 10188SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10189 EVT VT = Op.getValueType(); 10190 EVT OpVT = VT; 10191 unsigned NumBits = VT.getSizeInBits(); 10192 DebugLoc dl = Op.getDebugLoc(); 10193 10194 Op = Op.getOperand(0); 10195 if (VT == MVT::i8) { 10196 // Zero extend to i32 since there is not an i8 bsr. 10197 OpVT = MVT::i32; 10198 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10199 } 10200 10201 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10202 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10203 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10204 10205 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10206 SDValue Ops[] = { 10207 Op, 10208 DAG.getConstant(NumBits+NumBits-1, OpVT), 10209 DAG.getConstant(X86::COND_E, MVT::i8), 10210 Op.getValue(1) 10211 }; 10212 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10213 10214 // Finally xor with NumBits-1. 10215 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10216 10217 if (VT == MVT::i8) 10218 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10219 return Op; 10220} 10221 10222SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10223 SelectionDAG &DAG) const { 10224 EVT VT = Op.getValueType(); 10225 EVT OpVT = VT; 10226 unsigned NumBits = VT.getSizeInBits(); 10227 DebugLoc dl = Op.getDebugLoc(); 10228 10229 Op = Op.getOperand(0); 10230 if (VT == MVT::i8) { 10231 // Zero extend to i32 since there is not an i8 bsr. 10232 OpVT = MVT::i32; 10233 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10234 } 10235 10236 // Issue a bsr (scan bits in reverse). 10237 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10238 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10239 10240 // And xor with NumBits-1. 10241 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10242 10243 if (VT == MVT::i8) 10244 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10245 return Op; 10246} 10247 10248SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10249 EVT VT = Op.getValueType(); 10250 unsigned NumBits = VT.getSizeInBits(); 10251 DebugLoc dl = Op.getDebugLoc(); 10252 Op = Op.getOperand(0); 10253 10254 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10255 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10256 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10257 10258 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10259 SDValue Ops[] = { 10260 Op, 10261 DAG.getConstant(NumBits, VT), 10262 DAG.getConstant(X86::COND_E, MVT::i8), 10263 Op.getValue(1) 10264 }; 10265 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10266} 10267 10268// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10269// ones, and then concatenate the result back. 10270static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10271 EVT VT = Op.getValueType(); 10272 10273 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10274 "Unsupported value type for operation"); 10275 10276 unsigned NumElems = VT.getVectorNumElements(); 10277 DebugLoc dl = Op.getDebugLoc(); 10278 10279 // Extract the LHS vectors 10280 SDValue LHS = Op.getOperand(0); 10281 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10282 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10283 10284 // Extract the RHS vectors 10285 SDValue RHS = Op.getOperand(1); 10286 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 10287 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 10288 10289 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10290 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10291 10292 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10293 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10294 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10295} 10296 10297SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10298 assert(Op.getValueType().getSizeInBits() == 256 && 10299 Op.getValueType().isInteger() && 10300 "Only handle AVX 256-bit vector integer operation"); 10301 return Lower256IntArith(Op, DAG); 10302} 10303 10304SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10305 assert(Op.getValueType().getSizeInBits() == 256 && 10306 Op.getValueType().isInteger() && 10307 "Only handle AVX 256-bit vector integer operation"); 10308 return Lower256IntArith(Op, DAG); 10309} 10310 10311SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10312 EVT VT = Op.getValueType(); 10313 10314 // Decompose 256-bit ops into smaller 128-bit ops. 10315 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10316 return Lower256IntArith(Op, DAG); 10317 10318 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10319 "Only know how to lower V2I64/V4I64 multiply"); 10320 10321 DebugLoc dl = Op.getDebugLoc(); 10322 10323 // Ahi = psrlqi(a, 32); 10324 // Bhi = psrlqi(b, 32); 10325 // 10326 // AloBlo = pmuludq(a, b); 10327 // AloBhi = pmuludq(a, Bhi); 10328 // AhiBlo = pmuludq(Ahi, b); 10329 10330 // AloBhi = psllqi(AloBhi, 32); 10331 // AhiBlo = psllqi(AhiBlo, 32); 10332 // return AloBlo + AloBhi + AhiBlo; 10333 10334 SDValue A = Op.getOperand(0); 10335 SDValue B = Op.getOperand(1); 10336 10337 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10338 10339 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10340 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10341 10342 // Bit cast to 32-bit vectors for MULUDQ 10343 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10344 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10345 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10346 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10347 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10348 10349 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10350 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10351 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10352 10353 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10354 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10355 10356 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10357 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10358} 10359 10360SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10361 10362 EVT VT = Op.getValueType(); 10363 DebugLoc dl = Op.getDebugLoc(); 10364 SDValue R = Op.getOperand(0); 10365 SDValue Amt = Op.getOperand(1); 10366 LLVMContext *Context = DAG.getContext(); 10367 10368 if (!Subtarget->hasSSE2()) 10369 return SDValue(); 10370 10371 // Optimize shl/srl/sra with constant shift amount. 10372 if (isSplatVector(Amt.getNode())) { 10373 SDValue SclrAmt = Amt->getOperand(0); 10374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10375 uint64_t ShiftAmt = C->getZExtValue(); 10376 10377 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10378 (Subtarget->hasAVX2() && 10379 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10380 if (Op.getOpcode() == ISD::SHL) 10381 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10382 DAG.getConstant(ShiftAmt, MVT::i32)); 10383 if (Op.getOpcode() == ISD::SRL) 10384 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10385 DAG.getConstant(ShiftAmt, MVT::i32)); 10386 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10387 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10388 DAG.getConstant(ShiftAmt, MVT::i32)); 10389 } 10390 10391 if (VT == MVT::v16i8) { 10392 if (Op.getOpcode() == ISD::SHL) { 10393 // Make a large shift. 10394 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10395 DAG.getConstant(ShiftAmt, MVT::i32)); 10396 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10397 // Zero out the rightmost bits. 10398 SmallVector<SDValue, 16> V(16, 10399 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10400 MVT::i8)); 10401 return DAG.getNode(ISD::AND, dl, VT, SHL, 10402 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10403 } 10404 if (Op.getOpcode() == ISD::SRL) { 10405 // Make a large shift. 10406 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10407 DAG.getConstant(ShiftAmt, MVT::i32)); 10408 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10409 // Zero out the leftmost bits. 10410 SmallVector<SDValue, 16> V(16, 10411 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10412 MVT::i8)); 10413 return DAG.getNode(ISD::AND, dl, VT, SRL, 10414 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10415 } 10416 if (Op.getOpcode() == ISD::SRA) { 10417 if (ShiftAmt == 7) { 10418 // R s>> 7 === R s< 0 10419 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10420 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10421 } 10422 10423 // R s>> a === ((R u>> a) ^ m) - m 10424 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10425 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10426 MVT::i8)); 10427 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10428 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10429 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10430 return Res; 10431 } 10432 llvm_unreachable("Unknown shift opcode."); 10433 } 10434 10435 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10436 if (Op.getOpcode() == ISD::SHL) { 10437 // Make a large shift. 10438 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10439 DAG.getConstant(ShiftAmt, MVT::i32)); 10440 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10441 // Zero out the rightmost bits. 10442 SmallVector<SDValue, 32> V(32, 10443 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10444 MVT::i8)); 10445 return DAG.getNode(ISD::AND, dl, VT, SHL, 10446 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10447 } 10448 if (Op.getOpcode() == ISD::SRL) { 10449 // Make a large shift. 10450 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10451 DAG.getConstant(ShiftAmt, MVT::i32)); 10452 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10453 // Zero out the leftmost bits. 10454 SmallVector<SDValue, 32> V(32, 10455 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10456 MVT::i8)); 10457 return DAG.getNode(ISD::AND, dl, VT, SRL, 10458 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10459 } 10460 if (Op.getOpcode() == ISD::SRA) { 10461 if (ShiftAmt == 7) { 10462 // R s>> 7 === R s< 0 10463 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10464 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10465 } 10466 10467 // R s>> a === ((R u>> a) ^ m) - m 10468 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10469 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10470 MVT::i8)); 10471 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10472 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10473 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10474 return Res; 10475 } 10476 llvm_unreachable("Unknown shift opcode."); 10477 } 10478 } 10479 } 10480 10481 // Lower SHL with variable shift amount. 10482 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10483 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10484 DAG.getConstant(23, MVT::i32)); 10485 10486 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10487 Constant *C = ConstantDataVector::get(*Context, CV); 10488 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10489 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10490 MachinePointerInfo::getConstantPool(), 10491 false, false, false, 16); 10492 10493 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10494 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10495 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10496 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10497 } 10498 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10499 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10500 10501 // a = a << 5; 10502 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10503 DAG.getConstant(5, MVT::i32)); 10504 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10505 10506 // Turn 'a' into a mask suitable for VSELECT 10507 SDValue VSelM = DAG.getConstant(0x80, VT); 10508 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10509 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10510 10511 SDValue CM1 = DAG.getConstant(0x0f, VT); 10512 SDValue CM2 = DAG.getConstant(0x3f, VT); 10513 10514 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10515 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10516 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10517 DAG.getConstant(4, MVT::i32), DAG); 10518 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10519 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10520 10521 // a += a 10522 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10523 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10524 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10525 10526 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10527 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10528 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10529 DAG.getConstant(2, MVT::i32), DAG); 10530 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10531 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10532 10533 // a += a 10534 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10535 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10536 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10537 10538 // return VSELECT(r, r+r, a); 10539 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10540 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10541 return R; 10542 } 10543 10544 // Decompose 256-bit shifts into smaller 128-bit shifts. 10545 if (VT.getSizeInBits() == 256) { 10546 unsigned NumElems = VT.getVectorNumElements(); 10547 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10548 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10549 10550 // Extract the two vectors 10551 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 10552 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 10553 10554 // Recreate the shift amount vectors 10555 SDValue Amt1, Amt2; 10556 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10557 // Constant shift amount 10558 SmallVector<SDValue, 4> Amt1Csts; 10559 SmallVector<SDValue, 4> Amt2Csts; 10560 for (unsigned i = 0; i != NumElems/2; ++i) 10561 Amt1Csts.push_back(Amt->getOperand(i)); 10562 for (unsigned i = NumElems/2; i != NumElems; ++i) 10563 Amt2Csts.push_back(Amt->getOperand(i)); 10564 10565 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10566 &Amt1Csts[0], NumElems/2); 10567 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10568 &Amt2Csts[0], NumElems/2); 10569 } else { 10570 // Variable shift amount 10571 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 10572 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 10573 } 10574 10575 // Issue new vector shifts for the smaller types 10576 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10577 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10578 10579 // Concatenate the result back 10580 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10581 } 10582 10583 return SDValue(); 10584} 10585 10586SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10587 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10588 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10589 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10590 // has only one use. 10591 SDNode *N = Op.getNode(); 10592 SDValue LHS = N->getOperand(0); 10593 SDValue RHS = N->getOperand(1); 10594 unsigned BaseOp = 0; 10595 unsigned Cond = 0; 10596 DebugLoc DL = Op.getDebugLoc(); 10597 switch (Op.getOpcode()) { 10598 default: llvm_unreachable("Unknown ovf instruction!"); 10599 case ISD::SADDO: 10600 // A subtract of one will be selected as a INC. Note that INC doesn't 10601 // set CF, so we can't do this for UADDO. 10602 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10603 if (C->isOne()) { 10604 BaseOp = X86ISD::INC; 10605 Cond = X86::COND_O; 10606 break; 10607 } 10608 BaseOp = X86ISD::ADD; 10609 Cond = X86::COND_O; 10610 break; 10611 case ISD::UADDO: 10612 BaseOp = X86ISD::ADD; 10613 Cond = X86::COND_B; 10614 break; 10615 case ISD::SSUBO: 10616 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10617 // set CF, so we can't do this for USUBO. 10618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10619 if (C->isOne()) { 10620 BaseOp = X86ISD::DEC; 10621 Cond = X86::COND_O; 10622 break; 10623 } 10624 BaseOp = X86ISD::SUB; 10625 Cond = X86::COND_O; 10626 break; 10627 case ISD::USUBO: 10628 BaseOp = X86ISD::SUB; 10629 Cond = X86::COND_B; 10630 break; 10631 case ISD::SMULO: 10632 BaseOp = X86ISD::SMUL; 10633 Cond = X86::COND_O; 10634 break; 10635 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10636 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10637 MVT::i32); 10638 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10639 10640 SDValue SetCC = 10641 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10642 DAG.getConstant(X86::COND_O, MVT::i32), 10643 SDValue(Sum.getNode(), 2)); 10644 10645 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10646 } 10647 } 10648 10649 // Also sets EFLAGS. 10650 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10651 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10652 10653 SDValue SetCC = 10654 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10655 DAG.getConstant(Cond, MVT::i32), 10656 SDValue(Sum.getNode(), 1)); 10657 10658 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10659} 10660 10661SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10662 SelectionDAG &DAG) const { 10663 DebugLoc dl = Op.getDebugLoc(); 10664 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10665 EVT VT = Op.getValueType(); 10666 10667 if (!Subtarget->hasSSE2() || !VT.isVector()) 10668 return SDValue(); 10669 10670 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10671 ExtraVT.getScalarType().getSizeInBits(); 10672 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10673 10674 switch (VT.getSimpleVT().SimpleTy) { 10675 default: return SDValue(); 10676 case MVT::v8i32: 10677 case MVT::v16i16: 10678 if (!Subtarget->hasAVX()) 10679 return SDValue(); 10680 if (!Subtarget->hasAVX2()) { 10681 // needs to be split 10682 unsigned NumElems = VT.getVectorNumElements(); 10683 10684 // Extract the LHS vectors 10685 SDValue LHS = Op.getOperand(0); 10686 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10687 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10688 10689 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10690 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10691 10692 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10693 unsigned ExtraNumElems = ExtraVT.getVectorNumElements(); 10694 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10695 ExtraNumElems/2); 10696 SDValue Extra = DAG.getValueType(ExtraVT); 10697 10698 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10699 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10700 10701 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10702 } 10703 // fall through 10704 case MVT::v4i32: 10705 case MVT::v8i16: { 10706 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10707 Op.getOperand(0), ShAmt, DAG); 10708 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10709 } 10710 } 10711} 10712 10713 10714SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10715 DebugLoc dl = Op.getDebugLoc(); 10716 10717 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10718 // There isn't any reason to disable it if the target processor supports it. 10719 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10720 SDValue Chain = Op.getOperand(0); 10721 SDValue Zero = DAG.getConstant(0, MVT::i32); 10722 SDValue Ops[] = { 10723 DAG.getRegister(X86::ESP, MVT::i32), // Base 10724 DAG.getTargetConstant(1, MVT::i8), // Scale 10725 DAG.getRegister(0, MVT::i32), // Index 10726 DAG.getTargetConstant(0, MVT::i32), // Disp 10727 DAG.getRegister(0, MVT::i32), // Segment. 10728 Zero, 10729 Chain 10730 }; 10731 SDNode *Res = 10732 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10733 array_lengthof(Ops)); 10734 return SDValue(Res, 0); 10735 } 10736 10737 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10738 if (!isDev) 10739 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10740 10741 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10742 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10743 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10744 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10745 10746 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10747 if (!Op1 && !Op2 && !Op3 && Op4) 10748 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10749 10750 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10751 if (Op1 && !Op2 && !Op3 && !Op4) 10752 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10753 10754 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10755 // (MFENCE)>; 10756 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10757} 10758 10759SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10760 SelectionDAG &DAG) const { 10761 DebugLoc dl = Op.getDebugLoc(); 10762 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10763 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10764 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10765 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10766 10767 // The only fence that needs an instruction is a sequentially-consistent 10768 // cross-thread fence. 10769 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10770 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10771 // no-sse2). There isn't any reason to disable it if the target processor 10772 // supports it. 10773 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10774 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10775 10776 SDValue Chain = Op.getOperand(0); 10777 SDValue Zero = DAG.getConstant(0, MVT::i32); 10778 SDValue Ops[] = { 10779 DAG.getRegister(X86::ESP, MVT::i32), // Base 10780 DAG.getTargetConstant(1, MVT::i8), // Scale 10781 DAG.getRegister(0, MVT::i32), // Index 10782 DAG.getTargetConstant(0, MVT::i32), // Disp 10783 DAG.getRegister(0, MVT::i32), // Segment. 10784 Zero, 10785 Chain 10786 }; 10787 SDNode *Res = 10788 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10789 array_lengthof(Ops)); 10790 return SDValue(Res, 0); 10791 } 10792 10793 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10794 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10795} 10796 10797 10798SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10799 EVT T = Op.getValueType(); 10800 DebugLoc DL = Op.getDebugLoc(); 10801 unsigned Reg = 0; 10802 unsigned size = 0; 10803 switch(T.getSimpleVT().SimpleTy) { 10804 default: llvm_unreachable("Invalid value type!"); 10805 case MVT::i8: Reg = X86::AL; size = 1; break; 10806 case MVT::i16: Reg = X86::AX; size = 2; break; 10807 case MVT::i32: Reg = X86::EAX; size = 4; break; 10808 case MVT::i64: 10809 assert(Subtarget->is64Bit() && "Node not type legal!"); 10810 Reg = X86::RAX; size = 8; 10811 break; 10812 } 10813 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10814 Op.getOperand(2), SDValue()); 10815 SDValue Ops[] = { cpIn.getValue(0), 10816 Op.getOperand(1), 10817 Op.getOperand(3), 10818 DAG.getTargetConstant(size, MVT::i8), 10819 cpIn.getValue(1) }; 10820 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10821 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10822 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10823 Ops, 5, T, MMO); 10824 SDValue cpOut = 10825 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10826 return cpOut; 10827} 10828 10829SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10830 SelectionDAG &DAG) const { 10831 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10832 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10833 SDValue TheChain = Op.getOperand(0); 10834 DebugLoc dl = Op.getDebugLoc(); 10835 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10836 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10837 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10838 rax.getValue(2)); 10839 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10840 DAG.getConstant(32, MVT::i8)); 10841 SDValue Ops[] = { 10842 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10843 rdx.getValue(1) 10844 }; 10845 return DAG.getMergeValues(Ops, 2, dl); 10846} 10847 10848SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10849 SelectionDAG &DAG) const { 10850 EVT SrcVT = Op.getOperand(0).getValueType(); 10851 EVT DstVT = Op.getValueType(); 10852 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10853 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10854 assert((DstVT == MVT::i64 || 10855 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10856 "Unexpected custom BITCAST"); 10857 // i64 <=> MMX conversions are Legal. 10858 if (SrcVT==MVT::i64 && DstVT.isVector()) 10859 return Op; 10860 if (DstVT==MVT::i64 && SrcVT.isVector()) 10861 return Op; 10862 // MMX <=> MMX conversions are Legal. 10863 if (SrcVT.isVector() && DstVT.isVector()) 10864 return Op; 10865 // All other conversions need to be expanded. 10866 return SDValue(); 10867} 10868 10869SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10870 SDNode *Node = Op.getNode(); 10871 DebugLoc dl = Node->getDebugLoc(); 10872 EVT T = Node->getValueType(0); 10873 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10874 DAG.getConstant(0, T), Node->getOperand(2)); 10875 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10876 cast<AtomicSDNode>(Node)->getMemoryVT(), 10877 Node->getOperand(0), 10878 Node->getOperand(1), negOp, 10879 cast<AtomicSDNode>(Node)->getSrcValue(), 10880 cast<AtomicSDNode>(Node)->getAlignment(), 10881 cast<AtomicSDNode>(Node)->getOrdering(), 10882 cast<AtomicSDNode>(Node)->getSynchScope()); 10883} 10884 10885static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10886 SDNode *Node = Op.getNode(); 10887 DebugLoc dl = Node->getDebugLoc(); 10888 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10889 10890 // Convert seq_cst store -> xchg 10891 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10892 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10893 // (The only way to get a 16-byte store is cmpxchg16b) 10894 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10895 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10896 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10897 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10898 cast<AtomicSDNode>(Node)->getMemoryVT(), 10899 Node->getOperand(0), 10900 Node->getOperand(1), Node->getOperand(2), 10901 cast<AtomicSDNode>(Node)->getMemOperand(), 10902 cast<AtomicSDNode>(Node)->getOrdering(), 10903 cast<AtomicSDNode>(Node)->getSynchScope()); 10904 return Swap.getValue(1); 10905 } 10906 // Other atomic stores have a simple pattern. 10907 return Op; 10908} 10909 10910static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10911 EVT VT = Op.getNode()->getValueType(0); 10912 10913 // Let legalize expand this if it isn't a legal type yet. 10914 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10915 return SDValue(); 10916 10917 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10918 10919 unsigned Opc; 10920 bool ExtraOp = false; 10921 switch (Op.getOpcode()) { 10922 default: llvm_unreachable("Invalid code"); 10923 case ISD::ADDC: Opc = X86ISD::ADD; break; 10924 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10925 case ISD::SUBC: Opc = X86ISD::SUB; break; 10926 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10927 } 10928 10929 if (!ExtraOp) 10930 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10931 Op.getOperand(1)); 10932 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10933 Op.getOperand(1), Op.getOperand(2)); 10934} 10935 10936/// LowerOperation - Provide custom lowering hooks for some operations. 10937/// 10938SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10939 switch (Op.getOpcode()) { 10940 default: llvm_unreachable("Should not custom lower this!"); 10941 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10942 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10943 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10944 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10945 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10946 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10947 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10948 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10949 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10950 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10951 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10952 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10953 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10954 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10955 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10956 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10957 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10958 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10959 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10960 case ISD::SHL_PARTS: 10961 case ISD::SRA_PARTS: 10962 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10963 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10964 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10965 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10966 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10967 case ISD::FABS: return LowerFABS(Op, DAG); 10968 case ISD::FNEG: return LowerFNEG(Op, DAG); 10969 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10970 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10971 case ISD::SETCC: return LowerSETCC(Op, DAG); 10972 case ISD::SELECT: return LowerSELECT(Op, DAG); 10973 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10974 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10975 case ISD::VASTART: return LowerVASTART(Op, DAG); 10976 case ISD::VAARG: return LowerVAARG(Op, DAG); 10977 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10978 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10979 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10980 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10981 case ISD::FRAME_TO_ARGS_OFFSET: 10982 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10983 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10984 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10985 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10986 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10987 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10988 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10989 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10990 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10991 case ISD::MUL: return LowerMUL(Op, DAG); 10992 case ISD::SRA: 10993 case ISD::SRL: 10994 case ISD::SHL: return LowerShift(Op, DAG); 10995 case ISD::SADDO: 10996 case ISD::UADDO: 10997 case ISD::SSUBO: 10998 case ISD::USUBO: 10999 case ISD::SMULO: 11000 case ISD::UMULO: return LowerXALUO(Op, DAG); 11001 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 11002 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 11003 case ISD::ADDC: 11004 case ISD::ADDE: 11005 case ISD::SUBC: 11006 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 11007 case ISD::ADD: return LowerADD(Op, DAG); 11008 case ISD::SUB: return LowerSUB(Op, DAG); 11009 } 11010} 11011 11012static void ReplaceATOMIC_LOAD(SDNode *Node, 11013 SmallVectorImpl<SDValue> &Results, 11014 SelectionDAG &DAG) { 11015 DebugLoc dl = Node->getDebugLoc(); 11016 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 11017 11018 // Convert wide load -> cmpxchg8b/cmpxchg16b 11019 // FIXME: On 32-bit, load -> fild or movq would be more efficient 11020 // (The only way to get a 16-byte load is cmpxchg16b) 11021 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 11022 SDValue Zero = DAG.getConstant(0, VT); 11023 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 11024 Node->getOperand(0), 11025 Node->getOperand(1), Zero, Zero, 11026 cast<AtomicSDNode>(Node)->getMemOperand(), 11027 cast<AtomicSDNode>(Node)->getOrdering(), 11028 cast<AtomicSDNode>(Node)->getSynchScope()); 11029 Results.push_back(Swap.getValue(0)); 11030 Results.push_back(Swap.getValue(1)); 11031} 11032 11033void X86TargetLowering:: 11034ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 11035 SelectionDAG &DAG, unsigned NewOp) const { 11036 DebugLoc dl = Node->getDebugLoc(); 11037 assert (Node->getValueType(0) == MVT::i64 && 11038 "Only know how to expand i64 atomics"); 11039 11040 SDValue Chain = Node->getOperand(0); 11041 SDValue In1 = Node->getOperand(1); 11042 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11043 Node->getOperand(2), DAG.getIntPtrConstant(0)); 11044 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 11045 Node->getOperand(2), DAG.getIntPtrConstant(1)); 11046 SDValue Ops[] = { Chain, In1, In2L, In2H }; 11047 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 11048 SDValue Result = 11049 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 11050 cast<MemSDNode>(Node)->getMemOperand()); 11051 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 11052 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 11053 Results.push_back(Result.getValue(2)); 11054} 11055 11056/// ReplaceNodeResults - Replace a node with an illegal result type 11057/// with a new node built out of custom code. 11058void X86TargetLowering::ReplaceNodeResults(SDNode *N, 11059 SmallVectorImpl<SDValue>&Results, 11060 SelectionDAG &DAG) const { 11061 DebugLoc dl = N->getDebugLoc(); 11062 switch (N->getOpcode()) { 11063 default: 11064 llvm_unreachable("Do not know how to custom type legalize this operation!"); 11065 case ISD::SIGN_EXTEND_INREG: 11066 case ISD::ADDC: 11067 case ISD::ADDE: 11068 case ISD::SUBC: 11069 case ISD::SUBE: 11070 // We don't want to expand or promote these. 11071 return; 11072 case ISD::FP_TO_SINT: 11073 case ISD::FP_TO_UINT: { 11074 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 11075 11076 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 11077 return; 11078 11079 std::pair<SDValue,SDValue> Vals = 11080 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 11081 SDValue FIST = Vals.first, StackSlot = Vals.second; 11082 if (FIST.getNode() != 0) { 11083 EVT VT = N->getValueType(0); 11084 // Return a load from the stack slot. 11085 if (StackSlot.getNode() != 0) 11086 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 11087 MachinePointerInfo(), 11088 false, false, false, 0)); 11089 else 11090 Results.push_back(FIST); 11091 } 11092 return; 11093 } 11094 case ISD::READCYCLECOUNTER: { 11095 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11096 SDValue TheChain = N->getOperand(0); 11097 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11098 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 11099 rd.getValue(1)); 11100 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 11101 eax.getValue(2)); 11102 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 11103 SDValue Ops[] = { eax, edx }; 11104 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 11105 Results.push_back(edx.getValue(1)); 11106 return; 11107 } 11108 case ISD::ATOMIC_CMP_SWAP: { 11109 EVT T = N->getValueType(0); 11110 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 11111 bool Regs64bit = T == MVT::i128; 11112 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11113 SDValue cpInL, cpInH; 11114 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11115 DAG.getConstant(0, HalfT)); 11116 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11117 DAG.getConstant(1, HalfT)); 11118 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11119 Regs64bit ? X86::RAX : X86::EAX, 11120 cpInL, SDValue()); 11121 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11122 Regs64bit ? X86::RDX : X86::EDX, 11123 cpInH, cpInL.getValue(1)); 11124 SDValue swapInL, swapInH; 11125 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11126 DAG.getConstant(0, HalfT)); 11127 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11128 DAG.getConstant(1, HalfT)); 11129 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11130 Regs64bit ? X86::RBX : X86::EBX, 11131 swapInL, cpInH.getValue(1)); 11132 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11133 Regs64bit ? X86::RCX : X86::ECX, 11134 swapInH, swapInL.getValue(1)); 11135 SDValue Ops[] = { swapInH.getValue(0), 11136 N->getOperand(1), 11137 swapInH.getValue(1) }; 11138 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11139 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11140 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11141 X86ISD::LCMPXCHG8_DAG; 11142 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11143 Ops, 3, T, MMO); 11144 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11145 Regs64bit ? X86::RAX : X86::EAX, 11146 HalfT, Result.getValue(1)); 11147 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11148 Regs64bit ? X86::RDX : X86::EDX, 11149 HalfT, cpOutL.getValue(2)); 11150 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11151 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11152 Results.push_back(cpOutH.getValue(1)); 11153 return; 11154 } 11155 case ISD::ATOMIC_LOAD_ADD: 11156 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 11157 return; 11158 case ISD::ATOMIC_LOAD_AND: 11159 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 11160 return; 11161 case ISD::ATOMIC_LOAD_NAND: 11162 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 11163 return; 11164 case ISD::ATOMIC_LOAD_OR: 11165 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 11166 return; 11167 case ISD::ATOMIC_LOAD_SUB: 11168 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 11169 return; 11170 case ISD::ATOMIC_LOAD_XOR: 11171 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11172 return; 11173 case ISD::ATOMIC_SWAP: 11174 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11175 return; 11176 case ISD::ATOMIC_LOAD: 11177 ReplaceATOMIC_LOAD(N, Results, DAG); 11178 } 11179} 11180 11181const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11182 switch (Opcode) { 11183 default: return NULL; 11184 case X86ISD::BSF: return "X86ISD::BSF"; 11185 case X86ISD::BSR: return "X86ISD::BSR"; 11186 case X86ISD::SHLD: return "X86ISD::SHLD"; 11187 case X86ISD::SHRD: return "X86ISD::SHRD"; 11188 case X86ISD::FAND: return "X86ISD::FAND"; 11189 case X86ISD::FOR: return "X86ISD::FOR"; 11190 case X86ISD::FXOR: return "X86ISD::FXOR"; 11191 case X86ISD::FSRL: return "X86ISD::FSRL"; 11192 case X86ISD::FILD: return "X86ISD::FILD"; 11193 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11194 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11195 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11196 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11197 case X86ISD::FLD: return "X86ISD::FLD"; 11198 case X86ISD::FST: return "X86ISD::FST"; 11199 case X86ISD::CALL: return "X86ISD::CALL"; 11200 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11201 case X86ISD::BT: return "X86ISD::BT"; 11202 case X86ISD::CMP: return "X86ISD::CMP"; 11203 case X86ISD::COMI: return "X86ISD::COMI"; 11204 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11205 case X86ISD::SETCC: return "X86ISD::SETCC"; 11206 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11207 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11208 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11209 case X86ISD::CMOV: return "X86ISD::CMOV"; 11210 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11211 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11212 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11213 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11214 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11215 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11216 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11217 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11218 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11219 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11220 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11221 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11222 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11223 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11224 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11225 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11226 case X86ISD::BLENDPW: return "X86ISD::BLENDPW"; 11227 case X86ISD::BLENDPS: return "X86ISD::BLENDPS"; 11228 case X86ISD::BLENDPD: return "X86ISD::BLENDPD"; 11229 case X86ISD::HADD: return "X86ISD::HADD"; 11230 case X86ISD::HSUB: return "X86ISD::HSUB"; 11231 case X86ISD::FHADD: return "X86ISD::FHADD"; 11232 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11233 case X86ISD::FMAX: return "X86ISD::FMAX"; 11234 case X86ISD::FMIN: return "X86ISD::FMIN"; 11235 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11236 case X86ISD::FRCP: return "X86ISD::FRCP"; 11237 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11238 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11239 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11240 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11241 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11242 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 11243 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11244 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11245 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11246 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11247 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11248 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11249 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11250 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11251 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11252 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11253 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11254 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11255 case X86ISD::VSHL: return "X86ISD::VSHL"; 11256 case X86ISD::VSRL: return "X86ISD::VSRL"; 11257 case X86ISD::VSRA: return "X86ISD::VSRA"; 11258 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11259 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11260 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11261 case X86ISD::CMPP: return "X86ISD::CMPP"; 11262 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11263 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11264 case X86ISD::ADD: return "X86ISD::ADD"; 11265 case X86ISD::SUB: return "X86ISD::SUB"; 11266 case X86ISD::ADC: return "X86ISD::ADC"; 11267 case X86ISD::SBB: return "X86ISD::SBB"; 11268 case X86ISD::SMUL: return "X86ISD::SMUL"; 11269 case X86ISD::UMUL: return "X86ISD::UMUL"; 11270 case X86ISD::INC: return "X86ISD::INC"; 11271 case X86ISD::DEC: return "X86ISD::DEC"; 11272 case X86ISD::OR: return "X86ISD::OR"; 11273 case X86ISD::XOR: return "X86ISD::XOR"; 11274 case X86ISD::AND: return "X86ISD::AND"; 11275 case X86ISD::ANDN: return "X86ISD::ANDN"; 11276 case X86ISD::BLSI: return "X86ISD::BLSI"; 11277 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11278 case X86ISD::BLSR: return "X86ISD::BLSR"; 11279 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11280 case X86ISD::PTEST: return "X86ISD::PTEST"; 11281 case X86ISD::TESTP: return "X86ISD::TESTP"; 11282 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11283 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11284 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11285 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11286 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11287 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11288 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11289 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11290 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11291 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11292 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11293 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11294 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11295 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11296 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11297 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11298 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11299 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11300 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11301 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11302 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 11303 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 11304 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11305 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11306 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11307 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11308 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11309 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11310 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11311 case X86ISD::SAHF: return "X86ISD::SAHF"; 11312 } 11313} 11314 11315// isLegalAddressingMode - Return true if the addressing mode represented 11316// by AM is legal for this target, for a load/store of the specified type. 11317bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11318 Type *Ty) const { 11319 // X86 supports extremely general addressing modes. 11320 CodeModel::Model M = getTargetMachine().getCodeModel(); 11321 Reloc::Model R = getTargetMachine().getRelocationModel(); 11322 11323 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11324 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11325 return false; 11326 11327 if (AM.BaseGV) { 11328 unsigned GVFlags = 11329 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11330 11331 // If a reference to this global requires an extra load, we can't fold it. 11332 if (isGlobalStubReference(GVFlags)) 11333 return false; 11334 11335 // If BaseGV requires a register for the PIC base, we cannot also have a 11336 // BaseReg specified. 11337 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11338 return false; 11339 11340 // If lower 4G is not available, then we must use rip-relative addressing. 11341 if ((M != CodeModel::Small || R != Reloc::Static) && 11342 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11343 return false; 11344 } 11345 11346 switch (AM.Scale) { 11347 case 0: 11348 case 1: 11349 case 2: 11350 case 4: 11351 case 8: 11352 // These scales always work. 11353 break; 11354 case 3: 11355 case 5: 11356 case 9: 11357 // These scales are formed with basereg+scalereg. Only accept if there is 11358 // no basereg yet. 11359 if (AM.HasBaseReg) 11360 return false; 11361 break; 11362 default: // Other stuff never works. 11363 return false; 11364 } 11365 11366 return true; 11367} 11368 11369 11370bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11371 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11372 return false; 11373 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11374 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11375 if (NumBits1 <= NumBits2) 11376 return false; 11377 return true; 11378} 11379 11380bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11381 if (!VT1.isInteger() || !VT2.isInteger()) 11382 return false; 11383 unsigned NumBits1 = VT1.getSizeInBits(); 11384 unsigned NumBits2 = VT2.getSizeInBits(); 11385 if (NumBits1 <= NumBits2) 11386 return false; 11387 return true; 11388} 11389 11390bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11391 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11392 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11393} 11394 11395bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11396 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11397 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11398} 11399 11400bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11401 // i16 instructions are longer (0x66 prefix) and potentially slower. 11402 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11403} 11404 11405/// isShuffleMaskLegal - Targets can use this to indicate that they only 11406/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11407/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11408/// are assumed to be legal. 11409bool 11410X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11411 EVT VT) const { 11412 // Very little shuffling can be done for 64-bit vectors right now. 11413 if (VT.getSizeInBits() == 64) 11414 return false; 11415 11416 // FIXME: pshufb, blends, shifts. 11417 return (VT.getVectorNumElements() == 2 || 11418 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11419 isMOVLMask(M, VT) || 11420 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11421 isPSHUFDMask(M, VT) || 11422 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) || 11423 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) || 11424 isPALIGNRMask(M, VT, Subtarget) || 11425 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11426 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11427 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11428 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11429} 11430 11431bool 11432X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11433 EVT VT) const { 11434 unsigned NumElts = VT.getVectorNumElements(); 11435 // FIXME: This collection of masks seems suspect. 11436 if (NumElts == 2) 11437 return true; 11438 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11439 return (isMOVLMask(Mask, VT) || 11440 isCommutedMOVLMask(Mask, VT, true) || 11441 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11442 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11443 } 11444 return false; 11445} 11446 11447//===----------------------------------------------------------------------===// 11448// X86 Scheduler Hooks 11449//===----------------------------------------------------------------------===// 11450 11451// private utility function 11452MachineBasicBlock * 11453X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11454 MachineBasicBlock *MBB, 11455 unsigned regOpc, 11456 unsigned immOpc, 11457 unsigned LoadOpc, 11458 unsigned CXchgOpc, 11459 unsigned notOpc, 11460 unsigned EAXreg, 11461 const TargetRegisterClass *RC, 11462 bool Invert) const { 11463 // For the atomic bitwise operator, we generate 11464 // thisMBB: 11465 // newMBB: 11466 // ld t1 = [bitinstr.addr] 11467 // op t2 = t1, [bitinstr.val] 11468 // not t3 = t2 (if Invert) 11469 // mov EAX = t1 11470 // lcs dest = [bitinstr.addr], t3 [EAX is implicit] 11471 // bz newMBB 11472 // fallthrough -->nextMBB 11473 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11474 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11475 MachineFunction::iterator MBBIter = MBB; 11476 ++MBBIter; 11477 11478 /// First build the CFG 11479 MachineFunction *F = MBB->getParent(); 11480 MachineBasicBlock *thisMBB = MBB; 11481 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11482 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11483 F->insert(MBBIter, newMBB); 11484 F->insert(MBBIter, nextMBB); 11485 11486 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11487 nextMBB->splice(nextMBB->begin(), thisMBB, 11488 llvm::next(MachineBasicBlock::iterator(bInstr)), 11489 thisMBB->end()); 11490 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11491 11492 // Update thisMBB to fall through to newMBB 11493 thisMBB->addSuccessor(newMBB); 11494 11495 // newMBB jumps to itself and fall through to nextMBB 11496 newMBB->addSuccessor(nextMBB); 11497 newMBB->addSuccessor(newMBB); 11498 11499 // Insert instructions into newMBB based on incoming instruction 11500 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11501 "unexpected number of operands"); 11502 DebugLoc dl = bInstr->getDebugLoc(); 11503 MachineOperand& destOper = bInstr->getOperand(0); 11504 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11505 int numArgs = bInstr->getNumOperands() - 1; 11506 for (int i=0; i < numArgs; ++i) 11507 argOpers[i] = &bInstr->getOperand(i+1); 11508 11509 // x86 address has 4 operands: base, index, scale, and displacement 11510 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11511 int valArgIndx = lastAddrIndx + 1; 11512 11513 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11514 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11515 for (int i=0; i <= lastAddrIndx; ++i) 11516 (*MIB).addOperand(*argOpers[i]); 11517 11518 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11519 assert((argOpers[valArgIndx]->isReg() || 11520 argOpers[valArgIndx]->isImm()) && 11521 "invalid operand"); 11522 if (argOpers[valArgIndx]->isReg()) 11523 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11524 else 11525 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11526 MIB.addReg(t1); 11527 (*MIB).addOperand(*argOpers[valArgIndx]); 11528 11529 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11530 if (Invert) { 11531 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2); 11532 } 11533 else 11534 t3 = t2; 11535 11536 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11537 MIB.addReg(t1); 11538 11539 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11540 for (int i=0; i <= lastAddrIndx; ++i) 11541 (*MIB).addOperand(*argOpers[i]); 11542 MIB.addReg(t3); 11543 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11544 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11545 bInstr->memoperands_end()); 11546 11547 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11548 MIB.addReg(EAXreg); 11549 11550 // insert branch 11551 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11552 11553 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11554 return nextMBB; 11555} 11556 11557// private utility function: 64 bit atomics on 32 bit host. 11558MachineBasicBlock * 11559X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11560 MachineBasicBlock *MBB, 11561 unsigned regOpcL, 11562 unsigned regOpcH, 11563 unsigned immOpcL, 11564 unsigned immOpcH, 11565 bool Invert) const { 11566 // For the atomic bitwise operator, we generate 11567 // thisMBB (instructions are in pairs, except cmpxchg8b) 11568 // ld t1,t2 = [bitinstr.addr] 11569 // newMBB: 11570 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11571 // op t5, t6 <- out1, out2, [bitinstr.val] 11572 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11573 // neg t7, t8 < t5, t6 (if Invert) 11574 // mov ECX, EBX <- t5, t6 11575 // mov EAX, EDX <- t1, t2 11576 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11577 // mov t3, t4 <- EAX, EDX 11578 // bz newMBB 11579 // result in out1, out2 11580 // fallthrough -->nextMBB 11581 11582 const TargetRegisterClass *RC = &X86::GR32RegClass; 11583 const unsigned LoadOpc = X86::MOV32rm; 11584 const unsigned NotOpc = X86::NOT32r; 11585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11586 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11587 MachineFunction::iterator MBBIter = MBB; 11588 ++MBBIter; 11589 11590 /// First build the CFG 11591 MachineFunction *F = MBB->getParent(); 11592 MachineBasicBlock *thisMBB = MBB; 11593 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11594 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11595 F->insert(MBBIter, newMBB); 11596 F->insert(MBBIter, nextMBB); 11597 11598 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11599 nextMBB->splice(nextMBB->begin(), thisMBB, 11600 llvm::next(MachineBasicBlock::iterator(bInstr)), 11601 thisMBB->end()); 11602 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11603 11604 // Update thisMBB to fall through to newMBB 11605 thisMBB->addSuccessor(newMBB); 11606 11607 // newMBB jumps to itself and fall through to nextMBB 11608 newMBB->addSuccessor(nextMBB); 11609 newMBB->addSuccessor(newMBB); 11610 11611 DebugLoc dl = bInstr->getDebugLoc(); 11612 // Insert instructions into newMBB based on incoming instruction 11613 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11614 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11615 "unexpected number of operands"); 11616 MachineOperand& dest1Oper = bInstr->getOperand(0); 11617 MachineOperand& dest2Oper = bInstr->getOperand(1); 11618 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11619 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11620 argOpers[i] = &bInstr->getOperand(i+2); 11621 11622 // We use some of the operands multiple times, so conservatively just 11623 // clear any kill flags that might be present. 11624 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11625 argOpers[i]->setIsKill(false); 11626 } 11627 11628 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11629 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11630 11631 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11632 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11633 for (int i=0; i <= lastAddrIndx; ++i) 11634 (*MIB).addOperand(*argOpers[i]); 11635 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11636 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11637 // add 4 to displacement. 11638 for (int i=0; i <= lastAddrIndx-2; ++i) 11639 (*MIB).addOperand(*argOpers[i]); 11640 MachineOperand newOp3 = *(argOpers[3]); 11641 if (newOp3.isImm()) 11642 newOp3.setImm(newOp3.getImm()+4); 11643 else 11644 newOp3.setOffset(newOp3.getOffset()+4); 11645 (*MIB).addOperand(newOp3); 11646 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11647 11648 // t3/4 are defined later, at the bottom of the loop 11649 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11650 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11651 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11652 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11653 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11654 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11655 11656 // The subsequent operations should be using the destination registers of 11657 // the PHI instructions. 11658 t1 = dest1Oper.getReg(); 11659 t2 = dest2Oper.getReg(); 11660 11661 int valArgIndx = lastAddrIndx + 1; 11662 assert((argOpers[valArgIndx]->isReg() || 11663 argOpers[valArgIndx]->isImm()) && 11664 "invalid operand"); 11665 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11666 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11667 if (argOpers[valArgIndx]->isReg()) 11668 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11669 else 11670 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11671 if (regOpcL != X86::MOV32rr) 11672 MIB.addReg(t1); 11673 (*MIB).addOperand(*argOpers[valArgIndx]); 11674 assert(argOpers[valArgIndx + 1]->isReg() == 11675 argOpers[valArgIndx]->isReg()); 11676 assert(argOpers[valArgIndx + 1]->isImm() == 11677 argOpers[valArgIndx]->isImm()); 11678 if (argOpers[valArgIndx + 1]->isReg()) 11679 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11680 else 11681 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11682 if (regOpcH != X86::MOV32rr) 11683 MIB.addReg(t2); 11684 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11685 11686 unsigned t7, t8; 11687 if (Invert) { 11688 t7 = F->getRegInfo().createVirtualRegister(RC); 11689 t8 = F->getRegInfo().createVirtualRegister(RC); 11690 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5); 11691 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6); 11692 } else { 11693 t7 = t5; 11694 t8 = t6; 11695 } 11696 11697 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11698 MIB.addReg(t1); 11699 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11700 MIB.addReg(t2); 11701 11702 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11703 MIB.addReg(t7); 11704 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11705 MIB.addReg(t8); 11706 11707 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11708 for (int i=0; i <= lastAddrIndx; ++i) 11709 (*MIB).addOperand(*argOpers[i]); 11710 11711 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11712 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11713 bInstr->memoperands_end()); 11714 11715 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11716 MIB.addReg(X86::EAX); 11717 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11718 MIB.addReg(X86::EDX); 11719 11720 // insert branch 11721 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11722 11723 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11724 return nextMBB; 11725} 11726 11727// private utility function 11728MachineBasicBlock * 11729X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11730 MachineBasicBlock *MBB, 11731 unsigned cmovOpc) const { 11732 // For the atomic min/max operator, we generate 11733 // thisMBB: 11734 // newMBB: 11735 // ld t1 = [min/max.addr] 11736 // mov t2 = [min/max.val] 11737 // cmp t1, t2 11738 // cmov[cond] t2 = t1 11739 // mov EAX = t1 11740 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11741 // bz newMBB 11742 // fallthrough -->nextMBB 11743 // 11744 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11745 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11746 MachineFunction::iterator MBBIter = MBB; 11747 ++MBBIter; 11748 11749 /// First build the CFG 11750 MachineFunction *F = MBB->getParent(); 11751 MachineBasicBlock *thisMBB = MBB; 11752 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11753 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11754 F->insert(MBBIter, newMBB); 11755 F->insert(MBBIter, nextMBB); 11756 11757 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11758 nextMBB->splice(nextMBB->begin(), thisMBB, 11759 llvm::next(MachineBasicBlock::iterator(mInstr)), 11760 thisMBB->end()); 11761 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11762 11763 // Update thisMBB to fall through to newMBB 11764 thisMBB->addSuccessor(newMBB); 11765 11766 // newMBB jumps to newMBB and fall through to nextMBB 11767 newMBB->addSuccessor(nextMBB); 11768 newMBB->addSuccessor(newMBB); 11769 11770 DebugLoc dl = mInstr->getDebugLoc(); 11771 // Insert instructions into newMBB based on incoming instruction 11772 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11773 "unexpected number of operands"); 11774 MachineOperand& destOper = mInstr->getOperand(0); 11775 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11776 int numArgs = mInstr->getNumOperands() - 1; 11777 for (int i=0; i < numArgs; ++i) 11778 argOpers[i] = &mInstr->getOperand(i+1); 11779 11780 // x86 address has 4 operands: base, index, scale, and displacement 11781 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11782 int valArgIndx = lastAddrIndx + 1; 11783 11784 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11785 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11786 for (int i=0; i <= lastAddrIndx; ++i) 11787 (*MIB).addOperand(*argOpers[i]); 11788 11789 // We only support register and immediate values 11790 assert((argOpers[valArgIndx]->isReg() || 11791 argOpers[valArgIndx]->isImm()) && 11792 "invalid operand"); 11793 11794 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11795 if (argOpers[valArgIndx]->isReg()) 11796 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11797 else 11798 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11799 (*MIB).addOperand(*argOpers[valArgIndx]); 11800 11801 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11802 MIB.addReg(t1); 11803 11804 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11805 MIB.addReg(t1); 11806 MIB.addReg(t2); 11807 11808 // Generate movc 11809 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11810 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11811 MIB.addReg(t2); 11812 MIB.addReg(t1); 11813 11814 // Cmp and exchange if none has modified the memory location 11815 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11816 for (int i=0; i <= lastAddrIndx; ++i) 11817 (*MIB).addOperand(*argOpers[i]); 11818 MIB.addReg(t3); 11819 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11820 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11821 mInstr->memoperands_end()); 11822 11823 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11824 MIB.addReg(X86::EAX); 11825 11826 // insert branch 11827 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11828 11829 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11830 return nextMBB; 11831} 11832 11833// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11834// or XMM0_V32I8 in AVX all of this code can be replaced with that 11835// in the .td file. 11836MachineBasicBlock * 11837X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11838 unsigned numArgs, bool memArg) const { 11839 assert(Subtarget->hasSSE42() && 11840 "Target must have SSE4.2 or AVX features enabled"); 11841 11842 DebugLoc dl = MI->getDebugLoc(); 11843 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11844 unsigned Opc; 11845 if (!Subtarget->hasAVX()) { 11846 if (memArg) 11847 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11848 else 11849 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11850 } else { 11851 if (memArg) 11852 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11853 else 11854 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11855 } 11856 11857 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11858 for (unsigned i = 0; i < numArgs; ++i) { 11859 MachineOperand &Op = MI->getOperand(i+1); 11860 if (!(Op.isReg() && Op.isImplicit())) 11861 MIB.addOperand(Op); 11862 } 11863 BuildMI(*BB, MI, dl, 11864 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11865 MI->getOperand(0).getReg()) 11866 .addReg(X86::XMM0); 11867 11868 MI->eraseFromParent(); 11869 return BB; 11870} 11871 11872MachineBasicBlock * 11873X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11874 DebugLoc dl = MI->getDebugLoc(); 11875 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11876 11877 // Address into RAX/EAX, other two args into ECX, EDX. 11878 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11879 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11880 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11881 for (int i = 0; i < X86::AddrNumOperands; ++i) 11882 MIB.addOperand(MI->getOperand(i)); 11883 11884 unsigned ValOps = X86::AddrNumOperands; 11885 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11886 .addReg(MI->getOperand(ValOps).getReg()); 11887 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11888 .addReg(MI->getOperand(ValOps+1).getReg()); 11889 11890 // The instruction doesn't actually take any operands though. 11891 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11892 11893 MI->eraseFromParent(); // The pseudo is gone now. 11894 return BB; 11895} 11896 11897MachineBasicBlock * 11898X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11899 DebugLoc dl = MI->getDebugLoc(); 11900 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11901 11902 // First arg in ECX, the second in EAX. 11903 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11904 .addReg(MI->getOperand(0).getReg()); 11905 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11906 .addReg(MI->getOperand(1).getReg()); 11907 11908 // The instruction doesn't actually take any operands though. 11909 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11910 11911 MI->eraseFromParent(); // The pseudo is gone now. 11912 return BB; 11913} 11914 11915MachineBasicBlock * 11916X86TargetLowering::EmitVAARG64WithCustomInserter( 11917 MachineInstr *MI, 11918 MachineBasicBlock *MBB) const { 11919 // Emit va_arg instruction on X86-64. 11920 11921 // Operands to this pseudo-instruction: 11922 // 0 ) Output : destination address (reg) 11923 // 1-5) Input : va_list address (addr, i64mem) 11924 // 6 ) ArgSize : Size (in bytes) of vararg type 11925 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11926 // 8 ) Align : Alignment of type 11927 // 9 ) EFLAGS (implicit-def) 11928 11929 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11930 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11931 11932 unsigned DestReg = MI->getOperand(0).getReg(); 11933 MachineOperand &Base = MI->getOperand(1); 11934 MachineOperand &Scale = MI->getOperand(2); 11935 MachineOperand &Index = MI->getOperand(3); 11936 MachineOperand &Disp = MI->getOperand(4); 11937 MachineOperand &Segment = MI->getOperand(5); 11938 unsigned ArgSize = MI->getOperand(6).getImm(); 11939 unsigned ArgMode = MI->getOperand(7).getImm(); 11940 unsigned Align = MI->getOperand(8).getImm(); 11941 11942 // Memory Reference 11943 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11944 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11945 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11946 11947 // Machine Information 11948 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11949 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11950 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11951 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11952 DebugLoc DL = MI->getDebugLoc(); 11953 11954 // struct va_list { 11955 // i32 gp_offset 11956 // i32 fp_offset 11957 // i64 overflow_area (address) 11958 // i64 reg_save_area (address) 11959 // } 11960 // sizeof(va_list) = 24 11961 // alignment(va_list) = 8 11962 11963 unsigned TotalNumIntRegs = 6; 11964 unsigned TotalNumXMMRegs = 8; 11965 bool UseGPOffset = (ArgMode == 1); 11966 bool UseFPOffset = (ArgMode == 2); 11967 unsigned MaxOffset = TotalNumIntRegs * 8 + 11968 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11969 11970 /* Align ArgSize to a multiple of 8 */ 11971 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11972 bool NeedsAlign = (Align > 8); 11973 11974 MachineBasicBlock *thisMBB = MBB; 11975 MachineBasicBlock *overflowMBB; 11976 MachineBasicBlock *offsetMBB; 11977 MachineBasicBlock *endMBB; 11978 11979 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11980 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11981 unsigned OffsetReg = 0; 11982 11983 if (!UseGPOffset && !UseFPOffset) { 11984 // If we only pull from the overflow region, we don't create a branch. 11985 // We don't need to alter control flow. 11986 OffsetDestReg = 0; // unused 11987 OverflowDestReg = DestReg; 11988 11989 offsetMBB = NULL; 11990 overflowMBB = thisMBB; 11991 endMBB = thisMBB; 11992 } else { 11993 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11994 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11995 // If not, pull from overflow_area. (branch to overflowMBB) 11996 // 11997 // thisMBB 11998 // | . 11999 // | . 12000 // offsetMBB overflowMBB 12001 // | . 12002 // | . 12003 // endMBB 12004 12005 // Registers for the PHI in endMBB 12006 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 12007 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 12008 12009 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12010 MachineFunction *MF = MBB->getParent(); 12011 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12012 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12013 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12014 12015 MachineFunction::iterator MBBIter = MBB; 12016 ++MBBIter; 12017 12018 // Insert the new basic blocks 12019 MF->insert(MBBIter, offsetMBB); 12020 MF->insert(MBBIter, overflowMBB); 12021 MF->insert(MBBIter, endMBB); 12022 12023 // Transfer the remainder of MBB and its successor edges to endMBB. 12024 endMBB->splice(endMBB->begin(), thisMBB, 12025 llvm::next(MachineBasicBlock::iterator(MI)), 12026 thisMBB->end()); 12027 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 12028 12029 // Make offsetMBB and overflowMBB successors of thisMBB 12030 thisMBB->addSuccessor(offsetMBB); 12031 thisMBB->addSuccessor(overflowMBB); 12032 12033 // endMBB is a successor of both offsetMBB and overflowMBB 12034 offsetMBB->addSuccessor(endMBB); 12035 overflowMBB->addSuccessor(endMBB); 12036 12037 // Load the offset value into a register 12038 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12039 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 12040 .addOperand(Base) 12041 .addOperand(Scale) 12042 .addOperand(Index) 12043 .addDisp(Disp, UseFPOffset ? 4 : 0) 12044 .addOperand(Segment) 12045 .setMemRefs(MMOBegin, MMOEnd); 12046 12047 // Check if there is enough room left to pull this argument. 12048 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 12049 .addReg(OffsetReg) 12050 .addImm(MaxOffset + 8 - ArgSizeA8); 12051 12052 // Branch to "overflowMBB" if offset >= max 12053 // Fall through to "offsetMBB" otherwise 12054 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 12055 .addMBB(overflowMBB); 12056 } 12057 12058 // In offsetMBB, emit code to use the reg_save_area. 12059 if (offsetMBB) { 12060 assert(OffsetReg != 0); 12061 12062 // Read the reg_save_area address. 12063 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 12064 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 12065 .addOperand(Base) 12066 .addOperand(Scale) 12067 .addOperand(Index) 12068 .addDisp(Disp, 16) 12069 .addOperand(Segment) 12070 .setMemRefs(MMOBegin, MMOEnd); 12071 12072 // Zero-extend the offset 12073 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 12074 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 12075 .addImm(0) 12076 .addReg(OffsetReg) 12077 .addImm(X86::sub_32bit); 12078 12079 // Add the offset to the reg_save_area to get the final address. 12080 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 12081 .addReg(OffsetReg64) 12082 .addReg(RegSaveReg); 12083 12084 // Compute the offset for the next argument 12085 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 12086 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 12087 .addReg(OffsetReg) 12088 .addImm(UseFPOffset ? 16 : 8); 12089 12090 // Store it back into the va_list. 12091 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 12092 .addOperand(Base) 12093 .addOperand(Scale) 12094 .addOperand(Index) 12095 .addDisp(Disp, UseFPOffset ? 4 : 0) 12096 .addOperand(Segment) 12097 .addReg(NextOffsetReg) 12098 .setMemRefs(MMOBegin, MMOEnd); 12099 12100 // Jump to endMBB 12101 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 12102 .addMBB(endMBB); 12103 } 12104 12105 // 12106 // Emit code to use overflow area 12107 // 12108 12109 // Load the overflow_area address into a register. 12110 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 12111 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 12112 .addOperand(Base) 12113 .addOperand(Scale) 12114 .addOperand(Index) 12115 .addDisp(Disp, 8) 12116 .addOperand(Segment) 12117 .setMemRefs(MMOBegin, MMOEnd); 12118 12119 // If we need to align it, do so. Otherwise, just copy the address 12120 // to OverflowDestReg. 12121 if (NeedsAlign) { 12122 // Align the overflow address 12123 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12124 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12125 12126 // aligned_addr = (addr + (align-1)) & ~(align-1) 12127 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12128 .addReg(OverflowAddrReg) 12129 .addImm(Align-1); 12130 12131 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12132 .addReg(TmpReg) 12133 .addImm(~(uint64_t)(Align-1)); 12134 } else { 12135 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12136 .addReg(OverflowAddrReg); 12137 } 12138 12139 // Compute the next overflow address after this argument. 12140 // (the overflow address should be kept 8-byte aligned) 12141 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12142 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12143 .addReg(OverflowDestReg) 12144 .addImm(ArgSizeA8); 12145 12146 // Store the new overflow address. 12147 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12148 .addOperand(Base) 12149 .addOperand(Scale) 12150 .addOperand(Index) 12151 .addDisp(Disp, 8) 12152 .addOperand(Segment) 12153 .addReg(NextAddrReg) 12154 .setMemRefs(MMOBegin, MMOEnd); 12155 12156 // If we branched, emit the PHI to the front of endMBB. 12157 if (offsetMBB) { 12158 BuildMI(*endMBB, endMBB->begin(), DL, 12159 TII->get(X86::PHI), DestReg) 12160 .addReg(OffsetDestReg).addMBB(offsetMBB) 12161 .addReg(OverflowDestReg).addMBB(overflowMBB); 12162 } 12163 12164 // Erase the pseudo instruction 12165 MI->eraseFromParent(); 12166 12167 return endMBB; 12168} 12169 12170MachineBasicBlock * 12171X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12172 MachineInstr *MI, 12173 MachineBasicBlock *MBB) const { 12174 // Emit code to save XMM registers to the stack. The ABI says that the 12175 // number of registers to save is given in %al, so it's theoretically 12176 // possible to do an indirect jump trick to avoid saving all of them, 12177 // however this code takes a simpler approach and just executes all 12178 // of the stores if %al is non-zero. It's less code, and it's probably 12179 // easier on the hardware branch predictor, and stores aren't all that 12180 // expensive anyway. 12181 12182 // Create the new basic blocks. One block contains all the XMM stores, 12183 // and one block is the final destination regardless of whether any 12184 // stores were performed. 12185 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12186 MachineFunction *F = MBB->getParent(); 12187 MachineFunction::iterator MBBIter = MBB; 12188 ++MBBIter; 12189 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12190 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12191 F->insert(MBBIter, XMMSaveMBB); 12192 F->insert(MBBIter, EndMBB); 12193 12194 // Transfer the remainder of MBB and its successor edges to EndMBB. 12195 EndMBB->splice(EndMBB->begin(), MBB, 12196 llvm::next(MachineBasicBlock::iterator(MI)), 12197 MBB->end()); 12198 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12199 12200 // The original block will now fall through to the XMM save block. 12201 MBB->addSuccessor(XMMSaveMBB); 12202 // The XMMSaveMBB will fall through to the end block. 12203 XMMSaveMBB->addSuccessor(EndMBB); 12204 12205 // Now add the instructions. 12206 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12207 DebugLoc DL = MI->getDebugLoc(); 12208 12209 unsigned CountReg = MI->getOperand(0).getReg(); 12210 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12211 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12212 12213 if (!Subtarget->isTargetWin64()) { 12214 // If %al is 0, branch around the XMM save block. 12215 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12216 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12217 MBB->addSuccessor(EndMBB); 12218 } 12219 12220 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12221 // In the XMM save block, save all the XMM argument registers. 12222 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12223 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12224 MachineMemOperand *MMO = 12225 F->getMachineMemOperand( 12226 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12227 MachineMemOperand::MOStore, 12228 /*Size=*/16, /*Align=*/16); 12229 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12230 .addFrameIndex(RegSaveFrameIndex) 12231 .addImm(/*Scale=*/1) 12232 .addReg(/*IndexReg=*/0) 12233 .addImm(/*Disp=*/Offset) 12234 .addReg(/*Segment=*/0) 12235 .addReg(MI->getOperand(i).getReg()) 12236 .addMemOperand(MMO); 12237 } 12238 12239 MI->eraseFromParent(); // The pseudo instruction is gone now. 12240 12241 return EndMBB; 12242} 12243 12244// The EFLAGS operand of SelectItr might be missing a kill marker 12245// because there were multiple uses of EFLAGS, and ISel didn't know 12246// which to mark. Figure out whether SelectItr should have had a 12247// kill marker, and set it if it should. Returns the correct kill 12248// marker value. 12249static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12250 MachineBasicBlock* BB, 12251 const TargetRegisterInfo* TRI) { 12252 // Scan forward through BB for a use/def of EFLAGS. 12253 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12254 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12255 const MachineInstr& mi = *miI; 12256 if (mi.readsRegister(X86::EFLAGS)) 12257 return false; 12258 if (mi.definesRegister(X86::EFLAGS)) 12259 break; // Should have kill-flag - update below. 12260 } 12261 12262 // If we hit the end of the block, check whether EFLAGS is live into a 12263 // successor. 12264 if (miI == BB->end()) { 12265 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12266 sEnd = BB->succ_end(); 12267 sItr != sEnd; ++sItr) { 12268 MachineBasicBlock* succ = *sItr; 12269 if (succ->isLiveIn(X86::EFLAGS)) 12270 return false; 12271 } 12272 } 12273 12274 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12275 // out. SelectMI should have a kill flag on EFLAGS. 12276 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12277 return true; 12278} 12279 12280MachineBasicBlock * 12281X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12282 MachineBasicBlock *BB) const { 12283 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12284 DebugLoc DL = MI->getDebugLoc(); 12285 12286 // To "insert" a SELECT_CC instruction, we actually have to insert the 12287 // diamond control-flow pattern. The incoming instruction knows the 12288 // destination vreg to set, the condition code register to branch on, the 12289 // true/false values to select between, and a branch opcode to use. 12290 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12291 MachineFunction::iterator It = BB; 12292 ++It; 12293 12294 // thisMBB: 12295 // ... 12296 // TrueVal = ... 12297 // cmpTY ccX, r1, r2 12298 // bCC copy1MBB 12299 // fallthrough --> copy0MBB 12300 MachineBasicBlock *thisMBB = BB; 12301 MachineFunction *F = BB->getParent(); 12302 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12303 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12304 F->insert(It, copy0MBB); 12305 F->insert(It, sinkMBB); 12306 12307 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12308 // live into the sink and copy blocks. 12309 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12310 if (!MI->killsRegister(X86::EFLAGS) && 12311 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12312 copy0MBB->addLiveIn(X86::EFLAGS); 12313 sinkMBB->addLiveIn(X86::EFLAGS); 12314 } 12315 12316 // Transfer the remainder of BB and its successor edges to sinkMBB. 12317 sinkMBB->splice(sinkMBB->begin(), BB, 12318 llvm::next(MachineBasicBlock::iterator(MI)), 12319 BB->end()); 12320 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12321 12322 // Add the true and fallthrough blocks as its successors. 12323 BB->addSuccessor(copy0MBB); 12324 BB->addSuccessor(sinkMBB); 12325 12326 // Create the conditional branch instruction. 12327 unsigned Opc = 12328 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12329 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12330 12331 // copy0MBB: 12332 // %FalseValue = ... 12333 // # fallthrough to sinkMBB 12334 copy0MBB->addSuccessor(sinkMBB); 12335 12336 // sinkMBB: 12337 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12338 // ... 12339 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12340 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12341 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12342 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12343 12344 MI->eraseFromParent(); // The pseudo instruction is gone now. 12345 return sinkMBB; 12346} 12347 12348MachineBasicBlock * 12349X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12350 bool Is64Bit) const { 12351 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12352 DebugLoc DL = MI->getDebugLoc(); 12353 MachineFunction *MF = BB->getParent(); 12354 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12355 12356 assert(getTargetMachine().Options.EnableSegmentedStacks); 12357 12358 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12359 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12360 12361 // BB: 12362 // ... [Till the alloca] 12363 // If stacklet is not large enough, jump to mallocMBB 12364 // 12365 // bumpMBB: 12366 // Allocate by subtracting from RSP 12367 // Jump to continueMBB 12368 // 12369 // mallocMBB: 12370 // Allocate by call to runtime 12371 // 12372 // continueMBB: 12373 // ... 12374 // [rest of original BB] 12375 // 12376 12377 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12378 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12379 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12380 12381 MachineRegisterInfo &MRI = MF->getRegInfo(); 12382 const TargetRegisterClass *AddrRegClass = 12383 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12384 12385 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12386 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12387 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12388 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12389 sizeVReg = MI->getOperand(1).getReg(), 12390 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12391 12392 MachineFunction::iterator MBBIter = BB; 12393 ++MBBIter; 12394 12395 MF->insert(MBBIter, bumpMBB); 12396 MF->insert(MBBIter, mallocMBB); 12397 MF->insert(MBBIter, continueMBB); 12398 12399 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12400 (MachineBasicBlock::iterator(MI)), BB->end()); 12401 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12402 12403 // Add code to the main basic block to check if the stack limit has been hit, 12404 // and if so, jump to mallocMBB otherwise to bumpMBB. 12405 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12406 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12407 .addReg(tmpSPVReg).addReg(sizeVReg); 12408 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12409 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12410 .addReg(SPLimitVReg); 12411 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12412 12413 // bumpMBB simply decreases the stack pointer, since we know the current 12414 // stacklet has enough space. 12415 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12416 .addReg(SPLimitVReg); 12417 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12418 .addReg(SPLimitVReg); 12419 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12420 12421 // Calls into a routine in libgcc to allocate more space from the heap. 12422 const uint32_t *RegMask = 12423 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12424 if (Is64Bit) { 12425 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12426 .addReg(sizeVReg); 12427 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12428 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12429 .addRegMask(RegMask) 12430 .addReg(X86::RAX, RegState::ImplicitDefine); 12431 } else { 12432 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12433 .addImm(12); 12434 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12435 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12436 .addExternalSymbol("__morestack_allocate_stack_space") 12437 .addRegMask(RegMask) 12438 .addReg(X86::EAX, RegState::ImplicitDefine); 12439 } 12440 12441 if (!Is64Bit) 12442 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12443 .addImm(16); 12444 12445 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12446 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12447 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12448 12449 // Set up the CFG correctly. 12450 BB->addSuccessor(bumpMBB); 12451 BB->addSuccessor(mallocMBB); 12452 mallocMBB->addSuccessor(continueMBB); 12453 bumpMBB->addSuccessor(continueMBB); 12454 12455 // Take care of the PHI nodes. 12456 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12457 MI->getOperand(0).getReg()) 12458 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12459 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12460 12461 // Delete the original pseudo instruction. 12462 MI->eraseFromParent(); 12463 12464 // And we're done. 12465 return continueMBB; 12466} 12467 12468MachineBasicBlock * 12469X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12470 MachineBasicBlock *BB) const { 12471 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12472 DebugLoc DL = MI->getDebugLoc(); 12473 12474 assert(!Subtarget->isTargetEnvMacho()); 12475 12476 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12477 // non-trivial part is impdef of ESP. 12478 12479 if (Subtarget->isTargetWin64()) { 12480 if (Subtarget->isTargetCygMing()) { 12481 // ___chkstk(Mingw64): 12482 // Clobbers R10, R11, RAX and EFLAGS. 12483 // Updates RSP. 12484 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12485 .addExternalSymbol("___chkstk") 12486 .addReg(X86::RAX, RegState::Implicit) 12487 .addReg(X86::RSP, RegState::Implicit) 12488 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12489 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12490 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12491 } else { 12492 // __chkstk(MSVCRT): does not update stack pointer. 12493 // Clobbers R10, R11 and EFLAGS. 12494 // FIXME: RAX(allocated size) might be reused and not killed. 12495 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12496 .addExternalSymbol("__chkstk") 12497 .addReg(X86::RAX, RegState::Implicit) 12498 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12499 // RAX has the offset to subtracted from RSP. 12500 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12501 .addReg(X86::RSP) 12502 .addReg(X86::RAX); 12503 } 12504 } else { 12505 const char *StackProbeSymbol = 12506 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12507 12508 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12509 .addExternalSymbol(StackProbeSymbol) 12510 .addReg(X86::EAX, RegState::Implicit) 12511 .addReg(X86::ESP, RegState::Implicit) 12512 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12513 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12514 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12515 } 12516 12517 MI->eraseFromParent(); // The pseudo instruction is gone now. 12518 return BB; 12519} 12520 12521MachineBasicBlock * 12522X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12523 MachineBasicBlock *BB) const { 12524 // This is pretty easy. We're taking the value that we received from 12525 // our load from the relocation, sticking it in either RDI (x86-64) 12526 // or EAX and doing an indirect call. The return value will then 12527 // be in the normal return register. 12528 const X86InstrInfo *TII 12529 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12530 DebugLoc DL = MI->getDebugLoc(); 12531 MachineFunction *F = BB->getParent(); 12532 12533 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12534 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12535 12536 // Get a register mask for the lowered call. 12537 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12538 // proper register mask. 12539 const uint32_t *RegMask = 12540 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12541 if (Subtarget->is64Bit()) { 12542 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12543 TII->get(X86::MOV64rm), X86::RDI) 12544 .addReg(X86::RIP) 12545 .addImm(0).addReg(0) 12546 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12547 MI->getOperand(3).getTargetFlags()) 12548 .addReg(0); 12549 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12550 addDirectMem(MIB, X86::RDI); 12551 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12552 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12553 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12554 TII->get(X86::MOV32rm), X86::EAX) 12555 .addReg(0) 12556 .addImm(0).addReg(0) 12557 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12558 MI->getOperand(3).getTargetFlags()) 12559 .addReg(0); 12560 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12561 addDirectMem(MIB, X86::EAX); 12562 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12563 } else { 12564 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12565 TII->get(X86::MOV32rm), X86::EAX) 12566 .addReg(TII->getGlobalBaseReg(F)) 12567 .addImm(0).addReg(0) 12568 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12569 MI->getOperand(3).getTargetFlags()) 12570 .addReg(0); 12571 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12572 addDirectMem(MIB, X86::EAX); 12573 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12574 } 12575 12576 MI->eraseFromParent(); // The pseudo instruction is gone now. 12577 return BB; 12578} 12579 12580MachineBasicBlock * 12581X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12582 MachineBasicBlock *BB) const { 12583 switch (MI->getOpcode()) { 12584 default: llvm_unreachable("Unexpected instr type to insert"); 12585 case X86::TAILJMPd64: 12586 case X86::TAILJMPr64: 12587 case X86::TAILJMPm64: 12588 llvm_unreachable("TAILJMP64 would not be touched here."); 12589 case X86::TCRETURNdi64: 12590 case X86::TCRETURNri64: 12591 case X86::TCRETURNmi64: 12592 return BB; 12593 case X86::WIN_ALLOCA: 12594 return EmitLoweredWinAlloca(MI, BB); 12595 case X86::SEG_ALLOCA_32: 12596 return EmitLoweredSegAlloca(MI, BB, false); 12597 case X86::SEG_ALLOCA_64: 12598 return EmitLoweredSegAlloca(MI, BB, true); 12599 case X86::TLSCall_32: 12600 case X86::TLSCall_64: 12601 return EmitLoweredTLSCall(MI, BB); 12602 case X86::CMOV_GR8: 12603 case X86::CMOV_FR32: 12604 case X86::CMOV_FR64: 12605 case X86::CMOV_V4F32: 12606 case X86::CMOV_V2F64: 12607 case X86::CMOV_V2I64: 12608 case X86::CMOV_V8F32: 12609 case X86::CMOV_V4F64: 12610 case X86::CMOV_V4I64: 12611 case X86::CMOV_GR16: 12612 case X86::CMOV_GR32: 12613 case X86::CMOV_RFP32: 12614 case X86::CMOV_RFP64: 12615 case X86::CMOV_RFP80: 12616 return EmitLoweredSelect(MI, BB); 12617 12618 case X86::FP32_TO_INT16_IN_MEM: 12619 case X86::FP32_TO_INT32_IN_MEM: 12620 case X86::FP32_TO_INT64_IN_MEM: 12621 case X86::FP64_TO_INT16_IN_MEM: 12622 case X86::FP64_TO_INT32_IN_MEM: 12623 case X86::FP64_TO_INT64_IN_MEM: 12624 case X86::FP80_TO_INT16_IN_MEM: 12625 case X86::FP80_TO_INT32_IN_MEM: 12626 case X86::FP80_TO_INT64_IN_MEM: { 12627 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12628 DebugLoc DL = MI->getDebugLoc(); 12629 12630 // Change the floating point control register to use "round towards zero" 12631 // mode when truncating to an integer value. 12632 MachineFunction *F = BB->getParent(); 12633 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12634 addFrameReference(BuildMI(*BB, MI, DL, 12635 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12636 12637 // Load the old value of the high byte of the control word... 12638 unsigned OldCW = 12639 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 12640 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12641 CWFrameIdx); 12642 12643 // Set the high part to be round to zero... 12644 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12645 .addImm(0xC7F); 12646 12647 // Reload the modified control word now... 12648 addFrameReference(BuildMI(*BB, MI, DL, 12649 TII->get(X86::FLDCW16m)), CWFrameIdx); 12650 12651 // Restore the memory image of control word to original value 12652 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12653 .addReg(OldCW); 12654 12655 // Get the X86 opcode to use. 12656 unsigned Opc; 12657 switch (MI->getOpcode()) { 12658 default: llvm_unreachable("illegal opcode!"); 12659 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12660 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12661 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12662 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12663 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12664 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12665 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12666 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12667 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12668 } 12669 12670 X86AddressMode AM; 12671 MachineOperand &Op = MI->getOperand(0); 12672 if (Op.isReg()) { 12673 AM.BaseType = X86AddressMode::RegBase; 12674 AM.Base.Reg = Op.getReg(); 12675 } else { 12676 AM.BaseType = X86AddressMode::FrameIndexBase; 12677 AM.Base.FrameIndex = Op.getIndex(); 12678 } 12679 Op = MI->getOperand(1); 12680 if (Op.isImm()) 12681 AM.Scale = Op.getImm(); 12682 Op = MI->getOperand(2); 12683 if (Op.isImm()) 12684 AM.IndexReg = Op.getImm(); 12685 Op = MI->getOperand(3); 12686 if (Op.isGlobal()) { 12687 AM.GV = Op.getGlobal(); 12688 } else { 12689 AM.Disp = Op.getImm(); 12690 } 12691 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12692 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12693 12694 // Reload the original control word now. 12695 addFrameReference(BuildMI(*BB, MI, DL, 12696 TII->get(X86::FLDCW16m)), CWFrameIdx); 12697 12698 MI->eraseFromParent(); // The pseudo instruction is gone now. 12699 return BB; 12700 } 12701 // String/text processing lowering. 12702 case X86::PCMPISTRM128REG: 12703 case X86::VPCMPISTRM128REG: 12704 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12705 case X86::PCMPISTRM128MEM: 12706 case X86::VPCMPISTRM128MEM: 12707 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12708 case X86::PCMPESTRM128REG: 12709 case X86::VPCMPESTRM128REG: 12710 return EmitPCMP(MI, BB, 5, false /* in mem */); 12711 case X86::PCMPESTRM128MEM: 12712 case X86::VPCMPESTRM128MEM: 12713 return EmitPCMP(MI, BB, 5, true /* in mem */); 12714 12715 // Thread synchronization. 12716 case X86::MONITOR: 12717 return EmitMonitor(MI, BB); 12718 case X86::MWAIT: 12719 return EmitMwait(MI, BB); 12720 12721 // Atomic Lowering. 12722 case X86::ATOMAND32: 12723 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12724 X86::AND32ri, X86::MOV32rm, 12725 X86::LCMPXCHG32, 12726 X86::NOT32r, X86::EAX, 12727 &X86::GR32RegClass); 12728 case X86::ATOMOR32: 12729 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12730 X86::OR32ri, X86::MOV32rm, 12731 X86::LCMPXCHG32, 12732 X86::NOT32r, X86::EAX, 12733 &X86::GR32RegClass); 12734 case X86::ATOMXOR32: 12735 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12736 X86::XOR32ri, X86::MOV32rm, 12737 X86::LCMPXCHG32, 12738 X86::NOT32r, X86::EAX, 12739 &X86::GR32RegClass); 12740 case X86::ATOMNAND32: 12741 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12742 X86::AND32ri, X86::MOV32rm, 12743 X86::LCMPXCHG32, 12744 X86::NOT32r, X86::EAX, 12745 &X86::GR32RegClass, true); 12746 case X86::ATOMMIN32: 12747 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12748 case X86::ATOMMAX32: 12749 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12750 case X86::ATOMUMIN32: 12751 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12752 case X86::ATOMUMAX32: 12753 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12754 12755 case X86::ATOMAND16: 12756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12757 X86::AND16ri, X86::MOV16rm, 12758 X86::LCMPXCHG16, 12759 X86::NOT16r, X86::AX, 12760 &X86::GR16RegClass); 12761 case X86::ATOMOR16: 12762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12763 X86::OR16ri, X86::MOV16rm, 12764 X86::LCMPXCHG16, 12765 X86::NOT16r, X86::AX, 12766 &X86::GR16RegClass); 12767 case X86::ATOMXOR16: 12768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12769 X86::XOR16ri, X86::MOV16rm, 12770 X86::LCMPXCHG16, 12771 X86::NOT16r, X86::AX, 12772 &X86::GR16RegClass); 12773 case X86::ATOMNAND16: 12774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12775 X86::AND16ri, X86::MOV16rm, 12776 X86::LCMPXCHG16, 12777 X86::NOT16r, X86::AX, 12778 &X86::GR16RegClass, true); 12779 case X86::ATOMMIN16: 12780 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12781 case X86::ATOMMAX16: 12782 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12783 case X86::ATOMUMIN16: 12784 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12785 case X86::ATOMUMAX16: 12786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12787 12788 case X86::ATOMAND8: 12789 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12790 X86::AND8ri, X86::MOV8rm, 12791 X86::LCMPXCHG8, 12792 X86::NOT8r, X86::AL, 12793 &X86::GR8RegClass); 12794 case X86::ATOMOR8: 12795 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12796 X86::OR8ri, X86::MOV8rm, 12797 X86::LCMPXCHG8, 12798 X86::NOT8r, X86::AL, 12799 &X86::GR8RegClass); 12800 case X86::ATOMXOR8: 12801 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12802 X86::XOR8ri, X86::MOV8rm, 12803 X86::LCMPXCHG8, 12804 X86::NOT8r, X86::AL, 12805 &X86::GR8RegClass); 12806 case X86::ATOMNAND8: 12807 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12808 X86::AND8ri, X86::MOV8rm, 12809 X86::LCMPXCHG8, 12810 X86::NOT8r, X86::AL, 12811 &X86::GR8RegClass, true); 12812 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12813 // This group is for 64-bit host. 12814 case X86::ATOMAND64: 12815 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12816 X86::AND64ri32, X86::MOV64rm, 12817 X86::LCMPXCHG64, 12818 X86::NOT64r, X86::RAX, 12819 &X86::GR64RegClass); 12820 case X86::ATOMOR64: 12821 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12822 X86::OR64ri32, X86::MOV64rm, 12823 X86::LCMPXCHG64, 12824 X86::NOT64r, X86::RAX, 12825 &X86::GR64RegClass); 12826 case X86::ATOMXOR64: 12827 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12828 X86::XOR64ri32, X86::MOV64rm, 12829 X86::LCMPXCHG64, 12830 X86::NOT64r, X86::RAX, 12831 &X86::GR64RegClass); 12832 case X86::ATOMNAND64: 12833 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12834 X86::AND64ri32, X86::MOV64rm, 12835 X86::LCMPXCHG64, 12836 X86::NOT64r, X86::RAX, 12837 &X86::GR64RegClass, true); 12838 case X86::ATOMMIN64: 12839 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12840 case X86::ATOMMAX64: 12841 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12842 case X86::ATOMUMIN64: 12843 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12844 case X86::ATOMUMAX64: 12845 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12846 12847 // This group does 64-bit operations on a 32-bit host. 12848 case X86::ATOMAND6432: 12849 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12850 X86::AND32rr, X86::AND32rr, 12851 X86::AND32ri, X86::AND32ri, 12852 false); 12853 case X86::ATOMOR6432: 12854 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12855 X86::OR32rr, X86::OR32rr, 12856 X86::OR32ri, X86::OR32ri, 12857 false); 12858 case X86::ATOMXOR6432: 12859 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12860 X86::XOR32rr, X86::XOR32rr, 12861 X86::XOR32ri, X86::XOR32ri, 12862 false); 12863 case X86::ATOMNAND6432: 12864 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12865 X86::AND32rr, X86::AND32rr, 12866 X86::AND32ri, X86::AND32ri, 12867 true); 12868 case X86::ATOMADD6432: 12869 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12870 X86::ADD32rr, X86::ADC32rr, 12871 X86::ADD32ri, X86::ADC32ri, 12872 false); 12873 case X86::ATOMSUB6432: 12874 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12875 X86::SUB32rr, X86::SBB32rr, 12876 X86::SUB32ri, X86::SBB32ri, 12877 false); 12878 case X86::ATOMSWAP6432: 12879 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12880 X86::MOV32rr, X86::MOV32rr, 12881 X86::MOV32ri, X86::MOV32ri, 12882 false); 12883 case X86::VASTART_SAVE_XMM_REGS: 12884 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12885 12886 case X86::VAARG_64: 12887 return EmitVAARG64WithCustomInserter(MI, BB); 12888 } 12889} 12890 12891//===----------------------------------------------------------------------===// 12892// X86 Optimization Hooks 12893//===----------------------------------------------------------------------===// 12894 12895void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12896 APInt &KnownZero, 12897 APInt &KnownOne, 12898 const SelectionDAG &DAG, 12899 unsigned Depth) const { 12900 unsigned BitWidth = KnownZero.getBitWidth(); 12901 unsigned Opc = Op.getOpcode(); 12902 assert((Opc >= ISD::BUILTIN_OP_END || 12903 Opc == ISD::INTRINSIC_WO_CHAIN || 12904 Opc == ISD::INTRINSIC_W_CHAIN || 12905 Opc == ISD::INTRINSIC_VOID) && 12906 "Should use MaskedValueIsZero if you don't know whether Op" 12907 " is a target node!"); 12908 12909 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12910 switch (Opc) { 12911 default: break; 12912 case X86ISD::ADD: 12913 case X86ISD::SUB: 12914 case X86ISD::ADC: 12915 case X86ISD::SBB: 12916 case X86ISD::SMUL: 12917 case X86ISD::UMUL: 12918 case X86ISD::INC: 12919 case X86ISD::DEC: 12920 case X86ISD::OR: 12921 case X86ISD::XOR: 12922 case X86ISD::AND: 12923 // These nodes' second result is a boolean. 12924 if (Op.getResNo() == 0) 12925 break; 12926 // Fallthrough 12927 case X86ISD::SETCC: 12928 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12929 break; 12930 case ISD::INTRINSIC_WO_CHAIN: { 12931 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12932 unsigned NumLoBits = 0; 12933 switch (IntId) { 12934 default: break; 12935 case Intrinsic::x86_sse_movmsk_ps: 12936 case Intrinsic::x86_avx_movmsk_ps_256: 12937 case Intrinsic::x86_sse2_movmsk_pd: 12938 case Intrinsic::x86_avx_movmsk_pd_256: 12939 case Intrinsic::x86_mmx_pmovmskb: 12940 case Intrinsic::x86_sse2_pmovmskb_128: 12941 case Intrinsic::x86_avx2_pmovmskb: { 12942 // High bits of movmskp{s|d}, pmovmskb are known zero. 12943 switch (IntId) { 12944 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12945 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12946 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12947 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12948 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12949 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12950 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12951 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12952 } 12953 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12954 break; 12955 } 12956 } 12957 break; 12958 } 12959 } 12960} 12961 12962unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12963 unsigned Depth) const { 12964 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12965 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12966 return Op.getValueType().getScalarType().getSizeInBits(); 12967 12968 // Fallback case. 12969 return 1; 12970} 12971 12972/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12973/// node is a GlobalAddress + offset. 12974bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12975 const GlobalValue* &GA, 12976 int64_t &Offset) const { 12977 if (N->getOpcode() == X86ISD::Wrapper) { 12978 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12979 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12980 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12981 return true; 12982 } 12983 } 12984 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12985} 12986 12987/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12988/// same as extracting the high 128-bit part of 256-bit vector and then 12989/// inserting the result into the low part of a new 256-bit vector 12990static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12991 EVT VT = SVOp->getValueType(0); 12992 unsigned NumElems = VT.getVectorNumElements(); 12993 12994 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12995 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 12996 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12997 SVOp->getMaskElt(j) >= 0) 12998 return false; 12999 13000 return true; 13001} 13002 13003/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 13004/// same as extracting the low 128-bit part of 256-bit vector and then 13005/// inserting the result into the high part of a new 256-bit vector 13006static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 13007 EVT VT = SVOp->getValueType(0); 13008 unsigned NumElems = VT.getVectorNumElements(); 13009 13010 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13011 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 13012 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 13013 SVOp->getMaskElt(j) >= 0) 13014 return false; 13015 13016 return true; 13017} 13018 13019/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 13020static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 13021 TargetLowering::DAGCombinerInfo &DCI, 13022 const X86Subtarget* Subtarget) { 13023 DebugLoc dl = N->getDebugLoc(); 13024 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 13025 SDValue V1 = SVOp->getOperand(0); 13026 SDValue V2 = SVOp->getOperand(1); 13027 EVT VT = SVOp->getValueType(0); 13028 unsigned NumElems = VT.getVectorNumElements(); 13029 13030 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 13031 V2.getOpcode() == ISD::CONCAT_VECTORS) { 13032 // 13033 // 0,0,0,... 13034 // | 13035 // V UNDEF BUILD_VECTOR UNDEF 13036 // \ / \ / 13037 // CONCAT_VECTOR CONCAT_VECTOR 13038 // \ / 13039 // \ / 13040 // RESULT: V + zero extended 13041 // 13042 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 13043 V2.getOperand(1).getOpcode() != ISD::UNDEF || 13044 V1.getOperand(1).getOpcode() != ISD::UNDEF) 13045 return SDValue(); 13046 13047 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 13048 return SDValue(); 13049 13050 // To match the shuffle mask, the first half of the mask should 13051 // be exactly the first vector, and all the rest a splat with the 13052 // first element of the second one. 13053 for (unsigned i = 0; i != NumElems/2; ++i) 13054 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 13055 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 13056 return SDValue(); 13057 13058 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 13059 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 13060 if (Ld->hasNUsesOfValue(1, 0)) { 13061 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 13062 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 13063 SDValue ResNode = 13064 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 13065 Ld->getMemoryVT(), 13066 Ld->getPointerInfo(), 13067 Ld->getAlignment(), 13068 false/*isVolatile*/, true/*ReadMem*/, 13069 false/*WriteMem*/); 13070 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 13071 } 13072 } 13073 13074 // Emit a zeroed vector and insert the desired subvector on its 13075 // first half. 13076 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 13077 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 13078 return DCI.CombineTo(N, InsV); 13079 } 13080 13081 //===--------------------------------------------------------------------===// 13082 // Combine some shuffles into subvector extracts and inserts: 13083 // 13084 13085 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 13086 if (isShuffleHigh128VectorInsertLow(SVOp)) { 13087 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 13088 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 13089 return DCI.CombineTo(N, InsV); 13090 } 13091 13092 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 13093 if (isShuffleLow128VectorInsertHigh(SVOp)) { 13094 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 13095 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 13096 return DCI.CombineTo(N, InsV); 13097 } 13098 13099 return SDValue(); 13100} 13101 13102/// PerformShuffleCombine - Performs several different shuffle combines. 13103static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 13104 TargetLowering::DAGCombinerInfo &DCI, 13105 const X86Subtarget *Subtarget) { 13106 DebugLoc dl = N->getDebugLoc(); 13107 EVT VT = N->getValueType(0); 13108 13109 // Don't create instructions with illegal types after legalize types has run. 13110 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13111 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13112 return SDValue(); 13113 13114 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13115 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 13116 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13117 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 13118 13119 // Only handle 128 wide vector from here on. 13120 if (VT.getSizeInBits() != 128) 13121 return SDValue(); 13122 13123 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13124 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13125 // consecutive, non-overlapping, and in the right order. 13126 SmallVector<SDValue, 16> Elts; 13127 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13128 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13129 13130 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13131} 13132 13133 13134/// DCI, PerformTruncateCombine - Converts truncate operation to 13135/// a sequence of vector shuffle operations. 13136/// It is possible when we truncate 256-bit vector to 128-bit vector 13137 13138SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 13139 DAGCombinerInfo &DCI) const { 13140 if (!DCI.isBeforeLegalizeOps()) 13141 return SDValue(); 13142 13143 if (!Subtarget->hasAVX()) 13144 return SDValue(); 13145 13146 EVT VT = N->getValueType(0); 13147 SDValue Op = N->getOperand(0); 13148 EVT OpVT = Op.getValueType(); 13149 DebugLoc dl = N->getDebugLoc(); 13150 13151 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 13152 13153 if (Subtarget->hasAVX2()) { 13154 // AVX2: v4i64 -> v4i32 13155 13156 // VPERMD 13157 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 13158 13159 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op); 13160 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32), 13161 ShufMask); 13162 13163 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, 13164 DAG.getIntPtrConstant(0)); 13165 } 13166 13167 // AVX: v4i64 -> v4i32 13168 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13169 DAG.getIntPtrConstant(0)); 13170 13171 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13172 DAG.getIntPtrConstant(2)); 13173 13174 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13175 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13176 13177 // PSHUFD 13178 static const int ShufMask1[] = {0, 2, 0, 0}; 13179 13180 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1); 13181 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1); 13182 13183 // MOVLHPS 13184 static const int ShufMask2[] = {0, 1, 4, 5}; 13185 13186 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 13187 } 13188 13189 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 13190 13191 if (Subtarget->hasAVX2()) { 13192 // AVX2: v8i32 -> v8i16 13193 13194 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op); 13195 13196 // PSHUFB 13197 SmallVector<SDValue,32> pshufbMask; 13198 for (unsigned i = 0; i < 2; ++i) { 13199 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 13200 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 13201 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 13202 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 13203 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 13204 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 13205 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 13206 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 13207 for (unsigned j = 0; j < 8; ++j) 13208 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 13209 } 13210 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, 13211 &pshufbMask[0], 32); 13212 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV); 13213 13214 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op); 13215 13216 static const int ShufMask[] = {0, 2, -1, -1}; 13217 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64), 13218 &ShufMask[0]); 13219 13220 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13221 DAG.getIntPtrConstant(0)); 13222 13223 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 13224 } 13225 13226 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13227 DAG.getIntPtrConstant(0)); 13228 13229 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13230 DAG.getIntPtrConstant(4)); 13231 13232 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13233 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13234 13235 // PSHUFB 13236 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13237 -1, -1, -1, -1, -1, -1, -1, -1}; 13238 13239 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8), 13240 ShufMask1); 13241 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8), 13242 ShufMask1); 13243 13244 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13245 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13246 13247 // MOVLHPS 13248 static const int ShufMask2[] = {0, 1, 4, 5}; 13249 13250 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13251 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13252 } 13253 13254 return SDValue(); 13255} 13256 13257/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13258/// specific shuffle of a load can be folded into a single element load. 13259/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13260/// shuffles have been customed lowered so we need to handle those here. 13261static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13262 TargetLowering::DAGCombinerInfo &DCI) { 13263 if (DCI.isBeforeLegalizeOps()) 13264 return SDValue(); 13265 13266 SDValue InVec = N->getOperand(0); 13267 SDValue EltNo = N->getOperand(1); 13268 13269 if (!isa<ConstantSDNode>(EltNo)) 13270 return SDValue(); 13271 13272 EVT VT = InVec.getValueType(); 13273 13274 bool HasShuffleIntoBitcast = false; 13275 if (InVec.getOpcode() == ISD::BITCAST) { 13276 // Don't duplicate a load with other uses. 13277 if (!InVec.hasOneUse()) 13278 return SDValue(); 13279 EVT BCVT = InVec.getOperand(0).getValueType(); 13280 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13281 return SDValue(); 13282 InVec = InVec.getOperand(0); 13283 HasShuffleIntoBitcast = true; 13284 } 13285 13286 if (!isTargetShuffle(InVec.getOpcode())) 13287 return SDValue(); 13288 13289 // Don't duplicate a load with other uses. 13290 if (!InVec.hasOneUse()) 13291 return SDValue(); 13292 13293 SmallVector<int, 16> ShuffleMask; 13294 bool UnaryShuffle; 13295 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask, 13296 UnaryShuffle)) 13297 return SDValue(); 13298 13299 // Select the input vector, guarding against out of range extract vector. 13300 unsigned NumElems = VT.getVectorNumElements(); 13301 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13302 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13303 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13304 : InVec.getOperand(1); 13305 13306 // If inputs to shuffle are the same for both ops, then allow 2 uses 13307 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13308 13309 if (LdNode.getOpcode() == ISD::BITCAST) { 13310 // Don't duplicate a load with other uses. 13311 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13312 return SDValue(); 13313 13314 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13315 LdNode = LdNode.getOperand(0); 13316 } 13317 13318 if (!ISD::isNormalLoad(LdNode.getNode())) 13319 return SDValue(); 13320 13321 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13322 13323 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13324 return SDValue(); 13325 13326 if (HasShuffleIntoBitcast) { 13327 // If there's a bitcast before the shuffle, check if the load type and 13328 // alignment is valid. 13329 unsigned Align = LN0->getAlignment(); 13330 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13331 unsigned NewAlign = TLI.getTargetData()-> 13332 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13333 13334 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13335 return SDValue(); 13336 } 13337 13338 // All checks match so transform back to vector_shuffle so that DAG combiner 13339 // can finish the job 13340 DebugLoc dl = N->getDebugLoc(); 13341 13342 // Create shuffle node taking into account the case that its a unary shuffle 13343 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13344 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13345 InVec.getOperand(0), Shuffle, 13346 &ShuffleMask[0]); 13347 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13348 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13349 EltNo); 13350} 13351 13352/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13353/// generation and convert it from being a bunch of shuffles and extracts 13354/// to a simple store and scalar loads to extract the elements. 13355static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13356 TargetLowering::DAGCombinerInfo &DCI) { 13357 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13358 if (NewOp.getNode()) 13359 return NewOp; 13360 13361 SDValue InputVector = N->getOperand(0); 13362 13363 // Only operate on vectors of 4 elements, where the alternative shuffling 13364 // gets to be more expensive. 13365 if (InputVector.getValueType() != MVT::v4i32) 13366 return SDValue(); 13367 13368 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13369 // single use which is a sign-extend or zero-extend, and all elements are 13370 // used. 13371 SmallVector<SDNode *, 4> Uses; 13372 unsigned ExtractedElements = 0; 13373 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13374 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13375 if (UI.getUse().getResNo() != InputVector.getResNo()) 13376 return SDValue(); 13377 13378 SDNode *Extract = *UI; 13379 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13380 return SDValue(); 13381 13382 if (Extract->getValueType(0) != MVT::i32) 13383 return SDValue(); 13384 if (!Extract->hasOneUse()) 13385 return SDValue(); 13386 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13387 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13388 return SDValue(); 13389 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13390 return SDValue(); 13391 13392 // Record which element was extracted. 13393 ExtractedElements |= 13394 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13395 13396 Uses.push_back(Extract); 13397 } 13398 13399 // If not all the elements were used, this may not be worthwhile. 13400 if (ExtractedElements != 15) 13401 return SDValue(); 13402 13403 // Ok, we've now decided to do the transformation. 13404 DebugLoc dl = InputVector.getDebugLoc(); 13405 13406 // Store the value to a temporary stack slot. 13407 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13408 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13409 MachinePointerInfo(), false, false, 0); 13410 13411 // Replace each use (extract) with a load of the appropriate element. 13412 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13413 UE = Uses.end(); UI != UE; ++UI) { 13414 SDNode *Extract = *UI; 13415 13416 // cOMpute the element's address. 13417 SDValue Idx = Extract->getOperand(1); 13418 unsigned EltSize = 13419 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13420 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13421 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13422 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13423 13424 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13425 StackPtr, OffsetVal); 13426 13427 // Load the scalar. 13428 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13429 ScalarAddr, MachinePointerInfo(), 13430 false, false, false, 0); 13431 13432 // Replace the exact with the load. 13433 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13434 } 13435 13436 // The replacement was made in place; don't return anything. 13437 return SDValue(); 13438} 13439 13440/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13441/// nodes. 13442static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13443 TargetLowering::DAGCombinerInfo &DCI, 13444 const X86Subtarget *Subtarget) { 13445 13446 13447 DebugLoc DL = N->getDebugLoc(); 13448 SDValue Cond = N->getOperand(0); 13449 // Get the LHS/RHS of the select. 13450 SDValue LHS = N->getOperand(1); 13451 SDValue RHS = N->getOperand(2); 13452 EVT VT = LHS.getValueType(); 13453 13454 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13455 // instructions match the semantics of the common C idiom x<y?x:y but not 13456 // x<=y?x:y, because of how they handle negative zero (which can be 13457 // ignored in unsafe-math mode). 13458 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13459 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13460 (Subtarget->hasSSE2() || 13461 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13462 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13463 13464 unsigned Opcode = 0; 13465 // Check for x CC y ? x : y. 13466 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13467 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13468 switch (CC) { 13469 default: break; 13470 case ISD::SETULT: 13471 // Converting this to a min would handle NaNs incorrectly, and swapping 13472 // the operands would cause it to handle comparisons between positive 13473 // and negative zero incorrectly. 13474 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13475 if (!DAG.getTarget().Options.UnsafeFPMath && 13476 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13477 break; 13478 std::swap(LHS, RHS); 13479 } 13480 Opcode = X86ISD::FMIN; 13481 break; 13482 case ISD::SETOLE: 13483 // Converting this to a min would handle comparisons between positive 13484 // and negative zero incorrectly. 13485 if (!DAG.getTarget().Options.UnsafeFPMath && 13486 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13487 break; 13488 Opcode = X86ISD::FMIN; 13489 break; 13490 case ISD::SETULE: 13491 // Converting this to a min would handle both negative zeros and NaNs 13492 // incorrectly, but we can swap the operands to fix both. 13493 std::swap(LHS, RHS); 13494 case ISD::SETOLT: 13495 case ISD::SETLT: 13496 case ISD::SETLE: 13497 Opcode = X86ISD::FMIN; 13498 break; 13499 13500 case ISD::SETOGE: 13501 // Converting this to a max would handle comparisons between positive 13502 // and negative zero incorrectly. 13503 if (!DAG.getTarget().Options.UnsafeFPMath && 13504 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13505 break; 13506 Opcode = X86ISD::FMAX; 13507 break; 13508 case ISD::SETUGT: 13509 // Converting this to a max would handle NaNs incorrectly, and swapping 13510 // the operands would cause it to handle comparisons between positive 13511 // and negative zero incorrectly. 13512 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13513 if (!DAG.getTarget().Options.UnsafeFPMath && 13514 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13515 break; 13516 std::swap(LHS, RHS); 13517 } 13518 Opcode = X86ISD::FMAX; 13519 break; 13520 case ISD::SETUGE: 13521 // Converting this to a max would handle both negative zeros and NaNs 13522 // incorrectly, but we can swap the operands to fix both. 13523 std::swap(LHS, RHS); 13524 case ISD::SETOGT: 13525 case ISD::SETGT: 13526 case ISD::SETGE: 13527 Opcode = X86ISD::FMAX; 13528 break; 13529 } 13530 // Check for x CC y ? y : x -- a min/max with reversed arms. 13531 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13532 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13533 switch (CC) { 13534 default: break; 13535 case ISD::SETOGE: 13536 // Converting this to a min would handle comparisons between positive 13537 // and negative zero incorrectly, and swapping the operands would 13538 // cause it to handle NaNs incorrectly. 13539 if (!DAG.getTarget().Options.UnsafeFPMath && 13540 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13541 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13542 break; 13543 std::swap(LHS, RHS); 13544 } 13545 Opcode = X86ISD::FMIN; 13546 break; 13547 case ISD::SETUGT: 13548 // Converting this to a min would handle NaNs incorrectly. 13549 if (!DAG.getTarget().Options.UnsafeFPMath && 13550 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13551 break; 13552 Opcode = X86ISD::FMIN; 13553 break; 13554 case ISD::SETUGE: 13555 // Converting this to a min would handle both negative zeros and NaNs 13556 // incorrectly, but we can swap the operands to fix both. 13557 std::swap(LHS, RHS); 13558 case ISD::SETOGT: 13559 case ISD::SETGT: 13560 case ISD::SETGE: 13561 Opcode = X86ISD::FMIN; 13562 break; 13563 13564 case ISD::SETULT: 13565 // Converting this to a max would handle NaNs incorrectly. 13566 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13567 break; 13568 Opcode = X86ISD::FMAX; 13569 break; 13570 case ISD::SETOLE: 13571 // Converting this to a max would handle comparisons between positive 13572 // and negative zero incorrectly, and swapping the operands would 13573 // cause it to handle NaNs incorrectly. 13574 if (!DAG.getTarget().Options.UnsafeFPMath && 13575 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13576 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13577 break; 13578 std::swap(LHS, RHS); 13579 } 13580 Opcode = X86ISD::FMAX; 13581 break; 13582 case ISD::SETULE: 13583 // Converting this to a max would handle both negative zeros and NaNs 13584 // incorrectly, but we can swap the operands to fix both. 13585 std::swap(LHS, RHS); 13586 case ISD::SETOLT: 13587 case ISD::SETLT: 13588 case ISD::SETLE: 13589 Opcode = X86ISD::FMAX; 13590 break; 13591 } 13592 } 13593 13594 if (Opcode) 13595 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13596 } 13597 13598 // If this is a select between two integer constants, try to do some 13599 // optimizations. 13600 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13601 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13602 // Don't do this for crazy integer types. 13603 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13604 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13605 // so that TrueC (the true value) is larger than FalseC. 13606 bool NeedsCondInvert = false; 13607 13608 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13609 // Efficiently invertible. 13610 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13611 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13612 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13613 NeedsCondInvert = true; 13614 std::swap(TrueC, FalseC); 13615 } 13616 13617 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13618 if (FalseC->getAPIntValue() == 0 && 13619 TrueC->getAPIntValue().isPowerOf2()) { 13620 if (NeedsCondInvert) // Invert the condition if needed. 13621 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13622 DAG.getConstant(1, Cond.getValueType())); 13623 13624 // Zero extend the condition if needed. 13625 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13626 13627 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13628 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13629 DAG.getConstant(ShAmt, MVT::i8)); 13630 } 13631 13632 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13633 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13634 if (NeedsCondInvert) // Invert the condition if needed. 13635 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13636 DAG.getConstant(1, Cond.getValueType())); 13637 13638 // Zero extend the condition if needed. 13639 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13640 FalseC->getValueType(0), Cond); 13641 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13642 SDValue(FalseC, 0)); 13643 } 13644 13645 // Optimize cases that will turn into an LEA instruction. This requires 13646 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13647 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13648 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13649 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13650 13651 bool isFastMultiplier = false; 13652 if (Diff < 10) { 13653 switch ((unsigned char)Diff) { 13654 default: break; 13655 case 1: // result = add base, cond 13656 case 2: // result = lea base( , cond*2) 13657 case 3: // result = lea base(cond, cond*2) 13658 case 4: // result = lea base( , cond*4) 13659 case 5: // result = lea base(cond, cond*4) 13660 case 8: // result = lea base( , cond*8) 13661 case 9: // result = lea base(cond, cond*8) 13662 isFastMultiplier = true; 13663 break; 13664 } 13665 } 13666 13667 if (isFastMultiplier) { 13668 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13669 if (NeedsCondInvert) // Invert the condition if needed. 13670 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13671 DAG.getConstant(1, Cond.getValueType())); 13672 13673 // Zero extend the condition if needed. 13674 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13675 Cond); 13676 // Scale the condition by the difference. 13677 if (Diff != 1) 13678 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13679 DAG.getConstant(Diff, Cond.getValueType())); 13680 13681 // Add the base if non-zero. 13682 if (FalseC->getAPIntValue() != 0) 13683 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13684 SDValue(FalseC, 0)); 13685 return Cond; 13686 } 13687 } 13688 } 13689 } 13690 13691 // Canonicalize max and min: 13692 // (x > y) ? x : y -> (x >= y) ? x : y 13693 // (x < y) ? x : y -> (x <= y) ? x : y 13694 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13695 // the need for an extra compare 13696 // against zero. e.g. 13697 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13698 // subl %esi, %edi 13699 // testl %edi, %edi 13700 // movl $0, %eax 13701 // cmovgl %edi, %eax 13702 // => 13703 // xorl %eax, %eax 13704 // subl %esi, $edi 13705 // cmovsl %eax, %edi 13706 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13707 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13708 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13709 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13710 switch (CC) { 13711 default: break; 13712 case ISD::SETLT: 13713 case ISD::SETGT: { 13714 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13715 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13716 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13717 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13718 } 13719 } 13720 } 13721 13722 // If we know that this node is legal then we know that it is going to be 13723 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13724 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13725 // to simplify previous instructions. 13726 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13727 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13728 !DCI.isBeforeLegalize() && 13729 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13730 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13731 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13732 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13733 13734 APInt KnownZero, KnownOne; 13735 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13736 DCI.isBeforeLegalizeOps()); 13737 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13738 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13739 DCI.CommitTargetLoweringOpt(TLO); 13740 } 13741 13742 return SDValue(); 13743} 13744 13745/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13746static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13747 TargetLowering::DAGCombinerInfo &DCI) { 13748 DebugLoc DL = N->getDebugLoc(); 13749 13750 // If the flag operand isn't dead, don't touch this CMOV. 13751 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13752 return SDValue(); 13753 13754 SDValue FalseOp = N->getOperand(0); 13755 SDValue TrueOp = N->getOperand(1); 13756 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13757 SDValue Cond = N->getOperand(3); 13758 if (CC == X86::COND_E || CC == X86::COND_NE) { 13759 switch (Cond.getOpcode()) { 13760 default: break; 13761 case X86ISD::BSR: 13762 case X86ISD::BSF: 13763 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13764 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13765 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13766 } 13767 } 13768 13769 // If this is a select between two integer constants, try to do some 13770 // optimizations. Note that the operands are ordered the opposite of SELECT 13771 // operands. 13772 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13773 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13774 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13775 // larger than FalseC (the false value). 13776 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13777 CC = X86::GetOppositeBranchCondition(CC); 13778 std::swap(TrueC, FalseC); 13779 } 13780 13781 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13782 // This is efficient for any integer data type (including i8/i16) and 13783 // shift amount. 13784 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13785 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13786 DAG.getConstant(CC, MVT::i8), Cond); 13787 13788 // Zero extend the condition if needed. 13789 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13790 13791 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13792 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13793 DAG.getConstant(ShAmt, MVT::i8)); 13794 if (N->getNumValues() == 2) // Dead flag value? 13795 return DCI.CombineTo(N, Cond, SDValue()); 13796 return Cond; 13797 } 13798 13799 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13800 // for any integer data type, including i8/i16. 13801 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13802 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13803 DAG.getConstant(CC, MVT::i8), Cond); 13804 13805 // Zero extend the condition if needed. 13806 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13807 FalseC->getValueType(0), Cond); 13808 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13809 SDValue(FalseC, 0)); 13810 13811 if (N->getNumValues() == 2) // Dead flag value? 13812 return DCI.CombineTo(N, Cond, SDValue()); 13813 return Cond; 13814 } 13815 13816 // Optimize cases that will turn into an LEA instruction. This requires 13817 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13818 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13819 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13820 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13821 13822 bool isFastMultiplier = false; 13823 if (Diff < 10) { 13824 switch ((unsigned char)Diff) { 13825 default: break; 13826 case 1: // result = add base, cond 13827 case 2: // result = lea base( , cond*2) 13828 case 3: // result = lea base(cond, cond*2) 13829 case 4: // result = lea base( , cond*4) 13830 case 5: // result = lea base(cond, cond*4) 13831 case 8: // result = lea base( , cond*8) 13832 case 9: // result = lea base(cond, cond*8) 13833 isFastMultiplier = true; 13834 break; 13835 } 13836 } 13837 13838 if (isFastMultiplier) { 13839 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13840 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13841 DAG.getConstant(CC, MVT::i8), Cond); 13842 // Zero extend the condition if needed. 13843 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13844 Cond); 13845 // Scale the condition by the difference. 13846 if (Diff != 1) 13847 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13848 DAG.getConstant(Diff, Cond.getValueType())); 13849 13850 // Add the base if non-zero. 13851 if (FalseC->getAPIntValue() != 0) 13852 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13853 SDValue(FalseC, 0)); 13854 if (N->getNumValues() == 2) // Dead flag value? 13855 return DCI.CombineTo(N, Cond, SDValue()); 13856 return Cond; 13857 } 13858 } 13859 } 13860 } 13861 return SDValue(); 13862} 13863 13864 13865/// PerformMulCombine - Optimize a single multiply with constant into two 13866/// in order to implement it with two cheaper instructions, e.g. 13867/// LEA + SHL, LEA + LEA. 13868static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13869 TargetLowering::DAGCombinerInfo &DCI) { 13870 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13871 return SDValue(); 13872 13873 EVT VT = N->getValueType(0); 13874 if (VT != MVT::i64) 13875 return SDValue(); 13876 13877 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13878 if (!C) 13879 return SDValue(); 13880 uint64_t MulAmt = C->getZExtValue(); 13881 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13882 return SDValue(); 13883 13884 uint64_t MulAmt1 = 0; 13885 uint64_t MulAmt2 = 0; 13886 if ((MulAmt % 9) == 0) { 13887 MulAmt1 = 9; 13888 MulAmt2 = MulAmt / 9; 13889 } else if ((MulAmt % 5) == 0) { 13890 MulAmt1 = 5; 13891 MulAmt2 = MulAmt / 5; 13892 } else if ((MulAmt % 3) == 0) { 13893 MulAmt1 = 3; 13894 MulAmt2 = MulAmt / 3; 13895 } 13896 if (MulAmt2 && 13897 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13898 DebugLoc DL = N->getDebugLoc(); 13899 13900 if (isPowerOf2_64(MulAmt2) && 13901 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13902 // If second multiplifer is pow2, issue it first. We want the multiply by 13903 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13904 // is an add. 13905 std::swap(MulAmt1, MulAmt2); 13906 13907 SDValue NewMul; 13908 if (isPowerOf2_64(MulAmt1)) 13909 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13910 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13911 else 13912 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13913 DAG.getConstant(MulAmt1, VT)); 13914 13915 if (isPowerOf2_64(MulAmt2)) 13916 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13917 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13918 else 13919 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13920 DAG.getConstant(MulAmt2, VT)); 13921 13922 // Do not add new nodes to DAG combiner worklist. 13923 DCI.CombineTo(N, NewMul, false); 13924 } 13925 return SDValue(); 13926} 13927 13928static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13929 SDValue N0 = N->getOperand(0); 13930 SDValue N1 = N->getOperand(1); 13931 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13932 EVT VT = N0.getValueType(); 13933 13934 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13935 // since the result of setcc_c is all zero's or all ones. 13936 if (VT.isInteger() && !VT.isVector() && 13937 N1C && N0.getOpcode() == ISD::AND && 13938 N0.getOperand(1).getOpcode() == ISD::Constant) { 13939 SDValue N00 = N0.getOperand(0); 13940 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13941 ((N00.getOpcode() == ISD::ANY_EXTEND || 13942 N00.getOpcode() == ISD::ZERO_EXTEND) && 13943 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13944 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13945 APInt ShAmt = N1C->getAPIntValue(); 13946 Mask = Mask.shl(ShAmt); 13947 if (Mask != 0) 13948 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13949 N00, DAG.getConstant(Mask, VT)); 13950 } 13951 } 13952 13953 13954 // Hardware support for vector shifts is sparse which makes us scalarize the 13955 // vector operations in many cases. Also, on sandybridge ADD is faster than 13956 // shl. 13957 // (shl V, 1) -> add V,V 13958 if (isSplatVector(N1.getNode())) { 13959 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13960 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13961 // We shift all of the values by one. In many cases we do not have 13962 // hardware support for this operation. This is better expressed as an ADD 13963 // of two values. 13964 if (N1C && (1 == N1C->getZExtValue())) { 13965 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13966 } 13967 } 13968 13969 return SDValue(); 13970} 13971 13972/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13973/// when possible. 13974static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13975 TargetLowering::DAGCombinerInfo &DCI, 13976 const X86Subtarget *Subtarget) { 13977 EVT VT = N->getValueType(0); 13978 if (N->getOpcode() == ISD::SHL) { 13979 SDValue V = PerformSHLCombine(N, DAG); 13980 if (V.getNode()) return V; 13981 } 13982 13983 // On X86 with SSE2 support, we can transform this to a vector shift if 13984 // all elements are shifted by the same amount. We can't do this in legalize 13985 // because the a constant vector is typically transformed to a constant pool 13986 // so we have no knowledge of the shift amount. 13987 if (!Subtarget->hasSSE2()) 13988 return SDValue(); 13989 13990 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13991 (!Subtarget->hasAVX2() || 13992 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13993 return SDValue(); 13994 13995 SDValue ShAmtOp = N->getOperand(1); 13996 EVT EltVT = VT.getVectorElementType(); 13997 DebugLoc DL = N->getDebugLoc(); 13998 SDValue BaseShAmt = SDValue(); 13999 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 14000 unsigned NumElts = VT.getVectorNumElements(); 14001 unsigned i = 0; 14002 for (; i != NumElts; ++i) { 14003 SDValue Arg = ShAmtOp.getOperand(i); 14004 if (Arg.getOpcode() == ISD::UNDEF) continue; 14005 BaseShAmt = Arg; 14006 break; 14007 } 14008 // Handle the case where the build_vector is all undef 14009 // FIXME: Should DAG allow this? 14010 if (i == NumElts) 14011 return SDValue(); 14012 14013 for (; i != NumElts; ++i) { 14014 SDValue Arg = ShAmtOp.getOperand(i); 14015 if (Arg.getOpcode() == ISD::UNDEF) continue; 14016 if (Arg != BaseShAmt) { 14017 return SDValue(); 14018 } 14019 } 14020 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 14021 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 14022 SDValue InVec = ShAmtOp.getOperand(0); 14023 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 14024 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 14025 unsigned i = 0; 14026 for (; i != NumElts; ++i) { 14027 SDValue Arg = InVec.getOperand(i); 14028 if (Arg.getOpcode() == ISD::UNDEF) continue; 14029 BaseShAmt = Arg; 14030 break; 14031 } 14032 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 14033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 14034 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 14035 if (C->getZExtValue() == SplatIdx) 14036 BaseShAmt = InVec.getOperand(1); 14037 } 14038 } 14039 if (BaseShAmt.getNode() == 0) { 14040 // Don't create instructions with illegal types after legalize 14041 // types has run. 14042 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 14043 !DCI.isBeforeLegalize()) 14044 return SDValue(); 14045 14046 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 14047 DAG.getIntPtrConstant(0)); 14048 } 14049 } else 14050 return SDValue(); 14051 14052 // The shift amount is an i32. 14053 if (EltVT.bitsGT(MVT::i32)) 14054 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 14055 else if (EltVT.bitsLT(MVT::i32)) 14056 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 14057 14058 // The shift amount is identical so we can do a vector shift. 14059 SDValue ValOp = N->getOperand(0); 14060 switch (N->getOpcode()) { 14061 default: 14062 llvm_unreachable("Unknown shift opcode!"); 14063 case ISD::SHL: 14064 switch (VT.getSimpleVT().SimpleTy) { 14065 default: return SDValue(); 14066 case MVT::v2i64: 14067 case MVT::v4i32: 14068 case MVT::v8i16: 14069 case MVT::v4i64: 14070 case MVT::v8i32: 14071 case MVT::v16i16: 14072 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 14073 } 14074 case ISD::SRA: 14075 switch (VT.getSimpleVT().SimpleTy) { 14076 default: return SDValue(); 14077 case MVT::v4i32: 14078 case MVT::v8i16: 14079 case MVT::v8i32: 14080 case MVT::v16i16: 14081 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 14082 } 14083 case ISD::SRL: 14084 switch (VT.getSimpleVT().SimpleTy) { 14085 default: return SDValue(); 14086 case MVT::v2i64: 14087 case MVT::v4i32: 14088 case MVT::v8i16: 14089 case MVT::v4i64: 14090 case MVT::v8i32: 14091 case MVT::v16i16: 14092 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 14093 } 14094 } 14095} 14096 14097 14098// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 14099// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 14100// and friends. Likewise for OR -> CMPNEQSS. 14101static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 14102 TargetLowering::DAGCombinerInfo &DCI, 14103 const X86Subtarget *Subtarget) { 14104 unsigned opcode; 14105 14106 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 14107 // we're requiring SSE2 for both. 14108 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 14109 SDValue N0 = N->getOperand(0); 14110 SDValue N1 = N->getOperand(1); 14111 SDValue CMP0 = N0->getOperand(1); 14112 SDValue CMP1 = N1->getOperand(1); 14113 DebugLoc DL = N->getDebugLoc(); 14114 14115 // The SETCCs should both refer to the same CMP. 14116 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 14117 return SDValue(); 14118 14119 SDValue CMP00 = CMP0->getOperand(0); 14120 SDValue CMP01 = CMP0->getOperand(1); 14121 EVT VT = CMP00.getValueType(); 14122 14123 if (VT == MVT::f32 || VT == MVT::f64) { 14124 bool ExpectingFlags = false; 14125 // Check for any users that want flags: 14126 for (SDNode::use_iterator UI = N->use_begin(), 14127 UE = N->use_end(); 14128 !ExpectingFlags && UI != UE; ++UI) 14129 switch (UI->getOpcode()) { 14130 default: 14131 case ISD::BR_CC: 14132 case ISD::BRCOND: 14133 case ISD::SELECT: 14134 ExpectingFlags = true; 14135 break; 14136 case ISD::CopyToReg: 14137 case ISD::SIGN_EXTEND: 14138 case ISD::ZERO_EXTEND: 14139 case ISD::ANY_EXTEND: 14140 break; 14141 } 14142 14143 if (!ExpectingFlags) { 14144 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 14145 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 14146 14147 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 14148 X86::CondCode tmp = cc0; 14149 cc0 = cc1; 14150 cc1 = tmp; 14151 } 14152 14153 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 14154 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 14155 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 14156 X86ISD::NodeType NTOperator = is64BitFP ? 14157 X86ISD::FSETCCsd : X86ISD::FSETCCss; 14158 // FIXME: need symbolic constants for these magic numbers. 14159 // See X86ATTInstPrinter.cpp:printSSECC(). 14160 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 14161 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 14162 DAG.getConstant(x86cc, MVT::i8)); 14163 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 14164 OnesOrZeroesF); 14165 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 14166 DAG.getConstant(1, MVT::i32)); 14167 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 14168 return OneBitOfTruth; 14169 } 14170 } 14171 } 14172 } 14173 return SDValue(); 14174} 14175 14176/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 14177/// so it can be folded inside ANDNP. 14178static bool CanFoldXORWithAllOnes(const SDNode *N) { 14179 EVT VT = N->getValueType(0); 14180 14181 // Match direct AllOnes for 128 and 256-bit vectors 14182 if (ISD::isBuildVectorAllOnes(N)) 14183 return true; 14184 14185 // Look through a bit convert. 14186 if (N->getOpcode() == ISD::BITCAST) 14187 N = N->getOperand(0).getNode(); 14188 14189 // Sometimes the operand may come from a insert_subvector building a 256-bit 14190 // allones vector 14191 if (VT.getSizeInBits() == 256 && 14192 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 14193 SDValue V1 = N->getOperand(0); 14194 SDValue V2 = N->getOperand(1); 14195 14196 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 14197 V1.getOperand(0).getOpcode() == ISD::UNDEF && 14198 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 14199 ISD::isBuildVectorAllOnes(V2.getNode())) 14200 return true; 14201 } 14202 14203 return false; 14204} 14205 14206static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 14207 TargetLowering::DAGCombinerInfo &DCI, 14208 const X86Subtarget *Subtarget) { 14209 if (DCI.isBeforeLegalizeOps()) 14210 return SDValue(); 14211 14212 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14213 if (R.getNode()) 14214 return R; 14215 14216 EVT VT = N->getValueType(0); 14217 14218 // Create ANDN, BLSI, and BLSR instructions 14219 // BLSI is X & (-X) 14220 // BLSR is X & (X-1) 14221 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 14222 SDValue N0 = N->getOperand(0); 14223 SDValue N1 = N->getOperand(1); 14224 DebugLoc DL = N->getDebugLoc(); 14225 14226 // Check LHS for not 14227 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 14228 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 14229 // Check RHS for not 14230 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 14231 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14232 14233 // Check LHS for neg 14234 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14235 isZero(N0.getOperand(0))) 14236 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14237 14238 // Check RHS for neg 14239 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14240 isZero(N1.getOperand(0))) 14241 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14242 14243 // Check LHS for X-1 14244 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14245 isAllOnes(N0.getOperand(1))) 14246 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14247 14248 // Check RHS for X-1 14249 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14250 isAllOnes(N1.getOperand(1))) 14251 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14252 14253 return SDValue(); 14254 } 14255 14256 // Want to form ANDNP nodes: 14257 // 1) In the hopes of then easily combining them with OR and AND nodes 14258 // to form PBLEND/PSIGN. 14259 // 2) To match ANDN packed intrinsics 14260 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14261 return SDValue(); 14262 14263 SDValue N0 = N->getOperand(0); 14264 SDValue N1 = N->getOperand(1); 14265 DebugLoc DL = N->getDebugLoc(); 14266 14267 // Check LHS for vnot 14268 if (N0.getOpcode() == ISD::XOR && 14269 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14270 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14271 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14272 14273 // Check RHS for vnot 14274 if (N1.getOpcode() == ISD::XOR && 14275 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14276 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14277 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14278 14279 return SDValue(); 14280} 14281 14282static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14283 TargetLowering::DAGCombinerInfo &DCI, 14284 const X86Subtarget *Subtarget) { 14285 if (DCI.isBeforeLegalizeOps()) 14286 return SDValue(); 14287 14288 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14289 if (R.getNode()) 14290 return R; 14291 14292 EVT VT = N->getValueType(0); 14293 14294 SDValue N0 = N->getOperand(0); 14295 SDValue N1 = N->getOperand(1); 14296 14297 // look for psign/blend 14298 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14299 if (!Subtarget->hasSSSE3() || 14300 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14301 return SDValue(); 14302 14303 // Canonicalize pandn to RHS 14304 if (N0.getOpcode() == X86ISD::ANDNP) 14305 std::swap(N0, N1); 14306 // or (and (m, y), (pandn m, x)) 14307 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14308 SDValue Mask = N1.getOperand(0); 14309 SDValue X = N1.getOperand(1); 14310 SDValue Y; 14311 if (N0.getOperand(0) == Mask) 14312 Y = N0.getOperand(1); 14313 if (N0.getOperand(1) == Mask) 14314 Y = N0.getOperand(0); 14315 14316 // Check to see if the mask appeared in both the AND and ANDNP and 14317 if (!Y.getNode()) 14318 return SDValue(); 14319 14320 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14321 // Look through mask bitcast. 14322 if (Mask.getOpcode() == ISD::BITCAST) 14323 Mask = Mask.getOperand(0); 14324 if (X.getOpcode() == ISD::BITCAST) 14325 X = X.getOperand(0); 14326 if (Y.getOpcode() == ISD::BITCAST) 14327 Y = Y.getOperand(0); 14328 14329 EVT MaskVT = Mask.getValueType(); 14330 14331 // Validate that the Mask operand is a vector sra node. 14332 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14333 // there is no psrai.b 14334 if (Mask.getOpcode() != X86ISD::VSRAI) 14335 return SDValue(); 14336 14337 // Check that the SRA is all signbits. 14338 SDValue SraC = Mask.getOperand(1); 14339 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14340 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14341 if ((SraAmt + 1) != EltBits) 14342 return SDValue(); 14343 14344 DebugLoc DL = N->getDebugLoc(); 14345 14346 // Now we know we at least have a plendvb with the mask val. See if 14347 // we can form a psignb/w/d. 14348 // psign = x.type == y.type == mask.type && y = sub(0, x); 14349 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14350 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14351 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14352 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14353 "Unsupported VT for PSIGN"); 14354 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14355 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14356 } 14357 // PBLENDVB only available on SSE 4.1 14358 if (!Subtarget->hasSSE41()) 14359 return SDValue(); 14360 14361 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14362 14363 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14364 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14365 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14366 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14367 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14368 } 14369 } 14370 14371 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14372 return SDValue(); 14373 14374 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14375 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14376 std::swap(N0, N1); 14377 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14378 return SDValue(); 14379 if (!N0.hasOneUse() || !N1.hasOneUse()) 14380 return SDValue(); 14381 14382 SDValue ShAmt0 = N0.getOperand(1); 14383 if (ShAmt0.getValueType() != MVT::i8) 14384 return SDValue(); 14385 SDValue ShAmt1 = N1.getOperand(1); 14386 if (ShAmt1.getValueType() != MVT::i8) 14387 return SDValue(); 14388 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14389 ShAmt0 = ShAmt0.getOperand(0); 14390 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14391 ShAmt1 = ShAmt1.getOperand(0); 14392 14393 DebugLoc DL = N->getDebugLoc(); 14394 unsigned Opc = X86ISD::SHLD; 14395 SDValue Op0 = N0.getOperand(0); 14396 SDValue Op1 = N1.getOperand(0); 14397 if (ShAmt0.getOpcode() == ISD::SUB) { 14398 Opc = X86ISD::SHRD; 14399 std::swap(Op0, Op1); 14400 std::swap(ShAmt0, ShAmt1); 14401 } 14402 14403 unsigned Bits = VT.getSizeInBits(); 14404 if (ShAmt1.getOpcode() == ISD::SUB) { 14405 SDValue Sum = ShAmt1.getOperand(0); 14406 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14407 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14408 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14409 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14410 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14411 return DAG.getNode(Opc, DL, VT, 14412 Op0, Op1, 14413 DAG.getNode(ISD::TRUNCATE, DL, 14414 MVT::i8, ShAmt0)); 14415 } 14416 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14417 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14418 if (ShAmt0C && 14419 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14420 return DAG.getNode(Opc, DL, VT, 14421 N0.getOperand(0), N1.getOperand(0), 14422 DAG.getNode(ISD::TRUNCATE, DL, 14423 MVT::i8, ShAmt0)); 14424 } 14425 14426 return SDValue(); 14427} 14428 14429// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14430static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14431 TargetLowering::DAGCombinerInfo &DCI, 14432 const X86Subtarget *Subtarget) { 14433 if (DCI.isBeforeLegalizeOps()) 14434 return SDValue(); 14435 14436 EVT VT = N->getValueType(0); 14437 14438 if (VT != MVT::i32 && VT != MVT::i64) 14439 return SDValue(); 14440 14441 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14442 14443 // Create BLSMSK instructions by finding X ^ (X-1) 14444 SDValue N0 = N->getOperand(0); 14445 SDValue N1 = N->getOperand(1); 14446 DebugLoc DL = N->getDebugLoc(); 14447 14448 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14449 isAllOnes(N0.getOperand(1))) 14450 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14451 14452 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14453 isAllOnes(N1.getOperand(1))) 14454 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14455 14456 return SDValue(); 14457} 14458 14459/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14460static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14461 const X86Subtarget *Subtarget) { 14462 LoadSDNode *Ld = cast<LoadSDNode>(N); 14463 EVT RegVT = Ld->getValueType(0); 14464 EVT MemVT = Ld->getMemoryVT(); 14465 DebugLoc dl = Ld->getDebugLoc(); 14466 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14467 14468 ISD::LoadExtType Ext = Ld->getExtensionType(); 14469 14470 // If this is a vector EXT Load then attempt to optimize it using a 14471 // shuffle. We need SSE4 for the shuffles. 14472 // TODO: It is possible to support ZExt by zeroing the undef values 14473 // during the shuffle phase or after the shuffle. 14474 if (RegVT.isVector() && RegVT.isInteger() && 14475 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14476 assert(MemVT != RegVT && "Cannot extend to the same type"); 14477 assert(MemVT.isVector() && "Must load a vector from memory"); 14478 14479 unsigned NumElems = RegVT.getVectorNumElements(); 14480 unsigned RegSz = RegVT.getSizeInBits(); 14481 unsigned MemSz = MemVT.getSizeInBits(); 14482 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14483 // All sizes must be a power of two 14484 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14485 14486 // Attempt to load the original value using a single load op. 14487 // Find a scalar type which is equal to the loaded word size. 14488 MVT SclrLoadTy = MVT::i8; 14489 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14490 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14491 MVT Tp = (MVT::SimpleValueType)tp; 14492 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14493 SclrLoadTy = Tp; 14494 break; 14495 } 14496 } 14497 14498 // Proceed if a load word is found. 14499 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14500 14501 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14502 RegSz/SclrLoadTy.getSizeInBits()); 14503 14504 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14505 RegSz/MemVT.getScalarType().getSizeInBits()); 14506 // Can't shuffle using an illegal type. 14507 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14508 14509 // Perform a single load. 14510 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14511 Ld->getBasePtr(), 14512 Ld->getPointerInfo(), Ld->isVolatile(), 14513 Ld->isNonTemporal(), Ld->isInvariant(), 14514 Ld->getAlignment()); 14515 14516 // Insert the word loaded into a vector. 14517 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14518 LoadUnitVecVT, ScalarLoad); 14519 14520 // Bitcast the loaded value to a vector of the original element type, in 14521 // the size of the target vector type. 14522 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14523 ScalarInVector); 14524 unsigned SizeRatio = RegSz/MemSz; 14525 14526 // Redistribute the loaded elements into the different locations. 14527 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14528 for (unsigned i = 0; i != NumElems; ++i) 14529 ShuffleVec[i*SizeRatio] = i; 14530 14531 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14532 DAG.getUNDEF(WideVecVT), 14533 &ShuffleVec[0]); 14534 14535 // Bitcast to the requested type. 14536 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14537 // Replace the original load with the new sequence 14538 // and return the new chain. 14539 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14540 return SDValue(ScalarLoad.getNode(), 1); 14541 } 14542 14543 return SDValue(); 14544} 14545 14546/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14547static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14548 const X86Subtarget *Subtarget) { 14549 StoreSDNode *St = cast<StoreSDNode>(N); 14550 EVT VT = St->getValue().getValueType(); 14551 EVT StVT = St->getMemoryVT(); 14552 DebugLoc dl = St->getDebugLoc(); 14553 SDValue StoredVal = St->getOperand(1); 14554 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14555 14556 // If we are saving a concatenation of two XMM registers, perform two stores. 14557 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14558 // 128-bit ones. If in the future the cost becomes only one memory access the 14559 // first version would be better. 14560 if (VT.getSizeInBits() == 256 && 14561 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14562 StoredVal.getNumOperands() == 2) { 14563 14564 SDValue Value0 = StoredVal.getOperand(0); 14565 SDValue Value1 = StoredVal.getOperand(1); 14566 14567 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14568 SDValue Ptr0 = St->getBasePtr(); 14569 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14570 14571 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14572 St->getPointerInfo(), St->isVolatile(), 14573 St->isNonTemporal(), St->getAlignment()); 14574 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14575 St->getPointerInfo(), St->isVolatile(), 14576 St->isNonTemporal(), St->getAlignment()); 14577 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14578 } 14579 14580 // Optimize trunc store (of multiple scalars) to shuffle and store. 14581 // First, pack all of the elements in one place. Next, store to memory 14582 // in fewer chunks. 14583 if (St->isTruncatingStore() && VT.isVector()) { 14584 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14585 unsigned NumElems = VT.getVectorNumElements(); 14586 assert(StVT != VT && "Cannot truncate to the same type"); 14587 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14588 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14589 14590 // From, To sizes and ElemCount must be pow of two 14591 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14592 // We are going to use the original vector elt for storing. 14593 // Accumulated smaller vector elements must be a multiple of the store size. 14594 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14595 14596 unsigned SizeRatio = FromSz / ToSz; 14597 14598 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14599 14600 // Create a type on which we perform the shuffle 14601 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14602 StVT.getScalarType(), NumElems*SizeRatio); 14603 14604 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14605 14606 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14607 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14608 for (unsigned i = 0; i != NumElems; ++i) 14609 ShuffleVec[i] = i * SizeRatio; 14610 14611 // Can't shuffle using an illegal type 14612 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14613 14614 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14615 DAG.getUNDEF(WideVecVT), 14616 &ShuffleVec[0]); 14617 // At this point all of the data is stored at the bottom of the 14618 // register. We now need to save it to mem. 14619 14620 // Find the largest store unit 14621 MVT StoreType = MVT::i8; 14622 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14623 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14624 MVT Tp = (MVT::SimpleValueType)tp; 14625 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14626 StoreType = Tp; 14627 } 14628 14629 // Bitcast the original vector into a vector of store-size units 14630 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14631 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14632 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14633 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14634 SmallVector<SDValue, 8> Chains; 14635 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14636 TLI.getPointerTy()); 14637 SDValue Ptr = St->getBasePtr(); 14638 14639 // Perform one or more big stores into memory. 14640 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { 14641 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14642 StoreType, ShuffWide, 14643 DAG.getIntPtrConstant(i)); 14644 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14645 St->getPointerInfo(), St->isVolatile(), 14646 St->isNonTemporal(), St->getAlignment()); 14647 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14648 Chains.push_back(Ch); 14649 } 14650 14651 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14652 Chains.size()); 14653 } 14654 14655 14656 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14657 // the FP state in cases where an emms may be missing. 14658 // A preferable solution to the general problem is to figure out the right 14659 // places to insert EMMS. This qualifies as a quick hack. 14660 14661 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14662 if (VT.getSizeInBits() != 64) 14663 return SDValue(); 14664 14665 const Function *F = DAG.getMachineFunction().getFunction(); 14666 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14667 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14668 && Subtarget->hasSSE2(); 14669 if ((VT.isVector() || 14670 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14671 isa<LoadSDNode>(St->getValue()) && 14672 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14673 St->getChain().hasOneUse() && !St->isVolatile()) { 14674 SDNode* LdVal = St->getValue().getNode(); 14675 LoadSDNode *Ld = 0; 14676 int TokenFactorIndex = -1; 14677 SmallVector<SDValue, 8> Ops; 14678 SDNode* ChainVal = St->getChain().getNode(); 14679 // Must be a store of a load. We currently handle two cases: the load 14680 // is a direct child, and it's under an intervening TokenFactor. It is 14681 // possible to dig deeper under nested TokenFactors. 14682 if (ChainVal == LdVal) 14683 Ld = cast<LoadSDNode>(St->getChain()); 14684 else if (St->getValue().hasOneUse() && 14685 ChainVal->getOpcode() == ISD::TokenFactor) { 14686 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14687 if (ChainVal->getOperand(i).getNode() == LdVal) { 14688 TokenFactorIndex = i; 14689 Ld = cast<LoadSDNode>(St->getValue()); 14690 } else 14691 Ops.push_back(ChainVal->getOperand(i)); 14692 } 14693 } 14694 14695 if (!Ld || !ISD::isNormalLoad(Ld)) 14696 return SDValue(); 14697 14698 // If this is not the MMX case, i.e. we are just turning i64 load/store 14699 // into f64 load/store, avoid the transformation if there are multiple 14700 // uses of the loaded value. 14701 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14702 return SDValue(); 14703 14704 DebugLoc LdDL = Ld->getDebugLoc(); 14705 DebugLoc StDL = N->getDebugLoc(); 14706 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14707 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14708 // pair instead. 14709 if (Subtarget->is64Bit() || F64IsLegal) { 14710 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14711 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14712 Ld->getPointerInfo(), Ld->isVolatile(), 14713 Ld->isNonTemporal(), Ld->isInvariant(), 14714 Ld->getAlignment()); 14715 SDValue NewChain = NewLd.getValue(1); 14716 if (TokenFactorIndex != -1) { 14717 Ops.push_back(NewChain); 14718 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14719 Ops.size()); 14720 } 14721 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14722 St->getPointerInfo(), 14723 St->isVolatile(), St->isNonTemporal(), 14724 St->getAlignment()); 14725 } 14726 14727 // Otherwise, lower to two pairs of 32-bit loads / stores. 14728 SDValue LoAddr = Ld->getBasePtr(); 14729 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14730 DAG.getConstant(4, MVT::i32)); 14731 14732 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14733 Ld->getPointerInfo(), 14734 Ld->isVolatile(), Ld->isNonTemporal(), 14735 Ld->isInvariant(), Ld->getAlignment()); 14736 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14737 Ld->getPointerInfo().getWithOffset(4), 14738 Ld->isVolatile(), Ld->isNonTemporal(), 14739 Ld->isInvariant(), 14740 MinAlign(Ld->getAlignment(), 4)); 14741 14742 SDValue NewChain = LoLd.getValue(1); 14743 if (TokenFactorIndex != -1) { 14744 Ops.push_back(LoLd); 14745 Ops.push_back(HiLd); 14746 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14747 Ops.size()); 14748 } 14749 14750 LoAddr = St->getBasePtr(); 14751 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14752 DAG.getConstant(4, MVT::i32)); 14753 14754 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14755 St->getPointerInfo(), 14756 St->isVolatile(), St->isNonTemporal(), 14757 St->getAlignment()); 14758 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14759 St->getPointerInfo().getWithOffset(4), 14760 St->isVolatile(), 14761 St->isNonTemporal(), 14762 MinAlign(St->getAlignment(), 4)); 14763 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14764 } 14765 return SDValue(); 14766} 14767 14768/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14769/// and return the operands for the horizontal operation in LHS and RHS. A 14770/// horizontal operation performs the binary operation on successive elements 14771/// of its first operand, then on successive elements of its second operand, 14772/// returning the resulting values in a vector. For example, if 14773/// A = < float a0, float a1, float a2, float a3 > 14774/// and 14775/// B = < float b0, float b1, float b2, float b3 > 14776/// then the result of doing a horizontal operation on A and B is 14777/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14778/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14779/// A horizontal-op B, for some already available A and B, and if so then LHS is 14780/// set to A, RHS to B, and the routine returns 'true'. 14781/// Note that the binary operation should have the property that if one of the 14782/// operands is UNDEF then the result is UNDEF. 14783static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14784 // Look for the following pattern: if 14785 // A = < float a0, float a1, float a2, float a3 > 14786 // B = < float b0, float b1, float b2, float b3 > 14787 // and 14788 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14789 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14790 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14791 // which is A horizontal-op B. 14792 14793 // At least one of the operands should be a vector shuffle. 14794 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14795 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14796 return false; 14797 14798 EVT VT = LHS.getValueType(); 14799 14800 assert((VT.is128BitVector() || VT.is256BitVector()) && 14801 "Unsupported vector type for horizontal add/sub"); 14802 14803 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14804 // operate independently on 128-bit lanes. 14805 unsigned NumElts = VT.getVectorNumElements(); 14806 unsigned NumLanes = VT.getSizeInBits()/128; 14807 unsigned NumLaneElts = NumElts / NumLanes; 14808 assert((NumLaneElts % 2 == 0) && 14809 "Vector type should have an even number of elements in each lane"); 14810 unsigned HalfLaneElts = NumLaneElts/2; 14811 14812 // View LHS in the form 14813 // LHS = VECTOR_SHUFFLE A, B, LMask 14814 // If LHS is not a shuffle then pretend it is the shuffle 14815 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14816 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14817 // type VT. 14818 SDValue A, B; 14819 SmallVector<int, 16> LMask(NumElts); 14820 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14821 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14822 A = LHS.getOperand(0); 14823 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14824 B = LHS.getOperand(1); 14825 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14826 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14827 } else { 14828 if (LHS.getOpcode() != ISD::UNDEF) 14829 A = LHS; 14830 for (unsigned i = 0; i != NumElts; ++i) 14831 LMask[i] = i; 14832 } 14833 14834 // Likewise, view RHS in the form 14835 // RHS = VECTOR_SHUFFLE C, D, RMask 14836 SDValue C, D; 14837 SmallVector<int, 16> RMask(NumElts); 14838 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14839 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14840 C = RHS.getOperand(0); 14841 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14842 D = RHS.getOperand(1); 14843 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14844 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14845 } else { 14846 if (RHS.getOpcode() != ISD::UNDEF) 14847 C = RHS; 14848 for (unsigned i = 0; i != NumElts; ++i) 14849 RMask[i] = i; 14850 } 14851 14852 // Check that the shuffles are both shuffling the same vectors. 14853 if (!(A == C && B == D) && !(A == D && B == C)) 14854 return false; 14855 14856 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14857 if (!A.getNode() && !B.getNode()) 14858 return false; 14859 14860 // If A and B occur in reverse order in RHS, then "swap" them (which means 14861 // rewriting the mask). 14862 if (A != C) 14863 CommuteVectorShuffleMask(RMask, NumElts); 14864 14865 // At this point LHS and RHS are equivalent to 14866 // LHS = VECTOR_SHUFFLE A, B, LMask 14867 // RHS = VECTOR_SHUFFLE A, B, RMask 14868 // Check that the masks correspond to performing a horizontal operation. 14869 for (unsigned i = 0; i != NumElts; ++i) { 14870 int LIdx = LMask[i], RIdx = RMask[i]; 14871 14872 // Ignore any UNDEF components. 14873 if (LIdx < 0 || RIdx < 0 || 14874 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14875 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14876 continue; 14877 14878 // Check that successive elements are being operated on. If not, this is 14879 // not a horizontal operation. 14880 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14881 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14882 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14883 if (!(LIdx == Index && RIdx == Index + 1) && 14884 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14885 return false; 14886 } 14887 14888 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14889 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14890 return true; 14891} 14892 14893/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14894static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14895 const X86Subtarget *Subtarget) { 14896 EVT VT = N->getValueType(0); 14897 SDValue LHS = N->getOperand(0); 14898 SDValue RHS = N->getOperand(1); 14899 14900 // Try to synthesize horizontal adds from adds of shuffles. 14901 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14902 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14903 isHorizontalBinOp(LHS, RHS, true)) 14904 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14905 return SDValue(); 14906} 14907 14908/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14909static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14910 const X86Subtarget *Subtarget) { 14911 EVT VT = N->getValueType(0); 14912 SDValue LHS = N->getOperand(0); 14913 SDValue RHS = N->getOperand(1); 14914 14915 // Try to synthesize horizontal subs from subs of shuffles. 14916 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14917 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14918 isHorizontalBinOp(LHS, RHS, false)) 14919 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14920 return SDValue(); 14921} 14922 14923/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14924/// X86ISD::FXOR nodes. 14925static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14926 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14927 // F[X]OR(0.0, x) -> x 14928 // F[X]OR(x, 0.0) -> x 14929 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14930 if (C->getValueAPF().isPosZero()) 14931 return N->getOperand(1); 14932 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14933 if (C->getValueAPF().isPosZero()) 14934 return N->getOperand(0); 14935 return SDValue(); 14936} 14937 14938/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14939static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14940 // FAND(0.0, x) -> 0.0 14941 // FAND(x, 0.0) -> 0.0 14942 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14943 if (C->getValueAPF().isPosZero()) 14944 return N->getOperand(0); 14945 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14946 if (C->getValueAPF().isPosZero()) 14947 return N->getOperand(1); 14948 return SDValue(); 14949} 14950 14951static SDValue PerformBTCombine(SDNode *N, 14952 SelectionDAG &DAG, 14953 TargetLowering::DAGCombinerInfo &DCI) { 14954 // BT ignores high bits in the bit index operand. 14955 SDValue Op1 = N->getOperand(1); 14956 if (Op1.hasOneUse()) { 14957 unsigned BitWidth = Op1.getValueSizeInBits(); 14958 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14959 APInt KnownZero, KnownOne; 14960 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14961 !DCI.isBeforeLegalizeOps()); 14962 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14963 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14964 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14965 DCI.CommitTargetLoweringOpt(TLO); 14966 } 14967 return SDValue(); 14968} 14969 14970static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14971 SDValue Op = N->getOperand(0); 14972 if (Op.getOpcode() == ISD::BITCAST) 14973 Op = Op.getOperand(0); 14974 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14975 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14976 VT.getVectorElementType().getSizeInBits() == 14977 OpVT.getVectorElementType().getSizeInBits()) { 14978 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14979 } 14980 return SDValue(); 14981} 14982 14983static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14984 TargetLowering::DAGCombinerInfo &DCI, 14985 const X86Subtarget *Subtarget) { 14986 if (!DCI.isBeforeLegalizeOps()) 14987 return SDValue(); 14988 14989 if (!Subtarget->hasAVX()) 14990 return SDValue(); 14991 14992 EVT VT = N->getValueType(0); 14993 SDValue Op = N->getOperand(0); 14994 EVT OpVT = Op.getValueType(); 14995 DebugLoc dl = N->getDebugLoc(); 14996 14997 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14998 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14999 15000 if (Subtarget->hasAVX2()) 15001 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op); 15002 15003 // Optimize vectors in AVX mode 15004 // Sign extend v8i16 to v8i32 and 15005 // v4i32 to v4i64 15006 // 15007 // Divide input vector into two parts 15008 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 15009 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 15010 // concat the vectors to original VT 15011 15012 unsigned NumElems = OpVT.getVectorNumElements(); 15013 SmallVector<int,8> ShufMask1(NumElems, -1); 15014 for (unsigned i = 0; i != NumElems/2; ++i) 15015 ShufMask1[i] = i; 15016 15017 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 15018 &ShufMask1[0]); 15019 15020 SmallVector<int,8> ShufMask2(NumElems, -1); 15021 for (unsigned i = 0; i != NumElems/2; ++i) 15022 ShufMask2[i] = i + NumElems/2; 15023 15024 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 15025 &ShufMask2[0]); 15026 15027 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 15028 VT.getVectorNumElements()/2); 15029 15030 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 15031 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 15032 15033 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15034 } 15035 return SDValue(); 15036} 15037 15038static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 15039 TargetLowering::DAGCombinerInfo &DCI, 15040 const X86Subtarget *Subtarget) { 15041 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 15042 // (and (i32 x86isd::setcc_carry), 1) 15043 // This eliminates the zext. This transformation is necessary because 15044 // ISD::SETCC is always legalized to i8. 15045 DebugLoc dl = N->getDebugLoc(); 15046 SDValue N0 = N->getOperand(0); 15047 EVT VT = N->getValueType(0); 15048 EVT OpVT = N0.getValueType(); 15049 15050 if (N0.getOpcode() == ISD::AND && 15051 N0.hasOneUse() && 15052 N0.getOperand(0).hasOneUse()) { 15053 SDValue N00 = N0.getOperand(0); 15054 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 15055 return SDValue(); 15056 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 15057 if (!C || C->getZExtValue() != 1) 15058 return SDValue(); 15059 return DAG.getNode(ISD::AND, dl, VT, 15060 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 15061 N00.getOperand(0), N00.getOperand(1)), 15062 DAG.getConstant(1, VT)); 15063 } 15064 15065 // Optimize vectors in AVX mode: 15066 // 15067 // v8i16 -> v8i32 15068 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 15069 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 15070 // Concat upper and lower parts. 15071 // 15072 // v4i32 -> v4i64 15073 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 15074 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 15075 // Concat upper and lower parts. 15076 // 15077 if (!DCI.isBeforeLegalizeOps()) 15078 return SDValue(); 15079 15080 if (!Subtarget->hasAVX()) 15081 return SDValue(); 15082 15083 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 15084 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 15085 15086 if (Subtarget->hasAVX2()) 15087 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0); 15088 15089 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 15090 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec); 15091 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec); 15092 15093 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 15094 VT.getVectorNumElements()/2); 15095 15096 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 15097 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 15098 15099 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 15100 } 15101 15102 return SDValue(); 15103} 15104 15105// Optimize x == -y --> x+y == 0 15106// x != -y --> x+y != 0 15107static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15108 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 15109 SDValue LHS = N->getOperand(0); 15110 SDValue RHS = N->getOperand(1); 15111 15112 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 15113 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 15114 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 15115 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15116 LHS.getValueType(), RHS, LHS.getOperand(1)); 15117 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15118 addV, DAG.getConstant(0, addV.getValueType()), CC); 15119 } 15120 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 15121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 15122 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 15123 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15124 RHS.getValueType(), LHS, RHS.getOperand(1)); 15125 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15126 addV, DAG.getConstant(0, addV.getValueType()), CC); 15127 } 15128 return SDValue(); 15129} 15130 15131// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 15132static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15133 unsigned X86CC = N->getConstantOperandVal(0); 15134 SDValue EFLAG = N->getOperand(1); 15135 DebugLoc DL = N->getDebugLoc(); 15136 15137 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 15138 // a zext and produces an all-ones bit which is more useful than 0/1 in some 15139 // cases. 15140 if (X86CC == X86::COND_B) 15141 return DAG.getNode(ISD::AND, DL, MVT::i8, 15142 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 15143 DAG.getConstant(X86CC, MVT::i8), EFLAG), 15144 DAG.getConstant(1, MVT::i8)); 15145 15146 return SDValue(); 15147} 15148 15149static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) { 15150 SDValue Op0 = N->getOperand(0); 15151 EVT InVT = Op0->getValueType(0); 15152 15153 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) 15154 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15155 DebugLoc dl = N->getDebugLoc(); 15156 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15157 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); 15158 // Notice that we use SINT_TO_FP because we know that the high bits 15159 // are zero and SINT_TO_FP is better supported by the hardware. 15160 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15161 } 15162 15163 return SDValue(); 15164} 15165 15166static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 15167 const X86TargetLowering *XTLI) { 15168 SDValue Op0 = N->getOperand(0); 15169 EVT InVT = Op0->getValueType(0); 15170 15171 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 15172 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15173 DebugLoc dl = N->getDebugLoc(); 15174 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15175 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 15176 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15177 } 15178 15179 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 15180 // a 32-bit target where SSE doesn't support i64->FP operations. 15181 if (Op0.getOpcode() == ISD::LOAD) { 15182 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 15183 EVT VT = Ld->getValueType(0); 15184 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 15185 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 15186 !XTLI->getSubtarget()->is64Bit() && 15187 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 15188 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 15189 Ld->getChain(), Op0, DAG); 15190 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 15191 return FILDChain; 15192 } 15193 } 15194 return SDValue(); 15195} 15196 15197static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) { 15198 EVT VT = N->getValueType(0); 15199 15200 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT() 15201 if (VT == MVT::v8i8 || VT == MVT::v4i8) { 15202 DebugLoc dl = N->getDebugLoc(); 15203 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15204 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0)); 15205 return DAG.getNode(ISD::TRUNCATE, dl, VT, I); 15206 } 15207 15208 return SDValue(); 15209} 15210 15211// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 15212static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 15213 X86TargetLowering::DAGCombinerInfo &DCI) { 15214 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 15215 // the result is either zero or one (depending on the input carry bit). 15216 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 15217 if (X86::isZeroNode(N->getOperand(0)) && 15218 X86::isZeroNode(N->getOperand(1)) && 15219 // We don't have a good way to replace an EFLAGS use, so only do this when 15220 // dead right now. 15221 SDValue(N, 1).use_empty()) { 15222 DebugLoc DL = N->getDebugLoc(); 15223 EVT VT = N->getValueType(0); 15224 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 15225 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 15226 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 15227 DAG.getConstant(X86::COND_B,MVT::i8), 15228 N->getOperand(2)), 15229 DAG.getConstant(1, VT)); 15230 return DCI.CombineTo(N, Res1, CarryOut); 15231 } 15232 15233 return SDValue(); 15234} 15235 15236// fold (add Y, (sete X, 0)) -> adc 0, Y 15237// (add Y, (setne X, 0)) -> sbb -1, Y 15238// (sub (sete X, 0), Y) -> sbb 0, Y 15239// (sub (setne X, 0), Y) -> adc -1, Y 15240static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 15241 DebugLoc DL = N->getDebugLoc(); 15242 15243 // Look through ZExts. 15244 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 15245 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 15246 return SDValue(); 15247 15248 SDValue SetCC = Ext.getOperand(0); 15249 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 15250 return SDValue(); 15251 15252 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 15253 if (CC != X86::COND_E && CC != X86::COND_NE) 15254 return SDValue(); 15255 15256 SDValue Cmp = SetCC.getOperand(1); 15257 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 15258 !X86::isZeroNode(Cmp.getOperand(1)) || 15259 !Cmp.getOperand(0).getValueType().isInteger()) 15260 return SDValue(); 15261 15262 SDValue CmpOp0 = Cmp.getOperand(0); 15263 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 15264 DAG.getConstant(1, CmpOp0.getValueType())); 15265 15266 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 15267 if (CC == X86::COND_NE) 15268 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 15269 DL, OtherVal.getValueType(), OtherVal, 15270 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 15271 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 15272 DL, OtherVal.getValueType(), OtherVal, 15273 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 15274} 15275 15276/// PerformADDCombine - Do target-specific dag combines on integer adds. 15277static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 15278 const X86Subtarget *Subtarget) { 15279 EVT VT = N->getValueType(0); 15280 SDValue Op0 = N->getOperand(0); 15281 SDValue Op1 = N->getOperand(1); 15282 15283 // Try to synthesize horizontal adds from adds of shuffles. 15284 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15285 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15286 isHorizontalBinOp(Op0, Op1, true)) 15287 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 15288 15289 return OptimizeConditionalInDecrement(N, DAG); 15290} 15291 15292static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 15293 const X86Subtarget *Subtarget) { 15294 SDValue Op0 = N->getOperand(0); 15295 SDValue Op1 = N->getOperand(1); 15296 15297 // X86 can't encode an immediate LHS of a sub. See if we can push the 15298 // negation into a preceding instruction. 15299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 15300 // If the RHS of the sub is a XOR with one use and a constant, invert the 15301 // immediate. Then add one to the LHS of the sub so we can turn 15302 // X-Y -> X+~Y+1, saving one register. 15303 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 15304 isa<ConstantSDNode>(Op1.getOperand(1))) { 15305 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 15306 EVT VT = Op0.getValueType(); 15307 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 15308 Op1.getOperand(0), 15309 DAG.getConstant(~XorC, VT)); 15310 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 15311 DAG.getConstant(C->getAPIntValue()+1, VT)); 15312 } 15313 } 15314 15315 // Try to synthesize horizontal adds from adds of shuffles. 15316 EVT VT = N->getValueType(0); 15317 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15318 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15319 isHorizontalBinOp(Op0, Op1, true)) 15320 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15321 15322 return OptimizeConditionalInDecrement(N, DAG); 15323} 15324 15325SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15326 DAGCombinerInfo &DCI) const { 15327 SelectionDAG &DAG = DCI.DAG; 15328 switch (N->getOpcode()) { 15329 default: break; 15330 case ISD::EXTRACT_VECTOR_ELT: 15331 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15332 case ISD::VSELECT: 15333 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15334 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15335 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15336 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15337 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15338 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15339 case ISD::SHL: 15340 case ISD::SRA: 15341 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15342 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15343 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15344 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15345 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 15346 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15347 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG); 15348 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15349 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG); 15350 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15351 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15352 case X86ISD::FXOR: 15353 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15354 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15355 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15356 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15357 case ISD::ANY_EXTEND: 15358 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 15359 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15360 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15361 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 15362 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15363 case X86ISD::SHUFP: // Handle all target specific shuffles 15364 case X86ISD::PALIGN: 15365 case X86ISD::UNPCKH: 15366 case X86ISD::UNPCKL: 15367 case X86ISD::MOVHLPS: 15368 case X86ISD::MOVLHPS: 15369 case X86ISD::PSHUFD: 15370 case X86ISD::PSHUFHW: 15371 case X86ISD::PSHUFLW: 15372 case X86ISD::MOVSS: 15373 case X86ISD::MOVSD: 15374 case X86ISD::VPERMILP: 15375 case X86ISD::VPERM2X128: 15376 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15377 } 15378 15379 return SDValue(); 15380} 15381 15382/// isTypeDesirableForOp - Return true if the target has native support for 15383/// the specified value type and it is 'desirable' to use the type for the 15384/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15385/// instruction encodings are longer and some i16 instructions are slow. 15386bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15387 if (!isTypeLegal(VT)) 15388 return false; 15389 if (VT != MVT::i16) 15390 return true; 15391 15392 switch (Opc) { 15393 default: 15394 return true; 15395 case ISD::LOAD: 15396 case ISD::SIGN_EXTEND: 15397 case ISD::ZERO_EXTEND: 15398 case ISD::ANY_EXTEND: 15399 case ISD::SHL: 15400 case ISD::SRL: 15401 case ISD::SUB: 15402 case ISD::ADD: 15403 case ISD::MUL: 15404 case ISD::AND: 15405 case ISD::OR: 15406 case ISD::XOR: 15407 return false; 15408 } 15409} 15410 15411/// IsDesirableToPromoteOp - This method query the target whether it is 15412/// beneficial for dag combiner to promote the specified node. If true, it 15413/// should return the desired promotion type by reference. 15414bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15415 EVT VT = Op.getValueType(); 15416 if (VT != MVT::i16) 15417 return false; 15418 15419 bool Promote = false; 15420 bool Commute = false; 15421 switch (Op.getOpcode()) { 15422 default: break; 15423 case ISD::LOAD: { 15424 LoadSDNode *LD = cast<LoadSDNode>(Op); 15425 // If the non-extending load has a single use and it's not live out, then it 15426 // might be folded. 15427 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15428 Op.hasOneUse()*/) { 15429 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15430 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15431 // The only case where we'd want to promote LOAD (rather then it being 15432 // promoted as an operand is when it's only use is liveout. 15433 if (UI->getOpcode() != ISD::CopyToReg) 15434 return false; 15435 } 15436 } 15437 Promote = true; 15438 break; 15439 } 15440 case ISD::SIGN_EXTEND: 15441 case ISD::ZERO_EXTEND: 15442 case ISD::ANY_EXTEND: 15443 Promote = true; 15444 break; 15445 case ISD::SHL: 15446 case ISD::SRL: { 15447 SDValue N0 = Op.getOperand(0); 15448 // Look out for (store (shl (load), x)). 15449 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15450 return false; 15451 Promote = true; 15452 break; 15453 } 15454 case ISD::ADD: 15455 case ISD::MUL: 15456 case ISD::AND: 15457 case ISD::OR: 15458 case ISD::XOR: 15459 Commute = true; 15460 // fallthrough 15461 case ISD::SUB: { 15462 SDValue N0 = Op.getOperand(0); 15463 SDValue N1 = Op.getOperand(1); 15464 if (!Commute && MayFoldLoad(N1)) 15465 return false; 15466 // Avoid disabling potential load folding opportunities. 15467 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15468 return false; 15469 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15470 return false; 15471 Promote = true; 15472 } 15473 } 15474 15475 PVT = MVT::i32; 15476 return Promote; 15477} 15478 15479//===----------------------------------------------------------------------===// 15480// X86 Inline Assembly Support 15481//===----------------------------------------------------------------------===// 15482 15483namespace { 15484 // Helper to match a string separated by whitespace. 15485 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15486 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15487 15488 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15489 StringRef piece(*args[i]); 15490 if (!s.startswith(piece)) // Check if the piece matches. 15491 return false; 15492 15493 s = s.substr(piece.size()); 15494 StringRef::size_type pos = s.find_first_not_of(" \t"); 15495 if (pos == 0) // We matched a prefix. 15496 return false; 15497 15498 s = s.substr(pos); 15499 } 15500 15501 return s.empty(); 15502 } 15503 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15504} 15505 15506bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15507 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15508 15509 std::string AsmStr = IA->getAsmString(); 15510 15511 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15512 if (!Ty || Ty->getBitWidth() % 16 != 0) 15513 return false; 15514 15515 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15516 SmallVector<StringRef, 4> AsmPieces; 15517 SplitString(AsmStr, AsmPieces, ";\n"); 15518 15519 switch (AsmPieces.size()) { 15520 default: return false; 15521 case 1: 15522 // FIXME: this should verify that we are targeting a 486 or better. If not, 15523 // we will turn this bswap into something that will be lowered to logical 15524 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15525 // lower so don't worry about this. 15526 // bswap $0 15527 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15528 matchAsm(AsmPieces[0], "bswapl", "$0") || 15529 matchAsm(AsmPieces[0], "bswapq", "$0") || 15530 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15531 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15532 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15533 // No need to check constraints, nothing other than the equivalent of 15534 // "=r,0" would be valid here. 15535 return IntrinsicLowering::LowerToByteSwap(CI); 15536 } 15537 15538 // rorw $$8, ${0:w} --> llvm.bswap.i16 15539 if (CI->getType()->isIntegerTy(16) && 15540 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15541 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15542 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15543 AsmPieces.clear(); 15544 const std::string &ConstraintsStr = IA->getConstraintString(); 15545 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15546 std::sort(AsmPieces.begin(), AsmPieces.end()); 15547 if (AsmPieces.size() == 4 && 15548 AsmPieces[0] == "~{cc}" && 15549 AsmPieces[1] == "~{dirflag}" && 15550 AsmPieces[2] == "~{flags}" && 15551 AsmPieces[3] == "~{fpsr}") 15552 return IntrinsicLowering::LowerToByteSwap(CI); 15553 } 15554 break; 15555 case 3: 15556 if (CI->getType()->isIntegerTy(32) && 15557 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15558 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15559 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15560 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15561 AsmPieces.clear(); 15562 const std::string &ConstraintsStr = IA->getConstraintString(); 15563 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15564 std::sort(AsmPieces.begin(), AsmPieces.end()); 15565 if (AsmPieces.size() == 4 && 15566 AsmPieces[0] == "~{cc}" && 15567 AsmPieces[1] == "~{dirflag}" && 15568 AsmPieces[2] == "~{flags}" && 15569 AsmPieces[3] == "~{fpsr}") 15570 return IntrinsicLowering::LowerToByteSwap(CI); 15571 } 15572 15573 if (CI->getType()->isIntegerTy(64)) { 15574 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15575 if (Constraints.size() >= 2 && 15576 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15577 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15578 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15579 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15580 matchAsm(AsmPieces[1], "bswap", "%edx") && 15581 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15582 return IntrinsicLowering::LowerToByteSwap(CI); 15583 } 15584 } 15585 break; 15586 } 15587 return false; 15588} 15589 15590 15591 15592/// getConstraintType - Given a constraint letter, return the type of 15593/// constraint it is for this target. 15594X86TargetLowering::ConstraintType 15595X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15596 if (Constraint.size() == 1) { 15597 switch (Constraint[0]) { 15598 case 'R': 15599 case 'q': 15600 case 'Q': 15601 case 'f': 15602 case 't': 15603 case 'u': 15604 case 'y': 15605 case 'x': 15606 case 'Y': 15607 case 'l': 15608 return C_RegisterClass; 15609 case 'a': 15610 case 'b': 15611 case 'c': 15612 case 'd': 15613 case 'S': 15614 case 'D': 15615 case 'A': 15616 return C_Register; 15617 case 'I': 15618 case 'J': 15619 case 'K': 15620 case 'L': 15621 case 'M': 15622 case 'N': 15623 case 'G': 15624 case 'C': 15625 case 'e': 15626 case 'Z': 15627 return C_Other; 15628 default: 15629 break; 15630 } 15631 } 15632 return TargetLowering::getConstraintType(Constraint); 15633} 15634 15635/// Examine constraint type and operand type and determine a weight value. 15636/// This object must already have been set up with the operand type 15637/// and the current alternative constraint selected. 15638TargetLowering::ConstraintWeight 15639 X86TargetLowering::getSingleConstraintMatchWeight( 15640 AsmOperandInfo &info, const char *constraint) const { 15641 ConstraintWeight weight = CW_Invalid; 15642 Value *CallOperandVal = info.CallOperandVal; 15643 // If we don't have a value, we can't do a match, 15644 // but allow it at the lowest weight. 15645 if (CallOperandVal == NULL) 15646 return CW_Default; 15647 Type *type = CallOperandVal->getType(); 15648 // Look at the constraint type. 15649 switch (*constraint) { 15650 default: 15651 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15652 case 'R': 15653 case 'q': 15654 case 'Q': 15655 case 'a': 15656 case 'b': 15657 case 'c': 15658 case 'd': 15659 case 'S': 15660 case 'D': 15661 case 'A': 15662 if (CallOperandVal->getType()->isIntegerTy()) 15663 weight = CW_SpecificReg; 15664 break; 15665 case 'f': 15666 case 't': 15667 case 'u': 15668 if (type->isFloatingPointTy()) 15669 weight = CW_SpecificReg; 15670 break; 15671 case 'y': 15672 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15673 weight = CW_SpecificReg; 15674 break; 15675 case 'x': 15676 case 'Y': 15677 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15678 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15679 weight = CW_Register; 15680 break; 15681 case 'I': 15682 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15683 if (C->getZExtValue() <= 31) 15684 weight = CW_Constant; 15685 } 15686 break; 15687 case 'J': 15688 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15689 if (C->getZExtValue() <= 63) 15690 weight = CW_Constant; 15691 } 15692 break; 15693 case 'K': 15694 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15695 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15696 weight = CW_Constant; 15697 } 15698 break; 15699 case 'L': 15700 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15701 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15702 weight = CW_Constant; 15703 } 15704 break; 15705 case 'M': 15706 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15707 if (C->getZExtValue() <= 3) 15708 weight = CW_Constant; 15709 } 15710 break; 15711 case 'N': 15712 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15713 if (C->getZExtValue() <= 0xff) 15714 weight = CW_Constant; 15715 } 15716 break; 15717 case 'G': 15718 case 'C': 15719 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15720 weight = CW_Constant; 15721 } 15722 break; 15723 case 'e': 15724 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15725 if ((C->getSExtValue() >= -0x80000000LL) && 15726 (C->getSExtValue() <= 0x7fffffffLL)) 15727 weight = CW_Constant; 15728 } 15729 break; 15730 case 'Z': 15731 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15732 if (C->getZExtValue() <= 0xffffffff) 15733 weight = CW_Constant; 15734 } 15735 break; 15736 } 15737 return weight; 15738} 15739 15740/// LowerXConstraint - try to replace an X constraint, which matches anything, 15741/// with another that has more specific requirements based on the type of the 15742/// corresponding operand. 15743const char *X86TargetLowering:: 15744LowerXConstraint(EVT ConstraintVT) const { 15745 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15746 // 'f' like normal targets. 15747 if (ConstraintVT.isFloatingPoint()) { 15748 if (Subtarget->hasSSE2()) 15749 return "Y"; 15750 if (Subtarget->hasSSE1()) 15751 return "x"; 15752 } 15753 15754 return TargetLowering::LowerXConstraint(ConstraintVT); 15755} 15756 15757/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15758/// vector. If it is invalid, don't add anything to Ops. 15759void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15760 std::string &Constraint, 15761 std::vector<SDValue>&Ops, 15762 SelectionDAG &DAG) const { 15763 SDValue Result(0, 0); 15764 15765 // Only support length 1 constraints for now. 15766 if (Constraint.length() > 1) return; 15767 15768 char ConstraintLetter = Constraint[0]; 15769 switch (ConstraintLetter) { 15770 default: break; 15771 case 'I': 15772 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15773 if (C->getZExtValue() <= 31) { 15774 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15775 break; 15776 } 15777 } 15778 return; 15779 case 'J': 15780 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15781 if (C->getZExtValue() <= 63) { 15782 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15783 break; 15784 } 15785 } 15786 return; 15787 case 'K': 15788 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15789 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15790 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15791 break; 15792 } 15793 } 15794 return; 15795 case 'N': 15796 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15797 if (C->getZExtValue() <= 255) { 15798 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15799 break; 15800 } 15801 } 15802 return; 15803 case 'e': { 15804 // 32-bit signed value 15805 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15806 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15807 C->getSExtValue())) { 15808 // Widen to 64 bits here to get it sign extended. 15809 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15810 break; 15811 } 15812 // FIXME gcc accepts some relocatable values here too, but only in certain 15813 // memory models; it's complicated. 15814 } 15815 return; 15816 } 15817 case 'Z': { 15818 // 32-bit unsigned value 15819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15820 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15821 C->getZExtValue())) { 15822 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15823 break; 15824 } 15825 } 15826 // FIXME gcc accepts some relocatable values here too, but only in certain 15827 // memory models; it's complicated. 15828 return; 15829 } 15830 case 'i': { 15831 // Literal immediates are always ok. 15832 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15833 // Widen to 64 bits here to get it sign extended. 15834 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15835 break; 15836 } 15837 15838 // In any sort of PIC mode addresses need to be computed at runtime by 15839 // adding in a register or some sort of table lookup. These can't 15840 // be used as immediates. 15841 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15842 return; 15843 15844 // If we are in non-pic codegen mode, we allow the address of a global (with 15845 // an optional displacement) to be used with 'i'. 15846 GlobalAddressSDNode *GA = 0; 15847 int64_t Offset = 0; 15848 15849 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15850 while (1) { 15851 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15852 Offset += GA->getOffset(); 15853 break; 15854 } else if (Op.getOpcode() == ISD::ADD) { 15855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15856 Offset += C->getZExtValue(); 15857 Op = Op.getOperand(0); 15858 continue; 15859 } 15860 } else if (Op.getOpcode() == ISD::SUB) { 15861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15862 Offset += -C->getZExtValue(); 15863 Op = Op.getOperand(0); 15864 continue; 15865 } 15866 } 15867 15868 // Otherwise, this isn't something we can handle, reject it. 15869 return; 15870 } 15871 15872 const GlobalValue *GV = GA->getGlobal(); 15873 // If we require an extra load to get this address, as in PIC mode, we 15874 // can't accept it. 15875 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15876 getTargetMachine()))) 15877 return; 15878 15879 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15880 GA->getValueType(0), Offset); 15881 break; 15882 } 15883 } 15884 15885 if (Result.getNode()) { 15886 Ops.push_back(Result); 15887 return; 15888 } 15889 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15890} 15891 15892std::pair<unsigned, const TargetRegisterClass*> 15893X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15894 EVT VT) const { 15895 // First, see if this is a constraint that directly corresponds to an LLVM 15896 // register class. 15897 if (Constraint.size() == 1) { 15898 // GCC Constraint Letters 15899 switch (Constraint[0]) { 15900 default: break; 15901 // TODO: Slight differences here in allocation order and leaving 15902 // RIP in the class. Do they matter any more here than they do 15903 // in the normal allocation? 15904 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15905 if (Subtarget->is64Bit()) { 15906 if (VT == MVT::i32 || VT == MVT::f32) 15907 return std::make_pair(0U, &X86::GR32RegClass); 15908 if (VT == MVT::i16) 15909 return std::make_pair(0U, &X86::GR16RegClass); 15910 if (VT == MVT::i8 || VT == MVT::i1) 15911 return std::make_pair(0U, &X86::GR8RegClass); 15912 if (VT == MVT::i64 || VT == MVT::f64) 15913 return std::make_pair(0U, &X86::GR64RegClass); 15914 break; 15915 } 15916 // 32-bit fallthrough 15917 case 'Q': // Q_REGS 15918 if (VT == MVT::i32 || VT == MVT::f32) 15919 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 15920 if (VT == MVT::i16) 15921 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 15922 if (VT == MVT::i8 || VT == MVT::i1) 15923 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 15924 if (VT == MVT::i64) 15925 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 15926 break; 15927 case 'r': // GENERAL_REGS 15928 case 'l': // INDEX_REGS 15929 if (VT == MVT::i8 || VT == MVT::i1) 15930 return std::make_pair(0U, &X86::GR8RegClass); 15931 if (VT == MVT::i16) 15932 return std::make_pair(0U, &X86::GR16RegClass); 15933 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15934 return std::make_pair(0U, &X86::GR32RegClass); 15935 return std::make_pair(0U, &X86::GR64RegClass); 15936 case 'R': // LEGACY_REGS 15937 if (VT == MVT::i8 || VT == MVT::i1) 15938 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 15939 if (VT == MVT::i16) 15940 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 15941 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15942 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 15943 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 15944 case 'f': // FP Stack registers. 15945 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15946 // value to the correct fpstack register class. 15947 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15948 return std::make_pair(0U, &X86::RFP32RegClass); 15949 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15950 return std::make_pair(0U, &X86::RFP64RegClass); 15951 return std::make_pair(0U, &X86::RFP80RegClass); 15952 case 'y': // MMX_REGS if MMX allowed. 15953 if (!Subtarget->hasMMX()) break; 15954 return std::make_pair(0U, &X86::VR64RegClass); 15955 case 'Y': // SSE_REGS if SSE2 allowed 15956 if (!Subtarget->hasSSE2()) break; 15957 // FALL THROUGH. 15958 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15959 if (!Subtarget->hasSSE1()) break; 15960 15961 switch (VT.getSimpleVT().SimpleTy) { 15962 default: break; 15963 // Scalar SSE types. 15964 case MVT::f32: 15965 case MVT::i32: 15966 return std::make_pair(0U, &X86::FR32RegClass); 15967 case MVT::f64: 15968 case MVT::i64: 15969 return std::make_pair(0U, &X86::FR64RegClass); 15970 // Vector types. 15971 case MVT::v16i8: 15972 case MVT::v8i16: 15973 case MVT::v4i32: 15974 case MVT::v2i64: 15975 case MVT::v4f32: 15976 case MVT::v2f64: 15977 return std::make_pair(0U, &X86::VR128RegClass); 15978 // AVX types. 15979 case MVT::v32i8: 15980 case MVT::v16i16: 15981 case MVT::v8i32: 15982 case MVT::v4i64: 15983 case MVT::v8f32: 15984 case MVT::v4f64: 15985 return std::make_pair(0U, &X86::VR256RegClass); 15986 } 15987 break; 15988 } 15989 } 15990 15991 // Use the default implementation in TargetLowering to convert the register 15992 // constraint into a member of a register class. 15993 std::pair<unsigned, const TargetRegisterClass*> Res; 15994 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15995 15996 // Not found as a standard register? 15997 if (Res.second == 0) { 15998 // Map st(0) -> st(7) -> ST0 15999 if (Constraint.size() == 7 && Constraint[0] == '{' && 16000 tolower(Constraint[1]) == 's' && 16001 tolower(Constraint[2]) == 't' && 16002 Constraint[3] == '(' && 16003 (Constraint[4] >= '0' && Constraint[4] <= '7') && 16004 Constraint[5] == ')' && 16005 Constraint[6] == '}') { 16006 16007 Res.first = X86::ST0+Constraint[4]-'0'; 16008 Res.second = &X86::RFP80RegClass; 16009 return Res; 16010 } 16011 16012 // GCC allows "st(0)" to be called just plain "st". 16013 if (StringRef("{st}").equals_lower(Constraint)) { 16014 Res.first = X86::ST0; 16015 Res.second = &X86::RFP80RegClass; 16016 return Res; 16017 } 16018 16019 // flags -> EFLAGS 16020 if (StringRef("{flags}").equals_lower(Constraint)) { 16021 Res.first = X86::EFLAGS; 16022 Res.second = &X86::CCRRegClass; 16023 return Res; 16024 } 16025 16026 // 'A' means EAX + EDX. 16027 if (Constraint == "A") { 16028 Res.first = X86::EAX; 16029 Res.second = &X86::GR32_ADRegClass; 16030 return Res; 16031 } 16032 return Res; 16033 } 16034 16035 // Otherwise, check to see if this is a register class of the wrong value 16036 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 16037 // turn into {ax},{dx}. 16038 if (Res.second->hasType(VT)) 16039 return Res; // Correct type already, nothing to do. 16040 16041 // All of the single-register GCC register classes map their values onto 16042 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 16043 // really want an 8-bit or 32-bit register, map to the appropriate register 16044 // class and return the appropriate register. 16045 if (Res.second == &X86::GR16RegClass) { 16046 if (VT == MVT::i8) { 16047 unsigned DestReg = 0; 16048 switch (Res.first) { 16049 default: break; 16050 case X86::AX: DestReg = X86::AL; break; 16051 case X86::DX: DestReg = X86::DL; break; 16052 case X86::CX: DestReg = X86::CL; break; 16053 case X86::BX: DestReg = X86::BL; break; 16054 } 16055 if (DestReg) { 16056 Res.first = DestReg; 16057 Res.second = &X86::GR8RegClass; 16058 } 16059 } else if (VT == MVT::i32) { 16060 unsigned DestReg = 0; 16061 switch (Res.first) { 16062 default: break; 16063 case X86::AX: DestReg = X86::EAX; break; 16064 case X86::DX: DestReg = X86::EDX; break; 16065 case X86::CX: DestReg = X86::ECX; break; 16066 case X86::BX: DestReg = X86::EBX; break; 16067 case X86::SI: DestReg = X86::ESI; break; 16068 case X86::DI: DestReg = X86::EDI; break; 16069 case X86::BP: DestReg = X86::EBP; break; 16070 case X86::SP: DestReg = X86::ESP; break; 16071 } 16072 if (DestReg) { 16073 Res.first = DestReg; 16074 Res.second = &X86::GR32RegClass; 16075 } 16076 } else if (VT == MVT::i64) { 16077 unsigned DestReg = 0; 16078 switch (Res.first) { 16079 default: break; 16080 case X86::AX: DestReg = X86::RAX; break; 16081 case X86::DX: DestReg = X86::RDX; break; 16082 case X86::CX: DestReg = X86::RCX; break; 16083 case X86::BX: DestReg = X86::RBX; break; 16084 case X86::SI: DestReg = X86::RSI; break; 16085 case X86::DI: DestReg = X86::RDI; break; 16086 case X86::BP: DestReg = X86::RBP; break; 16087 case X86::SP: DestReg = X86::RSP; break; 16088 } 16089 if (DestReg) { 16090 Res.first = DestReg; 16091 Res.second = &X86::GR64RegClass; 16092 } 16093 } 16094 } else if (Res.second == &X86::FR32RegClass || 16095 Res.second == &X86::FR64RegClass || 16096 Res.second == &X86::VR128RegClass) { 16097 // Handle references to XMM physical registers that got mapped into the 16098 // wrong class. This can happen with constraints like {xmm0} where the 16099 // target independent register mapper will just pick the first match it can 16100 // find, ignoring the required type. 16101 if (VT == MVT::f32) 16102 Res.second = &X86::FR32RegClass; 16103 else if (VT == MVT::f64) 16104 Res.second = &X86::FR64RegClass; 16105 else if (X86::VR128RegClass.hasType(VT)) 16106 Res.second = &X86::VR128RegClass; 16107 } 16108 16109 return Res; 16110} 16111