X86ISelLowering.cpp revision 29582d1223d2cd851e136bfe39c508930c4b5592
1f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// 3f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// The LLVM Compiler Infrastructure 4f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// 5f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// This file is distributed under the University of Illinois Open Source 6f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// License. See LICENSE.TXT for details. 7f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// 8f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette//===----------------------------------------------------------------------===// 9f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// 10f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// This file defines the interfaces that X86 uses to lower LLVM code into a 11f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// selection DAG. 12f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// 13f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette//===----------------------------------------------------------------------===// 14f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 15f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "X86.h" 16f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "X86InstrBuilder.h" 17f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "X86ISelLowering.h" 18f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "X86MachineFunctionInfo.h" 19f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "X86TargetMachine.h" 20f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CallingConv.h" 21f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Constants.h" 22f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/DerivedTypes.h" 23f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/GlobalVariable.h" 24f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Function.h" 25f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Intrinsics.h" 26f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/ADT/BitVector.h" 27f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/ADT/VectorExtras.h" 28f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/CallingConvLower.h" 29f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/MachineFrameInfo.h" 30f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/MachineFunction.h" 31f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/MachineInstrBuilder.h" 32f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/MachineModuleInfo.h" 33f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/MachineRegisterInfo.h" 34f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/PseudoSourceValue.h" 35f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/CodeGen/SelectionDAG.h" 36f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Support/MathExtras.h" 37f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Support/Debug.h" 38f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Target/TargetOptions.h" 39f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/ADT/SmallSet.h" 40f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/ADT/StringExtras.h" 41f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette#include "llvm/Support/CommandLine.h" 42f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viveretteusing namespace llvm; 43f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 44f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverettestatic cl::opt<bool> 45f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan ViveretteDisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 46f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 47f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette// Forward declarations. 48f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverettestatic SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl); 49f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 50f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan ViveretteX86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 51f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette : TargetLowering(TM) { 52f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette Subtarget = &TM.getSubtarget<X86Subtarget>(); 53f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette X86ScalarSSEf64 = Subtarget->hasSSE2(); 54f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette X86ScalarSSEf32 = Subtarget->hasSSE1(); 55f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 56f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 57f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette bool Fast = false; 58f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 59f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette RegInfo = TM.getRegisterInfo(); 60f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette TD = getTargetData(); 61f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 62f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // Set up the TargetLowering object. 63f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 64f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // X86 is weird, it always uses i8 for shift amounts and setcc results. 65f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setShiftAmountType(MVT::i8); 66f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setBooleanContents(ZeroOrOneBooleanContent); 67f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setSchedulingPreference(SchedulingForRegPressure); 68f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 69f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setStackPointerRegisterToSaveRestore(X86StackPtr); 70f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 71f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette if (Subtarget->isTargetDarwin()) { 72f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 73f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setUseUnderscoreSetJmp(false); 74f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setUseUnderscoreLongJmp(false); 75f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette } else if (Subtarget->isTargetMingw()) { 76f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // MS runtime is weird: it exports _setjmp, but longjmp! 77f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setUseUnderscoreSetJmp(true); 78f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setUseUnderscoreLongJmp(false); 79f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette } else { 80f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setUseUnderscoreSetJmp(true); 81f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setUseUnderscoreLongJmp(true); 82f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette } 83f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 84f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // Set up the register classes. 85f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette addRegisterClass(MVT::i8, X86::GR8RegisterClass); 86f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette addRegisterClass(MVT::i16, X86::GR16RegisterClass); 87f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette addRegisterClass(MVT::i32, X86::GR32RegisterClass); 88f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette if (Subtarget->is64Bit()) 89f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette addRegisterClass(MVT::i64, X86::GR64RegisterClass); 90f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 91f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 92f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 93f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // We don't accept any truncstore of integer registers. 94f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setTruncStoreAction(MVT::i64, MVT::i32, Expand); 95f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setTruncStoreAction(MVT::i64, MVT::i16, Expand); 96f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 97f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setTruncStoreAction(MVT::i32, MVT::i16, Expand); 98f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 99f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setTruncStoreAction(MVT::i16, MVT::i8, Expand); 100f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 101f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // SETOEQ and SETUNE require checking two conditions. 102f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 103f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 104f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 105f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 106f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 107f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 108f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 109f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 110f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // operation. 111f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 112f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 113f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 114f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 115f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette if (Subtarget->is64Bit()) { 116f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 117f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 118f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette } else { 119f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette if (X86ScalarSSEf64) { 120f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // We have an impenetrably clever algorithm for ui64->double only. 121f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 122f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 123f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // We have faster algorithm for ui32->single only. 124f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 125f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette } else 126f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 127f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette } 128f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette 129f11879ae94e7598cb6ae59fdc13104947b66e3e6Alan Viverette // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 130 // this operation. 131 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 132 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 133 // SSE has no i16 to fp conversion, only i32 134 if (X86ScalarSSEf32) { 135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 136 // f32 and f64 cases are Legal, f80 case is not 137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 138 } else { 139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 141 } 142 143 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 144 // are Legal, f80 is custom lowered. 145 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 146 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 147 148 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 149 // this operation. 150 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 151 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 152 153 if (X86ScalarSSEf32) { 154 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 155 // f32 and f64 cases are Legal, f80 case is not 156 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 157 } else { 158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 159 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 160 } 161 162 // Handle FP_TO_UINT by promoting the destination to a larger signed 163 // conversion. 164 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 165 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 166 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 167 168 if (Subtarget->is64Bit()) { 169 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 170 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 171 } else { 172 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 173 // Expand FP_TO_UINT into a select. 174 // FIXME: We would like to use a Custom expander here eventually to do 175 // the optimal thing for SSE vs. the default expansion in the legalizer. 176 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 177 else 178 // With SSE3 we can use fisttpll to convert to a signed i64. 179 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 180 } 181 182 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 183 if (!X86ScalarSSEf64) { 184 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 185 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 186 } 187 188 // Scalar integer divide and remainder are lowered to use operations that 189 // produce two results, to match the available instructions. This exposes 190 // the two-result form to trivial CSE, which is able to combine x/y and x%y 191 // into a single instruction. 192 // 193 // Scalar integer multiply-high is also lowered to use two-result 194 // operations, to match the available instructions. However, plain multiply 195 // (low) operations are left as Legal, as there are single-result 196 // instructions for this in x86. Using the two-result multiply instructions 197 // when both high and low results are needed must be arranged by dagcombine. 198 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 199 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 200 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 201 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 202 setOperationAction(ISD::SREM , MVT::i8 , Expand); 203 setOperationAction(ISD::UREM , MVT::i8 , Expand); 204 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 205 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 206 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 207 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 208 setOperationAction(ISD::SREM , MVT::i16 , Expand); 209 setOperationAction(ISD::UREM , MVT::i16 , Expand); 210 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 211 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 212 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 213 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 214 setOperationAction(ISD::SREM , MVT::i32 , Expand); 215 setOperationAction(ISD::UREM , MVT::i32 , Expand); 216 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 217 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 218 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 219 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 220 setOperationAction(ISD::SREM , MVT::i64 , Expand); 221 setOperationAction(ISD::UREM , MVT::i64 , Expand); 222 223 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 224 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 225 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 226 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 227 if (Subtarget->is64Bit()) 228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 232 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 233 setOperationAction(ISD::FREM , MVT::f32 , Expand); 234 setOperationAction(ISD::FREM , MVT::f64 , Expand); 235 setOperationAction(ISD::FREM , MVT::f80 , Expand); 236 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 237 238 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 239 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 240 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 241 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 242 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 243 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 244 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 245 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 246 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 247 if (Subtarget->is64Bit()) { 248 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 249 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 250 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 251 } 252 253 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 254 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 255 256 // These should be promoted to a larger select which is supported. 257 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 258 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 259 // X86 wants to expand cmov itself. 260 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 261 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 262 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 263 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 264 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 265 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 266 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 267 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 268 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 269 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 270 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 271 if (Subtarget->is64Bit()) { 272 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 273 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 274 } 275 // X86 ret instruction may pop stack. 276 setOperationAction(ISD::RET , MVT::Other, Custom); 277 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 278 279 // Darwin ABI issue. 280 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 281 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 282 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 284 if (Subtarget->is64Bit()) 285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 286 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 287 if (Subtarget->is64Bit()) { 288 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 289 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 290 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 291 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 292 } 293 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 294 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 295 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 296 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 297 if (Subtarget->is64Bit()) { 298 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 299 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 300 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 301 } 302 303 if (Subtarget->hasSSE1()) 304 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 305 306 if (!Subtarget->hasSSE2()) 307 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 308 309 // Expand certain atomics 310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 314 315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 319 320 if (!Subtarget->is64Bit()) { 321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 327 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 328 } 329 330 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. 331 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 332 // FIXME - use subtarget debug flags 333 if (!Subtarget->isTargetDarwin() && 334 !Subtarget->isTargetELF() && 335 !Subtarget->isTargetCygMing()) { 336 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 337 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 338 } 339 340 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 341 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 342 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 343 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 344 if (Subtarget->is64Bit()) { 345 setExceptionPointerRegister(X86::RAX); 346 setExceptionSelectorRegister(X86::RDX); 347 } else { 348 setExceptionPointerRegister(X86::EAX); 349 setExceptionSelectorRegister(X86::EDX); 350 } 351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 352 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 353 354 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 355 356 setOperationAction(ISD::TRAP, MVT::Other, Legal); 357 358 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 359 setOperationAction(ISD::VASTART , MVT::Other, Custom); 360 setOperationAction(ISD::VAEND , MVT::Other, Expand); 361 if (Subtarget->is64Bit()) { 362 setOperationAction(ISD::VAARG , MVT::Other, Custom); 363 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 364 } else { 365 setOperationAction(ISD::VAARG , MVT::Other, Expand); 366 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 367 } 368 369 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 370 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 371 if (Subtarget->is64Bit()) 372 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 373 if (Subtarget->isTargetCygMing()) 374 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 375 else 376 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 377 378 if (!UseSoftFloat && X86ScalarSSEf64) { 379 // f32 and f64 use SSE. 380 // Set up the FP register classes. 381 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 382 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 383 384 // Use ANDPD to simulate FABS. 385 setOperationAction(ISD::FABS , MVT::f64, Custom); 386 setOperationAction(ISD::FABS , MVT::f32, Custom); 387 388 // Use XORP to simulate FNEG. 389 setOperationAction(ISD::FNEG , MVT::f64, Custom); 390 setOperationAction(ISD::FNEG , MVT::f32, Custom); 391 392 // Use ANDPD and ORPD to simulate FCOPYSIGN. 393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 395 396 // We don't support sin/cos/fmod 397 setOperationAction(ISD::FSIN , MVT::f64, Expand); 398 setOperationAction(ISD::FCOS , MVT::f64, Expand); 399 setOperationAction(ISD::FSIN , MVT::f32, Expand); 400 setOperationAction(ISD::FCOS , MVT::f32, Expand); 401 402 // Expand FP immediates into loads from the stack, except for the special 403 // cases we handle. 404 addLegalFPImmediate(APFloat(+0.0)); // xorpd 405 addLegalFPImmediate(APFloat(+0.0f)); // xorps 406 407 // Floating truncations from f80 and extensions to f80 go through memory. 408 // If optimizing, we lie about this though and handle it in 409 // InstructionSelectPreprocess so that dagcombine2 can hack on these. 410 if (Fast) { 411 setConvertAction(MVT::f32, MVT::f80, Expand); 412 setConvertAction(MVT::f64, MVT::f80, Expand); 413 setConvertAction(MVT::f80, MVT::f32, Expand); 414 setConvertAction(MVT::f80, MVT::f64, Expand); 415 } 416 } else if (!UseSoftFloat && X86ScalarSSEf32) { 417 // Use SSE for f32, x87 for f64. 418 // Set up the FP register classes. 419 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 421 422 // Use ANDPS to simulate FABS. 423 setOperationAction(ISD::FABS , MVT::f32, Custom); 424 425 // Use XORP to simulate FNEG. 426 setOperationAction(ISD::FNEG , MVT::f32, Custom); 427 428 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 429 430 // Use ANDPS and ORPS to simulate FCOPYSIGN. 431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 433 434 // We don't support sin/cos/fmod 435 setOperationAction(ISD::FSIN , MVT::f32, Expand); 436 setOperationAction(ISD::FCOS , MVT::f32, Expand); 437 438 // Special cases we handle for FP constants. 439 addLegalFPImmediate(APFloat(+0.0f)); // xorps 440 addLegalFPImmediate(APFloat(+0.0)); // FLD0 441 addLegalFPImmediate(APFloat(+1.0)); // FLD1 442 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 443 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 444 445 // SSE <-> X87 conversions go through memory. If optimizing, we lie about 446 // this though and handle it in InstructionSelectPreprocess so that 447 // dagcombine2 can hack on these. 448 if (Fast) { 449 setConvertAction(MVT::f32, MVT::f64, Expand); 450 setConvertAction(MVT::f32, MVT::f80, Expand); 451 setConvertAction(MVT::f80, MVT::f32, Expand); 452 setConvertAction(MVT::f64, MVT::f32, Expand); 453 // And x87->x87 truncations also. 454 setConvertAction(MVT::f80, MVT::f64, Expand); 455 } 456 457 if (!UnsafeFPMath) { 458 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 459 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 460 } 461 } else if (!UseSoftFloat) { 462 // f32 and f64 in x87. 463 // Set up the FP register classes. 464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 466 467 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 468 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 471 472 // Floating truncations go through memory. If optimizing, we lie about 473 // this though and handle it in InstructionSelectPreprocess so that 474 // dagcombine2 can hack on these. 475 if (Fast) { 476 setConvertAction(MVT::f80, MVT::f32, Expand); 477 setConvertAction(MVT::f64, MVT::f32, Expand); 478 setConvertAction(MVT::f80, MVT::f64, Expand); 479 } 480 481 if (!UnsafeFPMath) { 482 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 483 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 484 } 485 addLegalFPImmediate(APFloat(+0.0)); // FLD0 486 addLegalFPImmediate(APFloat(+1.0)); // FLD1 487 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 488 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 489 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 490 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 491 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 492 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 493 } 494 495 // Long double always uses X87. 496 if (!UseSoftFloat) { 497 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 498 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 499 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 500 { 501 bool ignored; 502 APFloat TmpFlt(+0.0); 503 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 504 &ignored); 505 addLegalFPImmediate(TmpFlt); // FLD0 506 TmpFlt.changeSign(); 507 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 508 APFloat TmpFlt2(+1.0); 509 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 510 &ignored); 511 addLegalFPImmediate(TmpFlt2); // FLD1 512 TmpFlt2.changeSign(); 513 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 514 } 515 516 if (!UnsafeFPMath) { 517 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 518 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 519 } 520 } 521 522 // Always use a library call for pow. 523 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 524 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 525 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 526 527 setOperationAction(ISD::FLOG, MVT::f80, Expand); 528 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 529 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 530 setOperationAction(ISD::FEXP, MVT::f80, Expand); 531 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 532 533 // First set operation action for all vector types to either promote 534 // (for widening) or expand (for scalarization). Then we will selectively 535 // turn on ones that can be effectively codegen'd. 536 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 537 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 538 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 539 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 540 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 541 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 542 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 543 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 546 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 547 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 548 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 549 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 550 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 551 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 553 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 581 } 582 583 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 584 // with -msoft-float, disable use of MMX as well. 585 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 586 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 587 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 588 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 589 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 590 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 591 592 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 593 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 594 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 595 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 596 597 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 598 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 599 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 600 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 601 602 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 603 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 604 605 setOperationAction(ISD::AND, MVT::v8i8, Promote); 606 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 607 setOperationAction(ISD::AND, MVT::v4i16, Promote); 608 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 609 setOperationAction(ISD::AND, MVT::v2i32, Promote); 610 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 611 setOperationAction(ISD::AND, MVT::v1i64, Legal); 612 613 setOperationAction(ISD::OR, MVT::v8i8, Promote); 614 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 615 setOperationAction(ISD::OR, MVT::v4i16, Promote); 616 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 617 setOperationAction(ISD::OR, MVT::v2i32, Promote); 618 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 619 setOperationAction(ISD::OR, MVT::v1i64, Legal); 620 621 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 622 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 623 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 624 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 625 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 626 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 627 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 628 629 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 630 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 631 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 632 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 633 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 634 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 635 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 636 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 637 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 638 639 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 640 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 641 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 642 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 643 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 644 645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 647 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 648 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 649 650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 652 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 653 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 654 655 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 656 657 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); 658 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); 659 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 660 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 661 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 662 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 663 } 664 665 if (!UseSoftFloat && Subtarget->hasSSE1()) { 666 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 667 668 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 669 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 670 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 671 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 672 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 673 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 674 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 675 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 677 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 678 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 679 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 680 } 681 682 if (!UseSoftFloat && Subtarget->hasSSE2()) { 683 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 684 685 // FIXME: Unfortunately -soft-float means XMM registers cannot be used even 686 // for integer operations. 687 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 688 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 689 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 690 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 691 692 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 693 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 694 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 695 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 696 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 697 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 698 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 699 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 700 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 701 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 702 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 703 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 704 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 705 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 706 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 707 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 708 709 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 710 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 711 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 712 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 713 714 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 715 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 716 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 717 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 718 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 719 720 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 721 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 722 MVT VT = (MVT::SimpleValueType)i; 723 // Do not attempt to custom lower non-power-of-2 vectors 724 if (!isPowerOf2_32(VT.getVectorNumElements())) 725 continue; 726 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 727 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 728 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 729 } 730 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 731 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 732 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 733 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 734 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 735 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 736 if (Subtarget->is64Bit()) { 737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 738 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 739 } 740 741 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 742 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 743 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote); 744 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64); 745 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote); 746 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64); 747 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote); 748 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64); 749 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote); 750 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64); 751 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote); 752 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64); 753 } 754 755 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 756 757 // Custom lower v2i64 and v2f64 selects. 758 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 759 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 760 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 761 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 762 763 } 764 765 if (Subtarget->hasSSE41()) { 766 // FIXME: Do we need to handle scalar-to-vector here? 767 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 768 769 // i8 and i16 vectors are custom , because the source register and source 770 // source memory operand types are not the same width. f32 vectors are 771 // custom since the immediate controlling the insert encodes additional 772 // information. 773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 774 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 775 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 776 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 777 778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 782 783 if (Subtarget->is64Bit()) { 784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 785 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 786 } 787 } 788 789 if (Subtarget->hasSSE42()) { 790 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 791 } 792 793 // We want to custom lower some of our intrinsics. 794 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 795 796 // Add/Sub/Mul with overflow operations are custom lowered. 797 setOperationAction(ISD::SADDO, MVT::i32, Custom); 798 setOperationAction(ISD::SADDO, MVT::i64, Custom); 799 setOperationAction(ISD::UADDO, MVT::i32, Custom); 800 setOperationAction(ISD::UADDO, MVT::i64, Custom); 801 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 802 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 803 setOperationAction(ISD::USUBO, MVT::i32, Custom); 804 setOperationAction(ISD::USUBO, MVT::i64, Custom); 805 setOperationAction(ISD::SMULO, MVT::i32, Custom); 806 setOperationAction(ISD::SMULO, MVT::i64, Custom); 807 setOperationAction(ISD::UMULO, MVT::i32, Custom); 808 setOperationAction(ISD::UMULO, MVT::i64, Custom); 809 810 // We have target-specific dag combine patterns for the following nodes: 811 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 812 setTargetDAGCombine(ISD::BUILD_VECTOR); 813 setTargetDAGCombine(ISD::SELECT); 814 setTargetDAGCombine(ISD::SHL); 815 setTargetDAGCombine(ISD::SRA); 816 setTargetDAGCombine(ISD::SRL); 817 setTargetDAGCombine(ISD::STORE); 818 819 computeRegisterProperties(); 820 821 // FIXME: These should be based on subtarget info. Plus, the values should 822 // be smaller when we are in optimizing for size mode. 823 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 824 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 825 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 826 allowUnalignedMemoryAccesses = true; // x86 supports it! 827 setPrefLoopAlignment(16); 828} 829 830 831MVT X86TargetLowering::getSetCCResultType(MVT VT) const { 832 return MVT::i8; 833} 834 835 836/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 837/// the desired ByVal argument alignment. 838static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 839 if (MaxAlign == 16) 840 return; 841 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 842 if (VTy->getBitWidth() == 128) 843 MaxAlign = 16; 844 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 845 unsigned EltAlign = 0; 846 getMaxByValAlign(ATy->getElementType(), EltAlign); 847 if (EltAlign > MaxAlign) 848 MaxAlign = EltAlign; 849 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 850 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 851 unsigned EltAlign = 0; 852 getMaxByValAlign(STy->getElementType(i), EltAlign); 853 if (EltAlign > MaxAlign) 854 MaxAlign = EltAlign; 855 if (MaxAlign == 16) 856 break; 857 } 858 } 859 return; 860} 861 862/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 863/// function arguments in the caller parameter area. For X86, aggregates 864/// that contain SSE vectors are placed at 16-byte boundaries while the rest 865/// are at 4-byte boundaries. 866unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 867 if (Subtarget->is64Bit()) { 868 // Max of 8 and alignment of type. 869 unsigned TyAlign = TD->getABITypeAlignment(Ty); 870 if (TyAlign > 8) 871 return TyAlign; 872 return 8; 873 } 874 875 unsigned Align = 4; 876 if (Subtarget->hasSSE1()) 877 getMaxByValAlign(Ty, Align); 878 return Align; 879} 880 881/// getOptimalMemOpType - Returns the target specific optimal type for load 882/// and store operations as a result of memset, memcpy, and memmove 883/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 884/// determining it. 885MVT 886X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 887 bool isSrcConst, bool isSrcStr) const { 888 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 889 // linux. This is because the stack realignment code can't handle certain 890 // cases like PR2962. This should be removed when PR2962 is fixed. 891 if (Subtarget->getStackAlignment() >= 16) { 892 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 893 return MVT::v4i32; 894 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 895 return MVT::v4f32; 896 } 897 if (Subtarget->is64Bit() && Size >= 8) 898 return MVT::i64; 899 return MVT::i32; 900} 901 902 903/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 904/// jumptable. 905SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 906 SelectionDAG &DAG) const { 907 if (usesGlobalOffsetTable()) 908 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 909 if (!Subtarget->isPICStyleRIPRel()) 910 // This doesn't have DebugLoc associated with it, but is not really the 911 // same as a Register. 912 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 913 getPointerTy()); 914 return Table; 915} 916 917//===----------------------------------------------------------------------===// 918// Return Value Calling Convention Implementation 919//===----------------------------------------------------------------------===// 920 921#include "X86GenCallingConv.inc" 922 923/// LowerRET - Lower an ISD::RET node. 924SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 925 DebugLoc dl = Op.getDebugLoc(); 926 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 927 928 SmallVector<CCValAssign, 16> RVLocs; 929 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 930 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 931 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 932 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86); 933 934 // If this is the first return lowered for this function, add the regs to the 935 // liveout set for the function. 936 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 937 for (unsigned i = 0; i != RVLocs.size(); ++i) 938 if (RVLocs[i].isRegLoc()) 939 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 940 } 941 SDValue Chain = Op.getOperand(0); 942 943 // Handle tail call return. 944 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); 945 if (Chain.getOpcode() == X86ISD::TAILCALL) { 946 SDValue TailCall = Chain; 947 SDValue TargetAddress = TailCall.getOperand(1); 948 SDValue StackAdjustment = TailCall.getOperand(2); 949 assert(((TargetAddress.getOpcode() == ISD::Register && 950 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX || 951 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || 952 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 953 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 954 "Expecting an global address, external symbol, or register"); 955 assert(StackAdjustment.getOpcode() == ISD::Constant && 956 "Expecting a const value"); 957 958 SmallVector<SDValue,8> Operands; 959 Operands.push_back(Chain.getOperand(0)); 960 Operands.push_back(TargetAddress); 961 Operands.push_back(StackAdjustment); 962 // Copy registers used by the call. Last operand is a flag so it is not 963 // copied. 964 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 965 Operands.push_back(Chain.getOperand(i)); 966 } 967 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0], 968 Operands.size()); 969 } 970 971 // Regular return. 972 SDValue Flag; 973 974 SmallVector<SDValue, 6> RetOps; 975 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 976 // Operand #1 = Bytes To Pop 977 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 978 979 // Copy the result values into the output registers. 980 for (unsigned i = 0; i != RVLocs.size(); ++i) { 981 CCValAssign &VA = RVLocs[i]; 982 assert(VA.isRegLoc() && "Can only return in registers!"); 983 SDValue ValToCopy = Op.getOperand(i*2+1); 984 985 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 986 // the RET instruction and handled by the FP Stackifier. 987 if (VA.getLocReg() == X86::ST0 || 988 VA.getLocReg() == X86::ST1) { 989 // If this is a copy from an xmm register to ST(0), use an FPExtend to 990 // change the value to the FP stack register class. 991 if (isScalarFPTypeInSSEReg(VA.getValVT())) 992 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 993 RetOps.push_back(ValToCopy); 994 // Don't emit a copytoreg. 995 continue; 996 } 997 998 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 999 // which is returned in RAX / RDX. 1000 if (Subtarget->is64Bit()) { 1001 MVT ValVT = ValToCopy.getValueType(); 1002 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1003 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1004 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1005 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1006 } 1007 } 1008 1009 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1010 Flag = Chain.getValue(1); 1011 } 1012 1013 // The x86-64 ABI for returning structs by value requires that we copy 1014 // the sret argument into %rax for the return. We saved the argument into 1015 // a virtual register in the entry block, so now we copy the value out 1016 // and into %rax. 1017 if (Subtarget->is64Bit() && 1018 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1019 MachineFunction &MF = DAG.getMachineFunction(); 1020 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1021 unsigned Reg = FuncInfo->getSRetReturnReg(); 1022 if (!Reg) { 1023 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1024 FuncInfo->setSRetReturnReg(Reg); 1025 } 1026 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1027 1028 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1029 Flag = Chain.getValue(1); 1030 } 1031 1032 RetOps[0] = Chain; // Update chain. 1033 1034 // Add the flag if we have it. 1035 if (Flag.getNode()) 1036 RetOps.push_back(Flag); 1037 1038 return DAG.getNode(X86ISD::RET_FLAG, dl, 1039 MVT::Other, &RetOps[0], RetOps.size()); 1040} 1041 1042 1043/// LowerCallResult - Lower the result values of an ISD::CALL into the 1044/// appropriate copies out of appropriate physical registers. This assumes that 1045/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 1046/// being lowered. The returns a SDNode with the same number of values as the 1047/// ISD::CALL. 1048SDNode *X86TargetLowering:: 1049LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 1050 unsigned CallingConv, SelectionDAG &DAG) { 1051 1052 DebugLoc dl = TheCall->getDebugLoc(); 1053 // Assign locations to each value returned by this call. 1054 SmallVector<CCValAssign, 16> RVLocs; 1055 bool isVarArg = TheCall->isVarArg(); 1056 bool Is64Bit = Subtarget->is64Bit(); 1057 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 1058 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); 1059 1060 SmallVector<SDValue, 8> ResultVals; 1061 1062 // Copy all of the result registers out of their specified physreg. 1063 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1064 CCValAssign &VA = RVLocs[i]; 1065 MVT CopyVT = VA.getValVT(); 1066 1067 // If this is x86-64, and we disabled SSE, we can't return FP values 1068 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1069 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) { 1070 cerr << "SSE register return with SSE disabled\n"; 1071 exit(1); 1072 } 1073 1074 // If this is a call to a function that returns an fp value on the floating 1075 // point stack, but where we prefer to use the value in xmm registers, copy 1076 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1077 if ((VA.getLocReg() == X86::ST0 || 1078 VA.getLocReg() == X86::ST1) && 1079 isScalarFPTypeInSSEReg(VA.getValVT())) { 1080 CopyVT = MVT::f80; 1081 } 1082 1083 SDValue Val; 1084 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1085 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1086 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1087 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1088 MVT::v2i64, InFlag).getValue(1); 1089 Val = Chain.getValue(0); 1090 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1091 Val, DAG.getConstant(0, MVT::i64)); 1092 } else { 1093 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1094 MVT::i64, InFlag).getValue(1); 1095 Val = Chain.getValue(0); 1096 } 1097 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1098 } else { 1099 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1100 CopyVT, InFlag).getValue(1); 1101 Val = Chain.getValue(0); 1102 } 1103 InFlag = Chain.getValue(2); 1104 1105 if (CopyVT != VA.getValVT()) { 1106 // Round the F80 the right size, which also moves to the appropriate xmm 1107 // register. 1108 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1109 // This truncation won't change the value. 1110 DAG.getIntPtrConstant(1)); 1111 } 1112 1113 ResultVals.push_back(Val); 1114 } 1115 1116 // Merge everything together with a MERGE_VALUES node. 1117 ResultVals.push_back(Chain); 1118 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), 1119 &ResultVals[0], ResultVals.size()).getNode(); 1120} 1121 1122 1123//===----------------------------------------------------------------------===// 1124// C & StdCall & Fast Calling Convention implementation 1125//===----------------------------------------------------------------------===// 1126// StdCall calling convention seems to be standard for many Windows' API 1127// routines and around. It differs from C calling convention just a little: 1128// callee should clean up the stack, not caller. Symbols should be also 1129// decorated in some fancy way :) It doesn't support any vector arguments. 1130// For info on fast calling convention see Fast Calling Convention (tail call) 1131// implementation LowerX86_32FastCCCallTo. 1132 1133/// AddLiveIn - This helper function adds the specified physical register to the 1134/// MachineFunction as a live in value. It also creates a corresponding virtual 1135/// register for it. 1136static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 1137 const TargetRegisterClass *RC) { 1138 assert(RC->contains(PReg) && "Not the correct regclass!"); 1139 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1140 MF.getRegInfo().addLiveIn(PReg, VReg); 1141 return VReg; 1142} 1143 1144/// CallIsStructReturn - Determines whether a CALL node uses struct return 1145/// semantics. 1146static bool CallIsStructReturn(CallSDNode *TheCall) { 1147 unsigned NumOps = TheCall->getNumArgs(); 1148 if (!NumOps) 1149 return false; 1150 1151 return TheCall->getArgFlags(0).isSRet(); 1152} 1153 1154/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct 1155/// return semantics. 1156static bool ArgsAreStructReturn(SDValue Op) { 1157 unsigned NumArgs = Op.getNode()->getNumValues() - 1; 1158 if (!NumArgs) 1159 return false; 1160 1161 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); 1162} 1163 1164/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires 1165/// the callee to pop its own arguments. Callee pop is necessary to support tail 1166/// calls. 1167bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) { 1168 if (IsVarArg) 1169 return false; 1170 1171 switch (CallingConv) { 1172 default: 1173 return false; 1174 case CallingConv::X86_StdCall: 1175 return !Subtarget->is64Bit(); 1176 case CallingConv::X86_FastCall: 1177 return !Subtarget->is64Bit(); 1178 case CallingConv::Fast: 1179 return PerformTailCallOpt; 1180 } 1181} 1182 1183/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1184/// given CallingConvention value. 1185CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const { 1186 if (Subtarget->is64Bit()) { 1187 if (Subtarget->isTargetWin64()) 1188 return CC_X86_Win64_C; 1189 else if (CC == CallingConv::Fast && PerformTailCallOpt) 1190 return CC_X86_64_TailCall; 1191 else 1192 return CC_X86_64_C; 1193 } 1194 1195 if (CC == CallingConv::X86_FastCall) 1196 return CC_X86_32_FastCall; 1197 else if (CC == CallingConv::Fast) 1198 return CC_X86_32_FastCC; 1199 else 1200 return CC_X86_32_C; 1201} 1202 1203/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to 1204/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. 1205NameDecorationStyle 1206X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) { 1207 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 1208 if (CC == CallingConv::X86_FastCall) 1209 return FastCall; 1210 else if (CC == CallingConv::X86_StdCall) 1211 return StdCall; 1212 return None; 1213} 1214 1215 1216/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer 1217/// in a register before calling. 1218bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { 1219 return !IsTailCall && !Is64Bit && 1220 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1221 Subtarget->isPICStyleGOT(); 1222} 1223 1224/// CallRequiresFnAddressInReg - Check whether the call requires the function 1225/// address to be loaded in a register. 1226bool 1227X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { 1228 return !Is64Bit && IsTailCall && 1229 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1230 Subtarget->isPICStyleGOT(); 1231} 1232 1233/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1234/// by "Src" to address "Dst" with size and alignment information specified by 1235/// the specific parameter attribute. The copy will be passed as a byval 1236/// function parameter. 1237static SDValue 1238CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1239 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1240 DebugLoc dl) { 1241 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1242 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1243 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1244} 1245 1246SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG, 1247 const CCValAssign &VA, 1248 MachineFrameInfo *MFI, 1249 unsigned CC, 1250 SDValue Root, unsigned i) { 1251 // Create the nodes corresponding to a load from this parameter slot. 1252 ISD::ArgFlagsTy Flags = 1253 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); 1254 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; 1255 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1256 1257 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1258 // changed with more analysis. 1259 // In case of tail call optimization mark all arguments mutable. Since they 1260 // could be overwritten by lowering of arguments in case of a tail call. 1261 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1262 VA.getLocMemOffset(), isImmutable); 1263 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1264 if (Flags.isByVal()) 1265 return FIN; 1266 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN, 1267 PseudoSourceValue::getFixedStack(FI), 0); 1268} 1269 1270SDValue 1271X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 1272 MachineFunction &MF = DAG.getMachineFunction(); 1273 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1274 DebugLoc dl = Op.getDebugLoc(); 1275 1276 const Function* Fn = MF.getFunction(); 1277 if (Fn->hasExternalLinkage() && 1278 Subtarget->isTargetCygMing() && 1279 Fn->getName() == "main") 1280 FuncInfo->setForceFramePointer(true); 1281 1282 // Decorate the function name. 1283 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); 1284 1285 MachineFrameInfo *MFI = MF.getFrameInfo(); 1286 SDValue Root = Op.getOperand(0); 1287 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1288 unsigned CC = MF.getFunction()->getCallingConv(); 1289 bool Is64Bit = Subtarget->is64Bit(); 1290 bool IsWin64 = Subtarget->isTargetWin64(); 1291 1292 assert(!(isVarArg && CC == CallingConv::Fast) && 1293 "Var args not supported with calling convention fastcc"); 1294 1295 // Assign locations to all of the incoming arguments. 1296 SmallVector<CCValAssign, 16> ArgLocs; 1297 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1298 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC)); 1299 1300 SmallVector<SDValue, 8> ArgValues; 1301 unsigned LastVal = ~0U; 1302 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1303 CCValAssign &VA = ArgLocs[i]; 1304 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1305 // places. 1306 assert(VA.getValNo() != LastVal && 1307 "Don't support value assigned to multiple locs yet"); 1308 LastVal = VA.getValNo(); 1309 1310 if (VA.isRegLoc()) { 1311 MVT RegVT = VA.getLocVT(); 1312 TargetRegisterClass *RC = NULL; 1313 if (RegVT == MVT::i32) 1314 RC = X86::GR32RegisterClass; 1315 else if (Is64Bit && RegVT == MVT::i64) 1316 RC = X86::GR64RegisterClass; 1317 else if (RegVT == MVT::f32) 1318 RC = X86::FR32RegisterClass; 1319 else if (RegVT == MVT::f64) 1320 RC = X86::FR64RegisterClass; 1321 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1322 RC = X86::VR128RegisterClass; 1323 else if (RegVT.isVector()) { 1324 assert(RegVT.getSizeInBits() == 64); 1325 if (!Is64Bit) 1326 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. 1327 else { 1328 // Darwin calling convention passes MMX values in either GPRs or 1329 // XMMs in x86-64. Other targets pass them in memory. 1330 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { 1331 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. 1332 RegVT = MVT::v2i64; 1333 } else { 1334 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. 1335 RegVT = MVT::i64; 1336 } 1337 } 1338 } else { 1339 assert(0 && "Unknown argument type!"); 1340 } 1341 1342 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 1343 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); 1344 1345 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1346 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1347 // right size. 1348 if (VA.getLocInfo() == CCValAssign::SExt) 1349 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1350 DAG.getValueType(VA.getValVT())); 1351 else if (VA.getLocInfo() == CCValAssign::ZExt) 1352 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1353 DAG.getValueType(VA.getValVT())); 1354 1355 if (VA.getLocInfo() != CCValAssign::Full) 1356 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1357 1358 // Handle MMX values passed in GPRs. 1359 if (Is64Bit && RegVT != VA.getLocVT()) { 1360 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) 1361 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue); 1362 else if (RC == X86::VR128RegisterClass) { 1363 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1364 ArgValue, DAG.getConstant(0, MVT::i64)); 1365 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue); 1366 } 1367 } 1368 1369 ArgValues.push_back(ArgValue); 1370 } else { 1371 assert(VA.isMemLoc()); 1372 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); 1373 } 1374 } 1375 1376 // The x86-64 ABI for returning structs by value requires that we copy 1377 // the sret argument into %rax for the return. Save the argument into 1378 // a virtual register so that we can access it from the return points. 1379 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1380 MachineFunction &MF = DAG.getMachineFunction(); 1381 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1382 unsigned Reg = FuncInfo->getSRetReturnReg(); 1383 if (!Reg) { 1384 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1385 FuncInfo->setSRetReturnReg(Reg); 1386 } 1387 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]); 1388 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); 1389 } 1390 1391 unsigned StackSize = CCInfo.getNextStackOffset(); 1392 // align stack specially for tail calls 1393 if (PerformTailCallOpt && CC == CallingConv::Fast) 1394 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1395 1396 // If the function takes variable number of arguments, make a frame index for 1397 // the start of the first vararg value... for expansion of llvm.va_start. 1398 if (isVarArg) { 1399 if (Is64Bit || CC != CallingConv::X86_FastCall) { 1400 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1401 } 1402 if (Is64Bit) { 1403 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1404 1405 // FIXME: We should really autogenerate these arrays 1406 static const unsigned GPR64ArgRegsWin64[] = { 1407 X86::RCX, X86::RDX, X86::R8, X86::R9 1408 }; 1409 static const unsigned XMMArgRegsWin64[] = { 1410 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1411 }; 1412 static const unsigned GPR64ArgRegs64Bit[] = { 1413 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1414 }; 1415 static const unsigned XMMArgRegs64Bit[] = { 1416 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1417 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1418 }; 1419 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1420 1421 if (IsWin64) { 1422 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1423 GPR64ArgRegs = GPR64ArgRegsWin64; 1424 XMMArgRegs = XMMArgRegsWin64; 1425 } else { 1426 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1427 GPR64ArgRegs = GPR64ArgRegs64Bit; 1428 XMMArgRegs = XMMArgRegs64Bit; 1429 } 1430 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1431 TotalNumIntRegs); 1432 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1433 TotalNumXMMRegs); 1434 1435 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1436 "SSE register cannot be used when SSE is disabled!"); 1437 assert(!(NumXMMRegs && UseSoftFloat) && 1438 "SSE register cannot be used when SSE is disabled!"); 1439 if (UseSoftFloat || !Subtarget->hasSSE1()) { 1440 // Kernel mode asks for SSE to be disabled, so don't push them 1441 // on the stack. 1442 TotalNumXMMRegs = 0; 1443 } 1444 // For X86-64, if there are vararg parameters that are passed via 1445 // registers, then we must store them to their spots on the stack so they 1446 // may be loaded by deferencing the result of va_next. 1447 VarArgsGPOffset = NumIntRegs * 8; 1448 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1449 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1450 TotalNumXMMRegs * 16, 16); 1451 1452 // Store the integer parameter registers. 1453 SmallVector<SDValue, 8> MemOps; 1454 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1455 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1456 DAG.getIntPtrConstant(VarArgsGPOffset)); 1457 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1458 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1459 X86::GR64RegisterClass); 1460 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); 1461 SDValue Store = 1462 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1463 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1464 MemOps.push_back(Store); 1465 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 1466 DAG.getIntPtrConstant(8)); 1467 } 1468 1469 // Now store the XMM (fp + vector) parameter registers. 1470 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1471 DAG.getIntPtrConstant(VarArgsFPOffset)); 1472 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1473 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1474 X86::VR128RegisterClass); 1475 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32); 1476 SDValue Store = 1477 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1478 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1479 MemOps.push_back(Store); 1480 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 1481 DAG.getIntPtrConstant(16)); 1482 } 1483 if (!MemOps.empty()) 1484 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1485 &MemOps[0], MemOps.size()); 1486 } 1487 } 1488 1489 ArgValues.push_back(Root); 1490 1491 // Some CCs need callee pop. 1492 if (IsCalleePop(isVarArg, CC)) { 1493 BytesToPopOnReturn = StackSize; // Callee pops everything. 1494 BytesCallerReserves = 0; 1495 } else { 1496 BytesToPopOnReturn = 0; // Callee pops nothing. 1497 // If this is an sret function, the return should pop the hidden pointer. 1498 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op)) 1499 BytesToPopOnReturn = 4; 1500 BytesCallerReserves = StackSize; 1501 } 1502 1503 if (!Is64Bit) { 1504 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1505 if (CC == CallingConv::X86_FastCall) 1506 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1507 } 1508 1509 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1510 1511 // Return the new list of results. 1512 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 1513 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 1514} 1515 1516SDValue 1517X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 1518 const SDValue &StackPtr, 1519 const CCValAssign &VA, 1520 SDValue Chain, 1521 SDValue Arg, ISD::ArgFlagsTy Flags) { 1522 DebugLoc dl = TheCall->getDebugLoc(); 1523 unsigned LocMemOffset = VA.getLocMemOffset(); 1524 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1525 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1526 if (Flags.isByVal()) { 1527 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1528 } 1529 return DAG.getStore(Chain, dl, Arg, PtrOff, 1530 PseudoSourceValue::getStack(), LocMemOffset); 1531} 1532 1533/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1534/// optimization is performed and it is required. 1535SDValue 1536X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1537 SDValue &OutRetAddr, 1538 SDValue Chain, 1539 bool IsTailCall, 1540 bool Is64Bit, 1541 int FPDiff, 1542 DebugLoc dl) { 1543 if (!IsTailCall || FPDiff==0) return Chain; 1544 1545 // Adjust the Return address stack slot. 1546 MVT VT = getPointerTy(); 1547 OutRetAddr = getReturnAddressFrameIndex(DAG); 1548 1549 // Load the "old" Return address. 1550 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0); 1551 return SDValue(OutRetAddr.getNode(), 1); 1552} 1553 1554/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1555/// optimization is performed and it is required (FPDiff!=0). 1556static SDValue 1557EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1558 SDValue Chain, SDValue RetAddrFrIdx, 1559 bool Is64Bit, int FPDiff, DebugLoc dl) { 1560 // Store the return address to the appropriate stack slot. 1561 if (!FPDiff) return Chain; 1562 // Calculate the new stack slot for the return address. 1563 int SlotSize = Is64Bit ? 8 : 4; 1564 int NewReturnAddrFI = 1565 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1566 MVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1567 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1568 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1569 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1570 return Chain; 1571} 1572 1573SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 1574 MachineFunction &MF = DAG.getMachineFunction(); 1575 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 1576 SDValue Chain = TheCall->getChain(); 1577 unsigned CC = TheCall->getCallingConv(); 1578 bool isVarArg = TheCall->isVarArg(); 1579 bool IsTailCall = TheCall->isTailCall() && 1580 CC == CallingConv::Fast && PerformTailCallOpt; 1581 SDValue Callee = TheCall->getCallee(); 1582 bool Is64Bit = Subtarget->is64Bit(); 1583 bool IsStructRet = CallIsStructReturn(TheCall); 1584 DebugLoc dl = TheCall->getDebugLoc(); 1585 1586 assert(!(isVarArg && CC == CallingConv::Fast) && 1587 "Var args not supported with calling convention fastcc"); 1588 1589 // Analyze operands of the call, assigning locations to each operand. 1590 SmallVector<CCValAssign, 16> ArgLocs; 1591 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1592 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC)); 1593 1594 // Get a count of how many bytes are to be pushed on the stack. 1595 unsigned NumBytes = CCInfo.getNextStackOffset(); 1596 if (PerformTailCallOpt && CC == CallingConv::Fast) 1597 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1598 1599 int FPDiff = 0; 1600 if (IsTailCall) { 1601 // Lower arguments at fp - stackoffset + fpdiff. 1602 unsigned NumBytesCallerPushed = 1603 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1604 FPDiff = NumBytesCallerPushed - NumBytes; 1605 1606 // Set the delta of movement of the returnaddr stackslot. 1607 // But only set if delta is greater than previous delta. 1608 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1609 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1610 } 1611 1612 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1613 1614 SDValue RetAddrFrIdx; 1615 // Load return adress for tail calls. 1616 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, 1617 FPDiff, dl); 1618 1619 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1620 SmallVector<SDValue, 8> MemOpChains; 1621 SDValue StackPtr; 1622 1623 // Walk the register/memloc assignments, inserting copies/loads. In the case 1624 // of tail call optimization arguments are handle later. 1625 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1626 CCValAssign &VA = ArgLocs[i]; 1627 SDValue Arg = TheCall->getArg(i); 1628 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1629 bool isByVal = Flags.isByVal(); 1630 1631 // Promote the value if needed. 1632 switch (VA.getLocInfo()) { 1633 default: assert(0 && "Unknown loc info!"); 1634 case CCValAssign::Full: break; 1635 case CCValAssign::SExt: 1636 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1637 break; 1638 case CCValAssign::ZExt: 1639 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1640 break; 1641 case CCValAssign::AExt: 1642 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1643 break; 1644 } 1645 1646 if (VA.isRegLoc()) { 1647 if (Is64Bit) { 1648 MVT RegVT = VA.getLocVT(); 1649 if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1650 switch (VA.getLocReg()) { 1651 default: 1652 break; 1653 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: 1654 case X86::R8: { 1655 // Special case: passing MMX values in GPR registers. 1656 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1657 break; 1658 } 1659 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: 1660 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { 1661 // Special case: passing MMX values in XMM registers. 1662 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1663 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1664 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64, 1665 DAG.getUNDEF(MVT::v2i64), Arg, 1666 getMOVLMask(2, DAG, dl)); 1667 break; 1668 } 1669 } 1670 } 1671 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1672 } else { 1673 if (!IsTailCall || (IsTailCall && isByVal)) { 1674 assert(VA.isMemLoc()); 1675 if (StackPtr.getNode() == 0) 1676 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1677 1678 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, 1679 Chain, Arg, Flags)); 1680 } 1681 } 1682 } 1683 1684 if (!MemOpChains.empty()) 1685 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1686 &MemOpChains[0], MemOpChains.size()); 1687 1688 // Build a sequence of copy-to-reg nodes chained together with token chain 1689 // and flag operands which copy the outgoing args into registers. 1690 SDValue InFlag; 1691 // Tail call byval lowering might overwrite argument registers so in case of 1692 // tail call optimization the copies to registers are lowered later. 1693 if (!IsTailCall) 1694 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1695 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1696 RegsToPass[i].second, InFlag); 1697 InFlag = Chain.getValue(1); 1698 } 1699 1700 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1701 // GOT pointer. 1702 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { 1703 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1704 DAG.getNode(X86ISD::GlobalBaseReg, 1705 DebugLoc::getUnknownLoc(), 1706 getPointerTy()), 1707 InFlag); 1708 InFlag = Chain.getValue(1); 1709 } 1710 // If we are tail calling and generating PIC/GOT style code load the address 1711 // of the callee into ecx. The value in ecx is used as target of the tail 1712 // jump. This is done to circumvent the ebx/callee-saved problem for tail 1713 // calls on PIC/GOT architectures. Normally we would just put the address of 1714 // GOT into ebx and then call target@PLT. But for tail callss ebx would be 1715 // restored (since ebx is callee saved) before jumping to the target@PLT. 1716 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { 1717 // Note: The actual moving to ecx is done further down. 1718 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1719 if (G && !G->getGlobal()->hasHiddenVisibility() && 1720 !G->getGlobal()->hasProtectedVisibility()) 1721 Callee = LowerGlobalAddress(Callee, DAG); 1722 else if (isa<ExternalSymbolSDNode>(Callee)) 1723 Callee = LowerExternalSymbol(Callee,DAG); 1724 } 1725 1726 if (Is64Bit && isVarArg) { 1727 // From AMD64 ABI document: 1728 // For calls that may call functions that use varargs or stdargs 1729 // (prototype-less calls or calls to functions containing ellipsis (...) in 1730 // the declaration) %al is used as hidden argument to specify the number 1731 // of SSE registers used. The contents of %al do not need to match exactly 1732 // the number of registers, but must be an ubound on the number of SSE 1733 // registers used and is in the range 0 - 8 inclusive. 1734 1735 // FIXME: Verify this on Win64 1736 // Count the number of XMM registers allocated. 1737 static const unsigned XMMArgRegs[] = { 1738 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1739 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1740 }; 1741 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1742 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1743 && "SSE registers cannot be used when SSE is disabled"); 1744 1745 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1746 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1747 InFlag = Chain.getValue(1); 1748 } 1749 1750 1751 // For tail calls lower the arguments to the 'real' stack slot. 1752 if (IsTailCall) { 1753 SmallVector<SDValue, 8> MemOpChains2; 1754 SDValue FIN; 1755 int FI = 0; 1756 // Do not flag preceeding copytoreg stuff together with the following stuff. 1757 InFlag = SDValue(); 1758 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1759 CCValAssign &VA = ArgLocs[i]; 1760 if (!VA.isRegLoc()) { 1761 assert(VA.isMemLoc()); 1762 SDValue Arg = TheCall->getArg(i); 1763 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1764 // Create frame index. 1765 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1766 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1767 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1768 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1769 1770 if (Flags.isByVal()) { 1771 // Copy relative to framepointer. 1772 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1773 if (StackPtr.getNode() == 0) 1774 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1775 getPointerTy()); 1776 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 1777 1778 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, 1779 Flags, DAG, dl)); 1780 } else { 1781 // Store relative to framepointer. 1782 MemOpChains2.push_back( 1783 DAG.getStore(Chain, dl, Arg, FIN, 1784 PseudoSourceValue::getFixedStack(FI), 0)); 1785 } 1786 } 1787 } 1788 1789 if (!MemOpChains2.empty()) 1790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1791 &MemOpChains2[0], MemOpChains2.size()); 1792 1793 // Copy arguments to their registers. 1794 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1795 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1796 RegsToPass[i].second, InFlag); 1797 InFlag = Chain.getValue(1); 1798 } 1799 InFlag =SDValue(); 1800 1801 // Store the return address to the appropriate stack slot. 1802 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1803 FPDiff, dl); 1804 } 1805 1806 // If the callee is a GlobalAddress node (quite common, every direct call is) 1807 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1808 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1809 // We should use extra load for direct calls to dllimported functions in 1810 // non-JIT mode. 1811 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1812 getTargetMachine(), true)) 1813 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(), 1814 G->getOffset()); 1815 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1816 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1817 } else if (IsTailCall) { 1818 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX; 1819 1820 Chain = DAG.getCopyToReg(Chain, dl, 1821 DAG.getRegister(Opc, getPointerTy()), 1822 Callee,InFlag); 1823 Callee = DAG.getRegister(Opc, getPointerTy()); 1824 // Add register as live out. 1825 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); 1826 } 1827 1828 // Returns a chain & a flag for retval copy to use. 1829 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1830 SmallVector<SDValue, 8> Ops; 1831 1832 if (IsTailCall) { 1833 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1834 DAG.getIntPtrConstant(0, true), InFlag); 1835 InFlag = Chain.getValue(1); 1836 1837 // Returns a chain & a flag for retval copy to use. 1838 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1839 Ops.clear(); 1840 } 1841 1842 Ops.push_back(Chain); 1843 Ops.push_back(Callee); 1844 1845 if (IsTailCall) 1846 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1847 1848 // Add argument registers to the end of the list so that they are known live 1849 // into the call. 1850 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1851 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1852 RegsToPass[i].second.getValueType())); 1853 1854 // Add an implicit use GOT pointer in EBX. 1855 if (!IsTailCall && !Is64Bit && 1856 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1857 Subtarget->isPICStyleGOT()) 1858 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1859 1860 // Add an implicit use of AL for x86 vararg functions. 1861 if (Is64Bit && isVarArg) 1862 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1863 1864 if (InFlag.getNode()) 1865 Ops.push_back(InFlag); 1866 1867 if (IsTailCall) { 1868 assert(InFlag.getNode() && 1869 "Flag must be set. Depend on flag being set in LowerRET"); 1870 Chain = DAG.getNode(X86ISD::TAILCALL, dl, 1871 TheCall->getVTList(), &Ops[0], Ops.size()); 1872 1873 return SDValue(Chain.getNode(), Op.getResNo()); 1874 } 1875 1876 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 1877 InFlag = Chain.getValue(1); 1878 1879 // Create the CALLSEQ_END node. 1880 unsigned NumBytesForCalleeToPush; 1881 if (IsCalleePop(isVarArg, CC)) 1882 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 1883 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet) 1884 // If this is is a call to a struct-return function, the callee 1885 // pops the hidden struct pointer, so we have to push it back. 1886 // This is common for Darwin/X86, Linux & Mingw32 targets. 1887 NumBytesForCalleeToPush = 4; 1888 else 1889 NumBytesForCalleeToPush = 0; // Callee pops nothing. 1890 1891 // Returns a flag for retval copy to use. 1892 Chain = DAG.getCALLSEQ_END(Chain, 1893 DAG.getIntPtrConstant(NumBytes, true), 1894 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 1895 true), 1896 InFlag); 1897 InFlag = Chain.getValue(1); 1898 1899 // Handle result values, copying them out of physregs into vregs that we 1900 // return. 1901 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 1902 Op.getResNo()); 1903} 1904 1905 1906//===----------------------------------------------------------------------===// 1907// Fast Calling Convention (tail call) implementation 1908//===----------------------------------------------------------------------===// 1909 1910// Like std call, callee cleans arguments, convention except that ECX is 1911// reserved for storing the tail called function address. Only 2 registers are 1912// free for argument passing (inreg). Tail call optimization is performed 1913// provided: 1914// * tailcallopt is enabled 1915// * caller/callee are fastcc 1916// On X86_64 architecture with GOT-style position independent code only local 1917// (within module) calls are supported at the moment. 1918// To keep the stack aligned according to platform abi the function 1919// GetAlignedArgumentStackSize ensures that argument delta is always multiples 1920// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 1921// If a tail called function callee has more arguments than the caller the 1922// caller needs to make sure that there is room to move the RETADDR to. This is 1923// achieved by reserving an area the size of the argument delta right after the 1924// original REtADDR, but before the saved framepointer or the spilled registers 1925// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 1926// stack layout: 1927// arg1 1928// arg2 1929// RETADDR 1930// [ new RETADDR 1931// move area ] 1932// (possible EBP) 1933// ESI 1934// EDI 1935// local1 .. 1936 1937/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 1938/// for a 16 byte align requirement. 1939unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 1940 SelectionDAG& DAG) { 1941 MachineFunction &MF = DAG.getMachineFunction(); 1942 const TargetMachine &TM = MF.getTarget(); 1943 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 1944 unsigned StackAlignment = TFI.getStackAlignment(); 1945 uint64_t AlignMask = StackAlignment - 1; 1946 int64_t Offset = StackSize; 1947 uint64_t SlotSize = TD->getPointerSize(); 1948 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 1949 // Number smaller than 12 so just add the difference. 1950 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 1951 } else { 1952 // Mask out lower bits, add stackalignment once plus the 12 bytes. 1953 Offset = ((~AlignMask) & Offset) + StackAlignment + 1954 (StackAlignment-SlotSize); 1955 } 1956 return Offset; 1957} 1958 1959/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1960/// following the call is a return. A function is eligible if caller/callee 1961/// calling conventions match, currently only fastcc supports tail calls, and 1962/// the function CALL is immediatly followed by a RET. 1963bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall, 1964 SDValue Ret, 1965 SelectionDAG& DAG) const { 1966 if (!PerformTailCallOpt) 1967 return false; 1968 1969 if (CheckTailCallReturnConstraints(TheCall, Ret)) { 1970 MachineFunction &MF = DAG.getMachineFunction(); 1971 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1972 unsigned CalleeCC= TheCall->getCallingConv(); 1973 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1974 SDValue Callee = TheCall->getCallee(); 1975 // On x86/32Bit PIC/GOT tail calls are supported. 1976 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || 1977 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) 1978 return true; 1979 1980 // Can only do local tail calls (in same module, hidden or protected) on 1981 // x86_64 PIC/GOT at the moment. 1982 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1983 return G->getGlobal()->hasHiddenVisibility() 1984 || G->getGlobal()->hasProtectedVisibility(); 1985 } 1986 } 1987 1988 return false; 1989} 1990 1991FastISel * 1992X86TargetLowering::createFastISel(MachineFunction &mf, 1993 MachineModuleInfo *mmo, 1994 DwarfWriter *dw, 1995 DenseMap<const Value *, unsigned> &vm, 1996 DenseMap<const BasicBlock *, 1997 MachineBasicBlock *> &bm, 1998 DenseMap<const AllocaInst *, int> &am 1999#ifndef NDEBUG 2000 , SmallSet<Instruction*, 8> &cil 2001#endif 2002 ) { 2003 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2004#ifndef NDEBUG 2005 , cil 2006#endif 2007 ); 2008} 2009 2010 2011//===----------------------------------------------------------------------===// 2012// Other Lowering Hooks 2013//===----------------------------------------------------------------------===// 2014 2015 2016SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2017 MachineFunction &MF = DAG.getMachineFunction(); 2018 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2019 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2020 2021 if (ReturnAddrIndex == 0) { 2022 // Set up a frame object for the return address. 2023 uint64_t SlotSize = TD->getPointerSize(); 2024 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize); 2025 FuncInfo->setRAIndex(ReturnAddrIndex); 2026 } 2027 2028 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2029} 2030 2031 2032/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2033/// specific condition code, returning the condition code and the LHS/RHS of the 2034/// comparison to make. 2035static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2036 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2037 if (!isFP) { 2038 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2039 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2040 // X > -1 -> X == 0, jump !sign. 2041 RHS = DAG.getConstant(0, RHS.getValueType()); 2042 return X86::COND_NS; 2043 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2044 // X < 0 -> X == 0, jump on sign. 2045 return X86::COND_S; 2046 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2047 // X < 1 -> X <= 0 2048 RHS = DAG.getConstant(0, RHS.getValueType()); 2049 return X86::COND_LE; 2050 } 2051 } 2052 2053 switch (SetCCOpcode) { 2054 default: assert(0 && "Invalid integer condition!"); 2055 case ISD::SETEQ: return X86::COND_E; 2056 case ISD::SETGT: return X86::COND_G; 2057 case ISD::SETGE: return X86::COND_GE; 2058 case ISD::SETLT: return X86::COND_L; 2059 case ISD::SETLE: return X86::COND_LE; 2060 case ISD::SETNE: return X86::COND_NE; 2061 case ISD::SETULT: return X86::COND_B; 2062 case ISD::SETUGT: return X86::COND_A; 2063 case ISD::SETULE: return X86::COND_BE; 2064 case ISD::SETUGE: return X86::COND_AE; 2065 } 2066 } 2067 2068 // First determine if it is required or is profitable to flip the operands. 2069 2070 // If LHS is a foldable load, but RHS is not, flip the condition. 2071 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2072 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2073 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2074 std::swap(LHS, RHS); 2075 } 2076 2077 switch (SetCCOpcode) { 2078 default: break; 2079 case ISD::SETOLT: 2080 case ISD::SETOLE: 2081 case ISD::SETUGT: 2082 case ISD::SETUGE: 2083 std::swap(LHS, RHS); 2084 break; 2085 } 2086 2087 // On a floating point condition, the flags are set as follows: 2088 // ZF PF CF op 2089 // 0 | 0 | 0 | X > Y 2090 // 0 | 0 | 1 | X < Y 2091 // 1 | 0 | 0 | X == Y 2092 // 1 | 1 | 1 | unordered 2093 switch (SetCCOpcode) { 2094 default: assert(0 && "Condcode should be pre-legalized away"); 2095 case ISD::SETUEQ: 2096 case ISD::SETEQ: return X86::COND_E; 2097 case ISD::SETOLT: // flipped 2098 case ISD::SETOGT: 2099 case ISD::SETGT: return X86::COND_A; 2100 case ISD::SETOLE: // flipped 2101 case ISD::SETOGE: 2102 case ISD::SETGE: return X86::COND_AE; 2103 case ISD::SETUGT: // flipped 2104 case ISD::SETULT: 2105 case ISD::SETLT: return X86::COND_B; 2106 case ISD::SETUGE: // flipped 2107 case ISD::SETULE: 2108 case ISD::SETLE: return X86::COND_BE; 2109 case ISD::SETONE: 2110 case ISD::SETNE: return X86::COND_NE; 2111 case ISD::SETUO: return X86::COND_P; 2112 case ISD::SETO: return X86::COND_NP; 2113 } 2114} 2115 2116/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2117/// code. Current x86 isa includes the following FP cmov instructions: 2118/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2119static bool hasFPCMov(unsigned X86CC) { 2120 switch (X86CC) { 2121 default: 2122 return false; 2123 case X86::COND_B: 2124 case X86::COND_BE: 2125 case X86::COND_E: 2126 case X86::COND_P: 2127 case X86::COND_A: 2128 case X86::COND_AE: 2129 case X86::COND_NE: 2130 case X86::COND_NP: 2131 return true; 2132 } 2133} 2134 2135/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 2136/// true if Op is undef or if its value falls within the specified range (L, H]. 2137static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) { 2138 if (Op.getOpcode() == ISD::UNDEF) 2139 return true; 2140 2141 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue(); 2142 return (Val >= Low && Val < Hi); 2143} 2144 2145/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 2146/// true if Op is undef or if its value equal to the specified value. 2147static bool isUndefOrEqual(SDValue Op, unsigned Val) { 2148 if (Op.getOpcode() == ISD::UNDEF) 2149 return true; 2150 return cast<ConstantSDNode>(Op)->getZExtValue() == Val; 2151} 2152 2153/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 2154/// specifies a shuffle of elements that is suitable for input to PSHUFD. 2155bool X86::isPSHUFDMask(SDNode *N) { 2156 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2157 2158 if (N->getNumOperands() != 2 && N->getNumOperands() != 4) 2159 return false; 2160 2161 // Check if the value doesn't reference the second vector. 2162 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2163 SDValue Arg = N->getOperand(i); 2164 if (Arg.getOpcode() == ISD::UNDEF) continue; 2165 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2166 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e) 2167 return false; 2168 } 2169 2170 return true; 2171} 2172 2173/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 2174/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 2175bool X86::isPSHUFHWMask(SDNode *N) { 2176 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2177 2178 if (N->getNumOperands() != 8) 2179 return false; 2180 2181 // Lower quadword copied in order. 2182 for (unsigned i = 0; i != 4; ++i) { 2183 SDValue Arg = N->getOperand(i); 2184 if (Arg.getOpcode() == ISD::UNDEF) continue; 2185 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2186 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i) 2187 return false; 2188 } 2189 2190 // Upper quadword shuffled. 2191 for (unsigned i = 4; i != 8; ++i) { 2192 SDValue Arg = N->getOperand(i); 2193 if (Arg.getOpcode() == ISD::UNDEF) continue; 2194 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2195 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2196 if (Val < 4 || Val > 7) 2197 return false; 2198 } 2199 2200 return true; 2201} 2202 2203/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 2204/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 2205bool X86::isPSHUFLWMask(SDNode *N) { 2206 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2207 2208 if (N->getNumOperands() != 8) 2209 return false; 2210 2211 // Upper quadword copied in order. 2212 for (unsigned i = 4; i != 8; ++i) 2213 if (!isUndefOrEqual(N->getOperand(i), i)) 2214 return false; 2215 2216 // Lower quadword shuffled. 2217 for (unsigned i = 0; i != 4; ++i) 2218 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 2219 return false; 2220 2221 return true; 2222} 2223 2224/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2225/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2226template<class SDOperand> 2227static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) { 2228 if (NumElems != 2 && NumElems != 4) return false; 2229 2230 unsigned Half = NumElems / 2; 2231 for (unsigned i = 0; i < Half; ++i) 2232 if (!isUndefOrInRange(Elems[i], 0, NumElems)) 2233 return false; 2234 for (unsigned i = Half; i < NumElems; ++i) 2235 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) 2236 return false; 2237 2238 return true; 2239} 2240 2241bool X86::isSHUFPMask(SDNode *N) { 2242 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2243 return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); 2244} 2245 2246/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2247/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2248/// half elements to come from vector 1 (which would equal the dest.) and 2249/// the upper half to come from vector 2. 2250template<class SDOperand> 2251static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) { 2252 if (NumOps != 2 && NumOps != 4) return false; 2253 2254 unsigned Half = NumOps / 2; 2255 for (unsigned i = 0; i < Half; ++i) 2256 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) 2257 return false; 2258 for (unsigned i = Half; i < NumOps; ++i) 2259 if (!isUndefOrInRange(Ops[i], 0, NumOps)) 2260 return false; 2261 return true; 2262} 2263 2264static bool isCommutedSHUFP(SDNode *N) { 2265 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2266 return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); 2267} 2268 2269/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2270/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2271bool X86::isMOVHLPSMask(SDNode *N) { 2272 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2273 2274 if (N->getNumOperands() != 4) 2275 return false; 2276 2277 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2278 return isUndefOrEqual(N->getOperand(0), 6) && 2279 isUndefOrEqual(N->getOperand(1), 7) && 2280 isUndefOrEqual(N->getOperand(2), 2) && 2281 isUndefOrEqual(N->getOperand(3), 3); 2282} 2283 2284/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2285/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2286/// <2, 3, 2, 3> 2287bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 2288 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2289 2290 if (N->getNumOperands() != 4) 2291 return false; 2292 2293 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 2294 return isUndefOrEqual(N->getOperand(0), 2) && 2295 isUndefOrEqual(N->getOperand(1), 3) && 2296 isUndefOrEqual(N->getOperand(2), 2) && 2297 isUndefOrEqual(N->getOperand(3), 3); 2298} 2299 2300/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2301/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2302bool X86::isMOVLPMask(SDNode *N) { 2303 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2304 2305 unsigned NumElems = N->getNumOperands(); 2306 if (NumElems != 2 && NumElems != 4) 2307 return false; 2308 2309 for (unsigned i = 0; i < NumElems/2; ++i) 2310 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2311 return false; 2312 2313 for (unsigned i = NumElems/2; i < NumElems; ++i) 2314 if (!isUndefOrEqual(N->getOperand(i), i)) 2315 return false; 2316 2317 return true; 2318} 2319 2320/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2321/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2322/// and MOVLHPS. 2323bool X86::isMOVHPMask(SDNode *N) { 2324 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2325 2326 unsigned NumElems = N->getNumOperands(); 2327 if (NumElems != 2 && NumElems != 4) 2328 return false; 2329 2330 for (unsigned i = 0; i < NumElems/2; ++i) 2331 if (!isUndefOrEqual(N->getOperand(i), i)) 2332 return false; 2333 2334 for (unsigned i = 0; i < NumElems/2; ++i) { 2335 SDValue Arg = N->getOperand(i + NumElems/2); 2336 if (!isUndefOrEqual(Arg, i + NumElems)) 2337 return false; 2338 } 2339 2340 return true; 2341} 2342 2343/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2344/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2345template<class SDOperand> 2346bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts, 2347 bool V2IsSplat = false) { 2348 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2349 return false; 2350 2351 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2352 SDValue BitI = Elts[i]; 2353 SDValue BitI1 = Elts[i+1]; 2354 if (!isUndefOrEqual(BitI, j)) 2355 return false; 2356 if (V2IsSplat) { 2357 if (!isUndefOrEqual(BitI1, NumElts)) 2358 return false; 2359 } else { 2360 if (!isUndefOrEqual(BitI1, j + NumElts)) 2361 return false; 2362 } 2363 } 2364 2365 return true; 2366} 2367 2368bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2369 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2370 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2371} 2372 2373/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2374/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2375template<class SDOperand> 2376bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts, 2377 bool V2IsSplat = false) { 2378 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2379 return false; 2380 2381 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2382 SDValue BitI = Elts[i]; 2383 SDValue BitI1 = Elts[i+1]; 2384 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2385 return false; 2386 if (V2IsSplat) { 2387 if (isUndefOrEqual(BitI1, NumElts)) 2388 return false; 2389 } else { 2390 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2391 return false; 2392 } 2393 } 2394 2395 return true; 2396} 2397 2398bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2399 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2400 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2401} 2402 2403/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2404/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2405/// <0, 0, 1, 1> 2406bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2407 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2408 2409 unsigned NumElems = N->getNumOperands(); 2410 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2411 return false; 2412 2413 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2414 SDValue BitI = N->getOperand(i); 2415 SDValue BitI1 = N->getOperand(i+1); 2416 2417 if (!isUndefOrEqual(BitI, j)) 2418 return false; 2419 if (!isUndefOrEqual(BitI1, j)) 2420 return false; 2421 } 2422 2423 return true; 2424} 2425 2426/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2427/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2428/// <2, 2, 3, 3> 2429bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { 2430 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2431 2432 unsigned NumElems = N->getNumOperands(); 2433 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2434 return false; 2435 2436 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2437 SDValue BitI = N->getOperand(i); 2438 SDValue BitI1 = N->getOperand(i + 1); 2439 2440 if (!isUndefOrEqual(BitI, j)) 2441 return false; 2442 if (!isUndefOrEqual(BitI1, j)) 2443 return false; 2444 } 2445 2446 return true; 2447} 2448 2449/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2450/// specifies a shuffle of elements that is suitable for input to MOVSS, 2451/// MOVSD, and MOVD, i.e. setting the lowest element. 2452template<class SDOperand> 2453static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) { 2454 if (NumElts != 2 && NumElts != 4) 2455 return false; 2456 2457 if (!isUndefOrEqual(Elts[0], NumElts)) 2458 return false; 2459 2460 for (unsigned i = 1; i < NumElts; ++i) { 2461 if (!isUndefOrEqual(Elts[i], i)) 2462 return false; 2463 } 2464 2465 return true; 2466} 2467 2468bool X86::isMOVLMask(SDNode *N) { 2469 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2470 return ::isMOVLMask(N->op_begin(), N->getNumOperands()); 2471} 2472 2473/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2474/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2475/// element of vector 2 and the other elements to come from vector 1 in order. 2476template<class SDOperand> 2477static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps, 2478 bool V2IsSplat = false, 2479 bool V2IsUndef = false) { 2480 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2481 return false; 2482 2483 if (!isUndefOrEqual(Ops[0], 0)) 2484 return false; 2485 2486 for (unsigned i = 1; i < NumOps; ++i) { 2487 SDValue Arg = Ops[i]; 2488 if (!(isUndefOrEqual(Arg, i+NumOps) || 2489 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || 2490 (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) 2491 return false; 2492 } 2493 2494 return true; 2495} 2496 2497static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2498 bool V2IsUndef = false) { 2499 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2500 return isCommutedMOVL(N->op_begin(), N->getNumOperands(), 2501 V2IsSplat, V2IsUndef); 2502} 2503 2504/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2505/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2506bool X86::isMOVSHDUPMask(SDNode *N) { 2507 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2508 2509 if (N->getNumOperands() != 4) 2510 return false; 2511 2512 // Expect 1, 1, 3, 3 2513 for (unsigned i = 0; i < 2; ++i) { 2514 SDValue Arg = N->getOperand(i); 2515 if (Arg.getOpcode() == ISD::UNDEF) continue; 2516 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2517 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2518 if (Val != 1) return false; 2519 } 2520 2521 bool HasHi = false; 2522 for (unsigned i = 2; i < 4; ++i) { 2523 SDValue Arg = N->getOperand(i); 2524 if (Arg.getOpcode() == ISD::UNDEF) continue; 2525 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2526 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2527 if (Val != 3) return false; 2528 HasHi = true; 2529 } 2530 2531 // Don't use movshdup if it can be done with a shufps. 2532 return HasHi; 2533} 2534 2535/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2536/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2537bool X86::isMOVSLDUPMask(SDNode *N) { 2538 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2539 2540 if (N->getNumOperands() != 4) 2541 return false; 2542 2543 // Expect 0, 0, 2, 2 2544 for (unsigned i = 0; i < 2; ++i) { 2545 SDValue Arg = N->getOperand(i); 2546 if (Arg.getOpcode() == ISD::UNDEF) continue; 2547 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2548 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2549 if (Val != 0) return false; 2550 } 2551 2552 bool HasHi = false; 2553 for (unsigned i = 2; i < 4; ++i) { 2554 SDValue Arg = N->getOperand(i); 2555 if (Arg.getOpcode() == ISD::UNDEF) continue; 2556 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2557 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2558 if (Val != 2) return false; 2559 HasHi = true; 2560 } 2561 2562 // Don't use movshdup if it can be done with a shufps. 2563 return HasHi; 2564} 2565 2566/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand 2567/// specifies a identity operation on the LHS or RHS. 2568static bool isIdentityMask(SDNode *N, bool RHS = false) { 2569 unsigned NumElems = N->getNumOperands(); 2570 for (unsigned i = 0; i < NumElems; ++i) 2571 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0))) 2572 return false; 2573 return true; 2574} 2575 2576/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2577/// a splat of a single element. 2578static bool isSplatMask(SDNode *N) { 2579 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2580 2581 // This is a splat operation if each element of the permute is the same, and 2582 // if the value doesn't reference the second vector. 2583 unsigned NumElems = N->getNumOperands(); 2584 SDValue ElementBase; 2585 unsigned i = 0; 2586 for (; i != NumElems; ++i) { 2587 SDValue Elt = N->getOperand(i); 2588 if (isa<ConstantSDNode>(Elt)) { 2589 ElementBase = Elt; 2590 break; 2591 } 2592 } 2593 2594 if (!ElementBase.getNode()) 2595 return false; 2596 2597 for (; i != NumElems; ++i) { 2598 SDValue Arg = N->getOperand(i); 2599 if (Arg.getOpcode() == ISD::UNDEF) continue; 2600 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2601 if (Arg != ElementBase) return false; 2602 } 2603 2604 // Make sure it is a splat of the first vector operand. 2605 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems; 2606} 2607 2608/// getSplatMaskEltNo - Given a splat mask, return the index to the element 2609/// we want to splat. 2610static SDValue getSplatMaskEltNo(SDNode *N) { 2611 assert(isSplatMask(N) && "Not a splat mask"); 2612 unsigned NumElems = N->getNumOperands(); 2613 SDValue ElementBase; 2614 unsigned i = 0; 2615 for (; i != NumElems; ++i) { 2616 SDValue Elt = N->getOperand(i); 2617 if (isa<ConstantSDNode>(Elt)) 2618 return Elt; 2619 } 2620 assert(0 && " No splat value found!"); 2621 return SDValue(); 2622} 2623 2624 2625/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2626/// a splat of a single element and it's a 2 or 4 element mask. 2627bool X86::isSplatMask(SDNode *N) { 2628 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2629 2630 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2631 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2632 return false; 2633 return ::isSplatMask(N); 2634} 2635 2636/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 2637/// specifies a splat of zero element. 2638bool X86::isSplatLoMask(SDNode *N) { 2639 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2640 2641 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 2642 if (!isUndefOrEqual(N->getOperand(i), 0)) 2643 return false; 2644 return true; 2645} 2646 2647/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2648/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2649bool X86::isMOVDDUPMask(SDNode *N) { 2650 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2651 2652 unsigned e = N->getNumOperands() / 2; 2653 for (unsigned i = 0; i < e; ++i) 2654 if (!isUndefOrEqual(N->getOperand(i), i)) 2655 return false; 2656 for (unsigned i = 0; i < e; ++i) 2657 if (!isUndefOrEqual(N->getOperand(e+i), i)) 2658 return false; 2659 return true; 2660} 2661 2662/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2663/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2664/// instructions. 2665unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2666 unsigned NumOperands = N->getNumOperands(); 2667 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2668 unsigned Mask = 0; 2669 for (unsigned i = 0; i < NumOperands; ++i) { 2670 unsigned Val = 0; 2671 SDValue Arg = N->getOperand(NumOperands-i-1); 2672 if (Arg.getOpcode() != ISD::UNDEF) 2673 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2674 if (Val >= NumOperands) Val -= NumOperands; 2675 Mask |= Val; 2676 if (i != NumOperands - 1) 2677 Mask <<= Shift; 2678 } 2679 2680 return Mask; 2681} 2682 2683/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2684/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2685/// instructions. 2686unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2687 unsigned Mask = 0; 2688 // 8 nodes, but we only care about the last 4. 2689 for (unsigned i = 7; i >= 4; --i) { 2690 unsigned Val = 0; 2691 SDValue Arg = N->getOperand(i); 2692 if (Arg.getOpcode() != ISD::UNDEF) { 2693 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2694 Mask |= (Val - 4); 2695 } 2696 if (i != 4) 2697 Mask <<= 2; 2698 } 2699 2700 return Mask; 2701} 2702 2703/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2704/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2705/// instructions. 2706unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2707 unsigned Mask = 0; 2708 // 8 nodes, but we only care about the first 4. 2709 for (int i = 3; i >= 0; --i) { 2710 unsigned Val = 0; 2711 SDValue Arg = N->getOperand(i); 2712 if (Arg.getOpcode() != ISD::UNDEF) 2713 Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2714 Mask |= Val; 2715 if (i != 0) 2716 Mask <<= 2; 2717 } 2718 2719 return Mask; 2720} 2721 2722/// CommuteVectorShuffle - Swap vector_shuffle operands as well as 2723/// values in ther permute mask. 2724static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1, 2725 SDValue &V2, SDValue &Mask, 2726 SelectionDAG &DAG) { 2727 MVT VT = Op.getValueType(); 2728 MVT MaskVT = Mask.getValueType(); 2729 MVT EltVT = MaskVT.getVectorElementType(); 2730 unsigned NumElems = Mask.getNumOperands(); 2731 SmallVector<SDValue, 8> MaskVec; 2732 DebugLoc dl = Op.getDebugLoc(); 2733 2734 for (unsigned i = 0; i != NumElems; ++i) { 2735 SDValue Arg = Mask.getOperand(i); 2736 if (Arg.getOpcode() == ISD::UNDEF) { 2737 MaskVec.push_back(DAG.getUNDEF(EltVT)); 2738 continue; 2739 } 2740 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2741 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2742 if (Val < NumElems) 2743 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2744 else 2745 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2746 } 2747 2748 std::swap(V1, V2); 2749 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems); 2750 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask); 2751} 2752 2753/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2754/// the two vector operands have swapped position. 2755static 2756SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) { 2757 MVT MaskVT = Mask.getValueType(); 2758 MVT EltVT = MaskVT.getVectorElementType(); 2759 unsigned NumElems = Mask.getNumOperands(); 2760 SmallVector<SDValue, 8> MaskVec; 2761 for (unsigned i = 0; i != NumElems; ++i) { 2762 SDValue Arg = Mask.getOperand(i); 2763 if (Arg.getOpcode() == ISD::UNDEF) { 2764 MaskVec.push_back(DAG.getUNDEF(EltVT)); 2765 continue; 2766 } 2767 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2768 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2769 if (Val < NumElems) 2770 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2771 else 2772 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2773 } 2774 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems); 2775} 2776 2777 2778/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2779/// match movhlps. The lower half elements should come from upper half of 2780/// V1 (and in order), and the upper half elements should come from the upper 2781/// half of V2 (and in order). 2782static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2783 unsigned NumElems = Mask->getNumOperands(); 2784 if (NumElems != 4) 2785 return false; 2786 for (unsigned i = 0, e = 2; i != e; ++i) 2787 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2788 return false; 2789 for (unsigned i = 2; i != 4; ++i) 2790 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2791 return false; 2792 return true; 2793} 2794 2795/// isScalarLoadToVector - Returns true if the node is a scalar load that 2796/// is promoted to a vector. It also returns the LoadSDNode by reference if 2797/// required. 2798static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2799 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 2800 return false; 2801 N = N->getOperand(0).getNode(); 2802 if (!ISD::isNON_EXTLoad(N)) 2803 return false; 2804 if (LD) 2805 *LD = cast<LoadSDNode>(N); 2806 return true; 2807} 2808 2809/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2810/// match movlp{s|d}. The lower half elements should come from lower half of 2811/// V1 (and in order), and the upper half elements should come from the upper 2812/// half of V2 (and in order). And since V1 will become the source of the 2813/// MOVLP, it must be either a vector load or a scalar load to vector. 2814static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2815 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2816 return false; 2817 // Is V2 is a vector load, don't do this transformation. We will try to use 2818 // load folding shufps op. 2819 if (ISD::isNON_EXTLoad(V2)) 2820 return false; 2821 2822 unsigned NumElems = Mask->getNumOperands(); 2823 if (NumElems != 2 && NumElems != 4) 2824 return false; 2825 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2826 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2827 return false; 2828 for (unsigned i = NumElems/2; i != NumElems; ++i) 2829 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2830 return false; 2831 return true; 2832} 2833 2834/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2835/// all the same. 2836static bool isSplatVector(SDNode *N) { 2837 if (N->getOpcode() != ISD::BUILD_VECTOR) 2838 return false; 2839 2840 SDValue SplatValue = N->getOperand(0); 2841 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2842 if (N->getOperand(i) != SplatValue) 2843 return false; 2844 return true; 2845} 2846 2847/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2848/// to an undef. 2849static bool isUndefShuffle(SDNode *N) { 2850 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2851 return false; 2852 2853 SDValue V1 = N->getOperand(0); 2854 SDValue V2 = N->getOperand(1); 2855 SDValue Mask = N->getOperand(2); 2856 unsigned NumElems = Mask.getNumOperands(); 2857 for (unsigned i = 0; i != NumElems; ++i) { 2858 SDValue Arg = Mask.getOperand(i); 2859 if (Arg.getOpcode() != ISD::UNDEF) { 2860 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2861 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2862 return false; 2863 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2864 return false; 2865 } 2866 } 2867 return true; 2868} 2869 2870/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2871/// constant +0.0. 2872static inline bool isZeroNode(SDValue Elt) { 2873 return ((isa<ConstantSDNode>(Elt) && 2874 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 2875 (isa<ConstantFPSDNode>(Elt) && 2876 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2877} 2878 2879/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2880/// to an zero vector. 2881static bool isZeroShuffle(SDNode *N) { 2882 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2883 return false; 2884 2885 SDValue V1 = N->getOperand(0); 2886 SDValue V2 = N->getOperand(1); 2887 SDValue Mask = N->getOperand(2); 2888 unsigned NumElems = Mask.getNumOperands(); 2889 for (unsigned i = 0; i != NumElems; ++i) { 2890 SDValue Arg = Mask.getOperand(i); 2891 if (Arg.getOpcode() == ISD::UNDEF) 2892 continue; 2893 2894 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 2895 if (Idx < NumElems) { 2896 unsigned Opc = V1.getNode()->getOpcode(); 2897 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 2898 continue; 2899 if (Opc != ISD::BUILD_VECTOR || 2900 !isZeroNode(V1.getNode()->getOperand(Idx))) 2901 return false; 2902 } else if (Idx >= NumElems) { 2903 unsigned Opc = V2.getNode()->getOpcode(); 2904 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 2905 continue; 2906 if (Opc != ISD::BUILD_VECTOR || 2907 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems))) 2908 return false; 2909 } 2910 } 2911 return true; 2912} 2913 2914/// getZeroVector - Returns a vector of specified type with all zero elements. 2915/// 2916static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG, 2917 DebugLoc dl) { 2918 assert(VT.isVector() && "Expected a vector type"); 2919 2920 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2921 // type. This ensures they get CSE'd. 2922 SDValue Vec; 2923 if (VT.getSizeInBits() == 64) { // MMX 2924 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2925 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2926 } else if (HasSSE2) { // SSE2 2927 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2928 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2929 } else { // SSE1 2930 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2931 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 2932 } 2933 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2934} 2935 2936/// getOnesVector - Returns a vector of specified type with all bits set. 2937/// 2938static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { 2939 assert(VT.isVector() && "Expected a vector type"); 2940 2941 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2942 // type. This ensures they get CSE'd. 2943 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2944 SDValue Vec; 2945 if (VT.getSizeInBits() == 64) // MMX 2946 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2947 else // SSE 2948 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2949 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2950} 2951 2952 2953/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2954/// that point to V2 points to its first element. 2955static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) { 2956 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2957 2958 bool Changed = false; 2959 SmallVector<SDValue, 8> MaskVec; 2960 unsigned NumElems = Mask.getNumOperands(); 2961 for (unsigned i = 0; i != NumElems; ++i) { 2962 SDValue Arg = Mask.getOperand(i); 2963 if (Arg.getOpcode() != ISD::UNDEF) { 2964 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue(); 2965 if (Val > NumElems) { 2966 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2967 Changed = true; 2968 } 2969 } 2970 MaskVec.push_back(Arg); 2971 } 2972 2973 if (Changed) 2974 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(), 2975 Mask.getValueType(), 2976 &MaskVec[0], MaskVec.size()); 2977 return Mask; 2978} 2979 2980/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2981/// operation of specified width. 2982static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) { 2983 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2984 MVT BaseVT = MaskVT.getVectorElementType(); 2985 2986 SmallVector<SDValue, 8> MaskVec; 2987 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2988 for (unsigned i = 1; i != NumElems; ++i) 2989 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2990 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 2991 &MaskVec[0], MaskVec.size()); 2992} 2993 2994/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2995/// of specified width. 2996static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG, 2997 DebugLoc dl) { 2998 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2999 MVT BaseVT = MaskVT.getVectorElementType(); 3000 SmallVector<SDValue, 8> MaskVec; 3001 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3002 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 3003 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 3004 } 3005 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3006 &MaskVec[0], MaskVec.size()); 3007} 3008 3009/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 3010/// of specified width. 3011static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG, 3012 DebugLoc dl) { 3013 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3014 MVT BaseVT = MaskVT.getVectorElementType(); 3015 unsigned Half = NumElems/2; 3016 SmallVector<SDValue, 8> MaskVec; 3017 for (unsigned i = 0; i != Half; ++i) { 3018 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 3019 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 3020 } 3021 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3022 &MaskVec[0], MaskVec.size()); 3023} 3024 3025/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps 3026/// element #0 of a vector with the specified index, leaving the rest of the 3027/// elements in place. 3028static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, 3029 SelectionDAG &DAG, DebugLoc dl) { 3030 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3031 MVT BaseVT = MaskVT.getVectorElementType(); 3032 SmallVector<SDValue, 8> MaskVec; 3033 // Element #0 of the result gets the elt we are replacing. 3034 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); 3035 for (unsigned i = 1; i != NumElems; ++i) 3036 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); 3037 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3038 &MaskVec[0], MaskVec.size()); 3039} 3040 3041/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3042static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) { 3043 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; 3044 MVT VT = Op.getValueType(); 3045 if (PVT == VT) 3046 return Op; 3047 SDValue V1 = Op.getOperand(0); 3048 SDValue Mask = Op.getOperand(2); 3049 unsigned MaskNumElems = Mask.getNumOperands(); 3050 unsigned NumElems = MaskNumElems; 3051 DebugLoc dl = Op.getDebugLoc(); 3052 // Special handling of v4f32 -> v4i32. 3053 if (VT != MVT::v4f32) { 3054 // Find which element we want to splat. 3055 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode(); 3056 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue(); 3057 // unpack elements to the correct location 3058 while (NumElems > 4) { 3059 if (EltNo < NumElems/2) { 3060 Mask = getUnpacklMask(MaskNumElems, DAG, dl); 3061 } else { 3062 Mask = getUnpackhMask(MaskNumElems, DAG, dl); 3063 EltNo -= NumElems/2; 3064 } 3065 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask); 3066 NumElems >>= 1; 3067 } 3068 SDValue Cst = DAG.getConstant(EltNo, MVT::i32); 3069 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3070 } 3071 3072 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3073 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1, 3074 DAG.getUNDEF(PVT), Mask); 3075 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle); 3076} 3077 3078/// isVectorLoad - Returns true if the node is a vector load, a scalar 3079/// load that's promoted to vector, or a load bitcasted. 3080static bool isVectorLoad(SDValue Op) { 3081 assert(Op.getValueType().isVector() && "Expected a vector type"); 3082 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR || 3083 Op.getOpcode() == ISD::BIT_CONVERT) { 3084 return isa<LoadSDNode>(Op.getOperand(0)); 3085 } 3086 return isa<LoadSDNode>(Op); 3087} 3088 3089 3090/// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64. 3091/// 3092static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask, 3093 SelectionDAG &DAG, bool HasSSE3) { 3094 // If we have sse3 and shuffle has more than one use or input is a load, then 3095 // use movddup. Otherwise, use movlhps. 3096 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1)); 3097 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32; 3098 MVT VT = Op.getValueType(); 3099 if (VT == PVT) 3100 return Op; 3101 DebugLoc dl = Op.getDebugLoc(); 3102 unsigned NumElems = PVT.getVectorNumElements(); 3103 if (NumElems == 2) { 3104 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3105 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3106 } else { 3107 assert(NumElems == 4); 3108 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32); 3109 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32); 3110 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 3111 Cst0, Cst1, Cst0, Cst1); 3112 } 3113 3114 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3115 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1, 3116 DAG.getUNDEF(PVT), Mask); 3117 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle); 3118} 3119 3120/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3121/// vector of zero or undef vector. This produces a shuffle where the low 3122/// element of V2 is swizzled into the zero/undef vector, landing at element 3123/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3124static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3125 bool isZero, bool HasSSE2, 3126 SelectionDAG &DAG) { 3127 DebugLoc dl = V2.getDebugLoc(); 3128 MVT VT = V2.getValueType(); 3129 SDValue V1 = isZero 3130 ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT); 3131 unsigned NumElems = V2.getValueType().getVectorNumElements(); 3132 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3133 MVT EVT = MaskVT.getVectorElementType(); 3134 SmallVector<SDValue, 16> MaskVec; 3135 for (unsigned i = 0; i != NumElems; ++i) 3136 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. 3137 MaskVec.push_back(DAG.getConstant(NumElems, EVT)); 3138 else 3139 MaskVec.push_back(DAG.getConstant(i, EVT)); 3140 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3141 &MaskVec[0], MaskVec.size()); 3142 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask); 3143} 3144 3145/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3146/// a shuffle that is zero. 3147static 3148unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask, 3149 unsigned NumElems, bool Low, 3150 SelectionDAG &DAG) { 3151 unsigned NumZeros = 0; 3152 for (unsigned i = 0; i < NumElems; ++i) { 3153 unsigned Index = Low ? i : NumElems-i-1; 3154 SDValue Idx = Mask.getOperand(Index); 3155 if (Idx.getOpcode() == ISD::UNDEF) { 3156 ++NumZeros; 3157 continue; 3158 } 3159 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index); 3160 if (Elt.getNode() && isZeroNode(Elt)) 3161 ++NumZeros; 3162 else 3163 break; 3164 } 3165 return NumZeros; 3166} 3167 3168/// isVectorShift - Returns true if the shuffle can be implemented as a 3169/// logical left or right shift of a vector. 3170static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG, 3171 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3172 unsigned NumElems = Mask.getNumOperands(); 3173 3174 isLeft = true; 3175 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG); 3176 if (!NumZeros) { 3177 isLeft = false; 3178 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG); 3179 if (!NumZeros) 3180 return false; 3181 } 3182 3183 bool SeenV1 = false; 3184 bool SeenV2 = false; 3185 for (unsigned i = NumZeros; i < NumElems; ++i) { 3186 unsigned Val = isLeft ? (i - NumZeros) : i; 3187 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros)); 3188 if (Idx.getOpcode() == ISD::UNDEF) 3189 continue; 3190 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue(); 3191 if (Index < NumElems) 3192 SeenV1 = true; 3193 else { 3194 Index -= NumElems; 3195 SeenV2 = true; 3196 } 3197 if (Index != Val) 3198 return false; 3199 } 3200 if (SeenV1 && SeenV2) 3201 return false; 3202 3203 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1); 3204 ShAmt = NumZeros; 3205 return true; 3206} 3207 3208 3209/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3210/// 3211static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3212 unsigned NumNonZero, unsigned NumZero, 3213 SelectionDAG &DAG, TargetLowering &TLI) { 3214 if (NumNonZero > 8) 3215 return SDValue(); 3216 3217 DebugLoc dl = Op.getDebugLoc(); 3218 SDValue V(0, 0); 3219 bool First = true; 3220 for (unsigned i = 0; i < 16; ++i) { 3221 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3222 if (ThisIsNonZero && First) { 3223 if (NumZero) 3224 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3225 else 3226 V = DAG.getUNDEF(MVT::v8i16); 3227 First = false; 3228 } 3229 3230 if ((i & 1) != 0) { 3231 SDValue ThisElt(0, 0), LastElt(0, 0); 3232 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3233 if (LastIsNonZero) { 3234 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3235 MVT::i16, Op.getOperand(i-1)); 3236 } 3237 if (ThisIsNonZero) { 3238 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3239 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3240 ThisElt, DAG.getConstant(8, MVT::i8)); 3241 if (LastIsNonZero) 3242 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3243 } else 3244 ThisElt = LastElt; 3245 3246 if (ThisElt.getNode()) 3247 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3248 DAG.getIntPtrConstant(i/2)); 3249 } 3250 } 3251 3252 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3253} 3254 3255/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3256/// 3257static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3258 unsigned NumNonZero, unsigned NumZero, 3259 SelectionDAG &DAG, TargetLowering &TLI) { 3260 if (NumNonZero > 4) 3261 return SDValue(); 3262 3263 DebugLoc dl = Op.getDebugLoc(); 3264 SDValue V(0, 0); 3265 bool First = true; 3266 for (unsigned i = 0; i < 8; ++i) { 3267 bool isNonZero = (NonZeros & (1 << i)) != 0; 3268 if (isNonZero) { 3269 if (First) { 3270 if (NumZero) 3271 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3272 else 3273 V = DAG.getUNDEF(MVT::v8i16); 3274 First = false; 3275 } 3276 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3277 MVT::v8i16, V, Op.getOperand(i), 3278 DAG.getIntPtrConstant(i)); 3279 } 3280 } 3281 3282 return V; 3283} 3284 3285/// getVShift - Return a vector logical shift node. 3286/// 3287static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, 3288 unsigned NumBits, SelectionDAG &DAG, 3289 const TargetLowering &TLI, DebugLoc dl) { 3290 bool isMMX = VT.getSizeInBits() == 64; 3291 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3292 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3293 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3294 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3295 DAG.getNode(Opc, dl, ShVT, SrcOp, 3296 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3297} 3298 3299SDValue 3300X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3301 DebugLoc dl = Op.getDebugLoc(); 3302 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3303 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3304 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3305 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3306 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3307 // eliminated on x86-32 hosts. 3308 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3309 return Op; 3310 3311 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3312 return getOnesVector(Op.getValueType(), DAG, dl); 3313 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3314 } 3315 3316 MVT VT = Op.getValueType(); 3317 MVT EVT = VT.getVectorElementType(); 3318 unsigned EVTBits = EVT.getSizeInBits(); 3319 3320 unsigned NumElems = Op.getNumOperands(); 3321 unsigned NumZero = 0; 3322 unsigned NumNonZero = 0; 3323 unsigned NonZeros = 0; 3324 bool IsAllConstants = true; 3325 SmallSet<SDValue, 8> Values; 3326 for (unsigned i = 0; i < NumElems; ++i) { 3327 SDValue Elt = Op.getOperand(i); 3328 if (Elt.getOpcode() == ISD::UNDEF) 3329 continue; 3330 Values.insert(Elt); 3331 if (Elt.getOpcode() != ISD::Constant && 3332 Elt.getOpcode() != ISD::ConstantFP) 3333 IsAllConstants = false; 3334 if (isZeroNode(Elt)) 3335 NumZero++; 3336 else { 3337 NonZeros |= (1 << i); 3338 NumNonZero++; 3339 } 3340 } 3341 3342 if (NumNonZero == 0) { 3343 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3344 return DAG.getUNDEF(VT); 3345 } 3346 3347 // Special case for single non-zero, non-undef, element. 3348 if (NumNonZero == 1 && NumElems <= 4) { 3349 unsigned Idx = CountTrailingZeros_32(NonZeros); 3350 SDValue Item = Op.getOperand(Idx); 3351 3352 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3353 // the value are obviously zero, truncate the value to i32 and do the 3354 // insertion that way. Only do this if the value is non-constant or if the 3355 // value is a constant being inserted into element 0. It is cheaper to do 3356 // a constant pool load than it is to do a movd + shuffle. 3357 if (EVT == MVT::i64 && !Subtarget->is64Bit() && 3358 (!IsAllConstants || Idx == 0)) { 3359 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3360 // Handle MMX and SSE both. 3361 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3362 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3363 3364 // Truncate the value (which may itself be a constant) to i32, and 3365 // convert it to a vector with movd (S2V+shuffle to zero extend). 3366 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3367 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3368 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3369 Subtarget->hasSSE2(), DAG); 3370 3371 // Now we have our 32-bit value zero extended in the low element of 3372 // a vector. If Idx != 0, swizzle it into place. 3373 if (Idx != 0) { 3374 SDValue Ops[] = { 3375 Item, DAG.getUNDEF(Item.getValueType()), 3376 getSwapEltZeroMask(VecElts, Idx, DAG, dl) 3377 }; 3378 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3); 3379 } 3380 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3381 } 3382 } 3383 3384 // If we have a constant or non-constant insertion into the low element of 3385 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3386 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3387 // depending on what the source datatype is. Because we can only get here 3388 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64. 3389 if (Idx == 0 && 3390 // Don't do this for i64 values on x86-32. 3391 (EVT != MVT::i64 || Subtarget->is64Bit())) { 3392 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3393 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3394 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3395 Subtarget->hasSSE2(), DAG); 3396 } 3397 3398 // Is it a vector logical left shift? 3399 if (NumElems == 2 && Idx == 1 && 3400 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) { 3401 unsigned NumBits = VT.getSizeInBits(); 3402 return getVShift(true, VT, 3403 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3404 VT, Op.getOperand(1)), 3405 NumBits/2, DAG, *this, dl); 3406 } 3407 3408 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3409 return SDValue(); 3410 3411 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3412 // is a non-constant being inserted into an element other than the low one, 3413 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3414 // movd/movss) to move this into the low element, then shuffle it into 3415 // place. 3416 if (EVTBits == 32) { 3417 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3418 3419 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3420 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3421 Subtarget->hasSSE2(), DAG); 3422 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3423 MVT MaskEVT = MaskVT.getVectorElementType(); 3424 SmallVector<SDValue, 8> MaskVec; 3425 for (unsigned i = 0; i < NumElems; i++) 3426 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 3427 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3428 &MaskVec[0], MaskVec.size()); 3429 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item, 3430 DAG.getUNDEF(VT), Mask); 3431 } 3432 } 3433 3434 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3435 if (Values.size() == 1) 3436 return SDValue(); 3437 3438 // A vector full of immediates; various special cases are already 3439 // handled, so this is best done with a single constant-pool load. 3440 if (IsAllConstants) 3441 return SDValue(); 3442 3443 // Let legalizer expand 2-wide build_vectors. 3444 if (EVTBits == 64) { 3445 if (NumNonZero == 1) { 3446 // One half is zero or undef. 3447 unsigned Idx = CountTrailingZeros_32(NonZeros); 3448 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3449 Op.getOperand(Idx)); 3450 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3451 Subtarget->hasSSE2(), DAG); 3452 } 3453 return SDValue(); 3454 } 3455 3456 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3457 if (EVTBits == 8 && NumElems == 16) { 3458 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3459 *this); 3460 if (V.getNode()) return V; 3461 } 3462 3463 if (EVTBits == 16 && NumElems == 8) { 3464 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3465 *this); 3466 if (V.getNode()) return V; 3467 } 3468 3469 // If element VT is == 32 bits, turn it into a number of shuffles. 3470 SmallVector<SDValue, 8> V; 3471 V.resize(NumElems); 3472 if (NumElems == 4 && NumZero > 0) { 3473 for (unsigned i = 0; i < 4; ++i) { 3474 bool isZero = !(NonZeros & (1 << i)); 3475 if (isZero) 3476 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3477 else 3478 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3479 } 3480 3481 for (unsigned i = 0; i < 2; ++i) { 3482 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3483 default: break; 3484 case 0: 3485 V[i] = V[i*2]; // Must be a zero vector. 3486 break; 3487 case 1: 3488 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2], 3489 getMOVLMask(NumElems, DAG, dl)); 3490 break; 3491 case 2: 3492 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1], 3493 getMOVLMask(NumElems, DAG, dl)); 3494 break; 3495 case 3: 3496 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1], 3497 getUnpacklMask(NumElems, DAG, dl)); 3498 break; 3499 } 3500 } 3501 3502 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3503 MVT EVT = MaskVT.getVectorElementType(); 3504 SmallVector<SDValue, 8> MaskVec; 3505 bool Reverse = (NonZeros & 0x3) == 2; 3506 for (unsigned i = 0; i < 2; ++i) 3507 if (Reverse) 3508 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3509 else 3510 MaskVec.push_back(DAG.getConstant(i, EVT)); 3511 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3512 for (unsigned i = 0; i < 2; ++i) 3513 if (Reverse) 3514 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3515 else 3516 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3517 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3518 &MaskVec[0], MaskVec.size()); 3519 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask); 3520 } 3521 3522 if (Values.size() > 2) { 3523 // Expand into a number of unpckl*. 3524 // e.g. for v4f32 3525 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3526 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3527 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3528 SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl); 3529 for (unsigned i = 0; i < NumElems; ++i) 3530 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3531 NumElems >>= 1; 3532 while (NumElems != 0) { 3533 for (unsigned i = 0; i < NumElems; ++i) 3534 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems], 3535 UnpckMask); 3536 NumElems >>= 1; 3537 } 3538 return V[0]; 3539 } 3540 3541 return SDValue(); 3542} 3543 3544// v8i16 shuffles - Prefer shuffles in the following order: 3545// 1. [all] pshuflw, pshufhw, optional move 3546// 2. [ssse3] 1 x pshufb 3547// 3. [ssse3] 2 x pshufb + 1 x por 3548// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3549static 3550SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, 3551 SDValue PermMask, SelectionDAG &DAG, 3552 X86TargetLowering &TLI, DebugLoc dl) { 3553 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(), 3554 PermMask.getNode()->op_end()); 3555 SmallVector<int, 8> MaskVals; 3556 3557 // Determine if more than 1 of the words in each of the low and high quadwords 3558 // of the result come from the same quadword of one of the two inputs. Undef 3559 // mask values count as coming from any quadword, for better codegen. 3560 SmallVector<unsigned, 4> LoQuad(4); 3561 SmallVector<unsigned, 4> HiQuad(4); 3562 BitVector InputQuads(4); 3563 for (unsigned i = 0; i < 8; ++i) { 3564 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3565 SDValue Elt = MaskElts[i]; 3566 int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 : 3567 cast<ConstantSDNode>(Elt)->getZExtValue(); 3568 MaskVals.push_back(EltIdx); 3569 if (EltIdx < 0) { 3570 ++Quad[0]; 3571 ++Quad[1]; 3572 ++Quad[2]; 3573 ++Quad[3]; 3574 continue; 3575 } 3576 ++Quad[EltIdx / 4]; 3577 InputQuads.set(EltIdx / 4); 3578 } 3579 3580 int BestLoQuad = -1; 3581 unsigned MaxQuad = 1; 3582 for (unsigned i = 0; i < 4; ++i) { 3583 if (LoQuad[i] > MaxQuad) { 3584 BestLoQuad = i; 3585 MaxQuad = LoQuad[i]; 3586 } 3587 } 3588 3589 int BestHiQuad = -1; 3590 MaxQuad = 1; 3591 for (unsigned i = 0; i < 4; ++i) { 3592 if (HiQuad[i] > MaxQuad) { 3593 BestHiQuad = i; 3594 MaxQuad = HiQuad[i]; 3595 } 3596 } 3597 3598 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3599 // of the two input vectors, shuffle them into one input vector so only a 3600 // single pshufb instruction is necessary. If There are more than 2 input 3601 // quads, disable the next transformation since it does not help SSSE3. 3602 bool V1Used = InputQuads[0] || InputQuads[1]; 3603 bool V2Used = InputQuads[2] || InputQuads[3]; 3604 if (TLI.getSubtarget()->hasSSSE3()) { 3605 if (InputQuads.count() == 2 && V1Used && V2Used) { 3606 BestLoQuad = InputQuads.find_first(); 3607 BestHiQuad = InputQuads.find_next(BestLoQuad); 3608 } 3609 if (InputQuads.count() > 2) { 3610 BestLoQuad = -1; 3611 BestHiQuad = -1; 3612 } 3613 } 3614 3615 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3616 // the shuffle mask. If a quad is scored as -1, that means that it contains 3617 // words from all 4 input quadwords. 3618 SDValue NewV; 3619 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3620 SmallVector<SDValue,8> MaskV; 3621 MaskV.push_back(DAG.getConstant(BestLoQuad < 0 ? 0 : BestLoQuad, MVT::i64)); 3622 MaskV.push_back(DAG.getConstant(BestHiQuad < 0 ? 1 : BestHiQuad, MVT::i64)); 3623 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, &MaskV[0], 2); 3624 3625 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64, 3626 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3627 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask); 3628 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3629 3630 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3631 // source words for the shuffle, to aid later transformations. 3632 bool AllWordsInNewV = true; 3633 for (unsigned i = 0; i != 8; ++i) { 3634 int idx = MaskVals[i]; 3635 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3636 continue; 3637 AllWordsInNewV = false; 3638 break; 3639 } 3640 3641 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 3642 if (AllWordsInNewV) { 3643 for (int i = 0; i != 8; ++i) { 3644 int idx = MaskVals[i]; 3645 if (idx < 0) 3646 continue; 3647 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 3648 if ((idx != i) && idx < 4) 3649 pshufhw = false; 3650 if ((idx != i) && idx > 3) 3651 pshuflw = false; 3652 } 3653 V1 = NewV; 3654 V2Used = false; 3655 BestLoQuad = 0; 3656 BestHiQuad = 1; 3657 } 3658 3659 // If we've eliminated the use of V2, and the new mask is a pshuflw or 3660 // pshufhw, that's as cheap as it gets. Return the new shuffle. 3661 if (pshufhw || pshuflw) { 3662 MaskV.clear(); 3663 for (unsigned i = 0; i != 8; ++i) 3664 MaskV.push_back((MaskVals[i] < 0) ? DAG.getUNDEF(MVT::i16) 3665 : DAG.getConstant(MaskVals[i], 3666 MVT::i16)); 3667 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV, 3668 DAG.getUNDEF(MVT::v8i16), 3669 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, 3670 &MaskV[0], 8)); 3671 } 3672 } 3673 3674 // If we have SSSE3, and all words of the result are from 1 input vector, 3675 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 3676 // is present, fall back to case 4. 3677 if (TLI.getSubtarget()->hasSSSE3()) { 3678 SmallVector<SDValue,16> pshufbMask; 3679 3680 // If we have elements from both input vectors, set the high bit of the 3681 // shuffle mask element to zero out elements that come from V2 in the V1 3682 // mask, and elements that come from V1 in the V2 mask, so that the two 3683 // results can be OR'd together. 3684 bool TwoInputs = V1Used && V2Used; 3685 for (unsigned i = 0; i != 8; ++i) { 3686 int EltIdx = MaskVals[i] * 2; 3687 if (TwoInputs && (EltIdx >= 16)) { 3688 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3689 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3690 continue; 3691 } 3692 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3693 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 3694 } 3695 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 3696 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3697 DAG.getNode(ISD::BUILD_VECTOR, dl, 3698 MVT::v16i8, &pshufbMask[0], 16)); 3699 if (!TwoInputs) 3700 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3701 3702 // Calculate the shuffle mask for the second input, shuffle it, and 3703 // OR it with the first shuffled input. 3704 pshufbMask.clear(); 3705 for (unsigned i = 0; i != 8; ++i) { 3706 int EltIdx = MaskVals[i] * 2; 3707 if (EltIdx < 16) { 3708 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3709 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3710 continue; 3711 } 3712 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3713 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 3714 } 3715 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 3716 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3717 DAG.getNode(ISD::BUILD_VECTOR, dl, 3718 MVT::v16i8, &pshufbMask[0], 16)); 3719 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3720 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3721 } 3722 3723 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 3724 // and update MaskVals with new element order. 3725 BitVector InOrder(8); 3726 if (BestLoQuad >= 0) { 3727 SmallVector<SDValue, 8> MaskV; 3728 for (int i = 0; i != 4; ++i) { 3729 int idx = MaskVals[i]; 3730 if (idx < 0) { 3731 MaskV.push_back(DAG.getUNDEF(MVT::i16)); 3732 InOrder.set(i); 3733 } else if ((idx / 4) == BestLoQuad) { 3734 MaskV.push_back(DAG.getConstant(idx & 3, MVT::i16)); 3735 InOrder.set(i); 3736 } else { 3737 MaskV.push_back(DAG.getUNDEF(MVT::i16)); 3738 } 3739 } 3740 for (unsigned i = 4; i != 8; ++i) 3741 MaskV.push_back(DAG.getConstant(i, MVT::i16)); 3742 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV, 3743 DAG.getUNDEF(MVT::v8i16), 3744 DAG.getNode(ISD::BUILD_VECTOR, dl, 3745 MVT::v8i16, &MaskV[0], 8)); 3746 } 3747 3748 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 3749 // and update MaskVals with the new element order. 3750 if (BestHiQuad >= 0) { 3751 SmallVector<SDValue, 8> MaskV; 3752 for (unsigned i = 0; i != 4; ++i) 3753 MaskV.push_back(DAG.getConstant(i, MVT::i16)); 3754 for (unsigned i = 4; i != 8; ++i) { 3755 int idx = MaskVals[i]; 3756 if (idx < 0) { 3757 MaskV.push_back(DAG.getUNDEF(MVT::i16)); 3758 InOrder.set(i); 3759 } else if ((idx / 4) == BestHiQuad) { 3760 MaskV.push_back(DAG.getConstant((idx & 3) + 4, MVT::i16)); 3761 InOrder.set(i); 3762 } else { 3763 MaskV.push_back(DAG.getUNDEF(MVT::i16)); 3764 } 3765 } 3766 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV, 3767 DAG.getUNDEF(MVT::v8i16), 3768 DAG.getNode(ISD::BUILD_VECTOR, dl, 3769 MVT::v8i16, &MaskV[0], 8)); 3770 } 3771 3772 // In case BestHi & BestLo were both -1, which means each quadword has a word 3773 // from each of the four input quadwords, calculate the InOrder bitvector now 3774 // before falling through to the insert/extract cleanup. 3775 if (BestLoQuad == -1 && BestHiQuad == -1) { 3776 NewV = V1; 3777 for (int i = 0; i != 8; ++i) 3778 if (MaskVals[i] < 0 || MaskVals[i] == i) 3779 InOrder.set(i); 3780 } 3781 3782 // The other elements are put in the right place using pextrw and pinsrw. 3783 for (unsigned i = 0; i != 8; ++i) { 3784 if (InOrder[i]) 3785 continue; 3786 int EltIdx = MaskVals[i]; 3787 if (EltIdx < 0) 3788 continue; 3789 SDValue ExtOp = (EltIdx < 8) 3790 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 3791 DAG.getIntPtrConstant(EltIdx)) 3792 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 3793 DAG.getIntPtrConstant(EltIdx - 8)); 3794 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 3795 DAG.getIntPtrConstant(i)); 3796 } 3797 return NewV; 3798} 3799 3800// v16i8 shuffles - Prefer shuffles in the following order: 3801// 1. [ssse3] 1 x pshufb 3802// 2. [ssse3] 2 x pshufb + 1 x por 3803// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 3804static 3805SDValue LowerVECTOR_SHUFFLEv16i8(SDValue V1, SDValue V2, 3806 SDValue PermMask, SelectionDAG &DAG, 3807 X86TargetLowering &TLI, DebugLoc dl) { 3808 SmallVector<SDValue, 16> MaskElts(PermMask.getNode()->op_begin(), 3809 PermMask.getNode()->op_end()); 3810 SmallVector<int, 16> MaskVals; 3811 3812 // If we have SSSE3, case 1 is generated when all result bytes come from 3813 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 3814 // present, fall back to case 3. 3815 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 3816 bool V1Only = true; 3817 bool V2Only = true; 3818 for (unsigned i = 0; i < 16; ++i) { 3819 SDValue Elt = MaskElts[i]; 3820 int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 : 3821 cast<ConstantSDNode>(Elt)->getZExtValue(); 3822 MaskVals.push_back(EltIdx); 3823 if (EltIdx < 0) 3824 continue; 3825 if (EltIdx < 16) 3826 V2Only = false; 3827 else 3828 V1Only = false; 3829 } 3830 3831 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 3832 if (TLI.getSubtarget()->hasSSSE3()) { 3833 SmallVector<SDValue,16> pshufbMask; 3834 3835 // If all result elements are from one input vector, then only translate 3836 // undef mask values to 0x80 (zero out result) in the pshufb mask. 3837 // 3838 // Otherwise, we have elements from both input vectors, and must zero out 3839 // elements that come from V2 in the first mask, and V1 in the second mask 3840 // so that we can OR them together. 3841 bool TwoInputs = !(V1Only || V2Only); 3842 for (unsigned i = 0; i != 16; ++i) { 3843 int EltIdx = MaskVals[i]; 3844 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 3845 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3846 continue; 3847 } 3848 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3849 } 3850 // If all the elements are from V2, assign it to V1 and return after 3851 // building the first pshufb. 3852 if (V2Only) 3853 V1 = V2; 3854 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3855 DAG.getNode(ISD::BUILD_VECTOR, dl, 3856 MVT::v16i8, &pshufbMask[0], 16)); 3857 if (!TwoInputs) 3858 return V1; 3859 3860 // Calculate the shuffle mask for the second input, shuffle it, and 3861 // OR it with the first shuffled input. 3862 pshufbMask.clear(); 3863 for (unsigned i = 0; i != 16; ++i) { 3864 int EltIdx = MaskVals[i]; 3865 if (EltIdx < 16) { 3866 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3867 continue; 3868 } 3869 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3870 } 3871 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3872 DAG.getNode(ISD::BUILD_VECTOR, dl, 3873 MVT::v16i8, &pshufbMask[0], 16)); 3874 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3875 } 3876 3877 // No SSSE3 - Calculate in place words and then fix all out of place words 3878 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 3879 // the 16 different words that comprise the two doublequadword input vectors. 3880 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3881 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 3882 SDValue NewV = V2Only ? V2 : V1; 3883 for (int i = 0; i != 8; ++i) { 3884 int Elt0 = MaskVals[i*2]; 3885 int Elt1 = MaskVals[i*2+1]; 3886 3887 // This word of the result is all undef, skip it. 3888 if (Elt0 < 0 && Elt1 < 0) 3889 continue; 3890 3891 // This word of the result is already in the correct place, skip it. 3892 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 3893 continue; 3894 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 3895 continue; 3896 3897 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 3898 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 3899 SDValue InsElt; 3900 3901 // If Elt1 is defined, extract it from the appropriate source. If the 3902 // source byte is not also odd, shift the extracted word left 8 bits. 3903 if (Elt1 >= 0) { 3904 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3905 DAG.getIntPtrConstant(Elt1 / 2)); 3906 if ((Elt1 & 1) == 0) 3907 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 3908 DAG.getConstant(8, TLI.getShiftAmountTy())); 3909 } 3910 // If Elt0 is defined, extract it from the appropriate source. If the 3911 // source byte is not also even, shift the extracted word right 8 bits. If 3912 // Elt1 was also defined, OR the extracted values together before 3913 // inserting them in the result. 3914 if (Elt0 >= 0) { 3915 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 3916 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 3917 if ((Elt0 & 1) != 0) 3918 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 3919 DAG.getConstant(8, TLI.getShiftAmountTy())); 3920 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 3921 : InsElt0; 3922 } 3923 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3924 DAG.getIntPtrConstant(i)); 3925 } 3926 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 3927} 3928 3929/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3930/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3931/// done when every pair / quad of shuffle mask elements point to elements in 3932/// the right sequence. e.g. 3933/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3934static 3935SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2, 3936 MVT VT, 3937 SDValue PermMask, SelectionDAG &DAG, 3938 TargetLowering &TLI, DebugLoc dl) { 3939 unsigned NumElems = PermMask.getNumOperands(); 3940 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3941 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3942 MVT MaskEltVT = MaskVT.getVectorElementType(); 3943 MVT NewVT = MaskVT; 3944 switch (VT.getSimpleVT()) { 3945 default: assert(false && "Unexpected!"); 3946 case MVT::v4f32: NewVT = MVT::v2f64; break; 3947 case MVT::v4i32: NewVT = MVT::v2i64; break; 3948 case MVT::v8i16: NewVT = MVT::v4i32; break; 3949 case MVT::v16i8: NewVT = MVT::v4i32; break; 3950 } 3951 3952 if (NewWidth == 2) { 3953 if (VT.isInteger()) 3954 NewVT = MVT::v2i64; 3955 else 3956 NewVT = MVT::v2f64; 3957 } 3958 unsigned Scale = NumElems / NewWidth; 3959 SmallVector<SDValue, 8> MaskVec; 3960 for (unsigned i = 0; i < NumElems; i += Scale) { 3961 unsigned StartIdx = ~0U; 3962 for (unsigned j = 0; j < Scale; ++j) { 3963 SDValue Elt = PermMask.getOperand(i+j); 3964 if (Elt.getOpcode() == ISD::UNDEF) 3965 continue; 3966 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue(); 3967 if (StartIdx == ~0U) 3968 StartIdx = EltIdx - (EltIdx % Scale); 3969 if (EltIdx != StartIdx + j) 3970 return SDValue(); 3971 } 3972 if (StartIdx == ~0U) 3973 MaskVec.push_back(DAG.getUNDEF(MaskEltVT)); 3974 else 3975 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT)); 3976 } 3977 3978 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 3979 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 3980 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2, 3981 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 3982 &MaskVec[0], MaskVec.size())); 3983} 3984 3985/// getVZextMovL - Return a zero-extending vector move low node. 3986/// 3987static SDValue getVZextMovL(MVT VT, MVT OpVT, 3988 SDValue SrcOp, SelectionDAG &DAG, 3989 const X86Subtarget *Subtarget, DebugLoc dl) { 3990 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3991 LoadSDNode *LD = NULL; 3992 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 3993 LD = dyn_cast<LoadSDNode>(SrcOp); 3994 if (!LD) { 3995 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3996 // instead. 3997 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3998 if ((EVT != MVT::i64 || Subtarget->is64Bit()) && 3999 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4000 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4001 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { 4002 // PR2108 4003 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4004 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4005 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4006 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4007 OpVT, 4008 SrcOp.getOperand(0) 4009 .getOperand(0)))); 4010 } 4011 } 4012 } 4013 4014 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4015 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4016 DAG.getNode(ISD::BIT_CONVERT, dl, 4017 OpVT, SrcOp))); 4018} 4019 4020/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4021/// shuffles. 4022static SDValue 4023LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2, 4024 SDValue PermMask, MVT VT, SelectionDAG &DAG, 4025 DebugLoc dl) { 4026 MVT MaskVT = PermMask.getValueType(); 4027 MVT MaskEVT = MaskVT.getVectorElementType(); 4028 SmallVector<std::pair<int, int>, 8> Locs; 4029 Locs.resize(4); 4030 SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT)); 4031 unsigned NumHi = 0; 4032 unsigned NumLo = 0; 4033 for (unsigned i = 0; i != 4; ++i) { 4034 SDValue Elt = PermMask.getOperand(i); 4035 if (Elt.getOpcode() == ISD::UNDEF) { 4036 Locs[i] = std::make_pair(-1, -1); 4037 } else { 4038 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue(); 4039 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!"); 4040 if (Val < 4) { 4041 Locs[i] = std::make_pair(0, NumLo); 4042 Mask1[NumLo] = Elt; 4043 NumLo++; 4044 } else { 4045 Locs[i] = std::make_pair(1, NumHi); 4046 if (2+NumHi < 4) 4047 Mask1[2+NumHi] = Elt; 4048 NumHi++; 4049 } 4050 } 4051 } 4052 4053 if (NumLo <= 2 && NumHi <= 2) { 4054 // If no more than two elements come from either vector. This can be 4055 // implemented with two shuffles. First shuffle gather the elements. 4056 // The second shuffle, which takes the first shuffle as both of its 4057 // vector operands, put the elements into the right order. 4058 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, 4059 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4060 &Mask1[0], Mask1.size())); 4061 4062 SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT)); 4063 for (unsigned i = 0; i != 4; ++i) { 4064 if (Locs[i].first == -1) 4065 continue; 4066 else { 4067 unsigned Idx = (i < 2) ? 0 : 4; 4068 Idx += Locs[i].first * 2 + Locs[i].second; 4069 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 4070 } 4071 } 4072 4073 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, 4074 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4075 &Mask2[0], Mask2.size())); 4076 } else if (NumLo == 3 || NumHi == 3) { 4077 // Otherwise, we must have three elements from one vector, call it X, and 4078 // one element from the other, call it Y. First, use a shufps to build an 4079 // intermediate vector with the one element from Y and the element from X 4080 // that will be in the same half in the final destination (the indexes don't 4081 // matter). Then, use a shufps to build the final vector, taking the half 4082 // containing the element from Y from the intermediate, and the other half 4083 // from X. 4084 if (NumHi == 3) { 4085 // Normalize it so the 3 elements come from V1. 4086 PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl); 4087 std::swap(V1, V2); 4088 } 4089 4090 // Find the element from V2. 4091 unsigned HiIndex; 4092 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4093 SDValue Elt = PermMask.getOperand(HiIndex); 4094 if (Elt.getOpcode() == ISD::UNDEF) 4095 continue; 4096 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue(); 4097 if (Val >= 4) 4098 break; 4099 } 4100 4101 Mask1[0] = PermMask.getOperand(HiIndex); 4102 Mask1[1] = DAG.getUNDEF(MaskEVT); 4103 Mask1[2] = PermMask.getOperand(HiIndex^1); 4104 Mask1[3] = DAG.getUNDEF(MaskEVT); 4105 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, 4106 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4)); 4107 4108 if (HiIndex >= 2) { 4109 Mask1[0] = PermMask.getOperand(0); 4110 Mask1[1] = PermMask.getOperand(1); 4111 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT); 4112 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT); 4113 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, 4114 DAG.getNode(ISD::BUILD_VECTOR, dl, 4115 MaskVT, &Mask1[0], 4)); 4116 } else { 4117 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT); 4118 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT); 4119 Mask1[2] = PermMask.getOperand(2); 4120 Mask1[3] = PermMask.getOperand(3); 4121 if (Mask1[2].getOpcode() != ISD::UNDEF) 4122 Mask1[2] = 4123 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4, 4124 MaskEVT); 4125 if (Mask1[3].getOpcode() != ISD::UNDEF) 4126 Mask1[3] = 4127 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4, 4128 MaskEVT); 4129 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1, 4130 DAG.getNode(ISD::BUILD_VECTOR, dl, 4131 MaskVT, &Mask1[0], 4)); 4132 } 4133 } 4134 4135 // Break it into (shuffle shuffle_hi, shuffle_lo). 4136 Locs.clear(); 4137 SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT)); 4138 SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT)); 4139 SmallVector<SDValue,8> *MaskPtr = &LoMask; 4140 unsigned MaskIdx = 0; 4141 unsigned LoIdx = 0; 4142 unsigned HiIdx = 2; 4143 for (unsigned i = 0; i != 4; ++i) { 4144 if (i == 2) { 4145 MaskPtr = &HiMask; 4146 MaskIdx = 1; 4147 LoIdx = 0; 4148 HiIdx = 2; 4149 } 4150 SDValue Elt = PermMask.getOperand(i); 4151 if (Elt.getOpcode() == ISD::UNDEF) { 4152 Locs[i] = std::make_pair(-1, -1); 4153 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) { 4154 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4155 (*MaskPtr)[LoIdx] = Elt; 4156 LoIdx++; 4157 } else { 4158 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4159 (*MaskPtr)[HiIdx] = Elt; 4160 HiIdx++; 4161 } 4162 } 4163 4164 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, 4165 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4166 &LoMask[0], LoMask.size())); 4167 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, 4168 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4169 &HiMask[0], HiMask.size())); 4170 SmallVector<SDValue, 8> MaskOps; 4171 for (unsigned i = 0; i != 4; ++i) { 4172 if (Locs[i].first == -1) { 4173 MaskOps.push_back(DAG.getUNDEF(MaskEVT)); 4174 } else { 4175 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4176 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 4177 } 4178 } 4179 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle, 4180 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4181 &MaskOps[0], MaskOps.size())); 4182} 4183 4184SDValue 4185X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4186 SDValue V1 = Op.getOperand(0); 4187 SDValue V2 = Op.getOperand(1); 4188 SDValue PermMask = Op.getOperand(2); 4189 MVT VT = Op.getValueType(); 4190 DebugLoc dl = Op.getDebugLoc(); 4191 unsigned NumElems = PermMask.getNumOperands(); 4192 bool isMMX = VT.getSizeInBits() == 64; 4193 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4194 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4195 bool V1IsSplat = false; 4196 bool V2IsSplat = false; 4197 4198 // FIXME: Check for legal shuffle and return? 4199 4200 if (isUndefShuffle(Op.getNode())) 4201 return DAG.getUNDEF(VT); 4202 4203 if (isZeroShuffle(Op.getNode())) 4204 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4205 4206 if (isIdentityMask(PermMask.getNode())) 4207 return V1; 4208 else if (isIdentityMask(PermMask.getNode(), true)) 4209 return V2; 4210 4211 // Canonicalize movddup shuffles. 4212 if (V2IsUndef && Subtarget->hasSSE2() && 4213 VT.getSizeInBits() == 128 && 4214 X86::isMOVDDUPMask(PermMask.getNode())) 4215 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3()); 4216 4217 if (isSplatMask(PermMask.getNode())) { 4218 if (isMMX || NumElems < 4) return Op; 4219 // Promote it to a v4{if}32 splat. 4220 return PromoteSplat(Op, DAG, Subtarget->hasSSE2()); 4221 } 4222 4223 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4224 // do it! 4225 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4226 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, 4227 *this, dl); 4228 if (NewOp.getNode()) 4229 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4230 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4231 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4232 // FIXME: Figure out a cleaner way to do this. 4233 // Try to make use of movq to zero out the top part. 4234 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4235 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 4236 DAG, *this, dl); 4237 if (NewOp.getNode()) { 4238 SDValue NewV1 = NewOp.getOperand(0); 4239 SDValue NewV2 = NewOp.getOperand(1); 4240 SDValue NewMask = NewOp.getOperand(2); 4241 if (isCommutedMOVL(NewMask.getNode(), true, false)) { 4242 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); 4243 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget, 4244 dl); 4245 } 4246 } 4247 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4248 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 4249 DAG, *this, dl); 4250 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode())) 4251 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4252 DAG, Subtarget, dl); 4253 } 4254 } 4255 4256 // Check if this can be converted into a logical shift. 4257 bool isLeft = false; 4258 unsigned ShAmt = 0; 4259 SDValue ShVal; 4260 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt); 4261 if (isShift && ShVal.hasOneUse()) { 4262 // If the shifted value has multiple uses, it may be cheaper to use 4263 // v_set0 + movlhps or movhlps, etc. 4264 MVT EVT = VT.getVectorElementType(); 4265 ShAmt *= EVT.getSizeInBits(); 4266 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4267 } 4268 4269 if (X86::isMOVLMask(PermMask.getNode())) { 4270 if (V1IsUndef) 4271 return V2; 4272 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4273 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4274 if (!isMMX) 4275 return Op; 4276 } 4277 4278 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) || 4279 X86::isMOVSLDUPMask(PermMask.getNode()) || 4280 X86::isMOVHLPSMask(PermMask.getNode()) || 4281 X86::isMOVHPMask(PermMask.getNode()) || 4282 X86::isMOVLPMask(PermMask.getNode()))) 4283 return Op; 4284 4285 if (ShouldXformToMOVHLPS(PermMask.getNode()) || 4286 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode())) 4287 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4288 4289 if (isShift) { 4290 // No better options. Use a vshl / vsrl. 4291 MVT EVT = VT.getVectorElementType(); 4292 ShAmt *= EVT.getSizeInBits(); 4293 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4294 } 4295 4296 bool Commuted = false; 4297 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4298 // 1,1,1,1 -> v8i16 though. 4299 V1IsSplat = isSplatVector(V1.getNode()); 4300 V2IsSplat = isSplatVector(V2.getNode()); 4301 4302 // Canonicalize the splat or undef, if present, to be on the RHS. 4303 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4304 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4305 std::swap(V1IsSplat, V2IsSplat); 4306 std::swap(V1IsUndef, V2IsUndef); 4307 Commuted = true; 4308 } 4309 4310 // FIXME: Figure out a cleaner way to do this. 4311 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) { 4312 if (V2IsUndef) return V1; 4313 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4314 if (V2IsSplat) { 4315 // V2 is a splat, so the mask may be malformed. That is, it may point 4316 // to any V2 element. The instruction selectior won't like this. Get 4317 // a corrected mask and commute to form a proper MOVS{S|D}. 4318 SDValue NewMask = getMOVLMask(NumElems, DAG, dl); 4319 if (NewMask.getNode() != PermMask.getNode()) 4320 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); 4321 } 4322 return Op; 4323 } 4324 4325 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) || 4326 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) || 4327 X86::isUNPCKLMask(PermMask.getNode()) || 4328 X86::isUNPCKHMask(PermMask.getNode())) 4329 return Op; 4330 4331 if (V2IsSplat) { 4332 // Normalize mask so all entries that point to V2 points to its first 4333 // element then try to match unpck{h|l} again. If match, return a 4334 // new vector_shuffle with the corrected mask. 4335 SDValue NewMask = NormalizeMask(PermMask, DAG); 4336 if (NewMask.getNode() != PermMask.getNode()) { 4337 if (X86::isUNPCKLMask(NewMask.getNode(), true)) { 4338 SDValue NewMask = getUnpacklMask(NumElems, DAG, dl); 4339 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); 4340 } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) { 4341 SDValue NewMask = getUnpackhMask(NumElems, DAG, dl); 4342 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask); 4343 } 4344 } 4345 } 4346 4347 // Normalize the node to match x86 shuffle ops if needed 4348 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode())) 4349 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4350 4351 if (Commuted) { 4352 // Commute is back and try unpck* again. 4353 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4354 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) || 4355 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) || 4356 X86::isUNPCKLMask(PermMask.getNode()) || 4357 X86::isUNPCKHMask(PermMask.getNode())) 4358 return Op; 4359 } 4360 4361 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4362 // Try PSHUF* first, then SHUFP*. 4363 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically 4364 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. 4365 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) { 4366 if (V2.getOpcode() != ISD::UNDEF) 4367 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, 4368 DAG.getUNDEF(VT), PermMask); 4369 return Op; 4370 } 4371 4372 if (!isMMX) { 4373 if (Subtarget->hasSSE2() && 4374 (X86::isPSHUFDMask(PermMask.getNode()) || 4375 X86::isPSHUFHWMask(PermMask.getNode()) || 4376 X86::isPSHUFLWMask(PermMask.getNode()))) { 4377 MVT RVT = VT; 4378 if (VT == MVT::v4f32) { 4379 RVT = MVT::v4i32; 4380 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, 4381 DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1), 4382 DAG.getUNDEF(RVT), PermMask); 4383 } else if (V2.getOpcode() != ISD::UNDEF) 4384 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1, 4385 DAG.getUNDEF(RVT), PermMask); 4386 if (RVT != VT) 4387 Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op); 4388 return Op; 4389 } 4390 4391 // Binary or unary shufps. 4392 if (X86::isSHUFPMask(PermMask.getNode()) || 4393 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode()))) 4394 return Op; 4395 } 4396 4397 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4398 if (VT == MVT::v8i16) { 4399 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl); 4400 if (NewOp.getNode()) 4401 return NewOp; 4402 } 4403 4404 if (VT == MVT::v16i8) { 4405 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(V1, V2, PermMask, DAG, *this, dl); 4406 if (NewOp.getNode()) 4407 return NewOp; 4408 } 4409 4410 // Handle all 4 wide cases with a number of shuffles except for MMX. 4411 if (NumElems == 4 && !isMMX) 4412 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl); 4413 4414 return SDValue(); 4415} 4416 4417SDValue 4418X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4419 SelectionDAG &DAG) { 4420 MVT VT = Op.getValueType(); 4421 DebugLoc dl = Op.getDebugLoc(); 4422 if (VT.getSizeInBits() == 8) { 4423 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4424 Op.getOperand(0), Op.getOperand(1)); 4425 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4426 DAG.getValueType(VT)); 4427 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4428 } else if (VT.getSizeInBits() == 16) { 4429 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4430 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4431 if (Idx == 0) 4432 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4433 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4434 DAG.getNode(ISD::BIT_CONVERT, dl, 4435 MVT::v4i32, 4436 Op.getOperand(0)), 4437 Op.getOperand(1))); 4438 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4439 Op.getOperand(0), Op.getOperand(1)); 4440 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4441 DAG.getValueType(VT)); 4442 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4443 } else if (VT == MVT::f32) { 4444 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4445 // the result back to FR32 register. It's only worth matching if the 4446 // result has a single use which is a store or a bitcast to i32. And in 4447 // the case of a store, it's not worth it if the index is a constant 0, 4448 // because a MOVSSmr can be used instead, which is smaller and faster. 4449 if (!Op.hasOneUse()) 4450 return SDValue(); 4451 SDNode *User = *Op.getNode()->use_begin(); 4452 if ((User->getOpcode() != ISD::STORE || 4453 (isa<ConstantSDNode>(Op.getOperand(1)) && 4454 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4455 (User->getOpcode() != ISD::BIT_CONVERT || 4456 User->getValueType(0) != MVT::i32)) 4457 return SDValue(); 4458 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4459 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4460 Op.getOperand(0)), 4461 Op.getOperand(1)); 4462 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4463 } else if (VT == MVT::i32) { 4464 // ExtractPS works with constant index. 4465 if (isa<ConstantSDNode>(Op.getOperand(1))) 4466 return Op; 4467 } 4468 return SDValue(); 4469} 4470 4471 4472SDValue 4473X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4474 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4475 return SDValue(); 4476 4477 if (Subtarget->hasSSE41()) { 4478 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4479 if (Res.getNode()) 4480 return Res; 4481 } 4482 4483 MVT VT = Op.getValueType(); 4484 DebugLoc dl = Op.getDebugLoc(); 4485 // TODO: handle v16i8. 4486 if (VT.getSizeInBits() == 16) { 4487 SDValue Vec = Op.getOperand(0); 4488 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4489 if (Idx == 0) 4490 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4491 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4492 DAG.getNode(ISD::BIT_CONVERT, dl, 4493 MVT::v4i32, Vec), 4494 Op.getOperand(1))); 4495 // Transform it so it match pextrw which produces a 32-bit result. 4496 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); 4497 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT, 4498 Op.getOperand(0), Op.getOperand(1)); 4499 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract, 4500 DAG.getValueType(VT)); 4501 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4502 } else if (VT.getSizeInBits() == 32) { 4503 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4504 if (Idx == 0) 4505 return Op; 4506 // SHUFPS the element to the lowest double word, then movss. 4507 MVT MaskVT = MVT::getIntVectorWithNumElements(4); 4508 SmallVector<SDValue, 8> IdxVec; 4509 IdxVec. 4510 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); 4511 IdxVec. 4512 push_back(DAG.getUNDEF(MaskVT.getVectorElementType())); 4513 IdxVec. 4514 push_back(DAG.getUNDEF(MaskVT.getVectorElementType())); 4515 IdxVec. 4516 push_back(DAG.getUNDEF(MaskVT.getVectorElementType())); 4517 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4518 &IdxVec[0], IdxVec.size()); 4519 SDValue Vec = Op.getOperand(0); 4520 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(), 4521 Vec, DAG.getUNDEF(Vec.getValueType()), Mask); 4522 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4523 DAG.getIntPtrConstant(0)); 4524 } else if (VT.getSizeInBits() == 64) { 4525 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4526 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4527 // to match extract_elt for f64. 4528 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4529 if (Idx == 0) 4530 return Op; 4531 4532 // UNPCKHPD the element to the lowest double word, then movsd. 4533 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4534 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4535 MVT MaskVT = MVT::getIntVectorWithNumElements(2); 4536 SmallVector<SDValue, 8> IdxVec; 4537 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); 4538 IdxVec. 4539 push_back(DAG.getUNDEF(MaskVT.getVectorElementType())); 4540 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, 4541 &IdxVec[0], IdxVec.size()); 4542 SDValue Vec = Op.getOperand(0); 4543 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(), 4544 Vec, DAG.getUNDEF(Vec.getValueType()), 4545 Mask); 4546 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4547 DAG.getIntPtrConstant(0)); 4548 } 4549 4550 return SDValue(); 4551} 4552 4553SDValue 4554X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4555 MVT VT = Op.getValueType(); 4556 MVT EVT = VT.getVectorElementType(); 4557 DebugLoc dl = Op.getDebugLoc(); 4558 4559 SDValue N0 = Op.getOperand(0); 4560 SDValue N1 = Op.getOperand(1); 4561 SDValue N2 = Op.getOperand(2); 4562 4563 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4564 isa<ConstantSDNode>(N2)) { 4565 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4566 : X86ISD::PINSRW; 4567 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4568 // argument. 4569 if (N1.getValueType() != MVT::i32) 4570 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4571 if (N2.getValueType() != MVT::i32) 4572 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4573 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4574 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4575 // Bits [7:6] of the constant are the source select. This will always be 4576 // zero here. The DAG Combiner may combine an extract_elt index into these 4577 // bits. For example (insert (extract, 3), 2) could be matched by putting 4578 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4579 // Bits [5:4] of the constant are the destination select. This is the 4580 // value of the incoming immediate. 4581 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4582 // combine either bitwise AND or insert of float 0.0 to set these bits. 4583 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4584 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4585 } else if (EVT == MVT::i32) { 4586 // InsertPS works with constant index. 4587 if (isa<ConstantSDNode>(N2)) 4588 return Op; 4589 } 4590 return SDValue(); 4591} 4592 4593SDValue 4594X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4595 MVT VT = Op.getValueType(); 4596 MVT EVT = VT.getVectorElementType(); 4597 4598 if (Subtarget->hasSSE41()) 4599 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4600 4601 if (EVT == MVT::i8) 4602 return SDValue(); 4603 4604 DebugLoc dl = Op.getDebugLoc(); 4605 SDValue N0 = Op.getOperand(0); 4606 SDValue N1 = Op.getOperand(1); 4607 SDValue N2 = Op.getOperand(2); 4608 4609 if (EVT.getSizeInBits() == 16) { 4610 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4611 // as its second argument. 4612 if (N1.getValueType() != MVT::i32) 4613 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4614 if (N2.getValueType() != MVT::i32) 4615 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4616 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 4617 } 4618 return SDValue(); 4619} 4620 4621SDValue 4622X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4623 DebugLoc dl = Op.getDebugLoc(); 4624 if (Op.getValueType() == MVT::v2f32) 4625 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4626 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4627 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4628 Op.getOperand(0)))); 4629 4630 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4631 MVT VT = MVT::v2i32; 4632 switch (Op.getValueType().getSimpleVT()) { 4633 default: break; 4634 case MVT::v16i8: 4635 case MVT::v8i16: 4636 VT = MVT::v4i32; 4637 break; 4638 } 4639 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4640 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4641} 4642 4643// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4644// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4645// one of the above mentioned nodes. It has to be wrapped because otherwise 4646// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4647// be used to form addressing mode. These wrapped nodes will be selected 4648// into MOV32ri. 4649SDValue 4650X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4651 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4652 // FIXME there isn't really any debug info here, should come from the parent 4653 DebugLoc dl = CP->getDebugLoc(); 4654 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), 4655 getPointerTy(), 4656 CP->getAlignment()); 4657 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4658 // With PIC, the address is actually $g + Offset. 4659 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4660 !Subtarget->isPICStyleRIPRel()) { 4661 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4662 DAG.getNode(X86ISD::GlobalBaseReg, 4663 DebugLoc::getUnknownLoc(), 4664 getPointerTy()), 4665 Result); 4666 } 4667 4668 return Result; 4669} 4670 4671SDValue 4672X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 4673 int64_t Offset, 4674 SelectionDAG &DAG) const { 4675 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 4676 bool ExtraLoadRequired = 4677 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false); 4678 4679 // Create the TargetGlobalAddress node, folding in the constant 4680 // offset if it is legal. 4681 SDValue Result; 4682 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) { 4683 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 4684 Offset = 0; 4685 } else 4686 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0); 4687 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4688 4689 // With PIC, the address is actually $g + Offset. 4690 if (IsPic && !Subtarget->isPICStyleRIPRel()) { 4691 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4692 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 4693 Result); 4694 } 4695 4696 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 4697 // load the value at address GV, not the value of GV itself. This means that 4698 // the GlobalAddress must be in the base or index register of the address, not 4699 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 4700 // The same applies for external symbols during PIC codegen 4701 if (ExtraLoadRequired) 4702 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 4703 PseudoSourceValue::getGOT(), 0); 4704 4705 // If there was a non-zero offset that we didn't fold, create an explicit 4706 // addition for it. 4707 if (Offset != 0) 4708 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 4709 DAG.getConstant(Offset, getPointerTy())); 4710 4711 return Result; 4712} 4713 4714SDValue 4715X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4716 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4717 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 4718 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 4719} 4720 4721// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4722static SDValue 4723LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4724 const MVT PtrVT) { 4725 SDValue InFlag; 4726 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 4727 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 4728 DAG.getNode(X86ISD::GlobalBaseReg, 4729 DebugLoc::getUnknownLoc(), 4730 PtrVT), InFlag); 4731 InFlag = Chain.getValue(1); 4732 4733 // emit leal symbol@TLSGD(,%ebx,1), %eax 4734 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4735 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4736 GA->getValueType(0), 4737 GA->getOffset()); 4738 SDValue Ops[] = { Chain, TGA, InFlag }; 4739 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 4740 InFlag = Result.getValue(2); 4741 Chain = Result.getValue(1); 4742 4743 // call ___tls_get_addr. This function receives its argument in 4744 // the register EAX. 4745 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag); 4746 InFlag = Chain.getValue(1); 4747 4748 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4749 SDValue Ops1[] = { Chain, 4750 DAG.getTargetExternalSymbol("___tls_get_addr", 4751 PtrVT), 4752 DAG.getRegister(X86::EAX, PtrVT), 4753 DAG.getRegister(X86::EBX, PtrVT), 4754 InFlag }; 4755 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 5); 4756 InFlag = Chain.getValue(1); 4757 4758 return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag); 4759} 4760 4761// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4762static SDValue 4763LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4764 const MVT PtrVT) { 4765 SDValue InFlag, Chain; 4766 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 4767 4768 // emit leaq symbol@TLSGD(%rip), %rdi 4769 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4770 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4771 GA->getValueType(0), 4772 GA->getOffset()); 4773 SDValue Ops[] = { DAG.getEntryNode(), TGA}; 4774 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 4775 Chain = Result.getValue(1); 4776 InFlag = Result.getValue(2); 4777 4778 // call __tls_get_addr. This function receives its argument in 4779 // the register RDI. 4780 Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag); 4781 InFlag = Chain.getValue(1); 4782 4783 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4784 SDValue Ops1[] = { Chain, 4785 DAG.getTargetExternalSymbol("__tls_get_addr", 4786 PtrVT), 4787 DAG.getRegister(X86::RDI, PtrVT), 4788 InFlag }; 4789 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 4); 4790 InFlag = Chain.getValue(1); 4791 4792 return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag); 4793} 4794 4795// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4796// "local exec" model. 4797static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4798 const MVT PtrVT, TLSModel::Model model) { 4799 DebugLoc dl = GA->getDebugLoc(); 4800 // Get the Thread Pointer 4801 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, 4802 DebugLoc::getUnknownLoc(), PtrVT); 4803 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4804 // exec) 4805 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4806 GA->getValueType(0), 4807 GA->getOffset()); 4808 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA); 4809 4810 if (model == TLSModel::InitialExec) 4811 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 4812 PseudoSourceValue::getGOT(), 0); 4813 4814 // The address of the thread local variable is the add of the thread 4815 // pointer with the offset of the variable. 4816 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 4817} 4818 4819SDValue 4820X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4821 // TODO: implement the "local dynamic" model 4822 // TODO: implement the "initial exec"model for pic executables 4823 assert(Subtarget->isTargetELF() && 4824 "TLS not implemented for non-ELF targets"); 4825 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4826 GlobalValue *GV = GA->getGlobal(); 4827 TLSModel::Model model = 4828 getTLSModel (GV, getTargetMachine().getRelocationModel()); 4829 if (Subtarget->is64Bit()) { 4830 switch (model) { 4831 case TLSModel::GeneralDynamic: 4832 case TLSModel::LocalDynamic: // not implemented 4833 case TLSModel::InitialExec: // not implemented 4834 case TLSModel::LocalExec: // not implemented 4835 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4836 default: 4837 assert (0 && "Unknown TLS model"); 4838 } 4839 } else { 4840 switch (model) { 4841 case TLSModel::GeneralDynamic: 4842 case TLSModel::LocalDynamic: // not implemented 4843 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4844 4845 case TLSModel::InitialExec: 4846 case TLSModel::LocalExec: 4847 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model); 4848 default: 4849 assert (0 && "Unknown TLS model"); 4850 } 4851 } 4852} 4853 4854SDValue 4855X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4856 // FIXME there isn't really any debug info here 4857 DebugLoc dl = Op.getDebugLoc(); 4858 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4859 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 4860 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4861 // With PIC, the address is actually $g + Offset. 4862 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4863 !Subtarget->isPICStyleRIPRel()) { 4864 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4865 DAG.getNode(X86ISD::GlobalBaseReg, 4866 DebugLoc::getUnknownLoc(), 4867 getPointerTy()), 4868 Result); 4869 } 4870 4871 return Result; 4872} 4873 4874SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4875 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4876 // FIXME there isn't really any debug into here 4877 DebugLoc dl = JT->getDebugLoc(); 4878 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 4879 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4880 // With PIC, the address is actually $g + Offset. 4881 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4882 !Subtarget->isPICStyleRIPRel()) { 4883 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4884 DAG.getNode(X86ISD::GlobalBaseReg, 4885 DebugLoc::getUnknownLoc(), 4886 getPointerTy()), 4887 Result); 4888 } 4889 4890 return Result; 4891} 4892 4893/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4894/// take a 2 x i32 value to shift plus a shift amount. 4895SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4896 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4897 MVT VT = Op.getValueType(); 4898 unsigned VTBits = VT.getSizeInBits(); 4899 DebugLoc dl = Op.getDebugLoc(); 4900 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4901 SDValue ShOpLo = Op.getOperand(0); 4902 SDValue ShOpHi = Op.getOperand(1); 4903 SDValue ShAmt = Op.getOperand(2); 4904 SDValue Tmp1 = isSRA ? 4905 DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 4906 DAG.getConstant(VTBits - 1, MVT::i8)) : 4907 DAG.getConstant(0, VT); 4908 4909 SDValue Tmp2, Tmp3; 4910 if (Op.getOpcode() == ISD::SHL_PARTS) { 4911 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 4912 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 4913 } else { 4914 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 4915 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 4916 } 4917 4918 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 4919 DAG.getConstant(VTBits, MVT::i8)); 4920 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, 4921 AndNode, DAG.getConstant(0, MVT::i8)); 4922 4923 SDValue Hi, Lo; 4924 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4925 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4926 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4927 4928 if (Op.getOpcode() == ISD::SHL_PARTS) { 4929 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4930 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4931 } else { 4932 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4933 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4934 } 4935 4936 SDValue Ops[2] = { Lo, Hi }; 4937 return DAG.getMergeValues(Ops, 2, dl); 4938} 4939 4940SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4941 MVT SrcVT = Op.getOperand(0).getValueType(); 4942 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4943 "Unknown SINT_TO_FP to lower!"); 4944 4945 // These are really Legal; caller falls through into that case. 4946 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4947 return SDValue(); 4948 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && 4949 Subtarget->is64Bit()) 4950 return SDValue(); 4951 4952 DebugLoc dl = Op.getDebugLoc(); 4953 unsigned Size = SrcVT.getSizeInBits()/8; 4954 MachineFunction &MF = DAG.getMachineFunction(); 4955 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4956 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4957 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 4958 StackSlot, 4959 PseudoSourceValue::getFixedStack(SSFI), 0); 4960 4961 // Build the FILD 4962 SDVTList Tys; 4963 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4964 if (useSSE) 4965 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4966 else 4967 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4968 SmallVector<SDValue, 8> Ops; 4969 Ops.push_back(Chain); 4970 Ops.push_back(StackSlot); 4971 Ops.push_back(DAG.getValueType(SrcVT)); 4972 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 4973 Tys, &Ops[0], Ops.size()); 4974 4975 if (useSSE) { 4976 Chain = Result.getValue(1); 4977 SDValue InFlag = Result.getValue(2); 4978 4979 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4980 // shouldn't be necessary except that RFP cannot be live across 4981 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4982 MachineFunction &MF = DAG.getMachineFunction(); 4983 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4984 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4985 Tys = DAG.getVTList(MVT::Other); 4986 SmallVector<SDValue, 8> Ops; 4987 Ops.push_back(Chain); 4988 Ops.push_back(Result); 4989 Ops.push_back(StackSlot); 4990 Ops.push_back(DAG.getValueType(Op.getValueType())); 4991 Ops.push_back(InFlag); 4992 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size()); 4993 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 4994 PseudoSourceValue::getFixedStack(SSFI), 0); 4995 } 4996 4997 return Result; 4998} 4999 5000// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5001SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 5002 // This algorithm is not obvious. Here it is in C code, more or less: 5003 /* 5004 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5005 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5006 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5007 5008 // Copy ints to xmm registers. 5009 __m128i xh = _mm_cvtsi32_si128( hi ); 5010 __m128i xl = _mm_cvtsi32_si128( lo ); 5011 5012 // Combine into low half of a single xmm register. 5013 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5014 __m128d d; 5015 double sd; 5016 5017 // Merge in appropriate exponents to give the integer bits the right 5018 // magnitude. 5019 x = _mm_unpacklo_epi32( x, exp ); 5020 5021 // Subtract away the biases to deal with the IEEE-754 double precision 5022 // implicit 1. 5023 d = _mm_sub_pd( (__m128d) x, bias ); 5024 5025 // All conversions up to here are exact. The correctly rounded result is 5026 // calculated using the current rounding mode using the following 5027 // horizontal add. 5028 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5029 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5030 // store doesn't really need to be here (except 5031 // maybe to zero the other double) 5032 return sd; 5033 } 5034 */ 5035 5036 DebugLoc dl = Op.getDebugLoc(); 5037 5038 // Build some magic constants. 5039 std::vector<Constant*> CV0; 5040 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000))); 5041 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000))); 5042 CV0.push_back(ConstantInt::get(APInt(32, 0))); 5043 CV0.push_back(ConstantInt::get(APInt(32, 0))); 5044 Constant *C0 = ConstantVector::get(CV0); 5045 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4); 5046 5047 std::vector<Constant*> CV1; 5048 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL)))); 5049 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL)))); 5050 Constant *C1 = ConstantVector::get(CV1); 5051 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4); 5052 5053 SmallVector<SDValue, 4> MaskVec; 5054 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 5055 MaskVec.push_back(DAG.getConstant(4, MVT::i32)); 5056 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 5057 MaskVec.push_back(DAG.getConstant(5, MVT::i32)); 5058 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 5059 &MaskVec[0], MaskVec.size()); 5060 SmallVector<SDValue, 4> MaskVec2; 5061 MaskVec2.push_back(DAG.getConstant(1, MVT::i32)); 5062 MaskVec2.push_back(DAG.getConstant(0, MVT::i32)); 5063 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, 5064 &MaskVec2[0], MaskVec2.size()); 5065 5066 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5067 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5068 Op.getOperand(0), 5069 DAG.getIntPtrConstant(1))); 5070 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5071 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5072 Op.getOperand(0), 5073 DAG.getIntPtrConstant(0))); 5074 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32, 5075 XR1, XR2, UnpcklMask); 5076 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5077 PseudoSourceValue::getConstantPool(), 0, 5078 false, 16); 5079 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32, 5080 Unpck1, CLod0, UnpcklMask); 5081 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5082 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5083 PseudoSourceValue::getConstantPool(), 0, 5084 false, 16); 5085 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5086 5087 // Add the halves; easiest way is to swap them into another reg first. 5088 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64, 5089 Sub, Sub, ShufMask); 5090 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5091 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5092 DAG.getIntPtrConstant(0)); 5093} 5094 5095// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5096SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5097 DebugLoc dl = Op.getDebugLoc(); 5098 // FP constant to bias correct the final result. 5099 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5100 MVT::f64); 5101 5102 // Load the 32-bit value into an XMM register. 5103 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5104 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5105 Op.getOperand(0), 5106 DAG.getIntPtrConstant(0))); 5107 5108 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5109 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5110 DAG.getIntPtrConstant(0)); 5111 5112 // Or the load with the bias. 5113 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5114 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5115 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5116 MVT::v2f64, Load)), 5117 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5118 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5119 MVT::v2f64, Bias))); 5120 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5121 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5122 DAG.getIntPtrConstant(0)); 5123 5124 // Subtract the bias. 5125 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5126 5127 // Handle final rounding. 5128 MVT DestVT = Op.getValueType(); 5129 5130 if (DestVT.bitsLT(MVT::f64)) { 5131 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5132 DAG.getIntPtrConstant(0)); 5133 } else if (DestVT.bitsGT(MVT::f64)) { 5134 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5135 } 5136 5137 // Handle final rounding. 5138 return Sub; 5139} 5140 5141SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5142 SDValue N0 = Op.getOperand(0); 5143 DebugLoc dl = Op.getDebugLoc(); 5144 5145 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5146 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5147 // the optimization here. 5148 if (DAG.SignBitIsZero(N0)) 5149 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5150 5151 MVT SrcVT = N0.getValueType(); 5152 if (SrcVT == MVT::i64) { 5153 // We only handle SSE2 f64 target here; caller can handle the rest. 5154 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5155 return SDValue(); 5156 5157 return LowerUINT_TO_FP_i64(Op, DAG); 5158 } else if (SrcVT == MVT::i32) { 5159 return LowerUINT_TO_FP_i32(Op, DAG); 5160 } 5161 5162 assert(0 && "Unknown UINT_TO_FP to lower!"); 5163 return SDValue(); 5164} 5165 5166std::pair<SDValue,SDValue> X86TargetLowering:: 5167FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) { 5168 DebugLoc dl = Op.getDebugLoc(); 5169 assert(Op.getValueType().getSimpleVT() <= MVT::i64 && 5170 Op.getValueType().getSimpleVT() >= MVT::i16 && 5171 "Unknown FP_TO_SINT to lower!"); 5172 5173 // These are really Legal. 5174 if (Op.getValueType() == MVT::i32 && 5175 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5176 return std::make_pair(SDValue(), SDValue()); 5177 if (Subtarget->is64Bit() && 5178 Op.getValueType() == MVT::i64 && 5179 Op.getOperand(0).getValueType() != MVT::f80) 5180 return std::make_pair(SDValue(), SDValue()); 5181 5182 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5183 // stack slot. 5184 MachineFunction &MF = DAG.getMachineFunction(); 5185 unsigned MemSize = Op.getValueType().getSizeInBits()/8; 5186 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5187 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5188 unsigned Opc; 5189 switch (Op.getValueType().getSimpleVT()) { 5190 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 5191 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5192 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5193 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5194 } 5195 5196 SDValue Chain = DAG.getEntryNode(); 5197 SDValue Value = Op.getOperand(0); 5198 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5199 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5200 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5201 PseudoSourceValue::getFixedStack(SSFI), 0); 5202 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5203 SDValue Ops[] = { 5204 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5205 }; 5206 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5207 Chain = Value.getValue(1); 5208 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5209 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5210 } 5211 5212 // Build the FP_TO_INT*_IN_MEM 5213 SDValue Ops[] = { Chain, Value, StackSlot }; 5214 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5215 5216 return std::make_pair(FIST, StackSlot); 5217} 5218 5219SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5220 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG); 5221 SDValue FIST = Vals.first, StackSlot = Vals.second; 5222 if (FIST.getNode() == 0) return SDValue(); 5223 5224 // Load the result. 5225 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5226 FIST, StackSlot, NULL, 0); 5227} 5228 5229SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5230 DebugLoc dl = Op.getDebugLoc(); 5231 MVT VT = Op.getValueType(); 5232 MVT EltVT = VT; 5233 if (VT.isVector()) 5234 EltVT = VT.getVectorElementType(); 5235 std::vector<Constant*> CV; 5236 if (EltVT == MVT::f64) { 5237 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); 5238 CV.push_back(C); 5239 CV.push_back(C); 5240 } else { 5241 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))); 5242 CV.push_back(C); 5243 CV.push_back(C); 5244 CV.push_back(C); 5245 CV.push_back(C); 5246 } 5247 Constant *C = ConstantVector::get(CV); 5248 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5249 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5250 PseudoSourceValue::getConstantPool(), 0, 5251 false, 16); 5252 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5253} 5254 5255SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5256 DebugLoc dl = Op.getDebugLoc(); 5257 MVT VT = Op.getValueType(); 5258 MVT EltVT = VT; 5259 unsigned EltNum = 1; 5260 if (VT.isVector()) { 5261 EltVT = VT.getVectorElementType(); 5262 EltNum = VT.getVectorNumElements(); 5263 } 5264 std::vector<Constant*> CV; 5265 if (EltVT == MVT::f64) { 5266 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63))); 5267 CV.push_back(C); 5268 CV.push_back(C); 5269 } else { 5270 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31))); 5271 CV.push_back(C); 5272 CV.push_back(C); 5273 CV.push_back(C); 5274 CV.push_back(C); 5275 } 5276 Constant *C = ConstantVector::get(CV); 5277 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5278 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5279 PseudoSourceValue::getConstantPool(), 0, 5280 false, 16); 5281 if (VT.isVector()) { 5282 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5283 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5284 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5285 Op.getOperand(0)), 5286 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5287 } else { 5288 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5289 } 5290} 5291 5292SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5293 SDValue Op0 = Op.getOperand(0); 5294 SDValue Op1 = Op.getOperand(1); 5295 DebugLoc dl = Op.getDebugLoc(); 5296 MVT VT = Op.getValueType(); 5297 MVT SrcVT = Op1.getValueType(); 5298 5299 // If second operand is smaller, extend it first. 5300 if (SrcVT.bitsLT(VT)) { 5301 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5302 SrcVT = VT; 5303 } 5304 // And if it is bigger, shrink it first. 5305 if (SrcVT.bitsGT(VT)) { 5306 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5307 SrcVT = VT; 5308 } 5309 5310 // At this point the operands and the result should have the same 5311 // type, and that won't be f80 since that is not custom lowered. 5312 5313 // First get the sign bit of second operand. 5314 std::vector<Constant*> CV; 5315 if (SrcVT == MVT::f64) { 5316 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63)))); 5317 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5318 } else { 5319 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31)))); 5320 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5321 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5322 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5323 } 5324 Constant *C = ConstantVector::get(CV); 5325 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5326 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5327 PseudoSourceValue::getConstantPool(), 0, 5328 false, 16); 5329 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5330 5331 // Shift sign bit right or left if the two operands have different types. 5332 if (SrcVT.bitsGT(VT)) { 5333 // Op0 is MVT::f32, Op1 is MVT::f64. 5334 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5335 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5336 DAG.getConstant(32, MVT::i32)); 5337 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5338 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5339 DAG.getIntPtrConstant(0)); 5340 } 5341 5342 // Clear first operand sign bit. 5343 CV.clear(); 5344 if (VT == MVT::f64) { 5345 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))))); 5346 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5347 } else { 5348 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31))))); 5349 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5350 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5351 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5352 } 5353 C = ConstantVector::get(CV); 5354 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 5355 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5356 PseudoSourceValue::getConstantPool(), 0, 5357 false, 16); 5358 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5359 5360 // Or the value with the sign bit. 5361 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5362} 5363 5364SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5365 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5366 SDValue Op0 = Op.getOperand(0); 5367 SDValue Op1 = Op.getOperand(1); 5368 DebugLoc dl = Op.getDebugLoc(); 5369 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5370 5371 // Lower (X & (1 << N)) == 0 to BT(X, N). 5372 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5373 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5374 if (Op0.getOpcode() == ISD::AND && 5375 Op0.hasOneUse() && 5376 Op1.getOpcode() == ISD::Constant && 5377 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5378 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5379 SDValue LHS, RHS; 5380 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5381 if (ConstantSDNode *Op010C = 5382 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5383 if (Op010C->getZExtValue() == 1) { 5384 LHS = Op0.getOperand(0); 5385 RHS = Op0.getOperand(1).getOperand(1); 5386 } 5387 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5388 if (ConstantSDNode *Op000C = 5389 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5390 if (Op000C->getZExtValue() == 1) { 5391 LHS = Op0.getOperand(1); 5392 RHS = Op0.getOperand(0).getOperand(1); 5393 } 5394 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5395 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5396 SDValue AndLHS = Op0.getOperand(0); 5397 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5398 LHS = AndLHS.getOperand(0); 5399 RHS = AndLHS.getOperand(1); 5400 } 5401 } 5402 5403 if (LHS.getNode()) { 5404 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5405 // instruction. Since the shift amount is in-range-or-undefined, we know 5406 // that doing a bittest on the i16 value is ok. We extend to i32 because 5407 // the encoding for the i16 version is larger than the i32 version. 5408 if (LHS.getValueType() == MVT::i8) 5409 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5410 5411 // If the operand types disagree, extend the shift amount to match. Since 5412 // BT ignores high bits (like shifts) we can use anyextend. 5413 if (LHS.getValueType() != RHS.getValueType()) 5414 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5415 5416 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5417 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5418 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5419 DAG.getConstant(Cond, MVT::i8), BT); 5420 } 5421 } 5422 5423 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5424 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5425 5426 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5427 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5428 DAG.getConstant(X86CC, MVT::i8), Cond); 5429} 5430 5431SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5432 SDValue Cond; 5433 SDValue Op0 = Op.getOperand(0); 5434 SDValue Op1 = Op.getOperand(1); 5435 SDValue CC = Op.getOperand(2); 5436 MVT VT = Op.getValueType(); 5437 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5438 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5439 DebugLoc dl = Op.getDebugLoc(); 5440 5441 if (isFP) { 5442 unsigned SSECC = 8; 5443 MVT VT0 = Op0.getValueType(); 5444 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5445 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5446 bool Swap = false; 5447 5448 switch (SetCCOpcode) { 5449 default: break; 5450 case ISD::SETOEQ: 5451 case ISD::SETEQ: SSECC = 0; break; 5452 case ISD::SETOGT: 5453 case ISD::SETGT: Swap = true; // Fallthrough 5454 case ISD::SETLT: 5455 case ISD::SETOLT: SSECC = 1; break; 5456 case ISD::SETOGE: 5457 case ISD::SETGE: Swap = true; // Fallthrough 5458 case ISD::SETLE: 5459 case ISD::SETOLE: SSECC = 2; break; 5460 case ISD::SETUO: SSECC = 3; break; 5461 case ISD::SETUNE: 5462 case ISD::SETNE: SSECC = 4; break; 5463 case ISD::SETULE: Swap = true; 5464 case ISD::SETUGE: SSECC = 5; break; 5465 case ISD::SETULT: Swap = true; 5466 case ISD::SETUGT: SSECC = 6; break; 5467 case ISD::SETO: SSECC = 7; break; 5468 } 5469 if (Swap) 5470 std::swap(Op0, Op1); 5471 5472 // In the two special cases we can't handle, emit two comparisons. 5473 if (SSECC == 8) { 5474 if (SetCCOpcode == ISD::SETUEQ) { 5475 SDValue UNORD, EQ; 5476 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 5477 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 5478 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 5479 } 5480 else if (SetCCOpcode == ISD::SETONE) { 5481 SDValue ORD, NEQ; 5482 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 5483 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 5484 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 5485 } 5486 assert(0 && "Illegal FP comparison"); 5487 } 5488 // Handle all other FP comparisons here. 5489 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 5490 } 5491 5492 // We are handling one of the integer comparisons here. Since SSE only has 5493 // GT and EQ comparisons for integer, swapping operands and multiple 5494 // operations may be required for some comparisons. 5495 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 5496 bool Swap = false, Invert = false, FlipSigns = false; 5497 5498 switch (VT.getSimpleVT()) { 5499 default: break; 5500 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 5501 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 5502 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 5503 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 5504 } 5505 5506 switch (SetCCOpcode) { 5507 default: break; 5508 case ISD::SETNE: Invert = true; 5509 case ISD::SETEQ: Opc = EQOpc; break; 5510 case ISD::SETLT: Swap = true; 5511 case ISD::SETGT: Opc = GTOpc; break; 5512 case ISD::SETGE: Swap = true; 5513 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 5514 case ISD::SETULT: Swap = true; 5515 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 5516 case ISD::SETUGE: Swap = true; 5517 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 5518 } 5519 if (Swap) 5520 std::swap(Op0, Op1); 5521 5522 // Since SSE has no unsigned integer comparisons, we need to flip the sign 5523 // bits of the inputs before performing those operations. 5524 if (FlipSigns) { 5525 MVT EltVT = VT.getVectorElementType(); 5526 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 5527 EltVT); 5528 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 5529 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 5530 SignBits.size()); 5531 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 5532 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 5533 } 5534 5535 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 5536 5537 // If the logical-not of the result is required, perform that now. 5538 if (Invert) 5539 Result = DAG.getNOT(dl, Result, VT); 5540 5541 return Result; 5542} 5543 5544// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 5545static bool isX86LogicalCmp(unsigned Opc) { 5546 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI; 5547} 5548 5549SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 5550 bool addTest = true; 5551 SDValue Cond = Op.getOperand(0); 5552 DebugLoc dl = Op.getDebugLoc(); 5553 SDValue CC; 5554 5555 if (Cond.getOpcode() == ISD::SETCC) 5556 Cond = LowerSETCC(Cond, DAG); 5557 5558 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5559 // setting operand in place of the X86ISD::SETCC. 5560 if (Cond.getOpcode() == X86ISD::SETCC) { 5561 CC = Cond.getOperand(0); 5562 5563 SDValue Cmp = Cond.getOperand(1); 5564 unsigned Opc = Cmp.getOpcode(); 5565 MVT VT = Op.getValueType(); 5566 5567 bool IllegalFPCMov = false; 5568 if (VT.isFloatingPoint() && !VT.isVector() && 5569 !isScalarFPTypeInSSEReg(VT)) // FPStack? 5570 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 5571 5572 if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME 5573 Cond = Cmp; 5574 addTest = false; 5575 } 5576 } 5577 5578 if (addTest) { 5579 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5580 Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond, 5581 DAG.getConstant(0, MVT::i8)); 5582 } 5583 5584 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), 5585 MVT::Flag); 5586 SmallVector<SDValue, 4> Ops; 5587 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 5588 // condition is true. 5589 Ops.push_back(Op.getOperand(2)); 5590 Ops.push_back(Op.getOperand(1)); 5591 Ops.push_back(CC); 5592 Ops.push_back(Cond); 5593 return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size()); 5594} 5595 5596// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 5597// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 5598// from the AND / OR. 5599static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 5600 Opc = Op.getOpcode(); 5601 if (Opc != ISD::OR && Opc != ISD::AND) 5602 return false; 5603 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5604 Op.getOperand(0).hasOneUse() && 5605 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 5606 Op.getOperand(1).hasOneUse()); 5607} 5608 5609// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 5610// 1 and that the SETCC node has a single use. 5611static bool isXor1OfSetCC(SDValue Op) { 5612 if (Op.getOpcode() != ISD::XOR) 5613 return false; 5614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5615 if (N1C && N1C->getAPIntValue() == 1) { 5616 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5617 Op.getOperand(0).hasOneUse(); 5618 } 5619 return false; 5620} 5621 5622SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 5623 bool addTest = true; 5624 SDValue Chain = Op.getOperand(0); 5625 SDValue Cond = Op.getOperand(1); 5626 SDValue Dest = Op.getOperand(2); 5627 DebugLoc dl = Op.getDebugLoc(); 5628 SDValue CC; 5629 5630 if (Cond.getOpcode() == ISD::SETCC) 5631 Cond = LowerSETCC(Cond, DAG); 5632#if 0 5633 // FIXME: LowerXALUO doesn't handle these!! 5634 else if (Cond.getOpcode() == X86ISD::ADD || 5635 Cond.getOpcode() == X86ISD::SUB || 5636 Cond.getOpcode() == X86ISD::SMUL || 5637 Cond.getOpcode() == X86ISD::UMUL) 5638 Cond = LowerXALUO(Cond, DAG); 5639#endif 5640 5641 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5642 // setting operand in place of the X86ISD::SETCC. 5643 if (Cond.getOpcode() == X86ISD::SETCC) { 5644 CC = Cond.getOperand(0); 5645 5646 SDValue Cmp = Cond.getOperand(1); 5647 unsigned Opc = Cmp.getOpcode(); 5648 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 5649 if (isX86LogicalCmp(Opc) || Opc == X86ISD::BT) { 5650 Cond = Cmp; 5651 addTest = false; 5652 } else { 5653 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 5654 default: break; 5655 case X86::COND_O: 5656 case X86::COND_B: 5657 // These can only come from an arithmetic instruction with overflow, 5658 // e.g. SADDO, UADDO. 5659 Cond = Cond.getNode()->getOperand(1); 5660 addTest = false; 5661 break; 5662 } 5663 } 5664 } else { 5665 unsigned CondOpc; 5666 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 5667 SDValue Cmp = Cond.getOperand(0).getOperand(1); 5668 unsigned Opc = Cmp.getOpcode(); 5669 if (CondOpc == ISD::OR) { 5670 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 5671 // two branches instead of an explicit OR instruction with a 5672 // separate test. 5673 if (Cmp == Cond.getOperand(1).getOperand(1) && 5674 isX86LogicalCmp(Opc)) { 5675 CC = Cond.getOperand(0).getOperand(0); 5676 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5677 Chain, Dest, CC, Cmp); 5678 CC = Cond.getOperand(1).getOperand(0); 5679 Cond = Cmp; 5680 addTest = false; 5681 } 5682 } else { // ISD::AND 5683 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 5684 // two branches instead of an explicit AND instruction with a 5685 // separate test. However, we only do this if this block doesn't 5686 // have a fall-through edge, because this requires an explicit 5687 // jmp when the condition is false. 5688 if (Cmp == Cond.getOperand(1).getOperand(1) && 5689 isX86LogicalCmp(Opc) && 5690 Op.getNode()->hasOneUse()) { 5691 X86::CondCode CCode = 5692 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5693 CCode = X86::GetOppositeBranchCondition(CCode); 5694 CC = DAG.getConstant(CCode, MVT::i8); 5695 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 5696 // Look for an unconditional branch following this conditional branch. 5697 // We need this because we need to reverse the successors in order 5698 // to implement FCMP_OEQ. 5699 if (User.getOpcode() == ISD::BR) { 5700 SDValue FalseBB = User.getOperand(1); 5701 SDValue NewBR = 5702 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 5703 assert(NewBR == User); 5704 Dest = FalseBB; 5705 5706 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5707 Chain, Dest, CC, Cmp); 5708 X86::CondCode CCode = 5709 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 5710 CCode = X86::GetOppositeBranchCondition(CCode); 5711 CC = DAG.getConstant(CCode, MVT::i8); 5712 Cond = Cmp; 5713 addTest = false; 5714 } 5715 } 5716 } 5717 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 5718 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 5719 // It should be transformed during dag combiner except when the condition 5720 // is set by a arithmetics with overflow node. 5721 X86::CondCode CCode = 5722 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5723 CCode = X86::GetOppositeBranchCondition(CCode); 5724 CC = DAG.getConstant(CCode, MVT::i8); 5725 Cond = Cond.getOperand(0).getOperand(1); 5726 addTest = false; 5727 } 5728 } 5729 5730 if (addTest) { 5731 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5732 Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond, 5733 DAG.getConstant(0, MVT::i8)); 5734 } 5735 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5736 Chain, Dest, CC, Cond); 5737} 5738 5739 5740// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 5741// Calls to _alloca is needed to probe the stack when allocating more than 4k 5742// bytes in one go. Touching the stack at 4K increments is necessary to ensure 5743// that the guard pages used by the OS virtual memory manager are allocated in 5744// correct sequence. 5745SDValue 5746X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5747 SelectionDAG &DAG) { 5748 assert(Subtarget->isTargetCygMing() && 5749 "This should be used only on Cygwin/Mingw targets"); 5750 DebugLoc dl = Op.getDebugLoc(); 5751 5752 // Get the inputs. 5753 SDValue Chain = Op.getOperand(0); 5754 SDValue Size = Op.getOperand(1); 5755 // FIXME: Ensure alignment here 5756 5757 SDValue Flag; 5758 5759 MVT IntPtr = getPointerTy(); 5760 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5761 5762 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 5763 5764 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 5765 Flag = Chain.getValue(1); 5766 5767 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5768 SDValue Ops[] = { Chain, 5769 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5770 DAG.getRegister(X86::EAX, IntPtr), 5771 DAG.getRegister(X86StackPtr, SPTy), 5772 Flag }; 5773 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); 5774 Flag = Chain.getValue(1); 5775 5776 Chain = DAG.getCALLSEQ_END(Chain, 5777 DAG.getIntPtrConstant(0, true), 5778 DAG.getIntPtrConstant(0, true), 5779 Flag); 5780 5781 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 5782 5783 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5784 return DAG.getMergeValues(Ops1, 2, dl); 5785} 5786 5787SDValue 5788X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 5789 SDValue Chain, 5790 SDValue Dst, SDValue Src, 5791 SDValue Size, unsigned Align, 5792 const Value *DstSV, 5793 uint64_t DstSVOff) { 5794 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5795 5796 // If not DWORD aligned or size is more than the threshold, call the library. 5797 // The libc version is likely to be faster for these cases. It can use the 5798 // address value and run time information about the CPU. 5799 if ((Align & 3) != 0 || 5800 !ConstantSize || 5801 ConstantSize->getZExtValue() > 5802 getSubtarget()->getMaxInlineSizeThreshold()) { 5803 SDValue InFlag(0, 0); 5804 5805 // Check to see if there is a specialized entry-point for memory zeroing. 5806 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5807 5808 if (const char *bzeroEntry = V && 5809 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5810 MVT IntPtr = getPointerTy(); 5811 const Type *IntPtrTy = TD->getIntPtrType(); 5812 TargetLowering::ArgListTy Args; 5813 TargetLowering::ArgListEntry Entry; 5814 Entry.Node = Dst; 5815 Entry.Ty = IntPtrTy; 5816 Args.push_back(Entry); 5817 Entry.Node = Size; 5818 Args.push_back(Entry); 5819 std::pair<SDValue,SDValue> CallResult = 5820 LowerCallTo(Chain, Type::VoidTy, false, false, false, false, 5821 CallingConv::C, false, 5822 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 5823 return CallResult.second; 5824 } 5825 5826 // Otherwise have the target-independent code call memset. 5827 return SDValue(); 5828 } 5829 5830 uint64_t SizeVal = ConstantSize->getZExtValue(); 5831 SDValue InFlag(0, 0); 5832 MVT AVT; 5833 SDValue Count; 5834 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5835 unsigned BytesLeft = 0; 5836 bool TwoRepStos = false; 5837 if (ValC) { 5838 unsigned ValReg; 5839 uint64_t Val = ValC->getZExtValue() & 255; 5840 5841 // If the value is a constant, then we can potentially use larger sets. 5842 switch (Align & 3) { 5843 case 2: // WORD aligned 5844 AVT = MVT::i16; 5845 ValReg = X86::AX; 5846 Val = (Val << 8) | Val; 5847 break; 5848 case 0: // DWORD aligned 5849 AVT = MVT::i32; 5850 ValReg = X86::EAX; 5851 Val = (Val << 8) | Val; 5852 Val = (Val << 16) | Val; 5853 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5854 AVT = MVT::i64; 5855 ValReg = X86::RAX; 5856 Val = (Val << 32) | Val; 5857 } 5858 break; 5859 default: // Byte aligned 5860 AVT = MVT::i8; 5861 ValReg = X86::AL; 5862 Count = DAG.getIntPtrConstant(SizeVal); 5863 break; 5864 } 5865 5866 if (AVT.bitsGT(MVT::i8)) { 5867 unsigned UBytes = AVT.getSizeInBits() / 8; 5868 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5869 BytesLeft = SizeVal % UBytes; 5870 } 5871 5872 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 5873 InFlag); 5874 InFlag = Chain.getValue(1); 5875 } else { 5876 AVT = MVT::i8; 5877 Count = DAG.getIntPtrConstant(SizeVal); 5878 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 5879 InFlag = Chain.getValue(1); 5880 } 5881 5882 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 5883 X86::ECX, 5884 Count, InFlag); 5885 InFlag = Chain.getValue(1); 5886 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 5887 X86::EDI, 5888 Dst, InFlag); 5889 InFlag = Chain.getValue(1); 5890 5891 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5892 SmallVector<SDValue, 8> Ops; 5893 Ops.push_back(Chain); 5894 Ops.push_back(DAG.getValueType(AVT)); 5895 Ops.push_back(InFlag); 5896 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5897 5898 if (TwoRepStos) { 5899 InFlag = Chain.getValue(1); 5900 Count = Size; 5901 MVT CVT = Count.getValueType(); 5902 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 5903 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5904 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 5905 X86::ECX, 5906 Left, InFlag); 5907 InFlag = Chain.getValue(1); 5908 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5909 Ops.clear(); 5910 Ops.push_back(Chain); 5911 Ops.push_back(DAG.getValueType(MVT::i8)); 5912 Ops.push_back(InFlag); 5913 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5914 } else if (BytesLeft) { 5915 // Handle the last 1 - 7 bytes. 5916 unsigned Offset = SizeVal - BytesLeft; 5917 MVT AddrVT = Dst.getValueType(); 5918 MVT SizeVT = Size.getValueType(); 5919 5920 Chain = DAG.getMemset(Chain, dl, 5921 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 5922 DAG.getConstant(Offset, AddrVT)), 5923 Src, 5924 DAG.getConstant(BytesLeft, SizeVT), 5925 Align, DstSV, DstSVOff + Offset); 5926 } 5927 5928 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 5929 return Chain; 5930} 5931 5932SDValue 5933X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 5934 SDValue Chain, SDValue Dst, SDValue Src, 5935 SDValue Size, unsigned Align, 5936 bool AlwaysInline, 5937 const Value *DstSV, uint64_t DstSVOff, 5938 const Value *SrcSV, uint64_t SrcSVOff) { 5939 // This requires the copy size to be a constant, preferrably 5940 // within a subtarget-specific limit. 5941 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5942 if (!ConstantSize) 5943 return SDValue(); 5944 uint64_t SizeVal = ConstantSize->getZExtValue(); 5945 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 5946 return SDValue(); 5947 5948 /// If not DWORD aligned, call the library. 5949 if ((Align & 3) != 0) 5950 return SDValue(); 5951 5952 // DWORD aligned 5953 MVT AVT = MVT::i32; 5954 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 5955 AVT = MVT::i64; 5956 5957 unsigned UBytes = AVT.getSizeInBits() / 8; 5958 unsigned CountVal = SizeVal / UBytes; 5959 SDValue Count = DAG.getIntPtrConstant(CountVal); 5960 unsigned BytesLeft = SizeVal % UBytes; 5961 5962 SDValue InFlag(0, 0); 5963 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 5964 X86::ECX, 5965 Count, InFlag); 5966 InFlag = Chain.getValue(1); 5967 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 5968 X86::EDI, 5969 Dst, InFlag); 5970 InFlag = Chain.getValue(1); 5971 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 5972 X86::ESI, 5973 Src, InFlag); 5974 InFlag = Chain.getValue(1); 5975 5976 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5977 SmallVector<SDValue, 8> Ops; 5978 Ops.push_back(Chain); 5979 Ops.push_back(DAG.getValueType(AVT)); 5980 Ops.push_back(InFlag); 5981 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size()); 5982 5983 SmallVector<SDValue, 4> Results; 5984 Results.push_back(RepMovs); 5985 if (BytesLeft) { 5986 // Handle the last 1 - 7 bytes. 5987 unsigned Offset = SizeVal - BytesLeft; 5988 MVT DstVT = Dst.getValueType(); 5989 MVT SrcVT = Src.getValueType(); 5990 MVT SizeVT = Size.getValueType(); 5991 Results.push_back(DAG.getMemcpy(Chain, dl, 5992 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 5993 DAG.getConstant(Offset, DstVT)), 5994 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 5995 DAG.getConstant(Offset, SrcVT)), 5996 DAG.getConstant(BytesLeft, SizeVT), 5997 Align, AlwaysInline, 5998 DstSV, DstSVOff + Offset, 5999 SrcSV, SrcSVOff + Offset)); 6000 } 6001 6002 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6003 &Results[0], Results.size()); 6004} 6005 6006SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6007 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6008 DebugLoc dl = Op.getDebugLoc(); 6009 6010 if (!Subtarget->is64Bit()) { 6011 // vastart just stores the address of the VarArgsFrameIndex slot into the 6012 // memory location argument. 6013 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6014 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 6015 } 6016 6017 // __va_list_tag: 6018 // gp_offset (0 - 6 * 8) 6019 // fp_offset (48 - 48 + 8 * 16) 6020 // overflow_arg_area (point to parameters coming in memory). 6021 // reg_save_area 6022 SmallVector<SDValue, 8> MemOps; 6023 SDValue FIN = Op.getOperand(1); 6024 // Store gp_offset 6025 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6026 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6027 FIN, SV, 0); 6028 MemOps.push_back(Store); 6029 6030 // Store fp_offset 6031 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6032 FIN, DAG.getIntPtrConstant(4)); 6033 Store = DAG.getStore(Op.getOperand(0), dl, 6034 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6035 FIN, SV, 0); 6036 MemOps.push_back(Store); 6037 6038 // Store ptr to overflow_arg_area 6039 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6040 FIN, DAG.getIntPtrConstant(4)); 6041 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6042 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0); 6043 MemOps.push_back(Store); 6044 6045 // Store ptr to reg_save_area. 6046 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6047 FIN, DAG.getIntPtrConstant(8)); 6048 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6049 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0); 6050 MemOps.push_back(Store); 6051 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6052 &MemOps[0], MemOps.size()); 6053} 6054 6055SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6056 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6057 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6058 SDValue Chain = Op.getOperand(0); 6059 SDValue SrcPtr = Op.getOperand(1); 6060 SDValue SrcSV = Op.getOperand(2); 6061 6062 assert(0 && "VAArgInst is not yet implemented for x86-64!"); 6063 abort(); 6064 return SDValue(); 6065} 6066 6067SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6068 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6069 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6070 SDValue Chain = Op.getOperand(0); 6071 SDValue DstPtr = Op.getOperand(1); 6072 SDValue SrcPtr = Op.getOperand(2); 6073 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6074 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6075 DebugLoc dl = Op.getDebugLoc(); 6076 6077 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6078 DAG.getIntPtrConstant(24), 8, false, 6079 DstSV, 0, SrcSV, 0); 6080} 6081 6082SDValue 6083X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6084 DebugLoc dl = Op.getDebugLoc(); 6085 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6086 switch (IntNo) { 6087 default: return SDValue(); // Don't custom lower most intrinsics. 6088 // Comparison intrinsics. 6089 case Intrinsic::x86_sse_comieq_ss: 6090 case Intrinsic::x86_sse_comilt_ss: 6091 case Intrinsic::x86_sse_comile_ss: 6092 case Intrinsic::x86_sse_comigt_ss: 6093 case Intrinsic::x86_sse_comige_ss: 6094 case Intrinsic::x86_sse_comineq_ss: 6095 case Intrinsic::x86_sse_ucomieq_ss: 6096 case Intrinsic::x86_sse_ucomilt_ss: 6097 case Intrinsic::x86_sse_ucomile_ss: 6098 case Intrinsic::x86_sse_ucomigt_ss: 6099 case Intrinsic::x86_sse_ucomige_ss: 6100 case Intrinsic::x86_sse_ucomineq_ss: 6101 case Intrinsic::x86_sse2_comieq_sd: 6102 case Intrinsic::x86_sse2_comilt_sd: 6103 case Intrinsic::x86_sse2_comile_sd: 6104 case Intrinsic::x86_sse2_comigt_sd: 6105 case Intrinsic::x86_sse2_comige_sd: 6106 case Intrinsic::x86_sse2_comineq_sd: 6107 case Intrinsic::x86_sse2_ucomieq_sd: 6108 case Intrinsic::x86_sse2_ucomilt_sd: 6109 case Intrinsic::x86_sse2_ucomile_sd: 6110 case Intrinsic::x86_sse2_ucomigt_sd: 6111 case Intrinsic::x86_sse2_ucomige_sd: 6112 case Intrinsic::x86_sse2_ucomineq_sd: { 6113 unsigned Opc = 0; 6114 ISD::CondCode CC = ISD::SETCC_INVALID; 6115 switch (IntNo) { 6116 default: break; 6117 case Intrinsic::x86_sse_comieq_ss: 6118 case Intrinsic::x86_sse2_comieq_sd: 6119 Opc = X86ISD::COMI; 6120 CC = ISD::SETEQ; 6121 break; 6122 case Intrinsic::x86_sse_comilt_ss: 6123 case Intrinsic::x86_sse2_comilt_sd: 6124 Opc = X86ISD::COMI; 6125 CC = ISD::SETLT; 6126 break; 6127 case Intrinsic::x86_sse_comile_ss: 6128 case Intrinsic::x86_sse2_comile_sd: 6129 Opc = X86ISD::COMI; 6130 CC = ISD::SETLE; 6131 break; 6132 case Intrinsic::x86_sse_comigt_ss: 6133 case Intrinsic::x86_sse2_comigt_sd: 6134 Opc = X86ISD::COMI; 6135 CC = ISD::SETGT; 6136 break; 6137 case Intrinsic::x86_sse_comige_ss: 6138 case Intrinsic::x86_sse2_comige_sd: 6139 Opc = X86ISD::COMI; 6140 CC = ISD::SETGE; 6141 break; 6142 case Intrinsic::x86_sse_comineq_ss: 6143 case Intrinsic::x86_sse2_comineq_sd: 6144 Opc = X86ISD::COMI; 6145 CC = ISD::SETNE; 6146 break; 6147 case Intrinsic::x86_sse_ucomieq_ss: 6148 case Intrinsic::x86_sse2_ucomieq_sd: 6149 Opc = X86ISD::UCOMI; 6150 CC = ISD::SETEQ; 6151 break; 6152 case Intrinsic::x86_sse_ucomilt_ss: 6153 case Intrinsic::x86_sse2_ucomilt_sd: 6154 Opc = X86ISD::UCOMI; 6155 CC = ISD::SETLT; 6156 break; 6157 case Intrinsic::x86_sse_ucomile_ss: 6158 case Intrinsic::x86_sse2_ucomile_sd: 6159 Opc = X86ISD::UCOMI; 6160 CC = ISD::SETLE; 6161 break; 6162 case Intrinsic::x86_sse_ucomigt_ss: 6163 case Intrinsic::x86_sse2_ucomigt_sd: 6164 Opc = X86ISD::UCOMI; 6165 CC = ISD::SETGT; 6166 break; 6167 case Intrinsic::x86_sse_ucomige_ss: 6168 case Intrinsic::x86_sse2_ucomige_sd: 6169 Opc = X86ISD::UCOMI; 6170 CC = ISD::SETGE; 6171 break; 6172 case Intrinsic::x86_sse_ucomineq_ss: 6173 case Intrinsic::x86_sse2_ucomineq_sd: 6174 Opc = X86ISD::UCOMI; 6175 CC = ISD::SETNE; 6176 break; 6177 } 6178 6179 SDValue LHS = Op.getOperand(1); 6180 SDValue RHS = Op.getOperand(2); 6181 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6182 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6183 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6184 DAG.getConstant(X86CC, MVT::i8), Cond); 6185 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6186 } 6187 6188 // Fix vector shift instructions where the last operand is a non-immediate 6189 // i32 value. 6190 case Intrinsic::x86_sse2_pslli_w: 6191 case Intrinsic::x86_sse2_pslli_d: 6192 case Intrinsic::x86_sse2_pslli_q: 6193 case Intrinsic::x86_sse2_psrli_w: 6194 case Intrinsic::x86_sse2_psrli_d: 6195 case Intrinsic::x86_sse2_psrli_q: 6196 case Intrinsic::x86_sse2_psrai_w: 6197 case Intrinsic::x86_sse2_psrai_d: 6198 case Intrinsic::x86_mmx_pslli_w: 6199 case Intrinsic::x86_mmx_pslli_d: 6200 case Intrinsic::x86_mmx_pslli_q: 6201 case Intrinsic::x86_mmx_psrli_w: 6202 case Intrinsic::x86_mmx_psrli_d: 6203 case Intrinsic::x86_mmx_psrli_q: 6204 case Intrinsic::x86_mmx_psrai_w: 6205 case Intrinsic::x86_mmx_psrai_d: { 6206 SDValue ShAmt = Op.getOperand(2); 6207 if (isa<ConstantSDNode>(ShAmt)) 6208 return SDValue(); 6209 6210 unsigned NewIntNo = 0; 6211 MVT ShAmtVT = MVT::v4i32; 6212 switch (IntNo) { 6213 case Intrinsic::x86_sse2_pslli_w: 6214 NewIntNo = Intrinsic::x86_sse2_psll_w; 6215 break; 6216 case Intrinsic::x86_sse2_pslli_d: 6217 NewIntNo = Intrinsic::x86_sse2_psll_d; 6218 break; 6219 case Intrinsic::x86_sse2_pslli_q: 6220 NewIntNo = Intrinsic::x86_sse2_psll_q; 6221 break; 6222 case Intrinsic::x86_sse2_psrli_w: 6223 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6224 break; 6225 case Intrinsic::x86_sse2_psrli_d: 6226 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6227 break; 6228 case Intrinsic::x86_sse2_psrli_q: 6229 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6230 break; 6231 case Intrinsic::x86_sse2_psrai_w: 6232 NewIntNo = Intrinsic::x86_sse2_psra_w; 6233 break; 6234 case Intrinsic::x86_sse2_psrai_d: 6235 NewIntNo = Intrinsic::x86_sse2_psra_d; 6236 break; 6237 default: { 6238 ShAmtVT = MVT::v2i32; 6239 switch (IntNo) { 6240 case Intrinsic::x86_mmx_pslli_w: 6241 NewIntNo = Intrinsic::x86_mmx_psll_w; 6242 break; 6243 case Intrinsic::x86_mmx_pslli_d: 6244 NewIntNo = Intrinsic::x86_mmx_psll_d; 6245 break; 6246 case Intrinsic::x86_mmx_pslli_q: 6247 NewIntNo = Intrinsic::x86_mmx_psll_q; 6248 break; 6249 case Intrinsic::x86_mmx_psrli_w: 6250 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6251 break; 6252 case Intrinsic::x86_mmx_psrli_d: 6253 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6254 break; 6255 case Intrinsic::x86_mmx_psrli_q: 6256 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6257 break; 6258 case Intrinsic::x86_mmx_psrai_w: 6259 NewIntNo = Intrinsic::x86_mmx_psra_w; 6260 break; 6261 case Intrinsic::x86_mmx_psrai_d: 6262 NewIntNo = Intrinsic::x86_mmx_psra_d; 6263 break; 6264 default: abort(); // Can't reach here. 6265 } 6266 break; 6267 } 6268 } 6269 MVT VT = Op.getValueType(); 6270 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, 6271 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt)); 6272 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6273 DAG.getConstant(NewIntNo, MVT::i32), 6274 Op.getOperand(1), ShAmt); 6275 } 6276 } 6277} 6278 6279SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6280 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6281 DebugLoc dl = Op.getDebugLoc(); 6282 6283 if (Depth > 0) { 6284 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6285 SDValue Offset = 6286 DAG.getConstant(TD->getPointerSize(), 6287 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 6288 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6289 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6290 FrameAddr, Offset), 6291 NULL, 0); 6292 } 6293 6294 // Just load the return address. 6295 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 6296 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6297 RetAddrFI, NULL, 0); 6298} 6299 6300SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6301 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6302 MFI->setFrameAddressIsTaken(true); 6303 MVT VT = Op.getValueType(); 6304 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 6305 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6306 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6307 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 6308 while (Depth--) 6309 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 6310 return FrameAddr; 6311} 6312 6313SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6314 SelectionDAG &DAG) { 6315 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6316} 6317 6318SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6319{ 6320 MachineFunction &MF = DAG.getMachineFunction(); 6321 SDValue Chain = Op.getOperand(0); 6322 SDValue Offset = Op.getOperand(1); 6323 SDValue Handler = Op.getOperand(2); 6324 DebugLoc dl = Op.getDebugLoc(); 6325 6326 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6327 getPointerTy()); 6328 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6329 6330 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 6331 DAG.getIntPtrConstant(-TD->getPointerSize())); 6332 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 6333 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0); 6334 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 6335 MF.getRegInfo().addLiveOut(StoreAddrReg); 6336 6337 return DAG.getNode(X86ISD::EH_RETURN, dl, 6338 MVT::Other, 6339 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 6340} 6341 6342SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 6343 SelectionDAG &DAG) { 6344 SDValue Root = Op.getOperand(0); 6345 SDValue Trmp = Op.getOperand(1); // trampoline 6346 SDValue FPtr = Op.getOperand(2); // nested function 6347 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 6348 DebugLoc dl = Op.getDebugLoc(); 6349 6350 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6351 6352 const X86InstrInfo *TII = 6353 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 6354 6355 if (Subtarget->is64Bit()) { 6356 SDValue OutChains[6]; 6357 6358 // Large code-model. 6359 6360 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 6361 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 6362 6363 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 6364 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 6365 6366 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 6367 6368 // Load the pointer to the nested function into R11. 6369 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 6370 SDValue Addr = Trmp; 6371 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6372 Addr, TrmpAddr, 0); 6373 6374 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6375 DAG.getConstant(2, MVT::i64)); 6376 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2); 6377 6378 // Load the 'nest' parameter value into R10. 6379 // R10 is specified in X86CallingConv.td 6380 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 6381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6382 DAG.getConstant(10, MVT::i64)); 6383 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6384 Addr, TrmpAddr, 10); 6385 6386 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6387 DAG.getConstant(12, MVT::i64)); 6388 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2); 6389 6390 // Jump to the nested function. 6391 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 6392 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6393 DAG.getConstant(20, MVT::i64)); 6394 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6395 Addr, TrmpAddr, 20); 6396 6397 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 6398 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6399 DAG.getConstant(22, MVT::i64)); 6400 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 6401 TrmpAddr, 22); 6402 6403 SDValue Ops[] = 6404 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 6405 return DAG.getMergeValues(Ops, 2, dl); 6406 } else { 6407 const Function *Func = 6408 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 6409 unsigned CC = Func->getCallingConv(); 6410 unsigned NestReg; 6411 6412 switch (CC) { 6413 default: 6414 assert(0 && "Unsupported calling convention"); 6415 case CallingConv::C: 6416 case CallingConv::X86_StdCall: { 6417 // Pass 'nest' parameter in ECX. 6418 // Must be kept in sync with X86CallingConv.td 6419 NestReg = X86::ECX; 6420 6421 // Check that ECX wasn't needed by an 'inreg' parameter. 6422 const FunctionType *FTy = Func->getFunctionType(); 6423 const AttrListPtr &Attrs = Func->getAttributes(); 6424 6425 if (!Attrs.isEmpty() && !Func->isVarArg()) { 6426 unsigned InRegCount = 0; 6427 unsigned Idx = 1; 6428 6429 for (FunctionType::param_iterator I = FTy->param_begin(), 6430 E = FTy->param_end(); I != E; ++I, ++Idx) 6431 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 6432 // FIXME: should only count parameters that are lowered to integers. 6433 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 6434 6435 if (InRegCount > 2) { 6436 cerr << "Nest register in use - reduce number of inreg parameters!\n"; 6437 abort(); 6438 } 6439 } 6440 break; 6441 } 6442 case CallingConv::X86_FastCall: 6443 case CallingConv::Fast: 6444 // Pass 'nest' parameter in EAX. 6445 // Must be kept in sync with X86CallingConv.td 6446 NestReg = X86::EAX; 6447 break; 6448 } 6449 6450 SDValue OutChains[4]; 6451 SDValue Addr, Disp; 6452 6453 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6454 DAG.getConstant(10, MVT::i32)); 6455 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 6456 6457 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 6458 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 6459 OutChains[0] = DAG.getStore(Root, dl, 6460 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 6461 Trmp, TrmpAddr, 0); 6462 6463 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6464 DAG.getConstant(1, MVT::i32)); 6465 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1); 6466 6467 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 6468 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6469 DAG.getConstant(5, MVT::i32)); 6470 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 6471 TrmpAddr, 5, false, 1); 6472 6473 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6474 DAG.getConstant(6, MVT::i32)); 6475 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1); 6476 6477 SDValue Ops[] = 6478 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 6479 return DAG.getMergeValues(Ops, 2, dl); 6480 } 6481} 6482 6483SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 6484 /* 6485 The rounding mode is in bits 11:10 of FPSR, and has the following 6486 settings: 6487 00 Round to nearest 6488 01 Round to -inf 6489 10 Round to +inf 6490 11 Round to 0 6491 6492 FLT_ROUNDS, on the other hand, expects the following: 6493 -1 Undefined 6494 0 Round to 0 6495 1 Round to nearest 6496 2 Round to +inf 6497 3 Round to -inf 6498 6499 To perform the conversion, we do: 6500 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 6501 */ 6502 6503 MachineFunction &MF = DAG.getMachineFunction(); 6504 const TargetMachine &TM = MF.getTarget(); 6505 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 6506 unsigned StackAlignment = TFI.getStackAlignment(); 6507 MVT VT = Op.getValueType(); 6508 DebugLoc dl = Op.getDebugLoc(); 6509 6510 // Save FP Control Word to stack slot 6511 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 6512 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6513 6514 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 6515 DAG.getEntryNode(), StackSlot); 6516 6517 // Load FP Control Word from stack slot 6518 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0); 6519 6520 // Transform as necessary 6521 SDValue CWD1 = 6522 DAG.getNode(ISD::SRL, dl, MVT::i16, 6523 DAG.getNode(ISD::AND, dl, MVT::i16, 6524 CWD, DAG.getConstant(0x800, MVT::i16)), 6525 DAG.getConstant(11, MVT::i8)); 6526 SDValue CWD2 = 6527 DAG.getNode(ISD::SRL, dl, MVT::i16, 6528 DAG.getNode(ISD::AND, dl, MVT::i16, 6529 CWD, DAG.getConstant(0x400, MVT::i16)), 6530 DAG.getConstant(9, MVT::i8)); 6531 6532 SDValue RetVal = 6533 DAG.getNode(ISD::AND, dl, MVT::i16, 6534 DAG.getNode(ISD::ADD, dl, MVT::i16, 6535 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 6536 DAG.getConstant(1, MVT::i16)), 6537 DAG.getConstant(3, MVT::i16)); 6538 6539 6540 return DAG.getNode((VT.getSizeInBits() < 16 ? 6541 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 6542} 6543 6544SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 6545 MVT VT = Op.getValueType(); 6546 MVT OpVT = VT; 6547 unsigned NumBits = VT.getSizeInBits(); 6548 DebugLoc dl = Op.getDebugLoc(); 6549 6550 Op = Op.getOperand(0); 6551 if (VT == MVT::i8) { 6552 // Zero extend to i32 since there is not an i8 bsr. 6553 OpVT = MVT::i32; 6554 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6555 } 6556 6557 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 6558 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6559 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 6560 6561 // If src is zero (i.e. bsr sets ZF), returns NumBits. 6562 SmallVector<SDValue, 4> Ops; 6563 Ops.push_back(Op); 6564 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 6565 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6566 Ops.push_back(Op.getValue(1)); 6567 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6568 6569 // Finally xor with NumBits-1. 6570 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 6571 6572 if (VT == MVT::i8) 6573 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6574 return Op; 6575} 6576 6577SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 6578 MVT VT = Op.getValueType(); 6579 MVT OpVT = VT; 6580 unsigned NumBits = VT.getSizeInBits(); 6581 DebugLoc dl = Op.getDebugLoc(); 6582 6583 Op = Op.getOperand(0); 6584 if (VT == MVT::i8) { 6585 OpVT = MVT::i32; 6586 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6587 } 6588 6589 // Issue a bsf (scan bits forward) which also sets EFLAGS. 6590 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6591 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 6592 6593 // If src is zero (i.e. bsf sets ZF), returns NumBits. 6594 SmallVector<SDValue, 4> Ops; 6595 Ops.push_back(Op); 6596 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 6597 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6598 Ops.push_back(Op.getValue(1)); 6599 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6600 6601 if (VT == MVT::i8) 6602 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6603 return Op; 6604} 6605 6606SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 6607 MVT VT = Op.getValueType(); 6608 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 6609 DebugLoc dl = Op.getDebugLoc(); 6610 6611 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 6612 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 6613 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 6614 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 6615 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 6616 // 6617 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 6618 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 6619 // return AloBlo + AloBhi + AhiBlo; 6620 6621 SDValue A = Op.getOperand(0); 6622 SDValue B = Op.getOperand(1); 6623 6624 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6625 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6626 A, DAG.getConstant(32, MVT::i32)); 6627 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6628 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6629 B, DAG.getConstant(32, MVT::i32)); 6630 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6631 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6632 A, B); 6633 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6634 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6635 A, Bhi); 6636 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6637 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6638 Ahi, B); 6639 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6640 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6641 AloBhi, DAG.getConstant(32, MVT::i32)); 6642 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6643 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6644 AhiBlo, DAG.getConstant(32, MVT::i32)); 6645 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 6646 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 6647 return Res; 6648} 6649 6650 6651SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 6652 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 6653 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 6654 // looks for this combo and may remove the "setcc" instruction if the "setcc" 6655 // has only one use. 6656 SDNode *N = Op.getNode(); 6657 SDValue LHS = N->getOperand(0); 6658 SDValue RHS = N->getOperand(1); 6659 unsigned BaseOp = 0; 6660 unsigned Cond = 0; 6661 DebugLoc dl = Op.getDebugLoc(); 6662 6663 switch (Op.getOpcode()) { 6664 default: assert(0 && "Unknown ovf instruction!"); 6665 case ISD::SADDO: 6666 BaseOp = X86ISD::ADD; 6667 Cond = X86::COND_O; 6668 break; 6669 case ISD::UADDO: 6670 BaseOp = X86ISD::ADD; 6671 Cond = X86::COND_B; 6672 break; 6673 case ISD::SSUBO: 6674 BaseOp = X86ISD::SUB; 6675 Cond = X86::COND_O; 6676 break; 6677 case ISD::USUBO: 6678 BaseOp = X86ISD::SUB; 6679 Cond = X86::COND_B; 6680 break; 6681 case ISD::SMULO: 6682 BaseOp = X86ISD::SMUL; 6683 Cond = X86::COND_O; 6684 break; 6685 case ISD::UMULO: 6686 BaseOp = X86ISD::UMUL; 6687 Cond = X86::COND_B; 6688 break; 6689 } 6690 6691 // Also sets EFLAGS. 6692 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 6693 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 6694 6695 SDValue SetCC = 6696 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 6697 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 6698 6699 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 6700 return Sum; 6701} 6702 6703SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 6704 MVT T = Op.getValueType(); 6705 DebugLoc dl = Op.getDebugLoc(); 6706 unsigned Reg = 0; 6707 unsigned size = 0; 6708 switch(T.getSimpleVT()) { 6709 default: 6710 assert(false && "Invalid value type!"); 6711 case MVT::i8: Reg = X86::AL; size = 1; break; 6712 case MVT::i16: Reg = X86::AX; size = 2; break; 6713 case MVT::i32: Reg = X86::EAX; size = 4; break; 6714 case MVT::i64: 6715 assert(Subtarget->is64Bit() && "Node not type legal!"); 6716 Reg = X86::RAX; size = 8; 6717 break; 6718 } 6719 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 6720 Op.getOperand(2), SDValue()); 6721 SDValue Ops[] = { cpIn.getValue(0), 6722 Op.getOperand(1), 6723 Op.getOperand(3), 6724 DAG.getTargetConstant(size, MVT::i8), 6725 cpIn.getValue(1) }; 6726 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6727 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 6728 SDValue cpOut = 6729 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 6730 return cpOut; 6731} 6732 6733SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 6734 SelectionDAG &DAG) { 6735 assert(Subtarget->is64Bit() && "Result not type legalized?"); 6736 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6737 SDValue TheChain = Op.getOperand(0); 6738 DebugLoc dl = Op.getDebugLoc(); 6739 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6740 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 6741 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 6742 rax.getValue(2)); 6743 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 6744 DAG.getConstant(32, MVT::i8)); 6745 SDValue Ops[] = { 6746 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 6747 rdx.getValue(1) 6748 }; 6749 return DAG.getMergeValues(Ops, 2, dl); 6750} 6751 6752SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 6753 SDNode *Node = Op.getNode(); 6754 DebugLoc dl = Node->getDebugLoc(); 6755 MVT T = Node->getValueType(0); 6756 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 6757 DAG.getConstant(0, T), Node->getOperand(2)); 6758 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 6759 cast<AtomicSDNode>(Node)->getMemoryVT(), 6760 Node->getOperand(0), 6761 Node->getOperand(1), negOp, 6762 cast<AtomicSDNode>(Node)->getSrcValue(), 6763 cast<AtomicSDNode>(Node)->getAlignment()); 6764} 6765 6766/// LowerOperation - Provide custom lowering hooks for some operations. 6767/// 6768SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 6769 switch (Op.getOpcode()) { 6770 default: assert(0 && "Should not custom lower this!"); 6771 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 6772 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 6773 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 6774 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 6775 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 6776 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 6777 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 6778 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 6779 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 6780 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 6781 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 6782 case ISD::SHL_PARTS: 6783 case ISD::SRA_PARTS: 6784 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 6785 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 6786 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 6787 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 6788 case ISD::FABS: return LowerFABS(Op, DAG); 6789 case ISD::FNEG: return LowerFNEG(Op, DAG); 6790 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 6791 case ISD::SETCC: return LowerSETCC(Op, DAG); 6792 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 6793 case ISD::SELECT: return LowerSELECT(Op, DAG); 6794 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 6795 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 6796 case ISD::CALL: return LowerCALL(Op, DAG); 6797 case ISD::RET: return LowerRET(Op, DAG); 6798 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 6799 case ISD::VASTART: return LowerVASTART(Op, DAG); 6800 case ISD::VAARG: return LowerVAARG(Op, DAG); 6801 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 6802 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 6803 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 6804 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 6805 case ISD::FRAME_TO_ARGS_OFFSET: 6806 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 6807 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 6808 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 6809 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 6810 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 6811 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 6812 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 6813 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 6814 case ISD::SADDO: 6815 case ISD::UADDO: 6816 case ISD::SSUBO: 6817 case ISD::USUBO: 6818 case ISD::SMULO: 6819 case ISD::UMULO: return LowerXALUO(Op, DAG); 6820 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 6821 } 6822} 6823 6824void X86TargetLowering:: 6825ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 6826 SelectionDAG &DAG, unsigned NewOp) { 6827 MVT T = Node->getValueType(0); 6828 DebugLoc dl = Node->getDebugLoc(); 6829 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 6830 6831 SDValue Chain = Node->getOperand(0); 6832 SDValue In1 = Node->getOperand(1); 6833 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6834 Node->getOperand(2), DAG.getIntPtrConstant(0)); 6835 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6836 Node->getOperand(2), DAG.getIntPtrConstant(1)); 6837 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't 6838 // have a MemOperand. Pass the info through as a normal operand. 6839 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); 6840 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; 6841 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 6842 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5); 6843 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 6844 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6845 Results.push_back(Result.getValue(2)); 6846} 6847 6848/// ReplaceNodeResults - Replace a node with an illegal result type 6849/// with a new node built out of custom code. 6850void X86TargetLowering::ReplaceNodeResults(SDNode *N, 6851 SmallVectorImpl<SDValue>&Results, 6852 SelectionDAG &DAG) { 6853 DebugLoc dl = N->getDebugLoc(); 6854 switch (N->getOpcode()) { 6855 default: 6856 assert(false && "Do not know how to custom type legalize this operation!"); 6857 return; 6858 case ISD::FP_TO_SINT: { 6859 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG); 6860 SDValue FIST = Vals.first, StackSlot = Vals.second; 6861 if (FIST.getNode() != 0) { 6862 MVT VT = N->getValueType(0); 6863 // Return a load from the stack slot. 6864 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0)); 6865 } 6866 return; 6867 } 6868 case ISD::READCYCLECOUNTER: { 6869 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6870 SDValue TheChain = N->getOperand(0); 6871 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6872 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 6873 rd.getValue(1)); 6874 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 6875 eax.getValue(2)); 6876 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 6877 SDValue Ops[] = { eax, edx }; 6878 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 6879 Results.push_back(edx.getValue(1)); 6880 return; 6881 } 6882 case ISD::ATOMIC_CMP_SWAP: { 6883 MVT T = N->getValueType(0); 6884 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 6885 SDValue cpInL, cpInH; 6886 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 6887 DAG.getConstant(0, MVT::i32)); 6888 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 6889 DAG.getConstant(1, MVT::i32)); 6890 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 6891 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 6892 cpInL.getValue(1)); 6893 SDValue swapInL, swapInH; 6894 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 6895 DAG.getConstant(0, MVT::i32)); 6896 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 6897 DAG.getConstant(1, MVT::i32)); 6898 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 6899 cpInH.getValue(1)); 6900 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 6901 swapInL.getValue(1)); 6902 SDValue Ops[] = { swapInH.getValue(0), 6903 N->getOperand(1), 6904 swapInH.getValue(1) }; 6905 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6906 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 6907 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 6908 MVT::i32, Result.getValue(1)); 6909 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 6910 MVT::i32, cpOutL.getValue(2)); 6911 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 6912 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6913 Results.push_back(cpOutH.getValue(1)); 6914 return; 6915 } 6916 case ISD::ATOMIC_LOAD_ADD: 6917 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 6918 return; 6919 case ISD::ATOMIC_LOAD_AND: 6920 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 6921 return; 6922 case ISD::ATOMIC_LOAD_NAND: 6923 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 6924 return; 6925 case ISD::ATOMIC_LOAD_OR: 6926 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 6927 return; 6928 case ISD::ATOMIC_LOAD_SUB: 6929 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 6930 return; 6931 case ISD::ATOMIC_LOAD_XOR: 6932 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 6933 return; 6934 case ISD::ATOMIC_SWAP: 6935 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 6936 return; 6937 } 6938} 6939 6940const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 6941 switch (Opcode) { 6942 default: return NULL; 6943 case X86ISD::BSF: return "X86ISD::BSF"; 6944 case X86ISD::BSR: return "X86ISD::BSR"; 6945 case X86ISD::SHLD: return "X86ISD::SHLD"; 6946 case X86ISD::SHRD: return "X86ISD::SHRD"; 6947 case X86ISD::FAND: return "X86ISD::FAND"; 6948 case X86ISD::FOR: return "X86ISD::FOR"; 6949 case X86ISD::FXOR: return "X86ISD::FXOR"; 6950 case X86ISD::FSRL: return "X86ISD::FSRL"; 6951 case X86ISD::FILD: return "X86ISD::FILD"; 6952 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 6953 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 6954 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 6955 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 6956 case X86ISD::FLD: return "X86ISD::FLD"; 6957 case X86ISD::FST: return "X86ISD::FST"; 6958 case X86ISD::CALL: return "X86ISD::CALL"; 6959 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 6960 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 6961 case X86ISD::BT: return "X86ISD::BT"; 6962 case X86ISD::CMP: return "X86ISD::CMP"; 6963 case X86ISD::COMI: return "X86ISD::COMI"; 6964 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 6965 case X86ISD::SETCC: return "X86ISD::SETCC"; 6966 case X86ISD::CMOV: return "X86ISD::CMOV"; 6967 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 6968 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 6969 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 6970 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 6971 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 6972 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 6973 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 6974 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 6975 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 6976 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 6977 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 6978 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 6979 case X86ISD::FMAX: return "X86ISD::FMAX"; 6980 case X86ISD::FMIN: return "X86ISD::FMIN"; 6981 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 6982 case X86ISD::FRCP: return "X86ISD::FRCP"; 6983 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 6984 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; 6985 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 6986 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 6987 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 6988 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 6989 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 6990 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 6991 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 6992 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 6993 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 6994 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 6995 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 6996 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 6997 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 6998 case X86ISD::VSHL: return "X86ISD::VSHL"; 6999 case X86ISD::VSRL: return "X86ISD::VSRL"; 7000 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7001 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7002 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7003 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7004 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7005 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7006 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7007 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7008 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7009 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7010 case X86ISD::ADD: return "X86ISD::ADD"; 7011 case X86ISD::SUB: return "X86ISD::SUB"; 7012 case X86ISD::SMUL: return "X86ISD::SMUL"; 7013 case X86ISD::UMUL: return "X86ISD::UMUL"; 7014 } 7015} 7016 7017// isLegalAddressingMode - Return true if the addressing mode represented 7018// by AM is legal for this target, for a load/store of the specified type. 7019bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7020 const Type *Ty) const { 7021 // X86 supports extremely general addressing modes. 7022 7023 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7024 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) 7025 return false; 7026 7027 if (AM.BaseGV) { 7028 // We can only fold this if we don't need an extra load. 7029 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) 7030 return false; 7031 // If BaseGV requires a register, we cannot also have a BaseReg. 7032 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) && 7033 AM.HasBaseReg) 7034 return false; 7035 7036 // X86-64 only supports addr of globals in small code model. 7037 if (Subtarget->is64Bit()) { 7038 if (getTargetMachine().getCodeModel() != CodeModel::Small) 7039 return false; 7040 // If lower 4G is not available, then we must use rip-relative addressing. 7041 if (AM.BaseOffs || AM.Scale > 1) 7042 return false; 7043 } 7044 } 7045 7046 switch (AM.Scale) { 7047 case 0: 7048 case 1: 7049 case 2: 7050 case 4: 7051 case 8: 7052 // These scales always work. 7053 break; 7054 case 3: 7055 case 5: 7056 case 9: 7057 // These scales are formed with basereg+scalereg. Only accept if there is 7058 // no basereg yet. 7059 if (AM.HasBaseReg) 7060 return false; 7061 break; 7062 default: // Other stuff never works. 7063 return false; 7064 } 7065 7066 return true; 7067} 7068 7069 7070bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7071 if (!Ty1->isInteger() || !Ty2->isInteger()) 7072 return false; 7073 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7074 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7075 if (NumBits1 <= NumBits2) 7076 return false; 7077 return Subtarget->is64Bit() || NumBits1 < 64; 7078} 7079 7080bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { 7081 if (!VT1.isInteger() || !VT2.isInteger()) 7082 return false; 7083 unsigned NumBits1 = VT1.getSizeInBits(); 7084 unsigned NumBits2 = VT2.getSizeInBits(); 7085 if (NumBits1 <= NumBits2) 7086 return false; 7087 return Subtarget->is64Bit() || NumBits1 < 64; 7088} 7089 7090/// isShuffleMaskLegal - Targets can use this to indicate that they only 7091/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7092/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7093/// are assumed to be legal. 7094bool 7095X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const { 7096 // Only do shuffles on 128-bit vector types for now. 7097 // FIXME: pshufb, blends 7098 if (VT.getSizeInBits() == 64) return false; 7099 return (Mask.getNode()->getNumOperands() <= 4 || 7100 isIdentityMask(Mask.getNode()) || 7101 isIdentityMask(Mask.getNode(), true) || 7102 isSplatMask(Mask.getNode()) || 7103 X86::isPSHUFHWMask(Mask.getNode()) || 7104 X86::isPSHUFLWMask(Mask.getNode()) || 7105 X86::isUNPCKLMask(Mask.getNode()) || 7106 X86::isUNPCKHMask(Mask.getNode()) || 7107 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) || 7108 X86::isUNPCKH_v_undef_Mask(Mask.getNode())); 7109} 7110 7111bool 7112X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 7113 MVT EVT, SelectionDAG &DAG) const { 7114 unsigned NumElts = BVOps.size(); 7115 // Only do shuffles on 128-bit vector types for now. 7116 if (EVT.getSizeInBits() * NumElts == 64) return false; 7117 if (NumElts == 2) return true; 7118 if (NumElts == 4) { 7119 return (isMOVLMask(&BVOps[0], 4) || 7120 isCommutedMOVL(&BVOps[0], 4, true) || 7121 isSHUFPMask(&BVOps[0], 4) || 7122 isCommutedSHUFP(&BVOps[0], 4)); 7123 } 7124 return false; 7125} 7126 7127//===----------------------------------------------------------------------===// 7128// X86 Scheduler Hooks 7129//===----------------------------------------------------------------------===// 7130 7131// private utility function 7132MachineBasicBlock * 7133X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7134 MachineBasicBlock *MBB, 7135 unsigned regOpc, 7136 unsigned immOpc, 7137 unsigned LoadOpc, 7138 unsigned CXchgOpc, 7139 unsigned copyOpc, 7140 unsigned notOpc, 7141 unsigned EAXreg, 7142 TargetRegisterClass *RC, 7143 bool invSrc) const { 7144 // For the atomic bitwise operator, we generate 7145 // thisMBB: 7146 // newMBB: 7147 // ld t1 = [bitinstr.addr] 7148 // op t2 = t1, [bitinstr.val] 7149 // mov EAX = t1 7150 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7151 // bz newMBB 7152 // fallthrough -->nextMBB 7153 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7154 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7155 MachineFunction::iterator MBBIter = MBB; 7156 ++MBBIter; 7157 7158 /// First build the CFG 7159 MachineFunction *F = MBB->getParent(); 7160 MachineBasicBlock *thisMBB = MBB; 7161 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7162 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7163 F->insert(MBBIter, newMBB); 7164 F->insert(MBBIter, nextMBB); 7165 7166 // Move all successors to thisMBB to nextMBB 7167 nextMBB->transferSuccessors(thisMBB); 7168 7169 // Update thisMBB to fall through to newMBB 7170 thisMBB->addSuccessor(newMBB); 7171 7172 // newMBB jumps to itself and fall through to nextMBB 7173 newMBB->addSuccessor(nextMBB); 7174 newMBB->addSuccessor(newMBB); 7175 7176 // Insert instructions into newMBB based on incoming instruction 7177 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands"); 7178 DebugLoc dl = bInstr->getDebugLoc(); 7179 MachineOperand& destOper = bInstr->getOperand(0); 7180 MachineOperand* argOpers[6]; 7181 int numArgs = bInstr->getNumOperands() - 1; 7182 for (int i=0; i < numArgs; ++i) 7183 argOpers[i] = &bInstr->getOperand(i+1); 7184 7185 // x86 address has 4 operands: base, index, scale, and displacement 7186 int lastAddrIndx = 3; // [0,3] 7187 int valArgIndx = 4; 7188 7189 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7190 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7191 for (int i=0; i <= lastAddrIndx; ++i) 7192 (*MIB).addOperand(*argOpers[i]); 7193 7194 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7195 if (invSrc) { 7196 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7197 } 7198 else 7199 tt = t1; 7200 7201 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7202 assert((argOpers[valArgIndx]->isReg() || 7203 argOpers[valArgIndx]->isImm()) && 7204 "invalid operand"); 7205 if (argOpers[valArgIndx]->isReg()) 7206 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7207 else 7208 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7209 MIB.addReg(tt); 7210 (*MIB).addOperand(*argOpers[valArgIndx]); 7211 7212 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7213 MIB.addReg(t1); 7214 7215 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7216 for (int i=0; i <= lastAddrIndx; ++i) 7217 (*MIB).addOperand(*argOpers[i]); 7218 MIB.addReg(t2); 7219 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7220 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7221 7222 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7223 MIB.addReg(EAXreg); 7224 7225 // insert branch 7226 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7227 7228 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7229 return nextMBB; 7230} 7231 7232// private utility function: 64 bit atomics on 32 bit host. 7233MachineBasicBlock * 7234X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 7235 MachineBasicBlock *MBB, 7236 unsigned regOpcL, 7237 unsigned regOpcH, 7238 unsigned immOpcL, 7239 unsigned immOpcH, 7240 bool invSrc) const { 7241 // For the atomic bitwise operator, we generate 7242 // thisMBB (instructions are in pairs, except cmpxchg8b) 7243 // ld t1,t2 = [bitinstr.addr] 7244 // newMBB: 7245 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 7246 // op t5, t6 <- out1, out2, [bitinstr.val] 7247 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 7248 // mov ECX, EBX <- t5, t6 7249 // mov EAX, EDX <- t1, t2 7250 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 7251 // mov t3, t4 <- EAX, EDX 7252 // bz newMBB 7253 // result in out1, out2 7254 // fallthrough -->nextMBB 7255 7256 const TargetRegisterClass *RC = X86::GR32RegisterClass; 7257 const unsigned LoadOpc = X86::MOV32rm; 7258 const unsigned copyOpc = X86::MOV32rr; 7259 const unsigned NotOpc = X86::NOT32r; 7260 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7261 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7262 MachineFunction::iterator MBBIter = MBB; 7263 ++MBBIter; 7264 7265 /// First build the CFG 7266 MachineFunction *F = MBB->getParent(); 7267 MachineBasicBlock *thisMBB = MBB; 7268 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7269 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7270 F->insert(MBBIter, newMBB); 7271 F->insert(MBBIter, nextMBB); 7272 7273 // Move all successors to thisMBB to nextMBB 7274 nextMBB->transferSuccessors(thisMBB); 7275 7276 // Update thisMBB to fall through to newMBB 7277 thisMBB->addSuccessor(newMBB); 7278 7279 // newMBB jumps to itself and fall through to nextMBB 7280 newMBB->addSuccessor(nextMBB); 7281 newMBB->addSuccessor(newMBB); 7282 7283 DebugLoc dl = bInstr->getDebugLoc(); 7284 // Insert instructions into newMBB based on incoming instruction 7285 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 7286 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands"); 7287 MachineOperand& dest1Oper = bInstr->getOperand(0); 7288 MachineOperand& dest2Oper = bInstr->getOperand(1); 7289 MachineOperand* argOpers[6]; 7290 for (int i=0; i < 6; ++i) 7291 argOpers[i] = &bInstr->getOperand(i+2); 7292 7293 // x86 address has 4 operands: base, index, scale, and displacement 7294 int lastAddrIndx = 3; // [0,3] 7295 7296 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7297 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 7298 for (int i=0; i <= lastAddrIndx; ++i) 7299 (*MIB).addOperand(*argOpers[i]); 7300 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7301 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 7302 // add 4 to displacement. 7303 for (int i=0; i <= lastAddrIndx-1; ++i) 7304 (*MIB).addOperand(*argOpers[i]); 7305 MachineOperand newOp3 = *(argOpers[3]); 7306 if (newOp3.isImm()) 7307 newOp3.setImm(newOp3.getImm()+4); 7308 else 7309 newOp3.setOffset(newOp3.getOffset()+4); 7310 (*MIB).addOperand(newOp3); 7311 7312 // t3/4 are defined later, at the bottom of the loop 7313 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 7314 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 7315 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 7316 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 7317 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 7318 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 7319 7320 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); 7321 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); 7322 if (invSrc) { 7323 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1); 7324 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2); 7325 } else { 7326 tt1 = t1; 7327 tt2 = t2; 7328 } 7329 7330 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) && 7331 "invalid operand"); 7332 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 7333 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 7334 if (argOpers[4]->isReg()) 7335 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 7336 else 7337 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 7338 if (regOpcL != X86::MOV32rr) 7339 MIB.addReg(tt1); 7340 (*MIB).addOperand(*argOpers[4]); 7341 assert(argOpers[5]->isReg() == argOpers[4]->isReg()); 7342 assert(argOpers[5]->isImm() == argOpers[4]->isImm()); 7343 if (argOpers[5]->isReg()) 7344 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 7345 else 7346 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 7347 if (regOpcH != X86::MOV32rr) 7348 MIB.addReg(tt2); 7349 (*MIB).addOperand(*argOpers[5]); 7350 7351 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 7352 MIB.addReg(t1); 7353 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 7354 MIB.addReg(t2); 7355 7356 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 7357 MIB.addReg(t5); 7358 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 7359 MIB.addReg(t6); 7360 7361 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 7362 for (int i=0; i <= lastAddrIndx; ++i) 7363 (*MIB).addOperand(*argOpers[i]); 7364 7365 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7366 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7367 7368 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 7369 MIB.addReg(X86::EAX); 7370 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 7371 MIB.addReg(X86::EDX); 7372 7373 // insert branch 7374 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7375 7376 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7377 return nextMBB; 7378} 7379 7380// private utility function 7381MachineBasicBlock * 7382X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 7383 MachineBasicBlock *MBB, 7384 unsigned cmovOpc) const { 7385 // For the atomic min/max operator, we generate 7386 // thisMBB: 7387 // newMBB: 7388 // ld t1 = [min/max.addr] 7389 // mov t2 = [min/max.val] 7390 // cmp t1, t2 7391 // cmov[cond] t2 = t1 7392 // mov EAX = t1 7393 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7394 // bz newMBB 7395 // fallthrough -->nextMBB 7396 // 7397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7398 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7399 MachineFunction::iterator MBBIter = MBB; 7400 ++MBBIter; 7401 7402 /// First build the CFG 7403 MachineFunction *F = MBB->getParent(); 7404 MachineBasicBlock *thisMBB = MBB; 7405 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7406 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7407 F->insert(MBBIter, newMBB); 7408 F->insert(MBBIter, nextMBB); 7409 7410 // Move all successors to thisMBB to nextMBB 7411 nextMBB->transferSuccessors(thisMBB); 7412 7413 // Update thisMBB to fall through to newMBB 7414 thisMBB->addSuccessor(newMBB); 7415 7416 // newMBB jumps to newMBB and fall through to nextMBB 7417 newMBB->addSuccessor(nextMBB); 7418 newMBB->addSuccessor(newMBB); 7419 7420 DebugLoc dl = mInstr->getDebugLoc(); 7421 // Insert instructions into newMBB based on incoming instruction 7422 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands"); 7423 MachineOperand& destOper = mInstr->getOperand(0); 7424 MachineOperand* argOpers[6]; 7425 int numArgs = mInstr->getNumOperands() - 1; 7426 for (int i=0; i < numArgs; ++i) 7427 argOpers[i] = &mInstr->getOperand(i+1); 7428 7429 // x86 address has 4 operands: base, index, scale, and displacement 7430 int lastAddrIndx = 3; // [0,3] 7431 int valArgIndx = 4; 7432 7433 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7434 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 7435 for (int i=0; i <= lastAddrIndx; ++i) 7436 (*MIB).addOperand(*argOpers[i]); 7437 7438 // We only support register and immediate values 7439 assert((argOpers[valArgIndx]->isReg() || 7440 argOpers[valArgIndx]->isImm()) && 7441 "invalid operand"); 7442 7443 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7444 if (argOpers[valArgIndx]->isReg()) 7445 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7446 else 7447 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7448 (*MIB).addOperand(*argOpers[valArgIndx]); 7449 7450 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 7451 MIB.addReg(t1); 7452 7453 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 7454 MIB.addReg(t1); 7455 MIB.addReg(t2); 7456 7457 // Generate movc 7458 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7459 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 7460 MIB.addReg(t2); 7461 MIB.addReg(t1); 7462 7463 // Cmp and exchange if none has modified the memory location 7464 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 7465 for (int i=0; i <= lastAddrIndx; ++i) 7466 (*MIB).addOperand(*argOpers[i]); 7467 MIB.addReg(t3); 7468 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7469 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 7470 7471 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 7472 MIB.addReg(X86::EAX); 7473 7474 // insert branch 7475 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7476 7477 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 7478 return nextMBB; 7479} 7480 7481 7482MachineBasicBlock * 7483X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 7484 MachineBasicBlock *BB) const { 7485 DebugLoc dl = MI->getDebugLoc(); 7486 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7487 switch (MI->getOpcode()) { 7488 default: assert(false && "Unexpected instr type to insert"); 7489 case X86::CMOV_V1I64: 7490 case X86::CMOV_FR32: 7491 case X86::CMOV_FR64: 7492 case X86::CMOV_V4F32: 7493 case X86::CMOV_V2F64: 7494 case X86::CMOV_V2I64: { 7495 // To "insert" a SELECT_CC instruction, we actually have to insert the 7496 // diamond control-flow pattern. The incoming instruction knows the 7497 // destination vreg to set, the condition code register to branch on, the 7498 // true/false values to select between, and a branch opcode to use. 7499 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 7500 MachineFunction::iterator It = BB; 7501 ++It; 7502 7503 // thisMBB: 7504 // ... 7505 // TrueVal = ... 7506 // cmpTY ccX, r1, r2 7507 // bCC copy1MBB 7508 // fallthrough --> copy0MBB 7509 MachineBasicBlock *thisMBB = BB; 7510 MachineFunction *F = BB->getParent(); 7511 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 7512 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 7513 unsigned Opc = 7514 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 7515 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 7516 F->insert(It, copy0MBB); 7517 F->insert(It, sinkMBB); 7518 // Update machine-CFG edges by transferring all successors of the current 7519 // block to the new block which will contain the Phi node for the select. 7520 sinkMBB->transferSuccessors(BB); 7521 7522 // Add the true and fallthrough blocks as its successors. 7523 BB->addSuccessor(copy0MBB); 7524 BB->addSuccessor(sinkMBB); 7525 7526 // copy0MBB: 7527 // %FalseValue = ... 7528 // # fallthrough to sinkMBB 7529 BB = copy0MBB; 7530 7531 // Update machine-CFG edges 7532 BB->addSuccessor(sinkMBB); 7533 7534 // sinkMBB: 7535 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 7536 // ... 7537 BB = sinkMBB; 7538 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg()) 7539 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 7540 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 7541 7542 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7543 return BB; 7544 } 7545 7546 case X86::FP32_TO_INT16_IN_MEM: 7547 case X86::FP32_TO_INT32_IN_MEM: 7548 case X86::FP32_TO_INT64_IN_MEM: 7549 case X86::FP64_TO_INT16_IN_MEM: 7550 case X86::FP64_TO_INT32_IN_MEM: 7551 case X86::FP64_TO_INT64_IN_MEM: 7552 case X86::FP80_TO_INT16_IN_MEM: 7553 case X86::FP80_TO_INT32_IN_MEM: 7554 case X86::FP80_TO_INT64_IN_MEM: { 7555 // Change the floating point control register to use "round towards zero" 7556 // mode when truncating to an integer value. 7557 MachineFunction *F = BB->getParent(); 7558 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 7559 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx); 7560 7561 // Load the old value of the high byte of the control word... 7562 unsigned OldCW = 7563 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 7564 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW), 7565 CWFrameIdx); 7566 7567 // Set the high part to be round to zero... 7568 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx) 7569 .addImm(0xC7F); 7570 7571 // Reload the modified control word now... 7572 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); 7573 7574 // Restore the memory image of control word to original value 7575 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx) 7576 .addReg(OldCW); 7577 7578 // Get the X86 opcode to use. 7579 unsigned Opc; 7580 switch (MI->getOpcode()) { 7581 default: assert(0 && "illegal opcode!"); 7582 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 7583 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 7584 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 7585 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 7586 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 7587 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 7588 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 7589 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 7590 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 7591 } 7592 7593 X86AddressMode AM; 7594 MachineOperand &Op = MI->getOperand(0); 7595 if (Op.isReg()) { 7596 AM.BaseType = X86AddressMode::RegBase; 7597 AM.Base.Reg = Op.getReg(); 7598 } else { 7599 AM.BaseType = X86AddressMode::FrameIndexBase; 7600 AM.Base.FrameIndex = Op.getIndex(); 7601 } 7602 Op = MI->getOperand(1); 7603 if (Op.isImm()) 7604 AM.Scale = Op.getImm(); 7605 Op = MI->getOperand(2); 7606 if (Op.isImm()) 7607 AM.IndexReg = Op.getImm(); 7608 Op = MI->getOperand(3); 7609 if (Op.isGlobal()) { 7610 AM.GV = Op.getGlobal(); 7611 } else { 7612 AM.Disp = Op.getImm(); 7613 } 7614 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM) 7615 .addReg(MI->getOperand(4).getReg()); 7616 7617 // Reload the original control word now. 7618 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); 7619 7620 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7621 return BB; 7622 } 7623 case X86::ATOMAND32: 7624 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7625 X86::AND32ri, X86::MOV32rm, 7626 X86::LCMPXCHG32, X86::MOV32rr, 7627 X86::NOT32r, X86::EAX, 7628 X86::GR32RegisterClass); 7629 case X86::ATOMOR32: 7630 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 7631 X86::OR32ri, X86::MOV32rm, 7632 X86::LCMPXCHG32, X86::MOV32rr, 7633 X86::NOT32r, X86::EAX, 7634 X86::GR32RegisterClass); 7635 case X86::ATOMXOR32: 7636 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 7637 X86::XOR32ri, X86::MOV32rm, 7638 X86::LCMPXCHG32, X86::MOV32rr, 7639 X86::NOT32r, X86::EAX, 7640 X86::GR32RegisterClass); 7641 case X86::ATOMNAND32: 7642 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7643 X86::AND32ri, X86::MOV32rm, 7644 X86::LCMPXCHG32, X86::MOV32rr, 7645 X86::NOT32r, X86::EAX, 7646 X86::GR32RegisterClass, true); 7647 case X86::ATOMMIN32: 7648 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 7649 case X86::ATOMMAX32: 7650 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 7651 case X86::ATOMUMIN32: 7652 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 7653 case X86::ATOMUMAX32: 7654 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 7655 7656 case X86::ATOMAND16: 7657 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7658 X86::AND16ri, X86::MOV16rm, 7659 X86::LCMPXCHG16, X86::MOV16rr, 7660 X86::NOT16r, X86::AX, 7661 X86::GR16RegisterClass); 7662 case X86::ATOMOR16: 7663 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 7664 X86::OR16ri, X86::MOV16rm, 7665 X86::LCMPXCHG16, X86::MOV16rr, 7666 X86::NOT16r, X86::AX, 7667 X86::GR16RegisterClass); 7668 case X86::ATOMXOR16: 7669 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 7670 X86::XOR16ri, X86::MOV16rm, 7671 X86::LCMPXCHG16, X86::MOV16rr, 7672 X86::NOT16r, X86::AX, 7673 X86::GR16RegisterClass); 7674 case X86::ATOMNAND16: 7675 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7676 X86::AND16ri, X86::MOV16rm, 7677 X86::LCMPXCHG16, X86::MOV16rr, 7678 X86::NOT16r, X86::AX, 7679 X86::GR16RegisterClass, true); 7680 case X86::ATOMMIN16: 7681 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 7682 case X86::ATOMMAX16: 7683 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 7684 case X86::ATOMUMIN16: 7685 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 7686 case X86::ATOMUMAX16: 7687 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 7688 7689 case X86::ATOMAND8: 7690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7691 X86::AND8ri, X86::MOV8rm, 7692 X86::LCMPXCHG8, X86::MOV8rr, 7693 X86::NOT8r, X86::AL, 7694 X86::GR8RegisterClass); 7695 case X86::ATOMOR8: 7696 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 7697 X86::OR8ri, X86::MOV8rm, 7698 X86::LCMPXCHG8, X86::MOV8rr, 7699 X86::NOT8r, X86::AL, 7700 X86::GR8RegisterClass); 7701 case X86::ATOMXOR8: 7702 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 7703 X86::XOR8ri, X86::MOV8rm, 7704 X86::LCMPXCHG8, X86::MOV8rr, 7705 X86::NOT8r, X86::AL, 7706 X86::GR8RegisterClass); 7707 case X86::ATOMNAND8: 7708 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7709 X86::AND8ri, X86::MOV8rm, 7710 X86::LCMPXCHG8, X86::MOV8rr, 7711 X86::NOT8r, X86::AL, 7712 X86::GR8RegisterClass, true); 7713 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 7714 // This group is for 64-bit host. 7715 case X86::ATOMAND64: 7716 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7717 X86::AND64ri32, X86::MOV64rm, 7718 X86::LCMPXCHG64, X86::MOV64rr, 7719 X86::NOT64r, X86::RAX, 7720 X86::GR64RegisterClass); 7721 case X86::ATOMOR64: 7722 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 7723 X86::OR64ri32, X86::MOV64rm, 7724 X86::LCMPXCHG64, X86::MOV64rr, 7725 X86::NOT64r, X86::RAX, 7726 X86::GR64RegisterClass); 7727 case X86::ATOMXOR64: 7728 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 7729 X86::XOR64ri32, X86::MOV64rm, 7730 X86::LCMPXCHG64, X86::MOV64rr, 7731 X86::NOT64r, X86::RAX, 7732 X86::GR64RegisterClass); 7733 case X86::ATOMNAND64: 7734 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7735 X86::AND64ri32, X86::MOV64rm, 7736 X86::LCMPXCHG64, X86::MOV64rr, 7737 X86::NOT64r, X86::RAX, 7738 X86::GR64RegisterClass, true); 7739 case X86::ATOMMIN64: 7740 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 7741 case X86::ATOMMAX64: 7742 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 7743 case X86::ATOMUMIN64: 7744 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 7745 case X86::ATOMUMAX64: 7746 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 7747 7748 // This group does 64-bit operations on a 32-bit host. 7749 case X86::ATOMAND6432: 7750 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7751 X86::AND32rr, X86::AND32rr, 7752 X86::AND32ri, X86::AND32ri, 7753 false); 7754 case X86::ATOMOR6432: 7755 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7756 X86::OR32rr, X86::OR32rr, 7757 X86::OR32ri, X86::OR32ri, 7758 false); 7759 case X86::ATOMXOR6432: 7760 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7761 X86::XOR32rr, X86::XOR32rr, 7762 X86::XOR32ri, X86::XOR32ri, 7763 false); 7764 case X86::ATOMNAND6432: 7765 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7766 X86::AND32rr, X86::AND32rr, 7767 X86::AND32ri, X86::AND32ri, 7768 true); 7769 case X86::ATOMADD6432: 7770 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7771 X86::ADD32rr, X86::ADC32rr, 7772 X86::ADD32ri, X86::ADC32ri, 7773 false); 7774 case X86::ATOMSUB6432: 7775 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7776 X86::SUB32rr, X86::SBB32rr, 7777 X86::SUB32ri, X86::SBB32ri, 7778 false); 7779 case X86::ATOMSWAP6432: 7780 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7781 X86::MOV32rr, X86::MOV32rr, 7782 X86::MOV32ri, X86::MOV32ri, 7783 false); 7784 } 7785} 7786 7787//===----------------------------------------------------------------------===// 7788// X86 Optimization Hooks 7789//===----------------------------------------------------------------------===// 7790 7791void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7792 const APInt &Mask, 7793 APInt &KnownZero, 7794 APInt &KnownOne, 7795 const SelectionDAG &DAG, 7796 unsigned Depth) const { 7797 unsigned Opc = Op.getOpcode(); 7798 assert((Opc >= ISD::BUILTIN_OP_END || 7799 Opc == ISD::INTRINSIC_WO_CHAIN || 7800 Opc == ISD::INTRINSIC_W_CHAIN || 7801 Opc == ISD::INTRINSIC_VOID) && 7802 "Should use MaskedValueIsZero if you don't know whether Op" 7803 " is a target node!"); 7804 7805 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 7806 switch (Opc) { 7807 default: break; 7808 case X86ISD::ADD: 7809 case X86ISD::SUB: 7810 case X86ISD::SMUL: 7811 case X86ISD::UMUL: 7812 // These nodes' second result is a boolean. 7813 if (Op.getResNo() == 0) 7814 break; 7815 // Fallthrough 7816 case X86ISD::SETCC: 7817 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 7818 Mask.getBitWidth() - 1); 7819 break; 7820 } 7821} 7822 7823/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 7824/// node is a GlobalAddress + offset. 7825bool X86TargetLowering::isGAPlusOffset(SDNode *N, 7826 GlobalValue* &GA, int64_t &Offset) const{ 7827 if (N->getOpcode() == X86ISD::Wrapper) { 7828 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 7829 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 7830 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 7831 return true; 7832 } 7833 } 7834 return TargetLowering::isGAPlusOffset(N, GA, Offset); 7835} 7836 7837static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 7838 const TargetLowering &TLI) { 7839 GlobalValue *GV; 7840 int64_t Offset = 0; 7841 if (TLI.isGAPlusOffset(Base, GV, Offset)) 7842 return (GV->getAlignment() >= N && (Offset % N) == 0); 7843 // DAG combine handles the stack object case. 7844 return false; 7845} 7846 7847static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask, 7848 unsigned NumElems, MVT EVT, 7849 SDNode *&Base, 7850 SelectionDAG &DAG, MachineFrameInfo *MFI, 7851 const TargetLowering &TLI) { 7852 Base = NULL; 7853 for (unsigned i = 0; i < NumElems; ++i) { 7854 SDValue Idx = PermMask.getOperand(i); 7855 if (Idx.getOpcode() == ISD::UNDEF) { 7856 if (!Base) 7857 return false; 7858 continue; 7859 } 7860 7861 SDValue Elt = DAG.getShuffleScalarElt(N, i); 7862 if (!Elt.getNode() || 7863 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 7864 return false; 7865 if (!Base) { 7866 Base = Elt.getNode(); 7867 if (Base->getOpcode() == ISD::UNDEF) 7868 return false; 7869 continue; 7870 } 7871 if (Elt.getOpcode() == ISD::UNDEF) 7872 continue; 7873 7874 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base, 7875 EVT.getSizeInBits()/8, i, MFI)) 7876 return false; 7877 } 7878 return true; 7879} 7880 7881/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 7882/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 7883/// if the load addresses are consecutive, non-overlapping, and in the right 7884/// order. 7885static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 7886 const TargetLowering &TLI) { 7887 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7888 DebugLoc dl = N->getDebugLoc(); 7889 MVT VT = N->getValueType(0); 7890 MVT EVT = VT.getVectorElementType(); 7891 SDValue PermMask = N->getOperand(2); 7892 unsigned NumElems = PermMask.getNumOperands(); 7893 SDNode *Base = NULL; 7894 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base, 7895 DAG, MFI, TLI)) 7896 return SDValue(); 7897 7898 LoadSDNode *LD = cast<LoadSDNode>(Base); 7899 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI)) 7900 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 7901 LD->getSrcValue(), LD->getSrcValueOffset(), 7902 LD->isVolatile()); 7903 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 7904 LD->getSrcValue(), LD->getSrcValueOffset(), 7905 LD->isVolatile(), LD->getAlignment()); 7906} 7907 7908/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. 7909static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, 7910 TargetLowering::DAGCombinerInfo &DCI, 7911 const X86Subtarget *Subtarget, 7912 const TargetLowering &TLI) { 7913 unsigned NumOps = N->getNumOperands(); 7914 DebugLoc dl = N->getDebugLoc(); 7915 7916 // Ignore single operand BUILD_VECTOR. 7917 if (NumOps == 1) 7918 return SDValue(); 7919 7920 MVT VT = N->getValueType(0); 7921 MVT EVT = VT.getVectorElementType(); 7922 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit()) 7923 // We are looking for load i64 and zero extend. We want to transform 7924 // it before legalizer has a chance to expand it. Also look for i64 7925 // BUILD_PAIR bit casted to f64. 7926 return SDValue(); 7927 // This must be an insertion into a zero vector. 7928 SDValue HighElt = N->getOperand(1); 7929 if (!isZeroNode(HighElt)) 7930 return SDValue(); 7931 7932 // Value must be a load. 7933 SDNode *Base = N->getOperand(0).getNode(); 7934 if (!isa<LoadSDNode>(Base)) { 7935 if (Base->getOpcode() != ISD::BIT_CONVERT) 7936 return SDValue(); 7937 Base = Base->getOperand(0).getNode(); 7938 if (!isa<LoadSDNode>(Base)) 7939 return SDValue(); 7940 } 7941 7942 // Transform it into VZEXT_LOAD addr. 7943 LoadSDNode *LD = cast<LoadSDNode>(Base); 7944 7945 // Load must not be an extload. 7946 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 7947 return SDValue(); 7948 7949 // Load type should legal type so we don't have to legalize it. 7950 if (!TLI.isTypeLegal(VT)) 7951 return SDValue(); 7952 7953 SDVTList Tys = DAG.getVTList(VT, MVT::Other); 7954 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 7955 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 7956 TargetLowering::TargetLoweringOpt TLO(DAG); 7957 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1)); 7958 DCI.CommitTargetLoweringOpt(TLO); 7959 return ResNode; 7960} 7961 7962/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 7963static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 7964 const X86Subtarget *Subtarget) { 7965 DebugLoc dl = N->getDebugLoc(); 7966 SDValue Cond = N->getOperand(0); 7967 7968 // If we have SSE[12] support, try to form min/max nodes. 7969 if (Subtarget->hasSSE2() && 7970 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 7971 if (Cond.getOpcode() == ISD::SETCC) { 7972 // Get the LHS/RHS of the select. 7973 SDValue LHS = N->getOperand(1); 7974 SDValue RHS = N->getOperand(2); 7975 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 7976 7977 unsigned Opcode = 0; 7978 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 7979 switch (CC) { 7980 default: break; 7981 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 7982 case ISD::SETULE: 7983 case ISD::SETLE: 7984 if (!UnsafeFPMath) break; 7985 // FALL THROUGH. 7986 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 7987 case ISD::SETLT: 7988 Opcode = X86ISD::FMIN; 7989 break; 7990 7991 case ISD::SETOGT: // (X > Y) ? X : Y -> max 7992 case ISD::SETUGT: 7993 case ISD::SETGT: 7994 if (!UnsafeFPMath) break; 7995 // FALL THROUGH. 7996 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 7997 case ISD::SETGE: 7998 Opcode = X86ISD::FMAX; 7999 break; 8000 } 8001 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 8002 switch (CC) { 8003 default: break; 8004 case ISD::SETOGT: // (X > Y) ? Y : X -> min 8005 case ISD::SETUGT: 8006 case ISD::SETGT: 8007 if (!UnsafeFPMath) break; 8008 // FALL THROUGH. 8009 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 8010 case ISD::SETGE: 8011 Opcode = X86ISD::FMIN; 8012 break; 8013 8014 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 8015 case ISD::SETULE: 8016 case ISD::SETLE: 8017 if (!UnsafeFPMath) break; 8018 // FALL THROUGH. 8019 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 8020 case ISD::SETLT: 8021 Opcode = X86ISD::FMAX; 8022 break; 8023 } 8024 } 8025 8026 if (Opcode) 8027 return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS); 8028 } 8029 8030 } 8031 8032 return SDValue(); 8033} 8034 8035/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 8036/// when possible. 8037static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 8038 const X86Subtarget *Subtarget) { 8039 // On X86 with SSE2 support, we can transform this to a vector shift if 8040 // all elements are shifted by the same amount. We can't do this in legalize 8041 // because the a constant vector is typically transformed to a constant pool 8042 // so we have no knowledge of the shift amount. 8043 if (!Subtarget->hasSSE2()) 8044 return SDValue(); 8045 8046 MVT VT = N->getValueType(0); 8047 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 8048 return SDValue(); 8049 8050 SDValue ShAmtOp = N->getOperand(1); 8051 MVT EltVT = VT.getVectorElementType(); 8052 DebugLoc dl = N->getDebugLoc(); 8053 SDValue BaseShAmt; 8054 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 8055 unsigned NumElts = VT.getVectorNumElements(); 8056 unsigned i = 0; 8057 for (; i != NumElts; ++i) { 8058 SDValue Arg = ShAmtOp.getOperand(i); 8059 if (Arg.getOpcode() == ISD::UNDEF) continue; 8060 BaseShAmt = Arg; 8061 break; 8062 } 8063 for (; i != NumElts; ++i) { 8064 SDValue Arg = ShAmtOp.getOperand(i); 8065 if (Arg.getOpcode() == ISD::UNDEF) continue; 8066 if (Arg != BaseShAmt) { 8067 return SDValue(); 8068 } 8069 } 8070 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 8071 isSplatMask(ShAmtOp.getOperand(2).getNode())) { 8072 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ShAmtOp, 8073 DAG.getIntPtrConstant(0)); 8074 } else 8075 return SDValue(); 8076 8077 if (EltVT.bitsGT(MVT::i32)) 8078 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt); 8079 else if (EltVT.bitsLT(MVT::i32)) 8080 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BaseShAmt); 8081 8082 // The shift amount is identical so we can do a vector shift. 8083 SDValue ValOp = N->getOperand(0); 8084 switch (N->getOpcode()) { 8085 default: 8086 assert(0 && "Unknown shift opcode!"); 8087 break; 8088 case ISD::SHL: 8089 if (VT == MVT::v2i64) 8090 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8091 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8092 ValOp, BaseShAmt); 8093 if (VT == MVT::v4i32) 8094 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8095 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 8096 ValOp, BaseShAmt); 8097 if (VT == MVT::v8i16) 8098 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8099 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 8100 ValOp, BaseShAmt); 8101 break; 8102 case ISD::SRA: 8103 if (VT == MVT::v4i32) 8104 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8105 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 8106 ValOp, BaseShAmt); 8107 if (VT == MVT::v8i16) 8108 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8109 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 8110 ValOp, BaseShAmt); 8111 break; 8112 case ISD::SRL: 8113 if (VT == MVT::v2i64) 8114 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8115 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8116 ValOp, BaseShAmt); 8117 if (VT == MVT::v4i32) 8118 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8119 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 8120 ValOp, BaseShAmt); 8121 if (VT == MVT::v8i16) 8122 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8123 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 8124 ValOp, BaseShAmt); 8125 break; 8126 } 8127 return SDValue(); 8128} 8129 8130/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 8131static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 8132 const X86Subtarget *Subtarget) { 8133 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 8134 // the FP state in cases where an emms may be missing. 8135 // A preferable solution to the general problem is to figure out the right 8136 // places to insert EMMS. This qualifies as a quick hack. 8137 StoreSDNode *St = cast<StoreSDNode>(N); 8138 if (St->getValue().getValueType().isVector() && 8139 St->getValue().getValueType().getSizeInBits() == 64 && 8140 isa<LoadSDNode>(St->getValue()) && 8141 !cast<LoadSDNode>(St->getValue())->isVolatile() && 8142 St->getChain().hasOneUse() && !St->isVolatile()) { 8143 SDNode* LdVal = St->getValue().getNode(); 8144 LoadSDNode *Ld = 0; 8145 int TokenFactorIndex = -1; 8146 SmallVector<SDValue, 8> Ops; 8147 SDNode* ChainVal = St->getChain().getNode(); 8148 // Must be a store of a load. We currently handle two cases: the load 8149 // is a direct child, and it's under an intervening TokenFactor. It is 8150 // possible to dig deeper under nested TokenFactors. 8151 if (ChainVal == LdVal) 8152 Ld = cast<LoadSDNode>(St->getChain()); 8153 else if (St->getValue().hasOneUse() && 8154 ChainVal->getOpcode() == ISD::TokenFactor) { 8155 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 8156 if (ChainVal->getOperand(i).getNode() == LdVal) { 8157 TokenFactorIndex = i; 8158 Ld = cast<LoadSDNode>(St->getValue()); 8159 } else 8160 Ops.push_back(ChainVal->getOperand(i)); 8161 } 8162 } 8163 if (Ld) { 8164 DebugLoc dl = N->getDebugLoc(); 8165 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 8166 if (Subtarget->is64Bit()) { 8167 SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(), 8168 Ld->getBasePtr(), Ld->getSrcValue(), 8169 Ld->getSrcValueOffset(), Ld->isVolatile(), 8170 Ld->getAlignment()); 8171 SDValue NewChain = NewLd.getValue(1); 8172 if (TokenFactorIndex != -1) { 8173 Ops.push_back(NewChain); 8174 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0], 8175 Ops.size()); 8176 } 8177 return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(), 8178 St->getSrcValue(), St->getSrcValueOffset(), 8179 St->isVolatile(), St->getAlignment()); 8180 } 8181 8182 // Otherwise, lower to two 32-bit copies. 8183 SDValue LoAddr = Ld->getBasePtr(); 8184 SDValue HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr, 8185 DAG.getConstant(4, MVT::i32)); 8186 8187 SDValue LoLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), LoAddr, 8188 Ld->getSrcValue(), Ld->getSrcValueOffset(), 8189 Ld->isVolatile(), Ld->getAlignment()); 8190 SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr, 8191 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 8192 Ld->isVolatile(), 8193 MinAlign(Ld->getAlignment(), 4)); 8194 8195 SDValue NewChain = LoLd.getValue(1); 8196 if (TokenFactorIndex != -1) { 8197 Ops.push_back(LoLd); 8198 Ops.push_back(HiLd); 8199 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0], 8200 Ops.size()); 8201 } 8202 8203 LoAddr = St->getBasePtr(); 8204 HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr, 8205 DAG.getConstant(4, MVT::i32)); 8206 8207 SDValue LoSt = DAG.getStore(NewChain, dl, LoLd, LoAddr, 8208 St->getSrcValue(), St->getSrcValueOffset(), 8209 St->isVolatile(), St->getAlignment()); 8210 SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr, 8211 St->getSrcValue(), 8212 St->getSrcValueOffset() + 4, 8213 St->isVolatile(), 8214 MinAlign(St->getAlignment(), 4)); 8215 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt); 8216 } 8217 } 8218 return SDValue(); 8219} 8220 8221/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 8222/// X86ISD::FXOR nodes. 8223static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 8224 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 8225 // F[X]OR(0.0, x) -> x 8226 // F[X]OR(x, 0.0) -> x 8227 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8228 if (C->getValueAPF().isPosZero()) 8229 return N->getOperand(1); 8230 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8231 if (C->getValueAPF().isPosZero()) 8232 return N->getOperand(0); 8233 return SDValue(); 8234} 8235 8236/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 8237static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 8238 // FAND(0.0, x) -> 0.0 8239 // FAND(x, 0.0) -> 0.0 8240 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8241 if (C->getValueAPF().isPosZero()) 8242 return N->getOperand(0); 8243 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8244 if (C->getValueAPF().isPosZero()) 8245 return N->getOperand(1); 8246 return SDValue(); 8247} 8248 8249static SDValue PerformBTCombine(SDNode *N, 8250 SelectionDAG &DAG, 8251 TargetLowering::DAGCombinerInfo &DCI) { 8252 // BT ignores high bits in the bit index operand. 8253 SDValue Op1 = N->getOperand(1); 8254 if (Op1.hasOneUse()) { 8255 unsigned BitWidth = Op1.getValueSizeInBits(); 8256 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 8257 APInt KnownZero, KnownOne; 8258 TargetLowering::TargetLoweringOpt TLO(DAG); 8259 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8260 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 8261 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 8262 DCI.CommitTargetLoweringOpt(TLO); 8263 } 8264 return SDValue(); 8265} 8266 8267SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 8268 DAGCombinerInfo &DCI) const { 8269 SelectionDAG &DAG = DCI.DAG; 8270 switch (N->getOpcode()) { 8271 default: break; 8272 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 8273 case ISD::BUILD_VECTOR: 8274 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this); 8275 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 8276 case ISD::SHL: 8277 case ISD::SRA: 8278 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 8279 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 8280 case X86ISD::FXOR: 8281 case X86ISD::FOR: return PerformFORCombine(N, DAG); 8282 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 8283 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 8284 } 8285 8286 return SDValue(); 8287} 8288 8289//===----------------------------------------------------------------------===// 8290// X86 Inline Assembly Support 8291//===----------------------------------------------------------------------===// 8292 8293/// getConstraintType - Given a constraint letter, return the type of 8294/// constraint it is for this target. 8295X86TargetLowering::ConstraintType 8296X86TargetLowering::getConstraintType(const std::string &Constraint) const { 8297 if (Constraint.size() == 1) { 8298 switch (Constraint[0]) { 8299 case 'A': 8300 return C_Register; 8301 case 'f': 8302 case 'r': 8303 case 'R': 8304 case 'l': 8305 case 'q': 8306 case 'Q': 8307 case 'x': 8308 case 'y': 8309 case 'Y': 8310 return C_RegisterClass; 8311 case 'e': 8312 case 'Z': 8313 return C_Other; 8314 default: 8315 break; 8316 } 8317 } 8318 return TargetLowering::getConstraintType(Constraint); 8319} 8320 8321/// LowerXConstraint - try to replace an X constraint, which matches anything, 8322/// with another that has more specific requirements based on the type of the 8323/// corresponding operand. 8324const char *X86TargetLowering:: 8325LowerXConstraint(MVT ConstraintVT) const { 8326 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 8327 // 'f' like normal targets. 8328 if (ConstraintVT.isFloatingPoint()) { 8329 if (Subtarget->hasSSE2()) 8330 return "Y"; 8331 if (Subtarget->hasSSE1()) 8332 return "x"; 8333 } 8334 8335 return TargetLowering::LowerXConstraint(ConstraintVT); 8336} 8337 8338/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8339/// vector. If it is invalid, don't add anything to Ops. 8340void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8341 char Constraint, 8342 bool hasMemory, 8343 std::vector<SDValue>&Ops, 8344 SelectionDAG &DAG) const { 8345 SDValue Result(0, 0); 8346 8347 switch (Constraint) { 8348 default: break; 8349 case 'I': 8350 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8351 if (C->getZExtValue() <= 31) { 8352 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8353 break; 8354 } 8355 } 8356 return; 8357 case 'J': 8358 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8359 if (C->getZExtValue() <= 63) { 8360 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8361 break; 8362 } 8363 } 8364 return; 8365 case 'N': 8366 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8367 if (C->getZExtValue() <= 255) { 8368 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8369 break; 8370 } 8371 } 8372 return; 8373 case 'e': { 8374 // 32-bit signed value 8375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8376 const ConstantInt *CI = C->getConstantIntValue(); 8377 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) { 8378 // Widen to 64 bits here to get it sign extended. 8379 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 8380 break; 8381 } 8382 // FIXME gcc accepts some relocatable values here too, but only in certain 8383 // memory models; it's complicated. 8384 } 8385 return; 8386 } 8387 case 'Z': { 8388 // 32-bit unsigned value 8389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8390 const ConstantInt *CI = C->getConstantIntValue(); 8391 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) { 8392 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8393 break; 8394 } 8395 } 8396 // FIXME gcc accepts some relocatable values here too, but only in certain 8397 // memory models; it's complicated. 8398 return; 8399 } 8400 case 'i': { 8401 // Literal immediates are always ok. 8402 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 8403 // Widen to 64 bits here to get it sign extended. 8404 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 8405 break; 8406 } 8407 8408 // If we are in non-pic codegen mode, we allow the address of a global (with 8409 // an optional displacement) to be used with 'i'. 8410 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 8411 int64_t Offset = 0; 8412 8413 // Match either (GA) or (GA+C) 8414 if (GA) { 8415 Offset = GA->getOffset(); 8416 } else if (Op.getOpcode() == ISD::ADD) { 8417 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8418 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 8419 if (C && GA) { 8420 Offset = GA->getOffset()+C->getZExtValue(); 8421 } else { 8422 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8423 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 8424 if (C && GA) 8425 Offset = GA->getOffset()+C->getZExtValue(); 8426 else 8427 C = 0, GA = 0; 8428 } 8429 } 8430 8431 if (GA) { 8432 if (hasMemory) 8433 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(), 8434 Offset, DAG); 8435 else 8436 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 8437 Offset); 8438 Result = Op; 8439 break; 8440 } 8441 8442 // Otherwise, not valid for this mode. 8443 return; 8444 } 8445 } 8446 8447 if (Result.getNode()) { 8448 Ops.push_back(Result); 8449 return; 8450 } 8451 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 8452 Ops, DAG); 8453} 8454 8455std::vector<unsigned> X86TargetLowering:: 8456getRegClassForInlineAsmConstraint(const std::string &Constraint, 8457 MVT VT) const { 8458 if (Constraint.size() == 1) { 8459 // FIXME: not handling fp-stack yet! 8460 switch (Constraint[0]) { // GCC X86 Constraint Letters 8461 default: break; // Unknown constraint letter 8462 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 8463 case 'Q': // Q_REGS 8464 if (VT == MVT::i32) 8465 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 8466 else if (VT == MVT::i16) 8467 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 8468 else if (VT == MVT::i8) 8469 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 8470 else if (VT == MVT::i64) 8471 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 8472 break; 8473 } 8474 } 8475 8476 return std::vector<unsigned>(); 8477} 8478 8479std::pair<unsigned, const TargetRegisterClass*> 8480X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8481 MVT VT) const { 8482 // First, see if this is a constraint that directly corresponds to an LLVM 8483 // register class. 8484 if (Constraint.size() == 1) { 8485 // GCC Constraint Letters 8486 switch (Constraint[0]) { 8487 default: break; 8488 case 'r': // GENERAL_REGS 8489 case 'R': // LEGACY_REGS 8490 case 'l': // INDEX_REGS 8491 if (VT == MVT::i8) 8492 return std::make_pair(0U, X86::GR8RegisterClass); 8493 if (VT == MVT::i16) 8494 return std::make_pair(0U, X86::GR16RegisterClass); 8495 if (VT == MVT::i32 || !Subtarget->is64Bit()) 8496 return std::make_pair(0U, X86::GR32RegisterClass); 8497 return std::make_pair(0U, X86::GR64RegisterClass); 8498 case 'f': // FP Stack registers. 8499 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 8500 // value to the correct fpstack register class. 8501 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 8502 return std::make_pair(0U, X86::RFP32RegisterClass); 8503 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 8504 return std::make_pair(0U, X86::RFP64RegisterClass); 8505 return std::make_pair(0U, X86::RFP80RegisterClass); 8506 case 'y': // MMX_REGS if MMX allowed. 8507 if (!Subtarget->hasMMX()) break; 8508 return std::make_pair(0U, X86::VR64RegisterClass); 8509 case 'Y': // SSE_REGS if SSE2 allowed 8510 if (!Subtarget->hasSSE2()) break; 8511 // FALL THROUGH. 8512 case 'x': // SSE_REGS if SSE1 allowed 8513 if (!Subtarget->hasSSE1()) break; 8514 8515 switch (VT.getSimpleVT()) { 8516 default: break; 8517 // Scalar SSE types. 8518 case MVT::f32: 8519 case MVT::i32: 8520 return std::make_pair(0U, X86::FR32RegisterClass); 8521 case MVT::f64: 8522 case MVT::i64: 8523 return std::make_pair(0U, X86::FR64RegisterClass); 8524 // Vector types. 8525 case MVT::v16i8: 8526 case MVT::v8i16: 8527 case MVT::v4i32: 8528 case MVT::v2i64: 8529 case MVT::v4f32: 8530 case MVT::v2f64: 8531 return std::make_pair(0U, X86::VR128RegisterClass); 8532 } 8533 break; 8534 } 8535 } 8536 8537 // Use the default implementation in TargetLowering to convert the register 8538 // constraint into a member of a register class. 8539 std::pair<unsigned, const TargetRegisterClass*> Res; 8540 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8541 8542 // Not found as a standard register? 8543 if (Res.second == 0) { 8544 // GCC calls "st(0)" just plain "st". 8545 if (StringsEqualNoCase("{st}", Constraint)) { 8546 Res.first = X86::ST0; 8547 Res.second = X86::RFP80RegisterClass; 8548 } 8549 // 'A' means EAX + EDX. 8550 if (Constraint == "A") { 8551 Res.first = X86::EAX; 8552 Res.second = X86::GRADRegisterClass; 8553 } 8554 return Res; 8555 } 8556 8557 // Otherwise, check to see if this is a register class of the wrong value 8558 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 8559 // turn into {ax},{dx}. 8560 if (Res.second->hasType(VT)) 8561 return Res; // Correct type already, nothing to do. 8562 8563 // All of the single-register GCC register classes map their values onto 8564 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 8565 // really want an 8-bit or 32-bit register, map to the appropriate register 8566 // class and return the appropriate register. 8567 if (Res.second == X86::GR16RegisterClass) { 8568 if (VT == MVT::i8) { 8569 unsigned DestReg = 0; 8570 switch (Res.first) { 8571 default: break; 8572 case X86::AX: DestReg = X86::AL; break; 8573 case X86::DX: DestReg = X86::DL; break; 8574 case X86::CX: DestReg = X86::CL; break; 8575 case X86::BX: DestReg = X86::BL; break; 8576 } 8577 if (DestReg) { 8578 Res.first = DestReg; 8579 Res.second = Res.second = X86::GR8RegisterClass; 8580 } 8581 } else if (VT == MVT::i32) { 8582 unsigned DestReg = 0; 8583 switch (Res.first) { 8584 default: break; 8585 case X86::AX: DestReg = X86::EAX; break; 8586 case X86::DX: DestReg = X86::EDX; break; 8587 case X86::CX: DestReg = X86::ECX; break; 8588 case X86::BX: DestReg = X86::EBX; break; 8589 case X86::SI: DestReg = X86::ESI; break; 8590 case X86::DI: DestReg = X86::EDI; break; 8591 case X86::BP: DestReg = X86::EBP; break; 8592 case X86::SP: DestReg = X86::ESP; break; 8593 } 8594 if (DestReg) { 8595 Res.first = DestReg; 8596 Res.second = Res.second = X86::GR32RegisterClass; 8597 } 8598 } else if (VT == MVT::i64) { 8599 unsigned DestReg = 0; 8600 switch (Res.first) { 8601 default: break; 8602 case X86::AX: DestReg = X86::RAX; break; 8603 case X86::DX: DestReg = X86::RDX; break; 8604 case X86::CX: DestReg = X86::RCX; break; 8605 case X86::BX: DestReg = X86::RBX; break; 8606 case X86::SI: DestReg = X86::RSI; break; 8607 case X86::DI: DestReg = X86::RDI; break; 8608 case X86::BP: DestReg = X86::RBP; break; 8609 case X86::SP: DestReg = X86::RSP; break; 8610 } 8611 if (DestReg) { 8612 Res.first = DestReg; 8613 Res.second = Res.second = X86::GR64RegisterClass; 8614 } 8615 } 8616 } else if (Res.second == X86::FR32RegisterClass || 8617 Res.second == X86::FR64RegisterClass || 8618 Res.second == X86::VR128RegisterClass) { 8619 // Handle references to XMM physical registers that got mapped into the 8620 // wrong class. This can happen with constraints like {xmm0} where the 8621 // target independent register mapper will just pick the first match it can 8622 // find, ignoring the required type. 8623 if (VT == MVT::f32) 8624 Res.second = X86::FR32RegisterClass; 8625 else if (VT == MVT::f64) 8626 Res.second = X86::FR64RegisterClass; 8627 else if (X86::VR128RegisterClass->hasType(VT)) 8628 Res.second = X86::VR128RegisterClass; 8629 } 8630 8631 return Res; 8632} 8633 8634//===----------------------------------------------------------------------===// 8635// X86 Widen vector type 8636//===----------------------------------------------------------------------===// 8637 8638/// getWidenVectorType: given a vector type, returns the type to widen 8639/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 8640/// If there is no vector type that we want to widen to, returns MVT::Other 8641/// When and where to widen is target dependent based on the cost of 8642/// scalarizing vs using the wider vector type. 8643 8644MVT X86TargetLowering::getWidenVectorType(MVT VT) const { 8645 assert(VT.isVector()); 8646 if (isTypeLegal(VT)) 8647 return VT; 8648 8649 // TODO: In computeRegisterProperty, we can compute the list of legal vector 8650 // type based on element type. This would speed up our search (though 8651 // it may not be worth it since the size of the list is relatively 8652 // small). 8653 MVT EltVT = VT.getVectorElementType(); 8654 unsigned NElts = VT.getVectorNumElements(); 8655 8656 // On X86, it make sense to widen any vector wider than 1 8657 if (NElts <= 1) 8658 return MVT::Other; 8659 8660 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 8661 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 8662 MVT SVT = (MVT::SimpleValueType)nVT; 8663 8664 if (isTypeLegal(SVT) && 8665 SVT.getVectorElementType() == EltVT && 8666 SVT.getVectorNumElements() > NElts) 8667 return SVT; 8668 } 8669 return MVT::Other; 8670} 8671