X86ISelLowering.cpp revision 2c651fe6f445724627dcc48064797dca2aa4aedc
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl) { 69 EVT VT = Vec.getValueType(); 70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 71 EVT ElVT = VT.getVectorElementType(); 72 int Factor = VT.getSizeInBits()/128; 73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 74 VT.getVectorNumElements()/Factor); 75 76 // Extract from UNDEF is UNDEF. 77 if (Vec.getOpcode() == ISD::UNDEF) 78 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 79 80 if (isa<ConstantSDNode>(Idx)) { 81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 82 83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 84 // we can match to VEXTRACTF128. 85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 86 87 // This is the index of the first element of the 128-bit chunk 88 // we want. 89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 90 * ElemsPerChunk); 91 92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 94 VecIdx); 95 96 return Result; 97 } 98 99 return SDValue(); 100} 101 102/// Generate a DAG to put 128-bits into a vector > 128 bits. This 103/// sets things up to match to an AVX VINSERTF128 instruction or a 104/// simple superregister reference. Idx is an index in the 128 bits 105/// we want. It need not be aligned to a 128-bit bounday. That makes 106/// lowering INSERT_VECTOR_ELT operations easier. 107static SDValue Insert128BitVector(SDValue Result, 108 SDValue Vec, 109 SDValue Idx, 110 SelectionDAG &DAG, 111 DebugLoc dl) { 112 if (isa<ConstantSDNode>(Idx)) { 113 EVT VT = Vec.getValueType(); 114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 115 116 EVT ElVT = VT.getVectorElementType(); 117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 118 EVT ResultVT = Result.getValueType(); 119 120 // Insert the relevant 128 bits. 121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 122 123 // This is the index of the first element of the 128-bit chunk 124 // we want. 125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 126 * ElemsPerChunk); 127 128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 130 VecIdx); 131 return Result; 132 } 133 134 return SDValue(); 135} 136 137static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 139 bool is64Bit = Subtarget->is64Bit(); 140 141 if (Subtarget->isTargetEnvMacho()) { 142 if (is64Bit) 143 return new X8664_MachoTargetObjectFile(); 144 return new TargetLoweringObjectFileMachO(); 145 } 146 147 if (Subtarget->isTargetELF()) 148 return new TargetLoweringObjectFileELF(); 149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 150 return new TargetLoweringObjectFileCOFF(); 151 llvm_unreachable("unknown subtarget type"); 152} 153 154X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 155 : TargetLowering(TM, createTLOF(TM)) { 156 Subtarget = &TM.getSubtarget<X86Subtarget>(); 157 X86ScalarSSEf64 = Subtarget->hasSSE2(); 158 X86ScalarSSEf32 = Subtarget->hasSSE1(); 159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 160 161 RegInfo = TM.getRegisterInfo(); 162 TD = getTargetData(); 163 164 // Set up the TargetLowering object. 165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 166 167 // X86 is weird, it always uses i8 for shift amounts and setcc results. 168 setBooleanContents(ZeroOrOneBooleanContent); 169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 171 172 // For 64-bit since we have so many registers use the ILP scheduler, for 173 // 32-bit code use the register pressure specific scheduling. 174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 175 if (Subtarget->is64Bit()) 176 setSchedulingPreference(Sched::ILP); 177 else if (Subtarget->isAtom()) 178 setSchedulingPreference(Sched::Hybrid); 179 else 180 setSchedulingPreference(Sched::RegPressure); 181 setStackPointerRegisterToSaveRestore(X86StackPtr); 182 183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 184 // Setup Windows compiler runtime calls. 185 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 187 setLibcallName(RTLIB::SREM_I64, "_allrem"); 188 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 189 setLibcallName(RTLIB::MUL_I64, "_allmul"); 190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 195 196 // The _ftol2 runtime function has an unusual calling conv, which 197 // is modeled by a special pseudo-instruction. 198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 202 } 203 204 if (Subtarget->isTargetDarwin()) { 205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 206 setUseUnderscoreSetJmp(false); 207 setUseUnderscoreLongJmp(false); 208 } else if (Subtarget->isTargetMingw()) { 209 // MS runtime is weird: it exports _setjmp, but longjmp! 210 setUseUnderscoreSetJmp(true); 211 setUseUnderscoreLongJmp(false); 212 } else { 213 setUseUnderscoreSetJmp(true); 214 setUseUnderscoreLongJmp(true); 215 } 216 217 // Set up the register classes. 218 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 219 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 220 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 221 if (Subtarget->is64Bit()) 222 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 223 224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 225 226 // We don't accept any truncstore of integer registers. 227 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 228 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 230 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 232 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 233 234 // SETOEQ and SETUNE require checking two conditions. 235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 241 242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 243 // operation. 244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 247 248 if (Subtarget->is64Bit()) { 249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 } else if (!TM.Options.UseSoftFloat) { 252 // We have an algorithm for SSE2->double, and we turn this into a 253 // 64-bit FILD followed by conditional FADD for other targets. 254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 255 // We have an algorithm for SSE2, and we turn this into a 64-bit 256 // FILD for other targets. 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 258 } 259 260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 261 // this operation. 262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 264 265 if (!TM.Options.UseSoftFloat) { 266 // SSE has no i16 to fp conversion, only i32 267 if (X86ScalarSSEf32) { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 269 // f32 and f64 cases are Legal, f80 case is not 270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 274 } 275 } else { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 278 } 279 280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 281 // are Legal, f80 is custom lowered. 282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 284 285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 286 // this operation. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 289 290 if (X86ScalarSSEf32) { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 292 // f32 and f64 cases are Legal, f80 case is not 293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 294 } else { 295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 297 } 298 299 // Handle FP_TO_UINT by promoting the destination to a larger signed 300 // conversion. 301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 304 305 if (Subtarget->is64Bit()) { 306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 308 } else if (!TM.Options.UseSoftFloat) { 309 // Since AVX is a superset of SSE3, only check for SSE here. 310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 311 // Expand FP_TO_UINT into a select. 312 // FIXME: We would like to use a Custom expander here eventually to do 313 // the optimal thing for SSE vs. the default expansion in the legalizer. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 315 else 316 // With SSE3 we can use fisttpll to convert to a signed i64; without 317 // SSE, we're stuck with a fistpll. 318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 319 } 320 321 if (isTargetFTOL()) { 322 // Use the _ftol2 runtime function, which has a pseudo-instruction 323 // to handle its weird calling convention. 324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 325 } 326 327 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 328 if (!X86ScalarSSEf64) { 329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 331 if (Subtarget->is64Bit()) { 332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 333 // Without SSE, i64->f64 goes through memory. 334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 335 } 336 } 337 338 // Scalar integer divide and remainder are lowered to use operations that 339 // produce two results, to match the available instructions. This exposes 340 // the two-result form to trivial CSE, which is able to combine x/y and x%y 341 // into a single instruction. 342 // 343 // Scalar integer multiply-high is also lowered to use two-result 344 // operations, to match the available instructions. However, plain multiply 345 // (low) operations are left as Legal, as there are single-result 346 // instructions for this in x86. Using the two-result multiply instructions 347 // when both high and low results are needed must be arranged by dagcombine. 348 for (unsigned i = 0, e = 4; i != e; ++i) { 349 MVT VT = IntVTs[i]; 350 setOperationAction(ISD::MULHS, VT, Expand); 351 setOperationAction(ISD::MULHU, VT, Expand); 352 setOperationAction(ISD::SDIV, VT, Expand); 353 setOperationAction(ISD::UDIV, VT, Expand); 354 setOperationAction(ISD::SREM, VT, Expand); 355 setOperationAction(ISD::UREM, VT, Expand); 356 357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 358 setOperationAction(ISD::ADDC, VT, Custom); 359 setOperationAction(ISD::ADDE, VT, Custom); 360 setOperationAction(ISD::SUBC, VT, Custom); 361 setOperationAction(ISD::SUBE, VT, Custom); 362 } 363 364 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 365 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 366 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 368 if (Subtarget->is64Bit()) 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f32 , Expand); 375 setOperationAction(ISD::FREM , MVT::f64 , Expand); 376 setOperationAction(ISD::FREM , MVT::f80 , Expand); 377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 378 379 // Promote the i8 variants and force them on up to i32 which has a shorter 380 // encoding. 381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 385 if (Subtarget->hasBMI()) { 386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 388 if (Subtarget->is64Bit()) 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 390 } else { 391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 393 if (Subtarget->is64Bit()) 394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 395 } 396 397 if (Subtarget->hasLZCNT()) { 398 // When promoting the i8 variants, force them to i32 for a shorter 399 // encoding. 400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 406 if (Subtarget->is64Bit()) 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 408 } else { 409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 418 } 419 } 420 421 if (Subtarget->hasPOPCNT()) { 422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 423 } else { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 427 if (Subtarget->is64Bit()) 428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 429 } 430 431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 433 434 // These should be promoted to a larger select which is supported. 435 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 436 // X86 wants to expand cmov itself. 437 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 438 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 439 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 440 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 441 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 443 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 444 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 446 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 447 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 449 if (Subtarget->is64Bit()) { 450 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 451 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 452 } 453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 454 455 // Darwin ABI issue. 456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 464 if (Subtarget->is64Bit()) { 465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 470 } 471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 475 if (Subtarget->is64Bit()) { 476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 479 } 480 481 if (Subtarget->hasSSE1()) 482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 483 484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 486 487 // On X86 and X86-64, atomic operations are lowered to locked instructions. 488 // Locked instructions, in turn, have implicit fence semantics (all memory 489 // operations are flushed before issuing the locked instruction, and they 490 // are not buffered), so we can fold away the common pattern of 491 // fence-atomic-fence. 492 setShouldFoldAtomicFences(true); 493 494 // Expand certain atomics 495 for (unsigned i = 0, e = 4; i != e; ++i) { 496 MVT VT = IntVTs[i]; 497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 500 } 501 502 if (!Subtarget->is64Bit()) { 503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 511 } 512 513 if (Subtarget->hasCmpxchg16b()) { 514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 515 } 516 517 // FIXME - use subtarget debug flags 518 if (!Subtarget->isTargetDarwin() && 519 !Subtarget->isTargetELF() && 520 !Subtarget->isTargetCygMing()) { 521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 522 } 523 524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 528 if (Subtarget->is64Bit()) { 529 setExceptionPointerRegister(X86::RAX); 530 setExceptionSelectorRegister(X86::RDX); 531 } else { 532 setExceptionPointerRegister(X86::EAX); 533 setExceptionSelectorRegister(X86::EDX); 534 } 535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 537 538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 540 541 setOperationAction(ISD::TRAP, MVT::Other, Legal); 542 543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 544 setOperationAction(ISD::VASTART , MVT::Other, Custom); 545 setOperationAction(ISD::VAEND , MVT::Other, Expand); 546 if (Subtarget->is64Bit()) { 547 setOperationAction(ISD::VAARG , MVT::Other, Custom); 548 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 549 } else { 550 setOperationAction(ISD::VAARG , MVT::Other, Expand); 551 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 552 } 553 554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 556 557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 559 MVT::i64 : MVT::i32, Custom); 560 else if (TM.Options.EnableSegmentedStacks) 561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 562 MVT::i64 : MVT::i32, Custom); 563 else 564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 565 MVT::i64 : MVT::i32, Expand); 566 567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 568 // f32 and f64 use SSE. 569 // Set up the FP register classes. 570 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 571 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 572 573 // Use ANDPD to simulate FABS. 574 setOperationAction(ISD::FABS , MVT::f64, Custom); 575 setOperationAction(ISD::FABS , MVT::f32, Custom); 576 577 // Use XORP to simulate FNEG. 578 setOperationAction(ISD::FNEG , MVT::f64, Custom); 579 setOperationAction(ISD::FNEG , MVT::f32, Custom); 580 581 // Use ANDPD and ORPD to simulate FCOPYSIGN. 582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 584 585 // Lower this to FGETSIGNx86 plus an AND. 586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 588 589 // We don't support sin/cos/fmod 590 setOperationAction(ISD::FSIN , MVT::f64, Expand); 591 setOperationAction(ISD::FCOS , MVT::f64, Expand); 592 setOperationAction(ISD::FSIN , MVT::f32, Expand); 593 setOperationAction(ISD::FCOS , MVT::f32, Expand); 594 595 // Expand FP immediates into loads from the stack, except for the special 596 // cases we handle. 597 addLegalFPImmediate(APFloat(+0.0)); // xorpd 598 addLegalFPImmediate(APFloat(+0.0f)); // xorps 599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 600 // Use SSE for f32, x87 for f64. 601 // Set up the FP register classes. 602 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 604 605 // Use ANDPS to simulate FABS. 606 setOperationAction(ISD::FABS , MVT::f32, Custom); 607 608 // Use XORP to simulate FNEG. 609 setOperationAction(ISD::FNEG , MVT::f32, Custom); 610 611 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 612 613 // Use ANDPS and ORPS to simulate FCOPYSIGN. 614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 616 617 // We don't support sin/cos/fmod 618 setOperationAction(ISD::FSIN , MVT::f32, Expand); 619 setOperationAction(ISD::FCOS , MVT::f32, Expand); 620 621 // Special cases we handle for FP constants. 622 addLegalFPImmediate(APFloat(+0.0f)); // xorps 623 addLegalFPImmediate(APFloat(+0.0)); // FLD0 624 addLegalFPImmediate(APFloat(+1.0)); // FLD1 625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 627 628 if (!TM.Options.UnsafeFPMath) { 629 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 630 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 631 } 632 } else if (!TM.Options.UseSoftFloat) { 633 // f32 and f64 in x87. 634 // Set up the FP register classes. 635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 637 638 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 639 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 642 643 if (!TM.Options.UnsafeFPMath) { 644 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 645 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 646 } 647 addLegalFPImmediate(APFloat(+0.0)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 655 } 656 657 // We don't support FMA. 658 setOperationAction(ISD::FMA, MVT::f64, Expand); 659 setOperationAction(ISD::FMA, MVT::f32, Expand); 660 661 // Long double always uses X87. 662 if (!TM.Options.UseSoftFloat) { 663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 664 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 666 { 667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 668 addLegalFPImmediate(TmpFlt); // FLD0 669 TmpFlt.changeSign(); 670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 671 672 bool ignored; 673 APFloat TmpFlt2(+1.0); 674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 675 &ignored); 676 addLegalFPImmediate(TmpFlt2); // FLD1 677 TmpFlt2.changeSign(); 678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 679 } 680 681 if (!TM.Options.UnsafeFPMath) { 682 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 683 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 684 } 685 686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 687 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 689 setOperationAction(ISD::FRINT, MVT::f80, Expand); 690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 691 setOperationAction(ISD::FMA, MVT::f80, Expand); 692 } 693 694 // Always use a library call for pow. 695 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 696 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 697 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 698 699 setOperationAction(ISD::FLOG, MVT::f80, Expand); 700 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 701 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 702 setOperationAction(ISD::FEXP, MVT::f80, Expand); 703 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 704 705 // First set operation action for all vector types to either promote 706 // (for widening) or expand (for scalarization). Then we will selectively 707 // turn on ones that can be effectively codegen'd. 708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 769 setTruncStoreAction((MVT::SimpleValueType)VT, 770 (MVT::SimpleValueType)InnerVT, Expand); 771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 } 775 776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 777 // with -msoft-float, disable use of MMX as well. 778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 780 // No operations on x86mmx supported, everything uses intrinsics. 781 } 782 783 // MMX-sized vectors (other than x86mmx) are expected to be expanded 784 // into smaller operations. 785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 789 setOperationAction(ISD::AND, MVT::v8i8, Expand); 790 setOperationAction(ISD::AND, MVT::v4i16, Expand); 791 setOperationAction(ISD::AND, MVT::v2i32, Expand); 792 setOperationAction(ISD::AND, MVT::v1i64, Expand); 793 setOperationAction(ISD::OR, MVT::v8i8, Expand); 794 setOperationAction(ISD::OR, MVT::v4i16, Expand); 795 setOperationAction(ISD::OR, MVT::v2i32, Expand); 796 setOperationAction(ISD::OR, MVT::v1i64, Expand); 797 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 814 815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 817 818 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 830 } 831 832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 834 835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 836 // registers cannot be used even for integer operations. 837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 841 842 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 843 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 844 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 845 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 846 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 847 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 848 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 849 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 850 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 851 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 852 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 858 859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 863 864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 869 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 875 876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 878 EVT VT = (MVT::SimpleValueType)i; 879 // Do not attempt to custom lower non-power-of-2 vectors 880 if (!isPowerOf2_32(VT.getVectorNumElements())) 881 continue; 882 // Do not attempt to custom lower non-128-bit vectors 883 if (!VT.is128BitVector()) 884 continue; 885 setOperationAction(ISD::BUILD_VECTOR, 886 VT.getSimpleVT().SimpleTy, Custom); 887 setOperationAction(ISD::VECTOR_SHUFFLE, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 890 VT.getSimpleVT().SimpleTy, Custom); 891 } 892 893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 899 900 if (Subtarget->is64Bit()) { 901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 903 } 904 905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 908 EVT VT = SVT; 909 910 // Do not attempt to promote non-128-bit vectors 911 if (!VT.is128BitVector()) 912 continue; 913 914 setOperationAction(ISD::AND, SVT, Promote); 915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 916 setOperationAction(ISD::OR, SVT, Promote); 917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 918 setOperationAction(ISD::XOR, SVT, Promote); 919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 920 setOperationAction(ISD::LOAD, SVT, Promote); 921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 922 setOperationAction(ISD::SELECT, SVT, Promote); 923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 924 } 925 926 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 927 928 // Custom lower v2i64 and v2f64 selects. 929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 933 934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 936 } 937 938 if (Subtarget->hasSSE41()) { 939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 940 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 942 setOperationAction(ISD::FRINT, MVT::f32, Legal); 943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 945 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 947 setOperationAction(ISD::FRINT, MVT::f64, Legal); 948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 949 950 // FIXME: Do we need to handle scalar-to-vector here? 951 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 952 953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 958 959 // i8 and i16 vectors are custom , because the source register and source 960 // source memory operand types are not the same width. f32 vectors are 961 // custom since the immediate controlling the insert encodes additional 962 // information. 963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 967 968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 972 973 // FIXME: these should be Legal but thats only for the case where 974 // the index is constant. For now custom expand to deal with that. 975 if (Subtarget->is64Bit()) { 976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 978 } 979 } 980 981 if (Subtarget->hasSSE2()) { 982 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 983 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 984 985 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 986 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 987 988 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 989 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 990 991 if (Subtarget->hasAVX2()) { 992 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 993 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 994 995 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 996 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 997 998 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 999 } else { 1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1002 1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1005 1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1007 } 1008 } 1009 1010 if (Subtarget->hasSSE42()) 1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1012 1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1020 1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1024 1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1031 1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1038 1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1042 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1049 1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1052 1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1055 1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1058 1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1063 1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1067 1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1072 1073 if (Subtarget->hasAVX2()) { 1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1078 1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1083 1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1087 // Don't lower v32i8 because there is no 128-bit byte mul 1088 1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1090 1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1093 1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1096 1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1098 } else { 1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1103 1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1108 1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1112 // Don't lower v32i8 because there is no 128-bit byte mul 1113 1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1116 1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1119 1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1121 } 1122 1123 // Custom lower several nodes for 256-bit types. 1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1127 EVT VT = SVT; 1128 1129 // Extract subvector is special because the value type 1130 // (result) is 128-bit but the source is 256-bit wide. 1131 if (VT.is128BitVector()) 1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1133 1134 // Do not attempt to custom lower other non-256-bit vectors 1135 if (!VT.is256BitVector()) 1136 continue; 1137 1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1144 } 1145 1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1149 EVT VT = SVT; 1150 1151 // Do not attempt to promote non-256-bit vectors 1152 if (!VT.is256BitVector()) 1153 continue; 1154 1155 setOperationAction(ISD::AND, SVT, Promote); 1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1157 setOperationAction(ISD::OR, SVT, Promote); 1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1159 setOperationAction(ISD::XOR, SVT, Promote); 1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::LOAD, SVT, Promote); 1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1163 setOperationAction(ISD::SELECT, SVT, Promote); 1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1165 } 1166 } 1167 1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1169 // of this type with custom code. 1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1173 Custom); 1174 } 1175 1176 // We want to custom lower some of our intrinsics. 1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1178 1179 1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1181 // handle type legalization for these operations here. 1182 // 1183 // FIXME: We really should do custom legalization for addition and 1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1185 // than generic legalization for 64-bit multiplication-with-overflow, though. 1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1187 // Add/Sub/Mul with overflow operations are custom lowered. 1188 MVT VT = IntVTs[i]; 1189 setOperationAction(ISD::SADDO, VT, Custom); 1190 setOperationAction(ISD::UADDO, VT, Custom); 1191 setOperationAction(ISD::SSUBO, VT, Custom); 1192 setOperationAction(ISD::USUBO, VT, Custom); 1193 setOperationAction(ISD::SMULO, VT, Custom); 1194 setOperationAction(ISD::UMULO, VT, Custom); 1195 } 1196 1197 // There are no 8-bit 3-address imul/mul instructions 1198 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1199 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1200 1201 if (!Subtarget->is64Bit()) { 1202 // These libcalls are not available in 32-bit. 1203 setLibcallName(RTLIB::SHL_I128, 0); 1204 setLibcallName(RTLIB::SRL_I128, 0); 1205 setLibcallName(RTLIB::SRA_I128, 0); 1206 } 1207 1208 // We have target-specific dag combine patterns for the following nodes: 1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1211 setTargetDAGCombine(ISD::VSELECT); 1212 setTargetDAGCombine(ISD::SELECT); 1213 setTargetDAGCombine(ISD::SHL); 1214 setTargetDAGCombine(ISD::SRA); 1215 setTargetDAGCombine(ISD::SRL); 1216 setTargetDAGCombine(ISD::OR); 1217 setTargetDAGCombine(ISD::AND); 1218 setTargetDAGCombine(ISD::ADD); 1219 setTargetDAGCombine(ISD::FADD); 1220 setTargetDAGCombine(ISD::FSUB); 1221 setTargetDAGCombine(ISD::SUB); 1222 setTargetDAGCombine(ISD::LOAD); 1223 setTargetDAGCombine(ISD::STORE); 1224 setTargetDAGCombine(ISD::ZERO_EXTEND); 1225 setTargetDAGCombine(ISD::SIGN_EXTEND); 1226 setTargetDAGCombine(ISD::TRUNCATE); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasSSE1()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->getStackAlignment() >= 32) { 1331 if (Subtarget->hasAVX2()) 1332 return MVT::v8i32; 1333 if (Subtarget->hasAVX()) 1334 return MVT::v8f32; 1335 } 1336 if (Subtarget->hasSSE2()) 1337 return MVT::v4i32; 1338 if (Subtarget->hasSSE1()) 1339 return MVT::v4f32; 1340 } else if (!MemcpyStrSrc && Size >= 8 && 1341 !Subtarget->is64Bit() && 1342 Subtarget->getStackAlignment() >= 8 && 1343 Subtarget->hasSSE2()) { 1344 // Do not use f64 to lower memcpy if source is string constant. It's 1345 // better to use i32 to avoid the loads. 1346 return MVT::f64; 1347 } 1348 } 1349 if (Subtarget->is64Bit() && Size >= 8) 1350 return MVT::i64; 1351 return MVT::i32; 1352} 1353 1354/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1355/// current function. The returned value is a member of the 1356/// MachineJumpTableInfo::JTEntryKind enum. 1357unsigned X86TargetLowering::getJumpTableEncoding() const { 1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1359 // symbol. 1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1361 Subtarget->isPICStyleGOT()) 1362 return MachineJumpTableInfo::EK_Custom32; 1363 1364 // Otherwise, use the normal jump table encoding heuristics. 1365 return TargetLowering::getJumpTableEncoding(); 1366} 1367 1368const MCExpr * 1369X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1370 const MachineBasicBlock *MBB, 1371 unsigned uid,MCContext &Ctx) const{ 1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1373 Subtarget->isPICStyleGOT()); 1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1375 // entries. 1376 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1377 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1378} 1379 1380/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1381/// jumptable. 1382SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1383 SelectionDAG &DAG) const { 1384 if (!Subtarget->is64Bit()) 1385 // This doesn't have DebugLoc associated with it, but is not really the 1386 // same as a Register. 1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1388 return Table; 1389} 1390 1391/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1392/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1393/// MCExpr. 1394const MCExpr *X86TargetLowering:: 1395getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1396 MCContext &Ctx) const { 1397 // X86-64 uses RIP relative addressing based on the jump table label. 1398 if (Subtarget->isPICStyleRIPRel()) 1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1400 1401 // Otherwise, the reference is relative to the PIC base. 1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1403} 1404 1405// FIXME: Why this routine is here? Move to RegInfo! 1406std::pair<const TargetRegisterClass*, uint8_t> 1407X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1408 const TargetRegisterClass *RRC = 0; 1409 uint8_t Cost = 1; 1410 switch (VT.getSimpleVT().SimpleTy) { 1411 default: 1412 return TargetLowering::findRepresentativeClass(VT); 1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1414 RRC = (Subtarget->is64Bit() 1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1416 break; 1417 case MVT::x86mmx: 1418 RRC = X86::VR64RegisterClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = X86::VR128RegisterClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDValue TCChain = Chain; 1588 SDNode *Copy = *N->use_begin(); 1589 if (Copy->getOpcode() == ISD::CopyToReg) { 1590 // If the copy has a glue operand, we conservatively assume it isn't safe to 1591 // perform a tail call. 1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1593 return false; 1594 TCChain = Copy->getOperand(0); 1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1596 return false; 1597 1598 bool HasRet = false; 1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1600 UI != UE; ++UI) { 1601 if (UI->getOpcode() != X86ISD::RET_FLAG) 1602 return false; 1603 HasRet = true; 1604 } 1605 1606 if (!HasRet) 1607 return false; 1608 1609 Chain = TCChain; 1610 return true; 1611} 1612 1613EVT 1614X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1615 ISD::NodeType ExtendKind) const { 1616 MVT ReturnMVT; 1617 // TODO: Is this also valid on 32-bit? 1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1619 ReturnMVT = MVT::i8; 1620 else 1621 ReturnMVT = MVT::i32; 1622 1623 EVT MinVT = getRegisterType(Context, ReturnMVT); 1624 return VT.bitsLT(MinVT) ? MinVT : VT; 1625} 1626 1627/// LowerCallResult - Lower the result values of a call into the 1628/// appropriate copies out of appropriate physical registers. 1629/// 1630SDValue 1631X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1632 CallingConv::ID CallConv, bool isVarArg, 1633 const SmallVectorImpl<ISD::InputArg> &Ins, 1634 DebugLoc dl, SelectionDAG &DAG, 1635 SmallVectorImpl<SDValue> &InVals) const { 1636 1637 // Assign locations to each value returned by this call. 1638 SmallVector<CCValAssign, 16> RVLocs; 1639 bool Is64Bit = Subtarget->is64Bit(); 1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1641 getTargetMachine(), RVLocs, *DAG.getContext()); 1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1643 1644 // Copy all of the result registers out of their specified physreg. 1645 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1646 CCValAssign &VA = RVLocs[i]; 1647 EVT CopyVT = VA.getValVT(); 1648 1649 // If this is x86-64, and we disabled SSE, we can't return FP values 1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1652 report_fatal_error("SSE register return with SSE disabled"); 1653 } 1654 1655 SDValue Val; 1656 1657 // If this is a call to a function that returns an fp value on the floating 1658 // point stack, we must guarantee the the value is popped from the stack, so 1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1660 // if the return value is not used. We use the FpPOP_RETVAL instruction 1661 // instead. 1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1663 // If we prefer to use the value in xmm registers, copy it out as f80 and 1664 // use a truncate to move it from fp stack reg to xmm reg. 1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1666 SDValue Ops[] = { Chain, InFlag }; 1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1668 MVT::Other, MVT::Glue, Ops, 2), 1); 1669 Val = Chain.getValue(0); 1670 1671 // Round the f80 to the right size, which also moves it to the appropriate 1672 // xmm register. 1673 if (CopyVT != VA.getValVT()) 1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1675 // This truncation won't change the value. 1676 DAG.getIntPtrConstant(1)); 1677 } else { 1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1679 CopyVT, InFlag).getValue(1); 1680 Val = Chain.getValue(0); 1681 } 1682 InFlag = Chain.getValue(2); 1683 InVals.push_back(Val); 1684 } 1685 1686 return Chain; 1687} 1688 1689 1690//===----------------------------------------------------------------------===// 1691// C & StdCall & Fast Calling Convention implementation 1692//===----------------------------------------------------------------------===// 1693// StdCall calling convention seems to be standard for many Windows' API 1694// routines and around. It differs from C calling convention just a little: 1695// callee should clean up the stack, not caller. Symbols should be also 1696// decorated in some fancy way :) It doesn't support any vector arguments. 1697// For info on fast calling convention see Fast Calling Convention (tail call) 1698// implementation LowerX86_32FastCCCallTo. 1699 1700/// CallIsStructReturn - Determines whether a call uses struct return 1701/// semantics. 1702static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1703 if (Outs.empty()) 1704 return false; 1705 1706 return Outs[0].Flags.isSRet(); 1707} 1708 1709/// ArgsAreStructReturn - Determines whether a function uses struct 1710/// return semantics. 1711static bool 1712ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1713 if (Ins.empty()) 1714 return false; 1715 1716 return Ins[0].Flags.isSRet(); 1717} 1718 1719/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1720/// by "Src" to address "Dst" with size and alignment information specified by 1721/// the specific parameter attribute. The copy will be passed as a byval 1722/// function parameter. 1723static SDValue 1724CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1726 DebugLoc dl) { 1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1728 1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1730 /*isVolatile*/false, /*AlwaysInline=*/true, 1731 MachinePointerInfo(), MachinePointerInfo()); 1732} 1733 1734/// IsTailCallConvention - Return true if the calling convention is one that 1735/// supports tail call optimization. 1736static bool IsTailCallConvention(CallingConv::ID CC) { 1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1738} 1739 1740bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1742 return false; 1743 1744 CallSite CS(CI); 1745 CallingConv::ID CalleeCC = CS.getCallingConv(); 1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1747 return false; 1748 1749 return true; 1750} 1751 1752/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1753/// a tailcall target by changing its ABI. 1754static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1755 bool GuaranteedTailCallOpt) { 1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1757} 1758 1759SDValue 1760X86TargetLowering::LowerMemArgument(SDValue Chain, 1761 CallingConv::ID CallConv, 1762 const SmallVectorImpl<ISD::InputArg> &Ins, 1763 DebugLoc dl, SelectionDAG &DAG, 1764 const CCValAssign &VA, 1765 MachineFrameInfo *MFI, 1766 unsigned i) const { 1767 // Create the nodes corresponding to a load from this parameter slot. 1768 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1770 getTargetMachine().Options.GuaranteedTailCallOpt); 1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1772 EVT ValVT; 1773 1774 // If value is passed by pointer we have address passed instead of the value 1775 // itself. 1776 if (VA.getLocInfo() == CCValAssign::Indirect) 1777 ValVT = VA.getLocVT(); 1778 else 1779 ValVT = VA.getValVT(); 1780 1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1782 // changed with more analysis. 1783 // In case of tail call optimization mark all arguments mutable. Since they 1784 // could be overwritten by lowering of arguments in case of a tail call. 1785 if (Flags.isByVal()) { 1786 unsigned Bytes = Flags.getByValSize(); 1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1789 return DAG.getFrameIndex(FI, getPointerTy()); 1790 } else { 1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1792 VA.getLocMemOffset(), isImmutable); 1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1794 return DAG.getLoad(ValVT, dl, Chain, FIN, 1795 MachinePointerInfo::getFixedStack(FI), 1796 false, false, false, 0); 1797 } 1798} 1799 1800SDValue 1801X86TargetLowering::LowerFormalArguments(SDValue Chain, 1802 CallingConv::ID CallConv, 1803 bool isVarArg, 1804 const SmallVectorImpl<ISD::InputArg> &Ins, 1805 DebugLoc dl, 1806 SelectionDAG &DAG, 1807 SmallVectorImpl<SDValue> &InVals) 1808 const { 1809 MachineFunction &MF = DAG.getMachineFunction(); 1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1811 1812 const Function* Fn = MF.getFunction(); 1813 if (Fn->hasExternalLinkage() && 1814 Subtarget->isTargetCygMing() && 1815 Fn->getName() == "main") 1816 FuncInfo->setForceFramePointer(true); 1817 1818 MachineFrameInfo *MFI = MF.getFrameInfo(); 1819 bool Is64Bit = Subtarget->is64Bit(); 1820 bool IsWindows = Subtarget->isTargetWindows(); 1821 bool IsWin64 = Subtarget->isTargetWin64(); 1822 1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1824 "Var args not supported with calling convention fastcc or ghc"); 1825 1826 // Assign locations to all of the incoming arguments. 1827 SmallVector<CCValAssign, 16> ArgLocs; 1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1829 ArgLocs, *DAG.getContext()); 1830 1831 // Allocate shadow area for Win64 1832 if (IsWin64) { 1833 CCInfo.AllocateStack(32, 8); 1834 } 1835 1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1837 1838 unsigned LastVal = ~0U; 1839 SDValue ArgValue; 1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1841 CCValAssign &VA = ArgLocs[i]; 1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1843 // places. 1844 assert(VA.getValNo() != LastVal && 1845 "Don't support value assigned to multiple locs yet"); 1846 (void)LastVal; 1847 LastVal = VA.getValNo(); 1848 1849 if (VA.isRegLoc()) { 1850 EVT RegVT = VA.getLocVT(); 1851 const TargetRegisterClass *RC; 1852 if (RegVT == MVT::i32) 1853 RC = X86::GR32RegisterClass; 1854 else if (Is64Bit && RegVT == MVT::i64) 1855 RC = X86::GR64RegisterClass; 1856 else if (RegVT == MVT::f32) 1857 RC = X86::FR32RegisterClass; 1858 else if (RegVT == MVT::f64) 1859 RC = X86::FR64RegisterClass; 1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1861 RC = X86::VR256RegisterClass; 1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1863 RC = X86::VR128RegisterClass; 1864 else if (RegVT == MVT::x86mmx) 1865 RC = X86::VR64RegisterClass; 1866 else 1867 llvm_unreachable("Unknown argument type!"); 1868 1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1871 1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1874 // right size. 1875 if (VA.getLocInfo() == CCValAssign::SExt) 1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1877 DAG.getValueType(VA.getValVT())); 1878 else if (VA.getLocInfo() == CCValAssign::ZExt) 1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1880 DAG.getValueType(VA.getValVT())); 1881 else if (VA.getLocInfo() == CCValAssign::BCvt) 1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1883 1884 if (VA.isExtInLoc()) { 1885 // Handle MMX values passed in XMM regs. 1886 if (RegVT.isVector()) { 1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1888 ArgValue); 1889 } else 1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1891 } 1892 } else { 1893 assert(VA.isMemLoc()); 1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1895 } 1896 1897 // If value is passed via pointer - do a load. 1898 if (VA.getLocInfo() == CCValAssign::Indirect) 1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1900 MachinePointerInfo(), false, false, false, 0); 1901 1902 InVals.push_back(ArgValue); 1903 } 1904 1905 // The x86-64 ABI for returning structs by value requires that we copy 1906 // the sret argument into %rax for the return. Save the argument into 1907 // a virtual register so that we can access it from the return points. 1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1910 unsigned Reg = FuncInfo->getSRetReturnReg(); 1911 if (!Reg) { 1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1913 FuncInfo->setSRetReturnReg(Reg); 1914 } 1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1917 } 1918 1919 unsigned StackSize = CCInfo.getNextStackOffset(); 1920 // Align stack specially for tail calls. 1921 if (FuncIsMadeTailCallSafe(CallConv, 1922 MF.getTarget().Options.GuaranteedTailCallOpt)) 1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1924 1925 // If the function takes variable number of arguments, make a frame index for 1926 // the start of the first vararg value... for expansion of llvm.va_start. 1927 if (isVarArg) { 1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1929 CallConv != CallingConv::X86_ThisCall)) { 1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1931 } 1932 if (Is64Bit) { 1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1934 1935 // FIXME: We should really autogenerate these arrays 1936 static const uint16_t GPR64ArgRegsWin64[] = { 1937 X86::RCX, X86::RDX, X86::R8, X86::R9 1938 }; 1939 static const uint16_t GPR64ArgRegs64Bit[] = { 1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1941 }; 1942 static const uint16_t XMMArgRegs64Bit[] = { 1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1945 }; 1946 const uint16_t *GPR64ArgRegs; 1947 unsigned NumXMMRegs = 0; 1948 1949 if (IsWin64) { 1950 // The XMM registers which might contain var arg parameters are shadowed 1951 // in their paired GPR. So we only need to save the GPR to their home 1952 // slots. 1953 TotalNumIntRegs = 4; 1954 GPR64ArgRegs = GPR64ArgRegsWin64; 1955 } else { 1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1957 GPR64ArgRegs = GPR64ArgRegs64Bit; 1958 1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1960 TotalNumXMMRegs); 1961 } 1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1963 TotalNumIntRegs); 1964 1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1967 "SSE register cannot be used when SSE is disabled!"); 1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1969 NoImplicitFloatOps) && 1970 "SSE register cannot be used when SSE is disabled!"); 1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1972 !Subtarget->hasSSE1()) 1973 // Kernel mode asks for SSE to be disabled, so don't push them 1974 // on the stack. 1975 TotalNumXMMRegs = 0; 1976 1977 if (IsWin64) { 1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1979 // Get to the caller-allocated home save location. Add 8 to account 1980 // for the return address. 1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1982 FuncInfo->setRegSaveFrameIndex( 1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1984 // Fixup to set vararg frame on shadow area (4 x i64). 1985 if (NumIntRegs < 4) 1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1987 } else { 1988 // For X86-64, if there are vararg parameters that are passed via 1989 // registers, then we must store them to their spots on the stack so 1990 // they may be loaded by deferencing the result of va_next. 1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1993 FuncInfo->setRegSaveFrameIndex( 1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1995 false)); 1996 } 1997 1998 // Store the integer parameter registers. 1999 SmallVector<SDValue, 8> MemOps; 2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2001 getPointerTy()); 2002 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2005 DAG.getIntPtrConstant(Offset)); 2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2007 X86::GR64RegisterClass); 2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2009 SDValue Store = 2010 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2011 MachinePointerInfo::getFixedStack( 2012 FuncInfo->getRegSaveFrameIndex(), Offset), 2013 false, false, 0); 2014 MemOps.push_back(Store); 2015 Offset += 8; 2016 } 2017 2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2019 // Now store the XMM (fp + vector) parameter registers. 2020 SmallVector<SDValue, 11> SaveXMMOps; 2021 SaveXMMOps.push_back(Chain); 2022 2023 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2025 SaveXMMOps.push_back(ALVal); 2026 2027 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2028 FuncInfo->getRegSaveFrameIndex())); 2029 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2030 FuncInfo->getVarArgsFPOffset())); 2031 2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2034 X86::VR128RegisterClass); 2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2036 SaveXMMOps.push_back(Val); 2037 } 2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2039 MVT::Other, 2040 &SaveXMMOps[0], SaveXMMOps.size())); 2041 } 2042 2043 if (!MemOps.empty()) 2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2045 &MemOps[0], MemOps.size()); 2046 } 2047 } 2048 2049 // Some CCs need callee pop. 2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2051 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2053 } else { 2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2055 // If this is an sret function, the return should pop the hidden pointer. 2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2057 ArgsAreStructReturn(Ins)) 2058 FuncInfo->setBytesToPopOnReturn(4); 2059 } 2060 2061 if (!Is64Bit) { 2062 // RegSaveFrameIndex is X86-64 only. 2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2064 if (CallConv == CallingConv::X86_FastCall || 2065 CallConv == CallingConv::X86_ThisCall) 2066 // fastcc functions can't have varargs. 2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2068 } 2069 2070 FuncInfo->setArgumentStackSize(StackSize); 2071 2072 return Chain; 2073} 2074 2075SDValue 2076X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2077 SDValue StackPtr, SDValue Arg, 2078 DebugLoc dl, SelectionDAG &DAG, 2079 const CCValAssign &VA, 2080 ISD::ArgFlagsTy Flags) const { 2081 unsigned LocMemOffset = VA.getLocMemOffset(); 2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2084 if (Flags.isByVal()) 2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2086 2087 return DAG.getStore(Chain, dl, Arg, PtrOff, 2088 MachinePointerInfo::getStack(LocMemOffset), 2089 false, false, 0); 2090} 2091 2092/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2093/// optimization is performed and it is required. 2094SDValue 2095X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2096 SDValue &OutRetAddr, SDValue Chain, 2097 bool IsTailCall, bool Is64Bit, 2098 int FPDiff, DebugLoc dl) const { 2099 // Adjust the Return address stack slot. 2100 EVT VT = getPointerTy(); 2101 OutRetAddr = getReturnAddressFrameIndex(DAG); 2102 2103 // Load the "old" Return address. 2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2105 false, false, false, 0); 2106 return SDValue(OutRetAddr.getNode(), 1); 2107} 2108 2109/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2110/// optimization is performed and it is required (FPDiff!=0). 2111static SDValue 2112EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2113 SDValue Chain, SDValue RetAddrFrIdx, 2114 bool Is64Bit, int FPDiff, DebugLoc dl) { 2115 // Store the return address to the appropriate stack slot. 2116 if (!FPDiff) return Chain; 2117 // Calculate the new stack slot for the return address. 2118 int SlotSize = Is64Bit ? 8 : 4; 2119 int NewReturnAddrFI = 2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2125 false, false, 0); 2126 return Chain; 2127} 2128 2129SDValue 2130X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2131 CallingConv::ID CallConv, bool isVarArg, 2132 bool doesNotRet, bool &isTailCall, 2133 const SmallVectorImpl<ISD::OutputArg> &Outs, 2134 const SmallVectorImpl<SDValue> &OutVals, 2135 const SmallVectorImpl<ISD::InputArg> &Ins, 2136 DebugLoc dl, SelectionDAG &DAG, 2137 SmallVectorImpl<SDValue> &InVals) const { 2138 MachineFunction &MF = DAG.getMachineFunction(); 2139 bool Is64Bit = Subtarget->is64Bit(); 2140 bool IsWin64 = Subtarget->isTargetWin64(); 2141 bool IsWindows = Subtarget->isTargetWindows(); 2142 bool IsStructRet = CallIsStructReturn(Outs); 2143 bool IsSibcall = false; 2144 2145 if (MF.getTarget().Options.DisableTailCalls) 2146 isTailCall = false; 2147 2148 if (isTailCall) { 2149 // Check if it's really possible to do a tail call. 2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2152 Outs, OutVals, Ins, DAG); 2153 2154 // Sibcalls are automatically detected tailcalls which do not require 2155 // ABI changes. 2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2157 IsSibcall = true; 2158 2159 if (isTailCall) 2160 ++NumTailCalls; 2161 } 2162 2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2164 "Var args not supported with calling convention fastcc or ghc"); 2165 2166 // Analyze operands of the call, assigning locations to each operand. 2167 SmallVector<CCValAssign, 16> ArgLocs; 2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2169 ArgLocs, *DAG.getContext()); 2170 2171 // Allocate shadow area for Win64 2172 if (IsWin64) { 2173 CCInfo.AllocateStack(32, 8); 2174 } 2175 2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2177 2178 // Get a count of how many bytes are to be pushed on the stack. 2179 unsigned NumBytes = CCInfo.getNextStackOffset(); 2180 if (IsSibcall) 2181 // This is a sibcall. The memory operands are available in caller's 2182 // own caller's stack. 2183 NumBytes = 0; 2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2185 IsTailCallConvention(CallConv)) 2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2187 2188 int FPDiff = 0; 2189 if (isTailCall && !IsSibcall) { 2190 // Lower arguments at fp - stackoffset + fpdiff. 2191 unsigned NumBytesCallerPushed = 2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2193 FPDiff = NumBytesCallerPushed - NumBytes; 2194 2195 // Set the delta of movement of the returnaddr stackslot. 2196 // But only set if delta is greater than previous delta. 2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2199 } 2200 2201 if (!IsSibcall) 2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2203 2204 SDValue RetAddrFrIdx; 2205 // Load return address for tail calls. 2206 if (isTailCall && FPDiff) 2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2208 Is64Bit, FPDiff, dl); 2209 2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2211 SmallVector<SDValue, 8> MemOpChains; 2212 SDValue StackPtr; 2213 2214 // Walk the register/memloc assignments, inserting copies/loads. In the case 2215 // of tail call optimization arguments are handle later. 2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2217 CCValAssign &VA = ArgLocs[i]; 2218 EVT RegVT = VA.getLocVT(); 2219 SDValue Arg = OutVals[i]; 2220 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2221 bool isByVal = Flags.isByVal(); 2222 2223 // Promote the value if needed. 2224 switch (VA.getLocInfo()) { 2225 default: llvm_unreachable("Unknown loc info!"); 2226 case CCValAssign::Full: break; 2227 case CCValAssign::SExt: 2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2229 break; 2230 case CCValAssign::ZExt: 2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2232 break; 2233 case CCValAssign::AExt: 2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2235 // Special case: passing MMX values in XMM registers. 2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2239 } else 2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2241 break; 2242 case CCValAssign::BCvt: 2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2244 break; 2245 case CCValAssign::Indirect: { 2246 // Store the argument. 2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2250 MachinePointerInfo::getFixedStack(FI), 2251 false, false, 0); 2252 Arg = SpillSlot; 2253 break; 2254 } 2255 } 2256 2257 if (VA.isRegLoc()) { 2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2259 if (isVarArg && IsWin64) { 2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2261 // shadow reg if callee is a varargs function. 2262 unsigned ShadowReg = 0; 2263 switch (VA.getLocReg()) { 2264 case X86::XMM0: ShadowReg = X86::RCX; break; 2265 case X86::XMM1: ShadowReg = X86::RDX; break; 2266 case X86::XMM2: ShadowReg = X86::R8; break; 2267 case X86::XMM3: ShadowReg = X86::R9; break; 2268 } 2269 if (ShadowReg) 2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2271 } 2272 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2273 assert(VA.isMemLoc()); 2274 if (StackPtr.getNode() == 0) 2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2277 dl, DAG, VA, Flags)); 2278 } 2279 } 2280 2281 if (!MemOpChains.empty()) 2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2283 &MemOpChains[0], MemOpChains.size()); 2284 2285 // Build a sequence of copy-to-reg nodes chained together with token chain 2286 // and flag operands which copy the outgoing args into registers. 2287 SDValue InFlag; 2288 // Tail call byval lowering might overwrite argument registers so in case of 2289 // tail call optimization the copies to registers are lowered later. 2290 if (!isTailCall) 2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2293 RegsToPass[i].second, InFlag); 2294 InFlag = Chain.getValue(1); 2295 } 2296 2297 if (Subtarget->isPICStyleGOT()) { 2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2299 // GOT pointer. 2300 if (!isTailCall) { 2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2302 DAG.getNode(X86ISD::GlobalBaseReg, 2303 DebugLoc(), getPointerTy()), 2304 InFlag); 2305 InFlag = Chain.getValue(1); 2306 } else { 2307 // If we are tail calling and generating PIC/GOT style code load the 2308 // address of the callee into ECX. The value in ecx is used as target of 2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2310 // for tail calls on PIC/GOT architectures. Normally we would just put the 2311 // address of GOT into ebx and then call target@PLT. But for tail calls 2312 // ebx would be restored (since ebx is callee saved) before jumping to the 2313 // target@PLT. 2314 2315 // Note: The actual moving to ECX is done further down. 2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2317 if (G && !G->getGlobal()->hasHiddenVisibility() && 2318 !G->getGlobal()->hasProtectedVisibility()) 2319 Callee = LowerGlobalAddress(Callee, DAG); 2320 else if (isa<ExternalSymbolSDNode>(Callee)) 2321 Callee = LowerExternalSymbol(Callee, DAG); 2322 } 2323 } 2324 2325 if (Is64Bit && isVarArg && !IsWin64) { 2326 // From AMD64 ABI document: 2327 // For calls that may call functions that use varargs or stdargs 2328 // (prototype-less calls or calls to functions containing ellipsis (...) in 2329 // the declaration) %al is used as hidden argument to specify the number 2330 // of SSE registers used. The contents of %al do not need to match exactly 2331 // the number of registers, but must be an ubound on the number of SSE 2332 // registers used and is in the range 0 - 8 inclusive. 2333 2334 // Count the number of XMM registers allocated. 2335 static const uint16_t XMMArgRegs[] = { 2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2338 }; 2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2340 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2341 && "SSE registers cannot be used when SSE is disabled"); 2342 2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2345 InFlag = Chain.getValue(1); 2346 } 2347 2348 2349 // For tail calls lower the arguments to the 'real' stack slot. 2350 if (isTailCall) { 2351 // Force all the incoming stack arguments to be loaded from the stack 2352 // before any new outgoing arguments are stored to the stack, because the 2353 // outgoing stack slots may alias the incoming argument stack slots, and 2354 // the alias isn't otherwise explicit. This is slightly more conservative 2355 // than necessary, because it means that each store effectively depends 2356 // on every argument instead of just those arguments it would clobber. 2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2358 2359 SmallVector<SDValue, 8> MemOpChains2; 2360 SDValue FIN; 2361 int FI = 0; 2362 // Do not flag preceding copytoreg stuff together with the following stuff. 2363 InFlag = SDValue(); 2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2366 CCValAssign &VA = ArgLocs[i]; 2367 if (VA.isRegLoc()) 2368 continue; 2369 assert(VA.isMemLoc()); 2370 SDValue Arg = OutVals[i]; 2371 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2372 // Create frame index. 2373 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2376 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2377 2378 if (Flags.isByVal()) { 2379 // Copy relative to framepointer. 2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2381 if (StackPtr.getNode() == 0) 2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2383 getPointerTy()); 2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2385 2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2387 ArgChain, 2388 Flags, DAG, dl)); 2389 } else { 2390 // Store relative to framepointer. 2391 MemOpChains2.push_back( 2392 DAG.getStore(ArgChain, dl, Arg, FIN, 2393 MachinePointerInfo::getFixedStack(FI), 2394 false, false, 0)); 2395 } 2396 } 2397 } 2398 2399 if (!MemOpChains2.empty()) 2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2401 &MemOpChains2[0], MemOpChains2.size()); 2402 2403 // Copy arguments to their registers. 2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2406 RegsToPass[i].second, InFlag); 2407 InFlag = Chain.getValue(1); 2408 } 2409 InFlag =SDValue(); 2410 2411 // Store the return address to the appropriate stack slot. 2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2413 FPDiff, dl); 2414 } 2415 2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2418 // In the 64-bit large code model, we have to make all calls 2419 // through a register, since the call instruction's 32-bit 2420 // pc-relative offset may not be large enough to hold the whole 2421 // address. 2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2423 // If the callee is a GlobalAddress node (quite common, every direct call 2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2425 // it. 2426 2427 // We should use extra load for direct calls to dllimported functions in 2428 // non-JIT mode. 2429 const GlobalValue *GV = G->getGlobal(); 2430 if (!GV->hasDLLImportLinkage()) { 2431 unsigned char OpFlags = 0; 2432 bool ExtraLoad = false; 2433 unsigned WrapperKind = ISD::DELETED_NODE; 2434 2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2436 // external symbols most go through the PLT in PIC mode. If the symbol 2437 // has hidden or protected visibility, or if it is static or local, then 2438 // we don't need to use the PLT - we can directly call it. 2439 if (Subtarget->isTargetELF() && 2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2442 OpFlags = X86II::MO_PLT; 2443 } else if (Subtarget->isPICStyleStubAny() && 2444 (GV->isDeclaration() || GV->isWeakForLinker()) && 2445 (!Subtarget->getTargetTriple().isMacOSX() || 2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2447 // PC-relative references to external symbols should go through $stub, 2448 // unless we're building with the leopard linker or later, which 2449 // automatically synthesizes these stubs. 2450 OpFlags = X86II::MO_DARWIN_STUB; 2451 } else if (Subtarget->isPICStyleRIPRel() && 2452 isa<Function>(GV) && 2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2454 // If the function is marked as non-lazy, generate an indirect call 2455 // which loads from the GOT directly. This avoids runtime overhead 2456 // at the cost of eager binding (and one extra byte of encoding). 2457 OpFlags = X86II::MO_GOTPCREL; 2458 WrapperKind = X86ISD::WrapperRIP; 2459 ExtraLoad = true; 2460 } 2461 2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2463 G->getOffset(), OpFlags); 2464 2465 // Add a wrapper if needed. 2466 if (WrapperKind != ISD::DELETED_NODE) 2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2468 // Add extra indirection if needed. 2469 if (ExtraLoad) 2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2471 MachinePointerInfo::getGOT(), 2472 false, false, false, 0); 2473 } 2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2475 unsigned char OpFlags = 0; 2476 2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2478 // external symbols should go through the PLT. 2479 if (Subtarget->isTargetELF() && 2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2481 OpFlags = X86II::MO_PLT; 2482 } else if (Subtarget->isPICStyleStubAny() && 2483 (!Subtarget->getTargetTriple().isMacOSX() || 2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2485 // PC-relative references to external symbols should go through $stub, 2486 // unless we're building with the leopard linker or later, which 2487 // automatically synthesizes these stubs. 2488 OpFlags = X86II::MO_DARWIN_STUB; 2489 } 2490 2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2492 OpFlags); 2493 } 2494 2495 // Returns a chain & a flag for retval copy to use. 2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2497 SmallVector<SDValue, 8> Ops; 2498 2499 if (!IsSibcall && isTailCall) { 2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2501 DAG.getIntPtrConstant(0, true), InFlag); 2502 InFlag = Chain.getValue(1); 2503 } 2504 2505 Ops.push_back(Chain); 2506 Ops.push_back(Callee); 2507 2508 if (isTailCall) 2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2510 2511 // Add argument registers to the end of the list so that they are known live 2512 // into the call. 2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2515 RegsToPass[i].second.getValueType())); 2516 2517 // Add an implicit use GOT pointer in EBX. 2518 if (!isTailCall && Subtarget->isPICStyleGOT()) 2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2520 2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2522 if (Is64Bit && isVarArg && !IsWin64) 2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2524 2525 // Add a register mask operand representing the call-preserved registers. 2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2528 assert(Mask && "Missing call preserved mask for calling convention"); 2529 Ops.push_back(DAG.getRegisterMask(Mask)); 2530 2531 if (InFlag.getNode()) 2532 Ops.push_back(InFlag); 2533 2534 if (isTailCall) { 2535 // We used to do: 2536 //// If this is the first return lowered for this function, add the regs 2537 //// to the liveout set for the function. 2538 // This isn't right, although it's probably harmless on x86; liveouts 2539 // should be computed from returns not tail calls. Consider a void 2540 // function making a tail call to a function returning int. 2541 return DAG.getNode(X86ISD::TC_RETURN, dl, 2542 NodeTys, &Ops[0], Ops.size()); 2543 } 2544 2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2546 InFlag = Chain.getValue(1); 2547 2548 // Create the CALLSEQ_END node. 2549 unsigned NumBytesForCalleeToPush; 2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2551 getTargetMachine().Options.GuaranteedTailCallOpt)) 2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2554 IsStructRet) 2555 // If this is a call to a struct-return function, the callee 2556 // pops the hidden struct pointer, so we have to push it back. 2557 // This is common for Darwin/X86, Linux & Mingw32 targets. 2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2559 NumBytesForCalleeToPush = 4; 2560 else 2561 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2562 2563 // Returns a flag for retval copy to use. 2564 if (!IsSibcall) { 2565 Chain = DAG.getCALLSEQ_END(Chain, 2566 DAG.getIntPtrConstant(NumBytes, true), 2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2568 true), 2569 InFlag); 2570 InFlag = Chain.getValue(1); 2571 } 2572 2573 // Handle result values, copying them out of physregs into vregs that we 2574 // return. 2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2576 Ins, dl, DAG, InVals); 2577} 2578 2579 2580//===----------------------------------------------------------------------===// 2581// Fast Calling Convention (tail call) implementation 2582//===----------------------------------------------------------------------===// 2583 2584// Like std call, callee cleans arguments, convention except that ECX is 2585// reserved for storing the tail called function address. Only 2 registers are 2586// free for argument passing (inreg). Tail call optimization is performed 2587// provided: 2588// * tailcallopt is enabled 2589// * caller/callee are fastcc 2590// On X86_64 architecture with GOT-style position independent code only local 2591// (within module) calls are supported at the moment. 2592// To keep the stack aligned according to platform abi the function 2593// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2594// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2595// If a tail called function callee has more arguments than the caller the 2596// caller needs to make sure that there is room to move the RETADDR to. This is 2597// achieved by reserving an area the size of the argument delta right after the 2598// original REtADDR, but before the saved framepointer or the spilled registers 2599// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2600// stack layout: 2601// arg1 2602// arg2 2603// RETADDR 2604// [ new RETADDR 2605// move area ] 2606// (possible EBP) 2607// ESI 2608// EDI 2609// local1 .. 2610 2611/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2612/// for a 16 byte align requirement. 2613unsigned 2614X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2615 SelectionDAG& DAG) const { 2616 MachineFunction &MF = DAG.getMachineFunction(); 2617 const TargetMachine &TM = MF.getTarget(); 2618 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2619 unsigned StackAlignment = TFI.getStackAlignment(); 2620 uint64_t AlignMask = StackAlignment - 1; 2621 int64_t Offset = StackSize; 2622 uint64_t SlotSize = TD->getPointerSize(); 2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2624 // Number smaller than 12 so just add the difference. 2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2626 } else { 2627 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2628 Offset = ((~AlignMask) & Offset) + StackAlignment + 2629 (StackAlignment-SlotSize); 2630 } 2631 return Offset; 2632} 2633 2634/// MatchingStackOffset - Return true if the given stack call argument is 2635/// already available in the same position (relatively) of the caller's 2636/// incoming argument stack. 2637static 2638bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2640 const X86InstrInfo *TII) { 2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2642 int FI = INT_MAX; 2643 if (Arg.getOpcode() == ISD::CopyFromReg) { 2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2645 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2646 return false; 2647 MachineInstr *Def = MRI->getVRegDef(VR); 2648 if (!Def) 2649 return false; 2650 if (!Flags.isByVal()) { 2651 if (!TII->isLoadFromStackSlot(Def, FI)) 2652 return false; 2653 } else { 2654 unsigned Opcode = Def->getOpcode(); 2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2656 Def->getOperand(1).isFI()) { 2657 FI = Def->getOperand(1).getIndex(); 2658 Bytes = Flags.getByValSize(); 2659 } else 2660 return false; 2661 } 2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2663 if (Flags.isByVal()) 2664 // ByVal argument is passed in as a pointer but it's now being 2665 // dereferenced. e.g. 2666 // define @foo(%struct.X* %A) { 2667 // tail call @bar(%struct.X* byval %A) 2668 // } 2669 return false; 2670 SDValue Ptr = Ld->getBasePtr(); 2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2672 if (!FINode) 2673 return false; 2674 FI = FINode->getIndex(); 2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2677 FI = FINode->getIndex(); 2678 Bytes = Flags.getByValSize(); 2679 } else 2680 return false; 2681 2682 assert(FI != INT_MAX); 2683 if (!MFI->isFixedObjectIndex(FI)) 2684 return false; 2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2686} 2687 2688/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2689/// for tail call optimization. Targets which want to do tail call 2690/// optimization should implement this function. 2691bool 2692X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2693 CallingConv::ID CalleeCC, 2694 bool isVarArg, 2695 bool isCalleeStructRet, 2696 bool isCallerStructRet, 2697 const SmallVectorImpl<ISD::OutputArg> &Outs, 2698 const SmallVectorImpl<SDValue> &OutVals, 2699 const SmallVectorImpl<ISD::InputArg> &Ins, 2700 SelectionDAG& DAG) const { 2701 if (!IsTailCallConvention(CalleeCC) && 2702 CalleeCC != CallingConv::C) 2703 return false; 2704 2705 // If -tailcallopt is specified, make fastcc functions tail-callable. 2706 const MachineFunction &MF = DAG.getMachineFunction(); 2707 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2708 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2709 bool CCMatch = CallerCC == CalleeCC; 2710 2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2712 if (IsTailCallConvention(CalleeCC) && CCMatch) 2713 return true; 2714 return false; 2715 } 2716 2717 // Look for obvious safe cases to perform tail call optimization that do not 2718 // require ABI changes. This is what gcc calls sibcall. 2719 2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2721 // emit a special epilogue. 2722 if (RegInfo->needsStackRealignment(MF)) 2723 return false; 2724 2725 // Also avoid sibcall optimization if either caller or callee uses struct 2726 // return semantics. 2727 if (isCalleeStructRet || isCallerStructRet) 2728 return false; 2729 2730 // An stdcall caller is expected to clean up its arguments; the callee 2731 // isn't going to do that. 2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2733 return false; 2734 2735 // Do not sibcall optimize vararg calls unless all arguments are passed via 2736 // registers. 2737 if (isVarArg && !Outs.empty()) { 2738 2739 // Optimizing for varargs on Win64 is unlikely to be safe without 2740 // additional testing. 2741 if (Subtarget->isTargetWin64()) 2742 return false; 2743 2744 SmallVector<CCValAssign, 16> ArgLocs; 2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2746 getTargetMachine(), ArgLocs, *DAG.getContext()); 2747 2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2750 if (!ArgLocs[i].isRegLoc()) 2751 return false; 2752 } 2753 2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2755 // stack. Therefore, if it's not used by the call it is not safe to optimize 2756 // this into a sibcall. 2757 bool Unused = false; 2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2759 if (!Ins[i].Used) { 2760 Unused = true; 2761 break; 2762 } 2763 } 2764 if (Unused) { 2765 SmallVector<CCValAssign, 16> RVLocs; 2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2767 getTargetMachine(), RVLocs, *DAG.getContext()); 2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2770 CCValAssign &VA = RVLocs[i]; 2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2772 return false; 2773 } 2774 } 2775 2776 // If the calling conventions do not match, then we'd better make sure the 2777 // results are returned in the same way as what the caller expects. 2778 if (!CCMatch) { 2779 SmallVector<CCValAssign, 16> RVLocs1; 2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2781 getTargetMachine(), RVLocs1, *DAG.getContext()); 2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2783 2784 SmallVector<CCValAssign, 16> RVLocs2; 2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2786 getTargetMachine(), RVLocs2, *DAG.getContext()); 2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2788 2789 if (RVLocs1.size() != RVLocs2.size()) 2790 return false; 2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2793 return false; 2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2795 return false; 2796 if (RVLocs1[i].isRegLoc()) { 2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2798 return false; 2799 } else { 2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2801 return false; 2802 } 2803 } 2804 } 2805 2806 // If the callee takes no arguments then go on to check the results of the 2807 // call. 2808 if (!Outs.empty()) { 2809 // Check if stack adjustment is needed. For now, do not do this if any 2810 // argument is passed on the stack. 2811 SmallVector<CCValAssign, 16> ArgLocs; 2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2813 getTargetMachine(), ArgLocs, *DAG.getContext()); 2814 2815 // Allocate shadow area for Win64 2816 if (Subtarget->isTargetWin64()) { 2817 CCInfo.AllocateStack(32, 8); 2818 } 2819 2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2821 if (CCInfo.getNextStackOffset()) { 2822 MachineFunction &MF = DAG.getMachineFunction(); 2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2824 return false; 2825 2826 // Check if the arguments are already laid out in the right way as 2827 // the caller's fixed stack objects. 2828 MachineFrameInfo *MFI = MF.getFrameInfo(); 2829 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2830 const X86InstrInfo *TII = 2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2833 CCValAssign &VA = ArgLocs[i]; 2834 SDValue Arg = OutVals[i]; 2835 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2836 if (VA.getLocInfo() == CCValAssign::Indirect) 2837 return false; 2838 if (!VA.isRegLoc()) { 2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2840 MFI, MRI, TII)) 2841 return false; 2842 } 2843 } 2844 } 2845 2846 // If the tailcall address may be in a register, then make sure it's 2847 // possible to register allocate for it. In 32-bit, the call address can 2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2849 // callee-saved registers are restored. These happen to be the same 2850 // registers used to pass 'inreg' arguments so watch out for those. 2851 if (!Subtarget->is64Bit() && 2852 !isa<GlobalAddressSDNode>(Callee) && 2853 !isa<ExternalSymbolSDNode>(Callee)) { 2854 unsigned NumInRegs = 0; 2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2856 CCValAssign &VA = ArgLocs[i]; 2857 if (!VA.isRegLoc()) 2858 continue; 2859 unsigned Reg = VA.getLocReg(); 2860 switch (Reg) { 2861 default: break; 2862 case X86::EAX: case X86::EDX: case X86::ECX: 2863 if (++NumInRegs == 3) 2864 return false; 2865 break; 2866 } 2867 } 2868 } 2869 } 2870 2871 return true; 2872} 2873 2874FastISel * 2875X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2876 return X86::createFastISel(funcInfo); 2877} 2878 2879 2880//===----------------------------------------------------------------------===// 2881// Other Lowering Hooks 2882//===----------------------------------------------------------------------===// 2883 2884static bool MayFoldLoad(SDValue Op) { 2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2886} 2887 2888static bool MayFoldIntoStore(SDValue Op) { 2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2890} 2891 2892static bool isTargetShuffle(unsigned Opcode) { 2893 switch(Opcode) { 2894 default: return false; 2895 case X86ISD::PSHUFD: 2896 case X86ISD::PSHUFHW: 2897 case X86ISD::PSHUFLW: 2898 case X86ISD::SHUFP: 2899 case X86ISD::PALIGN: 2900 case X86ISD::MOVLHPS: 2901 case X86ISD::MOVLHPD: 2902 case X86ISD::MOVHLPS: 2903 case X86ISD::MOVLPS: 2904 case X86ISD::MOVLPD: 2905 case X86ISD::MOVSHDUP: 2906 case X86ISD::MOVSLDUP: 2907 case X86ISD::MOVDDUP: 2908 case X86ISD::MOVSS: 2909 case X86ISD::MOVSD: 2910 case X86ISD::UNPCKL: 2911 case X86ISD::UNPCKH: 2912 case X86ISD::VPERMILP: 2913 case X86ISD::VPERM2X128: 2914 return true; 2915 } 2916} 2917 2918static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2919 SDValue V1, SelectionDAG &DAG) { 2920 switch(Opc) { 2921 default: llvm_unreachable("Unknown x86 shuffle node"); 2922 case X86ISD::MOVSHDUP: 2923 case X86ISD::MOVSLDUP: 2924 case X86ISD::MOVDDUP: 2925 return DAG.getNode(Opc, dl, VT, V1); 2926 } 2927} 2928 2929static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2930 SDValue V1, unsigned TargetMask, 2931 SelectionDAG &DAG) { 2932 switch(Opc) { 2933 default: llvm_unreachable("Unknown x86 shuffle node"); 2934 case X86ISD::PSHUFD: 2935 case X86ISD::PSHUFHW: 2936 case X86ISD::PSHUFLW: 2937 case X86ISD::VPERMILP: 2938 case X86ISD::VPERMI: 2939 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2940 } 2941} 2942 2943static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2944 SDValue V1, SDValue V2, unsigned TargetMask, 2945 SelectionDAG &DAG) { 2946 switch(Opc) { 2947 default: llvm_unreachable("Unknown x86 shuffle node"); 2948 case X86ISD::PALIGN: 2949 case X86ISD::SHUFP: 2950 case X86ISD::VPERM2X128: 2951 return DAG.getNode(Opc, dl, VT, V1, V2, 2952 DAG.getConstant(TargetMask, MVT::i8)); 2953 } 2954} 2955 2956static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2957 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2958 switch(Opc) { 2959 default: llvm_unreachable("Unknown x86 shuffle node"); 2960 case X86ISD::MOVLHPS: 2961 case X86ISD::MOVLHPD: 2962 case X86ISD::MOVHLPS: 2963 case X86ISD::MOVLPS: 2964 case X86ISD::MOVLPD: 2965 case X86ISD::MOVSS: 2966 case X86ISD::MOVSD: 2967 case X86ISD::UNPCKL: 2968 case X86ISD::UNPCKH: 2969 return DAG.getNode(Opc, dl, VT, V1, V2); 2970 } 2971} 2972 2973SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2974 MachineFunction &MF = DAG.getMachineFunction(); 2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2976 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2977 2978 if (ReturnAddrIndex == 0) { 2979 // Set up a frame object for the return address. 2980 uint64_t SlotSize = TD->getPointerSize(); 2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2982 false); 2983 FuncInfo->setRAIndex(ReturnAddrIndex); 2984 } 2985 2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2987} 2988 2989 2990bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2991 bool hasSymbolicDisplacement) { 2992 // Offset should fit into 32 bit immediate field. 2993 if (!isInt<32>(Offset)) 2994 return false; 2995 2996 // If we don't have a symbolic displacement - we don't have any extra 2997 // restrictions. 2998 if (!hasSymbolicDisplacement) 2999 return true; 3000 3001 // FIXME: Some tweaks might be needed for medium code model. 3002 if (M != CodeModel::Small && M != CodeModel::Kernel) 3003 return false; 3004 3005 // For small code model we assume that latest object is 16MB before end of 31 3006 // bits boundary. We may also accept pretty large negative constants knowing 3007 // that all objects are in the positive half of address space. 3008 if (M == CodeModel::Small && Offset < 16*1024*1024) 3009 return true; 3010 3011 // For kernel code model we know that all object resist in the negative half 3012 // of 32bits address space. We may not accept negative offsets, since they may 3013 // be just off and we may accept pretty large positive ones. 3014 if (M == CodeModel::Kernel && Offset > 0) 3015 return true; 3016 3017 return false; 3018} 3019 3020/// isCalleePop - Determines whether the callee is required to pop its 3021/// own arguments. Callee pop is necessary to support tail calls. 3022bool X86::isCalleePop(CallingConv::ID CallingConv, 3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3024 if (IsVarArg) 3025 return false; 3026 3027 switch (CallingConv) { 3028 default: 3029 return false; 3030 case CallingConv::X86_StdCall: 3031 return !is64Bit; 3032 case CallingConv::X86_FastCall: 3033 return !is64Bit; 3034 case CallingConv::X86_ThisCall: 3035 return !is64Bit; 3036 case CallingConv::Fast: 3037 return TailCallOpt; 3038 case CallingConv::GHC: 3039 return TailCallOpt; 3040 } 3041} 3042 3043/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3044/// specific condition code, returning the condition code and the LHS/RHS of the 3045/// comparison to make. 3046static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3048 if (!isFP) { 3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3051 // X > -1 -> X == 0, jump !sign. 3052 RHS = DAG.getConstant(0, RHS.getValueType()); 3053 return X86::COND_NS; 3054 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3055 // X < 0 -> X == 0, jump on sign. 3056 return X86::COND_S; 3057 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3058 // X < 1 -> X <= 0 3059 RHS = DAG.getConstant(0, RHS.getValueType()); 3060 return X86::COND_LE; 3061 } 3062 } 3063 3064 switch (SetCCOpcode) { 3065 default: llvm_unreachable("Invalid integer condition!"); 3066 case ISD::SETEQ: return X86::COND_E; 3067 case ISD::SETGT: return X86::COND_G; 3068 case ISD::SETGE: return X86::COND_GE; 3069 case ISD::SETLT: return X86::COND_L; 3070 case ISD::SETLE: return X86::COND_LE; 3071 case ISD::SETNE: return X86::COND_NE; 3072 case ISD::SETULT: return X86::COND_B; 3073 case ISD::SETUGT: return X86::COND_A; 3074 case ISD::SETULE: return X86::COND_BE; 3075 case ISD::SETUGE: return X86::COND_AE; 3076 } 3077 } 3078 3079 // First determine if it is required or is profitable to flip the operands. 3080 3081 // If LHS is a foldable load, but RHS is not, flip the condition. 3082 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3083 !ISD::isNON_EXTLoad(RHS.getNode())) { 3084 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3085 std::swap(LHS, RHS); 3086 } 3087 3088 switch (SetCCOpcode) { 3089 default: break; 3090 case ISD::SETOLT: 3091 case ISD::SETOLE: 3092 case ISD::SETUGT: 3093 case ISD::SETUGE: 3094 std::swap(LHS, RHS); 3095 break; 3096 } 3097 3098 // On a floating point condition, the flags are set as follows: 3099 // ZF PF CF op 3100 // 0 | 0 | 0 | X > Y 3101 // 0 | 0 | 1 | X < Y 3102 // 1 | 0 | 0 | X == Y 3103 // 1 | 1 | 1 | unordered 3104 switch (SetCCOpcode) { 3105 default: llvm_unreachable("Condcode should be pre-legalized away"); 3106 case ISD::SETUEQ: 3107 case ISD::SETEQ: return X86::COND_E; 3108 case ISD::SETOLT: // flipped 3109 case ISD::SETOGT: 3110 case ISD::SETGT: return X86::COND_A; 3111 case ISD::SETOLE: // flipped 3112 case ISD::SETOGE: 3113 case ISD::SETGE: return X86::COND_AE; 3114 case ISD::SETUGT: // flipped 3115 case ISD::SETULT: 3116 case ISD::SETLT: return X86::COND_B; 3117 case ISD::SETUGE: // flipped 3118 case ISD::SETULE: 3119 case ISD::SETLE: return X86::COND_BE; 3120 case ISD::SETONE: 3121 case ISD::SETNE: return X86::COND_NE; 3122 case ISD::SETUO: return X86::COND_P; 3123 case ISD::SETO: return X86::COND_NP; 3124 case ISD::SETOEQ: 3125 case ISD::SETUNE: return X86::COND_INVALID; 3126 } 3127} 3128 3129/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3130/// code. Current x86 isa includes the following FP cmov instructions: 3131/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3132static bool hasFPCMov(unsigned X86CC) { 3133 switch (X86CC) { 3134 default: 3135 return false; 3136 case X86::COND_B: 3137 case X86::COND_BE: 3138 case X86::COND_E: 3139 case X86::COND_P: 3140 case X86::COND_A: 3141 case X86::COND_AE: 3142 case X86::COND_NE: 3143 case X86::COND_NP: 3144 return true; 3145 } 3146} 3147 3148/// isFPImmLegal - Returns true if the target can instruction select the 3149/// specified FP immediate natively. If false, the legalizer will 3150/// materialize the FP immediate as a load from a constant pool. 3151bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3152 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3153 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3154 return true; 3155 } 3156 return false; 3157} 3158 3159/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3160/// the specified range (L, H]. 3161static bool isUndefOrInRange(int Val, int Low, int Hi) { 3162 return (Val < 0) || (Val >= Low && Val < Hi); 3163} 3164 3165/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3166/// specified value. 3167static bool isUndefOrEqual(int Val, int CmpVal) { 3168 if (Val < 0 || Val == CmpVal) 3169 return true; 3170 return false; 3171} 3172 3173/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3174/// from position Pos and ending in Pos+Size, falls within the specified 3175/// sequential range (L, L+Pos]. or is undef. 3176static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3177 int Pos, int Size, int Low) { 3178 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3179 if (!isUndefOrEqual(Mask[i], Low)) 3180 return false; 3181 return true; 3182} 3183 3184/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3185/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3186/// the second operand. 3187static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3188 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3189 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3190 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3191 return (Mask[0] < 2 && Mask[1] < 2); 3192 return false; 3193} 3194 3195/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3196/// is suitable for input to PSHUFHW. 3197static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3198 if (VT != MVT::v8i16) 3199 return false; 3200 3201 // Lower quadword copied in order or undef. 3202 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3203 return false; 3204 3205 // Upper quadword shuffled. 3206 for (unsigned i = 4; i != 8; ++i) 3207 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3208 return false; 3209 3210 return true; 3211} 3212 3213/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3214/// is suitable for input to PSHUFLW. 3215static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3216 if (VT != MVT::v8i16) 3217 return false; 3218 3219 // Upper quadword copied in order. 3220 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3221 return false; 3222 3223 // Lower quadword shuffled. 3224 for (unsigned i = 0; i != 4; ++i) 3225 if (Mask[i] >= 4) 3226 return false; 3227 3228 return true; 3229} 3230 3231/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3232/// is suitable for input to PALIGNR. 3233static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3234 const X86Subtarget *Subtarget) { 3235 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3236 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3237 return false; 3238 3239 unsigned NumElts = VT.getVectorNumElements(); 3240 unsigned NumLanes = VT.getSizeInBits()/128; 3241 unsigned NumLaneElts = NumElts/NumLanes; 3242 3243 // Do not handle 64-bit element shuffles with palignr. 3244 if (NumLaneElts == 2) 3245 return false; 3246 3247 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3248 unsigned i; 3249 for (i = 0; i != NumLaneElts; ++i) { 3250 if (Mask[i+l] >= 0) 3251 break; 3252 } 3253 3254 // Lane is all undef, go to next lane 3255 if (i == NumLaneElts) 3256 continue; 3257 3258 int Start = Mask[i+l]; 3259 3260 // Make sure its in this lane in one of the sources 3261 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3262 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3263 return false; 3264 3265 // If not lane 0, then we must match lane 0 3266 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3267 return false; 3268 3269 // Correct second source to be contiguous with first source 3270 if (Start >= (int)NumElts) 3271 Start -= NumElts - NumLaneElts; 3272 3273 // Make sure we're shifting in the right direction. 3274 if (Start <= (int)(i+l)) 3275 return false; 3276 3277 Start -= i; 3278 3279 // Check the rest of the elements to see if they are consecutive. 3280 for (++i; i != NumLaneElts; ++i) { 3281 int Idx = Mask[i+l]; 3282 3283 // Make sure its in this lane 3284 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3285 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3286 return false; 3287 3288 // If not lane 0, then we must match lane 0 3289 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3290 return false; 3291 3292 if (Idx >= (int)NumElts) 3293 Idx -= NumElts - NumLaneElts; 3294 3295 if (!isUndefOrEqual(Idx, Start+i)) 3296 return false; 3297 3298 } 3299 } 3300 3301 return true; 3302} 3303 3304/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3305/// the two vector operands have swapped position. 3306static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3307 unsigned NumElems) { 3308 for (unsigned i = 0; i != NumElems; ++i) { 3309 int idx = Mask[i]; 3310 if (idx < 0) 3311 continue; 3312 else if (idx < (int)NumElems) 3313 Mask[i] = idx + NumElems; 3314 else 3315 Mask[i] = idx - NumElems; 3316 } 3317} 3318 3319/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3320/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3321/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3322/// reverse of what x86 shuffles want. 3323static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3324 bool Commuted = false) { 3325 if (!HasAVX && VT.getSizeInBits() == 256) 3326 return false; 3327 3328 unsigned NumElems = VT.getVectorNumElements(); 3329 unsigned NumLanes = VT.getSizeInBits()/128; 3330 unsigned NumLaneElems = NumElems/NumLanes; 3331 3332 if (NumLaneElems != 2 && NumLaneElems != 4) 3333 return false; 3334 3335 // VSHUFPSY divides the resulting vector into 4 chunks. 3336 // The sources are also splitted into 4 chunks, and each destination 3337 // chunk must come from a different source chunk. 3338 // 3339 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3340 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3341 // 3342 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3343 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3344 // 3345 // VSHUFPDY divides the resulting vector into 4 chunks. 3346 // The sources are also splitted into 4 chunks, and each destination 3347 // chunk must come from a different source chunk. 3348 // 3349 // SRC1 => X3 X2 X1 X0 3350 // SRC2 => Y3 Y2 Y1 Y0 3351 // 3352 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3353 // 3354 unsigned HalfLaneElems = NumLaneElems/2; 3355 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3356 for (unsigned i = 0; i != NumLaneElems; ++i) { 3357 int Idx = Mask[i+l]; 3358 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3359 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3360 return false; 3361 // For VSHUFPSY, the mask of the second half must be the same as the 3362 // first but with the appropriate offsets. This works in the same way as 3363 // VPERMILPS works with masks. 3364 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3365 continue; 3366 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3367 return false; 3368 } 3369 } 3370 3371 return true; 3372} 3373 3374/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3375/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3376static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3377 unsigned NumElems = VT.getVectorNumElements(); 3378 3379 if (VT.getSizeInBits() != 128) 3380 return false; 3381 3382 if (NumElems != 4) 3383 return false; 3384 3385 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3386 return isUndefOrEqual(Mask[0], 6) && 3387 isUndefOrEqual(Mask[1], 7) && 3388 isUndefOrEqual(Mask[2], 2) && 3389 isUndefOrEqual(Mask[3], 3); 3390} 3391 3392/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3393/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3394/// <2, 3, 2, 3> 3395static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3396 unsigned NumElems = VT.getVectorNumElements(); 3397 3398 if (VT.getSizeInBits() != 128) 3399 return false; 3400 3401 if (NumElems != 4) 3402 return false; 3403 3404 return isUndefOrEqual(Mask[0], 2) && 3405 isUndefOrEqual(Mask[1], 3) && 3406 isUndefOrEqual(Mask[2], 2) && 3407 isUndefOrEqual(Mask[3], 3); 3408} 3409 3410/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3411/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3412static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3413 if (VT.getSizeInBits() != 128) 3414 return false; 3415 3416 unsigned NumElems = VT.getVectorNumElements(); 3417 3418 if (NumElems != 2 && NumElems != 4) 3419 return false; 3420 3421 for (unsigned i = 0; i != NumElems/2; ++i) 3422 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3423 return false; 3424 3425 for (unsigned i = NumElems/2; i != NumElems; ++i) 3426 if (!isUndefOrEqual(Mask[i], i)) 3427 return false; 3428 3429 return true; 3430} 3431 3432/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3433/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3434static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3435 unsigned NumElems = VT.getVectorNumElements(); 3436 3437 if ((NumElems != 2 && NumElems != 4) 3438 || VT.getSizeInBits() > 128) 3439 return false; 3440 3441 for (unsigned i = 0; i != NumElems/2; ++i) 3442 if (!isUndefOrEqual(Mask[i], i)) 3443 return false; 3444 3445 for (unsigned i = 0; i != NumElems/2; ++i) 3446 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems)) 3447 return false; 3448 3449 return true; 3450} 3451 3452/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3453/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3454static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3455 bool HasAVX2, bool V2IsSplat = false) { 3456 unsigned NumElts = VT.getVectorNumElements(); 3457 3458 assert((VT.is128BitVector() || VT.is256BitVector()) && 3459 "Unsupported vector type for unpckh"); 3460 3461 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3462 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3463 return false; 3464 3465 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3466 // independently on 128-bit lanes. 3467 unsigned NumLanes = VT.getSizeInBits()/128; 3468 unsigned NumLaneElts = NumElts/NumLanes; 3469 3470 for (unsigned l = 0; l != NumLanes; ++l) { 3471 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3472 i != (l+1)*NumLaneElts; 3473 i += 2, ++j) { 3474 int BitI = Mask[i]; 3475 int BitI1 = Mask[i+1]; 3476 if (!isUndefOrEqual(BitI, j)) 3477 return false; 3478 if (V2IsSplat) { 3479 if (!isUndefOrEqual(BitI1, NumElts)) 3480 return false; 3481 } else { 3482 if (!isUndefOrEqual(BitI1, j + NumElts)) 3483 return false; 3484 } 3485 } 3486 } 3487 3488 return true; 3489} 3490 3491/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3492/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3493static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3494 bool HasAVX2, bool V2IsSplat = false) { 3495 unsigned NumElts = VT.getVectorNumElements(); 3496 3497 assert((VT.is128BitVector() || VT.is256BitVector()) && 3498 "Unsupported vector type for unpckh"); 3499 3500 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3501 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3502 return false; 3503 3504 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3505 // independently on 128-bit lanes. 3506 unsigned NumLanes = VT.getSizeInBits()/128; 3507 unsigned NumLaneElts = NumElts/NumLanes; 3508 3509 for (unsigned l = 0; l != NumLanes; ++l) { 3510 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3511 i != (l+1)*NumLaneElts; i += 2, ++j) { 3512 int BitI = Mask[i]; 3513 int BitI1 = Mask[i+1]; 3514 if (!isUndefOrEqual(BitI, j)) 3515 return false; 3516 if (V2IsSplat) { 3517 if (isUndefOrEqual(BitI1, NumElts)) 3518 return false; 3519 } else { 3520 if (!isUndefOrEqual(BitI1, j+NumElts)) 3521 return false; 3522 } 3523 } 3524 } 3525 return true; 3526} 3527 3528/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3529/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3530/// <0, 0, 1, 1> 3531static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3532 bool HasAVX2) { 3533 unsigned NumElts = VT.getVectorNumElements(); 3534 3535 assert((VT.is128BitVector() || VT.is256BitVector()) && 3536 "Unsupported vector type for unpckh"); 3537 3538 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3539 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3540 return false; 3541 3542 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3543 // FIXME: Need a better way to get rid of this, there's no latency difference 3544 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3545 // the former later. We should also remove the "_undef" special mask. 3546 if (NumElts == 4 && VT.getSizeInBits() == 256) 3547 return false; 3548 3549 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3550 // independently on 128-bit lanes. 3551 unsigned NumLanes = VT.getSizeInBits()/128; 3552 unsigned NumLaneElts = NumElts/NumLanes; 3553 3554 for (unsigned l = 0; l != NumLanes; ++l) { 3555 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3556 i != (l+1)*NumLaneElts; 3557 i += 2, ++j) { 3558 int BitI = Mask[i]; 3559 int BitI1 = Mask[i+1]; 3560 3561 if (!isUndefOrEqual(BitI, j)) 3562 return false; 3563 if (!isUndefOrEqual(BitI1, j)) 3564 return false; 3565 } 3566 } 3567 3568 return true; 3569} 3570 3571/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3572/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3573/// <2, 2, 3, 3> 3574static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3575 unsigned NumElts = VT.getVectorNumElements(); 3576 3577 assert((VT.is128BitVector() || VT.is256BitVector()) && 3578 "Unsupported vector type for unpckh"); 3579 3580 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3581 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3582 return false; 3583 3584 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3585 // independently on 128-bit lanes. 3586 unsigned NumLanes = VT.getSizeInBits()/128; 3587 unsigned NumLaneElts = NumElts/NumLanes; 3588 3589 for (unsigned l = 0; l != NumLanes; ++l) { 3590 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3591 i != (l+1)*NumLaneElts; i += 2, ++j) { 3592 int BitI = Mask[i]; 3593 int BitI1 = Mask[i+1]; 3594 if (!isUndefOrEqual(BitI, j)) 3595 return false; 3596 if (!isUndefOrEqual(BitI1, j)) 3597 return false; 3598 } 3599 } 3600 return true; 3601} 3602 3603/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3604/// specifies a shuffle of elements that is suitable for input to MOVSS, 3605/// MOVSD, and MOVD, i.e. setting the lowest element. 3606static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3607 if (VT.getVectorElementType().getSizeInBits() < 32) 3608 return false; 3609 if (VT.getSizeInBits() == 256) 3610 return false; 3611 3612 unsigned NumElts = VT.getVectorNumElements(); 3613 3614 if (!isUndefOrEqual(Mask[0], NumElts)) 3615 return false; 3616 3617 for (unsigned i = 1; i != NumElts; ++i) 3618 if (!isUndefOrEqual(Mask[i], i)) 3619 return false; 3620 3621 return true; 3622} 3623 3624/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3625/// as permutations between 128-bit chunks or halves. As an example: this 3626/// shuffle bellow: 3627/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3628/// The first half comes from the second half of V1 and the second half from the 3629/// the second half of V2. 3630static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3631 if (!HasAVX || VT.getSizeInBits() != 256) 3632 return false; 3633 3634 // The shuffle result is divided into half A and half B. In total the two 3635 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3636 // B must come from C, D, E or F. 3637 unsigned HalfSize = VT.getVectorNumElements()/2; 3638 bool MatchA = false, MatchB = false; 3639 3640 // Check if A comes from one of C, D, E, F. 3641 for (unsigned Half = 0; Half != 4; ++Half) { 3642 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3643 MatchA = true; 3644 break; 3645 } 3646 } 3647 3648 // Check if B comes from one of C, D, E, F. 3649 for (unsigned Half = 0; Half != 4; ++Half) { 3650 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3651 MatchB = true; 3652 break; 3653 } 3654 } 3655 3656 return MatchA && MatchB; 3657} 3658 3659/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3660/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3661static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3662 EVT VT = SVOp->getValueType(0); 3663 3664 unsigned HalfSize = VT.getVectorNumElements()/2; 3665 3666 unsigned FstHalf = 0, SndHalf = 0; 3667 for (unsigned i = 0; i < HalfSize; ++i) { 3668 if (SVOp->getMaskElt(i) > 0) { 3669 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3670 break; 3671 } 3672 } 3673 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3674 if (SVOp->getMaskElt(i) > 0) { 3675 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3676 break; 3677 } 3678 } 3679 3680 return (FstHalf | (SndHalf << 4)); 3681} 3682 3683/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3684/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3685/// Note that VPERMIL mask matching is different depending whether theunderlying 3686/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3687/// to the same elements of the low, but to the higher half of the source. 3688/// In VPERMILPD the two lanes could be shuffled independently of each other 3689/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3690static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3691 if (!HasAVX) 3692 return false; 3693 3694 unsigned NumElts = VT.getVectorNumElements(); 3695 // Only match 256-bit with 32/64-bit types 3696 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3697 return false; 3698 3699 unsigned NumLanes = VT.getSizeInBits()/128; 3700 unsigned LaneSize = NumElts/NumLanes; 3701 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3702 for (unsigned i = 0; i != LaneSize; ++i) { 3703 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3704 return false; 3705 if (NumElts != 8 || l == 0) 3706 continue; 3707 // VPERMILPS handling 3708 if (Mask[i] < 0) 3709 continue; 3710 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3711 return false; 3712 } 3713 } 3714 3715 return true; 3716} 3717 3718/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3719/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3720/// element of vector 2 and the other elements to come from vector 1 in order. 3721static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3722 bool V2IsSplat = false, bool V2IsUndef = false) { 3723 unsigned NumOps = VT.getVectorNumElements(); 3724 if (VT.getSizeInBits() == 256) 3725 return false; 3726 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3727 return false; 3728 3729 if (!isUndefOrEqual(Mask[0], 0)) 3730 return false; 3731 3732 for (unsigned i = 1; i != NumOps; ++i) 3733 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3734 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3735 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3736 return false; 3737 3738 return true; 3739} 3740 3741/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3742/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3743/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3744static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3745 const X86Subtarget *Subtarget) { 3746 if (!Subtarget->hasSSE3()) 3747 return false; 3748 3749 unsigned NumElems = VT.getVectorNumElements(); 3750 3751 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3752 (VT.getSizeInBits() == 256 && NumElems != 8)) 3753 return false; 3754 3755 // "i+1" is the value the indexed mask element must have 3756 for (unsigned i = 0; i != NumElems; i += 2) 3757 if (!isUndefOrEqual(Mask[i], i+1) || 3758 !isUndefOrEqual(Mask[i+1], i+1)) 3759 return false; 3760 3761 return true; 3762} 3763 3764/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3765/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3766/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3767static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3768 const X86Subtarget *Subtarget) { 3769 if (!Subtarget->hasSSE3()) 3770 return false; 3771 3772 unsigned NumElems = VT.getVectorNumElements(); 3773 3774 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3775 (VT.getSizeInBits() == 256 && NumElems != 8)) 3776 return false; 3777 3778 // "i" is the value the indexed mask element must have 3779 for (unsigned i = 0; i != NumElems; i += 2) 3780 if (!isUndefOrEqual(Mask[i], i) || 3781 !isUndefOrEqual(Mask[i+1], i)) 3782 return false; 3783 3784 return true; 3785} 3786 3787/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3788/// specifies a shuffle of elements that is suitable for input to 256-bit 3789/// version of MOVDDUP. 3790static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3791 unsigned NumElts = VT.getVectorNumElements(); 3792 3793 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3794 return false; 3795 3796 for (unsigned i = 0; i != NumElts/2; ++i) 3797 if (!isUndefOrEqual(Mask[i], 0)) 3798 return false; 3799 for (unsigned i = NumElts/2; i != NumElts; ++i) 3800 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3801 return false; 3802 return true; 3803} 3804 3805/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3806/// specifies a shuffle of elements that is suitable for input to 128-bit 3807/// version of MOVDDUP. 3808static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3809 if (VT.getSizeInBits() != 128) 3810 return false; 3811 3812 unsigned e = VT.getVectorNumElements() / 2; 3813 for (unsigned i = 0; i != e; ++i) 3814 if (!isUndefOrEqual(Mask[i], i)) 3815 return false; 3816 for (unsigned i = 0; i != e; ++i) 3817 if (!isUndefOrEqual(Mask[e+i], i)) 3818 return false; 3819 return true; 3820} 3821 3822/// isVEXTRACTF128Index - Return true if the specified 3823/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3824/// suitable for input to VEXTRACTF128. 3825bool X86::isVEXTRACTF128Index(SDNode *N) { 3826 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3827 return false; 3828 3829 // The index should be aligned on a 128-bit boundary. 3830 uint64_t Index = 3831 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3832 3833 unsigned VL = N->getValueType(0).getVectorNumElements(); 3834 unsigned VBits = N->getValueType(0).getSizeInBits(); 3835 unsigned ElSize = VBits / VL; 3836 bool Result = (Index * ElSize) % 128 == 0; 3837 3838 return Result; 3839} 3840 3841/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3842/// operand specifies a subvector insert that is suitable for input to 3843/// VINSERTF128. 3844bool X86::isVINSERTF128Index(SDNode *N) { 3845 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3846 return false; 3847 3848 // The index should be aligned on a 128-bit boundary. 3849 uint64_t Index = 3850 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3851 3852 unsigned VL = N->getValueType(0).getVectorNumElements(); 3853 unsigned VBits = N->getValueType(0).getSizeInBits(); 3854 unsigned ElSize = VBits / VL; 3855 bool Result = (Index * ElSize) % 128 == 0; 3856 3857 return Result; 3858} 3859 3860/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3861/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3862/// Handles 128-bit and 256-bit. 3863static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3864 EVT VT = N->getValueType(0); 3865 3866 assert((VT.is128BitVector() || VT.is256BitVector()) && 3867 "Unsupported vector type for PSHUF/SHUFP"); 3868 3869 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3870 // independently on 128-bit lanes. 3871 unsigned NumElts = VT.getVectorNumElements(); 3872 unsigned NumLanes = VT.getSizeInBits()/128; 3873 unsigned NumLaneElts = NumElts/NumLanes; 3874 3875 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3876 "Only supports 2 or 4 elements per lane"); 3877 3878 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3879 unsigned Mask = 0; 3880 for (unsigned i = 0; i != NumElts; ++i) { 3881 int Elt = N->getMaskElt(i); 3882 if (Elt < 0) continue; 3883 Elt %= NumLaneElts; 3884 unsigned ShAmt = i << Shift; 3885 if (ShAmt >= 8) ShAmt -= 8; 3886 Mask |= Elt << ShAmt; 3887 } 3888 3889 return Mask; 3890} 3891 3892/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3893/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3894static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3895 unsigned Mask = 0; 3896 // 8 nodes, but we only care about the last 4. 3897 for (unsigned i = 7; i >= 4; --i) { 3898 int Val = N->getMaskElt(i); 3899 if (Val >= 0) 3900 Mask |= (Val - 4); 3901 if (i != 4) 3902 Mask <<= 2; 3903 } 3904 return Mask; 3905} 3906 3907/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3908/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3909static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3910 unsigned Mask = 0; 3911 // 8 nodes, but we only care about the first 4. 3912 for (int i = 3; i >= 0; --i) { 3913 int Val = N->getMaskElt(i); 3914 if (Val >= 0) 3915 Mask |= Val; 3916 if (i != 0) 3917 Mask <<= 2; 3918 } 3919 return Mask; 3920} 3921 3922/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3923/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3924static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3925 EVT VT = SVOp->getValueType(0); 3926 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3927 3928 unsigned NumElts = VT.getVectorNumElements(); 3929 unsigned NumLanes = VT.getSizeInBits()/128; 3930 unsigned NumLaneElts = NumElts/NumLanes; 3931 3932 int Val = 0; 3933 unsigned i; 3934 for (i = 0; i != NumElts; ++i) { 3935 Val = SVOp->getMaskElt(i); 3936 if (Val >= 0) 3937 break; 3938 } 3939 if (Val >= (int)NumElts) 3940 Val -= NumElts - NumLaneElts; 3941 3942 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3943 return (Val - i) * EltSize; 3944} 3945 3946/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3947/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3948/// instructions. 3949unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3950 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3951 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3952 3953 uint64_t Index = 3954 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3955 3956 EVT VecVT = N->getOperand(0).getValueType(); 3957 EVT ElVT = VecVT.getVectorElementType(); 3958 3959 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3960 return Index / NumElemsPerChunk; 3961} 3962 3963/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3964/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3965/// instructions. 3966unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3967 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3968 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3969 3970 uint64_t Index = 3971 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3972 3973 EVT VecVT = N->getValueType(0); 3974 EVT ElVT = VecVT.getVectorElementType(); 3975 3976 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3977 return Index / NumElemsPerChunk; 3978} 3979 3980/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 3981/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 3982/// Handles 256-bit. 3983static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 3984 EVT VT = N->getValueType(0); 3985 3986 unsigned NumElts = VT.getVectorNumElements(); 3987 3988 assert((VT.is256BitVector() && NumElts == 4) && 3989 "Unsupported vector type for VPERMQ/VPERMPD"); 3990 3991 unsigned Mask = 0; 3992 for (unsigned i = 0; i != NumElts; ++i) { 3993 int Elt = N->getMaskElt(i); 3994 if (Elt < 0) 3995 continue; 3996 Mask |= Elt << (i*2); 3997 } 3998 3999 return Mask; 4000} 4001/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4002/// constant +0.0. 4003bool X86::isZeroNode(SDValue Elt) { 4004 return ((isa<ConstantSDNode>(Elt) && 4005 cast<ConstantSDNode>(Elt)->isNullValue()) || 4006 (isa<ConstantFPSDNode>(Elt) && 4007 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4008} 4009 4010/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4011/// their permute mask. 4012static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4013 SelectionDAG &DAG) { 4014 EVT VT = SVOp->getValueType(0); 4015 unsigned NumElems = VT.getVectorNumElements(); 4016 SmallVector<int, 8> MaskVec; 4017 4018 for (unsigned i = 0; i != NumElems; ++i) { 4019 int idx = SVOp->getMaskElt(i); 4020 if (idx < 0) 4021 MaskVec.push_back(idx); 4022 else if (idx < (int)NumElems) 4023 MaskVec.push_back(idx + NumElems); 4024 else 4025 MaskVec.push_back(idx - NumElems); 4026 } 4027 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4028 SVOp->getOperand(0), &MaskVec[0]); 4029} 4030 4031/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4032/// match movhlps. The lower half elements should come from upper half of 4033/// V1 (and in order), and the upper half elements should come from the upper 4034/// half of V2 (and in order). 4035static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4036 if (VT.getSizeInBits() != 128) 4037 return false; 4038 if (VT.getVectorNumElements() != 4) 4039 return false; 4040 for (unsigned i = 0, e = 2; i != e; ++i) 4041 if (!isUndefOrEqual(Mask[i], i+2)) 4042 return false; 4043 for (unsigned i = 2; i != 4; ++i) 4044 if (!isUndefOrEqual(Mask[i], i+4)) 4045 return false; 4046 return true; 4047} 4048 4049/// isScalarLoadToVector - Returns true if the node is a scalar load that 4050/// is promoted to a vector. It also returns the LoadSDNode by reference if 4051/// required. 4052static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4053 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4054 return false; 4055 N = N->getOperand(0).getNode(); 4056 if (!ISD::isNON_EXTLoad(N)) 4057 return false; 4058 if (LD) 4059 *LD = cast<LoadSDNode>(N); 4060 return true; 4061} 4062 4063// Test whether the given value is a vector value which will be legalized 4064// into a load. 4065static bool WillBeConstantPoolLoad(SDNode *N) { 4066 if (N->getOpcode() != ISD::BUILD_VECTOR) 4067 return false; 4068 4069 // Check for any non-constant elements. 4070 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4071 switch (N->getOperand(i).getNode()->getOpcode()) { 4072 case ISD::UNDEF: 4073 case ISD::ConstantFP: 4074 case ISD::Constant: 4075 break; 4076 default: 4077 return false; 4078 } 4079 4080 // Vectors of all-zeros and all-ones are materialized with special 4081 // instructions rather than being loaded. 4082 return !ISD::isBuildVectorAllZeros(N) && 4083 !ISD::isBuildVectorAllOnes(N); 4084} 4085 4086/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4087/// match movlp{s|d}. The lower half elements should come from lower half of 4088/// V1 (and in order), and the upper half elements should come from the upper 4089/// half of V2 (and in order). And since V1 will become the source of the 4090/// MOVLP, it must be either a vector load or a scalar load to vector. 4091static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4092 ArrayRef<int> Mask, EVT VT) { 4093 if (VT.getSizeInBits() != 128) 4094 return false; 4095 4096 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4097 return false; 4098 // Is V2 is a vector load, don't do this transformation. We will try to use 4099 // load folding shufps op. 4100 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4101 return false; 4102 4103 unsigned NumElems = VT.getVectorNumElements(); 4104 4105 if (NumElems != 2 && NumElems != 4) 4106 return false; 4107 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4108 if (!isUndefOrEqual(Mask[i], i)) 4109 return false; 4110 for (unsigned i = NumElems/2; i != NumElems; ++i) 4111 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4112 return false; 4113 return true; 4114} 4115 4116/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4117/// all the same. 4118static bool isSplatVector(SDNode *N) { 4119 if (N->getOpcode() != ISD::BUILD_VECTOR) 4120 return false; 4121 4122 SDValue SplatValue = N->getOperand(0); 4123 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4124 if (N->getOperand(i) != SplatValue) 4125 return false; 4126 return true; 4127} 4128 4129/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4130/// to an zero vector. 4131/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4132static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4133 SDValue V1 = N->getOperand(0); 4134 SDValue V2 = N->getOperand(1); 4135 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4136 for (unsigned i = 0; i != NumElems; ++i) { 4137 int Idx = N->getMaskElt(i); 4138 if (Idx >= (int)NumElems) { 4139 unsigned Opc = V2.getOpcode(); 4140 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4141 continue; 4142 if (Opc != ISD::BUILD_VECTOR || 4143 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4144 return false; 4145 } else if (Idx >= 0) { 4146 unsigned Opc = V1.getOpcode(); 4147 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4148 continue; 4149 if (Opc != ISD::BUILD_VECTOR || 4150 !X86::isZeroNode(V1.getOperand(Idx))) 4151 return false; 4152 } 4153 } 4154 return true; 4155} 4156 4157/// getZeroVector - Returns a vector of specified type with all zero elements. 4158/// 4159static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4160 SelectionDAG &DAG, DebugLoc dl) { 4161 assert(VT.isVector() && "Expected a vector type"); 4162 4163 // Always build SSE zero vectors as <4 x i32> bitcasted 4164 // to their dest type. This ensures they get CSE'd. 4165 SDValue Vec; 4166 if (VT.getSizeInBits() == 128) { // SSE 4167 if (Subtarget->hasSSE2()) { // SSE2 4168 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4169 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4170 } else { // SSE1 4171 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4173 } 4174 } else if (VT.getSizeInBits() == 256) { // AVX 4175 if (Subtarget->hasAVX2()) { // AVX2 4176 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4177 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4179 } else { 4180 // 256-bit logic and arithmetic instructions in AVX are all 4181 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4182 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4183 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4184 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4185 } 4186 } 4187 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4188} 4189 4190/// getOnesVector - Returns a vector of specified type with all bits set. 4191/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4192/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4193/// Then bitcast to their original type, ensuring they get CSE'd. 4194static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4195 DebugLoc dl) { 4196 assert(VT.isVector() && "Expected a vector type"); 4197 assert((VT.is128BitVector() || VT.is256BitVector()) 4198 && "Expected a 128-bit or 256-bit vector type"); 4199 4200 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4201 SDValue Vec; 4202 if (VT.getSizeInBits() == 256) { 4203 if (HasAVX2) { // AVX2 4204 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4206 } else { // AVX 4207 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4208 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4209 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4210 Vec = Insert128BitVector(InsV, Vec, 4211 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4212 } 4213 } else { 4214 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4215 } 4216 4217 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4218} 4219 4220/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4221/// that point to V2 points to its first element. 4222static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4223 for (unsigned i = 0; i != NumElems; ++i) { 4224 if (Mask[i] > (int)NumElems) { 4225 Mask[i] = NumElems; 4226 } 4227 } 4228} 4229 4230/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4231/// operation of specified width. 4232static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4233 SDValue V2) { 4234 unsigned NumElems = VT.getVectorNumElements(); 4235 SmallVector<int, 8> Mask; 4236 Mask.push_back(NumElems); 4237 for (unsigned i = 1; i != NumElems; ++i) 4238 Mask.push_back(i); 4239 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4240} 4241 4242/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4243static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4244 SDValue V2) { 4245 unsigned NumElems = VT.getVectorNumElements(); 4246 SmallVector<int, 8> Mask; 4247 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4248 Mask.push_back(i); 4249 Mask.push_back(i + NumElems); 4250 } 4251 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4252} 4253 4254/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4255static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4256 SDValue V2) { 4257 unsigned NumElems = VT.getVectorNumElements(); 4258 unsigned Half = NumElems/2; 4259 SmallVector<int, 8> Mask; 4260 for (unsigned i = 0; i != Half; ++i) { 4261 Mask.push_back(i + Half); 4262 Mask.push_back(i + NumElems + Half); 4263 } 4264 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4265} 4266 4267// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4268// a generic shuffle instruction because the target has no such instructions. 4269// Generate shuffles which repeat i16 and i8 several times until they can be 4270// represented by v4f32 and then be manipulated by target suported shuffles. 4271static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4272 EVT VT = V.getValueType(); 4273 int NumElems = VT.getVectorNumElements(); 4274 DebugLoc dl = V.getDebugLoc(); 4275 4276 while (NumElems > 4) { 4277 if (EltNo < NumElems/2) { 4278 V = getUnpackl(DAG, dl, VT, V, V); 4279 } else { 4280 V = getUnpackh(DAG, dl, VT, V, V); 4281 EltNo -= NumElems/2; 4282 } 4283 NumElems >>= 1; 4284 } 4285 return V; 4286} 4287 4288/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4289static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4290 EVT VT = V.getValueType(); 4291 DebugLoc dl = V.getDebugLoc(); 4292 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4293 && "Vector size not supported"); 4294 4295 if (VT.getSizeInBits() == 128) { 4296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4297 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4298 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4299 &SplatMask[0]); 4300 } else { 4301 // To use VPERMILPS to splat scalars, the second half of indicies must 4302 // refer to the higher part, which is a duplication of the lower one, 4303 // because VPERMILPS can only handle in-lane permutations. 4304 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4305 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4306 4307 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4308 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4309 &SplatMask[0]); 4310 } 4311 4312 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4313} 4314 4315/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4316static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4317 EVT SrcVT = SV->getValueType(0); 4318 SDValue V1 = SV->getOperand(0); 4319 DebugLoc dl = SV->getDebugLoc(); 4320 4321 int EltNo = SV->getSplatIndex(); 4322 int NumElems = SrcVT.getVectorNumElements(); 4323 unsigned Size = SrcVT.getSizeInBits(); 4324 4325 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4326 "Unknown how to promote splat for type"); 4327 4328 // Extract the 128-bit part containing the splat element and update 4329 // the splat element index when it refers to the higher register. 4330 if (Size == 256) { 4331 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4332 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4333 if (Idx > 0) 4334 EltNo -= NumElems/2; 4335 } 4336 4337 // All i16 and i8 vector types can't be used directly by a generic shuffle 4338 // instruction because the target has no such instruction. Generate shuffles 4339 // which repeat i16 and i8 several times until they fit in i32, and then can 4340 // be manipulated by target suported shuffles. 4341 EVT EltVT = SrcVT.getVectorElementType(); 4342 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4343 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4344 4345 // Recreate the 256-bit vector and place the same 128-bit vector 4346 // into the low and high part. This is necessary because we want 4347 // to use VPERM* to shuffle the vectors 4348 if (Size == 256) { 4349 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4350 DAG.getConstant(0, MVT::i32), DAG, dl); 4351 V1 = Insert128BitVector(InsV, V1, 4352 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4353 } 4354 4355 return getLegalSplat(DAG, V1, EltNo); 4356} 4357 4358/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4359/// vector of zero or undef vector. This produces a shuffle where the low 4360/// element of V2 is swizzled into the zero/undef vector, landing at element 4361/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4362static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4363 bool IsZero, 4364 const X86Subtarget *Subtarget, 4365 SelectionDAG &DAG) { 4366 EVT VT = V2.getValueType(); 4367 SDValue V1 = IsZero 4368 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4369 unsigned NumElems = VT.getVectorNumElements(); 4370 SmallVector<int, 16> MaskVec; 4371 for (unsigned i = 0; i != NumElems; ++i) 4372 // If this is the insertion idx, put the low elt of V2 here. 4373 MaskVec.push_back(i == Idx ? NumElems : i); 4374 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4375} 4376 4377/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4378/// target specific opcode. Returns true if the Mask could be calculated. 4379/// Sets IsUnary to true if only uses one source. 4380static bool getTargetShuffleMask(SDNode *N, EVT VT, 4381 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4382 unsigned NumElems = VT.getVectorNumElements(); 4383 SDValue ImmN; 4384 4385 IsUnary = false; 4386 switch(N->getOpcode()) { 4387 case X86ISD::SHUFP: 4388 ImmN = N->getOperand(N->getNumOperands()-1); 4389 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4390 break; 4391 case X86ISD::UNPCKH: 4392 DecodeUNPCKHMask(VT, Mask); 4393 break; 4394 case X86ISD::UNPCKL: 4395 DecodeUNPCKLMask(VT, Mask); 4396 break; 4397 case X86ISD::MOVHLPS: 4398 DecodeMOVHLPSMask(NumElems, Mask); 4399 break; 4400 case X86ISD::MOVLHPS: 4401 DecodeMOVLHPSMask(NumElems, Mask); 4402 break; 4403 case X86ISD::PSHUFD: 4404 case X86ISD::VPERMILP: 4405 ImmN = N->getOperand(N->getNumOperands()-1); 4406 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4407 IsUnary = true; 4408 break; 4409 case X86ISD::PSHUFHW: 4410 ImmN = N->getOperand(N->getNumOperands()-1); 4411 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4412 IsUnary = true; 4413 break; 4414 case X86ISD::PSHUFLW: 4415 ImmN = N->getOperand(N->getNumOperands()-1); 4416 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4417 IsUnary = true; 4418 break; 4419 case X86ISD::MOVSS: 4420 case X86ISD::MOVSD: { 4421 // The index 0 always comes from the first element of the second source, 4422 // this is why MOVSS and MOVSD are used in the first place. The other 4423 // elements come from the other positions of the first source vector 4424 Mask.push_back(NumElems); 4425 for (unsigned i = 1; i != NumElems; ++i) { 4426 Mask.push_back(i); 4427 } 4428 break; 4429 } 4430 case X86ISD::VPERM2X128: 4431 ImmN = N->getOperand(N->getNumOperands()-1); 4432 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4433 break; 4434 case X86ISD::MOVDDUP: 4435 case X86ISD::MOVLHPD: 4436 case X86ISD::MOVLPD: 4437 case X86ISD::MOVLPS: 4438 case X86ISD::MOVSHDUP: 4439 case X86ISD::MOVSLDUP: 4440 case X86ISD::PALIGN: 4441 // Not yet implemented 4442 return false; 4443 default: llvm_unreachable("unknown target shuffle node"); 4444 } 4445 4446 return true; 4447} 4448 4449/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4450/// element of the result of the vector shuffle. 4451static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4452 unsigned Depth) { 4453 if (Depth == 6) 4454 return SDValue(); // Limit search depth. 4455 4456 SDValue V = SDValue(N, 0); 4457 EVT VT = V.getValueType(); 4458 unsigned Opcode = V.getOpcode(); 4459 4460 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4461 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4462 int Elt = SV->getMaskElt(Index); 4463 4464 if (Elt < 0) 4465 return DAG.getUNDEF(VT.getVectorElementType()); 4466 4467 unsigned NumElems = VT.getVectorNumElements(); 4468 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4469 : SV->getOperand(1); 4470 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4471 } 4472 4473 // Recurse into target specific vector shuffles to find scalars. 4474 if (isTargetShuffle(Opcode)) { 4475 unsigned NumElems = VT.getVectorNumElements(); 4476 SmallVector<int, 16> ShuffleMask; 4477 SDValue ImmN; 4478 bool IsUnary; 4479 4480 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary)) 4481 return SDValue(); 4482 4483 int Elt = ShuffleMask[Index]; 4484 if (Elt < 0) 4485 return DAG.getUNDEF(VT.getVectorElementType()); 4486 4487 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4488 : N->getOperand(1); 4489 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4490 Depth+1); 4491 } 4492 4493 // Actual nodes that may contain scalar elements 4494 if (Opcode == ISD::BITCAST) { 4495 V = V.getOperand(0); 4496 EVT SrcVT = V.getValueType(); 4497 unsigned NumElems = VT.getVectorNumElements(); 4498 4499 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4500 return SDValue(); 4501 } 4502 4503 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4504 return (Index == 0) ? V.getOperand(0) 4505 : DAG.getUNDEF(VT.getVectorElementType()); 4506 4507 if (V.getOpcode() == ISD::BUILD_VECTOR) 4508 return V.getOperand(Index); 4509 4510 return SDValue(); 4511} 4512 4513/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4514/// shuffle operation which come from a consecutively from a zero. The 4515/// search can start in two different directions, from left or right. 4516static 4517unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4518 bool ZerosFromLeft, SelectionDAG &DAG) { 4519 unsigned i; 4520 for (i = 0; i != NumElems; ++i) { 4521 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4522 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4523 if (!(Elt.getNode() && 4524 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4525 break; 4526 } 4527 4528 return i; 4529} 4530 4531/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4532/// correspond consecutively to elements from one of the vector operands, 4533/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4534static 4535bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4536 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4537 unsigned NumElems, unsigned &OpNum) { 4538 bool SeenV1 = false; 4539 bool SeenV2 = false; 4540 4541 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4542 int Idx = SVOp->getMaskElt(i); 4543 // Ignore undef indicies 4544 if (Idx < 0) 4545 continue; 4546 4547 if (Idx < (int)NumElems) 4548 SeenV1 = true; 4549 else 4550 SeenV2 = true; 4551 4552 // Only accept consecutive elements from the same vector 4553 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4554 return false; 4555 } 4556 4557 OpNum = SeenV1 ? 0 : 1; 4558 return true; 4559} 4560 4561/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4562/// logical left shift of a vector. 4563static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4564 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4565 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4566 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4567 false /* check zeros from right */, DAG); 4568 unsigned OpSrc; 4569 4570 if (!NumZeros) 4571 return false; 4572 4573 // Considering the elements in the mask that are not consecutive zeros, 4574 // check if they consecutively come from only one of the source vectors. 4575 // 4576 // V1 = {X, A, B, C} 0 4577 // \ \ \ / 4578 // vector_shuffle V1, V2 <1, 2, 3, X> 4579 // 4580 if (!isShuffleMaskConsecutive(SVOp, 4581 0, // Mask Start Index 4582 NumElems-NumZeros, // Mask End Index(exclusive) 4583 NumZeros, // Where to start looking in the src vector 4584 NumElems, // Number of elements in vector 4585 OpSrc)) // Which source operand ? 4586 return false; 4587 4588 isLeft = false; 4589 ShAmt = NumZeros; 4590 ShVal = SVOp->getOperand(OpSrc); 4591 return true; 4592} 4593 4594/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4595/// logical left shift of a vector. 4596static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4597 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4598 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4599 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4600 true /* check zeros from left */, DAG); 4601 unsigned OpSrc; 4602 4603 if (!NumZeros) 4604 return false; 4605 4606 // Considering the elements in the mask that are not consecutive zeros, 4607 // check if they consecutively come from only one of the source vectors. 4608 // 4609 // 0 { A, B, X, X } = V2 4610 // / \ / / 4611 // vector_shuffle V1, V2 <X, X, 4, 5> 4612 // 4613 if (!isShuffleMaskConsecutive(SVOp, 4614 NumZeros, // Mask Start Index 4615 NumElems, // Mask End Index(exclusive) 4616 0, // Where to start looking in the src vector 4617 NumElems, // Number of elements in vector 4618 OpSrc)) // Which source operand ? 4619 return false; 4620 4621 isLeft = true; 4622 ShAmt = NumZeros; 4623 ShVal = SVOp->getOperand(OpSrc); 4624 return true; 4625} 4626 4627/// isVectorShift - Returns true if the shuffle can be implemented as a 4628/// logical left or right shift of a vector. 4629static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4630 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4631 // Although the logic below support any bitwidth size, there are no 4632 // shift instructions which handle more than 128-bit vectors. 4633 if (SVOp->getValueType(0).getSizeInBits() > 128) 4634 return false; 4635 4636 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4637 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4638 return true; 4639 4640 return false; 4641} 4642 4643/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4644/// 4645static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4646 unsigned NumNonZero, unsigned NumZero, 4647 SelectionDAG &DAG, 4648 const X86Subtarget* Subtarget, 4649 const TargetLowering &TLI) { 4650 if (NumNonZero > 8) 4651 return SDValue(); 4652 4653 DebugLoc dl = Op.getDebugLoc(); 4654 SDValue V(0, 0); 4655 bool First = true; 4656 for (unsigned i = 0; i < 16; ++i) { 4657 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4658 if (ThisIsNonZero && First) { 4659 if (NumZero) 4660 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4661 else 4662 V = DAG.getUNDEF(MVT::v8i16); 4663 First = false; 4664 } 4665 4666 if ((i & 1) != 0) { 4667 SDValue ThisElt(0, 0), LastElt(0, 0); 4668 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4669 if (LastIsNonZero) { 4670 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4671 MVT::i16, Op.getOperand(i-1)); 4672 } 4673 if (ThisIsNonZero) { 4674 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4675 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4676 ThisElt, DAG.getConstant(8, MVT::i8)); 4677 if (LastIsNonZero) 4678 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4679 } else 4680 ThisElt = LastElt; 4681 4682 if (ThisElt.getNode()) 4683 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4684 DAG.getIntPtrConstant(i/2)); 4685 } 4686 } 4687 4688 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4689} 4690 4691/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4692/// 4693static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4694 unsigned NumNonZero, unsigned NumZero, 4695 SelectionDAG &DAG, 4696 const X86Subtarget* Subtarget, 4697 const TargetLowering &TLI) { 4698 if (NumNonZero > 4) 4699 return SDValue(); 4700 4701 DebugLoc dl = Op.getDebugLoc(); 4702 SDValue V(0, 0); 4703 bool First = true; 4704 for (unsigned i = 0; i < 8; ++i) { 4705 bool isNonZero = (NonZeros & (1 << i)) != 0; 4706 if (isNonZero) { 4707 if (First) { 4708 if (NumZero) 4709 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4710 else 4711 V = DAG.getUNDEF(MVT::v8i16); 4712 First = false; 4713 } 4714 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4715 MVT::v8i16, V, Op.getOperand(i), 4716 DAG.getIntPtrConstant(i)); 4717 } 4718 } 4719 4720 return V; 4721} 4722 4723/// getVShift - Return a vector logical shift node. 4724/// 4725static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4726 unsigned NumBits, SelectionDAG &DAG, 4727 const TargetLowering &TLI, DebugLoc dl) { 4728 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4729 EVT ShVT = MVT::v2i64; 4730 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4731 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4732 return DAG.getNode(ISD::BITCAST, dl, VT, 4733 DAG.getNode(Opc, dl, ShVT, SrcOp, 4734 DAG.getConstant(NumBits, 4735 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4736} 4737 4738SDValue 4739X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4740 SelectionDAG &DAG) const { 4741 4742 // Check if the scalar load can be widened into a vector load. And if 4743 // the address is "base + cst" see if the cst can be "absorbed" into 4744 // the shuffle mask. 4745 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4746 SDValue Ptr = LD->getBasePtr(); 4747 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4748 return SDValue(); 4749 EVT PVT = LD->getValueType(0); 4750 if (PVT != MVT::i32 && PVT != MVT::f32) 4751 return SDValue(); 4752 4753 int FI = -1; 4754 int64_t Offset = 0; 4755 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4756 FI = FINode->getIndex(); 4757 Offset = 0; 4758 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4759 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4760 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4761 Offset = Ptr.getConstantOperandVal(1); 4762 Ptr = Ptr.getOperand(0); 4763 } else { 4764 return SDValue(); 4765 } 4766 4767 // FIXME: 256-bit vector instructions don't require a strict alignment, 4768 // improve this code to support it better. 4769 unsigned RequiredAlign = VT.getSizeInBits()/8; 4770 SDValue Chain = LD->getChain(); 4771 // Make sure the stack object alignment is at least 16 or 32. 4772 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4773 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4774 if (MFI->isFixedObjectIndex(FI)) { 4775 // Can't change the alignment. FIXME: It's possible to compute 4776 // the exact stack offset and reference FI + adjust offset instead. 4777 // If someone *really* cares about this. That's the way to implement it. 4778 return SDValue(); 4779 } else { 4780 MFI->setObjectAlignment(FI, RequiredAlign); 4781 } 4782 } 4783 4784 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4785 // Ptr + (Offset & ~15). 4786 if (Offset < 0) 4787 return SDValue(); 4788 if ((Offset % RequiredAlign) & 3) 4789 return SDValue(); 4790 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4791 if (StartOffset) 4792 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4793 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4794 4795 int EltNo = (Offset - StartOffset) >> 2; 4796 int NumElems = VT.getVectorNumElements(); 4797 4798 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4799 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4800 LD->getPointerInfo().getWithOffset(StartOffset), 4801 false, false, false, 0); 4802 4803 SmallVector<int, 8> Mask; 4804 for (int i = 0; i < NumElems; ++i) 4805 Mask.push_back(EltNo); 4806 4807 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4808 } 4809 4810 return SDValue(); 4811} 4812 4813/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4814/// vector of type 'VT', see if the elements can be replaced by a single large 4815/// load which has the same value as a build_vector whose operands are 'elts'. 4816/// 4817/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4818/// 4819/// FIXME: we'd also like to handle the case where the last elements are zero 4820/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4821/// There's even a handy isZeroNode for that purpose. 4822static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4823 DebugLoc &DL, SelectionDAG &DAG) { 4824 EVT EltVT = VT.getVectorElementType(); 4825 unsigned NumElems = Elts.size(); 4826 4827 LoadSDNode *LDBase = NULL; 4828 unsigned LastLoadedElt = -1U; 4829 4830 // For each element in the initializer, see if we've found a load or an undef. 4831 // If we don't find an initial load element, or later load elements are 4832 // non-consecutive, bail out. 4833 for (unsigned i = 0; i < NumElems; ++i) { 4834 SDValue Elt = Elts[i]; 4835 4836 if (!Elt.getNode() || 4837 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4838 return SDValue(); 4839 if (!LDBase) { 4840 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4841 return SDValue(); 4842 LDBase = cast<LoadSDNode>(Elt.getNode()); 4843 LastLoadedElt = i; 4844 continue; 4845 } 4846 if (Elt.getOpcode() == ISD::UNDEF) 4847 continue; 4848 4849 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4850 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4851 return SDValue(); 4852 LastLoadedElt = i; 4853 } 4854 4855 // If we have found an entire vector of loads and undefs, then return a large 4856 // load of the entire vector width starting at the base pointer. If we found 4857 // consecutive loads for the low half, generate a vzext_load node. 4858 if (LastLoadedElt == NumElems - 1) { 4859 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4860 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4861 LDBase->getPointerInfo(), 4862 LDBase->isVolatile(), LDBase->isNonTemporal(), 4863 LDBase->isInvariant(), 0); 4864 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4865 LDBase->getPointerInfo(), 4866 LDBase->isVolatile(), LDBase->isNonTemporal(), 4867 LDBase->isInvariant(), LDBase->getAlignment()); 4868 } else if (NumElems == 4 && LastLoadedElt == 1 && 4869 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4870 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4871 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4872 SDValue ResNode = 4873 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4874 LDBase->getPointerInfo(), 4875 LDBase->getAlignment(), 4876 false/*isVolatile*/, true/*ReadMem*/, 4877 false/*WriteMem*/); 4878 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4879 } 4880 return SDValue(); 4881} 4882 4883/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 4884/// to generate a splat value for the following cases: 4885/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 4886/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4887/// a scalar load, or a constant. 4888/// The VBROADCAST node is returned when a pattern is found, 4889/// or SDValue() otherwise. 4890SDValue 4891X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 4892 if (!Subtarget->hasAVX()) 4893 return SDValue(); 4894 4895 EVT VT = Op.getValueType(); 4896 DebugLoc dl = Op.getDebugLoc(); 4897 4898 SDValue Ld; 4899 bool ConstSplatVal; 4900 4901 switch (Op.getOpcode()) { 4902 default: 4903 // Unknown pattern found. 4904 return SDValue(); 4905 4906 case ISD::BUILD_VECTOR: { 4907 // The BUILD_VECTOR node must be a splat. 4908 if (!isSplatVector(Op.getNode())) 4909 return SDValue(); 4910 4911 Ld = Op.getOperand(0); 4912 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4913 Ld.getOpcode() == ISD::ConstantFP); 4914 4915 // The suspected load node has several users. Make sure that all 4916 // of its users are from the BUILD_VECTOR node. 4917 // Constants may have multiple users. 4918 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4919 return SDValue(); 4920 break; 4921 } 4922 4923 case ISD::VECTOR_SHUFFLE: { 4924 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4925 4926 // Shuffles must have a splat mask where the first element is 4927 // broadcasted. 4928 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4929 return SDValue(); 4930 4931 SDValue Sc = Op.getOperand(0); 4932 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4933 return SDValue(); 4934 4935 Ld = Sc.getOperand(0); 4936 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4937 Ld.getOpcode() == ISD::ConstantFP); 4938 4939 // The scalar_to_vector node and the suspected 4940 // load node must have exactly one user. 4941 // Constants may have multiple users. 4942 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 4943 return SDValue(); 4944 break; 4945 } 4946 } 4947 4948 bool Is256 = VT.getSizeInBits() == 256; 4949 bool Is128 = VT.getSizeInBits() == 128; 4950 4951 // Handle the broadcasting a single constant scalar from the constant pool 4952 // into a vector. On Sandybridge it is still better to load a constant vector 4953 // from the constant pool and not to broadcast it from a scalar. 4954 if (ConstSplatVal && Subtarget->hasAVX2()) { 4955 EVT CVT = Ld.getValueType(); 4956 assert(!CVT.isVector() && "Must not broadcast a vector type"); 4957 unsigned ScalarSize = CVT.getSizeInBits(); 4958 4959 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) || 4960 (Is128 && (ScalarSize == 32))) { 4961 4962 const Constant *C = 0; 4963 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 4964 C = CI->getConstantIntValue(); 4965 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 4966 C = CF->getConstantFPValue(); 4967 4968 assert(C && "Invalid constant type"); 4969 4970 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 4971 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 4972 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 4973 MachinePointerInfo::getConstantPool(), 4974 false, false, false, Alignment); 4975 4976 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4977 } 4978 } 4979 4980 // The scalar source must be a normal load. 4981 if (!ISD::isNormalLoad(Ld.getNode())) 4982 return SDValue(); 4983 4984 // Reject loads that have uses of the chain result 4985 if (Ld->hasAnyUseOfValue(1)) 4986 return SDValue(); 4987 4988 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4989 4990 // VBroadcast to YMM 4991 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4992 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4993 4994 // VBroadcast to XMM 4995 if (Is128 && (ScalarSize == 32)) 4996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4997 4998 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 4999 // double since there is vbroadcastsd xmm 5000 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5001 // VBroadcast to YMM 5002 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 5003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5004 5005 // VBroadcast to XMM 5006 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 5007 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5008 } 5009 5010 // Unsupported broadcast. 5011 return SDValue(); 5012} 5013 5014SDValue 5015X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5016 DebugLoc dl = Op.getDebugLoc(); 5017 5018 EVT VT = Op.getValueType(); 5019 EVT ExtVT = VT.getVectorElementType(); 5020 unsigned NumElems = Op.getNumOperands(); 5021 5022 // Vectors containing all zeros can be matched by pxor and xorps later 5023 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5024 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5025 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5026 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5027 return Op; 5028 5029 return getZeroVector(VT, Subtarget, DAG, dl); 5030 } 5031 5032 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5033 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5034 // vpcmpeqd on 256-bit vectors. 5035 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5036 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5037 return Op; 5038 5039 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5040 } 5041 5042 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5043 if (Broadcast.getNode()) 5044 return Broadcast; 5045 5046 unsigned EVTBits = ExtVT.getSizeInBits(); 5047 5048 unsigned NumZero = 0; 5049 unsigned NumNonZero = 0; 5050 unsigned NonZeros = 0; 5051 bool IsAllConstants = true; 5052 SmallSet<SDValue, 8> Values; 5053 for (unsigned i = 0; i < NumElems; ++i) { 5054 SDValue Elt = Op.getOperand(i); 5055 if (Elt.getOpcode() == ISD::UNDEF) 5056 continue; 5057 Values.insert(Elt); 5058 if (Elt.getOpcode() != ISD::Constant && 5059 Elt.getOpcode() != ISD::ConstantFP) 5060 IsAllConstants = false; 5061 if (X86::isZeroNode(Elt)) 5062 NumZero++; 5063 else { 5064 NonZeros |= (1 << i); 5065 NumNonZero++; 5066 } 5067 } 5068 5069 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5070 if (NumNonZero == 0) 5071 return DAG.getUNDEF(VT); 5072 5073 // Special case for single non-zero, non-undef, element. 5074 if (NumNonZero == 1) { 5075 unsigned Idx = CountTrailingZeros_32(NonZeros); 5076 SDValue Item = Op.getOperand(Idx); 5077 5078 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5079 // the value are obviously zero, truncate the value to i32 and do the 5080 // insertion that way. Only do this if the value is non-constant or if the 5081 // value is a constant being inserted into element 0. It is cheaper to do 5082 // a constant pool load than it is to do a movd + shuffle. 5083 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5084 (!IsAllConstants || Idx == 0)) { 5085 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5086 // Handle SSE only. 5087 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5088 EVT VecVT = MVT::v4i32; 5089 unsigned VecElts = 4; 5090 5091 // Truncate the value (which may itself be a constant) to i32, and 5092 // convert it to a vector with movd (S2V+shuffle to zero extend). 5093 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5094 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5095 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5096 5097 // Now we have our 32-bit value zero extended in the low element of 5098 // a vector. If Idx != 0, swizzle it into place. 5099 if (Idx != 0) { 5100 SmallVector<int, 4> Mask; 5101 Mask.push_back(Idx); 5102 for (unsigned i = 1; i != VecElts; ++i) 5103 Mask.push_back(i); 5104 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5105 DAG.getUNDEF(Item.getValueType()), 5106 &Mask[0]); 5107 } 5108 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5109 } 5110 } 5111 5112 // If we have a constant or non-constant insertion into the low element of 5113 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5114 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5115 // depending on what the source datatype is. 5116 if (Idx == 0) { 5117 if (NumZero == 0) 5118 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5119 5120 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5121 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5122 if (VT.getSizeInBits() == 256) { 5123 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5124 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5125 Item, DAG.getIntPtrConstant(0)); 5126 } 5127 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5128 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5129 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5130 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5131 } 5132 5133 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5134 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5135 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5136 if (VT.getSizeInBits() == 256) { 5137 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5138 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5139 DAG, dl); 5140 } else { 5141 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5142 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5143 } 5144 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5145 } 5146 } 5147 5148 // Is it a vector logical left shift? 5149 if (NumElems == 2 && Idx == 1 && 5150 X86::isZeroNode(Op.getOperand(0)) && 5151 !X86::isZeroNode(Op.getOperand(1))) { 5152 unsigned NumBits = VT.getSizeInBits(); 5153 return getVShift(true, VT, 5154 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5155 VT, Op.getOperand(1)), 5156 NumBits/2, DAG, *this, dl); 5157 } 5158 5159 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5160 return SDValue(); 5161 5162 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5163 // is a non-constant being inserted into an element other than the low one, 5164 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5165 // movd/movss) to move this into the low element, then shuffle it into 5166 // place. 5167 if (EVTBits == 32) { 5168 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5169 5170 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5171 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5172 SmallVector<int, 8> MaskVec; 5173 for (unsigned i = 0; i < NumElems; i++) 5174 MaskVec.push_back(i == Idx ? 0 : 1); 5175 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5176 } 5177 } 5178 5179 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5180 if (Values.size() == 1) { 5181 if (EVTBits == 32) { 5182 // Instead of a shuffle like this: 5183 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5184 // Check if it's possible to issue this instead. 5185 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5186 unsigned Idx = CountTrailingZeros_32(NonZeros); 5187 SDValue Item = Op.getOperand(Idx); 5188 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5189 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5190 } 5191 return SDValue(); 5192 } 5193 5194 // A vector full of immediates; various special cases are already 5195 // handled, so this is best done with a single constant-pool load. 5196 if (IsAllConstants) 5197 return SDValue(); 5198 5199 // For AVX-length vectors, build the individual 128-bit pieces and use 5200 // shuffles to put them in place. 5201 if (VT.getSizeInBits() == 256) { 5202 SmallVector<SDValue, 32> V; 5203 for (unsigned i = 0; i != NumElems; ++i) 5204 V.push_back(Op.getOperand(i)); 5205 5206 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5207 5208 // Build both the lower and upper subvector. 5209 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5210 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5211 NumElems/2); 5212 5213 // Recreate the wider vector with the lower and upper part. 5214 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5215 DAG.getConstant(0, MVT::i32), DAG, dl); 5216 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5217 DAG, dl); 5218 } 5219 5220 // Let legalizer expand 2-wide build_vectors. 5221 if (EVTBits == 64) { 5222 if (NumNonZero == 1) { 5223 // One half is zero or undef. 5224 unsigned Idx = CountTrailingZeros_32(NonZeros); 5225 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5226 Op.getOperand(Idx)); 5227 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5228 } 5229 return SDValue(); 5230 } 5231 5232 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5233 if (EVTBits == 8 && NumElems == 16) { 5234 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5235 Subtarget, *this); 5236 if (V.getNode()) return V; 5237 } 5238 5239 if (EVTBits == 16 && NumElems == 8) { 5240 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5241 Subtarget, *this); 5242 if (V.getNode()) return V; 5243 } 5244 5245 // If element VT is == 32 bits, turn it into a number of shuffles. 5246 SmallVector<SDValue, 8> V(NumElems); 5247 if (NumElems == 4 && NumZero > 0) { 5248 for (unsigned i = 0; i < 4; ++i) { 5249 bool isZero = !(NonZeros & (1 << i)); 5250 if (isZero) 5251 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5252 else 5253 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5254 } 5255 5256 for (unsigned i = 0; i < 2; ++i) { 5257 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5258 default: break; 5259 case 0: 5260 V[i] = V[i*2]; // Must be a zero vector. 5261 break; 5262 case 1: 5263 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5264 break; 5265 case 2: 5266 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5267 break; 5268 case 3: 5269 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5270 break; 5271 } 5272 } 5273 5274 bool Reverse1 = (NonZeros & 0x3) == 2; 5275 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5276 int MaskVec[] = { 5277 Reverse1 ? 1 : 0, 5278 Reverse1 ? 0 : 1, 5279 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5280 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5281 }; 5282 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5283 } 5284 5285 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5286 // Check for a build vector of consecutive loads. 5287 for (unsigned i = 0; i < NumElems; ++i) 5288 V[i] = Op.getOperand(i); 5289 5290 // Check for elements which are consecutive loads. 5291 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5292 if (LD.getNode()) 5293 return LD; 5294 5295 // For SSE 4.1, use insertps to put the high elements into the low element. 5296 if (getSubtarget()->hasSSE41()) { 5297 SDValue Result; 5298 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5299 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5300 else 5301 Result = DAG.getUNDEF(VT); 5302 5303 for (unsigned i = 1; i < NumElems; ++i) { 5304 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5305 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5306 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5307 } 5308 return Result; 5309 } 5310 5311 // Otherwise, expand into a number of unpckl*, start by extending each of 5312 // our (non-undef) elements to the full vector width with the element in the 5313 // bottom slot of the vector (which generates no code for SSE). 5314 for (unsigned i = 0; i < NumElems; ++i) { 5315 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5316 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5317 else 5318 V[i] = DAG.getUNDEF(VT); 5319 } 5320 5321 // Next, we iteratively mix elements, e.g. for v4f32: 5322 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5323 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5324 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5325 unsigned EltStride = NumElems >> 1; 5326 while (EltStride != 0) { 5327 for (unsigned i = 0; i < EltStride; ++i) { 5328 // If V[i+EltStride] is undef and this is the first round of mixing, 5329 // then it is safe to just drop this shuffle: V[i] is already in the 5330 // right place, the one element (since it's the first round) being 5331 // inserted as undef can be dropped. This isn't safe for successive 5332 // rounds because they will permute elements within both vectors. 5333 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5334 EltStride == NumElems/2) 5335 continue; 5336 5337 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5338 } 5339 EltStride >>= 1; 5340 } 5341 return V[0]; 5342 } 5343 return SDValue(); 5344} 5345 5346// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5347// them in a MMX register. This is better than doing a stack convert. 5348static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5349 DebugLoc dl = Op.getDebugLoc(); 5350 EVT ResVT = Op.getValueType(); 5351 5352 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5353 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5354 int Mask[2]; 5355 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5356 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5357 InVec = Op.getOperand(1); 5358 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5359 unsigned NumElts = ResVT.getVectorNumElements(); 5360 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5361 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5362 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5363 } else { 5364 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5365 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5366 Mask[0] = 0; Mask[1] = 2; 5367 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5368 } 5369 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5370} 5371 5372// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5373// to create 256-bit vectors from two other 128-bit ones. 5374static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5375 DebugLoc dl = Op.getDebugLoc(); 5376 EVT ResVT = Op.getValueType(); 5377 5378 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5379 5380 SDValue V1 = Op.getOperand(0); 5381 SDValue V2 = Op.getOperand(1); 5382 unsigned NumElems = ResVT.getVectorNumElements(); 5383 5384 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5385 DAG.getConstant(0, MVT::i32), DAG, dl); 5386 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5387 DAG, dl); 5388} 5389 5390SDValue 5391X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5392 EVT ResVT = Op.getValueType(); 5393 5394 assert(Op.getNumOperands() == 2); 5395 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5396 "Unsupported CONCAT_VECTORS for value type"); 5397 5398 // We support concatenate two MMX registers and place them in a MMX register. 5399 // This is better than doing a stack convert. 5400 if (ResVT.is128BitVector()) 5401 return LowerMMXCONCAT_VECTORS(Op, DAG); 5402 5403 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5404 // from two other 128-bit ones. 5405 return LowerAVXCONCAT_VECTORS(Op, DAG); 5406} 5407 5408// Try to lower a shuffle node into a simple blend instruction. 5409static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op, 5410 const X86Subtarget *Subtarget, 5411 SelectionDAG &DAG) { 5412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5413 SDValue V1 = SVOp->getOperand(0); 5414 SDValue V2 = SVOp->getOperand(1); 5415 DebugLoc dl = SVOp->getDebugLoc(); 5416 EVT VT = Op.getValueType(); 5417 EVT InVT = V1.getValueType(); 5418 int MaskSize = VT.getVectorNumElements(); 5419 int InSize = InVT.getVectorNumElements(); 5420 5421 if (!Subtarget->hasSSE41()) 5422 return SDValue(); 5423 5424 if (MaskSize != InSize) 5425 return SDValue(); 5426 5427 int ISDNo = 0; 5428 MVT OpTy; 5429 5430 switch (VT.getSimpleVT().SimpleTy) { 5431 default: return SDValue(); 5432 case MVT::v8i16: 5433 ISDNo = X86ISD::BLENDPW; 5434 OpTy = MVT::v8i16; 5435 break; 5436 case MVT::v4i32: 5437 case MVT::v4f32: 5438 ISDNo = X86ISD::BLENDPS; 5439 OpTy = MVT::v4f32; 5440 break; 5441 case MVT::v2i64: 5442 case MVT::v2f64: 5443 ISDNo = X86ISD::BLENDPD; 5444 OpTy = MVT::v2f64; 5445 break; 5446 case MVT::v8i32: 5447 case MVT::v8f32: 5448 if (!Subtarget->hasAVX()) 5449 return SDValue(); 5450 ISDNo = X86ISD::BLENDPS; 5451 OpTy = MVT::v8f32; 5452 break; 5453 case MVT::v4i64: 5454 case MVT::v4f64: 5455 if (!Subtarget->hasAVX()) 5456 return SDValue(); 5457 ISDNo = X86ISD::BLENDPD; 5458 OpTy = MVT::v4f64; 5459 break; 5460 case MVT::v16i16: 5461 if (!Subtarget->hasAVX2()) 5462 return SDValue(); 5463 ISDNo = X86ISD::BLENDPW; 5464 OpTy = MVT::v16i16; 5465 break; 5466 } 5467 assert(ISDNo && "Invalid Op Number"); 5468 5469 unsigned MaskVals = 0; 5470 5471 for (int i = 0; i < MaskSize; ++i) { 5472 int EltIdx = SVOp->getMaskElt(i); 5473 if (EltIdx == i || EltIdx == -1) 5474 MaskVals |= (1<<i); 5475 else if (EltIdx == (i + MaskSize)) 5476 continue; // Bit is set to zero; 5477 else return SDValue(); 5478 } 5479 5480 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); 5481 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2); 5482 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2, 5483 DAG.getConstant(MaskVals, MVT::i32)); 5484 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5485} 5486 5487// v8i16 shuffles - Prefer shuffles in the following order: 5488// 1. [all] pshuflw, pshufhw, optional move 5489// 2. [ssse3] 1 x pshufb 5490// 3. [ssse3] 2 x pshufb + 1 x por 5491// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5492SDValue 5493X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5494 SelectionDAG &DAG) const { 5495 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5496 SDValue V1 = SVOp->getOperand(0); 5497 SDValue V2 = SVOp->getOperand(1); 5498 DebugLoc dl = SVOp->getDebugLoc(); 5499 SmallVector<int, 8> MaskVals; 5500 5501 // Determine if more than 1 of the words in each of the low and high quadwords 5502 // of the result come from the same quadword of one of the two inputs. Undef 5503 // mask values count as coming from any quadword, for better codegen. 5504 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5505 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5506 std::bitset<4> InputQuads; 5507 for (unsigned i = 0; i < 8; ++i) { 5508 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5509 int EltIdx = SVOp->getMaskElt(i); 5510 MaskVals.push_back(EltIdx); 5511 if (EltIdx < 0) { 5512 ++Quad[0]; 5513 ++Quad[1]; 5514 ++Quad[2]; 5515 ++Quad[3]; 5516 continue; 5517 } 5518 ++Quad[EltIdx / 4]; 5519 InputQuads.set(EltIdx / 4); 5520 } 5521 5522 int BestLoQuad = -1; 5523 unsigned MaxQuad = 1; 5524 for (unsigned i = 0; i < 4; ++i) { 5525 if (LoQuad[i] > MaxQuad) { 5526 BestLoQuad = i; 5527 MaxQuad = LoQuad[i]; 5528 } 5529 } 5530 5531 int BestHiQuad = -1; 5532 MaxQuad = 1; 5533 for (unsigned i = 0; i < 4; ++i) { 5534 if (HiQuad[i] > MaxQuad) { 5535 BestHiQuad = i; 5536 MaxQuad = HiQuad[i]; 5537 } 5538 } 5539 5540 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5541 // of the two input vectors, shuffle them into one input vector so only a 5542 // single pshufb instruction is necessary. If There are more than 2 input 5543 // quads, disable the next transformation since it does not help SSSE3. 5544 bool V1Used = InputQuads[0] || InputQuads[1]; 5545 bool V2Used = InputQuads[2] || InputQuads[3]; 5546 if (Subtarget->hasSSSE3()) { 5547 if (InputQuads.count() == 2 && V1Used && V2Used) { 5548 BestLoQuad = InputQuads[0] ? 0 : 1; 5549 BestHiQuad = InputQuads[2] ? 2 : 3; 5550 } 5551 if (InputQuads.count() > 2) { 5552 BestLoQuad = -1; 5553 BestHiQuad = -1; 5554 } 5555 } 5556 5557 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5558 // the shuffle mask. If a quad is scored as -1, that means that it contains 5559 // words from all 4 input quadwords. 5560 SDValue NewV; 5561 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5562 int MaskV[] = { 5563 BestLoQuad < 0 ? 0 : BestLoQuad, 5564 BestHiQuad < 0 ? 1 : BestHiQuad 5565 }; 5566 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5567 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5568 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5569 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5570 5571 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5572 // source words for the shuffle, to aid later transformations. 5573 bool AllWordsInNewV = true; 5574 bool InOrder[2] = { true, true }; 5575 for (unsigned i = 0; i != 8; ++i) { 5576 int idx = MaskVals[i]; 5577 if (idx != (int)i) 5578 InOrder[i/4] = false; 5579 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5580 continue; 5581 AllWordsInNewV = false; 5582 break; 5583 } 5584 5585 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5586 if (AllWordsInNewV) { 5587 for (int i = 0; i != 8; ++i) { 5588 int idx = MaskVals[i]; 5589 if (idx < 0) 5590 continue; 5591 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5592 if ((idx != i) && idx < 4) 5593 pshufhw = false; 5594 if ((idx != i) && idx > 3) 5595 pshuflw = false; 5596 } 5597 V1 = NewV; 5598 V2Used = false; 5599 BestLoQuad = 0; 5600 BestHiQuad = 1; 5601 } 5602 5603 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5604 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5605 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5606 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5607 unsigned TargetMask = 0; 5608 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5609 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5610 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5611 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5612 getShufflePSHUFLWImmediate(SVOp); 5613 V1 = NewV.getOperand(0); 5614 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5615 } 5616 } 5617 5618 // If we have SSSE3, and all words of the result are from 1 input vector, 5619 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5620 // is present, fall back to case 4. 5621 if (Subtarget->hasSSSE3()) { 5622 SmallVector<SDValue,16> pshufbMask; 5623 5624 // If we have elements from both input vectors, set the high bit of the 5625 // shuffle mask element to zero out elements that come from V2 in the V1 5626 // mask, and elements that come from V1 in the V2 mask, so that the two 5627 // results can be OR'd together. 5628 bool TwoInputs = V1Used && V2Used; 5629 for (unsigned i = 0; i != 8; ++i) { 5630 int EltIdx = MaskVals[i] * 2; 5631 if (TwoInputs && (EltIdx >= 16)) { 5632 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5633 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5634 continue; 5635 } 5636 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5637 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5638 } 5639 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5640 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5641 DAG.getNode(ISD::BUILD_VECTOR, dl, 5642 MVT::v16i8, &pshufbMask[0], 16)); 5643 if (!TwoInputs) 5644 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5645 5646 // Calculate the shuffle mask for the second input, shuffle it, and 5647 // OR it with the first shuffled input. 5648 pshufbMask.clear(); 5649 for (unsigned i = 0; i != 8; ++i) { 5650 int EltIdx = MaskVals[i] * 2; 5651 if (EltIdx < 16) { 5652 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5653 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5654 continue; 5655 } 5656 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5657 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5658 } 5659 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5660 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5661 DAG.getNode(ISD::BUILD_VECTOR, dl, 5662 MVT::v16i8, &pshufbMask[0], 16)); 5663 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5664 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5665 } 5666 5667 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5668 // and update MaskVals with new element order. 5669 std::bitset<8> InOrder; 5670 if (BestLoQuad >= 0) { 5671 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5672 for (int i = 0; i != 4; ++i) { 5673 int idx = MaskVals[i]; 5674 if (idx < 0) { 5675 InOrder.set(i); 5676 } else if ((idx / 4) == BestLoQuad) { 5677 MaskV[i] = idx & 3; 5678 InOrder.set(i); 5679 } 5680 } 5681 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5682 &MaskV[0]); 5683 5684 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5686 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5687 NewV.getOperand(0), 5688 getShufflePSHUFLWImmediate(SVOp), DAG); 5689 } 5690 } 5691 5692 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5693 // and update MaskVals with the new element order. 5694 if (BestHiQuad >= 0) { 5695 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5696 for (unsigned i = 4; i != 8; ++i) { 5697 int idx = MaskVals[i]; 5698 if (idx < 0) { 5699 InOrder.set(i); 5700 } else if ((idx / 4) == BestHiQuad) { 5701 MaskV[i] = (idx & 3) + 4; 5702 InOrder.set(i); 5703 } 5704 } 5705 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5706 &MaskV[0]); 5707 5708 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5710 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5711 NewV.getOperand(0), 5712 getShufflePSHUFHWImmediate(SVOp), DAG); 5713 } 5714 } 5715 5716 // In case BestHi & BestLo were both -1, which means each quadword has a word 5717 // from each of the four input quadwords, calculate the InOrder bitvector now 5718 // before falling through to the insert/extract cleanup. 5719 if (BestLoQuad == -1 && BestHiQuad == -1) { 5720 NewV = V1; 5721 for (int i = 0; i != 8; ++i) 5722 if (MaskVals[i] < 0 || MaskVals[i] == i) 5723 InOrder.set(i); 5724 } 5725 5726 // The other elements are put in the right place using pextrw and pinsrw. 5727 for (unsigned i = 0; i != 8; ++i) { 5728 if (InOrder[i]) 5729 continue; 5730 int EltIdx = MaskVals[i]; 5731 if (EltIdx < 0) 5732 continue; 5733 SDValue ExtOp = (EltIdx < 8) 5734 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5735 DAG.getIntPtrConstant(EltIdx)) 5736 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5737 DAG.getIntPtrConstant(EltIdx - 8)); 5738 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5739 DAG.getIntPtrConstant(i)); 5740 } 5741 return NewV; 5742} 5743 5744// v16i8 shuffles - Prefer shuffles in the following order: 5745// 1. [ssse3] 1 x pshufb 5746// 2. [ssse3] 2 x pshufb + 1 x por 5747// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5748static 5749SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5750 SelectionDAG &DAG, 5751 const X86TargetLowering &TLI) { 5752 SDValue V1 = SVOp->getOperand(0); 5753 SDValue V2 = SVOp->getOperand(1); 5754 DebugLoc dl = SVOp->getDebugLoc(); 5755 ArrayRef<int> MaskVals = SVOp->getMask(); 5756 5757 // If we have SSSE3, case 1 is generated when all result bytes come from 5758 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5759 // present, fall back to case 3. 5760 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5761 bool V1Only = true; 5762 bool V2Only = true; 5763 for (unsigned i = 0; i < 16; ++i) { 5764 int EltIdx = MaskVals[i]; 5765 if (EltIdx < 0) 5766 continue; 5767 if (EltIdx < 16) 5768 V2Only = false; 5769 else 5770 V1Only = false; 5771 } 5772 5773 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5774 if (TLI.getSubtarget()->hasSSSE3()) { 5775 SmallVector<SDValue,16> pshufbMask; 5776 5777 // If all result elements are from one input vector, then only translate 5778 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5779 // 5780 // Otherwise, we have elements from both input vectors, and must zero out 5781 // elements that come from V2 in the first mask, and V1 in the second mask 5782 // so that we can OR them together. 5783 bool TwoInputs = !(V1Only || V2Only); 5784 for (unsigned i = 0; i != 16; ++i) { 5785 int EltIdx = MaskVals[i]; 5786 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5787 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5788 continue; 5789 } 5790 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5791 } 5792 // If all the elements are from V2, assign it to V1 and return after 5793 // building the first pshufb. 5794 if (V2Only) 5795 V1 = V2; 5796 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5797 DAG.getNode(ISD::BUILD_VECTOR, dl, 5798 MVT::v16i8, &pshufbMask[0], 16)); 5799 if (!TwoInputs) 5800 return V1; 5801 5802 // Calculate the shuffle mask for the second input, shuffle it, and 5803 // OR it with the first shuffled input. 5804 pshufbMask.clear(); 5805 for (unsigned i = 0; i != 16; ++i) { 5806 int EltIdx = MaskVals[i]; 5807 if (EltIdx < 16) { 5808 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5809 continue; 5810 } 5811 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5812 } 5813 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5814 DAG.getNode(ISD::BUILD_VECTOR, dl, 5815 MVT::v16i8, &pshufbMask[0], 16)); 5816 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5817 } 5818 5819 // No SSSE3 - Calculate in place words and then fix all out of place words 5820 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5821 // the 16 different words that comprise the two doublequadword input vectors. 5822 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5823 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5824 SDValue NewV = V2Only ? V2 : V1; 5825 for (int i = 0; i != 8; ++i) { 5826 int Elt0 = MaskVals[i*2]; 5827 int Elt1 = MaskVals[i*2+1]; 5828 5829 // This word of the result is all undef, skip it. 5830 if (Elt0 < 0 && Elt1 < 0) 5831 continue; 5832 5833 // This word of the result is already in the correct place, skip it. 5834 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5835 continue; 5836 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5837 continue; 5838 5839 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5840 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5841 SDValue InsElt; 5842 5843 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5844 // using a single extract together, load it and store it. 5845 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5846 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5847 DAG.getIntPtrConstant(Elt1 / 2)); 5848 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5849 DAG.getIntPtrConstant(i)); 5850 continue; 5851 } 5852 5853 // If Elt1 is defined, extract it from the appropriate source. If the 5854 // source byte is not also odd, shift the extracted word left 8 bits 5855 // otherwise clear the bottom 8 bits if we need to do an or. 5856 if (Elt1 >= 0) { 5857 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5858 DAG.getIntPtrConstant(Elt1 / 2)); 5859 if ((Elt1 & 1) == 0) 5860 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5861 DAG.getConstant(8, 5862 TLI.getShiftAmountTy(InsElt.getValueType()))); 5863 else if (Elt0 >= 0) 5864 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5865 DAG.getConstant(0xFF00, MVT::i16)); 5866 } 5867 // If Elt0 is defined, extract it from the appropriate source. If the 5868 // source byte is not also even, shift the extracted word right 8 bits. If 5869 // Elt1 was also defined, OR the extracted values together before 5870 // inserting them in the result. 5871 if (Elt0 >= 0) { 5872 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5873 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5874 if ((Elt0 & 1) != 0) 5875 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5876 DAG.getConstant(8, 5877 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5878 else if (Elt1 >= 0) 5879 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5880 DAG.getConstant(0x00FF, MVT::i16)); 5881 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5882 : InsElt0; 5883 } 5884 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5885 DAG.getIntPtrConstant(i)); 5886 } 5887 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5888} 5889 5890/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5891/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5892/// done when every pair / quad of shuffle mask elements point to elements in 5893/// the right sequence. e.g. 5894/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5895static 5896SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5897 SelectionDAG &DAG, DebugLoc dl) { 5898 EVT VT = SVOp->getValueType(0); 5899 SDValue V1 = SVOp->getOperand(0); 5900 SDValue V2 = SVOp->getOperand(1); 5901 unsigned NumElems = VT.getVectorNumElements(); 5902 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5903 EVT NewVT; 5904 switch (VT.getSimpleVT().SimpleTy) { 5905 default: llvm_unreachable("Unexpected!"); 5906 case MVT::v4f32: NewVT = MVT::v2f64; break; 5907 case MVT::v4i32: NewVT = MVT::v2i64; break; 5908 case MVT::v8i16: NewVT = MVT::v4i32; break; 5909 case MVT::v16i8: NewVT = MVT::v4i32; break; 5910 } 5911 5912 int Scale = NumElems / NewWidth; 5913 SmallVector<int, 8> MaskVec; 5914 for (unsigned i = 0; i < NumElems; i += Scale) { 5915 int StartIdx = -1; 5916 for (int j = 0; j < Scale; ++j) { 5917 int EltIdx = SVOp->getMaskElt(i+j); 5918 if (EltIdx < 0) 5919 continue; 5920 if (StartIdx == -1) 5921 StartIdx = EltIdx - (EltIdx % Scale); 5922 if (EltIdx != StartIdx + j) 5923 return SDValue(); 5924 } 5925 if (StartIdx == -1) 5926 MaskVec.push_back(-1); 5927 else 5928 MaskVec.push_back(StartIdx / Scale); 5929 } 5930 5931 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5932 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5933 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5934} 5935 5936/// getVZextMovL - Return a zero-extending vector move low node. 5937/// 5938static SDValue getVZextMovL(EVT VT, EVT OpVT, 5939 SDValue SrcOp, SelectionDAG &DAG, 5940 const X86Subtarget *Subtarget, DebugLoc dl) { 5941 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5942 LoadSDNode *LD = NULL; 5943 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5944 LD = dyn_cast<LoadSDNode>(SrcOp); 5945 if (!LD) { 5946 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5947 // instead. 5948 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5949 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5950 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5951 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5952 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5953 // PR2108 5954 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5955 return DAG.getNode(ISD::BITCAST, dl, VT, 5956 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5957 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5958 OpVT, 5959 SrcOp.getOperand(0) 5960 .getOperand(0)))); 5961 } 5962 } 5963 } 5964 5965 return DAG.getNode(ISD::BITCAST, dl, VT, 5966 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5967 DAG.getNode(ISD::BITCAST, dl, 5968 OpVT, SrcOp))); 5969} 5970 5971/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5972/// which could not be matched by any known target speficic shuffle 5973static SDValue 5974LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5975 EVT VT = SVOp->getValueType(0); 5976 5977 unsigned NumElems = VT.getVectorNumElements(); 5978 unsigned NumLaneElems = NumElems / 2; 5979 5980 DebugLoc dl = SVOp->getDebugLoc(); 5981 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5982 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 5983 SDValue Shufs[2]; 5984 5985 SmallVector<int, 16> Mask; 5986 for (unsigned l = 0; l < 2; ++l) { 5987 // Build a shuffle mask for the output, discovering on the fly which 5988 // input vectors to use as shuffle operands (recorded in InputUsed). 5989 // If building a suitable shuffle vector proves too hard, then bail 5990 // out with useBuildVector set. 5991 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 5992 unsigned LaneStart = l * NumLaneElems; 5993 for (unsigned i = 0; i != NumLaneElems; ++i) { 5994 // The mask element. This indexes into the input. 5995 int Idx = SVOp->getMaskElt(i+LaneStart); 5996 if (Idx < 0) { 5997 // the mask element does not index into any input vector. 5998 Mask.push_back(-1); 5999 continue; 6000 } 6001 6002 // The input vector this mask element indexes into. 6003 int Input = Idx / NumLaneElems; 6004 6005 // Turn the index into an offset from the start of the input vector. 6006 Idx -= Input * NumLaneElems; 6007 6008 // Find or create a shuffle vector operand to hold this input. 6009 unsigned OpNo; 6010 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 6011 if (InputUsed[OpNo] == Input) 6012 // This input vector is already an operand. 6013 break; 6014 if (InputUsed[OpNo] < 0) { 6015 // Create a new operand for this input vector. 6016 InputUsed[OpNo] = Input; 6017 break; 6018 } 6019 } 6020 6021 if (OpNo >= array_lengthof(InputUsed)) { 6022 // More than two input vectors used! Give up. 6023 return SDValue(); 6024 } 6025 6026 // Add the mask index for the new shuffle vector. 6027 Mask.push_back(Idx + OpNo * NumLaneElems); 6028 } 6029 6030 if (InputUsed[0] < 0) { 6031 // No input vectors were used! The result is undefined. 6032 Shufs[l] = DAG.getUNDEF(NVT); 6033 } else { 6034 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6035 DAG.getConstant((InputUsed[0] % 2) * NumLaneElems, MVT::i32), 6036 DAG, dl); 6037 // If only one input was used, use an undefined vector for the other. 6038 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6039 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6040 DAG.getConstant((InputUsed[1] % 2) * NumLaneElems, MVT::i32), 6041 DAG, dl); 6042 // At least one input vector was used. Create a new shuffle vector. 6043 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6044 } 6045 6046 Mask.clear(); 6047 } 6048 6049 // Concatenate the result back 6050 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shufs[0], 6051 DAG.getConstant(0, MVT::i32), DAG, dl); 6052 return Insert128BitVector(V, Shufs[1],DAG.getConstant(NumLaneElems, MVT::i32), 6053 DAG, dl); 6054} 6055 6056/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6057/// 4 elements, and match them with several different shuffle types. 6058static SDValue 6059LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6060 SDValue V1 = SVOp->getOperand(0); 6061 SDValue V2 = SVOp->getOperand(1); 6062 DebugLoc dl = SVOp->getDebugLoc(); 6063 EVT VT = SVOp->getValueType(0); 6064 6065 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6066 6067 std::pair<int, int> Locs[4]; 6068 int Mask1[] = { -1, -1, -1, -1 }; 6069 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6070 6071 unsigned NumHi = 0; 6072 unsigned NumLo = 0; 6073 for (unsigned i = 0; i != 4; ++i) { 6074 int Idx = PermMask[i]; 6075 if (Idx < 0) { 6076 Locs[i] = std::make_pair(-1, -1); 6077 } else { 6078 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6079 if (Idx < 4) { 6080 Locs[i] = std::make_pair(0, NumLo); 6081 Mask1[NumLo] = Idx; 6082 NumLo++; 6083 } else { 6084 Locs[i] = std::make_pair(1, NumHi); 6085 if (2+NumHi < 4) 6086 Mask1[2+NumHi] = Idx; 6087 NumHi++; 6088 } 6089 } 6090 } 6091 6092 if (NumLo <= 2 && NumHi <= 2) { 6093 // If no more than two elements come from either vector. This can be 6094 // implemented with two shuffles. First shuffle gather the elements. 6095 // The second shuffle, which takes the first shuffle as both of its 6096 // vector operands, put the elements into the right order. 6097 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6098 6099 int Mask2[] = { -1, -1, -1, -1 }; 6100 6101 for (unsigned i = 0; i != 4; ++i) 6102 if (Locs[i].first != -1) { 6103 unsigned Idx = (i < 2) ? 0 : 4; 6104 Idx += Locs[i].first * 2 + Locs[i].second; 6105 Mask2[i] = Idx; 6106 } 6107 6108 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6109 } else if (NumLo == 3 || NumHi == 3) { 6110 // Otherwise, we must have three elements from one vector, call it X, and 6111 // one element from the other, call it Y. First, use a shufps to build an 6112 // intermediate vector with the one element from Y and the element from X 6113 // that will be in the same half in the final destination (the indexes don't 6114 // matter). Then, use a shufps to build the final vector, taking the half 6115 // containing the element from Y from the intermediate, and the other half 6116 // from X. 6117 if (NumHi == 3) { 6118 // Normalize it so the 3 elements come from V1. 6119 CommuteVectorShuffleMask(PermMask, 4); 6120 std::swap(V1, V2); 6121 } 6122 6123 // Find the element from V2. 6124 unsigned HiIndex; 6125 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6126 int Val = PermMask[HiIndex]; 6127 if (Val < 0) 6128 continue; 6129 if (Val >= 4) 6130 break; 6131 } 6132 6133 Mask1[0] = PermMask[HiIndex]; 6134 Mask1[1] = -1; 6135 Mask1[2] = PermMask[HiIndex^1]; 6136 Mask1[3] = -1; 6137 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6138 6139 if (HiIndex >= 2) { 6140 Mask1[0] = PermMask[0]; 6141 Mask1[1] = PermMask[1]; 6142 Mask1[2] = HiIndex & 1 ? 6 : 4; 6143 Mask1[3] = HiIndex & 1 ? 4 : 6; 6144 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6145 } else { 6146 Mask1[0] = HiIndex & 1 ? 2 : 0; 6147 Mask1[1] = HiIndex & 1 ? 0 : 2; 6148 Mask1[2] = PermMask[2]; 6149 Mask1[3] = PermMask[3]; 6150 if (Mask1[2] >= 0) 6151 Mask1[2] += 4; 6152 if (Mask1[3] >= 0) 6153 Mask1[3] += 4; 6154 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6155 } 6156 } 6157 6158 // Break it into (shuffle shuffle_hi, shuffle_lo). 6159 int LoMask[] = { -1, -1, -1, -1 }; 6160 int HiMask[] = { -1, -1, -1, -1 }; 6161 6162 int *MaskPtr = LoMask; 6163 unsigned MaskIdx = 0; 6164 unsigned LoIdx = 0; 6165 unsigned HiIdx = 2; 6166 for (unsigned i = 0; i != 4; ++i) { 6167 if (i == 2) { 6168 MaskPtr = HiMask; 6169 MaskIdx = 1; 6170 LoIdx = 0; 6171 HiIdx = 2; 6172 } 6173 int Idx = PermMask[i]; 6174 if (Idx < 0) { 6175 Locs[i] = std::make_pair(-1, -1); 6176 } else if (Idx < 4) { 6177 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6178 MaskPtr[LoIdx] = Idx; 6179 LoIdx++; 6180 } else { 6181 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6182 MaskPtr[HiIdx] = Idx; 6183 HiIdx++; 6184 } 6185 } 6186 6187 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6188 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6189 int MaskOps[] = { -1, -1, -1, -1 }; 6190 for (unsigned i = 0; i != 4; ++i) 6191 if (Locs[i].first != -1) 6192 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6193 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6194} 6195 6196static bool MayFoldVectorLoad(SDValue V) { 6197 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6198 V = V.getOperand(0); 6199 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6200 V = V.getOperand(0); 6201 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6202 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6203 // BUILD_VECTOR (load), undef 6204 V = V.getOperand(0); 6205 if (MayFoldLoad(V)) 6206 return true; 6207 return false; 6208} 6209 6210// FIXME: the version above should always be used. Since there's 6211// a bug where several vector shuffles can't be folded because the 6212// DAG is not updated during lowering and a node claims to have two 6213// uses while it only has one, use this version, and let isel match 6214// another instruction if the load really happens to have more than 6215// one use. Remove this version after this bug get fixed. 6216// rdar://8434668, PR8156 6217static bool RelaxedMayFoldVectorLoad(SDValue V) { 6218 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6219 V = V.getOperand(0); 6220 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6221 V = V.getOperand(0); 6222 if (ISD::isNormalLoad(V.getNode())) 6223 return true; 6224 return false; 6225} 6226 6227static 6228SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6229 EVT VT = Op.getValueType(); 6230 6231 // Canonizalize to v2f64. 6232 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6233 return DAG.getNode(ISD::BITCAST, dl, VT, 6234 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6235 V1, DAG)); 6236} 6237 6238static 6239SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6240 bool HasSSE2) { 6241 SDValue V1 = Op.getOperand(0); 6242 SDValue V2 = Op.getOperand(1); 6243 EVT VT = Op.getValueType(); 6244 6245 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6246 6247 if (HasSSE2 && VT == MVT::v2f64) 6248 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6249 6250 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6251 return DAG.getNode(ISD::BITCAST, dl, VT, 6252 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6253 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6254 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6255} 6256 6257static 6258SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6259 SDValue V1 = Op.getOperand(0); 6260 SDValue V2 = Op.getOperand(1); 6261 EVT VT = Op.getValueType(); 6262 6263 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6264 "unsupported shuffle type"); 6265 6266 if (V2.getOpcode() == ISD::UNDEF) 6267 V2 = V1; 6268 6269 // v4i32 or v4f32 6270 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6271} 6272 6273static 6274SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6275 SDValue V1 = Op.getOperand(0); 6276 SDValue V2 = Op.getOperand(1); 6277 EVT VT = Op.getValueType(); 6278 unsigned NumElems = VT.getVectorNumElements(); 6279 6280 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6281 // operand of these instructions is only memory, so check if there's a 6282 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6283 // same masks. 6284 bool CanFoldLoad = false; 6285 6286 // Trivial case, when V2 comes from a load. 6287 if (MayFoldVectorLoad(V2)) 6288 CanFoldLoad = true; 6289 6290 // When V1 is a load, it can be folded later into a store in isel, example: 6291 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6292 // turns into: 6293 // (MOVLPSmr addr:$src1, VR128:$src2) 6294 // So, recognize this potential and also use MOVLPS or MOVLPD 6295 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6296 CanFoldLoad = true; 6297 6298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6299 if (CanFoldLoad) { 6300 if (HasSSE2 && NumElems == 2) 6301 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6302 6303 if (NumElems == 4) 6304 // If we don't care about the second element, procede to use movss. 6305 if (SVOp->getMaskElt(1) != -1) 6306 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6307 } 6308 6309 // movl and movlp will both match v2i64, but v2i64 is never matched by 6310 // movl earlier because we make it strict to avoid messing with the movlp load 6311 // folding logic (see the code above getMOVLP call). Match it here then, 6312 // this is horrible, but will stay like this until we move all shuffle 6313 // matching to x86 specific nodes. Note that for the 1st condition all 6314 // types are matched with movsd. 6315 if (HasSSE2) { 6316 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6317 // as to remove this logic from here, as much as possible 6318 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6319 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6320 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6321 } 6322 6323 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6324 6325 // Invert the operand order and use SHUFPS to match it. 6326 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6327 getShuffleSHUFImmediate(SVOp), DAG); 6328} 6329 6330SDValue 6331X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6333 EVT VT = Op.getValueType(); 6334 DebugLoc dl = Op.getDebugLoc(); 6335 SDValue V1 = Op.getOperand(0); 6336 SDValue V2 = Op.getOperand(1); 6337 6338 if (isZeroShuffle(SVOp)) 6339 return getZeroVector(VT, Subtarget, DAG, dl); 6340 6341 // Handle splat operations 6342 if (SVOp->isSplat()) { 6343 unsigned NumElem = VT.getVectorNumElements(); 6344 int Size = VT.getSizeInBits(); 6345 6346 // Use vbroadcast whenever the splat comes from a foldable load 6347 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6348 if (Broadcast.getNode()) 6349 return Broadcast; 6350 6351 // Handle splats by matching through known shuffle masks 6352 if ((Size == 128 && NumElem <= 4) || 6353 (Size == 256 && NumElem < 8)) 6354 return SDValue(); 6355 6356 // All remaning splats are promoted to target supported vector shuffles. 6357 return PromoteSplat(SVOp, DAG); 6358 } 6359 6360 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6361 // do it! 6362 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6363 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6364 if (NewOp.getNode()) 6365 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6366 } else if ((VT == MVT::v4i32 || 6367 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6368 // FIXME: Figure out a cleaner way to do this. 6369 // Try to make use of movq to zero out the top part. 6370 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6371 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6372 if (NewOp.getNode()) { 6373 EVT NewVT = NewOp.getValueType(); 6374 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6375 NewVT, true, false)) 6376 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6377 DAG, Subtarget, dl); 6378 } 6379 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6380 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6381 if (NewOp.getNode()) { 6382 EVT NewVT = NewOp.getValueType(); 6383 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6384 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6385 DAG, Subtarget, dl); 6386 } 6387 } 6388 } 6389 return SDValue(); 6390} 6391 6392SDValue 6393X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6395 SDValue V1 = Op.getOperand(0); 6396 SDValue V2 = Op.getOperand(1); 6397 EVT VT = Op.getValueType(); 6398 DebugLoc dl = Op.getDebugLoc(); 6399 unsigned NumElems = VT.getVectorNumElements(); 6400 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6401 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6402 bool V1IsSplat = false; 6403 bool V2IsSplat = false; 6404 bool HasSSE2 = Subtarget->hasSSE2(); 6405 bool HasAVX = Subtarget->hasAVX(); 6406 bool HasAVX2 = Subtarget->hasAVX2(); 6407 MachineFunction &MF = DAG.getMachineFunction(); 6408 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6409 6410 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6411 6412 if (V1IsUndef && V2IsUndef) 6413 return DAG.getUNDEF(VT); 6414 6415 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6416 6417 // Vector shuffle lowering takes 3 steps: 6418 // 6419 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6420 // narrowing and commutation of operands should be handled. 6421 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6422 // shuffle nodes. 6423 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6424 // so the shuffle can be broken into other shuffles and the legalizer can 6425 // try the lowering again. 6426 // 6427 // The general idea is that no vector_shuffle operation should be left to 6428 // be matched during isel, all of them must be converted to a target specific 6429 // node here. 6430 6431 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6432 // narrowing and commutation of operands should be handled. The actual code 6433 // doesn't include all of those, work in progress... 6434 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6435 if (NewOp.getNode()) 6436 return NewOp; 6437 6438 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6439 6440 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6441 // unpckh_undef). Only use pshufd if speed is more important than size. 6442 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6443 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6444 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6445 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6446 6447 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6448 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6449 return getMOVDDup(Op, dl, V1, DAG); 6450 6451 if (isMOVHLPS_v_undef_Mask(M, VT)) 6452 return getMOVHighToLow(Op, dl, DAG); 6453 6454 // Use to match splats 6455 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6456 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6457 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6458 6459 if (isPSHUFDMask(M, VT)) { 6460 // The actual implementation will match the mask in the if above and then 6461 // during isel it can match several different instructions, not only pshufd 6462 // as its name says, sad but true, emulate the behavior for now... 6463 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6464 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6465 6466 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6467 6468 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6469 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6470 6471 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6472 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6473 6474 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6475 TargetMask, DAG); 6476 } 6477 6478 // Check if this can be converted into a logical shift. 6479 bool isLeft = false; 6480 unsigned ShAmt = 0; 6481 SDValue ShVal; 6482 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6483 if (isShift && ShVal.hasOneUse()) { 6484 // If the shifted value has multiple uses, it may be cheaper to use 6485 // v_set0 + movlhps or movhlps, etc. 6486 EVT EltVT = VT.getVectorElementType(); 6487 ShAmt *= EltVT.getSizeInBits(); 6488 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6489 } 6490 6491 if (isMOVLMask(M, VT)) { 6492 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6493 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6494 if (!isMOVLPMask(M, VT)) { 6495 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6496 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6497 6498 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6499 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6500 } 6501 } 6502 6503 // FIXME: fold these into legal mask. 6504 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6505 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6506 6507 if (isMOVHLPSMask(M, VT)) 6508 return getMOVHighToLow(Op, dl, DAG); 6509 6510 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6511 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6512 6513 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6514 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6515 6516 if (isMOVLPMask(M, VT)) 6517 return getMOVLP(Op, dl, DAG, HasSSE2); 6518 6519 if (ShouldXformToMOVHLPS(M, VT) || 6520 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6521 return CommuteVectorShuffle(SVOp, DAG); 6522 6523 if (isShift) { 6524 // No better options. Use a vshldq / vsrldq. 6525 EVT EltVT = VT.getVectorElementType(); 6526 ShAmt *= EltVT.getSizeInBits(); 6527 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6528 } 6529 6530 bool Commuted = false; 6531 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6532 // 1,1,1,1 -> v8i16 though. 6533 V1IsSplat = isSplatVector(V1.getNode()); 6534 V2IsSplat = isSplatVector(V2.getNode()); 6535 6536 // Canonicalize the splat or undef, if present, to be on the RHS. 6537 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6538 CommuteVectorShuffleMask(M, NumElems); 6539 std::swap(V1, V2); 6540 std::swap(V1IsSplat, V2IsSplat); 6541 Commuted = true; 6542 } 6543 6544 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6545 // Shuffling low element of v1 into undef, just return v1. 6546 if (V2IsUndef) 6547 return V1; 6548 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6549 // the instruction selector will not match, so get a canonical MOVL with 6550 // swapped operands to undo the commute. 6551 return getMOVL(DAG, dl, VT, V2, V1); 6552 } 6553 6554 if (isUNPCKLMask(M, VT, HasAVX2)) 6555 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6556 6557 if (isUNPCKHMask(M, VT, HasAVX2)) 6558 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6559 6560 if (V2IsSplat) { 6561 // Normalize mask so all entries that point to V2 points to its first 6562 // element then try to match unpck{h|l} again. If match, return a 6563 // new vector_shuffle with the corrected mask.p 6564 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6565 NormalizeMask(NewMask, NumElems); 6566 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) { 6567 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6568 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) { 6569 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6570 } 6571 } 6572 6573 if (Commuted) { 6574 // Commute is back and try unpck* again. 6575 // FIXME: this seems wrong. 6576 CommuteVectorShuffleMask(M, NumElems); 6577 std::swap(V1, V2); 6578 std::swap(V1IsSplat, V2IsSplat); 6579 Commuted = false; 6580 6581 if (isUNPCKLMask(M, VT, HasAVX2)) 6582 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6583 6584 if (isUNPCKHMask(M, VT, HasAVX2)) 6585 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6586 } 6587 6588 // Normalize the node to match x86 shuffle ops if needed 6589 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6590 return CommuteVectorShuffle(SVOp, DAG); 6591 6592 // The checks below are all present in isShuffleMaskLegal, but they are 6593 // inlined here right now to enable us to directly emit target specific 6594 // nodes, and remove one by one until they don't return Op anymore. 6595 6596 if (isPALIGNRMask(M, VT, Subtarget)) 6597 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6598 getShufflePALIGNRImmediate(SVOp), 6599 DAG); 6600 6601 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6602 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6603 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6604 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6605 } 6606 6607 if (isPSHUFHWMask(M, VT)) 6608 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6609 getShufflePSHUFHWImmediate(SVOp), 6610 DAG); 6611 6612 if (isPSHUFLWMask(M, VT)) 6613 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6614 getShufflePSHUFLWImmediate(SVOp), 6615 DAG); 6616 6617 if (isSHUFPMask(M, VT, HasAVX)) 6618 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6619 getShuffleSHUFImmediate(SVOp), DAG); 6620 6621 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6622 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6623 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6624 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6625 6626 //===--------------------------------------------------------------------===// 6627 // Generate target specific nodes for 128 or 256-bit shuffles only 6628 // supported in the AVX instruction set. 6629 // 6630 6631 // Handle VMOVDDUPY permutations 6632 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6633 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6634 6635 // Handle VPERMILPS/D* permutations 6636 if (isVPERMILPMask(M, VT, HasAVX)) { 6637 if (HasAVX2 && VT == MVT::v8i32) 6638 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6639 getShuffleSHUFImmediate(SVOp), DAG); 6640 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6641 getShuffleSHUFImmediate(SVOp), DAG); 6642 } 6643 6644 // Handle VPERM2F128/VPERM2I128 permutations 6645 if (isVPERM2X128Mask(M, VT, HasAVX)) 6646 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6647 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6648 6649 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG); 6650 if (BlendOp.getNode()) 6651 return BlendOp; 6652 6653 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6654 SmallVector<SDValue, 8> permclMask; 6655 for (unsigned i = 0; i != 8; ++i) { 6656 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6657 } 6658 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6659 &permclMask[0], 8); 6660 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6661 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6662 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6663 } 6664 6665 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6666 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 6667 getShuffleCLImmediate(SVOp), DAG); 6668 6669 6670 //===--------------------------------------------------------------------===// 6671 // Since no target specific shuffle was selected for this generic one, 6672 // lower it into other known shuffles. FIXME: this isn't true yet, but 6673 // this is the plan. 6674 // 6675 6676 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6677 if (VT == MVT::v8i16) { 6678 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6679 if (NewOp.getNode()) 6680 return NewOp; 6681 } 6682 6683 if (VT == MVT::v16i8) { 6684 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6685 if (NewOp.getNode()) 6686 return NewOp; 6687 } 6688 6689 // Handle all 128-bit wide vectors with 4 elements, and match them with 6690 // several different shuffle types. 6691 if (NumElems == 4 && VT.getSizeInBits() == 128) 6692 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6693 6694 // Handle general 256-bit shuffles 6695 if (VT.is256BitVector()) 6696 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6697 6698 return SDValue(); 6699} 6700 6701SDValue 6702X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6703 SelectionDAG &DAG) const { 6704 EVT VT = Op.getValueType(); 6705 DebugLoc dl = Op.getDebugLoc(); 6706 6707 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6708 return SDValue(); 6709 6710 if (VT.getSizeInBits() == 8) { 6711 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6712 Op.getOperand(0), Op.getOperand(1)); 6713 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6714 DAG.getValueType(VT)); 6715 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6716 } else if (VT.getSizeInBits() == 16) { 6717 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6718 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6719 if (Idx == 0) 6720 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6721 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6722 DAG.getNode(ISD::BITCAST, dl, 6723 MVT::v4i32, 6724 Op.getOperand(0)), 6725 Op.getOperand(1))); 6726 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6727 Op.getOperand(0), Op.getOperand(1)); 6728 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6729 DAG.getValueType(VT)); 6730 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6731 } else if (VT == MVT::f32) { 6732 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6733 // the result back to FR32 register. It's only worth matching if the 6734 // result has a single use which is a store or a bitcast to i32. And in 6735 // the case of a store, it's not worth it if the index is a constant 0, 6736 // because a MOVSSmr can be used instead, which is smaller and faster. 6737 if (!Op.hasOneUse()) 6738 return SDValue(); 6739 SDNode *User = *Op.getNode()->use_begin(); 6740 if ((User->getOpcode() != ISD::STORE || 6741 (isa<ConstantSDNode>(Op.getOperand(1)) && 6742 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6743 (User->getOpcode() != ISD::BITCAST || 6744 User->getValueType(0) != MVT::i32)) 6745 return SDValue(); 6746 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6747 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6748 Op.getOperand(0)), 6749 Op.getOperand(1)); 6750 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6751 } else if (VT == MVT::i32 || VT == MVT::i64) { 6752 // ExtractPS/pextrq works with constant index. 6753 if (isa<ConstantSDNode>(Op.getOperand(1))) 6754 return Op; 6755 } 6756 return SDValue(); 6757} 6758 6759 6760SDValue 6761X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6762 SelectionDAG &DAG) const { 6763 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6764 return SDValue(); 6765 6766 SDValue Vec = Op.getOperand(0); 6767 EVT VecVT = Vec.getValueType(); 6768 6769 // If this is a 256-bit vector result, first extract the 128-bit vector and 6770 // then extract the element from the 128-bit vector. 6771 if (VecVT.getSizeInBits() == 256) { 6772 DebugLoc dl = Op.getNode()->getDebugLoc(); 6773 unsigned NumElems = VecVT.getVectorNumElements(); 6774 SDValue Idx = Op.getOperand(1); 6775 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6776 6777 // Get the 128-bit vector. 6778 bool Upper = IdxVal >= NumElems/2; 6779 Vec = Extract128BitVector(Vec, 6780 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6781 6782 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6783 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6784 } 6785 6786 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6787 6788 if (Subtarget->hasSSE41()) { 6789 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6790 if (Res.getNode()) 6791 return Res; 6792 } 6793 6794 EVT VT = Op.getValueType(); 6795 DebugLoc dl = Op.getDebugLoc(); 6796 // TODO: handle v16i8. 6797 if (VT.getSizeInBits() == 16) { 6798 SDValue Vec = Op.getOperand(0); 6799 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6800 if (Idx == 0) 6801 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6802 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6803 DAG.getNode(ISD::BITCAST, dl, 6804 MVT::v4i32, Vec), 6805 Op.getOperand(1))); 6806 // Transform it so it match pextrw which produces a 32-bit result. 6807 EVT EltVT = MVT::i32; 6808 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6809 Op.getOperand(0), Op.getOperand(1)); 6810 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6811 DAG.getValueType(VT)); 6812 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6813 } else if (VT.getSizeInBits() == 32) { 6814 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6815 if (Idx == 0) 6816 return Op; 6817 6818 // SHUFPS the element to the lowest double word, then movss. 6819 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6820 EVT VVT = Op.getOperand(0).getValueType(); 6821 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6822 DAG.getUNDEF(VVT), Mask); 6823 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6824 DAG.getIntPtrConstant(0)); 6825 } else if (VT.getSizeInBits() == 64) { 6826 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6827 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6828 // to match extract_elt for f64. 6829 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6830 if (Idx == 0) 6831 return Op; 6832 6833 // UNPCKHPD the element to the lowest double word, then movsd. 6834 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6835 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6836 int Mask[2] = { 1, -1 }; 6837 EVT VVT = Op.getOperand(0).getValueType(); 6838 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6839 DAG.getUNDEF(VVT), Mask); 6840 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6841 DAG.getIntPtrConstant(0)); 6842 } 6843 6844 return SDValue(); 6845} 6846 6847SDValue 6848X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6849 SelectionDAG &DAG) const { 6850 EVT VT = Op.getValueType(); 6851 EVT EltVT = VT.getVectorElementType(); 6852 DebugLoc dl = Op.getDebugLoc(); 6853 6854 SDValue N0 = Op.getOperand(0); 6855 SDValue N1 = Op.getOperand(1); 6856 SDValue N2 = Op.getOperand(2); 6857 6858 if (VT.getSizeInBits() == 256) 6859 return SDValue(); 6860 6861 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6862 isa<ConstantSDNode>(N2)) { 6863 unsigned Opc; 6864 if (VT == MVT::v8i16) 6865 Opc = X86ISD::PINSRW; 6866 else if (VT == MVT::v16i8) 6867 Opc = X86ISD::PINSRB; 6868 else 6869 Opc = X86ISD::PINSRB; 6870 6871 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6872 // argument. 6873 if (N1.getValueType() != MVT::i32) 6874 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6875 if (N2.getValueType() != MVT::i32) 6876 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6877 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6878 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6879 // Bits [7:6] of the constant are the source select. This will always be 6880 // zero here. The DAG Combiner may combine an extract_elt index into these 6881 // bits. For example (insert (extract, 3), 2) could be matched by putting 6882 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6883 // Bits [5:4] of the constant are the destination select. This is the 6884 // value of the incoming immediate. 6885 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6886 // combine either bitwise AND or insert of float 0.0 to set these bits. 6887 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6888 // Create this as a scalar to vector.. 6889 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6890 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6891 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6892 isa<ConstantSDNode>(N2)) { 6893 // PINSR* works with constant index. 6894 return Op; 6895 } 6896 return SDValue(); 6897} 6898 6899SDValue 6900X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6901 EVT VT = Op.getValueType(); 6902 EVT EltVT = VT.getVectorElementType(); 6903 6904 DebugLoc dl = Op.getDebugLoc(); 6905 SDValue N0 = Op.getOperand(0); 6906 SDValue N1 = Op.getOperand(1); 6907 SDValue N2 = Op.getOperand(2); 6908 6909 // If this is a 256-bit vector result, first extract the 128-bit vector, 6910 // insert the element into the extracted half and then place it back. 6911 if (VT.getSizeInBits() == 256) { 6912 if (!isa<ConstantSDNode>(N2)) 6913 return SDValue(); 6914 6915 // Get the desired 128-bit vector half. 6916 unsigned NumElems = VT.getVectorNumElements(); 6917 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6918 bool Upper = IdxVal >= NumElems/2; 6919 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6920 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6921 6922 // Insert the element into the desired half. 6923 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6924 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6925 6926 // Insert the changed part back to the 256-bit vector 6927 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6928 } 6929 6930 if (Subtarget->hasSSE41()) 6931 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6932 6933 if (EltVT == MVT::i8) 6934 return SDValue(); 6935 6936 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6937 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6938 // as its second argument. 6939 if (N1.getValueType() != MVT::i32) 6940 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6941 if (N2.getValueType() != MVT::i32) 6942 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6943 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6944 } 6945 return SDValue(); 6946} 6947 6948SDValue 6949X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6950 LLVMContext *Context = DAG.getContext(); 6951 DebugLoc dl = Op.getDebugLoc(); 6952 EVT OpVT = Op.getValueType(); 6953 6954 // If this is a 256-bit vector result, first insert into a 128-bit 6955 // vector and then insert into the 256-bit vector. 6956 if (OpVT.getSizeInBits() > 128) { 6957 // Insert into a 128-bit vector. 6958 EVT VT128 = EVT::getVectorVT(*Context, 6959 OpVT.getVectorElementType(), 6960 OpVT.getVectorNumElements() / 2); 6961 6962 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6963 6964 // Insert the 128-bit vector. 6965 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6966 DAG.getConstant(0, MVT::i32), 6967 DAG, dl); 6968 } 6969 6970 if (Op.getValueType() == MVT::v1i64 && 6971 Op.getOperand(0).getValueType() == MVT::i64) 6972 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6973 6974 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6975 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6976 "Expected an SSE type!"); 6977 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6978 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6979} 6980 6981// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6982// a simple subregister reference or explicit instructions to grab 6983// upper bits of a vector. 6984SDValue 6985X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6986 if (Subtarget->hasAVX()) { 6987 DebugLoc dl = Op.getNode()->getDebugLoc(); 6988 SDValue Vec = Op.getNode()->getOperand(0); 6989 SDValue Idx = Op.getNode()->getOperand(1); 6990 6991 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6992 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6993 return Extract128BitVector(Vec, Idx, DAG, dl); 6994 } 6995 } 6996 return SDValue(); 6997} 6998 6999// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7000// simple superregister reference or explicit instructions to insert 7001// the upper bits of a vector. 7002SDValue 7003X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7004 if (Subtarget->hasAVX()) { 7005 DebugLoc dl = Op.getNode()->getDebugLoc(); 7006 SDValue Vec = Op.getNode()->getOperand(0); 7007 SDValue SubVec = Op.getNode()->getOperand(1); 7008 SDValue Idx = Op.getNode()->getOperand(2); 7009 7010 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7011 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7012 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7013 } 7014 } 7015 return SDValue(); 7016} 7017 7018// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7019// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7020// one of the above mentioned nodes. It has to be wrapped because otherwise 7021// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7022// be used to form addressing mode. These wrapped nodes will be selected 7023// into MOV32ri. 7024SDValue 7025X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7026 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7027 7028 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7029 // global base reg. 7030 unsigned char OpFlag = 0; 7031 unsigned WrapperKind = X86ISD::Wrapper; 7032 CodeModel::Model M = getTargetMachine().getCodeModel(); 7033 7034 if (Subtarget->isPICStyleRIPRel() && 7035 (M == CodeModel::Small || M == CodeModel::Kernel)) 7036 WrapperKind = X86ISD::WrapperRIP; 7037 else if (Subtarget->isPICStyleGOT()) 7038 OpFlag = X86II::MO_GOTOFF; 7039 else if (Subtarget->isPICStyleStubPIC()) 7040 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7041 7042 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7043 CP->getAlignment(), 7044 CP->getOffset(), OpFlag); 7045 DebugLoc DL = CP->getDebugLoc(); 7046 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7047 // With PIC, the address is actually $g + Offset. 7048 if (OpFlag) { 7049 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7050 DAG.getNode(X86ISD::GlobalBaseReg, 7051 DebugLoc(), getPointerTy()), 7052 Result); 7053 } 7054 7055 return Result; 7056} 7057 7058SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7059 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7060 7061 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7062 // global base reg. 7063 unsigned char OpFlag = 0; 7064 unsigned WrapperKind = X86ISD::Wrapper; 7065 CodeModel::Model M = getTargetMachine().getCodeModel(); 7066 7067 if (Subtarget->isPICStyleRIPRel() && 7068 (M == CodeModel::Small || M == CodeModel::Kernel)) 7069 WrapperKind = X86ISD::WrapperRIP; 7070 else if (Subtarget->isPICStyleGOT()) 7071 OpFlag = X86II::MO_GOTOFF; 7072 else if (Subtarget->isPICStyleStubPIC()) 7073 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7074 7075 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7076 OpFlag); 7077 DebugLoc DL = JT->getDebugLoc(); 7078 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7079 7080 // With PIC, the address is actually $g + Offset. 7081 if (OpFlag) 7082 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7083 DAG.getNode(X86ISD::GlobalBaseReg, 7084 DebugLoc(), getPointerTy()), 7085 Result); 7086 7087 return Result; 7088} 7089 7090SDValue 7091X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7092 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7093 7094 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7095 // global base reg. 7096 unsigned char OpFlag = 0; 7097 unsigned WrapperKind = X86ISD::Wrapper; 7098 CodeModel::Model M = getTargetMachine().getCodeModel(); 7099 7100 if (Subtarget->isPICStyleRIPRel() && 7101 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7102 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7103 OpFlag = X86II::MO_GOTPCREL; 7104 WrapperKind = X86ISD::WrapperRIP; 7105 } else if (Subtarget->isPICStyleGOT()) { 7106 OpFlag = X86II::MO_GOT; 7107 } else if (Subtarget->isPICStyleStubPIC()) { 7108 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7109 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7110 OpFlag = X86II::MO_DARWIN_NONLAZY; 7111 } 7112 7113 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7114 7115 DebugLoc DL = Op.getDebugLoc(); 7116 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7117 7118 7119 // With PIC, the address is actually $g + Offset. 7120 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7121 !Subtarget->is64Bit()) { 7122 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7123 DAG.getNode(X86ISD::GlobalBaseReg, 7124 DebugLoc(), getPointerTy()), 7125 Result); 7126 } 7127 7128 // For symbols that require a load from a stub to get the address, emit the 7129 // load. 7130 if (isGlobalStubReference(OpFlag)) 7131 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7132 MachinePointerInfo::getGOT(), false, false, false, 0); 7133 7134 return Result; 7135} 7136 7137SDValue 7138X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7139 // Create the TargetBlockAddressAddress node. 7140 unsigned char OpFlags = 7141 Subtarget->ClassifyBlockAddressReference(); 7142 CodeModel::Model M = getTargetMachine().getCodeModel(); 7143 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7144 DebugLoc dl = Op.getDebugLoc(); 7145 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7146 /*isTarget=*/true, OpFlags); 7147 7148 if (Subtarget->isPICStyleRIPRel() && 7149 (M == CodeModel::Small || M == CodeModel::Kernel)) 7150 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7151 else 7152 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7153 7154 // With PIC, the address is actually $g + Offset. 7155 if (isGlobalRelativeToPICBase(OpFlags)) { 7156 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7157 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7158 Result); 7159 } 7160 7161 return Result; 7162} 7163 7164SDValue 7165X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7166 int64_t Offset, 7167 SelectionDAG &DAG) const { 7168 // Create the TargetGlobalAddress node, folding in the constant 7169 // offset if it is legal. 7170 unsigned char OpFlags = 7171 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7172 CodeModel::Model M = getTargetMachine().getCodeModel(); 7173 SDValue Result; 7174 if (OpFlags == X86II::MO_NO_FLAG && 7175 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7176 // A direct static reference to a global. 7177 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7178 Offset = 0; 7179 } else { 7180 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7181 } 7182 7183 if (Subtarget->isPICStyleRIPRel() && 7184 (M == CodeModel::Small || M == CodeModel::Kernel)) 7185 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7186 else 7187 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7188 7189 // With PIC, the address is actually $g + Offset. 7190 if (isGlobalRelativeToPICBase(OpFlags)) { 7191 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7192 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7193 Result); 7194 } 7195 7196 // For globals that require a load from a stub to get the address, emit the 7197 // load. 7198 if (isGlobalStubReference(OpFlags)) 7199 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7200 MachinePointerInfo::getGOT(), false, false, false, 0); 7201 7202 // If there was a non-zero offset that we didn't fold, create an explicit 7203 // addition for it. 7204 if (Offset != 0) 7205 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7206 DAG.getConstant(Offset, getPointerTy())); 7207 7208 return Result; 7209} 7210 7211SDValue 7212X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7213 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7214 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7215 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7216} 7217 7218static SDValue 7219GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7220 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7221 unsigned char OperandFlags) { 7222 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7223 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7224 DebugLoc dl = GA->getDebugLoc(); 7225 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7226 GA->getValueType(0), 7227 GA->getOffset(), 7228 OperandFlags); 7229 if (InFlag) { 7230 SDValue Ops[] = { Chain, TGA, *InFlag }; 7231 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7232 } else { 7233 SDValue Ops[] = { Chain, TGA }; 7234 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7235 } 7236 7237 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7238 MFI->setAdjustsStack(true); 7239 7240 SDValue Flag = Chain.getValue(1); 7241 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7242} 7243 7244// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7245static SDValue 7246LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7247 const EVT PtrVT) { 7248 SDValue InFlag; 7249 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7250 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7251 DAG.getNode(X86ISD::GlobalBaseReg, 7252 DebugLoc(), PtrVT), InFlag); 7253 InFlag = Chain.getValue(1); 7254 7255 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7256} 7257 7258// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7259static SDValue 7260LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7261 const EVT PtrVT) { 7262 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7263 X86::RAX, X86II::MO_TLSGD); 7264} 7265 7266// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7267// "local exec" model. 7268static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7269 const EVT PtrVT, TLSModel::Model model, 7270 bool is64Bit) { 7271 DebugLoc dl = GA->getDebugLoc(); 7272 7273 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7274 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7275 is64Bit ? 257 : 256)); 7276 7277 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7278 DAG.getIntPtrConstant(0), 7279 MachinePointerInfo(Ptr), 7280 false, false, false, 0); 7281 7282 unsigned char OperandFlags = 0; 7283 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7284 // initialexec. 7285 unsigned WrapperKind = X86ISD::Wrapper; 7286 if (model == TLSModel::LocalExec) { 7287 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7288 } else if (is64Bit) { 7289 assert(model == TLSModel::InitialExec); 7290 OperandFlags = X86II::MO_GOTTPOFF; 7291 WrapperKind = X86ISD::WrapperRIP; 7292 } else { 7293 assert(model == TLSModel::InitialExec); 7294 OperandFlags = X86II::MO_INDNTPOFF; 7295 } 7296 7297 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7298 // exec) 7299 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7300 GA->getValueType(0), 7301 GA->getOffset(), OperandFlags); 7302 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7303 7304 if (model == TLSModel::InitialExec) 7305 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7306 MachinePointerInfo::getGOT(), false, false, false, 0); 7307 7308 // The address of the thread local variable is the add of the thread 7309 // pointer with the offset of the variable. 7310 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7311} 7312 7313SDValue 7314X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7315 7316 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7317 const GlobalValue *GV = GA->getGlobal(); 7318 7319 if (Subtarget->isTargetELF()) { 7320 // TODO: implement the "local dynamic" model 7321 // TODO: implement the "initial exec"model for pic executables 7322 7323 // If GV is an alias then use the aliasee for determining 7324 // thread-localness. 7325 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7326 GV = GA->resolveAliasedGlobal(false); 7327 7328 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7329 7330 switch (model) { 7331 case TLSModel::GeneralDynamic: 7332 case TLSModel::LocalDynamic: // not implemented 7333 if (Subtarget->is64Bit()) 7334 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7335 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7336 7337 case TLSModel::InitialExec: 7338 case TLSModel::LocalExec: 7339 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7340 Subtarget->is64Bit()); 7341 } 7342 } else if (Subtarget->isTargetDarwin()) { 7343 // Darwin only has one model of TLS. Lower to that. 7344 unsigned char OpFlag = 0; 7345 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7346 X86ISD::WrapperRIP : X86ISD::Wrapper; 7347 7348 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7349 // global base reg. 7350 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7351 !Subtarget->is64Bit(); 7352 if (PIC32) 7353 OpFlag = X86II::MO_TLVP_PIC_BASE; 7354 else 7355 OpFlag = X86II::MO_TLVP; 7356 DebugLoc DL = Op.getDebugLoc(); 7357 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7358 GA->getValueType(0), 7359 GA->getOffset(), OpFlag); 7360 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7361 7362 // With PIC32, the address is actually $g + Offset. 7363 if (PIC32) 7364 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7365 DAG.getNode(X86ISD::GlobalBaseReg, 7366 DebugLoc(), getPointerTy()), 7367 Offset); 7368 7369 // Lowering the machine isd will make sure everything is in the right 7370 // location. 7371 SDValue Chain = DAG.getEntryNode(); 7372 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7373 SDValue Args[] = { Chain, Offset }; 7374 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7375 7376 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7377 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7378 MFI->setAdjustsStack(true); 7379 7380 // And our return value (tls address) is in the standard call return value 7381 // location. 7382 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7383 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7384 Chain.getValue(1)); 7385 } else if (Subtarget->isTargetWindows()) { 7386 // Just use the implicit TLS architecture 7387 // Need to generate someting similar to: 7388 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7389 // ; from TEB 7390 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7391 // mov rcx, qword [rdx+rcx*8] 7392 // mov eax, .tls$:tlsvar 7393 // [rax+rcx] contains the address 7394 // Windows 64bit: gs:0x58 7395 // Windows 32bit: fs:__tls_array 7396 7397 // If GV is an alias then use the aliasee for determining 7398 // thread-localness. 7399 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7400 GV = GA->resolveAliasedGlobal(false); 7401 DebugLoc dl = GA->getDebugLoc(); 7402 SDValue Chain = DAG.getEntryNode(); 7403 7404 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7405 // %gs:0x58 (64-bit). 7406 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7407 ? Type::getInt8PtrTy(*DAG.getContext(), 7408 256) 7409 : Type::getInt32PtrTy(*DAG.getContext(), 7410 257)); 7411 7412 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7413 Subtarget->is64Bit() 7414 ? DAG.getIntPtrConstant(0x58) 7415 : DAG.getExternalSymbol("_tls_array", 7416 getPointerTy()), 7417 MachinePointerInfo(Ptr), 7418 false, false, false, 0); 7419 7420 // Load the _tls_index variable 7421 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7422 if (Subtarget->is64Bit()) 7423 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7424 IDX, MachinePointerInfo(), MVT::i32, 7425 false, false, 0); 7426 else 7427 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7428 false, false, false, 0); 7429 7430 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7431 getPointerTy()); 7432 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7433 7434 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7435 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7436 false, false, false, 0); 7437 7438 // Get the offset of start of .tls section 7439 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7440 GA->getValueType(0), 7441 GA->getOffset(), X86II::MO_SECREL); 7442 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7443 7444 // The address of the thread local variable is the add of the thread 7445 // pointer with the offset of the variable. 7446 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7447 } 7448 7449 llvm_unreachable("TLS not implemented for this target."); 7450} 7451 7452 7453/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7454/// and take a 2 x i32 value to shift plus a shift amount. 7455SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7456 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7457 EVT VT = Op.getValueType(); 7458 unsigned VTBits = VT.getSizeInBits(); 7459 DebugLoc dl = Op.getDebugLoc(); 7460 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7461 SDValue ShOpLo = Op.getOperand(0); 7462 SDValue ShOpHi = Op.getOperand(1); 7463 SDValue ShAmt = Op.getOperand(2); 7464 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7465 DAG.getConstant(VTBits - 1, MVT::i8)) 7466 : DAG.getConstant(0, VT); 7467 7468 SDValue Tmp2, Tmp3; 7469 if (Op.getOpcode() == ISD::SHL_PARTS) { 7470 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7471 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7472 } else { 7473 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7474 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7475 } 7476 7477 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7478 DAG.getConstant(VTBits, MVT::i8)); 7479 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7480 AndNode, DAG.getConstant(0, MVT::i8)); 7481 7482 SDValue Hi, Lo; 7483 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7484 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7485 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7486 7487 if (Op.getOpcode() == ISD::SHL_PARTS) { 7488 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7489 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7490 } else { 7491 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7492 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7493 } 7494 7495 SDValue Ops[2] = { Lo, Hi }; 7496 return DAG.getMergeValues(Ops, 2, dl); 7497} 7498 7499SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7500 SelectionDAG &DAG) const { 7501 EVT SrcVT = Op.getOperand(0).getValueType(); 7502 7503 if (SrcVT.isVector()) 7504 return SDValue(); 7505 7506 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7507 "Unknown SINT_TO_FP to lower!"); 7508 7509 // These are really Legal; return the operand so the caller accepts it as 7510 // Legal. 7511 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7512 return Op; 7513 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7514 Subtarget->is64Bit()) { 7515 return Op; 7516 } 7517 7518 DebugLoc dl = Op.getDebugLoc(); 7519 unsigned Size = SrcVT.getSizeInBits()/8; 7520 MachineFunction &MF = DAG.getMachineFunction(); 7521 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7522 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7523 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7524 StackSlot, 7525 MachinePointerInfo::getFixedStack(SSFI), 7526 false, false, 0); 7527 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7528} 7529 7530SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7531 SDValue StackSlot, 7532 SelectionDAG &DAG) const { 7533 // Build the FILD 7534 DebugLoc DL = Op.getDebugLoc(); 7535 SDVTList Tys; 7536 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7537 if (useSSE) 7538 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7539 else 7540 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7541 7542 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7543 7544 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7545 MachineMemOperand *MMO; 7546 if (FI) { 7547 int SSFI = FI->getIndex(); 7548 MMO = 7549 DAG.getMachineFunction() 7550 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7551 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7552 } else { 7553 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7554 StackSlot = StackSlot.getOperand(1); 7555 } 7556 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7557 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7558 X86ISD::FILD, DL, 7559 Tys, Ops, array_lengthof(Ops), 7560 SrcVT, MMO); 7561 7562 if (useSSE) { 7563 Chain = Result.getValue(1); 7564 SDValue InFlag = Result.getValue(2); 7565 7566 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7567 // shouldn't be necessary except that RFP cannot be live across 7568 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7569 MachineFunction &MF = DAG.getMachineFunction(); 7570 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7571 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7572 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7573 Tys = DAG.getVTList(MVT::Other); 7574 SDValue Ops[] = { 7575 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7576 }; 7577 MachineMemOperand *MMO = 7578 DAG.getMachineFunction() 7579 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7580 MachineMemOperand::MOStore, SSFISize, SSFISize); 7581 7582 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7583 Ops, array_lengthof(Ops), 7584 Op.getValueType(), MMO); 7585 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7586 MachinePointerInfo::getFixedStack(SSFI), 7587 false, false, false, 0); 7588 } 7589 7590 return Result; 7591} 7592 7593// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7594SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7595 SelectionDAG &DAG) const { 7596 // This algorithm is not obvious. Here it is what we're trying to output: 7597 /* 7598 movq %rax, %xmm0 7599 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7600 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7601 #ifdef __SSE3__ 7602 haddpd %xmm0, %xmm0 7603 #else 7604 pshufd $0x4e, %xmm0, %xmm1 7605 addpd %xmm1, %xmm0 7606 #endif 7607 */ 7608 7609 DebugLoc dl = Op.getDebugLoc(); 7610 LLVMContext *Context = DAG.getContext(); 7611 7612 // Build some magic constants. 7613 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7614 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7615 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7616 7617 SmallVector<Constant*,2> CV1; 7618 CV1.push_back( 7619 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7620 CV1.push_back( 7621 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7622 Constant *C1 = ConstantVector::get(CV1); 7623 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7624 7625 // Load the 64-bit value into an XMM register. 7626 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7627 Op.getOperand(0)); 7628 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7629 MachinePointerInfo::getConstantPool(), 7630 false, false, false, 16); 7631 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7632 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7633 CLod0); 7634 7635 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7636 MachinePointerInfo::getConstantPool(), 7637 false, false, false, 16); 7638 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7639 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7640 SDValue Result; 7641 7642 if (Subtarget->hasSSE3()) { 7643 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7644 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7645 } else { 7646 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7647 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7648 S2F, 0x4E, DAG); 7649 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7650 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7651 Sub); 7652 } 7653 7654 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7655 DAG.getIntPtrConstant(0)); 7656} 7657 7658// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7659SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7660 SelectionDAG &DAG) const { 7661 DebugLoc dl = Op.getDebugLoc(); 7662 // FP constant to bias correct the final result. 7663 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7664 MVT::f64); 7665 7666 // Load the 32-bit value into an XMM register. 7667 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7668 Op.getOperand(0)); 7669 7670 // Zero out the upper parts of the register. 7671 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7672 7673 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7675 DAG.getIntPtrConstant(0)); 7676 7677 // Or the load with the bias. 7678 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7679 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7680 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7681 MVT::v2f64, Load)), 7682 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7683 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7684 MVT::v2f64, Bias))); 7685 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7686 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7687 DAG.getIntPtrConstant(0)); 7688 7689 // Subtract the bias. 7690 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7691 7692 // Handle final rounding. 7693 EVT DestVT = Op.getValueType(); 7694 7695 if (DestVT.bitsLT(MVT::f64)) { 7696 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7697 DAG.getIntPtrConstant(0)); 7698 } else if (DestVT.bitsGT(MVT::f64)) { 7699 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7700 } 7701 7702 // Handle final rounding. 7703 return Sub; 7704} 7705 7706SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7707 SelectionDAG &DAG) const { 7708 SDValue N0 = Op.getOperand(0); 7709 DebugLoc dl = Op.getDebugLoc(); 7710 7711 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7712 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7713 // the optimization here. 7714 if (DAG.SignBitIsZero(N0)) 7715 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7716 7717 EVT SrcVT = N0.getValueType(); 7718 EVT DstVT = Op.getValueType(); 7719 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7720 return LowerUINT_TO_FP_i64(Op, DAG); 7721 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7722 return LowerUINT_TO_FP_i32(Op, DAG); 7723 else if (Subtarget->is64Bit() && 7724 SrcVT == MVT::i64 && DstVT == MVT::f32) 7725 return SDValue(); 7726 7727 // Make a 64-bit buffer, and use it to build an FILD. 7728 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7729 if (SrcVT == MVT::i32) { 7730 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7731 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7732 getPointerTy(), StackSlot, WordOff); 7733 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7734 StackSlot, MachinePointerInfo(), 7735 false, false, 0); 7736 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7737 OffsetSlot, MachinePointerInfo(), 7738 false, false, 0); 7739 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7740 return Fild; 7741 } 7742 7743 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7744 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7745 StackSlot, MachinePointerInfo(), 7746 false, false, 0); 7747 // For i64 source, we need to add the appropriate power of 2 if the input 7748 // was negative. This is the same as the optimization in 7749 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7750 // we must be careful to do the computation in x87 extended precision, not 7751 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7752 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7753 MachineMemOperand *MMO = 7754 DAG.getMachineFunction() 7755 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7756 MachineMemOperand::MOLoad, 8, 8); 7757 7758 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7759 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7760 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7761 MVT::i64, MMO); 7762 7763 APInt FF(32, 0x5F800000ULL); 7764 7765 // Check whether the sign bit is set. 7766 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7767 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7768 ISD::SETLT); 7769 7770 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7771 SDValue FudgePtr = DAG.getConstantPool( 7772 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7773 getPointerTy()); 7774 7775 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7776 SDValue Zero = DAG.getIntPtrConstant(0); 7777 SDValue Four = DAG.getIntPtrConstant(4); 7778 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7779 Zero, Four); 7780 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7781 7782 // Load the value out, extending it from f32 to f80. 7783 // FIXME: Avoid the extend by constructing the right constant pool? 7784 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7785 FudgePtr, MachinePointerInfo::getConstantPool(), 7786 MVT::f32, false, false, 4); 7787 // Extend everything to 80 bits to force it to be done on x87. 7788 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7789 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7790} 7791 7792std::pair<SDValue,SDValue> X86TargetLowering:: 7793FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7794 DebugLoc DL = Op.getDebugLoc(); 7795 7796 EVT DstTy = Op.getValueType(); 7797 7798 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7799 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7800 DstTy = MVT::i64; 7801 } 7802 7803 assert(DstTy.getSimpleVT() <= MVT::i64 && 7804 DstTy.getSimpleVT() >= MVT::i16 && 7805 "Unknown FP_TO_INT to lower!"); 7806 7807 // These are really Legal. 7808 if (DstTy == MVT::i32 && 7809 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7810 return std::make_pair(SDValue(), SDValue()); 7811 if (Subtarget->is64Bit() && 7812 DstTy == MVT::i64 && 7813 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7814 return std::make_pair(SDValue(), SDValue()); 7815 7816 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7817 // stack slot, or into the FTOL runtime function. 7818 MachineFunction &MF = DAG.getMachineFunction(); 7819 unsigned MemSize = DstTy.getSizeInBits()/8; 7820 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7821 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7822 7823 unsigned Opc; 7824 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7825 Opc = X86ISD::WIN_FTOL; 7826 else 7827 switch (DstTy.getSimpleVT().SimpleTy) { 7828 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7829 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7830 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7831 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7832 } 7833 7834 SDValue Chain = DAG.getEntryNode(); 7835 SDValue Value = Op.getOperand(0); 7836 EVT TheVT = Op.getOperand(0).getValueType(); 7837 // FIXME This causes a redundant load/store if the SSE-class value is already 7838 // in memory, such as if it is on the callstack. 7839 if (isScalarFPTypeInSSEReg(TheVT)) { 7840 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7841 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7842 MachinePointerInfo::getFixedStack(SSFI), 7843 false, false, 0); 7844 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7845 SDValue Ops[] = { 7846 Chain, StackSlot, DAG.getValueType(TheVT) 7847 }; 7848 7849 MachineMemOperand *MMO = 7850 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7851 MachineMemOperand::MOLoad, MemSize, MemSize); 7852 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7853 DstTy, MMO); 7854 Chain = Value.getValue(1); 7855 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7856 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7857 } 7858 7859 MachineMemOperand *MMO = 7860 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7861 MachineMemOperand::MOStore, MemSize, MemSize); 7862 7863 if (Opc != X86ISD::WIN_FTOL) { 7864 // Build the FP_TO_INT*_IN_MEM 7865 SDValue Ops[] = { Chain, Value, StackSlot }; 7866 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7867 Ops, 3, DstTy, MMO); 7868 return std::make_pair(FIST, StackSlot); 7869 } else { 7870 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7871 DAG.getVTList(MVT::Other, MVT::Glue), 7872 Chain, Value); 7873 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7874 MVT::i32, ftol.getValue(1)); 7875 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7876 MVT::i32, eax.getValue(2)); 7877 SDValue Ops[] = { eax, edx }; 7878 SDValue pair = IsReplace 7879 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7880 : DAG.getMergeValues(Ops, 2, DL); 7881 return std::make_pair(pair, SDValue()); 7882 } 7883} 7884 7885SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7886 SelectionDAG &DAG) const { 7887 if (Op.getValueType().isVector()) 7888 return SDValue(); 7889 7890 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7891 /*IsSigned=*/ true, /*IsReplace=*/ false); 7892 SDValue FIST = Vals.first, StackSlot = Vals.second; 7893 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7894 if (FIST.getNode() == 0) return Op; 7895 7896 if (StackSlot.getNode()) 7897 // Load the result. 7898 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7899 FIST, StackSlot, MachinePointerInfo(), 7900 false, false, false, 0); 7901 else 7902 // The node is the result. 7903 return FIST; 7904} 7905 7906SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7907 SelectionDAG &DAG) const { 7908 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7909 /*IsSigned=*/ false, /*IsReplace=*/ false); 7910 SDValue FIST = Vals.first, StackSlot = Vals.second; 7911 assert(FIST.getNode() && "Unexpected failure"); 7912 7913 if (StackSlot.getNode()) 7914 // Load the result. 7915 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7916 FIST, StackSlot, MachinePointerInfo(), 7917 false, false, false, 0); 7918 else 7919 // The node is the result. 7920 return FIST; 7921} 7922 7923SDValue X86TargetLowering::LowerFABS(SDValue Op, 7924 SelectionDAG &DAG) const { 7925 LLVMContext *Context = DAG.getContext(); 7926 DebugLoc dl = Op.getDebugLoc(); 7927 EVT VT = Op.getValueType(); 7928 EVT EltVT = VT; 7929 if (VT.isVector()) 7930 EltVT = VT.getVectorElementType(); 7931 Constant *C; 7932 if (EltVT == MVT::f64) { 7933 C = ConstantVector::getSplat(2, 7934 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7935 } else { 7936 C = ConstantVector::getSplat(4, 7937 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7938 } 7939 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7940 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7941 MachinePointerInfo::getConstantPool(), 7942 false, false, false, 16); 7943 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7944} 7945 7946SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7947 LLVMContext *Context = DAG.getContext(); 7948 DebugLoc dl = Op.getDebugLoc(); 7949 EVT VT = Op.getValueType(); 7950 EVT EltVT = VT; 7951 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7952 if (VT.isVector()) { 7953 EltVT = VT.getVectorElementType(); 7954 NumElts = VT.getVectorNumElements(); 7955 } 7956 Constant *C; 7957 if (EltVT == MVT::f64) 7958 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7959 else 7960 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7961 C = ConstantVector::getSplat(NumElts, C); 7962 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7963 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7964 MachinePointerInfo::getConstantPool(), 7965 false, false, false, 16); 7966 if (VT.isVector()) { 7967 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7968 return DAG.getNode(ISD::BITCAST, dl, VT, 7969 DAG.getNode(ISD::XOR, dl, XORVT, 7970 DAG.getNode(ISD::BITCAST, dl, XORVT, 7971 Op.getOperand(0)), 7972 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7973 } else { 7974 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7975 } 7976} 7977 7978SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7979 LLVMContext *Context = DAG.getContext(); 7980 SDValue Op0 = Op.getOperand(0); 7981 SDValue Op1 = Op.getOperand(1); 7982 DebugLoc dl = Op.getDebugLoc(); 7983 EVT VT = Op.getValueType(); 7984 EVT SrcVT = Op1.getValueType(); 7985 7986 // If second operand is smaller, extend it first. 7987 if (SrcVT.bitsLT(VT)) { 7988 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7989 SrcVT = VT; 7990 } 7991 // And if it is bigger, shrink it first. 7992 if (SrcVT.bitsGT(VT)) { 7993 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7994 SrcVT = VT; 7995 } 7996 7997 // At this point the operands and the result should have the same 7998 // type, and that won't be f80 since that is not custom lowered. 7999 8000 // First get the sign bit of second operand. 8001 SmallVector<Constant*,4> CV; 8002 if (SrcVT == MVT::f64) { 8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8005 } else { 8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8008 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8010 } 8011 Constant *C = ConstantVector::get(CV); 8012 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8013 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8014 MachinePointerInfo::getConstantPool(), 8015 false, false, false, 16); 8016 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8017 8018 // Shift sign bit right or left if the two operands have different types. 8019 if (SrcVT.bitsGT(VT)) { 8020 // Op0 is MVT::f32, Op1 is MVT::f64. 8021 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8022 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8023 DAG.getConstant(32, MVT::i32)); 8024 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8025 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8026 DAG.getIntPtrConstant(0)); 8027 } 8028 8029 // Clear first operand sign bit. 8030 CV.clear(); 8031 if (VT == MVT::f64) { 8032 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8034 } else { 8035 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8036 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8037 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8038 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8039 } 8040 C = ConstantVector::get(CV); 8041 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8042 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8043 MachinePointerInfo::getConstantPool(), 8044 false, false, false, 16); 8045 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8046 8047 // Or the value with the sign bit. 8048 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8049} 8050 8051SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8052 SDValue N0 = Op.getOperand(0); 8053 DebugLoc dl = Op.getDebugLoc(); 8054 EVT VT = Op.getValueType(); 8055 8056 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8057 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8058 DAG.getConstant(1, VT)); 8059 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8060} 8061 8062/// Emit nodes that will be selected as "test Op0,Op0", or something 8063/// equivalent. 8064SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8065 SelectionDAG &DAG) const { 8066 DebugLoc dl = Op.getDebugLoc(); 8067 8068 // CF and OF aren't always set the way we want. Determine which 8069 // of these we need. 8070 bool NeedCF = false; 8071 bool NeedOF = false; 8072 switch (X86CC) { 8073 default: break; 8074 case X86::COND_A: case X86::COND_AE: 8075 case X86::COND_B: case X86::COND_BE: 8076 NeedCF = true; 8077 break; 8078 case X86::COND_G: case X86::COND_GE: 8079 case X86::COND_L: case X86::COND_LE: 8080 case X86::COND_O: case X86::COND_NO: 8081 NeedOF = true; 8082 break; 8083 } 8084 8085 // See if we can use the EFLAGS value from the operand instead of 8086 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8087 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8088 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8089 // Emit a CMP with 0, which is the TEST pattern. 8090 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8091 DAG.getConstant(0, Op.getValueType())); 8092 8093 unsigned Opcode = 0; 8094 unsigned NumOperands = 0; 8095 switch (Op.getNode()->getOpcode()) { 8096 case ISD::ADD: 8097 // Due to an isel shortcoming, be conservative if this add is likely to be 8098 // selected as part of a load-modify-store instruction. When the root node 8099 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8100 // uses of other nodes in the match, such as the ADD in this case. This 8101 // leads to the ADD being left around and reselected, with the result being 8102 // two adds in the output. Alas, even if none our users are stores, that 8103 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8104 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8105 // climbing the DAG back to the root, and it doesn't seem to be worth the 8106 // effort. 8107 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8108 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8109 if (UI->getOpcode() != ISD::CopyToReg && 8110 UI->getOpcode() != ISD::SETCC && 8111 UI->getOpcode() != ISD::STORE) 8112 goto default_case; 8113 8114 if (ConstantSDNode *C = 8115 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8116 // An add of one will be selected as an INC. 8117 if (C->getAPIntValue() == 1) { 8118 Opcode = X86ISD::INC; 8119 NumOperands = 1; 8120 break; 8121 } 8122 8123 // An add of negative one (subtract of one) will be selected as a DEC. 8124 if (C->getAPIntValue().isAllOnesValue()) { 8125 Opcode = X86ISD::DEC; 8126 NumOperands = 1; 8127 break; 8128 } 8129 } 8130 8131 // Otherwise use a regular EFLAGS-setting add. 8132 Opcode = X86ISD::ADD; 8133 NumOperands = 2; 8134 break; 8135 case ISD::AND: { 8136 // If the primary and result isn't used, don't bother using X86ISD::AND, 8137 // because a TEST instruction will be better. 8138 bool NonFlagUse = false; 8139 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8140 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8141 SDNode *User = *UI; 8142 unsigned UOpNo = UI.getOperandNo(); 8143 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8144 // Look pass truncate. 8145 UOpNo = User->use_begin().getOperandNo(); 8146 User = *User->use_begin(); 8147 } 8148 8149 if (User->getOpcode() != ISD::BRCOND && 8150 User->getOpcode() != ISD::SETCC && 8151 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8152 NonFlagUse = true; 8153 break; 8154 } 8155 } 8156 8157 if (!NonFlagUse) 8158 break; 8159 } 8160 // FALL THROUGH 8161 case ISD::SUB: 8162 case ISD::OR: 8163 case ISD::XOR: 8164 // Due to the ISEL shortcoming noted above, be conservative if this op is 8165 // likely to be selected as part of a load-modify-store instruction. 8166 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8167 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8168 if (UI->getOpcode() == ISD::STORE) 8169 goto default_case; 8170 8171 // Otherwise use a regular EFLAGS-setting instruction. 8172 switch (Op.getNode()->getOpcode()) { 8173 default: llvm_unreachable("unexpected operator!"); 8174 case ISD::SUB: Opcode = X86ISD::SUB; break; 8175 case ISD::OR: Opcode = X86ISD::OR; break; 8176 case ISD::XOR: Opcode = X86ISD::XOR; break; 8177 case ISD::AND: Opcode = X86ISD::AND; break; 8178 } 8179 8180 NumOperands = 2; 8181 break; 8182 case X86ISD::ADD: 8183 case X86ISD::SUB: 8184 case X86ISD::INC: 8185 case X86ISD::DEC: 8186 case X86ISD::OR: 8187 case X86ISD::XOR: 8188 case X86ISD::AND: 8189 return SDValue(Op.getNode(), 1); 8190 default: 8191 default_case: 8192 break; 8193 } 8194 8195 if (Opcode == 0) 8196 // Emit a CMP with 0, which is the TEST pattern. 8197 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8198 DAG.getConstant(0, Op.getValueType())); 8199 8200 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8201 SmallVector<SDValue, 4> Ops; 8202 for (unsigned i = 0; i != NumOperands; ++i) 8203 Ops.push_back(Op.getOperand(i)); 8204 8205 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8206 DAG.ReplaceAllUsesWith(Op, New); 8207 return SDValue(New.getNode(), 1); 8208} 8209 8210/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8211/// equivalent. 8212SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8213 SelectionDAG &DAG) const { 8214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8215 if (C->getAPIntValue() == 0) 8216 return EmitTest(Op0, X86CC, DAG); 8217 8218 DebugLoc dl = Op0.getDebugLoc(); 8219 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8220} 8221 8222/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8223/// if it's possible. 8224SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8225 DebugLoc dl, SelectionDAG &DAG) const { 8226 SDValue Op0 = And.getOperand(0); 8227 SDValue Op1 = And.getOperand(1); 8228 if (Op0.getOpcode() == ISD::TRUNCATE) 8229 Op0 = Op0.getOperand(0); 8230 if (Op1.getOpcode() == ISD::TRUNCATE) 8231 Op1 = Op1.getOperand(0); 8232 8233 SDValue LHS, RHS; 8234 if (Op1.getOpcode() == ISD::SHL) 8235 std::swap(Op0, Op1); 8236 if (Op0.getOpcode() == ISD::SHL) { 8237 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8238 if (And00C->getZExtValue() == 1) { 8239 // If we looked past a truncate, check that it's only truncating away 8240 // known zeros. 8241 unsigned BitWidth = Op0.getValueSizeInBits(); 8242 unsigned AndBitWidth = And.getValueSizeInBits(); 8243 if (BitWidth > AndBitWidth) { 8244 APInt Zeros, Ones; 8245 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8246 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8247 return SDValue(); 8248 } 8249 LHS = Op1; 8250 RHS = Op0.getOperand(1); 8251 } 8252 } else if (Op1.getOpcode() == ISD::Constant) { 8253 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8254 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8255 SDValue AndLHS = Op0; 8256 8257 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8258 LHS = AndLHS.getOperand(0); 8259 RHS = AndLHS.getOperand(1); 8260 } 8261 8262 // Use BT if the immediate can't be encoded in a TEST instruction. 8263 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8264 LHS = AndLHS; 8265 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8266 } 8267 } 8268 8269 if (LHS.getNode()) { 8270 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8271 // instruction. Since the shift amount is in-range-or-undefined, we know 8272 // that doing a bittest on the i32 value is ok. We extend to i32 because 8273 // the encoding for the i16 version is larger than the i32 version. 8274 // Also promote i16 to i32 for performance / code size reason. 8275 if (LHS.getValueType() == MVT::i8 || 8276 LHS.getValueType() == MVT::i16) 8277 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8278 8279 // If the operand types disagree, extend the shift amount to match. Since 8280 // BT ignores high bits (like shifts) we can use anyextend. 8281 if (LHS.getValueType() != RHS.getValueType()) 8282 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8283 8284 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8285 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8286 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8287 DAG.getConstant(Cond, MVT::i8), BT); 8288 } 8289 8290 return SDValue(); 8291} 8292 8293SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8294 8295 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8296 8297 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8298 SDValue Op0 = Op.getOperand(0); 8299 SDValue Op1 = Op.getOperand(1); 8300 DebugLoc dl = Op.getDebugLoc(); 8301 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8302 8303 // Optimize to BT if possible. 8304 // Lower (X & (1 << N)) == 0 to BT(X, N). 8305 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8306 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8307 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8308 Op1.getOpcode() == ISD::Constant && 8309 cast<ConstantSDNode>(Op1)->isNullValue() && 8310 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8311 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8312 if (NewSetCC.getNode()) 8313 return NewSetCC; 8314 } 8315 8316 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8317 // these. 8318 if (Op1.getOpcode() == ISD::Constant && 8319 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8320 cast<ConstantSDNode>(Op1)->isNullValue()) && 8321 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8322 8323 // If the input is a setcc, then reuse the input setcc or use a new one with 8324 // the inverted condition. 8325 if (Op0.getOpcode() == X86ISD::SETCC) { 8326 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8327 bool Invert = (CC == ISD::SETNE) ^ 8328 cast<ConstantSDNode>(Op1)->isNullValue(); 8329 if (!Invert) return Op0; 8330 8331 CCode = X86::GetOppositeBranchCondition(CCode); 8332 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8333 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8334 } 8335 } 8336 8337 bool isFP = Op1.getValueType().isFloatingPoint(); 8338 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8339 if (X86CC == X86::COND_INVALID) 8340 return SDValue(); 8341 8342 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8343 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8344 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8345} 8346 8347// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8348// ones, and then concatenate the result back. 8349static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8350 EVT VT = Op.getValueType(); 8351 8352 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8353 "Unsupported value type for operation"); 8354 8355 int NumElems = VT.getVectorNumElements(); 8356 DebugLoc dl = Op.getDebugLoc(); 8357 SDValue CC = Op.getOperand(2); 8358 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8359 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8360 8361 // Extract the LHS vectors 8362 SDValue LHS = Op.getOperand(0); 8363 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8364 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8365 8366 // Extract the RHS vectors 8367 SDValue RHS = Op.getOperand(1); 8368 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8369 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8370 8371 // Issue the operation on the smaller types and concatenate the result back 8372 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8373 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8374 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8375 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8376 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8377} 8378 8379 8380SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8381 SDValue Cond; 8382 SDValue Op0 = Op.getOperand(0); 8383 SDValue Op1 = Op.getOperand(1); 8384 SDValue CC = Op.getOperand(2); 8385 EVT VT = Op.getValueType(); 8386 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8387 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8388 DebugLoc dl = Op.getDebugLoc(); 8389 8390 if (isFP) { 8391 unsigned SSECC = 8; 8392 EVT EltVT = Op0.getValueType().getVectorElementType(); 8393 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8394 8395 bool Swap = false; 8396 8397 // SSE Condition code mapping: 8398 // 0 - EQ 8399 // 1 - LT 8400 // 2 - LE 8401 // 3 - UNORD 8402 // 4 - NEQ 8403 // 5 - NLT 8404 // 6 - NLE 8405 // 7 - ORD 8406 switch (SetCCOpcode) { 8407 default: break; 8408 case ISD::SETOEQ: 8409 case ISD::SETEQ: SSECC = 0; break; 8410 case ISD::SETOGT: 8411 case ISD::SETGT: Swap = true; // Fallthrough 8412 case ISD::SETLT: 8413 case ISD::SETOLT: SSECC = 1; break; 8414 case ISD::SETOGE: 8415 case ISD::SETGE: Swap = true; // Fallthrough 8416 case ISD::SETLE: 8417 case ISD::SETOLE: SSECC = 2; break; 8418 case ISD::SETUO: SSECC = 3; break; 8419 case ISD::SETUNE: 8420 case ISD::SETNE: SSECC = 4; break; 8421 case ISD::SETULE: Swap = true; 8422 case ISD::SETUGE: SSECC = 5; break; 8423 case ISD::SETULT: Swap = true; 8424 case ISD::SETUGT: SSECC = 6; break; 8425 case ISD::SETO: SSECC = 7; break; 8426 } 8427 if (Swap) 8428 std::swap(Op0, Op1); 8429 8430 // In the two special cases we can't handle, emit two comparisons. 8431 if (SSECC == 8) { 8432 if (SetCCOpcode == ISD::SETUEQ) { 8433 SDValue UNORD, EQ; 8434 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8435 DAG.getConstant(3, MVT::i8)); 8436 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8437 DAG.getConstant(0, MVT::i8)); 8438 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8439 } else if (SetCCOpcode == ISD::SETONE) { 8440 SDValue ORD, NEQ; 8441 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8442 DAG.getConstant(7, MVT::i8)); 8443 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8444 DAG.getConstant(4, MVT::i8)); 8445 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8446 } 8447 llvm_unreachable("Illegal FP comparison"); 8448 } 8449 // Handle all other FP comparisons here. 8450 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8451 DAG.getConstant(SSECC, MVT::i8)); 8452 } 8453 8454 // Break 256-bit integer vector compare into smaller ones. 8455 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8456 return Lower256IntVSETCC(Op, DAG); 8457 8458 // We are handling one of the integer comparisons here. Since SSE only has 8459 // GT and EQ comparisons for integer, swapping operands and multiple 8460 // operations may be required for some comparisons. 8461 unsigned Opc = 0; 8462 bool Swap = false, Invert = false, FlipSigns = false; 8463 8464 switch (SetCCOpcode) { 8465 default: break; 8466 case ISD::SETNE: Invert = true; 8467 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8468 case ISD::SETLT: Swap = true; 8469 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8470 case ISD::SETGE: Swap = true; 8471 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8472 case ISD::SETULT: Swap = true; 8473 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8474 case ISD::SETUGE: Swap = true; 8475 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8476 } 8477 if (Swap) 8478 std::swap(Op0, Op1); 8479 8480 // Check that the operation in question is available (most are plain SSE2, 8481 // but PCMPGTQ and PCMPEQQ have different requirements). 8482 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8483 return SDValue(); 8484 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8485 return SDValue(); 8486 8487 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8488 // bits of the inputs before performing those operations. 8489 if (FlipSigns) { 8490 EVT EltVT = VT.getVectorElementType(); 8491 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8492 EltVT); 8493 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8494 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8495 SignBits.size()); 8496 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8497 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8498 } 8499 8500 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8501 8502 // If the logical-not of the result is required, perform that now. 8503 if (Invert) 8504 Result = DAG.getNOT(dl, Result, VT); 8505 8506 return Result; 8507} 8508 8509// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8510static bool isX86LogicalCmp(SDValue Op) { 8511 unsigned Opc = Op.getNode()->getOpcode(); 8512 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8513 return true; 8514 if (Op.getResNo() == 1 && 8515 (Opc == X86ISD::ADD || 8516 Opc == X86ISD::SUB || 8517 Opc == X86ISD::ADC || 8518 Opc == X86ISD::SBB || 8519 Opc == X86ISD::SMUL || 8520 Opc == X86ISD::UMUL || 8521 Opc == X86ISD::INC || 8522 Opc == X86ISD::DEC || 8523 Opc == X86ISD::OR || 8524 Opc == X86ISD::XOR || 8525 Opc == X86ISD::AND)) 8526 return true; 8527 8528 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8529 return true; 8530 8531 return false; 8532} 8533 8534static bool isZero(SDValue V) { 8535 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8536 return C && C->isNullValue(); 8537} 8538 8539static bool isAllOnes(SDValue V) { 8540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8541 return C && C->isAllOnesValue(); 8542} 8543 8544SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8545 bool addTest = true; 8546 SDValue Cond = Op.getOperand(0); 8547 SDValue Op1 = Op.getOperand(1); 8548 SDValue Op2 = Op.getOperand(2); 8549 DebugLoc DL = Op.getDebugLoc(); 8550 SDValue CC; 8551 8552 if (Cond.getOpcode() == ISD::SETCC) { 8553 SDValue NewCond = LowerSETCC(Cond, DAG); 8554 if (NewCond.getNode()) 8555 Cond = NewCond; 8556 } 8557 8558 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8559 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8560 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8561 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8562 if (Cond.getOpcode() == X86ISD::SETCC && 8563 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8564 isZero(Cond.getOperand(1).getOperand(1))) { 8565 SDValue Cmp = Cond.getOperand(1); 8566 8567 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8568 8569 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8570 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8571 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8572 8573 SDValue CmpOp0 = Cmp.getOperand(0); 8574 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8575 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8576 8577 SDValue Res = // Res = 0 or -1. 8578 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8579 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8580 8581 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8582 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8583 8584 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8585 if (N2C == 0 || !N2C->isNullValue()) 8586 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8587 return Res; 8588 } 8589 } 8590 8591 // Look past (and (setcc_carry (cmp ...)), 1). 8592 if (Cond.getOpcode() == ISD::AND && 8593 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8595 if (C && C->getAPIntValue() == 1) 8596 Cond = Cond.getOperand(0); 8597 } 8598 8599 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8600 // setting operand in place of the X86ISD::SETCC. 8601 unsigned CondOpcode = Cond.getOpcode(); 8602 if (CondOpcode == X86ISD::SETCC || 8603 CondOpcode == X86ISD::SETCC_CARRY) { 8604 CC = Cond.getOperand(0); 8605 8606 SDValue Cmp = Cond.getOperand(1); 8607 unsigned Opc = Cmp.getOpcode(); 8608 EVT VT = Op.getValueType(); 8609 8610 bool IllegalFPCMov = false; 8611 if (VT.isFloatingPoint() && !VT.isVector() && 8612 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8613 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8614 8615 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8616 Opc == X86ISD::BT) { // FIXME 8617 Cond = Cmp; 8618 addTest = false; 8619 } 8620 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8621 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8622 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8623 Cond.getOperand(0).getValueType() != MVT::i8)) { 8624 SDValue LHS = Cond.getOperand(0); 8625 SDValue RHS = Cond.getOperand(1); 8626 unsigned X86Opcode; 8627 unsigned X86Cond; 8628 SDVTList VTs; 8629 switch (CondOpcode) { 8630 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8631 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8632 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8633 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8634 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8635 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8636 default: llvm_unreachable("unexpected overflowing operator"); 8637 } 8638 if (CondOpcode == ISD::UMULO) 8639 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8640 MVT::i32); 8641 else 8642 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8643 8644 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8645 8646 if (CondOpcode == ISD::UMULO) 8647 Cond = X86Op.getValue(2); 8648 else 8649 Cond = X86Op.getValue(1); 8650 8651 CC = DAG.getConstant(X86Cond, MVT::i8); 8652 addTest = false; 8653 } 8654 8655 if (addTest) { 8656 // Look pass the truncate. 8657 if (Cond.getOpcode() == ISD::TRUNCATE) 8658 Cond = Cond.getOperand(0); 8659 8660 // We know the result of AND is compared against zero. Try to match 8661 // it to BT. 8662 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8663 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8664 if (NewSetCC.getNode()) { 8665 CC = NewSetCC.getOperand(0); 8666 Cond = NewSetCC.getOperand(1); 8667 addTest = false; 8668 } 8669 } 8670 } 8671 8672 if (addTest) { 8673 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8674 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8675 } 8676 8677 // a < b ? -1 : 0 -> RES = ~setcc_carry 8678 // a < b ? 0 : -1 -> RES = setcc_carry 8679 // a >= b ? -1 : 0 -> RES = setcc_carry 8680 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8681 if (Cond.getOpcode() == X86ISD::CMP) { 8682 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8683 8684 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8685 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8686 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8687 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8688 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8689 return DAG.getNOT(DL, Res, Res.getValueType()); 8690 return Res; 8691 } 8692 } 8693 8694 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8695 // condition is true. 8696 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8697 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8698 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8699} 8700 8701// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8702// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8703// from the AND / OR. 8704static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8705 Opc = Op.getOpcode(); 8706 if (Opc != ISD::OR && Opc != ISD::AND) 8707 return false; 8708 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8709 Op.getOperand(0).hasOneUse() && 8710 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8711 Op.getOperand(1).hasOneUse()); 8712} 8713 8714// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8715// 1 and that the SETCC node has a single use. 8716static bool isXor1OfSetCC(SDValue Op) { 8717 if (Op.getOpcode() != ISD::XOR) 8718 return false; 8719 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8720 if (N1C && N1C->getAPIntValue() == 1) { 8721 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8722 Op.getOperand(0).hasOneUse(); 8723 } 8724 return false; 8725} 8726 8727SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8728 bool addTest = true; 8729 SDValue Chain = Op.getOperand(0); 8730 SDValue Cond = Op.getOperand(1); 8731 SDValue Dest = Op.getOperand(2); 8732 DebugLoc dl = Op.getDebugLoc(); 8733 SDValue CC; 8734 bool Inverted = false; 8735 8736 if (Cond.getOpcode() == ISD::SETCC) { 8737 // Check for setcc([su]{add,sub,mul}o == 0). 8738 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8739 isa<ConstantSDNode>(Cond.getOperand(1)) && 8740 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8741 Cond.getOperand(0).getResNo() == 1 && 8742 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8743 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8744 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8745 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8746 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8747 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8748 Inverted = true; 8749 Cond = Cond.getOperand(0); 8750 } else { 8751 SDValue NewCond = LowerSETCC(Cond, DAG); 8752 if (NewCond.getNode()) 8753 Cond = NewCond; 8754 } 8755 } 8756#if 0 8757 // FIXME: LowerXALUO doesn't handle these!! 8758 else if (Cond.getOpcode() == X86ISD::ADD || 8759 Cond.getOpcode() == X86ISD::SUB || 8760 Cond.getOpcode() == X86ISD::SMUL || 8761 Cond.getOpcode() == X86ISD::UMUL) 8762 Cond = LowerXALUO(Cond, DAG); 8763#endif 8764 8765 // Look pass (and (setcc_carry (cmp ...)), 1). 8766 if (Cond.getOpcode() == ISD::AND && 8767 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8768 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8769 if (C && C->getAPIntValue() == 1) 8770 Cond = Cond.getOperand(0); 8771 } 8772 8773 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8774 // setting operand in place of the X86ISD::SETCC. 8775 unsigned CondOpcode = Cond.getOpcode(); 8776 if (CondOpcode == X86ISD::SETCC || 8777 CondOpcode == X86ISD::SETCC_CARRY) { 8778 CC = Cond.getOperand(0); 8779 8780 SDValue Cmp = Cond.getOperand(1); 8781 unsigned Opc = Cmp.getOpcode(); 8782 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8783 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8784 Cond = Cmp; 8785 addTest = false; 8786 } else { 8787 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8788 default: break; 8789 case X86::COND_O: 8790 case X86::COND_B: 8791 // These can only come from an arithmetic instruction with overflow, 8792 // e.g. SADDO, UADDO. 8793 Cond = Cond.getNode()->getOperand(1); 8794 addTest = false; 8795 break; 8796 } 8797 } 8798 } 8799 CondOpcode = Cond.getOpcode(); 8800 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8801 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8802 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8803 Cond.getOperand(0).getValueType() != MVT::i8)) { 8804 SDValue LHS = Cond.getOperand(0); 8805 SDValue RHS = Cond.getOperand(1); 8806 unsigned X86Opcode; 8807 unsigned X86Cond; 8808 SDVTList VTs; 8809 switch (CondOpcode) { 8810 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8811 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8812 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8813 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8814 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8815 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8816 default: llvm_unreachable("unexpected overflowing operator"); 8817 } 8818 if (Inverted) 8819 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8820 if (CondOpcode == ISD::UMULO) 8821 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8822 MVT::i32); 8823 else 8824 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8825 8826 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8827 8828 if (CondOpcode == ISD::UMULO) 8829 Cond = X86Op.getValue(2); 8830 else 8831 Cond = X86Op.getValue(1); 8832 8833 CC = DAG.getConstant(X86Cond, MVT::i8); 8834 addTest = false; 8835 } else { 8836 unsigned CondOpc; 8837 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8838 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8839 if (CondOpc == ISD::OR) { 8840 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8841 // two branches instead of an explicit OR instruction with a 8842 // separate test. 8843 if (Cmp == Cond.getOperand(1).getOperand(1) && 8844 isX86LogicalCmp(Cmp)) { 8845 CC = Cond.getOperand(0).getOperand(0); 8846 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8847 Chain, Dest, CC, Cmp); 8848 CC = Cond.getOperand(1).getOperand(0); 8849 Cond = Cmp; 8850 addTest = false; 8851 } 8852 } else { // ISD::AND 8853 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8854 // two branches instead of an explicit AND instruction with a 8855 // separate test. However, we only do this if this block doesn't 8856 // have a fall-through edge, because this requires an explicit 8857 // jmp when the condition is false. 8858 if (Cmp == Cond.getOperand(1).getOperand(1) && 8859 isX86LogicalCmp(Cmp) && 8860 Op.getNode()->hasOneUse()) { 8861 X86::CondCode CCode = 8862 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8863 CCode = X86::GetOppositeBranchCondition(CCode); 8864 CC = DAG.getConstant(CCode, MVT::i8); 8865 SDNode *User = *Op.getNode()->use_begin(); 8866 // Look for an unconditional branch following this conditional branch. 8867 // We need this because we need to reverse the successors in order 8868 // to implement FCMP_OEQ. 8869 if (User->getOpcode() == ISD::BR) { 8870 SDValue FalseBB = User->getOperand(1); 8871 SDNode *NewBR = 8872 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8873 assert(NewBR == User); 8874 (void)NewBR; 8875 Dest = FalseBB; 8876 8877 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8878 Chain, Dest, CC, Cmp); 8879 X86::CondCode CCode = 8880 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8881 CCode = X86::GetOppositeBranchCondition(CCode); 8882 CC = DAG.getConstant(CCode, MVT::i8); 8883 Cond = Cmp; 8884 addTest = false; 8885 } 8886 } 8887 } 8888 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8889 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8890 // It should be transformed during dag combiner except when the condition 8891 // is set by a arithmetics with overflow node. 8892 X86::CondCode CCode = 8893 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8894 CCode = X86::GetOppositeBranchCondition(CCode); 8895 CC = DAG.getConstant(CCode, MVT::i8); 8896 Cond = Cond.getOperand(0).getOperand(1); 8897 addTest = false; 8898 } else if (Cond.getOpcode() == ISD::SETCC && 8899 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8900 // For FCMP_OEQ, we can emit 8901 // two branches instead of an explicit AND instruction with a 8902 // separate test. However, we only do this if this block doesn't 8903 // have a fall-through edge, because this requires an explicit 8904 // jmp when the condition is false. 8905 if (Op.getNode()->hasOneUse()) { 8906 SDNode *User = *Op.getNode()->use_begin(); 8907 // Look for an unconditional branch following this conditional branch. 8908 // We need this because we need to reverse the successors in order 8909 // to implement FCMP_OEQ. 8910 if (User->getOpcode() == ISD::BR) { 8911 SDValue FalseBB = User->getOperand(1); 8912 SDNode *NewBR = 8913 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8914 assert(NewBR == User); 8915 (void)NewBR; 8916 Dest = FalseBB; 8917 8918 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8919 Cond.getOperand(0), Cond.getOperand(1)); 8920 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8921 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8922 Chain, Dest, CC, Cmp); 8923 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8924 Cond = Cmp; 8925 addTest = false; 8926 } 8927 } 8928 } else if (Cond.getOpcode() == ISD::SETCC && 8929 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8930 // For FCMP_UNE, we can emit 8931 // two branches instead of an explicit AND instruction with a 8932 // separate test. However, we only do this if this block doesn't 8933 // have a fall-through edge, because this requires an explicit 8934 // jmp when the condition is false. 8935 if (Op.getNode()->hasOneUse()) { 8936 SDNode *User = *Op.getNode()->use_begin(); 8937 // Look for an unconditional branch following this conditional branch. 8938 // We need this because we need to reverse the successors in order 8939 // to implement FCMP_UNE. 8940 if (User->getOpcode() == ISD::BR) { 8941 SDValue FalseBB = User->getOperand(1); 8942 SDNode *NewBR = 8943 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8944 assert(NewBR == User); 8945 (void)NewBR; 8946 8947 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8948 Cond.getOperand(0), Cond.getOperand(1)); 8949 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8950 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8951 Chain, Dest, CC, Cmp); 8952 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8953 Cond = Cmp; 8954 addTest = false; 8955 Dest = FalseBB; 8956 } 8957 } 8958 } 8959 } 8960 8961 if (addTest) { 8962 // Look pass the truncate. 8963 if (Cond.getOpcode() == ISD::TRUNCATE) 8964 Cond = Cond.getOperand(0); 8965 8966 // We know the result of AND is compared against zero. Try to match 8967 // it to BT. 8968 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8969 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8970 if (NewSetCC.getNode()) { 8971 CC = NewSetCC.getOperand(0); 8972 Cond = NewSetCC.getOperand(1); 8973 addTest = false; 8974 } 8975 } 8976 } 8977 8978 if (addTest) { 8979 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8980 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8981 } 8982 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8983 Chain, Dest, CC, Cond); 8984} 8985 8986 8987// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8988// Calls to _alloca is needed to probe the stack when allocating more than 4k 8989// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8990// that the guard pages used by the OS virtual memory manager are allocated in 8991// correct sequence. 8992SDValue 8993X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8994 SelectionDAG &DAG) const { 8995 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8996 getTargetMachine().Options.EnableSegmentedStacks) && 8997 "This should be used only on Windows targets or when segmented stacks " 8998 "are being used"); 8999 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9000 DebugLoc dl = Op.getDebugLoc(); 9001 9002 // Get the inputs. 9003 SDValue Chain = Op.getOperand(0); 9004 SDValue Size = Op.getOperand(1); 9005 // FIXME: Ensure alignment here 9006 9007 bool Is64Bit = Subtarget->is64Bit(); 9008 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9009 9010 if (getTargetMachine().Options.EnableSegmentedStacks) { 9011 MachineFunction &MF = DAG.getMachineFunction(); 9012 MachineRegisterInfo &MRI = MF.getRegInfo(); 9013 9014 if (Is64Bit) { 9015 // The 64 bit implementation of segmented stacks needs to clobber both r10 9016 // r11. This makes it impossible to use it along with nested parameters. 9017 const Function *F = MF.getFunction(); 9018 9019 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9020 I != E; I++) 9021 if (I->hasNestAttr()) 9022 report_fatal_error("Cannot use segmented stacks with functions that " 9023 "have nested arguments."); 9024 } 9025 9026 const TargetRegisterClass *AddrRegClass = 9027 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9028 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9029 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9030 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9031 DAG.getRegister(Vreg, SPTy)); 9032 SDValue Ops1[2] = { Value, Chain }; 9033 return DAG.getMergeValues(Ops1, 2, dl); 9034 } else { 9035 SDValue Flag; 9036 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9037 9038 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9039 Flag = Chain.getValue(1); 9040 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9041 9042 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9043 Flag = Chain.getValue(1); 9044 9045 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9046 9047 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9048 return DAG.getMergeValues(Ops1, 2, dl); 9049 } 9050} 9051 9052SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9053 MachineFunction &MF = DAG.getMachineFunction(); 9054 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9055 9056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9057 DebugLoc DL = Op.getDebugLoc(); 9058 9059 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9060 // vastart just stores the address of the VarArgsFrameIndex slot into the 9061 // memory location argument. 9062 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9063 getPointerTy()); 9064 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9065 MachinePointerInfo(SV), false, false, 0); 9066 } 9067 9068 // __va_list_tag: 9069 // gp_offset (0 - 6 * 8) 9070 // fp_offset (48 - 48 + 8 * 16) 9071 // overflow_arg_area (point to parameters coming in memory). 9072 // reg_save_area 9073 SmallVector<SDValue, 8> MemOps; 9074 SDValue FIN = Op.getOperand(1); 9075 // Store gp_offset 9076 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9077 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9078 MVT::i32), 9079 FIN, MachinePointerInfo(SV), false, false, 0); 9080 MemOps.push_back(Store); 9081 9082 // Store fp_offset 9083 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9084 FIN, DAG.getIntPtrConstant(4)); 9085 Store = DAG.getStore(Op.getOperand(0), DL, 9086 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9087 MVT::i32), 9088 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9089 MemOps.push_back(Store); 9090 9091 // Store ptr to overflow_arg_area 9092 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9093 FIN, DAG.getIntPtrConstant(4)); 9094 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9095 getPointerTy()); 9096 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9097 MachinePointerInfo(SV, 8), 9098 false, false, 0); 9099 MemOps.push_back(Store); 9100 9101 // Store ptr to reg_save_area. 9102 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9103 FIN, DAG.getIntPtrConstant(8)); 9104 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9105 getPointerTy()); 9106 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9107 MachinePointerInfo(SV, 16), false, false, 0); 9108 MemOps.push_back(Store); 9109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9110 &MemOps[0], MemOps.size()); 9111} 9112 9113SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9114 assert(Subtarget->is64Bit() && 9115 "LowerVAARG only handles 64-bit va_arg!"); 9116 assert((Subtarget->isTargetLinux() || 9117 Subtarget->isTargetDarwin()) && 9118 "Unhandled target in LowerVAARG"); 9119 assert(Op.getNode()->getNumOperands() == 4); 9120 SDValue Chain = Op.getOperand(0); 9121 SDValue SrcPtr = Op.getOperand(1); 9122 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9123 unsigned Align = Op.getConstantOperandVal(3); 9124 DebugLoc dl = Op.getDebugLoc(); 9125 9126 EVT ArgVT = Op.getNode()->getValueType(0); 9127 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9128 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9129 uint8_t ArgMode; 9130 9131 // Decide which area this value should be read from. 9132 // TODO: Implement the AMD64 ABI in its entirety. This simple 9133 // selection mechanism works only for the basic types. 9134 if (ArgVT == MVT::f80) { 9135 llvm_unreachable("va_arg for f80 not yet implemented"); 9136 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9137 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9138 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9139 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9140 } else { 9141 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9142 } 9143 9144 if (ArgMode == 2) { 9145 // Sanity Check: Make sure using fp_offset makes sense. 9146 assert(!getTargetMachine().Options.UseSoftFloat && 9147 !(DAG.getMachineFunction() 9148 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9149 Subtarget->hasSSE1()); 9150 } 9151 9152 // Insert VAARG_64 node into the DAG 9153 // VAARG_64 returns two values: Variable Argument Address, Chain 9154 SmallVector<SDValue, 11> InstOps; 9155 InstOps.push_back(Chain); 9156 InstOps.push_back(SrcPtr); 9157 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9158 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9159 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9160 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9161 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9162 VTs, &InstOps[0], InstOps.size(), 9163 MVT::i64, 9164 MachinePointerInfo(SV), 9165 /*Align=*/0, 9166 /*Volatile=*/false, 9167 /*ReadMem=*/true, 9168 /*WriteMem=*/true); 9169 Chain = VAARG.getValue(1); 9170 9171 // Load the next argument and return it 9172 return DAG.getLoad(ArgVT, dl, 9173 Chain, 9174 VAARG, 9175 MachinePointerInfo(), 9176 false, false, false, 0); 9177} 9178 9179SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9180 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9181 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9182 SDValue Chain = Op.getOperand(0); 9183 SDValue DstPtr = Op.getOperand(1); 9184 SDValue SrcPtr = Op.getOperand(2); 9185 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9186 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9187 DebugLoc DL = Op.getDebugLoc(); 9188 9189 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9190 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9191 false, 9192 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9193} 9194 9195// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9196// may or may not be a constant. Takes immediate version of shift as input. 9197static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9198 SDValue SrcOp, SDValue ShAmt, 9199 SelectionDAG &DAG) { 9200 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9201 9202 if (isa<ConstantSDNode>(ShAmt)) { 9203 switch (Opc) { 9204 default: llvm_unreachable("Unknown target vector shift node"); 9205 case X86ISD::VSHLI: 9206 case X86ISD::VSRLI: 9207 case X86ISD::VSRAI: 9208 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9209 } 9210 } 9211 9212 // Change opcode to non-immediate version 9213 switch (Opc) { 9214 default: llvm_unreachable("Unknown target vector shift node"); 9215 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9216 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9217 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9218 } 9219 9220 // Need to build a vector containing shift amount 9221 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9222 SDValue ShOps[4]; 9223 ShOps[0] = ShAmt; 9224 ShOps[1] = DAG.getConstant(0, MVT::i32); 9225 ShOps[2] = DAG.getUNDEF(MVT::i32); 9226 ShOps[3] = DAG.getUNDEF(MVT::i32); 9227 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9228 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9229 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9230} 9231 9232SDValue 9233X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9234 DebugLoc dl = Op.getDebugLoc(); 9235 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9236 switch (IntNo) { 9237 default: return SDValue(); // Don't custom lower most intrinsics. 9238 // Comparison intrinsics. 9239 case Intrinsic::x86_sse_comieq_ss: 9240 case Intrinsic::x86_sse_comilt_ss: 9241 case Intrinsic::x86_sse_comile_ss: 9242 case Intrinsic::x86_sse_comigt_ss: 9243 case Intrinsic::x86_sse_comige_ss: 9244 case Intrinsic::x86_sse_comineq_ss: 9245 case Intrinsic::x86_sse_ucomieq_ss: 9246 case Intrinsic::x86_sse_ucomilt_ss: 9247 case Intrinsic::x86_sse_ucomile_ss: 9248 case Intrinsic::x86_sse_ucomigt_ss: 9249 case Intrinsic::x86_sse_ucomige_ss: 9250 case Intrinsic::x86_sse_ucomineq_ss: 9251 case Intrinsic::x86_sse2_comieq_sd: 9252 case Intrinsic::x86_sse2_comilt_sd: 9253 case Intrinsic::x86_sse2_comile_sd: 9254 case Intrinsic::x86_sse2_comigt_sd: 9255 case Intrinsic::x86_sse2_comige_sd: 9256 case Intrinsic::x86_sse2_comineq_sd: 9257 case Intrinsic::x86_sse2_ucomieq_sd: 9258 case Intrinsic::x86_sse2_ucomilt_sd: 9259 case Intrinsic::x86_sse2_ucomile_sd: 9260 case Intrinsic::x86_sse2_ucomigt_sd: 9261 case Intrinsic::x86_sse2_ucomige_sd: 9262 case Intrinsic::x86_sse2_ucomineq_sd: { 9263 unsigned Opc = 0; 9264 ISD::CondCode CC = ISD::SETCC_INVALID; 9265 switch (IntNo) { 9266 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9267 case Intrinsic::x86_sse_comieq_ss: 9268 case Intrinsic::x86_sse2_comieq_sd: 9269 Opc = X86ISD::COMI; 9270 CC = ISD::SETEQ; 9271 break; 9272 case Intrinsic::x86_sse_comilt_ss: 9273 case Intrinsic::x86_sse2_comilt_sd: 9274 Opc = X86ISD::COMI; 9275 CC = ISD::SETLT; 9276 break; 9277 case Intrinsic::x86_sse_comile_ss: 9278 case Intrinsic::x86_sse2_comile_sd: 9279 Opc = X86ISD::COMI; 9280 CC = ISD::SETLE; 9281 break; 9282 case Intrinsic::x86_sse_comigt_ss: 9283 case Intrinsic::x86_sse2_comigt_sd: 9284 Opc = X86ISD::COMI; 9285 CC = ISD::SETGT; 9286 break; 9287 case Intrinsic::x86_sse_comige_ss: 9288 case Intrinsic::x86_sse2_comige_sd: 9289 Opc = X86ISD::COMI; 9290 CC = ISD::SETGE; 9291 break; 9292 case Intrinsic::x86_sse_comineq_ss: 9293 case Intrinsic::x86_sse2_comineq_sd: 9294 Opc = X86ISD::COMI; 9295 CC = ISD::SETNE; 9296 break; 9297 case Intrinsic::x86_sse_ucomieq_ss: 9298 case Intrinsic::x86_sse2_ucomieq_sd: 9299 Opc = X86ISD::UCOMI; 9300 CC = ISD::SETEQ; 9301 break; 9302 case Intrinsic::x86_sse_ucomilt_ss: 9303 case Intrinsic::x86_sse2_ucomilt_sd: 9304 Opc = X86ISD::UCOMI; 9305 CC = ISD::SETLT; 9306 break; 9307 case Intrinsic::x86_sse_ucomile_ss: 9308 case Intrinsic::x86_sse2_ucomile_sd: 9309 Opc = X86ISD::UCOMI; 9310 CC = ISD::SETLE; 9311 break; 9312 case Intrinsic::x86_sse_ucomigt_ss: 9313 case Intrinsic::x86_sse2_ucomigt_sd: 9314 Opc = X86ISD::UCOMI; 9315 CC = ISD::SETGT; 9316 break; 9317 case Intrinsic::x86_sse_ucomige_ss: 9318 case Intrinsic::x86_sse2_ucomige_sd: 9319 Opc = X86ISD::UCOMI; 9320 CC = ISD::SETGE; 9321 break; 9322 case Intrinsic::x86_sse_ucomineq_ss: 9323 case Intrinsic::x86_sse2_ucomineq_sd: 9324 Opc = X86ISD::UCOMI; 9325 CC = ISD::SETNE; 9326 break; 9327 } 9328 9329 SDValue LHS = Op.getOperand(1); 9330 SDValue RHS = Op.getOperand(2); 9331 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9332 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9333 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9334 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9335 DAG.getConstant(X86CC, MVT::i8), Cond); 9336 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9337 } 9338 // XOP comparison intrinsics 9339 case Intrinsic::x86_xop_vpcomltb: 9340 case Intrinsic::x86_xop_vpcomltw: 9341 case Intrinsic::x86_xop_vpcomltd: 9342 case Intrinsic::x86_xop_vpcomltq: 9343 case Intrinsic::x86_xop_vpcomltub: 9344 case Intrinsic::x86_xop_vpcomltuw: 9345 case Intrinsic::x86_xop_vpcomltud: 9346 case Intrinsic::x86_xop_vpcomltuq: 9347 case Intrinsic::x86_xop_vpcomleb: 9348 case Intrinsic::x86_xop_vpcomlew: 9349 case Intrinsic::x86_xop_vpcomled: 9350 case Intrinsic::x86_xop_vpcomleq: 9351 case Intrinsic::x86_xop_vpcomleub: 9352 case Intrinsic::x86_xop_vpcomleuw: 9353 case Intrinsic::x86_xop_vpcomleud: 9354 case Intrinsic::x86_xop_vpcomleuq: 9355 case Intrinsic::x86_xop_vpcomgtb: 9356 case Intrinsic::x86_xop_vpcomgtw: 9357 case Intrinsic::x86_xop_vpcomgtd: 9358 case Intrinsic::x86_xop_vpcomgtq: 9359 case Intrinsic::x86_xop_vpcomgtub: 9360 case Intrinsic::x86_xop_vpcomgtuw: 9361 case Intrinsic::x86_xop_vpcomgtud: 9362 case Intrinsic::x86_xop_vpcomgtuq: 9363 case Intrinsic::x86_xop_vpcomgeb: 9364 case Intrinsic::x86_xop_vpcomgew: 9365 case Intrinsic::x86_xop_vpcomged: 9366 case Intrinsic::x86_xop_vpcomgeq: 9367 case Intrinsic::x86_xop_vpcomgeub: 9368 case Intrinsic::x86_xop_vpcomgeuw: 9369 case Intrinsic::x86_xop_vpcomgeud: 9370 case Intrinsic::x86_xop_vpcomgeuq: 9371 case Intrinsic::x86_xop_vpcomeqb: 9372 case Intrinsic::x86_xop_vpcomeqw: 9373 case Intrinsic::x86_xop_vpcomeqd: 9374 case Intrinsic::x86_xop_vpcomeqq: 9375 case Intrinsic::x86_xop_vpcomequb: 9376 case Intrinsic::x86_xop_vpcomequw: 9377 case Intrinsic::x86_xop_vpcomequd: 9378 case Intrinsic::x86_xop_vpcomequq: 9379 case Intrinsic::x86_xop_vpcomneb: 9380 case Intrinsic::x86_xop_vpcomnew: 9381 case Intrinsic::x86_xop_vpcomned: 9382 case Intrinsic::x86_xop_vpcomneq: 9383 case Intrinsic::x86_xop_vpcomneub: 9384 case Intrinsic::x86_xop_vpcomneuw: 9385 case Intrinsic::x86_xop_vpcomneud: 9386 case Intrinsic::x86_xop_vpcomneuq: 9387 case Intrinsic::x86_xop_vpcomfalseb: 9388 case Intrinsic::x86_xop_vpcomfalsew: 9389 case Intrinsic::x86_xop_vpcomfalsed: 9390 case Intrinsic::x86_xop_vpcomfalseq: 9391 case Intrinsic::x86_xop_vpcomfalseub: 9392 case Intrinsic::x86_xop_vpcomfalseuw: 9393 case Intrinsic::x86_xop_vpcomfalseud: 9394 case Intrinsic::x86_xop_vpcomfalseuq: 9395 case Intrinsic::x86_xop_vpcomtrueb: 9396 case Intrinsic::x86_xop_vpcomtruew: 9397 case Intrinsic::x86_xop_vpcomtrued: 9398 case Intrinsic::x86_xop_vpcomtrueq: 9399 case Intrinsic::x86_xop_vpcomtrueub: 9400 case Intrinsic::x86_xop_vpcomtrueuw: 9401 case Intrinsic::x86_xop_vpcomtrueud: 9402 case Intrinsic::x86_xop_vpcomtrueuq: { 9403 unsigned CC = 0; 9404 unsigned Opc = 0; 9405 9406 switch (IntNo) { 9407 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9408 case Intrinsic::x86_xop_vpcomltb: 9409 case Intrinsic::x86_xop_vpcomltw: 9410 case Intrinsic::x86_xop_vpcomltd: 9411 case Intrinsic::x86_xop_vpcomltq: 9412 CC = 0; 9413 Opc = X86ISD::VPCOM; 9414 break; 9415 case Intrinsic::x86_xop_vpcomltub: 9416 case Intrinsic::x86_xop_vpcomltuw: 9417 case Intrinsic::x86_xop_vpcomltud: 9418 case Intrinsic::x86_xop_vpcomltuq: 9419 CC = 0; 9420 Opc = X86ISD::VPCOMU; 9421 break; 9422 case Intrinsic::x86_xop_vpcomleb: 9423 case Intrinsic::x86_xop_vpcomlew: 9424 case Intrinsic::x86_xop_vpcomled: 9425 case Intrinsic::x86_xop_vpcomleq: 9426 CC = 1; 9427 Opc = X86ISD::VPCOM; 9428 break; 9429 case Intrinsic::x86_xop_vpcomleub: 9430 case Intrinsic::x86_xop_vpcomleuw: 9431 case Intrinsic::x86_xop_vpcomleud: 9432 case Intrinsic::x86_xop_vpcomleuq: 9433 CC = 1; 9434 Opc = X86ISD::VPCOMU; 9435 break; 9436 case Intrinsic::x86_xop_vpcomgtb: 9437 case Intrinsic::x86_xop_vpcomgtw: 9438 case Intrinsic::x86_xop_vpcomgtd: 9439 case Intrinsic::x86_xop_vpcomgtq: 9440 CC = 2; 9441 Opc = X86ISD::VPCOM; 9442 break; 9443 case Intrinsic::x86_xop_vpcomgtub: 9444 case Intrinsic::x86_xop_vpcomgtuw: 9445 case Intrinsic::x86_xop_vpcomgtud: 9446 case Intrinsic::x86_xop_vpcomgtuq: 9447 CC = 2; 9448 Opc = X86ISD::VPCOMU; 9449 break; 9450 case Intrinsic::x86_xop_vpcomgeb: 9451 case Intrinsic::x86_xop_vpcomgew: 9452 case Intrinsic::x86_xop_vpcomged: 9453 case Intrinsic::x86_xop_vpcomgeq: 9454 CC = 3; 9455 Opc = X86ISD::VPCOM; 9456 break; 9457 case Intrinsic::x86_xop_vpcomgeub: 9458 case Intrinsic::x86_xop_vpcomgeuw: 9459 case Intrinsic::x86_xop_vpcomgeud: 9460 case Intrinsic::x86_xop_vpcomgeuq: 9461 CC = 3; 9462 Opc = X86ISD::VPCOMU; 9463 break; 9464 case Intrinsic::x86_xop_vpcomeqb: 9465 case Intrinsic::x86_xop_vpcomeqw: 9466 case Intrinsic::x86_xop_vpcomeqd: 9467 case Intrinsic::x86_xop_vpcomeqq: 9468 CC = 4; 9469 Opc = X86ISD::VPCOM; 9470 break; 9471 case Intrinsic::x86_xop_vpcomequb: 9472 case Intrinsic::x86_xop_vpcomequw: 9473 case Intrinsic::x86_xop_vpcomequd: 9474 case Intrinsic::x86_xop_vpcomequq: 9475 CC = 4; 9476 Opc = X86ISD::VPCOMU; 9477 break; 9478 case Intrinsic::x86_xop_vpcomneb: 9479 case Intrinsic::x86_xop_vpcomnew: 9480 case Intrinsic::x86_xop_vpcomned: 9481 case Intrinsic::x86_xop_vpcomneq: 9482 CC = 5; 9483 Opc = X86ISD::VPCOM; 9484 break; 9485 case Intrinsic::x86_xop_vpcomneub: 9486 case Intrinsic::x86_xop_vpcomneuw: 9487 case Intrinsic::x86_xop_vpcomneud: 9488 case Intrinsic::x86_xop_vpcomneuq: 9489 CC = 5; 9490 Opc = X86ISD::VPCOMU; 9491 break; 9492 case Intrinsic::x86_xop_vpcomfalseb: 9493 case Intrinsic::x86_xop_vpcomfalsew: 9494 case Intrinsic::x86_xop_vpcomfalsed: 9495 case Intrinsic::x86_xop_vpcomfalseq: 9496 CC = 6; 9497 Opc = X86ISD::VPCOM; 9498 break; 9499 case Intrinsic::x86_xop_vpcomfalseub: 9500 case Intrinsic::x86_xop_vpcomfalseuw: 9501 case Intrinsic::x86_xop_vpcomfalseud: 9502 case Intrinsic::x86_xop_vpcomfalseuq: 9503 CC = 6; 9504 Opc = X86ISD::VPCOMU; 9505 break; 9506 case Intrinsic::x86_xop_vpcomtrueb: 9507 case Intrinsic::x86_xop_vpcomtruew: 9508 case Intrinsic::x86_xop_vpcomtrued: 9509 case Intrinsic::x86_xop_vpcomtrueq: 9510 CC = 7; 9511 Opc = X86ISD::VPCOM; 9512 break; 9513 case Intrinsic::x86_xop_vpcomtrueub: 9514 case Intrinsic::x86_xop_vpcomtrueuw: 9515 case Intrinsic::x86_xop_vpcomtrueud: 9516 case Intrinsic::x86_xop_vpcomtrueuq: 9517 CC = 7; 9518 Opc = X86ISD::VPCOMU; 9519 break; 9520 } 9521 9522 SDValue LHS = Op.getOperand(1); 9523 SDValue RHS = Op.getOperand(2); 9524 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9525 DAG.getConstant(CC, MVT::i8)); 9526 } 9527 9528 // Arithmetic intrinsics. 9529 case Intrinsic::x86_sse2_pmulu_dq: 9530 case Intrinsic::x86_avx2_pmulu_dq: 9531 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9532 Op.getOperand(1), Op.getOperand(2)); 9533 case Intrinsic::x86_sse3_hadd_ps: 9534 case Intrinsic::x86_sse3_hadd_pd: 9535 case Intrinsic::x86_avx_hadd_ps_256: 9536 case Intrinsic::x86_avx_hadd_pd_256: 9537 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9538 Op.getOperand(1), Op.getOperand(2)); 9539 case Intrinsic::x86_sse3_hsub_ps: 9540 case Intrinsic::x86_sse3_hsub_pd: 9541 case Intrinsic::x86_avx_hsub_ps_256: 9542 case Intrinsic::x86_avx_hsub_pd_256: 9543 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9544 Op.getOperand(1), Op.getOperand(2)); 9545 case Intrinsic::x86_ssse3_phadd_w_128: 9546 case Intrinsic::x86_ssse3_phadd_d_128: 9547 case Intrinsic::x86_avx2_phadd_w: 9548 case Intrinsic::x86_avx2_phadd_d: 9549 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9550 Op.getOperand(1), Op.getOperand(2)); 9551 case Intrinsic::x86_ssse3_phsub_w_128: 9552 case Intrinsic::x86_ssse3_phsub_d_128: 9553 case Intrinsic::x86_avx2_phsub_w: 9554 case Intrinsic::x86_avx2_phsub_d: 9555 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9556 Op.getOperand(1), Op.getOperand(2)); 9557 case Intrinsic::x86_avx2_psllv_d: 9558 case Intrinsic::x86_avx2_psllv_q: 9559 case Intrinsic::x86_avx2_psllv_d_256: 9560 case Intrinsic::x86_avx2_psllv_q_256: 9561 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9562 Op.getOperand(1), Op.getOperand(2)); 9563 case Intrinsic::x86_avx2_psrlv_d: 9564 case Intrinsic::x86_avx2_psrlv_q: 9565 case Intrinsic::x86_avx2_psrlv_d_256: 9566 case Intrinsic::x86_avx2_psrlv_q_256: 9567 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9568 Op.getOperand(1), Op.getOperand(2)); 9569 case Intrinsic::x86_avx2_psrav_d: 9570 case Intrinsic::x86_avx2_psrav_d_256: 9571 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9572 Op.getOperand(1), Op.getOperand(2)); 9573 case Intrinsic::x86_ssse3_pshuf_b_128: 9574 case Intrinsic::x86_avx2_pshuf_b: 9575 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9576 Op.getOperand(1), Op.getOperand(2)); 9577 case Intrinsic::x86_ssse3_psign_b_128: 9578 case Intrinsic::x86_ssse3_psign_w_128: 9579 case Intrinsic::x86_ssse3_psign_d_128: 9580 case Intrinsic::x86_avx2_psign_b: 9581 case Intrinsic::x86_avx2_psign_w: 9582 case Intrinsic::x86_avx2_psign_d: 9583 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9584 Op.getOperand(1), Op.getOperand(2)); 9585 case Intrinsic::x86_sse41_insertps: 9586 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9587 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9588 case Intrinsic::x86_avx_vperm2f128_ps_256: 9589 case Intrinsic::x86_avx_vperm2f128_pd_256: 9590 case Intrinsic::x86_avx_vperm2f128_si_256: 9591 case Intrinsic::x86_avx2_vperm2i128: 9592 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9593 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9594 case Intrinsic::x86_avx_vpermil_ps: 9595 case Intrinsic::x86_avx_vpermil_pd: 9596 case Intrinsic::x86_avx_vpermil_ps_256: 9597 case Intrinsic::x86_avx_vpermil_pd_256: 9598 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(), 9599 Op.getOperand(1), Op.getOperand(2)); 9600 case Intrinsic::x86_avx2_permd: 9601 case Intrinsic::x86_avx2_permps: 9602 // Operands intentionally swapped. Mask is last operand to intrinsic, 9603 // but second operand for node/intruction. 9604 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 9605 Op.getOperand(2), Op.getOperand(1)); 9606 9607 // ptest and testp intrinsics. The intrinsic these come from are designed to 9608 // return an integer value, not just an instruction so lower it to the ptest 9609 // or testp pattern and a setcc for the result. 9610 case Intrinsic::x86_sse41_ptestz: 9611 case Intrinsic::x86_sse41_ptestc: 9612 case Intrinsic::x86_sse41_ptestnzc: 9613 case Intrinsic::x86_avx_ptestz_256: 9614 case Intrinsic::x86_avx_ptestc_256: 9615 case Intrinsic::x86_avx_ptestnzc_256: 9616 case Intrinsic::x86_avx_vtestz_ps: 9617 case Intrinsic::x86_avx_vtestc_ps: 9618 case Intrinsic::x86_avx_vtestnzc_ps: 9619 case Intrinsic::x86_avx_vtestz_pd: 9620 case Intrinsic::x86_avx_vtestc_pd: 9621 case Intrinsic::x86_avx_vtestnzc_pd: 9622 case Intrinsic::x86_avx_vtestz_ps_256: 9623 case Intrinsic::x86_avx_vtestc_ps_256: 9624 case Intrinsic::x86_avx_vtestnzc_ps_256: 9625 case Intrinsic::x86_avx_vtestz_pd_256: 9626 case Intrinsic::x86_avx_vtestc_pd_256: 9627 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9628 bool IsTestPacked = false; 9629 unsigned X86CC = 0; 9630 switch (IntNo) { 9631 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9632 case Intrinsic::x86_avx_vtestz_ps: 9633 case Intrinsic::x86_avx_vtestz_pd: 9634 case Intrinsic::x86_avx_vtestz_ps_256: 9635 case Intrinsic::x86_avx_vtestz_pd_256: 9636 IsTestPacked = true; // Fallthrough 9637 case Intrinsic::x86_sse41_ptestz: 9638 case Intrinsic::x86_avx_ptestz_256: 9639 // ZF = 1 9640 X86CC = X86::COND_E; 9641 break; 9642 case Intrinsic::x86_avx_vtestc_ps: 9643 case Intrinsic::x86_avx_vtestc_pd: 9644 case Intrinsic::x86_avx_vtestc_ps_256: 9645 case Intrinsic::x86_avx_vtestc_pd_256: 9646 IsTestPacked = true; // Fallthrough 9647 case Intrinsic::x86_sse41_ptestc: 9648 case Intrinsic::x86_avx_ptestc_256: 9649 // CF = 1 9650 X86CC = X86::COND_B; 9651 break; 9652 case Intrinsic::x86_avx_vtestnzc_ps: 9653 case Intrinsic::x86_avx_vtestnzc_pd: 9654 case Intrinsic::x86_avx_vtestnzc_ps_256: 9655 case Intrinsic::x86_avx_vtestnzc_pd_256: 9656 IsTestPacked = true; // Fallthrough 9657 case Intrinsic::x86_sse41_ptestnzc: 9658 case Intrinsic::x86_avx_ptestnzc_256: 9659 // ZF and CF = 0 9660 X86CC = X86::COND_A; 9661 break; 9662 } 9663 9664 SDValue LHS = Op.getOperand(1); 9665 SDValue RHS = Op.getOperand(2); 9666 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9667 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9668 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9669 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9670 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9671 } 9672 9673 // SSE/AVX shift intrinsics 9674 case Intrinsic::x86_sse2_psll_w: 9675 case Intrinsic::x86_sse2_psll_d: 9676 case Intrinsic::x86_sse2_psll_q: 9677 case Intrinsic::x86_avx2_psll_w: 9678 case Intrinsic::x86_avx2_psll_d: 9679 case Intrinsic::x86_avx2_psll_q: 9680 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9681 Op.getOperand(1), Op.getOperand(2)); 9682 case Intrinsic::x86_sse2_psrl_w: 9683 case Intrinsic::x86_sse2_psrl_d: 9684 case Intrinsic::x86_sse2_psrl_q: 9685 case Intrinsic::x86_avx2_psrl_w: 9686 case Intrinsic::x86_avx2_psrl_d: 9687 case Intrinsic::x86_avx2_psrl_q: 9688 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9689 Op.getOperand(1), Op.getOperand(2)); 9690 case Intrinsic::x86_sse2_psra_w: 9691 case Intrinsic::x86_sse2_psra_d: 9692 case Intrinsic::x86_avx2_psra_w: 9693 case Intrinsic::x86_avx2_psra_d: 9694 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9695 Op.getOperand(1), Op.getOperand(2)); 9696 case Intrinsic::x86_sse2_pslli_w: 9697 case Intrinsic::x86_sse2_pslli_d: 9698 case Intrinsic::x86_sse2_pslli_q: 9699 case Intrinsic::x86_avx2_pslli_w: 9700 case Intrinsic::x86_avx2_pslli_d: 9701 case Intrinsic::x86_avx2_pslli_q: 9702 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9703 Op.getOperand(1), Op.getOperand(2), DAG); 9704 case Intrinsic::x86_sse2_psrli_w: 9705 case Intrinsic::x86_sse2_psrli_d: 9706 case Intrinsic::x86_sse2_psrli_q: 9707 case Intrinsic::x86_avx2_psrli_w: 9708 case Intrinsic::x86_avx2_psrli_d: 9709 case Intrinsic::x86_avx2_psrli_q: 9710 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9711 Op.getOperand(1), Op.getOperand(2), DAG); 9712 case Intrinsic::x86_sse2_psrai_w: 9713 case Intrinsic::x86_sse2_psrai_d: 9714 case Intrinsic::x86_avx2_psrai_w: 9715 case Intrinsic::x86_avx2_psrai_d: 9716 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9717 Op.getOperand(1), Op.getOperand(2), DAG); 9718 // Fix vector shift instructions where the last operand is a non-immediate 9719 // i32 value. 9720 case Intrinsic::x86_mmx_pslli_w: 9721 case Intrinsic::x86_mmx_pslli_d: 9722 case Intrinsic::x86_mmx_pslli_q: 9723 case Intrinsic::x86_mmx_psrli_w: 9724 case Intrinsic::x86_mmx_psrli_d: 9725 case Intrinsic::x86_mmx_psrli_q: 9726 case Intrinsic::x86_mmx_psrai_w: 9727 case Intrinsic::x86_mmx_psrai_d: { 9728 SDValue ShAmt = Op.getOperand(2); 9729 if (isa<ConstantSDNode>(ShAmt)) 9730 return SDValue(); 9731 9732 unsigned NewIntNo = 0; 9733 switch (IntNo) { 9734 case Intrinsic::x86_mmx_pslli_w: 9735 NewIntNo = Intrinsic::x86_mmx_psll_w; 9736 break; 9737 case Intrinsic::x86_mmx_pslli_d: 9738 NewIntNo = Intrinsic::x86_mmx_psll_d; 9739 break; 9740 case Intrinsic::x86_mmx_pslli_q: 9741 NewIntNo = Intrinsic::x86_mmx_psll_q; 9742 break; 9743 case Intrinsic::x86_mmx_psrli_w: 9744 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9745 break; 9746 case Intrinsic::x86_mmx_psrli_d: 9747 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9748 break; 9749 case Intrinsic::x86_mmx_psrli_q: 9750 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9751 break; 9752 case Intrinsic::x86_mmx_psrai_w: 9753 NewIntNo = Intrinsic::x86_mmx_psra_w; 9754 break; 9755 case Intrinsic::x86_mmx_psrai_d: 9756 NewIntNo = Intrinsic::x86_mmx_psra_d; 9757 break; 9758 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9759 } 9760 9761 // The vector shift intrinsics with scalars uses 32b shift amounts but 9762 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9763 // to be zero. 9764 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9765 DAG.getConstant(0, MVT::i32)); 9766// FIXME this must be lowered to get rid of the invalid type. 9767 9768 EVT VT = Op.getValueType(); 9769 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9770 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9771 DAG.getConstant(NewIntNo, MVT::i32), 9772 Op.getOperand(1), ShAmt); 9773 } 9774 } 9775} 9776 9777SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9778 SelectionDAG &DAG) const { 9779 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9780 MFI->setReturnAddressIsTaken(true); 9781 9782 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9783 DebugLoc dl = Op.getDebugLoc(); 9784 9785 if (Depth > 0) { 9786 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9787 SDValue Offset = 9788 DAG.getConstant(TD->getPointerSize(), 9789 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9790 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9791 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9792 FrameAddr, Offset), 9793 MachinePointerInfo(), false, false, false, 0); 9794 } 9795 9796 // Just load the return address. 9797 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9798 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9799 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9800} 9801 9802SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9803 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9804 MFI->setFrameAddressIsTaken(true); 9805 9806 EVT VT = Op.getValueType(); 9807 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9808 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9809 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9810 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9811 while (Depth--) 9812 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9813 MachinePointerInfo(), 9814 false, false, false, 0); 9815 return FrameAddr; 9816} 9817 9818SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9819 SelectionDAG &DAG) const { 9820 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9821} 9822 9823SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9824 MachineFunction &MF = DAG.getMachineFunction(); 9825 SDValue Chain = Op.getOperand(0); 9826 SDValue Offset = Op.getOperand(1); 9827 SDValue Handler = Op.getOperand(2); 9828 DebugLoc dl = Op.getDebugLoc(); 9829 9830 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9831 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9832 getPointerTy()); 9833 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9834 9835 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9836 DAG.getIntPtrConstant(TD->getPointerSize())); 9837 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9838 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9839 false, false, 0); 9840 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9841 MF.getRegInfo().addLiveOut(StoreAddrReg); 9842 9843 return DAG.getNode(X86ISD::EH_RETURN, dl, 9844 MVT::Other, 9845 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9846} 9847 9848SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9849 SelectionDAG &DAG) const { 9850 return Op.getOperand(0); 9851} 9852 9853SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9854 SelectionDAG &DAG) const { 9855 SDValue Root = Op.getOperand(0); 9856 SDValue Trmp = Op.getOperand(1); // trampoline 9857 SDValue FPtr = Op.getOperand(2); // nested function 9858 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9859 DebugLoc dl = Op.getDebugLoc(); 9860 9861 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9862 9863 if (Subtarget->is64Bit()) { 9864 SDValue OutChains[6]; 9865 9866 // Large code-model. 9867 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9868 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9869 9870 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9871 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9872 9873 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9874 9875 // Load the pointer to the nested function into R11. 9876 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9877 SDValue Addr = Trmp; 9878 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9879 Addr, MachinePointerInfo(TrmpAddr), 9880 false, false, 0); 9881 9882 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9883 DAG.getConstant(2, MVT::i64)); 9884 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9885 MachinePointerInfo(TrmpAddr, 2), 9886 false, false, 2); 9887 9888 // Load the 'nest' parameter value into R10. 9889 // R10 is specified in X86CallingConv.td 9890 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9891 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9892 DAG.getConstant(10, MVT::i64)); 9893 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9894 Addr, MachinePointerInfo(TrmpAddr, 10), 9895 false, false, 0); 9896 9897 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9898 DAG.getConstant(12, MVT::i64)); 9899 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9900 MachinePointerInfo(TrmpAddr, 12), 9901 false, false, 2); 9902 9903 // Jump to the nested function. 9904 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9905 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9906 DAG.getConstant(20, MVT::i64)); 9907 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9908 Addr, MachinePointerInfo(TrmpAddr, 20), 9909 false, false, 0); 9910 9911 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9912 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9913 DAG.getConstant(22, MVT::i64)); 9914 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9915 MachinePointerInfo(TrmpAddr, 22), 9916 false, false, 0); 9917 9918 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9919 } else { 9920 const Function *Func = 9921 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9922 CallingConv::ID CC = Func->getCallingConv(); 9923 unsigned NestReg; 9924 9925 switch (CC) { 9926 default: 9927 llvm_unreachable("Unsupported calling convention"); 9928 case CallingConv::C: 9929 case CallingConv::X86_StdCall: { 9930 // Pass 'nest' parameter in ECX. 9931 // Must be kept in sync with X86CallingConv.td 9932 NestReg = X86::ECX; 9933 9934 // Check that ECX wasn't needed by an 'inreg' parameter. 9935 FunctionType *FTy = Func->getFunctionType(); 9936 const AttrListPtr &Attrs = Func->getAttributes(); 9937 9938 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9939 unsigned InRegCount = 0; 9940 unsigned Idx = 1; 9941 9942 for (FunctionType::param_iterator I = FTy->param_begin(), 9943 E = FTy->param_end(); I != E; ++I, ++Idx) 9944 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9945 // FIXME: should only count parameters that are lowered to integers. 9946 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9947 9948 if (InRegCount > 2) { 9949 report_fatal_error("Nest register in use - reduce number of inreg" 9950 " parameters!"); 9951 } 9952 } 9953 break; 9954 } 9955 case CallingConv::X86_FastCall: 9956 case CallingConv::X86_ThisCall: 9957 case CallingConv::Fast: 9958 // Pass 'nest' parameter in EAX. 9959 // Must be kept in sync with X86CallingConv.td 9960 NestReg = X86::EAX; 9961 break; 9962 } 9963 9964 SDValue OutChains[4]; 9965 SDValue Addr, Disp; 9966 9967 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9968 DAG.getConstant(10, MVT::i32)); 9969 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9970 9971 // This is storing the opcode for MOV32ri. 9972 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9973 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9974 OutChains[0] = DAG.getStore(Root, dl, 9975 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9976 Trmp, MachinePointerInfo(TrmpAddr), 9977 false, false, 0); 9978 9979 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9980 DAG.getConstant(1, MVT::i32)); 9981 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9982 MachinePointerInfo(TrmpAddr, 1), 9983 false, false, 1); 9984 9985 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9986 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9987 DAG.getConstant(5, MVT::i32)); 9988 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9989 MachinePointerInfo(TrmpAddr, 5), 9990 false, false, 1); 9991 9992 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9993 DAG.getConstant(6, MVT::i32)); 9994 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9995 MachinePointerInfo(TrmpAddr, 6), 9996 false, false, 1); 9997 9998 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9999 } 10000} 10001 10002SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10003 SelectionDAG &DAG) const { 10004 /* 10005 The rounding mode is in bits 11:10 of FPSR, and has the following 10006 settings: 10007 00 Round to nearest 10008 01 Round to -inf 10009 10 Round to +inf 10010 11 Round to 0 10011 10012 FLT_ROUNDS, on the other hand, expects the following: 10013 -1 Undefined 10014 0 Round to 0 10015 1 Round to nearest 10016 2 Round to +inf 10017 3 Round to -inf 10018 10019 To perform the conversion, we do: 10020 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10021 */ 10022 10023 MachineFunction &MF = DAG.getMachineFunction(); 10024 const TargetMachine &TM = MF.getTarget(); 10025 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10026 unsigned StackAlignment = TFI.getStackAlignment(); 10027 EVT VT = Op.getValueType(); 10028 DebugLoc DL = Op.getDebugLoc(); 10029 10030 // Save FP Control Word to stack slot 10031 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10032 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10033 10034 10035 MachineMemOperand *MMO = 10036 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10037 MachineMemOperand::MOStore, 2, 2); 10038 10039 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10040 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10041 DAG.getVTList(MVT::Other), 10042 Ops, 2, MVT::i16, MMO); 10043 10044 // Load FP Control Word from stack slot 10045 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10046 MachinePointerInfo(), false, false, false, 0); 10047 10048 // Transform as necessary 10049 SDValue CWD1 = 10050 DAG.getNode(ISD::SRL, DL, MVT::i16, 10051 DAG.getNode(ISD::AND, DL, MVT::i16, 10052 CWD, DAG.getConstant(0x800, MVT::i16)), 10053 DAG.getConstant(11, MVT::i8)); 10054 SDValue CWD2 = 10055 DAG.getNode(ISD::SRL, DL, MVT::i16, 10056 DAG.getNode(ISD::AND, DL, MVT::i16, 10057 CWD, DAG.getConstant(0x400, MVT::i16)), 10058 DAG.getConstant(9, MVT::i8)); 10059 10060 SDValue RetVal = 10061 DAG.getNode(ISD::AND, DL, MVT::i16, 10062 DAG.getNode(ISD::ADD, DL, MVT::i16, 10063 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10064 DAG.getConstant(1, MVT::i16)), 10065 DAG.getConstant(3, MVT::i16)); 10066 10067 10068 return DAG.getNode((VT.getSizeInBits() < 16 ? 10069 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10070} 10071 10072SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10073 EVT VT = Op.getValueType(); 10074 EVT OpVT = VT; 10075 unsigned NumBits = VT.getSizeInBits(); 10076 DebugLoc dl = Op.getDebugLoc(); 10077 10078 Op = Op.getOperand(0); 10079 if (VT == MVT::i8) { 10080 // Zero extend to i32 since there is not an i8 bsr. 10081 OpVT = MVT::i32; 10082 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10083 } 10084 10085 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10086 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10087 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10088 10089 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10090 SDValue Ops[] = { 10091 Op, 10092 DAG.getConstant(NumBits+NumBits-1, OpVT), 10093 DAG.getConstant(X86::COND_E, MVT::i8), 10094 Op.getValue(1) 10095 }; 10096 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10097 10098 // Finally xor with NumBits-1. 10099 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10100 10101 if (VT == MVT::i8) 10102 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10103 return Op; 10104} 10105 10106SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10107 SelectionDAG &DAG) const { 10108 EVT VT = Op.getValueType(); 10109 EVT OpVT = VT; 10110 unsigned NumBits = VT.getSizeInBits(); 10111 DebugLoc dl = Op.getDebugLoc(); 10112 10113 Op = Op.getOperand(0); 10114 if (VT == MVT::i8) { 10115 // Zero extend to i32 since there is not an i8 bsr. 10116 OpVT = MVT::i32; 10117 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10118 } 10119 10120 // Issue a bsr (scan bits in reverse). 10121 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10122 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10123 10124 // And xor with NumBits-1. 10125 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10126 10127 if (VT == MVT::i8) 10128 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10129 return Op; 10130} 10131 10132SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10133 EVT VT = Op.getValueType(); 10134 unsigned NumBits = VT.getSizeInBits(); 10135 DebugLoc dl = Op.getDebugLoc(); 10136 Op = Op.getOperand(0); 10137 10138 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10139 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10140 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10141 10142 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10143 SDValue Ops[] = { 10144 Op, 10145 DAG.getConstant(NumBits, VT), 10146 DAG.getConstant(X86::COND_E, MVT::i8), 10147 Op.getValue(1) 10148 }; 10149 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10150} 10151 10152// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10153// ones, and then concatenate the result back. 10154static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10155 EVT VT = Op.getValueType(); 10156 10157 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10158 "Unsupported value type for operation"); 10159 10160 int NumElems = VT.getVectorNumElements(); 10161 DebugLoc dl = Op.getDebugLoc(); 10162 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10163 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10164 10165 // Extract the LHS vectors 10166 SDValue LHS = Op.getOperand(0); 10167 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10168 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10169 10170 // Extract the RHS vectors 10171 SDValue RHS = Op.getOperand(1); 10172 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10173 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10174 10175 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10176 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10177 10178 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10179 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10180 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10181} 10182 10183SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10184 assert(Op.getValueType().getSizeInBits() == 256 && 10185 Op.getValueType().isInteger() && 10186 "Only handle AVX 256-bit vector integer operation"); 10187 return Lower256IntArith(Op, DAG); 10188} 10189 10190SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10191 assert(Op.getValueType().getSizeInBits() == 256 && 10192 Op.getValueType().isInteger() && 10193 "Only handle AVX 256-bit vector integer operation"); 10194 return Lower256IntArith(Op, DAG); 10195} 10196 10197SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10198 EVT VT = Op.getValueType(); 10199 10200 // Decompose 256-bit ops into smaller 128-bit ops. 10201 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10202 return Lower256IntArith(Op, DAG); 10203 10204 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10205 "Only know how to lower V2I64/V4I64 multiply"); 10206 10207 DebugLoc dl = Op.getDebugLoc(); 10208 10209 // Ahi = psrlqi(a, 32); 10210 // Bhi = psrlqi(b, 32); 10211 // 10212 // AloBlo = pmuludq(a, b); 10213 // AloBhi = pmuludq(a, Bhi); 10214 // AhiBlo = pmuludq(Ahi, b); 10215 10216 // AloBhi = psllqi(AloBhi, 32); 10217 // AhiBlo = psllqi(AhiBlo, 32); 10218 // return AloBlo + AloBhi + AhiBlo; 10219 10220 SDValue A = Op.getOperand(0); 10221 SDValue B = Op.getOperand(1); 10222 10223 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10224 10225 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10226 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10227 10228 // Bit cast to 32-bit vectors for MULUDQ 10229 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10230 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10231 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10232 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10233 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10234 10235 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10236 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10237 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10238 10239 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10240 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10241 10242 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10243 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10244} 10245 10246SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10247 10248 EVT VT = Op.getValueType(); 10249 DebugLoc dl = Op.getDebugLoc(); 10250 SDValue R = Op.getOperand(0); 10251 SDValue Amt = Op.getOperand(1); 10252 LLVMContext *Context = DAG.getContext(); 10253 10254 if (!Subtarget->hasSSE2()) 10255 return SDValue(); 10256 10257 // Optimize shl/srl/sra with constant shift amount. 10258 if (isSplatVector(Amt.getNode())) { 10259 SDValue SclrAmt = Amt->getOperand(0); 10260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10261 uint64_t ShiftAmt = C->getZExtValue(); 10262 10263 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10264 (Subtarget->hasAVX2() && 10265 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10266 if (Op.getOpcode() == ISD::SHL) 10267 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10268 DAG.getConstant(ShiftAmt, MVT::i32)); 10269 if (Op.getOpcode() == ISD::SRL) 10270 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10271 DAG.getConstant(ShiftAmt, MVT::i32)); 10272 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10273 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10274 DAG.getConstant(ShiftAmt, MVT::i32)); 10275 } 10276 10277 if (VT == MVT::v16i8) { 10278 if (Op.getOpcode() == ISD::SHL) { 10279 // Make a large shift. 10280 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10281 DAG.getConstant(ShiftAmt, MVT::i32)); 10282 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10283 // Zero out the rightmost bits. 10284 SmallVector<SDValue, 16> V(16, 10285 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10286 MVT::i8)); 10287 return DAG.getNode(ISD::AND, dl, VT, SHL, 10288 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10289 } 10290 if (Op.getOpcode() == ISD::SRL) { 10291 // Make a large shift. 10292 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10293 DAG.getConstant(ShiftAmt, MVT::i32)); 10294 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10295 // Zero out the leftmost bits. 10296 SmallVector<SDValue, 16> V(16, 10297 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10298 MVT::i8)); 10299 return DAG.getNode(ISD::AND, dl, VT, SRL, 10300 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10301 } 10302 if (Op.getOpcode() == ISD::SRA) { 10303 if (ShiftAmt == 7) { 10304 // R s>> 7 === R s< 0 10305 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10306 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10307 } 10308 10309 // R s>> a === ((R u>> a) ^ m) - m 10310 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10311 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10312 MVT::i8)); 10313 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10314 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10315 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10316 return Res; 10317 } 10318 } 10319 10320 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10321 if (Op.getOpcode() == ISD::SHL) { 10322 // Make a large shift. 10323 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10324 DAG.getConstant(ShiftAmt, MVT::i32)); 10325 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10326 // Zero out the rightmost bits. 10327 SmallVector<SDValue, 32> V(32, 10328 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10329 MVT::i8)); 10330 return DAG.getNode(ISD::AND, dl, VT, SHL, 10331 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10332 } 10333 if (Op.getOpcode() == ISD::SRL) { 10334 // Make a large shift. 10335 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10336 DAG.getConstant(ShiftAmt, MVT::i32)); 10337 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10338 // Zero out the leftmost bits. 10339 SmallVector<SDValue, 32> V(32, 10340 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10341 MVT::i8)); 10342 return DAG.getNode(ISD::AND, dl, VT, SRL, 10343 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10344 } 10345 if (Op.getOpcode() == ISD::SRA) { 10346 if (ShiftAmt == 7) { 10347 // R s>> 7 === R s< 0 10348 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10349 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10350 } 10351 10352 // R s>> a === ((R u>> a) ^ m) - m 10353 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10354 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10355 MVT::i8)); 10356 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10357 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10358 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10359 return Res; 10360 } 10361 } 10362 } 10363 } 10364 10365 // Lower SHL with variable shift amount. 10366 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10367 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10368 DAG.getConstant(23, MVT::i32)); 10369 10370 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10371 Constant *C = ConstantDataVector::get(*Context, CV); 10372 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10373 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10374 MachinePointerInfo::getConstantPool(), 10375 false, false, false, 16); 10376 10377 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10378 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10379 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10380 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10381 } 10382 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10383 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10384 10385 // a = a << 5; 10386 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10387 DAG.getConstant(5, MVT::i32)); 10388 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10389 10390 // Turn 'a' into a mask suitable for VSELECT 10391 SDValue VSelM = DAG.getConstant(0x80, VT); 10392 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10393 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10394 10395 SDValue CM1 = DAG.getConstant(0x0f, VT); 10396 SDValue CM2 = DAG.getConstant(0x3f, VT); 10397 10398 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10399 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10400 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10401 DAG.getConstant(4, MVT::i32), DAG); 10402 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10403 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10404 10405 // a += a 10406 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10407 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10408 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10409 10410 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10411 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10412 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10413 DAG.getConstant(2, MVT::i32), DAG); 10414 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10415 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10416 10417 // a += a 10418 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10419 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10420 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10421 10422 // return VSELECT(r, r+r, a); 10423 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10424 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10425 return R; 10426 } 10427 10428 // Decompose 256-bit shifts into smaller 128-bit shifts. 10429 if (VT.getSizeInBits() == 256) { 10430 unsigned NumElems = VT.getVectorNumElements(); 10431 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10432 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10433 10434 // Extract the two vectors 10435 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10436 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10437 DAG, dl); 10438 10439 // Recreate the shift amount vectors 10440 SDValue Amt1, Amt2; 10441 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10442 // Constant shift amount 10443 SmallVector<SDValue, 4> Amt1Csts; 10444 SmallVector<SDValue, 4> Amt2Csts; 10445 for (unsigned i = 0; i != NumElems/2; ++i) 10446 Amt1Csts.push_back(Amt->getOperand(i)); 10447 for (unsigned i = NumElems/2; i != NumElems; ++i) 10448 Amt2Csts.push_back(Amt->getOperand(i)); 10449 10450 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10451 &Amt1Csts[0], NumElems/2); 10452 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10453 &Amt2Csts[0], NumElems/2); 10454 } else { 10455 // Variable shift amount 10456 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10457 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10458 DAG, dl); 10459 } 10460 10461 // Issue new vector shifts for the smaller types 10462 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10463 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10464 10465 // Concatenate the result back 10466 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10467 } 10468 10469 return SDValue(); 10470} 10471 10472SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10473 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10474 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10475 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10476 // has only one use. 10477 SDNode *N = Op.getNode(); 10478 SDValue LHS = N->getOperand(0); 10479 SDValue RHS = N->getOperand(1); 10480 unsigned BaseOp = 0; 10481 unsigned Cond = 0; 10482 DebugLoc DL = Op.getDebugLoc(); 10483 switch (Op.getOpcode()) { 10484 default: llvm_unreachable("Unknown ovf instruction!"); 10485 case ISD::SADDO: 10486 // A subtract of one will be selected as a INC. Note that INC doesn't 10487 // set CF, so we can't do this for UADDO. 10488 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10489 if (C->isOne()) { 10490 BaseOp = X86ISD::INC; 10491 Cond = X86::COND_O; 10492 break; 10493 } 10494 BaseOp = X86ISD::ADD; 10495 Cond = X86::COND_O; 10496 break; 10497 case ISD::UADDO: 10498 BaseOp = X86ISD::ADD; 10499 Cond = X86::COND_B; 10500 break; 10501 case ISD::SSUBO: 10502 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10503 // set CF, so we can't do this for USUBO. 10504 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10505 if (C->isOne()) { 10506 BaseOp = X86ISD::DEC; 10507 Cond = X86::COND_O; 10508 break; 10509 } 10510 BaseOp = X86ISD::SUB; 10511 Cond = X86::COND_O; 10512 break; 10513 case ISD::USUBO: 10514 BaseOp = X86ISD::SUB; 10515 Cond = X86::COND_B; 10516 break; 10517 case ISD::SMULO: 10518 BaseOp = X86ISD::SMUL; 10519 Cond = X86::COND_O; 10520 break; 10521 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10522 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10523 MVT::i32); 10524 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10525 10526 SDValue SetCC = 10527 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10528 DAG.getConstant(X86::COND_O, MVT::i32), 10529 SDValue(Sum.getNode(), 2)); 10530 10531 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10532 } 10533 } 10534 10535 // Also sets EFLAGS. 10536 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10537 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10538 10539 SDValue SetCC = 10540 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10541 DAG.getConstant(Cond, MVT::i32), 10542 SDValue(Sum.getNode(), 1)); 10543 10544 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10545} 10546 10547SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10548 SelectionDAG &DAG) const { 10549 DebugLoc dl = Op.getDebugLoc(); 10550 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10551 EVT VT = Op.getValueType(); 10552 10553 if (!Subtarget->hasSSE2() || !VT.isVector()) 10554 return SDValue(); 10555 10556 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10557 ExtraVT.getScalarType().getSizeInBits(); 10558 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10559 10560 switch (VT.getSimpleVT().SimpleTy) { 10561 default: return SDValue(); 10562 case MVT::v8i32: 10563 case MVT::v16i16: 10564 if (!Subtarget->hasAVX()) 10565 return SDValue(); 10566 if (!Subtarget->hasAVX2()) { 10567 // needs to be split 10568 int NumElems = VT.getVectorNumElements(); 10569 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10570 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10571 10572 // Extract the LHS vectors 10573 SDValue LHS = Op.getOperand(0); 10574 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10575 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10576 10577 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10578 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10579 10580 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10581 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10582 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10583 ExtraNumElems/2); 10584 SDValue Extra = DAG.getValueType(ExtraVT); 10585 10586 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10587 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10588 10589 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10590 } 10591 // fall through 10592 case MVT::v4i32: 10593 case MVT::v8i16: { 10594 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10595 Op.getOperand(0), ShAmt, DAG); 10596 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10597 } 10598 } 10599} 10600 10601 10602SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10603 DebugLoc dl = Op.getDebugLoc(); 10604 10605 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10606 // There isn't any reason to disable it if the target processor supports it. 10607 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10608 SDValue Chain = Op.getOperand(0); 10609 SDValue Zero = DAG.getConstant(0, MVT::i32); 10610 SDValue Ops[] = { 10611 DAG.getRegister(X86::ESP, MVT::i32), // Base 10612 DAG.getTargetConstant(1, MVT::i8), // Scale 10613 DAG.getRegister(0, MVT::i32), // Index 10614 DAG.getTargetConstant(0, MVT::i32), // Disp 10615 DAG.getRegister(0, MVT::i32), // Segment. 10616 Zero, 10617 Chain 10618 }; 10619 SDNode *Res = 10620 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10621 array_lengthof(Ops)); 10622 return SDValue(Res, 0); 10623 } 10624 10625 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10626 if (!isDev) 10627 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10628 10629 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10630 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10631 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10632 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10633 10634 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10635 if (!Op1 && !Op2 && !Op3 && Op4) 10636 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10637 10638 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10639 if (Op1 && !Op2 && !Op3 && !Op4) 10640 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10641 10642 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10643 // (MFENCE)>; 10644 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10645} 10646 10647SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10648 SelectionDAG &DAG) const { 10649 DebugLoc dl = Op.getDebugLoc(); 10650 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10651 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10652 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10653 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10654 10655 // The only fence that needs an instruction is a sequentially-consistent 10656 // cross-thread fence. 10657 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10658 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10659 // no-sse2). There isn't any reason to disable it if the target processor 10660 // supports it. 10661 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10662 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10663 10664 SDValue Chain = Op.getOperand(0); 10665 SDValue Zero = DAG.getConstant(0, MVT::i32); 10666 SDValue Ops[] = { 10667 DAG.getRegister(X86::ESP, MVT::i32), // Base 10668 DAG.getTargetConstant(1, MVT::i8), // Scale 10669 DAG.getRegister(0, MVT::i32), // Index 10670 DAG.getTargetConstant(0, MVT::i32), // Disp 10671 DAG.getRegister(0, MVT::i32), // Segment. 10672 Zero, 10673 Chain 10674 }; 10675 SDNode *Res = 10676 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10677 array_lengthof(Ops)); 10678 return SDValue(Res, 0); 10679 } 10680 10681 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10682 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10683} 10684 10685 10686SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10687 EVT T = Op.getValueType(); 10688 DebugLoc DL = Op.getDebugLoc(); 10689 unsigned Reg = 0; 10690 unsigned size = 0; 10691 switch(T.getSimpleVT().SimpleTy) { 10692 default: llvm_unreachable("Invalid value type!"); 10693 case MVT::i8: Reg = X86::AL; size = 1; break; 10694 case MVT::i16: Reg = X86::AX; size = 2; break; 10695 case MVT::i32: Reg = X86::EAX; size = 4; break; 10696 case MVT::i64: 10697 assert(Subtarget->is64Bit() && "Node not type legal!"); 10698 Reg = X86::RAX; size = 8; 10699 break; 10700 } 10701 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10702 Op.getOperand(2), SDValue()); 10703 SDValue Ops[] = { cpIn.getValue(0), 10704 Op.getOperand(1), 10705 Op.getOperand(3), 10706 DAG.getTargetConstant(size, MVT::i8), 10707 cpIn.getValue(1) }; 10708 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10709 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10710 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10711 Ops, 5, T, MMO); 10712 SDValue cpOut = 10713 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10714 return cpOut; 10715} 10716 10717SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10718 SelectionDAG &DAG) const { 10719 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10720 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10721 SDValue TheChain = Op.getOperand(0); 10722 DebugLoc dl = Op.getDebugLoc(); 10723 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10724 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10725 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10726 rax.getValue(2)); 10727 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10728 DAG.getConstant(32, MVT::i8)); 10729 SDValue Ops[] = { 10730 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10731 rdx.getValue(1) 10732 }; 10733 return DAG.getMergeValues(Ops, 2, dl); 10734} 10735 10736SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10737 SelectionDAG &DAG) const { 10738 EVT SrcVT = Op.getOperand(0).getValueType(); 10739 EVT DstVT = Op.getValueType(); 10740 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10741 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10742 assert((DstVT == MVT::i64 || 10743 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10744 "Unexpected custom BITCAST"); 10745 // i64 <=> MMX conversions are Legal. 10746 if (SrcVT==MVT::i64 && DstVT.isVector()) 10747 return Op; 10748 if (DstVT==MVT::i64 && SrcVT.isVector()) 10749 return Op; 10750 // MMX <=> MMX conversions are Legal. 10751 if (SrcVT.isVector() && DstVT.isVector()) 10752 return Op; 10753 // All other conversions need to be expanded. 10754 return SDValue(); 10755} 10756 10757SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10758 SDNode *Node = Op.getNode(); 10759 DebugLoc dl = Node->getDebugLoc(); 10760 EVT T = Node->getValueType(0); 10761 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10762 DAG.getConstant(0, T), Node->getOperand(2)); 10763 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10764 cast<AtomicSDNode>(Node)->getMemoryVT(), 10765 Node->getOperand(0), 10766 Node->getOperand(1), negOp, 10767 cast<AtomicSDNode>(Node)->getSrcValue(), 10768 cast<AtomicSDNode>(Node)->getAlignment(), 10769 cast<AtomicSDNode>(Node)->getOrdering(), 10770 cast<AtomicSDNode>(Node)->getSynchScope()); 10771} 10772 10773static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10774 SDNode *Node = Op.getNode(); 10775 DebugLoc dl = Node->getDebugLoc(); 10776 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10777 10778 // Convert seq_cst store -> xchg 10779 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10780 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10781 // (The only way to get a 16-byte store is cmpxchg16b) 10782 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10783 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10784 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10785 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10786 cast<AtomicSDNode>(Node)->getMemoryVT(), 10787 Node->getOperand(0), 10788 Node->getOperand(1), Node->getOperand(2), 10789 cast<AtomicSDNode>(Node)->getMemOperand(), 10790 cast<AtomicSDNode>(Node)->getOrdering(), 10791 cast<AtomicSDNode>(Node)->getSynchScope()); 10792 return Swap.getValue(1); 10793 } 10794 // Other atomic stores have a simple pattern. 10795 return Op; 10796} 10797 10798static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10799 EVT VT = Op.getNode()->getValueType(0); 10800 10801 // Let legalize expand this if it isn't a legal type yet. 10802 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10803 return SDValue(); 10804 10805 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10806 10807 unsigned Opc; 10808 bool ExtraOp = false; 10809 switch (Op.getOpcode()) { 10810 default: llvm_unreachable("Invalid code"); 10811 case ISD::ADDC: Opc = X86ISD::ADD; break; 10812 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10813 case ISD::SUBC: Opc = X86ISD::SUB; break; 10814 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10815 } 10816 10817 if (!ExtraOp) 10818 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10819 Op.getOperand(1)); 10820 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10821 Op.getOperand(1), Op.getOperand(2)); 10822} 10823 10824/// LowerOperation - Provide custom lowering hooks for some operations. 10825/// 10826SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10827 switch (Op.getOpcode()) { 10828 default: llvm_unreachable("Should not custom lower this!"); 10829 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10830 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10831 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10832 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10833 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10834 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10835 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10836 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10837 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10838 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10839 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10840 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10841 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10842 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10843 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10844 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10845 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10846 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10847 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10848 case ISD::SHL_PARTS: 10849 case ISD::SRA_PARTS: 10850 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10851 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10852 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10853 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10854 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10855 case ISD::FABS: return LowerFABS(Op, DAG); 10856 case ISD::FNEG: return LowerFNEG(Op, DAG); 10857 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10858 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10859 case ISD::SETCC: return LowerSETCC(Op, DAG); 10860 case ISD::SELECT: return LowerSELECT(Op, DAG); 10861 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10862 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10863 case ISD::VASTART: return LowerVASTART(Op, DAG); 10864 case ISD::VAARG: return LowerVAARG(Op, DAG); 10865 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10866 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10867 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10868 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10869 case ISD::FRAME_TO_ARGS_OFFSET: 10870 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10871 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10872 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10873 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10874 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10875 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10876 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10877 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10878 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10879 case ISD::MUL: return LowerMUL(Op, DAG); 10880 case ISD::SRA: 10881 case ISD::SRL: 10882 case ISD::SHL: return LowerShift(Op, DAG); 10883 case ISD::SADDO: 10884 case ISD::UADDO: 10885 case ISD::SSUBO: 10886 case ISD::USUBO: 10887 case ISD::SMULO: 10888 case ISD::UMULO: return LowerXALUO(Op, DAG); 10889 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10890 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10891 case ISD::ADDC: 10892 case ISD::ADDE: 10893 case ISD::SUBC: 10894 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10895 case ISD::ADD: return LowerADD(Op, DAG); 10896 case ISD::SUB: return LowerSUB(Op, DAG); 10897 } 10898} 10899 10900static void ReplaceATOMIC_LOAD(SDNode *Node, 10901 SmallVectorImpl<SDValue> &Results, 10902 SelectionDAG &DAG) { 10903 DebugLoc dl = Node->getDebugLoc(); 10904 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10905 10906 // Convert wide load -> cmpxchg8b/cmpxchg16b 10907 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10908 // (The only way to get a 16-byte load is cmpxchg16b) 10909 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10910 SDValue Zero = DAG.getConstant(0, VT); 10911 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10912 Node->getOperand(0), 10913 Node->getOperand(1), Zero, Zero, 10914 cast<AtomicSDNode>(Node)->getMemOperand(), 10915 cast<AtomicSDNode>(Node)->getOrdering(), 10916 cast<AtomicSDNode>(Node)->getSynchScope()); 10917 Results.push_back(Swap.getValue(0)); 10918 Results.push_back(Swap.getValue(1)); 10919} 10920 10921void X86TargetLowering:: 10922ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10923 SelectionDAG &DAG, unsigned NewOp) const { 10924 DebugLoc dl = Node->getDebugLoc(); 10925 assert (Node->getValueType(0) == MVT::i64 && 10926 "Only know how to expand i64 atomics"); 10927 10928 SDValue Chain = Node->getOperand(0); 10929 SDValue In1 = Node->getOperand(1); 10930 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10931 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10932 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10933 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10934 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10935 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10936 SDValue Result = 10937 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10938 cast<MemSDNode>(Node)->getMemOperand()); 10939 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10940 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10941 Results.push_back(Result.getValue(2)); 10942} 10943 10944/// ReplaceNodeResults - Replace a node with an illegal result type 10945/// with a new node built out of custom code. 10946void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10947 SmallVectorImpl<SDValue>&Results, 10948 SelectionDAG &DAG) const { 10949 DebugLoc dl = N->getDebugLoc(); 10950 switch (N->getOpcode()) { 10951 default: 10952 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10953 case ISD::SIGN_EXTEND_INREG: 10954 case ISD::ADDC: 10955 case ISD::ADDE: 10956 case ISD::SUBC: 10957 case ISD::SUBE: 10958 // We don't want to expand or promote these. 10959 return; 10960 case ISD::FP_TO_SINT: 10961 case ISD::FP_TO_UINT: { 10962 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 10963 10964 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 10965 return; 10966 10967 std::pair<SDValue,SDValue> Vals = 10968 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 10969 SDValue FIST = Vals.first, StackSlot = Vals.second; 10970 if (FIST.getNode() != 0) { 10971 EVT VT = N->getValueType(0); 10972 // Return a load from the stack slot. 10973 if (StackSlot.getNode() != 0) 10974 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10975 MachinePointerInfo(), 10976 false, false, false, 0)); 10977 else 10978 Results.push_back(FIST); 10979 } 10980 return; 10981 } 10982 case ISD::READCYCLECOUNTER: { 10983 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10984 SDValue TheChain = N->getOperand(0); 10985 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10986 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10987 rd.getValue(1)); 10988 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10989 eax.getValue(2)); 10990 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10991 SDValue Ops[] = { eax, edx }; 10992 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10993 Results.push_back(edx.getValue(1)); 10994 return; 10995 } 10996 case ISD::ATOMIC_CMP_SWAP: { 10997 EVT T = N->getValueType(0); 10998 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10999 bool Regs64bit = T == MVT::i128; 11000 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11001 SDValue cpInL, cpInH; 11002 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11003 DAG.getConstant(0, HalfT)); 11004 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11005 DAG.getConstant(1, HalfT)); 11006 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11007 Regs64bit ? X86::RAX : X86::EAX, 11008 cpInL, SDValue()); 11009 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11010 Regs64bit ? X86::RDX : X86::EDX, 11011 cpInH, cpInL.getValue(1)); 11012 SDValue swapInL, swapInH; 11013 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11014 DAG.getConstant(0, HalfT)); 11015 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11016 DAG.getConstant(1, HalfT)); 11017 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11018 Regs64bit ? X86::RBX : X86::EBX, 11019 swapInL, cpInH.getValue(1)); 11020 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11021 Regs64bit ? X86::RCX : X86::ECX, 11022 swapInH, swapInL.getValue(1)); 11023 SDValue Ops[] = { swapInH.getValue(0), 11024 N->getOperand(1), 11025 swapInH.getValue(1) }; 11026 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11027 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11028 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11029 X86ISD::LCMPXCHG8_DAG; 11030 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11031 Ops, 3, T, MMO); 11032 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11033 Regs64bit ? X86::RAX : X86::EAX, 11034 HalfT, Result.getValue(1)); 11035 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11036 Regs64bit ? X86::RDX : X86::EDX, 11037 HalfT, cpOutL.getValue(2)); 11038 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11039 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11040 Results.push_back(cpOutH.getValue(1)); 11041 return; 11042 } 11043 case ISD::ATOMIC_LOAD_ADD: 11044 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 11045 return; 11046 case ISD::ATOMIC_LOAD_AND: 11047 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 11048 return; 11049 case ISD::ATOMIC_LOAD_NAND: 11050 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 11051 return; 11052 case ISD::ATOMIC_LOAD_OR: 11053 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 11054 return; 11055 case ISD::ATOMIC_LOAD_SUB: 11056 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 11057 return; 11058 case ISD::ATOMIC_LOAD_XOR: 11059 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11060 return; 11061 case ISD::ATOMIC_SWAP: 11062 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11063 return; 11064 case ISD::ATOMIC_LOAD: 11065 ReplaceATOMIC_LOAD(N, Results, DAG); 11066 } 11067} 11068 11069const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11070 switch (Opcode) { 11071 default: return NULL; 11072 case X86ISD::BSF: return "X86ISD::BSF"; 11073 case X86ISD::BSR: return "X86ISD::BSR"; 11074 case X86ISD::SHLD: return "X86ISD::SHLD"; 11075 case X86ISD::SHRD: return "X86ISD::SHRD"; 11076 case X86ISD::FAND: return "X86ISD::FAND"; 11077 case X86ISD::FOR: return "X86ISD::FOR"; 11078 case X86ISD::FXOR: return "X86ISD::FXOR"; 11079 case X86ISD::FSRL: return "X86ISD::FSRL"; 11080 case X86ISD::FILD: return "X86ISD::FILD"; 11081 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11082 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11083 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11084 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11085 case X86ISD::FLD: return "X86ISD::FLD"; 11086 case X86ISD::FST: return "X86ISD::FST"; 11087 case X86ISD::CALL: return "X86ISD::CALL"; 11088 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11089 case X86ISD::BT: return "X86ISD::BT"; 11090 case X86ISD::CMP: return "X86ISD::CMP"; 11091 case X86ISD::COMI: return "X86ISD::COMI"; 11092 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11093 case X86ISD::SETCC: return "X86ISD::SETCC"; 11094 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11095 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11096 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11097 case X86ISD::CMOV: return "X86ISD::CMOV"; 11098 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11099 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11100 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11101 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11102 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11103 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11104 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11105 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11106 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11107 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11108 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11109 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11110 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11111 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11112 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11113 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11114 case X86ISD::BLENDPW: return "X86ISD::BLENDPW"; 11115 case X86ISD::BLENDPS: return "X86ISD::BLENDPS"; 11116 case X86ISD::BLENDPD: return "X86ISD::BLENDPD"; 11117 case X86ISD::HADD: return "X86ISD::HADD"; 11118 case X86ISD::HSUB: return "X86ISD::HSUB"; 11119 case X86ISD::FHADD: return "X86ISD::FHADD"; 11120 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11121 case X86ISD::FMAX: return "X86ISD::FMAX"; 11122 case X86ISD::FMIN: return "X86ISD::FMIN"; 11123 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11124 case X86ISD::FRCP: return "X86ISD::FRCP"; 11125 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11126 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11127 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11128 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11129 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11130 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11131 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11132 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11133 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11134 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11135 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11136 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11137 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11138 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11139 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11140 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11141 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11142 case X86ISD::VSHL: return "X86ISD::VSHL"; 11143 case X86ISD::VSRL: return "X86ISD::VSRL"; 11144 case X86ISD::VSRA: return "X86ISD::VSRA"; 11145 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11146 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11147 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11148 case X86ISD::CMPP: return "X86ISD::CMPP"; 11149 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11150 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11151 case X86ISD::ADD: return "X86ISD::ADD"; 11152 case X86ISD::SUB: return "X86ISD::SUB"; 11153 case X86ISD::ADC: return "X86ISD::ADC"; 11154 case X86ISD::SBB: return "X86ISD::SBB"; 11155 case X86ISD::SMUL: return "X86ISD::SMUL"; 11156 case X86ISD::UMUL: return "X86ISD::UMUL"; 11157 case X86ISD::INC: return "X86ISD::INC"; 11158 case X86ISD::DEC: return "X86ISD::DEC"; 11159 case X86ISD::OR: return "X86ISD::OR"; 11160 case X86ISD::XOR: return "X86ISD::XOR"; 11161 case X86ISD::AND: return "X86ISD::AND"; 11162 case X86ISD::ANDN: return "X86ISD::ANDN"; 11163 case X86ISD::BLSI: return "X86ISD::BLSI"; 11164 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11165 case X86ISD::BLSR: return "X86ISD::BLSR"; 11166 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11167 case X86ISD::PTEST: return "X86ISD::PTEST"; 11168 case X86ISD::TESTP: return "X86ISD::TESTP"; 11169 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11170 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11171 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11172 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11173 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11174 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11175 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11176 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11177 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11178 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11179 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11180 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11181 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11182 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11183 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11184 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11185 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11186 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11187 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11188 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11189 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 11190 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 11191 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11192 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11193 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11194 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11195 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11196 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11197 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11198 } 11199} 11200 11201// isLegalAddressingMode - Return true if the addressing mode represented 11202// by AM is legal for this target, for a load/store of the specified type. 11203bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11204 Type *Ty) const { 11205 // X86 supports extremely general addressing modes. 11206 CodeModel::Model M = getTargetMachine().getCodeModel(); 11207 Reloc::Model R = getTargetMachine().getRelocationModel(); 11208 11209 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11210 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11211 return false; 11212 11213 if (AM.BaseGV) { 11214 unsigned GVFlags = 11215 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11216 11217 // If a reference to this global requires an extra load, we can't fold it. 11218 if (isGlobalStubReference(GVFlags)) 11219 return false; 11220 11221 // If BaseGV requires a register for the PIC base, we cannot also have a 11222 // BaseReg specified. 11223 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11224 return false; 11225 11226 // If lower 4G is not available, then we must use rip-relative addressing. 11227 if ((M != CodeModel::Small || R != Reloc::Static) && 11228 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11229 return false; 11230 } 11231 11232 switch (AM.Scale) { 11233 case 0: 11234 case 1: 11235 case 2: 11236 case 4: 11237 case 8: 11238 // These scales always work. 11239 break; 11240 case 3: 11241 case 5: 11242 case 9: 11243 // These scales are formed with basereg+scalereg. Only accept if there is 11244 // no basereg yet. 11245 if (AM.HasBaseReg) 11246 return false; 11247 break; 11248 default: // Other stuff never works. 11249 return false; 11250 } 11251 11252 return true; 11253} 11254 11255 11256bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11257 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11258 return false; 11259 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11260 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11261 if (NumBits1 <= NumBits2) 11262 return false; 11263 return true; 11264} 11265 11266bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11267 if (!VT1.isInteger() || !VT2.isInteger()) 11268 return false; 11269 unsigned NumBits1 = VT1.getSizeInBits(); 11270 unsigned NumBits2 = VT2.getSizeInBits(); 11271 if (NumBits1 <= NumBits2) 11272 return false; 11273 return true; 11274} 11275 11276bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11277 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11278 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11279} 11280 11281bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11282 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11283 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11284} 11285 11286bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11287 // i16 instructions are longer (0x66 prefix) and potentially slower. 11288 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11289} 11290 11291/// isShuffleMaskLegal - Targets can use this to indicate that they only 11292/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11293/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11294/// are assumed to be legal. 11295bool 11296X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11297 EVT VT) const { 11298 // Very little shuffling can be done for 64-bit vectors right now. 11299 if (VT.getSizeInBits() == 64) 11300 return false; 11301 11302 // FIXME: pshufb, blends, shifts. 11303 return (VT.getVectorNumElements() == 2 || 11304 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11305 isMOVLMask(M, VT) || 11306 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11307 isPSHUFDMask(M, VT) || 11308 isPSHUFHWMask(M, VT) || 11309 isPSHUFLWMask(M, VT) || 11310 isPALIGNRMask(M, VT, Subtarget) || 11311 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11312 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11313 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11314 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11315} 11316 11317bool 11318X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11319 EVT VT) const { 11320 unsigned NumElts = VT.getVectorNumElements(); 11321 // FIXME: This collection of masks seems suspect. 11322 if (NumElts == 2) 11323 return true; 11324 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11325 return (isMOVLMask(Mask, VT) || 11326 isCommutedMOVLMask(Mask, VT, true) || 11327 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11328 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11329 } 11330 return false; 11331} 11332 11333//===----------------------------------------------------------------------===// 11334// X86 Scheduler Hooks 11335//===----------------------------------------------------------------------===// 11336 11337// private utility function 11338MachineBasicBlock * 11339X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11340 MachineBasicBlock *MBB, 11341 unsigned regOpc, 11342 unsigned immOpc, 11343 unsigned LoadOpc, 11344 unsigned CXchgOpc, 11345 unsigned notOpc, 11346 unsigned EAXreg, 11347 const TargetRegisterClass *RC, 11348 bool Invert) const { 11349 // For the atomic bitwise operator, we generate 11350 // thisMBB: 11351 // newMBB: 11352 // ld t1 = [bitinstr.addr] 11353 // op t2 = t1, [bitinstr.val] 11354 // not t3 = t2 (if Invert) 11355 // mov EAX = t1 11356 // lcs dest = [bitinstr.addr], t3 [EAX is implicit] 11357 // bz newMBB 11358 // fallthrough -->nextMBB 11359 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11360 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11361 MachineFunction::iterator MBBIter = MBB; 11362 ++MBBIter; 11363 11364 /// First build the CFG 11365 MachineFunction *F = MBB->getParent(); 11366 MachineBasicBlock *thisMBB = MBB; 11367 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11368 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11369 F->insert(MBBIter, newMBB); 11370 F->insert(MBBIter, nextMBB); 11371 11372 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11373 nextMBB->splice(nextMBB->begin(), thisMBB, 11374 llvm::next(MachineBasicBlock::iterator(bInstr)), 11375 thisMBB->end()); 11376 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11377 11378 // Update thisMBB to fall through to newMBB 11379 thisMBB->addSuccessor(newMBB); 11380 11381 // newMBB jumps to itself and fall through to nextMBB 11382 newMBB->addSuccessor(nextMBB); 11383 newMBB->addSuccessor(newMBB); 11384 11385 // Insert instructions into newMBB based on incoming instruction 11386 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11387 "unexpected number of operands"); 11388 DebugLoc dl = bInstr->getDebugLoc(); 11389 MachineOperand& destOper = bInstr->getOperand(0); 11390 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11391 int numArgs = bInstr->getNumOperands() - 1; 11392 for (int i=0; i < numArgs; ++i) 11393 argOpers[i] = &bInstr->getOperand(i+1); 11394 11395 // x86 address has 4 operands: base, index, scale, and displacement 11396 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11397 int valArgIndx = lastAddrIndx + 1; 11398 11399 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11400 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11401 for (int i=0; i <= lastAddrIndx; ++i) 11402 (*MIB).addOperand(*argOpers[i]); 11403 11404 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11405 assert((argOpers[valArgIndx]->isReg() || 11406 argOpers[valArgIndx]->isImm()) && 11407 "invalid operand"); 11408 if (argOpers[valArgIndx]->isReg()) 11409 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11410 else 11411 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11412 MIB.addReg(t1); 11413 (*MIB).addOperand(*argOpers[valArgIndx]); 11414 11415 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11416 if (Invert) { 11417 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2); 11418 } 11419 else 11420 t3 = t2; 11421 11422 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11423 MIB.addReg(t1); 11424 11425 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11426 for (int i=0; i <= lastAddrIndx; ++i) 11427 (*MIB).addOperand(*argOpers[i]); 11428 MIB.addReg(t3); 11429 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11430 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11431 bInstr->memoperands_end()); 11432 11433 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11434 MIB.addReg(EAXreg); 11435 11436 // insert branch 11437 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11438 11439 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11440 return nextMBB; 11441} 11442 11443// private utility function: 64 bit atomics on 32 bit host. 11444MachineBasicBlock * 11445X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11446 MachineBasicBlock *MBB, 11447 unsigned regOpcL, 11448 unsigned regOpcH, 11449 unsigned immOpcL, 11450 unsigned immOpcH, 11451 bool Invert) const { 11452 // For the atomic bitwise operator, we generate 11453 // thisMBB (instructions are in pairs, except cmpxchg8b) 11454 // ld t1,t2 = [bitinstr.addr] 11455 // newMBB: 11456 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11457 // op t5, t6 <- out1, out2, [bitinstr.val] 11458 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11459 // neg t7, t8 < t5, t6 (if Invert) 11460 // mov ECX, EBX <- t5, t6 11461 // mov EAX, EDX <- t1, t2 11462 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11463 // mov t3, t4 <- EAX, EDX 11464 // bz newMBB 11465 // result in out1, out2 11466 // fallthrough -->nextMBB 11467 11468 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11469 const unsigned LoadOpc = X86::MOV32rm; 11470 const unsigned NotOpc = X86::NOT32r; 11471 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11472 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11473 MachineFunction::iterator MBBIter = MBB; 11474 ++MBBIter; 11475 11476 /// First build the CFG 11477 MachineFunction *F = MBB->getParent(); 11478 MachineBasicBlock *thisMBB = MBB; 11479 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11480 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11481 F->insert(MBBIter, newMBB); 11482 F->insert(MBBIter, nextMBB); 11483 11484 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11485 nextMBB->splice(nextMBB->begin(), thisMBB, 11486 llvm::next(MachineBasicBlock::iterator(bInstr)), 11487 thisMBB->end()); 11488 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11489 11490 // Update thisMBB to fall through to newMBB 11491 thisMBB->addSuccessor(newMBB); 11492 11493 // newMBB jumps to itself and fall through to nextMBB 11494 newMBB->addSuccessor(nextMBB); 11495 newMBB->addSuccessor(newMBB); 11496 11497 DebugLoc dl = bInstr->getDebugLoc(); 11498 // Insert instructions into newMBB based on incoming instruction 11499 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11500 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11501 "unexpected number of operands"); 11502 MachineOperand& dest1Oper = bInstr->getOperand(0); 11503 MachineOperand& dest2Oper = bInstr->getOperand(1); 11504 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11505 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11506 argOpers[i] = &bInstr->getOperand(i+2); 11507 11508 // We use some of the operands multiple times, so conservatively just 11509 // clear any kill flags that might be present. 11510 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11511 argOpers[i]->setIsKill(false); 11512 } 11513 11514 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11515 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11516 11517 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11518 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11519 for (int i=0; i <= lastAddrIndx; ++i) 11520 (*MIB).addOperand(*argOpers[i]); 11521 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11522 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11523 // add 4 to displacement. 11524 for (int i=0; i <= lastAddrIndx-2; ++i) 11525 (*MIB).addOperand(*argOpers[i]); 11526 MachineOperand newOp3 = *(argOpers[3]); 11527 if (newOp3.isImm()) 11528 newOp3.setImm(newOp3.getImm()+4); 11529 else 11530 newOp3.setOffset(newOp3.getOffset()+4); 11531 (*MIB).addOperand(newOp3); 11532 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11533 11534 // t3/4 are defined later, at the bottom of the loop 11535 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11536 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11537 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11538 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11539 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11540 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11541 11542 // The subsequent operations should be using the destination registers of 11543 // the PHI instructions. 11544 t1 = dest1Oper.getReg(); 11545 t2 = dest2Oper.getReg(); 11546 11547 int valArgIndx = lastAddrIndx + 1; 11548 assert((argOpers[valArgIndx]->isReg() || 11549 argOpers[valArgIndx]->isImm()) && 11550 "invalid operand"); 11551 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11552 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11553 if (argOpers[valArgIndx]->isReg()) 11554 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11555 else 11556 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11557 if (regOpcL != X86::MOV32rr) 11558 MIB.addReg(t1); 11559 (*MIB).addOperand(*argOpers[valArgIndx]); 11560 assert(argOpers[valArgIndx + 1]->isReg() == 11561 argOpers[valArgIndx]->isReg()); 11562 assert(argOpers[valArgIndx + 1]->isImm() == 11563 argOpers[valArgIndx]->isImm()); 11564 if (argOpers[valArgIndx + 1]->isReg()) 11565 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11566 else 11567 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11568 if (regOpcH != X86::MOV32rr) 11569 MIB.addReg(t2); 11570 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11571 11572 unsigned t7, t8; 11573 if (Invert) { 11574 t7 = F->getRegInfo().createVirtualRegister(RC); 11575 t8 = F->getRegInfo().createVirtualRegister(RC); 11576 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5); 11577 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6); 11578 } else { 11579 t7 = t5; 11580 t8 = t6; 11581 } 11582 11583 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11584 MIB.addReg(t1); 11585 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11586 MIB.addReg(t2); 11587 11588 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11589 MIB.addReg(t7); 11590 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11591 MIB.addReg(t8); 11592 11593 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11594 for (int i=0; i <= lastAddrIndx; ++i) 11595 (*MIB).addOperand(*argOpers[i]); 11596 11597 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11598 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11599 bInstr->memoperands_end()); 11600 11601 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11602 MIB.addReg(X86::EAX); 11603 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11604 MIB.addReg(X86::EDX); 11605 11606 // insert branch 11607 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11608 11609 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11610 return nextMBB; 11611} 11612 11613// private utility function 11614MachineBasicBlock * 11615X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11616 MachineBasicBlock *MBB, 11617 unsigned cmovOpc) const { 11618 // For the atomic min/max operator, we generate 11619 // thisMBB: 11620 // newMBB: 11621 // ld t1 = [min/max.addr] 11622 // mov t2 = [min/max.val] 11623 // cmp t1, t2 11624 // cmov[cond] t2 = t1 11625 // mov EAX = t1 11626 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11627 // bz newMBB 11628 // fallthrough -->nextMBB 11629 // 11630 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11631 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11632 MachineFunction::iterator MBBIter = MBB; 11633 ++MBBIter; 11634 11635 /// First build the CFG 11636 MachineFunction *F = MBB->getParent(); 11637 MachineBasicBlock *thisMBB = MBB; 11638 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11639 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11640 F->insert(MBBIter, newMBB); 11641 F->insert(MBBIter, nextMBB); 11642 11643 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11644 nextMBB->splice(nextMBB->begin(), thisMBB, 11645 llvm::next(MachineBasicBlock::iterator(mInstr)), 11646 thisMBB->end()); 11647 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11648 11649 // Update thisMBB to fall through to newMBB 11650 thisMBB->addSuccessor(newMBB); 11651 11652 // newMBB jumps to newMBB and fall through to nextMBB 11653 newMBB->addSuccessor(nextMBB); 11654 newMBB->addSuccessor(newMBB); 11655 11656 DebugLoc dl = mInstr->getDebugLoc(); 11657 // Insert instructions into newMBB based on incoming instruction 11658 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11659 "unexpected number of operands"); 11660 MachineOperand& destOper = mInstr->getOperand(0); 11661 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11662 int numArgs = mInstr->getNumOperands() - 1; 11663 for (int i=0; i < numArgs; ++i) 11664 argOpers[i] = &mInstr->getOperand(i+1); 11665 11666 // x86 address has 4 operands: base, index, scale, and displacement 11667 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11668 int valArgIndx = lastAddrIndx + 1; 11669 11670 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11671 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11672 for (int i=0; i <= lastAddrIndx; ++i) 11673 (*MIB).addOperand(*argOpers[i]); 11674 11675 // We only support register and immediate values 11676 assert((argOpers[valArgIndx]->isReg() || 11677 argOpers[valArgIndx]->isImm()) && 11678 "invalid operand"); 11679 11680 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11681 if (argOpers[valArgIndx]->isReg()) 11682 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11683 else 11684 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11685 (*MIB).addOperand(*argOpers[valArgIndx]); 11686 11687 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11688 MIB.addReg(t1); 11689 11690 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11691 MIB.addReg(t1); 11692 MIB.addReg(t2); 11693 11694 // Generate movc 11695 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11696 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11697 MIB.addReg(t2); 11698 MIB.addReg(t1); 11699 11700 // Cmp and exchange if none has modified the memory location 11701 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11702 for (int i=0; i <= lastAddrIndx; ++i) 11703 (*MIB).addOperand(*argOpers[i]); 11704 MIB.addReg(t3); 11705 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11706 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11707 mInstr->memoperands_end()); 11708 11709 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11710 MIB.addReg(X86::EAX); 11711 11712 // insert branch 11713 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11714 11715 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11716 return nextMBB; 11717} 11718 11719// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11720// or XMM0_V32I8 in AVX all of this code can be replaced with that 11721// in the .td file. 11722MachineBasicBlock * 11723X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11724 unsigned numArgs, bool memArg) const { 11725 assert(Subtarget->hasSSE42() && 11726 "Target must have SSE4.2 or AVX features enabled"); 11727 11728 DebugLoc dl = MI->getDebugLoc(); 11729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11730 unsigned Opc; 11731 if (!Subtarget->hasAVX()) { 11732 if (memArg) 11733 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11734 else 11735 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11736 } else { 11737 if (memArg) 11738 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11739 else 11740 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11741 } 11742 11743 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11744 for (unsigned i = 0; i < numArgs; ++i) { 11745 MachineOperand &Op = MI->getOperand(i+1); 11746 if (!(Op.isReg() && Op.isImplicit())) 11747 MIB.addOperand(Op); 11748 } 11749 BuildMI(*BB, MI, dl, 11750 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11751 MI->getOperand(0).getReg()) 11752 .addReg(X86::XMM0); 11753 11754 MI->eraseFromParent(); 11755 return BB; 11756} 11757 11758MachineBasicBlock * 11759X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11760 DebugLoc dl = MI->getDebugLoc(); 11761 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11762 11763 // Address into RAX/EAX, other two args into ECX, EDX. 11764 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11765 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11766 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11767 for (int i = 0; i < X86::AddrNumOperands; ++i) 11768 MIB.addOperand(MI->getOperand(i)); 11769 11770 unsigned ValOps = X86::AddrNumOperands; 11771 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11772 .addReg(MI->getOperand(ValOps).getReg()); 11773 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11774 .addReg(MI->getOperand(ValOps+1).getReg()); 11775 11776 // The instruction doesn't actually take any operands though. 11777 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11778 11779 MI->eraseFromParent(); // The pseudo is gone now. 11780 return BB; 11781} 11782 11783MachineBasicBlock * 11784X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11785 DebugLoc dl = MI->getDebugLoc(); 11786 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11787 11788 // First arg in ECX, the second in EAX. 11789 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11790 .addReg(MI->getOperand(0).getReg()); 11791 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11792 .addReg(MI->getOperand(1).getReg()); 11793 11794 // The instruction doesn't actually take any operands though. 11795 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11796 11797 MI->eraseFromParent(); // The pseudo is gone now. 11798 return BB; 11799} 11800 11801MachineBasicBlock * 11802X86TargetLowering::EmitVAARG64WithCustomInserter( 11803 MachineInstr *MI, 11804 MachineBasicBlock *MBB) const { 11805 // Emit va_arg instruction on X86-64. 11806 11807 // Operands to this pseudo-instruction: 11808 // 0 ) Output : destination address (reg) 11809 // 1-5) Input : va_list address (addr, i64mem) 11810 // 6 ) ArgSize : Size (in bytes) of vararg type 11811 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11812 // 8 ) Align : Alignment of type 11813 // 9 ) EFLAGS (implicit-def) 11814 11815 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11816 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11817 11818 unsigned DestReg = MI->getOperand(0).getReg(); 11819 MachineOperand &Base = MI->getOperand(1); 11820 MachineOperand &Scale = MI->getOperand(2); 11821 MachineOperand &Index = MI->getOperand(3); 11822 MachineOperand &Disp = MI->getOperand(4); 11823 MachineOperand &Segment = MI->getOperand(5); 11824 unsigned ArgSize = MI->getOperand(6).getImm(); 11825 unsigned ArgMode = MI->getOperand(7).getImm(); 11826 unsigned Align = MI->getOperand(8).getImm(); 11827 11828 // Memory Reference 11829 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11830 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11831 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11832 11833 // Machine Information 11834 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11835 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11836 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11837 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11838 DebugLoc DL = MI->getDebugLoc(); 11839 11840 // struct va_list { 11841 // i32 gp_offset 11842 // i32 fp_offset 11843 // i64 overflow_area (address) 11844 // i64 reg_save_area (address) 11845 // } 11846 // sizeof(va_list) = 24 11847 // alignment(va_list) = 8 11848 11849 unsigned TotalNumIntRegs = 6; 11850 unsigned TotalNumXMMRegs = 8; 11851 bool UseGPOffset = (ArgMode == 1); 11852 bool UseFPOffset = (ArgMode == 2); 11853 unsigned MaxOffset = TotalNumIntRegs * 8 + 11854 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11855 11856 /* Align ArgSize to a multiple of 8 */ 11857 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11858 bool NeedsAlign = (Align > 8); 11859 11860 MachineBasicBlock *thisMBB = MBB; 11861 MachineBasicBlock *overflowMBB; 11862 MachineBasicBlock *offsetMBB; 11863 MachineBasicBlock *endMBB; 11864 11865 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11866 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11867 unsigned OffsetReg = 0; 11868 11869 if (!UseGPOffset && !UseFPOffset) { 11870 // If we only pull from the overflow region, we don't create a branch. 11871 // We don't need to alter control flow. 11872 OffsetDestReg = 0; // unused 11873 OverflowDestReg = DestReg; 11874 11875 offsetMBB = NULL; 11876 overflowMBB = thisMBB; 11877 endMBB = thisMBB; 11878 } else { 11879 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11880 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11881 // If not, pull from overflow_area. (branch to overflowMBB) 11882 // 11883 // thisMBB 11884 // | . 11885 // | . 11886 // offsetMBB overflowMBB 11887 // | . 11888 // | . 11889 // endMBB 11890 11891 // Registers for the PHI in endMBB 11892 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11893 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11894 11895 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11896 MachineFunction *MF = MBB->getParent(); 11897 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11898 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11899 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11900 11901 MachineFunction::iterator MBBIter = MBB; 11902 ++MBBIter; 11903 11904 // Insert the new basic blocks 11905 MF->insert(MBBIter, offsetMBB); 11906 MF->insert(MBBIter, overflowMBB); 11907 MF->insert(MBBIter, endMBB); 11908 11909 // Transfer the remainder of MBB and its successor edges to endMBB. 11910 endMBB->splice(endMBB->begin(), thisMBB, 11911 llvm::next(MachineBasicBlock::iterator(MI)), 11912 thisMBB->end()); 11913 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11914 11915 // Make offsetMBB and overflowMBB successors of thisMBB 11916 thisMBB->addSuccessor(offsetMBB); 11917 thisMBB->addSuccessor(overflowMBB); 11918 11919 // endMBB is a successor of both offsetMBB and overflowMBB 11920 offsetMBB->addSuccessor(endMBB); 11921 overflowMBB->addSuccessor(endMBB); 11922 11923 // Load the offset value into a register 11924 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11925 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11926 .addOperand(Base) 11927 .addOperand(Scale) 11928 .addOperand(Index) 11929 .addDisp(Disp, UseFPOffset ? 4 : 0) 11930 .addOperand(Segment) 11931 .setMemRefs(MMOBegin, MMOEnd); 11932 11933 // Check if there is enough room left to pull this argument. 11934 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11935 .addReg(OffsetReg) 11936 .addImm(MaxOffset + 8 - ArgSizeA8); 11937 11938 // Branch to "overflowMBB" if offset >= max 11939 // Fall through to "offsetMBB" otherwise 11940 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11941 .addMBB(overflowMBB); 11942 } 11943 11944 // In offsetMBB, emit code to use the reg_save_area. 11945 if (offsetMBB) { 11946 assert(OffsetReg != 0); 11947 11948 // Read the reg_save_area address. 11949 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11950 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11951 .addOperand(Base) 11952 .addOperand(Scale) 11953 .addOperand(Index) 11954 .addDisp(Disp, 16) 11955 .addOperand(Segment) 11956 .setMemRefs(MMOBegin, MMOEnd); 11957 11958 // Zero-extend the offset 11959 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11960 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11961 .addImm(0) 11962 .addReg(OffsetReg) 11963 .addImm(X86::sub_32bit); 11964 11965 // Add the offset to the reg_save_area to get the final address. 11966 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11967 .addReg(OffsetReg64) 11968 .addReg(RegSaveReg); 11969 11970 // Compute the offset for the next argument 11971 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11972 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11973 .addReg(OffsetReg) 11974 .addImm(UseFPOffset ? 16 : 8); 11975 11976 // Store it back into the va_list. 11977 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11978 .addOperand(Base) 11979 .addOperand(Scale) 11980 .addOperand(Index) 11981 .addDisp(Disp, UseFPOffset ? 4 : 0) 11982 .addOperand(Segment) 11983 .addReg(NextOffsetReg) 11984 .setMemRefs(MMOBegin, MMOEnd); 11985 11986 // Jump to endMBB 11987 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11988 .addMBB(endMBB); 11989 } 11990 11991 // 11992 // Emit code to use overflow area 11993 // 11994 11995 // Load the overflow_area address into a register. 11996 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11997 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11998 .addOperand(Base) 11999 .addOperand(Scale) 12000 .addOperand(Index) 12001 .addDisp(Disp, 8) 12002 .addOperand(Segment) 12003 .setMemRefs(MMOBegin, MMOEnd); 12004 12005 // If we need to align it, do so. Otherwise, just copy the address 12006 // to OverflowDestReg. 12007 if (NeedsAlign) { 12008 // Align the overflow address 12009 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12010 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12011 12012 // aligned_addr = (addr + (align-1)) & ~(align-1) 12013 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12014 .addReg(OverflowAddrReg) 12015 .addImm(Align-1); 12016 12017 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12018 .addReg(TmpReg) 12019 .addImm(~(uint64_t)(Align-1)); 12020 } else { 12021 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12022 .addReg(OverflowAddrReg); 12023 } 12024 12025 // Compute the next overflow address after this argument. 12026 // (the overflow address should be kept 8-byte aligned) 12027 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12028 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12029 .addReg(OverflowDestReg) 12030 .addImm(ArgSizeA8); 12031 12032 // Store the new overflow address. 12033 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12034 .addOperand(Base) 12035 .addOperand(Scale) 12036 .addOperand(Index) 12037 .addDisp(Disp, 8) 12038 .addOperand(Segment) 12039 .addReg(NextAddrReg) 12040 .setMemRefs(MMOBegin, MMOEnd); 12041 12042 // If we branched, emit the PHI to the front of endMBB. 12043 if (offsetMBB) { 12044 BuildMI(*endMBB, endMBB->begin(), DL, 12045 TII->get(X86::PHI), DestReg) 12046 .addReg(OffsetDestReg).addMBB(offsetMBB) 12047 .addReg(OverflowDestReg).addMBB(overflowMBB); 12048 } 12049 12050 // Erase the pseudo instruction 12051 MI->eraseFromParent(); 12052 12053 return endMBB; 12054} 12055 12056MachineBasicBlock * 12057X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12058 MachineInstr *MI, 12059 MachineBasicBlock *MBB) const { 12060 // Emit code to save XMM registers to the stack. The ABI says that the 12061 // number of registers to save is given in %al, so it's theoretically 12062 // possible to do an indirect jump trick to avoid saving all of them, 12063 // however this code takes a simpler approach and just executes all 12064 // of the stores if %al is non-zero. It's less code, and it's probably 12065 // easier on the hardware branch predictor, and stores aren't all that 12066 // expensive anyway. 12067 12068 // Create the new basic blocks. One block contains all the XMM stores, 12069 // and one block is the final destination regardless of whether any 12070 // stores were performed. 12071 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12072 MachineFunction *F = MBB->getParent(); 12073 MachineFunction::iterator MBBIter = MBB; 12074 ++MBBIter; 12075 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12076 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12077 F->insert(MBBIter, XMMSaveMBB); 12078 F->insert(MBBIter, EndMBB); 12079 12080 // Transfer the remainder of MBB and its successor edges to EndMBB. 12081 EndMBB->splice(EndMBB->begin(), MBB, 12082 llvm::next(MachineBasicBlock::iterator(MI)), 12083 MBB->end()); 12084 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12085 12086 // The original block will now fall through to the XMM save block. 12087 MBB->addSuccessor(XMMSaveMBB); 12088 // The XMMSaveMBB will fall through to the end block. 12089 XMMSaveMBB->addSuccessor(EndMBB); 12090 12091 // Now add the instructions. 12092 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12093 DebugLoc DL = MI->getDebugLoc(); 12094 12095 unsigned CountReg = MI->getOperand(0).getReg(); 12096 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12097 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12098 12099 if (!Subtarget->isTargetWin64()) { 12100 // If %al is 0, branch around the XMM save block. 12101 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12102 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12103 MBB->addSuccessor(EndMBB); 12104 } 12105 12106 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12107 // In the XMM save block, save all the XMM argument registers. 12108 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12109 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12110 MachineMemOperand *MMO = 12111 F->getMachineMemOperand( 12112 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12113 MachineMemOperand::MOStore, 12114 /*Size=*/16, /*Align=*/16); 12115 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12116 .addFrameIndex(RegSaveFrameIndex) 12117 .addImm(/*Scale=*/1) 12118 .addReg(/*IndexReg=*/0) 12119 .addImm(/*Disp=*/Offset) 12120 .addReg(/*Segment=*/0) 12121 .addReg(MI->getOperand(i).getReg()) 12122 .addMemOperand(MMO); 12123 } 12124 12125 MI->eraseFromParent(); // The pseudo instruction is gone now. 12126 12127 return EndMBB; 12128} 12129 12130// The EFLAGS operand of SelectItr might be missing a kill marker 12131// because there were multiple uses of EFLAGS, and ISel didn't know 12132// which to mark. Figure out whether SelectItr should have had a 12133// kill marker, and set it if it should. Returns the correct kill 12134// marker value. 12135static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12136 MachineBasicBlock* BB, 12137 const TargetRegisterInfo* TRI) { 12138 // Scan forward through BB for a use/def of EFLAGS. 12139 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12140 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12141 const MachineInstr& mi = *miI; 12142 if (mi.readsRegister(X86::EFLAGS)) 12143 return false; 12144 if (mi.definesRegister(X86::EFLAGS)) 12145 break; // Should have kill-flag - update below. 12146 } 12147 12148 // If we hit the end of the block, check whether EFLAGS is live into a 12149 // successor. 12150 if (miI == BB->end()) { 12151 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12152 sEnd = BB->succ_end(); 12153 sItr != sEnd; ++sItr) { 12154 MachineBasicBlock* succ = *sItr; 12155 if (succ->isLiveIn(X86::EFLAGS)) 12156 return false; 12157 } 12158 } 12159 12160 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12161 // out. SelectMI should have a kill flag on EFLAGS. 12162 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12163 return true; 12164} 12165 12166MachineBasicBlock * 12167X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12168 MachineBasicBlock *BB) const { 12169 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12170 DebugLoc DL = MI->getDebugLoc(); 12171 12172 // To "insert" a SELECT_CC instruction, we actually have to insert the 12173 // diamond control-flow pattern. The incoming instruction knows the 12174 // destination vreg to set, the condition code register to branch on, the 12175 // true/false values to select between, and a branch opcode to use. 12176 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12177 MachineFunction::iterator It = BB; 12178 ++It; 12179 12180 // thisMBB: 12181 // ... 12182 // TrueVal = ... 12183 // cmpTY ccX, r1, r2 12184 // bCC copy1MBB 12185 // fallthrough --> copy0MBB 12186 MachineBasicBlock *thisMBB = BB; 12187 MachineFunction *F = BB->getParent(); 12188 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12189 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12190 F->insert(It, copy0MBB); 12191 F->insert(It, sinkMBB); 12192 12193 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12194 // live into the sink and copy blocks. 12195 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12196 if (!MI->killsRegister(X86::EFLAGS) && 12197 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12198 copy0MBB->addLiveIn(X86::EFLAGS); 12199 sinkMBB->addLiveIn(X86::EFLAGS); 12200 } 12201 12202 // Transfer the remainder of BB and its successor edges to sinkMBB. 12203 sinkMBB->splice(sinkMBB->begin(), BB, 12204 llvm::next(MachineBasicBlock::iterator(MI)), 12205 BB->end()); 12206 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12207 12208 // Add the true and fallthrough blocks as its successors. 12209 BB->addSuccessor(copy0MBB); 12210 BB->addSuccessor(sinkMBB); 12211 12212 // Create the conditional branch instruction. 12213 unsigned Opc = 12214 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12215 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12216 12217 // copy0MBB: 12218 // %FalseValue = ... 12219 // # fallthrough to sinkMBB 12220 copy0MBB->addSuccessor(sinkMBB); 12221 12222 // sinkMBB: 12223 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12224 // ... 12225 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12226 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12227 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12228 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12229 12230 MI->eraseFromParent(); // The pseudo instruction is gone now. 12231 return sinkMBB; 12232} 12233 12234MachineBasicBlock * 12235X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12236 bool Is64Bit) const { 12237 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12238 DebugLoc DL = MI->getDebugLoc(); 12239 MachineFunction *MF = BB->getParent(); 12240 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12241 12242 assert(getTargetMachine().Options.EnableSegmentedStacks); 12243 12244 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12245 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12246 12247 // BB: 12248 // ... [Till the alloca] 12249 // If stacklet is not large enough, jump to mallocMBB 12250 // 12251 // bumpMBB: 12252 // Allocate by subtracting from RSP 12253 // Jump to continueMBB 12254 // 12255 // mallocMBB: 12256 // Allocate by call to runtime 12257 // 12258 // continueMBB: 12259 // ... 12260 // [rest of original BB] 12261 // 12262 12263 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12264 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12265 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12266 12267 MachineRegisterInfo &MRI = MF->getRegInfo(); 12268 const TargetRegisterClass *AddrRegClass = 12269 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12270 12271 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12272 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12273 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12274 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12275 sizeVReg = MI->getOperand(1).getReg(), 12276 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12277 12278 MachineFunction::iterator MBBIter = BB; 12279 ++MBBIter; 12280 12281 MF->insert(MBBIter, bumpMBB); 12282 MF->insert(MBBIter, mallocMBB); 12283 MF->insert(MBBIter, continueMBB); 12284 12285 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12286 (MachineBasicBlock::iterator(MI)), BB->end()); 12287 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12288 12289 // Add code to the main basic block to check if the stack limit has been hit, 12290 // and if so, jump to mallocMBB otherwise to bumpMBB. 12291 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12292 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12293 .addReg(tmpSPVReg).addReg(sizeVReg); 12294 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12295 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12296 .addReg(SPLimitVReg); 12297 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12298 12299 // bumpMBB simply decreases the stack pointer, since we know the current 12300 // stacklet has enough space. 12301 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12302 .addReg(SPLimitVReg); 12303 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12304 .addReg(SPLimitVReg); 12305 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12306 12307 // Calls into a routine in libgcc to allocate more space from the heap. 12308 const uint32_t *RegMask = 12309 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12310 if (Is64Bit) { 12311 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12312 .addReg(sizeVReg); 12313 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12314 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12315 .addRegMask(RegMask) 12316 .addReg(X86::RAX, RegState::ImplicitDefine); 12317 } else { 12318 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12319 .addImm(12); 12320 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12321 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12322 .addExternalSymbol("__morestack_allocate_stack_space") 12323 .addRegMask(RegMask) 12324 .addReg(X86::EAX, RegState::ImplicitDefine); 12325 } 12326 12327 if (!Is64Bit) 12328 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12329 .addImm(16); 12330 12331 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12332 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12333 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12334 12335 // Set up the CFG correctly. 12336 BB->addSuccessor(bumpMBB); 12337 BB->addSuccessor(mallocMBB); 12338 mallocMBB->addSuccessor(continueMBB); 12339 bumpMBB->addSuccessor(continueMBB); 12340 12341 // Take care of the PHI nodes. 12342 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12343 MI->getOperand(0).getReg()) 12344 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12345 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12346 12347 // Delete the original pseudo instruction. 12348 MI->eraseFromParent(); 12349 12350 // And we're done. 12351 return continueMBB; 12352} 12353 12354MachineBasicBlock * 12355X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12356 MachineBasicBlock *BB) const { 12357 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12358 DebugLoc DL = MI->getDebugLoc(); 12359 12360 assert(!Subtarget->isTargetEnvMacho()); 12361 12362 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12363 // non-trivial part is impdef of ESP. 12364 12365 if (Subtarget->isTargetWin64()) { 12366 if (Subtarget->isTargetCygMing()) { 12367 // ___chkstk(Mingw64): 12368 // Clobbers R10, R11, RAX and EFLAGS. 12369 // Updates RSP. 12370 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12371 .addExternalSymbol("___chkstk") 12372 .addReg(X86::RAX, RegState::Implicit) 12373 .addReg(X86::RSP, RegState::Implicit) 12374 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12375 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12376 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12377 } else { 12378 // __chkstk(MSVCRT): does not update stack pointer. 12379 // Clobbers R10, R11 and EFLAGS. 12380 // FIXME: RAX(allocated size) might be reused and not killed. 12381 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12382 .addExternalSymbol("__chkstk") 12383 .addReg(X86::RAX, RegState::Implicit) 12384 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12385 // RAX has the offset to subtracted from RSP. 12386 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12387 .addReg(X86::RSP) 12388 .addReg(X86::RAX); 12389 } 12390 } else { 12391 const char *StackProbeSymbol = 12392 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12393 12394 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12395 .addExternalSymbol(StackProbeSymbol) 12396 .addReg(X86::EAX, RegState::Implicit) 12397 .addReg(X86::ESP, RegState::Implicit) 12398 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12399 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12400 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12401 } 12402 12403 MI->eraseFromParent(); // The pseudo instruction is gone now. 12404 return BB; 12405} 12406 12407MachineBasicBlock * 12408X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12409 MachineBasicBlock *BB) const { 12410 // This is pretty easy. We're taking the value that we received from 12411 // our load from the relocation, sticking it in either RDI (x86-64) 12412 // or EAX and doing an indirect call. The return value will then 12413 // be in the normal return register. 12414 const X86InstrInfo *TII 12415 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12416 DebugLoc DL = MI->getDebugLoc(); 12417 MachineFunction *F = BB->getParent(); 12418 12419 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12420 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12421 12422 // Get a register mask for the lowered call. 12423 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12424 // proper register mask. 12425 const uint32_t *RegMask = 12426 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12427 if (Subtarget->is64Bit()) { 12428 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12429 TII->get(X86::MOV64rm), X86::RDI) 12430 .addReg(X86::RIP) 12431 .addImm(0).addReg(0) 12432 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12433 MI->getOperand(3).getTargetFlags()) 12434 .addReg(0); 12435 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12436 addDirectMem(MIB, X86::RDI); 12437 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12438 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12439 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12440 TII->get(X86::MOV32rm), X86::EAX) 12441 .addReg(0) 12442 .addImm(0).addReg(0) 12443 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12444 MI->getOperand(3).getTargetFlags()) 12445 .addReg(0); 12446 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12447 addDirectMem(MIB, X86::EAX); 12448 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12449 } else { 12450 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12451 TII->get(X86::MOV32rm), X86::EAX) 12452 .addReg(TII->getGlobalBaseReg(F)) 12453 .addImm(0).addReg(0) 12454 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12455 MI->getOperand(3).getTargetFlags()) 12456 .addReg(0); 12457 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12458 addDirectMem(MIB, X86::EAX); 12459 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12460 } 12461 12462 MI->eraseFromParent(); // The pseudo instruction is gone now. 12463 return BB; 12464} 12465 12466MachineBasicBlock * 12467X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12468 MachineBasicBlock *BB) const { 12469 switch (MI->getOpcode()) { 12470 default: llvm_unreachable("Unexpected instr type to insert"); 12471 case X86::TAILJMPd64: 12472 case X86::TAILJMPr64: 12473 case X86::TAILJMPm64: 12474 llvm_unreachable("TAILJMP64 would not be touched here."); 12475 case X86::TCRETURNdi64: 12476 case X86::TCRETURNri64: 12477 case X86::TCRETURNmi64: 12478 return BB; 12479 case X86::WIN_ALLOCA: 12480 return EmitLoweredWinAlloca(MI, BB); 12481 case X86::SEG_ALLOCA_32: 12482 return EmitLoweredSegAlloca(MI, BB, false); 12483 case X86::SEG_ALLOCA_64: 12484 return EmitLoweredSegAlloca(MI, BB, true); 12485 case X86::TLSCall_32: 12486 case X86::TLSCall_64: 12487 return EmitLoweredTLSCall(MI, BB); 12488 case X86::CMOV_GR8: 12489 case X86::CMOV_FR32: 12490 case X86::CMOV_FR64: 12491 case X86::CMOV_V4F32: 12492 case X86::CMOV_V2F64: 12493 case X86::CMOV_V2I64: 12494 case X86::CMOV_V8F32: 12495 case X86::CMOV_V4F64: 12496 case X86::CMOV_V4I64: 12497 case X86::CMOV_GR16: 12498 case X86::CMOV_GR32: 12499 case X86::CMOV_RFP32: 12500 case X86::CMOV_RFP64: 12501 case X86::CMOV_RFP80: 12502 return EmitLoweredSelect(MI, BB); 12503 12504 case X86::FP32_TO_INT16_IN_MEM: 12505 case X86::FP32_TO_INT32_IN_MEM: 12506 case X86::FP32_TO_INT64_IN_MEM: 12507 case X86::FP64_TO_INT16_IN_MEM: 12508 case X86::FP64_TO_INT32_IN_MEM: 12509 case X86::FP64_TO_INT64_IN_MEM: 12510 case X86::FP80_TO_INT16_IN_MEM: 12511 case X86::FP80_TO_INT32_IN_MEM: 12512 case X86::FP80_TO_INT64_IN_MEM: { 12513 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12514 DebugLoc DL = MI->getDebugLoc(); 12515 12516 // Change the floating point control register to use "round towards zero" 12517 // mode when truncating to an integer value. 12518 MachineFunction *F = BB->getParent(); 12519 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12520 addFrameReference(BuildMI(*BB, MI, DL, 12521 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12522 12523 // Load the old value of the high byte of the control word... 12524 unsigned OldCW = 12525 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12526 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12527 CWFrameIdx); 12528 12529 // Set the high part to be round to zero... 12530 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12531 .addImm(0xC7F); 12532 12533 // Reload the modified control word now... 12534 addFrameReference(BuildMI(*BB, MI, DL, 12535 TII->get(X86::FLDCW16m)), CWFrameIdx); 12536 12537 // Restore the memory image of control word to original value 12538 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12539 .addReg(OldCW); 12540 12541 // Get the X86 opcode to use. 12542 unsigned Opc; 12543 switch (MI->getOpcode()) { 12544 default: llvm_unreachable("illegal opcode!"); 12545 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12546 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12547 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12548 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12549 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12550 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12551 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12552 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12553 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12554 } 12555 12556 X86AddressMode AM; 12557 MachineOperand &Op = MI->getOperand(0); 12558 if (Op.isReg()) { 12559 AM.BaseType = X86AddressMode::RegBase; 12560 AM.Base.Reg = Op.getReg(); 12561 } else { 12562 AM.BaseType = X86AddressMode::FrameIndexBase; 12563 AM.Base.FrameIndex = Op.getIndex(); 12564 } 12565 Op = MI->getOperand(1); 12566 if (Op.isImm()) 12567 AM.Scale = Op.getImm(); 12568 Op = MI->getOperand(2); 12569 if (Op.isImm()) 12570 AM.IndexReg = Op.getImm(); 12571 Op = MI->getOperand(3); 12572 if (Op.isGlobal()) { 12573 AM.GV = Op.getGlobal(); 12574 } else { 12575 AM.Disp = Op.getImm(); 12576 } 12577 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12578 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12579 12580 // Reload the original control word now. 12581 addFrameReference(BuildMI(*BB, MI, DL, 12582 TII->get(X86::FLDCW16m)), CWFrameIdx); 12583 12584 MI->eraseFromParent(); // The pseudo instruction is gone now. 12585 return BB; 12586 } 12587 // String/text processing lowering. 12588 case X86::PCMPISTRM128REG: 12589 case X86::VPCMPISTRM128REG: 12590 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12591 case X86::PCMPISTRM128MEM: 12592 case X86::VPCMPISTRM128MEM: 12593 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12594 case X86::PCMPESTRM128REG: 12595 case X86::VPCMPESTRM128REG: 12596 return EmitPCMP(MI, BB, 5, false /* in mem */); 12597 case X86::PCMPESTRM128MEM: 12598 case X86::VPCMPESTRM128MEM: 12599 return EmitPCMP(MI, BB, 5, true /* in mem */); 12600 12601 // Thread synchronization. 12602 case X86::MONITOR: 12603 return EmitMonitor(MI, BB); 12604 case X86::MWAIT: 12605 return EmitMwait(MI, BB); 12606 12607 // Atomic Lowering. 12608 case X86::ATOMAND32: 12609 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12610 X86::AND32ri, X86::MOV32rm, 12611 X86::LCMPXCHG32, 12612 X86::NOT32r, X86::EAX, 12613 X86::GR32RegisterClass); 12614 case X86::ATOMOR32: 12615 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12616 X86::OR32ri, X86::MOV32rm, 12617 X86::LCMPXCHG32, 12618 X86::NOT32r, X86::EAX, 12619 X86::GR32RegisterClass); 12620 case X86::ATOMXOR32: 12621 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12622 X86::XOR32ri, X86::MOV32rm, 12623 X86::LCMPXCHG32, 12624 X86::NOT32r, X86::EAX, 12625 X86::GR32RegisterClass); 12626 case X86::ATOMNAND32: 12627 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12628 X86::AND32ri, X86::MOV32rm, 12629 X86::LCMPXCHG32, 12630 X86::NOT32r, X86::EAX, 12631 X86::GR32RegisterClass, true); 12632 case X86::ATOMMIN32: 12633 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12634 case X86::ATOMMAX32: 12635 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12636 case X86::ATOMUMIN32: 12637 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12638 case X86::ATOMUMAX32: 12639 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12640 12641 case X86::ATOMAND16: 12642 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12643 X86::AND16ri, X86::MOV16rm, 12644 X86::LCMPXCHG16, 12645 X86::NOT16r, X86::AX, 12646 X86::GR16RegisterClass); 12647 case X86::ATOMOR16: 12648 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12649 X86::OR16ri, X86::MOV16rm, 12650 X86::LCMPXCHG16, 12651 X86::NOT16r, X86::AX, 12652 X86::GR16RegisterClass); 12653 case X86::ATOMXOR16: 12654 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12655 X86::XOR16ri, X86::MOV16rm, 12656 X86::LCMPXCHG16, 12657 X86::NOT16r, X86::AX, 12658 X86::GR16RegisterClass); 12659 case X86::ATOMNAND16: 12660 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12661 X86::AND16ri, X86::MOV16rm, 12662 X86::LCMPXCHG16, 12663 X86::NOT16r, X86::AX, 12664 X86::GR16RegisterClass, true); 12665 case X86::ATOMMIN16: 12666 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12667 case X86::ATOMMAX16: 12668 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12669 case X86::ATOMUMIN16: 12670 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12671 case X86::ATOMUMAX16: 12672 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12673 12674 case X86::ATOMAND8: 12675 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12676 X86::AND8ri, X86::MOV8rm, 12677 X86::LCMPXCHG8, 12678 X86::NOT8r, X86::AL, 12679 X86::GR8RegisterClass); 12680 case X86::ATOMOR8: 12681 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12682 X86::OR8ri, X86::MOV8rm, 12683 X86::LCMPXCHG8, 12684 X86::NOT8r, X86::AL, 12685 X86::GR8RegisterClass); 12686 case X86::ATOMXOR8: 12687 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12688 X86::XOR8ri, X86::MOV8rm, 12689 X86::LCMPXCHG8, 12690 X86::NOT8r, X86::AL, 12691 X86::GR8RegisterClass); 12692 case X86::ATOMNAND8: 12693 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12694 X86::AND8ri, X86::MOV8rm, 12695 X86::LCMPXCHG8, 12696 X86::NOT8r, X86::AL, 12697 X86::GR8RegisterClass, true); 12698 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12699 // This group is for 64-bit host. 12700 case X86::ATOMAND64: 12701 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12702 X86::AND64ri32, X86::MOV64rm, 12703 X86::LCMPXCHG64, 12704 X86::NOT64r, X86::RAX, 12705 X86::GR64RegisterClass); 12706 case X86::ATOMOR64: 12707 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12708 X86::OR64ri32, X86::MOV64rm, 12709 X86::LCMPXCHG64, 12710 X86::NOT64r, X86::RAX, 12711 X86::GR64RegisterClass); 12712 case X86::ATOMXOR64: 12713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12714 X86::XOR64ri32, X86::MOV64rm, 12715 X86::LCMPXCHG64, 12716 X86::NOT64r, X86::RAX, 12717 X86::GR64RegisterClass); 12718 case X86::ATOMNAND64: 12719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12720 X86::AND64ri32, X86::MOV64rm, 12721 X86::LCMPXCHG64, 12722 X86::NOT64r, X86::RAX, 12723 X86::GR64RegisterClass, true); 12724 case X86::ATOMMIN64: 12725 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12726 case X86::ATOMMAX64: 12727 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12728 case X86::ATOMUMIN64: 12729 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12730 case X86::ATOMUMAX64: 12731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12732 12733 // This group does 64-bit operations on a 32-bit host. 12734 case X86::ATOMAND6432: 12735 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12736 X86::AND32rr, X86::AND32rr, 12737 X86::AND32ri, X86::AND32ri, 12738 false); 12739 case X86::ATOMOR6432: 12740 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12741 X86::OR32rr, X86::OR32rr, 12742 X86::OR32ri, X86::OR32ri, 12743 false); 12744 case X86::ATOMXOR6432: 12745 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12746 X86::XOR32rr, X86::XOR32rr, 12747 X86::XOR32ri, X86::XOR32ri, 12748 false); 12749 case X86::ATOMNAND6432: 12750 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12751 X86::AND32rr, X86::AND32rr, 12752 X86::AND32ri, X86::AND32ri, 12753 true); 12754 case X86::ATOMADD6432: 12755 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12756 X86::ADD32rr, X86::ADC32rr, 12757 X86::ADD32ri, X86::ADC32ri, 12758 false); 12759 case X86::ATOMSUB6432: 12760 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12761 X86::SUB32rr, X86::SBB32rr, 12762 X86::SUB32ri, X86::SBB32ri, 12763 false); 12764 case X86::ATOMSWAP6432: 12765 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12766 X86::MOV32rr, X86::MOV32rr, 12767 X86::MOV32ri, X86::MOV32ri, 12768 false); 12769 case X86::VASTART_SAVE_XMM_REGS: 12770 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12771 12772 case X86::VAARG_64: 12773 return EmitVAARG64WithCustomInserter(MI, BB); 12774 } 12775} 12776 12777//===----------------------------------------------------------------------===// 12778// X86 Optimization Hooks 12779//===----------------------------------------------------------------------===// 12780 12781void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12782 APInt &KnownZero, 12783 APInt &KnownOne, 12784 const SelectionDAG &DAG, 12785 unsigned Depth) const { 12786 unsigned BitWidth = KnownZero.getBitWidth(); 12787 unsigned Opc = Op.getOpcode(); 12788 assert((Opc >= ISD::BUILTIN_OP_END || 12789 Opc == ISD::INTRINSIC_WO_CHAIN || 12790 Opc == ISD::INTRINSIC_W_CHAIN || 12791 Opc == ISD::INTRINSIC_VOID) && 12792 "Should use MaskedValueIsZero if you don't know whether Op" 12793 " is a target node!"); 12794 12795 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12796 switch (Opc) { 12797 default: break; 12798 case X86ISD::ADD: 12799 case X86ISD::SUB: 12800 case X86ISD::ADC: 12801 case X86ISD::SBB: 12802 case X86ISD::SMUL: 12803 case X86ISD::UMUL: 12804 case X86ISD::INC: 12805 case X86ISD::DEC: 12806 case X86ISD::OR: 12807 case X86ISD::XOR: 12808 case X86ISD::AND: 12809 // These nodes' second result is a boolean. 12810 if (Op.getResNo() == 0) 12811 break; 12812 // Fallthrough 12813 case X86ISD::SETCC: 12814 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12815 break; 12816 case ISD::INTRINSIC_WO_CHAIN: { 12817 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12818 unsigned NumLoBits = 0; 12819 switch (IntId) { 12820 default: break; 12821 case Intrinsic::x86_sse_movmsk_ps: 12822 case Intrinsic::x86_avx_movmsk_ps_256: 12823 case Intrinsic::x86_sse2_movmsk_pd: 12824 case Intrinsic::x86_avx_movmsk_pd_256: 12825 case Intrinsic::x86_mmx_pmovmskb: 12826 case Intrinsic::x86_sse2_pmovmskb_128: 12827 case Intrinsic::x86_avx2_pmovmskb: { 12828 // High bits of movmskp{s|d}, pmovmskb are known zero. 12829 switch (IntId) { 12830 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12831 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12832 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12833 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12834 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12835 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12836 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12837 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12838 } 12839 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12840 break; 12841 } 12842 } 12843 break; 12844 } 12845 } 12846} 12847 12848unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12849 unsigned Depth) const { 12850 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12851 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12852 return Op.getValueType().getScalarType().getSizeInBits(); 12853 12854 // Fallback case. 12855 return 1; 12856} 12857 12858/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12859/// node is a GlobalAddress + offset. 12860bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12861 const GlobalValue* &GA, 12862 int64_t &Offset) const { 12863 if (N->getOpcode() == X86ISD::Wrapper) { 12864 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12865 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12866 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12867 return true; 12868 } 12869 } 12870 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12871} 12872 12873/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12874/// same as extracting the high 128-bit part of 256-bit vector and then 12875/// inserting the result into the low part of a new 256-bit vector 12876static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12877 EVT VT = SVOp->getValueType(0); 12878 int NumElems = VT.getVectorNumElements(); 12879 12880 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12881 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12882 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12883 SVOp->getMaskElt(j) >= 0) 12884 return false; 12885 12886 return true; 12887} 12888 12889/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12890/// same as extracting the low 128-bit part of 256-bit vector and then 12891/// inserting the result into the high part of a new 256-bit vector 12892static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12893 EVT VT = SVOp->getValueType(0); 12894 int NumElems = VT.getVectorNumElements(); 12895 12896 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12897 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12898 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12899 SVOp->getMaskElt(j) >= 0) 12900 return false; 12901 12902 return true; 12903} 12904 12905/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12906static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12907 TargetLowering::DAGCombinerInfo &DCI, 12908 const X86Subtarget* Subtarget) { 12909 DebugLoc dl = N->getDebugLoc(); 12910 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12911 SDValue V1 = SVOp->getOperand(0); 12912 SDValue V2 = SVOp->getOperand(1); 12913 EVT VT = SVOp->getValueType(0); 12914 int NumElems = VT.getVectorNumElements(); 12915 12916 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12917 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12918 // 12919 // 0,0,0,... 12920 // | 12921 // V UNDEF BUILD_VECTOR UNDEF 12922 // \ / \ / 12923 // CONCAT_VECTOR CONCAT_VECTOR 12924 // \ / 12925 // \ / 12926 // RESULT: V + zero extended 12927 // 12928 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12929 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12930 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12931 return SDValue(); 12932 12933 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12934 return SDValue(); 12935 12936 // To match the shuffle mask, the first half of the mask should 12937 // be exactly the first vector, and all the rest a splat with the 12938 // first element of the second one. 12939 for (int i = 0; i < NumElems/2; ++i) 12940 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12941 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12942 return SDValue(); 12943 12944 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12945 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12946 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12947 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12948 SDValue ResNode = 12949 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12950 Ld->getMemoryVT(), 12951 Ld->getPointerInfo(), 12952 Ld->getAlignment(), 12953 false/*isVolatile*/, true/*ReadMem*/, 12954 false/*WriteMem*/); 12955 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12956 } 12957 12958 // Emit a zeroed vector and insert the desired subvector on its 12959 // first half. 12960 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12961 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12962 DAG.getConstant(0, MVT::i32), DAG, dl); 12963 return DCI.CombineTo(N, InsV); 12964 } 12965 12966 //===--------------------------------------------------------------------===// 12967 // Combine some shuffles into subvector extracts and inserts: 12968 // 12969 12970 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12971 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12972 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12973 DAG, dl); 12974 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12975 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12976 return DCI.CombineTo(N, InsV); 12977 } 12978 12979 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12980 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12981 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12982 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12983 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12984 return DCI.CombineTo(N, InsV); 12985 } 12986 12987 return SDValue(); 12988} 12989 12990/// PerformShuffleCombine - Performs several different shuffle combines. 12991static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12992 TargetLowering::DAGCombinerInfo &DCI, 12993 const X86Subtarget *Subtarget) { 12994 DebugLoc dl = N->getDebugLoc(); 12995 EVT VT = N->getValueType(0); 12996 12997 // Don't create instructions with illegal types after legalize types has run. 12998 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12999 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13000 return SDValue(); 13001 13002 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13003 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 13004 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13005 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 13006 13007 // Only handle 128 wide vector from here on. 13008 if (VT.getSizeInBits() != 128) 13009 return SDValue(); 13010 13011 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13012 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13013 // consecutive, non-overlapping, and in the right order. 13014 SmallVector<SDValue, 16> Elts; 13015 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13016 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13017 13018 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13019} 13020 13021 13022/// PerformTruncateCombine - Converts truncate operation to 13023/// a sequence of vector shuffle operations. 13024/// It is possible when we truncate 256-bit vector to 128-bit vector 13025 13026SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 13027 DAGCombinerInfo &DCI) const { 13028 if (!DCI.isBeforeLegalizeOps()) 13029 return SDValue(); 13030 13031 if (!Subtarget->hasAVX()) return SDValue(); 13032 13033 EVT VT = N->getValueType(0); 13034 SDValue Op = N->getOperand(0); 13035 EVT OpVT = Op.getValueType(); 13036 DebugLoc dl = N->getDebugLoc(); 13037 13038 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 13039 13040 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13041 DAG.getIntPtrConstant(0)); 13042 13043 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13044 DAG.getIntPtrConstant(2)); 13045 13046 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13047 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13048 13049 // PSHUFD 13050 int ShufMask1[] = {0, 2, 0, 0}; 13051 13052 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), 13053 ShufMask1); 13054 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), 13055 ShufMask1); 13056 13057 // MOVLHPS 13058 int ShufMask2[] = {0, 1, 4, 5}; 13059 13060 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 13061 } 13062 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 13063 13064 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13065 DAG.getIntPtrConstant(0)); 13066 13067 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13068 DAG.getIntPtrConstant(4)); 13069 13070 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13071 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13072 13073 // PSHUFB 13074 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13075 -1, -1, -1, -1, -1, -1, -1, -1}; 13076 13077 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, 13078 DAG.getUNDEF(MVT::v16i8), 13079 ShufMask1); 13080 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, 13081 DAG.getUNDEF(MVT::v16i8), 13082 ShufMask1); 13083 13084 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13085 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13086 13087 // MOVLHPS 13088 int ShufMask2[] = {0, 1, 4, 5}; 13089 13090 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13091 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13092 } 13093 13094 return SDValue(); 13095} 13096 13097/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13098/// specific shuffle of a load can be folded into a single element load. 13099/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13100/// shuffles have been customed lowered so we need to handle those here. 13101static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13102 TargetLowering::DAGCombinerInfo &DCI) { 13103 if (DCI.isBeforeLegalizeOps()) 13104 return SDValue(); 13105 13106 SDValue InVec = N->getOperand(0); 13107 SDValue EltNo = N->getOperand(1); 13108 13109 if (!isa<ConstantSDNode>(EltNo)) 13110 return SDValue(); 13111 13112 EVT VT = InVec.getValueType(); 13113 13114 bool HasShuffleIntoBitcast = false; 13115 if (InVec.getOpcode() == ISD::BITCAST) { 13116 // Don't duplicate a load with other uses. 13117 if (!InVec.hasOneUse()) 13118 return SDValue(); 13119 EVT BCVT = InVec.getOperand(0).getValueType(); 13120 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13121 return SDValue(); 13122 InVec = InVec.getOperand(0); 13123 HasShuffleIntoBitcast = true; 13124 } 13125 13126 if (!isTargetShuffle(InVec.getOpcode())) 13127 return SDValue(); 13128 13129 // Don't duplicate a load with other uses. 13130 if (!InVec.hasOneUse()) 13131 return SDValue(); 13132 13133 SmallVector<int, 16> ShuffleMask; 13134 bool UnaryShuffle; 13135 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle)) 13136 return SDValue(); 13137 13138 // Select the input vector, guarding against out of range extract vector. 13139 unsigned NumElems = VT.getVectorNumElements(); 13140 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13141 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13142 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13143 : InVec.getOperand(1); 13144 13145 // If inputs to shuffle are the same for both ops, then allow 2 uses 13146 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13147 13148 if (LdNode.getOpcode() == ISD::BITCAST) { 13149 // Don't duplicate a load with other uses. 13150 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13151 return SDValue(); 13152 13153 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13154 LdNode = LdNode.getOperand(0); 13155 } 13156 13157 if (!ISD::isNormalLoad(LdNode.getNode())) 13158 return SDValue(); 13159 13160 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13161 13162 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13163 return SDValue(); 13164 13165 if (HasShuffleIntoBitcast) { 13166 // If there's a bitcast before the shuffle, check if the load type and 13167 // alignment is valid. 13168 unsigned Align = LN0->getAlignment(); 13169 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13170 unsigned NewAlign = TLI.getTargetData()-> 13171 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13172 13173 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13174 return SDValue(); 13175 } 13176 13177 // All checks match so transform back to vector_shuffle so that DAG combiner 13178 // can finish the job 13179 DebugLoc dl = N->getDebugLoc(); 13180 13181 // Create shuffle node taking into account the case that its a unary shuffle 13182 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13183 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13184 InVec.getOperand(0), Shuffle, 13185 &ShuffleMask[0]); 13186 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13188 EltNo); 13189} 13190 13191/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13192/// generation and convert it from being a bunch of shuffles and extracts 13193/// to a simple store and scalar loads to extract the elements. 13194static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13195 TargetLowering::DAGCombinerInfo &DCI) { 13196 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13197 if (NewOp.getNode()) 13198 return NewOp; 13199 13200 SDValue InputVector = N->getOperand(0); 13201 13202 // Only operate on vectors of 4 elements, where the alternative shuffling 13203 // gets to be more expensive. 13204 if (InputVector.getValueType() != MVT::v4i32) 13205 return SDValue(); 13206 13207 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13208 // single use which is a sign-extend or zero-extend, and all elements are 13209 // used. 13210 SmallVector<SDNode *, 4> Uses; 13211 unsigned ExtractedElements = 0; 13212 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13213 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13214 if (UI.getUse().getResNo() != InputVector.getResNo()) 13215 return SDValue(); 13216 13217 SDNode *Extract = *UI; 13218 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13219 return SDValue(); 13220 13221 if (Extract->getValueType(0) != MVT::i32) 13222 return SDValue(); 13223 if (!Extract->hasOneUse()) 13224 return SDValue(); 13225 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13226 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13227 return SDValue(); 13228 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13229 return SDValue(); 13230 13231 // Record which element was extracted. 13232 ExtractedElements |= 13233 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13234 13235 Uses.push_back(Extract); 13236 } 13237 13238 // If not all the elements were used, this may not be worthwhile. 13239 if (ExtractedElements != 15) 13240 return SDValue(); 13241 13242 // Ok, we've now decided to do the transformation. 13243 DebugLoc dl = InputVector.getDebugLoc(); 13244 13245 // Store the value to a temporary stack slot. 13246 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13247 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13248 MachinePointerInfo(), false, false, 0); 13249 13250 // Replace each use (extract) with a load of the appropriate element. 13251 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13252 UE = Uses.end(); UI != UE; ++UI) { 13253 SDNode *Extract = *UI; 13254 13255 // cOMpute the element's address. 13256 SDValue Idx = Extract->getOperand(1); 13257 unsigned EltSize = 13258 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13259 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13260 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13261 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13262 13263 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13264 StackPtr, OffsetVal); 13265 13266 // Load the scalar. 13267 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13268 ScalarAddr, MachinePointerInfo(), 13269 false, false, false, 0); 13270 13271 // Replace the exact with the load. 13272 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13273 } 13274 13275 // The replacement was made in place; don't return anything. 13276 return SDValue(); 13277} 13278 13279/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13280/// nodes. 13281static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13282 TargetLowering::DAGCombinerInfo &DCI, 13283 const X86Subtarget *Subtarget) { 13284 13285 13286 DebugLoc DL = N->getDebugLoc(); 13287 SDValue Cond = N->getOperand(0); 13288 // Get the LHS/RHS of the select. 13289 SDValue LHS = N->getOperand(1); 13290 SDValue RHS = N->getOperand(2); 13291 EVT VT = LHS.getValueType(); 13292 13293 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13294 // instructions match the semantics of the common C idiom x<y?x:y but not 13295 // x<=y?x:y, because of how they handle negative zero (which can be 13296 // ignored in unsafe-math mode). 13297 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13298 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13299 (Subtarget->hasSSE2() || 13300 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13301 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13302 13303 unsigned Opcode = 0; 13304 // Check for x CC y ? x : y. 13305 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13306 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13307 switch (CC) { 13308 default: break; 13309 case ISD::SETULT: 13310 // Converting this to a min would handle NaNs incorrectly, and swapping 13311 // the operands would cause it to handle comparisons between positive 13312 // and negative zero incorrectly. 13313 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13314 if (!DAG.getTarget().Options.UnsafeFPMath && 13315 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13316 break; 13317 std::swap(LHS, RHS); 13318 } 13319 Opcode = X86ISD::FMIN; 13320 break; 13321 case ISD::SETOLE: 13322 // Converting this to a min would handle comparisons between positive 13323 // and negative zero incorrectly. 13324 if (!DAG.getTarget().Options.UnsafeFPMath && 13325 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13326 break; 13327 Opcode = X86ISD::FMIN; 13328 break; 13329 case ISD::SETULE: 13330 // Converting this to a min would handle both negative zeros and NaNs 13331 // incorrectly, but we can swap the operands to fix both. 13332 std::swap(LHS, RHS); 13333 case ISD::SETOLT: 13334 case ISD::SETLT: 13335 case ISD::SETLE: 13336 Opcode = X86ISD::FMIN; 13337 break; 13338 13339 case ISD::SETOGE: 13340 // Converting this to a max would handle comparisons between positive 13341 // and negative zero incorrectly. 13342 if (!DAG.getTarget().Options.UnsafeFPMath && 13343 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13344 break; 13345 Opcode = X86ISD::FMAX; 13346 break; 13347 case ISD::SETUGT: 13348 // Converting this to a max would handle NaNs incorrectly, and swapping 13349 // the operands would cause it to handle comparisons between positive 13350 // and negative zero incorrectly. 13351 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13352 if (!DAG.getTarget().Options.UnsafeFPMath && 13353 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13354 break; 13355 std::swap(LHS, RHS); 13356 } 13357 Opcode = X86ISD::FMAX; 13358 break; 13359 case ISD::SETUGE: 13360 // Converting this to a max would handle both negative zeros and NaNs 13361 // incorrectly, but we can swap the operands to fix both. 13362 std::swap(LHS, RHS); 13363 case ISD::SETOGT: 13364 case ISD::SETGT: 13365 case ISD::SETGE: 13366 Opcode = X86ISD::FMAX; 13367 break; 13368 } 13369 // Check for x CC y ? y : x -- a min/max with reversed arms. 13370 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13371 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13372 switch (CC) { 13373 default: break; 13374 case ISD::SETOGE: 13375 // Converting this to a min would handle comparisons between positive 13376 // and negative zero incorrectly, and swapping the operands would 13377 // cause it to handle NaNs incorrectly. 13378 if (!DAG.getTarget().Options.UnsafeFPMath && 13379 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13380 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13381 break; 13382 std::swap(LHS, RHS); 13383 } 13384 Opcode = X86ISD::FMIN; 13385 break; 13386 case ISD::SETUGT: 13387 // Converting this to a min would handle NaNs incorrectly. 13388 if (!DAG.getTarget().Options.UnsafeFPMath && 13389 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13390 break; 13391 Opcode = X86ISD::FMIN; 13392 break; 13393 case ISD::SETUGE: 13394 // Converting this to a min would handle both negative zeros and NaNs 13395 // incorrectly, but we can swap the operands to fix both. 13396 std::swap(LHS, RHS); 13397 case ISD::SETOGT: 13398 case ISD::SETGT: 13399 case ISD::SETGE: 13400 Opcode = X86ISD::FMIN; 13401 break; 13402 13403 case ISD::SETULT: 13404 // Converting this to a max would handle NaNs incorrectly. 13405 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13406 break; 13407 Opcode = X86ISD::FMAX; 13408 break; 13409 case ISD::SETOLE: 13410 // Converting this to a max would handle comparisons between positive 13411 // and negative zero incorrectly, and swapping the operands would 13412 // cause it to handle NaNs incorrectly. 13413 if (!DAG.getTarget().Options.UnsafeFPMath && 13414 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13415 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13416 break; 13417 std::swap(LHS, RHS); 13418 } 13419 Opcode = X86ISD::FMAX; 13420 break; 13421 case ISD::SETULE: 13422 // Converting this to a max would handle both negative zeros and NaNs 13423 // incorrectly, but we can swap the operands to fix both. 13424 std::swap(LHS, RHS); 13425 case ISD::SETOLT: 13426 case ISD::SETLT: 13427 case ISD::SETLE: 13428 Opcode = X86ISD::FMAX; 13429 break; 13430 } 13431 } 13432 13433 if (Opcode) 13434 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13435 } 13436 13437 // If this is a select between two integer constants, try to do some 13438 // optimizations. 13439 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13440 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13441 // Don't do this for crazy integer types. 13442 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13443 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13444 // so that TrueC (the true value) is larger than FalseC. 13445 bool NeedsCondInvert = false; 13446 13447 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13448 // Efficiently invertible. 13449 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13450 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13451 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13452 NeedsCondInvert = true; 13453 std::swap(TrueC, FalseC); 13454 } 13455 13456 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13457 if (FalseC->getAPIntValue() == 0 && 13458 TrueC->getAPIntValue().isPowerOf2()) { 13459 if (NeedsCondInvert) // Invert the condition if needed. 13460 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13461 DAG.getConstant(1, Cond.getValueType())); 13462 13463 // Zero extend the condition if needed. 13464 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13465 13466 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13467 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13468 DAG.getConstant(ShAmt, MVT::i8)); 13469 } 13470 13471 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13472 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13473 if (NeedsCondInvert) // Invert the condition if needed. 13474 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13475 DAG.getConstant(1, Cond.getValueType())); 13476 13477 // Zero extend the condition if needed. 13478 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13479 FalseC->getValueType(0), Cond); 13480 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13481 SDValue(FalseC, 0)); 13482 } 13483 13484 // Optimize cases that will turn into an LEA instruction. This requires 13485 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13486 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13487 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13488 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13489 13490 bool isFastMultiplier = false; 13491 if (Diff < 10) { 13492 switch ((unsigned char)Diff) { 13493 default: break; 13494 case 1: // result = add base, cond 13495 case 2: // result = lea base( , cond*2) 13496 case 3: // result = lea base(cond, cond*2) 13497 case 4: // result = lea base( , cond*4) 13498 case 5: // result = lea base(cond, cond*4) 13499 case 8: // result = lea base( , cond*8) 13500 case 9: // result = lea base(cond, cond*8) 13501 isFastMultiplier = true; 13502 break; 13503 } 13504 } 13505 13506 if (isFastMultiplier) { 13507 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13508 if (NeedsCondInvert) // Invert the condition if needed. 13509 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13510 DAG.getConstant(1, Cond.getValueType())); 13511 13512 // Zero extend the condition if needed. 13513 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13514 Cond); 13515 // Scale the condition by the difference. 13516 if (Diff != 1) 13517 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13518 DAG.getConstant(Diff, Cond.getValueType())); 13519 13520 // Add the base if non-zero. 13521 if (FalseC->getAPIntValue() != 0) 13522 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13523 SDValue(FalseC, 0)); 13524 return Cond; 13525 } 13526 } 13527 } 13528 } 13529 13530 // Canonicalize max and min: 13531 // (x > y) ? x : y -> (x >= y) ? x : y 13532 // (x < y) ? x : y -> (x <= y) ? x : y 13533 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13534 // the need for an extra compare 13535 // against zero. e.g. 13536 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13537 // subl %esi, %edi 13538 // testl %edi, %edi 13539 // movl $0, %eax 13540 // cmovgl %edi, %eax 13541 // => 13542 // xorl %eax, %eax 13543 // subl %esi, $edi 13544 // cmovsl %eax, %edi 13545 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13546 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13547 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13548 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13549 switch (CC) { 13550 default: break; 13551 case ISD::SETLT: 13552 case ISD::SETGT: { 13553 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13554 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13555 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13556 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13557 } 13558 } 13559 } 13560 13561 // If we know that this node is legal then we know that it is going to be 13562 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13563 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13564 // to simplify previous instructions. 13565 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13566 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13567 !DCI.isBeforeLegalize() && 13568 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13569 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13570 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13571 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13572 13573 APInt KnownZero, KnownOne; 13574 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13575 DCI.isBeforeLegalizeOps()); 13576 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13577 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13578 DCI.CommitTargetLoweringOpt(TLO); 13579 } 13580 13581 return SDValue(); 13582} 13583 13584/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13585static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13586 TargetLowering::DAGCombinerInfo &DCI) { 13587 DebugLoc DL = N->getDebugLoc(); 13588 13589 // If the flag operand isn't dead, don't touch this CMOV. 13590 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13591 return SDValue(); 13592 13593 SDValue FalseOp = N->getOperand(0); 13594 SDValue TrueOp = N->getOperand(1); 13595 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13596 SDValue Cond = N->getOperand(3); 13597 if (CC == X86::COND_E || CC == X86::COND_NE) { 13598 switch (Cond.getOpcode()) { 13599 default: break; 13600 case X86ISD::BSR: 13601 case X86ISD::BSF: 13602 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13603 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13604 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13605 } 13606 } 13607 13608 // If this is a select between two integer constants, try to do some 13609 // optimizations. Note that the operands are ordered the opposite of SELECT 13610 // operands. 13611 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13612 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13613 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13614 // larger than FalseC (the false value). 13615 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13616 CC = X86::GetOppositeBranchCondition(CC); 13617 std::swap(TrueC, FalseC); 13618 } 13619 13620 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13621 // This is efficient for any integer data type (including i8/i16) and 13622 // shift amount. 13623 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13624 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13625 DAG.getConstant(CC, MVT::i8), Cond); 13626 13627 // Zero extend the condition if needed. 13628 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13629 13630 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13631 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13632 DAG.getConstant(ShAmt, MVT::i8)); 13633 if (N->getNumValues() == 2) // Dead flag value? 13634 return DCI.CombineTo(N, Cond, SDValue()); 13635 return Cond; 13636 } 13637 13638 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13639 // for any integer data type, including i8/i16. 13640 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13641 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13642 DAG.getConstant(CC, MVT::i8), Cond); 13643 13644 // Zero extend the condition if needed. 13645 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13646 FalseC->getValueType(0), Cond); 13647 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13648 SDValue(FalseC, 0)); 13649 13650 if (N->getNumValues() == 2) // Dead flag value? 13651 return DCI.CombineTo(N, Cond, SDValue()); 13652 return Cond; 13653 } 13654 13655 // Optimize cases that will turn into an LEA instruction. This requires 13656 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13657 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13658 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13659 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13660 13661 bool isFastMultiplier = false; 13662 if (Diff < 10) { 13663 switch ((unsigned char)Diff) { 13664 default: break; 13665 case 1: // result = add base, cond 13666 case 2: // result = lea base( , cond*2) 13667 case 3: // result = lea base(cond, cond*2) 13668 case 4: // result = lea base( , cond*4) 13669 case 5: // result = lea base(cond, cond*4) 13670 case 8: // result = lea base( , cond*8) 13671 case 9: // result = lea base(cond, cond*8) 13672 isFastMultiplier = true; 13673 break; 13674 } 13675 } 13676 13677 if (isFastMultiplier) { 13678 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13679 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13680 DAG.getConstant(CC, MVT::i8), Cond); 13681 // Zero extend the condition if needed. 13682 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13683 Cond); 13684 // Scale the condition by the difference. 13685 if (Diff != 1) 13686 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13687 DAG.getConstant(Diff, Cond.getValueType())); 13688 13689 // Add the base if non-zero. 13690 if (FalseC->getAPIntValue() != 0) 13691 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13692 SDValue(FalseC, 0)); 13693 if (N->getNumValues() == 2) // Dead flag value? 13694 return DCI.CombineTo(N, Cond, SDValue()); 13695 return Cond; 13696 } 13697 } 13698 } 13699 } 13700 return SDValue(); 13701} 13702 13703 13704/// PerformMulCombine - Optimize a single multiply with constant into two 13705/// in order to implement it with two cheaper instructions, e.g. 13706/// LEA + SHL, LEA + LEA. 13707static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13708 TargetLowering::DAGCombinerInfo &DCI) { 13709 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13710 return SDValue(); 13711 13712 EVT VT = N->getValueType(0); 13713 if (VT != MVT::i64) 13714 return SDValue(); 13715 13716 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13717 if (!C) 13718 return SDValue(); 13719 uint64_t MulAmt = C->getZExtValue(); 13720 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13721 return SDValue(); 13722 13723 uint64_t MulAmt1 = 0; 13724 uint64_t MulAmt2 = 0; 13725 if ((MulAmt % 9) == 0) { 13726 MulAmt1 = 9; 13727 MulAmt2 = MulAmt / 9; 13728 } else if ((MulAmt % 5) == 0) { 13729 MulAmt1 = 5; 13730 MulAmt2 = MulAmt / 5; 13731 } else if ((MulAmt % 3) == 0) { 13732 MulAmt1 = 3; 13733 MulAmt2 = MulAmt / 3; 13734 } 13735 if (MulAmt2 && 13736 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13737 DebugLoc DL = N->getDebugLoc(); 13738 13739 if (isPowerOf2_64(MulAmt2) && 13740 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13741 // If second multiplifer is pow2, issue it first. We want the multiply by 13742 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13743 // is an add. 13744 std::swap(MulAmt1, MulAmt2); 13745 13746 SDValue NewMul; 13747 if (isPowerOf2_64(MulAmt1)) 13748 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13749 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13750 else 13751 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13752 DAG.getConstant(MulAmt1, VT)); 13753 13754 if (isPowerOf2_64(MulAmt2)) 13755 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13756 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13757 else 13758 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13759 DAG.getConstant(MulAmt2, VT)); 13760 13761 // Do not add new nodes to DAG combiner worklist. 13762 DCI.CombineTo(N, NewMul, false); 13763 } 13764 return SDValue(); 13765} 13766 13767static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13768 SDValue N0 = N->getOperand(0); 13769 SDValue N1 = N->getOperand(1); 13770 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13771 EVT VT = N0.getValueType(); 13772 13773 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13774 // since the result of setcc_c is all zero's or all ones. 13775 if (VT.isInteger() && !VT.isVector() && 13776 N1C && N0.getOpcode() == ISD::AND && 13777 N0.getOperand(1).getOpcode() == ISD::Constant) { 13778 SDValue N00 = N0.getOperand(0); 13779 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13780 ((N00.getOpcode() == ISD::ANY_EXTEND || 13781 N00.getOpcode() == ISD::ZERO_EXTEND) && 13782 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13783 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13784 APInt ShAmt = N1C->getAPIntValue(); 13785 Mask = Mask.shl(ShAmt); 13786 if (Mask != 0) 13787 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13788 N00, DAG.getConstant(Mask, VT)); 13789 } 13790 } 13791 13792 13793 // Hardware support for vector shifts is sparse which makes us scalarize the 13794 // vector operations in many cases. Also, on sandybridge ADD is faster than 13795 // shl. 13796 // (shl V, 1) -> add V,V 13797 if (isSplatVector(N1.getNode())) { 13798 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13799 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13800 // We shift all of the values by one. In many cases we do not have 13801 // hardware support for this operation. This is better expressed as an ADD 13802 // of two values. 13803 if (N1C && (1 == N1C->getZExtValue())) { 13804 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13805 } 13806 } 13807 13808 return SDValue(); 13809} 13810 13811/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13812/// when possible. 13813static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13814 TargetLowering::DAGCombinerInfo &DCI, 13815 const X86Subtarget *Subtarget) { 13816 EVT VT = N->getValueType(0); 13817 if (N->getOpcode() == ISD::SHL) { 13818 SDValue V = PerformSHLCombine(N, DAG); 13819 if (V.getNode()) return V; 13820 } 13821 13822 // On X86 with SSE2 support, we can transform this to a vector shift if 13823 // all elements are shifted by the same amount. We can't do this in legalize 13824 // because the a constant vector is typically transformed to a constant pool 13825 // so we have no knowledge of the shift amount. 13826 if (!Subtarget->hasSSE2()) 13827 return SDValue(); 13828 13829 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13830 (!Subtarget->hasAVX2() || 13831 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13832 return SDValue(); 13833 13834 SDValue ShAmtOp = N->getOperand(1); 13835 EVT EltVT = VT.getVectorElementType(); 13836 DebugLoc DL = N->getDebugLoc(); 13837 SDValue BaseShAmt = SDValue(); 13838 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13839 unsigned NumElts = VT.getVectorNumElements(); 13840 unsigned i = 0; 13841 for (; i != NumElts; ++i) { 13842 SDValue Arg = ShAmtOp.getOperand(i); 13843 if (Arg.getOpcode() == ISD::UNDEF) continue; 13844 BaseShAmt = Arg; 13845 break; 13846 } 13847 // Handle the case where the build_vector is all undef 13848 // FIXME: Should DAG allow this? 13849 if (i == NumElts) 13850 return SDValue(); 13851 13852 for (; i != NumElts; ++i) { 13853 SDValue Arg = ShAmtOp.getOperand(i); 13854 if (Arg.getOpcode() == ISD::UNDEF) continue; 13855 if (Arg != BaseShAmt) { 13856 return SDValue(); 13857 } 13858 } 13859 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13860 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13861 SDValue InVec = ShAmtOp.getOperand(0); 13862 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13863 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13864 unsigned i = 0; 13865 for (; i != NumElts; ++i) { 13866 SDValue Arg = InVec.getOperand(i); 13867 if (Arg.getOpcode() == ISD::UNDEF) continue; 13868 BaseShAmt = Arg; 13869 break; 13870 } 13871 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13872 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13873 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13874 if (C->getZExtValue() == SplatIdx) 13875 BaseShAmt = InVec.getOperand(1); 13876 } 13877 } 13878 if (BaseShAmt.getNode() == 0) { 13879 // Don't create instructions with illegal types after legalize 13880 // types has run. 13881 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13882 !DCI.isBeforeLegalize()) 13883 return SDValue(); 13884 13885 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13886 DAG.getIntPtrConstant(0)); 13887 } 13888 } else 13889 return SDValue(); 13890 13891 // The shift amount is an i32. 13892 if (EltVT.bitsGT(MVT::i32)) 13893 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13894 else if (EltVT.bitsLT(MVT::i32)) 13895 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13896 13897 // The shift amount is identical so we can do a vector shift. 13898 SDValue ValOp = N->getOperand(0); 13899 switch (N->getOpcode()) { 13900 default: 13901 llvm_unreachable("Unknown shift opcode!"); 13902 case ISD::SHL: 13903 switch (VT.getSimpleVT().SimpleTy) { 13904 default: return SDValue(); 13905 case MVT::v2i64: 13906 case MVT::v4i32: 13907 case MVT::v8i16: 13908 case MVT::v4i64: 13909 case MVT::v8i32: 13910 case MVT::v16i16: 13911 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13912 } 13913 case ISD::SRA: 13914 switch (VT.getSimpleVT().SimpleTy) { 13915 default: return SDValue(); 13916 case MVT::v4i32: 13917 case MVT::v8i16: 13918 case MVT::v8i32: 13919 case MVT::v16i16: 13920 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13921 } 13922 case ISD::SRL: 13923 switch (VT.getSimpleVT().SimpleTy) { 13924 default: return SDValue(); 13925 case MVT::v2i64: 13926 case MVT::v4i32: 13927 case MVT::v8i16: 13928 case MVT::v4i64: 13929 case MVT::v8i32: 13930 case MVT::v16i16: 13931 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13932 } 13933 } 13934} 13935 13936 13937// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13938// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13939// and friends. Likewise for OR -> CMPNEQSS. 13940static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13941 TargetLowering::DAGCombinerInfo &DCI, 13942 const X86Subtarget *Subtarget) { 13943 unsigned opcode; 13944 13945 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13946 // we're requiring SSE2 for both. 13947 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13948 SDValue N0 = N->getOperand(0); 13949 SDValue N1 = N->getOperand(1); 13950 SDValue CMP0 = N0->getOperand(1); 13951 SDValue CMP1 = N1->getOperand(1); 13952 DebugLoc DL = N->getDebugLoc(); 13953 13954 // The SETCCs should both refer to the same CMP. 13955 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13956 return SDValue(); 13957 13958 SDValue CMP00 = CMP0->getOperand(0); 13959 SDValue CMP01 = CMP0->getOperand(1); 13960 EVT VT = CMP00.getValueType(); 13961 13962 if (VT == MVT::f32 || VT == MVT::f64) { 13963 bool ExpectingFlags = false; 13964 // Check for any users that want flags: 13965 for (SDNode::use_iterator UI = N->use_begin(), 13966 UE = N->use_end(); 13967 !ExpectingFlags && UI != UE; ++UI) 13968 switch (UI->getOpcode()) { 13969 default: 13970 case ISD::BR_CC: 13971 case ISD::BRCOND: 13972 case ISD::SELECT: 13973 ExpectingFlags = true; 13974 break; 13975 case ISD::CopyToReg: 13976 case ISD::SIGN_EXTEND: 13977 case ISD::ZERO_EXTEND: 13978 case ISD::ANY_EXTEND: 13979 break; 13980 } 13981 13982 if (!ExpectingFlags) { 13983 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13984 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13985 13986 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13987 X86::CondCode tmp = cc0; 13988 cc0 = cc1; 13989 cc1 = tmp; 13990 } 13991 13992 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13993 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13994 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13995 X86ISD::NodeType NTOperator = is64BitFP ? 13996 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13997 // FIXME: need symbolic constants for these magic numbers. 13998 // See X86ATTInstPrinter.cpp:printSSECC(). 13999 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 14000 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 14001 DAG.getConstant(x86cc, MVT::i8)); 14002 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 14003 OnesOrZeroesF); 14004 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 14005 DAG.getConstant(1, MVT::i32)); 14006 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 14007 return OneBitOfTruth; 14008 } 14009 } 14010 } 14011 } 14012 return SDValue(); 14013} 14014 14015/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 14016/// so it can be folded inside ANDNP. 14017static bool CanFoldXORWithAllOnes(const SDNode *N) { 14018 EVT VT = N->getValueType(0); 14019 14020 // Match direct AllOnes for 128 and 256-bit vectors 14021 if (ISD::isBuildVectorAllOnes(N)) 14022 return true; 14023 14024 // Look through a bit convert. 14025 if (N->getOpcode() == ISD::BITCAST) 14026 N = N->getOperand(0).getNode(); 14027 14028 // Sometimes the operand may come from a insert_subvector building a 256-bit 14029 // allones vector 14030 if (VT.getSizeInBits() == 256 && 14031 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 14032 SDValue V1 = N->getOperand(0); 14033 SDValue V2 = N->getOperand(1); 14034 14035 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 14036 V1.getOperand(0).getOpcode() == ISD::UNDEF && 14037 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 14038 ISD::isBuildVectorAllOnes(V2.getNode())) 14039 return true; 14040 } 14041 14042 return false; 14043} 14044 14045static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 14046 TargetLowering::DAGCombinerInfo &DCI, 14047 const X86Subtarget *Subtarget) { 14048 if (DCI.isBeforeLegalizeOps()) 14049 return SDValue(); 14050 14051 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14052 if (R.getNode()) 14053 return R; 14054 14055 EVT VT = N->getValueType(0); 14056 14057 // Create ANDN, BLSI, and BLSR instructions 14058 // BLSI is X & (-X) 14059 // BLSR is X & (X-1) 14060 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 14061 SDValue N0 = N->getOperand(0); 14062 SDValue N1 = N->getOperand(1); 14063 DebugLoc DL = N->getDebugLoc(); 14064 14065 // Check LHS for not 14066 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 14067 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 14068 // Check RHS for not 14069 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 14070 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14071 14072 // Check LHS for neg 14073 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14074 isZero(N0.getOperand(0))) 14075 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14076 14077 // Check RHS for neg 14078 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14079 isZero(N1.getOperand(0))) 14080 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14081 14082 // Check LHS for X-1 14083 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14084 isAllOnes(N0.getOperand(1))) 14085 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14086 14087 // Check RHS for X-1 14088 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14089 isAllOnes(N1.getOperand(1))) 14090 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14091 14092 return SDValue(); 14093 } 14094 14095 // Want to form ANDNP nodes: 14096 // 1) In the hopes of then easily combining them with OR and AND nodes 14097 // to form PBLEND/PSIGN. 14098 // 2) To match ANDN packed intrinsics 14099 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14100 return SDValue(); 14101 14102 SDValue N0 = N->getOperand(0); 14103 SDValue N1 = N->getOperand(1); 14104 DebugLoc DL = N->getDebugLoc(); 14105 14106 // Check LHS for vnot 14107 if (N0.getOpcode() == ISD::XOR && 14108 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14109 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14110 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14111 14112 // Check RHS for vnot 14113 if (N1.getOpcode() == ISD::XOR && 14114 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14115 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14116 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14117 14118 return SDValue(); 14119} 14120 14121static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14122 TargetLowering::DAGCombinerInfo &DCI, 14123 const X86Subtarget *Subtarget) { 14124 if (DCI.isBeforeLegalizeOps()) 14125 return SDValue(); 14126 14127 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14128 if (R.getNode()) 14129 return R; 14130 14131 EVT VT = N->getValueType(0); 14132 14133 SDValue N0 = N->getOperand(0); 14134 SDValue N1 = N->getOperand(1); 14135 14136 // look for psign/blend 14137 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14138 if (!Subtarget->hasSSSE3() || 14139 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14140 return SDValue(); 14141 14142 // Canonicalize pandn to RHS 14143 if (N0.getOpcode() == X86ISD::ANDNP) 14144 std::swap(N0, N1); 14145 // or (and (m, y), (pandn m, x)) 14146 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14147 SDValue Mask = N1.getOperand(0); 14148 SDValue X = N1.getOperand(1); 14149 SDValue Y; 14150 if (N0.getOperand(0) == Mask) 14151 Y = N0.getOperand(1); 14152 if (N0.getOperand(1) == Mask) 14153 Y = N0.getOperand(0); 14154 14155 // Check to see if the mask appeared in both the AND and ANDNP and 14156 if (!Y.getNode()) 14157 return SDValue(); 14158 14159 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14160 // Look through mask bitcast. 14161 if (Mask.getOpcode() == ISD::BITCAST) 14162 Mask = Mask.getOperand(0); 14163 if (X.getOpcode() == ISD::BITCAST) 14164 X = X.getOperand(0); 14165 if (Y.getOpcode() == ISD::BITCAST) 14166 Y = Y.getOperand(0); 14167 14168 EVT MaskVT = Mask.getValueType(); 14169 14170 // Validate that the Mask operand is a vector sra node. 14171 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14172 // there is no psrai.b 14173 if (Mask.getOpcode() != X86ISD::VSRAI) 14174 return SDValue(); 14175 14176 // Check that the SRA is all signbits. 14177 SDValue SraC = Mask.getOperand(1); 14178 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14179 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14180 if ((SraAmt + 1) != EltBits) 14181 return SDValue(); 14182 14183 DebugLoc DL = N->getDebugLoc(); 14184 14185 // Now we know we at least have a plendvb with the mask val. See if 14186 // we can form a psignb/w/d. 14187 // psign = x.type == y.type == mask.type && y = sub(0, x); 14188 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14189 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14190 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14191 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14192 "Unsupported VT for PSIGN"); 14193 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14194 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14195 } 14196 // PBLENDVB only available on SSE 4.1 14197 if (!Subtarget->hasSSE41()) 14198 return SDValue(); 14199 14200 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14201 14202 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14203 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14204 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14205 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14206 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14207 } 14208 } 14209 14210 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14211 return SDValue(); 14212 14213 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14214 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14215 std::swap(N0, N1); 14216 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14217 return SDValue(); 14218 if (!N0.hasOneUse() || !N1.hasOneUse()) 14219 return SDValue(); 14220 14221 SDValue ShAmt0 = N0.getOperand(1); 14222 if (ShAmt0.getValueType() != MVT::i8) 14223 return SDValue(); 14224 SDValue ShAmt1 = N1.getOperand(1); 14225 if (ShAmt1.getValueType() != MVT::i8) 14226 return SDValue(); 14227 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14228 ShAmt0 = ShAmt0.getOperand(0); 14229 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14230 ShAmt1 = ShAmt1.getOperand(0); 14231 14232 DebugLoc DL = N->getDebugLoc(); 14233 unsigned Opc = X86ISD::SHLD; 14234 SDValue Op0 = N0.getOperand(0); 14235 SDValue Op1 = N1.getOperand(0); 14236 if (ShAmt0.getOpcode() == ISD::SUB) { 14237 Opc = X86ISD::SHRD; 14238 std::swap(Op0, Op1); 14239 std::swap(ShAmt0, ShAmt1); 14240 } 14241 14242 unsigned Bits = VT.getSizeInBits(); 14243 if (ShAmt1.getOpcode() == ISD::SUB) { 14244 SDValue Sum = ShAmt1.getOperand(0); 14245 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14246 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14247 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14248 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14249 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14250 return DAG.getNode(Opc, DL, VT, 14251 Op0, Op1, 14252 DAG.getNode(ISD::TRUNCATE, DL, 14253 MVT::i8, ShAmt0)); 14254 } 14255 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14256 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14257 if (ShAmt0C && 14258 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14259 return DAG.getNode(Opc, DL, VT, 14260 N0.getOperand(0), N1.getOperand(0), 14261 DAG.getNode(ISD::TRUNCATE, DL, 14262 MVT::i8, ShAmt0)); 14263 } 14264 14265 return SDValue(); 14266} 14267 14268// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14269static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14270 TargetLowering::DAGCombinerInfo &DCI, 14271 const X86Subtarget *Subtarget) { 14272 if (DCI.isBeforeLegalizeOps()) 14273 return SDValue(); 14274 14275 EVT VT = N->getValueType(0); 14276 14277 if (VT != MVT::i32 && VT != MVT::i64) 14278 return SDValue(); 14279 14280 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14281 14282 // Create BLSMSK instructions by finding X ^ (X-1) 14283 SDValue N0 = N->getOperand(0); 14284 SDValue N1 = N->getOperand(1); 14285 DebugLoc DL = N->getDebugLoc(); 14286 14287 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14288 isAllOnes(N0.getOperand(1))) 14289 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14290 14291 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14292 isAllOnes(N1.getOperand(1))) 14293 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14294 14295 return SDValue(); 14296} 14297 14298/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14299static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14300 const X86Subtarget *Subtarget) { 14301 LoadSDNode *Ld = cast<LoadSDNode>(N); 14302 EVT RegVT = Ld->getValueType(0); 14303 EVT MemVT = Ld->getMemoryVT(); 14304 DebugLoc dl = Ld->getDebugLoc(); 14305 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14306 14307 ISD::LoadExtType Ext = Ld->getExtensionType(); 14308 14309 // If this is a vector EXT Load then attempt to optimize it using a 14310 // shuffle. We need SSE4 for the shuffles. 14311 // TODO: It is possible to support ZExt by zeroing the undef values 14312 // during the shuffle phase or after the shuffle. 14313 if (RegVT.isVector() && RegVT.isInteger() && 14314 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14315 assert(MemVT != RegVT && "Cannot extend to the same type"); 14316 assert(MemVT.isVector() && "Must load a vector from memory"); 14317 14318 unsigned NumElems = RegVT.getVectorNumElements(); 14319 unsigned RegSz = RegVT.getSizeInBits(); 14320 unsigned MemSz = MemVT.getSizeInBits(); 14321 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14322 // All sizes must be a power of two 14323 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14324 14325 // Attempt to load the original value using a single load op. 14326 // Find a scalar type which is equal to the loaded word size. 14327 MVT SclrLoadTy = MVT::i8; 14328 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14329 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14330 MVT Tp = (MVT::SimpleValueType)tp; 14331 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14332 SclrLoadTy = Tp; 14333 break; 14334 } 14335 } 14336 14337 // Proceed if a load word is found. 14338 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14339 14340 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14341 RegSz/SclrLoadTy.getSizeInBits()); 14342 14343 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14344 RegSz/MemVT.getScalarType().getSizeInBits()); 14345 // Can't shuffle using an illegal type. 14346 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14347 14348 // Perform a single load. 14349 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14350 Ld->getBasePtr(), 14351 Ld->getPointerInfo(), Ld->isVolatile(), 14352 Ld->isNonTemporal(), Ld->isInvariant(), 14353 Ld->getAlignment()); 14354 14355 // Insert the word loaded into a vector. 14356 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14357 LoadUnitVecVT, ScalarLoad); 14358 14359 // Bitcast the loaded value to a vector of the original element type, in 14360 // the size of the target vector type. 14361 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14362 ScalarInVector); 14363 unsigned SizeRatio = RegSz/MemSz; 14364 14365 // Redistribute the loaded elements into the different locations. 14366 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14367 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14368 14369 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14370 DAG.getUNDEF(SlicedVec.getValueType()), 14371 ShuffleVec.data()); 14372 14373 // Bitcast to the requested type. 14374 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14375 // Replace the original load with the new sequence 14376 // and return the new chain. 14377 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14378 return SDValue(ScalarLoad.getNode(), 1); 14379 } 14380 14381 return SDValue(); 14382} 14383 14384/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14385static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14386 const X86Subtarget *Subtarget) { 14387 StoreSDNode *St = cast<StoreSDNode>(N); 14388 EVT VT = St->getValue().getValueType(); 14389 EVT StVT = St->getMemoryVT(); 14390 DebugLoc dl = St->getDebugLoc(); 14391 SDValue StoredVal = St->getOperand(1); 14392 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14393 14394 // If we are saving a concatenation of two XMM registers, perform two stores. 14395 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14396 // 128-bit ones. If in the future the cost becomes only one memory access the 14397 // first version would be better. 14398 if (VT.getSizeInBits() == 256 && 14399 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14400 StoredVal.getNumOperands() == 2) { 14401 14402 SDValue Value0 = StoredVal.getOperand(0); 14403 SDValue Value1 = StoredVal.getOperand(1); 14404 14405 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14406 SDValue Ptr0 = St->getBasePtr(); 14407 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14408 14409 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14410 St->getPointerInfo(), St->isVolatile(), 14411 St->isNonTemporal(), St->getAlignment()); 14412 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14413 St->getPointerInfo(), St->isVolatile(), 14414 St->isNonTemporal(), St->getAlignment()); 14415 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14416 } 14417 14418 // Optimize trunc store (of multiple scalars) to shuffle and store. 14419 // First, pack all of the elements in one place. Next, store to memory 14420 // in fewer chunks. 14421 if (St->isTruncatingStore() && VT.isVector()) { 14422 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14423 unsigned NumElems = VT.getVectorNumElements(); 14424 assert(StVT != VT && "Cannot truncate to the same type"); 14425 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14426 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14427 14428 // From, To sizes and ElemCount must be pow of two 14429 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14430 // We are going to use the original vector elt for storing. 14431 // Accumulated smaller vector elements must be a multiple of the store size. 14432 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14433 14434 unsigned SizeRatio = FromSz / ToSz; 14435 14436 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14437 14438 // Create a type on which we perform the shuffle 14439 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14440 StVT.getScalarType(), NumElems*SizeRatio); 14441 14442 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14443 14444 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14445 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14446 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14447 14448 // Can't shuffle using an illegal type 14449 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14450 14451 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14452 DAG.getUNDEF(WideVec.getValueType()), 14453 ShuffleVec.data()); 14454 // At this point all of the data is stored at the bottom of the 14455 // register. We now need to save it to mem. 14456 14457 // Find the largest store unit 14458 MVT StoreType = MVT::i8; 14459 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14460 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14461 MVT Tp = (MVT::SimpleValueType)tp; 14462 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14463 StoreType = Tp; 14464 } 14465 14466 // Bitcast the original vector into a vector of store-size units 14467 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14468 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14469 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14470 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14471 SmallVector<SDValue, 8> Chains; 14472 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14473 TLI.getPointerTy()); 14474 SDValue Ptr = St->getBasePtr(); 14475 14476 // Perform one or more big stores into memory. 14477 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14478 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14479 StoreType, ShuffWide, 14480 DAG.getIntPtrConstant(i)); 14481 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14482 St->getPointerInfo(), St->isVolatile(), 14483 St->isNonTemporal(), St->getAlignment()); 14484 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14485 Chains.push_back(Ch); 14486 } 14487 14488 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14489 Chains.size()); 14490 } 14491 14492 14493 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14494 // the FP state in cases where an emms may be missing. 14495 // A preferable solution to the general problem is to figure out the right 14496 // places to insert EMMS. This qualifies as a quick hack. 14497 14498 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14499 if (VT.getSizeInBits() != 64) 14500 return SDValue(); 14501 14502 const Function *F = DAG.getMachineFunction().getFunction(); 14503 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14504 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14505 && Subtarget->hasSSE2(); 14506 if ((VT.isVector() || 14507 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14508 isa<LoadSDNode>(St->getValue()) && 14509 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14510 St->getChain().hasOneUse() && !St->isVolatile()) { 14511 SDNode* LdVal = St->getValue().getNode(); 14512 LoadSDNode *Ld = 0; 14513 int TokenFactorIndex = -1; 14514 SmallVector<SDValue, 8> Ops; 14515 SDNode* ChainVal = St->getChain().getNode(); 14516 // Must be a store of a load. We currently handle two cases: the load 14517 // is a direct child, and it's under an intervening TokenFactor. It is 14518 // possible to dig deeper under nested TokenFactors. 14519 if (ChainVal == LdVal) 14520 Ld = cast<LoadSDNode>(St->getChain()); 14521 else if (St->getValue().hasOneUse() && 14522 ChainVal->getOpcode() == ISD::TokenFactor) { 14523 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14524 if (ChainVal->getOperand(i).getNode() == LdVal) { 14525 TokenFactorIndex = i; 14526 Ld = cast<LoadSDNode>(St->getValue()); 14527 } else 14528 Ops.push_back(ChainVal->getOperand(i)); 14529 } 14530 } 14531 14532 if (!Ld || !ISD::isNormalLoad(Ld)) 14533 return SDValue(); 14534 14535 // If this is not the MMX case, i.e. we are just turning i64 load/store 14536 // into f64 load/store, avoid the transformation if there are multiple 14537 // uses of the loaded value. 14538 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14539 return SDValue(); 14540 14541 DebugLoc LdDL = Ld->getDebugLoc(); 14542 DebugLoc StDL = N->getDebugLoc(); 14543 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14544 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14545 // pair instead. 14546 if (Subtarget->is64Bit() || F64IsLegal) { 14547 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14548 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14549 Ld->getPointerInfo(), Ld->isVolatile(), 14550 Ld->isNonTemporal(), Ld->isInvariant(), 14551 Ld->getAlignment()); 14552 SDValue NewChain = NewLd.getValue(1); 14553 if (TokenFactorIndex != -1) { 14554 Ops.push_back(NewChain); 14555 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14556 Ops.size()); 14557 } 14558 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14559 St->getPointerInfo(), 14560 St->isVolatile(), St->isNonTemporal(), 14561 St->getAlignment()); 14562 } 14563 14564 // Otherwise, lower to two pairs of 32-bit loads / stores. 14565 SDValue LoAddr = Ld->getBasePtr(); 14566 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14567 DAG.getConstant(4, MVT::i32)); 14568 14569 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14570 Ld->getPointerInfo(), 14571 Ld->isVolatile(), Ld->isNonTemporal(), 14572 Ld->isInvariant(), Ld->getAlignment()); 14573 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14574 Ld->getPointerInfo().getWithOffset(4), 14575 Ld->isVolatile(), Ld->isNonTemporal(), 14576 Ld->isInvariant(), 14577 MinAlign(Ld->getAlignment(), 4)); 14578 14579 SDValue NewChain = LoLd.getValue(1); 14580 if (TokenFactorIndex != -1) { 14581 Ops.push_back(LoLd); 14582 Ops.push_back(HiLd); 14583 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14584 Ops.size()); 14585 } 14586 14587 LoAddr = St->getBasePtr(); 14588 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14589 DAG.getConstant(4, MVT::i32)); 14590 14591 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14592 St->getPointerInfo(), 14593 St->isVolatile(), St->isNonTemporal(), 14594 St->getAlignment()); 14595 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14596 St->getPointerInfo().getWithOffset(4), 14597 St->isVolatile(), 14598 St->isNonTemporal(), 14599 MinAlign(St->getAlignment(), 4)); 14600 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14601 } 14602 return SDValue(); 14603} 14604 14605/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14606/// and return the operands for the horizontal operation in LHS and RHS. A 14607/// horizontal operation performs the binary operation on successive elements 14608/// of its first operand, then on successive elements of its second operand, 14609/// returning the resulting values in a vector. For example, if 14610/// A = < float a0, float a1, float a2, float a3 > 14611/// and 14612/// B = < float b0, float b1, float b2, float b3 > 14613/// then the result of doing a horizontal operation on A and B is 14614/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14615/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14616/// A horizontal-op B, for some already available A and B, and if so then LHS is 14617/// set to A, RHS to B, and the routine returns 'true'. 14618/// Note that the binary operation should have the property that if one of the 14619/// operands is UNDEF then the result is UNDEF. 14620static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14621 // Look for the following pattern: if 14622 // A = < float a0, float a1, float a2, float a3 > 14623 // B = < float b0, float b1, float b2, float b3 > 14624 // and 14625 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14626 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14627 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14628 // which is A horizontal-op B. 14629 14630 // At least one of the operands should be a vector shuffle. 14631 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14632 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14633 return false; 14634 14635 EVT VT = LHS.getValueType(); 14636 14637 assert((VT.is128BitVector() || VT.is256BitVector()) && 14638 "Unsupported vector type for horizontal add/sub"); 14639 14640 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14641 // operate independently on 128-bit lanes. 14642 unsigned NumElts = VT.getVectorNumElements(); 14643 unsigned NumLanes = VT.getSizeInBits()/128; 14644 unsigned NumLaneElts = NumElts / NumLanes; 14645 assert((NumLaneElts % 2 == 0) && 14646 "Vector type should have an even number of elements in each lane"); 14647 unsigned HalfLaneElts = NumLaneElts/2; 14648 14649 // View LHS in the form 14650 // LHS = VECTOR_SHUFFLE A, B, LMask 14651 // If LHS is not a shuffle then pretend it is the shuffle 14652 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14653 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14654 // type VT. 14655 SDValue A, B; 14656 SmallVector<int, 16> LMask(NumElts); 14657 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14658 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14659 A = LHS.getOperand(0); 14660 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14661 B = LHS.getOperand(1); 14662 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14663 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14664 } else { 14665 if (LHS.getOpcode() != ISD::UNDEF) 14666 A = LHS; 14667 for (unsigned i = 0; i != NumElts; ++i) 14668 LMask[i] = i; 14669 } 14670 14671 // Likewise, view RHS in the form 14672 // RHS = VECTOR_SHUFFLE C, D, RMask 14673 SDValue C, D; 14674 SmallVector<int, 16> RMask(NumElts); 14675 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14676 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14677 C = RHS.getOperand(0); 14678 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14679 D = RHS.getOperand(1); 14680 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14681 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14682 } else { 14683 if (RHS.getOpcode() != ISD::UNDEF) 14684 C = RHS; 14685 for (unsigned i = 0; i != NumElts; ++i) 14686 RMask[i] = i; 14687 } 14688 14689 // Check that the shuffles are both shuffling the same vectors. 14690 if (!(A == C && B == D) && !(A == D && B == C)) 14691 return false; 14692 14693 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14694 if (!A.getNode() && !B.getNode()) 14695 return false; 14696 14697 // If A and B occur in reverse order in RHS, then "swap" them (which means 14698 // rewriting the mask). 14699 if (A != C) 14700 CommuteVectorShuffleMask(RMask, NumElts); 14701 14702 // At this point LHS and RHS are equivalent to 14703 // LHS = VECTOR_SHUFFLE A, B, LMask 14704 // RHS = VECTOR_SHUFFLE A, B, RMask 14705 // Check that the masks correspond to performing a horizontal operation. 14706 for (unsigned i = 0; i != NumElts; ++i) { 14707 int LIdx = LMask[i], RIdx = RMask[i]; 14708 14709 // Ignore any UNDEF components. 14710 if (LIdx < 0 || RIdx < 0 || 14711 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14712 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14713 continue; 14714 14715 // Check that successive elements are being operated on. If not, this is 14716 // not a horizontal operation. 14717 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14718 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14719 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14720 if (!(LIdx == Index && RIdx == Index + 1) && 14721 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14722 return false; 14723 } 14724 14725 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14726 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14727 return true; 14728} 14729 14730/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14731static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14732 const X86Subtarget *Subtarget) { 14733 EVT VT = N->getValueType(0); 14734 SDValue LHS = N->getOperand(0); 14735 SDValue RHS = N->getOperand(1); 14736 14737 // Try to synthesize horizontal adds from adds of shuffles. 14738 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14739 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14740 isHorizontalBinOp(LHS, RHS, true)) 14741 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14742 return SDValue(); 14743} 14744 14745/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14746static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14747 const X86Subtarget *Subtarget) { 14748 EVT VT = N->getValueType(0); 14749 SDValue LHS = N->getOperand(0); 14750 SDValue RHS = N->getOperand(1); 14751 14752 // Try to synthesize horizontal subs from subs of shuffles. 14753 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14754 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14755 isHorizontalBinOp(LHS, RHS, false)) 14756 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14757 return SDValue(); 14758} 14759 14760/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14761/// X86ISD::FXOR nodes. 14762static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14763 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14764 // F[X]OR(0.0, x) -> x 14765 // F[X]OR(x, 0.0) -> x 14766 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14767 if (C->getValueAPF().isPosZero()) 14768 return N->getOperand(1); 14769 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14770 if (C->getValueAPF().isPosZero()) 14771 return N->getOperand(0); 14772 return SDValue(); 14773} 14774 14775/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14776static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14777 // FAND(0.0, x) -> 0.0 14778 // FAND(x, 0.0) -> 0.0 14779 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14780 if (C->getValueAPF().isPosZero()) 14781 return N->getOperand(0); 14782 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14783 if (C->getValueAPF().isPosZero()) 14784 return N->getOperand(1); 14785 return SDValue(); 14786} 14787 14788static SDValue PerformBTCombine(SDNode *N, 14789 SelectionDAG &DAG, 14790 TargetLowering::DAGCombinerInfo &DCI) { 14791 // BT ignores high bits in the bit index operand. 14792 SDValue Op1 = N->getOperand(1); 14793 if (Op1.hasOneUse()) { 14794 unsigned BitWidth = Op1.getValueSizeInBits(); 14795 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14796 APInt KnownZero, KnownOne; 14797 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14798 !DCI.isBeforeLegalizeOps()); 14799 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14800 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14801 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14802 DCI.CommitTargetLoweringOpt(TLO); 14803 } 14804 return SDValue(); 14805} 14806 14807static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14808 SDValue Op = N->getOperand(0); 14809 if (Op.getOpcode() == ISD::BITCAST) 14810 Op = Op.getOperand(0); 14811 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14812 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14813 VT.getVectorElementType().getSizeInBits() == 14814 OpVT.getVectorElementType().getSizeInBits()) { 14815 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14816 } 14817 return SDValue(); 14818} 14819 14820static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14821 TargetLowering::DAGCombinerInfo &DCI, 14822 const X86Subtarget *Subtarget) { 14823 if (!DCI.isBeforeLegalizeOps()) 14824 return SDValue(); 14825 14826 if (!Subtarget->hasAVX()) 14827 return SDValue(); 14828 14829 // Optimize vectors in AVX mode 14830 // Sign extend v8i16 to v8i32 and 14831 // v4i32 to v4i64 14832 // 14833 // Divide input vector into two parts 14834 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14835 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14836 // concat the vectors to original VT 14837 14838 EVT VT = N->getValueType(0); 14839 SDValue Op = N->getOperand(0); 14840 EVT OpVT = Op.getValueType(); 14841 DebugLoc dl = N->getDebugLoc(); 14842 14843 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14844 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14845 14846 unsigned NumElems = OpVT.getVectorNumElements(); 14847 SmallVector<int,8> ShufMask1(NumElems, -1); 14848 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i; 14849 14850 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14851 ShufMask1.data()); 14852 14853 SmallVector<int,8> ShufMask2(NumElems, -1); 14854 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2; 14855 14856 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14857 ShufMask2.data()); 14858 14859 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14860 VT.getVectorNumElements()/2); 14861 14862 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14863 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14864 14865 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14866 } 14867 return SDValue(); 14868} 14869 14870static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14871 const X86Subtarget *Subtarget) { 14872 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14873 // (and (i32 x86isd::setcc_carry), 1) 14874 // This eliminates the zext. This transformation is necessary because 14875 // ISD::SETCC is always legalized to i8. 14876 DebugLoc dl = N->getDebugLoc(); 14877 SDValue N0 = N->getOperand(0); 14878 EVT VT = N->getValueType(0); 14879 EVT OpVT = N0.getValueType(); 14880 14881 if (N0.getOpcode() == ISD::AND && 14882 N0.hasOneUse() && 14883 N0.getOperand(0).hasOneUse()) { 14884 SDValue N00 = N0.getOperand(0); 14885 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14886 return SDValue(); 14887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14888 if (!C || C->getZExtValue() != 1) 14889 return SDValue(); 14890 return DAG.getNode(ISD::AND, dl, VT, 14891 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14892 N00.getOperand(0), N00.getOperand(1)), 14893 DAG.getConstant(1, VT)); 14894 } 14895 // Optimize vectors in AVX mode: 14896 // 14897 // v8i16 -> v8i32 14898 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14899 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14900 // Concat upper and lower parts. 14901 // 14902 // v4i32 -> v4i64 14903 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14904 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14905 // Concat upper and lower parts. 14906 // 14907 if (Subtarget->hasAVX()) { 14908 14909 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14910 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14911 14912 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14913 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG); 14914 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG); 14915 14916 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14917 VT.getVectorNumElements()/2); 14918 14919 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14920 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14921 14922 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14923 } 14924 } 14925 14926 14927 return SDValue(); 14928} 14929 14930// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14931static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14932 unsigned X86CC = N->getConstantOperandVal(0); 14933 SDValue EFLAG = N->getOperand(1); 14934 DebugLoc DL = N->getDebugLoc(); 14935 14936 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14937 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14938 // cases. 14939 if (X86CC == X86::COND_B) 14940 return DAG.getNode(ISD::AND, DL, MVT::i8, 14941 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14942 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14943 DAG.getConstant(1, MVT::i8)); 14944 14945 return SDValue(); 14946} 14947 14948static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14949 const X86TargetLowering *XTLI) { 14950 SDValue Op0 = N->getOperand(0); 14951 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14952 // a 32-bit target where SSE doesn't support i64->FP operations. 14953 if (Op0.getOpcode() == ISD::LOAD) { 14954 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14955 EVT VT = Ld->getValueType(0); 14956 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14957 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14958 !XTLI->getSubtarget()->is64Bit() && 14959 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14960 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14961 Ld->getChain(), Op0, DAG); 14962 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14963 return FILDChain; 14964 } 14965 } 14966 return SDValue(); 14967} 14968 14969// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14970static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14971 X86TargetLowering::DAGCombinerInfo &DCI) { 14972 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14973 // the result is either zero or one (depending on the input carry bit). 14974 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14975 if (X86::isZeroNode(N->getOperand(0)) && 14976 X86::isZeroNode(N->getOperand(1)) && 14977 // We don't have a good way to replace an EFLAGS use, so only do this when 14978 // dead right now. 14979 SDValue(N, 1).use_empty()) { 14980 DebugLoc DL = N->getDebugLoc(); 14981 EVT VT = N->getValueType(0); 14982 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14983 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14984 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14985 DAG.getConstant(X86::COND_B,MVT::i8), 14986 N->getOperand(2)), 14987 DAG.getConstant(1, VT)); 14988 return DCI.CombineTo(N, Res1, CarryOut); 14989 } 14990 14991 return SDValue(); 14992} 14993 14994// fold (add Y, (sete X, 0)) -> adc 0, Y 14995// (add Y, (setne X, 0)) -> sbb -1, Y 14996// (sub (sete X, 0), Y) -> sbb 0, Y 14997// (sub (setne X, 0), Y) -> adc -1, Y 14998static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14999 DebugLoc DL = N->getDebugLoc(); 15000 15001 // Look through ZExts. 15002 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 15003 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 15004 return SDValue(); 15005 15006 SDValue SetCC = Ext.getOperand(0); 15007 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 15008 return SDValue(); 15009 15010 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 15011 if (CC != X86::COND_E && CC != X86::COND_NE) 15012 return SDValue(); 15013 15014 SDValue Cmp = SetCC.getOperand(1); 15015 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 15016 !X86::isZeroNode(Cmp.getOperand(1)) || 15017 !Cmp.getOperand(0).getValueType().isInteger()) 15018 return SDValue(); 15019 15020 SDValue CmpOp0 = Cmp.getOperand(0); 15021 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 15022 DAG.getConstant(1, CmpOp0.getValueType())); 15023 15024 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 15025 if (CC == X86::COND_NE) 15026 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 15027 DL, OtherVal.getValueType(), OtherVal, 15028 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 15029 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 15030 DL, OtherVal.getValueType(), OtherVal, 15031 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 15032} 15033 15034/// PerformADDCombine - Do target-specific dag combines on integer adds. 15035static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 15036 const X86Subtarget *Subtarget) { 15037 EVT VT = N->getValueType(0); 15038 SDValue Op0 = N->getOperand(0); 15039 SDValue Op1 = N->getOperand(1); 15040 15041 // Try to synthesize horizontal adds from adds of shuffles. 15042 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15043 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15044 isHorizontalBinOp(Op0, Op1, true)) 15045 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 15046 15047 return OptimizeConditionalInDecrement(N, DAG); 15048} 15049 15050static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 15051 const X86Subtarget *Subtarget) { 15052 SDValue Op0 = N->getOperand(0); 15053 SDValue Op1 = N->getOperand(1); 15054 15055 // X86 can't encode an immediate LHS of a sub. See if we can push the 15056 // negation into a preceding instruction. 15057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 15058 // If the RHS of the sub is a XOR with one use and a constant, invert the 15059 // immediate. Then add one to the LHS of the sub so we can turn 15060 // X-Y -> X+~Y+1, saving one register. 15061 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 15062 isa<ConstantSDNode>(Op1.getOperand(1))) { 15063 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 15064 EVT VT = Op0.getValueType(); 15065 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 15066 Op1.getOperand(0), 15067 DAG.getConstant(~XorC, VT)); 15068 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 15069 DAG.getConstant(C->getAPIntValue()+1, VT)); 15070 } 15071 } 15072 15073 // Try to synthesize horizontal adds from adds of shuffles. 15074 EVT VT = N->getValueType(0); 15075 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15076 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15077 isHorizontalBinOp(Op0, Op1, true)) 15078 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15079 15080 return OptimizeConditionalInDecrement(N, DAG); 15081} 15082 15083SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15084 DAGCombinerInfo &DCI) const { 15085 SelectionDAG &DAG = DCI.DAG; 15086 switch (N->getOpcode()) { 15087 default: break; 15088 case ISD::EXTRACT_VECTOR_ELT: 15089 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15090 case ISD::VSELECT: 15091 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15092 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15093 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15094 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15095 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15096 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15097 case ISD::SHL: 15098 case ISD::SRA: 15099 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15100 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15101 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15102 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15103 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 15104 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15105 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15106 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15107 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15108 case X86ISD::FXOR: 15109 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15110 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15111 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15112 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15113 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); 15114 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15115 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15116 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15117 case X86ISD::SHUFP: // Handle all target specific shuffles 15118 case X86ISD::PALIGN: 15119 case X86ISD::UNPCKH: 15120 case X86ISD::UNPCKL: 15121 case X86ISD::MOVHLPS: 15122 case X86ISD::MOVLHPS: 15123 case X86ISD::PSHUFD: 15124 case X86ISD::PSHUFHW: 15125 case X86ISD::PSHUFLW: 15126 case X86ISD::MOVSS: 15127 case X86ISD::MOVSD: 15128 case X86ISD::VPERMILP: 15129 case X86ISD::VPERM2X128: 15130 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15131 } 15132 15133 return SDValue(); 15134} 15135 15136/// isTypeDesirableForOp - Return true if the target has native support for 15137/// the specified value type and it is 'desirable' to use the type for the 15138/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15139/// instruction encodings are longer and some i16 instructions are slow. 15140bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15141 if (!isTypeLegal(VT)) 15142 return false; 15143 if (VT != MVT::i16) 15144 return true; 15145 15146 switch (Opc) { 15147 default: 15148 return true; 15149 case ISD::LOAD: 15150 case ISD::SIGN_EXTEND: 15151 case ISD::ZERO_EXTEND: 15152 case ISD::ANY_EXTEND: 15153 case ISD::SHL: 15154 case ISD::SRL: 15155 case ISD::SUB: 15156 case ISD::ADD: 15157 case ISD::MUL: 15158 case ISD::AND: 15159 case ISD::OR: 15160 case ISD::XOR: 15161 return false; 15162 } 15163} 15164 15165/// IsDesirableToPromoteOp - This method query the target whether it is 15166/// beneficial for dag combiner to promote the specified node. If true, it 15167/// should return the desired promotion type by reference. 15168bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15169 EVT VT = Op.getValueType(); 15170 if (VT != MVT::i16) 15171 return false; 15172 15173 bool Promote = false; 15174 bool Commute = false; 15175 switch (Op.getOpcode()) { 15176 default: break; 15177 case ISD::LOAD: { 15178 LoadSDNode *LD = cast<LoadSDNode>(Op); 15179 // If the non-extending load has a single use and it's not live out, then it 15180 // might be folded. 15181 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15182 Op.hasOneUse()*/) { 15183 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15184 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15185 // The only case where we'd want to promote LOAD (rather then it being 15186 // promoted as an operand is when it's only use is liveout. 15187 if (UI->getOpcode() != ISD::CopyToReg) 15188 return false; 15189 } 15190 } 15191 Promote = true; 15192 break; 15193 } 15194 case ISD::SIGN_EXTEND: 15195 case ISD::ZERO_EXTEND: 15196 case ISD::ANY_EXTEND: 15197 Promote = true; 15198 break; 15199 case ISD::SHL: 15200 case ISD::SRL: { 15201 SDValue N0 = Op.getOperand(0); 15202 // Look out for (store (shl (load), x)). 15203 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15204 return false; 15205 Promote = true; 15206 break; 15207 } 15208 case ISD::ADD: 15209 case ISD::MUL: 15210 case ISD::AND: 15211 case ISD::OR: 15212 case ISD::XOR: 15213 Commute = true; 15214 // fallthrough 15215 case ISD::SUB: { 15216 SDValue N0 = Op.getOperand(0); 15217 SDValue N1 = Op.getOperand(1); 15218 if (!Commute && MayFoldLoad(N1)) 15219 return false; 15220 // Avoid disabling potential load folding opportunities. 15221 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15222 return false; 15223 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15224 return false; 15225 Promote = true; 15226 } 15227 } 15228 15229 PVT = MVT::i32; 15230 return Promote; 15231} 15232 15233//===----------------------------------------------------------------------===// 15234// X86 Inline Assembly Support 15235//===----------------------------------------------------------------------===// 15236 15237namespace { 15238 // Helper to match a string separated by whitespace. 15239 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15240 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15241 15242 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15243 StringRef piece(*args[i]); 15244 if (!s.startswith(piece)) // Check if the piece matches. 15245 return false; 15246 15247 s = s.substr(piece.size()); 15248 StringRef::size_type pos = s.find_first_not_of(" \t"); 15249 if (pos == 0) // We matched a prefix. 15250 return false; 15251 15252 s = s.substr(pos); 15253 } 15254 15255 return s.empty(); 15256 } 15257 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15258} 15259 15260bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15261 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15262 15263 std::string AsmStr = IA->getAsmString(); 15264 15265 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15266 if (!Ty || Ty->getBitWidth() % 16 != 0) 15267 return false; 15268 15269 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15270 SmallVector<StringRef, 4> AsmPieces; 15271 SplitString(AsmStr, AsmPieces, ";\n"); 15272 15273 switch (AsmPieces.size()) { 15274 default: return false; 15275 case 1: 15276 // FIXME: this should verify that we are targeting a 486 or better. If not, 15277 // we will turn this bswap into something that will be lowered to logical 15278 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15279 // lower so don't worry about this. 15280 // bswap $0 15281 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15282 matchAsm(AsmPieces[0], "bswapl", "$0") || 15283 matchAsm(AsmPieces[0], "bswapq", "$0") || 15284 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15285 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15286 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15287 // No need to check constraints, nothing other than the equivalent of 15288 // "=r,0" would be valid here. 15289 return IntrinsicLowering::LowerToByteSwap(CI); 15290 } 15291 15292 // rorw $$8, ${0:w} --> llvm.bswap.i16 15293 if (CI->getType()->isIntegerTy(16) && 15294 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15295 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15296 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15297 AsmPieces.clear(); 15298 const std::string &ConstraintsStr = IA->getConstraintString(); 15299 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15300 std::sort(AsmPieces.begin(), AsmPieces.end()); 15301 if (AsmPieces.size() == 4 && 15302 AsmPieces[0] == "~{cc}" && 15303 AsmPieces[1] == "~{dirflag}" && 15304 AsmPieces[2] == "~{flags}" && 15305 AsmPieces[3] == "~{fpsr}") 15306 return IntrinsicLowering::LowerToByteSwap(CI); 15307 } 15308 break; 15309 case 3: 15310 if (CI->getType()->isIntegerTy(32) && 15311 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15312 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15313 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15314 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15315 AsmPieces.clear(); 15316 const std::string &ConstraintsStr = IA->getConstraintString(); 15317 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15318 std::sort(AsmPieces.begin(), AsmPieces.end()); 15319 if (AsmPieces.size() == 4 && 15320 AsmPieces[0] == "~{cc}" && 15321 AsmPieces[1] == "~{dirflag}" && 15322 AsmPieces[2] == "~{flags}" && 15323 AsmPieces[3] == "~{fpsr}") 15324 return IntrinsicLowering::LowerToByteSwap(CI); 15325 } 15326 15327 if (CI->getType()->isIntegerTy(64)) { 15328 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15329 if (Constraints.size() >= 2 && 15330 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15331 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15332 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15333 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15334 matchAsm(AsmPieces[1], "bswap", "%edx") && 15335 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15336 return IntrinsicLowering::LowerToByteSwap(CI); 15337 } 15338 } 15339 break; 15340 } 15341 return false; 15342} 15343 15344 15345 15346/// getConstraintType - Given a constraint letter, return the type of 15347/// constraint it is for this target. 15348X86TargetLowering::ConstraintType 15349X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15350 if (Constraint.size() == 1) { 15351 switch (Constraint[0]) { 15352 case 'R': 15353 case 'q': 15354 case 'Q': 15355 case 'f': 15356 case 't': 15357 case 'u': 15358 case 'y': 15359 case 'x': 15360 case 'Y': 15361 case 'l': 15362 return C_RegisterClass; 15363 case 'a': 15364 case 'b': 15365 case 'c': 15366 case 'd': 15367 case 'S': 15368 case 'D': 15369 case 'A': 15370 return C_Register; 15371 case 'I': 15372 case 'J': 15373 case 'K': 15374 case 'L': 15375 case 'M': 15376 case 'N': 15377 case 'G': 15378 case 'C': 15379 case 'e': 15380 case 'Z': 15381 return C_Other; 15382 default: 15383 break; 15384 } 15385 } 15386 return TargetLowering::getConstraintType(Constraint); 15387} 15388 15389/// Examine constraint type and operand type and determine a weight value. 15390/// This object must already have been set up with the operand type 15391/// and the current alternative constraint selected. 15392TargetLowering::ConstraintWeight 15393 X86TargetLowering::getSingleConstraintMatchWeight( 15394 AsmOperandInfo &info, const char *constraint) const { 15395 ConstraintWeight weight = CW_Invalid; 15396 Value *CallOperandVal = info.CallOperandVal; 15397 // If we don't have a value, we can't do a match, 15398 // but allow it at the lowest weight. 15399 if (CallOperandVal == NULL) 15400 return CW_Default; 15401 Type *type = CallOperandVal->getType(); 15402 // Look at the constraint type. 15403 switch (*constraint) { 15404 default: 15405 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15406 case 'R': 15407 case 'q': 15408 case 'Q': 15409 case 'a': 15410 case 'b': 15411 case 'c': 15412 case 'd': 15413 case 'S': 15414 case 'D': 15415 case 'A': 15416 if (CallOperandVal->getType()->isIntegerTy()) 15417 weight = CW_SpecificReg; 15418 break; 15419 case 'f': 15420 case 't': 15421 case 'u': 15422 if (type->isFloatingPointTy()) 15423 weight = CW_SpecificReg; 15424 break; 15425 case 'y': 15426 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15427 weight = CW_SpecificReg; 15428 break; 15429 case 'x': 15430 case 'Y': 15431 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15432 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15433 weight = CW_Register; 15434 break; 15435 case 'I': 15436 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15437 if (C->getZExtValue() <= 31) 15438 weight = CW_Constant; 15439 } 15440 break; 15441 case 'J': 15442 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15443 if (C->getZExtValue() <= 63) 15444 weight = CW_Constant; 15445 } 15446 break; 15447 case 'K': 15448 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15449 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15450 weight = CW_Constant; 15451 } 15452 break; 15453 case 'L': 15454 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15455 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15456 weight = CW_Constant; 15457 } 15458 break; 15459 case 'M': 15460 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15461 if (C->getZExtValue() <= 3) 15462 weight = CW_Constant; 15463 } 15464 break; 15465 case 'N': 15466 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15467 if (C->getZExtValue() <= 0xff) 15468 weight = CW_Constant; 15469 } 15470 break; 15471 case 'G': 15472 case 'C': 15473 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15474 weight = CW_Constant; 15475 } 15476 break; 15477 case 'e': 15478 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15479 if ((C->getSExtValue() >= -0x80000000LL) && 15480 (C->getSExtValue() <= 0x7fffffffLL)) 15481 weight = CW_Constant; 15482 } 15483 break; 15484 case 'Z': 15485 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15486 if (C->getZExtValue() <= 0xffffffff) 15487 weight = CW_Constant; 15488 } 15489 break; 15490 } 15491 return weight; 15492} 15493 15494/// LowerXConstraint - try to replace an X constraint, which matches anything, 15495/// with another that has more specific requirements based on the type of the 15496/// corresponding operand. 15497const char *X86TargetLowering:: 15498LowerXConstraint(EVT ConstraintVT) const { 15499 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15500 // 'f' like normal targets. 15501 if (ConstraintVT.isFloatingPoint()) { 15502 if (Subtarget->hasSSE2()) 15503 return "Y"; 15504 if (Subtarget->hasSSE1()) 15505 return "x"; 15506 } 15507 15508 return TargetLowering::LowerXConstraint(ConstraintVT); 15509} 15510 15511/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15512/// vector. If it is invalid, don't add anything to Ops. 15513void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15514 std::string &Constraint, 15515 std::vector<SDValue>&Ops, 15516 SelectionDAG &DAG) const { 15517 SDValue Result(0, 0); 15518 15519 // Only support length 1 constraints for now. 15520 if (Constraint.length() > 1) return; 15521 15522 char ConstraintLetter = Constraint[0]; 15523 switch (ConstraintLetter) { 15524 default: break; 15525 case 'I': 15526 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15527 if (C->getZExtValue() <= 31) { 15528 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15529 break; 15530 } 15531 } 15532 return; 15533 case 'J': 15534 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15535 if (C->getZExtValue() <= 63) { 15536 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15537 break; 15538 } 15539 } 15540 return; 15541 case 'K': 15542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15543 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15544 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15545 break; 15546 } 15547 } 15548 return; 15549 case 'N': 15550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15551 if (C->getZExtValue() <= 255) { 15552 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15553 break; 15554 } 15555 } 15556 return; 15557 case 'e': { 15558 // 32-bit signed value 15559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15560 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15561 C->getSExtValue())) { 15562 // Widen to 64 bits here to get it sign extended. 15563 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15564 break; 15565 } 15566 // FIXME gcc accepts some relocatable values here too, but only in certain 15567 // memory models; it's complicated. 15568 } 15569 return; 15570 } 15571 case 'Z': { 15572 // 32-bit unsigned value 15573 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15574 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15575 C->getZExtValue())) { 15576 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15577 break; 15578 } 15579 } 15580 // FIXME gcc accepts some relocatable values here too, but only in certain 15581 // memory models; it's complicated. 15582 return; 15583 } 15584 case 'i': { 15585 // Literal immediates are always ok. 15586 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15587 // Widen to 64 bits here to get it sign extended. 15588 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15589 break; 15590 } 15591 15592 // In any sort of PIC mode addresses need to be computed at runtime by 15593 // adding in a register or some sort of table lookup. These can't 15594 // be used as immediates. 15595 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15596 return; 15597 15598 // If we are in non-pic codegen mode, we allow the address of a global (with 15599 // an optional displacement) to be used with 'i'. 15600 GlobalAddressSDNode *GA = 0; 15601 int64_t Offset = 0; 15602 15603 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15604 while (1) { 15605 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15606 Offset += GA->getOffset(); 15607 break; 15608 } else if (Op.getOpcode() == ISD::ADD) { 15609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15610 Offset += C->getZExtValue(); 15611 Op = Op.getOperand(0); 15612 continue; 15613 } 15614 } else if (Op.getOpcode() == ISD::SUB) { 15615 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15616 Offset += -C->getZExtValue(); 15617 Op = Op.getOperand(0); 15618 continue; 15619 } 15620 } 15621 15622 // Otherwise, this isn't something we can handle, reject it. 15623 return; 15624 } 15625 15626 const GlobalValue *GV = GA->getGlobal(); 15627 // If we require an extra load to get this address, as in PIC mode, we 15628 // can't accept it. 15629 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15630 getTargetMachine()))) 15631 return; 15632 15633 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15634 GA->getValueType(0), Offset); 15635 break; 15636 } 15637 } 15638 15639 if (Result.getNode()) { 15640 Ops.push_back(Result); 15641 return; 15642 } 15643 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15644} 15645 15646std::pair<unsigned, const TargetRegisterClass*> 15647X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15648 EVT VT) const { 15649 // First, see if this is a constraint that directly corresponds to an LLVM 15650 // register class. 15651 if (Constraint.size() == 1) { 15652 // GCC Constraint Letters 15653 switch (Constraint[0]) { 15654 default: break; 15655 // TODO: Slight differences here in allocation order and leaving 15656 // RIP in the class. Do they matter any more here than they do 15657 // in the normal allocation? 15658 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15659 if (Subtarget->is64Bit()) { 15660 if (VT == MVT::i32 || VT == MVT::f32) 15661 return std::make_pair(0U, X86::GR32RegisterClass); 15662 else if (VT == MVT::i16) 15663 return std::make_pair(0U, X86::GR16RegisterClass); 15664 else if (VT == MVT::i8 || VT == MVT::i1) 15665 return std::make_pair(0U, X86::GR8RegisterClass); 15666 else if (VT == MVT::i64 || VT == MVT::f64) 15667 return std::make_pair(0U, X86::GR64RegisterClass); 15668 break; 15669 } 15670 // 32-bit fallthrough 15671 case 'Q': // Q_REGS 15672 if (VT == MVT::i32 || VT == MVT::f32) 15673 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15674 else if (VT == MVT::i16) 15675 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15676 else if (VT == MVT::i8 || VT == MVT::i1) 15677 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15678 else if (VT == MVT::i64) 15679 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15680 break; 15681 case 'r': // GENERAL_REGS 15682 case 'l': // INDEX_REGS 15683 if (VT == MVT::i8 || VT == MVT::i1) 15684 return std::make_pair(0U, X86::GR8RegisterClass); 15685 if (VT == MVT::i16) 15686 return std::make_pair(0U, X86::GR16RegisterClass); 15687 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15688 return std::make_pair(0U, X86::GR32RegisterClass); 15689 return std::make_pair(0U, X86::GR64RegisterClass); 15690 case 'R': // LEGACY_REGS 15691 if (VT == MVT::i8 || VT == MVT::i1) 15692 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15693 if (VT == MVT::i16) 15694 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15695 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15696 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15697 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15698 case 'f': // FP Stack registers. 15699 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15700 // value to the correct fpstack register class. 15701 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15702 return std::make_pair(0U, X86::RFP32RegisterClass); 15703 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15704 return std::make_pair(0U, X86::RFP64RegisterClass); 15705 return std::make_pair(0U, X86::RFP80RegisterClass); 15706 case 'y': // MMX_REGS if MMX allowed. 15707 if (!Subtarget->hasMMX()) break; 15708 return std::make_pair(0U, X86::VR64RegisterClass); 15709 case 'Y': // SSE_REGS if SSE2 allowed 15710 if (!Subtarget->hasSSE2()) break; 15711 // FALL THROUGH. 15712 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15713 if (!Subtarget->hasSSE1()) break; 15714 15715 switch (VT.getSimpleVT().SimpleTy) { 15716 default: break; 15717 // Scalar SSE types. 15718 case MVT::f32: 15719 case MVT::i32: 15720 return std::make_pair(0U, X86::FR32RegisterClass); 15721 case MVT::f64: 15722 case MVT::i64: 15723 return std::make_pair(0U, X86::FR64RegisterClass); 15724 // Vector types. 15725 case MVT::v16i8: 15726 case MVT::v8i16: 15727 case MVT::v4i32: 15728 case MVT::v2i64: 15729 case MVT::v4f32: 15730 case MVT::v2f64: 15731 return std::make_pair(0U, X86::VR128RegisterClass); 15732 // AVX types. 15733 case MVT::v32i8: 15734 case MVT::v16i16: 15735 case MVT::v8i32: 15736 case MVT::v4i64: 15737 case MVT::v8f32: 15738 case MVT::v4f64: 15739 return std::make_pair(0U, X86::VR256RegisterClass); 15740 15741 } 15742 break; 15743 } 15744 } 15745 15746 // Use the default implementation in TargetLowering to convert the register 15747 // constraint into a member of a register class. 15748 std::pair<unsigned, const TargetRegisterClass*> Res; 15749 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15750 15751 // Not found as a standard register? 15752 if (Res.second == 0) { 15753 // Map st(0) -> st(7) -> ST0 15754 if (Constraint.size() == 7 && Constraint[0] == '{' && 15755 tolower(Constraint[1]) == 's' && 15756 tolower(Constraint[2]) == 't' && 15757 Constraint[3] == '(' && 15758 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15759 Constraint[5] == ')' && 15760 Constraint[6] == '}') { 15761 15762 Res.first = X86::ST0+Constraint[4]-'0'; 15763 Res.second = X86::RFP80RegisterClass; 15764 return Res; 15765 } 15766 15767 // GCC allows "st(0)" to be called just plain "st". 15768 if (StringRef("{st}").equals_lower(Constraint)) { 15769 Res.first = X86::ST0; 15770 Res.second = X86::RFP80RegisterClass; 15771 return Res; 15772 } 15773 15774 // flags -> EFLAGS 15775 if (StringRef("{flags}").equals_lower(Constraint)) { 15776 Res.first = X86::EFLAGS; 15777 Res.second = X86::CCRRegisterClass; 15778 return Res; 15779 } 15780 15781 // 'A' means EAX + EDX. 15782 if (Constraint == "A") { 15783 Res.first = X86::EAX; 15784 Res.second = X86::GR32_ADRegisterClass; 15785 return Res; 15786 } 15787 return Res; 15788 } 15789 15790 // Otherwise, check to see if this is a register class of the wrong value 15791 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15792 // turn into {ax},{dx}. 15793 if (Res.second->hasType(VT)) 15794 return Res; // Correct type already, nothing to do. 15795 15796 // All of the single-register GCC register classes map their values onto 15797 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15798 // really want an 8-bit or 32-bit register, map to the appropriate register 15799 // class and return the appropriate register. 15800 if (Res.second == X86::GR16RegisterClass) { 15801 if (VT == MVT::i8) { 15802 unsigned DestReg = 0; 15803 switch (Res.first) { 15804 default: break; 15805 case X86::AX: DestReg = X86::AL; break; 15806 case X86::DX: DestReg = X86::DL; break; 15807 case X86::CX: DestReg = X86::CL; break; 15808 case X86::BX: DestReg = X86::BL; break; 15809 } 15810 if (DestReg) { 15811 Res.first = DestReg; 15812 Res.second = X86::GR8RegisterClass; 15813 } 15814 } else if (VT == MVT::i32) { 15815 unsigned DestReg = 0; 15816 switch (Res.first) { 15817 default: break; 15818 case X86::AX: DestReg = X86::EAX; break; 15819 case X86::DX: DestReg = X86::EDX; break; 15820 case X86::CX: DestReg = X86::ECX; break; 15821 case X86::BX: DestReg = X86::EBX; break; 15822 case X86::SI: DestReg = X86::ESI; break; 15823 case X86::DI: DestReg = X86::EDI; break; 15824 case X86::BP: DestReg = X86::EBP; break; 15825 case X86::SP: DestReg = X86::ESP; break; 15826 } 15827 if (DestReg) { 15828 Res.first = DestReg; 15829 Res.second = X86::GR32RegisterClass; 15830 } 15831 } else if (VT == MVT::i64) { 15832 unsigned DestReg = 0; 15833 switch (Res.first) { 15834 default: break; 15835 case X86::AX: DestReg = X86::RAX; break; 15836 case X86::DX: DestReg = X86::RDX; break; 15837 case X86::CX: DestReg = X86::RCX; break; 15838 case X86::BX: DestReg = X86::RBX; break; 15839 case X86::SI: DestReg = X86::RSI; break; 15840 case X86::DI: DestReg = X86::RDI; break; 15841 case X86::BP: DestReg = X86::RBP; break; 15842 case X86::SP: DestReg = X86::RSP; break; 15843 } 15844 if (DestReg) { 15845 Res.first = DestReg; 15846 Res.second = X86::GR64RegisterClass; 15847 } 15848 } 15849 } else if (Res.second == X86::FR32RegisterClass || 15850 Res.second == X86::FR64RegisterClass || 15851 Res.second == X86::VR128RegisterClass) { 15852 // Handle references to XMM physical registers that got mapped into the 15853 // wrong class. This can happen with constraints like {xmm0} where the 15854 // target independent register mapper will just pick the first match it can 15855 // find, ignoring the required type. 15856 if (VT == MVT::f32) 15857 Res.second = X86::FR32RegisterClass; 15858 else if (VT == MVT::f64) 15859 Res.second = X86::FR64RegisterClass; 15860 else if (X86::VR128RegisterClass->hasType(VT)) 15861 Res.second = X86::VR128RegisterClass; 15862 } 15863 15864 return Res; 15865} 15866