X86ISelLowering.cpp revision 2d496897934adfc0e3e1563dd64d9a7122971e22
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VectorExtras.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/Debug.h" 49#include "llvm/Support/Dwarf.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/MathExtras.h" 52#include "llvm/Support/raw_ostream.h" 53#include "llvm/Target/TargetOptions.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasXMMInt(); 172 X86ScalarSSEf32 = Subtarget->hasXMM(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 185 186 // For 64-bit since we have so many registers use the ILP scheduler, for 187 // 32-bit code use the register pressure specific scheduling. 188 if (Subtarget->is64Bit()) 189 setSchedulingPreference(Sched::ILP); 190 else 191 setSchedulingPreference(Sched::RegPressure); 192 setStackPointerRegisterToSaveRestore(X86StackPtr); 193 194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 195 // Setup Windows compiler runtime calls. 196 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 198 setLibcallName(RTLIB::SREM_I64, "_allrem"); 199 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 200 setLibcallName(RTLIB::MUL_I64, "_allmul"); 201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 210 } 211 212 if (Subtarget->isTargetDarwin()) { 213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 214 setUseUnderscoreSetJmp(false); 215 setUseUnderscoreLongJmp(false); 216 } else if (Subtarget->isTargetMingw()) { 217 // MS runtime is weird: it exports _setjmp, but longjmp! 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(false); 220 } else { 221 setUseUnderscoreSetJmp(true); 222 setUseUnderscoreLongJmp(true); 223 } 224 225 // Set up the register classes. 226 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 227 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 228 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 229 if (Subtarget->is64Bit()) 230 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 231 232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 233 234 // We don't accept any truncstore of integer registers. 235 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 236 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 240 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 241 242 // SETOEQ and SETUNE require checking two conditions. 243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 249 250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 251 // operation. 252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 255 256 if (Subtarget->is64Bit()) { 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 259 } else if (!UseSoftFloat) { 260 // We have an algorithm for SSE2->double, and we turn this into a 261 // 64-bit FILD followed by conditional FADD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 263 // We have an algorithm for SSE2, and we turn this into a 64-bit 264 // FILD for other targets. 265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 266 } 267 268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 269 // this operation. 270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 272 273 if (!UseSoftFloat) { 274 // SSE has no i16 to fp conversion, only i32 275 if (X86ScalarSSEf32) { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 // f32 and f64 cases are Legal, f80 case is not 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } else { 280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 282 } 283 } else { 284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 286 } 287 288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 289 // are Legal, f80 is custom lowered. 290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 292 293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 294 // this operation. 295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 297 298 if (X86ScalarSSEf32) { 299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 300 // f32 and f64 cases are Legal, f80 case is not 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } else { 303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 305 } 306 307 // Handle FP_TO_UINT by promoting the destination to a larger signed 308 // conversion. 309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 312 313 if (Subtarget->is64Bit()) { 314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 316 } else if (!UseSoftFloat) { 317 // Since AVX is a superset of SSE3, only check for SSE here. 318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 319 // Expand FP_TO_UINT into a select. 320 // FIXME: We would like to use a Custom expander here eventually to do 321 // the optimal thing for SSE vs. the default expansion in the legalizer. 322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 323 else 324 // With SSE3 we can use fisttpll to convert to a signed i64; without 325 // SSE, we're stuck with a fistpll. 326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 327 } 328 329 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 330 if (!X86ScalarSSEf64) { 331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 333 if (Subtarget->is64Bit()) { 334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 335 // Without SSE, i64->f64 goes through memory. 336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 337 } 338 } 339 340 // Scalar integer divide and remainder are lowered to use operations that 341 // produce two results, to match the available instructions. This exposes 342 // the two-result form to trivial CSE, which is able to combine x/y and x%y 343 // into a single instruction. 344 // 345 // Scalar integer multiply-high is also lowered to use two-result 346 // operations, to match the available instructions. However, plain multiply 347 // (low) operations are left as Legal, as there are single-result 348 // instructions for this in x86. Using the two-result multiply instructions 349 // when both high and low results are needed must be arranged by dagcombine. 350 for (unsigned i = 0, e = 4; i != e; ++i) { 351 MVT VT = IntVTs[i]; 352 setOperationAction(ISD::MULHS, VT, Expand); 353 setOperationAction(ISD::MULHU, VT, Expand); 354 setOperationAction(ISD::SDIV, VT, Expand); 355 setOperationAction(ISD::UDIV, VT, Expand); 356 setOperationAction(ISD::SREM, VT, Expand); 357 setOperationAction(ISD::UREM, VT, Expand); 358 359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 360 setOperationAction(ISD::ADDC, VT, Custom); 361 setOperationAction(ISD::ADDE, VT, Custom); 362 setOperationAction(ISD::SUBC, VT, Custom); 363 setOperationAction(ISD::SUBE, VT, Custom); 364 } 365 366 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 367 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 368 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 370 if (Subtarget->is64Bit()) 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 376 setOperationAction(ISD::FREM , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f64 , Expand); 378 setOperationAction(ISD::FREM , MVT::f80 , Expand); 379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 380 381 if (Subtarget->hasBMI()) { 382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 383 } else { 384 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 385 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 386 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 387 if (Subtarget->is64Bit()) 388 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 389 } 390 391 if (Subtarget->hasLZCNT()) { 392 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 393 } else { 394 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 395 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 396 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 397 if (Subtarget->is64Bit()) 398 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 399 } 400 401 if (Subtarget->hasPOPCNT()) { 402 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 403 } else { 404 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 405 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 406 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 407 if (Subtarget->is64Bit()) 408 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 409 } 410 411 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 412 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 413 414 // These should be promoted to a larger select which is supported. 415 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 416 // X86 wants to expand cmov itself. 417 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 418 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 419 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 420 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 421 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 422 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 423 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 424 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 425 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 426 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 427 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 428 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 429 if (Subtarget->is64Bit()) { 430 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 431 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 432 } 433 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 434 435 // Darwin ABI issue. 436 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 437 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 438 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 439 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 440 if (Subtarget->is64Bit()) 441 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 442 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 443 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 444 if (Subtarget->is64Bit()) { 445 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 446 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 447 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 448 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 449 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 450 } 451 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 452 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 453 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 454 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 455 if (Subtarget->is64Bit()) { 456 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 457 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 458 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 459 } 460 461 if (Subtarget->hasXMM()) 462 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 463 464 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 465 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 466 467 // On X86 and X86-64, atomic operations are lowered to locked instructions. 468 // Locked instructions, in turn, have implicit fence semantics (all memory 469 // operations are flushed before issuing the locked instruction, and they 470 // are not buffered), so we can fold away the common pattern of 471 // fence-atomic-fence. 472 setShouldFoldAtomicFences(true); 473 474 // Expand certain atomics 475 for (unsigned i = 0, e = 4; i != e; ++i) { 476 MVT VT = IntVTs[i]; 477 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 478 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 479 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 480 } 481 482 if (!Subtarget->is64Bit()) { 483 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 484 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 485 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 486 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 487 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 488 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 489 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 490 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 491 } 492 493 if (Subtarget->hasCmpxchg16b()) { 494 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 495 } 496 497 // FIXME - use subtarget debug flags 498 if (!Subtarget->isTargetDarwin() && 499 !Subtarget->isTargetELF() && 500 !Subtarget->isTargetCygMing()) { 501 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 502 } 503 504 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 505 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 506 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 507 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 508 if (Subtarget->is64Bit()) { 509 setExceptionPointerRegister(X86::RAX); 510 setExceptionSelectorRegister(X86::RDX); 511 } else { 512 setExceptionPointerRegister(X86::EAX); 513 setExceptionSelectorRegister(X86::EDX); 514 } 515 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 516 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 517 518 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 519 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 520 521 setOperationAction(ISD::TRAP, MVT::Other, Legal); 522 523 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 524 setOperationAction(ISD::VASTART , MVT::Other, Custom); 525 setOperationAction(ISD::VAEND , MVT::Other, Expand); 526 if (Subtarget->is64Bit()) { 527 setOperationAction(ISD::VAARG , MVT::Other, Custom); 528 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 529 } else { 530 setOperationAction(ISD::VAARG , MVT::Other, Expand); 531 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 532 } 533 534 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 535 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 536 537 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 538 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 539 MVT::i64 : MVT::i32, Custom); 540 else if (EnableSegmentedStacks) 541 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 542 MVT::i64 : MVT::i32, Custom); 543 else 544 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 545 MVT::i64 : MVT::i32, Expand); 546 547 if (!UseSoftFloat && X86ScalarSSEf64) { 548 // f32 and f64 use SSE. 549 // Set up the FP register classes. 550 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 551 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 552 553 // Use ANDPD to simulate FABS. 554 setOperationAction(ISD::FABS , MVT::f64, Custom); 555 setOperationAction(ISD::FABS , MVT::f32, Custom); 556 557 // Use XORP to simulate FNEG. 558 setOperationAction(ISD::FNEG , MVT::f64, Custom); 559 setOperationAction(ISD::FNEG , MVT::f32, Custom); 560 561 // Use ANDPD and ORPD to simulate FCOPYSIGN. 562 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 563 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 564 565 // Lower this to FGETSIGNx86 plus an AND. 566 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 567 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 568 569 // We don't support sin/cos/fmod 570 setOperationAction(ISD::FSIN , MVT::f64, Expand); 571 setOperationAction(ISD::FCOS , MVT::f64, Expand); 572 setOperationAction(ISD::FSIN , MVT::f32, Expand); 573 setOperationAction(ISD::FCOS , MVT::f32, Expand); 574 575 // Expand FP immediates into loads from the stack, except for the special 576 // cases we handle. 577 addLegalFPImmediate(APFloat(+0.0)); // xorpd 578 addLegalFPImmediate(APFloat(+0.0f)); // xorps 579 } else if (!UseSoftFloat && X86ScalarSSEf32) { 580 // Use SSE for f32, x87 for f64. 581 // Set up the FP register classes. 582 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 583 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 584 585 // Use ANDPS to simulate FABS. 586 setOperationAction(ISD::FABS , MVT::f32, Custom); 587 588 // Use XORP to simulate FNEG. 589 setOperationAction(ISD::FNEG , MVT::f32, Custom); 590 591 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 592 593 // Use ANDPS and ORPS to simulate FCOPYSIGN. 594 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 595 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 596 597 // We don't support sin/cos/fmod 598 setOperationAction(ISD::FSIN , MVT::f32, Expand); 599 setOperationAction(ISD::FCOS , MVT::f32, Expand); 600 601 // Special cases we handle for FP constants. 602 addLegalFPImmediate(APFloat(+0.0f)); // xorps 603 addLegalFPImmediate(APFloat(+0.0)); // FLD0 604 addLegalFPImmediate(APFloat(+1.0)); // FLD1 605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 607 608 if (!UnsafeFPMath) { 609 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 610 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 611 } 612 } else if (!UseSoftFloat) { 613 // f32 and f64 in x87. 614 // Set up the FP register classes. 615 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 616 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 617 618 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 619 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 620 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 622 623 if (!UnsafeFPMath) { 624 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 625 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 626 } 627 addLegalFPImmediate(APFloat(+0.0)); // FLD0 628 addLegalFPImmediate(APFloat(+1.0)); // FLD1 629 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 630 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 631 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 632 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 633 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 634 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 635 } 636 637 // We don't support FMA. 638 setOperationAction(ISD::FMA, MVT::f64, Expand); 639 setOperationAction(ISD::FMA, MVT::f32, Expand); 640 641 // Long double always uses X87. 642 if (!UseSoftFloat) { 643 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 644 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 645 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 646 { 647 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 648 addLegalFPImmediate(TmpFlt); // FLD0 649 TmpFlt.changeSign(); 650 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 651 652 bool ignored; 653 APFloat TmpFlt2(+1.0); 654 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 655 &ignored); 656 addLegalFPImmediate(TmpFlt2); // FLD1 657 TmpFlt2.changeSign(); 658 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 659 } 660 661 if (!UnsafeFPMath) { 662 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 663 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 664 } 665 666 setOperationAction(ISD::FMA, MVT::f80, Expand); 667 } 668 669 // Always use a library call for pow. 670 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 671 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 672 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 673 674 setOperationAction(ISD::FLOG, MVT::f80, Expand); 675 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 676 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 677 setOperationAction(ISD::FEXP, MVT::f80, Expand); 678 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 679 680 // First set operation action for all vector types to either promote 681 // (for widening) or expand (for scalarization). Then we will selectively 682 // turn on ones that can be effectively codegen'd. 683 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 684 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 685 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 686 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 692 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 700 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 702 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 703 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 735 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 740 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 741 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 742 setTruncStoreAction((MVT::SimpleValueType)VT, 743 (MVT::SimpleValueType)InnerVT, Expand); 744 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 745 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 746 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 747 } 748 749 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 750 // with -msoft-float, disable use of MMX as well. 751 if (!UseSoftFloat && Subtarget->hasMMX()) { 752 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 753 // No operations on x86mmx supported, everything uses intrinsics. 754 } 755 756 // MMX-sized vectors (other than x86mmx) are expected to be expanded 757 // into smaller operations. 758 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 759 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 760 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 761 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 762 setOperationAction(ISD::AND, MVT::v8i8, Expand); 763 setOperationAction(ISD::AND, MVT::v4i16, Expand); 764 setOperationAction(ISD::AND, MVT::v2i32, Expand); 765 setOperationAction(ISD::AND, MVT::v1i64, Expand); 766 setOperationAction(ISD::OR, MVT::v8i8, Expand); 767 setOperationAction(ISD::OR, MVT::v4i16, Expand); 768 setOperationAction(ISD::OR, MVT::v2i32, Expand); 769 setOperationAction(ISD::OR, MVT::v1i64, Expand); 770 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 771 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 772 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 773 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 774 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 779 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 780 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 781 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 782 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 783 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 784 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 785 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 786 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 787 788 if (!UseSoftFloat && Subtarget->hasXMM()) { 789 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 790 791 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 792 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 793 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 794 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 795 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 796 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 797 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 798 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 799 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 800 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 801 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 802 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 803 } 804 805 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 806 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 807 808 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 809 // registers cannot be used even for integer operations. 810 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 811 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 812 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 813 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 814 815 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 816 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 817 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 818 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 819 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 820 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 821 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 822 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 823 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 824 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 825 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 831 832 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 833 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 834 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 835 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 836 837 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 842 843 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 848 849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 850 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 851 EVT VT = (MVT::SimpleValueType)i; 852 // Do not attempt to custom lower non-power-of-2 vectors 853 if (!isPowerOf2_32(VT.getVectorNumElements())) 854 continue; 855 // Do not attempt to custom lower non-128-bit vectors 856 if (!VT.is128BitVector()) 857 continue; 858 setOperationAction(ISD::BUILD_VECTOR, 859 VT.getSimpleVT().SimpleTy, Custom); 860 setOperationAction(ISD::VECTOR_SHUFFLE, 861 VT.getSimpleVT().SimpleTy, Custom); 862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 863 VT.getSimpleVT().SimpleTy, Custom); 864 } 865 866 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 867 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 868 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 871 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 872 873 if (Subtarget->is64Bit()) { 874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 876 } 877 878 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 879 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 880 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 881 EVT VT = SVT; 882 883 // Do not attempt to promote non-128-bit vectors 884 if (!VT.is128BitVector()) 885 continue; 886 887 setOperationAction(ISD::AND, SVT, Promote); 888 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 889 setOperationAction(ISD::OR, SVT, Promote); 890 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 891 setOperationAction(ISD::XOR, SVT, Promote); 892 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 893 setOperationAction(ISD::LOAD, SVT, Promote); 894 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 895 setOperationAction(ISD::SELECT, SVT, Promote); 896 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 897 } 898 899 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 900 901 // Custom lower v2i64 and v2f64 selects. 902 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 903 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 904 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 905 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 906 907 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 908 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 909 } 910 911 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 912 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 913 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 914 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 915 setOperationAction(ISD::FRINT, MVT::f32, Legal); 916 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 917 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 918 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 919 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 920 setOperationAction(ISD::FRINT, MVT::f64, Legal); 921 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 922 923 // FIXME: Do we need to handle scalar-to-vector here? 924 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 925 926 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 927 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 928 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 929 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 930 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 931 932 // i8 and i16 vectors are custom , because the source register and source 933 // source memory operand types are not the same width. f32 vectors are 934 // custom since the immediate controlling the insert encodes additional 935 // information. 936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 937 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 938 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 939 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 940 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 945 946 // FIXME: these should be Legal but thats only for the case where 947 // the index is constant. For now custom expand to deal with that 948 if (Subtarget->is64Bit()) { 949 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 951 } 952 } 953 954 if (Subtarget->hasXMMInt()) { 955 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 956 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 957 958 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 959 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 960 961 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 962 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 963 964 if (Subtarget->hasAVX2()) { 965 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 966 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 967 968 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 969 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 970 971 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 972 } else { 973 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 974 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 975 976 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 977 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 978 979 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 980 } 981 } 982 983 if (Subtarget->hasSSE42() || Subtarget->hasAVX()) 984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 985 986 if (!UseSoftFloat && Subtarget->hasAVX()) { 987 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 988 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 989 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 990 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 991 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 992 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 993 994 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 995 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 996 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 997 998 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 999 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1000 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1001 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1002 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1003 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1004 1005 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1006 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1007 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1008 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1009 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1010 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1011 1012 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1013 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1014 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1015 1016 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1017 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1018 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1019 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1020 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1021 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1022 1023 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1024 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1025 1026 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1027 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1028 1029 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1030 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1031 1032 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1033 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1034 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1035 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1036 1037 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1038 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1039 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1040 1041 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1042 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1043 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1044 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1045 1046 if (Subtarget->hasAVX2()) { 1047 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1048 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1049 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1050 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1051 1052 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1053 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1054 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1055 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1056 1057 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1058 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1059 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1060 // Don't lower v32i8 because there is no 128-bit byte mul 1061 1062 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1063 1064 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1065 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1066 1067 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1068 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1069 1070 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1071 } else { 1072 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1073 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1074 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1075 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1076 1077 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1078 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1079 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1080 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1081 1082 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1083 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1084 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1085 // Don't lower v32i8 because there is no 128-bit byte mul 1086 1087 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1088 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1089 1090 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1091 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1092 1093 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1094 } 1095 1096 // Custom lower several nodes for 256-bit types. 1097 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1098 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1099 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1100 EVT VT = SVT; 1101 1102 // Extract subvector is special because the value type 1103 // (result) is 128-bit but the source is 256-bit wide. 1104 if (VT.is128BitVector()) 1105 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1106 1107 // Do not attempt to custom lower other non-256-bit vectors 1108 if (!VT.is256BitVector()) 1109 continue; 1110 1111 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1112 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1113 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1114 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1115 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1116 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1117 } 1118 1119 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1120 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1121 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1122 EVT VT = SVT; 1123 1124 // Do not attempt to promote non-256-bit vectors 1125 if (!VT.is256BitVector()) 1126 continue; 1127 1128 setOperationAction(ISD::AND, SVT, Promote); 1129 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1130 setOperationAction(ISD::OR, SVT, Promote); 1131 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1132 setOperationAction(ISD::XOR, SVT, Promote); 1133 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1134 setOperationAction(ISD::LOAD, SVT, Promote); 1135 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1136 setOperationAction(ISD::SELECT, SVT, Promote); 1137 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1138 } 1139 } 1140 1141 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1142 // of this type with custom code. 1143 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1144 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1145 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1146 } 1147 1148 // We want to custom lower some of our intrinsics. 1149 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1150 1151 1152 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1153 // handle type legalization for these operations here. 1154 // 1155 // FIXME: We really should do custom legalization for addition and 1156 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1157 // than generic legalization for 64-bit multiplication-with-overflow, though. 1158 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1159 // Add/Sub/Mul with overflow operations are custom lowered. 1160 MVT VT = IntVTs[i]; 1161 setOperationAction(ISD::SADDO, VT, Custom); 1162 setOperationAction(ISD::UADDO, VT, Custom); 1163 setOperationAction(ISD::SSUBO, VT, Custom); 1164 setOperationAction(ISD::USUBO, VT, Custom); 1165 setOperationAction(ISD::SMULO, VT, Custom); 1166 setOperationAction(ISD::UMULO, VT, Custom); 1167 } 1168 1169 // There are no 8-bit 3-address imul/mul instructions 1170 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1171 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1172 1173 if (!Subtarget->is64Bit()) { 1174 // These libcalls are not available in 32-bit. 1175 setLibcallName(RTLIB::SHL_I128, 0); 1176 setLibcallName(RTLIB::SRL_I128, 0); 1177 setLibcallName(RTLIB::SRA_I128, 0); 1178 } 1179 1180 // We have target-specific dag combine patterns for the following nodes: 1181 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1182 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1183 setTargetDAGCombine(ISD::BUILD_VECTOR); 1184 setTargetDAGCombine(ISD::VSELECT); 1185 setTargetDAGCombine(ISD::SELECT); 1186 setTargetDAGCombine(ISD::SHL); 1187 setTargetDAGCombine(ISD::SRA); 1188 setTargetDAGCombine(ISD::SRL); 1189 setTargetDAGCombine(ISD::OR); 1190 setTargetDAGCombine(ISD::AND); 1191 setTargetDAGCombine(ISD::ADD); 1192 setTargetDAGCombine(ISD::FADD); 1193 setTargetDAGCombine(ISD::FSUB); 1194 setTargetDAGCombine(ISD::SUB); 1195 setTargetDAGCombine(ISD::LOAD); 1196 setTargetDAGCombine(ISD::STORE); 1197 setTargetDAGCombine(ISD::ZERO_EXTEND); 1198 setTargetDAGCombine(ISD::SINT_TO_FP); 1199 if (Subtarget->is64Bit()) 1200 setTargetDAGCombine(ISD::MUL); 1201 if (Subtarget->hasBMI()) 1202 setTargetDAGCombine(ISD::XOR); 1203 1204 computeRegisterProperties(); 1205 1206 // On Darwin, -Os means optimize for size without hurting performance, 1207 // do not reduce the limit. 1208 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1209 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1210 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1211 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1212 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1213 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1214 setPrefLoopAlignment(16); 1215 benefitFromCodePlacementOpt = true; 1216 1217 setPrefFunctionAlignment(4); 1218} 1219 1220 1221EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1222 if (!VT.isVector()) return MVT::i8; 1223 return VT.changeVectorElementTypeToInteger(); 1224} 1225 1226 1227/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1228/// the desired ByVal argument alignment. 1229static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1230 if (MaxAlign == 16) 1231 return; 1232 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1233 if (VTy->getBitWidth() == 128) 1234 MaxAlign = 16; 1235 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1236 unsigned EltAlign = 0; 1237 getMaxByValAlign(ATy->getElementType(), EltAlign); 1238 if (EltAlign > MaxAlign) 1239 MaxAlign = EltAlign; 1240 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1241 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1242 unsigned EltAlign = 0; 1243 getMaxByValAlign(STy->getElementType(i), EltAlign); 1244 if (EltAlign > MaxAlign) 1245 MaxAlign = EltAlign; 1246 if (MaxAlign == 16) 1247 break; 1248 } 1249 } 1250 return; 1251} 1252 1253/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1254/// function arguments in the caller parameter area. For X86, aggregates 1255/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1256/// are at 4-byte boundaries. 1257unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1258 if (Subtarget->is64Bit()) { 1259 // Max of 8 and alignment of type. 1260 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1261 if (TyAlign > 8) 1262 return TyAlign; 1263 return 8; 1264 } 1265 1266 unsigned Align = 4; 1267 if (Subtarget->hasXMM()) 1268 getMaxByValAlign(Ty, Align); 1269 return Align; 1270} 1271 1272/// getOptimalMemOpType - Returns the target specific optimal type for load 1273/// and store operations as a result of memset, memcpy, and memmove 1274/// lowering. If DstAlign is zero that means it's safe to destination 1275/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1276/// means there isn't a need to check it against alignment requirement, 1277/// probably because the source does not need to be loaded. If 1278/// 'IsZeroVal' is true, that means it's safe to return a 1279/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1280/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1281/// constant so it does not need to be loaded. 1282/// It returns EVT::Other if the type should be determined using generic 1283/// target-independent logic. 1284EVT 1285X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1286 unsigned DstAlign, unsigned SrcAlign, 1287 bool IsZeroVal, 1288 bool MemcpyStrSrc, 1289 MachineFunction &MF) const { 1290 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1291 // linux. This is because the stack realignment code can't handle certain 1292 // cases like PR2962. This should be removed when PR2962 is fixed. 1293 const Function *F = MF.getFunction(); 1294 if (IsZeroVal && 1295 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1296 if (Size >= 16 && 1297 (Subtarget->isUnalignedMemAccessFast() || 1298 ((DstAlign == 0 || DstAlign >= 16) && 1299 (SrcAlign == 0 || SrcAlign >= 16))) && 1300 Subtarget->getStackAlignment() >= 16) { 1301 if (Subtarget->hasAVX() && 1302 Subtarget->getStackAlignment() >= 32) 1303 return MVT::v8f32; 1304 if (Subtarget->hasXMMInt()) 1305 return MVT::v4i32; 1306 if (Subtarget->hasXMM()) 1307 return MVT::v4f32; 1308 } else if (!MemcpyStrSrc && Size >= 8 && 1309 !Subtarget->is64Bit() && 1310 Subtarget->getStackAlignment() >= 8 && 1311 Subtarget->hasXMMInt()) { 1312 // Do not use f64 to lower memcpy if source is string constant. It's 1313 // better to use i32 to avoid the loads. 1314 return MVT::f64; 1315 } 1316 } 1317 if (Subtarget->is64Bit() && Size >= 8) 1318 return MVT::i64; 1319 return MVT::i32; 1320} 1321 1322/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1323/// current function. The returned value is a member of the 1324/// MachineJumpTableInfo::JTEntryKind enum. 1325unsigned X86TargetLowering::getJumpTableEncoding() const { 1326 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1327 // symbol. 1328 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1329 Subtarget->isPICStyleGOT()) 1330 return MachineJumpTableInfo::EK_Custom32; 1331 1332 // Otherwise, use the normal jump table encoding heuristics. 1333 return TargetLowering::getJumpTableEncoding(); 1334} 1335 1336const MCExpr * 1337X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1338 const MachineBasicBlock *MBB, 1339 unsigned uid,MCContext &Ctx) const{ 1340 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1341 Subtarget->isPICStyleGOT()); 1342 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1343 // entries. 1344 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1345 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1346} 1347 1348/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1349/// jumptable. 1350SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1351 SelectionDAG &DAG) const { 1352 if (!Subtarget->is64Bit()) 1353 // This doesn't have DebugLoc associated with it, but is not really the 1354 // same as a Register. 1355 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1356 return Table; 1357} 1358 1359/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1360/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1361/// MCExpr. 1362const MCExpr *X86TargetLowering:: 1363getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1364 MCContext &Ctx) const { 1365 // X86-64 uses RIP relative addressing based on the jump table label. 1366 if (Subtarget->isPICStyleRIPRel()) 1367 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1368 1369 // Otherwise, the reference is relative to the PIC base. 1370 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1371} 1372 1373// FIXME: Why this routine is here? Move to RegInfo! 1374std::pair<const TargetRegisterClass*, uint8_t> 1375X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1376 const TargetRegisterClass *RRC = 0; 1377 uint8_t Cost = 1; 1378 switch (VT.getSimpleVT().SimpleTy) { 1379 default: 1380 return TargetLowering::findRepresentativeClass(VT); 1381 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1382 RRC = (Subtarget->is64Bit() 1383 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1384 break; 1385 case MVT::x86mmx: 1386 RRC = X86::VR64RegisterClass; 1387 break; 1388 case MVT::f32: case MVT::f64: 1389 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1390 case MVT::v4f32: case MVT::v2f64: 1391 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1392 case MVT::v4f64: 1393 RRC = X86::VR128RegisterClass; 1394 break; 1395 } 1396 return std::make_pair(RRC, Cost); 1397} 1398 1399bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1400 unsigned &Offset) const { 1401 if (!Subtarget->isTargetLinux()) 1402 return false; 1403 1404 if (Subtarget->is64Bit()) { 1405 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1406 Offset = 0x28; 1407 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1408 AddressSpace = 256; 1409 else 1410 AddressSpace = 257; 1411 } else { 1412 // %gs:0x14 on i386 1413 Offset = 0x14; 1414 AddressSpace = 256; 1415 } 1416 return true; 1417} 1418 1419 1420//===----------------------------------------------------------------------===// 1421// Return Value Calling Convention Implementation 1422//===----------------------------------------------------------------------===// 1423 1424#include "X86GenCallingConv.inc" 1425 1426bool 1427X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1428 MachineFunction &MF, bool isVarArg, 1429 const SmallVectorImpl<ISD::OutputArg> &Outs, 1430 LLVMContext &Context) const { 1431 SmallVector<CCValAssign, 16> RVLocs; 1432 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1433 RVLocs, Context); 1434 return CCInfo.CheckReturn(Outs, RetCC_X86); 1435} 1436 1437SDValue 1438X86TargetLowering::LowerReturn(SDValue Chain, 1439 CallingConv::ID CallConv, bool isVarArg, 1440 const SmallVectorImpl<ISD::OutputArg> &Outs, 1441 const SmallVectorImpl<SDValue> &OutVals, 1442 DebugLoc dl, SelectionDAG &DAG) const { 1443 MachineFunction &MF = DAG.getMachineFunction(); 1444 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1445 1446 SmallVector<CCValAssign, 16> RVLocs; 1447 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1448 RVLocs, *DAG.getContext()); 1449 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1450 1451 // Add the regs to the liveout set for the function. 1452 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1453 for (unsigned i = 0; i != RVLocs.size(); ++i) 1454 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1455 MRI.addLiveOut(RVLocs[i].getLocReg()); 1456 1457 SDValue Flag; 1458 1459 SmallVector<SDValue, 6> RetOps; 1460 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1461 // Operand #1 = Bytes To Pop 1462 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1463 MVT::i16)); 1464 1465 // Copy the result values into the output registers. 1466 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1467 CCValAssign &VA = RVLocs[i]; 1468 assert(VA.isRegLoc() && "Can only return in registers!"); 1469 SDValue ValToCopy = OutVals[i]; 1470 EVT ValVT = ValToCopy.getValueType(); 1471 1472 // If this is x86-64, and we disabled SSE, we can't return FP values, 1473 // or SSE or MMX vectors. 1474 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1475 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1476 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1477 report_fatal_error("SSE register return with SSE disabled"); 1478 } 1479 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1480 // llvm-gcc has never done it right and no one has noticed, so this 1481 // should be OK for now. 1482 if (ValVT == MVT::f64 && 1483 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1484 report_fatal_error("SSE2 register return with SSE2 disabled"); 1485 1486 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1487 // the RET instruction and handled by the FP Stackifier. 1488 if (VA.getLocReg() == X86::ST0 || 1489 VA.getLocReg() == X86::ST1) { 1490 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1491 // change the value to the FP stack register class. 1492 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1493 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1494 RetOps.push_back(ValToCopy); 1495 // Don't emit a copytoreg. 1496 continue; 1497 } 1498 1499 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1500 // which is returned in RAX / RDX. 1501 if (Subtarget->is64Bit()) { 1502 if (ValVT == MVT::x86mmx) { 1503 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1504 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1505 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1506 ValToCopy); 1507 // If we don't have SSE2 available, convert to v4f32 so the generated 1508 // register is legal. 1509 if (!Subtarget->hasXMMInt()) 1510 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1511 } 1512 } 1513 } 1514 1515 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1516 Flag = Chain.getValue(1); 1517 } 1518 1519 // The x86-64 ABI for returning structs by value requires that we copy 1520 // the sret argument into %rax for the return. We saved the argument into 1521 // a virtual register in the entry block, so now we copy the value out 1522 // and into %rax. 1523 if (Subtarget->is64Bit() && 1524 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1525 MachineFunction &MF = DAG.getMachineFunction(); 1526 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1527 unsigned Reg = FuncInfo->getSRetReturnReg(); 1528 assert(Reg && 1529 "SRetReturnReg should have been set in LowerFormalArguments()."); 1530 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1531 1532 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1533 Flag = Chain.getValue(1); 1534 1535 // RAX now acts like a return value. 1536 MRI.addLiveOut(X86::RAX); 1537 } 1538 1539 RetOps[0] = Chain; // Update chain. 1540 1541 // Add the flag if we have it. 1542 if (Flag.getNode()) 1543 RetOps.push_back(Flag); 1544 1545 return DAG.getNode(X86ISD::RET_FLAG, dl, 1546 MVT::Other, &RetOps[0], RetOps.size()); 1547} 1548 1549bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1550 if (N->getNumValues() != 1) 1551 return false; 1552 if (!N->hasNUsesOfValue(1, 0)) 1553 return false; 1554 1555 SDNode *Copy = *N->use_begin(); 1556 if (Copy->getOpcode() != ISD::CopyToReg && 1557 Copy->getOpcode() != ISD::FP_EXTEND) 1558 return false; 1559 1560 bool HasRet = false; 1561 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1562 UI != UE; ++UI) { 1563 if (UI->getOpcode() != X86ISD::RET_FLAG) 1564 return false; 1565 HasRet = true; 1566 } 1567 1568 return HasRet; 1569} 1570 1571EVT 1572X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1573 ISD::NodeType ExtendKind) const { 1574 MVT ReturnMVT; 1575 // TODO: Is this also valid on 32-bit? 1576 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1577 ReturnMVT = MVT::i8; 1578 else 1579 ReturnMVT = MVT::i32; 1580 1581 EVT MinVT = getRegisterType(Context, ReturnMVT); 1582 return VT.bitsLT(MinVT) ? MinVT : VT; 1583} 1584 1585/// LowerCallResult - Lower the result values of a call into the 1586/// appropriate copies out of appropriate physical registers. 1587/// 1588SDValue 1589X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1590 CallingConv::ID CallConv, bool isVarArg, 1591 const SmallVectorImpl<ISD::InputArg> &Ins, 1592 DebugLoc dl, SelectionDAG &DAG, 1593 SmallVectorImpl<SDValue> &InVals) const { 1594 1595 // Assign locations to each value returned by this call. 1596 SmallVector<CCValAssign, 16> RVLocs; 1597 bool Is64Bit = Subtarget->is64Bit(); 1598 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1599 getTargetMachine(), RVLocs, *DAG.getContext()); 1600 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1601 1602 // Copy all of the result registers out of their specified physreg. 1603 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1604 CCValAssign &VA = RVLocs[i]; 1605 EVT CopyVT = VA.getValVT(); 1606 1607 // If this is x86-64, and we disabled SSE, we can't return FP values 1608 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1609 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1610 report_fatal_error("SSE register return with SSE disabled"); 1611 } 1612 1613 SDValue Val; 1614 1615 // If this is a call to a function that returns an fp value on the floating 1616 // point stack, we must guarantee the the value is popped from the stack, so 1617 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1618 // if the return value is not used. We use the FpPOP_RETVAL instruction 1619 // instead. 1620 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1621 // If we prefer to use the value in xmm registers, copy it out as f80 and 1622 // use a truncate to move it from fp stack reg to xmm reg. 1623 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1624 SDValue Ops[] = { Chain, InFlag }; 1625 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1626 MVT::Other, MVT::Glue, Ops, 2), 1); 1627 Val = Chain.getValue(0); 1628 1629 // Round the f80 to the right size, which also moves it to the appropriate 1630 // xmm register. 1631 if (CopyVT != VA.getValVT()) 1632 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1633 // This truncation won't change the value. 1634 DAG.getIntPtrConstant(1)); 1635 } else { 1636 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1637 CopyVT, InFlag).getValue(1); 1638 Val = Chain.getValue(0); 1639 } 1640 InFlag = Chain.getValue(2); 1641 InVals.push_back(Val); 1642 } 1643 1644 return Chain; 1645} 1646 1647 1648//===----------------------------------------------------------------------===// 1649// C & StdCall & Fast Calling Convention implementation 1650//===----------------------------------------------------------------------===// 1651// StdCall calling convention seems to be standard for many Windows' API 1652// routines and around. It differs from C calling convention just a little: 1653// callee should clean up the stack, not caller. Symbols should be also 1654// decorated in some fancy way :) It doesn't support any vector arguments. 1655// For info on fast calling convention see Fast Calling Convention (tail call) 1656// implementation LowerX86_32FastCCCallTo. 1657 1658/// CallIsStructReturn - Determines whether a call uses struct return 1659/// semantics. 1660static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1661 if (Outs.empty()) 1662 return false; 1663 1664 return Outs[0].Flags.isSRet(); 1665} 1666 1667/// ArgsAreStructReturn - Determines whether a function uses struct 1668/// return semantics. 1669static bool 1670ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1671 if (Ins.empty()) 1672 return false; 1673 1674 return Ins[0].Flags.isSRet(); 1675} 1676 1677/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1678/// by "Src" to address "Dst" with size and alignment information specified by 1679/// the specific parameter attribute. The copy will be passed as a byval 1680/// function parameter. 1681static SDValue 1682CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1683 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1684 DebugLoc dl) { 1685 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1686 1687 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1688 /*isVolatile*/false, /*AlwaysInline=*/true, 1689 MachinePointerInfo(), MachinePointerInfo()); 1690} 1691 1692/// IsTailCallConvention - Return true if the calling convention is one that 1693/// supports tail call optimization. 1694static bool IsTailCallConvention(CallingConv::ID CC) { 1695 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1696} 1697 1698bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1699 if (!CI->isTailCall()) 1700 return false; 1701 1702 CallSite CS(CI); 1703 CallingConv::ID CalleeCC = CS.getCallingConv(); 1704 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1705 return false; 1706 1707 return true; 1708} 1709 1710/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1711/// a tailcall target by changing its ABI. 1712static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1713 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1714} 1715 1716SDValue 1717X86TargetLowering::LowerMemArgument(SDValue Chain, 1718 CallingConv::ID CallConv, 1719 const SmallVectorImpl<ISD::InputArg> &Ins, 1720 DebugLoc dl, SelectionDAG &DAG, 1721 const CCValAssign &VA, 1722 MachineFrameInfo *MFI, 1723 unsigned i) const { 1724 // Create the nodes corresponding to a load from this parameter slot. 1725 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1726 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1727 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1728 EVT ValVT; 1729 1730 // If value is passed by pointer we have address passed instead of the value 1731 // itself. 1732 if (VA.getLocInfo() == CCValAssign::Indirect) 1733 ValVT = VA.getLocVT(); 1734 else 1735 ValVT = VA.getValVT(); 1736 1737 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1738 // changed with more analysis. 1739 // In case of tail call optimization mark all arguments mutable. Since they 1740 // could be overwritten by lowering of arguments in case of a tail call. 1741 if (Flags.isByVal()) { 1742 unsigned Bytes = Flags.getByValSize(); 1743 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1744 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1745 return DAG.getFrameIndex(FI, getPointerTy()); 1746 } else { 1747 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1748 VA.getLocMemOffset(), isImmutable); 1749 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1750 return DAG.getLoad(ValVT, dl, Chain, FIN, 1751 MachinePointerInfo::getFixedStack(FI), 1752 false, false, false, 0); 1753 } 1754} 1755 1756SDValue 1757X86TargetLowering::LowerFormalArguments(SDValue Chain, 1758 CallingConv::ID CallConv, 1759 bool isVarArg, 1760 const SmallVectorImpl<ISD::InputArg> &Ins, 1761 DebugLoc dl, 1762 SelectionDAG &DAG, 1763 SmallVectorImpl<SDValue> &InVals) 1764 const { 1765 MachineFunction &MF = DAG.getMachineFunction(); 1766 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1767 1768 const Function* Fn = MF.getFunction(); 1769 if (Fn->hasExternalLinkage() && 1770 Subtarget->isTargetCygMing() && 1771 Fn->getName() == "main") 1772 FuncInfo->setForceFramePointer(true); 1773 1774 MachineFrameInfo *MFI = MF.getFrameInfo(); 1775 bool Is64Bit = Subtarget->is64Bit(); 1776 bool IsWin64 = Subtarget->isTargetWin64(); 1777 1778 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1779 "Var args not supported with calling convention fastcc or ghc"); 1780 1781 // Assign locations to all of the incoming arguments. 1782 SmallVector<CCValAssign, 16> ArgLocs; 1783 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1784 ArgLocs, *DAG.getContext()); 1785 1786 // Allocate shadow area for Win64 1787 if (IsWin64) { 1788 CCInfo.AllocateStack(32, 8); 1789 } 1790 1791 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1792 1793 unsigned LastVal = ~0U; 1794 SDValue ArgValue; 1795 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1796 CCValAssign &VA = ArgLocs[i]; 1797 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1798 // places. 1799 assert(VA.getValNo() != LastVal && 1800 "Don't support value assigned to multiple locs yet"); 1801 (void)LastVal; 1802 LastVal = VA.getValNo(); 1803 1804 if (VA.isRegLoc()) { 1805 EVT RegVT = VA.getLocVT(); 1806 TargetRegisterClass *RC = NULL; 1807 if (RegVT == MVT::i32) 1808 RC = X86::GR32RegisterClass; 1809 else if (Is64Bit && RegVT == MVT::i64) 1810 RC = X86::GR64RegisterClass; 1811 else if (RegVT == MVT::f32) 1812 RC = X86::FR32RegisterClass; 1813 else if (RegVT == MVT::f64) 1814 RC = X86::FR64RegisterClass; 1815 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1816 RC = X86::VR256RegisterClass; 1817 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1818 RC = X86::VR128RegisterClass; 1819 else if (RegVT == MVT::x86mmx) 1820 RC = X86::VR64RegisterClass; 1821 else 1822 llvm_unreachable("Unknown argument type!"); 1823 1824 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1825 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1826 1827 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1828 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1829 // right size. 1830 if (VA.getLocInfo() == CCValAssign::SExt) 1831 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1832 DAG.getValueType(VA.getValVT())); 1833 else if (VA.getLocInfo() == CCValAssign::ZExt) 1834 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1835 DAG.getValueType(VA.getValVT())); 1836 else if (VA.getLocInfo() == CCValAssign::BCvt) 1837 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1838 1839 if (VA.isExtInLoc()) { 1840 // Handle MMX values passed in XMM regs. 1841 if (RegVT.isVector()) { 1842 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1843 ArgValue); 1844 } else 1845 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1846 } 1847 } else { 1848 assert(VA.isMemLoc()); 1849 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1850 } 1851 1852 // If value is passed via pointer - do a load. 1853 if (VA.getLocInfo() == CCValAssign::Indirect) 1854 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1855 MachinePointerInfo(), false, false, false, 0); 1856 1857 InVals.push_back(ArgValue); 1858 } 1859 1860 // The x86-64 ABI for returning structs by value requires that we copy 1861 // the sret argument into %rax for the return. Save the argument into 1862 // a virtual register so that we can access it from the return points. 1863 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1864 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1865 unsigned Reg = FuncInfo->getSRetReturnReg(); 1866 if (!Reg) { 1867 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1868 FuncInfo->setSRetReturnReg(Reg); 1869 } 1870 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1871 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1872 } 1873 1874 unsigned StackSize = CCInfo.getNextStackOffset(); 1875 // Align stack specially for tail calls. 1876 if (FuncIsMadeTailCallSafe(CallConv)) 1877 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1878 1879 // If the function takes variable number of arguments, make a frame index for 1880 // the start of the first vararg value... for expansion of llvm.va_start. 1881 if (isVarArg) { 1882 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1883 CallConv != CallingConv::X86_ThisCall)) { 1884 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1885 } 1886 if (Is64Bit) { 1887 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1888 1889 // FIXME: We should really autogenerate these arrays 1890 static const unsigned GPR64ArgRegsWin64[] = { 1891 X86::RCX, X86::RDX, X86::R8, X86::R9 1892 }; 1893 static const unsigned GPR64ArgRegs64Bit[] = { 1894 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1895 }; 1896 static const unsigned XMMArgRegs64Bit[] = { 1897 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1898 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1899 }; 1900 const unsigned *GPR64ArgRegs; 1901 unsigned NumXMMRegs = 0; 1902 1903 if (IsWin64) { 1904 // The XMM registers which might contain var arg parameters are shadowed 1905 // in their paired GPR. So we only need to save the GPR to their home 1906 // slots. 1907 TotalNumIntRegs = 4; 1908 GPR64ArgRegs = GPR64ArgRegsWin64; 1909 } else { 1910 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1911 GPR64ArgRegs = GPR64ArgRegs64Bit; 1912 1913 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1914 } 1915 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1916 TotalNumIntRegs); 1917 1918 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1919 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1920 "SSE register cannot be used when SSE is disabled!"); 1921 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1922 "SSE register cannot be used when SSE is disabled!"); 1923 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1924 // Kernel mode asks for SSE to be disabled, so don't push them 1925 // on the stack. 1926 TotalNumXMMRegs = 0; 1927 1928 if (IsWin64) { 1929 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1930 // Get to the caller-allocated home save location. Add 8 to account 1931 // for the return address. 1932 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1933 FuncInfo->setRegSaveFrameIndex( 1934 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1935 // Fixup to set vararg frame on shadow area (4 x i64). 1936 if (NumIntRegs < 4) 1937 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1938 } else { 1939 // For X86-64, if there are vararg parameters that are passed via 1940 // registers, then we must store them to their spots on the stack so they 1941 // may be loaded by deferencing the result of va_next. 1942 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1943 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1944 FuncInfo->setRegSaveFrameIndex( 1945 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1946 false)); 1947 } 1948 1949 // Store the integer parameter registers. 1950 SmallVector<SDValue, 8> MemOps; 1951 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1952 getPointerTy()); 1953 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1954 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1955 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1956 DAG.getIntPtrConstant(Offset)); 1957 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1958 X86::GR64RegisterClass); 1959 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1960 SDValue Store = 1961 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1962 MachinePointerInfo::getFixedStack( 1963 FuncInfo->getRegSaveFrameIndex(), Offset), 1964 false, false, 0); 1965 MemOps.push_back(Store); 1966 Offset += 8; 1967 } 1968 1969 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1970 // Now store the XMM (fp + vector) parameter registers. 1971 SmallVector<SDValue, 11> SaveXMMOps; 1972 SaveXMMOps.push_back(Chain); 1973 1974 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1975 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1976 SaveXMMOps.push_back(ALVal); 1977 1978 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1979 FuncInfo->getRegSaveFrameIndex())); 1980 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1981 FuncInfo->getVarArgsFPOffset())); 1982 1983 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1984 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1985 X86::VR128RegisterClass); 1986 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1987 SaveXMMOps.push_back(Val); 1988 } 1989 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1990 MVT::Other, 1991 &SaveXMMOps[0], SaveXMMOps.size())); 1992 } 1993 1994 if (!MemOps.empty()) 1995 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1996 &MemOps[0], MemOps.size()); 1997 } 1998 } 1999 2000 // Some CCs need callee pop. 2001 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 2002 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2003 } else { 2004 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2005 // If this is an sret function, the return should pop the hidden pointer. 2006 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 2007 FuncInfo->setBytesToPopOnReturn(4); 2008 } 2009 2010 if (!Is64Bit) { 2011 // RegSaveFrameIndex is X86-64 only. 2012 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2013 if (CallConv == CallingConv::X86_FastCall || 2014 CallConv == CallingConv::X86_ThisCall) 2015 // fastcc functions can't have varargs. 2016 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2017 } 2018 2019 FuncInfo->setArgumentStackSize(StackSize); 2020 2021 return Chain; 2022} 2023 2024SDValue 2025X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2026 SDValue StackPtr, SDValue Arg, 2027 DebugLoc dl, SelectionDAG &DAG, 2028 const CCValAssign &VA, 2029 ISD::ArgFlagsTy Flags) const { 2030 unsigned LocMemOffset = VA.getLocMemOffset(); 2031 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2032 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2033 if (Flags.isByVal()) 2034 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2035 2036 return DAG.getStore(Chain, dl, Arg, PtrOff, 2037 MachinePointerInfo::getStack(LocMemOffset), 2038 false, false, 0); 2039} 2040 2041/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2042/// optimization is performed and it is required. 2043SDValue 2044X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2045 SDValue &OutRetAddr, SDValue Chain, 2046 bool IsTailCall, bool Is64Bit, 2047 int FPDiff, DebugLoc dl) const { 2048 // Adjust the Return address stack slot. 2049 EVT VT = getPointerTy(); 2050 OutRetAddr = getReturnAddressFrameIndex(DAG); 2051 2052 // Load the "old" Return address. 2053 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2054 false, false, false, 0); 2055 return SDValue(OutRetAddr.getNode(), 1); 2056} 2057 2058/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2059/// optimization is performed and it is required (FPDiff!=0). 2060static SDValue 2061EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2062 SDValue Chain, SDValue RetAddrFrIdx, 2063 bool Is64Bit, int FPDiff, DebugLoc dl) { 2064 // Store the return address to the appropriate stack slot. 2065 if (!FPDiff) return Chain; 2066 // Calculate the new stack slot for the return address. 2067 int SlotSize = Is64Bit ? 8 : 4; 2068 int NewReturnAddrFI = 2069 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2070 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2071 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2072 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2073 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2074 false, false, 0); 2075 return Chain; 2076} 2077 2078SDValue 2079X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2080 CallingConv::ID CallConv, bool isVarArg, 2081 bool &isTailCall, 2082 const SmallVectorImpl<ISD::OutputArg> &Outs, 2083 const SmallVectorImpl<SDValue> &OutVals, 2084 const SmallVectorImpl<ISD::InputArg> &Ins, 2085 DebugLoc dl, SelectionDAG &DAG, 2086 SmallVectorImpl<SDValue> &InVals) const { 2087 MachineFunction &MF = DAG.getMachineFunction(); 2088 bool Is64Bit = Subtarget->is64Bit(); 2089 bool IsWin64 = Subtarget->isTargetWin64(); 2090 bool IsStructRet = CallIsStructReturn(Outs); 2091 bool IsSibcall = false; 2092 2093 if (isTailCall) { 2094 // Check if it's really possible to do a tail call. 2095 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2096 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2097 Outs, OutVals, Ins, DAG); 2098 2099 // Sibcalls are automatically detected tailcalls which do not require 2100 // ABI changes. 2101 if (!GuaranteedTailCallOpt && isTailCall) 2102 IsSibcall = true; 2103 2104 if (isTailCall) 2105 ++NumTailCalls; 2106 } 2107 2108 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2109 "Var args not supported with calling convention fastcc or ghc"); 2110 2111 // Analyze operands of the call, assigning locations to each operand. 2112 SmallVector<CCValAssign, 16> ArgLocs; 2113 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2114 ArgLocs, *DAG.getContext()); 2115 2116 // Allocate shadow area for Win64 2117 if (IsWin64) { 2118 CCInfo.AllocateStack(32, 8); 2119 } 2120 2121 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2122 2123 // Get a count of how many bytes are to be pushed on the stack. 2124 unsigned NumBytes = CCInfo.getNextStackOffset(); 2125 if (IsSibcall) 2126 // This is a sibcall. The memory operands are available in caller's 2127 // own caller's stack. 2128 NumBytes = 0; 2129 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2130 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2131 2132 int FPDiff = 0; 2133 if (isTailCall && !IsSibcall) { 2134 // Lower arguments at fp - stackoffset + fpdiff. 2135 unsigned NumBytesCallerPushed = 2136 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2137 FPDiff = NumBytesCallerPushed - NumBytes; 2138 2139 // Set the delta of movement of the returnaddr stackslot. 2140 // But only set if delta is greater than previous delta. 2141 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2142 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2143 } 2144 2145 if (!IsSibcall) 2146 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2147 2148 SDValue RetAddrFrIdx; 2149 // Load return address for tail calls. 2150 if (isTailCall && FPDiff) 2151 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2152 Is64Bit, FPDiff, dl); 2153 2154 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2155 SmallVector<SDValue, 8> MemOpChains; 2156 SDValue StackPtr; 2157 2158 // Walk the register/memloc assignments, inserting copies/loads. In the case 2159 // of tail call optimization arguments are handle later. 2160 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2161 CCValAssign &VA = ArgLocs[i]; 2162 EVT RegVT = VA.getLocVT(); 2163 SDValue Arg = OutVals[i]; 2164 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2165 bool isByVal = Flags.isByVal(); 2166 2167 // Promote the value if needed. 2168 switch (VA.getLocInfo()) { 2169 default: llvm_unreachable("Unknown loc info!"); 2170 case CCValAssign::Full: break; 2171 case CCValAssign::SExt: 2172 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2173 break; 2174 case CCValAssign::ZExt: 2175 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2176 break; 2177 case CCValAssign::AExt: 2178 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2179 // Special case: passing MMX values in XMM registers. 2180 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2181 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2182 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2183 } else 2184 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2185 break; 2186 case CCValAssign::BCvt: 2187 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2188 break; 2189 case CCValAssign::Indirect: { 2190 // Store the argument. 2191 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2192 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2193 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2194 MachinePointerInfo::getFixedStack(FI), 2195 false, false, 0); 2196 Arg = SpillSlot; 2197 break; 2198 } 2199 } 2200 2201 if (VA.isRegLoc()) { 2202 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2203 if (isVarArg && IsWin64) { 2204 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2205 // shadow reg if callee is a varargs function. 2206 unsigned ShadowReg = 0; 2207 switch (VA.getLocReg()) { 2208 case X86::XMM0: ShadowReg = X86::RCX; break; 2209 case X86::XMM1: ShadowReg = X86::RDX; break; 2210 case X86::XMM2: ShadowReg = X86::R8; break; 2211 case X86::XMM3: ShadowReg = X86::R9; break; 2212 } 2213 if (ShadowReg) 2214 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2215 } 2216 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2217 assert(VA.isMemLoc()); 2218 if (StackPtr.getNode() == 0) 2219 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2220 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2221 dl, DAG, VA, Flags)); 2222 } 2223 } 2224 2225 if (!MemOpChains.empty()) 2226 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2227 &MemOpChains[0], MemOpChains.size()); 2228 2229 // Build a sequence of copy-to-reg nodes chained together with token chain 2230 // and flag operands which copy the outgoing args into registers. 2231 SDValue InFlag; 2232 // Tail call byval lowering might overwrite argument registers so in case of 2233 // tail call optimization the copies to registers are lowered later. 2234 if (!isTailCall) 2235 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2236 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2237 RegsToPass[i].second, InFlag); 2238 InFlag = Chain.getValue(1); 2239 } 2240 2241 if (Subtarget->isPICStyleGOT()) { 2242 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2243 // GOT pointer. 2244 if (!isTailCall) { 2245 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2246 DAG.getNode(X86ISD::GlobalBaseReg, 2247 DebugLoc(), getPointerTy()), 2248 InFlag); 2249 InFlag = Chain.getValue(1); 2250 } else { 2251 // If we are tail calling and generating PIC/GOT style code load the 2252 // address of the callee into ECX. The value in ecx is used as target of 2253 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2254 // for tail calls on PIC/GOT architectures. Normally we would just put the 2255 // address of GOT into ebx and then call target@PLT. But for tail calls 2256 // ebx would be restored (since ebx is callee saved) before jumping to the 2257 // target@PLT. 2258 2259 // Note: The actual moving to ECX is done further down. 2260 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2261 if (G && !G->getGlobal()->hasHiddenVisibility() && 2262 !G->getGlobal()->hasProtectedVisibility()) 2263 Callee = LowerGlobalAddress(Callee, DAG); 2264 else if (isa<ExternalSymbolSDNode>(Callee)) 2265 Callee = LowerExternalSymbol(Callee, DAG); 2266 } 2267 } 2268 2269 if (Is64Bit && isVarArg && !IsWin64) { 2270 // From AMD64 ABI document: 2271 // For calls that may call functions that use varargs or stdargs 2272 // (prototype-less calls or calls to functions containing ellipsis (...) in 2273 // the declaration) %al is used as hidden argument to specify the number 2274 // of SSE registers used. The contents of %al do not need to match exactly 2275 // the number of registers, but must be an ubound on the number of SSE 2276 // registers used and is in the range 0 - 8 inclusive. 2277 2278 // Count the number of XMM registers allocated. 2279 static const unsigned XMMArgRegs[] = { 2280 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2281 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2282 }; 2283 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2284 assert((Subtarget->hasXMM() || !NumXMMRegs) 2285 && "SSE registers cannot be used when SSE is disabled"); 2286 2287 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2288 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2289 InFlag = Chain.getValue(1); 2290 } 2291 2292 2293 // For tail calls lower the arguments to the 'real' stack slot. 2294 if (isTailCall) { 2295 // Force all the incoming stack arguments to be loaded from the stack 2296 // before any new outgoing arguments are stored to the stack, because the 2297 // outgoing stack slots may alias the incoming argument stack slots, and 2298 // the alias isn't otherwise explicit. This is slightly more conservative 2299 // than necessary, because it means that each store effectively depends 2300 // on every argument instead of just those arguments it would clobber. 2301 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2302 2303 SmallVector<SDValue, 8> MemOpChains2; 2304 SDValue FIN; 2305 int FI = 0; 2306 // Do not flag preceding copytoreg stuff together with the following stuff. 2307 InFlag = SDValue(); 2308 if (GuaranteedTailCallOpt) { 2309 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2310 CCValAssign &VA = ArgLocs[i]; 2311 if (VA.isRegLoc()) 2312 continue; 2313 assert(VA.isMemLoc()); 2314 SDValue Arg = OutVals[i]; 2315 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2316 // Create frame index. 2317 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2318 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2319 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2320 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2321 2322 if (Flags.isByVal()) { 2323 // Copy relative to framepointer. 2324 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2325 if (StackPtr.getNode() == 0) 2326 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2327 getPointerTy()); 2328 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2329 2330 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2331 ArgChain, 2332 Flags, DAG, dl)); 2333 } else { 2334 // Store relative to framepointer. 2335 MemOpChains2.push_back( 2336 DAG.getStore(ArgChain, dl, Arg, FIN, 2337 MachinePointerInfo::getFixedStack(FI), 2338 false, false, 0)); 2339 } 2340 } 2341 } 2342 2343 if (!MemOpChains2.empty()) 2344 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2345 &MemOpChains2[0], MemOpChains2.size()); 2346 2347 // Copy arguments to their registers. 2348 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2349 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2350 RegsToPass[i].second, InFlag); 2351 InFlag = Chain.getValue(1); 2352 } 2353 InFlag =SDValue(); 2354 2355 // Store the return address to the appropriate stack slot. 2356 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2357 FPDiff, dl); 2358 } 2359 2360 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2361 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2362 // In the 64-bit large code model, we have to make all calls 2363 // through a register, since the call instruction's 32-bit 2364 // pc-relative offset may not be large enough to hold the whole 2365 // address. 2366 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2367 // If the callee is a GlobalAddress node (quite common, every direct call 2368 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2369 // it. 2370 2371 // We should use extra load for direct calls to dllimported functions in 2372 // non-JIT mode. 2373 const GlobalValue *GV = G->getGlobal(); 2374 if (!GV->hasDLLImportLinkage()) { 2375 unsigned char OpFlags = 0; 2376 bool ExtraLoad = false; 2377 unsigned WrapperKind = ISD::DELETED_NODE; 2378 2379 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2380 // external symbols most go through the PLT in PIC mode. If the symbol 2381 // has hidden or protected visibility, or if it is static or local, then 2382 // we don't need to use the PLT - we can directly call it. 2383 if (Subtarget->isTargetELF() && 2384 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2385 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2386 OpFlags = X86II::MO_PLT; 2387 } else if (Subtarget->isPICStyleStubAny() && 2388 (GV->isDeclaration() || GV->isWeakForLinker()) && 2389 (!Subtarget->getTargetTriple().isMacOSX() || 2390 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2391 // PC-relative references to external symbols should go through $stub, 2392 // unless we're building with the leopard linker or later, which 2393 // automatically synthesizes these stubs. 2394 OpFlags = X86II::MO_DARWIN_STUB; 2395 } else if (Subtarget->isPICStyleRIPRel() && 2396 isa<Function>(GV) && 2397 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2398 // If the function is marked as non-lazy, generate an indirect call 2399 // which loads from the GOT directly. This avoids runtime overhead 2400 // at the cost of eager binding (and one extra byte of encoding). 2401 OpFlags = X86II::MO_GOTPCREL; 2402 WrapperKind = X86ISD::WrapperRIP; 2403 ExtraLoad = true; 2404 } 2405 2406 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2407 G->getOffset(), OpFlags); 2408 2409 // Add a wrapper if needed. 2410 if (WrapperKind != ISD::DELETED_NODE) 2411 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2412 // Add extra indirection if needed. 2413 if (ExtraLoad) 2414 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2415 MachinePointerInfo::getGOT(), 2416 false, false, false, 0); 2417 } 2418 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2419 unsigned char OpFlags = 0; 2420 2421 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2422 // external symbols should go through the PLT. 2423 if (Subtarget->isTargetELF() && 2424 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2425 OpFlags = X86II::MO_PLT; 2426 } else if (Subtarget->isPICStyleStubAny() && 2427 (!Subtarget->getTargetTriple().isMacOSX() || 2428 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2429 // PC-relative references to external symbols should go through $stub, 2430 // unless we're building with the leopard linker or later, which 2431 // automatically synthesizes these stubs. 2432 OpFlags = X86II::MO_DARWIN_STUB; 2433 } 2434 2435 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2436 OpFlags); 2437 } 2438 2439 // Returns a chain & a flag for retval copy to use. 2440 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2441 SmallVector<SDValue, 8> Ops; 2442 2443 if (!IsSibcall && isTailCall) { 2444 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2445 DAG.getIntPtrConstant(0, true), InFlag); 2446 InFlag = Chain.getValue(1); 2447 } 2448 2449 Ops.push_back(Chain); 2450 Ops.push_back(Callee); 2451 2452 if (isTailCall) 2453 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2454 2455 // Add argument registers to the end of the list so that they are known live 2456 // into the call. 2457 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2458 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2459 RegsToPass[i].second.getValueType())); 2460 2461 // Add an implicit use GOT pointer in EBX. 2462 if (!isTailCall && Subtarget->isPICStyleGOT()) 2463 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2464 2465 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2466 if (Is64Bit && isVarArg && !IsWin64) 2467 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2468 2469 if (InFlag.getNode()) 2470 Ops.push_back(InFlag); 2471 2472 if (isTailCall) { 2473 // We used to do: 2474 //// If this is the first return lowered for this function, add the regs 2475 //// to the liveout set for the function. 2476 // This isn't right, although it's probably harmless on x86; liveouts 2477 // should be computed from returns not tail calls. Consider a void 2478 // function making a tail call to a function returning int. 2479 return DAG.getNode(X86ISD::TC_RETURN, dl, 2480 NodeTys, &Ops[0], Ops.size()); 2481 } 2482 2483 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2484 InFlag = Chain.getValue(1); 2485 2486 // Create the CALLSEQ_END node. 2487 unsigned NumBytesForCalleeToPush; 2488 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2489 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2490 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2491 // If this is a call to a struct-return function, the callee 2492 // pops the hidden struct pointer, so we have to push it back. 2493 // This is common for Darwin/X86, Linux & Mingw32 targets. 2494 NumBytesForCalleeToPush = 4; 2495 else 2496 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2497 2498 // Returns a flag for retval copy to use. 2499 if (!IsSibcall) { 2500 Chain = DAG.getCALLSEQ_END(Chain, 2501 DAG.getIntPtrConstant(NumBytes, true), 2502 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2503 true), 2504 InFlag); 2505 InFlag = Chain.getValue(1); 2506 } 2507 2508 // Handle result values, copying them out of physregs into vregs that we 2509 // return. 2510 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2511 Ins, dl, DAG, InVals); 2512} 2513 2514 2515//===----------------------------------------------------------------------===// 2516// Fast Calling Convention (tail call) implementation 2517//===----------------------------------------------------------------------===// 2518 2519// Like std call, callee cleans arguments, convention except that ECX is 2520// reserved for storing the tail called function address. Only 2 registers are 2521// free for argument passing (inreg). Tail call optimization is performed 2522// provided: 2523// * tailcallopt is enabled 2524// * caller/callee are fastcc 2525// On X86_64 architecture with GOT-style position independent code only local 2526// (within module) calls are supported at the moment. 2527// To keep the stack aligned according to platform abi the function 2528// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2529// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2530// If a tail called function callee has more arguments than the caller the 2531// caller needs to make sure that there is room to move the RETADDR to. This is 2532// achieved by reserving an area the size of the argument delta right after the 2533// original REtADDR, but before the saved framepointer or the spilled registers 2534// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2535// stack layout: 2536// arg1 2537// arg2 2538// RETADDR 2539// [ new RETADDR 2540// move area ] 2541// (possible EBP) 2542// ESI 2543// EDI 2544// local1 .. 2545 2546/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2547/// for a 16 byte align requirement. 2548unsigned 2549X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2550 SelectionDAG& DAG) const { 2551 MachineFunction &MF = DAG.getMachineFunction(); 2552 const TargetMachine &TM = MF.getTarget(); 2553 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2554 unsigned StackAlignment = TFI.getStackAlignment(); 2555 uint64_t AlignMask = StackAlignment - 1; 2556 int64_t Offset = StackSize; 2557 uint64_t SlotSize = TD->getPointerSize(); 2558 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2559 // Number smaller than 12 so just add the difference. 2560 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2561 } else { 2562 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2563 Offset = ((~AlignMask) & Offset) + StackAlignment + 2564 (StackAlignment-SlotSize); 2565 } 2566 return Offset; 2567} 2568 2569/// MatchingStackOffset - Return true if the given stack call argument is 2570/// already available in the same position (relatively) of the caller's 2571/// incoming argument stack. 2572static 2573bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2574 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2575 const X86InstrInfo *TII) { 2576 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2577 int FI = INT_MAX; 2578 if (Arg.getOpcode() == ISD::CopyFromReg) { 2579 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2580 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2581 return false; 2582 MachineInstr *Def = MRI->getVRegDef(VR); 2583 if (!Def) 2584 return false; 2585 if (!Flags.isByVal()) { 2586 if (!TII->isLoadFromStackSlot(Def, FI)) 2587 return false; 2588 } else { 2589 unsigned Opcode = Def->getOpcode(); 2590 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2591 Def->getOperand(1).isFI()) { 2592 FI = Def->getOperand(1).getIndex(); 2593 Bytes = Flags.getByValSize(); 2594 } else 2595 return false; 2596 } 2597 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2598 if (Flags.isByVal()) 2599 // ByVal argument is passed in as a pointer but it's now being 2600 // dereferenced. e.g. 2601 // define @foo(%struct.X* %A) { 2602 // tail call @bar(%struct.X* byval %A) 2603 // } 2604 return false; 2605 SDValue Ptr = Ld->getBasePtr(); 2606 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2607 if (!FINode) 2608 return false; 2609 FI = FINode->getIndex(); 2610 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2611 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2612 FI = FINode->getIndex(); 2613 Bytes = Flags.getByValSize(); 2614 } else 2615 return false; 2616 2617 assert(FI != INT_MAX); 2618 if (!MFI->isFixedObjectIndex(FI)) 2619 return false; 2620 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2621} 2622 2623/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2624/// for tail call optimization. Targets which want to do tail call 2625/// optimization should implement this function. 2626bool 2627X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2628 CallingConv::ID CalleeCC, 2629 bool isVarArg, 2630 bool isCalleeStructRet, 2631 bool isCallerStructRet, 2632 const SmallVectorImpl<ISD::OutputArg> &Outs, 2633 const SmallVectorImpl<SDValue> &OutVals, 2634 const SmallVectorImpl<ISD::InputArg> &Ins, 2635 SelectionDAG& DAG) const { 2636 if (!IsTailCallConvention(CalleeCC) && 2637 CalleeCC != CallingConv::C) 2638 return false; 2639 2640 // If -tailcallopt is specified, make fastcc functions tail-callable. 2641 const MachineFunction &MF = DAG.getMachineFunction(); 2642 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2643 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2644 bool CCMatch = CallerCC == CalleeCC; 2645 2646 if (GuaranteedTailCallOpt) { 2647 if (IsTailCallConvention(CalleeCC) && CCMatch) 2648 return true; 2649 return false; 2650 } 2651 2652 // Look for obvious safe cases to perform tail call optimization that do not 2653 // require ABI changes. This is what gcc calls sibcall. 2654 2655 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2656 // emit a special epilogue. 2657 if (RegInfo->needsStackRealignment(MF)) 2658 return false; 2659 2660 // Also avoid sibcall optimization if either caller or callee uses struct 2661 // return semantics. 2662 if (isCalleeStructRet || isCallerStructRet) 2663 return false; 2664 2665 // An stdcall caller is expected to clean up its arguments; the callee 2666 // isn't going to do that. 2667 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2668 return false; 2669 2670 // Do not sibcall optimize vararg calls unless all arguments are passed via 2671 // registers. 2672 if (isVarArg && !Outs.empty()) { 2673 2674 // Optimizing for varargs on Win64 is unlikely to be safe without 2675 // additional testing. 2676 if (Subtarget->isTargetWin64()) 2677 return false; 2678 2679 SmallVector<CCValAssign, 16> ArgLocs; 2680 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2681 getTargetMachine(), ArgLocs, *DAG.getContext()); 2682 2683 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2684 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2685 if (!ArgLocs[i].isRegLoc()) 2686 return false; 2687 } 2688 2689 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2690 // Therefore if it's not used by the call it is not safe to optimize this into 2691 // a sibcall. 2692 bool Unused = false; 2693 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2694 if (!Ins[i].Used) { 2695 Unused = true; 2696 break; 2697 } 2698 } 2699 if (Unused) { 2700 SmallVector<CCValAssign, 16> RVLocs; 2701 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2702 getTargetMachine(), RVLocs, *DAG.getContext()); 2703 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2704 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2705 CCValAssign &VA = RVLocs[i]; 2706 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2707 return false; 2708 } 2709 } 2710 2711 // If the calling conventions do not match, then we'd better make sure the 2712 // results are returned in the same way as what the caller expects. 2713 if (!CCMatch) { 2714 SmallVector<CCValAssign, 16> RVLocs1; 2715 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2716 getTargetMachine(), RVLocs1, *DAG.getContext()); 2717 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2718 2719 SmallVector<CCValAssign, 16> RVLocs2; 2720 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2721 getTargetMachine(), RVLocs2, *DAG.getContext()); 2722 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2723 2724 if (RVLocs1.size() != RVLocs2.size()) 2725 return false; 2726 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2727 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2728 return false; 2729 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2730 return false; 2731 if (RVLocs1[i].isRegLoc()) { 2732 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2733 return false; 2734 } else { 2735 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2736 return false; 2737 } 2738 } 2739 } 2740 2741 // If the callee takes no arguments then go on to check the results of the 2742 // call. 2743 if (!Outs.empty()) { 2744 // Check if stack adjustment is needed. For now, do not do this if any 2745 // argument is passed on the stack. 2746 SmallVector<CCValAssign, 16> ArgLocs; 2747 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2748 getTargetMachine(), ArgLocs, *DAG.getContext()); 2749 2750 // Allocate shadow area for Win64 2751 if (Subtarget->isTargetWin64()) { 2752 CCInfo.AllocateStack(32, 8); 2753 } 2754 2755 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2756 if (CCInfo.getNextStackOffset()) { 2757 MachineFunction &MF = DAG.getMachineFunction(); 2758 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2759 return false; 2760 2761 // Check if the arguments are already laid out in the right way as 2762 // the caller's fixed stack objects. 2763 MachineFrameInfo *MFI = MF.getFrameInfo(); 2764 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2765 const X86InstrInfo *TII = 2766 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2767 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2768 CCValAssign &VA = ArgLocs[i]; 2769 SDValue Arg = OutVals[i]; 2770 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2771 if (VA.getLocInfo() == CCValAssign::Indirect) 2772 return false; 2773 if (!VA.isRegLoc()) { 2774 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2775 MFI, MRI, TII)) 2776 return false; 2777 } 2778 } 2779 } 2780 2781 // If the tailcall address may be in a register, then make sure it's 2782 // possible to register allocate for it. In 32-bit, the call address can 2783 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2784 // callee-saved registers are restored. These happen to be the same 2785 // registers used to pass 'inreg' arguments so watch out for those. 2786 if (!Subtarget->is64Bit() && 2787 !isa<GlobalAddressSDNode>(Callee) && 2788 !isa<ExternalSymbolSDNode>(Callee)) { 2789 unsigned NumInRegs = 0; 2790 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2791 CCValAssign &VA = ArgLocs[i]; 2792 if (!VA.isRegLoc()) 2793 continue; 2794 unsigned Reg = VA.getLocReg(); 2795 switch (Reg) { 2796 default: break; 2797 case X86::EAX: case X86::EDX: case X86::ECX: 2798 if (++NumInRegs == 3) 2799 return false; 2800 break; 2801 } 2802 } 2803 } 2804 } 2805 2806 return true; 2807} 2808 2809FastISel * 2810X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2811 return X86::createFastISel(funcInfo); 2812} 2813 2814 2815//===----------------------------------------------------------------------===// 2816// Other Lowering Hooks 2817//===----------------------------------------------------------------------===// 2818 2819static bool MayFoldLoad(SDValue Op) { 2820 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2821} 2822 2823static bool MayFoldIntoStore(SDValue Op) { 2824 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2825} 2826 2827static bool isTargetShuffle(unsigned Opcode) { 2828 switch(Opcode) { 2829 default: return false; 2830 case X86ISD::PSHUFD: 2831 case X86ISD::PSHUFHW: 2832 case X86ISD::PSHUFLW: 2833 case X86ISD::SHUFPD: 2834 case X86ISD::PALIGN: 2835 case X86ISD::SHUFPS: 2836 case X86ISD::MOVLHPS: 2837 case X86ISD::MOVLHPD: 2838 case X86ISD::MOVHLPS: 2839 case X86ISD::MOVLPS: 2840 case X86ISD::MOVLPD: 2841 case X86ISD::MOVSHDUP: 2842 case X86ISD::MOVSLDUP: 2843 case X86ISD::MOVDDUP: 2844 case X86ISD::MOVSS: 2845 case X86ISD::MOVSD: 2846 case X86ISD::UNPCKLPS: 2847 case X86ISD::UNPCKLPD: 2848 case X86ISD::VUNPCKLPSY: 2849 case X86ISD::VUNPCKLPDY: 2850 case X86ISD::PUNPCKLWD: 2851 case X86ISD::PUNPCKLBW: 2852 case X86ISD::PUNPCKLDQ: 2853 case X86ISD::PUNPCKLQDQ: 2854 case X86ISD::UNPCKHPS: 2855 case X86ISD::UNPCKHPD: 2856 case X86ISD::VUNPCKHPSY: 2857 case X86ISD::VUNPCKHPDY: 2858 case X86ISD::PUNPCKHWD: 2859 case X86ISD::PUNPCKHBW: 2860 case X86ISD::PUNPCKHDQ: 2861 case X86ISD::PUNPCKHQDQ: 2862 case X86ISD::VPERMILPS: 2863 case X86ISD::VPERMILPSY: 2864 case X86ISD::VPERMILPD: 2865 case X86ISD::VPERMILPDY: 2866 case X86ISD::VPERM2F128: 2867 return true; 2868 } 2869 return false; 2870} 2871 2872static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2873 SDValue V1, SelectionDAG &DAG) { 2874 switch(Opc) { 2875 default: llvm_unreachable("Unknown x86 shuffle node"); 2876 case X86ISD::MOVSHDUP: 2877 case X86ISD::MOVSLDUP: 2878 case X86ISD::MOVDDUP: 2879 return DAG.getNode(Opc, dl, VT, V1); 2880 } 2881 2882 return SDValue(); 2883} 2884 2885static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2886 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2887 switch(Opc) { 2888 default: llvm_unreachable("Unknown x86 shuffle node"); 2889 case X86ISD::PSHUFD: 2890 case X86ISD::PSHUFHW: 2891 case X86ISD::PSHUFLW: 2892 case X86ISD::VPERMILPS: 2893 case X86ISD::VPERMILPSY: 2894 case X86ISD::VPERMILPD: 2895 case X86ISD::VPERMILPDY: 2896 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2897 } 2898 2899 return SDValue(); 2900} 2901 2902static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2903 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2904 switch(Opc) { 2905 default: llvm_unreachable("Unknown x86 shuffle node"); 2906 case X86ISD::PALIGN: 2907 case X86ISD::SHUFPD: 2908 case X86ISD::SHUFPS: 2909 case X86ISD::VPERM2F128: 2910 return DAG.getNode(Opc, dl, VT, V1, V2, 2911 DAG.getConstant(TargetMask, MVT::i8)); 2912 } 2913 return SDValue(); 2914} 2915 2916static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2917 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2918 switch(Opc) { 2919 default: llvm_unreachable("Unknown x86 shuffle node"); 2920 case X86ISD::MOVLHPS: 2921 case X86ISD::MOVLHPD: 2922 case X86ISD::MOVHLPS: 2923 case X86ISD::MOVLPS: 2924 case X86ISD::MOVLPD: 2925 case X86ISD::MOVSS: 2926 case X86ISD::MOVSD: 2927 case X86ISD::UNPCKLPS: 2928 case X86ISD::UNPCKLPD: 2929 case X86ISD::VUNPCKLPSY: 2930 case X86ISD::VUNPCKLPDY: 2931 case X86ISD::PUNPCKLWD: 2932 case X86ISD::PUNPCKLBW: 2933 case X86ISD::PUNPCKLDQ: 2934 case X86ISD::PUNPCKLQDQ: 2935 case X86ISD::UNPCKHPS: 2936 case X86ISD::UNPCKHPD: 2937 case X86ISD::VUNPCKHPSY: 2938 case X86ISD::VUNPCKHPDY: 2939 case X86ISD::PUNPCKHWD: 2940 case X86ISD::PUNPCKHBW: 2941 case X86ISD::PUNPCKHDQ: 2942 case X86ISD::PUNPCKHQDQ: 2943 return DAG.getNode(Opc, dl, VT, V1, V2); 2944 } 2945 return SDValue(); 2946} 2947 2948SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2949 MachineFunction &MF = DAG.getMachineFunction(); 2950 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2951 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2952 2953 if (ReturnAddrIndex == 0) { 2954 // Set up a frame object for the return address. 2955 uint64_t SlotSize = TD->getPointerSize(); 2956 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2957 false); 2958 FuncInfo->setRAIndex(ReturnAddrIndex); 2959 } 2960 2961 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2962} 2963 2964 2965bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2966 bool hasSymbolicDisplacement) { 2967 // Offset should fit into 32 bit immediate field. 2968 if (!isInt<32>(Offset)) 2969 return false; 2970 2971 // If we don't have a symbolic displacement - we don't have any extra 2972 // restrictions. 2973 if (!hasSymbolicDisplacement) 2974 return true; 2975 2976 // FIXME: Some tweaks might be needed for medium code model. 2977 if (M != CodeModel::Small && M != CodeModel::Kernel) 2978 return false; 2979 2980 // For small code model we assume that latest object is 16MB before end of 31 2981 // bits boundary. We may also accept pretty large negative constants knowing 2982 // that all objects are in the positive half of address space. 2983 if (M == CodeModel::Small && Offset < 16*1024*1024) 2984 return true; 2985 2986 // For kernel code model we know that all object resist in the negative half 2987 // of 32bits address space. We may not accept negative offsets, since they may 2988 // be just off and we may accept pretty large positive ones. 2989 if (M == CodeModel::Kernel && Offset > 0) 2990 return true; 2991 2992 return false; 2993} 2994 2995/// isCalleePop - Determines whether the callee is required to pop its 2996/// own arguments. Callee pop is necessary to support tail calls. 2997bool X86::isCalleePop(CallingConv::ID CallingConv, 2998 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 2999 if (IsVarArg) 3000 return false; 3001 3002 switch (CallingConv) { 3003 default: 3004 return false; 3005 case CallingConv::X86_StdCall: 3006 return !is64Bit; 3007 case CallingConv::X86_FastCall: 3008 return !is64Bit; 3009 case CallingConv::X86_ThisCall: 3010 return !is64Bit; 3011 case CallingConv::Fast: 3012 return TailCallOpt; 3013 case CallingConv::GHC: 3014 return TailCallOpt; 3015 } 3016} 3017 3018/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3019/// specific condition code, returning the condition code and the LHS/RHS of the 3020/// comparison to make. 3021static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3022 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3023 if (!isFP) { 3024 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3025 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3026 // X > -1 -> X == 0, jump !sign. 3027 RHS = DAG.getConstant(0, RHS.getValueType()); 3028 return X86::COND_NS; 3029 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3030 // X < 0 -> X == 0, jump on sign. 3031 return X86::COND_S; 3032 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3033 // X < 1 -> X <= 0 3034 RHS = DAG.getConstant(0, RHS.getValueType()); 3035 return X86::COND_LE; 3036 } 3037 } 3038 3039 switch (SetCCOpcode) { 3040 default: llvm_unreachable("Invalid integer condition!"); 3041 case ISD::SETEQ: return X86::COND_E; 3042 case ISD::SETGT: return X86::COND_G; 3043 case ISD::SETGE: return X86::COND_GE; 3044 case ISD::SETLT: return X86::COND_L; 3045 case ISD::SETLE: return X86::COND_LE; 3046 case ISD::SETNE: return X86::COND_NE; 3047 case ISD::SETULT: return X86::COND_B; 3048 case ISD::SETUGT: return X86::COND_A; 3049 case ISD::SETULE: return X86::COND_BE; 3050 case ISD::SETUGE: return X86::COND_AE; 3051 } 3052 } 3053 3054 // First determine if it is required or is profitable to flip the operands. 3055 3056 // If LHS is a foldable load, but RHS is not, flip the condition. 3057 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3058 !ISD::isNON_EXTLoad(RHS.getNode())) { 3059 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3060 std::swap(LHS, RHS); 3061 } 3062 3063 switch (SetCCOpcode) { 3064 default: break; 3065 case ISD::SETOLT: 3066 case ISD::SETOLE: 3067 case ISD::SETUGT: 3068 case ISD::SETUGE: 3069 std::swap(LHS, RHS); 3070 break; 3071 } 3072 3073 // On a floating point condition, the flags are set as follows: 3074 // ZF PF CF op 3075 // 0 | 0 | 0 | X > Y 3076 // 0 | 0 | 1 | X < Y 3077 // 1 | 0 | 0 | X == Y 3078 // 1 | 1 | 1 | unordered 3079 switch (SetCCOpcode) { 3080 default: llvm_unreachable("Condcode should be pre-legalized away"); 3081 case ISD::SETUEQ: 3082 case ISD::SETEQ: return X86::COND_E; 3083 case ISD::SETOLT: // flipped 3084 case ISD::SETOGT: 3085 case ISD::SETGT: return X86::COND_A; 3086 case ISD::SETOLE: // flipped 3087 case ISD::SETOGE: 3088 case ISD::SETGE: return X86::COND_AE; 3089 case ISD::SETUGT: // flipped 3090 case ISD::SETULT: 3091 case ISD::SETLT: return X86::COND_B; 3092 case ISD::SETUGE: // flipped 3093 case ISD::SETULE: 3094 case ISD::SETLE: return X86::COND_BE; 3095 case ISD::SETONE: 3096 case ISD::SETNE: return X86::COND_NE; 3097 case ISD::SETUO: return X86::COND_P; 3098 case ISD::SETO: return X86::COND_NP; 3099 case ISD::SETOEQ: 3100 case ISD::SETUNE: return X86::COND_INVALID; 3101 } 3102} 3103 3104/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3105/// code. Current x86 isa includes the following FP cmov instructions: 3106/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3107static bool hasFPCMov(unsigned X86CC) { 3108 switch (X86CC) { 3109 default: 3110 return false; 3111 case X86::COND_B: 3112 case X86::COND_BE: 3113 case X86::COND_E: 3114 case X86::COND_P: 3115 case X86::COND_A: 3116 case X86::COND_AE: 3117 case X86::COND_NE: 3118 case X86::COND_NP: 3119 return true; 3120 } 3121} 3122 3123/// isFPImmLegal - Returns true if the target can instruction select the 3124/// specified FP immediate natively. If false, the legalizer will 3125/// materialize the FP immediate as a load from a constant pool. 3126bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3127 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3128 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3129 return true; 3130 } 3131 return false; 3132} 3133 3134/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3135/// the specified range (L, H]. 3136static bool isUndefOrInRange(int Val, int Low, int Hi) { 3137 return (Val < 0) || (Val >= Low && Val < Hi); 3138} 3139 3140/// isUndefOrInRange - Return true if every element in Mask, begining 3141/// from position Pos and ending in Pos+Size, falls within the specified 3142/// range (L, L+Pos]. or is undef. 3143static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3144 int Pos, int Size, int Low, int Hi) { 3145 for (int i = Pos, e = Pos+Size; i != e; ++i) 3146 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3147 return false; 3148 return true; 3149} 3150 3151/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3152/// specified value. 3153static bool isUndefOrEqual(int Val, int CmpVal) { 3154 if (Val < 0 || Val == CmpVal) 3155 return true; 3156 return false; 3157} 3158 3159/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3160/// from position Pos and ending in Pos+Size, falls within the specified 3161/// sequential range (L, L+Pos]. or is undef. 3162static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3163 int Pos, int Size, int Low) { 3164 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3165 if (!isUndefOrEqual(Mask[i], Low)) 3166 return false; 3167 return true; 3168} 3169 3170/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3171/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3172/// the second operand. 3173static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3174 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3175 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3176 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3177 return (Mask[0] < 2 && Mask[1] < 2); 3178 return false; 3179} 3180 3181bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3182 SmallVector<int, 8> M; 3183 N->getMask(M); 3184 return ::isPSHUFDMask(M, N->getValueType(0)); 3185} 3186 3187/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3188/// is suitable for input to PSHUFHW. 3189static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3190 if (VT != MVT::v8i16) 3191 return false; 3192 3193 // Lower quadword copied in order or undef. 3194 for (int i = 0; i != 4; ++i) 3195 if (Mask[i] >= 0 && Mask[i] != i) 3196 return false; 3197 3198 // Upper quadword shuffled. 3199 for (int i = 4; i != 8; ++i) 3200 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3201 return false; 3202 3203 return true; 3204} 3205 3206bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3207 SmallVector<int, 8> M; 3208 N->getMask(M); 3209 return ::isPSHUFHWMask(M, N->getValueType(0)); 3210} 3211 3212/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3213/// is suitable for input to PSHUFLW. 3214static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3215 if (VT != MVT::v8i16) 3216 return false; 3217 3218 // Upper quadword copied in order. 3219 for (int i = 4; i != 8; ++i) 3220 if (Mask[i] >= 0 && Mask[i] != i) 3221 return false; 3222 3223 // Lower quadword shuffled. 3224 for (int i = 0; i != 4; ++i) 3225 if (Mask[i] >= 4) 3226 return false; 3227 3228 return true; 3229} 3230 3231bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3232 SmallVector<int, 8> M; 3233 N->getMask(M); 3234 return ::isPSHUFLWMask(M, N->getValueType(0)); 3235} 3236 3237/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3238/// is suitable for input to PALIGNR. 3239static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3240 bool hasSSSE3OrAVX) { 3241 int i, e = VT.getVectorNumElements(); 3242 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3243 return false; 3244 3245 // Do not handle v2i64 / v2f64 shuffles with palignr. 3246 if (e < 4 || !hasSSSE3OrAVX) 3247 return false; 3248 3249 for (i = 0; i != e; ++i) 3250 if (Mask[i] >= 0) 3251 break; 3252 3253 // All undef, not a palignr. 3254 if (i == e) 3255 return false; 3256 3257 // Make sure we're shifting in the right direction. 3258 if (Mask[i] <= i) 3259 return false; 3260 3261 int s = Mask[i] - i; 3262 3263 // Check the rest of the elements to see if they are consecutive. 3264 for (++i; i != e; ++i) { 3265 int m = Mask[i]; 3266 if (m >= 0 && m != s+i) 3267 return false; 3268 } 3269 return true; 3270} 3271 3272/// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand 3273/// specifies a shuffle of elements that is suitable for input to 256-bit 3274/// VSHUFPSY. 3275static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3276 const X86Subtarget *Subtarget) { 3277 int NumElems = VT.getVectorNumElements(); 3278 3279 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3280 return false; 3281 3282 if (NumElems != 8) 3283 return false; 3284 3285 // VSHUFPSY divides the resulting vector into 4 chunks. 3286 // The sources are also splitted into 4 chunks, and each destination 3287 // chunk must come from a different source chunk. 3288 // 3289 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3290 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3291 // 3292 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3293 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3294 // 3295 int QuarterSize = NumElems/4; 3296 int HalfSize = QuarterSize*2; 3297 for (int i = 0; i < QuarterSize; ++i) 3298 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3299 return false; 3300 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3301 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3302 return false; 3303 3304 // The mask of the second half must be the same as the first but with 3305 // the appropriate offsets. This works in the same way as VPERMILPS 3306 // works with masks. 3307 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { 3308 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3309 return false; 3310 int FstHalfIdx = i-HalfSize; 3311 if (Mask[FstHalfIdx] < 0) 3312 continue; 3313 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3314 return false; 3315 } 3316 for (int i = QuarterSize*3; i < NumElems; ++i) { 3317 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3318 return false; 3319 int FstHalfIdx = i-HalfSize; 3320 if (Mask[FstHalfIdx] < 0) 3321 continue; 3322 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3323 return false; 3324 3325 } 3326 3327 return true; 3328} 3329 3330/// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle 3331/// the specified VECTOR_MASK mask with VSHUFPSY instruction. 3332static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) { 3333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3334 EVT VT = SVOp->getValueType(0); 3335 int NumElems = VT.getVectorNumElements(); 3336 3337 assert(NumElems == 8 && VT.getSizeInBits() == 256 && 3338 "Only supports v8i32 and v8f32 types"); 3339 3340 int HalfSize = NumElems/2; 3341 unsigned Mask = 0; 3342 for (int i = 0; i != NumElems ; ++i) { 3343 if (SVOp->getMaskElt(i) < 0) 3344 continue; 3345 // The mask of the first half must be equal to the second one. 3346 unsigned Shamt = (i%HalfSize)*2; 3347 unsigned Elt = SVOp->getMaskElt(i) % HalfSize; 3348 Mask |= Elt << Shamt; 3349 } 3350 3351 return Mask; 3352} 3353 3354/// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand 3355/// specifies a shuffle of elements that is suitable for input to 256-bit 3356/// VSHUFPDY. This shuffle doesn't have the same restriction as the PS 3357/// version and the mask of the second half isn't binded with the first 3358/// one. 3359static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3360 const X86Subtarget *Subtarget) { 3361 int NumElems = VT.getVectorNumElements(); 3362 3363 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3364 return false; 3365 3366 if (NumElems != 4) 3367 return false; 3368 3369 // VSHUFPSY divides the resulting vector into 4 chunks. 3370 // The sources are also splitted into 4 chunks, and each destination 3371 // chunk must come from a different source chunk. 3372 // 3373 // SRC1 => X3 X2 X1 X0 3374 // SRC2 => Y3 Y2 Y1 Y0 3375 // 3376 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0 3377 // 3378 int QuarterSize = NumElems/4; 3379 int HalfSize = QuarterSize*2; 3380 for (int i = 0; i < QuarterSize; ++i) 3381 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3382 return false; 3383 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3384 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3385 return false; 3386 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) 3387 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3388 return false; 3389 for (int i = QuarterSize*3; i < NumElems; ++i) 3390 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3391 return false; 3392 3393 return true; 3394} 3395 3396/// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle 3397/// the specified VECTOR_MASK mask with VSHUFPDY instruction. 3398static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) { 3399 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3400 EVT VT = SVOp->getValueType(0); 3401 int NumElems = VT.getVectorNumElements(); 3402 3403 assert(NumElems == 4 && VT.getSizeInBits() == 256 && 3404 "Only supports v4i64 and v4f64 types"); 3405 3406 int HalfSize = NumElems/2; 3407 unsigned Mask = 0; 3408 for (int i = 0; i != NumElems ; ++i) { 3409 if (SVOp->getMaskElt(i) < 0) 3410 continue; 3411 int Elt = SVOp->getMaskElt(i) % HalfSize; 3412 Mask |= Elt << i; 3413 } 3414 3415 return Mask; 3416} 3417 3418/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3419/// specifies a shuffle of elements that is suitable for input to 128-bit 3420/// SHUFPS and SHUFPD. 3421static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3422 int NumElems = VT.getVectorNumElements(); 3423 3424 if (VT.getSizeInBits() != 128) 3425 return false; 3426 3427 if (NumElems != 2 && NumElems != 4) 3428 return false; 3429 3430 int Half = NumElems / 2; 3431 for (int i = 0; i < Half; ++i) 3432 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3433 return false; 3434 for (int i = Half; i < NumElems; ++i) 3435 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3436 return false; 3437 3438 return true; 3439} 3440 3441bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3442 SmallVector<int, 8> M; 3443 N->getMask(M); 3444 return ::isSHUFPMask(M, N->getValueType(0)); 3445} 3446 3447/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3448/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3449/// half elements to come from vector 1 (which would equal the dest.) and 3450/// the upper half to come from vector 2. 3451static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3452 int NumElems = VT.getVectorNumElements(); 3453 3454 if (NumElems != 2 && NumElems != 4) 3455 return false; 3456 3457 int Half = NumElems / 2; 3458 for (int i = 0; i < Half; ++i) 3459 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3460 return false; 3461 for (int i = Half; i < NumElems; ++i) 3462 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3463 return false; 3464 return true; 3465} 3466 3467static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3468 SmallVector<int, 8> M; 3469 N->getMask(M); 3470 return isCommutedSHUFPMask(M, N->getValueType(0)); 3471} 3472 3473/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3474/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3475bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3476 EVT VT = N->getValueType(0); 3477 unsigned NumElems = VT.getVectorNumElements(); 3478 3479 if (VT.getSizeInBits() != 128) 3480 return false; 3481 3482 if (NumElems != 4) 3483 return false; 3484 3485 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3486 return isUndefOrEqual(N->getMaskElt(0), 6) && 3487 isUndefOrEqual(N->getMaskElt(1), 7) && 3488 isUndefOrEqual(N->getMaskElt(2), 2) && 3489 isUndefOrEqual(N->getMaskElt(3), 3); 3490} 3491 3492/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3493/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3494/// <2, 3, 2, 3> 3495bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3496 EVT VT = N->getValueType(0); 3497 unsigned NumElems = VT.getVectorNumElements(); 3498 3499 if (VT.getSizeInBits() != 128) 3500 return false; 3501 3502 if (NumElems != 4) 3503 return false; 3504 3505 return isUndefOrEqual(N->getMaskElt(0), 2) && 3506 isUndefOrEqual(N->getMaskElt(1), 3) && 3507 isUndefOrEqual(N->getMaskElt(2), 2) && 3508 isUndefOrEqual(N->getMaskElt(3), 3); 3509} 3510 3511/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3512/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3513bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3514 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3515 3516 if (NumElems != 2 && NumElems != 4) 3517 return false; 3518 3519 for (unsigned i = 0; i < NumElems/2; ++i) 3520 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3521 return false; 3522 3523 for (unsigned i = NumElems/2; i < NumElems; ++i) 3524 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3525 return false; 3526 3527 return true; 3528} 3529 3530/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3531/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3532bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3533 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3534 3535 if ((NumElems != 2 && NumElems != 4) 3536 || N->getValueType(0).getSizeInBits() > 128) 3537 return false; 3538 3539 for (unsigned i = 0; i < NumElems/2; ++i) 3540 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3541 return false; 3542 3543 for (unsigned i = 0; i < NumElems/2; ++i) 3544 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3545 return false; 3546 3547 return true; 3548} 3549 3550/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3551/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3552static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3553 bool V2IsSplat = false) { 3554 int NumElts = VT.getVectorNumElements(); 3555 3556 assert((VT.is128BitVector() || VT.is256BitVector()) && 3557 "Unsupported vector type for unpckh"); 3558 3559 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3560 return false; 3561 3562 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3563 // independently on 128-bit lanes. 3564 unsigned NumLanes = VT.getSizeInBits()/128; 3565 unsigned NumLaneElts = NumElts/NumLanes; 3566 3567 unsigned Start = 0; 3568 unsigned End = NumLaneElts; 3569 for (unsigned s = 0; s < NumLanes; ++s) { 3570 for (unsigned i = Start, j = s * NumLaneElts; 3571 i != End; 3572 i += 2, ++j) { 3573 int BitI = Mask[i]; 3574 int BitI1 = Mask[i+1]; 3575 if (!isUndefOrEqual(BitI, j)) 3576 return false; 3577 if (V2IsSplat) { 3578 if (!isUndefOrEqual(BitI1, NumElts)) 3579 return false; 3580 } else { 3581 if (!isUndefOrEqual(BitI1, j + NumElts)) 3582 return false; 3583 } 3584 } 3585 // Process the next 128 bits. 3586 Start += NumLaneElts; 3587 End += NumLaneElts; 3588 } 3589 3590 return true; 3591} 3592 3593bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3594 SmallVector<int, 8> M; 3595 N->getMask(M); 3596 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3597} 3598 3599/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3600/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3601static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3602 bool V2IsSplat = false) { 3603 int NumElts = VT.getVectorNumElements(); 3604 3605 assert((VT.is128BitVector() || VT.is256BitVector()) && 3606 "Unsupported vector type for unpckh"); 3607 3608 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3609 return false; 3610 3611 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3612 // independently on 128-bit lanes. 3613 unsigned NumLanes = VT.getSizeInBits()/128; 3614 unsigned NumLaneElts = NumElts/NumLanes; 3615 3616 unsigned Start = 0; 3617 unsigned End = NumLaneElts; 3618 for (unsigned l = 0; l != NumLanes; ++l) { 3619 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3620 i != End; i += 2, ++j) { 3621 int BitI = Mask[i]; 3622 int BitI1 = Mask[i+1]; 3623 if (!isUndefOrEqual(BitI, j)) 3624 return false; 3625 if (V2IsSplat) { 3626 if (isUndefOrEqual(BitI1, NumElts)) 3627 return false; 3628 } else { 3629 if (!isUndefOrEqual(BitI1, j+NumElts)) 3630 return false; 3631 } 3632 } 3633 // Process the next 128 bits. 3634 Start += NumLaneElts; 3635 End += NumLaneElts; 3636 } 3637 return true; 3638} 3639 3640bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3641 SmallVector<int, 8> M; 3642 N->getMask(M); 3643 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3644} 3645 3646/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3647/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3648/// <0, 0, 1, 1> 3649static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3650 int NumElems = VT.getVectorNumElements(); 3651 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3652 return false; 3653 3654 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3655 // FIXME: Need a better way to get rid of this, there's no latency difference 3656 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3657 // the former later. We should also remove the "_undef" special mask. 3658 if (NumElems == 4 && VT.getSizeInBits() == 256) 3659 return false; 3660 3661 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3662 // independently on 128-bit lanes. 3663 unsigned NumLanes = VT.getSizeInBits() / 128; 3664 unsigned NumLaneElts = NumElems / NumLanes; 3665 3666 for (unsigned s = 0; s < NumLanes; ++s) { 3667 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3668 i != NumLaneElts * (s + 1); 3669 i += 2, ++j) { 3670 int BitI = Mask[i]; 3671 int BitI1 = Mask[i+1]; 3672 3673 if (!isUndefOrEqual(BitI, j)) 3674 return false; 3675 if (!isUndefOrEqual(BitI1, j)) 3676 return false; 3677 } 3678 } 3679 3680 return true; 3681} 3682 3683bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3684 SmallVector<int, 8> M; 3685 N->getMask(M); 3686 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3687} 3688 3689/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3690/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3691/// <2, 2, 3, 3> 3692static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3693 int NumElems = VT.getVectorNumElements(); 3694 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3695 return false; 3696 3697 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3698 int BitI = Mask[i]; 3699 int BitI1 = Mask[i+1]; 3700 if (!isUndefOrEqual(BitI, j)) 3701 return false; 3702 if (!isUndefOrEqual(BitI1, j)) 3703 return false; 3704 } 3705 return true; 3706} 3707 3708bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3709 SmallVector<int, 8> M; 3710 N->getMask(M); 3711 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3712} 3713 3714/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3715/// specifies a shuffle of elements that is suitable for input to MOVSS, 3716/// MOVSD, and MOVD, i.e. setting the lowest element. 3717static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3718 if (VT.getVectorElementType().getSizeInBits() < 32) 3719 return false; 3720 3721 int NumElts = VT.getVectorNumElements(); 3722 3723 if (!isUndefOrEqual(Mask[0], NumElts)) 3724 return false; 3725 3726 for (int i = 1; i < NumElts; ++i) 3727 if (!isUndefOrEqual(Mask[i], i)) 3728 return false; 3729 3730 return true; 3731} 3732 3733bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3734 SmallVector<int, 8> M; 3735 N->getMask(M); 3736 return ::isMOVLMask(M, N->getValueType(0)); 3737} 3738 3739/// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered 3740/// as permutations between 128-bit chunks or halves. As an example: this 3741/// shuffle bellow: 3742/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3743/// The first half comes from the second half of V1 and the second half from the 3744/// the second half of V2. 3745static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3746 const X86Subtarget *Subtarget) { 3747 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3748 return false; 3749 3750 // The shuffle result is divided into half A and half B. In total the two 3751 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3752 // B must come from C, D, E or F. 3753 int HalfSize = VT.getVectorNumElements()/2; 3754 bool MatchA = false, MatchB = false; 3755 3756 // Check if A comes from one of C, D, E, F. 3757 for (int Half = 0; Half < 4; ++Half) { 3758 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3759 MatchA = true; 3760 break; 3761 } 3762 } 3763 3764 // Check if B comes from one of C, D, E, F. 3765 for (int Half = 0; Half < 4; ++Half) { 3766 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3767 MatchB = true; 3768 break; 3769 } 3770 } 3771 3772 return MatchA && MatchB; 3773} 3774 3775/// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle 3776/// the specified VECTOR_MASK mask with VPERM2F128 instructions. 3777static unsigned getShuffleVPERM2F128Immediate(SDNode *N) { 3778 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3779 EVT VT = SVOp->getValueType(0); 3780 3781 int HalfSize = VT.getVectorNumElements()/2; 3782 3783 int FstHalf = 0, SndHalf = 0; 3784 for (int i = 0; i < HalfSize; ++i) { 3785 if (SVOp->getMaskElt(i) > 0) { 3786 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3787 break; 3788 } 3789 } 3790 for (int i = HalfSize; i < HalfSize*2; ++i) { 3791 if (SVOp->getMaskElt(i) > 0) { 3792 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3793 break; 3794 } 3795 } 3796 3797 return (FstHalf | (SndHalf << 4)); 3798} 3799 3800/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3801/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3802/// Note that VPERMIL mask matching is different depending whether theunderlying 3803/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3804/// to the same elements of the low, but to the higher half of the source. 3805/// In VPERMILPD the two lanes could be shuffled independently of each other 3806/// with the same restriction that lanes can't be crossed. 3807static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3808 const X86Subtarget *Subtarget) { 3809 int NumElts = VT.getVectorNumElements(); 3810 int NumLanes = VT.getSizeInBits()/128; 3811 3812 if (!Subtarget->hasAVX()) 3813 return false; 3814 3815 // Only match 256-bit with 64-bit types 3816 if (VT.getSizeInBits() != 256 || NumElts != 4) 3817 return false; 3818 3819 // The mask on the high lane is independent of the low. Both can match 3820 // any element in inside its own lane, but can't cross. 3821 int LaneSize = NumElts/NumLanes; 3822 for (int l = 0; l < NumLanes; ++l) 3823 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3824 int LaneStart = l*LaneSize; 3825 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3826 return false; 3827 } 3828 3829 return true; 3830} 3831 3832/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3833/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3834/// Note that VPERMIL mask matching is different depending whether theunderlying 3835/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3836/// to the same elements of the low, but to the higher half of the source. 3837/// In VPERMILPD the two lanes could be shuffled independently of each other 3838/// with the same restriction that lanes can't be crossed. 3839static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3840 const X86Subtarget *Subtarget) { 3841 unsigned NumElts = VT.getVectorNumElements(); 3842 unsigned NumLanes = VT.getSizeInBits()/128; 3843 3844 if (!Subtarget->hasAVX()) 3845 return false; 3846 3847 // Only match 256-bit with 32-bit types 3848 if (VT.getSizeInBits() != 256 || NumElts != 8) 3849 return false; 3850 3851 // The mask on the high lane should be the same as the low. Actually, 3852 // they can differ if any of the corresponding index in a lane is undef 3853 // and the other stays in range. 3854 int LaneSize = NumElts/NumLanes; 3855 for (int i = 0; i < LaneSize; ++i) { 3856 int HighElt = i+LaneSize; 3857 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts); 3858 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize); 3859 3860 if (!HighValid || !LowValid) 3861 return false; 3862 if (Mask[i] < 0 || Mask[HighElt] < 0) 3863 continue; 3864 if (Mask[HighElt]-Mask[i] != LaneSize) 3865 return false; 3866 } 3867 3868 return true; 3869} 3870 3871/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3872/// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3873static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3875 EVT VT = SVOp->getValueType(0); 3876 3877 int NumElts = VT.getVectorNumElements(); 3878 int NumLanes = VT.getSizeInBits()/128; 3879 int LaneSize = NumElts/NumLanes; 3880 3881 // Although the mask is equal for both lanes do it twice to get the cases 3882 // where a mask will match because the same mask element is undef on the 3883 // first half but valid on the second. This would get pathological cases 3884 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3885 unsigned Mask = 0; 3886 for (int l = 0; l < NumLanes; ++l) { 3887 for (int i = 0; i < LaneSize; ++i) { 3888 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3889 if (MaskElt < 0) 3890 continue; 3891 if (MaskElt >= LaneSize) 3892 MaskElt -= LaneSize; 3893 Mask |= MaskElt << (i*2); 3894 } 3895 } 3896 3897 return Mask; 3898} 3899 3900/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3901/// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3902static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3903 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3904 EVT VT = SVOp->getValueType(0); 3905 3906 int NumElts = VT.getVectorNumElements(); 3907 int NumLanes = VT.getSizeInBits()/128; 3908 3909 unsigned Mask = 0; 3910 int LaneSize = NumElts/NumLanes; 3911 for (int l = 0; l < NumLanes; ++l) 3912 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3913 int MaskElt = SVOp->getMaskElt(i); 3914 if (MaskElt < 0) 3915 continue; 3916 Mask |= (MaskElt-l*LaneSize) << i; 3917 } 3918 3919 return Mask; 3920} 3921 3922/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3923/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3924/// element of vector 2 and the other elements to come from vector 1 in order. 3925static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3926 bool V2IsSplat = false, bool V2IsUndef = false) { 3927 int NumOps = VT.getVectorNumElements(); 3928 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3929 return false; 3930 3931 if (!isUndefOrEqual(Mask[0], 0)) 3932 return false; 3933 3934 for (int i = 1; i < NumOps; ++i) 3935 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3936 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3937 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3938 return false; 3939 3940 return true; 3941} 3942 3943static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3944 bool V2IsUndef = false) { 3945 SmallVector<int, 8> M; 3946 N->getMask(M); 3947 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3948} 3949 3950/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3951/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3952/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3953bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3954 const X86Subtarget *Subtarget) { 3955 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3956 return false; 3957 3958 // The second vector must be undef 3959 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3960 return false; 3961 3962 EVT VT = N->getValueType(0); 3963 unsigned NumElems = VT.getVectorNumElements(); 3964 3965 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3966 (VT.getSizeInBits() == 256 && NumElems != 8)) 3967 return false; 3968 3969 // "i+1" is the value the indexed mask element must have 3970 for (unsigned i = 0; i < NumElems; i += 2) 3971 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3972 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3973 return false; 3974 3975 return true; 3976} 3977 3978/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3979/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3980/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3981bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3982 const X86Subtarget *Subtarget) { 3983 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3984 return false; 3985 3986 // The second vector must be undef 3987 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3988 return false; 3989 3990 EVT VT = N->getValueType(0); 3991 unsigned NumElems = VT.getVectorNumElements(); 3992 3993 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3994 (VT.getSizeInBits() == 256 && NumElems != 8)) 3995 return false; 3996 3997 // "i" is the value the indexed mask element must have 3998 for (unsigned i = 0; i < NumElems; i += 2) 3999 if (!isUndefOrEqual(N->getMaskElt(i), i) || 4000 !isUndefOrEqual(N->getMaskElt(i+1), i)) 4001 return false; 4002 4003 return true; 4004} 4005 4006/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 4007/// specifies a shuffle of elements that is suitable for input to 256-bit 4008/// version of MOVDDUP. 4009static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, 4010 const X86Subtarget *Subtarget) { 4011 EVT VT = N->getValueType(0); 4012 int NumElts = VT.getVectorNumElements(); 4013 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; 4014 4015 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || 4016 !V2IsUndef || NumElts != 4) 4017 return false; 4018 4019 for (int i = 0; i != NumElts/2; ++i) 4020 if (!isUndefOrEqual(N->getMaskElt(i), 0)) 4021 return false; 4022 for (int i = NumElts/2; i != NumElts; ++i) 4023 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) 4024 return false; 4025 return true; 4026} 4027 4028/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 4029/// specifies a shuffle of elements that is suitable for input to 128-bit 4030/// version of MOVDDUP. 4031bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 4032 EVT VT = N->getValueType(0); 4033 4034 if (VT.getSizeInBits() != 128) 4035 return false; 4036 4037 int e = VT.getVectorNumElements() / 2; 4038 for (int i = 0; i < e; ++i) 4039 if (!isUndefOrEqual(N->getMaskElt(i), i)) 4040 return false; 4041 for (int i = 0; i < e; ++i) 4042 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 4043 return false; 4044 return true; 4045} 4046 4047/// isVEXTRACTF128Index - Return true if the specified 4048/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 4049/// suitable for input to VEXTRACTF128. 4050bool X86::isVEXTRACTF128Index(SDNode *N) { 4051 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4052 return false; 4053 4054 // The index should be aligned on a 128-bit boundary. 4055 uint64_t Index = 4056 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4057 4058 unsigned VL = N->getValueType(0).getVectorNumElements(); 4059 unsigned VBits = N->getValueType(0).getSizeInBits(); 4060 unsigned ElSize = VBits / VL; 4061 bool Result = (Index * ElSize) % 128 == 0; 4062 4063 return Result; 4064} 4065 4066/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 4067/// operand specifies a subvector insert that is suitable for input to 4068/// VINSERTF128. 4069bool X86::isVINSERTF128Index(SDNode *N) { 4070 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4071 return false; 4072 4073 // The index should be aligned on a 128-bit boundary. 4074 uint64_t Index = 4075 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4076 4077 unsigned VL = N->getValueType(0).getVectorNumElements(); 4078 unsigned VBits = N->getValueType(0).getSizeInBits(); 4079 unsigned ElSize = VBits / VL; 4080 bool Result = (Index * ElSize) % 128 == 0; 4081 4082 return Result; 4083} 4084 4085/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4086/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4087unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 4088 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4089 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 4090 4091 unsigned Shift = (NumOperands == 4) ? 2 : 1; 4092 unsigned Mask = 0; 4093 for (int i = 0; i < NumOperands; ++i) { 4094 int Val = SVOp->getMaskElt(NumOperands-i-1); 4095 if (Val < 0) Val = 0; 4096 if (Val >= NumOperands) Val -= NumOperands; 4097 Mask |= Val; 4098 if (i != NumOperands - 1) 4099 Mask <<= Shift; 4100 } 4101 return Mask; 4102} 4103 4104/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4105/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4106unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 4107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4108 unsigned Mask = 0; 4109 // 8 nodes, but we only care about the last 4. 4110 for (unsigned i = 7; i >= 4; --i) { 4111 int Val = SVOp->getMaskElt(i); 4112 if (Val >= 0) 4113 Mask |= (Val - 4); 4114 if (i != 4) 4115 Mask <<= 2; 4116 } 4117 return Mask; 4118} 4119 4120/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4121/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4122unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4123 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4124 unsigned Mask = 0; 4125 // 8 nodes, but we only care about the first 4. 4126 for (int i = 3; i >= 0; --i) { 4127 int Val = SVOp->getMaskElt(i); 4128 if (Val >= 0) 4129 Mask |= Val; 4130 if (i != 0) 4131 Mask <<= 2; 4132 } 4133 return Mask; 4134} 4135 4136/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4137/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4138unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 4139 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4140 EVT VVT = N->getValueType(0); 4141 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 4142 int Val = 0; 4143 4144 unsigned i, e; 4145 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 4146 Val = SVOp->getMaskElt(i); 4147 if (Val >= 0) 4148 break; 4149 } 4150 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4151 return (Val - i) * EltSize; 4152} 4153 4154/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4155/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4156/// instructions. 4157unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4158 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4159 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4160 4161 uint64_t Index = 4162 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4163 4164 EVT VecVT = N->getOperand(0).getValueType(); 4165 EVT ElVT = VecVT.getVectorElementType(); 4166 4167 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4168 return Index / NumElemsPerChunk; 4169} 4170 4171/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4172/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4173/// instructions. 4174unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4175 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4176 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4177 4178 uint64_t Index = 4179 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4180 4181 EVT VecVT = N->getValueType(0); 4182 EVT ElVT = VecVT.getVectorElementType(); 4183 4184 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4185 return Index / NumElemsPerChunk; 4186} 4187 4188/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4189/// constant +0.0. 4190bool X86::isZeroNode(SDValue Elt) { 4191 return ((isa<ConstantSDNode>(Elt) && 4192 cast<ConstantSDNode>(Elt)->isNullValue()) || 4193 (isa<ConstantFPSDNode>(Elt) && 4194 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4195} 4196 4197/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4198/// their permute mask. 4199static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4200 SelectionDAG &DAG) { 4201 EVT VT = SVOp->getValueType(0); 4202 unsigned NumElems = VT.getVectorNumElements(); 4203 SmallVector<int, 8> MaskVec; 4204 4205 for (unsigned i = 0; i != NumElems; ++i) { 4206 int idx = SVOp->getMaskElt(i); 4207 if (idx < 0) 4208 MaskVec.push_back(idx); 4209 else if (idx < (int)NumElems) 4210 MaskVec.push_back(idx + NumElems); 4211 else 4212 MaskVec.push_back(idx - NumElems); 4213 } 4214 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4215 SVOp->getOperand(0), &MaskVec[0]); 4216} 4217 4218/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 4219/// the two vector operands have swapped position. 4220static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 4221 unsigned NumElems = VT.getVectorNumElements(); 4222 for (unsigned i = 0; i != NumElems; ++i) { 4223 int idx = Mask[i]; 4224 if (idx < 0) 4225 continue; 4226 else if (idx < (int)NumElems) 4227 Mask[i] = idx + NumElems; 4228 else 4229 Mask[i] = idx - NumElems; 4230 } 4231} 4232 4233/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4234/// match movhlps. The lower half elements should come from upper half of 4235/// V1 (and in order), and the upper half elements should come from the upper 4236/// half of V2 (and in order). 4237static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4238 EVT VT = Op->getValueType(0); 4239 if (VT.getSizeInBits() != 128) 4240 return false; 4241 if (VT.getVectorNumElements() != 4) 4242 return false; 4243 for (unsigned i = 0, e = 2; i != e; ++i) 4244 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4245 return false; 4246 for (unsigned i = 2; i != 4; ++i) 4247 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4248 return false; 4249 return true; 4250} 4251 4252/// isScalarLoadToVector - Returns true if the node is a scalar load that 4253/// is promoted to a vector. It also returns the LoadSDNode by reference if 4254/// required. 4255static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4256 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4257 return false; 4258 N = N->getOperand(0).getNode(); 4259 if (!ISD::isNON_EXTLoad(N)) 4260 return false; 4261 if (LD) 4262 *LD = cast<LoadSDNode>(N); 4263 return true; 4264} 4265 4266// Test whether the given value is a vector value which will be legalized 4267// into a load. 4268static bool WillBeConstantPoolLoad(SDNode *N) { 4269 if (N->getOpcode() != ISD::BUILD_VECTOR) 4270 return false; 4271 4272 // Check for any non-constant elements. 4273 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4274 switch (N->getOperand(i).getNode()->getOpcode()) { 4275 case ISD::UNDEF: 4276 case ISD::ConstantFP: 4277 case ISD::Constant: 4278 break; 4279 default: 4280 return false; 4281 } 4282 4283 // Vectors of all-zeros and all-ones are materialized with special 4284 // instructions rather than being loaded. 4285 return !ISD::isBuildVectorAllZeros(N) && 4286 !ISD::isBuildVectorAllOnes(N); 4287} 4288 4289/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4290/// match movlp{s|d}. The lower half elements should come from lower half of 4291/// V1 (and in order), and the upper half elements should come from the upper 4292/// half of V2 (and in order). And since V1 will become the source of the 4293/// MOVLP, it must be either a vector load or a scalar load to vector. 4294static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4295 ShuffleVectorSDNode *Op) { 4296 EVT VT = Op->getValueType(0); 4297 if (VT.getSizeInBits() != 128) 4298 return false; 4299 4300 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4301 return false; 4302 // Is V2 is a vector load, don't do this transformation. We will try to use 4303 // load folding shufps op. 4304 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4305 return false; 4306 4307 unsigned NumElems = VT.getVectorNumElements(); 4308 4309 if (NumElems != 2 && NumElems != 4) 4310 return false; 4311 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4312 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4313 return false; 4314 for (unsigned i = NumElems/2; i != NumElems; ++i) 4315 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4316 return false; 4317 return true; 4318} 4319 4320/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4321/// all the same. 4322static bool isSplatVector(SDNode *N) { 4323 if (N->getOpcode() != ISD::BUILD_VECTOR) 4324 return false; 4325 4326 SDValue SplatValue = N->getOperand(0); 4327 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4328 if (N->getOperand(i) != SplatValue) 4329 return false; 4330 return true; 4331} 4332 4333/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4334/// to an zero vector. 4335/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4336static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4337 SDValue V1 = N->getOperand(0); 4338 SDValue V2 = N->getOperand(1); 4339 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4340 for (unsigned i = 0; i != NumElems; ++i) { 4341 int Idx = N->getMaskElt(i); 4342 if (Idx >= (int)NumElems) { 4343 unsigned Opc = V2.getOpcode(); 4344 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4345 continue; 4346 if (Opc != ISD::BUILD_VECTOR || 4347 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4348 return false; 4349 } else if (Idx >= 0) { 4350 unsigned Opc = V1.getOpcode(); 4351 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4352 continue; 4353 if (Opc != ISD::BUILD_VECTOR || 4354 !X86::isZeroNode(V1.getOperand(Idx))) 4355 return false; 4356 } 4357 } 4358 return true; 4359} 4360 4361/// getZeroVector - Returns a vector of specified type with all zero elements. 4362/// 4363static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG, 4364 DebugLoc dl) { 4365 assert(VT.isVector() && "Expected a vector type"); 4366 4367 // Always build SSE zero vectors as <4 x i32> bitcasted 4368 // to their dest type. This ensures they get CSE'd. 4369 SDValue Vec; 4370 if (VT.getSizeInBits() == 128) { // SSE 4371 if (HasXMMInt) { // SSE2 4372 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4373 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4374 } else { // SSE1 4375 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4376 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4377 } 4378 } else if (VT.getSizeInBits() == 256) { // AVX 4379 // 256-bit logic and arithmetic instructions in AVX are 4380 // all floating-point, no support for integer ops. Default 4381 // to emitting fp zeroed vectors then. 4382 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4383 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4384 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4385 } 4386 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4387} 4388 4389/// getOnesVector - Returns a vector of specified type with all bits set. 4390/// Always build ones vectors as <4 x i32>. For 256-bit types, use two 4391/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their 4392/// original type, ensuring they get CSE'd. 4393static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4394 assert(VT.isVector() && "Expected a vector type"); 4395 assert((VT.is128BitVector() || VT.is256BitVector()) 4396 && "Expected a 128-bit or 256-bit vector type"); 4397 4398 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4399 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 4400 Cst, Cst, Cst, Cst); 4401 4402 if (VT.is256BitVector()) { 4403 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4404 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4405 Vec = Insert128BitVector(InsV, Vec, 4406 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4407 } 4408 4409 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4410} 4411 4412/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4413/// that point to V2 points to its first element. 4414static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4415 EVT VT = SVOp->getValueType(0); 4416 unsigned NumElems = VT.getVectorNumElements(); 4417 4418 bool Changed = false; 4419 SmallVector<int, 8> MaskVec; 4420 SVOp->getMask(MaskVec); 4421 4422 for (unsigned i = 0; i != NumElems; ++i) { 4423 if (MaskVec[i] > (int)NumElems) { 4424 MaskVec[i] = NumElems; 4425 Changed = true; 4426 } 4427 } 4428 if (Changed) 4429 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4430 SVOp->getOperand(1), &MaskVec[0]); 4431 return SDValue(SVOp, 0); 4432} 4433 4434/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4435/// operation of specified width. 4436static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4437 SDValue V2) { 4438 unsigned NumElems = VT.getVectorNumElements(); 4439 SmallVector<int, 8> Mask; 4440 Mask.push_back(NumElems); 4441 for (unsigned i = 1; i != NumElems; ++i) 4442 Mask.push_back(i); 4443 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4444} 4445 4446/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4447static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4448 SDValue V2) { 4449 unsigned NumElems = VT.getVectorNumElements(); 4450 SmallVector<int, 8> Mask; 4451 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4452 Mask.push_back(i); 4453 Mask.push_back(i + NumElems); 4454 } 4455 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4456} 4457 4458/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4459static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4460 SDValue V2) { 4461 unsigned NumElems = VT.getVectorNumElements(); 4462 unsigned Half = NumElems/2; 4463 SmallVector<int, 8> Mask; 4464 for (unsigned i = 0; i != Half; ++i) { 4465 Mask.push_back(i + Half); 4466 Mask.push_back(i + NumElems + Half); 4467 } 4468 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4469} 4470 4471// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4472// a generic shuffle instruction because the target has no such instructions. 4473// Generate shuffles which repeat i16 and i8 several times until they can be 4474// represented by v4f32 and then be manipulated by target suported shuffles. 4475static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4476 EVT VT = V.getValueType(); 4477 int NumElems = VT.getVectorNumElements(); 4478 DebugLoc dl = V.getDebugLoc(); 4479 4480 while (NumElems > 4) { 4481 if (EltNo < NumElems/2) { 4482 V = getUnpackl(DAG, dl, VT, V, V); 4483 } else { 4484 V = getUnpackh(DAG, dl, VT, V, V); 4485 EltNo -= NumElems/2; 4486 } 4487 NumElems >>= 1; 4488 } 4489 return V; 4490} 4491 4492/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4493static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4494 EVT VT = V.getValueType(); 4495 DebugLoc dl = V.getDebugLoc(); 4496 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4497 && "Vector size not supported"); 4498 4499 if (VT.getSizeInBits() == 128) { 4500 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4501 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4502 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4503 &SplatMask[0]); 4504 } else { 4505 // To use VPERMILPS to splat scalars, the second half of indicies must 4506 // refer to the higher part, which is a duplication of the lower one, 4507 // because VPERMILPS can only handle in-lane permutations. 4508 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4509 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4510 4511 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4512 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4513 &SplatMask[0]); 4514 } 4515 4516 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4517} 4518 4519/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4520static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4521 EVT SrcVT = SV->getValueType(0); 4522 SDValue V1 = SV->getOperand(0); 4523 DebugLoc dl = SV->getDebugLoc(); 4524 4525 int EltNo = SV->getSplatIndex(); 4526 int NumElems = SrcVT.getVectorNumElements(); 4527 unsigned Size = SrcVT.getSizeInBits(); 4528 4529 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4530 "Unknown how to promote splat for type"); 4531 4532 // Extract the 128-bit part containing the splat element and update 4533 // the splat element index when it refers to the higher register. 4534 if (Size == 256) { 4535 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4536 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4537 if (Idx > 0) 4538 EltNo -= NumElems/2; 4539 } 4540 4541 // All i16 and i8 vector types can't be used directly by a generic shuffle 4542 // instruction because the target has no such instruction. Generate shuffles 4543 // which repeat i16 and i8 several times until they fit in i32, and then can 4544 // be manipulated by target suported shuffles. 4545 EVT EltVT = SrcVT.getVectorElementType(); 4546 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4547 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4548 4549 // Recreate the 256-bit vector and place the same 128-bit vector 4550 // into the low and high part. This is necessary because we want 4551 // to use VPERM* to shuffle the vectors 4552 if (Size == 256) { 4553 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4554 DAG.getConstant(0, MVT::i32), DAG, dl); 4555 V1 = Insert128BitVector(InsV, V1, 4556 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4557 } 4558 4559 return getLegalSplat(DAG, V1, EltNo); 4560} 4561 4562/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4563/// vector of zero or undef vector. This produces a shuffle where the low 4564/// element of V2 is swizzled into the zero/undef vector, landing at element 4565/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4566static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4567 bool isZero, bool HasXMMInt, 4568 SelectionDAG &DAG) { 4569 EVT VT = V2.getValueType(); 4570 SDValue V1 = isZero 4571 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4572 unsigned NumElems = VT.getVectorNumElements(); 4573 SmallVector<int, 16> MaskVec; 4574 for (unsigned i = 0; i != NumElems; ++i) 4575 // If this is the insertion idx, put the low elt of V2 here. 4576 MaskVec.push_back(i == Idx ? NumElems : i); 4577 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4578} 4579 4580/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4581/// element of the result of the vector shuffle. 4582static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4583 unsigned Depth) { 4584 if (Depth == 6) 4585 return SDValue(); // Limit search depth. 4586 4587 SDValue V = SDValue(N, 0); 4588 EVT VT = V.getValueType(); 4589 unsigned Opcode = V.getOpcode(); 4590 4591 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4592 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4593 Index = SV->getMaskElt(Index); 4594 4595 if (Index < 0) 4596 return DAG.getUNDEF(VT.getVectorElementType()); 4597 4598 int NumElems = VT.getVectorNumElements(); 4599 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4600 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4601 } 4602 4603 // Recurse into target specific vector shuffles to find scalars. 4604 if (isTargetShuffle(Opcode)) { 4605 int NumElems = VT.getVectorNumElements(); 4606 SmallVector<unsigned, 16> ShuffleMask; 4607 SDValue ImmN; 4608 4609 switch(Opcode) { 4610 case X86ISD::SHUFPS: 4611 case X86ISD::SHUFPD: 4612 ImmN = N->getOperand(N->getNumOperands()-1); 4613 DecodeSHUFPSMask(NumElems, 4614 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4615 ShuffleMask); 4616 break; 4617 case X86ISD::PUNPCKHBW: 4618 case X86ISD::PUNPCKHWD: 4619 case X86ISD::PUNPCKHDQ: 4620 case X86ISD::PUNPCKHQDQ: 4621 DecodePUNPCKHMask(NumElems, ShuffleMask); 4622 break; 4623 case X86ISD::UNPCKHPS: 4624 case X86ISD::UNPCKHPD: 4625 case X86ISD::VUNPCKHPSY: 4626 case X86ISD::VUNPCKHPDY: 4627 DecodeUNPCKHPMask(NumElems, ShuffleMask); 4628 break; 4629 case X86ISD::PUNPCKLBW: 4630 case X86ISD::PUNPCKLWD: 4631 case X86ISD::PUNPCKLDQ: 4632 case X86ISD::PUNPCKLQDQ: 4633 DecodePUNPCKLMask(VT, ShuffleMask); 4634 break; 4635 case X86ISD::UNPCKLPS: 4636 case X86ISD::UNPCKLPD: 4637 case X86ISD::VUNPCKLPSY: 4638 case X86ISD::VUNPCKLPDY: 4639 DecodeUNPCKLPMask(VT, ShuffleMask); 4640 break; 4641 case X86ISD::MOVHLPS: 4642 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4643 break; 4644 case X86ISD::MOVLHPS: 4645 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4646 break; 4647 case X86ISD::PSHUFD: 4648 ImmN = N->getOperand(N->getNumOperands()-1); 4649 DecodePSHUFMask(NumElems, 4650 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4651 ShuffleMask); 4652 break; 4653 case X86ISD::PSHUFHW: 4654 ImmN = N->getOperand(N->getNumOperands()-1); 4655 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4656 ShuffleMask); 4657 break; 4658 case X86ISD::PSHUFLW: 4659 ImmN = N->getOperand(N->getNumOperands()-1); 4660 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4661 ShuffleMask); 4662 break; 4663 case X86ISD::MOVSS: 4664 case X86ISD::MOVSD: { 4665 // The index 0 always comes from the first element of the second source, 4666 // this is why MOVSS and MOVSD are used in the first place. The other 4667 // elements come from the other positions of the first source vector. 4668 unsigned OpNum = (Index == 0) ? 1 : 0; 4669 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4670 Depth+1); 4671 } 4672 case X86ISD::VPERMILPS: 4673 ImmN = N->getOperand(N->getNumOperands()-1); 4674 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4675 ShuffleMask); 4676 break; 4677 case X86ISD::VPERMILPSY: 4678 ImmN = N->getOperand(N->getNumOperands()-1); 4679 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4680 ShuffleMask); 4681 break; 4682 case X86ISD::VPERMILPD: 4683 ImmN = N->getOperand(N->getNumOperands()-1); 4684 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4685 ShuffleMask); 4686 break; 4687 case X86ISD::VPERMILPDY: 4688 ImmN = N->getOperand(N->getNumOperands()-1); 4689 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4690 ShuffleMask); 4691 break; 4692 case X86ISD::VPERM2F128: 4693 ImmN = N->getOperand(N->getNumOperands()-1); 4694 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4695 ShuffleMask); 4696 break; 4697 case X86ISD::MOVDDUP: 4698 case X86ISD::MOVLHPD: 4699 case X86ISD::MOVLPD: 4700 case X86ISD::MOVLPS: 4701 case X86ISD::MOVSHDUP: 4702 case X86ISD::MOVSLDUP: 4703 case X86ISD::PALIGN: 4704 return SDValue(); // Not yet implemented. 4705 default: 4706 assert(0 && "unknown target shuffle node"); 4707 return SDValue(); 4708 } 4709 4710 Index = ShuffleMask[Index]; 4711 if (Index < 0) 4712 return DAG.getUNDEF(VT.getVectorElementType()); 4713 4714 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4715 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4716 Depth+1); 4717 } 4718 4719 // Actual nodes that may contain scalar elements 4720 if (Opcode == ISD::BITCAST) { 4721 V = V.getOperand(0); 4722 EVT SrcVT = V.getValueType(); 4723 unsigned NumElems = VT.getVectorNumElements(); 4724 4725 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4726 return SDValue(); 4727 } 4728 4729 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4730 return (Index == 0) ? V.getOperand(0) 4731 : DAG.getUNDEF(VT.getVectorElementType()); 4732 4733 if (V.getOpcode() == ISD::BUILD_VECTOR) 4734 return V.getOperand(Index); 4735 4736 return SDValue(); 4737} 4738 4739/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4740/// shuffle operation which come from a consecutively from a zero. The 4741/// search can start in two different directions, from left or right. 4742static 4743unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4744 bool ZerosFromLeft, SelectionDAG &DAG) { 4745 int i = 0; 4746 4747 while (i < NumElems) { 4748 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4749 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4750 if (!(Elt.getNode() && 4751 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4752 break; 4753 ++i; 4754 } 4755 4756 return i; 4757} 4758 4759/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4760/// MaskE correspond consecutively to elements from one of the vector operands, 4761/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4762static 4763bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4764 int OpIdx, int NumElems, unsigned &OpNum) { 4765 bool SeenV1 = false; 4766 bool SeenV2 = false; 4767 4768 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4769 int Idx = SVOp->getMaskElt(i); 4770 // Ignore undef indicies 4771 if (Idx < 0) 4772 continue; 4773 4774 if (Idx < NumElems) 4775 SeenV1 = true; 4776 else 4777 SeenV2 = true; 4778 4779 // Only accept consecutive elements from the same vector 4780 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4781 return false; 4782 } 4783 4784 OpNum = SeenV1 ? 0 : 1; 4785 return true; 4786} 4787 4788/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4789/// logical left shift of a vector. 4790static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4791 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4792 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4793 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4794 false /* check zeros from right */, DAG); 4795 unsigned OpSrc; 4796 4797 if (!NumZeros) 4798 return false; 4799 4800 // Considering the elements in the mask that are not consecutive zeros, 4801 // check if they consecutively come from only one of the source vectors. 4802 // 4803 // V1 = {X, A, B, C} 0 4804 // \ \ \ / 4805 // vector_shuffle V1, V2 <1, 2, 3, X> 4806 // 4807 if (!isShuffleMaskConsecutive(SVOp, 4808 0, // Mask Start Index 4809 NumElems-NumZeros-1, // Mask End Index 4810 NumZeros, // Where to start looking in the src vector 4811 NumElems, // Number of elements in vector 4812 OpSrc)) // Which source operand ? 4813 return false; 4814 4815 isLeft = false; 4816 ShAmt = NumZeros; 4817 ShVal = SVOp->getOperand(OpSrc); 4818 return true; 4819} 4820 4821/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4822/// logical left shift of a vector. 4823static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4824 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4825 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4826 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4827 true /* check zeros from left */, DAG); 4828 unsigned OpSrc; 4829 4830 if (!NumZeros) 4831 return false; 4832 4833 // Considering the elements in the mask that are not consecutive zeros, 4834 // check if they consecutively come from only one of the source vectors. 4835 // 4836 // 0 { A, B, X, X } = V2 4837 // / \ / / 4838 // vector_shuffle V1, V2 <X, X, 4, 5> 4839 // 4840 if (!isShuffleMaskConsecutive(SVOp, 4841 NumZeros, // Mask Start Index 4842 NumElems-1, // Mask End Index 4843 0, // Where to start looking in the src vector 4844 NumElems, // Number of elements in vector 4845 OpSrc)) // Which source operand ? 4846 return false; 4847 4848 isLeft = true; 4849 ShAmt = NumZeros; 4850 ShVal = SVOp->getOperand(OpSrc); 4851 return true; 4852} 4853 4854/// isVectorShift - Returns true if the shuffle can be implemented as a 4855/// logical left or right shift of a vector. 4856static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4857 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4858 // Although the logic below support any bitwidth size, there are no 4859 // shift instructions which handle more than 128-bit vectors. 4860 if (SVOp->getValueType(0).getSizeInBits() > 128) 4861 return false; 4862 4863 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4864 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4865 return true; 4866 4867 return false; 4868} 4869 4870/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4871/// 4872static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4873 unsigned NumNonZero, unsigned NumZero, 4874 SelectionDAG &DAG, 4875 const TargetLowering &TLI) { 4876 if (NumNonZero > 8) 4877 return SDValue(); 4878 4879 DebugLoc dl = Op.getDebugLoc(); 4880 SDValue V(0, 0); 4881 bool First = true; 4882 for (unsigned i = 0; i < 16; ++i) { 4883 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4884 if (ThisIsNonZero && First) { 4885 if (NumZero) 4886 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4887 else 4888 V = DAG.getUNDEF(MVT::v8i16); 4889 First = false; 4890 } 4891 4892 if ((i & 1) != 0) { 4893 SDValue ThisElt(0, 0), LastElt(0, 0); 4894 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4895 if (LastIsNonZero) { 4896 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4897 MVT::i16, Op.getOperand(i-1)); 4898 } 4899 if (ThisIsNonZero) { 4900 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4901 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4902 ThisElt, DAG.getConstant(8, MVT::i8)); 4903 if (LastIsNonZero) 4904 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4905 } else 4906 ThisElt = LastElt; 4907 4908 if (ThisElt.getNode()) 4909 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4910 DAG.getIntPtrConstant(i/2)); 4911 } 4912 } 4913 4914 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4915} 4916 4917/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4918/// 4919static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4920 unsigned NumNonZero, unsigned NumZero, 4921 SelectionDAG &DAG, 4922 const TargetLowering &TLI) { 4923 if (NumNonZero > 4) 4924 return SDValue(); 4925 4926 DebugLoc dl = Op.getDebugLoc(); 4927 SDValue V(0, 0); 4928 bool First = true; 4929 for (unsigned i = 0; i < 8; ++i) { 4930 bool isNonZero = (NonZeros & (1 << i)) != 0; 4931 if (isNonZero) { 4932 if (First) { 4933 if (NumZero) 4934 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4935 else 4936 V = DAG.getUNDEF(MVT::v8i16); 4937 First = false; 4938 } 4939 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4940 MVT::v8i16, V, Op.getOperand(i), 4941 DAG.getIntPtrConstant(i)); 4942 } 4943 } 4944 4945 return V; 4946} 4947 4948/// getVShift - Return a vector logical shift node. 4949/// 4950static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4951 unsigned NumBits, SelectionDAG &DAG, 4952 const TargetLowering &TLI, DebugLoc dl) { 4953 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4954 EVT ShVT = MVT::v2i64; 4955 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4956 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4957 return DAG.getNode(ISD::BITCAST, dl, VT, 4958 DAG.getNode(Opc, dl, ShVT, SrcOp, 4959 DAG.getConstant(NumBits, 4960 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4961} 4962 4963SDValue 4964X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4965 SelectionDAG &DAG) const { 4966 4967 // Check if the scalar load can be widened into a vector load. And if 4968 // the address is "base + cst" see if the cst can be "absorbed" into 4969 // the shuffle mask. 4970 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4971 SDValue Ptr = LD->getBasePtr(); 4972 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4973 return SDValue(); 4974 EVT PVT = LD->getValueType(0); 4975 if (PVT != MVT::i32 && PVT != MVT::f32) 4976 return SDValue(); 4977 4978 int FI = -1; 4979 int64_t Offset = 0; 4980 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4981 FI = FINode->getIndex(); 4982 Offset = 0; 4983 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4984 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4985 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4986 Offset = Ptr.getConstantOperandVal(1); 4987 Ptr = Ptr.getOperand(0); 4988 } else { 4989 return SDValue(); 4990 } 4991 4992 // FIXME: 256-bit vector instructions don't require a strict alignment, 4993 // improve this code to support it better. 4994 unsigned RequiredAlign = VT.getSizeInBits()/8; 4995 SDValue Chain = LD->getChain(); 4996 // Make sure the stack object alignment is at least 16 or 32. 4997 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4998 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4999 if (MFI->isFixedObjectIndex(FI)) { 5000 // Can't change the alignment. FIXME: It's possible to compute 5001 // the exact stack offset and reference FI + adjust offset instead. 5002 // If someone *really* cares about this. That's the way to implement it. 5003 return SDValue(); 5004 } else { 5005 MFI->setObjectAlignment(FI, RequiredAlign); 5006 } 5007 } 5008 5009 // (Offset % 16 or 32) must be multiple of 4. Then address is then 5010 // Ptr + (Offset & ~15). 5011 if (Offset < 0) 5012 return SDValue(); 5013 if ((Offset % RequiredAlign) & 3) 5014 return SDValue(); 5015 int64_t StartOffset = Offset & ~(RequiredAlign-1); 5016 if (StartOffset) 5017 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 5018 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 5019 5020 int EltNo = (Offset - StartOffset) >> 2; 5021 int NumElems = VT.getVectorNumElements(); 5022 5023 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 5024 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 5025 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 5026 LD->getPointerInfo().getWithOffset(StartOffset), 5027 false, false, false, 0); 5028 5029 // Canonicalize it to a v4i32 or v8i32 shuffle. 5030 SmallVector<int, 8> Mask; 5031 for (int i = 0; i < NumElems; ++i) 5032 Mask.push_back(EltNo); 5033 5034 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 5035 return DAG.getNode(ISD::BITCAST, dl, NVT, 5036 DAG.getVectorShuffle(CanonVT, dl, V1, 5037 DAG.getUNDEF(CanonVT),&Mask[0])); 5038 } 5039 5040 return SDValue(); 5041} 5042 5043/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 5044/// vector of type 'VT', see if the elements can be replaced by a single large 5045/// load which has the same value as a build_vector whose operands are 'elts'. 5046/// 5047/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 5048/// 5049/// FIXME: we'd also like to handle the case where the last elements are zero 5050/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 5051/// There's even a handy isZeroNode for that purpose. 5052static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 5053 DebugLoc &DL, SelectionDAG &DAG) { 5054 EVT EltVT = VT.getVectorElementType(); 5055 unsigned NumElems = Elts.size(); 5056 5057 LoadSDNode *LDBase = NULL; 5058 unsigned LastLoadedElt = -1U; 5059 5060 // For each element in the initializer, see if we've found a load or an undef. 5061 // If we don't find an initial load element, or later load elements are 5062 // non-consecutive, bail out. 5063 for (unsigned i = 0; i < NumElems; ++i) { 5064 SDValue Elt = Elts[i]; 5065 5066 if (!Elt.getNode() || 5067 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 5068 return SDValue(); 5069 if (!LDBase) { 5070 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 5071 return SDValue(); 5072 LDBase = cast<LoadSDNode>(Elt.getNode()); 5073 LastLoadedElt = i; 5074 continue; 5075 } 5076 if (Elt.getOpcode() == ISD::UNDEF) 5077 continue; 5078 5079 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5080 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5081 return SDValue(); 5082 LastLoadedElt = i; 5083 } 5084 5085 // If we have found an entire vector of loads and undefs, then return a large 5086 // load of the entire vector width starting at the base pointer. If we found 5087 // consecutive loads for the low half, generate a vzext_load node. 5088 if (LastLoadedElt == NumElems - 1) { 5089 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5090 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5091 LDBase->getPointerInfo(), 5092 LDBase->isVolatile(), LDBase->isNonTemporal(), 5093 LDBase->isInvariant(), 0); 5094 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5095 LDBase->getPointerInfo(), 5096 LDBase->isVolatile(), LDBase->isNonTemporal(), 5097 LDBase->isInvariant(), LDBase->getAlignment()); 5098 } else if (NumElems == 4 && LastLoadedElt == 1 && 5099 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5100 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5101 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5102 SDValue ResNode = 5103 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5104 LDBase->getPointerInfo(), 5105 LDBase->getAlignment(), 5106 false/*isVolatile*/, true/*ReadMem*/, 5107 false/*WriteMem*/); 5108 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5109 } 5110 return SDValue(); 5111} 5112 5113SDValue 5114X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5115 DebugLoc dl = Op.getDebugLoc(); 5116 5117 EVT VT = Op.getValueType(); 5118 EVT ExtVT = VT.getVectorElementType(); 5119 unsigned NumElems = Op.getNumOperands(); 5120 5121 // Vectors containing all zeros can be matched by pxor and xorps later 5122 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5123 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5124 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5125 if (Op.getValueType() == MVT::v4i32 || 5126 Op.getValueType() == MVT::v8i32) 5127 return Op; 5128 5129 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl); 5130 } 5131 5132 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5133 // vectors or broken into v4i32 operations on 256-bit vectors. 5134 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5135 if (Op.getValueType() == MVT::v4i32) 5136 return Op; 5137 5138 return getOnesVector(Op.getValueType(), DAG, dl); 5139 } 5140 5141 unsigned EVTBits = ExtVT.getSizeInBits(); 5142 5143 unsigned NumZero = 0; 5144 unsigned NumNonZero = 0; 5145 unsigned NonZeros = 0; 5146 bool IsAllConstants = true; 5147 SmallSet<SDValue, 8> Values; 5148 for (unsigned i = 0; i < NumElems; ++i) { 5149 SDValue Elt = Op.getOperand(i); 5150 if (Elt.getOpcode() == ISD::UNDEF) 5151 continue; 5152 Values.insert(Elt); 5153 if (Elt.getOpcode() != ISD::Constant && 5154 Elt.getOpcode() != ISD::ConstantFP) 5155 IsAllConstants = false; 5156 if (X86::isZeroNode(Elt)) 5157 NumZero++; 5158 else { 5159 NonZeros |= (1 << i); 5160 NumNonZero++; 5161 } 5162 } 5163 5164 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5165 if (NumNonZero == 0) 5166 return DAG.getUNDEF(VT); 5167 5168 // Special case for single non-zero, non-undef, element. 5169 if (NumNonZero == 1) { 5170 unsigned Idx = CountTrailingZeros_32(NonZeros); 5171 SDValue Item = Op.getOperand(Idx); 5172 5173 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5174 // the value are obviously zero, truncate the value to i32 and do the 5175 // insertion that way. Only do this if the value is non-constant or if the 5176 // value is a constant being inserted into element 0. It is cheaper to do 5177 // a constant pool load than it is to do a movd + shuffle. 5178 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5179 (!IsAllConstants || Idx == 0)) { 5180 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5181 // Handle SSE only. 5182 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5183 EVT VecVT = MVT::v4i32; 5184 unsigned VecElts = 4; 5185 5186 // Truncate the value (which may itself be a constant) to i32, and 5187 // convert it to a vector with movd (S2V+shuffle to zero extend). 5188 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5189 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5190 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5191 Subtarget->hasXMMInt(), DAG); 5192 5193 // Now we have our 32-bit value zero extended in the low element of 5194 // a vector. If Idx != 0, swizzle it into place. 5195 if (Idx != 0) { 5196 SmallVector<int, 4> Mask; 5197 Mask.push_back(Idx); 5198 for (unsigned i = 1; i != VecElts; ++i) 5199 Mask.push_back(i); 5200 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5201 DAG.getUNDEF(Item.getValueType()), 5202 &Mask[0]); 5203 } 5204 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5205 } 5206 } 5207 5208 // If we have a constant or non-constant insertion into the low element of 5209 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5210 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5211 // depending on what the source datatype is. 5212 if (Idx == 0) { 5213 if (NumZero == 0) { 5214 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5215 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5216 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5217 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5218 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5219 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), 5220 DAG); 5221 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5222 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5223 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5224 EVT MiddleVT = MVT::v4i32; 5225 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 5226 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5227 Subtarget->hasXMMInt(), DAG); 5228 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5229 } 5230 } 5231 5232 // Is it a vector logical left shift? 5233 if (NumElems == 2 && Idx == 1 && 5234 X86::isZeroNode(Op.getOperand(0)) && 5235 !X86::isZeroNode(Op.getOperand(1))) { 5236 unsigned NumBits = VT.getSizeInBits(); 5237 return getVShift(true, VT, 5238 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5239 VT, Op.getOperand(1)), 5240 NumBits/2, DAG, *this, dl); 5241 } 5242 5243 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5244 return SDValue(); 5245 5246 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5247 // is a non-constant being inserted into an element other than the low one, 5248 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5249 // movd/movss) to move this into the low element, then shuffle it into 5250 // place. 5251 if (EVTBits == 32) { 5252 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5253 5254 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5255 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5256 Subtarget->hasXMMInt(), DAG); 5257 SmallVector<int, 8> MaskVec; 5258 for (unsigned i = 0; i < NumElems; i++) 5259 MaskVec.push_back(i == Idx ? 0 : 1); 5260 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5261 } 5262 } 5263 5264 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5265 if (Values.size() == 1) { 5266 if (EVTBits == 32) { 5267 // Instead of a shuffle like this: 5268 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5269 // Check if it's possible to issue this instead. 5270 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5271 unsigned Idx = CountTrailingZeros_32(NonZeros); 5272 SDValue Item = Op.getOperand(Idx); 5273 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5274 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5275 } 5276 return SDValue(); 5277 } 5278 5279 // A vector full of immediates; various special cases are already 5280 // handled, so this is best done with a single constant-pool load. 5281 if (IsAllConstants) 5282 return SDValue(); 5283 5284 // For AVX-length vectors, build the individual 128-bit pieces and use 5285 // shuffles to put them in place. 5286 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5287 SmallVector<SDValue, 32> V; 5288 for (unsigned i = 0; i < NumElems; ++i) 5289 V.push_back(Op.getOperand(i)); 5290 5291 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5292 5293 // Build both the lower and upper subvector. 5294 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5295 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5296 NumElems/2); 5297 5298 // Recreate the wider vector with the lower and upper part. 5299 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5300 DAG.getConstant(0, MVT::i32), DAG, dl); 5301 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5302 DAG, dl); 5303 } 5304 5305 // Let legalizer expand 2-wide build_vectors. 5306 if (EVTBits == 64) { 5307 if (NumNonZero == 1) { 5308 // One half is zero or undef. 5309 unsigned Idx = CountTrailingZeros_32(NonZeros); 5310 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5311 Op.getOperand(Idx)); 5312 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5313 Subtarget->hasXMMInt(), DAG); 5314 } 5315 return SDValue(); 5316 } 5317 5318 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5319 if (EVTBits == 8 && NumElems == 16) { 5320 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5321 *this); 5322 if (V.getNode()) return V; 5323 } 5324 5325 if (EVTBits == 16 && NumElems == 8) { 5326 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5327 *this); 5328 if (V.getNode()) return V; 5329 } 5330 5331 // If element VT is == 32 bits, turn it into a number of shuffles. 5332 SmallVector<SDValue, 8> V; 5333 V.resize(NumElems); 5334 if (NumElems == 4 && NumZero > 0) { 5335 for (unsigned i = 0; i < 4; ++i) { 5336 bool isZero = !(NonZeros & (1 << i)); 5337 if (isZero) 5338 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 5339 else 5340 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5341 } 5342 5343 for (unsigned i = 0; i < 2; ++i) { 5344 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5345 default: break; 5346 case 0: 5347 V[i] = V[i*2]; // Must be a zero vector. 5348 break; 5349 case 1: 5350 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5351 break; 5352 case 2: 5353 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5354 break; 5355 case 3: 5356 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5357 break; 5358 } 5359 } 5360 5361 SmallVector<int, 8> MaskVec; 5362 bool Reverse = (NonZeros & 0x3) == 2; 5363 for (unsigned i = 0; i < 2; ++i) 5364 MaskVec.push_back(Reverse ? 1-i : i); 5365 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5366 for (unsigned i = 0; i < 2; ++i) 5367 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5368 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5369 } 5370 5371 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5372 // Check for a build vector of consecutive loads. 5373 for (unsigned i = 0; i < NumElems; ++i) 5374 V[i] = Op.getOperand(i); 5375 5376 // Check for elements which are consecutive loads. 5377 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5378 if (LD.getNode()) 5379 return LD; 5380 5381 // For SSE 4.1, use insertps to put the high elements into the low element. 5382 if (getSubtarget()->hasSSE41() || getSubtarget()->hasAVX()) { 5383 SDValue Result; 5384 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5385 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5386 else 5387 Result = DAG.getUNDEF(VT); 5388 5389 for (unsigned i = 1; i < NumElems; ++i) { 5390 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5391 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5392 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5393 } 5394 return Result; 5395 } 5396 5397 // Otherwise, expand into a number of unpckl*, start by extending each of 5398 // our (non-undef) elements to the full vector width with the element in the 5399 // bottom slot of the vector (which generates no code for SSE). 5400 for (unsigned i = 0; i < NumElems; ++i) { 5401 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5402 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5403 else 5404 V[i] = DAG.getUNDEF(VT); 5405 } 5406 5407 // Next, we iteratively mix elements, e.g. for v4f32: 5408 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5409 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5410 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5411 unsigned EltStride = NumElems >> 1; 5412 while (EltStride != 0) { 5413 for (unsigned i = 0; i < EltStride; ++i) { 5414 // If V[i+EltStride] is undef and this is the first round of mixing, 5415 // then it is safe to just drop this shuffle: V[i] is already in the 5416 // right place, the one element (since it's the first round) being 5417 // inserted as undef can be dropped. This isn't safe for successive 5418 // rounds because they will permute elements within both vectors. 5419 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5420 EltStride == NumElems/2) 5421 continue; 5422 5423 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5424 } 5425 EltStride >>= 1; 5426 } 5427 return V[0]; 5428 } 5429 return SDValue(); 5430} 5431 5432// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5433// them in a MMX register. This is better than doing a stack convert. 5434static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5435 DebugLoc dl = Op.getDebugLoc(); 5436 EVT ResVT = Op.getValueType(); 5437 5438 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5439 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5440 int Mask[2]; 5441 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5442 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5443 InVec = Op.getOperand(1); 5444 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5445 unsigned NumElts = ResVT.getVectorNumElements(); 5446 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5447 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5448 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5449 } else { 5450 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5451 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5452 Mask[0] = 0; Mask[1] = 2; 5453 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5454 } 5455 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5456} 5457 5458// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5459// to create 256-bit vectors from two other 128-bit ones. 5460static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5461 DebugLoc dl = Op.getDebugLoc(); 5462 EVT ResVT = Op.getValueType(); 5463 5464 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5465 5466 SDValue V1 = Op.getOperand(0); 5467 SDValue V2 = Op.getOperand(1); 5468 unsigned NumElems = ResVT.getVectorNumElements(); 5469 5470 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5471 DAG.getConstant(0, MVT::i32), DAG, dl); 5472 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5473 DAG, dl); 5474} 5475 5476SDValue 5477X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5478 EVT ResVT = Op.getValueType(); 5479 5480 assert(Op.getNumOperands() == 2); 5481 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5482 "Unsupported CONCAT_VECTORS for value type"); 5483 5484 // We support concatenate two MMX registers and place them in a MMX register. 5485 // This is better than doing a stack convert. 5486 if (ResVT.is128BitVector()) 5487 return LowerMMXCONCAT_VECTORS(Op, DAG); 5488 5489 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5490 // from two other 128-bit ones. 5491 return LowerAVXCONCAT_VECTORS(Op, DAG); 5492} 5493 5494// v8i16 shuffles - Prefer shuffles in the following order: 5495// 1. [all] pshuflw, pshufhw, optional move 5496// 2. [ssse3] 1 x pshufb 5497// 3. [ssse3] 2 x pshufb + 1 x por 5498// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5499SDValue 5500X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5501 SelectionDAG &DAG) const { 5502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5503 SDValue V1 = SVOp->getOperand(0); 5504 SDValue V2 = SVOp->getOperand(1); 5505 DebugLoc dl = SVOp->getDebugLoc(); 5506 SmallVector<int, 8> MaskVals; 5507 5508 // Determine if more than 1 of the words in each of the low and high quadwords 5509 // of the result come from the same quadword of one of the two inputs. Undef 5510 // mask values count as coming from any quadword, for better codegen. 5511 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5512 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5513 BitVector InputQuads(4); 5514 for (unsigned i = 0; i < 8; ++i) { 5515 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5516 int EltIdx = SVOp->getMaskElt(i); 5517 MaskVals.push_back(EltIdx); 5518 if (EltIdx < 0) { 5519 ++Quad[0]; 5520 ++Quad[1]; 5521 ++Quad[2]; 5522 ++Quad[3]; 5523 continue; 5524 } 5525 ++Quad[EltIdx / 4]; 5526 InputQuads.set(EltIdx / 4); 5527 } 5528 5529 int BestLoQuad = -1; 5530 unsigned MaxQuad = 1; 5531 for (unsigned i = 0; i < 4; ++i) { 5532 if (LoQuad[i] > MaxQuad) { 5533 BestLoQuad = i; 5534 MaxQuad = LoQuad[i]; 5535 } 5536 } 5537 5538 int BestHiQuad = -1; 5539 MaxQuad = 1; 5540 for (unsigned i = 0; i < 4; ++i) { 5541 if (HiQuad[i] > MaxQuad) { 5542 BestHiQuad = i; 5543 MaxQuad = HiQuad[i]; 5544 } 5545 } 5546 5547 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5548 // of the two input vectors, shuffle them into one input vector so only a 5549 // single pshufb instruction is necessary. If There are more than 2 input 5550 // quads, disable the next transformation since it does not help SSSE3. 5551 bool V1Used = InputQuads[0] || InputQuads[1]; 5552 bool V2Used = InputQuads[2] || InputQuads[3]; 5553 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 5554 if (InputQuads.count() == 2 && V1Used && V2Used) { 5555 BestLoQuad = InputQuads.find_first(); 5556 BestHiQuad = InputQuads.find_next(BestLoQuad); 5557 } 5558 if (InputQuads.count() > 2) { 5559 BestLoQuad = -1; 5560 BestHiQuad = -1; 5561 } 5562 } 5563 5564 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5565 // the shuffle mask. If a quad is scored as -1, that means that it contains 5566 // words from all 4 input quadwords. 5567 SDValue NewV; 5568 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5569 SmallVector<int, 8> MaskV; 5570 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5571 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5572 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5573 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5574 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5575 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5576 5577 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5578 // source words for the shuffle, to aid later transformations. 5579 bool AllWordsInNewV = true; 5580 bool InOrder[2] = { true, true }; 5581 for (unsigned i = 0; i != 8; ++i) { 5582 int idx = MaskVals[i]; 5583 if (idx != (int)i) 5584 InOrder[i/4] = false; 5585 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5586 continue; 5587 AllWordsInNewV = false; 5588 break; 5589 } 5590 5591 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5592 if (AllWordsInNewV) { 5593 for (int i = 0; i != 8; ++i) { 5594 int idx = MaskVals[i]; 5595 if (idx < 0) 5596 continue; 5597 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5598 if ((idx != i) && idx < 4) 5599 pshufhw = false; 5600 if ((idx != i) && idx > 3) 5601 pshuflw = false; 5602 } 5603 V1 = NewV; 5604 V2Used = false; 5605 BestLoQuad = 0; 5606 BestHiQuad = 1; 5607 } 5608 5609 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5610 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5611 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5612 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5613 unsigned TargetMask = 0; 5614 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5615 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5616 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5617 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5618 V1 = NewV.getOperand(0); 5619 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5620 } 5621 } 5622 5623 // If we have SSSE3, and all words of the result are from 1 input vector, 5624 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5625 // is present, fall back to case 4. 5626 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 5627 SmallVector<SDValue,16> pshufbMask; 5628 5629 // If we have elements from both input vectors, set the high bit of the 5630 // shuffle mask element to zero out elements that come from V2 in the V1 5631 // mask, and elements that come from V1 in the V2 mask, so that the two 5632 // results can be OR'd together. 5633 bool TwoInputs = V1Used && V2Used; 5634 for (unsigned i = 0; i != 8; ++i) { 5635 int EltIdx = MaskVals[i] * 2; 5636 if (TwoInputs && (EltIdx >= 16)) { 5637 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5638 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5639 continue; 5640 } 5641 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5642 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5643 } 5644 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5645 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5646 DAG.getNode(ISD::BUILD_VECTOR, dl, 5647 MVT::v16i8, &pshufbMask[0], 16)); 5648 if (!TwoInputs) 5649 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5650 5651 // Calculate the shuffle mask for the second input, shuffle it, and 5652 // OR it with the first shuffled input. 5653 pshufbMask.clear(); 5654 for (unsigned i = 0; i != 8; ++i) { 5655 int EltIdx = MaskVals[i] * 2; 5656 if (EltIdx < 16) { 5657 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5658 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5659 continue; 5660 } 5661 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5662 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5663 } 5664 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5665 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5666 DAG.getNode(ISD::BUILD_VECTOR, dl, 5667 MVT::v16i8, &pshufbMask[0], 16)); 5668 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5669 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5670 } 5671 5672 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5673 // and update MaskVals with new element order. 5674 BitVector InOrder(8); 5675 if (BestLoQuad >= 0) { 5676 SmallVector<int, 8> MaskV; 5677 for (int i = 0; i != 4; ++i) { 5678 int idx = MaskVals[i]; 5679 if (idx < 0) { 5680 MaskV.push_back(-1); 5681 InOrder.set(i); 5682 } else if ((idx / 4) == BestLoQuad) { 5683 MaskV.push_back(idx & 3); 5684 InOrder.set(i); 5685 } else { 5686 MaskV.push_back(-1); 5687 } 5688 } 5689 for (unsigned i = 4; i != 8; ++i) 5690 MaskV.push_back(i); 5691 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5692 &MaskV[0]); 5693 5694 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && 5695 (Subtarget->hasSSSE3() || Subtarget->hasAVX())) 5696 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5697 NewV.getOperand(0), 5698 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5699 DAG); 5700 } 5701 5702 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5703 // and update MaskVals with the new element order. 5704 if (BestHiQuad >= 0) { 5705 SmallVector<int, 8> MaskV; 5706 for (unsigned i = 0; i != 4; ++i) 5707 MaskV.push_back(i); 5708 for (unsigned i = 4; i != 8; ++i) { 5709 int idx = MaskVals[i]; 5710 if (idx < 0) { 5711 MaskV.push_back(-1); 5712 InOrder.set(i); 5713 } else if ((idx / 4) == BestHiQuad) { 5714 MaskV.push_back((idx & 3) + 4); 5715 InOrder.set(i); 5716 } else { 5717 MaskV.push_back(-1); 5718 } 5719 } 5720 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5721 &MaskV[0]); 5722 5723 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && 5724 (Subtarget->hasSSSE3() || Subtarget->hasAVX())) 5725 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5726 NewV.getOperand(0), 5727 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5728 DAG); 5729 } 5730 5731 // In case BestHi & BestLo were both -1, which means each quadword has a word 5732 // from each of the four input quadwords, calculate the InOrder bitvector now 5733 // before falling through to the insert/extract cleanup. 5734 if (BestLoQuad == -1 && BestHiQuad == -1) { 5735 NewV = V1; 5736 for (int i = 0; i != 8; ++i) 5737 if (MaskVals[i] < 0 || MaskVals[i] == i) 5738 InOrder.set(i); 5739 } 5740 5741 // The other elements are put in the right place using pextrw and pinsrw. 5742 for (unsigned i = 0; i != 8; ++i) { 5743 if (InOrder[i]) 5744 continue; 5745 int EltIdx = MaskVals[i]; 5746 if (EltIdx < 0) 5747 continue; 5748 SDValue ExtOp = (EltIdx < 8) 5749 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5750 DAG.getIntPtrConstant(EltIdx)) 5751 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5752 DAG.getIntPtrConstant(EltIdx - 8)); 5753 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5754 DAG.getIntPtrConstant(i)); 5755 } 5756 return NewV; 5757} 5758 5759// v16i8 shuffles - Prefer shuffles in the following order: 5760// 1. [ssse3] 1 x pshufb 5761// 2. [ssse3] 2 x pshufb + 1 x por 5762// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5763static 5764SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5765 SelectionDAG &DAG, 5766 const X86TargetLowering &TLI) { 5767 SDValue V1 = SVOp->getOperand(0); 5768 SDValue V2 = SVOp->getOperand(1); 5769 DebugLoc dl = SVOp->getDebugLoc(); 5770 SmallVector<int, 16> MaskVals; 5771 SVOp->getMask(MaskVals); 5772 5773 // If we have SSSE3, case 1 is generated when all result bytes come from 5774 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5775 // present, fall back to case 3. 5776 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5777 bool V1Only = true; 5778 bool V2Only = true; 5779 for (unsigned i = 0; i < 16; ++i) { 5780 int EltIdx = MaskVals[i]; 5781 if (EltIdx < 0) 5782 continue; 5783 if (EltIdx < 16) 5784 V2Only = false; 5785 else 5786 V1Only = false; 5787 } 5788 5789 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5790 if (TLI.getSubtarget()->hasSSSE3() || TLI.getSubtarget()->hasAVX()) { 5791 SmallVector<SDValue,16> pshufbMask; 5792 5793 // If all result elements are from one input vector, then only translate 5794 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5795 // 5796 // Otherwise, we have elements from both input vectors, and must zero out 5797 // elements that come from V2 in the first mask, and V1 in the second mask 5798 // so that we can OR them together. 5799 bool TwoInputs = !(V1Only || V2Only); 5800 for (unsigned i = 0; i != 16; ++i) { 5801 int EltIdx = MaskVals[i]; 5802 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5803 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5804 continue; 5805 } 5806 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5807 } 5808 // If all the elements are from V2, assign it to V1 and return after 5809 // building the first pshufb. 5810 if (V2Only) 5811 V1 = V2; 5812 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5813 DAG.getNode(ISD::BUILD_VECTOR, dl, 5814 MVT::v16i8, &pshufbMask[0], 16)); 5815 if (!TwoInputs) 5816 return V1; 5817 5818 // Calculate the shuffle mask for the second input, shuffle it, and 5819 // OR it with the first shuffled input. 5820 pshufbMask.clear(); 5821 for (unsigned i = 0; i != 16; ++i) { 5822 int EltIdx = MaskVals[i]; 5823 if (EltIdx < 16) { 5824 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5825 continue; 5826 } 5827 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5828 } 5829 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5830 DAG.getNode(ISD::BUILD_VECTOR, dl, 5831 MVT::v16i8, &pshufbMask[0], 16)); 5832 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5833 } 5834 5835 // No SSSE3 - Calculate in place words and then fix all out of place words 5836 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5837 // the 16 different words that comprise the two doublequadword input vectors. 5838 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5839 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5840 SDValue NewV = V2Only ? V2 : V1; 5841 for (int i = 0; i != 8; ++i) { 5842 int Elt0 = MaskVals[i*2]; 5843 int Elt1 = MaskVals[i*2+1]; 5844 5845 // This word of the result is all undef, skip it. 5846 if (Elt0 < 0 && Elt1 < 0) 5847 continue; 5848 5849 // This word of the result is already in the correct place, skip it. 5850 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5851 continue; 5852 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5853 continue; 5854 5855 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5856 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5857 SDValue InsElt; 5858 5859 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5860 // using a single extract together, load it and store it. 5861 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5862 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5863 DAG.getIntPtrConstant(Elt1 / 2)); 5864 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5865 DAG.getIntPtrConstant(i)); 5866 continue; 5867 } 5868 5869 // If Elt1 is defined, extract it from the appropriate source. If the 5870 // source byte is not also odd, shift the extracted word left 8 bits 5871 // otherwise clear the bottom 8 bits if we need to do an or. 5872 if (Elt1 >= 0) { 5873 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5874 DAG.getIntPtrConstant(Elt1 / 2)); 5875 if ((Elt1 & 1) == 0) 5876 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5877 DAG.getConstant(8, 5878 TLI.getShiftAmountTy(InsElt.getValueType()))); 5879 else if (Elt0 >= 0) 5880 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5881 DAG.getConstant(0xFF00, MVT::i16)); 5882 } 5883 // If Elt0 is defined, extract it from the appropriate source. If the 5884 // source byte is not also even, shift the extracted word right 8 bits. If 5885 // Elt1 was also defined, OR the extracted values together before 5886 // inserting them in the result. 5887 if (Elt0 >= 0) { 5888 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5889 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5890 if ((Elt0 & 1) != 0) 5891 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5892 DAG.getConstant(8, 5893 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5894 else if (Elt1 >= 0) 5895 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5896 DAG.getConstant(0x00FF, MVT::i16)); 5897 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5898 : InsElt0; 5899 } 5900 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5901 DAG.getIntPtrConstant(i)); 5902 } 5903 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5904} 5905 5906/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5907/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5908/// done when every pair / quad of shuffle mask elements point to elements in 5909/// the right sequence. e.g. 5910/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5911static 5912SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5913 SelectionDAG &DAG, DebugLoc dl) { 5914 EVT VT = SVOp->getValueType(0); 5915 SDValue V1 = SVOp->getOperand(0); 5916 SDValue V2 = SVOp->getOperand(1); 5917 unsigned NumElems = VT.getVectorNumElements(); 5918 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5919 EVT NewVT; 5920 switch (VT.getSimpleVT().SimpleTy) { 5921 default: assert(false && "Unexpected!"); 5922 case MVT::v4f32: NewVT = MVT::v2f64; break; 5923 case MVT::v4i32: NewVT = MVT::v2i64; break; 5924 case MVT::v8i16: NewVT = MVT::v4i32; break; 5925 case MVT::v16i8: NewVT = MVT::v4i32; break; 5926 } 5927 5928 int Scale = NumElems / NewWidth; 5929 SmallVector<int, 8> MaskVec; 5930 for (unsigned i = 0; i < NumElems; i += Scale) { 5931 int StartIdx = -1; 5932 for (int j = 0; j < Scale; ++j) { 5933 int EltIdx = SVOp->getMaskElt(i+j); 5934 if (EltIdx < 0) 5935 continue; 5936 if (StartIdx == -1) 5937 StartIdx = EltIdx - (EltIdx % Scale); 5938 if (EltIdx != StartIdx + j) 5939 return SDValue(); 5940 } 5941 if (StartIdx == -1) 5942 MaskVec.push_back(-1); 5943 else 5944 MaskVec.push_back(StartIdx / Scale); 5945 } 5946 5947 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5948 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5949 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5950} 5951 5952/// getVZextMovL - Return a zero-extending vector move low node. 5953/// 5954static SDValue getVZextMovL(EVT VT, EVT OpVT, 5955 SDValue SrcOp, SelectionDAG &DAG, 5956 const X86Subtarget *Subtarget, DebugLoc dl) { 5957 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5958 LoadSDNode *LD = NULL; 5959 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5960 LD = dyn_cast<LoadSDNode>(SrcOp); 5961 if (!LD) { 5962 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5963 // instead. 5964 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5965 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5966 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5967 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5968 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5969 // PR2108 5970 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5971 return DAG.getNode(ISD::BITCAST, dl, VT, 5972 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5973 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5974 OpVT, 5975 SrcOp.getOperand(0) 5976 .getOperand(0)))); 5977 } 5978 } 5979 } 5980 5981 return DAG.getNode(ISD::BITCAST, dl, VT, 5982 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5983 DAG.getNode(ISD::BITCAST, dl, 5984 OpVT, SrcOp))); 5985} 5986 5987/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5988/// shuffle node referes to only one lane in the sources. 5989static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5990 EVT VT = SVOp->getValueType(0); 5991 int NumElems = VT.getVectorNumElements(); 5992 int HalfSize = NumElems/2; 5993 SmallVector<int, 16> M; 5994 SVOp->getMask(M); 5995 bool MatchA = false, MatchB = false; 5996 5997 for (int l = 0; l < NumElems*2; l += HalfSize) { 5998 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5999 MatchA = true; 6000 break; 6001 } 6002 } 6003 6004 for (int l = 0; l < NumElems*2; l += HalfSize) { 6005 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 6006 MatchB = true; 6007 break; 6008 } 6009 } 6010 6011 return MatchA && MatchB; 6012} 6013 6014/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 6015/// which could not be matched by any known target speficic shuffle 6016static SDValue 6017LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6018 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 6019 // If each half of a vector shuffle node referes to only one lane in the 6020 // source vectors, extract each used 128-bit lane and shuffle them using 6021 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 6022 // the work to the legalizer. 6023 DebugLoc dl = SVOp->getDebugLoc(); 6024 EVT VT = SVOp->getValueType(0); 6025 int NumElems = VT.getVectorNumElements(); 6026 int HalfSize = NumElems/2; 6027 6028 // Extract the reference for each half 6029 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 6030 int FstVecOpNum = 0, SndVecOpNum = 0; 6031 for (int i = 0; i < HalfSize; ++i) { 6032 int Elt = SVOp->getMaskElt(i); 6033 if (SVOp->getMaskElt(i) < 0) 6034 continue; 6035 FstVecOpNum = Elt/NumElems; 6036 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 6037 break; 6038 } 6039 for (int i = HalfSize; i < NumElems; ++i) { 6040 int Elt = SVOp->getMaskElt(i); 6041 if (SVOp->getMaskElt(i) < 0) 6042 continue; 6043 SndVecOpNum = Elt/NumElems; 6044 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 6045 break; 6046 } 6047 6048 // Extract the subvectors 6049 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 6050 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 6051 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 6052 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 6053 6054 // Generate 128-bit shuffles 6055 SmallVector<int, 16> MaskV1, MaskV2; 6056 for (int i = 0; i < HalfSize; ++i) { 6057 int Elt = SVOp->getMaskElt(i); 6058 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6059 } 6060 for (int i = HalfSize; i < NumElems; ++i) { 6061 int Elt = SVOp->getMaskElt(i); 6062 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 6063 } 6064 6065 EVT NVT = V1.getValueType(); 6066 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 6067 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 6068 6069 // Concatenate the result back 6070 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 6071 DAG.getConstant(0, MVT::i32), DAG, dl); 6072 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 6073 DAG, dl); 6074 } 6075 6076 return SDValue(); 6077} 6078 6079/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6080/// 4 elements, and match them with several different shuffle types. 6081static SDValue 6082LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6083 SDValue V1 = SVOp->getOperand(0); 6084 SDValue V2 = SVOp->getOperand(1); 6085 DebugLoc dl = SVOp->getDebugLoc(); 6086 EVT VT = SVOp->getValueType(0); 6087 6088 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6089 6090 SmallVector<std::pair<int, int>, 8> Locs; 6091 Locs.resize(4); 6092 SmallVector<int, 8> Mask1(4U, -1); 6093 SmallVector<int, 8> PermMask; 6094 SVOp->getMask(PermMask); 6095 6096 unsigned NumHi = 0; 6097 unsigned NumLo = 0; 6098 for (unsigned i = 0; i != 4; ++i) { 6099 int Idx = PermMask[i]; 6100 if (Idx < 0) { 6101 Locs[i] = std::make_pair(-1, -1); 6102 } else { 6103 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6104 if (Idx < 4) { 6105 Locs[i] = std::make_pair(0, NumLo); 6106 Mask1[NumLo] = Idx; 6107 NumLo++; 6108 } else { 6109 Locs[i] = std::make_pair(1, NumHi); 6110 if (2+NumHi < 4) 6111 Mask1[2+NumHi] = Idx; 6112 NumHi++; 6113 } 6114 } 6115 } 6116 6117 if (NumLo <= 2 && NumHi <= 2) { 6118 // If no more than two elements come from either vector. This can be 6119 // implemented with two shuffles. First shuffle gather the elements. 6120 // The second shuffle, which takes the first shuffle as both of its 6121 // vector operands, put the elements into the right order. 6122 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6123 6124 SmallVector<int, 8> Mask2(4U, -1); 6125 6126 for (unsigned i = 0; i != 4; ++i) { 6127 if (Locs[i].first == -1) 6128 continue; 6129 else { 6130 unsigned Idx = (i < 2) ? 0 : 4; 6131 Idx += Locs[i].first * 2 + Locs[i].second; 6132 Mask2[i] = Idx; 6133 } 6134 } 6135 6136 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6137 } else if (NumLo == 3 || NumHi == 3) { 6138 // Otherwise, we must have three elements from one vector, call it X, and 6139 // one element from the other, call it Y. First, use a shufps to build an 6140 // intermediate vector with the one element from Y and the element from X 6141 // that will be in the same half in the final destination (the indexes don't 6142 // matter). Then, use a shufps to build the final vector, taking the half 6143 // containing the element from Y from the intermediate, and the other half 6144 // from X. 6145 if (NumHi == 3) { 6146 // Normalize it so the 3 elements come from V1. 6147 CommuteVectorShuffleMask(PermMask, VT); 6148 std::swap(V1, V2); 6149 } 6150 6151 // Find the element from V2. 6152 unsigned HiIndex; 6153 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6154 int Val = PermMask[HiIndex]; 6155 if (Val < 0) 6156 continue; 6157 if (Val >= 4) 6158 break; 6159 } 6160 6161 Mask1[0] = PermMask[HiIndex]; 6162 Mask1[1] = -1; 6163 Mask1[2] = PermMask[HiIndex^1]; 6164 Mask1[3] = -1; 6165 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6166 6167 if (HiIndex >= 2) { 6168 Mask1[0] = PermMask[0]; 6169 Mask1[1] = PermMask[1]; 6170 Mask1[2] = HiIndex & 1 ? 6 : 4; 6171 Mask1[3] = HiIndex & 1 ? 4 : 6; 6172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6173 } else { 6174 Mask1[0] = HiIndex & 1 ? 2 : 0; 6175 Mask1[1] = HiIndex & 1 ? 0 : 2; 6176 Mask1[2] = PermMask[2]; 6177 Mask1[3] = PermMask[3]; 6178 if (Mask1[2] >= 0) 6179 Mask1[2] += 4; 6180 if (Mask1[3] >= 0) 6181 Mask1[3] += 4; 6182 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6183 } 6184 } 6185 6186 // Break it into (shuffle shuffle_hi, shuffle_lo). 6187 Locs.clear(); 6188 Locs.resize(4); 6189 SmallVector<int,8> LoMask(4U, -1); 6190 SmallVector<int,8> HiMask(4U, -1); 6191 6192 SmallVector<int,8> *MaskPtr = &LoMask; 6193 unsigned MaskIdx = 0; 6194 unsigned LoIdx = 0; 6195 unsigned HiIdx = 2; 6196 for (unsigned i = 0; i != 4; ++i) { 6197 if (i == 2) { 6198 MaskPtr = &HiMask; 6199 MaskIdx = 1; 6200 LoIdx = 0; 6201 HiIdx = 2; 6202 } 6203 int Idx = PermMask[i]; 6204 if (Idx < 0) { 6205 Locs[i] = std::make_pair(-1, -1); 6206 } else if (Idx < 4) { 6207 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6208 (*MaskPtr)[LoIdx] = Idx; 6209 LoIdx++; 6210 } else { 6211 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6212 (*MaskPtr)[HiIdx] = Idx; 6213 HiIdx++; 6214 } 6215 } 6216 6217 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6218 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6219 SmallVector<int, 8> MaskOps; 6220 for (unsigned i = 0; i != 4; ++i) { 6221 if (Locs[i].first == -1) { 6222 MaskOps.push_back(-1); 6223 } else { 6224 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6225 MaskOps.push_back(Idx); 6226 } 6227 } 6228 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6229} 6230 6231static bool MayFoldVectorLoad(SDValue V) { 6232 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6233 V = V.getOperand(0); 6234 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6235 V = V.getOperand(0); 6236 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6237 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6238 // BUILD_VECTOR (load), undef 6239 V = V.getOperand(0); 6240 if (MayFoldLoad(V)) 6241 return true; 6242 return false; 6243} 6244 6245// FIXME: the version above should always be used. Since there's 6246// a bug where several vector shuffles can't be folded because the 6247// DAG is not updated during lowering and a node claims to have two 6248// uses while it only has one, use this version, and let isel match 6249// another instruction if the load really happens to have more than 6250// one use. Remove this version after this bug get fixed. 6251// rdar://8434668, PR8156 6252static bool RelaxedMayFoldVectorLoad(SDValue V) { 6253 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6254 V = V.getOperand(0); 6255 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6256 V = V.getOperand(0); 6257 if (ISD::isNormalLoad(V.getNode())) 6258 return true; 6259 return false; 6260} 6261 6262/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6263/// a vector extract, and if both can be later optimized into a single load. 6264/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6265/// here because otherwise a target specific shuffle node is going to be 6266/// emitted for this shuffle, and the optimization not done. 6267/// FIXME: This is probably not the best approach, but fix the problem 6268/// until the right path is decided. 6269static 6270bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6271 const TargetLowering &TLI) { 6272 EVT VT = V.getValueType(); 6273 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6274 6275 // Be sure that the vector shuffle is present in a pattern like this: 6276 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6277 if (!V.hasOneUse()) 6278 return false; 6279 6280 SDNode *N = *V.getNode()->use_begin(); 6281 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6282 return false; 6283 6284 SDValue EltNo = N->getOperand(1); 6285 if (!isa<ConstantSDNode>(EltNo)) 6286 return false; 6287 6288 // If the bit convert changed the number of elements, it is unsafe 6289 // to examine the mask. 6290 bool HasShuffleIntoBitcast = false; 6291 if (V.getOpcode() == ISD::BITCAST) { 6292 EVT SrcVT = V.getOperand(0).getValueType(); 6293 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6294 return false; 6295 V = V.getOperand(0); 6296 HasShuffleIntoBitcast = true; 6297 } 6298 6299 // Select the input vector, guarding against out of range extract vector. 6300 unsigned NumElems = VT.getVectorNumElements(); 6301 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6302 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6303 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6304 6305 // Skip one more bit_convert if necessary 6306 if (V.getOpcode() == ISD::BITCAST) 6307 V = V.getOperand(0); 6308 6309 if (ISD::isNormalLoad(V.getNode())) { 6310 // Is the original load suitable? 6311 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6312 6313 // FIXME: avoid the multi-use bug that is preventing lots of 6314 // of foldings to be detected, this is still wrong of course, but 6315 // give the temporary desired behavior, and if it happens that 6316 // the load has real more uses, during isel it will not fold, and 6317 // will generate poor code. 6318 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 6319 return false; 6320 6321 if (!HasShuffleIntoBitcast) 6322 return true; 6323 6324 // If there's a bitcast before the shuffle, check if the load type and 6325 // alignment is valid. 6326 unsigned Align = LN0->getAlignment(); 6327 unsigned NewAlign = 6328 TLI.getTargetData()->getABITypeAlignment( 6329 VT.getTypeForEVT(*DAG.getContext())); 6330 6331 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6332 return false; 6333 } 6334 6335 return true; 6336} 6337 6338static 6339SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6340 EVT VT = Op.getValueType(); 6341 6342 // Canonizalize to v2f64. 6343 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6344 return DAG.getNode(ISD::BITCAST, dl, VT, 6345 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6346 V1, DAG)); 6347} 6348 6349static 6350SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6351 bool HasXMMInt) { 6352 SDValue V1 = Op.getOperand(0); 6353 SDValue V2 = Op.getOperand(1); 6354 EVT VT = Op.getValueType(); 6355 6356 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6357 6358 if (HasXMMInt && VT == MVT::v2f64) 6359 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6360 6361 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6362 return DAG.getNode(ISD::BITCAST, dl, VT, 6363 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6364 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6365 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6366} 6367 6368static 6369SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6370 SDValue V1 = Op.getOperand(0); 6371 SDValue V2 = Op.getOperand(1); 6372 EVT VT = Op.getValueType(); 6373 6374 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6375 "unsupported shuffle type"); 6376 6377 if (V2.getOpcode() == ISD::UNDEF) 6378 V2 = V1; 6379 6380 // v4i32 or v4f32 6381 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6382} 6383 6384static inline unsigned getSHUFPOpcode(EVT VT) { 6385 switch(VT.getSimpleVT().SimpleTy) { 6386 case MVT::v8i32: // Use fp unit for int unpack. 6387 case MVT::v8f32: 6388 case MVT::v4i32: // Use fp unit for int unpack. 6389 case MVT::v4f32: return X86ISD::SHUFPS; 6390 case MVT::v4i64: // Use fp unit for int unpack. 6391 case MVT::v4f64: 6392 case MVT::v2i64: // Use fp unit for int unpack. 6393 case MVT::v2f64: return X86ISD::SHUFPD; 6394 default: 6395 llvm_unreachable("Unknown type for shufp*"); 6396 } 6397 return 0; 6398} 6399 6400static 6401SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) { 6402 SDValue V1 = Op.getOperand(0); 6403 SDValue V2 = Op.getOperand(1); 6404 EVT VT = Op.getValueType(); 6405 unsigned NumElems = VT.getVectorNumElements(); 6406 6407 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6408 // operand of these instructions is only memory, so check if there's a 6409 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6410 // same masks. 6411 bool CanFoldLoad = false; 6412 6413 // Trivial case, when V2 comes from a load. 6414 if (MayFoldVectorLoad(V2)) 6415 CanFoldLoad = true; 6416 6417 // When V1 is a load, it can be folded later into a store in isel, example: 6418 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6419 // turns into: 6420 // (MOVLPSmr addr:$src1, VR128:$src2) 6421 // So, recognize this potential and also use MOVLPS or MOVLPD 6422 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6423 CanFoldLoad = true; 6424 6425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6426 if (CanFoldLoad) { 6427 if (HasXMMInt && NumElems == 2) 6428 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6429 6430 if (NumElems == 4) 6431 // If we don't care about the second element, procede to use movss. 6432 if (SVOp->getMaskElt(1) != -1) 6433 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6434 } 6435 6436 // movl and movlp will both match v2i64, but v2i64 is never matched by 6437 // movl earlier because we make it strict to avoid messing with the movlp load 6438 // folding logic (see the code above getMOVLP call). Match it here then, 6439 // this is horrible, but will stay like this until we move all shuffle 6440 // matching to x86 specific nodes. Note that for the 1st condition all 6441 // types are matched with movsd. 6442 if (HasXMMInt) { 6443 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6444 // as to remove this logic from here, as much as possible 6445 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6446 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6447 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6448 } 6449 6450 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6451 6452 // Invert the operand order and use SHUFPS to match it. 6453 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1, 6454 X86::getShuffleSHUFImmediate(SVOp), DAG); 6455} 6456 6457static inline unsigned getUNPCKLOpcode(EVT VT) { 6458 switch(VT.getSimpleVT().SimpleTy) { 6459 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 6460 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 6461 case MVT::v4f32: return X86ISD::UNPCKLPS; 6462 case MVT::v2f64: return X86ISD::UNPCKLPD; 6463 case MVT::v8i32: // Use fp unit for int unpack. 6464 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 6465 case MVT::v4i64: // Use fp unit for int unpack. 6466 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 6467 case MVT::v16i8: return X86ISD::PUNPCKLBW; 6468 case MVT::v8i16: return X86ISD::PUNPCKLWD; 6469 default: 6470 llvm_unreachable("Unknown type for unpckl"); 6471 } 6472 return 0; 6473} 6474 6475static inline unsigned getUNPCKHOpcode(EVT VT) { 6476 switch(VT.getSimpleVT().SimpleTy) { 6477 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 6478 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 6479 case MVT::v4f32: return X86ISD::UNPCKHPS; 6480 case MVT::v2f64: return X86ISD::UNPCKHPD; 6481 case MVT::v8i32: // Use fp unit for int unpack. 6482 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 6483 case MVT::v4i64: // Use fp unit for int unpack. 6484 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 6485 case MVT::v16i8: return X86ISD::PUNPCKHBW; 6486 case MVT::v8i16: return X86ISD::PUNPCKHWD; 6487 default: 6488 llvm_unreachable("Unknown type for unpckh"); 6489 } 6490 return 0; 6491} 6492 6493static inline unsigned getVPERMILOpcode(EVT VT) { 6494 switch(VT.getSimpleVT().SimpleTy) { 6495 case MVT::v4i32: 6496 case MVT::v4f32: return X86ISD::VPERMILPS; 6497 case MVT::v2i64: 6498 case MVT::v2f64: return X86ISD::VPERMILPD; 6499 case MVT::v8i32: 6500 case MVT::v8f32: return X86ISD::VPERMILPSY; 6501 case MVT::v4i64: 6502 case MVT::v4f64: return X86ISD::VPERMILPDY; 6503 default: 6504 llvm_unreachable("Unknown type for vpermil"); 6505 } 6506 return 0; 6507} 6508 6509/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 6510/// a vbroadcast node. The nodes are suitable whenever we can fold a load coming 6511/// from a 32 or 64 bit scalar. Update Op to the desired load to be folded. 6512static bool isVectorBroadcast(SDValue &Op) { 6513 EVT VT = Op.getValueType(); 6514 bool Is256 = VT.getSizeInBits() == 256; 6515 6516 assert((VT.getSizeInBits() == 128 || Is256) && 6517 "Unsupported type for vbroadcast node"); 6518 6519 SDValue V = Op; 6520 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6521 V = V.getOperand(0); 6522 6523 if (Is256 && !(V.hasOneUse() && 6524 V.getOpcode() == ISD::INSERT_SUBVECTOR && 6525 V.getOperand(0).getOpcode() == ISD::UNDEF)) 6526 return false; 6527 6528 if (Is256) 6529 V = V.getOperand(1); 6530 6531 if (!V.hasOneUse()) 6532 return false; 6533 6534 // Check the source scalar_to_vector type. 256-bit broadcasts are 6535 // supported for 32/64-bit sizes, while 128-bit ones are only supported 6536 // for 32-bit scalars. 6537 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR) 6538 return false; 6539 6540 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits(); 6541 if (ScalarSize != 32 && ScalarSize != 64) 6542 return false; 6543 if (!Is256 && ScalarSize == 64) 6544 return false; 6545 6546 V = V.getOperand(0); 6547 if (!MayFoldLoad(V)) 6548 return false; 6549 6550 // Return the load node 6551 Op = V; 6552 return true; 6553} 6554 6555static 6556SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6557 const TargetLowering &TLI, 6558 const X86Subtarget *Subtarget) { 6559 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6560 EVT VT = Op.getValueType(); 6561 DebugLoc dl = Op.getDebugLoc(); 6562 SDValue V1 = Op.getOperand(0); 6563 SDValue V2 = Op.getOperand(1); 6564 6565 if (isZeroShuffle(SVOp)) 6566 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 6567 6568 // Handle splat operations 6569 if (SVOp->isSplat()) { 6570 unsigned NumElem = VT.getVectorNumElements(); 6571 int Size = VT.getSizeInBits(); 6572 // Special case, this is the only place now where it's allowed to return 6573 // a vector_shuffle operation without using a target specific node, because 6574 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6575 // this be moved to DAGCombine instead? 6576 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6577 return Op; 6578 6579 // Use vbroadcast whenever the splat comes from a foldable load 6580 if (Subtarget->hasAVX() && isVectorBroadcast(V1)) 6581 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1); 6582 6583 // Handle splats by matching through known shuffle masks 6584 if ((Size == 128 && NumElem <= 4) || 6585 (Size == 256 && NumElem < 8)) 6586 return SDValue(); 6587 6588 // All remaning splats are promoted to target supported vector shuffles. 6589 return PromoteSplat(SVOp, DAG); 6590 } 6591 6592 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6593 // do it! 6594 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6595 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6596 if (NewOp.getNode()) 6597 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6598 } else if ((VT == MVT::v4i32 || 6599 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) { 6600 // FIXME: Figure out a cleaner way to do this. 6601 // Try to make use of movq to zero out the top part. 6602 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6603 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6604 if (NewOp.getNode()) { 6605 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6606 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6607 DAG, Subtarget, dl); 6608 } 6609 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6610 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6611 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6612 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6613 DAG, Subtarget, dl); 6614 } 6615 } 6616 return SDValue(); 6617} 6618 6619SDValue 6620X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6621 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6622 SDValue V1 = Op.getOperand(0); 6623 SDValue V2 = Op.getOperand(1); 6624 EVT VT = Op.getValueType(); 6625 DebugLoc dl = Op.getDebugLoc(); 6626 unsigned NumElems = VT.getVectorNumElements(); 6627 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6628 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6629 bool V1IsSplat = false; 6630 bool V2IsSplat = false; 6631 bool HasXMMInt = Subtarget->hasXMMInt(); 6632 MachineFunction &MF = DAG.getMachineFunction(); 6633 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6634 6635 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6636 6637 // Vector shuffle lowering takes 3 steps: 6638 // 6639 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6640 // narrowing and commutation of operands should be handled. 6641 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6642 // shuffle nodes. 6643 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6644 // so the shuffle can be broken into other shuffles and the legalizer can 6645 // try the lowering again. 6646 // 6647 // The general idea is that no vector_shuffle operation should be left to 6648 // be matched during isel, all of them must be converted to a target specific 6649 // node here. 6650 6651 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6652 // narrowing and commutation of operands should be handled. The actual code 6653 // doesn't include all of those, work in progress... 6654 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6655 if (NewOp.getNode()) 6656 return NewOp; 6657 6658 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6659 // unpckh_undef). Only use pshufd if speed is more important than size. 6660 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6661 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6662 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6663 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6664 6665 if (X86::isMOVDDUPMask(SVOp) && 6666 (Subtarget->hasSSE3() || Subtarget->hasAVX()) && 6667 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6668 return getMOVDDup(Op, dl, V1, DAG); 6669 6670 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6671 return getMOVHighToLow(Op, dl, DAG); 6672 6673 // Use to match splats 6674 if (HasXMMInt && X86::isUNPCKHMask(SVOp) && V2IsUndef && 6675 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6676 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6677 6678 if (X86::isPSHUFDMask(SVOp)) { 6679 // The actual implementation will match the mask in the if above and then 6680 // during isel it can match several different instructions, not only pshufd 6681 // as its name says, sad but true, emulate the behavior for now... 6682 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6683 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6684 6685 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6686 6687 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6688 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6689 6690 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1, 6691 TargetMask, DAG); 6692 } 6693 6694 // Check if this can be converted into a logical shift. 6695 bool isLeft = false; 6696 unsigned ShAmt = 0; 6697 SDValue ShVal; 6698 bool isShift = getSubtarget()->hasXMMInt() && 6699 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6700 if (isShift && ShVal.hasOneUse()) { 6701 // If the shifted value has multiple uses, it may be cheaper to use 6702 // v_set0 + movlhps or movhlps, etc. 6703 EVT EltVT = VT.getVectorElementType(); 6704 ShAmt *= EltVT.getSizeInBits(); 6705 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6706 } 6707 6708 if (X86::isMOVLMask(SVOp)) { 6709 if (V1IsUndef) 6710 return V2; 6711 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6712 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6713 if (!X86::isMOVLPMask(SVOp)) { 6714 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6715 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6716 6717 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6718 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6719 } 6720 } 6721 6722 // FIXME: fold these into legal mask. 6723 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 6724 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt); 6725 6726 if (X86::isMOVHLPSMask(SVOp)) 6727 return getMOVHighToLow(Op, dl, DAG); 6728 6729 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6730 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6731 6732 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6733 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6734 6735 if (X86::isMOVLPMask(SVOp)) 6736 return getMOVLP(Op, dl, DAG, HasXMMInt); 6737 6738 if (ShouldXformToMOVHLPS(SVOp) || 6739 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6740 return CommuteVectorShuffle(SVOp, DAG); 6741 6742 if (isShift) { 6743 // No better options. Use a vshl / vsrl. 6744 EVT EltVT = VT.getVectorElementType(); 6745 ShAmt *= EltVT.getSizeInBits(); 6746 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6747 } 6748 6749 bool Commuted = false; 6750 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6751 // 1,1,1,1 -> v8i16 though. 6752 V1IsSplat = isSplatVector(V1.getNode()); 6753 V2IsSplat = isSplatVector(V2.getNode()); 6754 6755 // Canonicalize the splat or undef, if present, to be on the RHS. 6756 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6757 Op = CommuteVectorShuffle(SVOp, DAG); 6758 SVOp = cast<ShuffleVectorSDNode>(Op); 6759 V1 = SVOp->getOperand(0); 6760 V2 = SVOp->getOperand(1); 6761 std::swap(V1IsSplat, V2IsSplat); 6762 std::swap(V1IsUndef, V2IsUndef); 6763 Commuted = true; 6764 } 6765 6766 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6767 // Shuffling low element of v1 into undef, just return v1. 6768 if (V2IsUndef) 6769 return V1; 6770 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6771 // the instruction selector will not match, so get a canonical MOVL with 6772 // swapped operands to undo the commute. 6773 return getMOVL(DAG, dl, VT, V2, V1); 6774 } 6775 6776 if (X86::isUNPCKLMask(SVOp)) 6777 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 6778 6779 if (X86::isUNPCKHMask(SVOp)) 6780 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 6781 6782 if (V2IsSplat) { 6783 // Normalize mask so all entries that point to V2 points to its first 6784 // element then try to match unpck{h|l} again. If match, return a 6785 // new vector_shuffle with the corrected mask. 6786 SDValue NewMask = NormalizeMask(SVOp, DAG); 6787 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6788 if (NSVOp != SVOp) { 6789 if (X86::isUNPCKLMask(NSVOp, true)) { 6790 return NewMask; 6791 } else if (X86::isUNPCKHMask(NSVOp, true)) { 6792 return NewMask; 6793 } 6794 } 6795 } 6796 6797 if (Commuted) { 6798 // Commute is back and try unpck* again. 6799 // FIXME: this seems wrong. 6800 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6801 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6802 6803 if (X86::isUNPCKLMask(NewSVOp)) 6804 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 6805 6806 if (X86::isUNPCKHMask(NewSVOp)) 6807 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 6808 } 6809 6810 // Normalize the node to match x86 shuffle ops if needed 6811 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6812 return CommuteVectorShuffle(SVOp, DAG); 6813 6814 // The checks below are all present in isShuffleMaskLegal, but they are 6815 // inlined here right now to enable us to directly emit target specific 6816 // nodes, and remove one by one until they don't return Op anymore. 6817 SmallVector<int, 16> M; 6818 SVOp->getMask(M); 6819 6820 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX())) 6821 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6822 X86::getShufflePALIGNRImmediate(SVOp), 6823 DAG); 6824 6825 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6826 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6827 if (VT == MVT::v2f64) 6828 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6829 if (VT == MVT::v2i64) 6830 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6831 } 6832 6833 if (isPSHUFHWMask(M, VT)) 6834 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6835 X86::getShufflePSHUFHWImmediate(SVOp), 6836 DAG); 6837 6838 if (isPSHUFLWMask(M, VT)) 6839 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6840 X86::getShufflePSHUFLWImmediate(SVOp), 6841 DAG); 6842 6843 if (isSHUFPMask(M, VT)) 6844 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6845 X86::getShuffleSHUFImmediate(SVOp), DAG); 6846 6847 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6848 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6849 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6850 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6851 6852 //===--------------------------------------------------------------------===// 6853 // Generate target specific nodes for 128 or 256-bit shuffles only 6854 // supported in the AVX instruction set. 6855 // 6856 6857 // Handle VMOVDDUPY permutations 6858 if (isMOVDDUPYMask(SVOp, Subtarget)) 6859 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6860 6861 // Handle VPERMILPS* permutations 6862 if (isVPERMILPSMask(M, VT, Subtarget)) 6863 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6864 getShuffleVPERMILPSImmediate(SVOp), DAG); 6865 6866 // Handle VPERMILPD* permutations 6867 if (isVPERMILPDMask(M, VT, Subtarget)) 6868 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6869 getShuffleVPERMILPDImmediate(SVOp), DAG); 6870 6871 // Handle VPERM2F128 permutations 6872 if (isVPERM2F128Mask(M, VT, Subtarget)) 6873 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2, 6874 getShuffleVPERM2F128Immediate(SVOp), DAG); 6875 6876 // Handle VSHUFPSY permutations 6877 if (isVSHUFPSYMask(M, VT, Subtarget)) 6878 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6879 getShuffleVSHUFPSYImmediate(SVOp), DAG); 6880 6881 // Handle VSHUFPDY permutations 6882 if (isVSHUFPDYMask(M, VT, Subtarget)) 6883 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6884 getShuffleVSHUFPDYImmediate(SVOp), DAG); 6885 6886 //===--------------------------------------------------------------------===// 6887 // Since no target specific shuffle was selected for this generic one, 6888 // lower it into other known shuffles. FIXME: this isn't true yet, but 6889 // this is the plan. 6890 // 6891 6892 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6893 if (VT == MVT::v8i16) { 6894 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6895 if (NewOp.getNode()) 6896 return NewOp; 6897 } 6898 6899 if (VT == MVT::v16i8) { 6900 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6901 if (NewOp.getNode()) 6902 return NewOp; 6903 } 6904 6905 // Handle all 128-bit wide vectors with 4 elements, and match them with 6906 // several different shuffle types. 6907 if (NumElems == 4 && VT.getSizeInBits() == 128) 6908 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6909 6910 // Handle general 256-bit shuffles 6911 if (VT.is256BitVector()) 6912 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6913 6914 return SDValue(); 6915} 6916 6917SDValue 6918X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6919 SelectionDAG &DAG) const { 6920 EVT VT = Op.getValueType(); 6921 DebugLoc dl = Op.getDebugLoc(); 6922 6923 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6924 return SDValue(); 6925 6926 if (VT.getSizeInBits() == 8) { 6927 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6928 Op.getOperand(0), Op.getOperand(1)); 6929 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6930 DAG.getValueType(VT)); 6931 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6932 } else if (VT.getSizeInBits() == 16) { 6933 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6934 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6935 if (Idx == 0) 6936 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6937 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6938 DAG.getNode(ISD::BITCAST, dl, 6939 MVT::v4i32, 6940 Op.getOperand(0)), 6941 Op.getOperand(1))); 6942 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6943 Op.getOperand(0), Op.getOperand(1)); 6944 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6945 DAG.getValueType(VT)); 6946 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6947 } else if (VT == MVT::f32) { 6948 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6949 // the result back to FR32 register. It's only worth matching if the 6950 // result has a single use which is a store or a bitcast to i32. And in 6951 // the case of a store, it's not worth it if the index is a constant 0, 6952 // because a MOVSSmr can be used instead, which is smaller and faster. 6953 if (!Op.hasOneUse()) 6954 return SDValue(); 6955 SDNode *User = *Op.getNode()->use_begin(); 6956 if ((User->getOpcode() != ISD::STORE || 6957 (isa<ConstantSDNode>(Op.getOperand(1)) && 6958 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6959 (User->getOpcode() != ISD::BITCAST || 6960 User->getValueType(0) != MVT::i32)) 6961 return SDValue(); 6962 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6963 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6964 Op.getOperand(0)), 6965 Op.getOperand(1)); 6966 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6967 } else if (VT == MVT::i32 || VT == MVT::i64) { 6968 // ExtractPS/pextrq works with constant index. 6969 if (isa<ConstantSDNode>(Op.getOperand(1))) 6970 return Op; 6971 } 6972 return SDValue(); 6973} 6974 6975 6976SDValue 6977X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6978 SelectionDAG &DAG) const { 6979 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6980 return SDValue(); 6981 6982 SDValue Vec = Op.getOperand(0); 6983 EVT VecVT = Vec.getValueType(); 6984 6985 // If this is a 256-bit vector result, first extract the 128-bit vector and 6986 // then extract the element from the 128-bit vector. 6987 if (VecVT.getSizeInBits() == 256) { 6988 DebugLoc dl = Op.getNode()->getDebugLoc(); 6989 unsigned NumElems = VecVT.getVectorNumElements(); 6990 SDValue Idx = Op.getOperand(1); 6991 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6992 6993 // Get the 128-bit vector. 6994 bool Upper = IdxVal >= NumElems/2; 6995 Vec = Extract128BitVector(Vec, 6996 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6997 6998 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6999 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 7000 } 7001 7002 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 7003 7004 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 7005 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 7006 if (Res.getNode()) 7007 return Res; 7008 } 7009 7010 EVT VT = Op.getValueType(); 7011 DebugLoc dl = Op.getDebugLoc(); 7012 // TODO: handle v16i8. 7013 if (VT.getSizeInBits() == 16) { 7014 SDValue Vec = Op.getOperand(0); 7015 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7016 if (Idx == 0) 7017 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 7018 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 7019 DAG.getNode(ISD::BITCAST, dl, 7020 MVT::v4i32, Vec), 7021 Op.getOperand(1))); 7022 // Transform it so it match pextrw which produces a 32-bit result. 7023 EVT EltVT = MVT::i32; 7024 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 7025 Op.getOperand(0), Op.getOperand(1)); 7026 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 7027 DAG.getValueType(VT)); 7028 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 7029 } else if (VT.getSizeInBits() == 32) { 7030 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7031 if (Idx == 0) 7032 return Op; 7033 7034 // SHUFPS the element to the lowest double word, then movss. 7035 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 7036 EVT VVT = Op.getOperand(0).getValueType(); 7037 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7038 DAG.getUNDEF(VVT), Mask); 7039 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7040 DAG.getIntPtrConstant(0)); 7041 } else if (VT.getSizeInBits() == 64) { 7042 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 7043 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 7044 // to match extract_elt for f64. 7045 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 7046 if (Idx == 0) 7047 return Op; 7048 7049 // UNPCKHPD the element to the lowest double word, then movsd. 7050 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 7051 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 7052 int Mask[2] = { 1, -1 }; 7053 EVT VVT = Op.getOperand(0).getValueType(); 7054 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 7055 DAG.getUNDEF(VVT), Mask); 7056 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 7057 DAG.getIntPtrConstant(0)); 7058 } 7059 7060 return SDValue(); 7061} 7062 7063SDValue 7064X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 7065 SelectionDAG &DAG) const { 7066 EVT VT = Op.getValueType(); 7067 EVT EltVT = VT.getVectorElementType(); 7068 DebugLoc dl = Op.getDebugLoc(); 7069 7070 SDValue N0 = Op.getOperand(0); 7071 SDValue N1 = Op.getOperand(1); 7072 SDValue N2 = Op.getOperand(2); 7073 7074 if (VT.getSizeInBits() == 256) 7075 return SDValue(); 7076 7077 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7078 isa<ConstantSDNode>(N2)) { 7079 unsigned Opc; 7080 if (VT == MVT::v8i16) 7081 Opc = X86ISD::PINSRW; 7082 else if (VT == MVT::v16i8) 7083 Opc = X86ISD::PINSRB; 7084 else 7085 Opc = X86ISD::PINSRB; 7086 7087 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7088 // argument. 7089 if (N1.getValueType() != MVT::i32) 7090 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7091 if (N2.getValueType() != MVT::i32) 7092 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7093 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7094 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7095 // Bits [7:6] of the constant are the source select. This will always be 7096 // zero here. The DAG Combiner may combine an extract_elt index into these 7097 // bits. For example (insert (extract, 3), 2) could be matched by putting 7098 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7099 // Bits [5:4] of the constant are the destination select. This is the 7100 // value of the incoming immediate. 7101 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7102 // combine either bitwise AND or insert of float 0.0 to set these bits. 7103 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7104 // Create this as a scalar to vector.. 7105 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7106 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7107 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 7108 isa<ConstantSDNode>(N2)) { 7109 // PINSR* works with constant index. 7110 return Op; 7111 } 7112 return SDValue(); 7113} 7114 7115SDValue 7116X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7117 EVT VT = Op.getValueType(); 7118 EVT EltVT = VT.getVectorElementType(); 7119 7120 DebugLoc dl = Op.getDebugLoc(); 7121 SDValue N0 = Op.getOperand(0); 7122 SDValue N1 = Op.getOperand(1); 7123 SDValue N2 = Op.getOperand(2); 7124 7125 // If this is a 256-bit vector result, first extract the 128-bit vector, 7126 // insert the element into the extracted half and then place it back. 7127 if (VT.getSizeInBits() == 256) { 7128 if (!isa<ConstantSDNode>(N2)) 7129 return SDValue(); 7130 7131 // Get the desired 128-bit vector half. 7132 unsigned NumElems = VT.getVectorNumElements(); 7133 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7134 bool Upper = IdxVal >= NumElems/2; 7135 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 7136 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 7137 7138 // Insert the element into the desired half. 7139 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 7140 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 7141 7142 // Insert the changed part back to the 256-bit vector 7143 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 7144 } 7145 7146 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) 7147 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7148 7149 if (EltVT == MVT::i8) 7150 return SDValue(); 7151 7152 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7153 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7154 // as its second argument. 7155 if (N1.getValueType() != MVT::i32) 7156 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7157 if (N2.getValueType() != MVT::i32) 7158 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7159 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7160 } 7161 return SDValue(); 7162} 7163 7164SDValue 7165X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 7166 LLVMContext *Context = DAG.getContext(); 7167 DebugLoc dl = Op.getDebugLoc(); 7168 EVT OpVT = Op.getValueType(); 7169 7170 // If this is a 256-bit vector result, first insert into a 128-bit 7171 // vector and then insert into the 256-bit vector. 7172 if (OpVT.getSizeInBits() > 128) { 7173 // Insert into a 128-bit vector. 7174 EVT VT128 = EVT::getVectorVT(*Context, 7175 OpVT.getVectorElementType(), 7176 OpVT.getVectorNumElements() / 2); 7177 7178 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7179 7180 // Insert the 128-bit vector. 7181 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7182 DAG.getConstant(0, MVT::i32), 7183 DAG, dl); 7184 } 7185 7186 if (Op.getValueType() == MVT::v1i64 && 7187 Op.getOperand(0).getValueType() == MVT::i64) 7188 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7189 7190 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7191 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7192 "Expected an SSE type!"); 7193 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7194 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7195} 7196 7197// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7198// a simple subregister reference or explicit instructions to grab 7199// upper bits of a vector. 7200SDValue 7201X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7202 if (Subtarget->hasAVX()) { 7203 DebugLoc dl = Op.getNode()->getDebugLoc(); 7204 SDValue Vec = Op.getNode()->getOperand(0); 7205 SDValue Idx = Op.getNode()->getOperand(1); 7206 7207 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7208 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7209 return Extract128BitVector(Vec, Idx, DAG, dl); 7210 } 7211 } 7212 return SDValue(); 7213} 7214 7215// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7216// simple superregister reference or explicit instructions to insert 7217// the upper bits of a vector. 7218SDValue 7219X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7220 if (Subtarget->hasAVX()) { 7221 DebugLoc dl = Op.getNode()->getDebugLoc(); 7222 SDValue Vec = Op.getNode()->getOperand(0); 7223 SDValue SubVec = Op.getNode()->getOperand(1); 7224 SDValue Idx = Op.getNode()->getOperand(2); 7225 7226 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7227 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7228 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7229 } 7230 } 7231 return SDValue(); 7232} 7233 7234// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7235// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7236// one of the above mentioned nodes. It has to be wrapped because otherwise 7237// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7238// be used to form addressing mode. These wrapped nodes will be selected 7239// into MOV32ri. 7240SDValue 7241X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7242 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7243 7244 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7245 // global base reg. 7246 unsigned char OpFlag = 0; 7247 unsigned WrapperKind = X86ISD::Wrapper; 7248 CodeModel::Model M = getTargetMachine().getCodeModel(); 7249 7250 if (Subtarget->isPICStyleRIPRel() && 7251 (M == CodeModel::Small || M == CodeModel::Kernel)) 7252 WrapperKind = X86ISD::WrapperRIP; 7253 else if (Subtarget->isPICStyleGOT()) 7254 OpFlag = X86II::MO_GOTOFF; 7255 else if (Subtarget->isPICStyleStubPIC()) 7256 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7257 7258 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7259 CP->getAlignment(), 7260 CP->getOffset(), OpFlag); 7261 DebugLoc DL = CP->getDebugLoc(); 7262 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7263 // With PIC, the address is actually $g + Offset. 7264 if (OpFlag) { 7265 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7266 DAG.getNode(X86ISD::GlobalBaseReg, 7267 DebugLoc(), getPointerTy()), 7268 Result); 7269 } 7270 7271 return Result; 7272} 7273 7274SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7275 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7276 7277 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7278 // global base reg. 7279 unsigned char OpFlag = 0; 7280 unsigned WrapperKind = X86ISD::Wrapper; 7281 CodeModel::Model M = getTargetMachine().getCodeModel(); 7282 7283 if (Subtarget->isPICStyleRIPRel() && 7284 (M == CodeModel::Small || M == CodeModel::Kernel)) 7285 WrapperKind = X86ISD::WrapperRIP; 7286 else if (Subtarget->isPICStyleGOT()) 7287 OpFlag = X86II::MO_GOTOFF; 7288 else if (Subtarget->isPICStyleStubPIC()) 7289 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7290 7291 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7292 OpFlag); 7293 DebugLoc DL = JT->getDebugLoc(); 7294 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7295 7296 // With PIC, the address is actually $g + Offset. 7297 if (OpFlag) 7298 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7299 DAG.getNode(X86ISD::GlobalBaseReg, 7300 DebugLoc(), getPointerTy()), 7301 Result); 7302 7303 return Result; 7304} 7305 7306SDValue 7307X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7308 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7309 7310 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7311 // global base reg. 7312 unsigned char OpFlag = 0; 7313 unsigned WrapperKind = X86ISD::Wrapper; 7314 CodeModel::Model M = getTargetMachine().getCodeModel(); 7315 7316 if (Subtarget->isPICStyleRIPRel() && 7317 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7318 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7319 OpFlag = X86II::MO_GOTPCREL; 7320 WrapperKind = X86ISD::WrapperRIP; 7321 } else if (Subtarget->isPICStyleGOT()) { 7322 OpFlag = X86II::MO_GOT; 7323 } else if (Subtarget->isPICStyleStubPIC()) { 7324 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7325 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7326 OpFlag = X86II::MO_DARWIN_NONLAZY; 7327 } 7328 7329 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7330 7331 DebugLoc DL = Op.getDebugLoc(); 7332 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7333 7334 7335 // With PIC, the address is actually $g + Offset. 7336 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7337 !Subtarget->is64Bit()) { 7338 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7339 DAG.getNode(X86ISD::GlobalBaseReg, 7340 DebugLoc(), getPointerTy()), 7341 Result); 7342 } 7343 7344 // For symbols that require a load from a stub to get the address, emit the 7345 // load. 7346 if (isGlobalStubReference(OpFlag)) 7347 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7348 MachinePointerInfo::getGOT(), false, false, false, 0); 7349 7350 return Result; 7351} 7352 7353SDValue 7354X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7355 // Create the TargetBlockAddressAddress node. 7356 unsigned char OpFlags = 7357 Subtarget->ClassifyBlockAddressReference(); 7358 CodeModel::Model M = getTargetMachine().getCodeModel(); 7359 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7360 DebugLoc dl = Op.getDebugLoc(); 7361 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7362 /*isTarget=*/true, OpFlags); 7363 7364 if (Subtarget->isPICStyleRIPRel() && 7365 (M == CodeModel::Small || M == CodeModel::Kernel)) 7366 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7367 else 7368 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7369 7370 // With PIC, the address is actually $g + Offset. 7371 if (isGlobalRelativeToPICBase(OpFlags)) { 7372 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7373 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7374 Result); 7375 } 7376 7377 return Result; 7378} 7379 7380SDValue 7381X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7382 int64_t Offset, 7383 SelectionDAG &DAG) const { 7384 // Create the TargetGlobalAddress node, folding in the constant 7385 // offset if it is legal. 7386 unsigned char OpFlags = 7387 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7388 CodeModel::Model M = getTargetMachine().getCodeModel(); 7389 SDValue Result; 7390 if (OpFlags == X86II::MO_NO_FLAG && 7391 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7392 // A direct static reference to a global. 7393 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7394 Offset = 0; 7395 } else { 7396 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7397 } 7398 7399 if (Subtarget->isPICStyleRIPRel() && 7400 (M == CodeModel::Small || M == CodeModel::Kernel)) 7401 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7402 else 7403 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7404 7405 // With PIC, the address is actually $g + Offset. 7406 if (isGlobalRelativeToPICBase(OpFlags)) { 7407 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7408 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7409 Result); 7410 } 7411 7412 // For globals that require a load from a stub to get the address, emit the 7413 // load. 7414 if (isGlobalStubReference(OpFlags)) 7415 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7416 MachinePointerInfo::getGOT(), false, false, false, 0); 7417 7418 // If there was a non-zero offset that we didn't fold, create an explicit 7419 // addition for it. 7420 if (Offset != 0) 7421 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7422 DAG.getConstant(Offset, getPointerTy())); 7423 7424 return Result; 7425} 7426 7427SDValue 7428X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7429 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7430 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7431 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7432} 7433 7434static SDValue 7435GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7436 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7437 unsigned char OperandFlags) { 7438 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7439 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7440 DebugLoc dl = GA->getDebugLoc(); 7441 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7442 GA->getValueType(0), 7443 GA->getOffset(), 7444 OperandFlags); 7445 if (InFlag) { 7446 SDValue Ops[] = { Chain, TGA, *InFlag }; 7447 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7448 } else { 7449 SDValue Ops[] = { Chain, TGA }; 7450 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7451 } 7452 7453 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7454 MFI->setAdjustsStack(true); 7455 7456 SDValue Flag = Chain.getValue(1); 7457 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7458} 7459 7460// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7461static SDValue 7462LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7463 const EVT PtrVT) { 7464 SDValue InFlag; 7465 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7466 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7467 DAG.getNode(X86ISD::GlobalBaseReg, 7468 DebugLoc(), PtrVT), InFlag); 7469 InFlag = Chain.getValue(1); 7470 7471 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7472} 7473 7474// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7475static SDValue 7476LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7477 const EVT PtrVT) { 7478 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7479 X86::RAX, X86II::MO_TLSGD); 7480} 7481 7482// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7483// "local exec" model. 7484static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7485 const EVT PtrVT, TLSModel::Model model, 7486 bool is64Bit) { 7487 DebugLoc dl = GA->getDebugLoc(); 7488 7489 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7490 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7491 is64Bit ? 257 : 256)); 7492 7493 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7494 DAG.getIntPtrConstant(0), 7495 MachinePointerInfo(Ptr), 7496 false, false, false, 0); 7497 7498 unsigned char OperandFlags = 0; 7499 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7500 // initialexec. 7501 unsigned WrapperKind = X86ISD::Wrapper; 7502 if (model == TLSModel::LocalExec) { 7503 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7504 } else if (is64Bit) { 7505 assert(model == TLSModel::InitialExec); 7506 OperandFlags = X86II::MO_GOTTPOFF; 7507 WrapperKind = X86ISD::WrapperRIP; 7508 } else { 7509 assert(model == TLSModel::InitialExec); 7510 OperandFlags = X86II::MO_INDNTPOFF; 7511 } 7512 7513 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7514 // exec) 7515 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7516 GA->getValueType(0), 7517 GA->getOffset(), OperandFlags); 7518 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7519 7520 if (model == TLSModel::InitialExec) 7521 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7522 MachinePointerInfo::getGOT(), false, false, false, 0); 7523 7524 // The address of the thread local variable is the add of the thread 7525 // pointer with the offset of the variable. 7526 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7527} 7528 7529SDValue 7530X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7531 7532 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7533 const GlobalValue *GV = GA->getGlobal(); 7534 7535 if (Subtarget->isTargetELF()) { 7536 // TODO: implement the "local dynamic" model 7537 // TODO: implement the "initial exec"model for pic executables 7538 7539 // If GV is an alias then use the aliasee for determining 7540 // thread-localness. 7541 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7542 GV = GA->resolveAliasedGlobal(false); 7543 7544 TLSModel::Model model 7545 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7546 7547 switch (model) { 7548 case TLSModel::GeneralDynamic: 7549 case TLSModel::LocalDynamic: // not implemented 7550 if (Subtarget->is64Bit()) 7551 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7552 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7553 7554 case TLSModel::InitialExec: 7555 case TLSModel::LocalExec: 7556 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7557 Subtarget->is64Bit()); 7558 } 7559 } else if (Subtarget->isTargetDarwin()) { 7560 // Darwin only has one model of TLS. Lower to that. 7561 unsigned char OpFlag = 0; 7562 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7563 X86ISD::WrapperRIP : X86ISD::Wrapper; 7564 7565 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7566 // global base reg. 7567 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7568 !Subtarget->is64Bit(); 7569 if (PIC32) 7570 OpFlag = X86II::MO_TLVP_PIC_BASE; 7571 else 7572 OpFlag = X86II::MO_TLVP; 7573 DebugLoc DL = Op.getDebugLoc(); 7574 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7575 GA->getValueType(0), 7576 GA->getOffset(), OpFlag); 7577 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7578 7579 // With PIC32, the address is actually $g + Offset. 7580 if (PIC32) 7581 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7582 DAG.getNode(X86ISD::GlobalBaseReg, 7583 DebugLoc(), getPointerTy()), 7584 Offset); 7585 7586 // Lowering the machine isd will make sure everything is in the right 7587 // location. 7588 SDValue Chain = DAG.getEntryNode(); 7589 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7590 SDValue Args[] = { Chain, Offset }; 7591 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7592 7593 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7594 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7595 MFI->setAdjustsStack(true); 7596 7597 // And our return value (tls address) is in the standard call return value 7598 // location. 7599 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7600 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7601 Chain.getValue(1)); 7602 } 7603 7604 assert(false && 7605 "TLS not implemented for this target."); 7606 7607 llvm_unreachable("Unreachable"); 7608 return SDValue(); 7609} 7610 7611 7612/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7613/// take a 2 x i32 value to shift plus a shift amount. 7614SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7615 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7616 EVT VT = Op.getValueType(); 7617 unsigned VTBits = VT.getSizeInBits(); 7618 DebugLoc dl = Op.getDebugLoc(); 7619 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7620 SDValue ShOpLo = Op.getOperand(0); 7621 SDValue ShOpHi = Op.getOperand(1); 7622 SDValue ShAmt = Op.getOperand(2); 7623 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7624 DAG.getConstant(VTBits - 1, MVT::i8)) 7625 : DAG.getConstant(0, VT); 7626 7627 SDValue Tmp2, Tmp3; 7628 if (Op.getOpcode() == ISD::SHL_PARTS) { 7629 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7630 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7631 } else { 7632 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7633 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7634 } 7635 7636 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7637 DAG.getConstant(VTBits, MVT::i8)); 7638 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7639 AndNode, DAG.getConstant(0, MVT::i8)); 7640 7641 SDValue Hi, Lo; 7642 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7643 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7644 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7645 7646 if (Op.getOpcode() == ISD::SHL_PARTS) { 7647 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7648 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7649 } else { 7650 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7651 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7652 } 7653 7654 SDValue Ops[2] = { Lo, Hi }; 7655 return DAG.getMergeValues(Ops, 2, dl); 7656} 7657 7658SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7659 SelectionDAG &DAG) const { 7660 EVT SrcVT = Op.getOperand(0).getValueType(); 7661 7662 if (SrcVT.isVector()) 7663 return SDValue(); 7664 7665 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7666 "Unknown SINT_TO_FP to lower!"); 7667 7668 // These are really Legal; return the operand so the caller accepts it as 7669 // Legal. 7670 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7671 return Op; 7672 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7673 Subtarget->is64Bit()) { 7674 return Op; 7675 } 7676 7677 DebugLoc dl = Op.getDebugLoc(); 7678 unsigned Size = SrcVT.getSizeInBits()/8; 7679 MachineFunction &MF = DAG.getMachineFunction(); 7680 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7681 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7682 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7683 StackSlot, 7684 MachinePointerInfo::getFixedStack(SSFI), 7685 false, false, 0); 7686 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7687} 7688 7689SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7690 SDValue StackSlot, 7691 SelectionDAG &DAG) const { 7692 // Build the FILD 7693 DebugLoc DL = Op.getDebugLoc(); 7694 SDVTList Tys; 7695 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7696 if (useSSE) 7697 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7698 else 7699 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7700 7701 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7702 7703 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7704 MachineMemOperand *MMO; 7705 if (FI) { 7706 int SSFI = FI->getIndex(); 7707 MMO = 7708 DAG.getMachineFunction() 7709 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7710 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7711 } else { 7712 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7713 StackSlot = StackSlot.getOperand(1); 7714 } 7715 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7716 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7717 X86ISD::FILD, DL, 7718 Tys, Ops, array_lengthof(Ops), 7719 SrcVT, MMO); 7720 7721 if (useSSE) { 7722 Chain = Result.getValue(1); 7723 SDValue InFlag = Result.getValue(2); 7724 7725 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7726 // shouldn't be necessary except that RFP cannot be live across 7727 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7728 MachineFunction &MF = DAG.getMachineFunction(); 7729 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7730 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7731 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7732 Tys = DAG.getVTList(MVT::Other); 7733 SDValue Ops[] = { 7734 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7735 }; 7736 MachineMemOperand *MMO = 7737 DAG.getMachineFunction() 7738 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7739 MachineMemOperand::MOStore, SSFISize, SSFISize); 7740 7741 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7742 Ops, array_lengthof(Ops), 7743 Op.getValueType(), MMO); 7744 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7745 MachinePointerInfo::getFixedStack(SSFI), 7746 false, false, false, 0); 7747 } 7748 7749 return Result; 7750} 7751 7752// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7753SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7754 SelectionDAG &DAG) const { 7755 // This algorithm is not obvious. Here it is in C code, more or less: 7756 /* 7757 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7758 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7759 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7760 7761 // Copy ints to xmm registers. 7762 __m128i xh = _mm_cvtsi32_si128( hi ); 7763 __m128i xl = _mm_cvtsi32_si128( lo ); 7764 7765 // Combine into low half of a single xmm register. 7766 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7767 __m128d d; 7768 double sd; 7769 7770 // Merge in appropriate exponents to give the integer bits the right 7771 // magnitude. 7772 x = _mm_unpacklo_epi32( x, exp ); 7773 7774 // Subtract away the biases to deal with the IEEE-754 double precision 7775 // implicit 1. 7776 d = _mm_sub_pd( (__m128d) x, bias ); 7777 7778 // All conversions up to here are exact. The correctly rounded result is 7779 // calculated using the current rounding mode using the following 7780 // horizontal add. 7781 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7782 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7783 // store doesn't really need to be here (except 7784 // maybe to zero the other double) 7785 return sd; 7786 } 7787 */ 7788 7789 DebugLoc dl = Op.getDebugLoc(); 7790 LLVMContext *Context = DAG.getContext(); 7791 7792 // Build some magic constants. 7793 std::vector<Constant*> CV0; 7794 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7795 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7796 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7797 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7798 Constant *C0 = ConstantVector::get(CV0); 7799 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7800 7801 std::vector<Constant*> CV1; 7802 CV1.push_back( 7803 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7804 CV1.push_back( 7805 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7806 Constant *C1 = ConstantVector::get(CV1); 7807 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7808 7809 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7810 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7811 Op.getOperand(0), 7812 DAG.getIntPtrConstant(1))); 7813 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7814 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7815 Op.getOperand(0), 7816 DAG.getIntPtrConstant(0))); 7817 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7818 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7819 MachinePointerInfo::getConstantPool(), 7820 false, false, false, 16); 7821 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7822 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7823 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7824 MachinePointerInfo::getConstantPool(), 7825 false, false, false, 16); 7826 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7827 7828 // Add the halves; easiest way is to swap them into another reg first. 7829 int ShufMask[2] = { 1, -1 }; 7830 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7831 DAG.getUNDEF(MVT::v2f64), ShufMask); 7832 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7833 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7834 DAG.getIntPtrConstant(0)); 7835} 7836 7837// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7838SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7839 SelectionDAG &DAG) const { 7840 DebugLoc dl = Op.getDebugLoc(); 7841 // FP constant to bias correct the final result. 7842 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7843 MVT::f64); 7844 7845 // Load the 32-bit value into an XMM register. 7846 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7847 Op.getOperand(0)); 7848 7849 // Zero out the upper parts of the register. 7850 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(), 7851 DAG); 7852 7853 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7854 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7855 DAG.getIntPtrConstant(0)); 7856 7857 // Or the load with the bias. 7858 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7859 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7860 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7861 MVT::v2f64, Load)), 7862 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7863 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7864 MVT::v2f64, Bias))); 7865 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7866 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7867 DAG.getIntPtrConstant(0)); 7868 7869 // Subtract the bias. 7870 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7871 7872 // Handle final rounding. 7873 EVT DestVT = Op.getValueType(); 7874 7875 if (DestVT.bitsLT(MVT::f64)) { 7876 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7877 DAG.getIntPtrConstant(0)); 7878 } else if (DestVT.bitsGT(MVT::f64)) { 7879 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7880 } 7881 7882 // Handle final rounding. 7883 return Sub; 7884} 7885 7886SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7887 SelectionDAG &DAG) const { 7888 SDValue N0 = Op.getOperand(0); 7889 DebugLoc dl = Op.getDebugLoc(); 7890 7891 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7892 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7893 // the optimization here. 7894 if (DAG.SignBitIsZero(N0)) 7895 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7896 7897 EVT SrcVT = N0.getValueType(); 7898 EVT DstVT = Op.getValueType(); 7899 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7900 return LowerUINT_TO_FP_i64(Op, DAG); 7901 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7902 return LowerUINT_TO_FP_i32(Op, DAG); 7903 7904 // Make a 64-bit buffer, and use it to build an FILD. 7905 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7906 if (SrcVT == MVT::i32) { 7907 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7908 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7909 getPointerTy(), StackSlot, WordOff); 7910 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7911 StackSlot, MachinePointerInfo(), 7912 false, false, 0); 7913 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7914 OffsetSlot, MachinePointerInfo(), 7915 false, false, 0); 7916 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7917 return Fild; 7918 } 7919 7920 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7921 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7922 StackSlot, MachinePointerInfo(), 7923 false, false, 0); 7924 // For i64 source, we need to add the appropriate power of 2 if the input 7925 // was negative. This is the same as the optimization in 7926 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7927 // we must be careful to do the computation in x87 extended precision, not 7928 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7929 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7930 MachineMemOperand *MMO = 7931 DAG.getMachineFunction() 7932 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7933 MachineMemOperand::MOLoad, 8, 8); 7934 7935 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7936 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7937 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7938 MVT::i64, MMO); 7939 7940 APInt FF(32, 0x5F800000ULL); 7941 7942 // Check whether the sign bit is set. 7943 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7944 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7945 ISD::SETLT); 7946 7947 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7948 SDValue FudgePtr = DAG.getConstantPool( 7949 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7950 getPointerTy()); 7951 7952 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7953 SDValue Zero = DAG.getIntPtrConstant(0); 7954 SDValue Four = DAG.getIntPtrConstant(4); 7955 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7956 Zero, Four); 7957 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7958 7959 // Load the value out, extending it from f32 to f80. 7960 // FIXME: Avoid the extend by constructing the right constant pool? 7961 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7962 FudgePtr, MachinePointerInfo::getConstantPool(), 7963 MVT::f32, false, false, 4); 7964 // Extend everything to 80 bits to force it to be done on x87. 7965 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7966 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7967} 7968 7969std::pair<SDValue,SDValue> X86TargetLowering:: 7970FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7971 DebugLoc DL = Op.getDebugLoc(); 7972 7973 EVT DstTy = Op.getValueType(); 7974 7975 if (!IsSigned) { 7976 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7977 DstTy = MVT::i64; 7978 } 7979 7980 assert(DstTy.getSimpleVT() <= MVT::i64 && 7981 DstTy.getSimpleVT() >= MVT::i16 && 7982 "Unknown FP_TO_SINT to lower!"); 7983 7984 // These are really Legal. 7985 if (DstTy == MVT::i32 && 7986 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7987 return std::make_pair(SDValue(), SDValue()); 7988 if (Subtarget->is64Bit() && 7989 DstTy == MVT::i64 && 7990 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7991 return std::make_pair(SDValue(), SDValue()); 7992 7993 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7994 // stack slot. 7995 MachineFunction &MF = DAG.getMachineFunction(); 7996 unsigned MemSize = DstTy.getSizeInBits()/8; 7997 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7998 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7999 8000 8001 8002 unsigned Opc; 8003 switch (DstTy.getSimpleVT().SimpleTy) { 8004 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 8005 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 8006 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 8007 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 8008 } 8009 8010 SDValue Chain = DAG.getEntryNode(); 8011 SDValue Value = Op.getOperand(0); 8012 EVT TheVT = Op.getOperand(0).getValueType(); 8013 if (isScalarFPTypeInSSEReg(TheVT)) { 8014 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 8015 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 8016 MachinePointerInfo::getFixedStack(SSFI), 8017 false, false, 0); 8018 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 8019 SDValue Ops[] = { 8020 Chain, StackSlot, DAG.getValueType(TheVT) 8021 }; 8022 8023 MachineMemOperand *MMO = 8024 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8025 MachineMemOperand::MOLoad, MemSize, MemSize); 8026 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 8027 DstTy, MMO); 8028 Chain = Value.getValue(1); 8029 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 8030 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 8031 } 8032 8033 MachineMemOperand *MMO = 8034 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 8035 MachineMemOperand::MOStore, MemSize, MemSize); 8036 8037 // Build the FP_TO_INT*_IN_MEM 8038 SDValue Ops[] = { Chain, Value, StackSlot }; 8039 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 8040 Ops, 3, DstTy, MMO); 8041 8042 return std::make_pair(FIST, StackSlot); 8043} 8044 8045SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 8046 SelectionDAG &DAG) const { 8047 if (Op.getValueType().isVector()) 8048 return SDValue(); 8049 8050 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 8051 SDValue FIST = Vals.first, StackSlot = Vals.second; 8052 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 8053 if (FIST.getNode() == 0) return Op; 8054 8055 // Load the result. 8056 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8057 FIST, StackSlot, MachinePointerInfo(), 8058 false, false, false, 0); 8059} 8060 8061SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 8062 SelectionDAG &DAG) const { 8063 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 8064 SDValue FIST = Vals.first, StackSlot = Vals.second; 8065 assert(FIST.getNode() && "Unexpected failure"); 8066 8067 // Load the result. 8068 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 8069 FIST, StackSlot, MachinePointerInfo(), 8070 false, false, false, 0); 8071} 8072 8073SDValue X86TargetLowering::LowerFABS(SDValue Op, 8074 SelectionDAG &DAG) const { 8075 LLVMContext *Context = DAG.getContext(); 8076 DebugLoc dl = Op.getDebugLoc(); 8077 EVT VT = Op.getValueType(); 8078 EVT EltVT = VT; 8079 if (VT.isVector()) 8080 EltVT = VT.getVectorElementType(); 8081 std::vector<Constant*> CV; 8082 if (EltVT == MVT::f64) { 8083 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 8084 CV.push_back(C); 8085 CV.push_back(C); 8086 } else { 8087 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 8088 CV.push_back(C); 8089 CV.push_back(C); 8090 CV.push_back(C); 8091 CV.push_back(C); 8092 } 8093 Constant *C = ConstantVector::get(CV); 8094 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8095 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8096 MachinePointerInfo::getConstantPool(), 8097 false, false, false, 16); 8098 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8099} 8100 8101SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8102 LLVMContext *Context = DAG.getContext(); 8103 DebugLoc dl = Op.getDebugLoc(); 8104 EVT VT = Op.getValueType(); 8105 EVT EltVT = VT; 8106 if (VT.isVector()) 8107 EltVT = VT.getVectorElementType(); 8108 std::vector<Constant*> CV; 8109 if (EltVT == MVT::f64) { 8110 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8111 CV.push_back(C); 8112 CV.push_back(C); 8113 } else { 8114 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8115 CV.push_back(C); 8116 CV.push_back(C); 8117 CV.push_back(C); 8118 CV.push_back(C); 8119 } 8120 Constant *C = ConstantVector::get(CV); 8121 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8122 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8123 MachinePointerInfo::getConstantPool(), 8124 false, false, false, 16); 8125 if (VT.isVector()) { 8126 return DAG.getNode(ISD::BITCAST, dl, VT, 8127 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 8128 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8129 Op.getOperand(0)), 8130 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 8131 } else { 8132 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8133 } 8134} 8135 8136SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8137 LLVMContext *Context = DAG.getContext(); 8138 SDValue Op0 = Op.getOperand(0); 8139 SDValue Op1 = Op.getOperand(1); 8140 DebugLoc dl = Op.getDebugLoc(); 8141 EVT VT = Op.getValueType(); 8142 EVT SrcVT = Op1.getValueType(); 8143 8144 // If second operand is smaller, extend it first. 8145 if (SrcVT.bitsLT(VT)) { 8146 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8147 SrcVT = VT; 8148 } 8149 // And if it is bigger, shrink it first. 8150 if (SrcVT.bitsGT(VT)) { 8151 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8152 SrcVT = VT; 8153 } 8154 8155 // At this point the operands and the result should have the same 8156 // type, and that won't be f80 since that is not custom lowered. 8157 8158 // First get the sign bit of second operand. 8159 std::vector<Constant*> CV; 8160 if (SrcVT == MVT::f64) { 8161 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8162 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8163 } else { 8164 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8165 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8166 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8167 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8168 } 8169 Constant *C = ConstantVector::get(CV); 8170 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8171 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8172 MachinePointerInfo::getConstantPool(), 8173 false, false, false, 16); 8174 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8175 8176 // Shift sign bit right or left if the two operands have different types. 8177 if (SrcVT.bitsGT(VT)) { 8178 // Op0 is MVT::f32, Op1 is MVT::f64. 8179 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8180 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8181 DAG.getConstant(32, MVT::i32)); 8182 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8183 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8184 DAG.getIntPtrConstant(0)); 8185 } 8186 8187 // Clear first operand sign bit. 8188 CV.clear(); 8189 if (VT == MVT::f64) { 8190 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8191 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8192 } else { 8193 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8194 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8195 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8196 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8197 } 8198 C = ConstantVector::get(CV); 8199 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8200 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8201 MachinePointerInfo::getConstantPool(), 8202 false, false, false, 16); 8203 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8204 8205 // Or the value with the sign bit. 8206 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8207} 8208 8209SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8210 SDValue N0 = Op.getOperand(0); 8211 DebugLoc dl = Op.getDebugLoc(); 8212 EVT VT = Op.getValueType(); 8213 8214 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8215 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8216 DAG.getConstant(1, VT)); 8217 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8218} 8219 8220/// Emit nodes that will be selected as "test Op0,Op0", or something 8221/// equivalent. 8222SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8223 SelectionDAG &DAG) const { 8224 DebugLoc dl = Op.getDebugLoc(); 8225 8226 // CF and OF aren't always set the way we want. Determine which 8227 // of these we need. 8228 bool NeedCF = false; 8229 bool NeedOF = false; 8230 switch (X86CC) { 8231 default: break; 8232 case X86::COND_A: case X86::COND_AE: 8233 case X86::COND_B: case X86::COND_BE: 8234 NeedCF = true; 8235 break; 8236 case X86::COND_G: case X86::COND_GE: 8237 case X86::COND_L: case X86::COND_LE: 8238 case X86::COND_O: case X86::COND_NO: 8239 NeedOF = true; 8240 break; 8241 } 8242 8243 // See if we can use the EFLAGS value from the operand instead of 8244 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8245 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8246 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8247 // Emit a CMP with 0, which is the TEST pattern. 8248 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8249 DAG.getConstant(0, Op.getValueType())); 8250 8251 unsigned Opcode = 0; 8252 unsigned NumOperands = 0; 8253 switch (Op.getNode()->getOpcode()) { 8254 case ISD::ADD: 8255 // Due to an isel shortcoming, be conservative if this add is likely to be 8256 // selected as part of a load-modify-store instruction. When the root node 8257 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8258 // uses of other nodes in the match, such as the ADD in this case. This 8259 // leads to the ADD being left around and reselected, with the result being 8260 // two adds in the output. Alas, even if none our users are stores, that 8261 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8262 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8263 // climbing the DAG back to the root, and it doesn't seem to be worth the 8264 // effort. 8265 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8266 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8267 if (UI->getOpcode() != ISD::CopyToReg && 8268 UI->getOpcode() != ISD::SETCC && 8269 UI->getOpcode() != ISD::STORE) 8270 goto default_case; 8271 8272 if (ConstantSDNode *C = 8273 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8274 // An add of one will be selected as an INC. 8275 if (C->getAPIntValue() == 1) { 8276 Opcode = X86ISD::INC; 8277 NumOperands = 1; 8278 break; 8279 } 8280 8281 // An add of negative one (subtract of one) will be selected as a DEC. 8282 if (C->getAPIntValue().isAllOnesValue()) { 8283 Opcode = X86ISD::DEC; 8284 NumOperands = 1; 8285 break; 8286 } 8287 } 8288 8289 // Otherwise use a regular EFLAGS-setting add. 8290 Opcode = X86ISD::ADD; 8291 NumOperands = 2; 8292 break; 8293 case ISD::AND: { 8294 // If the primary and result isn't used, don't bother using X86ISD::AND, 8295 // because a TEST instruction will be better. 8296 bool NonFlagUse = false; 8297 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8298 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8299 SDNode *User = *UI; 8300 unsigned UOpNo = UI.getOperandNo(); 8301 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8302 // Look pass truncate. 8303 UOpNo = User->use_begin().getOperandNo(); 8304 User = *User->use_begin(); 8305 } 8306 8307 if (User->getOpcode() != ISD::BRCOND && 8308 User->getOpcode() != ISD::SETCC && 8309 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8310 NonFlagUse = true; 8311 break; 8312 } 8313 } 8314 8315 if (!NonFlagUse) 8316 break; 8317 } 8318 // FALL THROUGH 8319 case ISD::SUB: 8320 case ISD::OR: 8321 case ISD::XOR: 8322 // Due to the ISEL shortcoming noted above, be conservative if this op is 8323 // likely to be selected as part of a load-modify-store instruction. 8324 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8325 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8326 if (UI->getOpcode() == ISD::STORE) 8327 goto default_case; 8328 8329 // Otherwise use a regular EFLAGS-setting instruction. 8330 switch (Op.getNode()->getOpcode()) { 8331 default: llvm_unreachable("unexpected operator!"); 8332 case ISD::SUB: Opcode = X86ISD::SUB; break; 8333 case ISD::OR: Opcode = X86ISD::OR; break; 8334 case ISD::XOR: Opcode = X86ISD::XOR; break; 8335 case ISD::AND: Opcode = X86ISD::AND; break; 8336 } 8337 8338 NumOperands = 2; 8339 break; 8340 case X86ISD::ADD: 8341 case X86ISD::SUB: 8342 case X86ISD::INC: 8343 case X86ISD::DEC: 8344 case X86ISD::OR: 8345 case X86ISD::XOR: 8346 case X86ISD::AND: 8347 return SDValue(Op.getNode(), 1); 8348 default: 8349 default_case: 8350 break; 8351 } 8352 8353 if (Opcode == 0) 8354 // Emit a CMP with 0, which is the TEST pattern. 8355 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8356 DAG.getConstant(0, Op.getValueType())); 8357 8358 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8359 SmallVector<SDValue, 4> Ops; 8360 for (unsigned i = 0; i != NumOperands; ++i) 8361 Ops.push_back(Op.getOperand(i)); 8362 8363 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8364 DAG.ReplaceAllUsesWith(Op, New); 8365 return SDValue(New.getNode(), 1); 8366} 8367 8368/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8369/// equivalent. 8370SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8371 SelectionDAG &DAG) const { 8372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8373 if (C->getAPIntValue() == 0) 8374 return EmitTest(Op0, X86CC, DAG); 8375 8376 DebugLoc dl = Op0.getDebugLoc(); 8377 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8378} 8379 8380/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8381/// if it's possible. 8382SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8383 DebugLoc dl, SelectionDAG &DAG) const { 8384 SDValue Op0 = And.getOperand(0); 8385 SDValue Op1 = And.getOperand(1); 8386 if (Op0.getOpcode() == ISD::TRUNCATE) 8387 Op0 = Op0.getOperand(0); 8388 if (Op1.getOpcode() == ISD::TRUNCATE) 8389 Op1 = Op1.getOperand(0); 8390 8391 SDValue LHS, RHS; 8392 if (Op1.getOpcode() == ISD::SHL) 8393 std::swap(Op0, Op1); 8394 if (Op0.getOpcode() == ISD::SHL) { 8395 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8396 if (And00C->getZExtValue() == 1) { 8397 // If we looked past a truncate, check that it's only truncating away 8398 // known zeros. 8399 unsigned BitWidth = Op0.getValueSizeInBits(); 8400 unsigned AndBitWidth = And.getValueSizeInBits(); 8401 if (BitWidth > AndBitWidth) { 8402 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8403 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8404 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8405 return SDValue(); 8406 } 8407 LHS = Op1; 8408 RHS = Op0.getOperand(1); 8409 } 8410 } else if (Op1.getOpcode() == ISD::Constant) { 8411 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8412 SDValue AndLHS = Op0; 8413 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 8414 LHS = AndLHS.getOperand(0); 8415 RHS = AndLHS.getOperand(1); 8416 } 8417 } 8418 8419 if (LHS.getNode()) { 8420 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8421 // instruction. Since the shift amount is in-range-or-undefined, we know 8422 // that doing a bittest on the i32 value is ok. We extend to i32 because 8423 // the encoding for the i16 version is larger than the i32 version. 8424 // Also promote i16 to i32 for performance / code size reason. 8425 if (LHS.getValueType() == MVT::i8 || 8426 LHS.getValueType() == MVT::i16) 8427 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8428 8429 // If the operand types disagree, extend the shift amount to match. Since 8430 // BT ignores high bits (like shifts) we can use anyextend. 8431 if (LHS.getValueType() != RHS.getValueType()) 8432 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8433 8434 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8435 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8436 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8437 DAG.getConstant(Cond, MVT::i8), BT); 8438 } 8439 8440 return SDValue(); 8441} 8442 8443SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8444 8445 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8446 8447 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8448 SDValue Op0 = Op.getOperand(0); 8449 SDValue Op1 = Op.getOperand(1); 8450 DebugLoc dl = Op.getDebugLoc(); 8451 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8452 8453 // Optimize to BT if possible. 8454 // Lower (X & (1 << N)) == 0 to BT(X, N). 8455 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8456 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8457 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8458 Op1.getOpcode() == ISD::Constant && 8459 cast<ConstantSDNode>(Op1)->isNullValue() && 8460 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8461 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8462 if (NewSetCC.getNode()) 8463 return NewSetCC; 8464 } 8465 8466 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8467 // these. 8468 if (Op1.getOpcode() == ISD::Constant && 8469 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8470 cast<ConstantSDNode>(Op1)->isNullValue()) && 8471 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8472 8473 // If the input is a setcc, then reuse the input setcc or use a new one with 8474 // the inverted condition. 8475 if (Op0.getOpcode() == X86ISD::SETCC) { 8476 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8477 bool Invert = (CC == ISD::SETNE) ^ 8478 cast<ConstantSDNode>(Op1)->isNullValue(); 8479 if (!Invert) return Op0; 8480 8481 CCode = X86::GetOppositeBranchCondition(CCode); 8482 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8483 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8484 } 8485 } 8486 8487 bool isFP = Op1.getValueType().isFloatingPoint(); 8488 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8489 if (X86CC == X86::COND_INVALID) 8490 return SDValue(); 8491 8492 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8493 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8494 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8495} 8496 8497// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8498// ones, and then concatenate the result back. 8499static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8500 EVT VT = Op.getValueType(); 8501 8502 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8503 "Unsupported value type for operation"); 8504 8505 int NumElems = VT.getVectorNumElements(); 8506 DebugLoc dl = Op.getDebugLoc(); 8507 SDValue CC = Op.getOperand(2); 8508 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8509 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8510 8511 // Extract the LHS vectors 8512 SDValue LHS = Op.getOperand(0); 8513 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8514 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8515 8516 // Extract the RHS vectors 8517 SDValue RHS = Op.getOperand(1); 8518 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8519 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8520 8521 // Issue the operation on the smaller types and concatenate the result back 8522 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8523 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8524 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8525 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8526 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8527} 8528 8529 8530SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8531 SDValue Cond; 8532 SDValue Op0 = Op.getOperand(0); 8533 SDValue Op1 = Op.getOperand(1); 8534 SDValue CC = Op.getOperand(2); 8535 EVT VT = Op.getValueType(); 8536 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8537 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8538 DebugLoc dl = Op.getDebugLoc(); 8539 8540 if (isFP) { 8541 unsigned SSECC = 8; 8542 EVT EltVT = Op0.getValueType().getVectorElementType(); 8543 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8544 8545 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8546 bool Swap = false; 8547 8548 // SSE Condition code mapping: 8549 // 0 - EQ 8550 // 1 - LT 8551 // 2 - LE 8552 // 3 - UNORD 8553 // 4 - NEQ 8554 // 5 - NLT 8555 // 6 - NLE 8556 // 7 - ORD 8557 switch (SetCCOpcode) { 8558 default: break; 8559 case ISD::SETOEQ: 8560 case ISD::SETEQ: SSECC = 0; break; 8561 case ISD::SETOGT: 8562 case ISD::SETGT: Swap = true; // Fallthrough 8563 case ISD::SETLT: 8564 case ISD::SETOLT: SSECC = 1; break; 8565 case ISD::SETOGE: 8566 case ISD::SETGE: Swap = true; // Fallthrough 8567 case ISD::SETLE: 8568 case ISD::SETOLE: SSECC = 2; break; 8569 case ISD::SETUO: SSECC = 3; break; 8570 case ISD::SETUNE: 8571 case ISD::SETNE: SSECC = 4; break; 8572 case ISD::SETULE: Swap = true; 8573 case ISD::SETUGE: SSECC = 5; break; 8574 case ISD::SETULT: Swap = true; 8575 case ISD::SETUGT: SSECC = 6; break; 8576 case ISD::SETO: SSECC = 7; break; 8577 } 8578 if (Swap) 8579 std::swap(Op0, Op1); 8580 8581 // In the two special cases we can't handle, emit two comparisons. 8582 if (SSECC == 8) { 8583 if (SetCCOpcode == ISD::SETUEQ) { 8584 SDValue UNORD, EQ; 8585 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8586 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8587 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8588 } else if (SetCCOpcode == ISD::SETONE) { 8589 SDValue ORD, NEQ; 8590 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8591 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8592 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8593 } 8594 llvm_unreachable("Illegal FP comparison"); 8595 } 8596 // Handle all other FP comparisons here. 8597 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8598 } 8599 8600 // Break 256-bit integer vector compare into smaller ones. 8601 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8602 return Lower256IntVSETCC(Op, DAG); 8603 8604 // We are handling one of the integer comparisons here. Since SSE only has 8605 // GT and EQ comparisons for integer, swapping operands and multiple 8606 // operations may be required for some comparisons. 8607 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8608 bool Swap = false, Invert = false, FlipSigns = false; 8609 8610 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 8611 default: break; 8612 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8613 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8614 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8615 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8616 } 8617 8618 switch (SetCCOpcode) { 8619 default: break; 8620 case ISD::SETNE: Invert = true; 8621 case ISD::SETEQ: Opc = EQOpc; break; 8622 case ISD::SETLT: Swap = true; 8623 case ISD::SETGT: Opc = GTOpc; break; 8624 case ISD::SETGE: Swap = true; 8625 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8626 case ISD::SETULT: Swap = true; 8627 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8628 case ISD::SETUGE: Swap = true; 8629 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8630 } 8631 if (Swap) 8632 std::swap(Op0, Op1); 8633 8634 // Check that the operation in question is available (most are plain SSE2, 8635 // but PCMPGTQ and PCMPEQQ have different requirements). 8636 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX()) 8637 return SDValue(); 8638 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX()) 8639 return SDValue(); 8640 8641 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8642 // bits of the inputs before performing those operations. 8643 if (FlipSigns) { 8644 EVT EltVT = VT.getVectorElementType(); 8645 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8646 EltVT); 8647 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8648 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8649 SignBits.size()); 8650 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8651 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8652 } 8653 8654 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8655 8656 // If the logical-not of the result is required, perform that now. 8657 if (Invert) 8658 Result = DAG.getNOT(dl, Result, VT); 8659 8660 return Result; 8661} 8662 8663// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8664static bool isX86LogicalCmp(SDValue Op) { 8665 unsigned Opc = Op.getNode()->getOpcode(); 8666 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8667 return true; 8668 if (Op.getResNo() == 1 && 8669 (Opc == X86ISD::ADD || 8670 Opc == X86ISD::SUB || 8671 Opc == X86ISD::ADC || 8672 Opc == X86ISD::SBB || 8673 Opc == X86ISD::SMUL || 8674 Opc == X86ISD::UMUL || 8675 Opc == X86ISD::INC || 8676 Opc == X86ISD::DEC || 8677 Opc == X86ISD::OR || 8678 Opc == X86ISD::XOR || 8679 Opc == X86ISD::AND)) 8680 return true; 8681 8682 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8683 return true; 8684 8685 return false; 8686} 8687 8688static bool isZero(SDValue V) { 8689 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8690 return C && C->isNullValue(); 8691} 8692 8693static bool isAllOnes(SDValue V) { 8694 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8695 return C && C->isAllOnesValue(); 8696} 8697 8698SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8699 bool addTest = true; 8700 SDValue Cond = Op.getOperand(0); 8701 SDValue Op1 = Op.getOperand(1); 8702 SDValue Op2 = Op.getOperand(2); 8703 DebugLoc DL = Op.getDebugLoc(); 8704 SDValue CC; 8705 8706 if (Cond.getOpcode() == ISD::SETCC) { 8707 SDValue NewCond = LowerSETCC(Cond, DAG); 8708 if (NewCond.getNode()) 8709 Cond = NewCond; 8710 } 8711 8712 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8713 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8714 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8715 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8716 if (Cond.getOpcode() == X86ISD::SETCC && 8717 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8718 isZero(Cond.getOperand(1).getOperand(1))) { 8719 SDValue Cmp = Cond.getOperand(1); 8720 8721 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8722 8723 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8724 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8725 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8726 8727 SDValue CmpOp0 = Cmp.getOperand(0); 8728 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8729 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8730 8731 SDValue Res = // Res = 0 or -1. 8732 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8733 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8734 8735 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8736 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8737 8738 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8739 if (N2C == 0 || !N2C->isNullValue()) 8740 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8741 return Res; 8742 } 8743 } 8744 8745 // Look past (and (setcc_carry (cmp ...)), 1). 8746 if (Cond.getOpcode() == ISD::AND && 8747 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8748 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8749 if (C && C->getAPIntValue() == 1) 8750 Cond = Cond.getOperand(0); 8751 } 8752 8753 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8754 // setting operand in place of the X86ISD::SETCC. 8755 unsigned CondOpcode = Cond.getOpcode(); 8756 if (CondOpcode == X86ISD::SETCC || 8757 CondOpcode == X86ISD::SETCC_CARRY) { 8758 CC = Cond.getOperand(0); 8759 8760 SDValue Cmp = Cond.getOperand(1); 8761 unsigned Opc = Cmp.getOpcode(); 8762 EVT VT = Op.getValueType(); 8763 8764 bool IllegalFPCMov = false; 8765 if (VT.isFloatingPoint() && !VT.isVector() && 8766 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8767 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8768 8769 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8770 Opc == X86ISD::BT) { // FIXME 8771 Cond = Cmp; 8772 addTest = false; 8773 } 8774 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8775 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8776 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8777 Cond.getOperand(0).getValueType() != MVT::i8)) { 8778 SDValue LHS = Cond.getOperand(0); 8779 SDValue RHS = Cond.getOperand(1); 8780 unsigned X86Opcode; 8781 unsigned X86Cond; 8782 SDVTList VTs; 8783 switch (CondOpcode) { 8784 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8785 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8786 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8787 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8788 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8789 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8790 default: llvm_unreachable("unexpected overflowing operator"); 8791 } 8792 if (CondOpcode == ISD::UMULO) 8793 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8794 MVT::i32); 8795 else 8796 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8797 8798 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8799 8800 if (CondOpcode == ISD::UMULO) 8801 Cond = X86Op.getValue(2); 8802 else 8803 Cond = X86Op.getValue(1); 8804 8805 CC = DAG.getConstant(X86Cond, MVT::i8); 8806 addTest = false; 8807 } 8808 8809 if (addTest) { 8810 // Look pass the truncate. 8811 if (Cond.getOpcode() == ISD::TRUNCATE) 8812 Cond = Cond.getOperand(0); 8813 8814 // We know the result of AND is compared against zero. Try to match 8815 // it to BT. 8816 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8817 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8818 if (NewSetCC.getNode()) { 8819 CC = NewSetCC.getOperand(0); 8820 Cond = NewSetCC.getOperand(1); 8821 addTest = false; 8822 } 8823 } 8824 } 8825 8826 if (addTest) { 8827 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8828 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8829 } 8830 8831 // a < b ? -1 : 0 -> RES = ~setcc_carry 8832 // a < b ? 0 : -1 -> RES = setcc_carry 8833 // a >= b ? -1 : 0 -> RES = setcc_carry 8834 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8835 if (Cond.getOpcode() == X86ISD::CMP) { 8836 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8837 8838 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8839 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8840 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8841 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8842 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8843 return DAG.getNOT(DL, Res, Res.getValueType()); 8844 return Res; 8845 } 8846 } 8847 8848 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8849 // condition is true. 8850 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8851 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8852 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8853} 8854 8855// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8856// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8857// from the AND / OR. 8858static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8859 Opc = Op.getOpcode(); 8860 if (Opc != ISD::OR && Opc != ISD::AND) 8861 return false; 8862 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8863 Op.getOperand(0).hasOneUse() && 8864 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8865 Op.getOperand(1).hasOneUse()); 8866} 8867 8868// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8869// 1 and that the SETCC node has a single use. 8870static bool isXor1OfSetCC(SDValue Op) { 8871 if (Op.getOpcode() != ISD::XOR) 8872 return false; 8873 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8874 if (N1C && N1C->getAPIntValue() == 1) { 8875 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8876 Op.getOperand(0).hasOneUse(); 8877 } 8878 return false; 8879} 8880 8881SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8882 bool addTest = true; 8883 SDValue Chain = Op.getOperand(0); 8884 SDValue Cond = Op.getOperand(1); 8885 SDValue Dest = Op.getOperand(2); 8886 DebugLoc dl = Op.getDebugLoc(); 8887 SDValue CC; 8888 bool Inverted = false; 8889 8890 if (Cond.getOpcode() == ISD::SETCC) { 8891 // Check for setcc([su]{add,sub,mul}o == 0). 8892 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8893 isa<ConstantSDNode>(Cond.getOperand(1)) && 8894 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8895 Cond.getOperand(0).getResNo() == 1 && 8896 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8897 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8898 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8899 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8900 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8901 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8902 Inverted = true; 8903 Cond = Cond.getOperand(0); 8904 } else { 8905 SDValue NewCond = LowerSETCC(Cond, DAG); 8906 if (NewCond.getNode()) 8907 Cond = NewCond; 8908 } 8909 } 8910#if 0 8911 // FIXME: LowerXALUO doesn't handle these!! 8912 else if (Cond.getOpcode() == X86ISD::ADD || 8913 Cond.getOpcode() == X86ISD::SUB || 8914 Cond.getOpcode() == X86ISD::SMUL || 8915 Cond.getOpcode() == X86ISD::UMUL) 8916 Cond = LowerXALUO(Cond, DAG); 8917#endif 8918 8919 // Look pass (and (setcc_carry (cmp ...)), 1). 8920 if (Cond.getOpcode() == ISD::AND && 8921 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8923 if (C && C->getAPIntValue() == 1) 8924 Cond = Cond.getOperand(0); 8925 } 8926 8927 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8928 // setting operand in place of the X86ISD::SETCC. 8929 unsigned CondOpcode = Cond.getOpcode(); 8930 if (CondOpcode == X86ISD::SETCC || 8931 CondOpcode == X86ISD::SETCC_CARRY) { 8932 CC = Cond.getOperand(0); 8933 8934 SDValue Cmp = Cond.getOperand(1); 8935 unsigned Opc = Cmp.getOpcode(); 8936 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8937 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8938 Cond = Cmp; 8939 addTest = false; 8940 } else { 8941 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8942 default: break; 8943 case X86::COND_O: 8944 case X86::COND_B: 8945 // These can only come from an arithmetic instruction with overflow, 8946 // e.g. SADDO, UADDO. 8947 Cond = Cond.getNode()->getOperand(1); 8948 addTest = false; 8949 break; 8950 } 8951 } 8952 } 8953 CondOpcode = Cond.getOpcode(); 8954 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8955 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8956 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8957 Cond.getOperand(0).getValueType() != MVT::i8)) { 8958 SDValue LHS = Cond.getOperand(0); 8959 SDValue RHS = Cond.getOperand(1); 8960 unsigned X86Opcode; 8961 unsigned X86Cond; 8962 SDVTList VTs; 8963 switch (CondOpcode) { 8964 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8965 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8966 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8967 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8968 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8969 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8970 default: llvm_unreachable("unexpected overflowing operator"); 8971 } 8972 if (Inverted) 8973 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8974 if (CondOpcode == ISD::UMULO) 8975 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8976 MVT::i32); 8977 else 8978 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8979 8980 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8981 8982 if (CondOpcode == ISD::UMULO) 8983 Cond = X86Op.getValue(2); 8984 else 8985 Cond = X86Op.getValue(1); 8986 8987 CC = DAG.getConstant(X86Cond, MVT::i8); 8988 addTest = false; 8989 } else { 8990 unsigned CondOpc; 8991 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8992 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8993 if (CondOpc == ISD::OR) { 8994 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8995 // two branches instead of an explicit OR instruction with a 8996 // separate test. 8997 if (Cmp == Cond.getOperand(1).getOperand(1) && 8998 isX86LogicalCmp(Cmp)) { 8999 CC = Cond.getOperand(0).getOperand(0); 9000 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9001 Chain, Dest, CC, Cmp); 9002 CC = Cond.getOperand(1).getOperand(0); 9003 Cond = Cmp; 9004 addTest = false; 9005 } 9006 } else { // ISD::AND 9007 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 9008 // two branches instead of an explicit AND instruction with a 9009 // separate test. However, we only do this if this block doesn't 9010 // have a fall-through edge, because this requires an explicit 9011 // jmp when the condition is false. 9012 if (Cmp == Cond.getOperand(1).getOperand(1) && 9013 isX86LogicalCmp(Cmp) && 9014 Op.getNode()->hasOneUse()) { 9015 X86::CondCode CCode = 9016 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9017 CCode = X86::GetOppositeBranchCondition(CCode); 9018 CC = DAG.getConstant(CCode, MVT::i8); 9019 SDNode *User = *Op.getNode()->use_begin(); 9020 // Look for an unconditional branch following this conditional branch. 9021 // We need this because we need to reverse the successors in order 9022 // to implement FCMP_OEQ. 9023 if (User->getOpcode() == ISD::BR) { 9024 SDValue FalseBB = User->getOperand(1); 9025 SDNode *NewBR = 9026 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9027 assert(NewBR == User); 9028 (void)NewBR; 9029 Dest = FalseBB; 9030 9031 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9032 Chain, Dest, CC, Cmp); 9033 X86::CondCode CCode = 9034 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 9035 CCode = X86::GetOppositeBranchCondition(CCode); 9036 CC = DAG.getConstant(CCode, MVT::i8); 9037 Cond = Cmp; 9038 addTest = false; 9039 } 9040 } 9041 } 9042 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 9043 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 9044 // It should be transformed during dag combiner except when the condition 9045 // is set by a arithmetics with overflow node. 9046 X86::CondCode CCode = 9047 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 9048 CCode = X86::GetOppositeBranchCondition(CCode); 9049 CC = DAG.getConstant(CCode, MVT::i8); 9050 Cond = Cond.getOperand(0).getOperand(1); 9051 addTest = false; 9052 } else if (Cond.getOpcode() == ISD::SETCC && 9053 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 9054 // For FCMP_OEQ, we can emit 9055 // two branches instead of an explicit AND instruction with a 9056 // separate test. However, we only do this if this block doesn't 9057 // have a fall-through edge, because this requires an explicit 9058 // jmp when the condition is false. 9059 if (Op.getNode()->hasOneUse()) { 9060 SDNode *User = *Op.getNode()->use_begin(); 9061 // Look for an unconditional branch following this conditional branch. 9062 // We need this because we need to reverse the successors in order 9063 // to implement FCMP_OEQ. 9064 if (User->getOpcode() == ISD::BR) { 9065 SDValue FalseBB = User->getOperand(1); 9066 SDNode *NewBR = 9067 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9068 assert(NewBR == User); 9069 (void)NewBR; 9070 Dest = FalseBB; 9071 9072 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9073 Cond.getOperand(0), Cond.getOperand(1)); 9074 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9075 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9076 Chain, Dest, CC, Cmp); 9077 CC = DAG.getConstant(X86::COND_P, MVT::i8); 9078 Cond = Cmp; 9079 addTest = false; 9080 } 9081 } 9082 } else if (Cond.getOpcode() == ISD::SETCC && 9083 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 9084 // For FCMP_UNE, we can emit 9085 // two branches instead of an explicit AND instruction with a 9086 // separate test. However, we only do this if this block doesn't 9087 // have a fall-through edge, because this requires an explicit 9088 // jmp when the condition is false. 9089 if (Op.getNode()->hasOneUse()) { 9090 SDNode *User = *Op.getNode()->use_begin(); 9091 // Look for an unconditional branch following this conditional branch. 9092 // We need this because we need to reverse the successors in order 9093 // to implement FCMP_UNE. 9094 if (User->getOpcode() == ISD::BR) { 9095 SDValue FalseBB = User->getOperand(1); 9096 SDNode *NewBR = 9097 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 9098 assert(NewBR == User); 9099 (void)NewBR; 9100 9101 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 9102 Cond.getOperand(0), Cond.getOperand(1)); 9103 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9104 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9105 Chain, Dest, CC, Cmp); 9106 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 9107 Cond = Cmp; 9108 addTest = false; 9109 Dest = FalseBB; 9110 } 9111 } 9112 } 9113 } 9114 9115 if (addTest) { 9116 // Look pass the truncate. 9117 if (Cond.getOpcode() == ISD::TRUNCATE) 9118 Cond = Cond.getOperand(0); 9119 9120 // We know the result of AND is compared against zero. Try to match 9121 // it to BT. 9122 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 9123 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 9124 if (NewSetCC.getNode()) { 9125 CC = NewSetCC.getOperand(0); 9126 Cond = NewSetCC.getOperand(1); 9127 addTest = false; 9128 } 9129 } 9130 } 9131 9132 if (addTest) { 9133 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9134 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9135 } 9136 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9137 Chain, Dest, CC, Cond); 9138} 9139 9140 9141// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9142// Calls to _alloca is needed to probe the stack when allocating more than 4k 9143// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9144// that the guard pages used by the OS virtual memory manager are allocated in 9145// correct sequence. 9146SDValue 9147X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9148 SelectionDAG &DAG) const { 9149 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9150 EnableSegmentedStacks) && 9151 "This should be used only on Windows targets or when segmented stacks " 9152 "are being used"); 9153 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9154 DebugLoc dl = Op.getDebugLoc(); 9155 9156 // Get the inputs. 9157 SDValue Chain = Op.getOperand(0); 9158 SDValue Size = Op.getOperand(1); 9159 // FIXME: Ensure alignment here 9160 9161 bool Is64Bit = Subtarget->is64Bit(); 9162 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9163 9164 if (EnableSegmentedStacks) { 9165 MachineFunction &MF = DAG.getMachineFunction(); 9166 MachineRegisterInfo &MRI = MF.getRegInfo(); 9167 9168 if (Is64Bit) { 9169 // The 64 bit implementation of segmented stacks needs to clobber both r10 9170 // r11. This makes it impossible to use it along with nested parameters. 9171 const Function *F = MF.getFunction(); 9172 9173 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9174 I != E; I++) 9175 if (I->hasNestAttr()) 9176 report_fatal_error("Cannot use segmented stacks with functions that " 9177 "have nested arguments."); 9178 } 9179 9180 const TargetRegisterClass *AddrRegClass = 9181 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9182 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9183 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9184 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9185 DAG.getRegister(Vreg, SPTy)); 9186 SDValue Ops1[2] = { Value, Chain }; 9187 return DAG.getMergeValues(Ops1, 2, dl); 9188 } else { 9189 SDValue Flag; 9190 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9191 9192 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9193 Flag = Chain.getValue(1); 9194 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9195 9196 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9197 Flag = Chain.getValue(1); 9198 9199 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9200 9201 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9202 return DAG.getMergeValues(Ops1, 2, dl); 9203 } 9204} 9205 9206SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9207 MachineFunction &MF = DAG.getMachineFunction(); 9208 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9209 9210 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9211 DebugLoc DL = Op.getDebugLoc(); 9212 9213 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9214 // vastart just stores the address of the VarArgsFrameIndex slot into the 9215 // memory location argument. 9216 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9217 getPointerTy()); 9218 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9219 MachinePointerInfo(SV), false, false, 0); 9220 } 9221 9222 // __va_list_tag: 9223 // gp_offset (0 - 6 * 8) 9224 // fp_offset (48 - 48 + 8 * 16) 9225 // overflow_arg_area (point to parameters coming in memory). 9226 // reg_save_area 9227 SmallVector<SDValue, 8> MemOps; 9228 SDValue FIN = Op.getOperand(1); 9229 // Store gp_offset 9230 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9231 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9232 MVT::i32), 9233 FIN, MachinePointerInfo(SV), false, false, 0); 9234 MemOps.push_back(Store); 9235 9236 // Store fp_offset 9237 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9238 FIN, DAG.getIntPtrConstant(4)); 9239 Store = DAG.getStore(Op.getOperand(0), DL, 9240 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9241 MVT::i32), 9242 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9243 MemOps.push_back(Store); 9244 9245 // Store ptr to overflow_arg_area 9246 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9247 FIN, DAG.getIntPtrConstant(4)); 9248 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9249 getPointerTy()); 9250 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9251 MachinePointerInfo(SV, 8), 9252 false, false, 0); 9253 MemOps.push_back(Store); 9254 9255 // Store ptr to reg_save_area. 9256 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9257 FIN, DAG.getIntPtrConstant(8)); 9258 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9259 getPointerTy()); 9260 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9261 MachinePointerInfo(SV, 16), false, false, 0); 9262 MemOps.push_back(Store); 9263 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9264 &MemOps[0], MemOps.size()); 9265} 9266 9267SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9268 assert(Subtarget->is64Bit() && 9269 "LowerVAARG only handles 64-bit va_arg!"); 9270 assert((Subtarget->isTargetLinux() || 9271 Subtarget->isTargetDarwin()) && 9272 "Unhandled target in LowerVAARG"); 9273 assert(Op.getNode()->getNumOperands() == 4); 9274 SDValue Chain = Op.getOperand(0); 9275 SDValue SrcPtr = Op.getOperand(1); 9276 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9277 unsigned Align = Op.getConstantOperandVal(3); 9278 DebugLoc dl = Op.getDebugLoc(); 9279 9280 EVT ArgVT = Op.getNode()->getValueType(0); 9281 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9282 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9283 uint8_t ArgMode; 9284 9285 // Decide which area this value should be read from. 9286 // TODO: Implement the AMD64 ABI in its entirety. This simple 9287 // selection mechanism works only for the basic types. 9288 if (ArgVT == MVT::f80) { 9289 llvm_unreachable("va_arg for f80 not yet implemented"); 9290 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9291 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9292 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9293 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9294 } else { 9295 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9296 } 9297 9298 if (ArgMode == 2) { 9299 // Sanity Check: Make sure using fp_offset makes sense. 9300 assert(!UseSoftFloat && 9301 !(DAG.getMachineFunction() 9302 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9303 Subtarget->hasXMM()); 9304 } 9305 9306 // Insert VAARG_64 node into the DAG 9307 // VAARG_64 returns two values: Variable Argument Address, Chain 9308 SmallVector<SDValue, 11> InstOps; 9309 InstOps.push_back(Chain); 9310 InstOps.push_back(SrcPtr); 9311 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9312 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9313 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9314 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9315 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9316 VTs, &InstOps[0], InstOps.size(), 9317 MVT::i64, 9318 MachinePointerInfo(SV), 9319 /*Align=*/0, 9320 /*Volatile=*/false, 9321 /*ReadMem=*/true, 9322 /*WriteMem=*/true); 9323 Chain = VAARG.getValue(1); 9324 9325 // Load the next argument and return it 9326 return DAG.getLoad(ArgVT, dl, 9327 Chain, 9328 VAARG, 9329 MachinePointerInfo(), 9330 false, false, false, 0); 9331} 9332 9333SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9334 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9335 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9336 SDValue Chain = Op.getOperand(0); 9337 SDValue DstPtr = Op.getOperand(1); 9338 SDValue SrcPtr = Op.getOperand(2); 9339 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9340 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9341 DebugLoc DL = Op.getDebugLoc(); 9342 9343 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9344 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9345 false, 9346 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9347} 9348 9349SDValue 9350X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9351 DebugLoc dl = Op.getDebugLoc(); 9352 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9353 switch (IntNo) { 9354 default: return SDValue(); // Don't custom lower most intrinsics. 9355 // Comparison intrinsics. 9356 case Intrinsic::x86_sse_comieq_ss: 9357 case Intrinsic::x86_sse_comilt_ss: 9358 case Intrinsic::x86_sse_comile_ss: 9359 case Intrinsic::x86_sse_comigt_ss: 9360 case Intrinsic::x86_sse_comige_ss: 9361 case Intrinsic::x86_sse_comineq_ss: 9362 case Intrinsic::x86_sse_ucomieq_ss: 9363 case Intrinsic::x86_sse_ucomilt_ss: 9364 case Intrinsic::x86_sse_ucomile_ss: 9365 case Intrinsic::x86_sse_ucomigt_ss: 9366 case Intrinsic::x86_sse_ucomige_ss: 9367 case Intrinsic::x86_sse_ucomineq_ss: 9368 case Intrinsic::x86_sse2_comieq_sd: 9369 case Intrinsic::x86_sse2_comilt_sd: 9370 case Intrinsic::x86_sse2_comile_sd: 9371 case Intrinsic::x86_sse2_comigt_sd: 9372 case Intrinsic::x86_sse2_comige_sd: 9373 case Intrinsic::x86_sse2_comineq_sd: 9374 case Intrinsic::x86_sse2_ucomieq_sd: 9375 case Intrinsic::x86_sse2_ucomilt_sd: 9376 case Intrinsic::x86_sse2_ucomile_sd: 9377 case Intrinsic::x86_sse2_ucomigt_sd: 9378 case Intrinsic::x86_sse2_ucomige_sd: 9379 case Intrinsic::x86_sse2_ucomineq_sd: { 9380 unsigned Opc = 0; 9381 ISD::CondCode CC = ISD::SETCC_INVALID; 9382 switch (IntNo) { 9383 default: break; 9384 case Intrinsic::x86_sse_comieq_ss: 9385 case Intrinsic::x86_sse2_comieq_sd: 9386 Opc = X86ISD::COMI; 9387 CC = ISD::SETEQ; 9388 break; 9389 case Intrinsic::x86_sse_comilt_ss: 9390 case Intrinsic::x86_sse2_comilt_sd: 9391 Opc = X86ISD::COMI; 9392 CC = ISD::SETLT; 9393 break; 9394 case Intrinsic::x86_sse_comile_ss: 9395 case Intrinsic::x86_sse2_comile_sd: 9396 Opc = X86ISD::COMI; 9397 CC = ISD::SETLE; 9398 break; 9399 case Intrinsic::x86_sse_comigt_ss: 9400 case Intrinsic::x86_sse2_comigt_sd: 9401 Opc = X86ISD::COMI; 9402 CC = ISD::SETGT; 9403 break; 9404 case Intrinsic::x86_sse_comige_ss: 9405 case Intrinsic::x86_sse2_comige_sd: 9406 Opc = X86ISD::COMI; 9407 CC = ISD::SETGE; 9408 break; 9409 case Intrinsic::x86_sse_comineq_ss: 9410 case Intrinsic::x86_sse2_comineq_sd: 9411 Opc = X86ISD::COMI; 9412 CC = ISD::SETNE; 9413 break; 9414 case Intrinsic::x86_sse_ucomieq_ss: 9415 case Intrinsic::x86_sse2_ucomieq_sd: 9416 Opc = X86ISD::UCOMI; 9417 CC = ISD::SETEQ; 9418 break; 9419 case Intrinsic::x86_sse_ucomilt_ss: 9420 case Intrinsic::x86_sse2_ucomilt_sd: 9421 Opc = X86ISD::UCOMI; 9422 CC = ISD::SETLT; 9423 break; 9424 case Intrinsic::x86_sse_ucomile_ss: 9425 case Intrinsic::x86_sse2_ucomile_sd: 9426 Opc = X86ISD::UCOMI; 9427 CC = ISD::SETLE; 9428 break; 9429 case Intrinsic::x86_sse_ucomigt_ss: 9430 case Intrinsic::x86_sse2_ucomigt_sd: 9431 Opc = X86ISD::UCOMI; 9432 CC = ISD::SETGT; 9433 break; 9434 case Intrinsic::x86_sse_ucomige_ss: 9435 case Intrinsic::x86_sse2_ucomige_sd: 9436 Opc = X86ISD::UCOMI; 9437 CC = ISD::SETGE; 9438 break; 9439 case Intrinsic::x86_sse_ucomineq_ss: 9440 case Intrinsic::x86_sse2_ucomineq_sd: 9441 Opc = X86ISD::UCOMI; 9442 CC = ISD::SETNE; 9443 break; 9444 } 9445 9446 SDValue LHS = Op.getOperand(1); 9447 SDValue RHS = Op.getOperand(2); 9448 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9449 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9450 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9451 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9452 DAG.getConstant(X86CC, MVT::i8), Cond); 9453 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9454 } 9455 // Arithmetic intrinsics. 9456 case Intrinsic::x86_sse3_hadd_ps: 9457 case Intrinsic::x86_sse3_hadd_pd: 9458 case Intrinsic::x86_avx_hadd_ps_256: 9459 case Intrinsic::x86_avx_hadd_pd_256: 9460 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9461 Op.getOperand(1), Op.getOperand(2)); 9462 case Intrinsic::x86_sse3_hsub_ps: 9463 case Intrinsic::x86_sse3_hsub_pd: 9464 case Intrinsic::x86_avx_hsub_ps_256: 9465 case Intrinsic::x86_avx_hsub_pd_256: 9466 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9467 Op.getOperand(1), Op.getOperand(2)); 9468 // ptest and testp intrinsics. The intrinsic these come from are designed to 9469 // return an integer value, not just an instruction so lower it to the ptest 9470 // or testp pattern and a setcc for the result. 9471 case Intrinsic::x86_sse41_ptestz: 9472 case Intrinsic::x86_sse41_ptestc: 9473 case Intrinsic::x86_sse41_ptestnzc: 9474 case Intrinsic::x86_avx_ptestz_256: 9475 case Intrinsic::x86_avx_ptestc_256: 9476 case Intrinsic::x86_avx_ptestnzc_256: 9477 case Intrinsic::x86_avx_vtestz_ps: 9478 case Intrinsic::x86_avx_vtestc_ps: 9479 case Intrinsic::x86_avx_vtestnzc_ps: 9480 case Intrinsic::x86_avx_vtestz_pd: 9481 case Intrinsic::x86_avx_vtestc_pd: 9482 case Intrinsic::x86_avx_vtestnzc_pd: 9483 case Intrinsic::x86_avx_vtestz_ps_256: 9484 case Intrinsic::x86_avx_vtestc_ps_256: 9485 case Intrinsic::x86_avx_vtestnzc_ps_256: 9486 case Intrinsic::x86_avx_vtestz_pd_256: 9487 case Intrinsic::x86_avx_vtestc_pd_256: 9488 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9489 bool IsTestPacked = false; 9490 unsigned X86CC = 0; 9491 switch (IntNo) { 9492 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9493 case Intrinsic::x86_avx_vtestz_ps: 9494 case Intrinsic::x86_avx_vtestz_pd: 9495 case Intrinsic::x86_avx_vtestz_ps_256: 9496 case Intrinsic::x86_avx_vtestz_pd_256: 9497 IsTestPacked = true; // Fallthrough 9498 case Intrinsic::x86_sse41_ptestz: 9499 case Intrinsic::x86_avx_ptestz_256: 9500 // ZF = 1 9501 X86CC = X86::COND_E; 9502 break; 9503 case Intrinsic::x86_avx_vtestc_ps: 9504 case Intrinsic::x86_avx_vtestc_pd: 9505 case Intrinsic::x86_avx_vtestc_ps_256: 9506 case Intrinsic::x86_avx_vtestc_pd_256: 9507 IsTestPacked = true; // Fallthrough 9508 case Intrinsic::x86_sse41_ptestc: 9509 case Intrinsic::x86_avx_ptestc_256: 9510 // CF = 1 9511 X86CC = X86::COND_B; 9512 break; 9513 case Intrinsic::x86_avx_vtestnzc_ps: 9514 case Intrinsic::x86_avx_vtestnzc_pd: 9515 case Intrinsic::x86_avx_vtestnzc_ps_256: 9516 case Intrinsic::x86_avx_vtestnzc_pd_256: 9517 IsTestPacked = true; // Fallthrough 9518 case Intrinsic::x86_sse41_ptestnzc: 9519 case Intrinsic::x86_avx_ptestnzc_256: 9520 // ZF and CF = 0 9521 X86CC = X86::COND_A; 9522 break; 9523 } 9524 9525 SDValue LHS = Op.getOperand(1); 9526 SDValue RHS = Op.getOperand(2); 9527 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9528 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9529 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9530 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9531 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9532 } 9533 9534 // Fix vector shift instructions where the last operand is a non-immediate 9535 // i32 value. 9536 case Intrinsic::x86_avx2_pslli_w: 9537 case Intrinsic::x86_avx2_pslli_d: 9538 case Intrinsic::x86_avx2_pslli_q: 9539 case Intrinsic::x86_avx2_psrli_w: 9540 case Intrinsic::x86_avx2_psrli_d: 9541 case Intrinsic::x86_avx2_psrli_q: 9542 case Intrinsic::x86_avx2_psrai_w: 9543 case Intrinsic::x86_avx2_psrai_d: 9544 case Intrinsic::x86_sse2_pslli_w: 9545 case Intrinsic::x86_sse2_pslli_d: 9546 case Intrinsic::x86_sse2_pslli_q: 9547 case Intrinsic::x86_sse2_psrli_w: 9548 case Intrinsic::x86_sse2_psrli_d: 9549 case Intrinsic::x86_sse2_psrli_q: 9550 case Intrinsic::x86_sse2_psrai_w: 9551 case Intrinsic::x86_sse2_psrai_d: 9552 case Intrinsic::x86_mmx_pslli_w: 9553 case Intrinsic::x86_mmx_pslli_d: 9554 case Intrinsic::x86_mmx_pslli_q: 9555 case Intrinsic::x86_mmx_psrli_w: 9556 case Intrinsic::x86_mmx_psrli_d: 9557 case Intrinsic::x86_mmx_psrli_q: 9558 case Intrinsic::x86_mmx_psrai_w: 9559 case Intrinsic::x86_mmx_psrai_d: { 9560 SDValue ShAmt = Op.getOperand(2); 9561 if (isa<ConstantSDNode>(ShAmt)) 9562 return SDValue(); 9563 9564 unsigned NewIntNo = 0; 9565 EVT ShAmtVT = MVT::v4i32; 9566 switch (IntNo) { 9567 case Intrinsic::x86_sse2_pslli_w: 9568 NewIntNo = Intrinsic::x86_sse2_psll_w; 9569 break; 9570 case Intrinsic::x86_sse2_pslli_d: 9571 NewIntNo = Intrinsic::x86_sse2_psll_d; 9572 break; 9573 case Intrinsic::x86_sse2_pslli_q: 9574 NewIntNo = Intrinsic::x86_sse2_psll_q; 9575 break; 9576 case Intrinsic::x86_sse2_psrli_w: 9577 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9578 break; 9579 case Intrinsic::x86_sse2_psrli_d: 9580 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9581 break; 9582 case Intrinsic::x86_sse2_psrli_q: 9583 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9584 break; 9585 case Intrinsic::x86_sse2_psrai_w: 9586 NewIntNo = Intrinsic::x86_sse2_psra_w; 9587 break; 9588 case Intrinsic::x86_sse2_psrai_d: 9589 NewIntNo = Intrinsic::x86_sse2_psra_d; 9590 break; 9591 case Intrinsic::x86_avx2_pslli_w: 9592 NewIntNo = Intrinsic::x86_avx2_psll_w; 9593 break; 9594 case Intrinsic::x86_avx2_pslli_d: 9595 NewIntNo = Intrinsic::x86_avx2_psll_d; 9596 break; 9597 case Intrinsic::x86_avx2_pslli_q: 9598 NewIntNo = Intrinsic::x86_avx2_psll_q; 9599 break; 9600 case Intrinsic::x86_avx2_psrli_w: 9601 NewIntNo = Intrinsic::x86_avx2_psrl_w; 9602 break; 9603 case Intrinsic::x86_avx2_psrli_d: 9604 NewIntNo = Intrinsic::x86_avx2_psrl_d; 9605 break; 9606 case Intrinsic::x86_avx2_psrli_q: 9607 NewIntNo = Intrinsic::x86_avx2_psrl_q; 9608 break; 9609 case Intrinsic::x86_avx2_psrai_w: 9610 NewIntNo = Intrinsic::x86_avx2_psra_w; 9611 break; 9612 case Intrinsic::x86_avx2_psrai_d: 9613 NewIntNo = Intrinsic::x86_avx2_psra_d; 9614 break; 9615 default: { 9616 ShAmtVT = MVT::v2i32; 9617 switch (IntNo) { 9618 case Intrinsic::x86_mmx_pslli_w: 9619 NewIntNo = Intrinsic::x86_mmx_psll_w; 9620 break; 9621 case Intrinsic::x86_mmx_pslli_d: 9622 NewIntNo = Intrinsic::x86_mmx_psll_d; 9623 break; 9624 case Intrinsic::x86_mmx_pslli_q: 9625 NewIntNo = Intrinsic::x86_mmx_psll_q; 9626 break; 9627 case Intrinsic::x86_mmx_psrli_w: 9628 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9629 break; 9630 case Intrinsic::x86_mmx_psrli_d: 9631 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9632 break; 9633 case Intrinsic::x86_mmx_psrli_q: 9634 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9635 break; 9636 case Intrinsic::x86_mmx_psrai_w: 9637 NewIntNo = Intrinsic::x86_mmx_psra_w; 9638 break; 9639 case Intrinsic::x86_mmx_psrai_d: 9640 NewIntNo = Intrinsic::x86_mmx_psra_d; 9641 break; 9642 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9643 } 9644 break; 9645 } 9646 } 9647 9648 // The vector shift intrinsics with scalars uses 32b shift amounts but 9649 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9650 // to be zero. 9651 SDValue ShOps[4]; 9652 ShOps[0] = ShAmt; 9653 ShOps[1] = DAG.getConstant(0, MVT::i32); 9654 if (ShAmtVT == MVT::v4i32) { 9655 ShOps[2] = DAG.getUNDEF(MVT::i32); 9656 ShOps[3] = DAG.getUNDEF(MVT::i32); 9657 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9658 } else { 9659 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9660// FIXME this must be lowered to get rid of the invalid type. 9661 } 9662 9663 EVT VT = Op.getValueType(); 9664 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9665 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9666 DAG.getConstant(NewIntNo, MVT::i32), 9667 Op.getOperand(1), ShAmt); 9668 } 9669 } 9670} 9671 9672SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9673 SelectionDAG &DAG) const { 9674 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9675 MFI->setReturnAddressIsTaken(true); 9676 9677 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9678 DebugLoc dl = Op.getDebugLoc(); 9679 9680 if (Depth > 0) { 9681 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9682 SDValue Offset = 9683 DAG.getConstant(TD->getPointerSize(), 9684 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9685 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9686 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9687 FrameAddr, Offset), 9688 MachinePointerInfo(), false, false, false, 0); 9689 } 9690 9691 // Just load the return address. 9692 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9693 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9694 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9695} 9696 9697SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9698 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9699 MFI->setFrameAddressIsTaken(true); 9700 9701 EVT VT = Op.getValueType(); 9702 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9703 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9704 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9705 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9706 while (Depth--) 9707 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9708 MachinePointerInfo(), 9709 false, false, false, 0); 9710 return FrameAddr; 9711} 9712 9713SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9714 SelectionDAG &DAG) const { 9715 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9716} 9717 9718SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9719 MachineFunction &MF = DAG.getMachineFunction(); 9720 SDValue Chain = Op.getOperand(0); 9721 SDValue Offset = Op.getOperand(1); 9722 SDValue Handler = Op.getOperand(2); 9723 DebugLoc dl = Op.getDebugLoc(); 9724 9725 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9726 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9727 getPointerTy()); 9728 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9729 9730 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9731 DAG.getIntPtrConstant(TD->getPointerSize())); 9732 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9733 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9734 false, false, 0); 9735 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9736 MF.getRegInfo().addLiveOut(StoreAddrReg); 9737 9738 return DAG.getNode(X86ISD::EH_RETURN, dl, 9739 MVT::Other, 9740 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9741} 9742 9743SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9744 SelectionDAG &DAG) const { 9745 return Op.getOperand(0); 9746} 9747 9748SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9749 SelectionDAG &DAG) const { 9750 SDValue Root = Op.getOperand(0); 9751 SDValue Trmp = Op.getOperand(1); // trampoline 9752 SDValue FPtr = Op.getOperand(2); // nested function 9753 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9754 DebugLoc dl = Op.getDebugLoc(); 9755 9756 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9757 9758 if (Subtarget->is64Bit()) { 9759 SDValue OutChains[6]; 9760 9761 // Large code-model. 9762 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9763 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9764 9765 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9766 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9767 9768 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9769 9770 // Load the pointer to the nested function into R11. 9771 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9772 SDValue Addr = Trmp; 9773 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9774 Addr, MachinePointerInfo(TrmpAddr), 9775 false, false, 0); 9776 9777 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9778 DAG.getConstant(2, MVT::i64)); 9779 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9780 MachinePointerInfo(TrmpAddr, 2), 9781 false, false, 2); 9782 9783 // Load the 'nest' parameter value into R10. 9784 // R10 is specified in X86CallingConv.td 9785 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9786 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9787 DAG.getConstant(10, MVT::i64)); 9788 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9789 Addr, MachinePointerInfo(TrmpAddr, 10), 9790 false, false, 0); 9791 9792 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9793 DAG.getConstant(12, MVT::i64)); 9794 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9795 MachinePointerInfo(TrmpAddr, 12), 9796 false, false, 2); 9797 9798 // Jump to the nested function. 9799 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9800 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9801 DAG.getConstant(20, MVT::i64)); 9802 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9803 Addr, MachinePointerInfo(TrmpAddr, 20), 9804 false, false, 0); 9805 9806 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9807 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9808 DAG.getConstant(22, MVT::i64)); 9809 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9810 MachinePointerInfo(TrmpAddr, 22), 9811 false, false, 0); 9812 9813 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9814 } else { 9815 const Function *Func = 9816 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9817 CallingConv::ID CC = Func->getCallingConv(); 9818 unsigned NestReg; 9819 9820 switch (CC) { 9821 default: 9822 llvm_unreachable("Unsupported calling convention"); 9823 case CallingConv::C: 9824 case CallingConv::X86_StdCall: { 9825 // Pass 'nest' parameter in ECX. 9826 // Must be kept in sync with X86CallingConv.td 9827 NestReg = X86::ECX; 9828 9829 // Check that ECX wasn't needed by an 'inreg' parameter. 9830 FunctionType *FTy = Func->getFunctionType(); 9831 const AttrListPtr &Attrs = Func->getAttributes(); 9832 9833 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9834 unsigned InRegCount = 0; 9835 unsigned Idx = 1; 9836 9837 for (FunctionType::param_iterator I = FTy->param_begin(), 9838 E = FTy->param_end(); I != E; ++I, ++Idx) 9839 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9840 // FIXME: should only count parameters that are lowered to integers. 9841 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9842 9843 if (InRegCount > 2) { 9844 report_fatal_error("Nest register in use - reduce number of inreg" 9845 " parameters!"); 9846 } 9847 } 9848 break; 9849 } 9850 case CallingConv::X86_FastCall: 9851 case CallingConv::X86_ThisCall: 9852 case CallingConv::Fast: 9853 // Pass 'nest' parameter in EAX. 9854 // Must be kept in sync with X86CallingConv.td 9855 NestReg = X86::EAX; 9856 break; 9857 } 9858 9859 SDValue OutChains[4]; 9860 SDValue Addr, Disp; 9861 9862 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9863 DAG.getConstant(10, MVT::i32)); 9864 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9865 9866 // This is storing the opcode for MOV32ri. 9867 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9868 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9869 OutChains[0] = DAG.getStore(Root, dl, 9870 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9871 Trmp, MachinePointerInfo(TrmpAddr), 9872 false, false, 0); 9873 9874 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9875 DAG.getConstant(1, MVT::i32)); 9876 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9877 MachinePointerInfo(TrmpAddr, 1), 9878 false, false, 1); 9879 9880 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9881 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9882 DAG.getConstant(5, MVT::i32)); 9883 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9884 MachinePointerInfo(TrmpAddr, 5), 9885 false, false, 1); 9886 9887 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9888 DAG.getConstant(6, MVT::i32)); 9889 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9890 MachinePointerInfo(TrmpAddr, 6), 9891 false, false, 1); 9892 9893 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9894 } 9895} 9896 9897SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9898 SelectionDAG &DAG) const { 9899 /* 9900 The rounding mode is in bits 11:10 of FPSR, and has the following 9901 settings: 9902 00 Round to nearest 9903 01 Round to -inf 9904 10 Round to +inf 9905 11 Round to 0 9906 9907 FLT_ROUNDS, on the other hand, expects the following: 9908 -1 Undefined 9909 0 Round to 0 9910 1 Round to nearest 9911 2 Round to +inf 9912 3 Round to -inf 9913 9914 To perform the conversion, we do: 9915 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9916 */ 9917 9918 MachineFunction &MF = DAG.getMachineFunction(); 9919 const TargetMachine &TM = MF.getTarget(); 9920 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9921 unsigned StackAlignment = TFI.getStackAlignment(); 9922 EVT VT = Op.getValueType(); 9923 DebugLoc DL = Op.getDebugLoc(); 9924 9925 // Save FP Control Word to stack slot 9926 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9927 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9928 9929 9930 MachineMemOperand *MMO = 9931 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9932 MachineMemOperand::MOStore, 2, 2); 9933 9934 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9935 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9936 DAG.getVTList(MVT::Other), 9937 Ops, 2, MVT::i16, MMO); 9938 9939 // Load FP Control Word from stack slot 9940 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9941 MachinePointerInfo(), false, false, false, 0); 9942 9943 // Transform as necessary 9944 SDValue CWD1 = 9945 DAG.getNode(ISD::SRL, DL, MVT::i16, 9946 DAG.getNode(ISD::AND, DL, MVT::i16, 9947 CWD, DAG.getConstant(0x800, MVT::i16)), 9948 DAG.getConstant(11, MVT::i8)); 9949 SDValue CWD2 = 9950 DAG.getNode(ISD::SRL, DL, MVT::i16, 9951 DAG.getNode(ISD::AND, DL, MVT::i16, 9952 CWD, DAG.getConstant(0x400, MVT::i16)), 9953 DAG.getConstant(9, MVT::i8)); 9954 9955 SDValue RetVal = 9956 DAG.getNode(ISD::AND, DL, MVT::i16, 9957 DAG.getNode(ISD::ADD, DL, MVT::i16, 9958 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9959 DAG.getConstant(1, MVT::i16)), 9960 DAG.getConstant(3, MVT::i16)); 9961 9962 9963 return DAG.getNode((VT.getSizeInBits() < 16 ? 9964 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9965} 9966 9967SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9968 EVT VT = Op.getValueType(); 9969 EVT OpVT = VT; 9970 unsigned NumBits = VT.getSizeInBits(); 9971 DebugLoc dl = Op.getDebugLoc(); 9972 9973 Op = Op.getOperand(0); 9974 if (VT == MVT::i8) { 9975 // Zero extend to i32 since there is not an i8 bsr. 9976 OpVT = MVT::i32; 9977 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9978 } 9979 9980 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9981 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9982 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9983 9984 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9985 SDValue Ops[] = { 9986 Op, 9987 DAG.getConstant(NumBits+NumBits-1, OpVT), 9988 DAG.getConstant(X86::COND_E, MVT::i8), 9989 Op.getValue(1) 9990 }; 9991 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9992 9993 // Finally xor with NumBits-1. 9994 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9995 9996 if (VT == MVT::i8) 9997 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9998 return Op; 9999} 10000 10001SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10002 EVT VT = Op.getValueType(); 10003 EVT OpVT = VT; 10004 unsigned NumBits = VT.getSizeInBits(); 10005 DebugLoc dl = Op.getDebugLoc(); 10006 10007 Op = Op.getOperand(0); 10008 if (VT == MVT::i8) { 10009 OpVT = MVT::i32; 10010 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10011 } 10012 10013 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10014 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10015 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10016 10017 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10018 SDValue Ops[] = { 10019 Op, 10020 DAG.getConstant(NumBits, OpVT), 10021 DAG.getConstant(X86::COND_E, MVT::i8), 10022 Op.getValue(1) 10023 }; 10024 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10025 10026 if (VT == MVT::i8) 10027 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10028 return Op; 10029} 10030 10031// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10032// ones, and then concatenate the result back. 10033static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10034 EVT VT = Op.getValueType(); 10035 10036 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10037 "Unsupported value type for operation"); 10038 10039 int NumElems = VT.getVectorNumElements(); 10040 DebugLoc dl = Op.getDebugLoc(); 10041 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10042 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10043 10044 // Extract the LHS vectors 10045 SDValue LHS = Op.getOperand(0); 10046 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10047 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10048 10049 // Extract the RHS vectors 10050 SDValue RHS = Op.getOperand(1); 10051 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10052 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10053 10054 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10055 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10056 10057 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10058 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10059 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10060} 10061 10062SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10063 assert(Op.getValueType().getSizeInBits() == 256 && 10064 Op.getValueType().isInteger() && 10065 "Only handle AVX 256-bit vector integer operation"); 10066 return Lower256IntArith(Op, DAG); 10067} 10068 10069SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10070 assert(Op.getValueType().getSizeInBits() == 256 && 10071 Op.getValueType().isInteger() && 10072 "Only handle AVX 256-bit vector integer operation"); 10073 return Lower256IntArith(Op, DAG); 10074} 10075 10076SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10077 EVT VT = Op.getValueType(); 10078 10079 // Decompose 256-bit ops into smaller 128-bit ops. 10080 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10081 return Lower256IntArith(Op, DAG); 10082 10083 DebugLoc dl = Op.getDebugLoc(); 10084 10085 SDValue A = Op.getOperand(0); 10086 SDValue B = Op.getOperand(1); 10087 10088 if (VT == MVT::v4i64) { 10089 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); 10090 10091 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); 10092 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); 10093 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); 10094 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); 10095 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); 10096 // 10097 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); 10098 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); 10099 // return AloBlo + AloBhi + AhiBlo; 10100 10101 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10102 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 10103 A, DAG.getConstant(32, MVT::i32)); 10104 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10105 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 10106 B, DAG.getConstant(32, MVT::i32)); 10107 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10108 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 10109 A, B); 10110 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10111 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 10112 A, Bhi); 10113 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10114 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 10115 Ahi, B); 10116 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10117 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 10118 AloBhi, DAG.getConstant(32, MVT::i32)); 10119 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10120 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 10121 AhiBlo, DAG.getConstant(32, MVT::i32)); 10122 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10123 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10124 return Res; 10125 } 10126 10127 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 10128 10129 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 10130 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 10131 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 10132 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 10133 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 10134 // 10135 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 10136 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 10137 // return AloBlo + AloBhi + AhiBlo; 10138 10139 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10140 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10141 A, DAG.getConstant(32, MVT::i32)); 10142 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10143 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10144 B, DAG.getConstant(32, MVT::i32)); 10145 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10146 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10147 A, B); 10148 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10149 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10150 A, Bhi); 10151 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10152 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 10153 Ahi, B); 10154 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10155 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10156 AloBhi, DAG.getConstant(32, MVT::i32)); 10157 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10158 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10159 AhiBlo, DAG.getConstant(32, MVT::i32)); 10160 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10161 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10162 return Res; 10163} 10164 10165SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10166 10167 EVT VT = Op.getValueType(); 10168 DebugLoc dl = Op.getDebugLoc(); 10169 SDValue R = Op.getOperand(0); 10170 SDValue Amt = Op.getOperand(1); 10171 LLVMContext *Context = DAG.getContext(); 10172 10173 if (!Subtarget->hasXMMInt()) 10174 return SDValue(); 10175 10176 // Optimize shl/srl/sra with constant shift amount. 10177 if (isSplatVector(Amt.getNode())) { 10178 SDValue SclrAmt = Amt->getOperand(0); 10179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10180 uint64_t ShiftAmt = C->getZExtValue(); 10181 10182 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) { 10183 // Make a large shift. 10184 SDValue SHL = 10185 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10186 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10187 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10188 // Zero out the rightmost bits. 10189 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt), 10190 MVT::i8)); 10191 return DAG.getNode(ISD::AND, dl, VT, SHL, 10192 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10193 } 10194 10195 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 10196 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10197 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 10198 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10199 10200 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 10201 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10202 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10203 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10204 10205 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 10206 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10207 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10208 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10209 10210 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) { 10211 // Make a large shift. 10212 SDValue SRL = 10213 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10214 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10215 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10216 // Zero out the leftmost bits. 10217 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10218 MVT::i8)); 10219 return DAG.getNode(ISD::AND, dl, VT, SRL, 10220 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10221 } 10222 10223 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 10224 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10225 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 10226 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10227 10228 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 10229 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10230 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 10231 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10232 10233 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 10234 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10235 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 10236 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10237 10238 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 10239 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10240 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 10241 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10242 10243 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 10244 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10245 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 10246 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10247 10248 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) { 10249 if (ShiftAmt == 7) { 10250 // R s>> 7 === R s< 0 10251 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 10252 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R); 10253 } 10254 10255 // R s>> a === ((R u>> a) ^ m) - m 10256 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10257 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10258 MVT::i8)); 10259 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10260 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10261 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10262 return Res; 10263 } 10264 10265 if (Subtarget->hasAVX2()) { 10266 if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SHL) 10267 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10268 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 10269 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10270 10271 if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SHL) 10272 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10273 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32), 10274 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10275 10276 if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SHL) 10277 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10278 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 10279 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10280 10281 if (VT == MVT::v4i64 && Op.getOpcode() == ISD::SRL) 10282 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10283 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 10284 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10285 10286 if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRL) 10287 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10288 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32), 10289 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10290 10291 if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRL) 10292 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10293 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 10294 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10295 10296 if (VT == MVT::v8i32 && Op.getOpcode() == ISD::SRA) 10297 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10298 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32), 10299 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10300 10301 if (VT == MVT::v16i16 && Op.getOpcode() == ISD::SRA) 10302 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10303 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32), 10304 R, DAG.getConstant(ShiftAmt, MVT::i32)); 10305 } 10306 } 10307 } 10308 10309 // Lower SHL with variable shift amount. 10310 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10311 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10312 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 10313 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 10314 10315 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10316 10317 std::vector<Constant*> CV(4, CI); 10318 Constant *C = ConstantVector::get(CV); 10319 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10320 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10321 MachinePointerInfo::getConstantPool(), 10322 false, false, false, 16); 10323 10324 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10325 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10326 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10327 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10328 } 10329 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10330 // a = a << 5; 10331 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10332 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 10333 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 10334 10335 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 10336 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 10337 10338 std::vector<Constant*> CVM1(16, CM1); 10339 std::vector<Constant*> CVM2(16, CM2); 10340 Constant *C = ConstantVector::get(CVM1); 10341 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10342 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10343 MachinePointerInfo::getConstantPool(), 10344 false, false, false, 16); 10345 10346 // r = pblendv(r, psllw(r & (char16)15, 4), a); 10347 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10348 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10349 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10350 DAG.getConstant(4, MVT::i32)); 10351 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10352 // a += a 10353 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10354 10355 C = ConstantVector::get(CVM2); 10356 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10357 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10358 MachinePointerInfo::getConstantPool(), 10359 false, false, false, 16); 10360 10361 // r = pblendv(r, psllw(r & (char16)63, 2), a); 10362 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10363 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10364 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10365 DAG.getConstant(2, MVT::i32)); 10366 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10367 // a += a 10368 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10369 10370 // return pblendv(r, r+r, a); 10371 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, 10372 R, DAG.getNode(ISD::ADD, dl, VT, R, R)); 10373 return R; 10374 } 10375 10376 // Decompose 256-bit shifts into smaller 128-bit shifts. 10377 if (VT.getSizeInBits() == 256) { 10378 int NumElems = VT.getVectorNumElements(); 10379 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10380 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10381 10382 // Extract the two vectors 10383 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10384 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10385 DAG, dl); 10386 10387 // Recreate the shift amount vectors 10388 SDValue Amt1, Amt2; 10389 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10390 // Constant shift amount 10391 SmallVector<SDValue, 4> Amt1Csts; 10392 SmallVector<SDValue, 4> Amt2Csts; 10393 for (int i = 0; i < NumElems/2; ++i) 10394 Amt1Csts.push_back(Amt->getOperand(i)); 10395 for (int i = NumElems/2; i < NumElems; ++i) 10396 Amt2Csts.push_back(Amt->getOperand(i)); 10397 10398 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10399 &Amt1Csts[0], NumElems/2); 10400 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10401 &Amt2Csts[0], NumElems/2); 10402 } else { 10403 // Variable shift amount 10404 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10405 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10406 DAG, dl); 10407 } 10408 10409 // Issue new vector shifts for the smaller types 10410 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10411 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10412 10413 // Concatenate the result back 10414 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10415 } 10416 10417 return SDValue(); 10418} 10419 10420SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10421 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10422 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10423 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10424 // has only one use. 10425 SDNode *N = Op.getNode(); 10426 SDValue LHS = N->getOperand(0); 10427 SDValue RHS = N->getOperand(1); 10428 unsigned BaseOp = 0; 10429 unsigned Cond = 0; 10430 DebugLoc DL = Op.getDebugLoc(); 10431 switch (Op.getOpcode()) { 10432 default: llvm_unreachable("Unknown ovf instruction!"); 10433 case ISD::SADDO: 10434 // A subtract of one will be selected as a INC. Note that INC doesn't 10435 // set CF, so we can't do this for UADDO. 10436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10437 if (C->isOne()) { 10438 BaseOp = X86ISD::INC; 10439 Cond = X86::COND_O; 10440 break; 10441 } 10442 BaseOp = X86ISD::ADD; 10443 Cond = X86::COND_O; 10444 break; 10445 case ISD::UADDO: 10446 BaseOp = X86ISD::ADD; 10447 Cond = X86::COND_B; 10448 break; 10449 case ISD::SSUBO: 10450 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10451 // set CF, so we can't do this for USUBO. 10452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10453 if (C->isOne()) { 10454 BaseOp = X86ISD::DEC; 10455 Cond = X86::COND_O; 10456 break; 10457 } 10458 BaseOp = X86ISD::SUB; 10459 Cond = X86::COND_O; 10460 break; 10461 case ISD::USUBO: 10462 BaseOp = X86ISD::SUB; 10463 Cond = X86::COND_B; 10464 break; 10465 case ISD::SMULO: 10466 BaseOp = X86ISD::SMUL; 10467 Cond = X86::COND_O; 10468 break; 10469 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10470 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10471 MVT::i32); 10472 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10473 10474 SDValue SetCC = 10475 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10476 DAG.getConstant(X86::COND_O, MVT::i32), 10477 SDValue(Sum.getNode(), 2)); 10478 10479 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10480 } 10481 } 10482 10483 // Also sets EFLAGS. 10484 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10485 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10486 10487 SDValue SetCC = 10488 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10489 DAG.getConstant(Cond, MVT::i32), 10490 SDValue(Sum.getNode(), 1)); 10491 10492 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10493} 10494 10495SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 10496 DebugLoc dl = Op.getDebugLoc(); 10497 SDNode* Node = Op.getNode(); 10498 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 10499 EVT VT = Node->getValueType(0); 10500 if (Subtarget->hasXMMInt() && VT.isVector()) { 10501 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10502 ExtraVT.getScalarType().getSizeInBits(); 10503 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10504 10505 unsigned SHLIntrinsicsID = 0; 10506 unsigned SRAIntrinsicsID = 0; 10507 switch (VT.getSimpleVT().SimpleTy) { 10508 default: 10509 return SDValue(); 10510 case MVT::v4i32: { 10511 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10512 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10513 break; 10514 } 10515 case MVT::v8i16: { 10516 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10517 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10518 break; 10519 } 10520 } 10521 10522 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10523 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10524 Node->getOperand(0), ShAmt); 10525 10526 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10527 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10528 Tmp1, ShAmt); 10529 } 10530 10531 return SDValue(); 10532} 10533 10534 10535SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10536 DebugLoc dl = Op.getDebugLoc(); 10537 10538 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10539 // There isn't any reason to disable it if the target processor supports it. 10540 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) { 10541 SDValue Chain = Op.getOperand(0); 10542 SDValue Zero = DAG.getConstant(0, MVT::i32); 10543 SDValue Ops[] = { 10544 DAG.getRegister(X86::ESP, MVT::i32), // Base 10545 DAG.getTargetConstant(1, MVT::i8), // Scale 10546 DAG.getRegister(0, MVT::i32), // Index 10547 DAG.getTargetConstant(0, MVT::i32), // Disp 10548 DAG.getRegister(0, MVT::i32), // Segment. 10549 Zero, 10550 Chain 10551 }; 10552 SDNode *Res = 10553 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10554 array_lengthof(Ops)); 10555 return SDValue(Res, 0); 10556 } 10557 10558 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10559 if (!isDev) 10560 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10561 10562 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10563 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10564 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10565 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10566 10567 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10568 if (!Op1 && !Op2 && !Op3 && Op4) 10569 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10570 10571 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10572 if (Op1 && !Op2 && !Op3 && !Op4) 10573 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10574 10575 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10576 // (MFENCE)>; 10577 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10578} 10579 10580SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10581 SelectionDAG &DAG) const { 10582 DebugLoc dl = Op.getDebugLoc(); 10583 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10584 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10585 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10586 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10587 10588 // The only fence that needs an instruction is a sequentially-consistent 10589 // cross-thread fence. 10590 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10591 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10592 // no-sse2). There isn't any reason to disable it if the target processor 10593 // supports it. 10594 if (Subtarget->hasXMMInt() || Subtarget->is64Bit()) 10595 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10596 10597 SDValue Chain = Op.getOperand(0); 10598 SDValue Zero = DAG.getConstant(0, MVT::i32); 10599 SDValue Ops[] = { 10600 DAG.getRegister(X86::ESP, MVT::i32), // Base 10601 DAG.getTargetConstant(1, MVT::i8), // Scale 10602 DAG.getRegister(0, MVT::i32), // Index 10603 DAG.getTargetConstant(0, MVT::i32), // Disp 10604 DAG.getRegister(0, MVT::i32), // Segment. 10605 Zero, 10606 Chain 10607 }; 10608 SDNode *Res = 10609 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10610 array_lengthof(Ops)); 10611 return SDValue(Res, 0); 10612 } 10613 10614 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10615 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10616} 10617 10618 10619SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10620 EVT T = Op.getValueType(); 10621 DebugLoc DL = Op.getDebugLoc(); 10622 unsigned Reg = 0; 10623 unsigned size = 0; 10624 switch(T.getSimpleVT().SimpleTy) { 10625 default: 10626 assert(false && "Invalid value type!"); 10627 case MVT::i8: Reg = X86::AL; size = 1; break; 10628 case MVT::i16: Reg = X86::AX; size = 2; break; 10629 case MVT::i32: Reg = X86::EAX; size = 4; break; 10630 case MVT::i64: 10631 assert(Subtarget->is64Bit() && "Node not type legal!"); 10632 Reg = X86::RAX; size = 8; 10633 break; 10634 } 10635 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10636 Op.getOperand(2), SDValue()); 10637 SDValue Ops[] = { cpIn.getValue(0), 10638 Op.getOperand(1), 10639 Op.getOperand(3), 10640 DAG.getTargetConstant(size, MVT::i8), 10641 cpIn.getValue(1) }; 10642 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10643 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10644 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10645 Ops, 5, T, MMO); 10646 SDValue cpOut = 10647 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10648 return cpOut; 10649} 10650 10651SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10652 SelectionDAG &DAG) const { 10653 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10654 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10655 SDValue TheChain = Op.getOperand(0); 10656 DebugLoc dl = Op.getDebugLoc(); 10657 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10658 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10659 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10660 rax.getValue(2)); 10661 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10662 DAG.getConstant(32, MVT::i8)); 10663 SDValue Ops[] = { 10664 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10665 rdx.getValue(1) 10666 }; 10667 return DAG.getMergeValues(Ops, 2, dl); 10668} 10669 10670SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10671 SelectionDAG &DAG) const { 10672 EVT SrcVT = Op.getOperand(0).getValueType(); 10673 EVT DstVT = Op.getValueType(); 10674 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() && 10675 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10676 assert((DstVT == MVT::i64 || 10677 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10678 "Unexpected custom BITCAST"); 10679 // i64 <=> MMX conversions are Legal. 10680 if (SrcVT==MVT::i64 && DstVT.isVector()) 10681 return Op; 10682 if (DstVT==MVT::i64 && SrcVT.isVector()) 10683 return Op; 10684 // MMX <=> MMX conversions are Legal. 10685 if (SrcVT.isVector() && DstVT.isVector()) 10686 return Op; 10687 // All other conversions need to be expanded. 10688 return SDValue(); 10689} 10690 10691SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10692 SDNode *Node = Op.getNode(); 10693 DebugLoc dl = Node->getDebugLoc(); 10694 EVT T = Node->getValueType(0); 10695 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10696 DAG.getConstant(0, T), Node->getOperand(2)); 10697 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10698 cast<AtomicSDNode>(Node)->getMemoryVT(), 10699 Node->getOperand(0), 10700 Node->getOperand(1), negOp, 10701 cast<AtomicSDNode>(Node)->getSrcValue(), 10702 cast<AtomicSDNode>(Node)->getAlignment(), 10703 cast<AtomicSDNode>(Node)->getOrdering(), 10704 cast<AtomicSDNode>(Node)->getSynchScope()); 10705} 10706 10707static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10708 SDNode *Node = Op.getNode(); 10709 DebugLoc dl = Node->getDebugLoc(); 10710 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10711 10712 // Convert seq_cst store -> xchg 10713 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10714 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10715 // (The only way to get a 16-byte store is cmpxchg16b) 10716 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10717 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10718 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10719 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10720 cast<AtomicSDNode>(Node)->getMemoryVT(), 10721 Node->getOperand(0), 10722 Node->getOperand(1), Node->getOperand(2), 10723 cast<AtomicSDNode>(Node)->getMemOperand(), 10724 cast<AtomicSDNode>(Node)->getOrdering(), 10725 cast<AtomicSDNode>(Node)->getSynchScope()); 10726 return Swap.getValue(1); 10727 } 10728 // Other atomic stores have a simple pattern. 10729 return Op; 10730} 10731 10732static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10733 EVT VT = Op.getNode()->getValueType(0); 10734 10735 // Let legalize expand this if it isn't a legal type yet. 10736 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10737 return SDValue(); 10738 10739 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10740 10741 unsigned Opc; 10742 bool ExtraOp = false; 10743 switch (Op.getOpcode()) { 10744 default: assert(0 && "Invalid code"); 10745 case ISD::ADDC: Opc = X86ISD::ADD; break; 10746 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10747 case ISD::SUBC: Opc = X86ISD::SUB; break; 10748 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10749 } 10750 10751 if (!ExtraOp) 10752 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10753 Op.getOperand(1)); 10754 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10755 Op.getOperand(1), Op.getOperand(2)); 10756} 10757 10758/// LowerOperation - Provide custom lowering hooks for some operations. 10759/// 10760SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10761 switch (Op.getOpcode()) { 10762 default: llvm_unreachable("Should not custom lower this!"); 10763 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10764 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10765 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10766 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10767 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10768 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10769 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10770 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10771 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10772 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10773 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10774 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10775 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10776 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10777 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10778 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10779 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10780 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10781 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10782 case ISD::SHL_PARTS: 10783 case ISD::SRA_PARTS: 10784 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10785 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10786 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10787 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10788 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10789 case ISD::FABS: return LowerFABS(Op, DAG); 10790 case ISD::FNEG: return LowerFNEG(Op, DAG); 10791 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10792 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10793 case ISD::SETCC: return LowerSETCC(Op, DAG); 10794 case ISD::SELECT: return LowerSELECT(Op, DAG); 10795 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10796 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10797 case ISD::VASTART: return LowerVASTART(Op, DAG); 10798 case ISD::VAARG: return LowerVAARG(Op, DAG); 10799 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10800 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10801 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10802 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10803 case ISD::FRAME_TO_ARGS_OFFSET: 10804 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10805 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10806 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10807 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10808 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10809 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10810 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10811 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10812 case ISD::MUL: return LowerMUL(Op, DAG); 10813 case ISD::SRA: 10814 case ISD::SRL: 10815 case ISD::SHL: return LowerShift(Op, DAG); 10816 case ISD::SADDO: 10817 case ISD::UADDO: 10818 case ISD::SSUBO: 10819 case ISD::USUBO: 10820 case ISD::SMULO: 10821 case ISD::UMULO: return LowerXALUO(Op, DAG); 10822 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10823 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10824 case ISD::ADDC: 10825 case ISD::ADDE: 10826 case ISD::SUBC: 10827 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10828 case ISD::ADD: return LowerADD(Op, DAG); 10829 case ISD::SUB: return LowerSUB(Op, DAG); 10830 } 10831} 10832 10833static void ReplaceATOMIC_LOAD(SDNode *Node, 10834 SmallVectorImpl<SDValue> &Results, 10835 SelectionDAG &DAG) { 10836 DebugLoc dl = Node->getDebugLoc(); 10837 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10838 10839 // Convert wide load -> cmpxchg8b/cmpxchg16b 10840 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10841 // (The only way to get a 16-byte load is cmpxchg16b) 10842 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10843 SDValue Zero = DAG.getConstant(0, VT); 10844 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10845 Node->getOperand(0), 10846 Node->getOperand(1), Zero, Zero, 10847 cast<AtomicSDNode>(Node)->getMemOperand(), 10848 cast<AtomicSDNode>(Node)->getOrdering(), 10849 cast<AtomicSDNode>(Node)->getSynchScope()); 10850 Results.push_back(Swap.getValue(0)); 10851 Results.push_back(Swap.getValue(1)); 10852} 10853 10854void X86TargetLowering:: 10855ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10856 SelectionDAG &DAG, unsigned NewOp) const { 10857 DebugLoc dl = Node->getDebugLoc(); 10858 assert (Node->getValueType(0) == MVT::i64 && 10859 "Only know how to expand i64 atomics"); 10860 10861 SDValue Chain = Node->getOperand(0); 10862 SDValue In1 = Node->getOperand(1); 10863 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10864 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10865 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10866 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10867 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10868 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10869 SDValue Result = 10870 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10871 cast<MemSDNode>(Node)->getMemOperand()); 10872 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10873 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10874 Results.push_back(Result.getValue(2)); 10875} 10876 10877/// ReplaceNodeResults - Replace a node with an illegal result type 10878/// with a new node built out of custom code. 10879void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10880 SmallVectorImpl<SDValue>&Results, 10881 SelectionDAG &DAG) const { 10882 DebugLoc dl = N->getDebugLoc(); 10883 switch (N->getOpcode()) { 10884 default: 10885 assert(false && "Do not know how to custom type legalize this operation!"); 10886 return; 10887 case ISD::SIGN_EXTEND_INREG: 10888 case ISD::ADDC: 10889 case ISD::ADDE: 10890 case ISD::SUBC: 10891 case ISD::SUBE: 10892 // We don't want to expand or promote these. 10893 return; 10894 case ISD::FP_TO_SINT: { 10895 std::pair<SDValue,SDValue> Vals = 10896 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10897 SDValue FIST = Vals.first, StackSlot = Vals.second; 10898 if (FIST.getNode() != 0) { 10899 EVT VT = N->getValueType(0); 10900 // Return a load from the stack slot. 10901 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10902 MachinePointerInfo(), 10903 false, false, false, 0)); 10904 } 10905 return; 10906 } 10907 case ISD::READCYCLECOUNTER: { 10908 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10909 SDValue TheChain = N->getOperand(0); 10910 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10911 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10912 rd.getValue(1)); 10913 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10914 eax.getValue(2)); 10915 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10916 SDValue Ops[] = { eax, edx }; 10917 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10918 Results.push_back(edx.getValue(1)); 10919 return; 10920 } 10921 case ISD::ATOMIC_CMP_SWAP: { 10922 EVT T = N->getValueType(0); 10923 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10924 bool Regs64bit = T == MVT::i128; 10925 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10926 SDValue cpInL, cpInH; 10927 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10928 DAG.getConstant(0, HalfT)); 10929 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10930 DAG.getConstant(1, HalfT)); 10931 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10932 Regs64bit ? X86::RAX : X86::EAX, 10933 cpInL, SDValue()); 10934 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10935 Regs64bit ? X86::RDX : X86::EDX, 10936 cpInH, cpInL.getValue(1)); 10937 SDValue swapInL, swapInH; 10938 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10939 DAG.getConstant(0, HalfT)); 10940 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10941 DAG.getConstant(1, HalfT)); 10942 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10943 Regs64bit ? X86::RBX : X86::EBX, 10944 swapInL, cpInH.getValue(1)); 10945 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10946 Regs64bit ? X86::RCX : X86::ECX, 10947 swapInH, swapInL.getValue(1)); 10948 SDValue Ops[] = { swapInH.getValue(0), 10949 N->getOperand(1), 10950 swapInH.getValue(1) }; 10951 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10952 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10953 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10954 X86ISD::LCMPXCHG8_DAG; 10955 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10956 Ops, 3, T, MMO); 10957 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10958 Regs64bit ? X86::RAX : X86::EAX, 10959 HalfT, Result.getValue(1)); 10960 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10961 Regs64bit ? X86::RDX : X86::EDX, 10962 HalfT, cpOutL.getValue(2)); 10963 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10964 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10965 Results.push_back(cpOutH.getValue(1)); 10966 return; 10967 } 10968 case ISD::ATOMIC_LOAD_ADD: 10969 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10970 return; 10971 case ISD::ATOMIC_LOAD_AND: 10972 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10973 return; 10974 case ISD::ATOMIC_LOAD_NAND: 10975 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10976 return; 10977 case ISD::ATOMIC_LOAD_OR: 10978 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10979 return; 10980 case ISD::ATOMIC_LOAD_SUB: 10981 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10982 return; 10983 case ISD::ATOMIC_LOAD_XOR: 10984 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10985 return; 10986 case ISD::ATOMIC_SWAP: 10987 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10988 return; 10989 case ISD::ATOMIC_LOAD: 10990 ReplaceATOMIC_LOAD(N, Results, DAG); 10991 } 10992} 10993 10994const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10995 switch (Opcode) { 10996 default: return NULL; 10997 case X86ISD::BSF: return "X86ISD::BSF"; 10998 case X86ISD::BSR: return "X86ISD::BSR"; 10999 case X86ISD::SHLD: return "X86ISD::SHLD"; 11000 case X86ISD::SHRD: return "X86ISD::SHRD"; 11001 case X86ISD::FAND: return "X86ISD::FAND"; 11002 case X86ISD::FOR: return "X86ISD::FOR"; 11003 case X86ISD::FXOR: return "X86ISD::FXOR"; 11004 case X86ISD::FSRL: return "X86ISD::FSRL"; 11005 case X86ISD::FILD: return "X86ISD::FILD"; 11006 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11007 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11008 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11009 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11010 case X86ISD::FLD: return "X86ISD::FLD"; 11011 case X86ISD::FST: return "X86ISD::FST"; 11012 case X86ISD::CALL: return "X86ISD::CALL"; 11013 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11014 case X86ISD::BT: return "X86ISD::BT"; 11015 case X86ISD::CMP: return "X86ISD::CMP"; 11016 case X86ISD::COMI: return "X86ISD::COMI"; 11017 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11018 case X86ISD::SETCC: return "X86ISD::SETCC"; 11019 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11020 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11021 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11022 case X86ISD::CMOV: return "X86ISD::CMOV"; 11023 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11024 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11025 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11026 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11027 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11028 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11029 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11030 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11031 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11032 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11033 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11034 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11035 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11036 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11037 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 11038 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 11039 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 11040 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11041 case X86ISD::FHADD: return "X86ISD::FHADD"; 11042 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11043 case X86ISD::FMAX: return "X86ISD::FMAX"; 11044 case X86ISD::FMIN: return "X86ISD::FMIN"; 11045 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11046 case X86ISD::FRCP: return "X86ISD::FRCP"; 11047 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11048 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11049 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11050 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11051 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11052 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11053 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11054 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11055 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11056 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11057 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11058 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11059 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11060 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11061 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11062 case X86ISD::VSHL: return "X86ISD::VSHL"; 11063 case X86ISD::VSRL: return "X86ISD::VSRL"; 11064 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 11065 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 11066 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 11067 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 11068 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 11069 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 11070 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 11071 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 11072 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 11073 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 11074 case X86ISD::ADD: return "X86ISD::ADD"; 11075 case X86ISD::SUB: return "X86ISD::SUB"; 11076 case X86ISD::ADC: return "X86ISD::ADC"; 11077 case X86ISD::SBB: return "X86ISD::SBB"; 11078 case X86ISD::SMUL: return "X86ISD::SMUL"; 11079 case X86ISD::UMUL: return "X86ISD::UMUL"; 11080 case X86ISD::INC: return "X86ISD::INC"; 11081 case X86ISD::DEC: return "X86ISD::DEC"; 11082 case X86ISD::OR: return "X86ISD::OR"; 11083 case X86ISD::XOR: return "X86ISD::XOR"; 11084 case X86ISD::AND: return "X86ISD::AND"; 11085 case X86ISD::ANDN: return "X86ISD::ANDN"; 11086 case X86ISD::BLSI: return "X86ISD::BLSI"; 11087 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11088 case X86ISD::BLSR: return "X86ISD::BLSR"; 11089 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11090 case X86ISD::PTEST: return "X86ISD::PTEST"; 11091 case X86ISD::TESTP: return "X86ISD::TESTP"; 11092 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11093 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11094 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11095 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 11096 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11097 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 11098 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 11099 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 11100 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11101 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11102 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11103 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 11104 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11105 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11106 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11107 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11108 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11109 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 11110 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 11111 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11112 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11113 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 11114 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 11115 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 11116 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 11117 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 11118 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 11119 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 11120 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 11121 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 11122 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 11123 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 11124 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 11125 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 11126 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11127 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 11128 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 11129 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 11130 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 11131 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128"; 11132 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11133 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11134 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11135 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11136 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11137 } 11138} 11139 11140// isLegalAddressingMode - Return true if the addressing mode represented 11141// by AM is legal for this target, for a load/store of the specified type. 11142bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11143 Type *Ty) const { 11144 // X86 supports extremely general addressing modes. 11145 CodeModel::Model M = getTargetMachine().getCodeModel(); 11146 Reloc::Model R = getTargetMachine().getRelocationModel(); 11147 11148 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11149 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11150 return false; 11151 11152 if (AM.BaseGV) { 11153 unsigned GVFlags = 11154 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11155 11156 // If a reference to this global requires an extra load, we can't fold it. 11157 if (isGlobalStubReference(GVFlags)) 11158 return false; 11159 11160 // If BaseGV requires a register for the PIC base, we cannot also have a 11161 // BaseReg specified. 11162 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11163 return false; 11164 11165 // If lower 4G is not available, then we must use rip-relative addressing. 11166 if ((M != CodeModel::Small || R != Reloc::Static) && 11167 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11168 return false; 11169 } 11170 11171 switch (AM.Scale) { 11172 case 0: 11173 case 1: 11174 case 2: 11175 case 4: 11176 case 8: 11177 // These scales always work. 11178 break; 11179 case 3: 11180 case 5: 11181 case 9: 11182 // These scales are formed with basereg+scalereg. Only accept if there is 11183 // no basereg yet. 11184 if (AM.HasBaseReg) 11185 return false; 11186 break; 11187 default: // Other stuff never works. 11188 return false; 11189 } 11190 11191 return true; 11192} 11193 11194 11195bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11196 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11197 return false; 11198 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11199 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11200 if (NumBits1 <= NumBits2) 11201 return false; 11202 return true; 11203} 11204 11205bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11206 if (!VT1.isInteger() || !VT2.isInteger()) 11207 return false; 11208 unsigned NumBits1 = VT1.getSizeInBits(); 11209 unsigned NumBits2 = VT2.getSizeInBits(); 11210 if (NumBits1 <= NumBits2) 11211 return false; 11212 return true; 11213} 11214 11215bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11216 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11217 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11218} 11219 11220bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11221 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11222 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11223} 11224 11225bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11226 // i16 instructions are longer (0x66 prefix) and potentially slower. 11227 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11228} 11229 11230/// isShuffleMaskLegal - Targets can use this to indicate that they only 11231/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11232/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11233/// are assumed to be legal. 11234bool 11235X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11236 EVT VT) const { 11237 // Very little shuffling can be done for 64-bit vectors right now. 11238 if (VT.getSizeInBits() == 64) 11239 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()); 11240 11241 // FIXME: pshufb, blends, shifts. 11242 return (VT.getVectorNumElements() == 2 || 11243 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11244 isMOVLMask(M, VT) || 11245 isSHUFPMask(M, VT) || 11246 isPSHUFDMask(M, VT) || 11247 isPSHUFHWMask(M, VT) || 11248 isPSHUFLWMask(M, VT) || 11249 isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()) || 11250 isUNPCKLMask(M, VT) || 11251 isUNPCKHMask(M, VT) || 11252 isUNPCKL_v_undef_Mask(M, VT) || 11253 isUNPCKH_v_undef_Mask(M, VT)); 11254} 11255 11256bool 11257X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11258 EVT VT) const { 11259 unsigned NumElts = VT.getVectorNumElements(); 11260 // FIXME: This collection of masks seems suspect. 11261 if (NumElts == 2) 11262 return true; 11263 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11264 return (isMOVLMask(Mask, VT) || 11265 isCommutedMOVLMask(Mask, VT, true) || 11266 isSHUFPMask(Mask, VT) || 11267 isCommutedSHUFPMask(Mask, VT)); 11268 } 11269 return false; 11270} 11271 11272//===----------------------------------------------------------------------===// 11273// X86 Scheduler Hooks 11274//===----------------------------------------------------------------------===// 11275 11276// private utility function 11277MachineBasicBlock * 11278X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11279 MachineBasicBlock *MBB, 11280 unsigned regOpc, 11281 unsigned immOpc, 11282 unsigned LoadOpc, 11283 unsigned CXchgOpc, 11284 unsigned notOpc, 11285 unsigned EAXreg, 11286 TargetRegisterClass *RC, 11287 bool invSrc) const { 11288 // For the atomic bitwise operator, we generate 11289 // thisMBB: 11290 // newMBB: 11291 // ld t1 = [bitinstr.addr] 11292 // op t2 = t1, [bitinstr.val] 11293 // mov EAX = t1 11294 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11295 // bz newMBB 11296 // fallthrough -->nextMBB 11297 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11298 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11299 MachineFunction::iterator MBBIter = MBB; 11300 ++MBBIter; 11301 11302 /// First build the CFG 11303 MachineFunction *F = MBB->getParent(); 11304 MachineBasicBlock *thisMBB = MBB; 11305 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11306 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11307 F->insert(MBBIter, newMBB); 11308 F->insert(MBBIter, nextMBB); 11309 11310 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11311 nextMBB->splice(nextMBB->begin(), thisMBB, 11312 llvm::next(MachineBasicBlock::iterator(bInstr)), 11313 thisMBB->end()); 11314 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11315 11316 // Update thisMBB to fall through to newMBB 11317 thisMBB->addSuccessor(newMBB); 11318 11319 // newMBB jumps to itself and fall through to nextMBB 11320 newMBB->addSuccessor(nextMBB); 11321 newMBB->addSuccessor(newMBB); 11322 11323 // Insert instructions into newMBB based on incoming instruction 11324 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11325 "unexpected number of operands"); 11326 DebugLoc dl = bInstr->getDebugLoc(); 11327 MachineOperand& destOper = bInstr->getOperand(0); 11328 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11329 int numArgs = bInstr->getNumOperands() - 1; 11330 for (int i=0; i < numArgs; ++i) 11331 argOpers[i] = &bInstr->getOperand(i+1); 11332 11333 // x86 address has 4 operands: base, index, scale, and displacement 11334 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11335 int valArgIndx = lastAddrIndx + 1; 11336 11337 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11338 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11339 for (int i=0; i <= lastAddrIndx; ++i) 11340 (*MIB).addOperand(*argOpers[i]); 11341 11342 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11343 if (invSrc) { 11344 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11345 } 11346 else 11347 tt = t1; 11348 11349 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11350 assert((argOpers[valArgIndx]->isReg() || 11351 argOpers[valArgIndx]->isImm()) && 11352 "invalid operand"); 11353 if (argOpers[valArgIndx]->isReg()) 11354 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11355 else 11356 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11357 MIB.addReg(tt); 11358 (*MIB).addOperand(*argOpers[valArgIndx]); 11359 11360 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11361 MIB.addReg(t1); 11362 11363 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11364 for (int i=0; i <= lastAddrIndx; ++i) 11365 (*MIB).addOperand(*argOpers[i]); 11366 MIB.addReg(t2); 11367 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11368 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11369 bInstr->memoperands_end()); 11370 11371 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11372 MIB.addReg(EAXreg); 11373 11374 // insert branch 11375 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11376 11377 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11378 return nextMBB; 11379} 11380 11381// private utility function: 64 bit atomics on 32 bit host. 11382MachineBasicBlock * 11383X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11384 MachineBasicBlock *MBB, 11385 unsigned regOpcL, 11386 unsigned regOpcH, 11387 unsigned immOpcL, 11388 unsigned immOpcH, 11389 bool invSrc) const { 11390 // For the atomic bitwise operator, we generate 11391 // thisMBB (instructions are in pairs, except cmpxchg8b) 11392 // ld t1,t2 = [bitinstr.addr] 11393 // newMBB: 11394 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11395 // op t5, t6 <- out1, out2, [bitinstr.val] 11396 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11397 // mov ECX, EBX <- t5, t6 11398 // mov EAX, EDX <- t1, t2 11399 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11400 // mov t3, t4 <- EAX, EDX 11401 // bz newMBB 11402 // result in out1, out2 11403 // fallthrough -->nextMBB 11404 11405 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11406 const unsigned LoadOpc = X86::MOV32rm; 11407 const unsigned NotOpc = X86::NOT32r; 11408 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11409 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11410 MachineFunction::iterator MBBIter = MBB; 11411 ++MBBIter; 11412 11413 /// First build the CFG 11414 MachineFunction *F = MBB->getParent(); 11415 MachineBasicBlock *thisMBB = MBB; 11416 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11417 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11418 F->insert(MBBIter, newMBB); 11419 F->insert(MBBIter, nextMBB); 11420 11421 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11422 nextMBB->splice(nextMBB->begin(), thisMBB, 11423 llvm::next(MachineBasicBlock::iterator(bInstr)), 11424 thisMBB->end()); 11425 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11426 11427 // Update thisMBB to fall through to newMBB 11428 thisMBB->addSuccessor(newMBB); 11429 11430 // newMBB jumps to itself and fall through to nextMBB 11431 newMBB->addSuccessor(nextMBB); 11432 newMBB->addSuccessor(newMBB); 11433 11434 DebugLoc dl = bInstr->getDebugLoc(); 11435 // Insert instructions into newMBB based on incoming instruction 11436 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11437 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11438 "unexpected number of operands"); 11439 MachineOperand& dest1Oper = bInstr->getOperand(0); 11440 MachineOperand& dest2Oper = bInstr->getOperand(1); 11441 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11442 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11443 argOpers[i] = &bInstr->getOperand(i+2); 11444 11445 // We use some of the operands multiple times, so conservatively just 11446 // clear any kill flags that might be present. 11447 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11448 argOpers[i]->setIsKill(false); 11449 } 11450 11451 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11452 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11453 11454 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11455 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11456 for (int i=0; i <= lastAddrIndx; ++i) 11457 (*MIB).addOperand(*argOpers[i]); 11458 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11459 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11460 // add 4 to displacement. 11461 for (int i=0; i <= lastAddrIndx-2; ++i) 11462 (*MIB).addOperand(*argOpers[i]); 11463 MachineOperand newOp3 = *(argOpers[3]); 11464 if (newOp3.isImm()) 11465 newOp3.setImm(newOp3.getImm()+4); 11466 else 11467 newOp3.setOffset(newOp3.getOffset()+4); 11468 (*MIB).addOperand(newOp3); 11469 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11470 11471 // t3/4 are defined later, at the bottom of the loop 11472 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11473 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11474 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11475 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11476 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11477 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11478 11479 // The subsequent operations should be using the destination registers of 11480 //the PHI instructions. 11481 if (invSrc) { 11482 t1 = F->getRegInfo().createVirtualRegister(RC); 11483 t2 = F->getRegInfo().createVirtualRegister(RC); 11484 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11485 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11486 } else { 11487 t1 = dest1Oper.getReg(); 11488 t2 = dest2Oper.getReg(); 11489 } 11490 11491 int valArgIndx = lastAddrIndx + 1; 11492 assert((argOpers[valArgIndx]->isReg() || 11493 argOpers[valArgIndx]->isImm()) && 11494 "invalid operand"); 11495 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11496 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11497 if (argOpers[valArgIndx]->isReg()) 11498 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11499 else 11500 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11501 if (regOpcL != X86::MOV32rr) 11502 MIB.addReg(t1); 11503 (*MIB).addOperand(*argOpers[valArgIndx]); 11504 assert(argOpers[valArgIndx + 1]->isReg() == 11505 argOpers[valArgIndx]->isReg()); 11506 assert(argOpers[valArgIndx + 1]->isImm() == 11507 argOpers[valArgIndx]->isImm()); 11508 if (argOpers[valArgIndx + 1]->isReg()) 11509 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11510 else 11511 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11512 if (regOpcH != X86::MOV32rr) 11513 MIB.addReg(t2); 11514 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11515 11516 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11517 MIB.addReg(t1); 11518 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11519 MIB.addReg(t2); 11520 11521 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11522 MIB.addReg(t5); 11523 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11524 MIB.addReg(t6); 11525 11526 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11527 for (int i=0; i <= lastAddrIndx; ++i) 11528 (*MIB).addOperand(*argOpers[i]); 11529 11530 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11531 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11532 bInstr->memoperands_end()); 11533 11534 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11535 MIB.addReg(X86::EAX); 11536 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11537 MIB.addReg(X86::EDX); 11538 11539 // insert branch 11540 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11541 11542 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11543 return nextMBB; 11544} 11545 11546// private utility function 11547MachineBasicBlock * 11548X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11549 MachineBasicBlock *MBB, 11550 unsigned cmovOpc) const { 11551 // For the atomic min/max operator, we generate 11552 // thisMBB: 11553 // newMBB: 11554 // ld t1 = [min/max.addr] 11555 // mov t2 = [min/max.val] 11556 // cmp t1, t2 11557 // cmov[cond] t2 = t1 11558 // mov EAX = t1 11559 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11560 // bz newMBB 11561 // fallthrough -->nextMBB 11562 // 11563 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11564 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11565 MachineFunction::iterator MBBIter = MBB; 11566 ++MBBIter; 11567 11568 /// First build the CFG 11569 MachineFunction *F = MBB->getParent(); 11570 MachineBasicBlock *thisMBB = MBB; 11571 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11572 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11573 F->insert(MBBIter, newMBB); 11574 F->insert(MBBIter, nextMBB); 11575 11576 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11577 nextMBB->splice(nextMBB->begin(), thisMBB, 11578 llvm::next(MachineBasicBlock::iterator(mInstr)), 11579 thisMBB->end()); 11580 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11581 11582 // Update thisMBB to fall through to newMBB 11583 thisMBB->addSuccessor(newMBB); 11584 11585 // newMBB jumps to newMBB and fall through to nextMBB 11586 newMBB->addSuccessor(nextMBB); 11587 newMBB->addSuccessor(newMBB); 11588 11589 DebugLoc dl = mInstr->getDebugLoc(); 11590 // Insert instructions into newMBB based on incoming instruction 11591 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11592 "unexpected number of operands"); 11593 MachineOperand& destOper = mInstr->getOperand(0); 11594 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11595 int numArgs = mInstr->getNumOperands() - 1; 11596 for (int i=0; i < numArgs; ++i) 11597 argOpers[i] = &mInstr->getOperand(i+1); 11598 11599 // x86 address has 4 operands: base, index, scale, and displacement 11600 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11601 int valArgIndx = lastAddrIndx + 1; 11602 11603 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11604 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11605 for (int i=0; i <= lastAddrIndx; ++i) 11606 (*MIB).addOperand(*argOpers[i]); 11607 11608 // We only support register and immediate values 11609 assert((argOpers[valArgIndx]->isReg() || 11610 argOpers[valArgIndx]->isImm()) && 11611 "invalid operand"); 11612 11613 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11614 if (argOpers[valArgIndx]->isReg()) 11615 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11616 else 11617 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11618 (*MIB).addOperand(*argOpers[valArgIndx]); 11619 11620 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11621 MIB.addReg(t1); 11622 11623 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11624 MIB.addReg(t1); 11625 MIB.addReg(t2); 11626 11627 // Generate movc 11628 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11629 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11630 MIB.addReg(t2); 11631 MIB.addReg(t1); 11632 11633 // Cmp and exchange if none has modified the memory location 11634 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11635 for (int i=0; i <= lastAddrIndx; ++i) 11636 (*MIB).addOperand(*argOpers[i]); 11637 MIB.addReg(t3); 11638 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11639 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11640 mInstr->memoperands_end()); 11641 11642 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11643 MIB.addReg(X86::EAX); 11644 11645 // insert branch 11646 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11647 11648 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11649 return nextMBB; 11650} 11651 11652// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11653// or XMM0_V32I8 in AVX all of this code can be replaced with that 11654// in the .td file. 11655MachineBasicBlock * 11656X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11657 unsigned numArgs, bool memArg) const { 11658 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 11659 "Target must have SSE4.2 or AVX features enabled"); 11660 11661 DebugLoc dl = MI->getDebugLoc(); 11662 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11663 unsigned Opc; 11664 if (!Subtarget->hasAVX()) { 11665 if (memArg) 11666 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11667 else 11668 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11669 } else { 11670 if (memArg) 11671 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11672 else 11673 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11674 } 11675 11676 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11677 for (unsigned i = 0; i < numArgs; ++i) { 11678 MachineOperand &Op = MI->getOperand(i+1); 11679 if (!(Op.isReg() && Op.isImplicit())) 11680 MIB.addOperand(Op); 11681 } 11682 BuildMI(*BB, MI, dl, 11683 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11684 MI->getOperand(0).getReg()) 11685 .addReg(X86::XMM0); 11686 11687 MI->eraseFromParent(); 11688 return BB; 11689} 11690 11691MachineBasicBlock * 11692X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11693 DebugLoc dl = MI->getDebugLoc(); 11694 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11695 11696 // Address into RAX/EAX, other two args into ECX, EDX. 11697 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11698 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11699 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11700 for (int i = 0; i < X86::AddrNumOperands; ++i) 11701 MIB.addOperand(MI->getOperand(i)); 11702 11703 unsigned ValOps = X86::AddrNumOperands; 11704 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11705 .addReg(MI->getOperand(ValOps).getReg()); 11706 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11707 .addReg(MI->getOperand(ValOps+1).getReg()); 11708 11709 // The instruction doesn't actually take any operands though. 11710 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11711 11712 MI->eraseFromParent(); // The pseudo is gone now. 11713 return BB; 11714} 11715 11716MachineBasicBlock * 11717X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11718 DebugLoc dl = MI->getDebugLoc(); 11719 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11720 11721 // First arg in ECX, the second in EAX. 11722 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11723 .addReg(MI->getOperand(0).getReg()); 11724 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11725 .addReg(MI->getOperand(1).getReg()); 11726 11727 // The instruction doesn't actually take any operands though. 11728 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11729 11730 MI->eraseFromParent(); // The pseudo is gone now. 11731 return BB; 11732} 11733 11734MachineBasicBlock * 11735X86TargetLowering::EmitVAARG64WithCustomInserter( 11736 MachineInstr *MI, 11737 MachineBasicBlock *MBB) const { 11738 // Emit va_arg instruction on X86-64. 11739 11740 // Operands to this pseudo-instruction: 11741 // 0 ) Output : destination address (reg) 11742 // 1-5) Input : va_list address (addr, i64mem) 11743 // 6 ) ArgSize : Size (in bytes) of vararg type 11744 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11745 // 8 ) Align : Alignment of type 11746 // 9 ) EFLAGS (implicit-def) 11747 11748 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11749 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11750 11751 unsigned DestReg = MI->getOperand(0).getReg(); 11752 MachineOperand &Base = MI->getOperand(1); 11753 MachineOperand &Scale = MI->getOperand(2); 11754 MachineOperand &Index = MI->getOperand(3); 11755 MachineOperand &Disp = MI->getOperand(4); 11756 MachineOperand &Segment = MI->getOperand(5); 11757 unsigned ArgSize = MI->getOperand(6).getImm(); 11758 unsigned ArgMode = MI->getOperand(7).getImm(); 11759 unsigned Align = MI->getOperand(8).getImm(); 11760 11761 // Memory Reference 11762 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11763 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11764 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11765 11766 // Machine Information 11767 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11768 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11769 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11770 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11771 DebugLoc DL = MI->getDebugLoc(); 11772 11773 // struct va_list { 11774 // i32 gp_offset 11775 // i32 fp_offset 11776 // i64 overflow_area (address) 11777 // i64 reg_save_area (address) 11778 // } 11779 // sizeof(va_list) = 24 11780 // alignment(va_list) = 8 11781 11782 unsigned TotalNumIntRegs = 6; 11783 unsigned TotalNumXMMRegs = 8; 11784 bool UseGPOffset = (ArgMode == 1); 11785 bool UseFPOffset = (ArgMode == 2); 11786 unsigned MaxOffset = TotalNumIntRegs * 8 + 11787 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11788 11789 /* Align ArgSize to a multiple of 8 */ 11790 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11791 bool NeedsAlign = (Align > 8); 11792 11793 MachineBasicBlock *thisMBB = MBB; 11794 MachineBasicBlock *overflowMBB; 11795 MachineBasicBlock *offsetMBB; 11796 MachineBasicBlock *endMBB; 11797 11798 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11799 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11800 unsigned OffsetReg = 0; 11801 11802 if (!UseGPOffset && !UseFPOffset) { 11803 // If we only pull from the overflow region, we don't create a branch. 11804 // We don't need to alter control flow. 11805 OffsetDestReg = 0; // unused 11806 OverflowDestReg = DestReg; 11807 11808 offsetMBB = NULL; 11809 overflowMBB = thisMBB; 11810 endMBB = thisMBB; 11811 } else { 11812 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11813 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11814 // If not, pull from overflow_area. (branch to overflowMBB) 11815 // 11816 // thisMBB 11817 // | . 11818 // | . 11819 // offsetMBB overflowMBB 11820 // | . 11821 // | . 11822 // endMBB 11823 11824 // Registers for the PHI in endMBB 11825 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11826 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11827 11828 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11829 MachineFunction *MF = MBB->getParent(); 11830 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11831 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11832 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11833 11834 MachineFunction::iterator MBBIter = MBB; 11835 ++MBBIter; 11836 11837 // Insert the new basic blocks 11838 MF->insert(MBBIter, offsetMBB); 11839 MF->insert(MBBIter, overflowMBB); 11840 MF->insert(MBBIter, endMBB); 11841 11842 // Transfer the remainder of MBB and its successor edges to endMBB. 11843 endMBB->splice(endMBB->begin(), thisMBB, 11844 llvm::next(MachineBasicBlock::iterator(MI)), 11845 thisMBB->end()); 11846 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11847 11848 // Make offsetMBB and overflowMBB successors of thisMBB 11849 thisMBB->addSuccessor(offsetMBB); 11850 thisMBB->addSuccessor(overflowMBB); 11851 11852 // endMBB is a successor of both offsetMBB and overflowMBB 11853 offsetMBB->addSuccessor(endMBB); 11854 overflowMBB->addSuccessor(endMBB); 11855 11856 // Load the offset value into a register 11857 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11858 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11859 .addOperand(Base) 11860 .addOperand(Scale) 11861 .addOperand(Index) 11862 .addDisp(Disp, UseFPOffset ? 4 : 0) 11863 .addOperand(Segment) 11864 .setMemRefs(MMOBegin, MMOEnd); 11865 11866 // Check if there is enough room left to pull this argument. 11867 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11868 .addReg(OffsetReg) 11869 .addImm(MaxOffset + 8 - ArgSizeA8); 11870 11871 // Branch to "overflowMBB" if offset >= max 11872 // Fall through to "offsetMBB" otherwise 11873 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11874 .addMBB(overflowMBB); 11875 } 11876 11877 // In offsetMBB, emit code to use the reg_save_area. 11878 if (offsetMBB) { 11879 assert(OffsetReg != 0); 11880 11881 // Read the reg_save_area address. 11882 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11883 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11884 .addOperand(Base) 11885 .addOperand(Scale) 11886 .addOperand(Index) 11887 .addDisp(Disp, 16) 11888 .addOperand(Segment) 11889 .setMemRefs(MMOBegin, MMOEnd); 11890 11891 // Zero-extend the offset 11892 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11893 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11894 .addImm(0) 11895 .addReg(OffsetReg) 11896 .addImm(X86::sub_32bit); 11897 11898 // Add the offset to the reg_save_area to get the final address. 11899 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11900 .addReg(OffsetReg64) 11901 .addReg(RegSaveReg); 11902 11903 // Compute the offset for the next argument 11904 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11905 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11906 .addReg(OffsetReg) 11907 .addImm(UseFPOffset ? 16 : 8); 11908 11909 // Store it back into the va_list. 11910 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11911 .addOperand(Base) 11912 .addOperand(Scale) 11913 .addOperand(Index) 11914 .addDisp(Disp, UseFPOffset ? 4 : 0) 11915 .addOperand(Segment) 11916 .addReg(NextOffsetReg) 11917 .setMemRefs(MMOBegin, MMOEnd); 11918 11919 // Jump to endMBB 11920 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11921 .addMBB(endMBB); 11922 } 11923 11924 // 11925 // Emit code to use overflow area 11926 // 11927 11928 // Load the overflow_area address into a register. 11929 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11930 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11931 .addOperand(Base) 11932 .addOperand(Scale) 11933 .addOperand(Index) 11934 .addDisp(Disp, 8) 11935 .addOperand(Segment) 11936 .setMemRefs(MMOBegin, MMOEnd); 11937 11938 // If we need to align it, do so. Otherwise, just copy the address 11939 // to OverflowDestReg. 11940 if (NeedsAlign) { 11941 // Align the overflow address 11942 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11943 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11944 11945 // aligned_addr = (addr + (align-1)) & ~(align-1) 11946 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11947 .addReg(OverflowAddrReg) 11948 .addImm(Align-1); 11949 11950 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11951 .addReg(TmpReg) 11952 .addImm(~(uint64_t)(Align-1)); 11953 } else { 11954 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11955 .addReg(OverflowAddrReg); 11956 } 11957 11958 // Compute the next overflow address after this argument. 11959 // (the overflow address should be kept 8-byte aligned) 11960 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11961 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11962 .addReg(OverflowDestReg) 11963 .addImm(ArgSizeA8); 11964 11965 // Store the new overflow address. 11966 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11967 .addOperand(Base) 11968 .addOperand(Scale) 11969 .addOperand(Index) 11970 .addDisp(Disp, 8) 11971 .addOperand(Segment) 11972 .addReg(NextAddrReg) 11973 .setMemRefs(MMOBegin, MMOEnd); 11974 11975 // If we branched, emit the PHI to the front of endMBB. 11976 if (offsetMBB) { 11977 BuildMI(*endMBB, endMBB->begin(), DL, 11978 TII->get(X86::PHI), DestReg) 11979 .addReg(OffsetDestReg).addMBB(offsetMBB) 11980 .addReg(OverflowDestReg).addMBB(overflowMBB); 11981 } 11982 11983 // Erase the pseudo instruction 11984 MI->eraseFromParent(); 11985 11986 return endMBB; 11987} 11988 11989MachineBasicBlock * 11990X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11991 MachineInstr *MI, 11992 MachineBasicBlock *MBB) const { 11993 // Emit code to save XMM registers to the stack. The ABI says that the 11994 // number of registers to save is given in %al, so it's theoretically 11995 // possible to do an indirect jump trick to avoid saving all of them, 11996 // however this code takes a simpler approach and just executes all 11997 // of the stores if %al is non-zero. It's less code, and it's probably 11998 // easier on the hardware branch predictor, and stores aren't all that 11999 // expensive anyway. 12000 12001 // Create the new basic blocks. One block contains all the XMM stores, 12002 // and one block is the final destination regardless of whether any 12003 // stores were performed. 12004 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12005 MachineFunction *F = MBB->getParent(); 12006 MachineFunction::iterator MBBIter = MBB; 12007 ++MBBIter; 12008 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12009 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12010 F->insert(MBBIter, XMMSaveMBB); 12011 F->insert(MBBIter, EndMBB); 12012 12013 // Transfer the remainder of MBB and its successor edges to EndMBB. 12014 EndMBB->splice(EndMBB->begin(), MBB, 12015 llvm::next(MachineBasicBlock::iterator(MI)), 12016 MBB->end()); 12017 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12018 12019 // The original block will now fall through to the XMM save block. 12020 MBB->addSuccessor(XMMSaveMBB); 12021 // The XMMSaveMBB will fall through to the end block. 12022 XMMSaveMBB->addSuccessor(EndMBB); 12023 12024 // Now add the instructions. 12025 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12026 DebugLoc DL = MI->getDebugLoc(); 12027 12028 unsigned CountReg = MI->getOperand(0).getReg(); 12029 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12030 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12031 12032 if (!Subtarget->isTargetWin64()) { 12033 // If %al is 0, branch around the XMM save block. 12034 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12035 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12036 MBB->addSuccessor(EndMBB); 12037 } 12038 12039 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12040 // In the XMM save block, save all the XMM argument registers. 12041 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12042 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12043 MachineMemOperand *MMO = 12044 F->getMachineMemOperand( 12045 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12046 MachineMemOperand::MOStore, 12047 /*Size=*/16, /*Align=*/16); 12048 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12049 .addFrameIndex(RegSaveFrameIndex) 12050 .addImm(/*Scale=*/1) 12051 .addReg(/*IndexReg=*/0) 12052 .addImm(/*Disp=*/Offset) 12053 .addReg(/*Segment=*/0) 12054 .addReg(MI->getOperand(i).getReg()) 12055 .addMemOperand(MMO); 12056 } 12057 12058 MI->eraseFromParent(); // The pseudo instruction is gone now. 12059 12060 return EndMBB; 12061} 12062 12063MachineBasicBlock * 12064X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12065 MachineBasicBlock *BB) const { 12066 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12067 DebugLoc DL = MI->getDebugLoc(); 12068 12069 // To "insert" a SELECT_CC instruction, we actually have to insert the 12070 // diamond control-flow pattern. The incoming instruction knows the 12071 // destination vreg to set, the condition code register to branch on, the 12072 // true/false values to select between, and a branch opcode to use. 12073 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12074 MachineFunction::iterator It = BB; 12075 ++It; 12076 12077 // thisMBB: 12078 // ... 12079 // TrueVal = ... 12080 // cmpTY ccX, r1, r2 12081 // bCC copy1MBB 12082 // fallthrough --> copy0MBB 12083 MachineBasicBlock *thisMBB = BB; 12084 MachineFunction *F = BB->getParent(); 12085 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12086 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12087 F->insert(It, copy0MBB); 12088 F->insert(It, sinkMBB); 12089 12090 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12091 // live into the sink and copy blocks. 12092 if (!MI->killsRegister(X86::EFLAGS)) { 12093 copy0MBB->addLiveIn(X86::EFLAGS); 12094 sinkMBB->addLiveIn(X86::EFLAGS); 12095 } 12096 12097 // Transfer the remainder of BB and its successor edges to sinkMBB. 12098 sinkMBB->splice(sinkMBB->begin(), BB, 12099 llvm::next(MachineBasicBlock::iterator(MI)), 12100 BB->end()); 12101 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12102 12103 // Add the true and fallthrough blocks as its successors. 12104 BB->addSuccessor(copy0MBB); 12105 BB->addSuccessor(sinkMBB); 12106 12107 // Create the conditional branch instruction. 12108 unsigned Opc = 12109 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12110 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12111 12112 // copy0MBB: 12113 // %FalseValue = ... 12114 // # fallthrough to sinkMBB 12115 copy0MBB->addSuccessor(sinkMBB); 12116 12117 // sinkMBB: 12118 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12119 // ... 12120 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12121 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12122 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12123 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12124 12125 MI->eraseFromParent(); // The pseudo instruction is gone now. 12126 return sinkMBB; 12127} 12128 12129MachineBasicBlock * 12130X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12131 bool Is64Bit) const { 12132 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12133 DebugLoc DL = MI->getDebugLoc(); 12134 MachineFunction *MF = BB->getParent(); 12135 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12136 12137 assert(EnableSegmentedStacks); 12138 12139 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12140 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12141 12142 // BB: 12143 // ... [Till the alloca] 12144 // If stacklet is not large enough, jump to mallocMBB 12145 // 12146 // bumpMBB: 12147 // Allocate by subtracting from RSP 12148 // Jump to continueMBB 12149 // 12150 // mallocMBB: 12151 // Allocate by call to runtime 12152 // 12153 // continueMBB: 12154 // ... 12155 // [rest of original BB] 12156 // 12157 12158 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12159 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12160 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12161 12162 MachineRegisterInfo &MRI = MF->getRegInfo(); 12163 const TargetRegisterClass *AddrRegClass = 12164 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12165 12166 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12167 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12168 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12169 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12170 sizeVReg = MI->getOperand(1).getReg(), 12171 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12172 12173 MachineFunction::iterator MBBIter = BB; 12174 ++MBBIter; 12175 12176 MF->insert(MBBIter, bumpMBB); 12177 MF->insert(MBBIter, mallocMBB); 12178 MF->insert(MBBIter, continueMBB); 12179 12180 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12181 (MachineBasicBlock::iterator(MI)), BB->end()); 12182 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12183 12184 // Add code to the main basic block to check if the stack limit has been hit, 12185 // and if so, jump to mallocMBB otherwise to bumpMBB. 12186 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12187 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12188 .addReg(tmpSPVReg).addReg(sizeVReg); 12189 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12190 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12191 .addReg(SPLimitVReg); 12192 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12193 12194 // bumpMBB simply decreases the stack pointer, since we know the current 12195 // stacklet has enough space. 12196 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12197 .addReg(SPLimitVReg); 12198 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12199 .addReg(SPLimitVReg); 12200 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12201 12202 // Calls into a routine in libgcc to allocate more space from the heap. 12203 if (Is64Bit) { 12204 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12205 .addReg(sizeVReg); 12206 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12207 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12208 } else { 12209 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12210 .addImm(12); 12211 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12212 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12213 .addExternalSymbol("__morestack_allocate_stack_space"); 12214 } 12215 12216 if (!Is64Bit) 12217 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12218 .addImm(16); 12219 12220 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12221 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12222 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12223 12224 // Set up the CFG correctly. 12225 BB->addSuccessor(bumpMBB); 12226 BB->addSuccessor(mallocMBB); 12227 mallocMBB->addSuccessor(continueMBB); 12228 bumpMBB->addSuccessor(continueMBB); 12229 12230 // Take care of the PHI nodes. 12231 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12232 MI->getOperand(0).getReg()) 12233 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12234 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12235 12236 // Delete the original pseudo instruction. 12237 MI->eraseFromParent(); 12238 12239 // And we're done. 12240 return continueMBB; 12241} 12242 12243MachineBasicBlock * 12244X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12245 MachineBasicBlock *BB) const { 12246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12247 DebugLoc DL = MI->getDebugLoc(); 12248 12249 assert(!Subtarget->isTargetEnvMacho()); 12250 12251 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12252 // non-trivial part is impdef of ESP. 12253 12254 if (Subtarget->isTargetWin64()) { 12255 if (Subtarget->isTargetCygMing()) { 12256 // ___chkstk(Mingw64): 12257 // Clobbers R10, R11, RAX and EFLAGS. 12258 // Updates RSP. 12259 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12260 .addExternalSymbol("___chkstk") 12261 .addReg(X86::RAX, RegState::Implicit) 12262 .addReg(X86::RSP, RegState::Implicit) 12263 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12264 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12265 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12266 } else { 12267 // __chkstk(MSVCRT): does not update stack pointer. 12268 // Clobbers R10, R11 and EFLAGS. 12269 // FIXME: RAX(allocated size) might be reused and not killed. 12270 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12271 .addExternalSymbol("__chkstk") 12272 .addReg(X86::RAX, RegState::Implicit) 12273 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12274 // RAX has the offset to subtracted from RSP. 12275 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12276 .addReg(X86::RSP) 12277 .addReg(X86::RAX); 12278 } 12279 } else { 12280 const char *StackProbeSymbol = 12281 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12282 12283 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12284 .addExternalSymbol(StackProbeSymbol) 12285 .addReg(X86::EAX, RegState::Implicit) 12286 .addReg(X86::ESP, RegState::Implicit) 12287 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12288 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12289 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12290 } 12291 12292 MI->eraseFromParent(); // The pseudo instruction is gone now. 12293 return BB; 12294} 12295 12296MachineBasicBlock * 12297X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12298 MachineBasicBlock *BB) const { 12299 // This is pretty easy. We're taking the value that we received from 12300 // our load from the relocation, sticking it in either RDI (x86-64) 12301 // or EAX and doing an indirect call. The return value will then 12302 // be in the normal return register. 12303 const X86InstrInfo *TII 12304 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12305 DebugLoc DL = MI->getDebugLoc(); 12306 MachineFunction *F = BB->getParent(); 12307 12308 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12309 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12310 12311 if (Subtarget->is64Bit()) { 12312 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12313 TII->get(X86::MOV64rm), X86::RDI) 12314 .addReg(X86::RIP) 12315 .addImm(0).addReg(0) 12316 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12317 MI->getOperand(3).getTargetFlags()) 12318 .addReg(0); 12319 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12320 addDirectMem(MIB, X86::RDI); 12321 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12322 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12323 TII->get(X86::MOV32rm), X86::EAX) 12324 .addReg(0) 12325 .addImm(0).addReg(0) 12326 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12327 MI->getOperand(3).getTargetFlags()) 12328 .addReg(0); 12329 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12330 addDirectMem(MIB, X86::EAX); 12331 } else { 12332 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12333 TII->get(X86::MOV32rm), X86::EAX) 12334 .addReg(TII->getGlobalBaseReg(F)) 12335 .addImm(0).addReg(0) 12336 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12337 MI->getOperand(3).getTargetFlags()) 12338 .addReg(0); 12339 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12340 addDirectMem(MIB, X86::EAX); 12341 } 12342 12343 MI->eraseFromParent(); // The pseudo instruction is gone now. 12344 return BB; 12345} 12346 12347MachineBasicBlock * 12348X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12349 MachineBasicBlock *BB) const { 12350 switch (MI->getOpcode()) { 12351 default: assert(0 && "Unexpected instr type to insert"); 12352 case X86::TAILJMPd64: 12353 case X86::TAILJMPr64: 12354 case X86::TAILJMPm64: 12355 assert(0 && "TAILJMP64 would not be touched here."); 12356 case X86::TCRETURNdi64: 12357 case X86::TCRETURNri64: 12358 case X86::TCRETURNmi64: 12359 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12360 // On AMD64, additional defs should be added before register allocation. 12361 if (!Subtarget->isTargetWin64()) { 12362 MI->addRegisterDefined(X86::RSI); 12363 MI->addRegisterDefined(X86::RDI); 12364 MI->addRegisterDefined(X86::XMM6); 12365 MI->addRegisterDefined(X86::XMM7); 12366 MI->addRegisterDefined(X86::XMM8); 12367 MI->addRegisterDefined(X86::XMM9); 12368 MI->addRegisterDefined(X86::XMM10); 12369 MI->addRegisterDefined(X86::XMM11); 12370 MI->addRegisterDefined(X86::XMM12); 12371 MI->addRegisterDefined(X86::XMM13); 12372 MI->addRegisterDefined(X86::XMM14); 12373 MI->addRegisterDefined(X86::XMM15); 12374 } 12375 return BB; 12376 case X86::WIN_ALLOCA: 12377 return EmitLoweredWinAlloca(MI, BB); 12378 case X86::SEG_ALLOCA_32: 12379 return EmitLoweredSegAlloca(MI, BB, false); 12380 case X86::SEG_ALLOCA_64: 12381 return EmitLoweredSegAlloca(MI, BB, true); 12382 case X86::TLSCall_32: 12383 case X86::TLSCall_64: 12384 return EmitLoweredTLSCall(MI, BB); 12385 case X86::CMOV_GR8: 12386 case X86::CMOV_FR32: 12387 case X86::CMOV_FR64: 12388 case X86::CMOV_V4F32: 12389 case X86::CMOV_V2F64: 12390 case X86::CMOV_V2I64: 12391 case X86::CMOV_V8F32: 12392 case X86::CMOV_V4F64: 12393 case X86::CMOV_V4I64: 12394 case X86::CMOV_GR16: 12395 case X86::CMOV_GR32: 12396 case X86::CMOV_RFP32: 12397 case X86::CMOV_RFP64: 12398 case X86::CMOV_RFP80: 12399 return EmitLoweredSelect(MI, BB); 12400 12401 case X86::FP32_TO_INT16_IN_MEM: 12402 case X86::FP32_TO_INT32_IN_MEM: 12403 case X86::FP32_TO_INT64_IN_MEM: 12404 case X86::FP64_TO_INT16_IN_MEM: 12405 case X86::FP64_TO_INT32_IN_MEM: 12406 case X86::FP64_TO_INT64_IN_MEM: 12407 case X86::FP80_TO_INT16_IN_MEM: 12408 case X86::FP80_TO_INT32_IN_MEM: 12409 case X86::FP80_TO_INT64_IN_MEM: { 12410 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12411 DebugLoc DL = MI->getDebugLoc(); 12412 12413 // Change the floating point control register to use "round towards zero" 12414 // mode when truncating to an integer value. 12415 MachineFunction *F = BB->getParent(); 12416 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12417 addFrameReference(BuildMI(*BB, MI, DL, 12418 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12419 12420 // Load the old value of the high byte of the control word... 12421 unsigned OldCW = 12422 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12423 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12424 CWFrameIdx); 12425 12426 // Set the high part to be round to zero... 12427 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12428 .addImm(0xC7F); 12429 12430 // Reload the modified control word now... 12431 addFrameReference(BuildMI(*BB, MI, DL, 12432 TII->get(X86::FLDCW16m)), CWFrameIdx); 12433 12434 // Restore the memory image of control word to original value 12435 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12436 .addReg(OldCW); 12437 12438 // Get the X86 opcode to use. 12439 unsigned Opc; 12440 switch (MI->getOpcode()) { 12441 default: llvm_unreachable("illegal opcode!"); 12442 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12443 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12444 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12445 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12446 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12447 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12448 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12449 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12450 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12451 } 12452 12453 X86AddressMode AM; 12454 MachineOperand &Op = MI->getOperand(0); 12455 if (Op.isReg()) { 12456 AM.BaseType = X86AddressMode::RegBase; 12457 AM.Base.Reg = Op.getReg(); 12458 } else { 12459 AM.BaseType = X86AddressMode::FrameIndexBase; 12460 AM.Base.FrameIndex = Op.getIndex(); 12461 } 12462 Op = MI->getOperand(1); 12463 if (Op.isImm()) 12464 AM.Scale = Op.getImm(); 12465 Op = MI->getOperand(2); 12466 if (Op.isImm()) 12467 AM.IndexReg = Op.getImm(); 12468 Op = MI->getOperand(3); 12469 if (Op.isGlobal()) { 12470 AM.GV = Op.getGlobal(); 12471 } else { 12472 AM.Disp = Op.getImm(); 12473 } 12474 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12475 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12476 12477 // Reload the original control word now. 12478 addFrameReference(BuildMI(*BB, MI, DL, 12479 TII->get(X86::FLDCW16m)), CWFrameIdx); 12480 12481 MI->eraseFromParent(); // The pseudo instruction is gone now. 12482 return BB; 12483 } 12484 // String/text processing lowering. 12485 case X86::PCMPISTRM128REG: 12486 case X86::VPCMPISTRM128REG: 12487 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12488 case X86::PCMPISTRM128MEM: 12489 case X86::VPCMPISTRM128MEM: 12490 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12491 case X86::PCMPESTRM128REG: 12492 case X86::VPCMPESTRM128REG: 12493 return EmitPCMP(MI, BB, 5, false /* in mem */); 12494 case X86::PCMPESTRM128MEM: 12495 case X86::VPCMPESTRM128MEM: 12496 return EmitPCMP(MI, BB, 5, true /* in mem */); 12497 12498 // Thread synchronization. 12499 case X86::MONITOR: 12500 return EmitMonitor(MI, BB); 12501 case X86::MWAIT: 12502 return EmitMwait(MI, BB); 12503 12504 // Atomic Lowering. 12505 case X86::ATOMAND32: 12506 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12507 X86::AND32ri, X86::MOV32rm, 12508 X86::LCMPXCHG32, 12509 X86::NOT32r, X86::EAX, 12510 X86::GR32RegisterClass); 12511 case X86::ATOMOR32: 12512 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12513 X86::OR32ri, X86::MOV32rm, 12514 X86::LCMPXCHG32, 12515 X86::NOT32r, X86::EAX, 12516 X86::GR32RegisterClass); 12517 case X86::ATOMXOR32: 12518 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12519 X86::XOR32ri, X86::MOV32rm, 12520 X86::LCMPXCHG32, 12521 X86::NOT32r, X86::EAX, 12522 X86::GR32RegisterClass); 12523 case X86::ATOMNAND32: 12524 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12525 X86::AND32ri, X86::MOV32rm, 12526 X86::LCMPXCHG32, 12527 X86::NOT32r, X86::EAX, 12528 X86::GR32RegisterClass, true); 12529 case X86::ATOMMIN32: 12530 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12531 case X86::ATOMMAX32: 12532 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12533 case X86::ATOMUMIN32: 12534 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12535 case X86::ATOMUMAX32: 12536 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12537 12538 case X86::ATOMAND16: 12539 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12540 X86::AND16ri, X86::MOV16rm, 12541 X86::LCMPXCHG16, 12542 X86::NOT16r, X86::AX, 12543 X86::GR16RegisterClass); 12544 case X86::ATOMOR16: 12545 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12546 X86::OR16ri, X86::MOV16rm, 12547 X86::LCMPXCHG16, 12548 X86::NOT16r, X86::AX, 12549 X86::GR16RegisterClass); 12550 case X86::ATOMXOR16: 12551 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12552 X86::XOR16ri, X86::MOV16rm, 12553 X86::LCMPXCHG16, 12554 X86::NOT16r, X86::AX, 12555 X86::GR16RegisterClass); 12556 case X86::ATOMNAND16: 12557 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12558 X86::AND16ri, X86::MOV16rm, 12559 X86::LCMPXCHG16, 12560 X86::NOT16r, X86::AX, 12561 X86::GR16RegisterClass, true); 12562 case X86::ATOMMIN16: 12563 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12564 case X86::ATOMMAX16: 12565 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12566 case X86::ATOMUMIN16: 12567 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12568 case X86::ATOMUMAX16: 12569 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12570 12571 case X86::ATOMAND8: 12572 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12573 X86::AND8ri, X86::MOV8rm, 12574 X86::LCMPXCHG8, 12575 X86::NOT8r, X86::AL, 12576 X86::GR8RegisterClass); 12577 case X86::ATOMOR8: 12578 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12579 X86::OR8ri, X86::MOV8rm, 12580 X86::LCMPXCHG8, 12581 X86::NOT8r, X86::AL, 12582 X86::GR8RegisterClass); 12583 case X86::ATOMXOR8: 12584 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12585 X86::XOR8ri, X86::MOV8rm, 12586 X86::LCMPXCHG8, 12587 X86::NOT8r, X86::AL, 12588 X86::GR8RegisterClass); 12589 case X86::ATOMNAND8: 12590 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12591 X86::AND8ri, X86::MOV8rm, 12592 X86::LCMPXCHG8, 12593 X86::NOT8r, X86::AL, 12594 X86::GR8RegisterClass, true); 12595 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12596 // This group is for 64-bit host. 12597 case X86::ATOMAND64: 12598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12599 X86::AND64ri32, X86::MOV64rm, 12600 X86::LCMPXCHG64, 12601 X86::NOT64r, X86::RAX, 12602 X86::GR64RegisterClass); 12603 case X86::ATOMOR64: 12604 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12605 X86::OR64ri32, X86::MOV64rm, 12606 X86::LCMPXCHG64, 12607 X86::NOT64r, X86::RAX, 12608 X86::GR64RegisterClass); 12609 case X86::ATOMXOR64: 12610 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12611 X86::XOR64ri32, X86::MOV64rm, 12612 X86::LCMPXCHG64, 12613 X86::NOT64r, X86::RAX, 12614 X86::GR64RegisterClass); 12615 case X86::ATOMNAND64: 12616 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12617 X86::AND64ri32, X86::MOV64rm, 12618 X86::LCMPXCHG64, 12619 X86::NOT64r, X86::RAX, 12620 X86::GR64RegisterClass, true); 12621 case X86::ATOMMIN64: 12622 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12623 case X86::ATOMMAX64: 12624 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12625 case X86::ATOMUMIN64: 12626 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12627 case X86::ATOMUMAX64: 12628 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12629 12630 // This group does 64-bit operations on a 32-bit host. 12631 case X86::ATOMAND6432: 12632 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12633 X86::AND32rr, X86::AND32rr, 12634 X86::AND32ri, X86::AND32ri, 12635 false); 12636 case X86::ATOMOR6432: 12637 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12638 X86::OR32rr, X86::OR32rr, 12639 X86::OR32ri, X86::OR32ri, 12640 false); 12641 case X86::ATOMXOR6432: 12642 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12643 X86::XOR32rr, X86::XOR32rr, 12644 X86::XOR32ri, X86::XOR32ri, 12645 false); 12646 case X86::ATOMNAND6432: 12647 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12648 X86::AND32rr, X86::AND32rr, 12649 X86::AND32ri, X86::AND32ri, 12650 true); 12651 case X86::ATOMADD6432: 12652 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12653 X86::ADD32rr, X86::ADC32rr, 12654 X86::ADD32ri, X86::ADC32ri, 12655 false); 12656 case X86::ATOMSUB6432: 12657 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12658 X86::SUB32rr, X86::SBB32rr, 12659 X86::SUB32ri, X86::SBB32ri, 12660 false); 12661 case X86::ATOMSWAP6432: 12662 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12663 X86::MOV32rr, X86::MOV32rr, 12664 X86::MOV32ri, X86::MOV32ri, 12665 false); 12666 case X86::VASTART_SAVE_XMM_REGS: 12667 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12668 12669 case X86::VAARG_64: 12670 return EmitVAARG64WithCustomInserter(MI, BB); 12671 } 12672} 12673 12674//===----------------------------------------------------------------------===// 12675// X86 Optimization Hooks 12676//===----------------------------------------------------------------------===// 12677 12678void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12679 const APInt &Mask, 12680 APInt &KnownZero, 12681 APInt &KnownOne, 12682 const SelectionDAG &DAG, 12683 unsigned Depth) const { 12684 unsigned Opc = Op.getOpcode(); 12685 assert((Opc >= ISD::BUILTIN_OP_END || 12686 Opc == ISD::INTRINSIC_WO_CHAIN || 12687 Opc == ISD::INTRINSIC_W_CHAIN || 12688 Opc == ISD::INTRINSIC_VOID) && 12689 "Should use MaskedValueIsZero if you don't know whether Op" 12690 " is a target node!"); 12691 12692 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12693 switch (Opc) { 12694 default: break; 12695 case X86ISD::ADD: 12696 case X86ISD::SUB: 12697 case X86ISD::ADC: 12698 case X86ISD::SBB: 12699 case X86ISD::SMUL: 12700 case X86ISD::UMUL: 12701 case X86ISD::INC: 12702 case X86ISD::DEC: 12703 case X86ISD::OR: 12704 case X86ISD::XOR: 12705 case X86ISD::AND: 12706 // These nodes' second result is a boolean. 12707 if (Op.getResNo() == 0) 12708 break; 12709 // Fallthrough 12710 case X86ISD::SETCC: 12711 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12712 Mask.getBitWidth() - 1); 12713 break; 12714 case ISD::INTRINSIC_WO_CHAIN: { 12715 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12716 unsigned NumLoBits = 0; 12717 switch (IntId) { 12718 default: break; 12719 case Intrinsic::x86_sse_movmsk_ps: 12720 case Intrinsic::x86_avx_movmsk_ps_256: 12721 case Intrinsic::x86_sse2_movmsk_pd: 12722 case Intrinsic::x86_avx_movmsk_pd_256: 12723 case Intrinsic::x86_mmx_pmovmskb: 12724 case Intrinsic::x86_sse2_pmovmskb_128: { 12725 // High bits of movmskp{s|d}, pmovmskb are known zero. 12726 switch (IntId) { 12727 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12728 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12729 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12730 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12731 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12732 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12733 } 12734 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12735 Mask.getBitWidth() - NumLoBits); 12736 break; 12737 } 12738 } 12739 break; 12740 } 12741 } 12742} 12743 12744unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12745 unsigned Depth) const { 12746 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12747 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12748 return Op.getValueType().getScalarType().getSizeInBits(); 12749 12750 // Fallback case. 12751 return 1; 12752} 12753 12754/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12755/// node is a GlobalAddress + offset. 12756bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12757 const GlobalValue* &GA, 12758 int64_t &Offset) const { 12759 if (N->getOpcode() == X86ISD::Wrapper) { 12760 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12761 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12762 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12763 return true; 12764 } 12765 } 12766 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12767} 12768 12769/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12770/// same as extracting the high 128-bit part of 256-bit vector and then 12771/// inserting the result into the low part of a new 256-bit vector 12772static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12773 EVT VT = SVOp->getValueType(0); 12774 int NumElems = VT.getVectorNumElements(); 12775 12776 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12777 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12778 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12779 SVOp->getMaskElt(j) >= 0) 12780 return false; 12781 12782 return true; 12783} 12784 12785/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12786/// same as extracting the low 128-bit part of 256-bit vector and then 12787/// inserting the result into the high part of a new 256-bit vector 12788static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12789 EVT VT = SVOp->getValueType(0); 12790 int NumElems = VT.getVectorNumElements(); 12791 12792 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12793 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12794 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12795 SVOp->getMaskElt(j) >= 0) 12796 return false; 12797 12798 return true; 12799} 12800 12801/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12802static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12803 TargetLowering::DAGCombinerInfo &DCI) { 12804 DebugLoc dl = N->getDebugLoc(); 12805 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12806 SDValue V1 = SVOp->getOperand(0); 12807 SDValue V2 = SVOp->getOperand(1); 12808 EVT VT = SVOp->getValueType(0); 12809 int NumElems = VT.getVectorNumElements(); 12810 12811 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12812 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12813 // 12814 // 0,0,0,... 12815 // | 12816 // V UNDEF BUILD_VECTOR UNDEF 12817 // \ / \ / 12818 // CONCAT_VECTOR CONCAT_VECTOR 12819 // \ / 12820 // \ / 12821 // RESULT: V + zero extended 12822 // 12823 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12824 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12825 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12826 return SDValue(); 12827 12828 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12829 return SDValue(); 12830 12831 // To match the shuffle mask, the first half of the mask should 12832 // be exactly the first vector, and all the rest a splat with the 12833 // first element of the second one. 12834 for (int i = 0; i < NumElems/2; ++i) 12835 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12836 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12837 return SDValue(); 12838 12839 // Emit a zeroed vector and insert the desired subvector on its 12840 // first half. 12841 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 12842 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12843 DAG.getConstant(0, MVT::i32), DAG, dl); 12844 return DCI.CombineTo(N, InsV); 12845 } 12846 12847 //===--------------------------------------------------------------------===// 12848 // Combine some shuffles into subvector extracts and inserts: 12849 // 12850 12851 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12852 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12853 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12854 DAG, dl); 12855 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12856 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12857 return DCI.CombineTo(N, InsV); 12858 } 12859 12860 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12861 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12862 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12863 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12864 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12865 return DCI.CombineTo(N, InsV); 12866 } 12867 12868 return SDValue(); 12869} 12870 12871/// PerformShuffleCombine - Performs several different shuffle combines. 12872static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12873 TargetLowering::DAGCombinerInfo &DCI, 12874 const X86Subtarget *Subtarget) { 12875 DebugLoc dl = N->getDebugLoc(); 12876 EVT VT = N->getValueType(0); 12877 12878 // Don't create instructions with illegal types after legalize types has run. 12879 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12880 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12881 return SDValue(); 12882 12883 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12884 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12885 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12886 return PerformShuffleCombine256(N, DAG, DCI); 12887 12888 // Only handle 128 wide vector from here on. 12889 if (VT.getSizeInBits() != 128) 12890 return SDValue(); 12891 12892 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12893 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12894 // consecutive, non-overlapping, and in the right order. 12895 SmallVector<SDValue, 16> Elts; 12896 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12897 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12898 12899 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12900} 12901 12902/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12903/// generation and convert it from being a bunch of shuffles and extracts 12904/// to a simple store and scalar loads to extract the elements. 12905static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12906 const TargetLowering &TLI) { 12907 SDValue InputVector = N->getOperand(0); 12908 12909 // Only operate on vectors of 4 elements, where the alternative shuffling 12910 // gets to be more expensive. 12911 if (InputVector.getValueType() != MVT::v4i32) 12912 return SDValue(); 12913 12914 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12915 // single use which is a sign-extend or zero-extend, and all elements are 12916 // used. 12917 SmallVector<SDNode *, 4> Uses; 12918 unsigned ExtractedElements = 0; 12919 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12920 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12921 if (UI.getUse().getResNo() != InputVector.getResNo()) 12922 return SDValue(); 12923 12924 SDNode *Extract = *UI; 12925 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12926 return SDValue(); 12927 12928 if (Extract->getValueType(0) != MVT::i32) 12929 return SDValue(); 12930 if (!Extract->hasOneUse()) 12931 return SDValue(); 12932 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12933 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12934 return SDValue(); 12935 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12936 return SDValue(); 12937 12938 // Record which element was extracted. 12939 ExtractedElements |= 12940 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12941 12942 Uses.push_back(Extract); 12943 } 12944 12945 // If not all the elements were used, this may not be worthwhile. 12946 if (ExtractedElements != 15) 12947 return SDValue(); 12948 12949 // Ok, we've now decided to do the transformation. 12950 DebugLoc dl = InputVector.getDebugLoc(); 12951 12952 // Store the value to a temporary stack slot. 12953 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12954 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12955 MachinePointerInfo(), false, false, 0); 12956 12957 // Replace each use (extract) with a load of the appropriate element. 12958 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12959 UE = Uses.end(); UI != UE; ++UI) { 12960 SDNode *Extract = *UI; 12961 12962 // cOMpute the element's address. 12963 SDValue Idx = Extract->getOperand(1); 12964 unsigned EltSize = 12965 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12966 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12967 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12968 12969 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12970 StackPtr, OffsetVal); 12971 12972 // Load the scalar. 12973 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12974 ScalarAddr, MachinePointerInfo(), 12975 false, false, false, 0); 12976 12977 // Replace the exact with the load. 12978 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12979 } 12980 12981 // The replacement was made in place; don't return anything. 12982 return SDValue(); 12983} 12984 12985/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12986/// nodes. 12987static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12988 const X86Subtarget *Subtarget) { 12989 DebugLoc DL = N->getDebugLoc(); 12990 SDValue Cond = N->getOperand(0); 12991 // Get the LHS/RHS of the select. 12992 SDValue LHS = N->getOperand(1); 12993 SDValue RHS = N->getOperand(2); 12994 EVT VT = LHS.getValueType(); 12995 12996 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12997 // instructions match the semantics of the common C idiom x<y?x:y but not 12998 // x<=y?x:y, because of how they handle negative zero (which can be 12999 // ignored in unsafe-math mode). 13000 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13001 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13002 (Subtarget->hasXMMInt() || 13003 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13004 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13005 13006 unsigned Opcode = 0; 13007 // Check for x CC y ? x : y. 13008 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13009 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13010 switch (CC) { 13011 default: break; 13012 case ISD::SETULT: 13013 // Converting this to a min would handle NaNs incorrectly, and swapping 13014 // the operands would cause it to handle comparisons between positive 13015 // and negative zero incorrectly. 13016 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13017 if (!UnsafeFPMath && 13018 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13019 break; 13020 std::swap(LHS, RHS); 13021 } 13022 Opcode = X86ISD::FMIN; 13023 break; 13024 case ISD::SETOLE: 13025 // Converting this to a min would handle comparisons between positive 13026 // and negative zero incorrectly. 13027 if (!UnsafeFPMath && 13028 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13029 break; 13030 Opcode = X86ISD::FMIN; 13031 break; 13032 case ISD::SETULE: 13033 // Converting this to a min would handle both negative zeros and NaNs 13034 // incorrectly, but we can swap the operands to fix both. 13035 std::swap(LHS, RHS); 13036 case ISD::SETOLT: 13037 case ISD::SETLT: 13038 case ISD::SETLE: 13039 Opcode = X86ISD::FMIN; 13040 break; 13041 13042 case ISD::SETOGE: 13043 // Converting this to a max would handle comparisons between positive 13044 // and negative zero incorrectly. 13045 if (!UnsafeFPMath && 13046 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13047 break; 13048 Opcode = X86ISD::FMAX; 13049 break; 13050 case ISD::SETUGT: 13051 // Converting this to a max would handle NaNs incorrectly, and swapping 13052 // the operands would cause it to handle comparisons between positive 13053 // and negative zero incorrectly. 13054 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13055 if (!UnsafeFPMath && 13056 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13057 break; 13058 std::swap(LHS, RHS); 13059 } 13060 Opcode = X86ISD::FMAX; 13061 break; 13062 case ISD::SETUGE: 13063 // Converting this to a max would handle both negative zeros and NaNs 13064 // incorrectly, but we can swap the operands to fix both. 13065 std::swap(LHS, RHS); 13066 case ISD::SETOGT: 13067 case ISD::SETGT: 13068 case ISD::SETGE: 13069 Opcode = X86ISD::FMAX; 13070 break; 13071 } 13072 // Check for x CC y ? y : x -- a min/max with reversed arms. 13073 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13074 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13075 switch (CC) { 13076 default: break; 13077 case ISD::SETOGE: 13078 // Converting this to a min would handle comparisons between positive 13079 // and negative zero incorrectly, and swapping the operands would 13080 // cause it to handle NaNs incorrectly. 13081 if (!UnsafeFPMath && 13082 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13083 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13084 break; 13085 std::swap(LHS, RHS); 13086 } 13087 Opcode = X86ISD::FMIN; 13088 break; 13089 case ISD::SETUGT: 13090 // Converting this to a min would handle NaNs incorrectly. 13091 if (!UnsafeFPMath && 13092 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13093 break; 13094 Opcode = X86ISD::FMIN; 13095 break; 13096 case ISD::SETUGE: 13097 // Converting this to a min would handle both negative zeros and NaNs 13098 // incorrectly, but we can swap the operands to fix both. 13099 std::swap(LHS, RHS); 13100 case ISD::SETOGT: 13101 case ISD::SETGT: 13102 case ISD::SETGE: 13103 Opcode = X86ISD::FMIN; 13104 break; 13105 13106 case ISD::SETULT: 13107 // Converting this to a max would handle NaNs incorrectly. 13108 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13109 break; 13110 Opcode = X86ISD::FMAX; 13111 break; 13112 case ISD::SETOLE: 13113 // Converting this to a max would handle comparisons between positive 13114 // and negative zero incorrectly, and swapping the operands would 13115 // cause it to handle NaNs incorrectly. 13116 if (!UnsafeFPMath && 13117 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13118 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13119 break; 13120 std::swap(LHS, RHS); 13121 } 13122 Opcode = X86ISD::FMAX; 13123 break; 13124 case ISD::SETULE: 13125 // Converting this to a max would handle both negative zeros and NaNs 13126 // incorrectly, but we can swap the operands to fix both. 13127 std::swap(LHS, RHS); 13128 case ISD::SETOLT: 13129 case ISD::SETLT: 13130 case ISD::SETLE: 13131 Opcode = X86ISD::FMAX; 13132 break; 13133 } 13134 } 13135 13136 if (Opcode) 13137 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13138 } 13139 13140 // If this is a select between two integer constants, try to do some 13141 // optimizations. 13142 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13143 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13144 // Don't do this for crazy integer types. 13145 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13146 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13147 // so that TrueC (the true value) is larger than FalseC. 13148 bool NeedsCondInvert = false; 13149 13150 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13151 // Efficiently invertible. 13152 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13153 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13154 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13155 NeedsCondInvert = true; 13156 std::swap(TrueC, FalseC); 13157 } 13158 13159 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13160 if (FalseC->getAPIntValue() == 0 && 13161 TrueC->getAPIntValue().isPowerOf2()) { 13162 if (NeedsCondInvert) // Invert the condition if needed. 13163 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13164 DAG.getConstant(1, Cond.getValueType())); 13165 13166 // Zero extend the condition if needed. 13167 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13168 13169 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13170 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13171 DAG.getConstant(ShAmt, MVT::i8)); 13172 } 13173 13174 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13175 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13176 if (NeedsCondInvert) // Invert the condition if needed. 13177 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13178 DAG.getConstant(1, Cond.getValueType())); 13179 13180 // Zero extend the condition if needed. 13181 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13182 FalseC->getValueType(0), Cond); 13183 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13184 SDValue(FalseC, 0)); 13185 } 13186 13187 // Optimize cases that will turn into an LEA instruction. This requires 13188 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13189 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13190 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13191 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13192 13193 bool isFastMultiplier = false; 13194 if (Diff < 10) { 13195 switch ((unsigned char)Diff) { 13196 default: break; 13197 case 1: // result = add base, cond 13198 case 2: // result = lea base( , cond*2) 13199 case 3: // result = lea base(cond, cond*2) 13200 case 4: // result = lea base( , cond*4) 13201 case 5: // result = lea base(cond, cond*4) 13202 case 8: // result = lea base( , cond*8) 13203 case 9: // result = lea base(cond, cond*8) 13204 isFastMultiplier = true; 13205 break; 13206 } 13207 } 13208 13209 if (isFastMultiplier) { 13210 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13211 if (NeedsCondInvert) // Invert the condition if needed. 13212 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13213 DAG.getConstant(1, Cond.getValueType())); 13214 13215 // Zero extend the condition if needed. 13216 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13217 Cond); 13218 // Scale the condition by the difference. 13219 if (Diff != 1) 13220 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13221 DAG.getConstant(Diff, Cond.getValueType())); 13222 13223 // Add the base if non-zero. 13224 if (FalseC->getAPIntValue() != 0) 13225 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13226 SDValue(FalseC, 0)); 13227 return Cond; 13228 } 13229 } 13230 } 13231 } 13232 13233 return SDValue(); 13234} 13235 13236/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13237static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13238 TargetLowering::DAGCombinerInfo &DCI) { 13239 DebugLoc DL = N->getDebugLoc(); 13240 13241 // If the flag operand isn't dead, don't touch this CMOV. 13242 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13243 return SDValue(); 13244 13245 SDValue FalseOp = N->getOperand(0); 13246 SDValue TrueOp = N->getOperand(1); 13247 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13248 SDValue Cond = N->getOperand(3); 13249 if (CC == X86::COND_E || CC == X86::COND_NE) { 13250 switch (Cond.getOpcode()) { 13251 default: break; 13252 case X86ISD::BSR: 13253 case X86ISD::BSF: 13254 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13255 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13256 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13257 } 13258 } 13259 13260 // If this is a select between two integer constants, try to do some 13261 // optimizations. Note that the operands are ordered the opposite of SELECT 13262 // operands. 13263 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13264 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13265 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13266 // larger than FalseC (the false value). 13267 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13268 CC = X86::GetOppositeBranchCondition(CC); 13269 std::swap(TrueC, FalseC); 13270 } 13271 13272 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13273 // This is efficient for any integer data type (including i8/i16) and 13274 // shift amount. 13275 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13276 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13277 DAG.getConstant(CC, MVT::i8), Cond); 13278 13279 // Zero extend the condition if needed. 13280 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13281 13282 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13283 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13284 DAG.getConstant(ShAmt, MVT::i8)); 13285 if (N->getNumValues() == 2) // Dead flag value? 13286 return DCI.CombineTo(N, Cond, SDValue()); 13287 return Cond; 13288 } 13289 13290 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13291 // for any integer data type, including i8/i16. 13292 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13293 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13294 DAG.getConstant(CC, MVT::i8), Cond); 13295 13296 // Zero extend the condition if needed. 13297 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13298 FalseC->getValueType(0), Cond); 13299 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13300 SDValue(FalseC, 0)); 13301 13302 if (N->getNumValues() == 2) // Dead flag value? 13303 return DCI.CombineTo(N, Cond, SDValue()); 13304 return Cond; 13305 } 13306 13307 // Optimize cases that will turn into an LEA instruction. This requires 13308 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13309 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13310 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13311 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13312 13313 bool isFastMultiplier = false; 13314 if (Diff < 10) { 13315 switch ((unsigned char)Diff) { 13316 default: break; 13317 case 1: // result = add base, cond 13318 case 2: // result = lea base( , cond*2) 13319 case 3: // result = lea base(cond, cond*2) 13320 case 4: // result = lea base( , cond*4) 13321 case 5: // result = lea base(cond, cond*4) 13322 case 8: // result = lea base( , cond*8) 13323 case 9: // result = lea base(cond, cond*8) 13324 isFastMultiplier = true; 13325 break; 13326 } 13327 } 13328 13329 if (isFastMultiplier) { 13330 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13331 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13332 DAG.getConstant(CC, MVT::i8), Cond); 13333 // Zero extend the condition if needed. 13334 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13335 Cond); 13336 // Scale the condition by the difference. 13337 if (Diff != 1) 13338 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13339 DAG.getConstant(Diff, Cond.getValueType())); 13340 13341 // Add the base if non-zero. 13342 if (FalseC->getAPIntValue() != 0) 13343 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13344 SDValue(FalseC, 0)); 13345 if (N->getNumValues() == 2) // Dead flag value? 13346 return DCI.CombineTo(N, Cond, SDValue()); 13347 return Cond; 13348 } 13349 } 13350 } 13351 } 13352 return SDValue(); 13353} 13354 13355 13356/// PerformMulCombine - Optimize a single multiply with constant into two 13357/// in order to implement it with two cheaper instructions, e.g. 13358/// LEA + SHL, LEA + LEA. 13359static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13360 TargetLowering::DAGCombinerInfo &DCI) { 13361 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13362 return SDValue(); 13363 13364 EVT VT = N->getValueType(0); 13365 if (VT != MVT::i64) 13366 return SDValue(); 13367 13368 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13369 if (!C) 13370 return SDValue(); 13371 uint64_t MulAmt = C->getZExtValue(); 13372 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13373 return SDValue(); 13374 13375 uint64_t MulAmt1 = 0; 13376 uint64_t MulAmt2 = 0; 13377 if ((MulAmt % 9) == 0) { 13378 MulAmt1 = 9; 13379 MulAmt2 = MulAmt / 9; 13380 } else if ((MulAmt % 5) == 0) { 13381 MulAmt1 = 5; 13382 MulAmt2 = MulAmt / 5; 13383 } else if ((MulAmt % 3) == 0) { 13384 MulAmt1 = 3; 13385 MulAmt2 = MulAmt / 3; 13386 } 13387 if (MulAmt2 && 13388 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13389 DebugLoc DL = N->getDebugLoc(); 13390 13391 if (isPowerOf2_64(MulAmt2) && 13392 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13393 // If second multiplifer is pow2, issue it first. We want the multiply by 13394 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13395 // is an add. 13396 std::swap(MulAmt1, MulAmt2); 13397 13398 SDValue NewMul; 13399 if (isPowerOf2_64(MulAmt1)) 13400 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13401 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13402 else 13403 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13404 DAG.getConstant(MulAmt1, VT)); 13405 13406 if (isPowerOf2_64(MulAmt2)) 13407 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13408 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13409 else 13410 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13411 DAG.getConstant(MulAmt2, VT)); 13412 13413 // Do not add new nodes to DAG combiner worklist. 13414 DCI.CombineTo(N, NewMul, false); 13415 } 13416 return SDValue(); 13417} 13418 13419static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13420 SDValue N0 = N->getOperand(0); 13421 SDValue N1 = N->getOperand(1); 13422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13423 EVT VT = N0.getValueType(); 13424 13425 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13426 // since the result of setcc_c is all zero's or all ones. 13427 if (VT.isInteger() && !VT.isVector() && 13428 N1C && N0.getOpcode() == ISD::AND && 13429 N0.getOperand(1).getOpcode() == ISD::Constant) { 13430 SDValue N00 = N0.getOperand(0); 13431 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13432 ((N00.getOpcode() == ISD::ANY_EXTEND || 13433 N00.getOpcode() == ISD::ZERO_EXTEND) && 13434 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13435 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13436 APInt ShAmt = N1C->getAPIntValue(); 13437 Mask = Mask.shl(ShAmt); 13438 if (Mask != 0) 13439 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13440 N00, DAG.getConstant(Mask, VT)); 13441 } 13442 } 13443 13444 13445 // Hardware support for vector shifts is sparse which makes us scalarize the 13446 // vector operations in many cases. Also, on sandybridge ADD is faster than 13447 // shl. 13448 // (shl V, 1) -> add V,V 13449 if (isSplatVector(N1.getNode())) { 13450 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13452 // We shift all of the values by one. In many cases we do not have 13453 // hardware support for this operation. This is better expressed as an ADD 13454 // of two values. 13455 if (N1C && (1 == N1C->getZExtValue())) { 13456 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13457 } 13458 } 13459 13460 return SDValue(); 13461} 13462 13463/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13464/// when possible. 13465static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13466 const X86Subtarget *Subtarget) { 13467 EVT VT = N->getValueType(0); 13468 if (N->getOpcode() == ISD::SHL) { 13469 SDValue V = PerformSHLCombine(N, DAG); 13470 if (V.getNode()) return V; 13471 } 13472 13473 // On X86 with SSE2 support, we can transform this to a vector shift if 13474 // all elements are shifted by the same amount. We can't do this in legalize 13475 // because the a constant vector is typically transformed to a constant pool 13476 // so we have no knowledge of the shift amount. 13477 if (!Subtarget->hasXMMInt()) 13478 return SDValue(); 13479 13480 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13481 (!Subtarget->hasAVX2() || 13482 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13483 return SDValue(); 13484 13485 SDValue ShAmtOp = N->getOperand(1); 13486 EVT EltVT = VT.getVectorElementType(); 13487 DebugLoc DL = N->getDebugLoc(); 13488 SDValue BaseShAmt = SDValue(); 13489 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13490 unsigned NumElts = VT.getVectorNumElements(); 13491 unsigned i = 0; 13492 for (; i != NumElts; ++i) { 13493 SDValue Arg = ShAmtOp.getOperand(i); 13494 if (Arg.getOpcode() == ISD::UNDEF) continue; 13495 BaseShAmt = Arg; 13496 break; 13497 } 13498 for (; i != NumElts; ++i) { 13499 SDValue Arg = ShAmtOp.getOperand(i); 13500 if (Arg.getOpcode() == ISD::UNDEF) continue; 13501 if (Arg != BaseShAmt) { 13502 return SDValue(); 13503 } 13504 } 13505 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13506 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13507 SDValue InVec = ShAmtOp.getOperand(0); 13508 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13509 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13510 unsigned i = 0; 13511 for (; i != NumElts; ++i) { 13512 SDValue Arg = InVec.getOperand(i); 13513 if (Arg.getOpcode() == ISD::UNDEF) continue; 13514 BaseShAmt = Arg; 13515 break; 13516 } 13517 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13518 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13519 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13520 if (C->getZExtValue() == SplatIdx) 13521 BaseShAmt = InVec.getOperand(1); 13522 } 13523 } 13524 if (BaseShAmt.getNode() == 0) 13525 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13526 DAG.getIntPtrConstant(0)); 13527 } else 13528 return SDValue(); 13529 13530 // The shift amount is an i32. 13531 if (EltVT.bitsGT(MVT::i32)) 13532 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13533 else if (EltVT.bitsLT(MVT::i32)) 13534 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13535 13536 // The shift amount is identical so we can do a vector shift. 13537 SDValue ValOp = N->getOperand(0); 13538 switch (N->getOpcode()) { 13539 default: 13540 llvm_unreachable("Unknown shift opcode!"); 13541 break; 13542 case ISD::SHL: 13543 if (VT == MVT::v2i64) 13544 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13545 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13546 ValOp, BaseShAmt); 13547 if (VT == MVT::v4i32) 13548 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13549 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13550 ValOp, BaseShAmt); 13551 if (VT == MVT::v8i16) 13552 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13553 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13554 ValOp, BaseShAmt); 13555 if (VT == MVT::v4i64) 13556 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13557 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 13558 ValOp, BaseShAmt); 13559 if (VT == MVT::v8i32) 13560 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13561 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32), 13562 ValOp, BaseShAmt); 13563 if (VT == MVT::v16i16) 13564 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13565 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32), 13566 ValOp, BaseShAmt); 13567 break; 13568 case ISD::SRA: 13569 if (VT == MVT::v4i32) 13570 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13571 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13572 ValOp, BaseShAmt); 13573 if (VT == MVT::v8i16) 13574 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13575 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13576 ValOp, BaseShAmt); 13577 if (VT == MVT::v8i32) 13578 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13579 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32), 13580 ValOp, BaseShAmt); 13581 if (VT == MVT::v16i16) 13582 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13583 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32), 13584 ValOp, BaseShAmt); 13585 break; 13586 case ISD::SRL: 13587 if (VT == MVT::v2i64) 13588 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13589 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13590 ValOp, BaseShAmt); 13591 if (VT == MVT::v4i32) 13592 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13593 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13594 ValOp, BaseShAmt); 13595 if (VT == MVT::v8i16) 13596 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13597 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13598 ValOp, BaseShAmt); 13599 if (VT == MVT::v4i64) 13600 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13601 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 13602 ValOp, BaseShAmt); 13603 if (VT == MVT::v8i32) 13604 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13605 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32), 13606 ValOp, BaseShAmt); 13607 if (VT == MVT::v16i16) 13608 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13609 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32), 13610 ValOp, BaseShAmt); 13611 break; 13612 } 13613 return SDValue(); 13614} 13615 13616 13617// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13618// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13619// and friends. Likewise for OR -> CMPNEQSS. 13620static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13621 TargetLowering::DAGCombinerInfo &DCI, 13622 const X86Subtarget *Subtarget) { 13623 unsigned opcode; 13624 13625 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13626 // we're requiring SSE2 for both. 13627 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13628 SDValue N0 = N->getOperand(0); 13629 SDValue N1 = N->getOperand(1); 13630 SDValue CMP0 = N0->getOperand(1); 13631 SDValue CMP1 = N1->getOperand(1); 13632 DebugLoc DL = N->getDebugLoc(); 13633 13634 // The SETCCs should both refer to the same CMP. 13635 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13636 return SDValue(); 13637 13638 SDValue CMP00 = CMP0->getOperand(0); 13639 SDValue CMP01 = CMP0->getOperand(1); 13640 EVT VT = CMP00.getValueType(); 13641 13642 if (VT == MVT::f32 || VT == MVT::f64) { 13643 bool ExpectingFlags = false; 13644 // Check for any users that want flags: 13645 for (SDNode::use_iterator UI = N->use_begin(), 13646 UE = N->use_end(); 13647 !ExpectingFlags && UI != UE; ++UI) 13648 switch (UI->getOpcode()) { 13649 default: 13650 case ISD::BR_CC: 13651 case ISD::BRCOND: 13652 case ISD::SELECT: 13653 ExpectingFlags = true; 13654 break; 13655 case ISD::CopyToReg: 13656 case ISD::SIGN_EXTEND: 13657 case ISD::ZERO_EXTEND: 13658 case ISD::ANY_EXTEND: 13659 break; 13660 } 13661 13662 if (!ExpectingFlags) { 13663 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13664 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13665 13666 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13667 X86::CondCode tmp = cc0; 13668 cc0 = cc1; 13669 cc1 = tmp; 13670 } 13671 13672 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13673 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13674 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13675 X86ISD::NodeType NTOperator = is64BitFP ? 13676 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13677 // FIXME: need symbolic constants for these magic numbers. 13678 // See X86ATTInstPrinter.cpp:printSSECC(). 13679 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13680 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13681 DAG.getConstant(x86cc, MVT::i8)); 13682 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13683 OnesOrZeroesF); 13684 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13685 DAG.getConstant(1, MVT::i32)); 13686 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13687 return OneBitOfTruth; 13688 } 13689 } 13690 } 13691 } 13692 return SDValue(); 13693} 13694 13695/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13696/// so it can be folded inside ANDNP. 13697static bool CanFoldXORWithAllOnes(const SDNode *N) { 13698 EVT VT = N->getValueType(0); 13699 13700 // Match direct AllOnes for 128 and 256-bit vectors 13701 if (ISD::isBuildVectorAllOnes(N)) 13702 return true; 13703 13704 // Look through a bit convert. 13705 if (N->getOpcode() == ISD::BITCAST) 13706 N = N->getOperand(0).getNode(); 13707 13708 // Sometimes the operand may come from a insert_subvector building a 256-bit 13709 // allones vector 13710 if (VT.getSizeInBits() == 256 && 13711 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13712 SDValue V1 = N->getOperand(0); 13713 SDValue V2 = N->getOperand(1); 13714 13715 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13716 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13717 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13718 ISD::isBuildVectorAllOnes(V2.getNode())) 13719 return true; 13720 } 13721 13722 return false; 13723} 13724 13725static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13726 TargetLowering::DAGCombinerInfo &DCI, 13727 const X86Subtarget *Subtarget) { 13728 if (DCI.isBeforeLegalizeOps()) 13729 return SDValue(); 13730 13731 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13732 if (R.getNode()) 13733 return R; 13734 13735 EVT VT = N->getValueType(0); 13736 13737 // Create ANDN, BLSI, and BLSR instructions 13738 // BLSI is X & (-X) 13739 // BLSR is X & (X-1) 13740 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13741 SDValue N0 = N->getOperand(0); 13742 SDValue N1 = N->getOperand(1); 13743 DebugLoc DL = N->getDebugLoc(); 13744 13745 // Check LHS for not 13746 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13747 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13748 // Check RHS for not 13749 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13750 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13751 13752 // Check LHS for neg 13753 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13754 isZero(N0.getOperand(0))) 13755 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13756 13757 // Check RHS for neg 13758 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13759 isZero(N1.getOperand(0))) 13760 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13761 13762 // Check LHS for X-1 13763 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13764 isAllOnes(N0.getOperand(1))) 13765 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13766 13767 // Check RHS for X-1 13768 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13769 isAllOnes(N1.getOperand(1))) 13770 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13771 13772 return SDValue(); 13773 } 13774 13775 // Want to form ANDNP nodes: 13776 // 1) In the hopes of then easily combining them with OR and AND nodes 13777 // to form PBLEND/PSIGN. 13778 // 2) To match ANDN packed intrinsics 13779 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13780 return SDValue(); 13781 13782 SDValue N0 = N->getOperand(0); 13783 SDValue N1 = N->getOperand(1); 13784 DebugLoc DL = N->getDebugLoc(); 13785 13786 // Check LHS for vnot 13787 if (N0.getOpcode() == ISD::XOR && 13788 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13789 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13790 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13791 13792 // Check RHS for vnot 13793 if (N1.getOpcode() == ISD::XOR && 13794 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13795 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13796 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13797 13798 return SDValue(); 13799} 13800 13801static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13802 TargetLowering::DAGCombinerInfo &DCI, 13803 const X86Subtarget *Subtarget) { 13804 if (DCI.isBeforeLegalizeOps()) 13805 return SDValue(); 13806 13807 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13808 if (R.getNode()) 13809 return R; 13810 13811 EVT VT = N->getValueType(0); 13812 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 13813 return SDValue(); 13814 13815 SDValue N0 = N->getOperand(0); 13816 SDValue N1 = N->getOperand(1); 13817 13818 // look for psign/blend 13819 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 13820 if (VT == MVT::v2i64) { 13821 // Canonicalize pandn to RHS 13822 if (N0.getOpcode() == X86ISD::ANDNP) 13823 std::swap(N0, N1); 13824 // or (and (m, x), (pandn m, y)) 13825 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13826 SDValue Mask = N1.getOperand(0); 13827 SDValue X = N1.getOperand(1); 13828 SDValue Y; 13829 if (N0.getOperand(0) == Mask) 13830 Y = N0.getOperand(1); 13831 if (N0.getOperand(1) == Mask) 13832 Y = N0.getOperand(0); 13833 13834 // Check to see if the mask appeared in both the AND and ANDNP and 13835 if (!Y.getNode()) 13836 return SDValue(); 13837 13838 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13839 if (Mask.getOpcode() != ISD::BITCAST || 13840 X.getOpcode() != ISD::BITCAST || 13841 Y.getOpcode() != ISD::BITCAST) 13842 return SDValue(); 13843 13844 // Look through mask bitcast. 13845 Mask = Mask.getOperand(0); 13846 EVT MaskVT = Mask.getValueType(); 13847 13848 // Validate that the Mask operand is a vector sra node. The sra node 13849 // will be an intrinsic. 13850 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13851 return SDValue(); 13852 13853 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13854 // there is no psrai.b 13855 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13856 case Intrinsic::x86_sse2_psrai_w: 13857 case Intrinsic::x86_sse2_psrai_d: 13858 break; 13859 default: return SDValue(); 13860 } 13861 13862 // Check that the SRA is all signbits. 13863 SDValue SraC = Mask.getOperand(2); 13864 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13865 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13866 if ((SraAmt + 1) != EltBits) 13867 return SDValue(); 13868 13869 DebugLoc DL = N->getDebugLoc(); 13870 13871 // Now we know we at least have a plendvb with the mask val. See if 13872 // we can form a psignb/w/d. 13873 // psign = x.type == y.type == mask.type && y = sub(0, x); 13874 X = X.getOperand(0); 13875 Y = Y.getOperand(0); 13876 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13877 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13878 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 13879 unsigned Opc = 0; 13880 switch (EltBits) { 13881 case 8: Opc = X86ISD::PSIGNB; break; 13882 case 16: Opc = X86ISD::PSIGNW; break; 13883 case 32: Opc = X86ISD::PSIGND; break; 13884 default: break; 13885 } 13886 if (Opc) { 13887 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 13888 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 13889 } 13890 } 13891 // PBLENDVB only available on SSE 4.1 13892 if (!(Subtarget->hasSSE41() || Subtarget->hasAVX())) 13893 return SDValue(); 13894 13895 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 13896 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 13897 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 13898 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y); 13899 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 13900 } 13901 } 13902 } 13903 13904 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13905 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13906 std::swap(N0, N1); 13907 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13908 return SDValue(); 13909 if (!N0.hasOneUse() || !N1.hasOneUse()) 13910 return SDValue(); 13911 13912 SDValue ShAmt0 = N0.getOperand(1); 13913 if (ShAmt0.getValueType() != MVT::i8) 13914 return SDValue(); 13915 SDValue ShAmt1 = N1.getOperand(1); 13916 if (ShAmt1.getValueType() != MVT::i8) 13917 return SDValue(); 13918 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13919 ShAmt0 = ShAmt0.getOperand(0); 13920 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13921 ShAmt1 = ShAmt1.getOperand(0); 13922 13923 DebugLoc DL = N->getDebugLoc(); 13924 unsigned Opc = X86ISD::SHLD; 13925 SDValue Op0 = N0.getOperand(0); 13926 SDValue Op1 = N1.getOperand(0); 13927 if (ShAmt0.getOpcode() == ISD::SUB) { 13928 Opc = X86ISD::SHRD; 13929 std::swap(Op0, Op1); 13930 std::swap(ShAmt0, ShAmt1); 13931 } 13932 13933 unsigned Bits = VT.getSizeInBits(); 13934 if (ShAmt1.getOpcode() == ISD::SUB) { 13935 SDValue Sum = ShAmt1.getOperand(0); 13936 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13937 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13938 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13939 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13940 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13941 return DAG.getNode(Opc, DL, VT, 13942 Op0, Op1, 13943 DAG.getNode(ISD::TRUNCATE, DL, 13944 MVT::i8, ShAmt0)); 13945 } 13946 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13947 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13948 if (ShAmt0C && 13949 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13950 return DAG.getNode(Opc, DL, VT, 13951 N0.getOperand(0), N1.getOperand(0), 13952 DAG.getNode(ISD::TRUNCATE, DL, 13953 MVT::i8, ShAmt0)); 13954 } 13955 13956 return SDValue(); 13957} 13958 13959static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 13960 TargetLowering::DAGCombinerInfo &DCI, 13961 const X86Subtarget *Subtarget) { 13962 if (DCI.isBeforeLegalizeOps()) 13963 return SDValue(); 13964 13965 EVT VT = N->getValueType(0); 13966 13967 if (VT != MVT::i32 && VT != MVT::i64) 13968 return SDValue(); 13969 13970 // Create BLSMSK instructions by finding X ^ (X-1) 13971 SDValue N0 = N->getOperand(0); 13972 SDValue N1 = N->getOperand(1); 13973 DebugLoc DL = N->getDebugLoc(); 13974 13975 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13976 isAllOnes(N0.getOperand(1))) 13977 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 13978 13979 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13980 isAllOnes(N1.getOperand(1))) 13981 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 13982 13983 return SDValue(); 13984} 13985 13986/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13987static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13988 const X86Subtarget *Subtarget) { 13989 LoadSDNode *Ld = cast<LoadSDNode>(N); 13990 EVT RegVT = Ld->getValueType(0); 13991 EVT MemVT = Ld->getMemoryVT(); 13992 DebugLoc dl = Ld->getDebugLoc(); 13993 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13994 13995 ISD::LoadExtType Ext = Ld->getExtensionType(); 13996 13997 // If this is a vector EXT Load then attempt to optimize it using a 13998 // shuffle. We need SSE4 for the shuffles. 13999 // TODO: It is possible to support ZExt by zeroing the undef values 14000 // during the shuffle phase or after the shuffle. 14001 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14002 assert(MemVT != RegVT && "Cannot extend to the same type"); 14003 assert(MemVT.isVector() && "Must load a vector from memory"); 14004 14005 unsigned NumElems = RegVT.getVectorNumElements(); 14006 unsigned RegSz = RegVT.getSizeInBits(); 14007 unsigned MemSz = MemVT.getSizeInBits(); 14008 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14009 // All sizes must be a power of two 14010 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14011 14012 // Attempt to load the original value using a single load op. 14013 // Find a scalar type which is equal to the loaded word size. 14014 MVT SclrLoadTy = MVT::i8; 14015 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14016 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14017 MVT Tp = (MVT::SimpleValueType)tp; 14018 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14019 SclrLoadTy = Tp; 14020 break; 14021 } 14022 } 14023 14024 // Proceed if a load word is found. 14025 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14026 14027 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14028 RegSz/SclrLoadTy.getSizeInBits()); 14029 14030 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14031 RegSz/MemVT.getScalarType().getSizeInBits()); 14032 // Can't shuffle using an illegal type. 14033 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14034 14035 // Perform a single load. 14036 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14037 Ld->getBasePtr(), 14038 Ld->getPointerInfo(), Ld->isVolatile(), 14039 Ld->isNonTemporal(), Ld->isInvariant(), 14040 Ld->getAlignment()); 14041 14042 // Insert the word loaded into a vector. 14043 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14044 LoadUnitVecVT, ScalarLoad); 14045 14046 // Bitcast the loaded value to a vector of the original element type, in 14047 // the size of the target vector type. 14048 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector); 14049 unsigned SizeRatio = RegSz/MemSz; 14050 14051 // Redistribute the loaded elements into the different locations. 14052 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14053 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14054 14055 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14056 DAG.getUNDEF(SlicedVec.getValueType()), 14057 ShuffleVec.data()); 14058 14059 // Bitcast to the requested type. 14060 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14061 // Replace the original load with the new sequence 14062 // and return the new chain. 14063 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14064 return SDValue(ScalarLoad.getNode(), 1); 14065 } 14066 14067 return SDValue(); 14068} 14069 14070/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14071static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14072 const X86Subtarget *Subtarget) { 14073 StoreSDNode *St = cast<StoreSDNode>(N); 14074 EVT VT = St->getValue().getValueType(); 14075 EVT StVT = St->getMemoryVT(); 14076 DebugLoc dl = St->getDebugLoc(); 14077 SDValue StoredVal = St->getOperand(1); 14078 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14079 14080 // If we are saving a concatination of two XMM registers, perform two stores. 14081 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14082 // 128-bit ones. If in the future the cost becomes only one memory access the 14083 // first version would be better. 14084 if (VT.getSizeInBits() == 256 && 14085 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14086 StoredVal.getNumOperands() == 2) { 14087 14088 SDValue Value0 = StoredVal.getOperand(0); 14089 SDValue Value1 = StoredVal.getOperand(1); 14090 14091 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14092 SDValue Ptr0 = St->getBasePtr(); 14093 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14094 14095 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14096 St->getPointerInfo(), St->isVolatile(), 14097 St->isNonTemporal(), St->getAlignment()); 14098 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14099 St->getPointerInfo(), St->isVolatile(), 14100 St->isNonTemporal(), St->getAlignment()); 14101 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14102 } 14103 14104 // Optimize trunc store (of multiple scalars) to shuffle and store. 14105 // First, pack all of the elements in one place. Next, store to memory 14106 // in fewer chunks. 14107 if (St->isTruncatingStore() && VT.isVector()) { 14108 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14109 unsigned NumElems = VT.getVectorNumElements(); 14110 assert(StVT != VT && "Cannot truncate to the same type"); 14111 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14112 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14113 14114 // From, To sizes and ElemCount must be pow of two 14115 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14116 // We are going to use the original vector elt for storing. 14117 // Accumulated smaller vector elements must be a multiple of the store size. 14118 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14119 14120 unsigned SizeRatio = FromSz / ToSz; 14121 14122 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14123 14124 // Create a type on which we perform the shuffle 14125 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14126 StVT.getScalarType(), NumElems*SizeRatio); 14127 14128 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14129 14130 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14131 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14132 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14133 14134 // Can't shuffle using an illegal type 14135 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14136 14137 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14138 DAG.getUNDEF(WideVec.getValueType()), 14139 ShuffleVec.data()); 14140 // At this point all of the data is stored at the bottom of the 14141 // register. We now need to save it to mem. 14142 14143 // Find the largest store unit 14144 MVT StoreType = MVT::i8; 14145 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14146 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14147 MVT Tp = (MVT::SimpleValueType)tp; 14148 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14149 StoreType = Tp; 14150 } 14151 14152 // Bitcast the original vector into a vector of store-size units 14153 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14154 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14155 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14156 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14157 SmallVector<SDValue, 8> Chains; 14158 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14159 TLI.getPointerTy()); 14160 SDValue Ptr = St->getBasePtr(); 14161 14162 // Perform one or more big stores into memory. 14163 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14164 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14165 StoreType, ShuffWide, 14166 DAG.getIntPtrConstant(i)); 14167 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14168 St->getPointerInfo(), St->isVolatile(), 14169 St->isNonTemporal(), St->getAlignment()); 14170 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14171 Chains.push_back(Ch); 14172 } 14173 14174 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14175 Chains.size()); 14176 } 14177 14178 14179 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14180 // the FP state in cases where an emms may be missing. 14181 // A preferable solution to the general problem is to figure out the right 14182 // places to insert EMMS. This qualifies as a quick hack. 14183 14184 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14185 if (VT.getSizeInBits() != 64) 14186 return SDValue(); 14187 14188 const Function *F = DAG.getMachineFunction().getFunction(); 14189 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14190 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 14191 && Subtarget->hasXMMInt(); 14192 if ((VT.isVector() || 14193 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14194 isa<LoadSDNode>(St->getValue()) && 14195 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14196 St->getChain().hasOneUse() && !St->isVolatile()) { 14197 SDNode* LdVal = St->getValue().getNode(); 14198 LoadSDNode *Ld = 0; 14199 int TokenFactorIndex = -1; 14200 SmallVector<SDValue, 8> Ops; 14201 SDNode* ChainVal = St->getChain().getNode(); 14202 // Must be a store of a load. We currently handle two cases: the load 14203 // is a direct child, and it's under an intervening TokenFactor. It is 14204 // possible to dig deeper under nested TokenFactors. 14205 if (ChainVal == LdVal) 14206 Ld = cast<LoadSDNode>(St->getChain()); 14207 else if (St->getValue().hasOneUse() && 14208 ChainVal->getOpcode() == ISD::TokenFactor) { 14209 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 14210 if (ChainVal->getOperand(i).getNode() == LdVal) { 14211 TokenFactorIndex = i; 14212 Ld = cast<LoadSDNode>(St->getValue()); 14213 } else 14214 Ops.push_back(ChainVal->getOperand(i)); 14215 } 14216 } 14217 14218 if (!Ld || !ISD::isNormalLoad(Ld)) 14219 return SDValue(); 14220 14221 // If this is not the MMX case, i.e. we are just turning i64 load/store 14222 // into f64 load/store, avoid the transformation if there are multiple 14223 // uses of the loaded value. 14224 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14225 return SDValue(); 14226 14227 DebugLoc LdDL = Ld->getDebugLoc(); 14228 DebugLoc StDL = N->getDebugLoc(); 14229 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14230 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14231 // pair instead. 14232 if (Subtarget->is64Bit() || F64IsLegal) { 14233 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14234 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14235 Ld->getPointerInfo(), Ld->isVolatile(), 14236 Ld->isNonTemporal(), Ld->isInvariant(), 14237 Ld->getAlignment()); 14238 SDValue NewChain = NewLd.getValue(1); 14239 if (TokenFactorIndex != -1) { 14240 Ops.push_back(NewChain); 14241 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14242 Ops.size()); 14243 } 14244 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14245 St->getPointerInfo(), 14246 St->isVolatile(), St->isNonTemporal(), 14247 St->getAlignment()); 14248 } 14249 14250 // Otherwise, lower to two pairs of 32-bit loads / stores. 14251 SDValue LoAddr = Ld->getBasePtr(); 14252 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14253 DAG.getConstant(4, MVT::i32)); 14254 14255 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14256 Ld->getPointerInfo(), 14257 Ld->isVolatile(), Ld->isNonTemporal(), 14258 Ld->isInvariant(), Ld->getAlignment()); 14259 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14260 Ld->getPointerInfo().getWithOffset(4), 14261 Ld->isVolatile(), Ld->isNonTemporal(), 14262 Ld->isInvariant(), 14263 MinAlign(Ld->getAlignment(), 4)); 14264 14265 SDValue NewChain = LoLd.getValue(1); 14266 if (TokenFactorIndex != -1) { 14267 Ops.push_back(LoLd); 14268 Ops.push_back(HiLd); 14269 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14270 Ops.size()); 14271 } 14272 14273 LoAddr = St->getBasePtr(); 14274 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14275 DAG.getConstant(4, MVT::i32)); 14276 14277 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14278 St->getPointerInfo(), 14279 St->isVolatile(), St->isNonTemporal(), 14280 St->getAlignment()); 14281 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14282 St->getPointerInfo().getWithOffset(4), 14283 St->isVolatile(), 14284 St->isNonTemporal(), 14285 MinAlign(St->getAlignment(), 4)); 14286 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14287 } 14288 return SDValue(); 14289} 14290 14291/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14292/// and return the operands for the horizontal operation in LHS and RHS. A 14293/// horizontal operation performs the binary operation on successive elements 14294/// of its first operand, then on successive elements of its second operand, 14295/// returning the resulting values in a vector. For example, if 14296/// A = < float a0, float a1, float a2, float a3 > 14297/// and 14298/// B = < float b0, float b1, float b2, float b3 > 14299/// then the result of doing a horizontal operation on A and B is 14300/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14301/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14302/// A horizontal-op B, for some already available A and B, and if so then LHS is 14303/// set to A, RHS to B, and the routine returns 'true'. 14304/// Note that the binary operation should have the property that if one of the 14305/// operands is UNDEF then the result is UNDEF. 14306static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) { 14307 // Look for the following pattern: if 14308 // A = < float a0, float a1, float a2, float a3 > 14309 // B = < float b0, float b1, float b2, float b3 > 14310 // and 14311 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14312 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14313 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14314 // which is A horizontal-op B. 14315 14316 // At least one of the operands should be a vector shuffle. 14317 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14318 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14319 return false; 14320 14321 EVT VT = LHS.getValueType(); 14322 unsigned N = VT.getVectorNumElements(); 14323 14324 // View LHS in the form 14325 // LHS = VECTOR_SHUFFLE A, B, LMask 14326 // If LHS is not a shuffle then pretend it is the shuffle 14327 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14328 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14329 // type VT. 14330 SDValue A, B; 14331 SmallVector<int, 8> LMask(N); 14332 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14333 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14334 A = LHS.getOperand(0); 14335 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14336 B = LHS.getOperand(1); 14337 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask); 14338 } else { 14339 if (LHS.getOpcode() != ISD::UNDEF) 14340 A = LHS; 14341 for (unsigned i = 0; i != N; ++i) 14342 LMask[i] = i; 14343 } 14344 14345 // Likewise, view RHS in the form 14346 // RHS = VECTOR_SHUFFLE C, D, RMask 14347 SDValue C, D; 14348 SmallVector<int, 8> RMask(N); 14349 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14350 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14351 C = RHS.getOperand(0); 14352 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14353 D = RHS.getOperand(1); 14354 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask); 14355 } else { 14356 if (RHS.getOpcode() != ISD::UNDEF) 14357 C = RHS; 14358 for (unsigned i = 0; i != N; ++i) 14359 RMask[i] = i; 14360 } 14361 14362 // Check that the shuffles are both shuffling the same vectors. 14363 if (!(A == C && B == D) && !(A == D && B == C)) 14364 return false; 14365 14366 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14367 if (!A.getNode() && !B.getNode()) 14368 return false; 14369 14370 // If A and B occur in reverse order in RHS, then "swap" them (which means 14371 // rewriting the mask). 14372 if (A != C) 14373 for (unsigned i = 0; i != N; ++i) { 14374 unsigned Idx = RMask[i]; 14375 if (Idx < N) 14376 RMask[i] += N; 14377 else if (Idx < 2*N) 14378 RMask[i] -= N; 14379 } 14380 14381 // At this point LHS and RHS are equivalent to 14382 // LHS = VECTOR_SHUFFLE A, B, LMask 14383 // RHS = VECTOR_SHUFFLE A, B, RMask 14384 // Check that the masks correspond to performing a horizontal operation. 14385 for (unsigned i = 0; i != N; ++i) { 14386 unsigned LIdx = LMask[i], RIdx = RMask[i]; 14387 14388 // Ignore any UNDEF components. 14389 if (LIdx >= 2*N || RIdx >= 2*N || (!A.getNode() && (LIdx < N || RIdx < N)) 14390 || (!B.getNode() && (LIdx >= N || RIdx >= N))) 14391 continue; 14392 14393 // Check that successive elements are being operated on. If not, this is 14394 // not a horizontal operation. 14395 if (!(LIdx == 2*i && RIdx == 2*i + 1) && 14396 !(isCommutative && LIdx == 2*i + 1 && RIdx == 2*i)) 14397 return false; 14398 } 14399 14400 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14401 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14402 return true; 14403} 14404 14405/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14406static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14407 const X86Subtarget *Subtarget) { 14408 EVT VT = N->getValueType(0); 14409 SDValue LHS = N->getOperand(0); 14410 SDValue RHS = N->getOperand(1); 14411 14412 // Try to synthesize horizontal adds from adds of shuffles. 14413 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) && 14414 (VT == MVT::v4f32 || VT == MVT::v2f64) && 14415 isHorizontalBinOp(LHS, RHS, true)) 14416 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14417 return SDValue(); 14418} 14419 14420/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14421static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14422 const X86Subtarget *Subtarget) { 14423 EVT VT = N->getValueType(0); 14424 SDValue LHS = N->getOperand(0); 14425 SDValue RHS = N->getOperand(1); 14426 14427 // Try to synthesize horizontal subs from subs of shuffles. 14428 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) && 14429 (VT == MVT::v4f32 || VT == MVT::v2f64) && 14430 isHorizontalBinOp(LHS, RHS, false)) 14431 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14432 return SDValue(); 14433} 14434 14435/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14436/// X86ISD::FXOR nodes. 14437static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14438 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14439 // F[X]OR(0.0, x) -> x 14440 // F[X]OR(x, 0.0) -> x 14441 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14442 if (C->getValueAPF().isPosZero()) 14443 return N->getOperand(1); 14444 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14445 if (C->getValueAPF().isPosZero()) 14446 return N->getOperand(0); 14447 return SDValue(); 14448} 14449 14450/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14451static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14452 // FAND(0.0, x) -> 0.0 14453 // FAND(x, 0.0) -> 0.0 14454 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14455 if (C->getValueAPF().isPosZero()) 14456 return N->getOperand(0); 14457 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14458 if (C->getValueAPF().isPosZero()) 14459 return N->getOperand(1); 14460 return SDValue(); 14461} 14462 14463static SDValue PerformBTCombine(SDNode *N, 14464 SelectionDAG &DAG, 14465 TargetLowering::DAGCombinerInfo &DCI) { 14466 // BT ignores high bits in the bit index operand. 14467 SDValue Op1 = N->getOperand(1); 14468 if (Op1.hasOneUse()) { 14469 unsigned BitWidth = Op1.getValueSizeInBits(); 14470 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14471 APInt KnownZero, KnownOne; 14472 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14473 !DCI.isBeforeLegalizeOps()); 14474 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14475 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14476 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14477 DCI.CommitTargetLoweringOpt(TLO); 14478 } 14479 return SDValue(); 14480} 14481 14482static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14483 SDValue Op = N->getOperand(0); 14484 if (Op.getOpcode() == ISD::BITCAST) 14485 Op = Op.getOperand(0); 14486 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14487 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14488 VT.getVectorElementType().getSizeInBits() == 14489 OpVT.getVectorElementType().getSizeInBits()) { 14490 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14491 } 14492 return SDValue(); 14493} 14494 14495static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14496 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14497 // (and (i32 x86isd::setcc_carry), 1) 14498 // This eliminates the zext. This transformation is necessary because 14499 // ISD::SETCC is always legalized to i8. 14500 DebugLoc dl = N->getDebugLoc(); 14501 SDValue N0 = N->getOperand(0); 14502 EVT VT = N->getValueType(0); 14503 if (N0.getOpcode() == ISD::AND && 14504 N0.hasOneUse() && 14505 N0.getOperand(0).hasOneUse()) { 14506 SDValue N00 = N0.getOperand(0); 14507 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14508 return SDValue(); 14509 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14510 if (!C || C->getZExtValue() != 1) 14511 return SDValue(); 14512 return DAG.getNode(ISD::AND, dl, VT, 14513 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14514 N00.getOperand(0), N00.getOperand(1)), 14515 DAG.getConstant(1, VT)); 14516 } 14517 14518 return SDValue(); 14519} 14520 14521// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14522static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14523 unsigned X86CC = N->getConstantOperandVal(0); 14524 SDValue EFLAG = N->getOperand(1); 14525 DebugLoc DL = N->getDebugLoc(); 14526 14527 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14528 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14529 // cases. 14530 if (X86CC == X86::COND_B) 14531 return DAG.getNode(ISD::AND, DL, MVT::i8, 14532 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14533 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14534 DAG.getConstant(1, MVT::i8)); 14535 14536 return SDValue(); 14537} 14538 14539static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14540 const X86TargetLowering *XTLI) { 14541 SDValue Op0 = N->getOperand(0); 14542 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14543 // a 32-bit target where SSE doesn't support i64->FP operations. 14544 if (Op0.getOpcode() == ISD::LOAD) { 14545 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14546 EVT VT = Ld->getValueType(0); 14547 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14548 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14549 !XTLI->getSubtarget()->is64Bit() && 14550 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14551 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14552 Ld->getChain(), Op0, DAG); 14553 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14554 return FILDChain; 14555 } 14556 } 14557 return SDValue(); 14558} 14559 14560// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14561static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14562 X86TargetLowering::DAGCombinerInfo &DCI) { 14563 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14564 // the result is either zero or one (depending on the input carry bit). 14565 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14566 if (X86::isZeroNode(N->getOperand(0)) && 14567 X86::isZeroNode(N->getOperand(1)) && 14568 // We don't have a good way to replace an EFLAGS use, so only do this when 14569 // dead right now. 14570 SDValue(N, 1).use_empty()) { 14571 DebugLoc DL = N->getDebugLoc(); 14572 EVT VT = N->getValueType(0); 14573 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14574 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14575 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14576 DAG.getConstant(X86::COND_B,MVT::i8), 14577 N->getOperand(2)), 14578 DAG.getConstant(1, VT)); 14579 return DCI.CombineTo(N, Res1, CarryOut); 14580 } 14581 14582 return SDValue(); 14583} 14584 14585// fold (add Y, (sete X, 0)) -> adc 0, Y 14586// (add Y, (setne X, 0)) -> sbb -1, Y 14587// (sub (sete X, 0), Y) -> sbb 0, Y 14588// (sub (setne X, 0), Y) -> adc -1, Y 14589static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14590 DebugLoc DL = N->getDebugLoc(); 14591 14592 // Look through ZExts. 14593 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14594 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14595 return SDValue(); 14596 14597 SDValue SetCC = Ext.getOperand(0); 14598 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14599 return SDValue(); 14600 14601 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14602 if (CC != X86::COND_E && CC != X86::COND_NE) 14603 return SDValue(); 14604 14605 SDValue Cmp = SetCC.getOperand(1); 14606 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14607 !X86::isZeroNode(Cmp.getOperand(1)) || 14608 !Cmp.getOperand(0).getValueType().isInteger()) 14609 return SDValue(); 14610 14611 SDValue CmpOp0 = Cmp.getOperand(0); 14612 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14613 DAG.getConstant(1, CmpOp0.getValueType())); 14614 14615 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14616 if (CC == X86::COND_NE) 14617 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14618 DL, OtherVal.getValueType(), OtherVal, 14619 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14620 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14621 DL, OtherVal.getValueType(), OtherVal, 14622 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14623} 14624 14625static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { 14626 SDValue Op0 = N->getOperand(0); 14627 SDValue Op1 = N->getOperand(1); 14628 14629 // X86 can't encode an immediate LHS of a sub. See if we can push the 14630 // negation into a preceding instruction. 14631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14632 // If the RHS of the sub is a XOR with one use and a constant, invert the 14633 // immediate. Then add one to the LHS of the sub so we can turn 14634 // X-Y -> X+~Y+1, saving one register. 14635 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14636 isa<ConstantSDNode>(Op1.getOperand(1))) { 14637 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14638 EVT VT = Op0.getValueType(); 14639 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14640 Op1.getOperand(0), 14641 DAG.getConstant(~XorC, VT)); 14642 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14643 DAG.getConstant(C->getAPIntValue()+1, VT)); 14644 } 14645 } 14646 14647 return OptimizeConditionalInDecrement(N, DAG); 14648} 14649 14650SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14651 DAGCombinerInfo &DCI) const { 14652 SelectionDAG &DAG = DCI.DAG; 14653 switch (N->getOpcode()) { 14654 default: break; 14655 case ISD::EXTRACT_VECTOR_ELT: 14656 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14657 case ISD::VSELECT: 14658 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 14659 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14660 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); 14661 case ISD::SUB: return PerformSubCombine(N, DAG); 14662 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14663 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14664 case ISD::SHL: 14665 case ISD::SRA: 14666 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14667 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14668 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14669 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14670 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14671 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14672 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14673 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14674 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14675 case X86ISD::FXOR: 14676 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14677 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14678 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14679 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14680 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14681 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14682 case X86ISD::SHUFPS: // Handle all target specific shuffles 14683 case X86ISD::SHUFPD: 14684 case X86ISD::PALIGN: 14685 case X86ISD::PUNPCKHBW: 14686 case X86ISD::PUNPCKHWD: 14687 case X86ISD::PUNPCKHDQ: 14688 case X86ISD::PUNPCKHQDQ: 14689 case X86ISD::UNPCKHPS: 14690 case X86ISD::UNPCKHPD: 14691 case X86ISD::VUNPCKHPSY: 14692 case X86ISD::VUNPCKHPDY: 14693 case X86ISD::PUNPCKLBW: 14694 case X86ISD::PUNPCKLWD: 14695 case X86ISD::PUNPCKLDQ: 14696 case X86ISD::PUNPCKLQDQ: 14697 case X86ISD::UNPCKLPS: 14698 case X86ISD::UNPCKLPD: 14699 case X86ISD::VUNPCKLPSY: 14700 case X86ISD::VUNPCKLPDY: 14701 case X86ISD::MOVHLPS: 14702 case X86ISD::MOVLHPS: 14703 case X86ISD::PSHUFD: 14704 case X86ISD::PSHUFHW: 14705 case X86ISD::PSHUFLW: 14706 case X86ISD::MOVSS: 14707 case X86ISD::MOVSD: 14708 case X86ISD::VPERMILPS: 14709 case X86ISD::VPERMILPSY: 14710 case X86ISD::VPERMILPD: 14711 case X86ISD::VPERMILPDY: 14712 case X86ISD::VPERM2F128: 14713 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14714 } 14715 14716 return SDValue(); 14717} 14718 14719/// isTypeDesirableForOp - Return true if the target has native support for 14720/// the specified value type and it is 'desirable' to use the type for the 14721/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14722/// instruction encodings are longer and some i16 instructions are slow. 14723bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14724 if (!isTypeLegal(VT)) 14725 return false; 14726 if (VT != MVT::i16) 14727 return true; 14728 14729 switch (Opc) { 14730 default: 14731 return true; 14732 case ISD::LOAD: 14733 case ISD::SIGN_EXTEND: 14734 case ISD::ZERO_EXTEND: 14735 case ISD::ANY_EXTEND: 14736 case ISD::SHL: 14737 case ISD::SRL: 14738 case ISD::SUB: 14739 case ISD::ADD: 14740 case ISD::MUL: 14741 case ISD::AND: 14742 case ISD::OR: 14743 case ISD::XOR: 14744 return false; 14745 } 14746} 14747 14748/// IsDesirableToPromoteOp - This method query the target whether it is 14749/// beneficial for dag combiner to promote the specified node. If true, it 14750/// should return the desired promotion type by reference. 14751bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14752 EVT VT = Op.getValueType(); 14753 if (VT != MVT::i16) 14754 return false; 14755 14756 bool Promote = false; 14757 bool Commute = false; 14758 switch (Op.getOpcode()) { 14759 default: break; 14760 case ISD::LOAD: { 14761 LoadSDNode *LD = cast<LoadSDNode>(Op); 14762 // If the non-extending load has a single use and it's not live out, then it 14763 // might be folded. 14764 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14765 Op.hasOneUse()*/) { 14766 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14767 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14768 // The only case where we'd want to promote LOAD (rather then it being 14769 // promoted as an operand is when it's only use is liveout. 14770 if (UI->getOpcode() != ISD::CopyToReg) 14771 return false; 14772 } 14773 } 14774 Promote = true; 14775 break; 14776 } 14777 case ISD::SIGN_EXTEND: 14778 case ISD::ZERO_EXTEND: 14779 case ISD::ANY_EXTEND: 14780 Promote = true; 14781 break; 14782 case ISD::SHL: 14783 case ISD::SRL: { 14784 SDValue N0 = Op.getOperand(0); 14785 // Look out for (store (shl (load), x)). 14786 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14787 return false; 14788 Promote = true; 14789 break; 14790 } 14791 case ISD::ADD: 14792 case ISD::MUL: 14793 case ISD::AND: 14794 case ISD::OR: 14795 case ISD::XOR: 14796 Commute = true; 14797 // fallthrough 14798 case ISD::SUB: { 14799 SDValue N0 = Op.getOperand(0); 14800 SDValue N1 = Op.getOperand(1); 14801 if (!Commute && MayFoldLoad(N1)) 14802 return false; 14803 // Avoid disabling potential load folding opportunities. 14804 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14805 return false; 14806 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14807 return false; 14808 Promote = true; 14809 } 14810 } 14811 14812 PVT = MVT::i32; 14813 return Promote; 14814} 14815 14816//===----------------------------------------------------------------------===// 14817// X86 Inline Assembly Support 14818//===----------------------------------------------------------------------===// 14819 14820bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14821 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14822 14823 std::string AsmStr = IA->getAsmString(); 14824 14825 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14826 SmallVector<StringRef, 4> AsmPieces; 14827 SplitString(AsmStr, AsmPieces, ";\n"); 14828 14829 switch (AsmPieces.size()) { 14830 default: return false; 14831 case 1: 14832 AsmStr = AsmPieces[0]; 14833 AsmPieces.clear(); 14834 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 14835 14836 // FIXME: this should verify that we are targeting a 486 or better. If not, 14837 // we will turn this bswap into something that will be lowered to logical ops 14838 // instead of emitting the bswap asm. For now, we don't support 486 or lower 14839 // so don't worry about this. 14840 // bswap $0 14841 if (AsmPieces.size() == 2 && 14842 (AsmPieces[0] == "bswap" || 14843 AsmPieces[0] == "bswapq" || 14844 AsmPieces[0] == "bswapl") && 14845 (AsmPieces[1] == "$0" || 14846 AsmPieces[1] == "${0:q}")) { 14847 // No need to check constraints, nothing other than the equivalent of 14848 // "=r,0" would be valid here. 14849 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14850 if (!Ty || Ty->getBitWidth() % 16 != 0) 14851 return false; 14852 return IntrinsicLowering::LowerToByteSwap(CI); 14853 } 14854 // rorw $$8, ${0:w} --> llvm.bswap.i16 14855 if (CI->getType()->isIntegerTy(16) && 14856 AsmPieces.size() == 3 && 14857 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 14858 AsmPieces[1] == "$$8," && 14859 AsmPieces[2] == "${0:w}" && 14860 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14861 AsmPieces.clear(); 14862 const std::string &ConstraintsStr = IA->getConstraintString(); 14863 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14864 std::sort(AsmPieces.begin(), AsmPieces.end()); 14865 if (AsmPieces.size() == 4 && 14866 AsmPieces[0] == "~{cc}" && 14867 AsmPieces[1] == "~{dirflag}" && 14868 AsmPieces[2] == "~{flags}" && 14869 AsmPieces[3] == "~{fpsr}") { 14870 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14871 if (!Ty || Ty->getBitWidth() % 16 != 0) 14872 return false; 14873 return IntrinsicLowering::LowerToByteSwap(CI); 14874 } 14875 } 14876 break; 14877 case 3: 14878 if (CI->getType()->isIntegerTy(32) && 14879 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14880 SmallVector<StringRef, 4> Words; 14881 SplitString(AsmPieces[0], Words, " \t,"); 14882 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14883 Words[2] == "${0:w}") { 14884 Words.clear(); 14885 SplitString(AsmPieces[1], Words, " \t,"); 14886 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 14887 Words[2] == "$0") { 14888 Words.clear(); 14889 SplitString(AsmPieces[2], Words, " \t,"); 14890 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14891 Words[2] == "${0:w}") { 14892 AsmPieces.clear(); 14893 const std::string &ConstraintsStr = IA->getConstraintString(); 14894 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14895 std::sort(AsmPieces.begin(), AsmPieces.end()); 14896 if (AsmPieces.size() == 4 && 14897 AsmPieces[0] == "~{cc}" && 14898 AsmPieces[1] == "~{dirflag}" && 14899 AsmPieces[2] == "~{flags}" && 14900 AsmPieces[3] == "~{fpsr}") { 14901 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14902 if (!Ty || Ty->getBitWidth() % 16 != 0) 14903 return false; 14904 return IntrinsicLowering::LowerToByteSwap(CI); 14905 } 14906 } 14907 } 14908 } 14909 } 14910 14911 if (CI->getType()->isIntegerTy(64)) { 14912 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14913 if (Constraints.size() >= 2 && 14914 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14915 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14916 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14917 SmallVector<StringRef, 4> Words; 14918 SplitString(AsmPieces[0], Words, " \t"); 14919 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 14920 Words.clear(); 14921 SplitString(AsmPieces[1], Words, " \t"); 14922 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 14923 Words.clear(); 14924 SplitString(AsmPieces[2], Words, " \t,"); 14925 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 14926 Words[2] == "%edx") { 14927 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14928 if (!Ty || Ty->getBitWidth() % 16 != 0) 14929 return false; 14930 return IntrinsicLowering::LowerToByteSwap(CI); 14931 } 14932 } 14933 } 14934 } 14935 } 14936 break; 14937 } 14938 return false; 14939} 14940 14941 14942 14943/// getConstraintType - Given a constraint letter, return the type of 14944/// constraint it is for this target. 14945X86TargetLowering::ConstraintType 14946X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14947 if (Constraint.size() == 1) { 14948 switch (Constraint[0]) { 14949 case 'R': 14950 case 'q': 14951 case 'Q': 14952 case 'f': 14953 case 't': 14954 case 'u': 14955 case 'y': 14956 case 'x': 14957 case 'Y': 14958 case 'l': 14959 return C_RegisterClass; 14960 case 'a': 14961 case 'b': 14962 case 'c': 14963 case 'd': 14964 case 'S': 14965 case 'D': 14966 case 'A': 14967 return C_Register; 14968 case 'I': 14969 case 'J': 14970 case 'K': 14971 case 'L': 14972 case 'M': 14973 case 'N': 14974 case 'G': 14975 case 'C': 14976 case 'e': 14977 case 'Z': 14978 return C_Other; 14979 default: 14980 break; 14981 } 14982 } 14983 return TargetLowering::getConstraintType(Constraint); 14984} 14985 14986/// Examine constraint type and operand type and determine a weight value. 14987/// This object must already have been set up with the operand type 14988/// and the current alternative constraint selected. 14989TargetLowering::ConstraintWeight 14990 X86TargetLowering::getSingleConstraintMatchWeight( 14991 AsmOperandInfo &info, const char *constraint) const { 14992 ConstraintWeight weight = CW_Invalid; 14993 Value *CallOperandVal = info.CallOperandVal; 14994 // If we don't have a value, we can't do a match, 14995 // but allow it at the lowest weight. 14996 if (CallOperandVal == NULL) 14997 return CW_Default; 14998 Type *type = CallOperandVal->getType(); 14999 // Look at the constraint type. 15000 switch (*constraint) { 15001 default: 15002 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15003 case 'R': 15004 case 'q': 15005 case 'Q': 15006 case 'a': 15007 case 'b': 15008 case 'c': 15009 case 'd': 15010 case 'S': 15011 case 'D': 15012 case 'A': 15013 if (CallOperandVal->getType()->isIntegerTy()) 15014 weight = CW_SpecificReg; 15015 break; 15016 case 'f': 15017 case 't': 15018 case 'u': 15019 if (type->isFloatingPointTy()) 15020 weight = CW_SpecificReg; 15021 break; 15022 case 'y': 15023 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15024 weight = CW_SpecificReg; 15025 break; 15026 case 'x': 15027 case 'Y': 15028 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 15029 weight = CW_Register; 15030 break; 15031 case 'I': 15032 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15033 if (C->getZExtValue() <= 31) 15034 weight = CW_Constant; 15035 } 15036 break; 15037 case 'J': 15038 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15039 if (C->getZExtValue() <= 63) 15040 weight = CW_Constant; 15041 } 15042 break; 15043 case 'K': 15044 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15045 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15046 weight = CW_Constant; 15047 } 15048 break; 15049 case 'L': 15050 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15051 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15052 weight = CW_Constant; 15053 } 15054 break; 15055 case 'M': 15056 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15057 if (C->getZExtValue() <= 3) 15058 weight = CW_Constant; 15059 } 15060 break; 15061 case 'N': 15062 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15063 if (C->getZExtValue() <= 0xff) 15064 weight = CW_Constant; 15065 } 15066 break; 15067 case 'G': 15068 case 'C': 15069 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15070 weight = CW_Constant; 15071 } 15072 break; 15073 case 'e': 15074 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15075 if ((C->getSExtValue() >= -0x80000000LL) && 15076 (C->getSExtValue() <= 0x7fffffffLL)) 15077 weight = CW_Constant; 15078 } 15079 break; 15080 case 'Z': 15081 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15082 if (C->getZExtValue() <= 0xffffffff) 15083 weight = CW_Constant; 15084 } 15085 break; 15086 } 15087 return weight; 15088} 15089 15090/// LowerXConstraint - try to replace an X constraint, which matches anything, 15091/// with another that has more specific requirements based on the type of the 15092/// corresponding operand. 15093const char *X86TargetLowering:: 15094LowerXConstraint(EVT ConstraintVT) const { 15095 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15096 // 'f' like normal targets. 15097 if (ConstraintVT.isFloatingPoint()) { 15098 if (Subtarget->hasXMMInt()) 15099 return "Y"; 15100 if (Subtarget->hasXMM()) 15101 return "x"; 15102 } 15103 15104 return TargetLowering::LowerXConstraint(ConstraintVT); 15105} 15106 15107/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15108/// vector. If it is invalid, don't add anything to Ops. 15109void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15110 std::string &Constraint, 15111 std::vector<SDValue>&Ops, 15112 SelectionDAG &DAG) const { 15113 SDValue Result(0, 0); 15114 15115 // Only support length 1 constraints for now. 15116 if (Constraint.length() > 1) return; 15117 15118 char ConstraintLetter = Constraint[0]; 15119 switch (ConstraintLetter) { 15120 default: break; 15121 case 'I': 15122 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15123 if (C->getZExtValue() <= 31) { 15124 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15125 break; 15126 } 15127 } 15128 return; 15129 case 'J': 15130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15131 if (C->getZExtValue() <= 63) { 15132 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15133 break; 15134 } 15135 } 15136 return; 15137 case 'K': 15138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15139 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15140 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15141 break; 15142 } 15143 } 15144 return; 15145 case 'N': 15146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15147 if (C->getZExtValue() <= 255) { 15148 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15149 break; 15150 } 15151 } 15152 return; 15153 case 'e': { 15154 // 32-bit signed value 15155 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15156 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15157 C->getSExtValue())) { 15158 // Widen to 64 bits here to get it sign extended. 15159 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15160 break; 15161 } 15162 // FIXME gcc accepts some relocatable values here too, but only in certain 15163 // memory models; it's complicated. 15164 } 15165 return; 15166 } 15167 case 'Z': { 15168 // 32-bit unsigned value 15169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15170 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15171 C->getZExtValue())) { 15172 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15173 break; 15174 } 15175 } 15176 // FIXME gcc accepts some relocatable values here too, but only in certain 15177 // memory models; it's complicated. 15178 return; 15179 } 15180 case 'i': { 15181 // Literal immediates are always ok. 15182 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15183 // Widen to 64 bits here to get it sign extended. 15184 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15185 break; 15186 } 15187 15188 // In any sort of PIC mode addresses need to be computed at runtime by 15189 // adding in a register or some sort of table lookup. These can't 15190 // be used as immediates. 15191 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15192 return; 15193 15194 // If we are in non-pic codegen mode, we allow the address of a global (with 15195 // an optional displacement) to be used with 'i'. 15196 GlobalAddressSDNode *GA = 0; 15197 int64_t Offset = 0; 15198 15199 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15200 while (1) { 15201 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15202 Offset += GA->getOffset(); 15203 break; 15204 } else if (Op.getOpcode() == ISD::ADD) { 15205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15206 Offset += C->getZExtValue(); 15207 Op = Op.getOperand(0); 15208 continue; 15209 } 15210 } else if (Op.getOpcode() == ISD::SUB) { 15211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15212 Offset += -C->getZExtValue(); 15213 Op = Op.getOperand(0); 15214 continue; 15215 } 15216 } 15217 15218 // Otherwise, this isn't something we can handle, reject it. 15219 return; 15220 } 15221 15222 const GlobalValue *GV = GA->getGlobal(); 15223 // If we require an extra load to get this address, as in PIC mode, we 15224 // can't accept it. 15225 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15226 getTargetMachine()))) 15227 return; 15228 15229 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15230 GA->getValueType(0), Offset); 15231 break; 15232 } 15233 } 15234 15235 if (Result.getNode()) { 15236 Ops.push_back(Result); 15237 return; 15238 } 15239 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15240} 15241 15242std::pair<unsigned, const TargetRegisterClass*> 15243X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15244 EVT VT) const { 15245 // First, see if this is a constraint that directly corresponds to an LLVM 15246 // register class. 15247 if (Constraint.size() == 1) { 15248 // GCC Constraint Letters 15249 switch (Constraint[0]) { 15250 default: break; 15251 // TODO: Slight differences here in allocation order and leaving 15252 // RIP in the class. Do they matter any more here than they do 15253 // in the normal allocation? 15254 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15255 if (Subtarget->is64Bit()) { 15256 if (VT == MVT::i32 || VT == MVT::f32) 15257 return std::make_pair(0U, X86::GR32RegisterClass); 15258 else if (VT == MVT::i16) 15259 return std::make_pair(0U, X86::GR16RegisterClass); 15260 else if (VT == MVT::i8 || VT == MVT::i1) 15261 return std::make_pair(0U, X86::GR8RegisterClass); 15262 else if (VT == MVT::i64 || VT == MVT::f64) 15263 return std::make_pair(0U, X86::GR64RegisterClass); 15264 break; 15265 } 15266 // 32-bit fallthrough 15267 case 'Q': // Q_REGS 15268 if (VT == MVT::i32 || VT == MVT::f32) 15269 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15270 else if (VT == MVT::i16) 15271 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15272 else if (VT == MVT::i8 || VT == MVT::i1) 15273 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15274 else if (VT == MVT::i64) 15275 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15276 break; 15277 case 'r': // GENERAL_REGS 15278 case 'l': // INDEX_REGS 15279 if (VT == MVT::i8 || VT == MVT::i1) 15280 return std::make_pair(0U, X86::GR8RegisterClass); 15281 if (VT == MVT::i16) 15282 return std::make_pair(0U, X86::GR16RegisterClass); 15283 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15284 return std::make_pair(0U, X86::GR32RegisterClass); 15285 return std::make_pair(0U, X86::GR64RegisterClass); 15286 case 'R': // LEGACY_REGS 15287 if (VT == MVT::i8 || VT == MVT::i1) 15288 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15289 if (VT == MVT::i16) 15290 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15291 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15292 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15293 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15294 case 'f': // FP Stack registers. 15295 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15296 // value to the correct fpstack register class. 15297 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15298 return std::make_pair(0U, X86::RFP32RegisterClass); 15299 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15300 return std::make_pair(0U, X86::RFP64RegisterClass); 15301 return std::make_pair(0U, X86::RFP80RegisterClass); 15302 case 'y': // MMX_REGS if MMX allowed. 15303 if (!Subtarget->hasMMX()) break; 15304 return std::make_pair(0U, X86::VR64RegisterClass); 15305 case 'Y': // SSE_REGS if SSE2 allowed 15306 if (!Subtarget->hasXMMInt()) break; 15307 // FALL THROUGH. 15308 case 'x': // SSE_REGS if SSE1 allowed 15309 if (!Subtarget->hasXMM()) break; 15310 15311 switch (VT.getSimpleVT().SimpleTy) { 15312 default: break; 15313 // Scalar SSE types. 15314 case MVT::f32: 15315 case MVT::i32: 15316 return std::make_pair(0U, X86::FR32RegisterClass); 15317 case MVT::f64: 15318 case MVT::i64: 15319 return std::make_pair(0U, X86::FR64RegisterClass); 15320 // Vector types. 15321 case MVT::v16i8: 15322 case MVT::v8i16: 15323 case MVT::v4i32: 15324 case MVT::v2i64: 15325 case MVT::v4f32: 15326 case MVT::v2f64: 15327 return std::make_pair(0U, X86::VR128RegisterClass); 15328 } 15329 break; 15330 } 15331 } 15332 15333 // Use the default implementation in TargetLowering to convert the register 15334 // constraint into a member of a register class. 15335 std::pair<unsigned, const TargetRegisterClass*> Res; 15336 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15337 15338 // Not found as a standard register? 15339 if (Res.second == 0) { 15340 // Map st(0) -> st(7) -> ST0 15341 if (Constraint.size() == 7 && Constraint[0] == '{' && 15342 tolower(Constraint[1]) == 's' && 15343 tolower(Constraint[2]) == 't' && 15344 Constraint[3] == '(' && 15345 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15346 Constraint[5] == ')' && 15347 Constraint[6] == '}') { 15348 15349 Res.first = X86::ST0+Constraint[4]-'0'; 15350 Res.second = X86::RFP80RegisterClass; 15351 return Res; 15352 } 15353 15354 // GCC allows "st(0)" to be called just plain "st". 15355 if (StringRef("{st}").equals_lower(Constraint)) { 15356 Res.first = X86::ST0; 15357 Res.second = X86::RFP80RegisterClass; 15358 return Res; 15359 } 15360 15361 // flags -> EFLAGS 15362 if (StringRef("{flags}").equals_lower(Constraint)) { 15363 Res.first = X86::EFLAGS; 15364 Res.second = X86::CCRRegisterClass; 15365 return Res; 15366 } 15367 15368 // 'A' means EAX + EDX. 15369 if (Constraint == "A") { 15370 Res.first = X86::EAX; 15371 Res.second = X86::GR32_ADRegisterClass; 15372 return Res; 15373 } 15374 return Res; 15375 } 15376 15377 // Otherwise, check to see if this is a register class of the wrong value 15378 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15379 // turn into {ax},{dx}. 15380 if (Res.second->hasType(VT)) 15381 return Res; // Correct type already, nothing to do. 15382 15383 // All of the single-register GCC register classes map their values onto 15384 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15385 // really want an 8-bit or 32-bit register, map to the appropriate register 15386 // class and return the appropriate register. 15387 if (Res.second == X86::GR16RegisterClass) { 15388 if (VT == MVT::i8) { 15389 unsigned DestReg = 0; 15390 switch (Res.first) { 15391 default: break; 15392 case X86::AX: DestReg = X86::AL; break; 15393 case X86::DX: DestReg = X86::DL; break; 15394 case X86::CX: DestReg = X86::CL; break; 15395 case X86::BX: DestReg = X86::BL; break; 15396 } 15397 if (DestReg) { 15398 Res.first = DestReg; 15399 Res.second = X86::GR8RegisterClass; 15400 } 15401 } else if (VT == MVT::i32) { 15402 unsigned DestReg = 0; 15403 switch (Res.first) { 15404 default: break; 15405 case X86::AX: DestReg = X86::EAX; break; 15406 case X86::DX: DestReg = X86::EDX; break; 15407 case X86::CX: DestReg = X86::ECX; break; 15408 case X86::BX: DestReg = X86::EBX; break; 15409 case X86::SI: DestReg = X86::ESI; break; 15410 case X86::DI: DestReg = X86::EDI; break; 15411 case X86::BP: DestReg = X86::EBP; break; 15412 case X86::SP: DestReg = X86::ESP; break; 15413 } 15414 if (DestReg) { 15415 Res.first = DestReg; 15416 Res.second = X86::GR32RegisterClass; 15417 } 15418 } else if (VT == MVT::i64) { 15419 unsigned DestReg = 0; 15420 switch (Res.first) { 15421 default: break; 15422 case X86::AX: DestReg = X86::RAX; break; 15423 case X86::DX: DestReg = X86::RDX; break; 15424 case X86::CX: DestReg = X86::RCX; break; 15425 case X86::BX: DestReg = X86::RBX; break; 15426 case X86::SI: DestReg = X86::RSI; break; 15427 case X86::DI: DestReg = X86::RDI; break; 15428 case X86::BP: DestReg = X86::RBP; break; 15429 case X86::SP: DestReg = X86::RSP; break; 15430 } 15431 if (DestReg) { 15432 Res.first = DestReg; 15433 Res.second = X86::GR64RegisterClass; 15434 } 15435 } 15436 } else if (Res.second == X86::FR32RegisterClass || 15437 Res.second == X86::FR64RegisterClass || 15438 Res.second == X86::VR128RegisterClass) { 15439 // Handle references to XMM physical registers that got mapped into the 15440 // wrong class. This can happen with constraints like {xmm0} where the 15441 // target independent register mapper will just pick the first match it can 15442 // find, ignoring the required type. 15443 if (VT == MVT::f32) 15444 Res.second = X86::FR32RegisterClass; 15445 else if (VT == MVT::f64) 15446 Res.second = X86::FR64RegisterClass; 15447 else if (X86::VR128RegisterClass->hasType(VT)) 15448 Res.second = X86::VR128RegisterClass; 15449 } 15450 15451 return Res; 15452} 15453