X86ISelLowering.cpp revision 32c727cd95a7718e10e225bb9fc00be6681706aa
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "X86FastISel.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Function.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/ADT/BitVector.h" 28#include "llvm/ADT/VectorExtras.h" 29#include "llvm/CodeGen/CallingConvLower.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/PseudoSourceValue.h" 36#include "llvm/CodeGen/SelectionDAG.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Target/TargetOptions.h" 40#include "llvm/ADT/SmallSet.h" 41#include "llvm/ADT/StringExtras.h" 42using namespace llvm; 43 44// Forward declarations. 45static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG); 46 47X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 48 : TargetLowering(TM) { 49 Subtarget = &TM.getSubtarget<X86Subtarget>(); 50 X86ScalarSSEf64 = Subtarget->hasSSE2(); 51 X86ScalarSSEf32 = Subtarget->hasSSE1(); 52 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 53 54 bool Fast = false; 55 56 RegInfo = TM.getRegisterInfo(); 57 58 // Set up the TargetLowering object. 59 60 // X86 is weird, it always uses i8 for shift amounts and setcc results. 61 setShiftAmountType(MVT::i8); 62 setSetCCResultContents(ZeroOrOneSetCCResult); 63 setSchedulingPreference(SchedulingForRegPressure); 64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 65 setStackPointerRegisterToSaveRestore(X86StackPtr); 66 67 if (Subtarget->isTargetDarwin()) { 68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 69 setUseUnderscoreSetJmp(false); 70 setUseUnderscoreLongJmp(false); 71 } else if (Subtarget->isTargetMingw()) { 72 // MS runtime is weird: it exports _setjmp, but longjmp! 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(false); 75 } else { 76 setUseUnderscoreSetJmp(true); 77 setUseUnderscoreLongJmp(true); 78 } 79 80 // Set up the register classes. 81 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 82 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 83 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 84 if (Subtarget->is64Bit()) 85 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 86 87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 88 89 // We don't accept any truncstore of integer registers. 90 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 91 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 93 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 95 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 96 97 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 98 // operation. 99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 102 103 if (Subtarget->is64Bit()) { 104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 106 } else { 107 if (X86ScalarSSEf64) 108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. 109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 110 else 111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 112 } 113 114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 115 // this operation. 116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 118 // SSE has no i16 to fp conversion, only i32 119 if (X86ScalarSSEf32) { 120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 121 // f32 and f64 cases are Legal, f80 case is not 122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 123 } else { 124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 126 } 127 128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 129 // are Legal, f80 is custom lowered. 130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 132 133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 134 // this operation. 135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 137 138 if (X86ScalarSSEf32) { 139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 140 // f32 and f64 cases are Legal, f80 case is not 141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 142 } else { 143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 145 } 146 147 // Handle FP_TO_UINT by promoting the destination to a larger signed 148 // conversion. 149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 152 153 if (Subtarget->is64Bit()) { 154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 156 } else { 157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 158 // Expand FP_TO_UINT into a select. 159 // FIXME: We would like to use a Custom expander here eventually to do 160 // the optimal thing for SSE vs. the default expansion in the legalizer. 161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 162 else 163 // With SSE3 we can use fisttpll to convert to a signed i64. 164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 165 } 166 167 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 168 if (!X86ScalarSSEf64) { 169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 171 } 172 173 // Scalar integer divide and remainder are lowered to use operations that 174 // produce two results, to match the available instructions. This exposes 175 // the two-result form to trivial CSE, which is able to combine x/y and x%y 176 // into a single instruction. 177 // 178 // Scalar integer multiply-high is also lowered to use two-result 179 // operations, to match the available instructions. However, plain multiply 180 // (low) operations are left as Legal, as there are single-result 181 // instructions for this in x86. Using the two-result multiply instructions 182 // when both high and low results are needed must be arranged by dagcombine. 183 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 184 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 185 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 186 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 187 setOperationAction(ISD::SREM , MVT::i8 , Expand); 188 setOperationAction(ISD::UREM , MVT::i8 , Expand); 189 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 190 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 191 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 192 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 193 setOperationAction(ISD::SREM , MVT::i16 , Expand); 194 setOperationAction(ISD::UREM , MVT::i16 , Expand); 195 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 196 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 197 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 198 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 199 setOperationAction(ISD::SREM , MVT::i32 , Expand); 200 setOperationAction(ISD::UREM , MVT::i32 , Expand); 201 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 202 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 203 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 204 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 205 setOperationAction(ISD::SREM , MVT::i64 , Expand); 206 setOperationAction(ISD::UREM , MVT::i64 , Expand); 207 208 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 209 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 210 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 212 if (Subtarget->is64Bit()) 213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 218 setOperationAction(ISD::FREM , MVT::f32 , Expand); 219 setOperationAction(ISD::FREM , MVT::f64 , Expand); 220 setOperationAction(ISD::FREM , MVT::f80 , Expand); 221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 222 223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 232 if (Subtarget->is64Bit()) { 233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 236 } 237 238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 240 241 // These should be promoted to a larger select which is supported. 242 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 243 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 244 // X86 wants to expand cmov itself. 245 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 246 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 247 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 248 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 249 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 250 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 251 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 252 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 253 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 254 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 255 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 256 if (Subtarget->is64Bit()) { 257 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 258 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 259 } 260 // X86 ret instruction may pop stack. 261 setOperationAction(ISD::RET , MVT::Other, Custom); 262 if (!Subtarget->is64Bit()) 263 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 264 265 // Darwin ABI issue. 266 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 267 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 268 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 270 if (Subtarget->is64Bit()) 271 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 272 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 273 if (Subtarget->is64Bit()) { 274 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 275 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 276 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 277 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 278 } 279 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 280 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 281 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 282 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 283 if (Subtarget->is64Bit()) { 284 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 285 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 286 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 287 } 288 289 if (Subtarget->hasSSE1()) 290 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 291 292 if (!Subtarget->hasSSE2()) 293 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 294 295 // Expand certain atomics 296 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i8, Custom); 297 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i16, Custom); 298 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i32, Custom); 299 setOperationAction(ISD::ATOMIC_CMP_SWAP , MVT::i64, Custom); 300 301 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i8, Expand); 302 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i16, Expand); 303 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i32, Expand); 304 setOperationAction(ISD::ATOMIC_LOAD_SUB , MVT::i64, Expand); 305 306 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. 307 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 308 // FIXME - use subtarget debug flags 309 if (!Subtarget->isTargetDarwin() && 310 !Subtarget->isTargetELF() && 311 !Subtarget->isTargetCygMing()) { 312 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 313 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 314 } 315 316 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 317 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 318 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 319 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 320 if (Subtarget->is64Bit()) { 321 // FIXME: Verify 322 setExceptionPointerRegister(X86::RAX); 323 setExceptionSelectorRegister(X86::RDX); 324 } else { 325 setExceptionPointerRegister(X86::EAX); 326 setExceptionSelectorRegister(X86::EDX); 327 } 328 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 329 330 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 331 332 setOperationAction(ISD::TRAP, MVT::Other, Legal); 333 334 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 335 setOperationAction(ISD::VASTART , MVT::Other, Custom); 336 setOperationAction(ISD::VAEND , MVT::Other, Expand); 337 if (Subtarget->is64Bit()) { 338 setOperationAction(ISD::VAARG , MVT::Other, Custom); 339 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 340 } else { 341 setOperationAction(ISD::VAARG , MVT::Other, Expand); 342 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 343 } 344 345 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 346 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 347 if (Subtarget->is64Bit()) 348 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 349 if (Subtarget->isTargetCygMing()) 350 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 351 else 352 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 353 354 if (X86ScalarSSEf64) { 355 // f32 and f64 use SSE. 356 // Set up the FP register classes. 357 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 358 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 359 360 // Use ANDPD to simulate FABS. 361 setOperationAction(ISD::FABS , MVT::f64, Custom); 362 setOperationAction(ISD::FABS , MVT::f32, Custom); 363 364 // Use XORP to simulate FNEG. 365 setOperationAction(ISD::FNEG , MVT::f64, Custom); 366 setOperationAction(ISD::FNEG , MVT::f32, Custom); 367 368 // Use ANDPD and ORPD to simulate FCOPYSIGN. 369 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 370 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 371 372 // We don't support sin/cos/fmod 373 setOperationAction(ISD::FSIN , MVT::f64, Expand); 374 setOperationAction(ISD::FCOS , MVT::f64, Expand); 375 setOperationAction(ISD::FSIN , MVT::f32, Expand); 376 setOperationAction(ISD::FCOS , MVT::f32, Expand); 377 378 // Expand FP immediates into loads from the stack, except for the special 379 // cases we handle. 380 addLegalFPImmediate(APFloat(+0.0)); // xorpd 381 addLegalFPImmediate(APFloat(+0.0f)); // xorps 382 383 // Floating truncations from f80 and extensions to f80 go through memory. 384 // If optimizing, we lie about this though and handle it in 385 // InstructionSelectPreprocess so that dagcombine2 can hack on these. 386 if (Fast) { 387 setConvertAction(MVT::f32, MVT::f80, Expand); 388 setConvertAction(MVT::f64, MVT::f80, Expand); 389 setConvertAction(MVT::f80, MVT::f32, Expand); 390 setConvertAction(MVT::f80, MVT::f64, Expand); 391 } 392 } else if (X86ScalarSSEf32) { 393 // Use SSE for f32, x87 for f64. 394 // Set up the FP register classes. 395 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 396 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 397 398 // Use ANDPS to simulate FABS. 399 setOperationAction(ISD::FABS , MVT::f32, Custom); 400 401 // Use XORP to simulate FNEG. 402 setOperationAction(ISD::FNEG , MVT::f32, Custom); 403 404 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 405 406 // Use ANDPS and ORPS to simulate FCOPYSIGN. 407 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 408 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 409 410 // We don't support sin/cos/fmod 411 setOperationAction(ISD::FSIN , MVT::f32, Expand); 412 setOperationAction(ISD::FCOS , MVT::f32, Expand); 413 414 // Special cases we handle for FP constants. 415 addLegalFPImmediate(APFloat(+0.0f)); // xorps 416 addLegalFPImmediate(APFloat(+0.0)); // FLD0 417 addLegalFPImmediate(APFloat(+1.0)); // FLD1 418 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 419 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 420 421 // SSE <-> X87 conversions go through memory. If optimizing, we lie about 422 // this though and handle it in InstructionSelectPreprocess so that 423 // dagcombine2 can hack on these. 424 if (Fast) { 425 setConvertAction(MVT::f32, MVT::f64, Expand); 426 setConvertAction(MVT::f32, MVT::f80, Expand); 427 setConvertAction(MVT::f80, MVT::f32, Expand); 428 setConvertAction(MVT::f64, MVT::f32, Expand); 429 // And x87->x87 truncations also. 430 setConvertAction(MVT::f80, MVT::f64, Expand); 431 } 432 433 if (!UnsafeFPMath) { 434 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 435 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 436 } 437 } else { 438 // f32 and f64 in x87. 439 // Set up the FP register classes. 440 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 441 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 442 443 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 444 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 447 448 // Floating truncations go through memory. If optimizing, we lie about 449 // this though and handle it in InstructionSelectPreprocess so that 450 // dagcombine2 can hack on these. 451 if (Fast) { 452 setConvertAction(MVT::f80, MVT::f32, Expand); 453 setConvertAction(MVT::f64, MVT::f32, Expand); 454 setConvertAction(MVT::f80, MVT::f64, Expand); 455 } 456 457 if (!UnsafeFPMath) { 458 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 459 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 460 } 461 addLegalFPImmediate(APFloat(+0.0)); // FLD0 462 addLegalFPImmediate(APFloat(+1.0)); // FLD1 463 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 464 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 465 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 466 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 467 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 468 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 469 } 470 471 // Long double always uses X87. 472 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 473 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 474 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 475 { 476 APFloat TmpFlt(+0.0); 477 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven); 478 addLegalFPImmediate(TmpFlt); // FLD0 479 TmpFlt.changeSign(); 480 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 481 APFloat TmpFlt2(+1.0); 482 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven); 483 addLegalFPImmediate(TmpFlt2); // FLD1 484 TmpFlt2.changeSign(); 485 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 486 } 487 488 if (!UnsafeFPMath) { 489 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 490 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 491 } 492 493 // Always use a library call for pow. 494 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 495 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 496 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 497 498 // First set operation action for all vector types to expand. Then we 499 // will selectively turn on ones that can be effectively codegen'd. 500 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 501 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 502 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 503 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 504 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 505 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 506 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 507 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 508 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 509 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 510 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 511 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 512 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 513 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 514 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 515 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 516 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand); 517 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand); 518 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 519 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 520 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 521 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 522 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 523 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 524 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 525 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 526 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 527 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 528 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 529 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 530 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 531 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 532 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 533 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 534 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 535 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 538 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 539 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 540 } 541 542 if (Subtarget->hasMMX()) { 543 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 544 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 545 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 546 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 547 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 548 549 // FIXME: add MMX packed arithmetics 550 551 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 552 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 553 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 554 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 555 556 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 557 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 558 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 559 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 560 561 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 562 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 563 564 setOperationAction(ISD::AND, MVT::v8i8, Promote); 565 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 566 setOperationAction(ISD::AND, MVT::v4i16, Promote); 567 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 568 setOperationAction(ISD::AND, MVT::v2i32, Promote); 569 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 570 setOperationAction(ISD::AND, MVT::v1i64, Legal); 571 572 setOperationAction(ISD::OR, MVT::v8i8, Promote); 573 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 574 setOperationAction(ISD::OR, MVT::v4i16, Promote); 575 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 576 setOperationAction(ISD::OR, MVT::v2i32, Promote); 577 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 578 setOperationAction(ISD::OR, MVT::v1i64, Legal); 579 580 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 581 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 582 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 583 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 584 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 585 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 586 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 587 588 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 589 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 590 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 591 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 592 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 593 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 594 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 595 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 596 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 597 598 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 599 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 600 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 601 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 602 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 603 604 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 605 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 606 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 607 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 608 609 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 610 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 611 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 612 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 613 614 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 615 } 616 617 if (Subtarget->hasSSE1()) { 618 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 619 620 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 621 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 622 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 623 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 624 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 625 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 626 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 627 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 628 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 629 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 630 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 631 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 632 } 633 634 if (Subtarget->hasSSE2()) { 635 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 636 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 637 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 638 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 639 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 640 641 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 642 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 643 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 644 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 645 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 646 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 647 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 648 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 649 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 650 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 651 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 652 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 653 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 654 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 655 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 656 657 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 658 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 659 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 660 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 661 662 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 663 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 664 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 665 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 666 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 667 668 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 669 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 670 MVT VT = (MVT::SimpleValueType)i; 671 // Do not attempt to custom lower non-power-of-2 vectors 672 if (!isPowerOf2_32(VT.getVectorNumElements())) 673 continue; 674 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 675 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 676 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 677 } 678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 680 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 681 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 682 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 684 if (Subtarget->is64Bit()) { 685 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 687 } 688 689 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 690 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 691 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote); 692 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64); 693 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote); 694 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64); 695 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote); 696 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64); 697 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote); 698 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64); 699 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote); 700 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64); 701 } 702 703 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 704 705 // Custom lower v2i64 and v2f64 selects. 706 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 707 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 708 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 709 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 710 711 } 712 713 if (Subtarget->hasSSE41()) { 714 // FIXME: Do we need to handle scalar-to-vector here? 715 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 716 setOperationAction(ISD::MUL, MVT::v2i64, Legal); 717 718 // i8 and i16 vectors are custom , because the source register and source 719 // source memory operand types are not the same width. f32 vectors are 720 // custom since the immediate controlling the insert encodes additional 721 // information. 722 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 723 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 724 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); 725 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 726 727 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 728 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 729 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); 730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 731 732 if (Subtarget->is64Bit()) { 733 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 734 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 735 } 736 } 737 738 if (Subtarget->hasSSE42()) { 739 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 740 } 741 742 // We want to custom lower some of our intrinsics. 743 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 744 745 // We have target-specific dag combine patterns for the following nodes: 746 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 747 setTargetDAGCombine(ISD::BUILD_VECTOR); 748 setTargetDAGCombine(ISD::SELECT); 749 setTargetDAGCombine(ISD::STORE); 750 751 computeRegisterProperties(); 752 753 // FIXME: These should be based on subtarget info. Plus, the values should 754 // be smaller when we are in optimizing for size mode. 755 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 756 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 757 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 758 allowUnalignedMemoryAccesses = true; // x86 supports it! 759 setPrefLoopAlignment(16); 760} 761 762 763MVT X86TargetLowering::getSetCCResultType(const SDValue &) const { 764 return MVT::i8; 765} 766 767 768/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 769/// the desired ByVal argument alignment. 770static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 771 if (MaxAlign == 16) 772 return; 773 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 774 if (VTy->getBitWidth() == 128) 775 MaxAlign = 16; 776 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 777 unsigned EltAlign = 0; 778 getMaxByValAlign(ATy->getElementType(), EltAlign); 779 if (EltAlign > MaxAlign) 780 MaxAlign = EltAlign; 781 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 782 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 783 unsigned EltAlign = 0; 784 getMaxByValAlign(STy->getElementType(i), EltAlign); 785 if (EltAlign > MaxAlign) 786 MaxAlign = EltAlign; 787 if (MaxAlign == 16) 788 break; 789 } 790 } 791 return; 792} 793 794/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 795/// function arguments in the caller parameter area. For X86, aggregates 796/// that contain SSE vectors are placed at 16-byte boundaries while the rest 797/// are at 4-byte boundaries. 798unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 799 if (Subtarget->is64Bit()) { 800 // Max of 8 and alignment of type. 801 unsigned TyAlign = getTargetData()->getABITypeAlignment(Ty); 802 if (TyAlign > 8) 803 return TyAlign; 804 return 8; 805 } 806 807 unsigned Align = 4; 808 if (Subtarget->hasSSE1()) 809 getMaxByValAlign(Ty, Align); 810 return Align; 811} 812 813/// getOptimalMemOpType - Returns the target specific optimal type for load 814/// and store operations as a result of memset, memcpy, and memmove 815/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 816/// determining it. 817MVT 818X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 819 bool isSrcConst, bool isSrcStr) const { 820 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 821 return MVT::v4i32; 822 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 823 return MVT::v4f32; 824 if (Subtarget->is64Bit() && Size >= 8) 825 return MVT::i64; 826 return MVT::i32; 827} 828 829 830/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 831/// jumptable. 832SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 833 SelectionDAG &DAG) const { 834 if (usesGlobalOffsetTable()) 835 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 836 if (!Subtarget->isPICStyleRIPRel()) 837 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()); 838 return Table; 839} 840 841//===----------------------------------------------------------------------===// 842// Return Value Calling Convention Implementation 843//===----------------------------------------------------------------------===// 844 845#include "X86GenCallingConv.inc" 846 847/// LowerRET - Lower an ISD::RET node. 848SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 849 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 850 851 SmallVector<CCValAssign, 16> RVLocs; 852 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 853 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 854 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 855 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86); 856 857 // If this is the first return lowered for this function, add the regs to the 858 // liveout set for the function. 859 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 860 for (unsigned i = 0; i != RVLocs.size(); ++i) 861 if (RVLocs[i].isRegLoc()) 862 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 863 } 864 SDValue Chain = Op.getOperand(0); 865 866 // Handle tail call return. 867 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); 868 if (Chain.getOpcode() == X86ISD::TAILCALL) { 869 SDValue TailCall = Chain; 870 SDValue TargetAddress = TailCall.getOperand(1); 871 SDValue StackAdjustment = TailCall.getOperand(2); 872 assert(((TargetAddress.getOpcode() == ISD::Register && 873 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX || 874 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || 875 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 876 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 877 "Expecting an global address, external symbol, or register"); 878 assert(StackAdjustment.getOpcode() == ISD::Constant && 879 "Expecting a const value"); 880 881 SmallVector<SDValue,8> Operands; 882 Operands.push_back(Chain.getOperand(0)); 883 Operands.push_back(TargetAddress); 884 Operands.push_back(StackAdjustment); 885 // Copy registers used by the call. Last operand is a flag so it is not 886 // copied. 887 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 888 Operands.push_back(Chain.getOperand(i)); 889 } 890 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0], 891 Operands.size()); 892 } 893 894 // Regular return. 895 SDValue Flag; 896 897 SmallVector<SDValue, 6> RetOps; 898 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 899 // Operand #1 = Bytes To Pop 900 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 901 902 // Copy the result values into the output registers. 903 for (unsigned i = 0; i != RVLocs.size(); ++i) { 904 CCValAssign &VA = RVLocs[i]; 905 assert(VA.isRegLoc() && "Can only return in registers!"); 906 SDValue ValToCopy = Op.getOperand(i*2+1); 907 908 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 909 // the RET instruction and handled by the FP Stackifier. 910 if (RVLocs[i].getLocReg() == X86::ST0 || 911 RVLocs[i].getLocReg() == X86::ST1) { 912 // If this is a copy from an xmm register to ST(0), use an FPExtend to 913 // change the value to the FP stack register class. 914 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) 915 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy); 916 RetOps.push_back(ValToCopy); 917 // Don't emit a copytoreg. 918 continue; 919 } 920 921 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag); 922 Flag = Chain.getValue(1); 923 } 924 925 // The x86-64 ABI for returning structs by value requires that we copy 926 // the sret argument into %rax for the return. We saved the argument into 927 // a virtual register in the entry block, so now we copy the value out 928 // and into %rax. 929 if (Subtarget->is64Bit() && 930 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 931 MachineFunction &MF = DAG.getMachineFunction(); 932 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 933 unsigned Reg = FuncInfo->getSRetReturnReg(); 934 if (!Reg) { 935 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 936 FuncInfo->setSRetReturnReg(Reg); 937 } 938 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy()); 939 940 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag); 941 Flag = Chain.getValue(1); 942 } 943 944 RetOps[0] = Chain; // Update chain. 945 946 // Add the flag if we have it. 947 if (Flag.Val) 948 RetOps.push_back(Flag); 949 950 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size()); 951} 952 953 954/// LowerCallResult - Lower the result values of an ISD::CALL into the 955/// appropriate copies out of appropriate physical registers. This assumes that 956/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 957/// being lowered. The returns a SDNode with the same number of values as the 958/// ISD::CALL. 959SDNode *X86TargetLowering:: 960LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall, 961 unsigned CallingConv, SelectionDAG &DAG) { 962 963 // Assign locations to each value returned by this call. 964 SmallVector<CCValAssign, 16> RVLocs; 965 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; 966 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 967 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); 968 969 SmallVector<SDValue, 8> ResultVals; 970 971 // Copy all of the result registers out of their specified physreg. 972 for (unsigned i = 0; i != RVLocs.size(); ++i) { 973 MVT CopyVT = RVLocs[i].getValVT(); 974 975 // If this is a call to a function that returns an fp value on the floating 976 // point stack, but where we prefer to use the value in xmm registers, copy 977 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 978 if ((RVLocs[i].getLocReg() == X86::ST0 || 979 RVLocs[i].getLocReg() == X86::ST1) && 980 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 981 CopyVT = MVT::f80; 982 } 983 984 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 985 CopyVT, InFlag).getValue(1); 986 SDValue Val = Chain.getValue(0); 987 InFlag = Chain.getValue(2); 988 989 if (CopyVT != RVLocs[i].getValVT()) { 990 // Round the F80 the right size, which also moves to the appropriate xmm 991 // register. 992 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val, 993 // This truncation won't change the value. 994 DAG.getIntPtrConstant(1)); 995 } 996 997 ResultVals.push_back(Val); 998 } 999 1000 // Merge everything together with a MERGE_VALUES node. 1001 ResultVals.push_back(Chain); 1002 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], 1003 ResultVals.size()).Val; 1004} 1005 1006 1007//===----------------------------------------------------------------------===// 1008// C & StdCall & Fast Calling Convention implementation 1009//===----------------------------------------------------------------------===// 1010// StdCall calling convention seems to be standard for many Windows' API 1011// routines and around. It differs from C calling convention just a little: 1012// callee should clean up the stack, not caller. Symbols should be also 1013// decorated in some fancy way :) It doesn't support any vector arguments. 1014// For info on fast calling convention see Fast Calling Convention (tail call) 1015// implementation LowerX86_32FastCCCallTo. 1016 1017/// AddLiveIn - This helper function adds the specified physical register to the 1018/// MachineFunction as a live in value. It also creates a corresponding virtual 1019/// register for it. 1020static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 1021 const TargetRegisterClass *RC) { 1022 assert(RC->contains(PReg) && "Not the correct regclass!"); 1023 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1024 MF.getRegInfo().addLiveIn(PReg, VReg); 1025 return VReg; 1026} 1027 1028/// CallIsStructReturn - Determines whether a CALL node uses struct return 1029/// semantics. 1030static bool CallIsStructReturn(SDValue Op) { 1031 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1032 if (!NumOps) 1033 return false; 1034 1035 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet(); 1036} 1037 1038/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct 1039/// return semantics. 1040static bool ArgsAreStructReturn(SDValue Op) { 1041 unsigned NumArgs = Op.Val->getNumValues() - 1; 1042 if (!NumArgs) 1043 return false; 1044 1045 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); 1046} 1047 1048/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires 1049/// the callee to pop its own arguments. Callee pop is necessary to support tail 1050/// calls. 1051bool X86TargetLowering::IsCalleePop(SDValue Op) { 1052 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1053 if (IsVarArg) 1054 return false; 1055 1056 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 1057 default: 1058 return false; 1059 case CallingConv::X86_StdCall: 1060 return !Subtarget->is64Bit(); 1061 case CallingConv::X86_FastCall: 1062 return !Subtarget->is64Bit(); 1063 case CallingConv::Fast: 1064 return PerformTailCallOpt; 1065 } 1066} 1067 1068/// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or 1069/// FORMAL_ARGUMENTS node. 1070CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDValue Op) const { 1071 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1072 1073 if (Subtarget->is64Bit()) { 1074 if (Subtarget->isTargetWin64()) 1075 return CC_X86_Win64_C; 1076 else { 1077 if (CC == CallingConv::Fast && PerformTailCallOpt) 1078 return CC_X86_64_TailCall; 1079 else 1080 return CC_X86_64_C; 1081 } 1082 } 1083 1084 if (CC == CallingConv::X86_FastCall) 1085 return CC_X86_32_FastCall; 1086 else if (CC == CallingConv::Fast && PerformTailCallOpt) 1087 return CC_X86_32_TailCall; 1088 else 1089 return CC_X86_32_C; 1090} 1091 1092/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to 1093/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. 1094NameDecorationStyle 1095X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) { 1096 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1097 if (CC == CallingConv::X86_FastCall) 1098 return FastCall; 1099 else if (CC == CallingConv::X86_StdCall) 1100 return StdCall; 1101 return None; 1102} 1103 1104 1105/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer 1106/// in a register before calling. 1107bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { 1108 return !IsTailCall && !Is64Bit && 1109 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1110 Subtarget->isPICStyleGOT(); 1111} 1112 1113/// CallRequiresFnAddressInReg - Check whether the call requires the function 1114/// address to be loaded in a register. 1115bool 1116X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { 1117 return !Is64Bit && IsTailCall && 1118 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1119 Subtarget->isPICStyleGOT(); 1120} 1121 1122/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1123/// by "Src" to address "Dst" with size and alignment information specified by 1124/// the specific parameter attribute. The copy will be passed as a byval 1125/// function parameter. 1126static SDValue 1127CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1128 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { 1129 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1130 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), 1131 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1132} 1133 1134SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG, 1135 const CCValAssign &VA, 1136 MachineFrameInfo *MFI, 1137 unsigned CC, 1138 SDValue Root, unsigned i) { 1139 // Create the nodes corresponding to a load from this parameter slot. 1140 ISD::ArgFlagsTy Flags = 1141 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); 1142 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; 1143 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1144 1145 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1146 // changed with more analysis. 1147 // In case of tail call optimization mark all arguments mutable. Since they 1148 // could be overwritten by lowering of arguments in case of a tail call. 1149 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1150 VA.getLocMemOffset(), isImmutable); 1151 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1152 if (Flags.isByVal()) 1153 return FIN; 1154 return DAG.getLoad(VA.getValVT(), Root, FIN, 1155 PseudoSourceValue::getFixedStack(FI), 0); 1156} 1157 1158SDValue 1159X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 1160 MachineFunction &MF = DAG.getMachineFunction(); 1161 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1162 1163 const Function* Fn = MF.getFunction(); 1164 if (Fn->hasExternalLinkage() && 1165 Subtarget->isTargetCygMing() && 1166 Fn->getName() == "main") 1167 FuncInfo->setForceFramePointer(true); 1168 1169 // Decorate the function name. 1170 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); 1171 1172 MachineFrameInfo *MFI = MF.getFrameInfo(); 1173 SDValue Root = Op.getOperand(0); 1174 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1175 unsigned CC = MF.getFunction()->getCallingConv(); 1176 bool Is64Bit = Subtarget->is64Bit(); 1177 bool IsWin64 = Subtarget->isTargetWin64(); 1178 1179 assert(!(isVarArg && CC == CallingConv::Fast) && 1180 "Var args not supported with calling convention fastcc"); 1181 1182 // Assign locations to all of the incoming arguments. 1183 SmallVector<CCValAssign, 16> ArgLocs; 1184 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1185 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op)); 1186 1187 SmallVector<SDValue, 8> ArgValues; 1188 unsigned LastVal = ~0U; 1189 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1190 CCValAssign &VA = ArgLocs[i]; 1191 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1192 // places. 1193 assert(VA.getValNo() != LastVal && 1194 "Don't support value assigned to multiple locs yet"); 1195 LastVal = VA.getValNo(); 1196 1197 if (VA.isRegLoc()) { 1198 MVT RegVT = VA.getLocVT(); 1199 TargetRegisterClass *RC; 1200 if (RegVT == MVT::i32) 1201 RC = X86::GR32RegisterClass; 1202 else if (Is64Bit && RegVT == MVT::i64) 1203 RC = X86::GR64RegisterClass; 1204 else if (RegVT == MVT::f32) 1205 RC = X86::FR32RegisterClass; 1206 else if (RegVT == MVT::f64) 1207 RC = X86::FR64RegisterClass; 1208 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1209 RC = X86::VR128RegisterClass; 1210 else if (RegVT.isVector()) { 1211 assert(RegVT.getSizeInBits() == 64); 1212 if (!Is64Bit) 1213 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. 1214 else { 1215 // Darwin calling convention passes MMX values in either GPRs or 1216 // XMMs in x86-64. Other targets pass them in memory. 1217 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { 1218 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. 1219 RegVT = MVT::v2i64; 1220 } else { 1221 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. 1222 RegVT = MVT::i64; 1223 } 1224 } 1225 } else { 1226 assert(0 && "Unknown argument type!"); 1227 } 1228 1229 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 1230 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 1231 1232 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1233 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1234 // right size. 1235 if (VA.getLocInfo() == CCValAssign::SExt) 1236 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 1237 DAG.getValueType(VA.getValVT())); 1238 else if (VA.getLocInfo() == CCValAssign::ZExt) 1239 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 1240 DAG.getValueType(VA.getValVT())); 1241 1242 if (VA.getLocInfo() != CCValAssign::Full) 1243 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 1244 1245 // Handle MMX values passed in GPRs. 1246 if (Is64Bit && RegVT != VA.getLocVT()) { 1247 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) 1248 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1249 else if (RC == X86::VR128RegisterClass) { 1250 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, 1251 DAG.getConstant(0, MVT::i64)); 1252 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1253 } 1254 } 1255 1256 ArgValues.push_back(ArgValue); 1257 } else { 1258 assert(VA.isMemLoc()); 1259 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); 1260 } 1261 } 1262 1263 // The x86-64 ABI for returning structs by value requires that we copy 1264 // the sret argument into %rax for the return. Save the argument into 1265 // a virtual register so that we can access it from the return points. 1266 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1267 MachineFunction &MF = DAG.getMachineFunction(); 1268 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1269 unsigned Reg = FuncInfo->getSRetReturnReg(); 1270 if (!Reg) { 1271 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1272 FuncInfo->setSRetReturnReg(Reg); 1273 } 1274 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]); 1275 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root); 1276 } 1277 1278 unsigned StackSize = CCInfo.getNextStackOffset(); 1279 // align stack specially for tail calls 1280 if (CC == CallingConv::Fast) 1281 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1282 1283 // If the function takes variable number of arguments, make a frame index for 1284 // the start of the first vararg value... for expansion of llvm.va_start. 1285 if (isVarArg) { 1286 if (Is64Bit || CC != CallingConv::X86_FastCall) { 1287 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1288 } 1289 if (Is64Bit) { 1290 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1291 1292 // FIXME: We should really autogenerate these arrays 1293 static const unsigned GPR64ArgRegsWin64[] = { 1294 X86::RCX, X86::RDX, X86::R8, X86::R9 1295 }; 1296 static const unsigned XMMArgRegsWin64[] = { 1297 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1298 }; 1299 static const unsigned GPR64ArgRegs64Bit[] = { 1300 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1301 }; 1302 static const unsigned XMMArgRegs64Bit[] = { 1303 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1304 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1305 }; 1306 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1307 1308 if (IsWin64) { 1309 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1310 GPR64ArgRegs = GPR64ArgRegsWin64; 1311 XMMArgRegs = XMMArgRegsWin64; 1312 } else { 1313 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1314 GPR64ArgRegs = GPR64ArgRegs64Bit; 1315 XMMArgRegs = XMMArgRegs64Bit; 1316 } 1317 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1318 TotalNumIntRegs); 1319 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1320 TotalNumXMMRegs); 1321 1322 // For X86-64, if there are vararg parameters that are passed via 1323 // registers, then we must store them to their spots on the stack so they 1324 // may be loaded by deferencing the result of va_next. 1325 VarArgsGPOffset = NumIntRegs * 8; 1326 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1327 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1328 TotalNumXMMRegs * 16, 16); 1329 1330 // Store the integer parameter registers. 1331 SmallVector<SDValue, 8> MemOps; 1332 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1333 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1334 DAG.getIntPtrConstant(VarArgsGPOffset)); 1335 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1336 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1337 X86::GR64RegisterClass); 1338 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1339 SDValue Store = 1340 DAG.getStore(Val.getValue(1), Val, FIN, 1341 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1342 MemOps.push_back(Store); 1343 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1344 DAG.getIntPtrConstant(8)); 1345 } 1346 1347 // Now store the XMM (fp + vector) parameter registers. 1348 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1349 DAG.getIntPtrConstant(VarArgsFPOffset)); 1350 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1351 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1352 X86::VR128RegisterClass); 1353 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1354 SDValue Store = 1355 DAG.getStore(Val.getValue(1), Val, FIN, 1356 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1357 MemOps.push_back(Store); 1358 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1359 DAG.getIntPtrConstant(16)); 1360 } 1361 if (!MemOps.empty()) 1362 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1363 &MemOps[0], MemOps.size()); 1364 } 1365 } 1366 1367 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1368 // arguments and the arguments after the retaddr has been pushed are 1369 // aligned. 1370 if (!Is64Bit && CC == CallingConv::X86_FastCall && 1371 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() && 1372 (StackSize & 7) == 0) 1373 StackSize += 4; 1374 1375 ArgValues.push_back(Root); 1376 1377 // Some CCs need callee pop. 1378 if (IsCalleePop(Op)) { 1379 BytesToPopOnReturn = StackSize; // Callee pops everything. 1380 BytesCallerReserves = 0; 1381 } else { 1382 BytesToPopOnReturn = 0; // Callee pops nothing. 1383 // If this is an sret function, the return should pop the hidden pointer. 1384 if (!Is64Bit && ArgsAreStructReturn(Op)) 1385 BytesToPopOnReturn = 4; 1386 BytesCallerReserves = StackSize; 1387 } 1388 1389 if (!Is64Bit) { 1390 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1391 if (CC == CallingConv::X86_FastCall) 1392 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1393 } 1394 1395 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1396 1397 // Return the new list of results. 1398 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], 1399 ArgValues.size()).getValue(Op.ResNo); 1400} 1401 1402SDValue 1403X86TargetLowering::LowerMemOpCallTo(SDValue Op, SelectionDAG &DAG, 1404 const SDValue &StackPtr, 1405 const CCValAssign &VA, 1406 SDValue Chain, 1407 SDValue Arg) { 1408 unsigned LocMemOffset = VA.getLocMemOffset(); 1409 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1410 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1411 ISD::ArgFlagsTy Flags = 1412 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags(); 1413 if (Flags.isByVal()) { 1414 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); 1415 } 1416 return DAG.getStore(Chain, Arg, PtrOff, 1417 PseudoSourceValue::getStack(), LocMemOffset); 1418} 1419 1420/// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call 1421/// optimization is performed and it is required. 1422SDValue 1423X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1424 SDValue &OutRetAddr, 1425 SDValue Chain, 1426 bool IsTailCall, 1427 bool Is64Bit, 1428 int FPDiff) { 1429 if (!IsTailCall || FPDiff==0) return Chain; 1430 1431 // Adjust the Return address stack slot. 1432 MVT VT = getPointerTy(); 1433 OutRetAddr = getReturnAddressFrameIndex(DAG); 1434 // Load the "old" Return address. 1435 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0); 1436 return SDValue(OutRetAddr.Val, 1); 1437} 1438 1439/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1440/// optimization is performed and it is required (FPDiff!=0). 1441static SDValue 1442EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1443 SDValue Chain, SDValue RetAddrFrIdx, 1444 bool Is64Bit, int FPDiff) { 1445 // Store the return address to the appropriate stack slot. 1446 if (!FPDiff) return Chain; 1447 // Calculate the new stack slot for the return address. 1448 int SlotSize = Is64Bit ? 8 : 4; 1449 int NewReturnAddrFI = 1450 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1451 MVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1452 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1453 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, 1454 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1455 return Chain; 1456} 1457 1458SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 1459 MachineFunction &MF = DAG.getMachineFunction(); 1460 SDValue Chain = Op.getOperand(0); 1461 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1462 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1463 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 1464 && CC == CallingConv::Fast && PerformTailCallOpt; 1465 SDValue Callee = Op.getOperand(4); 1466 bool Is64Bit = Subtarget->is64Bit(); 1467 bool IsStructRet = CallIsStructReturn(Op); 1468 1469 assert(!(isVarArg && CC == CallingConv::Fast) && 1470 "Var args not supported with calling convention fastcc"); 1471 1472 // Analyze operands of the call, assigning locations to each operand. 1473 SmallVector<CCValAssign, 16> ArgLocs; 1474 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1475 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op)); 1476 1477 // Get a count of how many bytes are to be pushed on the stack. 1478 unsigned NumBytes = CCInfo.getNextStackOffset(); 1479 if (CC == CallingConv::Fast) 1480 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1481 1482 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1483 // arguments and the arguments after the retaddr has been pushed are aligned. 1484 if (!Is64Bit && CC == CallingConv::X86_FastCall && 1485 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() && 1486 (NumBytes & 7) == 0) 1487 NumBytes += 4; 1488 1489 int FPDiff = 0; 1490 if (IsTailCall) { 1491 // Lower arguments at fp - stackoffset + fpdiff. 1492 unsigned NumBytesCallerPushed = 1493 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1494 FPDiff = NumBytesCallerPushed - NumBytes; 1495 1496 // Set the delta of movement of the returnaddr stackslot. 1497 // But only set if delta is greater than previous delta. 1498 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1499 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1500 } 1501 1502 // If the address is a load, i.e. indirect function call, move callseq_start 1503 // above the load. This makes it possible for the load to fold into the call. 1504 if (Callee.Val == Chain.Val && ISD::isNormalLoad(Callee.Val) && 1505 Chain.hasOneUse() && Callee.hasOneUse()) 1506 Chain = Chain.getOperand(0); 1507 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes)); 1508 1509 SDValue RetAddrFrIdx; 1510 // Load return adress for tail calls. 1511 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, 1512 FPDiff); 1513 1514 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1515 SmallVector<SDValue, 8> MemOpChains; 1516 SDValue StackPtr; 1517 1518 // Walk the register/memloc assignments, inserting copies/loads. In the case 1519 // of tail call optimization arguments are handle later. 1520 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1521 CCValAssign &VA = ArgLocs[i]; 1522 SDValue Arg = Op.getOperand(5+2*VA.getValNo()); 1523 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))-> 1524 getArgFlags().isByVal(); 1525 1526 // Promote the value if needed. 1527 switch (VA.getLocInfo()) { 1528 default: assert(0 && "Unknown loc info!"); 1529 case CCValAssign::Full: break; 1530 case CCValAssign::SExt: 1531 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 1532 break; 1533 case CCValAssign::ZExt: 1534 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 1535 break; 1536 case CCValAssign::AExt: 1537 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 1538 break; 1539 } 1540 1541 if (VA.isRegLoc()) { 1542 if (Is64Bit) { 1543 MVT RegVT = VA.getLocVT(); 1544 if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1545 switch (VA.getLocReg()) { 1546 default: 1547 break; 1548 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: 1549 case X86::R8: { 1550 // Special case: passing MMX values in GPR registers. 1551 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); 1552 break; 1553 } 1554 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: 1555 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { 1556 // Special case: passing MMX values in XMM registers. 1557 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg); 1558 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg); 1559 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 1560 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg, 1561 getMOVLMask(2, DAG)); 1562 break; 1563 } 1564 } 1565 } 1566 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1567 } else { 1568 if (!IsTailCall || (IsTailCall && isByVal)) { 1569 assert(VA.isMemLoc()); 1570 if (StackPtr.Val == 0) 1571 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1572 1573 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain, 1574 Arg)); 1575 } 1576 } 1577 } 1578 1579 if (!MemOpChains.empty()) 1580 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1581 &MemOpChains[0], MemOpChains.size()); 1582 1583 // Build a sequence of copy-to-reg nodes chained together with token chain 1584 // and flag operands which copy the outgoing args into registers. 1585 SDValue InFlag; 1586 // Tail call byval lowering might overwrite argument registers so in case of 1587 // tail call optimization the copies to registers are lowered later. 1588 if (!IsTailCall) 1589 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1590 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1591 InFlag); 1592 InFlag = Chain.getValue(1); 1593 } 1594 1595 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1596 // GOT pointer. 1597 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { 1598 Chain = DAG.getCopyToReg(Chain, X86::EBX, 1599 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 1600 InFlag); 1601 InFlag = Chain.getValue(1); 1602 } 1603 // If we are tail calling and generating PIC/GOT style code load the address 1604 // of the callee into ecx. The value in ecx is used as target of the tail 1605 // jump. This is done to circumvent the ebx/callee-saved problem for tail 1606 // calls on PIC/GOT architectures. Normally we would just put the address of 1607 // GOT into ebx and then call target@PLT. But for tail callss ebx would be 1608 // restored (since ebx is callee saved) before jumping to the target@PLT. 1609 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { 1610 // Note: The actual moving to ecx is done further down. 1611 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1612 if (G && !G->getGlobal()->hasHiddenVisibility() && 1613 !G->getGlobal()->hasProtectedVisibility()) 1614 Callee = LowerGlobalAddress(Callee, DAG); 1615 else if (isa<ExternalSymbolSDNode>(Callee)) 1616 Callee = LowerExternalSymbol(Callee,DAG); 1617 } 1618 1619 if (Is64Bit && isVarArg) { 1620 // From AMD64 ABI document: 1621 // For calls that may call functions that use varargs or stdargs 1622 // (prototype-less calls or calls to functions containing ellipsis (...) in 1623 // the declaration) %al is used as hidden argument to specify the number 1624 // of SSE registers used. The contents of %al do not need to match exactly 1625 // the number of registers, but must be an ubound on the number of SSE 1626 // registers used and is in the range 0 - 8 inclusive. 1627 1628 // FIXME: Verify this on Win64 1629 // Count the number of XMM registers allocated. 1630 static const unsigned XMMArgRegs[] = { 1631 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1632 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1633 }; 1634 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1635 1636 Chain = DAG.getCopyToReg(Chain, X86::AL, 1637 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1638 InFlag = Chain.getValue(1); 1639 } 1640 1641 1642 // For tail calls lower the arguments to the 'real' stack slot. 1643 if (IsTailCall) { 1644 SmallVector<SDValue, 8> MemOpChains2; 1645 SDValue FIN; 1646 int FI = 0; 1647 // Do not flag preceeding copytoreg stuff together with the following stuff. 1648 InFlag = SDValue(); 1649 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1650 CCValAssign &VA = ArgLocs[i]; 1651 if (!VA.isRegLoc()) { 1652 assert(VA.isMemLoc()); 1653 SDValue Arg = Op.getOperand(5+2*VA.getValNo()); 1654 SDValue FlagsOp = Op.getOperand(6+2*VA.getValNo()); 1655 ISD::ArgFlagsTy Flags = 1656 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags(); 1657 // Create frame index. 1658 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1659 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1660 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1661 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1662 1663 if (Flags.isByVal()) { 1664 // Copy relative to framepointer. 1665 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1666 if (StackPtr.Val == 0) 1667 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1668 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source); 1669 1670 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, 1671 Flags, DAG)); 1672 } else { 1673 // Store relative to framepointer. 1674 MemOpChains2.push_back( 1675 DAG.getStore(Chain, Arg, FIN, 1676 PseudoSourceValue::getFixedStack(FI), 0)); 1677 } 1678 } 1679 } 1680 1681 if (!MemOpChains2.empty()) 1682 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1683 &MemOpChains2[0], MemOpChains2.size()); 1684 1685 // Copy arguments to their registers. 1686 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1687 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1688 InFlag); 1689 InFlag = Chain.getValue(1); 1690 } 1691 InFlag =SDValue(); 1692 1693 // Store the return address to the appropriate stack slot. 1694 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1695 FPDiff); 1696 } 1697 1698 // If the callee is a GlobalAddress node (quite common, every direct call is) 1699 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1700 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1701 // We should use extra load for direct calls to dllimported functions in 1702 // non-JIT mode. 1703 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1704 getTargetMachine(), true)) 1705 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1706 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1707 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1708 } else if (IsTailCall) { 1709 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX; 1710 1711 Chain = DAG.getCopyToReg(Chain, 1712 DAG.getRegister(Opc, getPointerTy()), 1713 Callee,InFlag); 1714 Callee = DAG.getRegister(Opc, getPointerTy()); 1715 // Add register as live out. 1716 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); 1717 } 1718 1719 // Returns a chain & a flag for retval copy to use. 1720 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1721 SmallVector<SDValue, 8> Ops; 1722 1723 if (IsTailCall) { 1724 Ops.push_back(Chain); 1725 Ops.push_back(DAG.getIntPtrConstant(NumBytes)); 1726 Ops.push_back(DAG.getIntPtrConstant(0)); 1727 if (InFlag.Val) 1728 Ops.push_back(InFlag); 1729 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1730 InFlag = Chain.getValue(1); 1731 1732 // Returns a chain & a flag for retval copy to use. 1733 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1734 Ops.clear(); 1735 } 1736 1737 Ops.push_back(Chain); 1738 Ops.push_back(Callee); 1739 1740 if (IsTailCall) 1741 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1742 1743 // Add argument registers to the end of the list so that they are known live 1744 // into the call. 1745 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1746 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1747 RegsToPass[i].second.getValueType())); 1748 1749 // Add an implicit use GOT pointer in EBX. 1750 if (!IsTailCall && !Is64Bit && 1751 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1752 Subtarget->isPICStyleGOT()) 1753 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1754 1755 // Add an implicit use of AL for x86 vararg functions. 1756 if (Is64Bit && isVarArg) 1757 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1758 1759 if (InFlag.Val) 1760 Ops.push_back(InFlag); 1761 1762 if (IsTailCall) { 1763 assert(InFlag.Val && 1764 "Flag must be set. Depend on flag being set in LowerRET"); 1765 Chain = DAG.getNode(X86ISD::TAILCALL, 1766 Op.Val->getVTList(), &Ops[0], Ops.size()); 1767 1768 return SDValue(Chain.Val, Op.ResNo); 1769 } 1770 1771 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); 1772 InFlag = Chain.getValue(1); 1773 1774 // Create the CALLSEQ_END node. 1775 unsigned NumBytesForCalleeToPush; 1776 if (IsCalleePop(Op)) 1777 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 1778 else if (!Is64Bit && IsStructRet) 1779 // If this is is a call to a struct-return function, the callee 1780 // pops the hidden struct pointer, so we have to push it back. 1781 // This is common for Darwin/X86, Linux & Mingw32 targets. 1782 NumBytesForCalleeToPush = 4; 1783 else 1784 NumBytesForCalleeToPush = 0; // Callee pops nothing. 1785 1786 // Returns a flag for retval copy to use. 1787 Chain = DAG.getCALLSEQ_END(Chain, 1788 DAG.getIntPtrConstant(NumBytes), 1789 DAG.getIntPtrConstant(NumBytesForCalleeToPush), 1790 InFlag); 1791 InFlag = Chain.getValue(1); 1792 1793 // Handle result values, copying them out of physregs into vregs that we 1794 // return. 1795 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 1796} 1797 1798 1799//===----------------------------------------------------------------------===// 1800// Fast Calling Convention (tail call) implementation 1801//===----------------------------------------------------------------------===// 1802 1803// Like std call, callee cleans arguments, convention except that ECX is 1804// reserved for storing the tail called function address. Only 2 registers are 1805// free for argument passing (inreg). Tail call optimization is performed 1806// provided: 1807// * tailcallopt is enabled 1808// * caller/callee are fastcc 1809// On X86_64 architecture with GOT-style position independent code only local 1810// (within module) calls are supported at the moment. 1811// To keep the stack aligned according to platform abi the function 1812// GetAlignedArgumentStackSize ensures that argument delta is always multiples 1813// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 1814// If a tail called function callee has more arguments than the caller the 1815// caller needs to make sure that there is room to move the RETADDR to. This is 1816// achieved by reserving an area the size of the argument delta right after the 1817// original REtADDR, but before the saved framepointer or the spilled registers 1818// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 1819// stack layout: 1820// arg1 1821// arg2 1822// RETADDR 1823// [ new RETADDR 1824// move area ] 1825// (possible EBP) 1826// ESI 1827// EDI 1828// local1 .. 1829 1830/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 1831/// for a 16 byte align requirement. 1832unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 1833 SelectionDAG& DAG) { 1834 if (PerformTailCallOpt) { 1835 MachineFunction &MF = DAG.getMachineFunction(); 1836 const TargetMachine &TM = MF.getTarget(); 1837 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 1838 unsigned StackAlignment = TFI.getStackAlignment(); 1839 uint64_t AlignMask = StackAlignment - 1; 1840 int64_t Offset = StackSize; 1841 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4; 1842 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 1843 // Number smaller than 12 so just add the difference. 1844 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 1845 } else { 1846 // Mask out lower bits, add stackalignment once plus the 12 bytes. 1847 Offset = ((~AlignMask) & Offset) + StackAlignment + 1848 (StackAlignment-SlotSize); 1849 } 1850 StackSize = Offset; 1851 } 1852 return StackSize; 1853} 1854 1855/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1856/// following the call is a return. A function is eligible if caller/callee 1857/// calling conventions match, currently only fastcc supports tail calls, and 1858/// the function CALL is immediatly followed by a RET. 1859bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call, 1860 SDValue Ret, 1861 SelectionDAG& DAG) const { 1862 if (!PerformTailCallOpt) 1863 return false; 1864 1865 if (CheckTailCallReturnConstraints(Call, Ret)) { 1866 MachineFunction &MF = DAG.getMachineFunction(); 1867 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1868 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue(); 1869 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1870 SDValue Callee = Call.getOperand(4); 1871 // On x86/32Bit PIC/GOT tail calls are supported. 1872 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || 1873 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) 1874 return true; 1875 1876 // Can only do local tail calls (in same module, hidden or protected) on 1877 // x86_64 PIC/GOT at the moment. 1878 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1879 return G->getGlobal()->hasHiddenVisibility() 1880 || G->getGlobal()->hasProtectedVisibility(); 1881 } 1882 } 1883 1884 return false; 1885} 1886 1887FastISel *X86TargetLowering::createFastISel(MachineFunction &mf) { 1888 return X86::createFastISel(mf); 1889} 1890 1891 1892//===----------------------------------------------------------------------===// 1893// Other Lowering Hooks 1894//===----------------------------------------------------------------------===// 1895 1896 1897SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1898 MachineFunction &MF = DAG.getMachineFunction(); 1899 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1900 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1901 1902 if (ReturnAddrIndex == 0) { 1903 // Set up a frame object for the return address. 1904 if (Subtarget->is64Bit()) 1905 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8); 1906 else 1907 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 1908 1909 FuncInfo->setRAIndex(ReturnAddrIndex); 1910 } 1911 1912 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1913} 1914 1915 1916 1917/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 1918/// specific condition code. It returns a false if it cannot do a direct 1919/// translation. X86CC is the translated CondCode. LHS/RHS are modified as 1920/// needed. 1921static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 1922 unsigned &X86CC, SDValue &LHS, SDValue &RHS, 1923 SelectionDAG &DAG) { 1924 X86CC = X86::COND_INVALID; 1925 if (!isFP) { 1926 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1927 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 1928 // X > -1 -> X == 0, jump !sign. 1929 RHS = DAG.getConstant(0, RHS.getValueType()); 1930 X86CC = X86::COND_NS; 1931 return true; 1932 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 1933 // X < 0 -> X == 0, jump on sign. 1934 X86CC = X86::COND_S; 1935 return true; 1936 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) { 1937 // X < 1 -> X <= 0 1938 RHS = DAG.getConstant(0, RHS.getValueType()); 1939 X86CC = X86::COND_LE; 1940 return true; 1941 } 1942 } 1943 1944 switch (SetCCOpcode) { 1945 default: break; 1946 case ISD::SETEQ: X86CC = X86::COND_E; break; 1947 case ISD::SETGT: X86CC = X86::COND_G; break; 1948 case ISD::SETGE: X86CC = X86::COND_GE; break; 1949 case ISD::SETLT: X86CC = X86::COND_L; break; 1950 case ISD::SETLE: X86CC = X86::COND_LE; break; 1951 case ISD::SETNE: X86CC = X86::COND_NE; break; 1952 case ISD::SETULT: X86CC = X86::COND_B; break; 1953 case ISD::SETUGT: X86CC = X86::COND_A; break; 1954 case ISD::SETULE: X86CC = X86::COND_BE; break; 1955 case ISD::SETUGE: X86CC = X86::COND_AE; break; 1956 } 1957 } else { 1958 // On a floating point condition, the flags are set as follows: 1959 // ZF PF CF op 1960 // 0 | 0 | 0 | X > Y 1961 // 0 | 0 | 1 | X < Y 1962 // 1 | 0 | 0 | X == Y 1963 // 1 | 1 | 1 | unordered 1964 bool Flip = false; 1965 switch (SetCCOpcode) { 1966 default: break; 1967 case ISD::SETUEQ: 1968 case ISD::SETEQ: X86CC = X86::COND_E; break; 1969 case ISD::SETOLT: Flip = true; // Fallthrough 1970 case ISD::SETOGT: 1971 case ISD::SETGT: X86CC = X86::COND_A; break; 1972 case ISD::SETOLE: Flip = true; // Fallthrough 1973 case ISD::SETOGE: 1974 case ISD::SETGE: X86CC = X86::COND_AE; break; 1975 case ISD::SETUGT: Flip = true; // Fallthrough 1976 case ISD::SETULT: 1977 case ISD::SETLT: X86CC = X86::COND_B; break; 1978 case ISD::SETUGE: Flip = true; // Fallthrough 1979 case ISD::SETULE: 1980 case ISD::SETLE: X86CC = X86::COND_BE; break; 1981 case ISD::SETONE: 1982 case ISD::SETNE: X86CC = X86::COND_NE; break; 1983 case ISD::SETUO: X86CC = X86::COND_P; break; 1984 case ISD::SETO: X86CC = X86::COND_NP; break; 1985 } 1986 if (Flip) 1987 std::swap(LHS, RHS); 1988 } 1989 1990 return X86CC != X86::COND_INVALID; 1991} 1992 1993/// hasFPCMov - is there a floating point cmov for the specific X86 condition 1994/// code. Current x86 isa includes the following FP cmov instructions: 1995/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 1996static bool hasFPCMov(unsigned X86CC) { 1997 switch (X86CC) { 1998 default: 1999 return false; 2000 case X86::COND_B: 2001 case X86::COND_BE: 2002 case X86::COND_E: 2003 case X86::COND_P: 2004 case X86::COND_A: 2005 case X86::COND_AE: 2006 case X86::COND_NE: 2007 case X86::COND_NP: 2008 return true; 2009 } 2010} 2011 2012/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 2013/// true if Op is undef or if its value falls within the specified range (L, H]. 2014static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) { 2015 if (Op.getOpcode() == ISD::UNDEF) 2016 return true; 2017 2018 unsigned Val = cast<ConstantSDNode>(Op)->getValue(); 2019 return (Val >= Low && Val < Hi); 2020} 2021 2022/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 2023/// true if Op is undef or if its value equal to the specified value. 2024static bool isUndefOrEqual(SDValue Op, unsigned Val) { 2025 if (Op.getOpcode() == ISD::UNDEF) 2026 return true; 2027 return cast<ConstantSDNode>(Op)->getValue() == Val; 2028} 2029 2030/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 2031/// specifies a shuffle of elements that is suitable for input to PSHUFD. 2032bool X86::isPSHUFDMask(SDNode *N) { 2033 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2034 2035 if (N->getNumOperands() != 2 && N->getNumOperands() != 4) 2036 return false; 2037 2038 // Check if the value doesn't reference the second vector. 2039 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2040 SDValue Arg = N->getOperand(i); 2041 if (Arg.getOpcode() == ISD::UNDEF) continue; 2042 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2043 if (cast<ConstantSDNode>(Arg)->getValue() >= e) 2044 return false; 2045 } 2046 2047 return true; 2048} 2049 2050/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 2051/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 2052bool X86::isPSHUFHWMask(SDNode *N) { 2053 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2054 2055 if (N->getNumOperands() != 8) 2056 return false; 2057 2058 // Lower quadword copied in order. 2059 for (unsigned i = 0; i != 4; ++i) { 2060 SDValue Arg = N->getOperand(i); 2061 if (Arg.getOpcode() == ISD::UNDEF) continue; 2062 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2063 if (cast<ConstantSDNode>(Arg)->getValue() != i) 2064 return false; 2065 } 2066 2067 // Upper quadword shuffled. 2068 for (unsigned i = 4; i != 8; ++i) { 2069 SDValue Arg = N->getOperand(i); 2070 if (Arg.getOpcode() == ISD::UNDEF) continue; 2071 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2072 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2073 if (Val < 4 || Val > 7) 2074 return false; 2075 } 2076 2077 return true; 2078} 2079 2080/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 2081/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 2082bool X86::isPSHUFLWMask(SDNode *N) { 2083 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2084 2085 if (N->getNumOperands() != 8) 2086 return false; 2087 2088 // Upper quadword copied in order. 2089 for (unsigned i = 4; i != 8; ++i) 2090 if (!isUndefOrEqual(N->getOperand(i), i)) 2091 return false; 2092 2093 // Lower quadword shuffled. 2094 for (unsigned i = 0; i != 4; ++i) 2095 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 2096 return false; 2097 2098 return true; 2099} 2100 2101/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2102/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2103static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) { 2104 if (NumElems != 2 && NumElems != 4) return false; 2105 2106 unsigned Half = NumElems / 2; 2107 for (unsigned i = 0; i < Half; ++i) 2108 if (!isUndefOrInRange(Elems[i], 0, NumElems)) 2109 return false; 2110 for (unsigned i = Half; i < NumElems; ++i) 2111 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) 2112 return false; 2113 2114 return true; 2115} 2116 2117bool X86::isSHUFPMask(SDNode *N) { 2118 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2119 return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); 2120} 2121 2122/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2123/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2124/// half elements to come from vector 1 (which would equal the dest.) and 2125/// the upper half to come from vector 2. 2126static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) { 2127 if (NumOps != 2 && NumOps != 4) return false; 2128 2129 unsigned Half = NumOps / 2; 2130 for (unsigned i = 0; i < Half; ++i) 2131 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) 2132 return false; 2133 for (unsigned i = Half; i < NumOps; ++i) 2134 if (!isUndefOrInRange(Ops[i], 0, NumOps)) 2135 return false; 2136 return true; 2137} 2138 2139static bool isCommutedSHUFP(SDNode *N) { 2140 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2141 return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); 2142} 2143 2144/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2145/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2146bool X86::isMOVHLPSMask(SDNode *N) { 2147 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2148 2149 if (N->getNumOperands() != 4) 2150 return false; 2151 2152 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2153 return isUndefOrEqual(N->getOperand(0), 6) && 2154 isUndefOrEqual(N->getOperand(1), 7) && 2155 isUndefOrEqual(N->getOperand(2), 2) && 2156 isUndefOrEqual(N->getOperand(3), 3); 2157} 2158 2159/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2160/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2161/// <2, 3, 2, 3> 2162bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 2163 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2164 2165 if (N->getNumOperands() != 4) 2166 return false; 2167 2168 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 2169 return isUndefOrEqual(N->getOperand(0), 2) && 2170 isUndefOrEqual(N->getOperand(1), 3) && 2171 isUndefOrEqual(N->getOperand(2), 2) && 2172 isUndefOrEqual(N->getOperand(3), 3); 2173} 2174 2175/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2176/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2177bool X86::isMOVLPMask(SDNode *N) { 2178 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2179 2180 unsigned NumElems = N->getNumOperands(); 2181 if (NumElems != 2 && NumElems != 4) 2182 return false; 2183 2184 for (unsigned i = 0; i < NumElems/2; ++i) 2185 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2186 return false; 2187 2188 for (unsigned i = NumElems/2; i < NumElems; ++i) 2189 if (!isUndefOrEqual(N->getOperand(i), i)) 2190 return false; 2191 2192 return true; 2193} 2194 2195/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2196/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2197/// and MOVLHPS. 2198bool X86::isMOVHPMask(SDNode *N) { 2199 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2200 2201 unsigned NumElems = N->getNumOperands(); 2202 if (NumElems != 2 && NumElems != 4) 2203 return false; 2204 2205 for (unsigned i = 0; i < NumElems/2; ++i) 2206 if (!isUndefOrEqual(N->getOperand(i), i)) 2207 return false; 2208 2209 for (unsigned i = 0; i < NumElems/2; ++i) { 2210 SDValue Arg = N->getOperand(i + NumElems/2); 2211 if (!isUndefOrEqual(Arg, i + NumElems)) 2212 return false; 2213 } 2214 2215 return true; 2216} 2217 2218/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2219/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2220bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts, 2221 bool V2IsSplat = false) { 2222 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2223 return false; 2224 2225 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2226 SDValue BitI = Elts[i]; 2227 SDValue BitI1 = Elts[i+1]; 2228 if (!isUndefOrEqual(BitI, j)) 2229 return false; 2230 if (V2IsSplat) { 2231 if (isUndefOrEqual(BitI1, NumElts)) 2232 return false; 2233 } else { 2234 if (!isUndefOrEqual(BitI1, j + NumElts)) 2235 return false; 2236 } 2237 } 2238 2239 return true; 2240} 2241 2242bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2243 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2244 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2245} 2246 2247/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2248/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2249bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts, 2250 bool V2IsSplat = false) { 2251 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2252 return false; 2253 2254 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2255 SDValue BitI = Elts[i]; 2256 SDValue BitI1 = Elts[i+1]; 2257 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2258 return false; 2259 if (V2IsSplat) { 2260 if (isUndefOrEqual(BitI1, NumElts)) 2261 return false; 2262 } else { 2263 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2264 return false; 2265 } 2266 } 2267 2268 return true; 2269} 2270 2271bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2272 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2273 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2274} 2275 2276/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2277/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2278/// <0, 0, 1, 1> 2279bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2280 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2281 2282 unsigned NumElems = N->getNumOperands(); 2283 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2284 return false; 2285 2286 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2287 SDValue BitI = N->getOperand(i); 2288 SDValue BitI1 = N->getOperand(i+1); 2289 2290 if (!isUndefOrEqual(BitI, j)) 2291 return false; 2292 if (!isUndefOrEqual(BitI1, j)) 2293 return false; 2294 } 2295 2296 return true; 2297} 2298 2299/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2300/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2301/// <2, 2, 3, 3> 2302bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { 2303 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2304 2305 unsigned NumElems = N->getNumOperands(); 2306 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2307 return false; 2308 2309 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2310 SDValue BitI = N->getOperand(i); 2311 SDValue BitI1 = N->getOperand(i + 1); 2312 2313 if (!isUndefOrEqual(BitI, j)) 2314 return false; 2315 if (!isUndefOrEqual(BitI1, j)) 2316 return false; 2317 } 2318 2319 return true; 2320} 2321 2322/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2323/// specifies a shuffle of elements that is suitable for input to MOVSS, 2324/// MOVSD, and MOVD, i.e. setting the lowest element. 2325static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) { 2326 if (NumElts != 2 && NumElts != 4) 2327 return false; 2328 2329 if (!isUndefOrEqual(Elts[0], NumElts)) 2330 return false; 2331 2332 for (unsigned i = 1; i < NumElts; ++i) { 2333 if (!isUndefOrEqual(Elts[i], i)) 2334 return false; 2335 } 2336 2337 return true; 2338} 2339 2340bool X86::isMOVLMask(SDNode *N) { 2341 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2342 return ::isMOVLMask(N->op_begin(), N->getNumOperands()); 2343} 2344 2345/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2346/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2347/// element of vector 2 and the other elements to come from vector 1 in order. 2348static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps, 2349 bool V2IsSplat = false, 2350 bool V2IsUndef = false) { 2351 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2352 return false; 2353 2354 if (!isUndefOrEqual(Ops[0], 0)) 2355 return false; 2356 2357 for (unsigned i = 1; i < NumOps; ++i) { 2358 SDValue Arg = Ops[i]; 2359 if (!(isUndefOrEqual(Arg, i+NumOps) || 2360 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || 2361 (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) 2362 return false; 2363 } 2364 2365 return true; 2366} 2367 2368static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2369 bool V2IsUndef = false) { 2370 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2371 return isCommutedMOVL(N->op_begin(), N->getNumOperands(), 2372 V2IsSplat, V2IsUndef); 2373} 2374 2375/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2376/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2377bool X86::isMOVSHDUPMask(SDNode *N) { 2378 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2379 2380 if (N->getNumOperands() != 4) 2381 return false; 2382 2383 // Expect 1, 1, 3, 3 2384 for (unsigned i = 0; i < 2; ++i) { 2385 SDValue Arg = N->getOperand(i); 2386 if (Arg.getOpcode() == ISD::UNDEF) continue; 2387 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2388 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2389 if (Val != 1) return false; 2390 } 2391 2392 bool HasHi = false; 2393 for (unsigned i = 2; i < 4; ++i) { 2394 SDValue Arg = N->getOperand(i); 2395 if (Arg.getOpcode() == ISD::UNDEF) continue; 2396 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2397 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2398 if (Val != 3) return false; 2399 HasHi = true; 2400 } 2401 2402 // Don't use movshdup if it can be done with a shufps. 2403 return HasHi; 2404} 2405 2406/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2407/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2408bool X86::isMOVSLDUPMask(SDNode *N) { 2409 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2410 2411 if (N->getNumOperands() != 4) 2412 return false; 2413 2414 // Expect 0, 0, 2, 2 2415 for (unsigned i = 0; i < 2; ++i) { 2416 SDValue Arg = N->getOperand(i); 2417 if (Arg.getOpcode() == ISD::UNDEF) continue; 2418 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2419 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2420 if (Val != 0) return false; 2421 } 2422 2423 bool HasHi = false; 2424 for (unsigned i = 2; i < 4; ++i) { 2425 SDValue Arg = N->getOperand(i); 2426 if (Arg.getOpcode() == ISD::UNDEF) continue; 2427 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2428 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2429 if (Val != 2) return false; 2430 HasHi = true; 2431 } 2432 2433 // Don't use movshdup if it can be done with a shufps. 2434 return HasHi; 2435} 2436 2437/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand 2438/// specifies a identity operation on the LHS or RHS. 2439static bool isIdentityMask(SDNode *N, bool RHS = false) { 2440 unsigned NumElems = N->getNumOperands(); 2441 for (unsigned i = 0; i < NumElems; ++i) 2442 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0))) 2443 return false; 2444 return true; 2445} 2446 2447/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2448/// a splat of a single element. 2449static bool isSplatMask(SDNode *N) { 2450 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2451 2452 // This is a splat operation if each element of the permute is the same, and 2453 // if the value doesn't reference the second vector. 2454 unsigned NumElems = N->getNumOperands(); 2455 SDValue ElementBase; 2456 unsigned i = 0; 2457 for (; i != NumElems; ++i) { 2458 SDValue Elt = N->getOperand(i); 2459 if (isa<ConstantSDNode>(Elt)) { 2460 ElementBase = Elt; 2461 break; 2462 } 2463 } 2464 2465 if (!ElementBase.Val) 2466 return false; 2467 2468 for (; i != NumElems; ++i) { 2469 SDValue Arg = N->getOperand(i); 2470 if (Arg.getOpcode() == ISD::UNDEF) continue; 2471 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2472 if (Arg != ElementBase) return false; 2473 } 2474 2475 // Make sure it is a splat of the first vector operand. 2476 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems; 2477} 2478 2479/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2480/// a splat of a single element and it's a 2 or 4 element mask. 2481bool X86::isSplatMask(SDNode *N) { 2482 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2483 2484 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2485 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2486 return false; 2487 return ::isSplatMask(N); 2488} 2489 2490/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 2491/// specifies a splat of zero element. 2492bool X86::isSplatLoMask(SDNode *N) { 2493 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2494 2495 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 2496 if (!isUndefOrEqual(N->getOperand(i), 0)) 2497 return false; 2498 return true; 2499} 2500 2501/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2502/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2503/// instructions. 2504unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2505 unsigned NumOperands = N->getNumOperands(); 2506 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2507 unsigned Mask = 0; 2508 for (unsigned i = 0; i < NumOperands; ++i) { 2509 unsigned Val = 0; 2510 SDValue Arg = N->getOperand(NumOperands-i-1); 2511 if (Arg.getOpcode() != ISD::UNDEF) 2512 Val = cast<ConstantSDNode>(Arg)->getValue(); 2513 if (Val >= NumOperands) Val -= NumOperands; 2514 Mask |= Val; 2515 if (i != NumOperands - 1) 2516 Mask <<= Shift; 2517 } 2518 2519 return Mask; 2520} 2521 2522/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2523/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2524/// instructions. 2525unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2526 unsigned Mask = 0; 2527 // 8 nodes, but we only care about the last 4. 2528 for (unsigned i = 7; i >= 4; --i) { 2529 unsigned Val = 0; 2530 SDValue Arg = N->getOperand(i); 2531 if (Arg.getOpcode() != ISD::UNDEF) 2532 Val = cast<ConstantSDNode>(Arg)->getValue(); 2533 Mask |= (Val - 4); 2534 if (i != 4) 2535 Mask <<= 2; 2536 } 2537 2538 return Mask; 2539} 2540 2541/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2542/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2543/// instructions. 2544unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2545 unsigned Mask = 0; 2546 // 8 nodes, but we only care about the first 4. 2547 for (int i = 3; i >= 0; --i) { 2548 unsigned Val = 0; 2549 SDValue Arg = N->getOperand(i); 2550 if (Arg.getOpcode() != ISD::UNDEF) 2551 Val = cast<ConstantSDNode>(Arg)->getValue(); 2552 Mask |= Val; 2553 if (i != 0) 2554 Mask <<= 2; 2555 } 2556 2557 return Mask; 2558} 2559 2560/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2561/// specifies a 8 element shuffle that can be broken into a pair of 2562/// PSHUFHW and PSHUFLW. 2563static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2564 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2565 2566 if (N->getNumOperands() != 8) 2567 return false; 2568 2569 // Lower quadword shuffled. 2570 for (unsigned i = 0; i != 4; ++i) { 2571 SDValue Arg = N->getOperand(i); 2572 if (Arg.getOpcode() == ISD::UNDEF) continue; 2573 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2574 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2575 if (Val >= 4) 2576 return false; 2577 } 2578 2579 // Upper quadword shuffled. 2580 for (unsigned i = 4; i != 8; ++i) { 2581 SDValue Arg = N->getOperand(i); 2582 if (Arg.getOpcode() == ISD::UNDEF) continue; 2583 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2584 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2585 if (Val < 4 || Val > 7) 2586 return false; 2587 } 2588 2589 return true; 2590} 2591 2592/// CommuteVectorShuffle - Swap vector_shuffle operands as well as 2593/// values in ther permute mask. 2594static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1, 2595 SDValue &V2, SDValue &Mask, 2596 SelectionDAG &DAG) { 2597 MVT VT = Op.getValueType(); 2598 MVT MaskVT = Mask.getValueType(); 2599 MVT EltVT = MaskVT.getVectorElementType(); 2600 unsigned NumElems = Mask.getNumOperands(); 2601 SmallVector<SDValue, 8> MaskVec; 2602 2603 for (unsigned i = 0; i != NumElems; ++i) { 2604 SDValue Arg = Mask.getOperand(i); 2605 if (Arg.getOpcode() == ISD::UNDEF) { 2606 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2607 continue; 2608 } 2609 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2610 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2611 if (Val < NumElems) 2612 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2613 else 2614 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2615 } 2616 2617 std::swap(V1, V2); 2618 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2619 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2620} 2621 2622/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2623/// the two vector operands have swapped position. 2624static 2625SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) { 2626 MVT MaskVT = Mask.getValueType(); 2627 MVT EltVT = MaskVT.getVectorElementType(); 2628 unsigned NumElems = Mask.getNumOperands(); 2629 SmallVector<SDValue, 8> MaskVec; 2630 for (unsigned i = 0; i != NumElems; ++i) { 2631 SDValue Arg = Mask.getOperand(i); 2632 if (Arg.getOpcode() == ISD::UNDEF) { 2633 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2634 continue; 2635 } 2636 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2637 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2638 if (Val < NumElems) 2639 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2640 else 2641 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2642 } 2643 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2644} 2645 2646 2647/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2648/// match movhlps. The lower half elements should come from upper half of 2649/// V1 (and in order), and the upper half elements should come from the upper 2650/// half of V2 (and in order). 2651static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2652 unsigned NumElems = Mask->getNumOperands(); 2653 if (NumElems != 4) 2654 return false; 2655 for (unsigned i = 0, e = 2; i != e; ++i) 2656 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2657 return false; 2658 for (unsigned i = 2; i != 4; ++i) 2659 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2660 return false; 2661 return true; 2662} 2663 2664/// isScalarLoadToVector - Returns true if the node is a scalar load that 2665/// is promoted to a vector. It also returns the LoadSDNode by reference if 2666/// required. 2667static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2668 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { 2669 N = N->getOperand(0).Val; 2670 if (ISD::isNON_EXTLoad(N)) { 2671 if (LD) 2672 *LD = cast<LoadSDNode>(N); 2673 return true; 2674 } 2675 } 2676 return false; 2677} 2678 2679/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2680/// match movlp{s|d}. The lower half elements should come from lower half of 2681/// V1 (and in order), and the upper half elements should come from the upper 2682/// half of V2 (and in order). And since V1 will become the source of the 2683/// MOVLP, it must be either a vector load or a scalar load to vector. 2684static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2685 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2686 return false; 2687 // Is V2 is a vector load, don't do this transformation. We will try to use 2688 // load folding shufps op. 2689 if (ISD::isNON_EXTLoad(V2)) 2690 return false; 2691 2692 unsigned NumElems = Mask->getNumOperands(); 2693 if (NumElems != 2 && NumElems != 4) 2694 return false; 2695 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2696 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2697 return false; 2698 for (unsigned i = NumElems/2; i != NumElems; ++i) 2699 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2700 return false; 2701 return true; 2702} 2703 2704/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2705/// all the same. 2706static bool isSplatVector(SDNode *N) { 2707 if (N->getOpcode() != ISD::BUILD_VECTOR) 2708 return false; 2709 2710 SDValue SplatValue = N->getOperand(0); 2711 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2712 if (N->getOperand(i) != SplatValue) 2713 return false; 2714 return true; 2715} 2716 2717/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2718/// to an undef. 2719static bool isUndefShuffle(SDNode *N) { 2720 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2721 return false; 2722 2723 SDValue V1 = N->getOperand(0); 2724 SDValue V2 = N->getOperand(1); 2725 SDValue Mask = N->getOperand(2); 2726 unsigned NumElems = Mask.getNumOperands(); 2727 for (unsigned i = 0; i != NumElems; ++i) { 2728 SDValue Arg = Mask.getOperand(i); 2729 if (Arg.getOpcode() != ISD::UNDEF) { 2730 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2731 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2732 return false; 2733 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2734 return false; 2735 } 2736 } 2737 return true; 2738} 2739 2740/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2741/// constant +0.0. 2742static inline bool isZeroNode(SDValue Elt) { 2743 return ((isa<ConstantSDNode>(Elt) && 2744 cast<ConstantSDNode>(Elt)->getValue() == 0) || 2745 (isa<ConstantFPSDNode>(Elt) && 2746 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2747} 2748 2749/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2750/// to an zero vector. 2751static bool isZeroShuffle(SDNode *N) { 2752 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2753 return false; 2754 2755 SDValue V1 = N->getOperand(0); 2756 SDValue V2 = N->getOperand(1); 2757 SDValue Mask = N->getOperand(2); 2758 unsigned NumElems = Mask.getNumOperands(); 2759 for (unsigned i = 0; i != NumElems; ++i) { 2760 SDValue Arg = Mask.getOperand(i); 2761 if (Arg.getOpcode() == ISD::UNDEF) 2762 continue; 2763 2764 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 2765 if (Idx < NumElems) { 2766 unsigned Opc = V1.Val->getOpcode(); 2767 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val)) 2768 continue; 2769 if (Opc != ISD::BUILD_VECTOR || 2770 !isZeroNode(V1.Val->getOperand(Idx))) 2771 return false; 2772 } else if (Idx >= NumElems) { 2773 unsigned Opc = V2.Val->getOpcode(); 2774 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val)) 2775 continue; 2776 if (Opc != ISD::BUILD_VECTOR || 2777 !isZeroNode(V2.Val->getOperand(Idx - NumElems))) 2778 return false; 2779 } 2780 } 2781 return true; 2782} 2783 2784/// getZeroVector - Returns a vector of specified type with all zero elements. 2785/// 2786static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) { 2787 assert(VT.isVector() && "Expected a vector type"); 2788 2789 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2790 // type. This ensures they get CSE'd. 2791 SDValue Vec; 2792 if (VT.getSizeInBits() == 64) { // MMX 2793 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2794 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2795 } else if (HasSSE2) { // SSE2 2796 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2797 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2798 } else { // SSE1 2799 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2800 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst); 2801 } 2802 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2803} 2804 2805/// getOnesVector - Returns a vector of specified type with all bits set. 2806/// 2807static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) { 2808 assert(VT.isVector() && "Expected a vector type"); 2809 2810 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2811 // type. This ensures they get CSE'd. 2812 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2813 SDValue Vec; 2814 if (VT.getSizeInBits() == 64) // MMX 2815 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2816 else // SSE 2817 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2818 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2819} 2820 2821 2822/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2823/// that point to V2 points to its first element. 2824static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) { 2825 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2826 2827 bool Changed = false; 2828 SmallVector<SDValue, 8> MaskVec; 2829 unsigned NumElems = Mask.getNumOperands(); 2830 for (unsigned i = 0; i != NumElems; ++i) { 2831 SDValue Arg = Mask.getOperand(i); 2832 if (Arg.getOpcode() != ISD::UNDEF) { 2833 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2834 if (Val > NumElems) { 2835 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2836 Changed = true; 2837 } 2838 } 2839 MaskVec.push_back(Arg); 2840 } 2841 2842 if (Changed) 2843 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 2844 &MaskVec[0], MaskVec.size()); 2845 return Mask; 2846} 2847 2848/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2849/// operation of specified width. 2850static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 2851 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2852 MVT BaseVT = MaskVT.getVectorElementType(); 2853 2854 SmallVector<SDValue, 8> MaskVec; 2855 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2856 for (unsigned i = 1; i != NumElems; ++i) 2857 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2858 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2859} 2860 2861/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2862/// of specified width. 2863static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 2864 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2865 MVT BaseVT = MaskVT.getVectorElementType(); 2866 SmallVector<SDValue, 8> MaskVec; 2867 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2868 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2869 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 2870 } 2871 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2872} 2873 2874/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 2875/// of specified width. 2876static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 2877 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2878 MVT BaseVT = MaskVT.getVectorElementType(); 2879 unsigned Half = NumElems/2; 2880 SmallVector<SDValue, 8> MaskVec; 2881 for (unsigned i = 0; i != Half; ++i) { 2882 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 2883 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 2884 } 2885 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2886} 2887 2888/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps 2889/// element #0 of a vector with the specified index, leaving the rest of the 2890/// elements in place. 2891static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, 2892 SelectionDAG &DAG) { 2893 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2894 MVT BaseVT = MaskVT.getVectorElementType(); 2895 SmallVector<SDValue, 8> MaskVec; 2896 // Element #0 of the result gets the elt we are replacing. 2897 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); 2898 for (unsigned i = 1; i != NumElems; ++i) 2899 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); 2900 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2901} 2902 2903/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 2904static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) { 2905 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32; 2906 MVT VT = Op.getValueType(); 2907 if (PVT == VT) 2908 return Op; 2909 SDValue V1 = Op.getOperand(0); 2910 SDValue Mask = Op.getOperand(2); 2911 unsigned NumElems = Mask.getNumOperands(); 2912 // Special handling of v4f32 -> v4i32. 2913 if (VT != MVT::v4f32) { 2914 Mask = getUnpacklMask(NumElems, DAG); 2915 while (NumElems > 4) { 2916 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 2917 NumElems >>= 1; 2918 } 2919 Mask = getZeroVector(MVT::v4i32, true, DAG); 2920 } 2921 2922 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1); 2923 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1, 2924 DAG.getNode(ISD::UNDEF, PVT), Mask); 2925 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 2926} 2927 2928/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 2929/// vector of zero or undef vector. This produces a shuffle where the low 2930/// element of V2 is swizzled into the zero/undef vector, landing at element 2931/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 2932static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 2933 bool isZero, bool HasSSE2, 2934 SelectionDAG &DAG) { 2935 MVT VT = V2.getValueType(); 2936 SDValue V1 = isZero 2937 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT); 2938 unsigned NumElems = V2.getValueType().getVectorNumElements(); 2939 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2940 MVT EVT = MaskVT.getVectorElementType(); 2941 SmallVector<SDValue, 16> MaskVec; 2942 for (unsigned i = 0; i != NumElems; ++i) 2943 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. 2944 MaskVec.push_back(DAG.getConstant(NumElems, EVT)); 2945 else 2946 MaskVec.push_back(DAG.getConstant(i, EVT)); 2947 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2948 &MaskVec[0], MaskVec.size()); 2949 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2950} 2951 2952/// getNumOfConsecutiveZeros - Return the number of elements in a result of 2953/// a shuffle that is zero. 2954static 2955unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask, 2956 unsigned NumElems, bool Low, 2957 SelectionDAG &DAG) { 2958 unsigned NumZeros = 0; 2959 for (unsigned i = 0; i < NumElems; ++i) { 2960 unsigned Index = Low ? i : NumElems-i-1; 2961 SDValue Idx = Mask.getOperand(Index); 2962 if (Idx.getOpcode() == ISD::UNDEF) { 2963 ++NumZeros; 2964 continue; 2965 } 2966 SDValue Elt = DAG.getShuffleScalarElt(Op.Val, Index); 2967 if (Elt.Val && isZeroNode(Elt)) 2968 ++NumZeros; 2969 else 2970 break; 2971 } 2972 return NumZeros; 2973} 2974 2975/// isVectorShift - Returns true if the shuffle can be implemented as a 2976/// logical left or right shift of a vector. 2977static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG, 2978 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 2979 unsigned NumElems = Mask.getNumOperands(); 2980 2981 isLeft = true; 2982 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG); 2983 if (!NumZeros) { 2984 isLeft = false; 2985 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG); 2986 if (!NumZeros) 2987 return false; 2988 } 2989 2990 bool SeenV1 = false; 2991 bool SeenV2 = false; 2992 for (unsigned i = NumZeros; i < NumElems; ++i) { 2993 unsigned Val = isLeft ? (i - NumZeros) : i; 2994 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros)); 2995 if (Idx.getOpcode() == ISD::UNDEF) 2996 continue; 2997 unsigned Index = cast<ConstantSDNode>(Idx)->getValue(); 2998 if (Index < NumElems) 2999 SeenV1 = true; 3000 else { 3001 Index -= NumElems; 3002 SeenV2 = true; 3003 } 3004 if (Index != Val) 3005 return false; 3006 } 3007 if (SeenV1 && SeenV2) 3008 return false; 3009 3010 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1); 3011 ShAmt = NumZeros; 3012 return true; 3013} 3014 3015 3016/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3017/// 3018static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3019 unsigned NumNonZero, unsigned NumZero, 3020 SelectionDAG &DAG, TargetLowering &TLI) { 3021 if (NumNonZero > 8) 3022 return SDValue(); 3023 3024 SDValue V(0, 0); 3025 bool First = true; 3026 for (unsigned i = 0; i < 16; ++i) { 3027 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3028 if (ThisIsNonZero && First) { 3029 if (NumZero) 3030 V = getZeroVector(MVT::v8i16, true, DAG); 3031 else 3032 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3033 First = false; 3034 } 3035 3036 if ((i & 1) != 0) { 3037 SDValue ThisElt(0, 0), LastElt(0, 0); 3038 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3039 if (LastIsNonZero) { 3040 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 3041 } 3042 if (ThisIsNonZero) { 3043 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 3044 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 3045 ThisElt, DAG.getConstant(8, MVT::i8)); 3046 if (LastIsNonZero) 3047 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 3048 } else 3049 ThisElt = LastElt; 3050 3051 if (ThisElt.Val) 3052 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 3053 DAG.getIntPtrConstant(i/2)); 3054 } 3055 } 3056 3057 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 3058} 3059 3060/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3061/// 3062static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3063 unsigned NumNonZero, unsigned NumZero, 3064 SelectionDAG &DAG, TargetLowering &TLI) { 3065 if (NumNonZero > 4) 3066 return SDValue(); 3067 3068 SDValue V(0, 0); 3069 bool First = true; 3070 for (unsigned i = 0; i < 8; ++i) { 3071 bool isNonZero = (NonZeros & (1 << i)) != 0; 3072 if (isNonZero) { 3073 if (First) { 3074 if (NumZero) 3075 V = getZeroVector(MVT::v8i16, true, DAG); 3076 else 3077 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 3078 First = false; 3079 } 3080 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 3081 DAG.getIntPtrConstant(i)); 3082 } 3083 } 3084 3085 return V; 3086} 3087 3088/// getVShift - Return a vector logical shift node. 3089/// 3090static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, 3091 unsigned NumBits, SelectionDAG &DAG, 3092 const TargetLowering &TLI) { 3093 bool isMMX = VT.getSizeInBits() == 64; 3094 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3095 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3096 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp); 3097 return DAG.getNode(ISD::BIT_CONVERT, VT, 3098 DAG.getNode(Opc, ShVT, SrcOp, 3099 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3100} 3101 3102SDValue 3103X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3104 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3105 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) { 3106 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3107 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3108 // eliminated on x86-32 hosts. 3109 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3110 return Op; 3111 3112 if (ISD::isBuildVectorAllOnes(Op.Val)) 3113 return getOnesVector(Op.getValueType(), DAG); 3114 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG); 3115 } 3116 3117 MVT VT = Op.getValueType(); 3118 MVT EVT = VT.getVectorElementType(); 3119 unsigned EVTBits = EVT.getSizeInBits(); 3120 3121 unsigned NumElems = Op.getNumOperands(); 3122 unsigned NumZero = 0; 3123 unsigned NumNonZero = 0; 3124 unsigned NonZeros = 0; 3125 bool IsAllConstants = true; 3126 SmallSet<SDValue, 8> Values; 3127 for (unsigned i = 0; i < NumElems; ++i) { 3128 SDValue Elt = Op.getOperand(i); 3129 if (Elt.getOpcode() == ISD::UNDEF) 3130 continue; 3131 Values.insert(Elt); 3132 if (Elt.getOpcode() != ISD::Constant && 3133 Elt.getOpcode() != ISD::ConstantFP) 3134 IsAllConstants = false; 3135 if (isZeroNode(Elt)) 3136 NumZero++; 3137 else { 3138 NonZeros |= (1 << i); 3139 NumNonZero++; 3140 } 3141 } 3142 3143 if (NumNonZero == 0) { 3144 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3145 return DAG.getNode(ISD::UNDEF, VT); 3146 } 3147 3148 // Special case for single non-zero, non-undef, element. 3149 if (NumNonZero == 1 && NumElems <= 4) { 3150 unsigned Idx = CountTrailingZeros_32(NonZeros); 3151 SDValue Item = Op.getOperand(Idx); 3152 3153 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3154 // the value are obviously zero, truncate the value to i32 and do the 3155 // insertion that way. Only do this if the value is non-constant or if the 3156 // value is a constant being inserted into element 0. It is cheaper to do 3157 // a constant pool load than it is to do a movd + shuffle. 3158 if (EVT == MVT::i64 && !Subtarget->is64Bit() && 3159 (!IsAllConstants || Idx == 0)) { 3160 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3161 // Handle MMX and SSE both. 3162 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3163 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3164 3165 // Truncate the value (which may itself be a constant) to i32, and 3166 // convert it to a vector with movd (S2V+shuffle to zero extend). 3167 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item); 3168 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item); 3169 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3170 Subtarget->hasSSE2(), DAG); 3171 3172 // Now we have our 32-bit value zero extended in the low element of 3173 // a vector. If Idx != 0, swizzle it into place. 3174 if (Idx != 0) { 3175 SDValue Ops[] = { 3176 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), 3177 getSwapEltZeroMask(VecElts, Idx, DAG) 3178 }; 3179 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3); 3180 } 3181 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item); 3182 } 3183 } 3184 3185 // If we have a constant or non-constant insertion into the low element of 3186 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3187 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3188 // depending on what the source datatype is. Because we can only get here 3189 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64. 3190 if (Idx == 0 && 3191 // Don't do this for i64 values on x86-32. 3192 (EVT != MVT::i64 || Subtarget->is64Bit())) { 3193 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3194 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3195 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3196 Subtarget->hasSSE2(), DAG); 3197 } 3198 3199 // Is it a vector logical left shift? 3200 if (NumElems == 2 && Idx == 1 && 3201 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) { 3202 unsigned NumBits = VT.getSizeInBits(); 3203 return getVShift(true, VT, 3204 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)), 3205 NumBits/2, DAG, *this); 3206 } 3207 3208 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3209 return SDValue(); 3210 3211 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3212 // is a non-constant being inserted into an element other than the low one, 3213 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3214 // movd/movss) to move this into the low element, then shuffle it into 3215 // place. 3216 if (EVTBits == 32) { 3217 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3218 3219 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3220 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3221 Subtarget->hasSSE2(), DAG); 3222 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3223 MVT MaskEVT = MaskVT.getVectorElementType(); 3224 SmallVector<SDValue, 8> MaskVec; 3225 for (unsigned i = 0; i < NumElems; i++) 3226 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 3227 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3228 &MaskVec[0], MaskVec.size()); 3229 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 3230 DAG.getNode(ISD::UNDEF, VT), Mask); 3231 } 3232 } 3233 3234 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3235 if (Values.size() == 1) 3236 return SDValue(); 3237 3238 // A vector full of immediates; various special cases are already 3239 // handled, so this is best done with a single constant-pool load. 3240 if (IsAllConstants) 3241 return SDValue(); 3242 3243 // Let legalizer expand 2-wide build_vectors. 3244 if (EVTBits == 64) { 3245 if (NumNonZero == 1) { 3246 // One half is zero or undef. 3247 unsigned Idx = CountTrailingZeros_32(NonZeros); 3248 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, 3249 Op.getOperand(Idx)); 3250 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3251 Subtarget->hasSSE2(), DAG); 3252 } 3253 return SDValue(); 3254 } 3255 3256 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3257 if (EVTBits == 8 && NumElems == 16) { 3258 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3259 *this); 3260 if (V.Val) return V; 3261 } 3262 3263 if (EVTBits == 16 && NumElems == 8) { 3264 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3265 *this); 3266 if (V.Val) return V; 3267 } 3268 3269 // If element VT is == 32 bits, turn it into a number of shuffles. 3270 SmallVector<SDValue, 8> V; 3271 V.resize(NumElems); 3272 if (NumElems == 4 && NumZero > 0) { 3273 for (unsigned i = 0; i < 4; ++i) { 3274 bool isZero = !(NonZeros & (1 << i)); 3275 if (isZero) 3276 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG); 3277 else 3278 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3279 } 3280 3281 for (unsigned i = 0; i < 2; ++i) { 3282 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3283 default: break; 3284 case 0: 3285 V[i] = V[i*2]; // Must be a zero vector. 3286 break; 3287 case 1: 3288 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 3289 getMOVLMask(NumElems, DAG)); 3290 break; 3291 case 2: 3292 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3293 getMOVLMask(NumElems, DAG)); 3294 break; 3295 case 3: 3296 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3297 getUnpacklMask(NumElems, DAG)); 3298 break; 3299 } 3300 } 3301 3302 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3303 MVT EVT = MaskVT.getVectorElementType(); 3304 SmallVector<SDValue, 8> MaskVec; 3305 bool Reverse = (NonZeros & 0x3) == 2; 3306 for (unsigned i = 0; i < 2; ++i) 3307 if (Reverse) 3308 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3309 else 3310 MaskVec.push_back(DAG.getConstant(i, EVT)); 3311 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3312 for (unsigned i = 0; i < 2; ++i) 3313 if (Reverse) 3314 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3315 else 3316 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3317 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3318 &MaskVec[0], MaskVec.size()); 3319 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 3320 } 3321 3322 if (Values.size() > 2) { 3323 // Expand into a number of unpckl*. 3324 // e.g. for v4f32 3325 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3326 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3327 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3328 SDValue UnpckMask = getUnpacklMask(NumElems, DAG); 3329 for (unsigned i = 0; i < NumElems; ++i) 3330 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3331 NumElems >>= 1; 3332 while (NumElems != 0) { 3333 for (unsigned i = 0; i < NumElems; ++i) 3334 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 3335 UnpckMask); 3336 NumElems >>= 1; 3337 } 3338 return V[0]; 3339 } 3340 3341 return SDValue(); 3342} 3343 3344static 3345SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2, 3346 SDValue PermMask, SelectionDAG &DAG, 3347 TargetLowering &TLI) { 3348 SDValue NewV; 3349 MVT MaskVT = MVT::getIntVectorWithNumElements(8); 3350 MVT MaskEVT = MaskVT.getVectorElementType(); 3351 MVT PtrVT = TLI.getPointerTy(); 3352 SmallVector<SDValue, 8> MaskElts(PermMask.Val->op_begin(), 3353 PermMask.Val->op_end()); 3354 3355 // First record which half of which vector the low elements come from. 3356 SmallVector<unsigned, 4> LowQuad(4); 3357 for (unsigned i = 0; i < 4; ++i) { 3358 SDValue Elt = MaskElts[i]; 3359 if (Elt.getOpcode() == ISD::UNDEF) 3360 continue; 3361 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3362 int QuadIdx = EltIdx / 4; 3363 ++LowQuad[QuadIdx]; 3364 } 3365 3366 int BestLowQuad = -1; 3367 unsigned MaxQuad = 1; 3368 for (unsigned i = 0; i < 4; ++i) { 3369 if (LowQuad[i] > MaxQuad) { 3370 BestLowQuad = i; 3371 MaxQuad = LowQuad[i]; 3372 } 3373 } 3374 3375 // Record which half of which vector the high elements come from. 3376 SmallVector<unsigned, 4> HighQuad(4); 3377 for (unsigned i = 4; i < 8; ++i) { 3378 SDValue Elt = MaskElts[i]; 3379 if (Elt.getOpcode() == ISD::UNDEF) 3380 continue; 3381 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3382 int QuadIdx = EltIdx / 4; 3383 ++HighQuad[QuadIdx]; 3384 } 3385 3386 int BestHighQuad = -1; 3387 MaxQuad = 1; 3388 for (unsigned i = 0; i < 4; ++i) { 3389 if (HighQuad[i] > MaxQuad) { 3390 BestHighQuad = i; 3391 MaxQuad = HighQuad[i]; 3392 } 3393 } 3394 3395 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it. 3396 if (BestLowQuad != -1 || BestHighQuad != -1) { 3397 // First sort the 4 chunks in order using shufpd. 3398 SmallVector<SDValue, 8> MaskVec; 3399 3400 if (BestLowQuad != -1) 3401 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32)); 3402 else 3403 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 3404 3405 if (BestHighQuad != -1) 3406 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32)); 3407 else 3408 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 3409 3410 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); 3411 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 3412 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), 3413 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); 3414 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV); 3415 3416 // Now sort high and low parts separately. 3417 BitVector InOrder(8); 3418 if (BestLowQuad != -1) { 3419 // Sort lower half in order using PSHUFLW. 3420 MaskVec.clear(); 3421 bool AnyOutOrder = false; 3422 3423 for (unsigned i = 0; i != 4; ++i) { 3424 SDValue Elt = MaskElts[i]; 3425 if (Elt.getOpcode() == ISD::UNDEF) { 3426 MaskVec.push_back(Elt); 3427 InOrder.set(i); 3428 } else { 3429 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3430 if (EltIdx != i) 3431 AnyOutOrder = true; 3432 3433 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT)); 3434 3435 // If this element is in the right place after this shuffle, then 3436 // remember it. 3437 if ((int)(EltIdx / 4) == BestLowQuad) 3438 InOrder.set(i); 3439 } 3440 } 3441 if (AnyOutOrder) { 3442 for (unsigned i = 4; i != 8; ++i) 3443 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3444 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3445 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3446 } 3447 } 3448 3449 if (BestHighQuad != -1) { 3450 // Sort high half in order using PSHUFHW if possible. 3451 MaskVec.clear(); 3452 3453 for (unsigned i = 0; i != 4; ++i) 3454 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3455 3456 bool AnyOutOrder = false; 3457 for (unsigned i = 4; i != 8; ++i) { 3458 SDValue Elt = MaskElts[i]; 3459 if (Elt.getOpcode() == ISD::UNDEF) { 3460 MaskVec.push_back(Elt); 3461 InOrder.set(i); 3462 } else { 3463 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3464 if (EltIdx != i) 3465 AnyOutOrder = true; 3466 3467 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT)); 3468 3469 // If this element is in the right place after this shuffle, then 3470 // remember it. 3471 if ((int)(EltIdx / 4) == BestHighQuad) 3472 InOrder.set(i); 3473 } 3474 } 3475 3476 if (AnyOutOrder) { 3477 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3478 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3479 } 3480 } 3481 3482 // The other elements are put in the right place using pextrw and pinsrw. 3483 for (unsigned i = 0; i != 8; ++i) { 3484 if (InOrder[i]) 3485 continue; 3486 SDValue Elt = MaskElts[i]; 3487 if (Elt.getOpcode() == ISD::UNDEF) 3488 continue; 3489 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3490 SDValue ExtOp = (EltIdx < 8) 3491 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3492 DAG.getConstant(EltIdx, PtrVT)) 3493 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3494 DAG.getConstant(EltIdx - 8, PtrVT)); 3495 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3496 DAG.getConstant(i, PtrVT)); 3497 } 3498 3499 return NewV; 3500 } 3501 3502 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as 3503 // few as possible. First, let's find out how many elements are already in the 3504 // right order. 3505 unsigned V1InOrder = 0; 3506 unsigned V1FromV1 = 0; 3507 unsigned V2InOrder = 0; 3508 unsigned V2FromV2 = 0; 3509 SmallVector<SDValue, 8> V1Elts; 3510 SmallVector<SDValue, 8> V2Elts; 3511 for (unsigned i = 0; i < 8; ++i) { 3512 SDValue Elt = MaskElts[i]; 3513 if (Elt.getOpcode() == ISD::UNDEF) { 3514 V1Elts.push_back(Elt); 3515 V2Elts.push_back(Elt); 3516 ++V1InOrder; 3517 ++V2InOrder; 3518 continue; 3519 } 3520 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3521 if (EltIdx == i) { 3522 V1Elts.push_back(Elt); 3523 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT)); 3524 ++V1InOrder; 3525 } else if (EltIdx == i+8) { 3526 V1Elts.push_back(Elt); 3527 V2Elts.push_back(DAG.getConstant(i, MaskEVT)); 3528 ++V2InOrder; 3529 } else if (EltIdx < 8) { 3530 V1Elts.push_back(Elt); 3531 ++V1FromV1; 3532 } else { 3533 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT)); 3534 ++V2FromV2; 3535 } 3536 } 3537 3538 if (V2InOrder > V1InOrder) { 3539 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3540 std::swap(V1, V2); 3541 std::swap(V1Elts, V2Elts); 3542 std::swap(V1FromV1, V2FromV2); 3543 } 3544 3545 if ((V1FromV1 + V1InOrder) != 8) { 3546 // Some elements are from V2. 3547 if (V1FromV1) { 3548 // If there are elements that are from V1 but out of place, 3549 // then first sort them in place 3550 SmallVector<SDValue, 8> MaskVec; 3551 for (unsigned i = 0; i < 8; ++i) { 3552 SDValue Elt = V1Elts[i]; 3553 if (Elt.getOpcode() == ISD::UNDEF) { 3554 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3555 continue; 3556 } 3557 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3558 if (EltIdx >= 8) 3559 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3560 else 3561 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); 3562 } 3563 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3564 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); 3565 } 3566 3567 NewV = V1; 3568 for (unsigned i = 0; i < 8; ++i) { 3569 SDValue Elt = V1Elts[i]; 3570 if (Elt.getOpcode() == ISD::UNDEF) 3571 continue; 3572 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3573 if (EltIdx < 8) 3574 continue; 3575 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3576 DAG.getConstant(EltIdx - 8, PtrVT)); 3577 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3578 DAG.getConstant(i, PtrVT)); 3579 } 3580 return NewV; 3581 } else { 3582 // All elements are from V1. 3583 NewV = V1; 3584 for (unsigned i = 0; i < 8; ++i) { 3585 SDValue Elt = V1Elts[i]; 3586 if (Elt.getOpcode() == ISD::UNDEF) 3587 continue; 3588 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3589 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3590 DAG.getConstant(EltIdx, PtrVT)); 3591 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3592 DAG.getConstant(i, PtrVT)); 3593 } 3594 return NewV; 3595 } 3596} 3597 3598/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3599/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3600/// done when every pair / quad of shuffle mask elements point to elements in 3601/// the right sequence. e.g. 3602/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3603static 3604SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2, 3605 MVT VT, 3606 SDValue PermMask, SelectionDAG &DAG, 3607 TargetLowering &TLI) { 3608 unsigned NumElems = PermMask.getNumOperands(); 3609 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3610 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3611 MVT MaskEltVT = MaskVT.getVectorElementType(); 3612 MVT NewVT = MaskVT; 3613 switch (VT.getSimpleVT()) { 3614 default: assert(false && "Unexpected!"); 3615 case MVT::v4f32: NewVT = MVT::v2f64; break; 3616 case MVT::v4i32: NewVT = MVT::v2i64; break; 3617 case MVT::v8i16: NewVT = MVT::v4i32; break; 3618 case MVT::v16i8: NewVT = MVT::v4i32; break; 3619 } 3620 3621 if (NewWidth == 2) { 3622 if (VT.isInteger()) 3623 NewVT = MVT::v2i64; 3624 else 3625 NewVT = MVT::v2f64; 3626 } 3627 unsigned Scale = NumElems / NewWidth; 3628 SmallVector<SDValue, 8> MaskVec; 3629 for (unsigned i = 0; i < NumElems; i += Scale) { 3630 unsigned StartIdx = ~0U; 3631 for (unsigned j = 0; j < Scale; ++j) { 3632 SDValue Elt = PermMask.getOperand(i+j); 3633 if (Elt.getOpcode() == ISD::UNDEF) 3634 continue; 3635 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3636 if (StartIdx == ~0U) 3637 StartIdx = EltIdx - (EltIdx % Scale); 3638 if (EltIdx != StartIdx + j) 3639 return SDValue(); 3640 } 3641 if (StartIdx == ~0U) 3642 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT)); 3643 else 3644 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT)); 3645 } 3646 3647 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1); 3648 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2); 3649 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2, 3650 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3651 &MaskVec[0], MaskVec.size())); 3652} 3653 3654/// getVZextMovL - Return a zero-extending vector move low node. 3655/// 3656static SDValue getVZextMovL(MVT VT, MVT OpVT, 3657 SDValue SrcOp, SelectionDAG &DAG, 3658 const X86Subtarget *Subtarget) { 3659 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3660 LoadSDNode *LD = NULL; 3661 if (!isScalarLoadToVector(SrcOp.Val, &LD)) 3662 LD = dyn_cast<LoadSDNode>(SrcOp); 3663 if (!LD) { 3664 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3665 // instead. 3666 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3667 if ((EVT != MVT::i64 || Subtarget->is64Bit()) && 3668 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 3669 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 3670 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { 3671 // PR2108 3672 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 3673 return DAG.getNode(ISD::BIT_CONVERT, VT, 3674 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, 3675 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT, 3676 SrcOp.getOperand(0).getOperand(0)))); 3677 } 3678 } 3679 } 3680 3681 return DAG.getNode(ISD::BIT_CONVERT, VT, 3682 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT, 3683 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp))); 3684} 3685 3686/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 3687/// shuffles. 3688static SDValue 3689LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2, 3690 SDValue PermMask, MVT VT, SelectionDAG &DAG) { 3691 MVT MaskVT = PermMask.getValueType(); 3692 MVT MaskEVT = MaskVT.getVectorElementType(); 3693 SmallVector<std::pair<int, int>, 8> Locs; 3694 Locs.reserve(4); 3695 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3696 unsigned NumHi = 0; 3697 unsigned NumLo = 0; 3698 for (unsigned i = 0; i != 4; ++i) { 3699 SDValue Elt = PermMask.getOperand(i); 3700 if (Elt.getOpcode() == ISD::UNDEF) { 3701 Locs[i] = std::make_pair(-1, -1); 3702 } else { 3703 unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); 3704 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!"); 3705 if (Val < 4) { 3706 Locs[i] = std::make_pair(0, NumLo); 3707 Mask1[NumLo] = Elt; 3708 NumLo++; 3709 } else { 3710 Locs[i] = std::make_pair(1, NumHi); 3711 if (2+NumHi < 4) 3712 Mask1[2+NumHi] = Elt; 3713 NumHi++; 3714 } 3715 } 3716 } 3717 3718 if (NumLo <= 2 && NumHi <= 2) { 3719 // If no more than two elements come from either vector. This can be 3720 // implemented with two shuffles. First shuffle gather the elements. 3721 // The second shuffle, which takes the first shuffle as both of its 3722 // vector operands, put the elements into the right order. 3723 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3724 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3725 &Mask1[0], Mask1.size())); 3726 3727 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3728 for (unsigned i = 0; i != 4; ++i) { 3729 if (Locs[i].first == -1) 3730 continue; 3731 else { 3732 unsigned Idx = (i < 2) ? 0 : 4; 3733 Idx += Locs[i].first * 2 + Locs[i].second; 3734 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 3735 } 3736 } 3737 3738 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 3739 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3740 &Mask2[0], Mask2.size())); 3741 } else if (NumLo == 3 || NumHi == 3) { 3742 // Otherwise, we must have three elements from one vector, call it X, and 3743 // one element from the other, call it Y. First, use a shufps to build an 3744 // intermediate vector with the one element from Y and the element from X 3745 // that will be in the same half in the final destination (the indexes don't 3746 // matter). Then, use a shufps to build the final vector, taking the half 3747 // containing the element from Y from the intermediate, and the other half 3748 // from X. 3749 if (NumHi == 3) { 3750 // Normalize it so the 3 elements come from V1. 3751 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3752 std::swap(V1, V2); 3753 } 3754 3755 // Find the element from V2. 3756 unsigned HiIndex; 3757 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 3758 SDValue Elt = PermMask.getOperand(HiIndex); 3759 if (Elt.getOpcode() == ISD::UNDEF) 3760 continue; 3761 unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); 3762 if (Val >= 4) 3763 break; 3764 } 3765 3766 Mask1[0] = PermMask.getOperand(HiIndex); 3767 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT); 3768 Mask1[2] = PermMask.getOperand(HiIndex^1); 3769 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT); 3770 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3771 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3772 3773 if (HiIndex >= 2) { 3774 Mask1[0] = PermMask.getOperand(0); 3775 Mask1[1] = PermMask.getOperand(1); 3776 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT); 3777 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT); 3778 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3779 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3780 } else { 3781 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT); 3782 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT); 3783 Mask1[2] = PermMask.getOperand(2); 3784 Mask1[3] = PermMask.getOperand(3); 3785 if (Mask1[2].getOpcode() != ISD::UNDEF) 3786 Mask1[2] = DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getValue()+4, 3787 MaskEVT); 3788 if (Mask1[3].getOpcode() != ISD::UNDEF) 3789 Mask1[3] = DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getValue()+4, 3790 MaskEVT); 3791 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, 3792 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4)); 3793 } 3794 } 3795 3796 // Break it into (shuffle shuffle_hi, shuffle_lo). 3797 Locs.clear(); 3798 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3799 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT)); 3800 SmallVector<SDValue,8> *MaskPtr = &LoMask; 3801 unsigned MaskIdx = 0; 3802 unsigned LoIdx = 0; 3803 unsigned HiIdx = 2; 3804 for (unsigned i = 0; i != 4; ++i) { 3805 if (i == 2) { 3806 MaskPtr = &HiMask; 3807 MaskIdx = 1; 3808 LoIdx = 0; 3809 HiIdx = 2; 3810 } 3811 SDValue Elt = PermMask.getOperand(i); 3812 if (Elt.getOpcode() == ISD::UNDEF) { 3813 Locs[i] = std::make_pair(-1, -1); 3814 } else if (cast<ConstantSDNode>(Elt)->getValue() < 4) { 3815 Locs[i] = std::make_pair(MaskIdx, LoIdx); 3816 (*MaskPtr)[LoIdx] = Elt; 3817 LoIdx++; 3818 } else { 3819 Locs[i] = std::make_pair(MaskIdx, HiIdx); 3820 (*MaskPtr)[HiIdx] = Elt; 3821 HiIdx++; 3822 } 3823 } 3824 3825 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3826 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3827 &LoMask[0], LoMask.size())); 3828 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3829 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3830 &HiMask[0], HiMask.size())); 3831 SmallVector<SDValue, 8> MaskOps; 3832 for (unsigned i = 0; i != 4; ++i) { 3833 if (Locs[i].first == -1) { 3834 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3835 } else { 3836 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 3837 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 3838 } 3839 } 3840 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 3841 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3842 &MaskOps[0], MaskOps.size())); 3843} 3844 3845SDValue 3846X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 3847 SDValue V1 = Op.getOperand(0); 3848 SDValue V2 = Op.getOperand(1); 3849 SDValue PermMask = Op.getOperand(2); 3850 MVT VT = Op.getValueType(); 3851 unsigned NumElems = PermMask.getNumOperands(); 3852 bool isMMX = VT.getSizeInBits() == 64; 3853 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 3854 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 3855 bool V1IsSplat = false; 3856 bool V2IsSplat = false; 3857 3858 if (isUndefShuffle(Op.Val)) 3859 return DAG.getNode(ISD::UNDEF, VT); 3860 3861 if (isZeroShuffle(Op.Val)) 3862 return getZeroVector(VT, Subtarget->hasSSE2(), DAG); 3863 3864 if (isIdentityMask(PermMask.Val)) 3865 return V1; 3866 else if (isIdentityMask(PermMask.Val, true)) 3867 return V2; 3868 3869 if (isSplatMask(PermMask.Val)) { 3870 if (isMMX || NumElems < 4) return Op; 3871 // Promote it to a v4{if}32 splat. 3872 return PromoteSplat(Op, DAG, Subtarget->hasSSE2()); 3873 } 3874 3875 // If the shuffle can be profitably rewritten as a narrower shuffle, then 3876 // do it! 3877 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 3878 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); 3879 if (NewOp.Val) 3880 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); 3881 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 3882 // FIXME: Figure out a cleaner way to do this. 3883 // Try to make use of movq to zero out the top part. 3884 if (ISD::isBuildVectorAllZeros(V2.Val)) { 3885 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 3886 DAG, *this); 3887 if (NewOp.Val) { 3888 SDValue NewV1 = NewOp.getOperand(0); 3889 SDValue NewV2 = NewOp.getOperand(1); 3890 SDValue NewMask = NewOp.getOperand(2); 3891 if (isCommutedMOVL(NewMask.Val, true, false)) { 3892 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); 3893 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget); 3894 } 3895 } 3896 } else if (ISD::isBuildVectorAllZeros(V1.Val)) { 3897 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, 3898 DAG, *this); 3899 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val)) 3900 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 3901 DAG, Subtarget); 3902 } 3903 } 3904 3905 // Check if this can be converted into a logical shift. 3906 bool isLeft = false; 3907 unsigned ShAmt = 0; 3908 SDValue ShVal; 3909 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt); 3910 if (isShift && ShVal.hasOneUse()) { 3911 // If the shifted value has multiple uses, it may be cheaper to use 3912 // v_set0 + movlhps or movhlps, etc. 3913 MVT EVT = VT.getVectorElementType(); 3914 ShAmt *= EVT.getSizeInBits(); 3915 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); 3916 } 3917 3918 if (X86::isMOVLMask(PermMask.Val)) { 3919 if (V1IsUndef) 3920 return V2; 3921 if (ISD::isBuildVectorAllZeros(V1.Val)) 3922 return getVZextMovL(VT, VT, V2, DAG, Subtarget); 3923 if (!isMMX) 3924 return Op; 3925 } 3926 3927 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.Val) || 3928 X86::isMOVSLDUPMask(PermMask.Val) || 3929 X86::isMOVHLPSMask(PermMask.Val) || 3930 X86::isMOVHPMask(PermMask.Val) || 3931 X86::isMOVLPMask(PermMask.Val))) 3932 return Op; 3933 3934 if (ShouldXformToMOVHLPS(PermMask.Val) || 3935 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val)) 3936 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3937 3938 if (isShift) { 3939 // No better options. Use a vshl / vsrl. 3940 MVT EVT = VT.getVectorElementType(); 3941 ShAmt *= EVT.getSizeInBits(); 3942 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this); 3943 } 3944 3945 bool Commuted = false; 3946 // FIXME: This should also accept a bitcast of a splat? Be careful, not 3947 // 1,1,1,1 -> v8i16 though. 3948 V1IsSplat = isSplatVector(V1.Val); 3949 V2IsSplat = isSplatVector(V2.Val); 3950 3951 // Canonicalize the splat or undef, if present, to be on the RHS. 3952 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 3953 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3954 std::swap(V1IsSplat, V2IsSplat); 3955 std::swap(V1IsUndef, V2IsUndef); 3956 Commuted = true; 3957 } 3958 3959 // FIXME: Figure out a cleaner way to do this. 3960 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) { 3961 if (V2IsUndef) return V1; 3962 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3963 if (V2IsSplat) { 3964 // V2 is a splat, so the mask may be malformed. That is, it may point 3965 // to any V2 element. The instruction selectior won't like this. Get 3966 // a corrected mask and commute to form a proper MOVS{S|D}. 3967 SDValue NewMask = getMOVLMask(NumElems, DAG); 3968 if (NewMask.Val != PermMask.Val) 3969 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3970 } 3971 return Op; 3972 } 3973 3974 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 3975 X86::isUNPCKH_v_undef_Mask(PermMask.Val) || 3976 X86::isUNPCKLMask(PermMask.Val) || 3977 X86::isUNPCKHMask(PermMask.Val)) 3978 return Op; 3979 3980 if (V2IsSplat) { 3981 // Normalize mask so all entries that point to V2 points to its first 3982 // element then try to match unpck{h|l} again. If match, return a 3983 // new vector_shuffle with the corrected mask. 3984 SDValue NewMask = NormalizeMask(PermMask, DAG); 3985 if (NewMask.Val != PermMask.Val) { 3986 if (X86::isUNPCKLMask(PermMask.Val, true)) { 3987 SDValue NewMask = getUnpacklMask(NumElems, DAG); 3988 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3989 } else if (X86::isUNPCKHMask(PermMask.Val, true)) { 3990 SDValue NewMask = getUnpackhMask(NumElems, DAG); 3991 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3992 } 3993 } 3994 } 3995 3996 // Normalize the node to match x86 shuffle ops if needed 3997 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val)) 3998 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3999 4000 if (Commuted) { 4001 // Commute is back and try unpck* again. 4002 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 4003 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 4004 X86::isUNPCKH_v_undef_Mask(PermMask.Val) || 4005 X86::isUNPCKLMask(PermMask.Val) || 4006 X86::isUNPCKHMask(PermMask.Val)) 4007 return Op; 4008 } 4009 4010 // Try PSHUF* first, then SHUFP*. 4011 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically 4012 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. 4013 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) { 4014 if (V2.getOpcode() != ISD::UNDEF) 4015 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 4016 DAG.getNode(ISD::UNDEF, VT), PermMask); 4017 return Op; 4018 } 4019 4020 if (!isMMX) { 4021 if (Subtarget->hasSSE2() && 4022 (X86::isPSHUFDMask(PermMask.Val) || 4023 X86::isPSHUFHWMask(PermMask.Val) || 4024 X86::isPSHUFLWMask(PermMask.Val))) { 4025 MVT RVT = VT; 4026 if (VT == MVT::v4f32) { 4027 RVT = MVT::v4i32; 4028 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, 4029 DAG.getNode(ISD::BIT_CONVERT, RVT, V1), 4030 DAG.getNode(ISD::UNDEF, RVT), PermMask); 4031 } else if (V2.getOpcode() != ISD::UNDEF) 4032 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1, 4033 DAG.getNode(ISD::UNDEF, RVT), PermMask); 4034 if (RVT != VT) 4035 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op); 4036 return Op; 4037 } 4038 4039 // Binary or unary shufps. 4040 if (X86::isSHUFPMask(PermMask.Val) || 4041 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val))) 4042 return Op; 4043 } 4044 4045 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4046 if (VT == MVT::v8i16) { 4047 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); 4048 if (NewOp.Val) 4049 return NewOp; 4050 } 4051 4052 // Handle all 4 wide cases with a number of shuffles except for MMX. 4053 if (NumElems == 4 && !isMMX) 4054 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG); 4055 4056 return SDValue(); 4057} 4058 4059SDValue 4060X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4061 SelectionDAG &DAG) { 4062 MVT VT = Op.getValueType(); 4063 if (VT.getSizeInBits() == 8) { 4064 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, 4065 Op.getOperand(0), Op.getOperand(1)); 4066 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 4067 DAG.getValueType(VT)); 4068 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4069 } else if (VT.getSizeInBits() == 16) { 4070 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, 4071 Op.getOperand(0), Op.getOperand(1)); 4072 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 4073 DAG.getValueType(VT)); 4074 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4075 } else if (VT == MVT::f32) { 4076 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4077 // the result back to FR32 register. It's only worth matching if the 4078 // result has a single use which is a store or a bitcast to i32. 4079 if (!Op.hasOneUse()) 4080 return SDValue(); 4081 SDNode *User = *Op.Val->use_begin(); 4082 if (User->getOpcode() != ISD::STORE && 4083 (User->getOpcode() != ISD::BIT_CONVERT || 4084 User->getValueType(0) != MVT::i32)) 4085 return SDValue(); 4086 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4087 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), 4088 Op.getOperand(1)); 4089 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); 4090 } 4091 return SDValue(); 4092} 4093 4094 4095SDValue 4096X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4097 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4098 return SDValue(); 4099 4100 if (Subtarget->hasSSE41()) { 4101 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4102 if (Res.Val) 4103 return Res; 4104 } 4105 4106 MVT VT = Op.getValueType(); 4107 // TODO: handle v16i8. 4108 if (VT.getSizeInBits() == 16) { 4109 SDValue Vec = Op.getOperand(0); 4110 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 4111 if (Idx == 0) 4112 return DAG.getNode(ISD::TRUNCATE, MVT::i16, 4113 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4114 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), 4115 Op.getOperand(1))); 4116 // Transform it so it match pextrw which produces a 32-bit result. 4117 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); 4118 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 4119 Op.getOperand(0), Op.getOperand(1)); 4120 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 4121 DAG.getValueType(VT)); 4122 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 4123 } else if (VT.getSizeInBits() == 32) { 4124 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 4125 if (Idx == 0) 4126 return Op; 4127 // SHUFPS the element to the lowest double word, then movss. 4128 MVT MaskVT = MVT::getIntVectorWithNumElements(4); 4129 SmallVector<SDValue, 8> IdxVec; 4130 IdxVec. 4131 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType())); 4132 IdxVec. 4133 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4134 IdxVec. 4135 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4136 IdxVec. 4137 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4138 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4139 &IdxVec[0], IdxVec.size()); 4140 SDValue Vec = Op.getOperand(0); 4141 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 4142 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 4143 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 4144 DAG.getIntPtrConstant(0)); 4145 } else if (VT.getSizeInBits() == 64) { 4146 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4147 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4148 // to match extract_elt for f64. 4149 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 4150 if (Idx == 0) 4151 return Op; 4152 4153 // UNPCKHPD the element to the lowest double word, then movsd. 4154 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4155 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4156 MVT MaskVT = MVT::getIntVectorWithNumElements(2); 4157 SmallVector<SDValue, 8> IdxVec; 4158 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType())); 4159 IdxVec. 4160 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType())); 4161 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4162 &IdxVec[0], IdxVec.size()); 4163 SDValue Vec = Op.getOperand(0); 4164 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 4165 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 4166 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 4167 DAG.getIntPtrConstant(0)); 4168 } 4169 4170 return SDValue(); 4171} 4172 4173SDValue 4174X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4175 MVT VT = Op.getValueType(); 4176 MVT EVT = VT.getVectorElementType(); 4177 4178 SDValue N0 = Op.getOperand(0); 4179 SDValue N1 = Op.getOperand(1); 4180 SDValue N2 = Op.getOperand(2); 4181 4182 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4183 isa<ConstantSDNode>(N2)) { 4184 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4185 : X86ISD::PINSRW; 4186 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4187 // argument. 4188 if (N1.getValueType() != MVT::i32) 4189 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 4190 if (N2.getValueType() != MVT::i32) 4191 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); 4192 return DAG.getNode(Opc, VT, N0, N1, N2); 4193 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4194 // Bits [7:6] of the constant are the source select. This will always be 4195 // zero here. The DAG Combiner may combine an extract_elt index into these 4196 // bits. For example (insert (extract, 3), 2) could be matched by putting 4197 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4198 // Bits [5:4] of the constant are the destination select. This is the 4199 // value of the incoming immediate. 4200 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4201 // combine either bitwise AND or insert of float 0.0 to set these bits. 4202 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4); 4203 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); 4204 } 4205 return SDValue(); 4206} 4207 4208SDValue 4209X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4210 MVT VT = Op.getValueType(); 4211 MVT EVT = VT.getVectorElementType(); 4212 4213 if (Subtarget->hasSSE41()) 4214 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4215 4216 if (EVT == MVT::i8) 4217 return SDValue(); 4218 4219 SDValue N0 = Op.getOperand(0); 4220 SDValue N1 = Op.getOperand(1); 4221 SDValue N2 = Op.getOperand(2); 4222 4223 if (EVT.getSizeInBits() == 16) { 4224 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4225 // as its second argument. 4226 if (N1.getValueType() != MVT::i32) 4227 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 4228 if (N2.getValueType() != MVT::i32) 4229 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); 4230 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 4231 } 4232 return SDValue(); 4233} 4234 4235SDValue 4236X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4237 if (Op.getValueType() == MVT::v2f32) 4238 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32, 4239 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32, 4240 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, 4241 Op.getOperand(0)))); 4242 4243 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 4244 MVT VT = MVT::v2i32; 4245 switch (Op.getValueType().getSimpleVT()) { 4246 default: break; 4247 case MVT::v16i8: 4248 case MVT::v8i16: 4249 VT = MVT::v4i32; 4250 break; 4251 } 4252 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), 4253 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt)); 4254} 4255 4256// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4257// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4258// one of the above mentioned nodes. It has to be wrapped because otherwise 4259// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4260// be used to form addressing mode. These wrapped nodes will be selected 4261// into MOV32ri. 4262SDValue 4263X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4264 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4265 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), 4266 getPointerTy(), 4267 CP->getAlignment()); 4268 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4269 // With PIC, the address is actually $g + Offset. 4270 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4271 !Subtarget->isPICStyleRIPRel()) { 4272 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4273 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4274 Result); 4275 } 4276 4277 return Result; 4278} 4279 4280SDValue 4281X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4282 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4283 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); 4284 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4285 // With PIC, the address is actually $g + Offset. 4286 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4287 !Subtarget->isPICStyleRIPRel()) { 4288 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4289 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4290 Result); 4291 } 4292 4293 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 4294 // load the value at address GV, not the value of GV itself. This means that 4295 // the GlobalAddress must be in the base or index register of the address, not 4296 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 4297 // The same applies for external symbols during PIC codegen 4298 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) 4299 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, 4300 PseudoSourceValue::getGOT(), 0); 4301 4302 return Result; 4303} 4304 4305// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4306static SDValue 4307LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4308 const MVT PtrVT) { 4309 SDValue InFlag; 4310 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, 4311 DAG.getNode(X86ISD::GlobalBaseReg, 4312 PtrVT), InFlag); 4313 InFlag = Chain.getValue(1); 4314 4315 // emit leal symbol@TLSGD(,%ebx,1), %eax 4316 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4317 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4318 GA->getValueType(0), 4319 GA->getOffset()); 4320 SDValue Ops[] = { Chain, TGA, InFlag }; 4321 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); 4322 InFlag = Result.getValue(2); 4323 Chain = Result.getValue(1); 4324 4325 // call ___tls_get_addr. This function receives its argument in 4326 // the register EAX. 4327 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag); 4328 InFlag = Chain.getValue(1); 4329 4330 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4331 SDValue Ops1[] = { Chain, 4332 DAG.getTargetExternalSymbol("___tls_get_addr", 4333 PtrVT), 4334 DAG.getRegister(X86::EAX, PtrVT), 4335 DAG.getRegister(X86::EBX, PtrVT), 4336 InFlag }; 4337 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5); 4338 InFlag = Chain.getValue(1); 4339 4340 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag); 4341} 4342 4343// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4344static SDValue 4345LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4346 const MVT PtrVT) { 4347 SDValue InFlag, Chain; 4348 4349 // emit leaq symbol@TLSGD(%rip), %rdi 4350 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 4351 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4352 GA->getValueType(0), 4353 GA->getOffset()); 4354 SDValue Ops[] = { DAG.getEntryNode(), TGA}; 4355 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2); 4356 Chain = Result.getValue(1); 4357 InFlag = Result.getValue(2); 4358 4359 // call __tls_get_addr. This function receives its argument in 4360 // the register RDI. 4361 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag); 4362 InFlag = Chain.getValue(1); 4363 4364 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4365 SDValue Ops1[] = { Chain, 4366 DAG.getTargetExternalSymbol("__tls_get_addr", 4367 PtrVT), 4368 DAG.getRegister(X86::RDI, PtrVT), 4369 InFlag }; 4370 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4); 4371 InFlag = Chain.getValue(1); 4372 4373 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag); 4374} 4375 4376// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4377// "local exec" model. 4378static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4379 const MVT PtrVT) { 4380 // Get the Thread Pointer 4381 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); 4382 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4383 // exec) 4384 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4385 GA->getValueType(0), 4386 GA->getOffset()); 4387 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); 4388 4389 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model 4390 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, 4391 PseudoSourceValue::getGOT(), 0); 4392 4393 // The address of the thread local variable is the add of the thread 4394 // pointer with the offset of the variable. 4395 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 4396} 4397 4398SDValue 4399X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4400 // TODO: implement the "local dynamic" model 4401 // TODO: implement the "initial exec"model for pic executables 4402 assert(Subtarget->isTargetELF() && 4403 "TLS not implemented for non-ELF targets"); 4404 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4405 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 4406 // otherwise use the "Local Exec"TLS Model 4407 if (Subtarget->is64Bit()) { 4408 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4409 } else { 4410 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 4411 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4412 else 4413 return LowerToTLSExecModel(GA, DAG, getPointerTy()); 4414 } 4415} 4416 4417SDValue 4418X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4419 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4420 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 4421 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4422 // With PIC, the address is actually $g + Offset. 4423 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4424 !Subtarget->isPICStyleRIPRel()) { 4425 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4426 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4427 Result); 4428 } 4429 4430 return Result; 4431} 4432 4433SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4434 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4435 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 4436 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4437 // With PIC, the address is actually $g + Offset. 4438 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4439 !Subtarget->isPICStyleRIPRel()) { 4440 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4441 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4442 Result); 4443 } 4444 4445 return Result; 4446} 4447 4448/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4449/// take a 2 x i32 value to shift plus a shift amount. 4450SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4451 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4452 MVT VT = Op.getValueType(); 4453 unsigned VTBits = VT.getSizeInBits(); 4454 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4455 SDValue ShOpLo = Op.getOperand(0); 4456 SDValue ShOpHi = Op.getOperand(1); 4457 SDValue ShAmt = Op.getOperand(2); 4458 SDValue Tmp1 = isSRA ? 4459 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : 4460 DAG.getConstant(0, VT); 4461 4462 SDValue Tmp2, Tmp3; 4463 if (Op.getOpcode() == ISD::SHL_PARTS) { 4464 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); 4465 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); 4466 } else { 4467 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); 4468 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); 4469 } 4470 4471 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 4472 DAG.getConstant(VTBits, MVT::i8)); 4473 SDValue Cond = DAG.getNode(X86ISD::CMP, VT, 4474 AndNode, DAG.getConstant(0, MVT::i8)); 4475 4476 SDValue Hi, Lo; 4477 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4478 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4479 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4480 4481 if (Op.getOpcode() == ISD::SHL_PARTS) { 4482 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); 4483 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); 4484 } else { 4485 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); 4486 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); 4487 } 4488 4489 SDValue Ops[2] = { Lo, Hi }; 4490 return DAG.getMergeValues(Ops, 2); 4491} 4492 4493SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4494 MVT SrcVT = Op.getOperand(0).getValueType(); 4495 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4496 "Unknown SINT_TO_FP to lower!"); 4497 4498 // These are really Legal; caller falls through into that case. 4499 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4500 return SDValue(); 4501 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && 4502 Subtarget->is64Bit()) 4503 return SDValue(); 4504 4505 unsigned Size = SrcVT.getSizeInBits()/8; 4506 MachineFunction &MF = DAG.getMachineFunction(); 4507 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4508 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4509 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), 4510 StackSlot, 4511 PseudoSourceValue::getFixedStack(SSFI), 0); 4512 4513 // Build the FILD 4514 SDVTList Tys; 4515 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4516 if (useSSE) 4517 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4518 else 4519 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4520 SmallVector<SDValue, 8> Ops; 4521 Ops.push_back(Chain); 4522 Ops.push_back(StackSlot); 4523 Ops.push_back(DAG.getValueType(SrcVT)); 4524 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, 4525 Tys, &Ops[0], Ops.size()); 4526 4527 if (useSSE) { 4528 Chain = Result.getValue(1); 4529 SDValue InFlag = Result.getValue(2); 4530 4531 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4532 // shouldn't be necessary except that RFP cannot be live across 4533 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4534 MachineFunction &MF = DAG.getMachineFunction(); 4535 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4536 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4537 Tys = DAG.getVTList(MVT::Other); 4538 SmallVector<SDValue, 8> Ops; 4539 Ops.push_back(Chain); 4540 Ops.push_back(Result); 4541 Ops.push_back(StackSlot); 4542 Ops.push_back(DAG.getValueType(Op.getValueType())); 4543 Ops.push_back(InFlag); 4544 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 4545 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, 4546 PseudoSourceValue::getFixedStack(SSFI), 0); 4547 } 4548 4549 return Result; 4550} 4551 4552std::pair<SDValue,SDValue> X86TargetLowering:: 4553FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) { 4554 assert(Op.getValueType().getSimpleVT() <= MVT::i64 && 4555 Op.getValueType().getSimpleVT() >= MVT::i16 && 4556 "Unknown FP_TO_SINT to lower!"); 4557 4558 // These are really Legal. 4559 if (Op.getValueType() == MVT::i32 && 4560 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 4561 return std::make_pair(SDValue(), SDValue()); 4562 if (Subtarget->is64Bit() && 4563 Op.getValueType() == MVT::i64 && 4564 Op.getOperand(0).getValueType() != MVT::f80) 4565 return std::make_pair(SDValue(), SDValue()); 4566 4567 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 4568 // stack slot. 4569 MachineFunction &MF = DAG.getMachineFunction(); 4570 unsigned MemSize = Op.getValueType().getSizeInBits()/8; 4571 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4572 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4573 unsigned Opc; 4574 switch (Op.getValueType().getSimpleVT()) { 4575 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 4576 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 4577 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 4578 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 4579 } 4580 4581 SDValue Chain = DAG.getEntryNode(); 4582 SDValue Value = Op.getOperand(0); 4583 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 4584 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 4585 Chain = DAG.getStore(Chain, Value, StackSlot, 4586 PseudoSourceValue::getFixedStack(SSFI), 0); 4587 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 4588 SDValue Ops[] = { 4589 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 4590 }; 4591 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 4592 Chain = Value.getValue(1); 4593 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4594 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4595 } 4596 4597 // Build the FP_TO_INT*_IN_MEM 4598 SDValue Ops[] = { Chain, Value, StackSlot }; 4599 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); 4600 4601 return std::make_pair(FIST, StackSlot); 4602} 4603 4604SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 4605 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG); 4606 SDValue FIST = Vals.first, StackSlot = Vals.second; 4607 if (FIST.Val == 0) return SDValue(); 4608 4609 // Load the result. 4610 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); 4611} 4612 4613SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { 4614 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG); 4615 SDValue FIST = Vals.first, StackSlot = Vals.second; 4616 if (FIST.Val == 0) return 0; 4617 4618 MVT VT = N->getValueType(0); 4619 4620 // Return a load from the stack slot. 4621 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0); 4622 4623 // Use MERGE_VALUES to drop the chain result value and get a node with one 4624 // result. This requires turning off getMergeValues simplification, since 4625 // otherwise it will give us Res back. 4626 return DAG.getMergeValues(&Res, 1, false).Val; 4627} 4628 4629SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 4630 MVT VT = Op.getValueType(); 4631 MVT EltVT = VT; 4632 if (VT.isVector()) 4633 EltVT = VT.getVectorElementType(); 4634 std::vector<Constant*> CV; 4635 if (EltVT == MVT::f64) { 4636 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); 4637 CV.push_back(C); 4638 CV.push_back(C); 4639 } else { 4640 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))); 4641 CV.push_back(C); 4642 CV.push_back(C); 4643 CV.push_back(C); 4644 CV.push_back(C); 4645 } 4646 Constant *C = ConstantVector::get(CV); 4647 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4648 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4649 PseudoSourceValue::getConstantPool(), 0, 4650 false, 16); 4651 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 4652} 4653 4654SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 4655 MVT VT = Op.getValueType(); 4656 MVT EltVT = VT; 4657 unsigned EltNum = 1; 4658 if (VT.isVector()) { 4659 EltVT = VT.getVectorElementType(); 4660 EltNum = VT.getVectorNumElements(); 4661 } 4662 std::vector<Constant*> CV; 4663 if (EltVT == MVT::f64) { 4664 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63))); 4665 CV.push_back(C); 4666 CV.push_back(C); 4667 } else { 4668 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31))); 4669 CV.push_back(C); 4670 CV.push_back(C); 4671 CV.push_back(C); 4672 CV.push_back(C); 4673 } 4674 Constant *C = ConstantVector::get(CV); 4675 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4676 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4677 PseudoSourceValue::getConstantPool(), 0, 4678 false, 16); 4679 if (VT.isVector()) { 4680 return DAG.getNode(ISD::BIT_CONVERT, VT, 4681 DAG.getNode(ISD::XOR, MVT::v2i64, 4682 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), 4683 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask))); 4684 } else { 4685 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 4686 } 4687} 4688 4689SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 4690 SDValue Op0 = Op.getOperand(0); 4691 SDValue Op1 = Op.getOperand(1); 4692 MVT VT = Op.getValueType(); 4693 MVT SrcVT = Op1.getValueType(); 4694 4695 // If second operand is smaller, extend it first. 4696 if (SrcVT.bitsLT(VT)) { 4697 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); 4698 SrcVT = VT; 4699 } 4700 // And if it is bigger, shrink it first. 4701 if (SrcVT.bitsGT(VT)) { 4702 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); 4703 SrcVT = VT; 4704 } 4705 4706 // At this point the operands and the result should have the same 4707 // type, and that won't be f80 since that is not custom lowered. 4708 4709 // First get the sign bit of second operand. 4710 std::vector<Constant*> CV; 4711 if (SrcVT == MVT::f64) { 4712 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63)))); 4713 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 4714 } else { 4715 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31)))); 4716 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4717 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4718 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4719 } 4720 Constant *C = ConstantVector::get(CV); 4721 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4722 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, 4723 PseudoSourceValue::getConstantPool(), 0, 4724 false, 16); 4725 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); 4726 4727 // Shift sign bit right or left if the two operands have different types. 4728 if (SrcVT.bitsGT(VT)) { 4729 // Op0 is MVT::f32, Op1 is MVT::f64. 4730 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); 4731 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, 4732 DAG.getConstant(32, MVT::i32)); 4733 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); 4734 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, 4735 DAG.getIntPtrConstant(0)); 4736 } 4737 4738 // Clear first operand sign bit. 4739 CV.clear(); 4740 if (VT == MVT::f64) { 4741 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))))); 4742 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 4743 } else { 4744 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31))))); 4745 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4746 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4747 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 4748 } 4749 C = ConstantVector::get(CV); 4750 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4751 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4752 PseudoSourceValue::getConstantPool(), 0, 4753 false, 16); 4754 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); 4755 4756 // Or the value with the sign bit. 4757 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); 4758} 4759 4760SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 4761 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 4762 SDValue Cond; 4763 SDValue Op0 = Op.getOperand(0); 4764 SDValue Op1 = Op.getOperand(1); 4765 SDValue CC = Op.getOperand(2); 4766 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 4767 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 4768 unsigned X86CC; 4769 4770 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, 4771 Op0, Op1, DAG)) { 4772 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); 4773 return DAG.getNode(X86ISD::SETCC, MVT::i8, 4774 DAG.getConstant(X86CC, MVT::i8), Cond); 4775 } 4776 4777 assert(isFP && "Illegal integer SetCC!"); 4778 4779 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); 4780 switch (SetCCOpcode) { 4781 default: assert(false && "Illegal floating point SetCC!"); 4782 case ISD::SETOEQ: { // !PF & ZF 4783 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4784 DAG.getConstant(X86::COND_NP, MVT::i8), Cond); 4785 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4786 DAG.getConstant(X86::COND_E, MVT::i8), Cond); 4787 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 4788 } 4789 case ISD::SETUNE: { // PF | !ZF 4790 SDValue Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4791 DAG.getConstant(X86::COND_P, MVT::i8), Cond); 4792 SDValue Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4793 DAG.getConstant(X86::COND_NE, MVT::i8), Cond); 4794 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 4795 } 4796 } 4797} 4798 4799SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 4800 SDValue Cond; 4801 SDValue Op0 = Op.getOperand(0); 4802 SDValue Op1 = Op.getOperand(1); 4803 SDValue CC = Op.getOperand(2); 4804 MVT VT = Op.getValueType(); 4805 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 4806 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 4807 4808 if (isFP) { 4809 unsigned SSECC = 8; 4810 MVT VT0 = Op0.getValueType(); 4811 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 4812 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 4813 bool Swap = false; 4814 4815 switch (SetCCOpcode) { 4816 default: break; 4817 case ISD::SETOEQ: 4818 case ISD::SETEQ: SSECC = 0; break; 4819 case ISD::SETOGT: 4820 case ISD::SETGT: Swap = true; // Fallthrough 4821 case ISD::SETLT: 4822 case ISD::SETOLT: SSECC = 1; break; 4823 case ISD::SETOGE: 4824 case ISD::SETGE: Swap = true; // Fallthrough 4825 case ISD::SETLE: 4826 case ISD::SETOLE: SSECC = 2; break; 4827 case ISD::SETUO: SSECC = 3; break; 4828 case ISD::SETUNE: 4829 case ISD::SETNE: SSECC = 4; break; 4830 case ISD::SETULE: Swap = true; 4831 case ISD::SETUGE: SSECC = 5; break; 4832 case ISD::SETULT: Swap = true; 4833 case ISD::SETUGT: SSECC = 6; break; 4834 case ISD::SETO: SSECC = 7; break; 4835 } 4836 if (Swap) 4837 std::swap(Op0, Op1); 4838 4839 // In the two special cases we can't handle, emit two comparisons. 4840 if (SSECC == 8) { 4841 if (SetCCOpcode == ISD::SETUEQ) { 4842 SDValue UNORD, EQ; 4843 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 4844 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 4845 return DAG.getNode(ISD::OR, VT, UNORD, EQ); 4846 } 4847 else if (SetCCOpcode == ISD::SETONE) { 4848 SDValue ORD, NEQ; 4849 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 4850 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 4851 return DAG.getNode(ISD::AND, VT, ORD, NEQ); 4852 } 4853 assert(0 && "Illegal FP comparison"); 4854 } 4855 // Handle all other FP comparisons here. 4856 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 4857 } 4858 4859 // We are handling one of the integer comparisons here. Since SSE only has 4860 // GT and EQ comparisons for integer, swapping operands and multiple 4861 // operations may be required for some comparisons. 4862 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 4863 bool Swap = false, Invert = false, FlipSigns = false; 4864 4865 switch (VT.getSimpleVT()) { 4866 default: break; 4867 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 4868 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 4869 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 4870 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 4871 } 4872 4873 switch (SetCCOpcode) { 4874 default: break; 4875 case ISD::SETNE: Invert = true; 4876 case ISD::SETEQ: Opc = EQOpc; break; 4877 case ISD::SETLT: Swap = true; 4878 case ISD::SETGT: Opc = GTOpc; break; 4879 case ISD::SETGE: Swap = true; 4880 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 4881 case ISD::SETULT: Swap = true; 4882 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 4883 case ISD::SETUGE: Swap = true; 4884 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 4885 } 4886 if (Swap) 4887 std::swap(Op0, Op1); 4888 4889 // Since SSE has no unsigned integer comparisons, we need to flip the sign 4890 // bits of the inputs before performing those operations. 4891 if (FlipSigns) { 4892 MVT EltVT = VT.getVectorElementType(); 4893 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT); 4894 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 4895 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0], 4896 SignBits.size()); 4897 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec); 4898 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec); 4899 } 4900 4901 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1); 4902 4903 // If the logical-not of the result is required, perform that now. 4904 if (Invert) { 4905 MVT EltVT = VT.getVectorElementType(); 4906 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT); 4907 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne); 4908 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], 4909 NegOnes.size()); 4910 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV); 4911 } 4912 return Result; 4913} 4914 4915SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 4916 bool addTest = true; 4917 SDValue Cond = Op.getOperand(0); 4918 SDValue CC; 4919 4920 if (Cond.getOpcode() == ISD::SETCC) 4921 Cond = LowerSETCC(Cond, DAG); 4922 4923 // If condition flag is set by a X86ISD::CMP, then use it as the condition 4924 // setting operand in place of the X86ISD::SETCC. 4925 if (Cond.getOpcode() == X86ISD::SETCC) { 4926 CC = Cond.getOperand(0); 4927 4928 SDValue Cmp = Cond.getOperand(1); 4929 unsigned Opc = Cmp.getOpcode(); 4930 MVT VT = Op.getValueType(); 4931 4932 bool IllegalFPCMov = false; 4933 if (VT.isFloatingPoint() && !VT.isVector() && 4934 !isScalarFPTypeInSSEReg(VT)) // FPStack? 4935 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); 4936 4937 if ((Opc == X86ISD::CMP || 4938 Opc == X86ISD::COMI || 4939 Opc == X86ISD::UCOMI) && !IllegalFPCMov) { 4940 Cond = Cmp; 4941 addTest = false; 4942 } 4943 } 4944 4945 if (addTest) { 4946 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4947 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 4948 } 4949 4950 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), 4951 MVT::Flag); 4952 SmallVector<SDValue, 4> Ops; 4953 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 4954 // condition is true. 4955 Ops.push_back(Op.getOperand(2)); 4956 Ops.push_back(Op.getOperand(1)); 4957 Ops.push_back(CC); 4958 Ops.push_back(Cond); 4959 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 4960} 4961 4962SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 4963 bool addTest = true; 4964 SDValue Chain = Op.getOperand(0); 4965 SDValue Cond = Op.getOperand(1); 4966 SDValue Dest = Op.getOperand(2); 4967 SDValue CC; 4968 4969 if (Cond.getOpcode() == ISD::SETCC) 4970 Cond = LowerSETCC(Cond, DAG); 4971 4972 // If condition flag is set by a X86ISD::CMP, then use it as the condition 4973 // setting operand in place of the X86ISD::SETCC. 4974 if (Cond.getOpcode() == X86ISD::SETCC) { 4975 CC = Cond.getOperand(0); 4976 4977 SDValue Cmp = Cond.getOperand(1); 4978 unsigned Opc = Cmp.getOpcode(); 4979 if (Opc == X86ISD::CMP || 4980 Opc == X86ISD::COMI || 4981 Opc == X86ISD::UCOMI) { 4982 Cond = Cmp; 4983 addTest = false; 4984 } 4985 } 4986 4987 if (addTest) { 4988 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4989 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 4990 } 4991 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 4992 Chain, Op.getOperand(2), CC, Cond); 4993} 4994 4995 4996// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 4997// Calls to _alloca is needed to probe the stack when allocating more than 4k 4998// bytes in one go. Touching the stack at 4K increments is necessary to ensure 4999// that the guard pages used by the OS virtual memory manager are allocated in 5000// correct sequence. 5001SDValue 5002X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5003 SelectionDAG &DAG) { 5004 assert(Subtarget->isTargetCygMing() && 5005 "This should be used only on Cygwin/Mingw targets"); 5006 5007 // Get the inputs. 5008 SDValue Chain = Op.getOperand(0); 5009 SDValue Size = Op.getOperand(1); 5010 // FIXME: Ensure alignment here 5011 5012 SDValue Flag; 5013 5014 MVT IntPtr = getPointerTy(); 5015 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5016 5017 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0)); 5018 5019 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); 5020 Flag = Chain.getValue(1); 5021 5022 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5023 SDValue Ops[] = { Chain, 5024 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5025 DAG.getRegister(X86::EAX, IntPtr), 5026 DAG.getRegister(X86StackPtr, SPTy), 5027 Flag }; 5028 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5); 5029 Flag = Chain.getValue(1); 5030 5031 Chain = DAG.getCALLSEQ_END(Chain, 5032 DAG.getIntPtrConstant(0), 5033 DAG.getIntPtrConstant(0), 5034 Flag); 5035 5036 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); 5037 5038 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5039 return DAG.getMergeValues(Ops1, 2); 5040} 5041 5042SDValue 5043X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, 5044 SDValue Chain, 5045 SDValue Dst, SDValue Src, 5046 SDValue Size, unsigned Align, 5047 const Value *DstSV, uint64_t DstSVOff) { 5048 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5049 5050 /// If not DWORD aligned or size is more than the threshold, call the library. 5051 /// The libc version is likely to be faster for these cases. It can use the 5052 /// address value and run time information about the CPU. 5053 if ((Align & 3) != 0 || 5054 !ConstantSize || 5055 ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) { 5056 SDValue InFlag(0, 0); 5057 5058 // Check to see if there is a specialized entry-point for memory zeroing. 5059 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5060 if (const char *bzeroEntry = 5061 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5062 MVT IntPtr = getPointerTy(); 5063 const Type *IntPtrTy = getTargetData()->getIntPtrType(); 5064 TargetLowering::ArgListTy Args; 5065 TargetLowering::ArgListEntry Entry; 5066 Entry.Node = Dst; 5067 Entry.Ty = IntPtrTy; 5068 Args.push_back(Entry); 5069 Entry.Node = Size; 5070 Args.push_back(Entry); 5071 std::pair<SDValue,SDValue> CallResult = 5072 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C, 5073 false, DAG.getExternalSymbol(bzeroEntry, IntPtr), 5074 Args, DAG); 5075 return CallResult.second; 5076 } 5077 5078 // Otherwise have the target-independent code call memset. 5079 return SDValue(); 5080 } 5081 5082 uint64_t SizeVal = ConstantSize->getValue(); 5083 SDValue InFlag(0, 0); 5084 MVT AVT; 5085 SDValue Count; 5086 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5087 unsigned BytesLeft = 0; 5088 bool TwoRepStos = false; 5089 if (ValC) { 5090 unsigned ValReg; 5091 uint64_t Val = ValC->getValue() & 255; 5092 5093 // If the value is a constant, then we can potentially use larger sets. 5094 switch (Align & 3) { 5095 case 2: // WORD aligned 5096 AVT = MVT::i16; 5097 ValReg = X86::AX; 5098 Val = (Val << 8) | Val; 5099 break; 5100 case 0: // DWORD aligned 5101 AVT = MVT::i32; 5102 ValReg = X86::EAX; 5103 Val = (Val << 8) | Val; 5104 Val = (Val << 16) | Val; 5105 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5106 AVT = MVT::i64; 5107 ValReg = X86::RAX; 5108 Val = (Val << 32) | Val; 5109 } 5110 break; 5111 default: // Byte aligned 5112 AVT = MVT::i8; 5113 ValReg = X86::AL; 5114 Count = DAG.getIntPtrConstant(SizeVal); 5115 break; 5116 } 5117 5118 if (AVT.bitsGT(MVT::i8)) { 5119 unsigned UBytes = AVT.getSizeInBits() / 8; 5120 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5121 BytesLeft = SizeVal % UBytes; 5122 } 5123 5124 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 5125 InFlag); 5126 InFlag = Chain.getValue(1); 5127 } else { 5128 AVT = MVT::i8; 5129 Count = DAG.getIntPtrConstant(SizeVal); 5130 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag); 5131 InFlag = Chain.getValue(1); 5132 } 5133 5134 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 5135 Count, InFlag); 5136 InFlag = Chain.getValue(1); 5137 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 5138 Dst, InFlag); 5139 InFlag = Chain.getValue(1); 5140 5141 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5142 SmallVector<SDValue, 8> Ops; 5143 Ops.push_back(Chain); 5144 Ops.push_back(DAG.getValueType(AVT)); 5145 Ops.push_back(InFlag); 5146 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 5147 5148 if (TwoRepStos) { 5149 InFlag = Chain.getValue(1); 5150 Count = Size; 5151 MVT CVT = Count.getValueType(); 5152 SDValue Left = DAG.getNode(ISD::AND, CVT, Count, 5153 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5154 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 5155 Left, InFlag); 5156 InFlag = Chain.getValue(1); 5157 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5158 Ops.clear(); 5159 Ops.push_back(Chain); 5160 Ops.push_back(DAG.getValueType(MVT::i8)); 5161 Ops.push_back(InFlag); 5162 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 5163 } else if (BytesLeft) { 5164 // Handle the last 1 - 7 bytes. 5165 unsigned Offset = SizeVal - BytesLeft; 5166 MVT AddrVT = Dst.getValueType(); 5167 MVT SizeVT = Size.getValueType(); 5168 5169 Chain = DAG.getMemset(Chain, 5170 DAG.getNode(ISD::ADD, AddrVT, Dst, 5171 DAG.getConstant(Offset, AddrVT)), 5172 Src, 5173 DAG.getConstant(BytesLeft, SizeVT), 5174 Align, DstSV, DstSVOff + Offset); 5175 } 5176 5177 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 5178 return Chain; 5179} 5180 5181SDValue 5182X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, 5183 SDValue Chain, SDValue Dst, SDValue Src, 5184 SDValue Size, unsigned Align, 5185 bool AlwaysInline, 5186 const Value *DstSV, uint64_t DstSVOff, 5187 const Value *SrcSV, uint64_t SrcSVOff) { 5188 // This requires the copy size to be a constant, preferrably 5189 // within a subtarget-specific limit. 5190 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5191 if (!ConstantSize) 5192 return SDValue(); 5193 uint64_t SizeVal = ConstantSize->getValue(); 5194 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 5195 return SDValue(); 5196 5197 /// If not DWORD aligned, call the library. 5198 if ((Align & 3) != 0) 5199 return SDValue(); 5200 5201 // DWORD aligned 5202 MVT AVT = MVT::i32; 5203 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 5204 AVT = MVT::i64; 5205 5206 unsigned UBytes = AVT.getSizeInBits() / 8; 5207 unsigned CountVal = SizeVal / UBytes; 5208 SDValue Count = DAG.getIntPtrConstant(CountVal); 5209 unsigned BytesLeft = SizeVal % UBytes; 5210 5211 SDValue InFlag(0, 0); 5212 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 5213 Count, InFlag); 5214 InFlag = Chain.getValue(1); 5215 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 5216 Dst, InFlag); 5217 InFlag = Chain.getValue(1); 5218 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 5219 Src, InFlag); 5220 InFlag = Chain.getValue(1); 5221 5222 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5223 SmallVector<SDValue, 8> Ops; 5224 Ops.push_back(Chain); 5225 Ops.push_back(DAG.getValueType(AVT)); 5226 Ops.push_back(InFlag); 5227 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 5228 5229 SmallVector<SDValue, 4> Results; 5230 Results.push_back(RepMovs); 5231 if (BytesLeft) { 5232 // Handle the last 1 - 7 bytes. 5233 unsigned Offset = SizeVal - BytesLeft; 5234 MVT DstVT = Dst.getValueType(); 5235 MVT SrcVT = Src.getValueType(); 5236 MVT SizeVT = Size.getValueType(); 5237 Results.push_back(DAG.getMemcpy(Chain, 5238 DAG.getNode(ISD::ADD, DstVT, Dst, 5239 DAG.getConstant(Offset, DstVT)), 5240 DAG.getNode(ISD::ADD, SrcVT, Src, 5241 DAG.getConstant(Offset, SrcVT)), 5242 DAG.getConstant(BytesLeft, SizeVT), 5243 Align, AlwaysInline, 5244 DstSV, DstSVOff + Offset, 5245 SrcSV, SrcSVOff + Offset)); 5246 } 5247 5248 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size()); 5249} 5250 5251/// Expand the result of: i64,outchain = READCYCLECOUNTER inchain 5252SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ 5253 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5254 SDValue TheChain = N->getOperand(0); 5255 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); 5256 if (Subtarget->is64Bit()) { 5257 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); 5258 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, 5259 MVT::i64, rax.getValue(2)); 5260 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, 5261 DAG.getConstant(32, MVT::i8)); 5262 SDValue Ops[] = { 5263 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1) 5264 }; 5265 5266 return DAG.getMergeValues(Ops, 2).Val; 5267 } 5268 5269 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); 5270 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, 5271 MVT::i32, eax.getValue(2)); 5272 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 5273 SDValue Ops[] = { eax, edx }; 5274 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2); 5275 5276 // Use a MERGE_VALUES to return the value and chain. 5277 Ops[1] = edx.getValue(1); 5278 return DAG.getMergeValues(Ops, 2).Val; 5279} 5280 5281SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 5282 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 5283 5284 if (!Subtarget->is64Bit()) { 5285 // vastart just stores the address of the VarArgsFrameIndex slot into the 5286 // memory location argument. 5287 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 5288 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); 5289 } 5290 5291 // __va_list_tag: 5292 // gp_offset (0 - 6 * 8) 5293 // fp_offset (48 - 48 + 8 * 16) 5294 // overflow_arg_area (point to parameters coming in memory). 5295 // reg_save_area 5296 SmallVector<SDValue, 8> MemOps; 5297 SDValue FIN = Op.getOperand(1); 5298 // Store gp_offset 5299 SDValue Store = DAG.getStore(Op.getOperand(0), 5300 DAG.getConstant(VarArgsGPOffset, MVT::i32), 5301 FIN, SV, 0); 5302 MemOps.push_back(Store); 5303 5304 // Store fp_offset 5305 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 5306 Store = DAG.getStore(Op.getOperand(0), 5307 DAG.getConstant(VarArgsFPOffset, MVT::i32), 5308 FIN, SV, 0); 5309 MemOps.push_back(Store); 5310 5311 // Store ptr to overflow_arg_area 5312 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 5313 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 5314 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); 5315 MemOps.push_back(Store); 5316 5317 // Store ptr to reg_save_area. 5318 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); 5319 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 5320 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); 5321 MemOps.push_back(Store); 5322 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 5323} 5324 5325SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 5326 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 5327 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 5328 SDValue Chain = Op.getOperand(0); 5329 SDValue SrcPtr = Op.getOperand(1); 5330 SDValue SrcSV = Op.getOperand(2); 5331 5332 assert(0 && "VAArgInst is not yet implemented for x86-64!"); 5333 abort(); 5334 return SDValue(); 5335} 5336 5337SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 5338 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 5339 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 5340 SDValue Chain = Op.getOperand(0); 5341 SDValue DstPtr = Op.getOperand(1); 5342 SDValue SrcPtr = Op.getOperand(2); 5343 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 5344 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 5345 5346 return DAG.getMemcpy(Chain, DstPtr, SrcPtr, 5347 DAG.getIntPtrConstant(24), 8, false, 5348 DstSV, 0, SrcSV, 0); 5349} 5350 5351SDValue 5352X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 5353 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 5354 switch (IntNo) { 5355 default: return SDValue(); // Don't custom lower most intrinsics. 5356 // Comparison intrinsics. 5357 case Intrinsic::x86_sse_comieq_ss: 5358 case Intrinsic::x86_sse_comilt_ss: 5359 case Intrinsic::x86_sse_comile_ss: 5360 case Intrinsic::x86_sse_comigt_ss: 5361 case Intrinsic::x86_sse_comige_ss: 5362 case Intrinsic::x86_sse_comineq_ss: 5363 case Intrinsic::x86_sse_ucomieq_ss: 5364 case Intrinsic::x86_sse_ucomilt_ss: 5365 case Intrinsic::x86_sse_ucomile_ss: 5366 case Intrinsic::x86_sse_ucomigt_ss: 5367 case Intrinsic::x86_sse_ucomige_ss: 5368 case Intrinsic::x86_sse_ucomineq_ss: 5369 case Intrinsic::x86_sse2_comieq_sd: 5370 case Intrinsic::x86_sse2_comilt_sd: 5371 case Intrinsic::x86_sse2_comile_sd: 5372 case Intrinsic::x86_sse2_comigt_sd: 5373 case Intrinsic::x86_sse2_comige_sd: 5374 case Intrinsic::x86_sse2_comineq_sd: 5375 case Intrinsic::x86_sse2_ucomieq_sd: 5376 case Intrinsic::x86_sse2_ucomilt_sd: 5377 case Intrinsic::x86_sse2_ucomile_sd: 5378 case Intrinsic::x86_sse2_ucomigt_sd: 5379 case Intrinsic::x86_sse2_ucomige_sd: 5380 case Intrinsic::x86_sse2_ucomineq_sd: { 5381 unsigned Opc = 0; 5382 ISD::CondCode CC = ISD::SETCC_INVALID; 5383 switch (IntNo) { 5384 default: break; 5385 case Intrinsic::x86_sse_comieq_ss: 5386 case Intrinsic::x86_sse2_comieq_sd: 5387 Opc = X86ISD::COMI; 5388 CC = ISD::SETEQ; 5389 break; 5390 case Intrinsic::x86_sse_comilt_ss: 5391 case Intrinsic::x86_sse2_comilt_sd: 5392 Opc = X86ISD::COMI; 5393 CC = ISD::SETLT; 5394 break; 5395 case Intrinsic::x86_sse_comile_ss: 5396 case Intrinsic::x86_sse2_comile_sd: 5397 Opc = X86ISD::COMI; 5398 CC = ISD::SETLE; 5399 break; 5400 case Intrinsic::x86_sse_comigt_ss: 5401 case Intrinsic::x86_sse2_comigt_sd: 5402 Opc = X86ISD::COMI; 5403 CC = ISD::SETGT; 5404 break; 5405 case Intrinsic::x86_sse_comige_ss: 5406 case Intrinsic::x86_sse2_comige_sd: 5407 Opc = X86ISD::COMI; 5408 CC = ISD::SETGE; 5409 break; 5410 case Intrinsic::x86_sse_comineq_ss: 5411 case Intrinsic::x86_sse2_comineq_sd: 5412 Opc = X86ISD::COMI; 5413 CC = ISD::SETNE; 5414 break; 5415 case Intrinsic::x86_sse_ucomieq_ss: 5416 case Intrinsic::x86_sse2_ucomieq_sd: 5417 Opc = X86ISD::UCOMI; 5418 CC = ISD::SETEQ; 5419 break; 5420 case Intrinsic::x86_sse_ucomilt_ss: 5421 case Intrinsic::x86_sse2_ucomilt_sd: 5422 Opc = X86ISD::UCOMI; 5423 CC = ISD::SETLT; 5424 break; 5425 case Intrinsic::x86_sse_ucomile_ss: 5426 case Intrinsic::x86_sse2_ucomile_sd: 5427 Opc = X86ISD::UCOMI; 5428 CC = ISD::SETLE; 5429 break; 5430 case Intrinsic::x86_sse_ucomigt_ss: 5431 case Intrinsic::x86_sse2_ucomigt_sd: 5432 Opc = X86ISD::UCOMI; 5433 CC = ISD::SETGT; 5434 break; 5435 case Intrinsic::x86_sse_ucomige_ss: 5436 case Intrinsic::x86_sse2_ucomige_sd: 5437 Opc = X86ISD::UCOMI; 5438 CC = ISD::SETGE; 5439 break; 5440 case Intrinsic::x86_sse_ucomineq_ss: 5441 case Intrinsic::x86_sse2_ucomineq_sd: 5442 Opc = X86ISD::UCOMI; 5443 CC = ISD::SETNE; 5444 break; 5445 } 5446 5447 unsigned X86CC; 5448 SDValue LHS = Op.getOperand(1); 5449 SDValue RHS = Op.getOperand(2); 5450 translateX86CC(CC, true, X86CC, LHS, RHS, DAG); 5451 5452 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); 5453 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, 5454 DAG.getConstant(X86CC, MVT::i8), Cond); 5455 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC); 5456 } 5457 5458 // Fix vector shift instructions where the last operand is a non-immediate 5459 // i32 value. 5460 case Intrinsic::x86_sse2_pslli_w: 5461 case Intrinsic::x86_sse2_pslli_d: 5462 case Intrinsic::x86_sse2_pslli_q: 5463 case Intrinsic::x86_sse2_psrli_w: 5464 case Intrinsic::x86_sse2_psrli_d: 5465 case Intrinsic::x86_sse2_psrli_q: 5466 case Intrinsic::x86_sse2_psrai_w: 5467 case Intrinsic::x86_sse2_psrai_d: 5468 case Intrinsic::x86_mmx_pslli_w: 5469 case Intrinsic::x86_mmx_pslli_d: 5470 case Intrinsic::x86_mmx_pslli_q: 5471 case Intrinsic::x86_mmx_psrli_w: 5472 case Intrinsic::x86_mmx_psrli_d: 5473 case Intrinsic::x86_mmx_psrli_q: 5474 case Intrinsic::x86_mmx_psrai_w: 5475 case Intrinsic::x86_mmx_psrai_d: { 5476 SDValue ShAmt = Op.getOperand(2); 5477 if (isa<ConstantSDNode>(ShAmt)) 5478 return SDValue(); 5479 5480 unsigned NewIntNo = 0; 5481 MVT ShAmtVT = MVT::v4i32; 5482 switch (IntNo) { 5483 case Intrinsic::x86_sse2_pslli_w: 5484 NewIntNo = Intrinsic::x86_sse2_psll_w; 5485 break; 5486 case Intrinsic::x86_sse2_pslli_d: 5487 NewIntNo = Intrinsic::x86_sse2_psll_d; 5488 break; 5489 case Intrinsic::x86_sse2_pslli_q: 5490 NewIntNo = Intrinsic::x86_sse2_psll_q; 5491 break; 5492 case Intrinsic::x86_sse2_psrli_w: 5493 NewIntNo = Intrinsic::x86_sse2_psrl_w; 5494 break; 5495 case Intrinsic::x86_sse2_psrli_d: 5496 NewIntNo = Intrinsic::x86_sse2_psrl_d; 5497 break; 5498 case Intrinsic::x86_sse2_psrli_q: 5499 NewIntNo = Intrinsic::x86_sse2_psrl_q; 5500 break; 5501 case Intrinsic::x86_sse2_psrai_w: 5502 NewIntNo = Intrinsic::x86_sse2_psra_w; 5503 break; 5504 case Intrinsic::x86_sse2_psrai_d: 5505 NewIntNo = Intrinsic::x86_sse2_psra_d; 5506 break; 5507 default: { 5508 ShAmtVT = MVT::v2i32; 5509 switch (IntNo) { 5510 case Intrinsic::x86_mmx_pslli_w: 5511 NewIntNo = Intrinsic::x86_mmx_psll_w; 5512 break; 5513 case Intrinsic::x86_mmx_pslli_d: 5514 NewIntNo = Intrinsic::x86_mmx_psll_d; 5515 break; 5516 case Intrinsic::x86_mmx_pslli_q: 5517 NewIntNo = Intrinsic::x86_mmx_psll_q; 5518 break; 5519 case Intrinsic::x86_mmx_psrli_w: 5520 NewIntNo = Intrinsic::x86_mmx_psrl_w; 5521 break; 5522 case Intrinsic::x86_mmx_psrli_d: 5523 NewIntNo = Intrinsic::x86_mmx_psrl_d; 5524 break; 5525 case Intrinsic::x86_mmx_psrli_q: 5526 NewIntNo = Intrinsic::x86_mmx_psrl_q; 5527 break; 5528 case Intrinsic::x86_mmx_psrai_w: 5529 NewIntNo = Intrinsic::x86_mmx_psra_w; 5530 break; 5531 case Intrinsic::x86_mmx_psrai_d: 5532 NewIntNo = Intrinsic::x86_mmx_psra_d; 5533 break; 5534 default: abort(); // Can't reach here. 5535 } 5536 break; 5537 } 5538 } 5539 MVT VT = Op.getValueType(); 5540 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT, 5541 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt)); 5542 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT, 5543 DAG.getConstant(NewIntNo, MVT::i32), 5544 Op.getOperand(1), ShAmt); 5545 } 5546 } 5547} 5548 5549SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 5550 // Depths > 0 not supported yet! 5551 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 5552 return SDValue(); 5553 5554 // Just load the return address 5555 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 5556 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 5557} 5558 5559SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 5560 // Depths > 0 not supported yet! 5561 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 5562 return SDValue(); 5563 5564 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 5565 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, 5566 DAG.getIntPtrConstant(!Subtarget->is64Bit() ? 4 : 8)); 5567} 5568 5569SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 5570 SelectionDAG &DAG) { 5571 // Is not yet supported on x86-64 5572 if (Subtarget->is64Bit()) 5573 return SDValue(); 5574 5575 return DAG.getIntPtrConstant(8); 5576} 5577 5578SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 5579{ 5580 assert(!Subtarget->is64Bit() && 5581 "Lowering of eh_return builtin is not supported yet on x86-64"); 5582 5583 MachineFunction &MF = DAG.getMachineFunction(); 5584 SDValue Chain = Op.getOperand(0); 5585 SDValue Offset = Op.getOperand(1); 5586 SDValue Handler = Op.getOperand(2); 5587 5588 SDValue Frame = DAG.getRegister(RegInfo->getFrameRegister(MF), 5589 getPointerTy()); 5590 5591 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, 5592 DAG.getIntPtrConstant(-4UL)); 5593 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); 5594 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); 5595 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr); 5596 MF.getRegInfo().addLiveOut(X86::ECX); 5597 5598 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other, 5599 Chain, DAG.getRegister(X86::ECX, getPointerTy())); 5600} 5601 5602SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 5603 SelectionDAG &DAG) { 5604 SDValue Root = Op.getOperand(0); 5605 SDValue Trmp = Op.getOperand(1); // trampoline 5606 SDValue FPtr = Op.getOperand(2); // nested function 5607 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 5608 5609 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 5610 5611 const X86InstrInfo *TII = 5612 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 5613 5614 if (Subtarget->is64Bit()) { 5615 SDValue OutChains[6]; 5616 5617 // Large code-model. 5618 5619 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 5620 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 5621 5622 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 5623 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 5624 5625 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 5626 5627 // Load the pointer to the nested function into R11. 5628 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 5629 SDValue Addr = Trmp; 5630 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5631 TrmpAddr, 0); 5632 5633 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); 5634 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); 5635 5636 // Load the 'nest' parameter value into R10. 5637 // R10 is specified in X86CallingConv.td 5638 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 5639 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); 5640 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5641 TrmpAddr, 10); 5642 5643 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); 5644 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); 5645 5646 // Jump to the nested function. 5647 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 5648 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); 5649 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5650 TrmpAddr, 20); 5651 5652 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 5653 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); 5654 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, 5655 TrmpAddr, 22); 5656 5657 SDValue Ops[] = 5658 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; 5659 return DAG.getMergeValues(Ops, 2); 5660 } else { 5661 const Function *Func = 5662 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 5663 unsigned CC = Func->getCallingConv(); 5664 unsigned NestReg; 5665 5666 switch (CC) { 5667 default: 5668 assert(0 && "Unsupported calling convention"); 5669 case CallingConv::C: 5670 case CallingConv::X86_StdCall: { 5671 // Pass 'nest' parameter in ECX. 5672 // Must be kept in sync with X86CallingConv.td 5673 NestReg = X86::ECX; 5674 5675 // Check that ECX wasn't needed by an 'inreg' parameter. 5676 const FunctionType *FTy = Func->getFunctionType(); 5677 const PAListPtr &Attrs = Func->getParamAttrs(); 5678 5679 if (!Attrs.isEmpty() && !Func->isVarArg()) { 5680 unsigned InRegCount = 0; 5681 unsigned Idx = 1; 5682 5683 for (FunctionType::param_iterator I = FTy->param_begin(), 5684 E = FTy->param_end(); I != E; ++I, ++Idx) 5685 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg)) 5686 // FIXME: should only count parameters that are lowered to integers. 5687 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32; 5688 5689 if (InRegCount > 2) { 5690 cerr << "Nest register in use - reduce number of inreg parameters!\n"; 5691 abort(); 5692 } 5693 } 5694 break; 5695 } 5696 case CallingConv::X86_FastCall: 5697 // Pass 'nest' parameter in EAX. 5698 // Must be kept in sync with X86CallingConv.td 5699 NestReg = X86::EAX; 5700 break; 5701 } 5702 5703 SDValue OutChains[4]; 5704 SDValue Addr, Disp; 5705 5706 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); 5707 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); 5708 5709 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 5710 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 5711 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 5712 Trmp, TrmpAddr, 0); 5713 5714 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); 5715 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); 5716 5717 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 5718 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); 5719 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, 5720 TrmpAddr, 5, false, 1); 5721 5722 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); 5723 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); 5724 5725 SDValue Ops[] = 5726 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; 5727 return DAG.getMergeValues(Ops, 2); 5728 } 5729} 5730 5731SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 5732 /* 5733 The rounding mode is in bits 11:10 of FPSR, and has the following 5734 settings: 5735 00 Round to nearest 5736 01 Round to -inf 5737 10 Round to +inf 5738 11 Round to 0 5739 5740 FLT_ROUNDS, on the other hand, expects the following: 5741 -1 Undefined 5742 0 Round to 0 5743 1 Round to nearest 5744 2 Round to +inf 5745 3 Round to -inf 5746 5747 To perform the conversion, we do: 5748 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 5749 */ 5750 5751 MachineFunction &MF = DAG.getMachineFunction(); 5752 const TargetMachine &TM = MF.getTarget(); 5753 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 5754 unsigned StackAlignment = TFI.getStackAlignment(); 5755 MVT VT = Op.getValueType(); 5756 5757 // Save FP Control Word to stack slot 5758 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 5759 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5760 5761 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, 5762 DAG.getEntryNode(), StackSlot); 5763 5764 // Load FP Control Word from stack slot 5765 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); 5766 5767 // Transform as necessary 5768 SDValue CWD1 = 5769 DAG.getNode(ISD::SRL, MVT::i16, 5770 DAG.getNode(ISD::AND, MVT::i16, 5771 CWD, DAG.getConstant(0x800, MVT::i16)), 5772 DAG.getConstant(11, MVT::i8)); 5773 SDValue CWD2 = 5774 DAG.getNode(ISD::SRL, MVT::i16, 5775 DAG.getNode(ISD::AND, MVT::i16, 5776 CWD, DAG.getConstant(0x400, MVT::i16)), 5777 DAG.getConstant(9, MVT::i8)); 5778 5779 SDValue RetVal = 5780 DAG.getNode(ISD::AND, MVT::i16, 5781 DAG.getNode(ISD::ADD, MVT::i16, 5782 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), 5783 DAG.getConstant(1, MVT::i16)), 5784 DAG.getConstant(3, MVT::i16)); 5785 5786 5787 return DAG.getNode((VT.getSizeInBits() < 16 ? 5788 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 5789} 5790 5791SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 5792 MVT VT = Op.getValueType(); 5793 MVT OpVT = VT; 5794 unsigned NumBits = VT.getSizeInBits(); 5795 5796 Op = Op.getOperand(0); 5797 if (VT == MVT::i8) { 5798 // Zero extend to i32 since there is not an i8 bsr. 5799 OpVT = MVT::i32; 5800 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 5801 } 5802 5803 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 5804 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 5805 Op = DAG.getNode(X86ISD::BSR, VTs, Op); 5806 5807 // If src is zero (i.e. bsr sets ZF), returns NumBits. 5808 SmallVector<SDValue, 4> Ops; 5809 Ops.push_back(Op); 5810 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 5811 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 5812 Ops.push_back(Op.getValue(1)); 5813 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 5814 5815 // Finally xor with NumBits-1. 5816 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 5817 5818 if (VT == MVT::i8) 5819 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 5820 return Op; 5821} 5822 5823SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 5824 MVT VT = Op.getValueType(); 5825 MVT OpVT = VT; 5826 unsigned NumBits = VT.getSizeInBits(); 5827 5828 Op = Op.getOperand(0); 5829 if (VT == MVT::i8) { 5830 OpVT = MVT::i32; 5831 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 5832 } 5833 5834 // Issue a bsf (scan bits forward) which also sets EFLAGS. 5835 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 5836 Op = DAG.getNode(X86ISD::BSF, VTs, Op); 5837 5838 // If src is zero (i.e. bsf sets ZF), returns NumBits. 5839 SmallVector<SDValue, 4> Ops; 5840 Ops.push_back(Op); 5841 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 5842 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 5843 Ops.push_back(Op.getValue(1)); 5844 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 5845 5846 if (VT == MVT::i8) 5847 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 5848 return Op; 5849} 5850 5851SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 5852 MVT T = Op.getValueType(); 5853 unsigned Reg = 0; 5854 unsigned size = 0; 5855 switch(T.getSimpleVT()) { 5856 default: 5857 assert(false && "Invalid value type!"); 5858 case MVT::i8: Reg = X86::AL; size = 1; break; 5859 case MVT::i16: Reg = X86::AX; size = 2; break; 5860 case MVT::i32: Reg = X86::EAX; size = 4; break; 5861 case MVT::i64: 5862 if (Subtarget->is64Bit()) { 5863 Reg = X86::RAX; size = 8; 5864 } else //Should go away when LowerType stuff lands 5865 return SDValue(ExpandATOMIC_CMP_SWAP(Op.Val, DAG), 0); 5866 break; 5867 }; 5868 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, 5869 Op.getOperand(3), SDValue()); 5870 SDValue Ops[] = { cpIn.getValue(0), 5871 Op.getOperand(1), 5872 Op.getOperand(2), 5873 DAG.getTargetConstant(size, MVT::i8), 5874 cpIn.getValue(1) }; 5875 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5876 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); 5877 SDValue cpOut = 5878 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); 5879 return cpOut; 5880} 5881 5882SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) { 5883 MVT T = Op->getValueType(0); 5884 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 5885 SDValue cpInL, cpInH; 5886 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), 5887 DAG.getConstant(0, MVT::i32)); 5888 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), 5889 DAG.getConstant(1, MVT::i32)); 5890 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX, 5891 cpInL, SDValue()); 5892 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, 5893 cpInH, cpInL.getValue(1)); 5894 SDValue swapInL, swapInH; 5895 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), 5896 DAG.getConstant(0, MVT::i32)); 5897 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), 5898 DAG.getConstant(1, MVT::i32)); 5899 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, 5900 swapInL, cpInH.getValue(1)); 5901 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, 5902 swapInH, swapInL.getValue(1)); 5903 SDValue Ops[] = { swapInH.getValue(0), 5904 Op->getOperand(1), 5905 swapInH.getValue(1)}; 5906 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5907 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); 5908 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, 5909 Result.getValue(1)); 5910 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, 5911 cpOutL.getValue(2)); 5912 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 5913 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); 5914 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) }; 5915 return DAG.getMergeValues(Vals, 2).Val; 5916} 5917 5918SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) { 5919 MVT T = Op->getValueType(0); 5920 SDValue negOp = DAG.getNode(ISD::SUB, T, 5921 DAG.getConstant(0, T), Op->getOperand(2)); 5922 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, Op->getOperand(0), 5923 Op->getOperand(1), negOp, 5924 cast<AtomicSDNode>(Op)->getSrcValue(), 5925 cast<AtomicSDNode>(Op)->getAlignment()).Val; 5926} 5927 5928/// LowerOperation - Provide custom lowering hooks for some operations. 5929/// 5930SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 5931 switch (Op.getOpcode()) { 5932 default: assert(0 && "Should not custom lower this!"); 5933 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 5934 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5935 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5936 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 5937 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 5938 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5939 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5940 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5941 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5942 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 5943 case ISD::SHL_PARTS: 5944 case ISD::SRA_PARTS: 5945 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 5946 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 5947 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 5948 case ISD::FABS: return LowerFABS(Op, DAG); 5949 case ISD::FNEG: return LowerFNEG(Op, DAG); 5950 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 5951 case ISD::SETCC: return LowerSETCC(Op, DAG); 5952 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 5953 case ISD::SELECT: return LowerSELECT(Op, DAG); 5954 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 5955 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5956 case ISD::CALL: return LowerCALL(Op, DAG); 5957 case ISD::RET: return LowerRET(Op, DAG); 5958 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 5959 case ISD::VASTART: return LowerVASTART(Op, DAG); 5960 case ISD::VAARG: return LowerVAARG(Op, DAG); 5961 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 5962 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5963 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5964 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5965 case ISD::FRAME_TO_ARGS_OFFSET: 5966 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 5967 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 5968 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 5969 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 5970 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5971 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 5972 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 5973 5974 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands. 5975 case ISD::READCYCLECOUNTER: 5976 return SDValue(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0); 5977 } 5978} 5979 5980/// ReplaceNodeResults - Replace a node with an illegal result type 5981/// with a new node built out of custom code. 5982SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 5983 switch (N->getOpcode()) { 5984 default: assert(0 && "Should not custom lower this!"); 5985 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG); 5986 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG); 5987 case ISD::ATOMIC_CMP_SWAP: return ExpandATOMIC_CMP_SWAP(N, DAG); 5988 case ISD::ATOMIC_LOAD_SUB: return ExpandATOMIC_LOAD_SUB(N,DAG); 5989 } 5990} 5991 5992const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 5993 switch (Opcode) { 5994 default: return NULL; 5995 case X86ISD::BSF: return "X86ISD::BSF"; 5996 case X86ISD::BSR: return "X86ISD::BSR"; 5997 case X86ISD::SHLD: return "X86ISD::SHLD"; 5998 case X86ISD::SHRD: return "X86ISD::SHRD"; 5999 case X86ISD::FAND: return "X86ISD::FAND"; 6000 case X86ISD::FOR: return "X86ISD::FOR"; 6001 case X86ISD::FXOR: return "X86ISD::FXOR"; 6002 case X86ISD::FSRL: return "X86ISD::FSRL"; 6003 case X86ISD::FILD: return "X86ISD::FILD"; 6004 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 6005 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 6006 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 6007 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 6008 case X86ISD::FLD: return "X86ISD::FLD"; 6009 case X86ISD::FST: return "X86ISD::FST"; 6010 case X86ISD::CALL: return "X86ISD::CALL"; 6011 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 6012 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 6013 case X86ISD::CMP: return "X86ISD::CMP"; 6014 case X86ISD::COMI: return "X86ISD::COMI"; 6015 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 6016 case X86ISD::SETCC: return "X86ISD::SETCC"; 6017 case X86ISD::CMOV: return "X86ISD::CMOV"; 6018 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 6019 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 6020 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 6021 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 6022 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 6023 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 6024 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 6025 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 6026 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 6027 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 6028 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 6029 case X86ISD::FMAX: return "X86ISD::FMAX"; 6030 case X86ISD::FMIN: return "X86ISD::FMIN"; 6031 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 6032 case X86ISD::FRCP: return "X86ISD::FRCP"; 6033 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 6034 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; 6035 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 6036 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 6037 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 6038 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 6039 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 6040 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 6041 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 6042 case X86ISD::VSHL: return "X86ISD::VSHL"; 6043 case X86ISD::VSRL: return "X86ISD::VSRL"; 6044 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 6045 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 6046 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 6047 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 6048 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 6049 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 6050 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 6051 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 6052 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 6053 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 6054 } 6055} 6056 6057// isLegalAddressingMode - Return true if the addressing mode represented 6058// by AM is legal for this target, for a load/store of the specified type. 6059bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 6060 const Type *Ty) const { 6061 // X86 supports extremely general addressing modes. 6062 6063 // X86 allows a sign-extended 32-bit immediate field as a displacement. 6064 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) 6065 return false; 6066 6067 if (AM.BaseGV) { 6068 // We can only fold this if we don't need an extra load. 6069 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) 6070 return false; 6071 6072 // X86-64 only supports addr of globals in small code model. 6073 if (Subtarget->is64Bit()) { 6074 if (getTargetMachine().getCodeModel() != CodeModel::Small) 6075 return false; 6076 // If lower 4G is not available, then we must use rip-relative addressing. 6077 if (AM.BaseOffs || AM.Scale > 1) 6078 return false; 6079 } 6080 } 6081 6082 switch (AM.Scale) { 6083 case 0: 6084 case 1: 6085 case 2: 6086 case 4: 6087 case 8: 6088 // These scales always work. 6089 break; 6090 case 3: 6091 case 5: 6092 case 9: 6093 // These scales are formed with basereg+scalereg. Only accept if there is 6094 // no basereg yet. 6095 if (AM.HasBaseReg) 6096 return false; 6097 break; 6098 default: // Other stuff never works. 6099 return false; 6100 } 6101 6102 return true; 6103} 6104 6105 6106bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 6107 if (!Ty1->isInteger() || !Ty2->isInteger()) 6108 return false; 6109 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6110 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6111 if (NumBits1 <= NumBits2) 6112 return false; 6113 return Subtarget->is64Bit() || NumBits1 < 64; 6114} 6115 6116bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { 6117 if (!VT1.isInteger() || !VT2.isInteger()) 6118 return false; 6119 unsigned NumBits1 = VT1.getSizeInBits(); 6120 unsigned NumBits2 = VT2.getSizeInBits(); 6121 if (NumBits1 <= NumBits2) 6122 return false; 6123 return Subtarget->is64Bit() || NumBits1 < 64; 6124} 6125 6126/// isShuffleMaskLegal - Targets can use this to indicate that they only 6127/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 6128/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 6129/// are assumed to be legal. 6130bool 6131X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const { 6132 // Only do shuffles on 128-bit vector types for now. 6133 if (VT.getSizeInBits() == 64) return false; 6134 return (Mask.Val->getNumOperands() <= 4 || 6135 isIdentityMask(Mask.Val) || 6136 isIdentityMask(Mask.Val, true) || 6137 isSplatMask(Mask.Val) || 6138 isPSHUFHW_PSHUFLWMask(Mask.Val) || 6139 X86::isUNPCKLMask(Mask.Val) || 6140 X86::isUNPCKHMask(Mask.Val) || 6141 X86::isUNPCKL_v_undef_Mask(Mask.Val) || 6142 X86::isUNPCKH_v_undef_Mask(Mask.Val)); 6143} 6144 6145bool 6146X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps, 6147 MVT EVT, SelectionDAG &DAG) const { 6148 unsigned NumElts = BVOps.size(); 6149 // Only do shuffles on 128-bit vector types for now. 6150 if (EVT.getSizeInBits() * NumElts == 64) return false; 6151 if (NumElts == 2) return true; 6152 if (NumElts == 4) { 6153 return (isMOVLMask(&BVOps[0], 4) || 6154 isCommutedMOVL(&BVOps[0], 4, true) || 6155 isSHUFPMask(&BVOps[0], 4) || 6156 isCommutedSHUFP(&BVOps[0], 4)); 6157 } 6158 return false; 6159} 6160 6161//===----------------------------------------------------------------------===// 6162// X86 Scheduler Hooks 6163//===----------------------------------------------------------------------===// 6164 6165// private utility function 6166MachineBasicBlock * 6167X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 6168 MachineBasicBlock *MBB, 6169 unsigned regOpc, 6170 unsigned immOpc, 6171 unsigned LoadOpc, 6172 unsigned CXchgOpc, 6173 unsigned copyOpc, 6174 unsigned notOpc, 6175 unsigned EAXreg, 6176 TargetRegisterClass *RC, 6177 bool invSrc) { 6178 // For the atomic bitwise operator, we generate 6179 // thisMBB: 6180 // newMBB: 6181 // ld t1 = [bitinstr.addr] 6182 // op t2 = t1, [bitinstr.val] 6183 // mov EAX = t1 6184 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 6185 // bz newMBB 6186 // fallthrough -->nextMBB 6187 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6188 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6189 MachineFunction::iterator MBBIter = MBB; 6190 ++MBBIter; 6191 6192 /// First build the CFG 6193 MachineFunction *F = MBB->getParent(); 6194 MachineBasicBlock *thisMBB = MBB; 6195 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6196 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6197 F->insert(MBBIter, newMBB); 6198 F->insert(MBBIter, nextMBB); 6199 6200 // Move all successors to thisMBB to nextMBB 6201 nextMBB->transferSuccessors(thisMBB); 6202 6203 // Update thisMBB to fall through to newMBB 6204 thisMBB->addSuccessor(newMBB); 6205 6206 // newMBB jumps to itself and fall through to nextMBB 6207 newMBB->addSuccessor(nextMBB); 6208 newMBB->addSuccessor(newMBB); 6209 6210 // Insert instructions into newMBB based on incoming instruction 6211 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands"); 6212 MachineOperand& destOper = bInstr->getOperand(0); 6213 MachineOperand* argOpers[6]; 6214 int numArgs = bInstr->getNumOperands() - 1; 6215 for (int i=0; i < numArgs; ++i) 6216 argOpers[i] = &bInstr->getOperand(i+1); 6217 6218 // x86 address has 4 operands: base, index, scale, and displacement 6219 int lastAddrIndx = 3; // [0,3] 6220 int valArgIndx = 4; 6221 6222 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 6223 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1); 6224 for (int i=0; i <= lastAddrIndx; ++i) 6225 (*MIB).addOperand(*argOpers[i]); 6226 6227 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 6228 if (invSrc) { 6229 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1); 6230 } 6231 else 6232 tt = t1; 6233 6234 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 6235 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm()) 6236 && "invalid operand"); 6237 if (argOpers[valArgIndx]->isReg()) 6238 MIB = BuildMI(newMBB, TII->get(regOpc), t2); 6239 else 6240 MIB = BuildMI(newMBB, TII->get(immOpc), t2); 6241 MIB.addReg(tt); 6242 (*MIB).addOperand(*argOpers[valArgIndx]); 6243 6244 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg); 6245 MIB.addReg(t1); 6246 6247 MIB = BuildMI(newMBB, TII->get(CXchgOpc)); 6248 for (int i=0; i <= lastAddrIndx; ++i) 6249 (*MIB).addOperand(*argOpers[i]); 6250 MIB.addReg(t2); 6251 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 6252 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 6253 6254 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg()); 6255 MIB.addReg(EAXreg); 6256 6257 // insert branch 6258 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 6259 6260 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 6261 return nextMBB; 6262} 6263 6264// private utility function 6265MachineBasicBlock * 6266X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 6267 MachineBasicBlock *MBB, 6268 unsigned cmovOpc) { 6269 // For the atomic min/max operator, we generate 6270 // thisMBB: 6271 // newMBB: 6272 // ld t1 = [min/max.addr] 6273 // mov t2 = [min/max.val] 6274 // cmp t1, t2 6275 // cmov[cond] t2 = t1 6276 // mov EAX = t1 6277 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 6278 // bz newMBB 6279 // fallthrough -->nextMBB 6280 // 6281 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6282 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 6283 MachineFunction::iterator MBBIter = MBB; 6284 ++MBBIter; 6285 6286 /// First build the CFG 6287 MachineFunction *F = MBB->getParent(); 6288 MachineBasicBlock *thisMBB = MBB; 6289 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 6290 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 6291 F->insert(MBBIter, newMBB); 6292 F->insert(MBBIter, nextMBB); 6293 6294 // Move all successors to thisMBB to nextMBB 6295 nextMBB->transferSuccessors(thisMBB); 6296 6297 // Update thisMBB to fall through to newMBB 6298 thisMBB->addSuccessor(newMBB); 6299 6300 // newMBB jumps to newMBB and fall through to nextMBB 6301 newMBB->addSuccessor(nextMBB); 6302 newMBB->addSuccessor(newMBB); 6303 6304 // Insert instructions into newMBB based on incoming instruction 6305 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands"); 6306 MachineOperand& destOper = mInstr->getOperand(0); 6307 MachineOperand* argOpers[6]; 6308 int numArgs = mInstr->getNumOperands() - 1; 6309 for (int i=0; i < numArgs; ++i) 6310 argOpers[i] = &mInstr->getOperand(i+1); 6311 6312 // x86 address has 4 operands: base, index, scale, and displacement 6313 int lastAddrIndx = 3; // [0,3] 6314 int valArgIndx = 4; 6315 6316 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 6317 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1); 6318 for (int i=0; i <= lastAddrIndx; ++i) 6319 (*MIB).addOperand(*argOpers[i]); 6320 6321 // We only support register and immediate values 6322 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm()) 6323 && "invalid operand"); 6324 6325 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 6326 if (argOpers[valArgIndx]->isReg()) 6327 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); 6328 else 6329 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2); 6330 (*MIB).addOperand(*argOpers[valArgIndx]); 6331 6332 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX); 6333 MIB.addReg(t1); 6334 6335 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr)); 6336 MIB.addReg(t1); 6337 MIB.addReg(t2); 6338 6339 // Generate movc 6340 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 6341 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3); 6342 MIB.addReg(t2); 6343 MIB.addReg(t1); 6344 6345 // Cmp and exchange if none has modified the memory location 6346 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32)); 6347 for (int i=0; i <= lastAddrIndx; ++i) 6348 (*MIB).addOperand(*argOpers[i]); 6349 MIB.addReg(t3); 6350 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 6351 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 6352 6353 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); 6354 MIB.addReg(X86::EAX); 6355 6356 // insert branch 6357 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB); 6358 6359 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 6360 return nextMBB; 6361} 6362 6363 6364MachineBasicBlock * 6365X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 6366 MachineBasicBlock *BB) { 6367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6368 switch (MI->getOpcode()) { 6369 default: assert(false && "Unexpected instr type to insert"); 6370 case X86::CMOV_FR32: 6371 case X86::CMOV_FR64: 6372 case X86::CMOV_V4F32: 6373 case X86::CMOV_V2F64: 6374 case X86::CMOV_V2I64: { 6375 // To "insert" a SELECT_CC instruction, we actually have to insert the 6376 // diamond control-flow pattern. The incoming instruction knows the 6377 // destination vreg to set, the condition code register to branch on, the 6378 // true/false values to select between, and a branch opcode to use. 6379 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6380 MachineFunction::iterator It = BB; 6381 ++It; 6382 6383 // thisMBB: 6384 // ... 6385 // TrueVal = ... 6386 // cmpTY ccX, r1, r2 6387 // bCC copy1MBB 6388 // fallthrough --> copy0MBB 6389 MachineBasicBlock *thisMBB = BB; 6390 MachineFunction *F = BB->getParent(); 6391 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6392 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6393 unsigned Opc = 6394 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 6395 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 6396 F->insert(It, copy0MBB); 6397 F->insert(It, sinkMBB); 6398 // Update machine-CFG edges by transferring all successors of the current 6399 // block to the new block which will contain the Phi node for the select. 6400 sinkMBB->transferSuccessors(BB); 6401 6402 // Add the true and fallthrough blocks as its successors. 6403 BB->addSuccessor(copy0MBB); 6404 BB->addSuccessor(sinkMBB); 6405 6406 // copy0MBB: 6407 // %FalseValue = ... 6408 // # fallthrough to sinkMBB 6409 BB = copy0MBB; 6410 6411 // Update machine-CFG edges 6412 BB->addSuccessor(sinkMBB); 6413 6414 // sinkMBB: 6415 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6416 // ... 6417 BB = sinkMBB; 6418 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) 6419 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6420 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6421 6422 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 6423 return BB; 6424 } 6425 6426 case X86::FP32_TO_INT16_IN_MEM: 6427 case X86::FP32_TO_INT32_IN_MEM: 6428 case X86::FP32_TO_INT64_IN_MEM: 6429 case X86::FP64_TO_INT16_IN_MEM: 6430 case X86::FP64_TO_INT32_IN_MEM: 6431 case X86::FP64_TO_INT64_IN_MEM: 6432 case X86::FP80_TO_INT16_IN_MEM: 6433 case X86::FP80_TO_INT32_IN_MEM: 6434 case X86::FP80_TO_INT64_IN_MEM: { 6435 // Change the floating point control register to use "round towards zero" 6436 // mode when truncating to an integer value. 6437 MachineFunction *F = BB->getParent(); 6438 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 6439 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); 6440 6441 // Load the old value of the high byte of the control word... 6442 unsigned OldCW = 6443 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 6444 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); 6445 6446 // Set the high part to be round to zero... 6447 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) 6448 .addImm(0xC7F); 6449 6450 // Reload the modified control word now... 6451 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 6452 6453 // Restore the memory image of control word to original value 6454 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) 6455 .addReg(OldCW); 6456 6457 // Get the X86 opcode to use. 6458 unsigned Opc; 6459 switch (MI->getOpcode()) { 6460 default: assert(0 && "illegal opcode!"); 6461 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 6462 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 6463 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 6464 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 6465 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 6466 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 6467 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 6468 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 6469 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 6470 } 6471 6472 X86AddressMode AM; 6473 MachineOperand &Op = MI->getOperand(0); 6474 if (Op.isRegister()) { 6475 AM.BaseType = X86AddressMode::RegBase; 6476 AM.Base.Reg = Op.getReg(); 6477 } else { 6478 AM.BaseType = X86AddressMode::FrameIndexBase; 6479 AM.Base.FrameIndex = Op.getIndex(); 6480 } 6481 Op = MI->getOperand(1); 6482 if (Op.isImmediate()) 6483 AM.Scale = Op.getImm(); 6484 Op = MI->getOperand(2); 6485 if (Op.isImmediate()) 6486 AM.IndexReg = Op.getImm(); 6487 Op = MI->getOperand(3); 6488 if (Op.isGlobalAddress()) { 6489 AM.GV = Op.getGlobal(); 6490 } else { 6491 AM.Disp = Op.getImm(); 6492 } 6493 addFullAddress(BuildMI(BB, TII->get(Opc)), AM) 6494 .addReg(MI->getOperand(4).getReg()); 6495 6496 // Reload the original control word now. 6497 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 6498 6499 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 6500 return BB; 6501 } 6502 case X86::ATOMAND32: 6503 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 6504 X86::AND32ri, X86::MOV32rm, 6505 X86::LCMPXCHG32, X86::MOV32rr, 6506 X86::NOT32r, X86::EAX, 6507 X86::GR32RegisterClass); 6508 case X86::ATOMOR32: 6509 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 6510 X86::OR32ri, X86::MOV32rm, 6511 X86::LCMPXCHG32, X86::MOV32rr, 6512 X86::NOT32r, X86::EAX, 6513 X86::GR32RegisterClass); 6514 case X86::ATOMXOR32: 6515 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 6516 X86::XOR32ri, X86::MOV32rm, 6517 X86::LCMPXCHG32, X86::MOV32rr, 6518 X86::NOT32r, X86::EAX, 6519 X86::GR32RegisterClass); 6520 case X86::ATOMNAND32: 6521 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 6522 X86::AND32ri, X86::MOV32rm, 6523 X86::LCMPXCHG32, X86::MOV32rr, 6524 X86::NOT32r, X86::EAX, 6525 X86::GR32RegisterClass, true); 6526 case X86::ATOMMIN32: 6527 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 6528 case X86::ATOMMAX32: 6529 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 6530 case X86::ATOMUMIN32: 6531 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 6532 case X86::ATOMUMAX32: 6533 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 6534 6535 case X86::ATOMAND16: 6536 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 6537 X86::AND16ri, X86::MOV16rm, 6538 X86::LCMPXCHG16, X86::MOV16rr, 6539 X86::NOT16r, X86::AX, 6540 X86::GR16RegisterClass); 6541 case X86::ATOMOR16: 6542 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 6543 X86::OR16ri, X86::MOV16rm, 6544 X86::LCMPXCHG16, X86::MOV16rr, 6545 X86::NOT16r, X86::AX, 6546 X86::GR16RegisterClass); 6547 case X86::ATOMXOR16: 6548 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 6549 X86::XOR16ri, X86::MOV16rm, 6550 X86::LCMPXCHG16, X86::MOV16rr, 6551 X86::NOT16r, X86::AX, 6552 X86::GR16RegisterClass); 6553 case X86::ATOMNAND16: 6554 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 6555 X86::AND16ri, X86::MOV16rm, 6556 X86::LCMPXCHG16, X86::MOV16rr, 6557 X86::NOT16r, X86::AX, 6558 X86::GR16RegisterClass, true); 6559 case X86::ATOMMIN16: 6560 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 6561 case X86::ATOMMAX16: 6562 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 6563 case X86::ATOMUMIN16: 6564 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 6565 case X86::ATOMUMAX16: 6566 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 6567 6568 case X86::ATOMAND8: 6569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 6570 X86::AND8ri, X86::MOV8rm, 6571 X86::LCMPXCHG8, X86::MOV8rr, 6572 X86::NOT8r, X86::AL, 6573 X86::GR8RegisterClass); 6574 case X86::ATOMOR8: 6575 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 6576 X86::OR8ri, X86::MOV8rm, 6577 X86::LCMPXCHG8, X86::MOV8rr, 6578 X86::NOT8r, X86::AL, 6579 X86::GR8RegisterClass); 6580 case X86::ATOMXOR8: 6581 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 6582 X86::XOR8ri, X86::MOV8rm, 6583 X86::LCMPXCHG8, X86::MOV8rr, 6584 X86::NOT8r, X86::AL, 6585 X86::GR8RegisterClass); 6586 case X86::ATOMNAND8: 6587 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 6588 X86::AND8ri, X86::MOV8rm, 6589 X86::LCMPXCHG8, X86::MOV8rr, 6590 X86::NOT8r, X86::AL, 6591 X86::GR8RegisterClass, true); 6592 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 6593 case X86::ATOMAND64: 6594 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 6595 X86::AND64ri32, X86::MOV64rm, 6596 X86::LCMPXCHG64, X86::MOV64rr, 6597 X86::NOT64r, X86::RAX, 6598 X86::GR64RegisterClass); 6599 case X86::ATOMOR64: 6600 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 6601 X86::OR64ri32, X86::MOV64rm, 6602 X86::LCMPXCHG64, X86::MOV64rr, 6603 X86::NOT64r, X86::RAX, 6604 X86::GR64RegisterClass); 6605 case X86::ATOMXOR64: 6606 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 6607 X86::XOR64ri32, X86::MOV64rm, 6608 X86::LCMPXCHG64, X86::MOV64rr, 6609 X86::NOT64r, X86::RAX, 6610 X86::GR64RegisterClass); 6611 case X86::ATOMNAND64: 6612 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 6613 X86::AND64ri32, X86::MOV64rm, 6614 X86::LCMPXCHG64, X86::MOV64rr, 6615 X86::NOT64r, X86::RAX, 6616 X86::GR64RegisterClass, true); 6617 case X86::ATOMMIN64: 6618 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 6619 case X86::ATOMMAX64: 6620 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 6621 case X86::ATOMUMIN64: 6622 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 6623 case X86::ATOMUMAX64: 6624 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 6625 } 6626} 6627 6628//===----------------------------------------------------------------------===// 6629// X86 Optimization Hooks 6630//===----------------------------------------------------------------------===// 6631 6632void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 6633 const APInt &Mask, 6634 APInt &KnownZero, 6635 APInt &KnownOne, 6636 const SelectionDAG &DAG, 6637 unsigned Depth) const { 6638 unsigned Opc = Op.getOpcode(); 6639 assert((Opc >= ISD::BUILTIN_OP_END || 6640 Opc == ISD::INTRINSIC_WO_CHAIN || 6641 Opc == ISD::INTRINSIC_W_CHAIN || 6642 Opc == ISD::INTRINSIC_VOID) && 6643 "Should use MaskedValueIsZero if you don't know whether Op" 6644 " is a target node!"); 6645 6646 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 6647 switch (Opc) { 6648 default: break; 6649 case X86ISD::SETCC: 6650 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 6651 Mask.getBitWidth() - 1); 6652 break; 6653 } 6654} 6655 6656/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 6657/// node is a GlobalAddress + offset. 6658bool X86TargetLowering::isGAPlusOffset(SDNode *N, 6659 GlobalValue* &GA, int64_t &Offset) const{ 6660 if (N->getOpcode() == X86ISD::Wrapper) { 6661 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 6662 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 6663 return true; 6664 } 6665 } 6666 return TargetLowering::isGAPlusOffset(N, GA, Offset); 6667} 6668 6669static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 6670 const TargetLowering &TLI) { 6671 GlobalValue *GV; 6672 int64_t Offset = 0; 6673 if (TLI.isGAPlusOffset(Base, GV, Offset)) 6674 return (GV->getAlignment() >= N && (Offset % N) == 0); 6675 // DAG combine handles the stack object case. 6676 return false; 6677} 6678 6679static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask, 6680 unsigned NumElems, MVT EVT, 6681 SDNode *&Base, 6682 SelectionDAG &DAG, MachineFrameInfo *MFI, 6683 const TargetLowering &TLI) { 6684 Base = NULL; 6685 for (unsigned i = 0; i < NumElems; ++i) { 6686 SDValue Idx = PermMask.getOperand(i); 6687 if (Idx.getOpcode() == ISD::UNDEF) { 6688 if (!Base) 6689 return false; 6690 continue; 6691 } 6692 6693 SDValue Elt = DAG.getShuffleScalarElt(N, i); 6694 if (!Elt.Val || 6695 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val))) 6696 return false; 6697 if (!Base) { 6698 Base = Elt.Val; 6699 if (Base->getOpcode() == ISD::UNDEF) 6700 return false; 6701 continue; 6702 } 6703 if (Elt.getOpcode() == ISD::UNDEF) 6704 continue; 6705 6706 if (!TLI.isConsecutiveLoad(Elt.Val, Base, 6707 EVT.getSizeInBits()/8, i, MFI)) 6708 return false; 6709 } 6710 return true; 6711} 6712 6713/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 6714/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 6715/// if the load addresses are consecutive, non-overlapping, and in the right 6716/// order. 6717static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 6718 const TargetLowering &TLI) { 6719 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6720 MVT VT = N->getValueType(0); 6721 MVT EVT = VT.getVectorElementType(); 6722 SDValue PermMask = N->getOperand(2); 6723 unsigned NumElems = PermMask.getNumOperands(); 6724 SDNode *Base = NULL; 6725 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base, 6726 DAG, MFI, TLI)) 6727 return SDValue(); 6728 6729 LoadSDNode *LD = cast<LoadSDNode>(Base); 6730 if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI)) 6731 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 6732 LD->getSrcValueOffset(), LD->isVolatile()); 6733 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 6734 LD->getSrcValueOffset(), LD->isVolatile(), 6735 LD->getAlignment()); 6736} 6737 6738/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd. 6739static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG, 6740 const X86Subtarget *Subtarget, 6741 const TargetLowering &TLI) { 6742 unsigned NumOps = N->getNumOperands(); 6743 6744 // Ignore single operand BUILD_VECTOR. 6745 if (NumOps == 1) 6746 return SDValue(); 6747 6748 MVT VT = N->getValueType(0); 6749 MVT EVT = VT.getVectorElementType(); 6750 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit()) 6751 // We are looking for load i64 and zero extend. We want to transform 6752 // it before legalizer has a chance to expand it. Also look for i64 6753 // BUILD_PAIR bit casted to f64. 6754 return SDValue(); 6755 // This must be an insertion into a zero vector. 6756 SDValue HighElt = N->getOperand(1); 6757 if (!isZeroNode(HighElt)) 6758 return SDValue(); 6759 6760 // Value must be a load. 6761 SDNode *Base = N->getOperand(0).Val; 6762 if (!isa<LoadSDNode>(Base)) { 6763 if (Base->getOpcode() != ISD::BIT_CONVERT) 6764 return SDValue(); 6765 Base = Base->getOperand(0).Val; 6766 if (!isa<LoadSDNode>(Base)) 6767 return SDValue(); 6768 } 6769 6770 // Transform it into VZEXT_LOAD addr. 6771 LoadSDNode *LD = cast<LoadSDNode>(Base); 6772 6773 // Load must not be an extload. 6774 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 6775 return SDValue(); 6776 6777 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr()); 6778} 6779 6780/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 6781static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 6782 const X86Subtarget *Subtarget) { 6783 SDValue Cond = N->getOperand(0); 6784 6785 // If we have SSE[12] support, try to form min/max nodes. 6786 if (Subtarget->hasSSE2() && 6787 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 6788 if (Cond.getOpcode() == ISD::SETCC) { 6789 // Get the LHS/RHS of the select. 6790 SDValue LHS = N->getOperand(1); 6791 SDValue RHS = N->getOperand(2); 6792 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 6793 6794 unsigned Opcode = 0; 6795 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 6796 switch (CC) { 6797 default: break; 6798 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 6799 case ISD::SETULE: 6800 case ISD::SETLE: 6801 if (!UnsafeFPMath) break; 6802 // FALL THROUGH. 6803 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 6804 case ISD::SETLT: 6805 Opcode = X86ISD::FMIN; 6806 break; 6807 6808 case ISD::SETOGT: // (X > Y) ? X : Y -> max 6809 case ISD::SETUGT: 6810 case ISD::SETGT: 6811 if (!UnsafeFPMath) break; 6812 // FALL THROUGH. 6813 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 6814 case ISD::SETGE: 6815 Opcode = X86ISD::FMAX; 6816 break; 6817 } 6818 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 6819 switch (CC) { 6820 default: break; 6821 case ISD::SETOGT: // (X > Y) ? Y : X -> min 6822 case ISD::SETUGT: 6823 case ISD::SETGT: 6824 if (!UnsafeFPMath) break; 6825 // FALL THROUGH. 6826 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 6827 case ISD::SETGE: 6828 Opcode = X86ISD::FMIN; 6829 break; 6830 6831 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 6832 case ISD::SETULE: 6833 case ISD::SETLE: 6834 if (!UnsafeFPMath) break; 6835 // FALL THROUGH. 6836 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 6837 case ISD::SETLT: 6838 Opcode = X86ISD::FMAX; 6839 break; 6840 } 6841 } 6842 6843 if (Opcode) 6844 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); 6845 } 6846 6847 } 6848 6849 return SDValue(); 6850} 6851 6852/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 6853static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 6854 const X86Subtarget *Subtarget) { 6855 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 6856 // the FP state in cases where an emms may be missing. 6857 // A preferable solution to the general problem is to figure out the right 6858 // places to insert EMMS. This qualifies as a quick hack. 6859 StoreSDNode *St = cast<StoreSDNode>(N); 6860 if (St->getValue().getValueType().isVector() && 6861 St->getValue().getValueType().getSizeInBits() == 64 && 6862 isa<LoadSDNode>(St->getValue()) && 6863 !cast<LoadSDNode>(St->getValue())->isVolatile() && 6864 St->getChain().hasOneUse() && !St->isVolatile()) { 6865 SDNode* LdVal = St->getValue().Val; 6866 LoadSDNode *Ld = 0; 6867 int TokenFactorIndex = -1; 6868 SmallVector<SDValue, 8> Ops; 6869 SDNode* ChainVal = St->getChain().Val; 6870 // Must be a store of a load. We currently handle two cases: the load 6871 // is a direct child, and it's under an intervening TokenFactor. It is 6872 // possible to dig deeper under nested TokenFactors. 6873 if (ChainVal == LdVal) 6874 Ld = cast<LoadSDNode>(St->getChain()); 6875 else if (St->getValue().hasOneUse() && 6876 ChainVal->getOpcode() == ISD::TokenFactor) { 6877 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 6878 if (ChainVal->getOperand(i).Val == LdVal) { 6879 TokenFactorIndex = i; 6880 Ld = cast<LoadSDNode>(St->getValue()); 6881 } else 6882 Ops.push_back(ChainVal->getOperand(i)); 6883 } 6884 } 6885 if (Ld) { 6886 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 6887 if (Subtarget->is64Bit()) { 6888 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), 6889 Ld->getBasePtr(), Ld->getSrcValue(), 6890 Ld->getSrcValueOffset(), Ld->isVolatile(), 6891 Ld->getAlignment()); 6892 SDValue NewChain = NewLd.getValue(1); 6893 if (TokenFactorIndex != -1) { 6894 Ops.push_back(NewChain); 6895 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 6896 Ops.size()); 6897 } 6898 return DAG.getStore(NewChain, NewLd, St->getBasePtr(), 6899 St->getSrcValue(), St->getSrcValueOffset(), 6900 St->isVolatile(), St->getAlignment()); 6901 } 6902 6903 // Otherwise, lower to two 32-bit copies. 6904 SDValue LoAddr = Ld->getBasePtr(); 6905 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 6906 DAG.getConstant(4, MVT::i32)); 6907 6908 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, 6909 Ld->getSrcValue(), Ld->getSrcValueOffset(), 6910 Ld->isVolatile(), Ld->getAlignment()); 6911 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, 6912 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 6913 Ld->isVolatile(), 6914 MinAlign(Ld->getAlignment(), 4)); 6915 6916 SDValue NewChain = LoLd.getValue(1); 6917 if (TokenFactorIndex != -1) { 6918 Ops.push_back(LoLd); 6919 Ops.push_back(HiLd); 6920 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 6921 Ops.size()); 6922 } 6923 6924 LoAddr = St->getBasePtr(); 6925 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 6926 DAG.getConstant(4, MVT::i32)); 6927 6928 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr, 6929 St->getSrcValue(), St->getSrcValueOffset(), 6930 St->isVolatile(), St->getAlignment()); 6931 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr, 6932 St->getSrcValue(), St->getSrcValueOffset()+4, 6933 St->isVolatile(), 6934 MinAlign(St->getAlignment(), 4)); 6935 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); 6936 } 6937 } 6938 return SDValue(); 6939} 6940 6941/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 6942/// X86ISD::FXOR nodes. 6943static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 6944 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 6945 // F[X]OR(0.0, x) -> x 6946 // F[X]OR(x, 0.0) -> x 6947 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 6948 if (C->getValueAPF().isPosZero()) 6949 return N->getOperand(1); 6950 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 6951 if (C->getValueAPF().isPosZero()) 6952 return N->getOperand(0); 6953 return SDValue(); 6954} 6955 6956/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 6957static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 6958 // FAND(0.0, x) -> 0.0 6959 // FAND(x, 0.0) -> 0.0 6960 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 6961 if (C->getValueAPF().isPosZero()) 6962 return N->getOperand(0); 6963 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 6964 if (C->getValueAPF().isPosZero()) 6965 return N->getOperand(1); 6966 return SDValue(); 6967} 6968 6969 6970SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 6971 DAGCombinerInfo &DCI) const { 6972 SelectionDAG &DAG = DCI.DAG; 6973 switch (N->getOpcode()) { 6974 default: break; 6975 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 6976 case ISD::BUILD_VECTOR: 6977 return PerformBuildVectorCombine(N, DAG, Subtarget, *this); 6978 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 6979 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 6980 case X86ISD::FXOR: 6981 case X86ISD::FOR: return PerformFORCombine(N, DAG); 6982 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 6983 } 6984 6985 return SDValue(); 6986} 6987 6988//===----------------------------------------------------------------------===// 6989// X86 Inline Assembly Support 6990//===----------------------------------------------------------------------===// 6991 6992/// getConstraintType - Given a constraint letter, return the type of 6993/// constraint it is for this target. 6994X86TargetLowering::ConstraintType 6995X86TargetLowering::getConstraintType(const std::string &Constraint) const { 6996 if (Constraint.size() == 1) { 6997 switch (Constraint[0]) { 6998 case 'A': 6999 case 'f': 7000 case 'r': 7001 case 'R': 7002 case 'l': 7003 case 'q': 7004 case 'Q': 7005 case 'x': 7006 case 'y': 7007 case 'Y': 7008 return C_RegisterClass; 7009 default: 7010 break; 7011 } 7012 } 7013 return TargetLowering::getConstraintType(Constraint); 7014} 7015 7016/// LowerXConstraint - try to replace an X constraint, which matches anything, 7017/// with another that has more specific requirements based on the type of the 7018/// corresponding operand. 7019const char *X86TargetLowering:: 7020LowerXConstraint(MVT ConstraintVT) const { 7021 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 7022 // 'f' like normal targets. 7023 if (ConstraintVT.isFloatingPoint()) { 7024 if (Subtarget->hasSSE2()) 7025 return "Y"; 7026 if (Subtarget->hasSSE1()) 7027 return "x"; 7028 } 7029 7030 return TargetLowering::LowerXConstraint(ConstraintVT); 7031} 7032 7033/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 7034/// vector. If it is invalid, don't add anything to Ops. 7035void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 7036 char Constraint, 7037 std::vector<SDValue>&Ops, 7038 SelectionDAG &DAG) const { 7039 SDValue Result(0, 0); 7040 7041 switch (Constraint) { 7042 default: break; 7043 case 'I': 7044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 7045 if (C->getValue() <= 31) { 7046 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType()); 7047 break; 7048 } 7049 } 7050 return; 7051 case 'N': 7052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 7053 if (C->getValue() <= 255) { 7054 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType()); 7055 break; 7056 } 7057 } 7058 return; 7059 case 'i': { 7060 // Literal immediates are always ok. 7061 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 7062 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType()); 7063 break; 7064 } 7065 7066 // If we are in non-pic codegen mode, we allow the address of a global (with 7067 // an optional displacement) to be used with 'i'. 7068 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 7069 int64_t Offset = 0; 7070 7071 // Match either (GA) or (GA+C) 7072 if (GA) { 7073 Offset = GA->getOffset(); 7074 } else if (Op.getOpcode() == ISD::ADD) { 7075 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7076 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 7077 if (C && GA) { 7078 Offset = GA->getOffset()+C->getValue(); 7079 } else { 7080 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 7081 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 7082 if (C && GA) 7083 Offset = GA->getOffset()+C->getValue(); 7084 else 7085 C = 0, GA = 0; 7086 } 7087 } 7088 7089 if (GA) { 7090 // If addressing this global requires a load (e.g. in PIC mode), we can't 7091 // match. 7092 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(), 7093 false)) 7094 return; 7095 7096 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 7097 Offset); 7098 Result = Op; 7099 break; 7100 } 7101 7102 // Otherwise, not valid for this mode. 7103 return; 7104 } 7105 } 7106 7107 if (Result.Val) { 7108 Ops.push_back(Result); 7109 return; 7110 } 7111 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 7112} 7113 7114std::vector<unsigned> X86TargetLowering:: 7115getRegClassForInlineAsmConstraint(const std::string &Constraint, 7116 MVT VT) const { 7117 if (Constraint.size() == 1) { 7118 // FIXME: not handling fp-stack yet! 7119 switch (Constraint[0]) { // GCC X86 Constraint Letters 7120 default: break; // Unknown constraint letter 7121 case 'A': // EAX/EDX 7122 if (VT == MVT::i32 || VT == MVT::i64) 7123 return make_vector<unsigned>(X86::EAX, X86::EDX, 0); 7124 break; 7125 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 7126 case 'Q': // Q_REGS 7127 if (VT == MVT::i32) 7128 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 7129 else if (VT == MVT::i16) 7130 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 7131 else if (VT == MVT::i8) 7132 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 7133 else if (VT == MVT::i64) 7134 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 7135 break; 7136 } 7137 } 7138 7139 return std::vector<unsigned>(); 7140} 7141 7142std::pair<unsigned, const TargetRegisterClass*> 7143X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 7144 MVT VT) const { 7145 // First, see if this is a constraint that directly corresponds to an LLVM 7146 // register class. 7147 if (Constraint.size() == 1) { 7148 // GCC Constraint Letters 7149 switch (Constraint[0]) { 7150 default: break; 7151 case 'r': // GENERAL_REGS 7152 case 'R': // LEGACY_REGS 7153 case 'l': // INDEX_REGS 7154 if (VT == MVT::i64 && Subtarget->is64Bit()) 7155 return std::make_pair(0U, X86::GR64RegisterClass); 7156 if (VT == MVT::i32) 7157 return std::make_pair(0U, X86::GR32RegisterClass); 7158 else if (VT == MVT::i16) 7159 return std::make_pair(0U, X86::GR16RegisterClass); 7160 else if (VT == MVT::i8) 7161 return std::make_pair(0U, X86::GR8RegisterClass); 7162 break; 7163 case 'f': // FP Stack registers. 7164 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 7165 // value to the correct fpstack register class. 7166 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 7167 return std::make_pair(0U, X86::RFP32RegisterClass); 7168 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 7169 return std::make_pair(0U, X86::RFP64RegisterClass); 7170 return std::make_pair(0U, X86::RFP80RegisterClass); 7171 case 'y': // MMX_REGS if MMX allowed. 7172 if (!Subtarget->hasMMX()) break; 7173 return std::make_pair(0U, X86::VR64RegisterClass); 7174 break; 7175 case 'Y': // SSE_REGS if SSE2 allowed 7176 if (!Subtarget->hasSSE2()) break; 7177 // FALL THROUGH. 7178 case 'x': // SSE_REGS if SSE1 allowed 7179 if (!Subtarget->hasSSE1()) break; 7180 7181 switch (VT.getSimpleVT()) { 7182 default: break; 7183 // Scalar SSE types. 7184 case MVT::f32: 7185 case MVT::i32: 7186 return std::make_pair(0U, X86::FR32RegisterClass); 7187 case MVT::f64: 7188 case MVT::i64: 7189 return std::make_pair(0U, X86::FR64RegisterClass); 7190 // Vector types. 7191 case MVT::v16i8: 7192 case MVT::v8i16: 7193 case MVT::v4i32: 7194 case MVT::v2i64: 7195 case MVT::v4f32: 7196 case MVT::v2f64: 7197 return std::make_pair(0U, X86::VR128RegisterClass); 7198 } 7199 break; 7200 } 7201 } 7202 7203 // Use the default implementation in TargetLowering to convert the register 7204 // constraint into a member of a register class. 7205 std::pair<unsigned, const TargetRegisterClass*> Res; 7206 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 7207 7208 // Not found as a standard register? 7209 if (Res.second == 0) { 7210 // GCC calls "st(0)" just plain "st". 7211 if (StringsEqualNoCase("{st}", Constraint)) { 7212 Res.first = X86::ST0; 7213 Res.second = X86::RFP80RegisterClass; 7214 } 7215 7216 return Res; 7217 } 7218 7219 // Otherwise, check to see if this is a register class of the wrong value 7220 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 7221 // turn into {ax},{dx}. 7222 if (Res.second->hasType(VT)) 7223 return Res; // Correct type already, nothing to do. 7224 7225 // All of the single-register GCC register classes map their values onto 7226 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 7227 // really want an 8-bit or 32-bit register, map to the appropriate register 7228 // class and return the appropriate register. 7229 if (Res.second != X86::GR16RegisterClass) 7230 return Res; 7231 7232 if (VT == MVT::i8) { 7233 unsigned DestReg = 0; 7234 switch (Res.first) { 7235 default: break; 7236 case X86::AX: DestReg = X86::AL; break; 7237 case X86::DX: DestReg = X86::DL; break; 7238 case X86::CX: DestReg = X86::CL; break; 7239 case X86::BX: DestReg = X86::BL; break; 7240 } 7241 if (DestReg) { 7242 Res.first = DestReg; 7243 Res.second = Res.second = X86::GR8RegisterClass; 7244 } 7245 } else if (VT == MVT::i32) { 7246 unsigned DestReg = 0; 7247 switch (Res.first) { 7248 default: break; 7249 case X86::AX: DestReg = X86::EAX; break; 7250 case X86::DX: DestReg = X86::EDX; break; 7251 case X86::CX: DestReg = X86::ECX; break; 7252 case X86::BX: DestReg = X86::EBX; break; 7253 case X86::SI: DestReg = X86::ESI; break; 7254 case X86::DI: DestReg = X86::EDI; break; 7255 case X86::BP: DestReg = X86::EBP; break; 7256 case X86::SP: DestReg = X86::ESP; break; 7257 } 7258 if (DestReg) { 7259 Res.first = DestReg; 7260 Res.second = Res.second = X86::GR32RegisterClass; 7261 } 7262 } else if (VT == MVT::i64) { 7263 unsigned DestReg = 0; 7264 switch (Res.first) { 7265 default: break; 7266 case X86::AX: DestReg = X86::RAX; break; 7267 case X86::DX: DestReg = X86::RDX; break; 7268 case X86::CX: DestReg = X86::RCX; break; 7269 case X86::BX: DestReg = X86::RBX; break; 7270 case X86::SI: DestReg = X86::RSI; break; 7271 case X86::DI: DestReg = X86::RDI; break; 7272 case X86::BP: DestReg = X86::RBP; break; 7273 case X86::SP: DestReg = X86::RSP; break; 7274 } 7275 if (DestReg) { 7276 Res.first = DestReg; 7277 Res.second = Res.second = X86::GR64RegisterClass; 7278 } 7279 } 7280 7281 return Res; 7282} 7283