X86ISelLowering.cpp revision 3d092dbb91af75c7d39798c6d7a52d32446c3381
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl) { 69 EVT VT = Vec.getValueType(); 70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 71 EVT ElVT = VT.getVectorElementType(); 72 int Factor = VT.getSizeInBits()/128; 73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 74 VT.getVectorNumElements()/Factor); 75 76 // Extract from UNDEF is UNDEF. 77 if (Vec.getOpcode() == ISD::UNDEF) 78 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 79 80 if (isa<ConstantSDNode>(Idx)) { 81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 82 83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 84 // we can match to VEXTRACTF128. 85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 86 87 // This is the index of the first element of the 128-bit chunk 88 // we want. 89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 90 * ElemsPerChunk); 91 92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 94 VecIdx); 95 96 return Result; 97 } 98 99 return SDValue(); 100} 101 102/// Generate a DAG to put 128-bits into a vector > 128 bits. This 103/// sets things up to match to an AVX VINSERTF128 instruction or a 104/// simple superregister reference. Idx is an index in the 128 bits 105/// we want. It need not be aligned to a 128-bit bounday. That makes 106/// lowering INSERT_VECTOR_ELT operations easier. 107static SDValue Insert128BitVector(SDValue Result, 108 SDValue Vec, 109 SDValue Idx, 110 SelectionDAG &DAG, 111 DebugLoc dl) { 112 if (isa<ConstantSDNode>(Idx)) { 113 EVT VT = Vec.getValueType(); 114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 115 116 EVT ElVT = VT.getVectorElementType(); 117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 118 EVT ResultVT = Result.getValueType(); 119 120 // Insert the relevant 128 bits. 121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 122 123 // This is the index of the first element of the 128-bit chunk 124 // we want. 125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 126 * ElemsPerChunk); 127 128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 130 VecIdx); 131 return Result; 132 } 133 134 return SDValue(); 135} 136 137static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 139 bool is64Bit = Subtarget->is64Bit(); 140 141 if (Subtarget->isTargetEnvMacho()) { 142 if (is64Bit) 143 return new X8664_MachoTargetObjectFile(); 144 return new TargetLoweringObjectFileMachO(); 145 } 146 147 if (Subtarget->isTargetELF()) 148 return new TargetLoweringObjectFileELF(); 149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 150 return new TargetLoweringObjectFileCOFF(); 151 llvm_unreachable("unknown subtarget type"); 152} 153 154X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 155 : TargetLowering(TM, createTLOF(TM)) { 156 Subtarget = &TM.getSubtarget<X86Subtarget>(); 157 X86ScalarSSEf64 = Subtarget->hasSSE2(); 158 X86ScalarSSEf32 = Subtarget->hasSSE1(); 159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 160 161 RegInfo = TM.getRegisterInfo(); 162 TD = getTargetData(); 163 164 // Set up the TargetLowering object. 165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 166 167 // X86 is weird, it always uses i8 for shift amounts and setcc results. 168 setBooleanContents(ZeroOrOneBooleanContent); 169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 171 172 // For 64-bit since we have so many registers use the ILP scheduler, for 173 // 32-bit code use the register pressure specific scheduling. 174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 175 if (Subtarget->is64Bit()) 176 setSchedulingPreference(Sched::ILP); 177 else if (Subtarget->isAtom()) 178 setSchedulingPreference(Sched::Hybrid); 179 else 180 setSchedulingPreference(Sched::RegPressure); 181 setStackPointerRegisterToSaveRestore(X86StackPtr); 182 183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 184 // Setup Windows compiler runtime calls. 185 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 187 setLibcallName(RTLIB::SREM_I64, "_allrem"); 188 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 189 setLibcallName(RTLIB::MUL_I64, "_allmul"); 190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 195 196 // The _ftol2 runtime function has an unusual calling conv, which 197 // is modeled by a special pseudo-instruction. 198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 202 } 203 204 if (Subtarget->isTargetDarwin()) { 205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 206 setUseUnderscoreSetJmp(false); 207 setUseUnderscoreLongJmp(false); 208 } else if (Subtarget->isTargetMingw()) { 209 // MS runtime is weird: it exports _setjmp, but longjmp! 210 setUseUnderscoreSetJmp(true); 211 setUseUnderscoreLongJmp(false); 212 } else { 213 setUseUnderscoreSetJmp(true); 214 setUseUnderscoreLongJmp(true); 215 } 216 217 // Set up the register classes. 218 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 219 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 220 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 221 if (Subtarget->is64Bit()) 222 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 223 224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 225 226 // We don't accept any truncstore of integer registers. 227 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 228 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 230 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 232 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 233 234 // SETOEQ and SETUNE require checking two conditions. 235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 241 242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 243 // operation. 244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 247 248 if (Subtarget->is64Bit()) { 249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 } else if (!TM.Options.UseSoftFloat) { 252 // We have an algorithm for SSE2->double, and we turn this into a 253 // 64-bit FILD followed by conditional FADD for other targets. 254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 255 // We have an algorithm for SSE2, and we turn this into a 64-bit 256 // FILD for other targets. 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 258 } 259 260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 261 // this operation. 262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 264 265 if (!TM.Options.UseSoftFloat) { 266 // SSE has no i16 to fp conversion, only i32 267 if (X86ScalarSSEf32) { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 269 // f32 and f64 cases are Legal, f80 case is not 270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 274 } 275 } else { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 278 } 279 280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 281 // are Legal, f80 is custom lowered. 282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 284 285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 286 // this operation. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 289 290 if (X86ScalarSSEf32) { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 292 // f32 and f64 cases are Legal, f80 case is not 293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 294 } else { 295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 297 } 298 299 // Handle FP_TO_UINT by promoting the destination to a larger signed 300 // conversion. 301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 304 305 if (Subtarget->is64Bit()) { 306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 308 } else if (!TM.Options.UseSoftFloat) { 309 // Since AVX is a superset of SSE3, only check for SSE here. 310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 311 // Expand FP_TO_UINT into a select. 312 // FIXME: We would like to use a Custom expander here eventually to do 313 // the optimal thing for SSE vs. the default expansion in the legalizer. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 315 else 316 // With SSE3 we can use fisttpll to convert to a signed i64; without 317 // SSE, we're stuck with a fistpll. 318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 319 } 320 321 if (isTargetFTOL()) { 322 // Use the _ftol2 runtime function, which has a pseudo-instruction 323 // to handle its weird calling convention. 324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 325 } 326 327 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 328 if (!X86ScalarSSEf64) { 329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 331 if (Subtarget->is64Bit()) { 332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 333 // Without SSE, i64->f64 goes through memory. 334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 335 } 336 } 337 338 // Scalar integer divide and remainder are lowered to use operations that 339 // produce two results, to match the available instructions. This exposes 340 // the two-result form to trivial CSE, which is able to combine x/y and x%y 341 // into a single instruction. 342 // 343 // Scalar integer multiply-high is also lowered to use two-result 344 // operations, to match the available instructions. However, plain multiply 345 // (low) operations are left as Legal, as there are single-result 346 // instructions for this in x86. Using the two-result multiply instructions 347 // when both high and low results are needed must be arranged by dagcombine. 348 for (unsigned i = 0, e = 4; i != e; ++i) { 349 MVT VT = IntVTs[i]; 350 setOperationAction(ISD::MULHS, VT, Expand); 351 setOperationAction(ISD::MULHU, VT, Expand); 352 setOperationAction(ISD::SDIV, VT, Expand); 353 setOperationAction(ISD::UDIV, VT, Expand); 354 setOperationAction(ISD::SREM, VT, Expand); 355 setOperationAction(ISD::UREM, VT, Expand); 356 357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 358 setOperationAction(ISD::ADDC, VT, Custom); 359 setOperationAction(ISD::ADDE, VT, Custom); 360 setOperationAction(ISD::SUBC, VT, Custom); 361 setOperationAction(ISD::SUBE, VT, Custom); 362 } 363 364 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 365 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 366 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 368 if (Subtarget->is64Bit()) 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f32 , Expand); 375 setOperationAction(ISD::FREM , MVT::f64 , Expand); 376 setOperationAction(ISD::FREM , MVT::f80 , Expand); 377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 378 379 // Promote the i8 variants and force them on up to i32 which has a shorter 380 // encoding. 381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 385 if (Subtarget->hasBMI()) { 386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 388 if (Subtarget->is64Bit()) 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 390 } else { 391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 393 if (Subtarget->is64Bit()) 394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 395 } 396 397 if (Subtarget->hasLZCNT()) { 398 // When promoting the i8 variants, force them to i32 for a shorter 399 // encoding. 400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 406 if (Subtarget->is64Bit()) 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 408 } else { 409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 418 } 419 } 420 421 if (Subtarget->hasPOPCNT()) { 422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 423 } else { 424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 427 if (Subtarget->is64Bit()) 428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 429 } 430 431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 433 434 // These should be promoted to a larger select which is supported. 435 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 436 // X86 wants to expand cmov itself. 437 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 438 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 439 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 440 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 441 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 442 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 443 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 444 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 446 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 447 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 448 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 449 if (Subtarget->is64Bit()) { 450 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 451 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 452 } 453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 454 455 // Darwin ABI issue. 456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) 461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 464 if (Subtarget->is64Bit()) { 465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 470 } 471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 475 if (Subtarget->is64Bit()) { 476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 479 } 480 481 if (Subtarget->hasSSE1()) 482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 483 484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 486 487 // On X86 and X86-64, atomic operations are lowered to locked instructions. 488 // Locked instructions, in turn, have implicit fence semantics (all memory 489 // operations are flushed before issuing the locked instruction, and they 490 // are not buffered), so we can fold away the common pattern of 491 // fence-atomic-fence. 492 setShouldFoldAtomicFences(true); 493 494 // Expand certain atomics 495 for (unsigned i = 0, e = 4; i != e; ++i) { 496 MVT VT = IntVTs[i]; 497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 500 } 501 502 if (!Subtarget->is64Bit()) { 503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 511 } 512 513 if (Subtarget->hasCmpxchg16b()) { 514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 515 } 516 517 // FIXME - use subtarget debug flags 518 if (!Subtarget->isTargetDarwin() && 519 !Subtarget->isTargetELF() && 520 !Subtarget->isTargetCygMing()) { 521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 522 } 523 524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 528 if (Subtarget->is64Bit()) { 529 setExceptionPointerRegister(X86::RAX); 530 setExceptionSelectorRegister(X86::RDX); 531 } else { 532 setExceptionPointerRegister(X86::EAX); 533 setExceptionSelectorRegister(X86::EDX); 534 } 535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 537 538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 540 541 setOperationAction(ISD::TRAP, MVT::Other, Legal); 542 543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 544 setOperationAction(ISD::VASTART , MVT::Other, Custom); 545 setOperationAction(ISD::VAEND , MVT::Other, Expand); 546 if (Subtarget->is64Bit()) { 547 setOperationAction(ISD::VAARG , MVT::Other, Custom); 548 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 549 } else { 550 setOperationAction(ISD::VAARG , MVT::Other, Expand); 551 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 552 } 553 554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 556 557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 559 MVT::i64 : MVT::i32, Custom); 560 else if (TM.Options.EnableSegmentedStacks) 561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 562 MVT::i64 : MVT::i32, Custom); 563 else 564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 565 MVT::i64 : MVT::i32, Expand); 566 567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 568 // f32 and f64 use SSE. 569 // Set up the FP register classes. 570 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 571 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 572 573 // Use ANDPD to simulate FABS. 574 setOperationAction(ISD::FABS , MVT::f64, Custom); 575 setOperationAction(ISD::FABS , MVT::f32, Custom); 576 577 // Use XORP to simulate FNEG. 578 setOperationAction(ISD::FNEG , MVT::f64, Custom); 579 setOperationAction(ISD::FNEG , MVT::f32, Custom); 580 581 // Use ANDPD and ORPD to simulate FCOPYSIGN. 582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 584 585 // Lower this to FGETSIGNx86 plus an AND. 586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 588 589 // We don't support sin/cos/fmod 590 setOperationAction(ISD::FSIN , MVT::f64, Expand); 591 setOperationAction(ISD::FCOS , MVT::f64, Expand); 592 setOperationAction(ISD::FSIN , MVT::f32, Expand); 593 setOperationAction(ISD::FCOS , MVT::f32, Expand); 594 595 // Expand FP immediates into loads from the stack, except for the special 596 // cases we handle. 597 addLegalFPImmediate(APFloat(+0.0)); // xorpd 598 addLegalFPImmediate(APFloat(+0.0f)); // xorps 599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 600 // Use SSE for f32, x87 for f64. 601 // Set up the FP register classes. 602 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 604 605 // Use ANDPS to simulate FABS. 606 setOperationAction(ISD::FABS , MVT::f32, Custom); 607 608 // Use XORP to simulate FNEG. 609 setOperationAction(ISD::FNEG , MVT::f32, Custom); 610 611 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 612 613 // Use ANDPS and ORPS to simulate FCOPYSIGN. 614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 616 617 // We don't support sin/cos/fmod 618 setOperationAction(ISD::FSIN , MVT::f32, Expand); 619 setOperationAction(ISD::FCOS , MVT::f32, Expand); 620 621 // Special cases we handle for FP constants. 622 addLegalFPImmediate(APFloat(+0.0f)); // xorps 623 addLegalFPImmediate(APFloat(+0.0)); // FLD0 624 addLegalFPImmediate(APFloat(+1.0)); // FLD1 625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 627 628 if (!TM.Options.UnsafeFPMath) { 629 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 630 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 631 } 632 } else if (!TM.Options.UseSoftFloat) { 633 // f32 and f64 in x87. 634 // Set up the FP register classes. 635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 637 638 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 639 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 642 643 if (!TM.Options.UnsafeFPMath) { 644 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 645 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 646 } 647 addLegalFPImmediate(APFloat(+0.0)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 655 } 656 657 // We don't support FMA. 658 setOperationAction(ISD::FMA, MVT::f64, Expand); 659 setOperationAction(ISD::FMA, MVT::f32, Expand); 660 661 // Long double always uses X87. 662 if (!TM.Options.UseSoftFloat) { 663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 664 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 666 { 667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 668 addLegalFPImmediate(TmpFlt); // FLD0 669 TmpFlt.changeSign(); 670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 671 672 bool ignored; 673 APFloat TmpFlt2(+1.0); 674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 675 &ignored); 676 addLegalFPImmediate(TmpFlt2); // FLD1 677 TmpFlt2.changeSign(); 678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 679 } 680 681 if (!TM.Options.UnsafeFPMath) { 682 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 683 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 684 } 685 686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 687 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 689 setOperationAction(ISD::FRINT, MVT::f80, Expand); 690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 691 setOperationAction(ISD::FMA, MVT::f80, Expand); 692 } 693 694 // Always use a library call for pow. 695 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 696 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 697 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 698 699 setOperationAction(ISD::FLOG, MVT::f80, Expand); 700 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 701 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 702 setOperationAction(ISD::FEXP, MVT::f80, Expand); 703 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 704 705 // First set operation action for all vector types to either promote 706 // (for widening) or expand (for scalarization). Then we will selectively 707 // turn on ones that can be effectively codegen'd. 708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 769 setTruncStoreAction((MVT::SimpleValueType)VT, 770 (MVT::SimpleValueType)InnerVT, Expand); 771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 774 } 775 776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 777 // with -msoft-float, disable use of MMX as well. 778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 780 // No operations on x86mmx supported, everything uses intrinsics. 781 } 782 783 // MMX-sized vectors (other than x86mmx) are expected to be expanded 784 // into smaller operations. 785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 789 setOperationAction(ISD::AND, MVT::v8i8, Expand); 790 setOperationAction(ISD::AND, MVT::v4i16, Expand); 791 setOperationAction(ISD::AND, MVT::v2i32, Expand); 792 setOperationAction(ISD::AND, MVT::v1i64, Expand); 793 setOperationAction(ISD::OR, MVT::v8i8, Expand); 794 setOperationAction(ISD::OR, MVT::v4i16, Expand); 795 setOperationAction(ISD::OR, MVT::v2i32, Expand); 796 setOperationAction(ISD::OR, MVT::v1i64, Expand); 797 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 814 815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 817 818 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 830 } 831 832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 834 835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 836 // registers cannot be used even for integer operations. 837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 841 842 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 843 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 844 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 845 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 846 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 847 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 848 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 849 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 850 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 851 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 852 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 858 859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 863 864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 869 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 875 876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 878 EVT VT = (MVT::SimpleValueType)i; 879 // Do not attempt to custom lower non-power-of-2 vectors 880 if (!isPowerOf2_32(VT.getVectorNumElements())) 881 continue; 882 // Do not attempt to custom lower non-128-bit vectors 883 if (!VT.is128BitVector()) 884 continue; 885 setOperationAction(ISD::BUILD_VECTOR, 886 VT.getSimpleVT().SimpleTy, Custom); 887 setOperationAction(ISD::VECTOR_SHUFFLE, 888 VT.getSimpleVT().SimpleTy, Custom); 889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 890 VT.getSimpleVT().SimpleTy, Custom); 891 } 892 893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 899 900 if (Subtarget->is64Bit()) { 901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 903 } 904 905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 908 EVT VT = SVT; 909 910 // Do not attempt to promote non-128-bit vectors 911 if (!VT.is128BitVector()) 912 continue; 913 914 setOperationAction(ISD::AND, SVT, Promote); 915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 916 setOperationAction(ISD::OR, SVT, Promote); 917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 918 setOperationAction(ISD::XOR, SVT, Promote); 919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 920 setOperationAction(ISD::LOAD, SVT, Promote); 921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 922 setOperationAction(ISD::SELECT, SVT, Promote); 923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 924 } 925 926 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 927 928 // Custom lower v2i64 and v2f64 selects. 929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 933 934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 936 } 937 938 if (Subtarget->hasSSE41()) { 939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 940 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 942 setOperationAction(ISD::FRINT, MVT::f32, Legal); 943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 945 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 947 setOperationAction(ISD::FRINT, MVT::f64, Legal); 948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 949 950 // FIXME: Do we need to handle scalar-to-vector here? 951 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 952 953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 958 959 // i8 and i16 vectors are custom , because the source register and source 960 // source memory operand types are not the same width. f32 vectors are 961 // custom since the immediate controlling the insert encodes additional 962 // information. 963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 967 968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 972 973 // FIXME: these should be Legal but thats only for the case where 974 // the index is constant. For now custom expand to deal with that. 975 if (Subtarget->is64Bit()) { 976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 978 } 979 } 980 981 if (Subtarget->hasSSE2()) { 982 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 983 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 984 985 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 986 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 987 988 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 989 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 990 991 if (Subtarget->hasAVX2()) { 992 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 993 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 994 995 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 996 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 997 998 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 999 } else { 1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1002 1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1005 1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1007 } 1008 } 1009 1010 if (Subtarget->hasSSE42()) 1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1012 1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1020 1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1024 1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1031 1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1038 1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1042 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1049 1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1052 1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1055 1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1058 1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1063 1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1067 1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1072 1073 if (Subtarget->hasAVX2()) { 1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1078 1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1083 1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1087 // Don't lower v32i8 because there is no 128-bit byte mul 1088 1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1090 1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1093 1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1096 1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1098 } else { 1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1103 1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1108 1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1112 // Don't lower v32i8 because there is no 128-bit byte mul 1113 1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1116 1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1119 1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1121 } 1122 1123 // Custom lower several nodes for 256-bit types. 1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1127 EVT VT = SVT; 1128 1129 // Extract subvector is special because the value type 1130 // (result) is 128-bit but the source is 256-bit wide. 1131 if (VT.is128BitVector()) 1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1133 1134 // Do not attempt to custom lower other non-256-bit vectors 1135 if (!VT.is256BitVector()) 1136 continue; 1137 1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1144 } 1145 1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1149 EVT VT = SVT; 1150 1151 // Do not attempt to promote non-256-bit vectors 1152 if (!VT.is256BitVector()) 1153 continue; 1154 1155 setOperationAction(ISD::AND, SVT, Promote); 1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1157 setOperationAction(ISD::OR, SVT, Promote); 1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1159 setOperationAction(ISD::XOR, SVT, Promote); 1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1161 setOperationAction(ISD::LOAD, SVT, Promote); 1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1163 setOperationAction(ISD::SELECT, SVT, Promote); 1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1165 } 1166 } 1167 1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1169 // of this type with custom code. 1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1173 Custom); 1174 } 1175 1176 // We want to custom lower some of our intrinsics. 1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1178 1179 1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1181 // handle type legalization for these operations here. 1182 // 1183 // FIXME: We really should do custom legalization for addition and 1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1185 // than generic legalization for 64-bit multiplication-with-overflow, though. 1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1187 // Add/Sub/Mul with overflow operations are custom lowered. 1188 MVT VT = IntVTs[i]; 1189 setOperationAction(ISD::SADDO, VT, Custom); 1190 setOperationAction(ISD::UADDO, VT, Custom); 1191 setOperationAction(ISD::SSUBO, VT, Custom); 1192 setOperationAction(ISD::USUBO, VT, Custom); 1193 setOperationAction(ISD::SMULO, VT, Custom); 1194 setOperationAction(ISD::UMULO, VT, Custom); 1195 } 1196 1197 // There are no 8-bit 3-address imul/mul instructions 1198 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1199 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1200 1201 if (!Subtarget->is64Bit()) { 1202 // These libcalls are not available in 32-bit. 1203 setLibcallName(RTLIB::SHL_I128, 0); 1204 setLibcallName(RTLIB::SRL_I128, 0); 1205 setLibcallName(RTLIB::SRA_I128, 0); 1206 } 1207 1208 // We have target-specific dag combine patterns for the following nodes: 1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1211 setTargetDAGCombine(ISD::VSELECT); 1212 setTargetDAGCombine(ISD::SELECT); 1213 setTargetDAGCombine(ISD::SHL); 1214 setTargetDAGCombine(ISD::SRA); 1215 setTargetDAGCombine(ISD::SRL); 1216 setTargetDAGCombine(ISD::OR); 1217 setTargetDAGCombine(ISD::AND); 1218 setTargetDAGCombine(ISD::ADD); 1219 setTargetDAGCombine(ISD::FADD); 1220 setTargetDAGCombine(ISD::FSUB); 1221 setTargetDAGCombine(ISD::SUB); 1222 setTargetDAGCombine(ISD::LOAD); 1223 setTargetDAGCombine(ISD::STORE); 1224 setTargetDAGCombine(ISD::ZERO_EXTEND); 1225 setTargetDAGCombine(ISD::SIGN_EXTEND); 1226 setTargetDAGCombine(ISD::TRUNCATE); 1227 setTargetDAGCombine(ISD::SINT_TO_FP); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279 return; 1280} 1281 1282/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1283/// function arguments in the caller parameter area. For X86, aggregates 1284/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1285/// are at 4-byte boundaries. 1286unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1287 if (Subtarget->is64Bit()) { 1288 // Max of 8 and alignment of type. 1289 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1290 if (TyAlign > 8) 1291 return TyAlign; 1292 return 8; 1293 } 1294 1295 unsigned Align = 4; 1296 if (Subtarget->hasSSE1()) 1297 getMaxByValAlign(Ty, Align); 1298 return Align; 1299} 1300 1301/// getOptimalMemOpType - Returns the target specific optimal type for load 1302/// and store operations as a result of memset, memcpy, and memmove 1303/// lowering. If DstAlign is zero that means it's safe to destination 1304/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1305/// means there isn't a need to check it against alignment requirement, 1306/// probably because the source does not need to be loaded. If 1307/// 'IsZeroVal' is true, that means it's safe to return a 1308/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1309/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1310/// constant so it does not need to be loaded. 1311/// It returns EVT::Other if the type should be determined using generic 1312/// target-independent logic. 1313EVT 1314X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1315 unsigned DstAlign, unsigned SrcAlign, 1316 bool IsZeroVal, 1317 bool MemcpyStrSrc, 1318 MachineFunction &MF) const { 1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1320 // linux. This is because the stack realignment code can't handle certain 1321 // cases like PR2962. This should be removed when PR2962 is fixed. 1322 const Function *F = MF.getFunction(); 1323 if (IsZeroVal && 1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1325 if (Size >= 16 && 1326 (Subtarget->isUnalignedMemAccessFast() || 1327 ((DstAlign == 0 || DstAlign >= 16) && 1328 (SrcAlign == 0 || SrcAlign >= 16))) && 1329 Subtarget->getStackAlignment() >= 16) { 1330 if (Subtarget->getStackAlignment() >= 32) { 1331 if (Subtarget->hasAVX2()) 1332 return MVT::v8i32; 1333 if (Subtarget->hasAVX()) 1334 return MVT::v8f32; 1335 } 1336 if (Subtarget->hasSSE2()) 1337 return MVT::v4i32; 1338 if (Subtarget->hasSSE1()) 1339 return MVT::v4f32; 1340 } else if (!MemcpyStrSrc && Size >= 8 && 1341 !Subtarget->is64Bit() && 1342 Subtarget->getStackAlignment() >= 8 && 1343 Subtarget->hasSSE2()) { 1344 // Do not use f64 to lower memcpy if source is string constant. It's 1345 // better to use i32 to avoid the loads. 1346 return MVT::f64; 1347 } 1348 } 1349 if (Subtarget->is64Bit() && Size >= 8) 1350 return MVT::i64; 1351 return MVT::i32; 1352} 1353 1354/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1355/// current function. The returned value is a member of the 1356/// MachineJumpTableInfo::JTEntryKind enum. 1357unsigned X86TargetLowering::getJumpTableEncoding() const { 1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1359 // symbol. 1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1361 Subtarget->isPICStyleGOT()) 1362 return MachineJumpTableInfo::EK_Custom32; 1363 1364 // Otherwise, use the normal jump table encoding heuristics. 1365 return TargetLowering::getJumpTableEncoding(); 1366} 1367 1368const MCExpr * 1369X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1370 const MachineBasicBlock *MBB, 1371 unsigned uid,MCContext &Ctx) const{ 1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1373 Subtarget->isPICStyleGOT()); 1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1375 // entries. 1376 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1377 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1378} 1379 1380/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1381/// jumptable. 1382SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1383 SelectionDAG &DAG) const { 1384 if (!Subtarget->is64Bit()) 1385 // This doesn't have DebugLoc associated with it, but is not really the 1386 // same as a Register. 1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1388 return Table; 1389} 1390 1391/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1392/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1393/// MCExpr. 1394const MCExpr *X86TargetLowering:: 1395getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1396 MCContext &Ctx) const { 1397 // X86-64 uses RIP relative addressing based on the jump table label. 1398 if (Subtarget->isPICStyleRIPRel()) 1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1400 1401 // Otherwise, the reference is relative to the PIC base. 1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1403} 1404 1405// FIXME: Why this routine is here? Move to RegInfo! 1406std::pair<const TargetRegisterClass*, uint8_t> 1407X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1408 const TargetRegisterClass *RRC = 0; 1409 uint8_t Cost = 1; 1410 switch (VT.getSimpleVT().SimpleTy) { 1411 default: 1412 return TargetLowering::findRepresentativeClass(VT); 1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1414 RRC = (Subtarget->is64Bit() 1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1416 break; 1417 case MVT::x86mmx: 1418 RRC = X86::VR64RegisterClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = X86::VR128RegisterClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDNode *Copy = *N->use_begin(); 1588 if (Copy->getOpcode() == ISD::CopyToReg) { 1589 // If the copy has a glue operand, we conservatively assume it isn't safe to 1590 // perform a tail call. 1591 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1592 return false; 1593 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1594 return false; 1595 1596 bool HasRet = false; 1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1598 UI != UE; ++UI) { 1599 if (UI->getOpcode() != X86ISD::RET_FLAG) 1600 return false; 1601 HasRet = true; 1602 } 1603 1604 return HasRet; 1605} 1606 1607EVT 1608X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1609 ISD::NodeType ExtendKind) const { 1610 MVT ReturnMVT; 1611 // TODO: Is this also valid on 32-bit? 1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1613 ReturnMVT = MVT::i8; 1614 else 1615 ReturnMVT = MVT::i32; 1616 1617 EVT MinVT = getRegisterType(Context, ReturnMVT); 1618 return VT.bitsLT(MinVT) ? MinVT : VT; 1619} 1620 1621/// LowerCallResult - Lower the result values of a call into the 1622/// appropriate copies out of appropriate physical registers. 1623/// 1624SDValue 1625X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1626 CallingConv::ID CallConv, bool isVarArg, 1627 const SmallVectorImpl<ISD::InputArg> &Ins, 1628 DebugLoc dl, SelectionDAG &DAG, 1629 SmallVectorImpl<SDValue> &InVals) const { 1630 1631 // Assign locations to each value returned by this call. 1632 SmallVector<CCValAssign, 16> RVLocs; 1633 bool Is64Bit = Subtarget->is64Bit(); 1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1635 getTargetMachine(), RVLocs, *DAG.getContext()); 1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1637 1638 // Copy all of the result registers out of their specified physreg. 1639 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1640 CCValAssign &VA = RVLocs[i]; 1641 EVT CopyVT = VA.getValVT(); 1642 1643 // If this is x86-64, and we disabled SSE, we can't return FP values 1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1646 report_fatal_error("SSE register return with SSE disabled"); 1647 } 1648 1649 SDValue Val; 1650 1651 // If this is a call to a function that returns an fp value on the floating 1652 // point stack, we must guarantee the the value is popped from the stack, so 1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1654 // if the return value is not used. We use the FpPOP_RETVAL instruction 1655 // instead. 1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1657 // If we prefer to use the value in xmm registers, copy it out as f80 and 1658 // use a truncate to move it from fp stack reg to xmm reg. 1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1660 SDValue Ops[] = { Chain, InFlag }; 1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1662 MVT::Other, MVT::Glue, Ops, 2), 1); 1663 Val = Chain.getValue(0); 1664 1665 // Round the f80 to the right size, which also moves it to the appropriate 1666 // xmm register. 1667 if (CopyVT != VA.getValVT()) 1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1669 // This truncation won't change the value. 1670 DAG.getIntPtrConstant(1)); 1671 } else { 1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1673 CopyVT, InFlag).getValue(1); 1674 Val = Chain.getValue(0); 1675 } 1676 InFlag = Chain.getValue(2); 1677 InVals.push_back(Val); 1678 } 1679 1680 return Chain; 1681} 1682 1683 1684//===----------------------------------------------------------------------===// 1685// C & StdCall & Fast Calling Convention implementation 1686//===----------------------------------------------------------------------===// 1687// StdCall calling convention seems to be standard for many Windows' API 1688// routines and around. It differs from C calling convention just a little: 1689// callee should clean up the stack, not caller. Symbols should be also 1690// decorated in some fancy way :) It doesn't support any vector arguments. 1691// For info on fast calling convention see Fast Calling Convention (tail call) 1692// implementation LowerX86_32FastCCCallTo. 1693 1694/// CallIsStructReturn - Determines whether a call uses struct return 1695/// semantics. 1696static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1697 if (Outs.empty()) 1698 return false; 1699 1700 return Outs[0].Flags.isSRet(); 1701} 1702 1703/// ArgsAreStructReturn - Determines whether a function uses struct 1704/// return semantics. 1705static bool 1706ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1707 if (Ins.empty()) 1708 return false; 1709 1710 return Ins[0].Flags.isSRet(); 1711} 1712 1713/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1714/// by "Src" to address "Dst" with size and alignment information specified by 1715/// the specific parameter attribute. The copy will be passed as a byval 1716/// function parameter. 1717static SDValue 1718CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1720 DebugLoc dl) { 1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1722 1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1724 /*isVolatile*/false, /*AlwaysInline=*/true, 1725 MachinePointerInfo(), MachinePointerInfo()); 1726} 1727 1728/// IsTailCallConvention - Return true if the calling convention is one that 1729/// supports tail call optimization. 1730static bool IsTailCallConvention(CallingConv::ID CC) { 1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1732} 1733 1734bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1736 return false; 1737 1738 CallSite CS(CI); 1739 CallingConv::ID CalleeCC = CS.getCallingConv(); 1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1741 return false; 1742 1743 return true; 1744} 1745 1746/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1747/// a tailcall target by changing its ABI. 1748static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1749 bool GuaranteedTailCallOpt) { 1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1751} 1752 1753SDValue 1754X86TargetLowering::LowerMemArgument(SDValue Chain, 1755 CallingConv::ID CallConv, 1756 const SmallVectorImpl<ISD::InputArg> &Ins, 1757 DebugLoc dl, SelectionDAG &DAG, 1758 const CCValAssign &VA, 1759 MachineFrameInfo *MFI, 1760 unsigned i) const { 1761 // Create the nodes corresponding to a load from this parameter slot. 1762 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1764 getTargetMachine().Options.GuaranteedTailCallOpt); 1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1766 EVT ValVT; 1767 1768 // If value is passed by pointer we have address passed instead of the value 1769 // itself. 1770 if (VA.getLocInfo() == CCValAssign::Indirect) 1771 ValVT = VA.getLocVT(); 1772 else 1773 ValVT = VA.getValVT(); 1774 1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1776 // changed with more analysis. 1777 // In case of tail call optimization mark all arguments mutable. Since they 1778 // could be overwritten by lowering of arguments in case of a tail call. 1779 if (Flags.isByVal()) { 1780 unsigned Bytes = Flags.getByValSize(); 1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1783 return DAG.getFrameIndex(FI, getPointerTy()); 1784 } else { 1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1786 VA.getLocMemOffset(), isImmutable); 1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1788 return DAG.getLoad(ValVT, dl, Chain, FIN, 1789 MachinePointerInfo::getFixedStack(FI), 1790 false, false, false, 0); 1791 } 1792} 1793 1794SDValue 1795X86TargetLowering::LowerFormalArguments(SDValue Chain, 1796 CallingConv::ID CallConv, 1797 bool isVarArg, 1798 const SmallVectorImpl<ISD::InputArg> &Ins, 1799 DebugLoc dl, 1800 SelectionDAG &DAG, 1801 SmallVectorImpl<SDValue> &InVals) 1802 const { 1803 MachineFunction &MF = DAG.getMachineFunction(); 1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1805 1806 const Function* Fn = MF.getFunction(); 1807 if (Fn->hasExternalLinkage() && 1808 Subtarget->isTargetCygMing() && 1809 Fn->getName() == "main") 1810 FuncInfo->setForceFramePointer(true); 1811 1812 MachineFrameInfo *MFI = MF.getFrameInfo(); 1813 bool Is64Bit = Subtarget->is64Bit(); 1814 bool IsWindows = Subtarget->isTargetWindows(); 1815 bool IsWin64 = Subtarget->isTargetWin64(); 1816 1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1818 "Var args not supported with calling convention fastcc or ghc"); 1819 1820 // Assign locations to all of the incoming arguments. 1821 SmallVector<CCValAssign, 16> ArgLocs; 1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1823 ArgLocs, *DAG.getContext()); 1824 1825 // Allocate shadow area for Win64 1826 if (IsWin64) { 1827 CCInfo.AllocateStack(32, 8); 1828 } 1829 1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1831 1832 unsigned LastVal = ~0U; 1833 SDValue ArgValue; 1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1835 CCValAssign &VA = ArgLocs[i]; 1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1837 // places. 1838 assert(VA.getValNo() != LastVal && 1839 "Don't support value assigned to multiple locs yet"); 1840 (void)LastVal; 1841 LastVal = VA.getValNo(); 1842 1843 if (VA.isRegLoc()) { 1844 EVT RegVT = VA.getLocVT(); 1845 const TargetRegisterClass *RC; 1846 if (RegVT == MVT::i32) 1847 RC = X86::GR32RegisterClass; 1848 else if (Is64Bit && RegVT == MVT::i64) 1849 RC = X86::GR64RegisterClass; 1850 else if (RegVT == MVT::f32) 1851 RC = X86::FR32RegisterClass; 1852 else if (RegVT == MVT::f64) 1853 RC = X86::FR64RegisterClass; 1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1855 RC = X86::VR256RegisterClass; 1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1857 RC = X86::VR128RegisterClass; 1858 else if (RegVT == MVT::x86mmx) 1859 RC = X86::VR64RegisterClass; 1860 else 1861 llvm_unreachable("Unknown argument type!"); 1862 1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1865 1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1868 // right size. 1869 if (VA.getLocInfo() == CCValAssign::SExt) 1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1871 DAG.getValueType(VA.getValVT())); 1872 else if (VA.getLocInfo() == CCValAssign::ZExt) 1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1874 DAG.getValueType(VA.getValVT())); 1875 else if (VA.getLocInfo() == CCValAssign::BCvt) 1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1877 1878 if (VA.isExtInLoc()) { 1879 // Handle MMX values passed in XMM regs. 1880 if (RegVT.isVector()) { 1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1882 ArgValue); 1883 } else 1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1885 } 1886 } else { 1887 assert(VA.isMemLoc()); 1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1889 } 1890 1891 // If value is passed via pointer - do a load. 1892 if (VA.getLocInfo() == CCValAssign::Indirect) 1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1894 MachinePointerInfo(), false, false, false, 0); 1895 1896 InVals.push_back(ArgValue); 1897 } 1898 1899 // The x86-64 ABI for returning structs by value requires that we copy 1900 // the sret argument into %rax for the return. Save the argument into 1901 // a virtual register so that we can access it from the return points. 1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1904 unsigned Reg = FuncInfo->getSRetReturnReg(); 1905 if (!Reg) { 1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1907 FuncInfo->setSRetReturnReg(Reg); 1908 } 1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1911 } 1912 1913 unsigned StackSize = CCInfo.getNextStackOffset(); 1914 // Align stack specially for tail calls. 1915 if (FuncIsMadeTailCallSafe(CallConv, 1916 MF.getTarget().Options.GuaranteedTailCallOpt)) 1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1918 1919 // If the function takes variable number of arguments, make a frame index for 1920 // the start of the first vararg value... for expansion of llvm.va_start. 1921 if (isVarArg) { 1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1923 CallConv != CallingConv::X86_ThisCall)) { 1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1925 } 1926 if (Is64Bit) { 1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1928 1929 // FIXME: We should really autogenerate these arrays 1930 static const uint16_t GPR64ArgRegsWin64[] = { 1931 X86::RCX, X86::RDX, X86::R8, X86::R9 1932 }; 1933 static const uint16_t GPR64ArgRegs64Bit[] = { 1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1935 }; 1936 static const uint16_t XMMArgRegs64Bit[] = { 1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1939 }; 1940 const uint16_t *GPR64ArgRegs; 1941 unsigned NumXMMRegs = 0; 1942 1943 if (IsWin64) { 1944 // The XMM registers which might contain var arg parameters are shadowed 1945 // in their paired GPR. So we only need to save the GPR to their home 1946 // slots. 1947 TotalNumIntRegs = 4; 1948 GPR64ArgRegs = GPR64ArgRegsWin64; 1949 } else { 1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1951 GPR64ArgRegs = GPR64ArgRegs64Bit; 1952 1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1954 TotalNumXMMRegs); 1955 } 1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1957 TotalNumIntRegs); 1958 1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1961 "SSE register cannot be used when SSE is disabled!"); 1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1963 NoImplicitFloatOps) && 1964 "SSE register cannot be used when SSE is disabled!"); 1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1966 !Subtarget->hasSSE1()) 1967 // Kernel mode asks for SSE to be disabled, so don't push them 1968 // on the stack. 1969 TotalNumXMMRegs = 0; 1970 1971 if (IsWin64) { 1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1973 // Get to the caller-allocated home save location. Add 8 to account 1974 // for the return address. 1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1976 FuncInfo->setRegSaveFrameIndex( 1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1978 // Fixup to set vararg frame on shadow area (4 x i64). 1979 if (NumIntRegs < 4) 1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1981 } else { 1982 // For X86-64, if there are vararg parameters that are passed via 1983 // registers, then we must store them to their spots on the stack so 1984 // they may be loaded by deferencing the result of va_next. 1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1987 FuncInfo->setRegSaveFrameIndex( 1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1989 false)); 1990 } 1991 1992 // Store the integer parameter registers. 1993 SmallVector<SDValue, 8> MemOps; 1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1995 getPointerTy()); 1996 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1999 DAG.getIntPtrConstant(Offset)); 2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2001 X86::GR64RegisterClass); 2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2003 SDValue Store = 2004 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2005 MachinePointerInfo::getFixedStack( 2006 FuncInfo->getRegSaveFrameIndex(), Offset), 2007 false, false, 0); 2008 MemOps.push_back(Store); 2009 Offset += 8; 2010 } 2011 2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2013 // Now store the XMM (fp + vector) parameter registers. 2014 SmallVector<SDValue, 11> SaveXMMOps; 2015 SaveXMMOps.push_back(Chain); 2016 2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2019 SaveXMMOps.push_back(ALVal); 2020 2021 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2022 FuncInfo->getRegSaveFrameIndex())); 2023 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2024 FuncInfo->getVarArgsFPOffset())); 2025 2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2028 X86::VR128RegisterClass); 2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2030 SaveXMMOps.push_back(Val); 2031 } 2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2033 MVT::Other, 2034 &SaveXMMOps[0], SaveXMMOps.size())); 2035 } 2036 2037 if (!MemOps.empty()) 2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2039 &MemOps[0], MemOps.size()); 2040 } 2041 } 2042 2043 // Some CCs need callee pop. 2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2045 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2047 } else { 2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2049 // If this is an sret function, the return should pop the hidden pointer. 2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2051 ArgsAreStructReturn(Ins)) 2052 FuncInfo->setBytesToPopOnReturn(4); 2053 } 2054 2055 if (!Is64Bit) { 2056 // RegSaveFrameIndex is X86-64 only. 2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2058 if (CallConv == CallingConv::X86_FastCall || 2059 CallConv == CallingConv::X86_ThisCall) 2060 // fastcc functions can't have varargs. 2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2062 } 2063 2064 FuncInfo->setArgumentStackSize(StackSize); 2065 2066 return Chain; 2067} 2068 2069SDValue 2070X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2071 SDValue StackPtr, SDValue Arg, 2072 DebugLoc dl, SelectionDAG &DAG, 2073 const CCValAssign &VA, 2074 ISD::ArgFlagsTy Flags) const { 2075 unsigned LocMemOffset = VA.getLocMemOffset(); 2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2078 if (Flags.isByVal()) 2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2080 2081 return DAG.getStore(Chain, dl, Arg, PtrOff, 2082 MachinePointerInfo::getStack(LocMemOffset), 2083 false, false, 0); 2084} 2085 2086/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2087/// optimization is performed and it is required. 2088SDValue 2089X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2090 SDValue &OutRetAddr, SDValue Chain, 2091 bool IsTailCall, bool Is64Bit, 2092 int FPDiff, DebugLoc dl) const { 2093 // Adjust the Return address stack slot. 2094 EVT VT = getPointerTy(); 2095 OutRetAddr = getReturnAddressFrameIndex(DAG); 2096 2097 // Load the "old" Return address. 2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2099 false, false, false, 0); 2100 return SDValue(OutRetAddr.getNode(), 1); 2101} 2102 2103/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2104/// optimization is performed and it is required (FPDiff!=0). 2105static SDValue 2106EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2107 SDValue Chain, SDValue RetAddrFrIdx, 2108 bool Is64Bit, int FPDiff, DebugLoc dl) { 2109 // Store the return address to the appropriate stack slot. 2110 if (!FPDiff) return Chain; 2111 // Calculate the new stack slot for the return address. 2112 int SlotSize = Is64Bit ? 8 : 4; 2113 int NewReturnAddrFI = 2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2119 false, false, 0); 2120 return Chain; 2121} 2122 2123SDValue 2124X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2125 CallingConv::ID CallConv, bool isVarArg, 2126 bool doesNotRet, bool &isTailCall, 2127 const SmallVectorImpl<ISD::OutputArg> &Outs, 2128 const SmallVectorImpl<SDValue> &OutVals, 2129 const SmallVectorImpl<ISD::InputArg> &Ins, 2130 DebugLoc dl, SelectionDAG &DAG, 2131 SmallVectorImpl<SDValue> &InVals) const { 2132 MachineFunction &MF = DAG.getMachineFunction(); 2133 bool Is64Bit = Subtarget->is64Bit(); 2134 bool IsWin64 = Subtarget->isTargetWin64(); 2135 bool IsWindows = Subtarget->isTargetWindows(); 2136 bool IsStructRet = CallIsStructReturn(Outs); 2137 bool IsSibcall = false; 2138 2139 if (MF.getTarget().Options.DisableTailCalls) 2140 isTailCall = false; 2141 2142 if (isTailCall) { 2143 // Check if it's really possible to do a tail call. 2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2146 Outs, OutVals, Ins, DAG); 2147 2148 // Sibcalls are automatically detected tailcalls which do not require 2149 // ABI changes. 2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2151 IsSibcall = true; 2152 2153 if (isTailCall) 2154 ++NumTailCalls; 2155 } 2156 2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2158 "Var args not supported with calling convention fastcc or ghc"); 2159 2160 // Analyze operands of the call, assigning locations to each operand. 2161 SmallVector<CCValAssign, 16> ArgLocs; 2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2163 ArgLocs, *DAG.getContext()); 2164 2165 // Allocate shadow area for Win64 2166 if (IsWin64) { 2167 CCInfo.AllocateStack(32, 8); 2168 } 2169 2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2171 2172 // Get a count of how many bytes are to be pushed on the stack. 2173 unsigned NumBytes = CCInfo.getNextStackOffset(); 2174 if (IsSibcall) 2175 // This is a sibcall. The memory operands are available in caller's 2176 // own caller's stack. 2177 NumBytes = 0; 2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2179 IsTailCallConvention(CallConv)) 2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2181 2182 int FPDiff = 0; 2183 if (isTailCall && !IsSibcall) { 2184 // Lower arguments at fp - stackoffset + fpdiff. 2185 unsigned NumBytesCallerPushed = 2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2187 FPDiff = NumBytesCallerPushed - NumBytes; 2188 2189 // Set the delta of movement of the returnaddr stackslot. 2190 // But only set if delta is greater than previous delta. 2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2193 } 2194 2195 if (!IsSibcall) 2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2197 2198 SDValue RetAddrFrIdx; 2199 // Load return address for tail calls. 2200 if (isTailCall && FPDiff) 2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2202 Is64Bit, FPDiff, dl); 2203 2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2205 SmallVector<SDValue, 8> MemOpChains; 2206 SDValue StackPtr; 2207 2208 // Walk the register/memloc assignments, inserting copies/loads. In the case 2209 // of tail call optimization arguments are handle later. 2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2211 CCValAssign &VA = ArgLocs[i]; 2212 EVT RegVT = VA.getLocVT(); 2213 SDValue Arg = OutVals[i]; 2214 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2215 bool isByVal = Flags.isByVal(); 2216 2217 // Promote the value if needed. 2218 switch (VA.getLocInfo()) { 2219 default: llvm_unreachable("Unknown loc info!"); 2220 case CCValAssign::Full: break; 2221 case CCValAssign::SExt: 2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2223 break; 2224 case CCValAssign::ZExt: 2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2226 break; 2227 case CCValAssign::AExt: 2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2229 // Special case: passing MMX values in XMM registers. 2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2233 } else 2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2235 break; 2236 case CCValAssign::BCvt: 2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2238 break; 2239 case CCValAssign::Indirect: { 2240 // Store the argument. 2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2244 MachinePointerInfo::getFixedStack(FI), 2245 false, false, 0); 2246 Arg = SpillSlot; 2247 break; 2248 } 2249 } 2250 2251 if (VA.isRegLoc()) { 2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2253 if (isVarArg && IsWin64) { 2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2255 // shadow reg if callee is a varargs function. 2256 unsigned ShadowReg = 0; 2257 switch (VA.getLocReg()) { 2258 case X86::XMM0: ShadowReg = X86::RCX; break; 2259 case X86::XMM1: ShadowReg = X86::RDX; break; 2260 case X86::XMM2: ShadowReg = X86::R8; break; 2261 case X86::XMM3: ShadowReg = X86::R9; break; 2262 } 2263 if (ShadowReg) 2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2265 } 2266 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2267 assert(VA.isMemLoc()); 2268 if (StackPtr.getNode() == 0) 2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2271 dl, DAG, VA, Flags)); 2272 } 2273 } 2274 2275 if (!MemOpChains.empty()) 2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2277 &MemOpChains[0], MemOpChains.size()); 2278 2279 // Build a sequence of copy-to-reg nodes chained together with token chain 2280 // and flag operands which copy the outgoing args into registers. 2281 SDValue InFlag; 2282 // Tail call byval lowering might overwrite argument registers so in case of 2283 // tail call optimization the copies to registers are lowered later. 2284 if (!isTailCall) 2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2287 RegsToPass[i].second, InFlag); 2288 InFlag = Chain.getValue(1); 2289 } 2290 2291 if (Subtarget->isPICStyleGOT()) { 2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2293 // GOT pointer. 2294 if (!isTailCall) { 2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2296 DAG.getNode(X86ISD::GlobalBaseReg, 2297 DebugLoc(), getPointerTy()), 2298 InFlag); 2299 InFlag = Chain.getValue(1); 2300 } else { 2301 // If we are tail calling and generating PIC/GOT style code load the 2302 // address of the callee into ECX. The value in ecx is used as target of 2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2304 // for tail calls on PIC/GOT architectures. Normally we would just put the 2305 // address of GOT into ebx and then call target@PLT. But for tail calls 2306 // ebx would be restored (since ebx is callee saved) before jumping to the 2307 // target@PLT. 2308 2309 // Note: The actual moving to ECX is done further down. 2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2311 if (G && !G->getGlobal()->hasHiddenVisibility() && 2312 !G->getGlobal()->hasProtectedVisibility()) 2313 Callee = LowerGlobalAddress(Callee, DAG); 2314 else if (isa<ExternalSymbolSDNode>(Callee)) 2315 Callee = LowerExternalSymbol(Callee, DAG); 2316 } 2317 } 2318 2319 if (Is64Bit && isVarArg && !IsWin64) { 2320 // From AMD64 ABI document: 2321 // For calls that may call functions that use varargs or stdargs 2322 // (prototype-less calls or calls to functions containing ellipsis (...) in 2323 // the declaration) %al is used as hidden argument to specify the number 2324 // of SSE registers used. The contents of %al do not need to match exactly 2325 // the number of registers, but must be an ubound on the number of SSE 2326 // registers used and is in the range 0 - 8 inclusive. 2327 2328 // Count the number of XMM registers allocated. 2329 static const uint16_t XMMArgRegs[] = { 2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2332 }; 2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2334 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2335 && "SSE registers cannot be used when SSE is disabled"); 2336 2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2339 InFlag = Chain.getValue(1); 2340 } 2341 2342 2343 // For tail calls lower the arguments to the 'real' stack slot. 2344 if (isTailCall) { 2345 // Force all the incoming stack arguments to be loaded from the stack 2346 // before any new outgoing arguments are stored to the stack, because the 2347 // outgoing stack slots may alias the incoming argument stack slots, and 2348 // the alias isn't otherwise explicit. This is slightly more conservative 2349 // than necessary, because it means that each store effectively depends 2350 // on every argument instead of just those arguments it would clobber. 2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2352 2353 SmallVector<SDValue, 8> MemOpChains2; 2354 SDValue FIN; 2355 int FI = 0; 2356 // Do not flag preceding copytoreg stuff together with the following stuff. 2357 InFlag = SDValue(); 2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2360 CCValAssign &VA = ArgLocs[i]; 2361 if (VA.isRegLoc()) 2362 continue; 2363 assert(VA.isMemLoc()); 2364 SDValue Arg = OutVals[i]; 2365 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2366 // Create frame index. 2367 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2370 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2371 2372 if (Flags.isByVal()) { 2373 // Copy relative to framepointer. 2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2375 if (StackPtr.getNode() == 0) 2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2377 getPointerTy()); 2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2379 2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2381 ArgChain, 2382 Flags, DAG, dl)); 2383 } else { 2384 // Store relative to framepointer. 2385 MemOpChains2.push_back( 2386 DAG.getStore(ArgChain, dl, Arg, FIN, 2387 MachinePointerInfo::getFixedStack(FI), 2388 false, false, 0)); 2389 } 2390 } 2391 } 2392 2393 if (!MemOpChains2.empty()) 2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2395 &MemOpChains2[0], MemOpChains2.size()); 2396 2397 // Copy arguments to their registers. 2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2400 RegsToPass[i].second, InFlag); 2401 InFlag = Chain.getValue(1); 2402 } 2403 InFlag =SDValue(); 2404 2405 // Store the return address to the appropriate stack slot. 2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2407 FPDiff, dl); 2408 } 2409 2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2412 // In the 64-bit large code model, we have to make all calls 2413 // through a register, since the call instruction's 32-bit 2414 // pc-relative offset may not be large enough to hold the whole 2415 // address. 2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2417 // If the callee is a GlobalAddress node (quite common, every direct call 2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2419 // it. 2420 2421 // We should use extra load for direct calls to dllimported functions in 2422 // non-JIT mode. 2423 const GlobalValue *GV = G->getGlobal(); 2424 if (!GV->hasDLLImportLinkage()) { 2425 unsigned char OpFlags = 0; 2426 bool ExtraLoad = false; 2427 unsigned WrapperKind = ISD::DELETED_NODE; 2428 2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2430 // external symbols most go through the PLT in PIC mode. If the symbol 2431 // has hidden or protected visibility, or if it is static or local, then 2432 // we don't need to use the PLT - we can directly call it. 2433 if (Subtarget->isTargetELF() && 2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2436 OpFlags = X86II::MO_PLT; 2437 } else if (Subtarget->isPICStyleStubAny() && 2438 (GV->isDeclaration() || GV->isWeakForLinker()) && 2439 (!Subtarget->getTargetTriple().isMacOSX() || 2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2441 // PC-relative references to external symbols should go through $stub, 2442 // unless we're building with the leopard linker or later, which 2443 // automatically synthesizes these stubs. 2444 OpFlags = X86II::MO_DARWIN_STUB; 2445 } else if (Subtarget->isPICStyleRIPRel() && 2446 isa<Function>(GV) && 2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2448 // If the function is marked as non-lazy, generate an indirect call 2449 // which loads from the GOT directly. This avoids runtime overhead 2450 // at the cost of eager binding (and one extra byte of encoding). 2451 OpFlags = X86II::MO_GOTPCREL; 2452 WrapperKind = X86ISD::WrapperRIP; 2453 ExtraLoad = true; 2454 } 2455 2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2457 G->getOffset(), OpFlags); 2458 2459 // Add a wrapper if needed. 2460 if (WrapperKind != ISD::DELETED_NODE) 2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2462 // Add extra indirection if needed. 2463 if (ExtraLoad) 2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2465 MachinePointerInfo::getGOT(), 2466 false, false, false, 0); 2467 } 2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2469 unsigned char OpFlags = 0; 2470 2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2472 // external symbols should go through the PLT. 2473 if (Subtarget->isTargetELF() && 2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2475 OpFlags = X86II::MO_PLT; 2476 } else if (Subtarget->isPICStyleStubAny() && 2477 (!Subtarget->getTargetTriple().isMacOSX() || 2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2479 // PC-relative references to external symbols should go through $stub, 2480 // unless we're building with the leopard linker or later, which 2481 // automatically synthesizes these stubs. 2482 OpFlags = X86II::MO_DARWIN_STUB; 2483 } 2484 2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2486 OpFlags); 2487 } 2488 2489 // Returns a chain & a flag for retval copy to use. 2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2491 SmallVector<SDValue, 8> Ops; 2492 2493 if (!IsSibcall && isTailCall) { 2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2495 DAG.getIntPtrConstant(0, true), InFlag); 2496 InFlag = Chain.getValue(1); 2497 } 2498 2499 Ops.push_back(Chain); 2500 Ops.push_back(Callee); 2501 2502 if (isTailCall) 2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2504 2505 // Add argument registers to the end of the list so that they are known live 2506 // into the call. 2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2509 RegsToPass[i].second.getValueType())); 2510 2511 // Add an implicit use GOT pointer in EBX. 2512 if (!isTailCall && Subtarget->isPICStyleGOT()) 2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2514 2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2516 if (Is64Bit && isVarArg && !IsWin64) 2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2518 2519 // Add a register mask operand representing the call-preserved registers. 2520 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2521 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2522 assert(Mask && "Missing call preserved mask for calling convention"); 2523 Ops.push_back(DAG.getRegisterMask(Mask)); 2524 2525 if (InFlag.getNode()) 2526 Ops.push_back(InFlag); 2527 2528 if (isTailCall) { 2529 // We used to do: 2530 //// If this is the first return lowered for this function, add the regs 2531 //// to the liveout set for the function. 2532 // This isn't right, although it's probably harmless on x86; liveouts 2533 // should be computed from returns not tail calls. Consider a void 2534 // function making a tail call to a function returning int. 2535 return DAG.getNode(X86ISD::TC_RETURN, dl, 2536 NodeTys, &Ops[0], Ops.size()); 2537 } 2538 2539 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2540 InFlag = Chain.getValue(1); 2541 2542 // Create the CALLSEQ_END node. 2543 unsigned NumBytesForCalleeToPush; 2544 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2545 getTargetMachine().Options.GuaranteedTailCallOpt)) 2546 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2547 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2548 IsStructRet) 2549 // If this is a call to a struct-return function, the callee 2550 // pops the hidden struct pointer, so we have to push it back. 2551 // This is common for Darwin/X86, Linux & Mingw32 targets. 2552 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2553 NumBytesForCalleeToPush = 4; 2554 else 2555 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2556 2557 // Returns a flag for retval copy to use. 2558 if (!IsSibcall) { 2559 Chain = DAG.getCALLSEQ_END(Chain, 2560 DAG.getIntPtrConstant(NumBytes, true), 2561 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2562 true), 2563 InFlag); 2564 InFlag = Chain.getValue(1); 2565 } 2566 2567 // Handle result values, copying them out of physregs into vregs that we 2568 // return. 2569 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2570 Ins, dl, DAG, InVals); 2571} 2572 2573 2574//===----------------------------------------------------------------------===// 2575// Fast Calling Convention (tail call) implementation 2576//===----------------------------------------------------------------------===// 2577 2578// Like std call, callee cleans arguments, convention except that ECX is 2579// reserved for storing the tail called function address. Only 2 registers are 2580// free for argument passing (inreg). Tail call optimization is performed 2581// provided: 2582// * tailcallopt is enabled 2583// * caller/callee are fastcc 2584// On X86_64 architecture with GOT-style position independent code only local 2585// (within module) calls are supported at the moment. 2586// To keep the stack aligned according to platform abi the function 2587// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2588// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2589// If a tail called function callee has more arguments than the caller the 2590// caller needs to make sure that there is room to move the RETADDR to. This is 2591// achieved by reserving an area the size of the argument delta right after the 2592// original REtADDR, but before the saved framepointer or the spilled registers 2593// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2594// stack layout: 2595// arg1 2596// arg2 2597// RETADDR 2598// [ new RETADDR 2599// move area ] 2600// (possible EBP) 2601// ESI 2602// EDI 2603// local1 .. 2604 2605/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2606/// for a 16 byte align requirement. 2607unsigned 2608X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2609 SelectionDAG& DAG) const { 2610 MachineFunction &MF = DAG.getMachineFunction(); 2611 const TargetMachine &TM = MF.getTarget(); 2612 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2613 unsigned StackAlignment = TFI.getStackAlignment(); 2614 uint64_t AlignMask = StackAlignment - 1; 2615 int64_t Offset = StackSize; 2616 uint64_t SlotSize = TD->getPointerSize(); 2617 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2618 // Number smaller than 12 so just add the difference. 2619 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2620 } else { 2621 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2622 Offset = ((~AlignMask) & Offset) + StackAlignment + 2623 (StackAlignment-SlotSize); 2624 } 2625 return Offset; 2626} 2627 2628/// MatchingStackOffset - Return true if the given stack call argument is 2629/// already available in the same position (relatively) of the caller's 2630/// incoming argument stack. 2631static 2632bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2633 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2634 const X86InstrInfo *TII) { 2635 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2636 int FI = INT_MAX; 2637 if (Arg.getOpcode() == ISD::CopyFromReg) { 2638 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2639 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2640 return false; 2641 MachineInstr *Def = MRI->getVRegDef(VR); 2642 if (!Def) 2643 return false; 2644 if (!Flags.isByVal()) { 2645 if (!TII->isLoadFromStackSlot(Def, FI)) 2646 return false; 2647 } else { 2648 unsigned Opcode = Def->getOpcode(); 2649 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2650 Def->getOperand(1).isFI()) { 2651 FI = Def->getOperand(1).getIndex(); 2652 Bytes = Flags.getByValSize(); 2653 } else 2654 return false; 2655 } 2656 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2657 if (Flags.isByVal()) 2658 // ByVal argument is passed in as a pointer but it's now being 2659 // dereferenced. e.g. 2660 // define @foo(%struct.X* %A) { 2661 // tail call @bar(%struct.X* byval %A) 2662 // } 2663 return false; 2664 SDValue Ptr = Ld->getBasePtr(); 2665 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2666 if (!FINode) 2667 return false; 2668 FI = FINode->getIndex(); 2669 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2670 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2671 FI = FINode->getIndex(); 2672 Bytes = Flags.getByValSize(); 2673 } else 2674 return false; 2675 2676 assert(FI != INT_MAX); 2677 if (!MFI->isFixedObjectIndex(FI)) 2678 return false; 2679 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2680} 2681 2682/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2683/// for tail call optimization. Targets which want to do tail call 2684/// optimization should implement this function. 2685bool 2686X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2687 CallingConv::ID CalleeCC, 2688 bool isVarArg, 2689 bool isCalleeStructRet, 2690 bool isCallerStructRet, 2691 const SmallVectorImpl<ISD::OutputArg> &Outs, 2692 const SmallVectorImpl<SDValue> &OutVals, 2693 const SmallVectorImpl<ISD::InputArg> &Ins, 2694 SelectionDAG& DAG) const { 2695 if (!IsTailCallConvention(CalleeCC) && 2696 CalleeCC != CallingConv::C) 2697 return false; 2698 2699 // If -tailcallopt is specified, make fastcc functions tail-callable. 2700 const MachineFunction &MF = DAG.getMachineFunction(); 2701 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2702 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2703 bool CCMatch = CallerCC == CalleeCC; 2704 2705 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2706 if (IsTailCallConvention(CalleeCC) && CCMatch) 2707 return true; 2708 return false; 2709 } 2710 2711 // Look for obvious safe cases to perform tail call optimization that do not 2712 // require ABI changes. This is what gcc calls sibcall. 2713 2714 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2715 // emit a special epilogue. 2716 if (RegInfo->needsStackRealignment(MF)) 2717 return false; 2718 2719 // Also avoid sibcall optimization if either caller or callee uses struct 2720 // return semantics. 2721 if (isCalleeStructRet || isCallerStructRet) 2722 return false; 2723 2724 // An stdcall caller is expected to clean up its arguments; the callee 2725 // isn't going to do that. 2726 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2727 return false; 2728 2729 // Do not sibcall optimize vararg calls unless all arguments are passed via 2730 // registers. 2731 if (isVarArg && !Outs.empty()) { 2732 2733 // Optimizing for varargs on Win64 is unlikely to be safe without 2734 // additional testing. 2735 if (Subtarget->isTargetWin64()) 2736 return false; 2737 2738 SmallVector<CCValAssign, 16> ArgLocs; 2739 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2740 getTargetMachine(), ArgLocs, *DAG.getContext()); 2741 2742 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2743 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2744 if (!ArgLocs[i].isRegLoc()) 2745 return false; 2746 } 2747 2748 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2749 // stack. Therefore, if it's not used by the call it is not safe to optimize 2750 // this into a sibcall. 2751 bool Unused = false; 2752 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2753 if (!Ins[i].Used) { 2754 Unused = true; 2755 break; 2756 } 2757 } 2758 if (Unused) { 2759 SmallVector<CCValAssign, 16> RVLocs; 2760 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2761 getTargetMachine(), RVLocs, *DAG.getContext()); 2762 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2763 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2764 CCValAssign &VA = RVLocs[i]; 2765 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2766 return false; 2767 } 2768 } 2769 2770 // If the calling conventions do not match, then we'd better make sure the 2771 // results are returned in the same way as what the caller expects. 2772 if (!CCMatch) { 2773 SmallVector<CCValAssign, 16> RVLocs1; 2774 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2775 getTargetMachine(), RVLocs1, *DAG.getContext()); 2776 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2777 2778 SmallVector<CCValAssign, 16> RVLocs2; 2779 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2780 getTargetMachine(), RVLocs2, *DAG.getContext()); 2781 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2782 2783 if (RVLocs1.size() != RVLocs2.size()) 2784 return false; 2785 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2786 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2787 return false; 2788 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2789 return false; 2790 if (RVLocs1[i].isRegLoc()) { 2791 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2792 return false; 2793 } else { 2794 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2795 return false; 2796 } 2797 } 2798 } 2799 2800 // If the callee takes no arguments then go on to check the results of the 2801 // call. 2802 if (!Outs.empty()) { 2803 // Check if stack adjustment is needed. For now, do not do this if any 2804 // argument is passed on the stack. 2805 SmallVector<CCValAssign, 16> ArgLocs; 2806 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2807 getTargetMachine(), ArgLocs, *DAG.getContext()); 2808 2809 // Allocate shadow area for Win64 2810 if (Subtarget->isTargetWin64()) { 2811 CCInfo.AllocateStack(32, 8); 2812 } 2813 2814 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2815 if (CCInfo.getNextStackOffset()) { 2816 MachineFunction &MF = DAG.getMachineFunction(); 2817 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2818 return false; 2819 2820 // Check if the arguments are already laid out in the right way as 2821 // the caller's fixed stack objects. 2822 MachineFrameInfo *MFI = MF.getFrameInfo(); 2823 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2824 const X86InstrInfo *TII = 2825 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2826 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2827 CCValAssign &VA = ArgLocs[i]; 2828 SDValue Arg = OutVals[i]; 2829 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2830 if (VA.getLocInfo() == CCValAssign::Indirect) 2831 return false; 2832 if (!VA.isRegLoc()) { 2833 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2834 MFI, MRI, TII)) 2835 return false; 2836 } 2837 } 2838 } 2839 2840 // If the tailcall address may be in a register, then make sure it's 2841 // possible to register allocate for it. In 32-bit, the call address can 2842 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2843 // callee-saved registers are restored. These happen to be the same 2844 // registers used to pass 'inreg' arguments so watch out for those. 2845 if (!Subtarget->is64Bit() && 2846 !isa<GlobalAddressSDNode>(Callee) && 2847 !isa<ExternalSymbolSDNode>(Callee)) { 2848 unsigned NumInRegs = 0; 2849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2850 CCValAssign &VA = ArgLocs[i]; 2851 if (!VA.isRegLoc()) 2852 continue; 2853 unsigned Reg = VA.getLocReg(); 2854 switch (Reg) { 2855 default: break; 2856 case X86::EAX: case X86::EDX: case X86::ECX: 2857 if (++NumInRegs == 3) 2858 return false; 2859 break; 2860 } 2861 } 2862 } 2863 } 2864 2865 return true; 2866} 2867 2868FastISel * 2869X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2870 return X86::createFastISel(funcInfo); 2871} 2872 2873 2874//===----------------------------------------------------------------------===// 2875// Other Lowering Hooks 2876//===----------------------------------------------------------------------===// 2877 2878static bool MayFoldLoad(SDValue Op) { 2879 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2880} 2881 2882static bool MayFoldIntoStore(SDValue Op) { 2883 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2884} 2885 2886static bool isTargetShuffle(unsigned Opcode) { 2887 switch(Opcode) { 2888 default: return false; 2889 case X86ISD::PSHUFD: 2890 case X86ISD::PSHUFHW: 2891 case X86ISD::PSHUFLW: 2892 case X86ISD::SHUFP: 2893 case X86ISD::PALIGN: 2894 case X86ISD::MOVLHPS: 2895 case X86ISD::MOVLHPD: 2896 case X86ISD::MOVHLPS: 2897 case X86ISD::MOVLPS: 2898 case X86ISD::MOVLPD: 2899 case X86ISD::MOVSHDUP: 2900 case X86ISD::MOVSLDUP: 2901 case X86ISD::MOVDDUP: 2902 case X86ISD::MOVSS: 2903 case X86ISD::MOVSD: 2904 case X86ISD::UNPCKL: 2905 case X86ISD::UNPCKH: 2906 case X86ISD::VPERMILP: 2907 case X86ISD::VPERM2X128: 2908 return true; 2909 } 2910} 2911 2912static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2913 SDValue V1, SelectionDAG &DAG) { 2914 switch(Opc) { 2915 default: llvm_unreachable("Unknown x86 shuffle node"); 2916 case X86ISD::MOVSHDUP: 2917 case X86ISD::MOVSLDUP: 2918 case X86ISD::MOVDDUP: 2919 return DAG.getNode(Opc, dl, VT, V1); 2920 } 2921} 2922 2923static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2924 SDValue V1, unsigned TargetMask, 2925 SelectionDAG &DAG) { 2926 switch(Opc) { 2927 default: llvm_unreachable("Unknown x86 shuffle node"); 2928 case X86ISD::PSHUFD: 2929 case X86ISD::PSHUFHW: 2930 case X86ISD::PSHUFLW: 2931 case X86ISD::VPERMILP: 2932 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2933 } 2934} 2935 2936static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2937 SDValue V1, SDValue V2, unsigned TargetMask, 2938 SelectionDAG &DAG) { 2939 switch(Opc) { 2940 default: llvm_unreachable("Unknown x86 shuffle node"); 2941 case X86ISD::PALIGN: 2942 case X86ISD::SHUFP: 2943 case X86ISD::VPERM2X128: 2944 return DAG.getNode(Opc, dl, VT, V1, V2, 2945 DAG.getConstant(TargetMask, MVT::i8)); 2946 } 2947} 2948 2949static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2950 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2951 switch(Opc) { 2952 default: llvm_unreachable("Unknown x86 shuffle node"); 2953 case X86ISD::MOVLHPS: 2954 case X86ISD::MOVLHPD: 2955 case X86ISD::MOVHLPS: 2956 case X86ISD::MOVLPS: 2957 case X86ISD::MOVLPD: 2958 case X86ISD::MOVSS: 2959 case X86ISD::MOVSD: 2960 case X86ISD::UNPCKL: 2961 case X86ISD::UNPCKH: 2962 return DAG.getNode(Opc, dl, VT, V1, V2); 2963 } 2964} 2965 2966SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2967 MachineFunction &MF = DAG.getMachineFunction(); 2968 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2969 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2970 2971 if (ReturnAddrIndex == 0) { 2972 // Set up a frame object for the return address. 2973 uint64_t SlotSize = TD->getPointerSize(); 2974 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2975 false); 2976 FuncInfo->setRAIndex(ReturnAddrIndex); 2977 } 2978 2979 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2980} 2981 2982 2983bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2984 bool hasSymbolicDisplacement) { 2985 // Offset should fit into 32 bit immediate field. 2986 if (!isInt<32>(Offset)) 2987 return false; 2988 2989 // If we don't have a symbolic displacement - we don't have any extra 2990 // restrictions. 2991 if (!hasSymbolicDisplacement) 2992 return true; 2993 2994 // FIXME: Some tweaks might be needed for medium code model. 2995 if (M != CodeModel::Small && M != CodeModel::Kernel) 2996 return false; 2997 2998 // For small code model we assume that latest object is 16MB before end of 31 2999 // bits boundary. We may also accept pretty large negative constants knowing 3000 // that all objects are in the positive half of address space. 3001 if (M == CodeModel::Small && Offset < 16*1024*1024) 3002 return true; 3003 3004 // For kernel code model we know that all object resist in the negative half 3005 // of 32bits address space. We may not accept negative offsets, since they may 3006 // be just off and we may accept pretty large positive ones. 3007 if (M == CodeModel::Kernel && Offset > 0) 3008 return true; 3009 3010 return false; 3011} 3012 3013/// isCalleePop - Determines whether the callee is required to pop its 3014/// own arguments. Callee pop is necessary to support tail calls. 3015bool X86::isCalleePop(CallingConv::ID CallingConv, 3016 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3017 if (IsVarArg) 3018 return false; 3019 3020 switch (CallingConv) { 3021 default: 3022 return false; 3023 case CallingConv::X86_StdCall: 3024 return !is64Bit; 3025 case CallingConv::X86_FastCall: 3026 return !is64Bit; 3027 case CallingConv::X86_ThisCall: 3028 return !is64Bit; 3029 case CallingConv::Fast: 3030 return TailCallOpt; 3031 case CallingConv::GHC: 3032 return TailCallOpt; 3033 } 3034} 3035 3036/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3037/// specific condition code, returning the condition code and the LHS/RHS of the 3038/// comparison to make. 3039static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3040 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3041 if (!isFP) { 3042 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3043 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3044 // X > -1 -> X == 0, jump !sign. 3045 RHS = DAG.getConstant(0, RHS.getValueType()); 3046 return X86::COND_NS; 3047 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3048 // X < 0 -> X == 0, jump on sign. 3049 return X86::COND_S; 3050 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3051 // X < 1 -> X <= 0 3052 RHS = DAG.getConstant(0, RHS.getValueType()); 3053 return X86::COND_LE; 3054 } 3055 } 3056 3057 switch (SetCCOpcode) { 3058 default: llvm_unreachable("Invalid integer condition!"); 3059 case ISD::SETEQ: return X86::COND_E; 3060 case ISD::SETGT: return X86::COND_G; 3061 case ISD::SETGE: return X86::COND_GE; 3062 case ISD::SETLT: return X86::COND_L; 3063 case ISD::SETLE: return X86::COND_LE; 3064 case ISD::SETNE: return X86::COND_NE; 3065 case ISD::SETULT: return X86::COND_B; 3066 case ISD::SETUGT: return X86::COND_A; 3067 case ISD::SETULE: return X86::COND_BE; 3068 case ISD::SETUGE: return X86::COND_AE; 3069 } 3070 } 3071 3072 // First determine if it is required or is profitable to flip the operands. 3073 3074 // If LHS is a foldable load, but RHS is not, flip the condition. 3075 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3076 !ISD::isNON_EXTLoad(RHS.getNode())) { 3077 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3078 std::swap(LHS, RHS); 3079 } 3080 3081 switch (SetCCOpcode) { 3082 default: break; 3083 case ISD::SETOLT: 3084 case ISD::SETOLE: 3085 case ISD::SETUGT: 3086 case ISD::SETUGE: 3087 std::swap(LHS, RHS); 3088 break; 3089 } 3090 3091 // On a floating point condition, the flags are set as follows: 3092 // ZF PF CF op 3093 // 0 | 0 | 0 | X > Y 3094 // 0 | 0 | 1 | X < Y 3095 // 1 | 0 | 0 | X == Y 3096 // 1 | 1 | 1 | unordered 3097 switch (SetCCOpcode) { 3098 default: llvm_unreachable("Condcode should be pre-legalized away"); 3099 case ISD::SETUEQ: 3100 case ISD::SETEQ: return X86::COND_E; 3101 case ISD::SETOLT: // flipped 3102 case ISD::SETOGT: 3103 case ISD::SETGT: return X86::COND_A; 3104 case ISD::SETOLE: // flipped 3105 case ISD::SETOGE: 3106 case ISD::SETGE: return X86::COND_AE; 3107 case ISD::SETUGT: // flipped 3108 case ISD::SETULT: 3109 case ISD::SETLT: return X86::COND_B; 3110 case ISD::SETUGE: // flipped 3111 case ISD::SETULE: 3112 case ISD::SETLE: return X86::COND_BE; 3113 case ISD::SETONE: 3114 case ISD::SETNE: return X86::COND_NE; 3115 case ISD::SETUO: return X86::COND_P; 3116 case ISD::SETO: return X86::COND_NP; 3117 case ISD::SETOEQ: 3118 case ISD::SETUNE: return X86::COND_INVALID; 3119 } 3120} 3121 3122/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3123/// code. Current x86 isa includes the following FP cmov instructions: 3124/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3125static bool hasFPCMov(unsigned X86CC) { 3126 switch (X86CC) { 3127 default: 3128 return false; 3129 case X86::COND_B: 3130 case X86::COND_BE: 3131 case X86::COND_E: 3132 case X86::COND_P: 3133 case X86::COND_A: 3134 case X86::COND_AE: 3135 case X86::COND_NE: 3136 case X86::COND_NP: 3137 return true; 3138 } 3139} 3140 3141/// isFPImmLegal - Returns true if the target can instruction select the 3142/// specified FP immediate natively. If false, the legalizer will 3143/// materialize the FP immediate as a load from a constant pool. 3144bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3145 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3146 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3147 return true; 3148 } 3149 return false; 3150} 3151 3152/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3153/// the specified range (L, H]. 3154static bool isUndefOrInRange(int Val, int Low, int Hi) { 3155 return (Val < 0) || (Val >= Low && Val < Hi); 3156} 3157 3158/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3159/// specified value. 3160static bool isUndefOrEqual(int Val, int CmpVal) { 3161 if (Val < 0 || Val == CmpVal) 3162 return true; 3163 return false; 3164} 3165 3166/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3167/// from position Pos and ending in Pos+Size, falls within the specified 3168/// sequential range (L, L+Pos]. or is undef. 3169static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3170 int Pos, int Size, int Low) { 3171 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3172 if (!isUndefOrEqual(Mask[i], Low)) 3173 return false; 3174 return true; 3175} 3176 3177/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3178/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3179/// the second operand. 3180static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3181 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3182 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3183 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3184 return (Mask[0] < 2 && Mask[1] < 2); 3185 return false; 3186} 3187 3188/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3189/// is suitable for input to PSHUFHW. 3190static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3191 if (VT != MVT::v8i16) 3192 return false; 3193 3194 // Lower quadword copied in order or undef. 3195 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3196 return false; 3197 3198 // Upper quadword shuffled. 3199 for (unsigned i = 4; i != 8; ++i) 3200 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3201 return false; 3202 3203 return true; 3204} 3205 3206/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3207/// is suitable for input to PSHUFLW. 3208static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3209 if (VT != MVT::v8i16) 3210 return false; 3211 3212 // Upper quadword copied in order. 3213 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3214 return false; 3215 3216 // Lower quadword shuffled. 3217 for (unsigned i = 0; i != 4; ++i) 3218 if (Mask[i] >= 4) 3219 return false; 3220 3221 return true; 3222} 3223 3224/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3225/// is suitable for input to PALIGNR. 3226static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3227 const X86Subtarget *Subtarget) { 3228 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3229 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3230 return false; 3231 3232 unsigned NumElts = VT.getVectorNumElements(); 3233 unsigned NumLanes = VT.getSizeInBits()/128; 3234 unsigned NumLaneElts = NumElts/NumLanes; 3235 3236 // Do not handle 64-bit element shuffles with palignr. 3237 if (NumLaneElts == 2) 3238 return false; 3239 3240 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3241 unsigned i; 3242 for (i = 0; i != NumLaneElts; ++i) { 3243 if (Mask[i+l] >= 0) 3244 break; 3245 } 3246 3247 // Lane is all undef, go to next lane 3248 if (i == NumLaneElts) 3249 continue; 3250 3251 int Start = Mask[i+l]; 3252 3253 // Make sure its in this lane in one of the sources 3254 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3255 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3256 return false; 3257 3258 // If not lane 0, then we must match lane 0 3259 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3260 return false; 3261 3262 // Correct second source to be contiguous with first source 3263 if (Start >= (int)NumElts) 3264 Start -= NumElts - NumLaneElts; 3265 3266 // Make sure we're shifting in the right direction. 3267 if (Start <= (int)(i+l)) 3268 return false; 3269 3270 Start -= i; 3271 3272 // Check the rest of the elements to see if they are consecutive. 3273 for (++i; i != NumLaneElts; ++i) { 3274 int Idx = Mask[i+l]; 3275 3276 // Make sure its in this lane 3277 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3278 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3279 return false; 3280 3281 // If not lane 0, then we must match lane 0 3282 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3283 return false; 3284 3285 if (Idx >= (int)NumElts) 3286 Idx -= NumElts - NumLaneElts; 3287 3288 if (!isUndefOrEqual(Idx, Start+i)) 3289 return false; 3290 3291 } 3292 } 3293 3294 return true; 3295} 3296 3297/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3298/// the two vector operands have swapped position. 3299static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3300 unsigned NumElems) { 3301 for (unsigned i = 0; i != NumElems; ++i) { 3302 int idx = Mask[i]; 3303 if (idx < 0) 3304 continue; 3305 else if (idx < (int)NumElems) 3306 Mask[i] = idx + NumElems; 3307 else 3308 Mask[i] = idx - NumElems; 3309 } 3310} 3311 3312/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3313/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3314/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3315/// reverse of what x86 shuffles want. 3316static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3317 bool Commuted = false) { 3318 if (!HasAVX && VT.getSizeInBits() == 256) 3319 return false; 3320 3321 unsigned NumElems = VT.getVectorNumElements(); 3322 unsigned NumLanes = VT.getSizeInBits()/128; 3323 unsigned NumLaneElems = NumElems/NumLanes; 3324 3325 if (NumLaneElems != 2 && NumLaneElems != 4) 3326 return false; 3327 3328 // VSHUFPSY divides the resulting vector into 4 chunks. 3329 // The sources are also splitted into 4 chunks, and each destination 3330 // chunk must come from a different source chunk. 3331 // 3332 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3333 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3334 // 3335 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3336 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3337 // 3338 // VSHUFPDY divides the resulting vector into 4 chunks. 3339 // The sources are also splitted into 4 chunks, and each destination 3340 // chunk must come from a different source chunk. 3341 // 3342 // SRC1 => X3 X2 X1 X0 3343 // SRC2 => Y3 Y2 Y1 Y0 3344 // 3345 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3346 // 3347 unsigned HalfLaneElems = NumLaneElems/2; 3348 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3349 for (unsigned i = 0; i != NumLaneElems; ++i) { 3350 int Idx = Mask[i+l]; 3351 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3352 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3353 return false; 3354 // For VSHUFPSY, the mask of the second half must be the same as the 3355 // first but with the appropriate offsets. This works in the same way as 3356 // VPERMILPS works with masks. 3357 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3358 continue; 3359 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3360 return false; 3361 } 3362 } 3363 3364 return true; 3365} 3366 3367/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3368/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3369static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3370 unsigned NumElems = VT.getVectorNumElements(); 3371 3372 if (VT.getSizeInBits() != 128) 3373 return false; 3374 3375 if (NumElems != 4) 3376 return false; 3377 3378 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3379 return isUndefOrEqual(Mask[0], 6) && 3380 isUndefOrEqual(Mask[1], 7) && 3381 isUndefOrEqual(Mask[2], 2) && 3382 isUndefOrEqual(Mask[3], 3); 3383} 3384 3385/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3386/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3387/// <2, 3, 2, 3> 3388static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3389 unsigned NumElems = VT.getVectorNumElements(); 3390 3391 if (VT.getSizeInBits() != 128) 3392 return false; 3393 3394 if (NumElems != 4) 3395 return false; 3396 3397 return isUndefOrEqual(Mask[0], 2) && 3398 isUndefOrEqual(Mask[1], 3) && 3399 isUndefOrEqual(Mask[2], 2) && 3400 isUndefOrEqual(Mask[3], 3); 3401} 3402 3403/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3404/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3405static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3406 if (VT.getSizeInBits() != 128) 3407 return false; 3408 3409 unsigned NumElems = VT.getVectorNumElements(); 3410 3411 if (NumElems != 2 && NumElems != 4) 3412 return false; 3413 3414 for (unsigned i = 0; i != NumElems/2; ++i) 3415 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3416 return false; 3417 3418 for (unsigned i = NumElems/2; i != NumElems; ++i) 3419 if (!isUndefOrEqual(Mask[i], i)) 3420 return false; 3421 3422 return true; 3423} 3424 3425/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3426/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3427static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3428 unsigned NumElems = VT.getVectorNumElements(); 3429 3430 if ((NumElems != 2 && NumElems != 4) 3431 || VT.getSizeInBits() > 128) 3432 return false; 3433 3434 for (unsigned i = 0; i != NumElems/2; ++i) 3435 if (!isUndefOrEqual(Mask[i], i)) 3436 return false; 3437 3438 for (unsigned i = 0; i != NumElems/2; ++i) 3439 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems)) 3440 return false; 3441 3442 return true; 3443} 3444 3445/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3446/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3447static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3448 bool HasAVX2, bool V2IsSplat = false) { 3449 unsigned NumElts = VT.getVectorNumElements(); 3450 3451 assert((VT.is128BitVector() || VT.is256BitVector()) && 3452 "Unsupported vector type for unpckh"); 3453 3454 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3455 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3456 return false; 3457 3458 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3459 // independently on 128-bit lanes. 3460 unsigned NumLanes = VT.getSizeInBits()/128; 3461 unsigned NumLaneElts = NumElts/NumLanes; 3462 3463 for (unsigned l = 0; l != NumLanes; ++l) { 3464 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3465 i != (l+1)*NumLaneElts; 3466 i += 2, ++j) { 3467 int BitI = Mask[i]; 3468 int BitI1 = Mask[i+1]; 3469 if (!isUndefOrEqual(BitI, j)) 3470 return false; 3471 if (V2IsSplat) { 3472 if (!isUndefOrEqual(BitI1, NumElts)) 3473 return false; 3474 } else { 3475 if (!isUndefOrEqual(BitI1, j + NumElts)) 3476 return false; 3477 } 3478 } 3479 } 3480 3481 return true; 3482} 3483 3484/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3485/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3486static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3487 bool HasAVX2, bool V2IsSplat = false) { 3488 unsigned NumElts = VT.getVectorNumElements(); 3489 3490 assert((VT.is128BitVector() || VT.is256BitVector()) && 3491 "Unsupported vector type for unpckh"); 3492 3493 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3494 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3495 return false; 3496 3497 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3498 // independently on 128-bit lanes. 3499 unsigned NumLanes = VT.getSizeInBits()/128; 3500 unsigned NumLaneElts = NumElts/NumLanes; 3501 3502 for (unsigned l = 0; l != NumLanes; ++l) { 3503 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3504 i != (l+1)*NumLaneElts; i += 2, ++j) { 3505 int BitI = Mask[i]; 3506 int BitI1 = Mask[i+1]; 3507 if (!isUndefOrEqual(BitI, j)) 3508 return false; 3509 if (V2IsSplat) { 3510 if (isUndefOrEqual(BitI1, NumElts)) 3511 return false; 3512 } else { 3513 if (!isUndefOrEqual(BitI1, j+NumElts)) 3514 return false; 3515 } 3516 } 3517 } 3518 return true; 3519} 3520 3521/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3522/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3523/// <0, 0, 1, 1> 3524static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3525 bool HasAVX2) { 3526 unsigned NumElts = VT.getVectorNumElements(); 3527 3528 assert((VT.is128BitVector() || VT.is256BitVector()) && 3529 "Unsupported vector type for unpckh"); 3530 3531 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3532 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3533 return false; 3534 3535 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3536 // FIXME: Need a better way to get rid of this, there's no latency difference 3537 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3538 // the former later. We should also remove the "_undef" special mask. 3539 if (NumElts == 4 && VT.getSizeInBits() == 256) 3540 return false; 3541 3542 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3543 // independently on 128-bit lanes. 3544 unsigned NumLanes = VT.getSizeInBits()/128; 3545 unsigned NumLaneElts = NumElts/NumLanes; 3546 3547 for (unsigned l = 0; l != NumLanes; ++l) { 3548 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3549 i != (l+1)*NumLaneElts; 3550 i += 2, ++j) { 3551 int BitI = Mask[i]; 3552 int BitI1 = Mask[i+1]; 3553 3554 if (!isUndefOrEqual(BitI, j)) 3555 return false; 3556 if (!isUndefOrEqual(BitI1, j)) 3557 return false; 3558 } 3559 } 3560 3561 return true; 3562} 3563 3564/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3565/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3566/// <2, 2, 3, 3> 3567static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3568 unsigned NumElts = VT.getVectorNumElements(); 3569 3570 assert((VT.is128BitVector() || VT.is256BitVector()) && 3571 "Unsupported vector type for unpckh"); 3572 3573 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3574 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3575 return false; 3576 3577 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3578 // independently on 128-bit lanes. 3579 unsigned NumLanes = VT.getSizeInBits()/128; 3580 unsigned NumLaneElts = NumElts/NumLanes; 3581 3582 for (unsigned l = 0; l != NumLanes; ++l) { 3583 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3584 i != (l+1)*NumLaneElts; i += 2, ++j) { 3585 int BitI = Mask[i]; 3586 int BitI1 = Mask[i+1]; 3587 if (!isUndefOrEqual(BitI, j)) 3588 return false; 3589 if (!isUndefOrEqual(BitI1, j)) 3590 return false; 3591 } 3592 } 3593 return true; 3594} 3595 3596/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3597/// specifies a shuffle of elements that is suitable for input to MOVSS, 3598/// MOVSD, and MOVD, i.e. setting the lowest element. 3599static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3600 if (VT.getVectorElementType().getSizeInBits() < 32) 3601 return false; 3602 if (VT.getSizeInBits() == 256) 3603 return false; 3604 3605 unsigned NumElts = VT.getVectorNumElements(); 3606 3607 if (!isUndefOrEqual(Mask[0], NumElts)) 3608 return false; 3609 3610 for (unsigned i = 1; i != NumElts; ++i) 3611 if (!isUndefOrEqual(Mask[i], i)) 3612 return false; 3613 3614 return true; 3615} 3616 3617/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3618/// as permutations between 128-bit chunks or halves. As an example: this 3619/// shuffle bellow: 3620/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3621/// The first half comes from the second half of V1 and the second half from the 3622/// the second half of V2. 3623static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3624 if (!HasAVX || VT.getSizeInBits() != 256) 3625 return false; 3626 3627 // The shuffle result is divided into half A and half B. In total the two 3628 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3629 // B must come from C, D, E or F. 3630 unsigned HalfSize = VT.getVectorNumElements()/2; 3631 bool MatchA = false, MatchB = false; 3632 3633 // Check if A comes from one of C, D, E, F. 3634 for (unsigned Half = 0; Half != 4; ++Half) { 3635 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3636 MatchA = true; 3637 break; 3638 } 3639 } 3640 3641 // Check if B comes from one of C, D, E, F. 3642 for (unsigned Half = 0; Half != 4; ++Half) { 3643 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3644 MatchB = true; 3645 break; 3646 } 3647 } 3648 3649 return MatchA && MatchB; 3650} 3651 3652/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3653/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3654static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3655 EVT VT = SVOp->getValueType(0); 3656 3657 unsigned HalfSize = VT.getVectorNumElements()/2; 3658 3659 unsigned FstHalf = 0, SndHalf = 0; 3660 for (unsigned i = 0; i < HalfSize; ++i) { 3661 if (SVOp->getMaskElt(i) > 0) { 3662 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3663 break; 3664 } 3665 } 3666 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3667 if (SVOp->getMaskElt(i) > 0) { 3668 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3669 break; 3670 } 3671 } 3672 3673 return (FstHalf | (SndHalf << 4)); 3674} 3675 3676/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3677/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3678/// Note that VPERMIL mask matching is different depending whether theunderlying 3679/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3680/// to the same elements of the low, but to the higher half of the source. 3681/// In VPERMILPD the two lanes could be shuffled independently of each other 3682/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3683static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3684 if (!HasAVX) 3685 return false; 3686 3687 unsigned NumElts = VT.getVectorNumElements(); 3688 // Only match 256-bit with 32/64-bit types 3689 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3690 return false; 3691 3692 unsigned NumLanes = VT.getSizeInBits()/128; 3693 unsigned LaneSize = NumElts/NumLanes; 3694 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3695 for (unsigned i = 0; i != LaneSize; ++i) { 3696 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3697 return false; 3698 if (NumElts != 8 || l == 0) 3699 continue; 3700 // VPERMILPS handling 3701 if (Mask[i] < 0) 3702 continue; 3703 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3704 return false; 3705 } 3706 } 3707 3708 return true; 3709} 3710 3711/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3712/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3713/// element of vector 2 and the other elements to come from vector 1 in order. 3714static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3715 bool V2IsSplat = false, bool V2IsUndef = false) { 3716 unsigned NumOps = VT.getVectorNumElements(); 3717 if (VT.getSizeInBits() == 256) 3718 return false; 3719 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3720 return false; 3721 3722 if (!isUndefOrEqual(Mask[0], 0)) 3723 return false; 3724 3725 for (unsigned i = 1; i != NumOps; ++i) 3726 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3727 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3728 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3729 return false; 3730 3731 return true; 3732} 3733 3734/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3735/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3736/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3737static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3738 const X86Subtarget *Subtarget) { 3739 if (!Subtarget->hasSSE3()) 3740 return false; 3741 3742 unsigned NumElems = VT.getVectorNumElements(); 3743 3744 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3745 (VT.getSizeInBits() == 256 && NumElems != 8)) 3746 return false; 3747 3748 // "i+1" is the value the indexed mask element must have 3749 for (unsigned i = 0; i != NumElems; i += 2) 3750 if (!isUndefOrEqual(Mask[i], i+1) || 3751 !isUndefOrEqual(Mask[i+1], i+1)) 3752 return false; 3753 3754 return true; 3755} 3756 3757/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3758/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3759/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3760static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3761 const X86Subtarget *Subtarget) { 3762 if (!Subtarget->hasSSE3()) 3763 return false; 3764 3765 unsigned NumElems = VT.getVectorNumElements(); 3766 3767 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3768 (VT.getSizeInBits() == 256 && NumElems != 8)) 3769 return false; 3770 3771 // "i" is the value the indexed mask element must have 3772 for (unsigned i = 0; i != NumElems; i += 2) 3773 if (!isUndefOrEqual(Mask[i], i) || 3774 !isUndefOrEqual(Mask[i+1], i)) 3775 return false; 3776 3777 return true; 3778} 3779 3780/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3781/// specifies a shuffle of elements that is suitable for input to 256-bit 3782/// version of MOVDDUP. 3783static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3784 unsigned NumElts = VT.getVectorNumElements(); 3785 3786 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3787 return false; 3788 3789 for (unsigned i = 0; i != NumElts/2; ++i) 3790 if (!isUndefOrEqual(Mask[i], 0)) 3791 return false; 3792 for (unsigned i = NumElts/2; i != NumElts; ++i) 3793 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3794 return false; 3795 return true; 3796} 3797 3798/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3799/// specifies a shuffle of elements that is suitable for input to 128-bit 3800/// version of MOVDDUP. 3801static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3802 if (VT.getSizeInBits() != 128) 3803 return false; 3804 3805 unsigned e = VT.getVectorNumElements() / 2; 3806 for (unsigned i = 0; i != e; ++i) 3807 if (!isUndefOrEqual(Mask[i], i)) 3808 return false; 3809 for (unsigned i = 0; i != e; ++i) 3810 if (!isUndefOrEqual(Mask[e+i], i)) 3811 return false; 3812 return true; 3813} 3814 3815/// isVEXTRACTF128Index - Return true if the specified 3816/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3817/// suitable for input to VEXTRACTF128. 3818bool X86::isVEXTRACTF128Index(SDNode *N) { 3819 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3820 return false; 3821 3822 // The index should be aligned on a 128-bit boundary. 3823 uint64_t Index = 3824 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3825 3826 unsigned VL = N->getValueType(0).getVectorNumElements(); 3827 unsigned VBits = N->getValueType(0).getSizeInBits(); 3828 unsigned ElSize = VBits / VL; 3829 bool Result = (Index * ElSize) % 128 == 0; 3830 3831 return Result; 3832} 3833 3834/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3835/// operand specifies a subvector insert that is suitable for input to 3836/// VINSERTF128. 3837bool X86::isVINSERTF128Index(SDNode *N) { 3838 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3839 return false; 3840 3841 // The index should be aligned on a 128-bit boundary. 3842 uint64_t Index = 3843 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3844 3845 unsigned VL = N->getValueType(0).getVectorNumElements(); 3846 unsigned VBits = N->getValueType(0).getSizeInBits(); 3847 unsigned ElSize = VBits / VL; 3848 bool Result = (Index * ElSize) % 128 == 0; 3849 3850 return Result; 3851} 3852 3853/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3854/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3855/// Handles 128-bit and 256-bit. 3856static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3857 EVT VT = N->getValueType(0); 3858 3859 assert((VT.is128BitVector() || VT.is256BitVector()) && 3860 "Unsupported vector type for PSHUF/SHUFP"); 3861 3862 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3863 // independently on 128-bit lanes. 3864 unsigned NumElts = VT.getVectorNumElements(); 3865 unsigned NumLanes = VT.getSizeInBits()/128; 3866 unsigned NumLaneElts = NumElts/NumLanes; 3867 3868 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3869 "Only supports 2 or 4 elements per lane"); 3870 3871 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3872 unsigned Mask = 0; 3873 for (unsigned i = 0; i != NumElts; ++i) { 3874 int Elt = N->getMaskElt(i); 3875 if (Elt < 0) continue; 3876 Elt %= NumLaneElts; 3877 unsigned ShAmt = i << Shift; 3878 if (ShAmt >= 8) ShAmt -= 8; 3879 Mask |= Elt << ShAmt; 3880 } 3881 3882 return Mask; 3883} 3884 3885/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3886/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3887static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3888 unsigned Mask = 0; 3889 // 8 nodes, but we only care about the last 4. 3890 for (unsigned i = 7; i >= 4; --i) { 3891 int Val = N->getMaskElt(i); 3892 if (Val >= 0) 3893 Mask |= (Val - 4); 3894 if (i != 4) 3895 Mask <<= 2; 3896 } 3897 return Mask; 3898} 3899 3900/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3901/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3902static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3903 unsigned Mask = 0; 3904 // 8 nodes, but we only care about the first 4. 3905 for (int i = 3; i >= 0; --i) { 3906 int Val = N->getMaskElt(i); 3907 if (Val >= 0) 3908 Mask |= Val; 3909 if (i != 0) 3910 Mask <<= 2; 3911 } 3912 return Mask; 3913} 3914 3915/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3916/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3917static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3918 EVT VT = SVOp->getValueType(0); 3919 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3920 3921 unsigned NumElts = VT.getVectorNumElements(); 3922 unsigned NumLanes = VT.getSizeInBits()/128; 3923 unsigned NumLaneElts = NumElts/NumLanes; 3924 3925 int Val = 0; 3926 unsigned i; 3927 for (i = 0; i != NumElts; ++i) { 3928 Val = SVOp->getMaskElt(i); 3929 if (Val >= 0) 3930 break; 3931 } 3932 if (Val >= (int)NumElts) 3933 Val -= NumElts - NumLaneElts; 3934 3935 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3936 return (Val - i) * EltSize; 3937} 3938 3939/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3940/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3941/// instructions. 3942unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3943 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3944 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3945 3946 uint64_t Index = 3947 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3948 3949 EVT VecVT = N->getOperand(0).getValueType(); 3950 EVT ElVT = VecVT.getVectorElementType(); 3951 3952 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3953 return Index / NumElemsPerChunk; 3954} 3955 3956/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3957/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3958/// instructions. 3959unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3960 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3961 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3962 3963 uint64_t Index = 3964 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3965 3966 EVT VecVT = N->getValueType(0); 3967 EVT ElVT = VecVT.getVectorElementType(); 3968 3969 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3970 return Index / NumElemsPerChunk; 3971} 3972 3973/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3974/// constant +0.0. 3975bool X86::isZeroNode(SDValue Elt) { 3976 return ((isa<ConstantSDNode>(Elt) && 3977 cast<ConstantSDNode>(Elt)->isNullValue()) || 3978 (isa<ConstantFPSDNode>(Elt) && 3979 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3980} 3981 3982/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3983/// their permute mask. 3984static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3985 SelectionDAG &DAG) { 3986 EVT VT = SVOp->getValueType(0); 3987 unsigned NumElems = VT.getVectorNumElements(); 3988 SmallVector<int, 8> MaskVec; 3989 3990 for (unsigned i = 0; i != NumElems; ++i) { 3991 int idx = SVOp->getMaskElt(i); 3992 if (idx < 0) 3993 MaskVec.push_back(idx); 3994 else if (idx < (int)NumElems) 3995 MaskVec.push_back(idx + NumElems); 3996 else 3997 MaskVec.push_back(idx - NumElems); 3998 } 3999 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4000 SVOp->getOperand(0), &MaskVec[0]); 4001} 4002 4003/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4004/// match movhlps. The lower half elements should come from upper half of 4005/// V1 (and in order), and the upper half elements should come from the upper 4006/// half of V2 (and in order). 4007static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4008 if (VT.getSizeInBits() != 128) 4009 return false; 4010 if (VT.getVectorNumElements() != 4) 4011 return false; 4012 for (unsigned i = 0, e = 2; i != e; ++i) 4013 if (!isUndefOrEqual(Mask[i], i+2)) 4014 return false; 4015 for (unsigned i = 2; i != 4; ++i) 4016 if (!isUndefOrEqual(Mask[i], i+4)) 4017 return false; 4018 return true; 4019} 4020 4021/// isScalarLoadToVector - Returns true if the node is a scalar load that 4022/// is promoted to a vector. It also returns the LoadSDNode by reference if 4023/// required. 4024static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4025 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4026 return false; 4027 N = N->getOperand(0).getNode(); 4028 if (!ISD::isNON_EXTLoad(N)) 4029 return false; 4030 if (LD) 4031 *LD = cast<LoadSDNode>(N); 4032 return true; 4033} 4034 4035// Test whether the given value is a vector value which will be legalized 4036// into a load. 4037static bool WillBeConstantPoolLoad(SDNode *N) { 4038 if (N->getOpcode() != ISD::BUILD_VECTOR) 4039 return false; 4040 4041 // Check for any non-constant elements. 4042 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4043 switch (N->getOperand(i).getNode()->getOpcode()) { 4044 case ISD::UNDEF: 4045 case ISD::ConstantFP: 4046 case ISD::Constant: 4047 break; 4048 default: 4049 return false; 4050 } 4051 4052 // Vectors of all-zeros and all-ones are materialized with special 4053 // instructions rather than being loaded. 4054 return !ISD::isBuildVectorAllZeros(N) && 4055 !ISD::isBuildVectorAllOnes(N); 4056} 4057 4058/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4059/// match movlp{s|d}. The lower half elements should come from lower half of 4060/// V1 (and in order), and the upper half elements should come from the upper 4061/// half of V2 (and in order). And since V1 will become the source of the 4062/// MOVLP, it must be either a vector load or a scalar load to vector. 4063static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4064 ArrayRef<int> Mask, EVT VT) { 4065 if (VT.getSizeInBits() != 128) 4066 return false; 4067 4068 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4069 return false; 4070 // Is V2 is a vector load, don't do this transformation. We will try to use 4071 // load folding shufps op. 4072 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4073 return false; 4074 4075 unsigned NumElems = VT.getVectorNumElements(); 4076 4077 if (NumElems != 2 && NumElems != 4) 4078 return false; 4079 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4080 if (!isUndefOrEqual(Mask[i], i)) 4081 return false; 4082 for (unsigned i = NumElems/2; i != NumElems; ++i) 4083 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4084 return false; 4085 return true; 4086} 4087 4088/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4089/// all the same. 4090static bool isSplatVector(SDNode *N) { 4091 if (N->getOpcode() != ISD::BUILD_VECTOR) 4092 return false; 4093 4094 SDValue SplatValue = N->getOperand(0); 4095 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4096 if (N->getOperand(i) != SplatValue) 4097 return false; 4098 return true; 4099} 4100 4101/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4102/// to an zero vector. 4103/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4104static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4105 SDValue V1 = N->getOperand(0); 4106 SDValue V2 = N->getOperand(1); 4107 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4108 for (unsigned i = 0; i != NumElems; ++i) { 4109 int Idx = N->getMaskElt(i); 4110 if (Idx >= (int)NumElems) { 4111 unsigned Opc = V2.getOpcode(); 4112 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4113 continue; 4114 if (Opc != ISD::BUILD_VECTOR || 4115 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4116 return false; 4117 } else if (Idx >= 0) { 4118 unsigned Opc = V1.getOpcode(); 4119 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4120 continue; 4121 if (Opc != ISD::BUILD_VECTOR || 4122 !X86::isZeroNode(V1.getOperand(Idx))) 4123 return false; 4124 } 4125 } 4126 return true; 4127} 4128 4129/// getZeroVector - Returns a vector of specified type with all zero elements. 4130/// 4131static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4132 SelectionDAG &DAG, DebugLoc dl) { 4133 assert(VT.isVector() && "Expected a vector type"); 4134 4135 // Always build SSE zero vectors as <4 x i32> bitcasted 4136 // to their dest type. This ensures they get CSE'd. 4137 SDValue Vec; 4138 if (VT.getSizeInBits() == 128) { // SSE 4139 if (Subtarget->hasSSE2()) { // SSE2 4140 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4141 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4142 } else { // SSE1 4143 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4144 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4145 } 4146 } else if (VT.getSizeInBits() == 256) { // AVX 4147 if (Subtarget->hasAVX2()) { // AVX2 4148 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4149 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4150 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4151 } else { 4152 // 256-bit logic and arithmetic instructions in AVX are all 4153 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4154 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4155 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4157 } 4158 } 4159 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4160} 4161 4162/// getOnesVector - Returns a vector of specified type with all bits set. 4163/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4164/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4165/// Then bitcast to their original type, ensuring they get CSE'd. 4166static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4167 DebugLoc dl) { 4168 assert(VT.isVector() && "Expected a vector type"); 4169 assert((VT.is128BitVector() || VT.is256BitVector()) 4170 && "Expected a 128-bit or 256-bit vector type"); 4171 4172 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4173 SDValue Vec; 4174 if (VT.getSizeInBits() == 256) { 4175 if (HasAVX2) { // AVX2 4176 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4177 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4178 } else { // AVX 4179 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4180 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4181 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4182 Vec = Insert128BitVector(InsV, Vec, 4183 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4184 } 4185 } else { 4186 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4187 } 4188 4189 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4190} 4191 4192/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4193/// that point to V2 points to its first element. 4194static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4195 for (unsigned i = 0; i != NumElems; ++i) { 4196 if (Mask[i] > (int)NumElems) { 4197 Mask[i] = NumElems; 4198 } 4199 } 4200} 4201 4202/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4203/// operation of specified width. 4204static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4205 SDValue V2) { 4206 unsigned NumElems = VT.getVectorNumElements(); 4207 SmallVector<int, 8> Mask; 4208 Mask.push_back(NumElems); 4209 for (unsigned i = 1; i != NumElems; ++i) 4210 Mask.push_back(i); 4211 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4212} 4213 4214/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4215static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4216 SDValue V2) { 4217 unsigned NumElems = VT.getVectorNumElements(); 4218 SmallVector<int, 8> Mask; 4219 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4220 Mask.push_back(i); 4221 Mask.push_back(i + NumElems); 4222 } 4223 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4224} 4225 4226/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4227static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4228 SDValue V2) { 4229 unsigned NumElems = VT.getVectorNumElements(); 4230 unsigned Half = NumElems/2; 4231 SmallVector<int, 8> Mask; 4232 for (unsigned i = 0; i != Half; ++i) { 4233 Mask.push_back(i + Half); 4234 Mask.push_back(i + NumElems + Half); 4235 } 4236 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4237} 4238 4239// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4240// a generic shuffle instruction because the target has no such instructions. 4241// Generate shuffles which repeat i16 and i8 several times until they can be 4242// represented by v4f32 and then be manipulated by target suported shuffles. 4243static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4244 EVT VT = V.getValueType(); 4245 int NumElems = VT.getVectorNumElements(); 4246 DebugLoc dl = V.getDebugLoc(); 4247 4248 while (NumElems > 4) { 4249 if (EltNo < NumElems/2) { 4250 V = getUnpackl(DAG, dl, VT, V, V); 4251 } else { 4252 V = getUnpackh(DAG, dl, VT, V, V); 4253 EltNo -= NumElems/2; 4254 } 4255 NumElems >>= 1; 4256 } 4257 return V; 4258} 4259 4260/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4261static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4262 EVT VT = V.getValueType(); 4263 DebugLoc dl = V.getDebugLoc(); 4264 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4265 && "Vector size not supported"); 4266 4267 if (VT.getSizeInBits() == 128) { 4268 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4269 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4270 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4271 &SplatMask[0]); 4272 } else { 4273 // To use VPERMILPS to splat scalars, the second half of indicies must 4274 // refer to the higher part, which is a duplication of the lower one, 4275 // because VPERMILPS can only handle in-lane permutations. 4276 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4277 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4278 4279 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4280 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4281 &SplatMask[0]); 4282 } 4283 4284 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4285} 4286 4287/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4288static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4289 EVT SrcVT = SV->getValueType(0); 4290 SDValue V1 = SV->getOperand(0); 4291 DebugLoc dl = SV->getDebugLoc(); 4292 4293 int EltNo = SV->getSplatIndex(); 4294 int NumElems = SrcVT.getVectorNumElements(); 4295 unsigned Size = SrcVT.getSizeInBits(); 4296 4297 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4298 "Unknown how to promote splat for type"); 4299 4300 // Extract the 128-bit part containing the splat element and update 4301 // the splat element index when it refers to the higher register. 4302 if (Size == 256) { 4303 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4304 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4305 if (Idx > 0) 4306 EltNo -= NumElems/2; 4307 } 4308 4309 // All i16 and i8 vector types can't be used directly by a generic shuffle 4310 // instruction because the target has no such instruction. Generate shuffles 4311 // which repeat i16 and i8 several times until they fit in i32, and then can 4312 // be manipulated by target suported shuffles. 4313 EVT EltVT = SrcVT.getVectorElementType(); 4314 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4315 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4316 4317 // Recreate the 256-bit vector and place the same 128-bit vector 4318 // into the low and high part. This is necessary because we want 4319 // to use VPERM* to shuffle the vectors 4320 if (Size == 256) { 4321 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4322 DAG.getConstant(0, MVT::i32), DAG, dl); 4323 V1 = Insert128BitVector(InsV, V1, 4324 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4325 } 4326 4327 return getLegalSplat(DAG, V1, EltNo); 4328} 4329 4330/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4331/// vector of zero or undef vector. This produces a shuffle where the low 4332/// element of V2 is swizzled into the zero/undef vector, landing at element 4333/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4334static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4335 bool IsZero, 4336 const X86Subtarget *Subtarget, 4337 SelectionDAG &DAG) { 4338 EVT VT = V2.getValueType(); 4339 SDValue V1 = IsZero 4340 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4341 unsigned NumElems = VT.getVectorNumElements(); 4342 SmallVector<int, 16> MaskVec; 4343 for (unsigned i = 0; i != NumElems; ++i) 4344 // If this is the insertion idx, put the low elt of V2 here. 4345 MaskVec.push_back(i == Idx ? NumElems : i); 4346 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4347} 4348 4349/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4350/// target specific opcode. Returns true if the Mask could be calculated. 4351/// Sets IsUnary to true if only uses one source. 4352static bool getTargetShuffleMask(SDNode *N, EVT VT, 4353 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4354 unsigned NumElems = VT.getVectorNumElements(); 4355 SDValue ImmN; 4356 4357 IsUnary = false; 4358 switch(N->getOpcode()) { 4359 case X86ISD::SHUFP: 4360 ImmN = N->getOperand(N->getNumOperands()-1); 4361 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4362 break; 4363 case X86ISD::UNPCKH: 4364 DecodeUNPCKHMask(VT, Mask); 4365 break; 4366 case X86ISD::UNPCKL: 4367 DecodeUNPCKLMask(VT, Mask); 4368 break; 4369 case X86ISD::MOVHLPS: 4370 DecodeMOVHLPSMask(NumElems, Mask); 4371 break; 4372 case X86ISD::MOVLHPS: 4373 DecodeMOVLHPSMask(NumElems, Mask); 4374 break; 4375 case X86ISD::PSHUFD: 4376 case X86ISD::VPERMILP: 4377 ImmN = N->getOperand(N->getNumOperands()-1); 4378 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4379 IsUnary = true; 4380 break; 4381 case X86ISD::PSHUFHW: 4382 ImmN = N->getOperand(N->getNumOperands()-1); 4383 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4384 IsUnary = true; 4385 break; 4386 case X86ISD::PSHUFLW: 4387 ImmN = N->getOperand(N->getNumOperands()-1); 4388 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4389 IsUnary = true; 4390 break; 4391 case X86ISD::MOVSS: 4392 case X86ISD::MOVSD: { 4393 // The index 0 always comes from the first element of the second source, 4394 // this is why MOVSS and MOVSD are used in the first place. The other 4395 // elements come from the other positions of the first source vector 4396 Mask.push_back(NumElems); 4397 for (unsigned i = 1; i != NumElems; ++i) { 4398 Mask.push_back(i); 4399 } 4400 break; 4401 } 4402 case X86ISD::VPERM2X128: 4403 ImmN = N->getOperand(N->getNumOperands()-1); 4404 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4405 break; 4406 case X86ISD::MOVDDUP: 4407 case X86ISD::MOVLHPD: 4408 case X86ISD::MOVLPD: 4409 case X86ISD::MOVLPS: 4410 case X86ISD::MOVSHDUP: 4411 case X86ISD::MOVSLDUP: 4412 case X86ISD::PALIGN: 4413 // Not yet implemented 4414 return false; 4415 default: llvm_unreachable("unknown target shuffle node"); 4416 } 4417 4418 return true; 4419} 4420 4421/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4422/// element of the result of the vector shuffle. 4423static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4424 unsigned Depth) { 4425 if (Depth == 6) 4426 return SDValue(); // Limit search depth. 4427 4428 SDValue V = SDValue(N, 0); 4429 EVT VT = V.getValueType(); 4430 unsigned Opcode = V.getOpcode(); 4431 4432 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4433 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4434 int Elt = SV->getMaskElt(Index); 4435 4436 if (Elt < 0) 4437 return DAG.getUNDEF(VT.getVectorElementType()); 4438 4439 unsigned NumElems = VT.getVectorNumElements(); 4440 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4441 : SV->getOperand(1); 4442 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4443 } 4444 4445 // Recurse into target specific vector shuffles to find scalars. 4446 if (isTargetShuffle(Opcode)) { 4447 unsigned NumElems = VT.getVectorNumElements(); 4448 SmallVector<int, 16> ShuffleMask; 4449 SDValue ImmN; 4450 bool IsUnary; 4451 4452 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary)) 4453 return SDValue(); 4454 4455 int Elt = ShuffleMask[Index]; 4456 if (Elt < 0) 4457 return DAG.getUNDEF(VT.getVectorElementType()); 4458 4459 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4460 : N->getOperand(1); 4461 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4462 Depth+1); 4463 } 4464 4465 // Actual nodes that may contain scalar elements 4466 if (Opcode == ISD::BITCAST) { 4467 V = V.getOperand(0); 4468 EVT SrcVT = V.getValueType(); 4469 unsigned NumElems = VT.getVectorNumElements(); 4470 4471 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4472 return SDValue(); 4473 } 4474 4475 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4476 return (Index == 0) ? V.getOperand(0) 4477 : DAG.getUNDEF(VT.getVectorElementType()); 4478 4479 if (V.getOpcode() == ISD::BUILD_VECTOR) 4480 return V.getOperand(Index); 4481 4482 return SDValue(); 4483} 4484 4485/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4486/// shuffle operation which come from a consecutively from a zero. The 4487/// search can start in two different directions, from left or right. 4488static 4489unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4490 bool ZerosFromLeft, SelectionDAG &DAG) { 4491 unsigned i; 4492 for (i = 0; i != NumElems; ++i) { 4493 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4494 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4495 if (!(Elt.getNode() && 4496 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4497 break; 4498 } 4499 4500 return i; 4501} 4502 4503/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4504/// correspond consecutively to elements from one of the vector operands, 4505/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4506static 4507bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4508 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4509 unsigned NumElems, unsigned &OpNum) { 4510 bool SeenV1 = false; 4511 bool SeenV2 = false; 4512 4513 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4514 int Idx = SVOp->getMaskElt(i); 4515 // Ignore undef indicies 4516 if (Idx < 0) 4517 continue; 4518 4519 if (Idx < (int)NumElems) 4520 SeenV1 = true; 4521 else 4522 SeenV2 = true; 4523 4524 // Only accept consecutive elements from the same vector 4525 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4526 return false; 4527 } 4528 4529 OpNum = SeenV1 ? 0 : 1; 4530 return true; 4531} 4532 4533/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4534/// logical left shift of a vector. 4535static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4536 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4537 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4538 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4539 false /* check zeros from right */, DAG); 4540 unsigned OpSrc; 4541 4542 if (!NumZeros) 4543 return false; 4544 4545 // Considering the elements in the mask that are not consecutive zeros, 4546 // check if they consecutively come from only one of the source vectors. 4547 // 4548 // V1 = {X, A, B, C} 0 4549 // \ \ \ / 4550 // vector_shuffle V1, V2 <1, 2, 3, X> 4551 // 4552 if (!isShuffleMaskConsecutive(SVOp, 4553 0, // Mask Start Index 4554 NumElems-NumZeros, // Mask End Index(exclusive) 4555 NumZeros, // Where to start looking in the src vector 4556 NumElems, // Number of elements in vector 4557 OpSrc)) // Which source operand ? 4558 return false; 4559 4560 isLeft = false; 4561 ShAmt = NumZeros; 4562 ShVal = SVOp->getOperand(OpSrc); 4563 return true; 4564} 4565 4566/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4567/// logical left shift of a vector. 4568static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4569 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4570 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4571 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4572 true /* check zeros from left */, DAG); 4573 unsigned OpSrc; 4574 4575 if (!NumZeros) 4576 return false; 4577 4578 // Considering the elements in the mask that are not consecutive zeros, 4579 // check if they consecutively come from only one of the source vectors. 4580 // 4581 // 0 { A, B, X, X } = V2 4582 // / \ / / 4583 // vector_shuffle V1, V2 <X, X, 4, 5> 4584 // 4585 if (!isShuffleMaskConsecutive(SVOp, 4586 NumZeros, // Mask Start Index 4587 NumElems, // Mask End Index(exclusive) 4588 0, // Where to start looking in the src vector 4589 NumElems, // Number of elements in vector 4590 OpSrc)) // Which source operand ? 4591 return false; 4592 4593 isLeft = true; 4594 ShAmt = NumZeros; 4595 ShVal = SVOp->getOperand(OpSrc); 4596 return true; 4597} 4598 4599/// isVectorShift - Returns true if the shuffle can be implemented as a 4600/// logical left or right shift of a vector. 4601static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4602 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4603 // Although the logic below support any bitwidth size, there are no 4604 // shift instructions which handle more than 128-bit vectors. 4605 if (SVOp->getValueType(0).getSizeInBits() > 128) 4606 return false; 4607 4608 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4609 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4610 return true; 4611 4612 return false; 4613} 4614 4615/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4616/// 4617static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4618 unsigned NumNonZero, unsigned NumZero, 4619 SelectionDAG &DAG, 4620 const X86Subtarget* Subtarget, 4621 const TargetLowering &TLI) { 4622 if (NumNonZero > 8) 4623 return SDValue(); 4624 4625 DebugLoc dl = Op.getDebugLoc(); 4626 SDValue V(0, 0); 4627 bool First = true; 4628 for (unsigned i = 0; i < 16; ++i) { 4629 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4630 if (ThisIsNonZero && First) { 4631 if (NumZero) 4632 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4633 else 4634 V = DAG.getUNDEF(MVT::v8i16); 4635 First = false; 4636 } 4637 4638 if ((i & 1) != 0) { 4639 SDValue ThisElt(0, 0), LastElt(0, 0); 4640 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4641 if (LastIsNonZero) { 4642 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4643 MVT::i16, Op.getOperand(i-1)); 4644 } 4645 if (ThisIsNonZero) { 4646 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4647 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4648 ThisElt, DAG.getConstant(8, MVT::i8)); 4649 if (LastIsNonZero) 4650 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4651 } else 4652 ThisElt = LastElt; 4653 4654 if (ThisElt.getNode()) 4655 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4656 DAG.getIntPtrConstant(i/2)); 4657 } 4658 } 4659 4660 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4661} 4662 4663/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4664/// 4665static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4666 unsigned NumNonZero, unsigned NumZero, 4667 SelectionDAG &DAG, 4668 const X86Subtarget* Subtarget, 4669 const TargetLowering &TLI) { 4670 if (NumNonZero > 4) 4671 return SDValue(); 4672 4673 DebugLoc dl = Op.getDebugLoc(); 4674 SDValue V(0, 0); 4675 bool First = true; 4676 for (unsigned i = 0; i < 8; ++i) { 4677 bool isNonZero = (NonZeros & (1 << i)) != 0; 4678 if (isNonZero) { 4679 if (First) { 4680 if (NumZero) 4681 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4682 else 4683 V = DAG.getUNDEF(MVT::v8i16); 4684 First = false; 4685 } 4686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4687 MVT::v8i16, V, Op.getOperand(i), 4688 DAG.getIntPtrConstant(i)); 4689 } 4690 } 4691 4692 return V; 4693} 4694 4695/// getVShift - Return a vector logical shift node. 4696/// 4697static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4698 unsigned NumBits, SelectionDAG &DAG, 4699 const TargetLowering &TLI, DebugLoc dl) { 4700 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4701 EVT ShVT = MVT::v2i64; 4702 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4703 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4704 return DAG.getNode(ISD::BITCAST, dl, VT, 4705 DAG.getNode(Opc, dl, ShVT, SrcOp, 4706 DAG.getConstant(NumBits, 4707 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4708} 4709 4710SDValue 4711X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4712 SelectionDAG &DAG) const { 4713 4714 // Check if the scalar load can be widened into a vector load. And if 4715 // the address is "base + cst" see if the cst can be "absorbed" into 4716 // the shuffle mask. 4717 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4718 SDValue Ptr = LD->getBasePtr(); 4719 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4720 return SDValue(); 4721 EVT PVT = LD->getValueType(0); 4722 if (PVT != MVT::i32 && PVT != MVT::f32) 4723 return SDValue(); 4724 4725 int FI = -1; 4726 int64_t Offset = 0; 4727 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4728 FI = FINode->getIndex(); 4729 Offset = 0; 4730 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4731 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4732 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4733 Offset = Ptr.getConstantOperandVal(1); 4734 Ptr = Ptr.getOperand(0); 4735 } else { 4736 return SDValue(); 4737 } 4738 4739 // FIXME: 256-bit vector instructions don't require a strict alignment, 4740 // improve this code to support it better. 4741 unsigned RequiredAlign = VT.getSizeInBits()/8; 4742 SDValue Chain = LD->getChain(); 4743 // Make sure the stack object alignment is at least 16 or 32. 4744 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4745 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4746 if (MFI->isFixedObjectIndex(FI)) { 4747 // Can't change the alignment. FIXME: It's possible to compute 4748 // the exact stack offset and reference FI + adjust offset instead. 4749 // If someone *really* cares about this. That's the way to implement it. 4750 return SDValue(); 4751 } else { 4752 MFI->setObjectAlignment(FI, RequiredAlign); 4753 } 4754 } 4755 4756 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4757 // Ptr + (Offset & ~15). 4758 if (Offset < 0) 4759 return SDValue(); 4760 if ((Offset % RequiredAlign) & 3) 4761 return SDValue(); 4762 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4763 if (StartOffset) 4764 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4765 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4766 4767 int EltNo = (Offset - StartOffset) >> 2; 4768 int NumElems = VT.getVectorNumElements(); 4769 4770 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4771 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4772 LD->getPointerInfo().getWithOffset(StartOffset), 4773 false, false, false, 0); 4774 4775 SmallVector<int, 8> Mask; 4776 for (int i = 0; i < NumElems; ++i) 4777 Mask.push_back(EltNo); 4778 4779 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4780 } 4781 4782 return SDValue(); 4783} 4784 4785/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4786/// vector of type 'VT', see if the elements can be replaced by a single large 4787/// load which has the same value as a build_vector whose operands are 'elts'. 4788/// 4789/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4790/// 4791/// FIXME: we'd also like to handle the case where the last elements are zero 4792/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4793/// There's even a handy isZeroNode for that purpose. 4794static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4795 DebugLoc &DL, SelectionDAG &DAG) { 4796 EVT EltVT = VT.getVectorElementType(); 4797 unsigned NumElems = Elts.size(); 4798 4799 LoadSDNode *LDBase = NULL; 4800 unsigned LastLoadedElt = -1U; 4801 4802 // For each element in the initializer, see if we've found a load or an undef. 4803 // If we don't find an initial load element, or later load elements are 4804 // non-consecutive, bail out. 4805 for (unsigned i = 0; i < NumElems; ++i) { 4806 SDValue Elt = Elts[i]; 4807 4808 if (!Elt.getNode() || 4809 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4810 return SDValue(); 4811 if (!LDBase) { 4812 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4813 return SDValue(); 4814 LDBase = cast<LoadSDNode>(Elt.getNode()); 4815 LastLoadedElt = i; 4816 continue; 4817 } 4818 if (Elt.getOpcode() == ISD::UNDEF) 4819 continue; 4820 4821 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4822 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4823 return SDValue(); 4824 LastLoadedElt = i; 4825 } 4826 4827 // If we have found an entire vector of loads and undefs, then return a large 4828 // load of the entire vector width starting at the base pointer. If we found 4829 // consecutive loads for the low half, generate a vzext_load node. 4830 if (LastLoadedElt == NumElems - 1) { 4831 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4832 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4833 LDBase->getPointerInfo(), 4834 LDBase->isVolatile(), LDBase->isNonTemporal(), 4835 LDBase->isInvariant(), 0); 4836 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4837 LDBase->getPointerInfo(), 4838 LDBase->isVolatile(), LDBase->isNonTemporal(), 4839 LDBase->isInvariant(), LDBase->getAlignment()); 4840 } else if (NumElems == 4 && LastLoadedElt == 1 && 4841 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4842 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4843 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4844 SDValue ResNode = 4845 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4846 LDBase->getPointerInfo(), 4847 LDBase->getAlignment(), 4848 false/*isVolatile*/, true/*ReadMem*/, 4849 false/*WriteMem*/); 4850 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4851 } 4852 return SDValue(); 4853} 4854 4855/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4856/// a vbroadcast node. We support two patterns: 4857/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4858/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4859/// a scalar load. 4860/// The scalar load node is returned when a pattern is found, 4861/// or SDValue() otherwise. 4862static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) { 4863 if (!Subtarget->hasAVX()) 4864 return SDValue(); 4865 4866 EVT VT = Op.getValueType(); 4867 SDValue V = Op; 4868 4869 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4870 V = V.getOperand(0); 4871 4872 //A suspected load to be broadcasted. 4873 SDValue Ld; 4874 4875 switch (V.getOpcode()) { 4876 default: 4877 // Unknown pattern found. 4878 return SDValue(); 4879 4880 case ISD::BUILD_VECTOR: { 4881 // The BUILD_VECTOR node must be a splat. 4882 if (!isSplatVector(V.getNode())) 4883 return SDValue(); 4884 4885 Ld = V.getOperand(0); 4886 4887 // The suspected load node has several users. Make sure that all 4888 // of its users are from the BUILD_VECTOR node. 4889 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4890 return SDValue(); 4891 break; 4892 } 4893 4894 case ISD::VECTOR_SHUFFLE: { 4895 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4896 4897 // Shuffles must have a splat mask where the first element is 4898 // broadcasted. 4899 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4900 return SDValue(); 4901 4902 SDValue Sc = Op.getOperand(0); 4903 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4904 return SDValue(); 4905 4906 Ld = Sc.getOperand(0); 4907 4908 // The scalar_to_vector node and the suspected 4909 // load node must have exactly one user. 4910 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 4911 return SDValue(); 4912 break; 4913 } 4914 } 4915 4916 // The scalar source must be a normal load. 4917 if (!ISD::isNormalLoad(Ld.getNode())) 4918 return SDValue(); 4919 4920 // Reject loads that have uses of the chain result 4921 if (Ld->hasAnyUseOfValue(1)) 4922 return SDValue(); 4923 4924 bool Is256 = VT.getSizeInBits() == 256; 4925 bool Is128 = VT.getSizeInBits() == 128; 4926 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4927 4928 // VBroadcast to YMM 4929 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4930 return Ld; 4931 4932 // VBroadcast to XMM 4933 if (Is128 && (ScalarSize == 32)) 4934 return Ld; 4935 4936 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 4937 // double since there is vbroadcastsd xmm 4938 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 4939 // VBroadcast to YMM 4940 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 4941 return Ld; 4942 4943 // VBroadcast to XMM 4944 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 4945 return Ld; 4946 } 4947 4948 // Unsupported broadcast. 4949 return SDValue(); 4950} 4951 4952SDValue 4953X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4954 DebugLoc dl = Op.getDebugLoc(); 4955 4956 EVT VT = Op.getValueType(); 4957 EVT ExtVT = VT.getVectorElementType(); 4958 unsigned NumElems = Op.getNumOperands(); 4959 4960 // Vectors containing all zeros can be matched by pxor and xorps later 4961 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 4962 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 4963 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 4964 if (VT == MVT::v4i32 || VT == MVT::v8i32) 4965 return Op; 4966 4967 return getZeroVector(VT, Subtarget, DAG, dl); 4968 } 4969 4970 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 4971 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 4972 // vpcmpeqd on 256-bit vectors. 4973 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 4974 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 4975 return Op; 4976 4977 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 4978 } 4979 4980 SDValue LD = isVectorBroadcast(Op, Subtarget); 4981 if (LD.getNode()) 4982 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 4983 4984 unsigned EVTBits = ExtVT.getSizeInBits(); 4985 4986 unsigned NumZero = 0; 4987 unsigned NumNonZero = 0; 4988 unsigned NonZeros = 0; 4989 bool IsAllConstants = true; 4990 SmallSet<SDValue, 8> Values; 4991 for (unsigned i = 0; i < NumElems; ++i) { 4992 SDValue Elt = Op.getOperand(i); 4993 if (Elt.getOpcode() == ISD::UNDEF) 4994 continue; 4995 Values.insert(Elt); 4996 if (Elt.getOpcode() != ISD::Constant && 4997 Elt.getOpcode() != ISD::ConstantFP) 4998 IsAllConstants = false; 4999 if (X86::isZeroNode(Elt)) 5000 NumZero++; 5001 else { 5002 NonZeros |= (1 << i); 5003 NumNonZero++; 5004 } 5005 } 5006 5007 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5008 if (NumNonZero == 0) 5009 return DAG.getUNDEF(VT); 5010 5011 // Special case for single non-zero, non-undef, element. 5012 if (NumNonZero == 1) { 5013 unsigned Idx = CountTrailingZeros_32(NonZeros); 5014 SDValue Item = Op.getOperand(Idx); 5015 5016 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5017 // the value are obviously zero, truncate the value to i32 and do the 5018 // insertion that way. Only do this if the value is non-constant or if the 5019 // value is a constant being inserted into element 0. It is cheaper to do 5020 // a constant pool load than it is to do a movd + shuffle. 5021 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5022 (!IsAllConstants || Idx == 0)) { 5023 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5024 // Handle SSE only. 5025 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5026 EVT VecVT = MVT::v4i32; 5027 unsigned VecElts = 4; 5028 5029 // Truncate the value (which may itself be a constant) to i32, and 5030 // convert it to a vector with movd (S2V+shuffle to zero extend). 5031 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5032 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5033 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5034 5035 // Now we have our 32-bit value zero extended in the low element of 5036 // a vector. If Idx != 0, swizzle it into place. 5037 if (Idx != 0) { 5038 SmallVector<int, 4> Mask; 5039 Mask.push_back(Idx); 5040 for (unsigned i = 1; i != VecElts; ++i) 5041 Mask.push_back(i); 5042 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5043 DAG.getUNDEF(Item.getValueType()), 5044 &Mask[0]); 5045 } 5046 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5047 } 5048 } 5049 5050 // If we have a constant or non-constant insertion into the low element of 5051 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5052 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5053 // depending on what the source datatype is. 5054 if (Idx == 0) { 5055 if (NumZero == 0) 5056 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5057 5058 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5059 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5060 if (VT.getSizeInBits() == 256) { 5061 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5062 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5063 Item, DAG.getIntPtrConstant(0)); 5064 } 5065 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5066 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5067 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5068 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5069 } 5070 5071 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5072 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5073 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5074 if (VT.getSizeInBits() == 256) { 5075 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5076 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5077 DAG, dl); 5078 } else { 5079 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5080 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5081 } 5082 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5083 } 5084 } 5085 5086 // Is it a vector logical left shift? 5087 if (NumElems == 2 && Idx == 1 && 5088 X86::isZeroNode(Op.getOperand(0)) && 5089 !X86::isZeroNode(Op.getOperand(1))) { 5090 unsigned NumBits = VT.getSizeInBits(); 5091 return getVShift(true, VT, 5092 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5093 VT, Op.getOperand(1)), 5094 NumBits/2, DAG, *this, dl); 5095 } 5096 5097 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5098 return SDValue(); 5099 5100 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5101 // is a non-constant being inserted into an element other than the low one, 5102 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5103 // movd/movss) to move this into the low element, then shuffle it into 5104 // place. 5105 if (EVTBits == 32) { 5106 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5107 5108 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5109 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5110 SmallVector<int, 8> MaskVec; 5111 for (unsigned i = 0; i < NumElems; i++) 5112 MaskVec.push_back(i == Idx ? 0 : 1); 5113 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5114 } 5115 } 5116 5117 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5118 if (Values.size() == 1) { 5119 if (EVTBits == 32) { 5120 // Instead of a shuffle like this: 5121 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5122 // Check if it's possible to issue this instead. 5123 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5124 unsigned Idx = CountTrailingZeros_32(NonZeros); 5125 SDValue Item = Op.getOperand(Idx); 5126 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5127 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5128 } 5129 return SDValue(); 5130 } 5131 5132 // A vector full of immediates; various special cases are already 5133 // handled, so this is best done with a single constant-pool load. 5134 if (IsAllConstants) 5135 return SDValue(); 5136 5137 // For AVX-length vectors, build the individual 128-bit pieces and use 5138 // shuffles to put them in place. 5139 if (VT.getSizeInBits() == 256) { 5140 SmallVector<SDValue, 32> V; 5141 for (unsigned i = 0; i != NumElems; ++i) 5142 V.push_back(Op.getOperand(i)); 5143 5144 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5145 5146 // Build both the lower and upper subvector. 5147 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5148 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5149 NumElems/2); 5150 5151 // Recreate the wider vector with the lower and upper part. 5152 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5153 DAG.getConstant(0, MVT::i32), DAG, dl); 5154 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5155 DAG, dl); 5156 } 5157 5158 // Let legalizer expand 2-wide build_vectors. 5159 if (EVTBits == 64) { 5160 if (NumNonZero == 1) { 5161 // One half is zero or undef. 5162 unsigned Idx = CountTrailingZeros_32(NonZeros); 5163 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5164 Op.getOperand(Idx)); 5165 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5166 } 5167 return SDValue(); 5168 } 5169 5170 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5171 if (EVTBits == 8 && NumElems == 16) { 5172 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5173 Subtarget, *this); 5174 if (V.getNode()) return V; 5175 } 5176 5177 if (EVTBits == 16 && NumElems == 8) { 5178 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5179 Subtarget, *this); 5180 if (V.getNode()) return V; 5181 } 5182 5183 // If element VT is == 32 bits, turn it into a number of shuffles. 5184 SmallVector<SDValue, 8> V(NumElems); 5185 if (NumElems == 4 && NumZero > 0) { 5186 for (unsigned i = 0; i < 4; ++i) { 5187 bool isZero = !(NonZeros & (1 << i)); 5188 if (isZero) 5189 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5190 else 5191 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5192 } 5193 5194 for (unsigned i = 0; i < 2; ++i) { 5195 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5196 default: break; 5197 case 0: 5198 V[i] = V[i*2]; // Must be a zero vector. 5199 break; 5200 case 1: 5201 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5202 break; 5203 case 2: 5204 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5205 break; 5206 case 3: 5207 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5208 break; 5209 } 5210 } 5211 5212 bool Reverse1 = (NonZeros & 0x3) == 2; 5213 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5214 int MaskVec[] = { 5215 Reverse1 ? 1 : 0, 5216 Reverse1 ? 0 : 1, 5217 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5218 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5219 }; 5220 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5221 } 5222 5223 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5224 // Check for a build vector of consecutive loads. 5225 for (unsigned i = 0; i < NumElems; ++i) 5226 V[i] = Op.getOperand(i); 5227 5228 // Check for elements which are consecutive loads. 5229 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5230 if (LD.getNode()) 5231 return LD; 5232 5233 // For SSE 4.1, use insertps to put the high elements into the low element. 5234 if (getSubtarget()->hasSSE41()) { 5235 SDValue Result; 5236 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5237 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5238 else 5239 Result = DAG.getUNDEF(VT); 5240 5241 for (unsigned i = 1; i < NumElems; ++i) { 5242 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5243 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5244 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5245 } 5246 return Result; 5247 } 5248 5249 // Otherwise, expand into a number of unpckl*, start by extending each of 5250 // our (non-undef) elements to the full vector width with the element in the 5251 // bottom slot of the vector (which generates no code for SSE). 5252 for (unsigned i = 0; i < NumElems; ++i) { 5253 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5254 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5255 else 5256 V[i] = DAG.getUNDEF(VT); 5257 } 5258 5259 // Next, we iteratively mix elements, e.g. for v4f32: 5260 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5261 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5262 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5263 unsigned EltStride = NumElems >> 1; 5264 while (EltStride != 0) { 5265 for (unsigned i = 0; i < EltStride; ++i) { 5266 // If V[i+EltStride] is undef and this is the first round of mixing, 5267 // then it is safe to just drop this shuffle: V[i] is already in the 5268 // right place, the one element (since it's the first round) being 5269 // inserted as undef can be dropped. This isn't safe for successive 5270 // rounds because they will permute elements within both vectors. 5271 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5272 EltStride == NumElems/2) 5273 continue; 5274 5275 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5276 } 5277 EltStride >>= 1; 5278 } 5279 return V[0]; 5280 } 5281 return SDValue(); 5282} 5283 5284// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5285// them in a MMX register. This is better than doing a stack convert. 5286static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5287 DebugLoc dl = Op.getDebugLoc(); 5288 EVT ResVT = Op.getValueType(); 5289 5290 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5291 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5292 int Mask[2]; 5293 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5294 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5295 InVec = Op.getOperand(1); 5296 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5297 unsigned NumElts = ResVT.getVectorNumElements(); 5298 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5299 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5300 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5301 } else { 5302 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5303 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5304 Mask[0] = 0; Mask[1] = 2; 5305 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5306 } 5307 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5308} 5309 5310// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5311// to create 256-bit vectors from two other 128-bit ones. 5312static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5313 DebugLoc dl = Op.getDebugLoc(); 5314 EVT ResVT = Op.getValueType(); 5315 5316 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5317 5318 SDValue V1 = Op.getOperand(0); 5319 SDValue V2 = Op.getOperand(1); 5320 unsigned NumElems = ResVT.getVectorNumElements(); 5321 5322 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5323 DAG.getConstant(0, MVT::i32), DAG, dl); 5324 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5325 DAG, dl); 5326} 5327 5328SDValue 5329X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5330 EVT ResVT = Op.getValueType(); 5331 5332 assert(Op.getNumOperands() == 2); 5333 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5334 "Unsupported CONCAT_VECTORS for value type"); 5335 5336 // We support concatenate two MMX registers and place them in a MMX register. 5337 // This is better than doing a stack convert. 5338 if (ResVT.is128BitVector()) 5339 return LowerMMXCONCAT_VECTORS(Op, DAG); 5340 5341 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5342 // from two other 128-bit ones. 5343 return LowerAVXCONCAT_VECTORS(Op, DAG); 5344} 5345 5346// v8i16 shuffles - Prefer shuffles in the following order: 5347// 1. [all] pshuflw, pshufhw, optional move 5348// 2. [ssse3] 1 x pshufb 5349// 3. [ssse3] 2 x pshufb + 1 x por 5350// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5351SDValue 5352X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5353 SelectionDAG &DAG) const { 5354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5355 SDValue V1 = SVOp->getOperand(0); 5356 SDValue V2 = SVOp->getOperand(1); 5357 DebugLoc dl = SVOp->getDebugLoc(); 5358 SmallVector<int, 8> MaskVals; 5359 5360 // Determine if more than 1 of the words in each of the low and high quadwords 5361 // of the result come from the same quadword of one of the two inputs. Undef 5362 // mask values count as coming from any quadword, for better codegen. 5363 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5364 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5365 std::bitset<4> InputQuads; 5366 for (unsigned i = 0; i < 8; ++i) { 5367 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5368 int EltIdx = SVOp->getMaskElt(i); 5369 MaskVals.push_back(EltIdx); 5370 if (EltIdx < 0) { 5371 ++Quad[0]; 5372 ++Quad[1]; 5373 ++Quad[2]; 5374 ++Quad[3]; 5375 continue; 5376 } 5377 ++Quad[EltIdx / 4]; 5378 InputQuads.set(EltIdx / 4); 5379 } 5380 5381 int BestLoQuad = -1; 5382 unsigned MaxQuad = 1; 5383 for (unsigned i = 0; i < 4; ++i) { 5384 if (LoQuad[i] > MaxQuad) { 5385 BestLoQuad = i; 5386 MaxQuad = LoQuad[i]; 5387 } 5388 } 5389 5390 int BestHiQuad = -1; 5391 MaxQuad = 1; 5392 for (unsigned i = 0; i < 4; ++i) { 5393 if (HiQuad[i] > MaxQuad) { 5394 BestHiQuad = i; 5395 MaxQuad = HiQuad[i]; 5396 } 5397 } 5398 5399 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5400 // of the two input vectors, shuffle them into one input vector so only a 5401 // single pshufb instruction is necessary. If There are more than 2 input 5402 // quads, disable the next transformation since it does not help SSSE3. 5403 bool V1Used = InputQuads[0] || InputQuads[1]; 5404 bool V2Used = InputQuads[2] || InputQuads[3]; 5405 if (Subtarget->hasSSSE3()) { 5406 if (InputQuads.count() == 2 && V1Used && V2Used) { 5407 BestLoQuad = InputQuads[0] ? 0 : 1; 5408 BestHiQuad = InputQuads[2] ? 2 : 3; 5409 } 5410 if (InputQuads.count() > 2) { 5411 BestLoQuad = -1; 5412 BestHiQuad = -1; 5413 } 5414 } 5415 5416 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5417 // the shuffle mask. If a quad is scored as -1, that means that it contains 5418 // words from all 4 input quadwords. 5419 SDValue NewV; 5420 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5421 int MaskV[] = { 5422 BestLoQuad < 0 ? 0 : BestLoQuad, 5423 BestHiQuad < 0 ? 1 : BestHiQuad 5424 }; 5425 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5426 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5427 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5428 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5429 5430 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5431 // source words for the shuffle, to aid later transformations. 5432 bool AllWordsInNewV = true; 5433 bool InOrder[2] = { true, true }; 5434 for (unsigned i = 0; i != 8; ++i) { 5435 int idx = MaskVals[i]; 5436 if (idx != (int)i) 5437 InOrder[i/4] = false; 5438 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5439 continue; 5440 AllWordsInNewV = false; 5441 break; 5442 } 5443 5444 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5445 if (AllWordsInNewV) { 5446 for (int i = 0; i != 8; ++i) { 5447 int idx = MaskVals[i]; 5448 if (idx < 0) 5449 continue; 5450 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5451 if ((idx != i) && idx < 4) 5452 pshufhw = false; 5453 if ((idx != i) && idx > 3) 5454 pshuflw = false; 5455 } 5456 V1 = NewV; 5457 V2Used = false; 5458 BestLoQuad = 0; 5459 BestHiQuad = 1; 5460 } 5461 5462 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5463 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5464 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5465 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5466 unsigned TargetMask = 0; 5467 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5468 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5469 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5470 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5471 getShufflePSHUFLWImmediate(SVOp); 5472 V1 = NewV.getOperand(0); 5473 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5474 } 5475 } 5476 5477 // If we have SSSE3, and all words of the result are from 1 input vector, 5478 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5479 // is present, fall back to case 4. 5480 if (Subtarget->hasSSSE3()) { 5481 SmallVector<SDValue,16> pshufbMask; 5482 5483 // If we have elements from both input vectors, set the high bit of the 5484 // shuffle mask element to zero out elements that come from V2 in the V1 5485 // mask, and elements that come from V1 in the V2 mask, so that the two 5486 // results can be OR'd together. 5487 bool TwoInputs = V1Used && V2Used; 5488 for (unsigned i = 0; i != 8; ++i) { 5489 int EltIdx = MaskVals[i] * 2; 5490 if (TwoInputs && (EltIdx >= 16)) { 5491 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5492 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5493 continue; 5494 } 5495 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5496 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5497 } 5498 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5499 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5500 DAG.getNode(ISD::BUILD_VECTOR, dl, 5501 MVT::v16i8, &pshufbMask[0], 16)); 5502 if (!TwoInputs) 5503 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5504 5505 // Calculate the shuffle mask for the second input, shuffle it, and 5506 // OR it with the first shuffled input. 5507 pshufbMask.clear(); 5508 for (unsigned i = 0; i != 8; ++i) { 5509 int EltIdx = MaskVals[i] * 2; 5510 if (EltIdx < 16) { 5511 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5512 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5513 continue; 5514 } 5515 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5516 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5517 } 5518 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5519 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5520 DAG.getNode(ISD::BUILD_VECTOR, dl, 5521 MVT::v16i8, &pshufbMask[0], 16)); 5522 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5523 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5524 } 5525 5526 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5527 // and update MaskVals with new element order. 5528 std::bitset<8> InOrder; 5529 if (BestLoQuad >= 0) { 5530 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5531 for (int i = 0; i != 4; ++i) { 5532 int idx = MaskVals[i]; 5533 if (idx < 0) { 5534 InOrder.set(i); 5535 } else if ((idx / 4) == BestLoQuad) { 5536 MaskV[i] = idx & 3; 5537 InOrder.set(i); 5538 } 5539 } 5540 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5541 &MaskV[0]); 5542 5543 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5544 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5545 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5546 NewV.getOperand(0), 5547 getShufflePSHUFLWImmediate(SVOp), DAG); 5548 } 5549 } 5550 5551 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5552 // and update MaskVals with the new element order. 5553 if (BestHiQuad >= 0) { 5554 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5555 for (unsigned i = 4; i != 8; ++i) { 5556 int idx = MaskVals[i]; 5557 if (idx < 0) { 5558 InOrder.set(i); 5559 } else if ((idx / 4) == BestHiQuad) { 5560 MaskV[i] = (idx & 3) + 4; 5561 InOrder.set(i); 5562 } 5563 } 5564 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5565 &MaskV[0]); 5566 5567 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5568 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5569 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5570 NewV.getOperand(0), 5571 getShufflePSHUFHWImmediate(SVOp), DAG); 5572 } 5573 } 5574 5575 // In case BestHi & BestLo were both -1, which means each quadword has a word 5576 // from each of the four input quadwords, calculate the InOrder bitvector now 5577 // before falling through to the insert/extract cleanup. 5578 if (BestLoQuad == -1 && BestHiQuad == -1) { 5579 NewV = V1; 5580 for (int i = 0; i != 8; ++i) 5581 if (MaskVals[i] < 0 || MaskVals[i] == i) 5582 InOrder.set(i); 5583 } 5584 5585 // The other elements are put in the right place using pextrw and pinsrw. 5586 for (unsigned i = 0; i != 8; ++i) { 5587 if (InOrder[i]) 5588 continue; 5589 int EltIdx = MaskVals[i]; 5590 if (EltIdx < 0) 5591 continue; 5592 SDValue ExtOp = (EltIdx < 8) 5593 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5594 DAG.getIntPtrConstant(EltIdx)) 5595 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5596 DAG.getIntPtrConstant(EltIdx - 8)); 5597 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5598 DAG.getIntPtrConstant(i)); 5599 } 5600 return NewV; 5601} 5602 5603// v16i8 shuffles - Prefer shuffles in the following order: 5604// 1. [ssse3] 1 x pshufb 5605// 2. [ssse3] 2 x pshufb + 1 x por 5606// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5607static 5608SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5609 SelectionDAG &DAG, 5610 const X86TargetLowering &TLI) { 5611 SDValue V1 = SVOp->getOperand(0); 5612 SDValue V2 = SVOp->getOperand(1); 5613 DebugLoc dl = SVOp->getDebugLoc(); 5614 ArrayRef<int> MaskVals = SVOp->getMask(); 5615 5616 // If we have SSSE3, case 1 is generated when all result bytes come from 5617 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5618 // present, fall back to case 3. 5619 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5620 bool V1Only = true; 5621 bool V2Only = true; 5622 for (unsigned i = 0; i < 16; ++i) { 5623 int EltIdx = MaskVals[i]; 5624 if (EltIdx < 0) 5625 continue; 5626 if (EltIdx < 16) 5627 V2Only = false; 5628 else 5629 V1Only = false; 5630 } 5631 5632 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5633 if (TLI.getSubtarget()->hasSSSE3()) { 5634 SmallVector<SDValue,16> pshufbMask; 5635 5636 // If all result elements are from one input vector, then only translate 5637 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5638 // 5639 // Otherwise, we have elements from both input vectors, and must zero out 5640 // elements that come from V2 in the first mask, and V1 in the second mask 5641 // so that we can OR them together. 5642 bool TwoInputs = !(V1Only || V2Only); 5643 for (unsigned i = 0; i != 16; ++i) { 5644 int EltIdx = MaskVals[i]; 5645 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5646 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5647 continue; 5648 } 5649 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5650 } 5651 // If all the elements are from V2, assign it to V1 and return after 5652 // building the first pshufb. 5653 if (V2Only) 5654 V1 = V2; 5655 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5656 DAG.getNode(ISD::BUILD_VECTOR, dl, 5657 MVT::v16i8, &pshufbMask[0], 16)); 5658 if (!TwoInputs) 5659 return V1; 5660 5661 // Calculate the shuffle mask for the second input, shuffle it, and 5662 // OR it with the first shuffled input. 5663 pshufbMask.clear(); 5664 for (unsigned i = 0; i != 16; ++i) { 5665 int EltIdx = MaskVals[i]; 5666 if (EltIdx < 16) { 5667 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5668 continue; 5669 } 5670 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5671 } 5672 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5673 DAG.getNode(ISD::BUILD_VECTOR, dl, 5674 MVT::v16i8, &pshufbMask[0], 16)); 5675 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5676 } 5677 5678 // No SSSE3 - Calculate in place words and then fix all out of place words 5679 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5680 // the 16 different words that comprise the two doublequadword input vectors. 5681 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5682 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5683 SDValue NewV = V2Only ? V2 : V1; 5684 for (int i = 0; i != 8; ++i) { 5685 int Elt0 = MaskVals[i*2]; 5686 int Elt1 = MaskVals[i*2+1]; 5687 5688 // This word of the result is all undef, skip it. 5689 if (Elt0 < 0 && Elt1 < 0) 5690 continue; 5691 5692 // This word of the result is already in the correct place, skip it. 5693 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5694 continue; 5695 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5696 continue; 5697 5698 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5699 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5700 SDValue InsElt; 5701 5702 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5703 // using a single extract together, load it and store it. 5704 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5705 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5706 DAG.getIntPtrConstant(Elt1 / 2)); 5707 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5708 DAG.getIntPtrConstant(i)); 5709 continue; 5710 } 5711 5712 // If Elt1 is defined, extract it from the appropriate source. If the 5713 // source byte is not also odd, shift the extracted word left 8 bits 5714 // otherwise clear the bottom 8 bits if we need to do an or. 5715 if (Elt1 >= 0) { 5716 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5717 DAG.getIntPtrConstant(Elt1 / 2)); 5718 if ((Elt1 & 1) == 0) 5719 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5720 DAG.getConstant(8, 5721 TLI.getShiftAmountTy(InsElt.getValueType()))); 5722 else if (Elt0 >= 0) 5723 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5724 DAG.getConstant(0xFF00, MVT::i16)); 5725 } 5726 // If Elt0 is defined, extract it from the appropriate source. If the 5727 // source byte is not also even, shift the extracted word right 8 bits. If 5728 // Elt1 was also defined, OR the extracted values together before 5729 // inserting them in the result. 5730 if (Elt0 >= 0) { 5731 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5732 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5733 if ((Elt0 & 1) != 0) 5734 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5735 DAG.getConstant(8, 5736 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5737 else if (Elt1 >= 0) 5738 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5739 DAG.getConstant(0x00FF, MVT::i16)); 5740 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5741 : InsElt0; 5742 } 5743 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5744 DAG.getIntPtrConstant(i)); 5745 } 5746 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5747} 5748 5749/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5750/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5751/// done when every pair / quad of shuffle mask elements point to elements in 5752/// the right sequence. e.g. 5753/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5754static 5755SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5756 SelectionDAG &DAG, DebugLoc dl) { 5757 EVT VT = SVOp->getValueType(0); 5758 SDValue V1 = SVOp->getOperand(0); 5759 SDValue V2 = SVOp->getOperand(1); 5760 unsigned NumElems = VT.getVectorNumElements(); 5761 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5762 EVT NewVT; 5763 switch (VT.getSimpleVT().SimpleTy) { 5764 default: llvm_unreachable("Unexpected!"); 5765 case MVT::v4f32: NewVT = MVT::v2f64; break; 5766 case MVT::v4i32: NewVT = MVT::v2i64; break; 5767 case MVT::v8i16: NewVT = MVT::v4i32; break; 5768 case MVT::v16i8: NewVT = MVT::v4i32; break; 5769 } 5770 5771 int Scale = NumElems / NewWidth; 5772 SmallVector<int, 8> MaskVec; 5773 for (unsigned i = 0; i < NumElems; i += Scale) { 5774 int StartIdx = -1; 5775 for (int j = 0; j < Scale; ++j) { 5776 int EltIdx = SVOp->getMaskElt(i+j); 5777 if (EltIdx < 0) 5778 continue; 5779 if (StartIdx == -1) 5780 StartIdx = EltIdx - (EltIdx % Scale); 5781 if (EltIdx != StartIdx + j) 5782 return SDValue(); 5783 } 5784 if (StartIdx == -1) 5785 MaskVec.push_back(-1); 5786 else 5787 MaskVec.push_back(StartIdx / Scale); 5788 } 5789 5790 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5791 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5792 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5793} 5794 5795/// getVZextMovL - Return a zero-extending vector move low node. 5796/// 5797static SDValue getVZextMovL(EVT VT, EVT OpVT, 5798 SDValue SrcOp, SelectionDAG &DAG, 5799 const X86Subtarget *Subtarget, DebugLoc dl) { 5800 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5801 LoadSDNode *LD = NULL; 5802 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5803 LD = dyn_cast<LoadSDNode>(SrcOp); 5804 if (!LD) { 5805 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5806 // instead. 5807 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5808 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5809 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5810 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5811 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5812 // PR2108 5813 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5814 return DAG.getNode(ISD::BITCAST, dl, VT, 5815 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5816 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5817 OpVT, 5818 SrcOp.getOperand(0) 5819 .getOperand(0)))); 5820 } 5821 } 5822 } 5823 5824 return DAG.getNode(ISD::BITCAST, dl, VT, 5825 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5826 DAG.getNode(ISD::BITCAST, dl, 5827 OpVT, SrcOp))); 5828} 5829 5830/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5831/// which could not be matched by any known target speficic shuffle 5832static SDValue 5833LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5834 EVT VT = SVOp->getValueType(0); 5835 5836 unsigned NumElems = VT.getVectorNumElements(); 5837 unsigned NumLaneElems = NumElems / 2; 5838 5839 int MinRange[2][2] = { { static_cast<int>(NumElems), 5840 static_cast<int>(NumElems) }, 5841 { static_cast<int>(NumElems), 5842 static_cast<int>(NumElems) } }; 5843 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } }; 5844 5845 // Collect used ranges for each source in each lane 5846 for (unsigned l = 0; l < 2; ++l) { 5847 unsigned LaneStart = l*NumLaneElems; 5848 for (unsigned i = 0; i != NumLaneElems; ++i) { 5849 int Idx = SVOp->getMaskElt(i+LaneStart); 5850 if (Idx < 0) 5851 continue; 5852 5853 int Input = 0; 5854 if (Idx >= (int)NumElems) { 5855 Idx -= NumElems; 5856 Input = 1; 5857 } 5858 5859 if (Idx > MaxRange[l][Input]) 5860 MaxRange[l][Input] = Idx; 5861 if (Idx < MinRange[l][Input]) 5862 MinRange[l][Input] = Idx; 5863 } 5864 } 5865 5866 // Make sure each range is 128-bits 5867 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } }; 5868 for (unsigned l = 0; l < 2; ++l) { 5869 for (unsigned Input = 0; Input < 2; ++Input) { 5870 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0) 5871 continue; 5872 5873 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems) 5874 ExtractIdx[l][Input] = 0; 5875 else if (MinRange[l][Input] >= (int)NumLaneElems && 5876 MaxRange[l][Input] < (int)NumElems) 5877 ExtractIdx[l][Input] = NumLaneElems; 5878 else 5879 return SDValue(); 5880 } 5881 } 5882 5883 DebugLoc dl = SVOp->getDebugLoc(); 5884 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5885 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2); 5886 5887 SDValue Ops[2][2]; 5888 for (unsigned l = 0; l < 2; ++l) { 5889 for (unsigned Input = 0; Input < 2; ++Input) { 5890 if (ExtractIdx[l][Input] >= 0) 5891 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input), 5892 DAG.getConstant(ExtractIdx[l][Input], MVT::i32), 5893 DAG, dl); 5894 else 5895 Ops[l][Input] = DAG.getUNDEF(NVT); 5896 } 5897 } 5898 5899 // Generate 128-bit shuffles 5900 SmallVector<int, 16> Mask1, Mask2; 5901 for (unsigned i = 0; i != NumLaneElems; ++i) { 5902 int Elt = SVOp->getMaskElt(i); 5903 if (Elt >= (int)NumElems) { 5904 Elt %= NumLaneElems; 5905 Elt += NumLaneElems; 5906 } else if (Elt >= 0) { 5907 Elt %= NumLaneElems; 5908 } 5909 Mask1.push_back(Elt); 5910 } 5911 for (unsigned i = NumLaneElems; i != NumElems; ++i) { 5912 int Elt = SVOp->getMaskElt(i); 5913 if (Elt >= (int)NumElems) { 5914 Elt %= NumLaneElems; 5915 Elt += NumLaneElems; 5916 } else if (Elt >= 0) { 5917 Elt %= NumLaneElems; 5918 } 5919 Mask2.push_back(Elt); 5920 } 5921 5922 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]); 5923 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]); 5924 5925 // Concatenate the result back 5926 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1, 5927 DAG.getConstant(0, MVT::i32), DAG, dl); 5928 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32), 5929 DAG, dl); 5930} 5931 5932/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 5933/// 4 elements, and match them with several different shuffle types. 5934static SDValue 5935LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5936 SDValue V1 = SVOp->getOperand(0); 5937 SDValue V2 = SVOp->getOperand(1); 5938 DebugLoc dl = SVOp->getDebugLoc(); 5939 EVT VT = SVOp->getValueType(0); 5940 5941 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 5942 5943 std::pair<int, int> Locs[4]; 5944 int Mask1[] = { -1, -1, -1, -1 }; 5945 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 5946 5947 unsigned NumHi = 0; 5948 unsigned NumLo = 0; 5949 for (unsigned i = 0; i != 4; ++i) { 5950 int Idx = PermMask[i]; 5951 if (Idx < 0) { 5952 Locs[i] = std::make_pair(-1, -1); 5953 } else { 5954 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 5955 if (Idx < 4) { 5956 Locs[i] = std::make_pair(0, NumLo); 5957 Mask1[NumLo] = Idx; 5958 NumLo++; 5959 } else { 5960 Locs[i] = std::make_pair(1, NumHi); 5961 if (2+NumHi < 4) 5962 Mask1[2+NumHi] = Idx; 5963 NumHi++; 5964 } 5965 } 5966 } 5967 5968 if (NumLo <= 2 && NumHi <= 2) { 5969 // If no more than two elements come from either vector. This can be 5970 // implemented with two shuffles. First shuffle gather the elements. 5971 // The second shuffle, which takes the first shuffle as both of its 5972 // vector operands, put the elements into the right order. 5973 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5974 5975 int Mask2[] = { -1, -1, -1, -1 }; 5976 5977 for (unsigned i = 0; i != 4; ++i) 5978 if (Locs[i].first != -1) { 5979 unsigned Idx = (i < 2) ? 0 : 4; 5980 Idx += Locs[i].first * 2 + Locs[i].second; 5981 Mask2[i] = Idx; 5982 } 5983 5984 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 5985 } else if (NumLo == 3 || NumHi == 3) { 5986 // Otherwise, we must have three elements from one vector, call it X, and 5987 // one element from the other, call it Y. First, use a shufps to build an 5988 // intermediate vector with the one element from Y and the element from X 5989 // that will be in the same half in the final destination (the indexes don't 5990 // matter). Then, use a shufps to build the final vector, taking the half 5991 // containing the element from Y from the intermediate, and the other half 5992 // from X. 5993 if (NumHi == 3) { 5994 // Normalize it so the 3 elements come from V1. 5995 CommuteVectorShuffleMask(PermMask, 4); 5996 std::swap(V1, V2); 5997 } 5998 5999 // Find the element from V2. 6000 unsigned HiIndex; 6001 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6002 int Val = PermMask[HiIndex]; 6003 if (Val < 0) 6004 continue; 6005 if (Val >= 4) 6006 break; 6007 } 6008 6009 Mask1[0] = PermMask[HiIndex]; 6010 Mask1[1] = -1; 6011 Mask1[2] = PermMask[HiIndex^1]; 6012 Mask1[3] = -1; 6013 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6014 6015 if (HiIndex >= 2) { 6016 Mask1[0] = PermMask[0]; 6017 Mask1[1] = PermMask[1]; 6018 Mask1[2] = HiIndex & 1 ? 6 : 4; 6019 Mask1[3] = HiIndex & 1 ? 4 : 6; 6020 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6021 } else { 6022 Mask1[0] = HiIndex & 1 ? 2 : 0; 6023 Mask1[1] = HiIndex & 1 ? 0 : 2; 6024 Mask1[2] = PermMask[2]; 6025 Mask1[3] = PermMask[3]; 6026 if (Mask1[2] >= 0) 6027 Mask1[2] += 4; 6028 if (Mask1[3] >= 0) 6029 Mask1[3] += 4; 6030 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6031 } 6032 } 6033 6034 // Break it into (shuffle shuffle_hi, shuffle_lo). 6035 int LoMask[] = { -1, -1, -1, -1 }; 6036 int HiMask[] = { -1, -1, -1, -1 }; 6037 6038 int *MaskPtr = LoMask; 6039 unsigned MaskIdx = 0; 6040 unsigned LoIdx = 0; 6041 unsigned HiIdx = 2; 6042 for (unsigned i = 0; i != 4; ++i) { 6043 if (i == 2) { 6044 MaskPtr = HiMask; 6045 MaskIdx = 1; 6046 LoIdx = 0; 6047 HiIdx = 2; 6048 } 6049 int Idx = PermMask[i]; 6050 if (Idx < 0) { 6051 Locs[i] = std::make_pair(-1, -1); 6052 } else if (Idx < 4) { 6053 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6054 MaskPtr[LoIdx] = Idx; 6055 LoIdx++; 6056 } else { 6057 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6058 MaskPtr[HiIdx] = Idx; 6059 HiIdx++; 6060 } 6061 } 6062 6063 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6064 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6065 int MaskOps[] = { -1, -1, -1, -1 }; 6066 for (unsigned i = 0; i != 4; ++i) 6067 if (Locs[i].first != -1) 6068 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6069 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6070} 6071 6072static bool MayFoldVectorLoad(SDValue V) { 6073 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6074 V = V.getOperand(0); 6075 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6076 V = V.getOperand(0); 6077 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6078 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6079 // BUILD_VECTOR (load), undef 6080 V = V.getOperand(0); 6081 if (MayFoldLoad(V)) 6082 return true; 6083 return false; 6084} 6085 6086// FIXME: the version above should always be used. Since there's 6087// a bug where several vector shuffles can't be folded because the 6088// DAG is not updated during lowering and a node claims to have two 6089// uses while it only has one, use this version, and let isel match 6090// another instruction if the load really happens to have more than 6091// one use. Remove this version after this bug get fixed. 6092// rdar://8434668, PR8156 6093static bool RelaxedMayFoldVectorLoad(SDValue V) { 6094 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6095 V = V.getOperand(0); 6096 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6097 V = V.getOperand(0); 6098 if (ISD::isNormalLoad(V.getNode())) 6099 return true; 6100 return false; 6101} 6102 6103static 6104SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6105 EVT VT = Op.getValueType(); 6106 6107 // Canonizalize to v2f64. 6108 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6109 return DAG.getNode(ISD::BITCAST, dl, VT, 6110 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6111 V1, DAG)); 6112} 6113 6114static 6115SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6116 bool HasSSE2) { 6117 SDValue V1 = Op.getOperand(0); 6118 SDValue V2 = Op.getOperand(1); 6119 EVT VT = Op.getValueType(); 6120 6121 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6122 6123 if (HasSSE2 && VT == MVT::v2f64) 6124 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6125 6126 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6127 return DAG.getNode(ISD::BITCAST, dl, VT, 6128 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6129 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6130 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6131} 6132 6133static 6134SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6135 SDValue V1 = Op.getOperand(0); 6136 SDValue V2 = Op.getOperand(1); 6137 EVT VT = Op.getValueType(); 6138 6139 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6140 "unsupported shuffle type"); 6141 6142 if (V2.getOpcode() == ISD::UNDEF) 6143 V2 = V1; 6144 6145 // v4i32 or v4f32 6146 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6147} 6148 6149static 6150SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6151 SDValue V1 = Op.getOperand(0); 6152 SDValue V2 = Op.getOperand(1); 6153 EVT VT = Op.getValueType(); 6154 unsigned NumElems = VT.getVectorNumElements(); 6155 6156 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6157 // operand of these instructions is only memory, so check if there's a 6158 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6159 // same masks. 6160 bool CanFoldLoad = false; 6161 6162 // Trivial case, when V2 comes from a load. 6163 if (MayFoldVectorLoad(V2)) 6164 CanFoldLoad = true; 6165 6166 // When V1 is a load, it can be folded later into a store in isel, example: 6167 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6168 // turns into: 6169 // (MOVLPSmr addr:$src1, VR128:$src2) 6170 // So, recognize this potential and also use MOVLPS or MOVLPD 6171 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6172 CanFoldLoad = true; 6173 6174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6175 if (CanFoldLoad) { 6176 if (HasSSE2 && NumElems == 2) 6177 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6178 6179 if (NumElems == 4) 6180 // If we don't care about the second element, procede to use movss. 6181 if (SVOp->getMaskElt(1) != -1) 6182 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6183 } 6184 6185 // movl and movlp will both match v2i64, but v2i64 is never matched by 6186 // movl earlier because we make it strict to avoid messing with the movlp load 6187 // folding logic (see the code above getMOVLP call). Match it here then, 6188 // this is horrible, but will stay like this until we move all shuffle 6189 // matching to x86 specific nodes. Note that for the 1st condition all 6190 // types are matched with movsd. 6191 if (HasSSE2) { 6192 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6193 // as to remove this logic from here, as much as possible 6194 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6195 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6196 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6197 } 6198 6199 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6200 6201 // Invert the operand order and use SHUFPS to match it. 6202 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6203 getShuffleSHUFImmediate(SVOp), DAG); 6204} 6205 6206static 6207SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6208 const TargetLowering &TLI, 6209 const X86Subtarget *Subtarget) { 6210 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6211 EVT VT = Op.getValueType(); 6212 DebugLoc dl = Op.getDebugLoc(); 6213 SDValue V1 = Op.getOperand(0); 6214 SDValue V2 = Op.getOperand(1); 6215 6216 if (isZeroShuffle(SVOp)) 6217 return getZeroVector(VT, Subtarget, DAG, dl); 6218 6219 // Handle splat operations 6220 if (SVOp->isSplat()) { 6221 unsigned NumElem = VT.getVectorNumElements(); 6222 int Size = VT.getSizeInBits(); 6223 6224 // Use vbroadcast whenever the splat comes from a foldable load 6225 SDValue LD = isVectorBroadcast(Op, Subtarget); 6226 if (LD.getNode()) 6227 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6228 6229 // Handle splats by matching through known shuffle masks 6230 if ((Size == 128 && NumElem <= 4) || 6231 (Size == 256 && NumElem < 8)) 6232 return SDValue(); 6233 6234 // All remaning splats are promoted to target supported vector shuffles. 6235 return PromoteSplat(SVOp, DAG); 6236 } 6237 6238 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6239 // do it! 6240 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6241 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6242 if (NewOp.getNode()) 6243 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6244 } else if ((VT == MVT::v4i32 || 6245 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6246 // FIXME: Figure out a cleaner way to do this. 6247 // Try to make use of movq to zero out the top part. 6248 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6249 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6250 if (NewOp.getNode()) { 6251 EVT NewVT = NewOp.getValueType(); 6252 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6253 NewVT, true, false)) 6254 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6255 DAG, Subtarget, dl); 6256 } 6257 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6258 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6259 if (NewOp.getNode()) { 6260 EVT NewVT = NewOp.getValueType(); 6261 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6262 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6263 DAG, Subtarget, dl); 6264 } 6265 } 6266 } 6267 return SDValue(); 6268} 6269 6270SDValue 6271X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6272 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6273 SDValue V1 = Op.getOperand(0); 6274 SDValue V2 = Op.getOperand(1); 6275 EVT VT = Op.getValueType(); 6276 DebugLoc dl = Op.getDebugLoc(); 6277 unsigned NumElems = VT.getVectorNumElements(); 6278 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6279 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6280 bool V1IsSplat = false; 6281 bool V2IsSplat = false; 6282 bool HasSSE2 = Subtarget->hasSSE2(); 6283 bool HasAVX = Subtarget->hasAVX(); 6284 bool HasAVX2 = Subtarget->hasAVX2(); 6285 MachineFunction &MF = DAG.getMachineFunction(); 6286 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6287 6288 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6289 6290 if (V1IsUndef && V2IsUndef) 6291 return DAG.getUNDEF(VT); 6292 6293 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6294 6295 // Vector shuffle lowering takes 3 steps: 6296 // 6297 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6298 // narrowing and commutation of operands should be handled. 6299 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6300 // shuffle nodes. 6301 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6302 // so the shuffle can be broken into other shuffles and the legalizer can 6303 // try the lowering again. 6304 // 6305 // The general idea is that no vector_shuffle operation should be left to 6306 // be matched during isel, all of them must be converted to a target specific 6307 // node here. 6308 6309 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6310 // narrowing and commutation of operands should be handled. The actual code 6311 // doesn't include all of those, work in progress... 6312 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6313 if (NewOp.getNode()) 6314 return NewOp; 6315 6316 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6317 6318 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6319 // unpckh_undef). Only use pshufd if speed is more important than size. 6320 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6321 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6322 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6323 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6324 6325 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6326 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6327 return getMOVDDup(Op, dl, V1, DAG); 6328 6329 if (isMOVHLPS_v_undef_Mask(M, VT)) 6330 return getMOVHighToLow(Op, dl, DAG); 6331 6332 // Use to match splats 6333 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6334 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6335 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6336 6337 if (isPSHUFDMask(M, VT)) { 6338 // The actual implementation will match the mask in the if above and then 6339 // during isel it can match several different instructions, not only pshufd 6340 // as its name says, sad but true, emulate the behavior for now... 6341 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6342 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6343 6344 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6345 6346 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6347 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6348 6349 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6350 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6351 6352 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6353 TargetMask, DAG); 6354 } 6355 6356 // Check if this can be converted into a logical shift. 6357 bool isLeft = false; 6358 unsigned ShAmt = 0; 6359 SDValue ShVal; 6360 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6361 if (isShift && ShVal.hasOneUse()) { 6362 // If the shifted value has multiple uses, it may be cheaper to use 6363 // v_set0 + movlhps or movhlps, etc. 6364 EVT EltVT = VT.getVectorElementType(); 6365 ShAmt *= EltVT.getSizeInBits(); 6366 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6367 } 6368 6369 if (isMOVLMask(M, VT)) { 6370 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6371 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6372 if (!isMOVLPMask(M, VT)) { 6373 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6374 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6375 6376 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6377 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6378 } 6379 } 6380 6381 // FIXME: fold these into legal mask. 6382 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6383 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6384 6385 if (isMOVHLPSMask(M, VT)) 6386 return getMOVHighToLow(Op, dl, DAG); 6387 6388 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6389 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6390 6391 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6392 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6393 6394 if (isMOVLPMask(M, VT)) 6395 return getMOVLP(Op, dl, DAG, HasSSE2); 6396 6397 if (ShouldXformToMOVHLPS(M, VT) || 6398 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6399 return CommuteVectorShuffle(SVOp, DAG); 6400 6401 if (isShift) { 6402 // No better options. Use a vshldq / vsrldq. 6403 EVT EltVT = VT.getVectorElementType(); 6404 ShAmt *= EltVT.getSizeInBits(); 6405 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6406 } 6407 6408 bool Commuted = false; 6409 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6410 // 1,1,1,1 -> v8i16 though. 6411 V1IsSplat = isSplatVector(V1.getNode()); 6412 V2IsSplat = isSplatVector(V2.getNode()); 6413 6414 // Canonicalize the splat or undef, if present, to be on the RHS. 6415 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6416 CommuteVectorShuffleMask(M, NumElems); 6417 std::swap(V1, V2); 6418 std::swap(V1IsSplat, V2IsSplat); 6419 Commuted = true; 6420 } 6421 6422 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6423 // Shuffling low element of v1 into undef, just return v1. 6424 if (V2IsUndef) 6425 return V1; 6426 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6427 // the instruction selector will not match, so get a canonical MOVL with 6428 // swapped operands to undo the commute. 6429 return getMOVL(DAG, dl, VT, V2, V1); 6430 } 6431 6432 if (isUNPCKLMask(M, VT, HasAVX2)) 6433 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6434 6435 if (isUNPCKHMask(M, VT, HasAVX2)) 6436 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6437 6438 if (V2IsSplat) { 6439 // Normalize mask so all entries that point to V2 points to its first 6440 // element then try to match unpck{h|l} again. If match, return a 6441 // new vector_shuffle with the corrected mask.p 6442 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6443 NormalizeMask(NewMask, NumElems); 6444 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) { 6445 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6446 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) { 6447 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6448 } 6449 } 6450 6451 if (Commuted) { 6452 // Commute is back and try unpck* again. 6453 // FIXME: this seems wrong. 6454 CommuteVectorShuffleMask(M, NumElems); 6455 std::swap(V1, V2); 6456 std::swap(V1IsSplat, V2IsSplat); 6457 Commuted = false; 6458 6459 if (isUNPCKLMask(M, VT, HasAVX2)) 6460 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6461 6462 if (isUNPCKHMask(M, VT, HasAVX2)) 6463 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6464 } 6465 6466 // Normalize the node to match x86 shuffle ops if needed 6467 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6468 return CommuteVectorShuffle(SVOp, DAG); 6469 6470 // The checks below are all present in isShuffleMaskLegal, but they are 6471 // inlined here right now to enable us to directly emit target specific 6472 // nodes, and remove one by one until they don't return Op anymore. 6473 6474 if (isPALIGNRMask(M, VT, Subtarget)) 6475 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6476 getShufflePALIGNRImmediate(SVOp), 6477 DAG); 6478 6479 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6480 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6481 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6482 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6483 } 6484 6485 if (isPSHUFHWMask(M, VT)) 6486 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6487 getShufflePSHUFHWImmediate(SVOp), 6488 DAG); 6489 6490 if (isPSHUFLWMask(M, VT)) 6491 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6492 getShufflePSHUFLWImmediate(SVOp), 6493 DAG); 6494 6495 if (isSHUFPMask(M, VT, HasAVX)) 6496 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6497 getShuffleSHUFImmediate(SVOp), DAG); 6498 6499 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6500 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6501 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6502 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6503 6504 //===--------------------------------------------------------------------===// 6505 // Generate target specific nodes for 128 or 256-bit shuffles only 6506 // supported in the AVX instruction set. 6507 // 6508 6509 // Handle VMOVDDUPY permutations 6510 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6511 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6512 6513 // Handle VPERMILPS/D* permutations 6514 if (isVPERMILPMask(M, VT, HasAVX)) { 6515 if (HasAVX2 && VT == MVT::v8i32) 6516 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6517 getShuffleSHUFImmediate(SVOp), DAG); 6518 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6519 getShuffleSHUFImmediate(SVOp), DAG); 6520 } 6521 6522 // Handle VPERM2F128/VPERM2I128 permutations 6523 if (isVPERM2X128Mask(M, VT, HasAVX)) 6524 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6525 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6526 6527 //===--------------------------------------------------------------------===// 6528 // Since no target specific shuffle was selected for this generic one, 6529 // lower it into other known shuffles. FIXME: this isn't true yet, but 6530 // this is the plan. 6531 // 6532 6533 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6534 if (VT == MVT::v8i16) { 6535 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6536 if (NewOp.getNode()) 6537 return NewOp; 6538 } 6539 6540 if (VT == MVT::v16i8) { 6541 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6542 if (NewOp.getNode()) 6543 return NewOp; 6544 } 6545 6546 // Handle all 128-bit wide vectors with 4 elements, and match them with 6547 // several different shuffle types. 6548 if (NumElems == 4 && VT.getSizeInBits() == 128) 6549 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6550 6551 // Handle general 256-bit shuffles 6552 if (VT.is256BitVector()) 6553 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6554 6555 return SDValue(); 6556} 6557 6558SDValue 6559X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6560 SelectionDAG &DAG) const { 6561 EVT VT = Op.getValueType(); 6562 DebugLoc dl = Op.getDebugLoc(); 6563 6564 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6565 return SDValue(); 6566 6567 if (VT.getSizeInBits() == 8) { 6568 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6569 Op.getOperand(0), Op.getOperand(1)); 6570 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6571 DAG.getValueType(VT)); 6572 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6573 } else if (VT.getSizeInBits() == 16) { 6574 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6575 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6576 if (Idx == 0) 6577 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6578 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6579 DAG.getNode(ISD::BITCAST, dl, 6580 MVT::v4i32, 6581 Op.getOperand(0)), 6582 Op.getOperand(1))); 6583 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6584 Op.getOperand(0), Op.getOperand(1)); 6585 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6586 DAG.getValueType(VT)); 6587 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6588 } else if (VT == MVT::f32) { 6589 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6590 // the result back to FR32 register. It's only worth matching if the 6591 // result has a single use which is a store or a bitcast to i32. And in 6592 // the case of a store, it's not worth it if the index is a constant 0, 6593 // because a MOVSSmr can be used instead, which is smaller and faster. 6594 if (!Op.hasOneUse()) 6595 return SDValue(); 6596 SDNode *User = *Op.getNode()->use_begin(); 6597 if ((User->getOpcode() != ISD::STORE || 6598 (isa<ConstantSDNode>(Op.getOperand(1)) && 6599 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6600 (User->getOpcode() != ISD::BITCAST || 6601 User->getValueType(0) != MVT::i32)) 6602 return SDValue(); 6603 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6604 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6605 Op.getOperand(0)), 6606 Op.getOperand(1)); 6607 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6608 } else if (VT == MVT::i32 || VT == MVT::i64) { 6609 // ExtractPS/pextrq works with constant index. 6610 if (isa<ConstantSDNode>(Op.getOperand(1))) 6611 return Op; 6612 } 6613 return SDValue(); 6614} 6615 6616 6617SDValue 6618X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6619 SelectionDAG &DAG) const { 6620 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6621 return SDValue(); 6622 6623 SDValue Vec = Op.getOperand(0); 6624 EVT VecVT = Vec.getValueType(); 6625 6626 // If this is a 256-bit vector result, first extract the 128-bit vector and 6627 // then extract the element from the 128-bit vector. 6628 if (VecVT.getSizeInBits() == 256) { 6629 DebugLoc dl = Op.getNode()->getDebugLoc(); 6630 unsigned NumElems = VecVT.getVectorNumElements(); 6631 SDValue Idx = Op.getOperand(1); 6632 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6633 6634 // Get the 128-bit vector. 6635 bool Upper = IdxVal >= NumElems/2; 6636 Vec = Extract128BitVector(Vec, 6637 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6638 6639 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6640 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6641 } 6642 6643 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6644 6645 if (Subtarget->hasSSE41()) { 6646 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6647 if (Res.getNode()) 6648 return Res; 6649 } 6650 6651 EVT VT = Op.getValueType(); 6652 DebugLoc dl = Op.getDebugLoc(); 6653 // TODO: handle v16i8. 6654 if (VT.getSizeInBits() == 16) { 6655 SDValue Vec = Op.getOperand(0); 6656 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6657 if (Idx == 0) 6658 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6659 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6660 DAG.getNode(ISD::BITCAST, dl, 6661 MVT::v4i32, Vec), 6662 Op.getOperand(1))); 6663 // Transform it so it match pextrw which produces a 32-bit result. 6664 EVT EltVT = MVT::i32; 6665 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6666 Op.getOperand(0), Op.getOperand(1)); 6667 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6668 DAG.getValueType(VT)); 6669 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6670 } else if (VT.getSizeInBits() == 32) { 6671 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6672 if (Idx == 0) 6673 return Op; 6674 6675 // SHUFPS the element to the lowest double word, then movss. 6676 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6677 EVT VVT = Op.getOperand(0).getValueType(); 6678 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6679 DAG.getUNDEF(VVT), Mask); 6680 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6681 DAG.getIntPtrConstant(0)); 6682 } else if (VT.getSizeInBits() == 64) { 6683 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6684 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6685 // to match extract_elt for f64. 6686 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6687 if (Idx == 0) 6688 return Op; 6689 6690 // UNPCKHPD the element to the lowest double word, then movsd. 6691 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6692 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6693 int Mask[2] = { 1, -1 }; 6694 EVT VVT = Op.getOperand(0).getValueType(); 6695 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6696 DAG.getUNDEF(VVT), Mask); 6697 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6698 DAG.getIntPtrConstant(0)); 6699 } 6700 6701 return SDValue(); 6702} 6703 6704SDValue 6705X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6706 SelectionDAG &DAG) const { 6707 EVT VT = Op.getValueType(); 6708 EVT EltVT = VT.getVectorElementType(); 6709 DebugLoc dl = Op.getDebugLoc(); 6710 6711 SDValue N0 = Op.getOperand(0); 6712 SDValue N1 = Op.getOperand(1); 6713 SDValue N2 = Op.getOperand(2); 6714 6715 if (VT.getSizeInBits() == 256) 6716 return SDValue(); 6717 6718 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6719 isa<ConstantSDNode>(N2)) { 6720 unsigned Opc; 6721 if (VT == MVT::v8i16) 6722 Opc = X86ISD::PINSRW; 6723 else if (VT == MVT::v16i8) 6724 Opc = X86ISD::PINSRB; 6725 else 6726 Opc = X86ISD::PINSRB; 6727 6728 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6729 // argument. 6730 if (N1.getValueType() != MVT::i32) 6731 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6732 if (N2.getValueType() != MVT::i32) 6733 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6734 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6735 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6736 // Bits [7:6] of the constant are the source select. This will always be 6737 // zero here. The DAG Combiner may combine an extract_elt index into these 6738 // bits. For example (insert (extract, 3), 2) could be matched by putting 6739 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6740 // Bits [5:4] of the constant are the destination select. This is the 6741 // value of the incoming immediate. 6742 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6743 // combine either bitwise AND or insert of float 0.0 to set these bits. 6744 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6745 // Create this as a scalar to vector.. 6746 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6747 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6748 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6749 isa<ConstantSDNode>(N2)) { 6750 // PINSR* works with constant index. 6751 return Op; 6752 } 6753 return SDValue(); 6754} 6755 6756SDValue 6757X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6758 EVT VT = Op.getValueType(); 6759 EVT EltVT = VT.getVectorElementType(); 6760 6761 DebugLoc dl = Op.getDebugLoc(); 6762 SDValue N0 = Op.getOperand(0); 6763 SDValue N1 = Op.getOperand(1); 6764 SDValue N2 = Op.getOperand(2); 6765 6766 // If this is a 256-bit vector result, first extract the 128-bit vector, 6767 // insert the element into the extracted half and then place it back. 6768 if (VT.getSizeInBits() == 256) { 6769 if (!isa<ConstantSDNode>(N2)) 6770 return SDValue(); 6771 6772 // Get the desired 128-bit vector half. 6773 unsigned NumElems = VT.getVectorNumElements(); 6774 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6775 bool Upper = IdxVal >= NumElems/2; 6776 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6777 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6778 6779 // Insert the element into the desired half. 6780 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6781 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6782 6783 // Insert the changed part back to the 256-bit vector 6784 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6785 } 6786 6787 if (Subtarget->hasSSE41()) 6788 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6789 6790 if (EltVT == MVT::i8) 6791 return SDValue(); 6792 6793 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6794 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6795 // as its second argument. 6796 if (N1.getValueType() != MVT::i32) 6797 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6798 if (N2.getValueType() != MVT::i32) 6799 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6800 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6801 } 6802 return SDValue(); 6803} 6804 6805SDValue 6806X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6807 LLVMContext *Context = DAG.getContext(); 6808 DebugLoc dl = Op.getDebugLoc(); 6809 EVT OpVT = Op.getValueType(); 6810 6811 // If this is a 256-bit vector result, first insert into a 128-bit 6812 // vector and then insert into the 256-bit vector. 6813 if (OpVT.getSizeInBits() > 128) { 6814 // Insert into a 128-bit vector. 6815 EVT VT128 = EVT::getVectorVT(*Context, 6816 OpVT.getVectorElementType(), 6817 OpVT.getVectorNumElements() / 2); 6818 6819 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6820 6821 // Insert the 128-bit vector. 6822 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6823 DAG.getConstant(0, MVT::i32), 6824 DAG, dl); 6825 } 6826 6827 if (Op.getValueType() == MVT::v1i64 && 6828 Op.getOperand(0).getValueType() == MVT::i64) 6829 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6830 6831 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6832 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6833 "Expected an SSE type!"); 6834 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6835 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6836} 6837 6838// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6839// a simple subregister reference or explicit instructions to grab 6840// upper bits of a vector. 6841SDValue 6842X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6843 if (Subtarget->hasAVX()) { 6844 DebugLoc dl = Op.getNode()->getDebugLoc(); 6845 SDValue Vec = Op.getNode()->getOperand(0); 6846 SDValue Idx = Op.getNode()->getOperand(1); 6847 6848 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6849 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6850 return Extract128BitVector(Vec, Idx, DAG, dl); 6851 } 6852 } 6853 return SDValue(); 6854} 6855 6856// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6857// simple superregister reference or explicit instructions to insert 6858// the upper bits of a vector. 6859SDValue 6860X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6861 if (Subtarget->hasAVX()) { 6862 DebugLoc dl = Op.getNode()->getDebugLoc(); 6863 SDValue Vec = Op.getNode()->getOperand(0); 6864 SDValue SubVec = Op.getNode()->getOperand(1); 6865 SDValue Idx = Op.getNode()->getOperand(2); 6866 6867 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6868 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6869 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6870 } 6871 } 6872 return SDValue(); 6873} 6874 6875// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6876// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6877// one of the above mentioned nodes. It has to be wrapped because otherwise 6878// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6879// be used to form addressing mode. These wrapped nodes will be selected 6880// into MOV32ri. 6881SDValue 6882X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6883 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6884 6885 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6886 // global base reg. 6887 unsigned char OpFlag = 0; 6888 unsigned WrapperKind = X86ISD::Wrapper; 6889 CodeModel::Model M = getTargetMachine().getCodeModel(); 6890 6891 if (Subtarget->isPICStyleRIPRel() && 6892 (M == CodeModel::Small || M == CodeModel::Kernel)) 6893 WrapperKind = X86ISD::WrapperRIP; 6894 else if (Subtarget->isPICStyleGOT()) 6895 OpFlag = X86II::MO_GOTOFF; 6896 else if (Subtarget->isPICStyleStubPIC()) 6897 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6898 6899 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6900 CP->getAlignment(), 6901 CP->getOffset(), OpFlag); 6902 DebugLoc DL = CP->getDebugLoc(); 6903 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6904 // With PIC, the address is actually $g + Offset. 6905 if (OpFlag) { 6906 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6907 DAG.getNode(X86ISD::GlobalBaseReg, 6908 DebugLoc(), getPointerTy()), 6909 Result); 6910 } 6911 6912 return Result; 6913} 6914 6915SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 6916 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 6917 6918 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6919 // global base reg. 6920 unsigned char OpFlag = 0; 6921 unsigned WrapperKind = X86ISD::Wrapper; 6922 CodeModel::Model M = getTargetMachine().getCodeModel(); 6923 6924 if (Subtarget->isPICStyleRIPRel() && 6925 (M == CodeModel::Small || M == CodeModel::Kernel)) 6926 WrapperKind = X86ISD::WrapperRIP; 6927 else if (Subtarget->isPICStyleGOT()) 6928 OpFlag = X86II::MO_GOTOFF; 6929 else if (Subtarget->isPICStyleStubPIC()) 6930 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6931 6932 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 6933 OpFlag); 6934 DebugLoc DL = JT->getDebugLoc(); 6935 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6936 6937 // With PIC, the address is actually $g + Offset. 6938 if (OpFlag) 6939 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6940 DAG.getNode(X86ISD::GlobalBaseReg, 6941 DebugLoc(), getPointerTy()), 6942 Result); 6943 6944 return Result; 6945} 6946 6947SDValue 6948X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 6949 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 6950 6951 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6952 // global base reg. 6953 unsigned char OpFlag = 0; 6954 unsigned WrapperKind = X86ISD::Wrapper; 6955 CodeModel::Model M = getTargetMachine().getCodeModel(); 6956 6957 if (Subtarget->isPICStyleRIPRel() && 6958 (M == CodeModel::Small || M == CodeModel::Kernel)) { 6959 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 6960 OpFlag = X86II::MO_GOTPCREL; 6961 WrapperKind = X86ISD::WrapperRIP; 6962 } else if (Subtarget->isPICStyleGOT()) { 6963 OpFlag = X86II::MO_GOT; 6964 } else if (Subtarget->isPICStyleStubPIC()) { 6965 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 6966 } else if (Subtarget->isPICStyleStubNoDynamic()) { 6967 OpFlag = X86II::MO_DARWIN_NONLAZY; 6968 } 6969 6970 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 6971 6972 DebugLoc DL = Op.getDebugLoc(); 6973 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6974 6975 6976 // With PIC, the address is actually $g + Offset. 6977 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 6978 !Subtarget->is64Bit()) { 6979 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6980 DAG.getNode(X86ISD::GlobalBaseReg, 6981 DebugLoc(), getPointerTy()), 6982 Result); 6983 } 6984 6985 // For symbols that require a load from a stub to get the address, emit the 6986 // load. 6987 if (isGlobalStubReference(OpFlag)) 6988 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 6989 MachinePointerInfo::getGOT(), false, false, false, 0); 6990 6991 return Result; 6992} 6993 6994SDValue 6995X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 6996 // Create the TargetBlockAddressAddress node. 6997 unsigned char OpFlags = 6998 Subtarget->ClassifyBlockAddressReference(); 6999 CodeModel::Model M = getTargetMachine().getCodeModel(); 7000 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7001 DebugLoc dl = Op.getDebugLoc(); 7002 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7003 /*isTarget=*/true, OpFlags); 7004 7005 if (Subtarget->isPICStyleRIPRel() && 7006 (M == CodeModel::Small || M == CodeModel::Kernel)) 7007 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7008 else 7009 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7010 7011 // With PIC, the address is actually $g + Offset. 7012 if (isGlobalRelativeToPICBase(OpFlags)) { 7013 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7014 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7015 Result); 7016 } 7017 7018 return Result; 7019} 7020 7021SDValue 7022X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7023 int64_t Offset, 7024 SelectionDAG &DAG) const { 7025 // Create the TargetGlobalAddress node, folding in the constant 7026 // offset if it is legal. 7027 unsigned char OpFlags = 7028 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7029 CodeModel::Model M = getTargetMachine().getCodeModel(); 7030 SDValue Result; 7031 if (OpFlags == X86II::MO_NO_FLAG && 7032 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7033 // A direct static reference to a global. 7034 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7035 Offset = 0; 7036 } else { 7037 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7038 } 7039 7040 if (Subtarget->isPICStyleRIPRel() && 7041 (M == CodeModel::Small || M == CodeModel::Kernel)) 7042 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7043 else 7044 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7045 7046 // With PIC, the address is actually $g + Offset. 7047 if (isGlobalRelativeToPICBase(OpFlags)) { 7048 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7049 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7050 Result); 7051 } 7052 7053 // For globals that require a load from a stub to get the address, emit the 7054 // load. 7055 if (isGlobalStubReference(OpFlags)) 7056 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7057 MachinePointerInfo::getGOT(), false, false, false, 0); 7058 7059 // If there was a non-zero offset that we didn't fold, create an explicit 7060 // addition for it. 7061 if (Offset != 0) 7062 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7063 DAG.getConstant(Offset, getPointerTy())); 7064 7065 return Result; 7066} 7067 7068SDValue 7069X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7070 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7071 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7072 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7073} 7074 7075static SDValue 7076GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7077 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7078 unsigned char OperandFlags) { 7079 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7080 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7081 DebugLoc dl = GA->getDebugLoc(); 7082 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7083 GA->getValueType(0), 7084 GA->getOffset(), 7085 OperandFlags); 7086 if (InFlag) { 7087 SDValue Ops[] = { Chain, TGA, *InFlag }; 7088 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7089 } else { 7090 SDValue Ops[] = { Chain, TGA }; 7091 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7092 } 7093 7094 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7095 MFI->setAdjustsStack(true); 7096 7097 SDValue Flag = Chain.getValue(1); 7098 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7099} 7100 7101// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7102static SDValue 7103LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7104 const EVT PtrVT) { 7105 SDValue InFlag; 7106 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7107 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7108 DAG.getNode(X86ISD::GlobalBaseReg, 7109 DebugLoc(), PtrVT), InFlag); 7110 InFlag = Chain.getValue(1); 7111 7112 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7113} 7114 7115// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7116static SDValue 7117LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7118 const EVT PtrVT) { 7119 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7120 X86::RAX, X86II::MO_TLSGD); 7121} 7122 7123// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7124// "local exec" model. 7125static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7126 const EVT PtrVT, TLSModel::Model model, 7127 bool is64Bit) { 7128 DebugLoc dl = GA->getDebugLoc(); 7129 7130 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7131 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7132 is64Bit ? 257 : 256)); 7133 7134 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7135 DAG.getIntPtrConstant(0), 7136 MachinePointerInfo(Ptr), 7137 false, false, false, 0); 7138 7139 unsigned char OperandFlags = 0; 7140 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7141 // initialexec. 7142 unsigned WrapperKind = X86ISD::Wrapper; 7143 if (model == TLSModel::LocalExec) { 7144 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7145 } else if (is64Bit) { 7146 assert(model == TLSModel::InitialExec); 7147 OperandFlags = X86II::MO_GOTTPOFF; 7148 WrapperKind = X86ISD::WrapperRIP; 7149 } else { 7150 assert(model == TLSModel::InitialExec); 7151 OperandFlags = X86II::MO_INDNTPOFF; 7152 } 7153 7154 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7155 // exec) 7156 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7157 GA->getValueType(0), 7158 GA->getOffset(), OperandFlags); 7159 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7160 7161 if (model == TLSModel::InitialExec) 7162 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7163 MachinePointerInfo::getGOT(), false, false, false, 0); 7164 7165 // The address of the thread local variable is the add of the thread 7166 // pointer with the offset of the variable. 7167 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7168} 7169 7170SDValue 7171X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7172 7173 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7174 const GlobalValue *GV = GA->getGlobal(); 7175 7176 if (Subtarget->isTargetELF()) { 7177 // TODO: implement the "local dynamic" model 7178 // TODO: implement the "initial exec"model for pic executables 7179 7180 // If GV is an alias then use the aliasee for determining 7181 // thread-localness. 7182 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7183 GV = GA->resolveAliasedGlobal(false); 7184 7185 TLSModel::Model model 7186 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7187 7188 switch (model) { 7189 case TLSModel::GeneralDynamic: 7190 case TLSModel::LocalDynamic: // not implemented 7191 if (Subtarget->is64Bit()) 7192 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7193 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7194 7195 case TLSModel::InitialExec: 7196 case TLSModel::LocalExec: 7197 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7198 Subtarget->is64Bit()); 7199 } 7200 } else if (Subtarget->isTargetDarwin()) { 7201 // Darwin only has one model of TLS. Lower to that. 7202 unsigned char OpFlag = 0; 7203 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7204 X86ISD::WrapperRIP : X86ISD::Wrapper; 7205 7206 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7207 // global base reg. 7208 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7209 !Subtarget->is64Bit(); 7210 if (PIC32) 7211 OpFlag = X86II::MO_TLVP_PIC_BASE; 7212 else 7213 OpFlag = X86II::MO_TLVP; 7214 DebugLoc DL = Op.getDebugLoc(); 7215 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7216 GA->getValueType(0), 7217 GA->getOffset(), OpFlag); 7218 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7219 7220 // With PIC32, the address is actually $g + Offset. 7221 if (PIC32) 7222 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7223 DAG.getNode(X86ISD::GlobalBaseReg, 7224 DebugLoc(), getPointerTy()), 7225 Offset); 7226 7227 // Lowering the machine isd will make sure everything is in the right 7228 // location. 7229 SDValue Chain = DAG.getEntryNode(); 7230 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7231 SDValue Args[] = { Chain, Offset }; 7232 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7233 7234 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7235 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7236 MFI->setAdjustsStack(true); 7237 7238 // And our return value (tls address) is in the standard call return value 7239 // location. 7240 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7241 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7242 Chain.getValue(1)); 7243 } else if (Subtarget->isTargetWindows()) { 7244 // Just use the implicit TLS architecture 7245 // Need to generate someting similar to: 7246 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7247 // ; from TEB 7248 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7249 // mov rcx, qword [rdx+rcx*8] 7250 // mov eax, .tls$:tlsvar 7251 // [rax+rcx] contains the address 7252 // Windows 64bit: gs:0x58 7253 // Windows 32bit: fs:__tls_array 7254 7255 // If GV is an alias then use the aliasee for determining 7256 // thread-localness. 7257 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7258 GV = GA->resolveAliasedGlobal(false); 7259 DebugLoc dl = GA->getDebugLoc(); 7260 SDValue Chain = DAG.getEntryNode(); 7261 7262 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7263 // %gs:0x58 (64-bit). 7264 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7265 ? Type::getInt8PtrTy(*DAG.getContext(), 7266 256) 7267 : Type::getInt32PtrTy(*DAG.getContext(), 7268 257)); 7269 7270 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7271 Subtarget->is64Bit() 7272 ? DAG.getIntPtrConstant(0x58) 7273 : DAG.getExternalSymbol("_tls_array", 7274 getPointerTy()), 7275 MachinePointerInfo(Ptr), 7276 false, false, false, 0); 7277 7278 // Load the _tls_index variable 7279 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7280 if (Subtarget->is64Bit()) 7281 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7282 IDX, MachinePointerInfo(), MVT::i32, 7283 false, false, 0); 7284 else 7285 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7286 false, false, false, 0); 7287 7288 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7289 getPointerTy()); 7290 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7291 7292 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7293 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7294 false, false, false, 0); 7295 7296 // Get the offset of start of .tls section 7297 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7298 GA->getValueType(0), 7299 GA->getOffset(), X86II::MO_SECREL); 7300 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7301 7302 // The address of the thread local variable is the add of the thread 7303 // pointer with the offset of the variable. 7304 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7305 } 7306 7307 llvm_unreachable("TLS not implemented for this target."); 7308} 7309 7310 7311/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7312/// and take a 2 x i32 value to shift plus a shift amount. 7313SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7314 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7315 EVT VT = Op.getValueType(); 7316 unsigned VTBits = VT.getSizeInBits(); 7317 DebugLoc dl = Op.getDebugLoc(); 7318 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7319 SDValue ShOpLo = Op.getOperand(0); 7320 SDValue ShOpHi = Op.getOperand(1); 7321 SDValue ShAmt = Op.getOperand(2); 7322 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7323 DAG.getConstant(VTBits - 1, MVT::i8)) 7324 : DAG.getConstant(0, VT); 7325 7326 SDValue Tmp2, Tmp3; 7327 if (Op.getOpcode() == ISD::SHL_PARTS) { 7328 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7329 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7330 } else { 7331 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7332 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7333 } 7334 7335 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7336 DAG.getConstant(VTBits, MVT::i8)); 7337 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7338 AndNode, DAG.getConstant(0, MVT::i8)); 7339 7340 SDValue Hi, Lo; 7341 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7342 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7343 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7344 7345 if (Op.getOpcode() == ISD::SHL_PARTS) { 7346 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7347 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7348 } else { 7349 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7350 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7351 } 7352 7353 SDValue Ops[2] = { Lo, Hi }; 7354 return DAG.getMergeValues(Ops, 2, dl); 7355} 7356 7357SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7358 SelectionDAG &DAG) const { 7359 EVT SrcVT = Op.getOperand(0).getValueType(); 7360 7361 if (SrcVT.isVector()) 7362 return SDValue(); 7363 7364 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7365 "Unknown SINT_TO_FP to lower!"); 7366 7367 // These are really Legal; return the operand so the caller accepts it as 7368 // Legal. 7369 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7370 return Op; 7371 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7372 Subtarget->is64Bit()) { 7373 return Op; 7374 } 7375 7376 DebugLoc dl = Op.getDebugLoc(); 7377 unsigned Size = SrcVT.getSizeInBits()/8; 7378 MachineFunction &MF = DAG.getMachineFunction(); 7379 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7380 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7381 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7382 StackSlot, 7383 MachinePointerInfo::getFixedStack(SSFI), 7384 false, false, 0); 7385 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7386} 7387 7388SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7389 SDValue StackSlot, 7390 SelectionDAG &DAG) const { 7391 // Build the FILD 7392 DebugLoc DL = Op.getDebugLoc(); 7393 SDVTList Tys; 7394 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7395 if (useSSE) 7396 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7397 else 7398 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7399 7400 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7401 7402 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7403 MachineMemOperand *MMO; 7404 if (FI) { 7405 int SSFI = FI->getIndex(); 7406 MMO = 7407 DAG.getMachineFunction() 7408 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7409 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7410 } else { 7411 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7412 StackSlot = StackSlot.getOperand(1); 7413 } 7414 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7415 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7416 X86ISD::FILD, DL, 7417 Tys, Ops, array_lengthof(Ops), 7418 SrcVT, MMO); 7419 7420 if (useSSE) { 7421 Chain = Result.getValue(1); 7422 SDValue InFlag = Result.getValue(2); 7423 7424 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7425 // shouldn't be necessary except that RFP cannot be live across 7426 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7427 MachineFunction &MF = DAG.getMachineFunction(); 7428 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7429 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7430 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7431 Tys = DAG.getVTList(MVT::Other); 7432 SDValue Ops[] = { 7433 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7434 }; 7435 MachineMemOperand *MMO = 7436 DAG.getMachineFunction() 7437 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7438 MachineMemOperand::MOStore, SSFISize, SSFISize); 7439 7440 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7441 Ops, array_lengthof(Ops), 7442 Op.getValueType(), MMO); 7443 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7444 MachinePointerInfo::getFixedStack(SSFI), 7445 false, false, false, 0); 7446 } 7447 7448 return Result; 7449} 7450 7451// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7452SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7453 SelectionDAG &DAG) const { 7454 // This algorithm is not obvious. Here it is what we're trying to output: 7455 /* 7456 movq %rax, %xmm0 7457 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7458 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7459 #ifdef __SSE3__ 7460 haddpd %xmm0, %xmm0 7461 #else 7462 pshufd $0x4e, %xmm0, %xmm1 7463 addpd %xmm1, %xmm0 7464 #endif 7465 */ 7466 7467 DebugLoc dl = Op.getDebugLoc(); 7468 LLVMContext *Context = DAG.getContext(); 7469 7470 // Build some magic constants. 7471 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7472 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7473 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7474 7475 SmallVector<Constant*,2> CV1; 7476 CV1.push_back( 7477 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7478 CV1.push_back( 7479 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7480 Constant *C1 = ConstantVector::get(CV1); 7481 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7482 7483 // Load the 64-bit value into an XMM register. 7484 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7485 Op.getOperand(0)); 7486 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7487 MachinePointerInfo::getConstantPool(), 7488 false, false, false, 16); 7489 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7490 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7491 CLod0); 7492 7493 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7494 MachinePointerInfo::getConstantPool(), 7495 false, false, false, 16); 7496 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7497 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7498 SDValue Result; 7499 7500 if (Subtarget->hasSSE3()) { 7501 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7502 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7503 } else { 7504 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7505 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7506 S2F, 0x4E, DAG); 7507 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7508 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7509 Sub); 7510 } 7511 7512 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7513 DAG.getIntPtrConstant(0)); 7514} 7515 7516// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7517SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7518 SelectionDAG &DAG) const { 7519 DebugLoc dl = Op.getDebugLoc(); 7520 // FP constant to bias correct the final result. 7521 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7522 MVT::f64); 7523 7524 // Load the 32-bit value into an XMM register. 7525 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7526 Op.getOperand(0)); 7527 7528 // Zero out the upper parts of the register. 7529 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7530 7531 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7532 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7533 DAG.getIntPtrConstant(0)); 7534 7535 // Or the load with the bias. 7536 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7537 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7538 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7539 MVT::v2f64, Load)), 7540 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7541 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7542 MVT::v2f64, Bias))); 7543 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7544 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7545 DAG.getIntPtrConstant(0)); 7546 7547 // Subtract the bias. 7548 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7549 7550 // Handle final rounding. 7551 EVT DestVT = Op.getValueType(); 7552 7553 if (DestVT.bitsLT(MVT::f64)) { 7554 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7555 DAG.getIntPtrConstant(0)); 7556 } else if (DestVT.bitsGT(MVT::f64)) { 7557 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7558 } 7559 7560 // Handle final rounding. 7561 return Sub; 7562} 7563 7564SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7565 SelectionDAG &DAG) const { 7566 SDValue N0 = Op.getOperand(0); 7567 DebugLoc dl = Op.getDebugLoc(); 7568 7569 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7570 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7571 // the optimization here. 7572 if (DAG.SignBitIsZero(N0)) 7573 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7574 7575 EVT SrcVT = N0.getValueType(); 7576 EVT DstVT = Op.getValueType(); 7577 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7578 return LowerUINT_TO_FP_i64(Op, DAG); 7579 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7580 return LowerUINT_TO_FP_i32(Op, DAG); 7581 else if (Subtarget->is64Bit() && 7582 SrcVT == MVT::i64 && DstVT == MVT::f32) 7583 return SDValue(); 7584 7585 // Make a 64-bit buffer, and use it to build an FILD. 7586 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7587 if (SrcVT == MVT::i32) { 7588 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7589 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7590 getPointerTy(), StackSlot, WordOff); 7591 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7592 StackSlot, MachinePointerInfo(), 7593 false, false, 0); 7594 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7595 OffsetSlot, MachinePointerInfo(), 7596 false, false, 0); 7597 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7598 return Fild; 7599 } 7600 7601 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7602 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7603 StackSlot, MachinePointerInfo(), 7604 false, false, 0); 7605 // For i64 source, we need to add the appropriate power of 2 if the input 7606 // was negative. This is the same as the optimization in 7607 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7608 // we must be careful to do the computation in x87 extended precision, not 7609 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7610 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7611 MachineMemOperand *MMO = 7612 DAG.getMachineFunction() 7613 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7614 MachineMemOperand::MOLoad, 8, 8); 7615 7616 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7617 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7618 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7619 MVT::i64, MMO); 7620 7621 APInt FF(32, 0x5F800000ULL); 7622 7623 // Check whether the sign bit is set. 7624 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7625 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7626 ISD::SETLT); 7627 7628 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7629 SDValue FudgePtr = DAG.getConstantPool( 7630 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7631 getPointerTy()); 7632 7633 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7634 SDValue Zero = DAG.getIntPtrConstant(0); 7635 SDValue Four = DAG.getIntPtrConstant(4); 7636 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7637 Zero, Four); 7638 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7639 7640 // Load the value out, extending it from f32 to f80. 7641 // FIXME: Avoid the extend by constructing the right constant pool? 7642 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7643 FudgePtr, MachinePointerInfo::getConstantPool(), 7644 MVT::f32, false, false, 4); 7645 // Extend everything to 80 bits to force it to be done on x87. 7646 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7647 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7648} 7649 7650std::pair<SDValue,SDValue> X86TargetLowering:: 7651FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7652 DebugLoc DL = Op.getDebugLoc(); 7653 7654 EVT DstTy = Op.getValueType(); 7655 7656 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7657 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7658 DstTy = MVT::i64; 7659 } 7660 7661 assert(DstTy.getSimpleVT() <= MVT::i64 && 7662 DstTy.getSimpleVT() >= MVT::i16 && 7663 "Unknown FP_TO_INT to lower!"); 7664 7665 // These are really Legal. 7666 if (DstTy == MVT::i32 && 7667 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7668 return std::make_pair(SDValue(), SDValue()); 7669 if (Subtarget->is64Bit() && 7670 DstTy == MVT::i64 && 7671 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7672 return std::make_pair(SDValue(), SDValue()); 7673 7674 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7675 // stack slot, or into the FTOL runtime function. 7676 MachineFunction &MF = DAG.getMachineFunction(); 7677 unsigned MemSize = DstTy.getSizeInBits()/8; 7678 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7679 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7680 7681 unsigned Opc; 7682 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7683 Opc = X86ISD::WIN_FTOL; 7684 else 7685 switch (DstTy.getSimpleVT().SimpleTy) { 7686 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7687 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7688 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7689 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7690 } 7691 7692 SDValue Chain = DAG.getEntryNode(); 7693 SDValue Value = Op.getOperand(0); 7694 EVT TheVT = Op.getOperand(0).getValueType(); 7695 // FIXME This causes a redundant load/store if the SSE-class value is already 7696 // in memory, such as if it is on the callstack. 7697 if (isScalarFPTypeInSSEReg(TheVT)) { 7698 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7699 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7700 MachinePointerInfo::getFixedStack(SSFI), 7701 false, false, 0); 7702 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7703 SDValue Ops[] = { 7704 Chain, StackSlot, DAG.getValueType(TheVT) 7705 }; 7706 7707 MachineMemOperand *MMO = 7708 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7709 MachineMemOperand::MOLoad, MemSize, MemSize); 7710 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7711 DstTy, MMO); 7712 Chain = Value.getValue(1); 7713 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7714 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7715 } 7716 7717 MachineMemOperand *MMO = 7718 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7719 MachineMemOperand::MOStore, MemSize, MemSize); 7720 7721 if (Opc != X86ISD::WIN_FTOL) { 7722 // Build the FP_TO_INT*_IN_MEM 7723 SDValue Ops[] = { Chain, Value, StackSlot }; 7724 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7725 Ops, 3, DstTy, MMO); 7726 return std::make_pair(FIST, StackSlot); 7727 } else { 7728 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7729 DAG.getVTList(MVT::Other, MVT::Glue), 7730 Chain, Value); 7731 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7732 MVT::i32, ftol.getValue(1)); 7733 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7734 MVT::i32, eax.getValue(2)); 7735 SDValue Ops[] = { eax, edx }; 7736 SDValue pair = IsReplace 7737 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7738 : DAG.getMergeValues(Ops, 2, DL); 7739 return std::make_pair(pair, SDValue()); 7740 } 7741} 7742 7743SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7744 SelectionDAG &DAG) const { 7745 if (Op.getValueType().isVector()) 7746 return SDValue(); 7747 7748 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7749 /*IsSigned=*/ true, /*IsReplace=*/ false); 7750 SDValue FIST = Vals.first, StackSlot = Vals.second; 7751 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7752 if (FIST.getNode() == 0) return Op; 7753 7754 if (StackSlot.getNode()) 7755 // Load the result. 7756 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7757 FIST, StackSlot, MachinePointerInfo(), 7758 false, false, false, 0); 7759 else 7760 // The node is the result. 7761 return FIST; 7762} 7763 7764SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7765 SelectionDAG &DAG) const { 7766 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7767 /*IsSigned=*/ false, /*IsReplace=*/ false); 7768 SDValue FIST = Vals.first, StackSlot = Vals.second; 7769 assert(FIST.getNode() && "Unexpected failure"); 7770 7771 if (StackSlot.getNode()) 7772 // Load the result. 7773 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7774 FIST, StackSlot, MachinePointerInfo(), 7775 false, false, false, 0); 7776 else 7777 // The node is the result. 7778 return FIST; 7779} 7780 7781SDValue X86TargetLowering::LowerFABS(SDValue Op, 7782 SelectionDAG &DAG) const { 7783 LLVMContext *Context = DAG.getContext(); 7784 DebugLoc dl = Op.getDebugLoc(); 7785 EVT VT = Op.getValueType(); 7786 EVT EltVT = VT; 7787 if (VT.isVector()) 7788 EltVT = VT.getVectorElementType(); 7789 Constant *C; 7790 if (EltVT == MVT::f64) { 7791 C = ConstantVector::getSplat(2, 7792 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7793 } else { 7794 C = ConstantVector::getSplat(4, 7795 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7796 } 7797 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7798 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7799 MachinePointerInfo::getConstantPool(), 7800 false, false, false, 16); 7801 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7802} 7803 7804SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7805 LLVMContext *Context = DAG.getContext(); 7806 DebugLoc dl = Op.getDebugLoc(); 7807 EVT VT = Op.getValueType(); 7808 EVT EltVT = VT; 7809 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7810 if (VT.isVector()) { 7811 EltVT = VT.getVectorElementType(); 7812 NumElts = VT.getVectorNumElements(); 7813 } 7814 Constant *C; 7815 if (EltVT == MVT::f64) 7816 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7817 else 7818 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7819 C = ConstantVector::getSplat(NumElts, C); 7820 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7821 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7822 MachinePointerInfo::getConstantPool(), 7823 false, false, false, 16); 7824 if (VT.isVector()) { 7825 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7826 return DAG.getNode(ISD::BITCAST, dl, VT, 7827 DAG.getNode(ISD::XOR, dl, XORVT, 7828 DAG.getNode(ISD::BITCAST, dl, XORVT, 7829 Op.getOperand(0)), 7830 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7831 } else { 7832 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7833 } 7834} 7835 7836SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7837 LLVMContext *Context = DAG.getContext(); 7838 SDValue Op0 = Op.getOperand(0); 7839 SDValue Op1 = Op.getOperand(1); 7840 DebugLoc dl = Op.getDebugLoc(); 7841 EVT VT = Op.getValueType(); 7842 EVT SrcVT = Op1.getValueType(); 7843 7844 // If second operand is smaller, extend it first. 7845 if (SrcVT.bitsLT(VT)) { 7846 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7847 SrcVT = VT; 7848 } 7849 // And if it is bigger, shrink it first. 7850 if (SrcVT.bitsGT(VT)) { 7851 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7852 SrcVT = VT; 7853 } 7854 7855 // At this point the operands and the result should have the same 7856 // type, and that won't be f80 since that is not custom lowered. 7857 7858 // First get the sign bit of second operand. 7859 SmallVector<Constant*,4> CV; 7860 if (SrcVT == MVT::f64) { 7861 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7862 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7863 } else { 7864 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7865 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7866 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7867 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7868 } 7869 Constant *C = ConstantVector::get(CV); 7870 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7871 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7872 MachinePointerInfo::getConstantPool(), 7873 false, false, false, 16); 7874 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7875 7876 // Shift sign bit right or left if the two operands have different types. 7877 if (SrcVT.bitsGT(VT)) { 7878 // Op0 is MVT::f32, Op1 is MVT::f64. 7879 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7880 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7881 DAG.getConstant(32, MVT::i32)); 7882 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7883 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7884 DAG.getIntPtrConstant(0)); 7885 } 7886 7887 // Clear first operand sign bit. 7888 CV.clear(); 7889 if (VT == MVT::f64) { 7890 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7891 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7892 } else { 7893 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7894 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7895 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7896 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7897 } 7898 C = ConstantVector::get(CV); 7899 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7900 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7901 MachinePointerInfo::getConstantPool(), 7902 false, false, false, 16); 7903 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7904 7905 // Or the value with the sign bit. 7906 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7907} 7908 7909SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7910 SDValue N0 = Op.getOperand(0); 7911 DebugLoc dl = Op.getDebugLoc(); 7912 EVT VT = Op.getValueType(); 7913 7914 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 7915 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 7916 DAG.getConstant(1, VT)); 7917 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 7918} 7919 7920/// Emit nodes that will be selected as "test Op0,Op0", or something 7921/// equivalent. 7922SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 7923 SelectionDAG &DAG) const { 7924 DebugLoc dl = Op.getDebugLoc(); 7925 7926 // CF and OF aren't always set the way we want. Determine which 7927 // of these we need. 7928 bool NeedCF = false; 7929 bool NeedOF = false; 7930 switch (X86CC) { 7931 default: break; 7932 case X86::COND_A: case X86::COND_AE: 7933 case X86::COND_B: case X86::COND_BE: 7934 NeedCF = true; 7935 break; 7936 case X86::COND_G: case X86::COND_GE: 7937 case X86::COND_L: case X86::COND_LE: 7938 case X86::COND_O: case X86::COND_NO: 7939 NeedOF = true; 7940 break; 7941 } 7942 7943 // See if we can use the EFLAGS value from the operand instead of 7944 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 7945 // we prove that the arithmetic won't overflow, we can't use OF or CF. 7946 if (Op.getResNo() != 0 || NeedOF || NeedCF) 7947 // Emit a CMP with 0, which is the TEST pattern. 7948 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7949 DAG.getConstant(0, Op.getValueType())); 7950 7951 unsigned Opcode = 0; 7952 unsigned NumOperands = 0; 7953 switch (Op.getNode()->getOpcode()) { 7954 case ISD::ADD: 7955 // Due to an isel shortcoming, be conservative if this add is likely to be 7956 // selected as part of a load-modify-store instruction. When the root node 7957 // in a match is a store, isel doesn't know how to remap non-chain non-flag 7958 // uses of other nodes in the match, such as the ADD in this case. This 7959 // leads to the ADD being left around and reselected, with the result being 7960 // two adds in the output. Alas, even if none our users are stores, that 7961 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 7962 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 7963 // climbing the DAG back to the root, and it doesn't seem to be worth the 7964 // effort. 7965 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7966 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7967 if (UI->getOpcode() != ISD::CopyToReg && 7968 UI->getOpcode() != ISD::SETCC && 7969 UI->getOpcode() != ISD::STORE) 7970 goto default_case; 7971 7972 if (ConstantSDNode *C = 7973 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 7974 // An add of one will be selected as an INC. 7975 if (C->getAPIntValue() == 1) { 7976 Opcode = X86ISD::INC; 7977 NumOperands = 1; 7978 break; 7979 } 7980 7981 // An add of negative one (subtract of one) will be selected as a DEC. 7982 if (C->getAPIntValue().isAllOnesValue()) { 7983 Opcode = X86ISD::DEC; 7984 NumOperands = 1; 7985 break; 7986 } 7987 } 7988 7989 // Otherwise use a regular EFLAGS-setting add. 7990 Opcode = X86ISD::ADD; 7991 NumOperands = 2; 7992 break; 7993 case ISD::AND: { 7994 // If the primary and result isn't used, don't bother using X86ISD::AND, 7995 // because a TEST instruction will be better. 7996 bool NonFlagUse = false; 7997 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7998 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 7999 SDNode *User = *UI; 8000 unsigned UOpNo = UI.getOperandNo(); 8001 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8002 // Look pass truncate. 8003 UOpNo = User->use_begin().getOperandNo(); 8004 User = *User->use_begin(); 8005 } 8006 8007 if (User->getOpcode() != ISD::BRCOND && 8008 User->getOpcode() != ISD::SETCC && 8009 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8010 NonFlagUse = true; 8011 break; 8012 } 8013 } 8014 8015 if (!NonFlagUse) 8016 break; 8017 } 8018 // FALL THROUGH 8019 case ISD::SUB: 8020 case ISD::OR: 8021 case ISD::XOR: 8022 // Due to the ISEL shortcoming noted above, be conservative if this op is 8023 // likely to be selected as part of a load-modify-store instruction. 8024 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8025 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8026 if (UI->getOpcode() == ISD::STORE) 8027 goto default_case; 8028 8029 // Otherwise use a regular EFLAGS-setting instruction. 8030 switch (Op.getNode()->getOpcode()) { 8031 default: llvm_unreachable("unexpected operator!"); 8032 case ISD::SUB: Opcode = X86ISD::SUB; break; 8033 case ISD::OR: Opcode = X86ISD::OR; break; 8034 case ISD::XOR: Opcode = X86ISD::XOR; break; 8035 case ISD::AND: Opcode = X86ISD::AND; break; 8036 } 8037 8038 NumOperands = 2; 8039 break; 8040 case X86ISD::ADD: 8041 case X86ISD::SUB: 8042 case X86ISD::INC: 8043 case X86ISD::DEC: 8044 case X86ISD::OR: 8045 case X86ISD::XOR: 8046 case X86ISD::AND: 8047 return SDValue(Op.getNode(), 1); 8048 default: 8049 default_case: 8050 break; 8051 } 8052 8053 if (Opcode == 0) 8054 // Emit a CMP with 0, which is the TEST pattern. 8055 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8056 DAG.getConstant(0, Op.getValueType())); 8057 8058 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8059 SmallVector<SDValue, 4> Ops; 8060 for (unsigned i = 0; i != NumOperands; ++i) 8061 Ops.push_back(Op.getOperand(i)); 8062 8063 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8064 DAG.ReplaceAllUsesWith(Op, New); 8065 return SDValue(New.getNode(), 1); 8066} 8067 8068/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8069/// equivalent. 8070SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8071 SelectionDAG &DAG) const { 8072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8073 if (C->getAPIntValue() == 0) 8074 return EmitTest(Op0, X86CC, DAG); 8075 8076 DebugLoc dl = Op0.getDebugLoc(); 8077 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8078} 8079 8080/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8081/// if it's possible. 8082SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8083 DebugLoc dl, SelectionDAG &DAG) const { 8084 SDValue Op0 = And.getOperand(0); 8085 SDValue Op1 = And.getOperand(1); 8086 if (Op0.getOpcode() == ISD::TRUNCATE) 8087 Op0 = Op0.getOperand(0); 8088 if (Op1.getOpcode() == ISD::TRUNCATE) 8089 Op1 = Op1.getOperand(0); 8090 8091 SDValue LHS, RHS; 8092 if (Op1.getOpcode() == ISD::SHL) 8093 std::swap(Op0, Op1); 8094 if (Op0.getOpcode() == ISD::SHL) { 8095 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8096 if (And00C->getZExtValue() == 1) { 8097 // If we looked past a truncate, check that it's only truncating away 8098 // known zeros. 8099 unsigned BitWidth = Op0.getValueSizeInBits(); 8100 unsigned AndBitWidth = And.getValueSizeInBits(); 8101 if (BitWidth > AndBitWidth) { 8102 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8103 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8104 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8105 return SDValue(); 8106 } 8107 LHS = Op1; 8108 RHS = Op0.getOperand(1); 8109 } 8110 } else if (Op1.getOpcode() == ISD::Constant) { 8111 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8112 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8113 SDValue AndLHS = Op0; 8114 8115 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8116 LHS = AndLHS.getOperand(0); 8117 RHS = AndLHS.getOperand(1); 8118 } 8119 8120 // Use BT if the immediate can't be encoded in a TEST instruction. 8121 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8122 LHS = AndLHS; 8123 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8124 } 8125 } 8126 8127 if (LHS.getNode()) { 8128 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8129 // instruction. Since the shift amount is in-range-or-undefined, we know 8130 // that doing a bittest on the i32 value is ok. We extend to i32 because 8131 // the encoding for the i16 version is larger than the i32 version. 8132 // Also promote i16 to i32 for performance / code size reason. 8133 if (LHS.getValueType() == MVT::i8 || 8134 LHS.getValueType() == MVT::i16) 8135 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8136 8137 // If the operand types disagree, extend the shift amount to match. Since 8138 // BT ignores high bits (like shifts) we can use anyextend. 8139 if (LHS.getValueType() != RHS.getValueType()) 8140 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8141 8142 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8143 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8144 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8145 DAG.getConstant(Cond, MVT::i8), BT); 8146 } 8147 8148 return SDValue(); 8149} 8150 8151SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8152 8153 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8154 8155 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8156 SDValue Op0 = Op.getOperand(0); 8157 SDValue Op1 = Op.getOperand(1); 8158 DebugLoc dl = Op.getDebugLoc(); 8159 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8160 8161 // Optimize to BT if possible. 8162 // Lower (X & (1 << N)) == 0 to BT(X, N). 8163 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8164 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8165 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8166 Op1.getOpcode() == ISD::Constant && 8167 cast<ConstantSDNode>(Op1)->isNullValue() && 8168 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8169 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8170 if (NewSetCC.getNode()) 8171 return NewSetCC; 8172 } 8173 8174 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8175 // these. 8176 if (Op1.getOpcode() == ISD::Constant && 8177 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8178 cast<ConstantSDNode>(Op1)->isNullValue()) && 8179 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8180 8181 // If the input is a setcc, then reuse the input setcc or use a new one with 8182 // the inverted condition. 8183 if (Op0.getOpcode() == X86ISD::SETCC) { 8184 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8185 bool Invert = (CC == ISD::SETNE) ^ 8186 cast<ConstantSDNode>(Op1)->isNullValue(); 8187 if (!Invert) return Op0; 8188 8189 CCode = X86::GetOppositeBranchCondition(CCode); 8190 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8191 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8192 } 8193 } 8194 8195 bool isFP = Op1.getValueType().isFloatingPoint(); 8196 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8197 if (X86CC == X86::COND_INVALID) 8198 return SDValue(); 8199 8200 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8201 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8202 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8203} 8204 8205// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8206// ones, and then concatenate the result back. 8207static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8208 EVT VT = Op.getValueType(); 8209 8210 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8211 "Unsupported value type for operation"); 8212 8213 int NumElems = VT.getVectorNumElements(); 8214 DebugLoc dl = Op.getDebugLoc(); 8215 SDValue CC = Op.getOperand(2); 8216 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8217 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8218 8219 // Extract the LHS vectors 8220 SDValue LHS = Op.getOperand(0); 8221 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8222 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8223 8224 // Extract the RHS vectors 8225 SDValue RHS = Op.getOperand(1); 8226 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8227 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8228 8229 // Issue the operation on the smaller types and concatenate the result back 8230 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8231 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8232 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8233 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8234 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8235} 8236 8237 8238SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8239 SDValue Cond; 8240 SDValue Op0 = Op.getOperand(0); 8241 SDValue Op1 = Op.getOperand(1); 8242 SDValue CC = Op.getOperand(2); 8243 EVT VT = Op.getValueType(); 8244 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8245 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8246 DebugLoc dl = Op.getDebugLoc(); 8247 8248 if (isFP) { 8249 unsigned SSECC = 8; 8250 EVT EltVT = Op0.getValueType().getVectorElementType(); 8251 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8252 8253 bool Swap = false; 8254 8255 // SSE Condition code mapping: 8256 // 0 - EQ 8257 // 1 - LT 8258 // 2 - LE 8259 // 3 - UNORD 8260 // 4 - NEQ 8261 // 5 - NLT 8262 // 6 - NLE 8263 // 7 - ORD 8264 switch (SetCCOpcode) { 8265 default: break; 8266 case ISD::SETOEQ: 8267 case ISD::SETEQ: SSECC = 0; break; 8268 case ISD::SETOGT: 8269 case ISD::SETGT: Swap = true; // Fallthrough 8270 case ISD::SETLT: 8271 case ISD::SETOLT: SSECC = 1; break; 8272 case ISD::SETOGE: 8273 case ISD::SETGE: Swap = true; // Fallthrough 8274 case ISD::SETLE: 8275 case ISD::SETOLE: SSECC = 2; break; 8276 case ISD::SETUO: SSECC = 3; break; 8277 case ISD::SETUNE: 8278 case ISD::SETNE: SSECC = 4; break; 8279 case ISD::SETULE: Swap = true; 8280 case ISD::SETUGE: SSECC = 5; break; 8281 case ISD::SETULT: Swap = true; 8282 case ISD::SETUGT: SSECC = 6; break; 8283 case ISD::SETO: SSECC = 7; break; 8284 } 8285 if (Swap) 8286 std::swap(Op0, Op1); 8287 8288 // In the two special cases we can't handle, emit two comparisons. 8289 if (SSECC == 8) { 8290 if (SetCCOpcode == ISD::SETUEQ) { 8291 SDValue UNORD, EQ; 8292 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8293 DAG.getConstant(3, MVT::i8)); 8294 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8295 DAG.getConstant(0, MVT::i8)); 8296 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8297 } else if (SetCCOpcode == ISD::SETONE) { 8298 SDValue ORD, NEQ; 8299 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8300 DAG.getConstant(7, MVT::i8)); 8301 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8302 DAG.getConstant(4, MVT::i8)); 8303 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8304 } 8305 llvm_unreachable("Illegal FP comparison"); 8306 } 8307 // Handle all other FP comparisons here. 8308 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8309 DAG.getConstant(SSECC, MVT::i8)); 8310 } 8311 8312 // Break 256-bit integer vector compare into smaller ones. 8313 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8314 return Lower256IntVSETCC(Op, DAG); 8315 8316 // We are handling one of the integer comparisons here. Since SSE only has 8317 // GT and EQ comparisons for integer, swapping operands and multiple 8318 // operations may be required for some comparisons. 8319 unsigned Opc = 0; 8320 bool Swap = false, Invert = false, FlipSigns = false; 8321 8322 switch (SetCCOpcode) { 8323 default: break; 8324 case ISD::SETNE: Invert = true; 8325 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8326 case ISD::SETLT: Swap = true; 8327 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8328 case ISD::SETGE: Swap = true; 8329 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8330 case ISD::SETULT: Swap = true; 8331 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8332 case ISD::SETUGE: Swap = true; 8333 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8334 } 8335 if (Swap) 8336 std::swap(Op0, Op1); 8337 8338 // Check that the operation in question is available (most are plain SSE2, 8339 // but PCMPGTQ and PCMPEQQ have different requirements). 8340 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8341 return SDValue(); 8342 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8343 return SDValue(); 8344 8345 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8346 // bits of the inputs before performing those operations. 8347 if (FlipSigns) { 8348 EVT EltVT = VT.getVectorElementType(); 8349 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8350 EltVT); 8351 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8352 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8353 SignBits.size()); 8354 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8355 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8356 } 8357 8358 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8359 8360 // If the logical-not of the result is required, perform that now. 8361 if (Invert) 8362 Result = DAG.getNOT(dl, Result, VT); 8363 8364 return Result; 8365} 8366 8367// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8368static bool isX86LogicalCmp(SDValue Op) { 8369 unsigned Opc = Op.getNode()->getOpcode(); 8370 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8371 return true; 8372 if (Op.getResNo() == 1 && 8373 (Opc == X86ISD::ADD || 8374 Opc == X86ISD::SUB || 8375 Opc == X86ISD::ADC || 8376 Opc == X86ISD::SBB || 8377 Opc == X86ISD::SMUL || 8378 Opc == X86ISD::UMUL || 8379 Opc == X86ISD::INC || 8380 Opc == X86ISD::DEC || 8381 Opc == X86ISD::OR || 8382 Opc == X86ISD::XOR || 8383 Opc == X86ISD::AND)) 8384 return true; 8385 8386 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8387 return true; 8388 8389 return false; 8390} 8391 8392static bool isZero(SDValue V) { 8393 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8394 return C && C->isNullValue(); 8395} 8396 8397static bool isAllOnes(SDValue V) { 8398 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8399 return C && C->isAllOnesValue(); 8400} 8401 8402SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8403 bool addTest = true; 8404 SDValue Cond = Op.getOperand(0); 8405 SDValue Op1 = Op.getOperand(1); 8406 SDValue Op2 = Op.getOperand(2); 8407 DebugLoc DL = Op.getDebugLoc(); 8408 SDValue CC; 8409 8410 if (Cond.getOpcode() == ISD::SETCC) { 8411 SDValue NewCond = LowerSETCC(Cond, DAG); 8412 if (NewCond.getNode()) 8413 Cond = NewCond; 8414 } 8415 8416 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8417 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8418 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8419 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8420 if (Cond.getOpcode() == X86ISD::SETCC && 8421 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8422 isZero(Cond.getOperand(1).getOperand(1))) { 8423 SDValue Cmp = Cond.getOperand(1); 8424 8425 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8426 8427 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8428 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8429 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8430 8431 SDValue CmpOp0 = Cmp.getOperand(0); 8432 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8433 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8434 8435 SDValue Res = // Res = 0 or -1. 8436 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8437 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8438 8439 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8440 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8441 8442 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8443 if (N2C == 0 || !N2C->isNullValue()) 8444 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8445 return Res; 8446 } 8447 } 8448 8449 // Look past (and (setcc_carry (cmp ...)), 1). 8450 if (Cond.getOpcode() == ISD::AND && 8451 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8452 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8453 if (C && C->getAPIntValue() == 1) 8454 Cond = Cond.getOperand(0); 8455 } 8456 8457 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8458 // setting operand in place of the X86ISD::SETCC. 8459 unsigned CondOpcode = Cond.getOpcode(); 8460 if (CondOpcode == X86ISD::SETCC || 8461 CondOpcode == X86ISD::SETCC_CARRY) { 8462 CC = Cond.getOperand(0); 8463 8464 SDValue Cmp = Cond.getOperand(1); 8465 unsigned Opc = Cmp.getOpcode(); 8466 EVT VT = Op.getValueType(); 8467 8468 bool IllegalFPCMov = false; 8469 if (VT.isFloatingPoint() && !VT.isVector() && 8470 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8471 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8472 8473 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8474 Opc == X86ISD::BT) { // FIXME 8475 Cond = Cmp; 8476 addTest = false; 8477 } 8478 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8479 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8480 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8481 Cond.getOperand(0).getValueType() != MVT::i8)) { 8482 SDValue LHS = Cond.getOperand(0); 8483 SDValue RHS = Cond.getOperand(1); 8484 unsigned X86Opcode; 8485 unsigned X86Cond; 8486 SDVTList VTs; 8487 switch (CondOpcode) { 8488 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8489 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8490 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8491 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8492 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8493 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8494 default: llvm_unreachable("unexpected overflowing operator"); 8495 } 8496 if (CondOpcode == ISD::UMULO) 8497 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8498 MVT::i32); 8499 else 8500 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8501 8502 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8503 8504 if (CondOpcode == ISD::UMULO) 8505 Cond = X86Op.getValue(2); 8506 else 8507 Cond = X86Op.getValue(1); 8508 8509 CC = DAG.getConstant(X86Cond, MVT::i8); 8510 addTest = false; 8511 } 8512 8513 if (addTest) { 8514 // Look pass the truncate. 8515 if (Cond.getOpcode() == ISD::TRUNCATE) 8516 Cond = Cond.getOperand(0); 8517 8518 // We know the result of AND is compared against zero. Try to match 8519 // it to BT. 8520 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8521 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8522 if (NewSetCC.getNode()) { 8523 CC = NewSetCC.getOperand(0); 8524 Cond = NewSetCC.getOperand(1); 8525 addTest = false; 8526 } 8527 } 8528 } 8529 8530 if (addTest) { 8531 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8532 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8533 } 8534 8535 // a < b ? -1 : 0 -> RES = ~setcc_carry 8536 // a < b ? 0 : -1 -> RES = setcc_carry 8537 // a >= b ? -1 : 0 -> RES = setcc_carry 8538 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8539 if (Cond.getOpcode() == X86ISD::CMP) { 8540 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8541 8542 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8543 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8544 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8545 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8546 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8547 return DAG.getNOT(DL, Res, Res.getValueType()); 8548 return Res; 8549 } 8550 } 8551 8552 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8553 // condition is true. 8554 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8555 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8556 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8557} 8558 8559// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8560// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8561// from the AND / OR. 8562static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8563 Opc = Op.getOpcode(); 8564 if (Opc != ISD::OR && Opc != ISD::AND) 8565 return false; 8566 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8567 Op.getOperand(0).hasOneUse() && 8568 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8569 Op.getOperand(1).hasOneUse()); 8570} 8571 8572// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8573// 1 and that the SETCC node has a single use. 8574static bool isXor1OfSetCC(SDValue Op) { 8575 if (Op.getOpcode() != ISD::XOR) 8576 return false; 8577 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8578 if (N1C && N1C->getAPIntValue() == 1) { 8579 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8580 Op.getOperand(0).hasOneUse(); 8581 } 8582 return false; 8583} 8584 8585SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8586 bool addTest = true; 8587 SDValue Chain = Op.getOperand(0); 8588 SDValue Cond = Op.getOperand(1); 8589 SDValue Dest = Op.getOperand(2); 8590 DebugLoc dl = Op.getDebugLoc(); 8591 SDValue CC; 8592 bool Inverted = false; 8593 8594 if (Cond.getOpcode() == ISD::SETCC) { 8595 // Check for setcc([su]{add,sub,mul}o == 0). 8596 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8597 isa<ConstantSDNode>(Cond.getOperand(1)) && 8598 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8599 Cond.getOperand(0).getResNo() == 1 && 8600 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8601 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8602 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8603 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8604 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8605 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8606 Inverted = true; 8607 Cond = Cond.getOperand(0); 8608 } else { 8609 SDValue NewCond = LowerSETCC(Cond, DAG); 8610 if (NewCond.getNode()) 8611 Cond = NewCond; 8612 } 8613 } 8614#if 0 8615 // FIXME: LowerXALUO doesn't handle these!! 8616 else if (Cond.getOpcode() == X86ISD::ADD || 8617 Cond.getOpcode() == X86ISD::SUB || 8618 Cond.getOpcode() == X86ISD::SMUL || 8619 Cond.getOpcode() == X86ISD::UMUL) 8620 Cond = LowerXALUO(Cond, DAG); 8621#endif 8622 8623 // Look pass (and (setcc_carry (cmp ...)), 1). 8624 if (Cond.getOpcode() == ISD::AND && 8625 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8626 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8627 if (C && C->getAPIntValue() == 1) 8628 Cond = Cond.getOperand(0); 8629 } 8630 8631 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8632 // setting operand in place of the X86ISD::SETCC. 8633 unsigned CondOpcode = Cond.getOpcode(); 8634 if (CondOpcode == X86ISD::SETCC || 8635 CondOpcode == X86ISD::SETCC_CARRY) { 8636 CC = Cond.getOperand(0); 8637 8638 SDValue Cmp = Cond.getOperand(1); 8639 unsigned Opc = Cmp.getOpcode(); 8640 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8641 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8642 Cond = Cmp; 8643 addTest = false; 8644 } else { 8645 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8646 default: break; 8647 case X86::COND_O: 8648 case X86::COND_B: 8649 // These can only come from an arithmetic instruction with overflow, 8650 // e.g. SADDO, UADDO. 8651 Cond = Cond.getNode()->getOperand(1); 8652 addTest = false; 8653 break; 8654 } 8655 } 8656 } 8657 CondOpcode = Cond.getOpcode(); 8658 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8659 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8660 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8661 Cond.getOperand(0).getValueType() != MVT::i8)) { 8662 SDValue LHS = Cond.getOperand(0); 8663 SDValue RHS = Cond.getOperand(1); 8664 unsigned X86Opcode; 8665 unsigned X86Cond; 8666 SDVTList VTs; 8667 switch (CondOpcode) { 8668 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8669 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8670 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8671 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8672 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8673 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8674 default: llvm_unreachable("unexpected overflowing operator"); 8675 } 8676 if (Inverted) 8677 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8678 if (CondOpcode == ISD::UMULO) 8679 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8680 MVT::i32); 8681 else 8682 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8683 8684 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8685 8686 if (CondOpcode == ISD::UMULO) 8687 Cond = X86Op.getValue(2); 8688 else 8689 Cond = X86Op.getValue(1); 8690 8691 CC = DAG.getConstant(X86Cond, MVT::i8); 8692 addTest = false; 8693 } else { 8694 unsigned CondOpc; 8695 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8696 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8697 if (CondOpc == ISD::OR) { 8698 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8699 // two branches instead of an explicit OR instruction with a 8700 // separate test. 8701 if (Cmp == Cond.getOperand(1).getOperand(1) && 8702 isX86LogicalCmp(Cmp)) { 8703 CC = Cond.getOperand(0).getOperand(0); 8704 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8705 Chain, Dest, CC, Cmp); 8706 CC = Cond.getOperand(1).getOperand(0); 8707 Cond = Cmp; 8708 addTest = false; 8709 } 8710 } else { // ISD::AND 8711 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8712 // two branches instead of an explicit AND instruction with a 8713 // separate test. However, we only do this if this block doesn't 8714 // have a fall-through edge, because this requires an explicit 8715 // jmp when the condition is false. 8716 if (Cmp == Cond.getOperand(1).getOperand(1) && 8717 isX86LogicalCmp(Cmp) && 8718 Op.getNode()->hasOneUse()) { 8719 X86::CondCode CCode = 8720 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8721 CCode = X86::GetOppositeBranchCondition(CCode); 8722 CC = DAG.getConstant(CCode, MVT::i8); 8723 SDNode *User = *Op.getNode()->use_begin(); 8724 // Look for an unconditional branch following this conditional branch. 8725 // We need this because we need to reverse the successors in order 8726 // to implement FCMP_OEQ. 8727 if (User->getOpcode() == ISD::BR) { 8728 SDValue FalseBB = User->getOperand(1); 8729 SDNode *NewBR = 8730 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8731 assert(NewBR == User); 8732 (void)NewBR; 8733 Dest = FalseBB; 8734 8735 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8736 Chain, Dest, CC, Cmp); 8737 X86::CondCode CCode = 8738 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8739 CCode = X86::GetOppositeBranchCondition(CCode); 8740 CC = DAG.getConstant(CCode, MVT::i8); 8741 Cond = Cmp; 8742 addTest = false; 8743 } 8744 } 8745 } 8746 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8747 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8748 // It should be transformed during dag combiner except when the condition 8749 // is set by a arithmetics with overflow node. 8750 X86::CondCode CCode = 8751 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8752 CCode = X86::GetOppositeBranchCondition(CCode); 8753 CC = DAG.getConstant(CCode, MVT::i8); 8754 Cond = Cond.getOperand(0).getOperand(1); 8755 addTest = false; 8756 } else if (Cond.getOpcode() == ISD::SETCC && 8757 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8758 // For FCMP_OEQ, we can emit 8759 // two branches instead of an explicit AND instruction with a 8760 // separate test. However, we only do this if this block doesn't 8761 // have a fall-through edge, because this requires an explicit 8762 // jmp when the condition is false. 8763 if (Op.getNode()->hasOneUse()) { 8764 SDNode *User = *Op.getNode()->use_begin(); 8765 // Look for an unconditional branch following this conditional branch. 8766 // We need this because we need to reverse the successors in order 8767 // to implement FCMP_OEQ. 8768 if (User->getOpcode() == ISD::BR) { 8769 SDValue FalseBB = User->getOperand(1); 8770 SDNode *NewBR = 8771 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8772 assert(NewBR == User); 8773 (void)NewBR; 8774 Dest = FalseBB; 8775 8776 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8777 Cond.getOperand(0), Cond.getOperand(1)); 8778 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8779 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8780 Chain, Dest, CC, Cmp); 8781 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8782 Cond = Cmp; 8783 addTest = false; 8784 } 8785 } 8786 } else if (Cond.getOpcode() == ISD::SETCC && 8787 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8788 // For FCMP_UNE, we can emit 8789 // two branches instead of an explicit AND instruction with a 8790 // separate test. However, we only do this if this block doesn't 8791 // have a fall-through edge, because this requires an explicit 8792 // jmp when the condition is false. 8793 if (Op.getNode()->hasOneUse()) { 8794 SDNode *User = *Op.getNode()->use_begin(); 8795 // Look for an unconditional branch following this conditional branch. 8796 // We need this because we need to reverse the successors in order 8797 // to implement FCMP_UNE. 8798 if (User->getOpcode() == ISD::BR) { 8799 SDValue FalseBB = User->getOperand(1); 8800 SDNode *NewBR = 8801 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8802 assert(NewBR == User); 8803 (void)NewBR; 8804 8805 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8806 Cond.getOperand(0), Cond.getOperand(1)); 8807 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8808 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8809 Chain, Dest, CC, Cmp); 8810 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8811 Cond = Cmp; 8812 addTest = false; 8813 Dest = FalseBB; 8814 } 8815 } 8816 } 8817 } 8818 8819 if (addTest) { 8820 // Look pass the truncate. 8821 if (Cond.getOpcode() == ISD::TRUNCATE) 8822 Cond = Cond.getOperand(0); 8823 8824 // We know the result of AND is compared against zero. Try to match 8825 // it to BT. 8826 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8827 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8828 if (NewSetCC.getNode()) { 8829 CC = NewSetCC.getOperand(0); 8830 Cond = NewSetCC.getOperand(1); 8831 addTest = false; 8832 } 8833 } 8834 } 8835 8836 if (addTest) { 8837 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8838 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8839 } 8840 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8841 Chain, Dest, CC, Cond); 8842} 8843 8844 8845// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8846// Calls to _alloca is needed to probe the stack when allocating more than 4k 8847// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8848// that the guard pages used by the OS virtual memory manager are allocated in 8849// correct sequence. 8850SDValue 8851X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8852 SelectionDAG &DAG) const { 8853 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8854 getTargetMachine().Options.EnableSegmentedStacks) && 8855 "This should be used only on Windows targets or when segmented stacks " 8856 "are being used"); 8857 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8858 DebugLoc dl = Op.getDebugLoc(); 8859 8860 // Get the inputs. 8861 SDValue Chain = Op.getOperand(0); 8862 SDValue Size = Op.getOperand(1); 8863 // FIXME: Ensure alignment here 8864 8865 bool Is64Bit = Subtarget->is64Bit(); 8866 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8867 8868 if (getTargetMachine().Options.EnableSegmentedStacks) { 8869 MachineFunction &MF = DAG.getMachineFunction(); 8870 MachineRegisterInfo &MRI = MF.getRegInfo(); 8871 8872 if (Is64Bit) { 8873 // The 64 bit implementation of segmented stacks needs to clobber both r10 8874 // r11. This makes it impossible to use it along with nested parameters. 8875 const Function *F = MF.getFunction(); 8876 8877 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8878 I != E; I++) 8879 if (I->hasNestAttr()) 8880 report_fatal_error("Cannot use segmented stacks with functions that " 8881 "have nested arguments."); 8882 } 8883 8884 const TargetRegisterClass *AddrRegClass = 8885 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8886 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8887 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8888 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8889 DAG.getRegister(Vreg, SPTy)); 8890 SDValue Ops1[2] = { Value, Chain }; 8891 return DAG.getMergeValues(Ops1, 2, dl); 8892 } else { 8893 SDValue Flag; 8894 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8895 8896 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8897 Flag = Chain.getValue(1); 8898 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8899 8900 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8901 Flag = Chain.getValue(1); 8902 8903 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8904 8905 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8906 return DAG.getMergeValues(Ops1, 2, dl); 8907 } 8908} 8909 8910SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8911 MachineFunction &MF = DAG.getMachineFunction(); 8912 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8913 8914 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8915 DebugLoc DL = Op.getDebugLoc(); 8916 8917 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8918 // vastart just stores the address of the VarArgsFrameIndex slot into the 8919 // memory location argument. 8920 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8921 getPointerTy()); 8922 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8923 MachinePointerInfo(SV), false, false, 0); 8924 } 8925 8926 // __va_list_tag: 8927 // gp_offset (0 - 6 * 8) 8928 // fp_offset (48 - 48 + 8 * 16) 8929 // overflow_arg_area (point to parameters coming in memory). 8930 // reg_save_area 8931 SmallVector<SDValue, 8> MemOps; 8932 SDValue FIN = Op.getOperand(1); 8933 // Store gp_offset 8934 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8935 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 8936 MVT::i32), 8937 FIN, MachinePointerInfo(SV), false, false, 0); 8938 MemOps.push_back(Store); 8939 8940 // Store fp_offset 8941 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8942 FIN, DAG.getIntPtrConstant(4)); 8943 Store = DAG.getStore(Op.getOperand(0), DL, 8944 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 8945 MVT::i32), 8946 FIN, MachinePointerInfo(SV, 4), false, false, 0); 8947 MemOps.push_back(Store); 8948 8949 // Store ptr to overflow_arg_area 8950 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8951 FIN, DAG.getIntPtrConstant(4)); 8952 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8953 getPointerTy()); 8954 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 8955 MachinePointerInfo(SV, 8), 8956 false, false, 0); 8957 MemOps.push_back(Store); 8958 8959 // Store ptr to reg_save_area. 8960 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8961 FIN, DAG.getIntPtrConstant(8)); 8962 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 8963 getPointerTy()); 8964 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 8965 MachinePointerInfo(SV, 16), false, false, 0); 8966 MemOps.push_back(Store); 8967 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 8968 &MemOps[0], MemOps.size()); 8969} 8970 8971SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 8972 assert(Subtarget->is64Bit() && 8973 "LowerVAARG only handles 64-bit va_arg!"); 8974 assert((Subtarget->isTargetLinux() || 8975 Subtarget->isTargetDarwin()) && 8976 "Unhandled target in LowerVAARG"); 8977 assert(Op.getNode()->getNumOperands() == 4); 8978 SDValue Chain = Op.getOperand(0); 8979 SDValue SrcPtr = Op.getOperand(1); 8980 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8981 unsigned Align = Op.getConstantOperandVal(3); 8982 DebugLoc dl = Op.getDebugLoc(); 8983 8984 EVT ArgVT = Op.getNode()->getValueType(0); 8985 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 8986 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 8987 uint8_t ArgMode; 8988 8989 // Decide which area this value should be read from. 8990 // TODO: Implement the AMD64 ABI in its entirety. This simple 8991 // selection mechanism works only for the basic types. 8992 if (ArgVT == MVT::f80) { 8993 llvm_unreachable("va_arg for f80 not yet implemented"); 8994 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 8995 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 8996 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 8997 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 8998 } else { 8999 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9000 } 9001 9002 if (ArgMode == 2) { 9003 // Sanity Check: Make sure using fp_offset makes sense. 9004 assert(!getTargetMachine().Options.UseSoftFloat && 9005 !(DAG.getMachineFunction() 9006 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9007 Subtarget->hasSSE1()); 9008 } 9009 9010 // Insert VAARG_64 node into the DAG 9011 // VAARG_64 returns two values: Variable Argument Address, Chain 9012 SmallVector<SDValue, 11> InstOps; 9013 InstOps.push_back(Chain); 9014 InstOps.push_back(SrcPtr); 9015 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9016 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9017 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9018 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9019 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9020 VTs, &InstOps[0], InstOps.size(), 9021 MVT::i64, 9022 MachinePointerInfo(SV), 9023 /*Align=*/0, 9024 /*Volatile=*/false, 9025 /*ReadMem=*/true, 9026 /*WriteMem=*/true); 9027 Chain = VAARG.getValue(1); 9028 9029 // Load the next argument and return it 9030 return DAG.getLoad(ArgVT, dl, 9031 Chain, 9032 VAARG, 9033 MachinePointerInfo(), 9034 false, false, false, 0); 9035} 9036 9037SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9038 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9039 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9040 SDValue Chain = Op.getOperand(0); 9041 SDValue DstPtr = Op.getOperand(1); 9042 SDValue SrcPtr = Op.getOperand(2); 9043 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9044 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9045 DebugLoc DL = Op.getDebugLoc(); 9046 9047 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9048 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9049 false, 9050 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9051} 9052 9053// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9054// may or may not be a constant. Takes immediate version of shift as input. 9055static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9056 SDValue SrcOp, SDValue ShAmt, 9057 SelectionDAG &DAG) { 9058 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9059 9060 if (isa<ConstantSDNode>(ShAmt)) { 9061 switch (Opc) { 9062 default: llvm_unreachable("Unknown target vector shift node"); 9063 case X86ISD::VSHLI: 9064 case X86ISD::VSRLI: 9065 case X86ISD::VSRAI: 9066 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9067 } 9068 } 9069 9070 // Change opcode to non-immediate version 9071 switch (Opc) { 9072 default: llvm_unreachable("Unknown target vector shift node"); 9073 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9074 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9075 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9076 } 9077 9078 // Need to build a vector containing shift amount 9079 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9080 SDValue ShOps[4]; 9081 ShOps[0] = ShAmt; 9082 ShOps[1] = DAG.getConstant(0, MVT::i32); 9083 ShOps[2] = DAG.getUNDEF(MVT::i32); 9084 ShOps[3] = DAG.getUNDEF(MVT::i32); 9085 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9086 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9087 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9088} 9089 9090SDValue 9091X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9092 DebugLoc dl = Op.getDebugLoc(); 9093 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9094 switch (IntNo) { 9095 default: return SDValue(); // Don't custom lower most intrinsics. 9096 // Comparison intrinsics. 9097 case Intrinsic::x86_sse_comieq_ss: 9098 case Intrinsic::x86_sse_comilt_ss: 9099 case Intrinsic::x86_sse_comile_ss: 9100 case Intrinsic::x86_sse_comigt_ss: 9101 case Intrinsic::x86_sse_comige_ss: 9102 case Intrinsic::x86_sse_comineq_ss: 9103 case Intrinsic::x86_sse_ucomieq_ss: 9104 case Intrinsic::x86_sse_ucomilt_ss: 9105 case Intrinsic::x86_sse_ucomile_ss: 9106 case Intrinsic::x86_sse_ucomigt_ss: 9107 case Intrinsic::x86_sse_ucomige_ss: 9108 case Intrinsic::x86_sse_ucomineq_ss: 9109 case Intrinsic::x86_sse2_comieq_sd: 9110 case Intrinsic::x86_sse2_comilt_sd: 9111 case Intrinsic::x86_sse2_comile_sd: 9112 case Intrinsic::x86_sse2_comigt_sd: 9113 case Intrinsic::x86_sse2_comige_sd: 9114 case Intrinsic::x86_sse2_comineq_sd: 9115 case Intrinsic::x86_sse2_ucomieq_sd: 9116 case Intrinsic::x86_sse2_ucomilt_sd: 9117 case Intrinsic::x86_sse2_ucomile_sd: 9118 case Intrinsic::x86_sse2_ucomigt_sd: 9119 case Intrinsic::x86_sse2_ucomige_sd: 9120 case Intrinsic::x86_sse2_ucomineq_sd: { 9121 unsigned Opc = 0; 9122 ISD::CondCode CC = ISD::SETCC_INVALID; 9123 switch (IntNo) { 9124 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9125 case Intrinsic::x86_sse_comieq_ss: 9126 case Intrinsic::x86_sse2_comieq_sd: 9127 Opc = X86ISD::COMI; 9128 CC = ISD::SETEQ; 9129 break; 9130 case Intrinsic::x86_sse_comilt_ss: 9131 case Intrinsic::x86_sse2_comilt_sd: 9132 Opc = X86ISD::COMI; 9133 CC = ISD::SETLT; 9134 break; 9135 case Intrinsic::x86_sse_comile_ss: 9136 case Intrinsic::x86_sse2_comile_sd: 9137 Opc = X86ISD::COMI; 9138 CC = ISD::SETLE; 9139 break; 9140 case Intrinsic::x86_sse_comigt_ss: 9141 case Intrinsic::x86_sse2_comigt_sd: 9142 Opc = X86ISD::COMI; 9143 CC = ISD::SETGT; 9144 break; 9145 case Intrinsic::x86_sse_comige_ss: 9146 case Intrinsic::x86_sse2_comige_sd: 9147 Opc = X86ISD::COMI; 9148 CC = ISD::SETGE; 9149 break; 9150 case Intrinsic::x86_sse_comineq_ss: 9151 case Intrinsic::x86_sse2_comineq_sd: 9152 Opc = X86ISD::COMI; 9153 CC = ISD::SETNE; 9154 break; 9155 case Intrinsic::x86_sse_ucomieq_ss: 9156 case Intrinsic::x86_sse2_ucomieq_sd: 9157 Opc = X86ISD::UCOMI; 9158 CC = ISD::SETEQ; 9159 break; 9160 case Intrinsic::x86_sse_ucomilt_ss: 9161 case Intrinsic::x86_sse2_ucomilt_sd: 9162 Opc = X86ISD::UCOMI; 9163 CC = ISD::SETLT; 9164 break; 9165 case Intrinsic::x86_sse_ucomile_ss: 9166 case Intrinsic::x86_sse2_ucomile_sd: 9167 Opc = X86ISD::UCOMI; 9168 CC = ISD::SETLE; 9169 break; 9170 case Intrinsic::x86_sse_ucomigt_ss: 9171 case Intrinsic::x86_sse2_ucomigt_sd: 9172 Opc = X86ISD::UCOMI; 9173 CC = ISD::SETGT; 9174 break; 9175 case Intrinsic::x86_sse_ucomige_ss: 9176 case Intrinsic::x86_sse2_ucomige_sd: 9177 Opc = X86ISD::UCOMI; 9178 CC = ISD::SETGE; 9179 break; 9180 case Intrinsic::x86_sse_ucomineq_ss: 9181 case Intrinsic::x86_sse2_ucomineq_sd: 9182 Opc = X86ISD::UCOMI; 9183 CC = ISD::SETNE; 9184 break; 9185 } 9186 9187 SDValue LHS = Op.getOperand(1); 9188 SDValue RHS = Op.getOperand(2); 9189 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9190 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9191 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9192 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9193 DAG.getConstant(X86CC, MVT::i8), Cond); 9194 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9195 } 9196 // XOP comparison intrinsics 9197 case Intrinsic::x86_xop_vpcomltb: 9198 case Intrinsic::x86_xop_vpcomltw: 9199 case Intrinsic::x86_xop_vpcomltd: 9200 case Intrinsic::x86_xop_vpcomltq: 9201 case Intrinsic::x86_xop_vpcomltub: 9202 case Intrinsic::x86_xop_vpcomltuw: 9203 case Intrinsic::x86_xop_vpcomltud: 9204 case Intrinsic::x86_xop_vpcomltuq: 9205 case Intrinsic::x86_xop_vpcomleb: 9206 case Intrinsic::x86_xop_vpcomlew: 9207 case Intrinsic::x86_xop_vpcomled: 9208 case Intrinsic::x86_xop_vpcomleq: 9209 case Intrinsic::x86_xop_vpcomleub: 9210 case Intrinsic::x86_xop_vpcomleuw: 9211 case Intrinsic::x86_xop_vpcomleud: 9212 case Intrinsic::x86_xop_vpcomleuq: 9213 case Intrinsic::x86_xop_vpcomgtb: 9214 case Intrinsic::x86_xop_vpcomgtw: 9215 case Intrinsic::x86_xop_vpcomgtd: 9216 case Intrinsic::x86_xop_vpcomgtq: 9217 case Intrinsic::x86_xop_vpcomgtub: 9218 case Intrinsic::x86_xop_vpcomgtuw: 9219 case Intrinsic::x86_xop_vpcomgtud: 9220 case Intrinsic::x86_xop_vpcomgtuq: 9221 case Intrinsic::x86_xop_vpcomgeb: 9222 case Intrinsic::x86_xop_vpcomgew: 9223 case Intrinsic::x86_xop_vpcomged: 9224 case Intrinsic::x86_xop_vpcomgeq: 9225 case Intrinsic::x86_xop_vpcomgeub: 9226 case Intrinsic::x86_xop_vpcomgeuw: 9227 case Intrinsic::x86_xop_vpcomgeud: 9228 case Intrinsic::x86_xop_vpcomgeuq: 9229 case Intrinsic::x86_xop_vpcomeqb: 9230 case Intrinsic::x86_xop_vpcomeqw: 9231 case Intrinsic::x86_xop_vpcomeqd: 9232 case Intrinsic::x86_xop_vpcomeqq: 9233 case Intrinsic::x86_xop_vpcomequb: 9234 case Intrinsic::x86_xop_vpcomequw: 9235 case Intrinsic::x86_xop_vpcomequd: 9236 case Intrinsic::x86_xop_vpcomequq: 9237 case Intrinsic::x86_xop_vpcomneb: 9238 case Intrinsic::x86_xop_vpcomnew: 9239 case Intrinsic::x86_xop_vpcomned: 9240 case Intrinsic::x86_xop_vpcomneq: 9241 case Intrinsic::x86_xop_vpcomneub: 9242 case Intrinsic::x86_xop_vpcomneuw: 9243 case Intrinsic::x86_xop_vpcomneud: 9244 case Intrinsic::x86_xop_vpcomneuq: 9245 case Intrinsic::x86_xop_vpcomfalseb: 9246 case Intrinsic::x86_xop_vpcomfalsew: 9247 case Intrinsic::x86_xop_vpcomfalsed: 9248 case Intrinsic::x86_xop_vpcomfalseq: 9249 case Intrinsic::x86_xop_vpcomfalseub: 9250 case Intrinsic::x86_xop_vpcomfalseuw: 9251 case Intrinsic::x86_xop_vpcomfalseud: 9252 case Intrinsic::x86_xop_vpcomfalseuq: 9253 case Intrinsic::x86_xop_vpcomtrueb: 9254 case Intrinsic::x86_xop_vpcomtruew: 9255 case Intrinsic::x86_xop_vpcomtrued: 9256 case Intrinsic::x86_xop_vpcomtrueq: 9257 case Intrinsic::x86_xop_vpcomtrueub: 9258 case Intrinsic::x86_xop_vpcomtrueuw: 9259 case Intrinsic::x86_xop_vpcomtrueud: 9260 case Intrinsic::x86_xop_vpcomtrueuq: { 9261 unsigned CC = 0; 9262 unsigned Opc = 0; 9263 9264 switch (IntNo) { 9265 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9266 case Intrinsic::x86_xop_vpcomltb: 9267 case Intrinsic::x86_xop_vpcomltw: 9268 case Intrinsic::x86_xop_vpcomltd: 9269 case Intrinsic::x86_xop_vpcomltq: 9270 CC = 0; 9271 Opc = X86ISD::VPCOM; 9272 break; 9273 case Intrinsic::x86_xop_vpcomltub: 9274 case Intrinsic::x86_xop_vpcomltuw: 9275 case Intrinsic::x86_xop_vpcomltud: 9276 case Intrinsic::x86_xop_vpcomltuq: 9277 CC = 0; 9278 Opc = X86ISD::VPCOMU; 9279 break; 9280 case Intrinsic::x86_xop_vpcomleb: 9281 case Intrinsic::x86_xop_vpcomlew: 9282 case Intrinsic::x86_xop_vpcomled: 9283 case Intrinsic::x86_xop_vpcomleq: 9284 CC = 1; 9285 Opc = X86ISD::VPCOM; 9286 break; 9287 case Intrinsic::x86_xop_vpcomleub: 9288 case Intrinsic::x86_xop_vpcomleuw: 9289 case Intrinsic::x86_xop_vpcomleud: 9290 case Intrinsic::x86_xop_vpcomleuq: 9291 CC = 1; 9292 Opc = X86ISD::VPCOMU; 9293 break; 9294 case Intrinsic::x86_xop_vpcomgtb: 9295 case Intrinsic::x86_xop_vpcomgtw: 9296 case Intrinsic::x86_xop_vpcomgtd: 9297 case Intrinsic::x86_xop_vpcomgtq: 9298 CC = 2; 9299 Opc = X86ISD::VPCOM; 9300 break; 9301 case Intrinsic::x86_xop_vpcomgtub: 9302 case Intrinsic::x86_xop_vpcomgtuw: 9303 case Intrinsic::x86_xop_vpcomgtud: 9304 case Intrinsic::x86_xop_vpcomgtuq: 9305 CC = 2; 9306 Opc = X86ISD::VPCOMU; 9307 break; 9308 case Intrinsic::x86_xop_vpcomgeb: 9309 case Intrinsic::x86_xop_vpcomgew: 9310 case Intrinsic::x86_xop_vpcomged: 9311 case Intrinsic::x86_xop_vpcomgeq: 9312 CC = 3; 9313 Opc = X86ISD::VPCOM; 9314 break; 9315 case Intrinsic::x86_xop_vpcomgeub: 9316 case Intrinsic::x86_xop_vpcomgeuw: 9317 case Intrinsic::x86_xop_vpcomgeud: 9318 case Intrinsic::x86_xop_vpcomgeuq: 9319 CC = 3; 9320 Opc = X86ISD::VPCOMU; 9321 break; 9322 case Intrinsic::x86_xop_vpcomeqb: 9323 case Intrinsic::x86_xop_vpcomeqw: 9324 case Intrinsic::x86_xop_vpcomeqd: 9325 case Intrinsic::x86_xop_vpcomeqq: 9326 CC = 4; 9327 Opc = X86ISD::VPCOM; 9328 break; 9329 case Intrinsic::x86_xop_vpcomequb: 9330 case Intrinsic::x86_xop_vpcomequw: 9331 case Intrinsic::x86_xop_vpcomequd: 9332 case Intrinsic::x86_xop_vpcomequq: 9333 CC = 4; 9334 Opc = X86ISD::VPCOMU; 9335 break; 9336 case Intrinsic::x86_xop_vpcomneb: 9337 case Intrinsic::x86_xop_vpcomnew: 9338 case Intrinsic::x86_xop_vpcomned: 9339 case Intrinsic::x86_xop_vpcomneq: 9340 CC = 5; 9341 Opc = X86ISD::VPCOM; 9342 break; 9343 case Intrinsic::x86_xop_vpcomneub: 9344 case Intrinsic::x86_xop_vpcomneuw: 9345 case Intrinsic::x86_xop_vpcomneud: 9346 case Intrinsic::x86_xop_vpcomneuq: 9347 CC = 5; 9348 Opc = X86ISD::VPCOMU; 9349 break; 9350 case Intrinsic::x86_xop_vpcomfalseb: 9351 case Intrinsic::x86_xop_vpcomfalsew: 9352 case Intrinsic::x86_xop_vpcomfalsed: 9353 case Intrinsic::x86_xop_vpcomfalseq: 9354 CC = 6; 9355 Opc = X86ISD::VPCOM; 9356 break; 9357 case Intrinsic::x86_xop_vpcomfalseub: 9358 case Intrinsic::x86_xop_vpcomfalseuw: 9359 case Intrinsic::x86_xop_vpcomfalseud: 9360 case Intrinsic::x86_xop_vpcomfalseuq: 9361 CC = 6; 9362 Opc = X86ISD::VPCOMU; 9363 break; 9364 case Intrinsic::x86_xop_vpcomtrueb: 9365 case Intrinsic::x86_xop_vpcomtruew: 9366 case Intrinsic::x86_xop_vpcomtrued: 9367 case Intrinsic::x86_xop_vpcomtrueq: 9368 CC = 7; 9369 Opc = X86ISD::VPCOM; 9370 break; 9371 case Intrinsic::x86_xop_vpcomtrueub: 9372 case Intrinsic::x86_xop_vpcomtrueuw: 9373 case Intrinsic::x86_xop_vpcomtrueud: 9374 case Intrinsic::x86_xop_vpcomtrueuq: 9375 CC = 7; 9376 Opc = X86ISD::VPCOMU; 9377 break; 9378 } 9379 9380 SDValue LHS = Op.getOperand(1); 9381 SDValue RHS = Op.getOperand(2); 9382 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9383 DAG.getConstant(CC, MVT::i8)); 9384 } 9385 9386 // Arithmetic intrinsics. 9387 case Intrinsic::x86_sse2_pmulu_dq: 9388 case Intrinsic::x86_avx2_pmulu_dq: 9389 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9390 Op.getOperand(1), Op.getOperand(2)); 9391 case Intrinsic::x86_sse3_hadd_ps: 9392 case Intrinsic::x86_sse3_hadd_pd: 9393 case Intrinsic::x86_avx_hadd_ps_256: 9394 case Intrinsic::x86_avx_hadd_pd_256: 9395 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9396 Op.getOperand(1), Op.getOperand(2)); 9397 case Intrinsic::x86_sse3_hsub_ps: 9398 case Intrinsic::x86_sse3_hsub_pd: 9399 case Intrinsic::x86_avx_hsub_ps_256: 9400 case Intrinsic::x86_avx_hsub_pd_256: 9401 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9402 Op.getOperand(1), Op.getOperand(2)); 9403 case Intrinsic::x86_ssse3_phadd_w_128: 9404 case Intrinsic::x86_ssse3_phadd_d_128: 9405 case Intrinsic::x86_avx2_phadd_w: 9406 case Intrinsic::x86_avx2_phadd_d: 9407 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9408 Op.getOperand(1), Op.getOperand(2)); 9409 case Intrinsic::x86_ssse3_phsub_w_128: 9410 case Intrinsic::x86_ssse3_phsub_d_128: 9411 case Intrinsic::x86_avx2_phsub_w: 9412 case Intrinsic::x86_avx2_phsub_d: 9413 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9414 Op.getOperand(1), Op.getOperand(2)); 9415 case Intrinsic::x86_avx2_psllv_d: 9416 case Intrinsic::x86_avx2_psllv_q: 9417 case Intrinsic::x86_avx2_psllv_d_256: 9418 case Intrinsic::x86_avx2_psllv_q_256: 9419 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9420 Op.getOperand(1), Op.getOperand(2)); 9421 case Intrinsic::x86_avx2_psrlv_d: 9422 case Intrinsic::x86_avx2_psrlv_q: 9423 case Intrinsic::x86_avx2_psrlv_d_256: 9424 case Intrinsic::x86_avx2_psrlv_q_256: 9425 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9426 Op.getOperand(1), Op.getOperand(2)); 9427 case Intrinsic::x86_avx2_psrav_d: 9428 case Intrinsic::x86_avx2_psrav_d_256: 9429 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9430 Op.getOperand(1), Op.getOperand(2)); 9431 case Intrinsic::x86_ssse3_pshuf_b_128: 9432 case Intrinsic::x86_avx2_pshuf_b: 9433 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9434 Op.getOperand(1), Op.getOperand(2)); 9435 case Intrinsic::x86_ssse3_psign_b_128: 9436 case Intrinsic::x86_ssse3_psign_w_128: 9437 case Intrinsic::x86_ssse3_psign_d_128: 9438 case Intrinsic::x86_avx2_psign_b: 9439 case Intrinsic::x86_avx2_psign_w: 9440 case Intrinsic::x86_avx2_psign_d: 9441 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9442 Op.getOperand(1), Op.getOperand(2)); 9443 case Intrinsic::x86_sse41_insertps: 9444 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9445 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9446 case Intrinsic::x86_avx_vperm2f128_ps_256: 9447 case Intrinsic::x86_avx_vperm2f128_pd_256: 9448 case Intrinsic::x86_avx_vperm2f128_si_256: 9449 case Intrinsic::x86_avx2_vperm2i128: 9450 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9451 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9452 case Intrinsic::x86_avx_vpermil_ps: 9453 case Intrinsic::x86_avx_vpermil_pd: 9454 case Intrinsic::x86_avx_vpermil_ps_256: 9455 case Intrinsic::x86_avx_vpermil_pd_256: 9456 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(), 9457 Op.getOperand(1), Op.getOperand(2)); 9458 9459 // ptest and testp intrinsics. The intrinsic these come from are designed to 9460 // return an integer value, not just an instruction so lower it to the ptest 9461 // or testp pattern and a setcc for the result. 9462 case Intrinsic::x86_sse41_ptestz: 9463 case Intrinsic::x86_sse41_ptestc: 9464 case Intrinsic::x86_sse41_ptestnzc: 9465 case Intrinsic::x86_avx_ptestz_256: 9466 case Intrinsic::x86_avx_ptestc_256: 9467 case Intrinsic::x86_avx_ptestnzc_256: 9468 case Intrinsic::x86_avx_vtestz_ps: 9469 case Intrinsic::x86_avx_vtestc_ps: 9470 case Intrinsic::x86_avx_vtestnzc_ps: 9471 case Intrinsic::x86_avx_vtestz_pd: 9472 case Intrinsic::x86_avx_vtestc_pd: 9473 case Intrinsic::x86_avx_vtestnzc_pd: 9474 case Intrinsic::x86_avx_vtestz_ps_256: 9475 case Intrinsic::x86_avx_vtestc_ps_256: 9476 case Intrinsic::x86_avx_vtestnzc_ps_256: 9477 case Intrinsic::x86_avx_vtestz_pd_256: 9478 case Intrinsic::x86_avx_vtestc_pd_256: 9479 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9480 bool IsTestPacked = false; 9481 unsigned X86CC = 0; 9482 switch (IntNo) { 9483 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9484 case Intrinsic::x86_avx_vtestz_ps: 9485 case Intrinsic::x86_avx_vtestz_pd: 9486 case Intrinsic::x86_avx_vtestz_ps_256: 9487 case Intrinsic::x86_avx_vtestz_pd_256: 9488 IsTestPacked = true; // Fallthrough 9489 case Intrinsic::x86_sse41_ptestz: 9490 case Intrinsic::x86_avx_ptestz_256: 9491 // ZF = 1 9492 X86CC = X86::COND_E; 9493 break; 9494 case Intrinsic::x86_avx_vtestc_ps: 9495 case Intrinsic::x86_avx_vtestc_pd: 9496 case Intrinsic::x86_avx_vtestc_ps_256: 9497 case Intrinsic::x86_avx_vtestc_pd_256: 9498 IsTestPacked = true; // Fallthrough 9499 case Intrinsic::x86_sse41_ptestc: 9500 case Intrinsic::x86_avx_ptestc_256: 9501 // CF = 1 9502 X86CC = X86::COND_B; 9503 break; 9504 case Intrinsic::x86_avx_vtestnzc_ps: 9505 case Intrinsic::x86_avx_vtestnzc_pd: 9506 case Intrinsic::x86_avx_vtestnzc_ps_256: 9507 case Intrinsic::x86_avx_vtestnzc_pd_256: 9508 IsTestPacked = true; // Fallthrough 9509 case Intrinsic::x86_sse41_ptestnzc: 9510 case Intrinsic::x86_avx_ptestnzc_256: 9511 // ZF and CF = 0 9512 X86CC = X86::COND_A; 9513 break; 9514 } 9515 9516 SDValue LHS = Op.getOperand(1); 9517 SDValue RHS = Op.getOperand(2); 9518 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9519 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9520 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9521 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9522 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9523 } 9524 9525 // SSE/AVX shift intrinsics 9526 case Intrinsic::x86_sse2_psll_w: 9527 case Intrinsic::x86_sse2_psll_d: 9528 case Intrinsic::x86_sse2_psll_q: 9529 case Intrinsic::x86_avx2_psll_w: 9530 case Intrinsic::x86_avx2_psll_d: 9531 case Intrinsic::x86_avx2_psll_q: 9532 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9533 Op.getOperand(1), Op.getOperand(2)); 9534 case Intrinsic::x86_sse2_psrl_w: 9535 case Intrinsic::x86_sse2_psrl_d: 9536 case Intrinsic::x86_sse2_psrl_q: 9537 case Intrinsic::x86_avx2_psrl_w: 9538 case Intrinsic::x86_avx2_psrl_d: 9539 case Intrinsic::x86_avx2_psrl_q: 9540 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9541 Op.getOperand(1), Op.getOperand(2)); 9542 case Intrinsic::x86_sse2_psra_w: 9543 case Intrinsic::x86_sse2_psra_d: 9544 case Intrinsic::x86_avx2_psra_w: 9545 case Intrinsic::x86_avx2_psra_d: 9546 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9547 Op.getOperand(1), Op.getOperand(2)); 9548 case Intrinsic::x86_sse2_pslli_w: 9549 case Intrinsic::x86_sse2_pslli_d: 9550 case Intrinsic::x86_sse2_pslli_q: 9551 case Intrinsic::x86_avx2_pslli_w: 9552 case Intrinsic::x86_avx2_pslli_d: 9553 case Intrinsic::x86_avx2_pslli_q: 9554 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9555 Op.getOperand(1), Op.getOperand(2), DAG); 9556 case Intrinsic::x86_sse2_psrli_w: 9557 case Intrinsic::x86_sse2_psrli_d: 9558 case Intrinsic::x86_sse2_psrli_q: 9559 case Intrinsic::x86_avx2_psrli_w: 9560 case Intrinsic::x86_avx2_psrli_d: 9561 case Intrinsic::x86_avx2_psrli_q: 9562 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9563 Op.getOperand(1), Op.getOperand(2), DAG); 9564 case Intrinsic::x86_sse2_psrai_w: 9565 case Intrinsic::x86_sse2_psrai_d: 9566 case Intrinsic::x86_avx2_psrai_w: 9567 case Intrinsic::x86_avx2_psrai_d: 9568 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9569 Op.getOperand(1), Op.getOperand(2), DAG); 9570 // Fix vector shift instructions where the last operand is a non-immediate 9571 // i32 value. 9572 case Intrinsic::x86_mmx_pslli_w: 9573 case Intrinsic::x86_mmx_pslli_d: 9574 case Intrinsic::x86_mmx_pslli_q: 9575 case Intrinsic::x86_mmx_psrli_w: 9576 case Intrinsic::x86_mmx_psrli_d: 9577 case Intrinsic::x86_mmx_psrli_q: 9578 case Intrinsic::x86_mmx_psrai_w: 9579 case Intrinsic::x86_mmx_psrai_d: { 9580 SDValue ShAmt = Op.getOperand(2); 9581 if (isa<ConstantSDNode>(ShAmt)) 9582 return SDValue(); 9583 9584 unsigned NewIntNo = 0; 9585 switch (IntNo) { 9586 case Intrinsic::x86_mmx_pslli_w: 9587 NewIntNo = Intrinsic::x86_mmx_psll_w; 9588 break; 9589 case Intrinsic::x86_mmx_pslli_d: 9590 NewIntNo = Intrinsic::x86_mmx_psll_d; 9591 break; 9592 case Intrinsic::x86_mmx_pslli_q: 9593 NewIntNo = Intrinsic::x86_mmx_psll_q; 9594 break; 9595 case Intrinsic::x86_mmx_psrli_w: 9596 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9597 break; 9598 case Intrinsic::x86_mmx_psrli_d: 9599 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9600 break; 9601 case Intrinsic::x86_mmx_psrli_q: 9602 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9603 break; 9604 case Intrinsic::x86_mmx_psrai_w: 9605 NewIntNo = Intrinsic::x86_mmx_psra_w; 9606 break; 9607 case Intrinsic::x86_mmx_psrai_d: 9608 NewIntNo = Intrinsic::x86_mmx_psra_d; 9609 break; 9610 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9611 } 9612 9613 // The vector shift intrinsics with scalars uses 32b shift amounts but 9614 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9615 // to be zero. 9616 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9617 DAG.getConstant(0, MVT::i32)); 9618// FIXME this must be lowered to get rid of the invalid type. 9619 9620 EVT VT = Op.getValueType(); 9621 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9622 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9623 DAG.getConstant(NewIntNo, MVT::i32), 9624 Op.getOperand(1), ShAmt); 9625 } 9626 } 9627} 9628 9629SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9630 SelectionDAG &DAG) const { 9631 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9632 MFI->setReturnAddressIsTaken(true); 9633 9634 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9635 DebugLoc dl = Op.getDebugLoc(); 9636 9637 if (Depth > 0) { 9638 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9639 SDValue Offset = 9640 DAG.getConstant(TD->getPointerSize(), 9641 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9642 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9643 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9644 FrameAddr, Offset), 9645 MachinePointerInfo(), false, false, false, 0); 9646 } 9647 9648 // Just load the return address. 9649 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9650 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9651 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9652} 9653 9654SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9655 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9656 MFI->setFrameAddressIsTaken(true); 9657 9658 EVT VT = Op.getValueType(); 9659 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9660 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9661 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9662 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9663 while (Depth--) 9664 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9665 MachinePointerInfo(), 9666 false, false, false, 0); 9667 return FrameAddr; 9668} 9669 9670SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9671 SelectionDAG &DAG) const { 9672 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9673} 9674 9675SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9676 MachineFunction &MF = DAG.getMachineFunction(); 9677 SDValue Chain = Op.getOperand(0); 9678 SDValue Offset = Op.getOperand(1); 9679 SDValue Handler = Op.getOperand(2); 9680 DebugLoc dl = Op.getDebugLoc(); 9681 9682 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9683 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9684 getPointerTy()); 9685 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9686 9687 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9688 DAG.getIntPtrConstant(TD->getPointerSize())); 9689 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9690 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9691 false, false, 0); 9692 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9693 MF.getRegInfo().addLiveOut(StoreAddrReg); 9694 9695 return DAG.getNode(X86ISD::EH_RETURN, dl, 9696 MVT::Other, 9697 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9698} 9699 9700SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9701 SelectionDAG &DAG) const { 9702 return Op.getOperand(0); 9703} 9704 9705SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9706 SelectionDAG &DAG) const { 9707 SDValue Root = Op.getOperand(0); 9708 SDValue Trmp = Op.getOperand(1); // trampoline 9709 SDValue FPtr = Op.getOperand(2); // nested function 9710 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9711 DebugLoc dl = Op.getDebugLoc(); 9712 9713 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9714 9715 if (Subtarget->is64Bit()) { 9716 SDValue OutChains[6]; 9717 9718 // Large code-model. 9719 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9720 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9721 9722 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9723 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9724 9725 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9726 9727 // Load the pointer to the nested function into R11. 9728 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9729 SDValue Addr = Trmp; 9730 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9731 Addr, MachinePointerInfo(TrmpAddr), 9732 false, false, 0); 9733 9734 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9735 DAG.getConstant(2, MVT::i64)); 9736 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9737 MachinePointerInfo(TrmpAddr, 2), 9738 false, false, 2); 9739 9740 // Load the 'nest' parameter value into R10. 9741 // R10 is specified in X86CallingConv.td 9742 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9743 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9744 DAG.getConstant(10, MVT::i64)); 9745 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9746 Addr, MachinePointerInfo(TrmpAddr, 10), 9747 false, false, 0); 9748 9749 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9750 DAG.getConstant(12, MVT::i64)); 9751 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9752 MachinePointerInfo(TrmpAddr, 12), 9753 false, false, 2); 9754 9755 // Jump to the nested function. 9756 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9757 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9758 DAG.getConstant(20, MVT::i64)); 9759 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9760 Addr, MachinePointerInfo(TrmpAddr, 20), 9761 false, false, 0); 9762 9763 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9765 DAG.getConstant(22, MVT::i64)); 9766 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9767 MachinePointerInfo(TrmpAddr, 22), 9768 false, false, 0); 9769 9770 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9771 } else { 9772 const Function *Func = 9773 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9774 CallingConv::ID CC = Func->getCallingConv(); 9775 unsigned NestReg; 9776 9777 switch (CC) { 9778 default: 9779 llvm_unreachable("Unsupported calling convention"); 9780 case CallingConv::C: 9781 case CallingConv::X86_StdCall: { 9782 // Pass 'nest' parameter in ECX. 9783 // Must be kept in sync with X86CallingConv.td 9784 NestReg = X86::ECX; 9785 9786 // Check that ECX wasn't needed by an 'inreg' parameter. 9787 FunctionType *FTy = Func->getFunctionType(); 9788 const AttrListPtr &Attrs = Func->getAttributes(); 9789 9790 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9791 unsigned InRegCount = 0; 9792 unsigned Idx = 1; 9793 9794 for (FunctionType::param_iterator I = FTy->param_begin(), 9795 E = FTy->param_end(); I != E; ++I, ++Idx) 9796 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9797 // FIXME: should only count parameters that are lowered to integers. 9798 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9799 9800 if (InRegCount > 2) { 9801 report_fatal_error("Nest register in use - reduce number of inreg" 9802 " parameters!"); 9803 } 9804 } 9805 break; 9806 } 9807 case CallingConv::X86_FastCall: 9808 case CallingConv::X86_ThisCall: 9809 case CallingConv::Fast: 9810 // Pass 'nest' parameter in EAX. 9811 // Must be kept in sync with X86CallingConv.td 9812 NestReg = X86::EAX; 9813 break; 9814 } 9815 9816 SDValue OutChains[4]; 9817 SDValue Addr, Disp; 9818 9819 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9820 DAG.getConstant(10, MVT::i32)); 9821 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9822 9823 // This is storing the opcode for MOV32ri. 9824 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9825 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9826 OutChains[0] = DAG.getStore(Root, dl, 9827 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9828 Trmp, MachinePointerInfo(TrmpAddr), 9829 false, false, 0); 9830 9831 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9832 DAG.getConstant(1, MVT::i32)); 9833 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9834 MachinePointerInfo(TrmpAddr, 1), 9835 false, false, 1); 9836 9837 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9838 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9839 DAG.getConstant(5, MVT::i32)); 9840 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9841 MachinePointerInfo(TrmpAddr, 5), 9842 false, false, 1); 9843 9844 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9845 DAG.getConstant(6, MVT::i32)); 9846 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9847 MachinePointerInfo(TrmpAddr, 6), 9848 false, false, 1); 9849 9850 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9851 } 9852} 9853 9854SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9855 SelectionDAG &DAG) const { 9856 /* 9857 The rounding mode is in bits 11:10 of FPSR, and has the following 9858 settings: 9859 00 Round to nearest 9860 01 Round to -inf 9861 10 Round to +inf 9862 11 Round to 0 9863 9864 FLT_ROUNDS, on the other hand, expects the following: 9865 -1 Undefined 9866 0 Round to 0 9867 1 Round to nearest 9868 2 Round to +inf 9869 3 Round to -inf 9870 9871 To perform the conversion, we do: 9872 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9873 */ 9874 9875 MachineFunction &MF = DAG.getMachineFunction(); 9876 const TargetMachine &TM = MF.getTarget(); 9877 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9878 unsigned StackAlignment = TFI.getStackAlignment(); 9879 EVT VT = Op.getValueType(); 9880 DebugLoc DL = Op.getDebugLoc(); 9881 9882 // Save FP Control Word to stack slot 9883 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9884 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9885 9886 9887 MachineMemOperand *MMO = 9888 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9889 MachineMemOperand::MOStore, 2, 2); 9890 9891 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9892 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9893 DAG.getVTList(MVT::Other), 9894 Ops, 2, MVT::i16, MMO); 9895 9896 // Load FP Control Word from stack slot 9897 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9898 MachinePointerInfo(), false, false, false, 0); 9899 9900 // Transform as necessary 9901 SDValue CWD1 = 9902 DAG.getNode(ISD::SRL, DL, MVT::i16, 9903 DAG.getNode(ISD::AND, DL, MVT::i16, 9904 CWD, DAG.getConstant(0x800, MVT::i16)), 9905 DAG.getConstant(11, MVT::i8)); 9906 SDValue CWD2 = 9907 DAG.getNode(ISD::SRL, DL, MVT::i16, 9908 DAG.getNode(ISD::AND, DL, MVT::i16, 9909 CWD, DAG.getConstant(0x400, MVT::i16)), 9910 DAG.getConstant(9, MVT::i8)); 9911 9912 SDValue RetVal = 9913 DAG.getNode(ISD::AND, DL, MVT::i16, 9914 DAG.getNode(ISD::ADD, DL, MVT::i16, 9915 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9916 DAG.getConstant(1, MVT::i16)), 9917 DAG.getConstant(3, MVT::i16)); 9918 9919 9920 return DAG.getNode((VT.getSizeInBits() < 16 ? 9921 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9922} 9923 9924SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9925 EVT VT = Op.getValueType(); 9926 EVT OpVT = VT; 9927 unsigned NumBits = VT.getSizeInBits(); 9928 DebugLoc dl = Op.getDebugLoc(); 9929 9930 Op = Op.getOperand(0); 9931 if (VT == MVT::i8) { 9932 // Zero extend to i32 since there is not an i8 bsr. 9933 OpVT = MVT::i32; 9934 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9935 } 9936 9937 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9938 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9939 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9940 9941 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9942 SDValue Ops[] = { 9943 Op, 9944 DAG.getConstant(NumBits+NumBits-1, OpVT), 9945 DAG.getConstant(X86::COND_E, MVT::i8), 9946 Op.getValue(1) 9947 }; 9948 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9949 9950 // Finally xor with NumBits-1. 9951 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9952 9953 if (VT == MVT::i8) 9954 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9955 return Op; 9956} 9957 9958SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 9959 SelectionDAG &DAG) const { 9960 EVT VT = Op.getValueType(); 9961 EVT OpVT = VT; 9962 unsigned NumBits = VT.getSizeInBits(); 9963 DebugLoc dl = Op.getDebugLoc(); 9964 9965 Op = Op.getOperand(0); 9966 if (VT == MVT::i8) { 9967 // Zero extend to i32 since there is not an i8 bsr. 9968 OpVT = MVT::i32; 9969 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9970 } 9971 9972 // Issue a bsr (scan bits in reverse). 9973 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9974 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9975 9976 // And xor with NumBits-1. 9977 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9978 9979 if (VT == MVT::i8) 9980 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9981 return Op; 9982} 9983 9984SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9985 EVT VT = Op.getValueType(); 9986 unsigned NumBits = VT.getSizeInBits(); 9987 DebugLoc dl = Op.getDebugLoc(); 9988 Op = Op.getOperand(0); 9989 9990 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9991 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9992 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9993 9994 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9995 SDValue Ops[] = { 9996 Op, 9997 DAG.getConstant(NumBits, VT), 9998 DAG.getConstant(X86::COND_E, MVT::i8), 9999 Op.getValue(1) 10000 }; 10001 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10002} 10003 10004// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10005// ones, and then concatenate the result back. 10006static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10007 EVT VT = Op.getValueType(); 10008 10009 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10010 "Unsupported value type for operation"); 10011 10012 int NumElems = VT.getVectorNumElements(); 10013 DebugLoc dl = Op.getDebugLoc(); 10014 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10015 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10016 10017 // Extract the LHS vectors 10018 SDValue LHS = Op.getOperand(0); 10019 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10020 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10021 10022 // Extract the RHS vectors 10023 SDValue RHS = Op.getOperand(1); 10024 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10025 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10026 10027 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10028 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10029 10030 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10031 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10032 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10033} 10034 10035SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10036 assert(Op.getValueType().getSizeInBits() == 256 && 10037 Op.getValueType().isInteger() && 10038 "Only handle AVX 256-bit vector integer operation"); 10039 return Lower256IntArith(Op, DAG); 10040} 10041 10042SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10043 assert(Op.getValueType().getSizeInBits() == 256 && 10044 Op.getValueType().isInteger() && 10045 "Only handle AVX 256-bit vector integer operation"); 10046 return Lower256IntArith(Op, DAG); 10047} 10048 10049SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10050 EVT VT = Op.getValueType(); 10051 10052 // Decompose 256-bit ops into smaller 128-bit ops. 10053 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10054 return Lower256IntArith(Op, DAG); 10055 10056 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10057 "Only know how to lower V2I64/V4I64 multiply"); 10058 10059 DebugLoc dl = Op.getDebugLoc(); 10060 10061 // Ahi = psrlqi(a, 32); 10062 // Bhi = psrlqi(b, 32); 10063 // 10064 // AloBlo = pmuludq(a, b); 10065 // AloBhi = pmuludq(a, Bhi); 10066 // AhiBlo = pmuludq(Ahi, b); 10067 10068 // AloBhi = psllqi(AloBhi, 32); 10069 // AhiBlo = psllqi(AhiBlo, 32); 10070 // return AloBlo + AloBhi + AhiBlo; 10071 10072 SDValue A = Op.getOperand(0); 10073 SDValue B = Op.getOperand(1); 10074 10075 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10076 10077 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10078 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10079 10080 // Bit cast to 32-bit vectors for MULUDQ 10081 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10082 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10083 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10084 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10085 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10086 10087 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10088 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10089 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10090 10091 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10092 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10093 10094 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10095 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10096} 10097 10098SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10099 10100 EVT VT = Op.getValueType(); 10101 DebugLoc dl = Op.getDebugLoc(); 10102 SDValue R = Op.getOperand(0); 10103 SDValue Amt = Op.getOperand(1); 10104 LLVMContext *Context = DAG.getContext(); 10105 10106 if (!Subtarget->hasSSE2()) 10107 return SDValue(); 10108 10109 // Optimize shl/srl/sra with constant shift amount. 10110 if (isSplatVector(Amt.getNode())) { 10111 SDValue SclrAmt = Amt->getOperand(0); 10112 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10113 uint64_t ShiftAmt = C->getZExtValue(); 10114 10115 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10116 (Subtarget->hasAVX2() && 10117 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10118 if (Op.getOpcode() == ISD::SHL) 10119 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10120 DAG.getConstant(ShiftAmt, MVT::i32)); 10121 if (Op.getOpcode() == ISD::SRL) 10122 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10123 DAG.getConstant(ShiftAmt, MVT::i32)); 10124 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10125 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10126 DAG.getConstant(ShiftAmt, MVT::i32)); 10127 } 10128 10129 if (VT == MVT::v16i8) { 10130 if (Op.getOpcode() == ISD::SHL) { 10131 // Make a large shift. 10132 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10133 DAG.getConstant(ShiftAmt, MVT::i32)); 10134 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10135 // Zero out the rightmost bits. 10136 SmallVector<SDValue, 16> V(16, 10137 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10138 MVT::i8)); 10139 return DAG.getNode(ISD::AND, dl, VT, SHL, 10140 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10141 } 10142 if (Op.getOpcode() == ISD::SRL) { 10143 // Make a large shift. 10144 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10145 DAG.getConstant(ShiftAmt, MVT::i32)); 10146 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10147 // Zero out the leftmost bits. 10148 SmallVector<SDValue, 16> V(16, 10149 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10150 MVT::i8)); 10151 return DAG.getNode(ISD::AND, dl, VT, SRL, 10152 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10153 } 10154 if (Op.getOpcode() == ISD::SRA) { 10155 if (ShiftAmt == 7) { 10156 // R s>> 7 === R s< 0 10157 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10158 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10159 } 10160 10161 // R s>> a === ((R u>> a) ^ m) - m 10162 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10163 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10164 MVT::i8)); 10165 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10166 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10167 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10168 return Res; 10169 } 10170 } 10171 10172 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10173 if (Op.getOpcode() == ISD::SHL) { 10174 // Make a large shift. 10175 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10176 DAG.getConstant(ShiftAmt, MVT::i32)); 10177 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10178 // Zero out the rightmost bits. 10179 SmallVector<SDValue, 32> V(32, 10180 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10181 MVT::i8)); 10182 return DAG.getNode(ISD::AND, dl, VT, SHL, 10183 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10184 } 10185 if (Op.getOpcode() == ISD::SRL) { 10186 // Make a large shift. 10187 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10188 DAG.getConstant(ShiftAmt, MVT::i32)); 10189 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10190 // Zero out the leftmost bits. 10191 SmallVector<SDValue, 32> V(32, 10192 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10193 MVT::i8)); 10194 return DAG.getNode(ISD::AND, dl, VT, SRL, 10195 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10196 } 10197 if (Op.getOpcode() == ISD::SRA) { 10198 if (ShiftAmt == 7) { 10199 // R s>> 7 === R s< 0 10200 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10201 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10202 } 10203 10204 // R s>> a === ((R u>> a) ^ m) - m 10205 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10206 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10207 MVT::i8)); 10208 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10209 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10210 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10211 return Res; 10212 } 10213 } 10214 } 10215 } 10216 10217 // Lower SHL with variable shift amount. 10218 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10219 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10220 DAG.getConstant(23, MVT::i32)); 10221 10222 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10223 Constant *C = ConstantDataVector::get(*Context, CV); 10224 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10225 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10226 MachinePointerInfo::getConstantPool(), 10227 false, false, false, 16); 10228 10229 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10230 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10231 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10232 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10233 } 10234 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10235 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10236 10237 // a = a << 5; 10238 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10239 DAG.getConstant(5, MVT::i32)); 10240 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10241 10242 // Turn 'a' into a mask suitable for VSELECT 10243 SDValue VSelM = DAG.getConstant(0x80, VT); 10244 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10245 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10246 10247 SDValue CM1 = DAG.getConstant(0x0f, VT); 10248 SDValue CM2 = DAG.getConstant(0x3f, VT); 10249 10250 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10251 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10252 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10253 DAG.getConstant(4, MVT::i32), DAG); 10254 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10255 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10256 10257 // a += a 10258 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10259 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10260 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10261 10262 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10263 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10264 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10265 DAG.getConstant(2, MVT::i32), DAG); 10266 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10267 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10268 10269 // a += a 10270 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10271 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10272 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10273 10274 // return VSELECT(r, r+r, a); 10275 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10276 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10277 return R; 10278 } 10279 10280 // Decompose 256-bit shifts into smaller 128-bit shifts. 10281 if (VT.getSizeInBits() == 256) { 10282 unsigned NumElems = VT.getVectorNumElements(); 10283 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10284 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10285 10286 // Extract the two vectors 10287 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10288 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10289 DAG, dl); 10290 10291 // Recreate the shift amount vectors 10292 SDValue Amt1, Amt2; 10293 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10294 // Constant shift amount 10295 SmallVector<SDValue, 4> Amt1Csts; 10296 SmallVector<SDValue, 4> Amt2Csts; 10297 for (unsigned i = 0; i != NumElems/2; ++i) 10298 Amt1Csts.push_back(Amt->getOperand(i)); 10299 for (unsigned i = NumElems/2; i != NumElems; ++i) 10300 Amt2Csts.push_back(Amt->getOperand(i)); 10301 10302 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10303 &Amt1Csts[0], NumElems/2); 10304 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10305 &Amt2Csts[0], NumElems/2); 10306 } else { 10307 // Variable shift amount 10308 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10309 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10310 DAG, dl); 10311 } 10312 10313 // Issue new vector shifts for the smaller types 10314 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10315 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10316 10317 // Concatenate the result back 10318 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10319 } 10320 10321 return SDValue(); 10322} 10323 10324SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10325 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10326 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10327 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10328 // has only one use. 10329 SDNode *N = Op.getNode(); 10330 SDValue LHS = N->getOperand(0); 10331 SDValue RHS = N->getOperand(1); 10332 unsigned BaseOp = 0; 10333 unsigned Cond = 0; 10334 DebugLoc DL = Op.getDebugLoc(); 10335 switch (Op.getOpcode()) { 10336 default: llvm_unreachable("Unknown ovf instruction!"); 10337 case ISD::SADDO: 10338 // A subtract of one will be selected as a INC. Note that INC doesn't 10339 // set CF, so we can't do this for UADDO. 10340 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10341 if (C->isOne()) { 10342 BaseOp = X86ISD::INC; 10343 Cond = X86::COND_O; 10344 break; 10345 } 10346 BaseOp = X86ISD::ADD; 10347 Cond = X86::COND_O; 10348 break; 10349 case ISD::UADDO: 10350 BaseOp = X86ISD::ADD; 10351 Cond = X86::COND_B; 10352 break; 10353 case ISD::SSUBO: 10354 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10355 // set CF, so we can't do this for USUBO. 10356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10357 if (C->isOne()) { 10358 BaseOp = X86ISD::DEC; 10359 Cond = X86::COND_O; 10360 break; 10361 } 10362 BaseOp = X86ISD::SUB; 10363 Cond = X86::COND_O; 10364 break; 10365 case ISD::USUBO: 10366 BaseOp = X86ISD::SUB; 10367 Cond = X86::COND_B; 10368 break; 10369 case ISD::SMULO: 10370 BaseOp = X86ISD::SMUL; 10371 Cond = X86::COND_O; 10372 break; 10373 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10374 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10375 MVT::i32); 10376 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10377 10378 SDValue SetCC = 10379 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10380 DAG.getConstant(X86::COND_O, MVT::i32), 10381 SDValue(Sum.getNode(), 2)); 10382 10383 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10384 } 10385 } 10386 10387 // Also sets EFLAGS. 10388 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10389 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10390 10391 SDValue SetCC = 10392 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10393 DAG.getConstant(Cond, MVT::i32), 10394 SDValue(Sum.getNode(), 1)); 10395 10396 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10397} 10398 10399SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10400 SelectionDAG &DAG) const { 10401 DebugLoc dl = Op.getDebugLoc(); 10402 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10403 EVT VT = Op.getValueType(); 10404 10405 if (!Subtarget->hasSSE2() || !VT.isVector()) 10406 return SDValue(); 10407 10408 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10409 ExtraVT.getScalarType().getSizeInBits(); 10410 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10411 10412 switch (VT.getSimpleVT().SimpleTy) { 10413 default: return SDValue(); 10414 case MVT::v8i32: 10415 case MVT::v16i16: 10416 if (!Subtarget->hasAVX()) 10417 return SDValue(); 10418 if (!Subtarget->hasAVX2()) { 10419 // needs to be split 10420 int NumElems = VT.getVectorNumElements(); 10421 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10422 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10423 10424 // Extract the LHS vectors 10425 SDValue LHS = Op.getOperand(0); 10426 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10427 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10428 10429 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10430 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10431 10432 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10433 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10434 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10435 ExtraNumElems/2); 10436 SDValue Extra = DAG.getValueType(ExtraVT); 10437 10438 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10439 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10440 10441 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10442 } 10443 // fall through 10444 case MVT::v4i32: 10445 case MVT::v8i16: { 10446 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10447 Op.getOperand(0), ShAmt, DAG); 10448 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10449 } 10450 } 10451} 10452 10453 10454SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10455 DebugLoc dl = Op.getDebugLoc(); 10456 10457 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10458 // There isn't any reason to disable it if the target processor supports it. 10459 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10460 SDValue Chain = Op.getOperand(0); 10461 SDValue Zero = DAG.getConstant(0, MVT::i32); 10462 SDValue Ops[] = { 10463 DAG.getRegister(X86::ESP, MVT::i32), // Base 10464 DAG.getTargetConstant(1, MVT::i8), // Scale 10465 DAG.getRegister(0, MVT::i32), // Index 10466 DAG.getTargetConstant(0, MVT::i32), // Disp 10467 DAG.getRegister(0, MVT::i32), // Segment. 10468 Zero, 10469 Chain 10470 }; 10471 SDNode *Res = 10472 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10473 array_lengthof(Ops)); 10474 return SDValue(Res, 0); 10475 } 10476 10477 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10478 if (!isDev) 10479 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10480 10481 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10482 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10483 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10484 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10485 10486 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10487 if (!Op1 && !Op2 && !Op3 && Op4) 10488 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10489 10490 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10491 if (Op1 && !Op2 && !Op3 && !Op4) 10492 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10493 10494 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10495 // (MFENCE)>; 10496 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10497} 10498 10499SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10500 SelectionDAG &DAG) const { 10501 DebugLoc dl = Op.getDebugLoc(); 10502 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10503 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10504 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10505 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10506 10507 // The only fence that needs an instruction is a sequentially-consistent 10508 // cross-thread fence. 10509 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10510 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10511 // no-sse2). There isn't any reason to disable it if the target processor 10512 // supports it. 10513 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10514 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10515 10516 SDValue Chain = Op.getOperand(0); 10517 SDValue Zero = DAG.getConstant(0, MVT::i32); 10518 SDValue Ops[] = { 10519 DAG.getRegister(X86::ESP, MVT::i32), // Base 10520 DAG.getTargetConstant(1, MVT::i8), // Scale 10521 DAG.getRegister(0, MVT::i32), // Index 10522 DAG.getTargetConstant(0, MVT::i32), // Disp 10523 DAG.getRegister(0, MVT::i32), // Segment. 10524 Zero, 10525 Chain 10526 }; 10527 SDNode *Res = 10528 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10529 array_lengthof(Ops)); 10530 return SDValue(Res, 0); 10531 } 10532 10533 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10534 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10535} 10536 10537 10538SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10539 EVT T = Op.getValueType(); 10540 DebugLoc DL = Op.getDebugLoc(); 10541 unsigned Reg = 0; 10542 unsigned size = 0; 10543 switch(T.getSimpleVT().SimpleTy) { 10544 default: llvm_unreachable("Invalid value type!"); 10545 case MVT::i8: Reg = X86::AL; size = 1; break; 10546 case MVT::i16: Reg = X86::AX; size = 2; break; 10547 case MVT::i32: Reg = X86::EAX; size = 4; break; 10548 case MVT::i64: 10549 assert(Subtarget->is64Bit() && "Node not type legal!"); 10550 Reg = X86::RAX; size = 8; 10551 break; 10552 } 10553 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10554 Op.getOperand(2), SDValue()); 10555 SDValue Ops[] = { cpIn.getValue(0), 10556 Op.getOperand(1), 10557 Op.getOperand(3), 10558 DAG.getTargetConstant(size, MVT::i8), 10559 cpIn.getValue(1) }; 10560 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10561 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10562 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10563 Ops, 5, T, MMO); 10564 SDValue cpOut = 10565 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10566 return cpOut; 10567} 10568 10569SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10570 SelectionDAG &DAG) const { 10571 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10572 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10573 SDValue TheChain = Op.getOperand(0); 10574 DebugLoc dl = Op.getDebugLoc(); 10575 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10576 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10577 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10578 rax.getValue(2)); 10579 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10580 DAG.getConstant(32, MVT::i8)); 10581 SDValue Ops[] = { 10582 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10583 rdx.getValue(1) 10584 }; 10585 return DAG.getMergeValues(Ops, 2, dl); 10586} 10587 10588SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10589 SelectionDAG &DAG) const { 10590 EVT SrcVT = Op.getOperand(0).getValueType(); 10591 EVT DstVT = Op.getValueType(); 10592 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10593 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10594 assert((DstVT == MVT::i64 || 10595 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10596 "Unexpected custom BITCAST"); 10597 // i64 <=> MMX conversions are Legal. 10598 if (SrcVT==MVT::i64 && DstVT.isVector()) 10599 return Op; 10600 if (DstVT==MVT::i64 && SrcVT.isVector()) 10601 return Op; 10602 // MMX <=> MMX conversions are Legal. 10603 if (SrcVT.isVector() && DstVT.isVector()) 10604 return Op; 10605 // All other conversions need to be expanded. 10606 return SDValue(); 10607} 10608 10609SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10610 SDNode *Node = Op.getNode(); 10611 DebugLoc dl = Node->getDebugLoc(); 10612 EVT T = Node->getValueType(0); 10613 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10614 DAG.getConstant(0, T), Node->getOperand(2)); 10615 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10616 cast<AtomicSDNode>(Node)->getMemoryVT(), 10617 Node->getOperand(0), 10618 Node->getOperand(1), negOp, 10619 cast<AtomicSDNode>(Node)->getSrcValue(), 10620 cast<AtomicSDNode>(Node)->getAlignment(), 10621 cast<AtomicSDNode>(Node)->getOrdering(), 10622 cast<AtomicSDNode>(Node)->getSynchScope()); 10623} 10624 10625static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10626 SDNode *Node = Op.getNode(); 10627 DebugLoc dl = Node->getDebugLoc(); 10628 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10629 10630 // Convert seq_cst store -> xchg 10631 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10632 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10633 // (The only way to get a 16-byte store is cmpxchg16b) 10634 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10635 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10636 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10637 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10638 cast<AtomicSDNode>(Node)->getMemoryVT(), 10639 Node->getOperand(0), 10640 Node->getOperand(1), Node->getOperand(2), 10641 cast<AtomicSDNode>(Node)->getMemOperand(), 10642 cast<AtomicSDNode>(Node)->getOrdering(), 10643 cast<AtomicSDNode>(Node)->getSynchScope()); 10644 return Swap.getValue(1); 10645 } 10646 // Other atomic stores have a simple pattern. 10647 return Op; 10648} 10649 10650static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10651 EVT VT = Op.getNode()->getValueType(0); 10652 10653 // Let legalize expand this if it isn't a legal type yet. 10654 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10655 return SDValue(); 10656 10657 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10658 10659 unsigned Opc; 10660 bool ExtraOp = false; 10661 switch (Op.getOpcode()) { 10662 default: llvm_unreachable("Invalid code"); 10663 case ISD::ADDC: Opc = X86ISD::ADD; break; 10664 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10665 case ISD::SUBC: Opc = X86ISD::SUB; break; 10666 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10667 } 10668 10669 if (!ExtraOp) 10670 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10671 Op.getOperand(1)); 10672 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10673 Op.getOperand(1), Op.getOperand(2)); 10674} 10675 10676/// LowerOperation - Provide custom lowering hooks for some operations. 10677/// 10678SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10679 switch (Op.getOpcode()) { 10680 default: llvm_unreachable("Should not custom lower this!"); 10681 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10682 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10683 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10684 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10685 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10686 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10687 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10688 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10689 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10690 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10691 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10692 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10693 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10694 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10695 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10696 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10697 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10698 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10699 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10700 case ISD::SHL_PARTS: 10701 case ISD::SRA_PARTS: 10702 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10703 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10704 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10705 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10706 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10707 case ISD::FABS: return LowerFABS(Op, DAG); 10708 case ISD::FNEG: return LowerFNEG(Op, DAG); 10709 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10710 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10711 case ISD::SETCC: return LowerSETCC(Op, DAG); 10712 case ISD::SELECT: return LowerSELECT(Op, DAG); 10713 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10714 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10715 case ISD::VASTART: return LowerVASTART(Op, DAG); 10716 case ISD::VAARG: return LowerVAARG(Op, DAG); 10717 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10718 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10719 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10720 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10721 case ISD::FRAME_TO_ARGS_OFFSET: 10722 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10723 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10724 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10725 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10726 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10727 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10728 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10729 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10730 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10731 case ISD::MUL: return LowerMUL(Op, DAG); 10732 case ISD::SRA: 10733 case ISD::SRL: 10734 case ISD::SHL: return LowerShift(Op, DAG); 10735 case ISD::SADDO: 10736 case ISD::UADDO: 10737 case ISD::SSUBO: 10738 case ISD::USUBO: 10739 case ISD::SMULO: 10740 case ISD::UMULO: return LowerXALUO(Op, DAG); 10741 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10742 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10743 case ISD::ADDC: 10744 case ISD::ADDE: 10745 case ISD::SUBC: 10746 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10747 case ISD::ADD: return LowerADD(Op, DAG); 10748 case ISD::SUB: return LowerSUB(Op, DAG); 10749 } 10750} 10751 10752static void ReplaceATOMIC_LOAD(SDNode *Node, 10753 SmallVectorImpl<SDValue> &Results, 10754 SelectionDAG &DAG) { 10755 DebugLoc dl = Node->getDebugLoc(); 10756 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10757 10758 // Convert wide load -> cmpxchg8b/cmpxchg16b 10759 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10760 // (The only way to get a 16-byte load is cmpxchg16b) 10761 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10762 SDValue Zero = DAG.getConstant(0, VT); 10763 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10764 Node->getOperand(0), 10765 Node->getOperand(1), Zero, Zero, 10766 cast<AtomicSDNode>(Node)->getMemOperand(), 10767 cast<AtomicSDNode>(Node)->getOrdering(), 10768 cast<AtomicSDNode>(Node)->getSynchScope()); 10769 Results.push_back(Swap.getValue(0)); 10770 Results.push_back(Swap.getValue(1)); 10771} 10772 10773void X86TargetLowering:: 10774ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10775 SelectionDAG &DAG, unsigned NewOp) const { 10776 DebugLoc dl = Node->getDebugLoc(); 10777 assert (Node->getValueType(0) == MVT::i64 && 10778 "Only know how to expand i64 atomics"); 10779 10780 SDValue Chain = Node->getOperand(0); 10781 SDValue In1 = Node->getOperand(1); 10782 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10783 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10784 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10785 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10786 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10787 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10788 SDValue Result = 10789 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10790 cast<MemSDNode>(Node)->getMemOperand()); 10791 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10792 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10793 Results.push_back(Result.getValue(2)); 10794} 10795 10796/// ReplaceNodeResults - Replace a node with an illegal result type 10797/// with a new node built out of custom code. 10798void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10799 SmallVectorImpl<SDValue>&Results, 10800 SelectionDAG &DAG) const { 10801 DebugLoc dl = N->getDebugLoc(); 10802 switch (N->getOpcode()) { 10803 default: 10804 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10805 case ISD::SIGN_EXTEND_INREG: 10806 case ISD::ADDC: 10807 case ISD::ADDE: 10808 case ISD::SUBC: 10809 case ISD::SUBE: 10810 // We don't want to expand or promote these. 10811 return; 10812 case ISD::FP_TO_SINT: 10813 case ISD::FP_TO_UINT: { 10814 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 10815 10816 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 10817 return; 10818 10819 std::pair<SDValue,SDValue> Vals = 10820 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 10821 SDValue FIST = Vals.first, StackSlot = Vals.second; 10822 if (FIST.getNode() != 0) { 10823 EVT VT = N->getValueType(0); 10824 // Return a load from the stack slot. 10825 if (StackSlot.getNode() != 0) 10826 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10827 MachinePointerInfo(), 10828 false, false, false, 0)); 10829 else 10830 Results.push_back(FIST); 10831 } 10832 return; 10833 } 10834 case ISD::READCYCLECOUNTER: { 10835 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10836 SDValue TheChain = N->getOperand(0); 10837 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10838 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10839 rd.getValue(1)); 10840 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10841 eax.getValue(2)); 10842 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10843 SDValue Ops[] = { eax, edx }; 10844 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10845 Results.push_back(edx.getValue(1)); 10846 return; 10847 } 10848 case ISD::ATOMIC_CMP_SWAP: { 10849 EVT T = N->getValueType(0); 10850 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10851 bool Regs64bit = T == MVT::i128; 10852 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10853 SDValue cpInL, cpInH; 10854 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10855 DAG.getConstant(0, HalfT)); 10856 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10857 DAG.getConstant(1, HalfT)); 10858 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10859 Regs64bit ? X86::RAX : X86::EAX, 10860 cpInL, SDValue()); 10861 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10862 Regs64bit ? X86::RDX : X86::EDX, 10863 cpInH, cpInL.getValue(1)); 10864 SDValue swapInL, swapInH; 10865 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10866 DAG.getConstant(0, HalfT)); 10867 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10868 DAG.getConstant(1, HalfT)); 10869 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10870 Regs64bit ? X86::RBX : X86::EBX, 10871 swapInL, cpInH.getValue(1)); 10872 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10873 Regs64bit ? X86::RCX : X86::ECX, 10874 swapInH, swapInL.getValue(1)); 10875 SDValue Ops[] = { swapInH.getValue(0), 10876 N->getOperand(1), 10877 swapInH.getValue(1) }; 10878 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10879 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10880 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10881 X86ISD::LCMPXCHG8_DAG; 10882 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10883 Ops, 3, T, MMO); 10884 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10885 Regs64bit ? X86::RAX : X86::EAX, 10886 HalfT, Result.getValue(1)); 10887 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10888 Regs64bit ? X86::RDX : X86::EDX, 10889 HalfT, cpOutL.getValue(2)); 10890 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10891 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10892 Results.push_back(cpOutH.getValue(1)); 10893 return; 10894 } 10895 case ISD::ATOMIC_LOAD_ADD: 10896 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10897 return; 10898 case ISD::ATOMIC_LOAD_AND: 10899 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10900 return; 10901 case ISD::ATOMIC_LOAD_NAND: 10902 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10903 return; 10904 case ISD::ATOMIC_LOAD_OR: 10905 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10906 return; 10907 case ISD::ATOMIC_LOAD_SUB: 10908 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10909 return; 10910 case ISD::ATOMIC_LOAD_XOR: 10911 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10912 return; 10913 case ISD::ATOMIC_SWAP: 10914 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10915 return; 10916 case ISD::ATOMIC_LOAD: 10917 ReplaceATOMIC_LOAD(N, Results, DAG); 10918 } 10919} 10920 10921const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10922 switch (Opcode) { 10923 default: return NULL; 10924 case X86ISD::BSF: return "X86ISD::BSF"; 10925 case X86ISD::BSR: return "X86ISD::BSR"; 10926 case X86ISD::SHLD: return "X86ISD::SHLD"; 10927 case X86ISD::SHRD: return "X86ISD::SHRD"; 10928 case X86ISD::FAND: return "X86ISD::FAND"; 10929 case X86ISD::FOR: return "X86ISD::FOR"; 10930 case X86ISD::FXOR: return "X86ISD::FXOR"; 10931 case X86ISD::FSRL: return "X86ISD::FSRL"; 10932 case X86ISD::FILD: return "X86ISD::FILD"; 10933 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10934 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10935 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10936 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10937 case X86ISD::FLD: return "X86ISD::FLD"; 10938 case X86ISD::FST: return "X86ISD::FST"; 10939 case X86ISD::CALL: return "X86ISD::CALL"; 10940 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10941 case X86ISD::BT: return "X86ISD::BT"; 10942 case X86ISD::CMP: return "X86ISD::CMP"; 10943 case X86ISD::COMI: return "X86ISD::COMI"; 10944 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10945 case X86ISD::SETCC: return "X86ISD::SETCC"; 10946 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10947 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10948 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10949 case X86ISD::CMOV: return "X86ISD::CMOV"; 10950 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10951 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10952 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10953 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10954 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10955 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10956 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10957 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10958 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10959 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10960 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10961 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10962 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10963 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10964 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 10965 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 10966 case X86ISD::HADD: return "X86ISD::HADD"; 10967 case X86ISD::HSUB: return "X86ISD::HSUB"; 10968 case X86ISD::FHADD: return "X86ISD::FHADD"; 10969 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10970 case X86ISD::FMAX: return "X86ISD::FMAX"; 10971 case X86ISD::FMIN: return "X86ISD::FMIN"; 10972 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10973 case X86ISD::FRCP: return "X86ISD::FRCP"; 10974 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10975 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10976 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10977 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10978 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10979 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10980 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10981 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10982 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10983 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10984 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10985 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10986 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10987 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10988 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10989 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 10990 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 10991 case X86ISD::VSHL: return "X86ISD::VSHL"; 10992 case X86ISD::VSRL: return "X86ISD::VSRL"; 10993 case X86ISD::VSRA: return "X86ISD::VSRA"; 10994 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 10995 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 10996 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 10997 case X86ISD::CMPP: return "X86ISD::CMPP"; 10998 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 10999 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11000 case X86ISD::ADD: return "X86ISD::ADD"; 11001 case X86ISD::SUB: return "X86ISD::SUB"; 11002 case X86ISD::ADC: return "X86ISD::ADC"; 11003 case X86ISD::SBB: return "X86ISD::SBB"; 11004 case X86ISD::SMUL: return "X86ISD::SMUL"; 11005 case X86ISD::UMUL: return "X86ISD::UMUL"; 11006 case X86ISD::INC: return "X86ISD::INC"; 11007 case X86ISD::DEC: return "X86ISD::DEC"; 11008 case X86ISD::OR: return "X86ISD::OR"; 11009 case X86ISD::XOR: return "X86ISD::XOR"; 11010 case X86ISD::AND: return "X86ISD::AND"; 11011 case X86ISD::ANDN: return "X86ISD::ANDN"; 11012 case X86ISD::BLSI: return "X86ISD::BLSI"; 11013 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11014 case X86ISD::BLSR: return "X86ISD::BLSR"; 11015 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11016 case X86ISD::PTEST: return "X86ISD::PTEST"; 11017 case X86ISD::TESTP: return "X86ISD::TESTP"; 11018 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11019 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11020 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11021 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11022 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11023 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11024 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11025 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11026 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11027 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11028 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11029 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11030 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11031 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11032 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11033 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11034 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11035 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11036 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11037 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11038 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11039 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11040 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11041 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11042 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11043 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11044 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11045 } 11046} 11047 11048// isLegalAddressingMode - Return true if the addressing mode represented 11049// by AM is legal for this target, for a load/store of the specified type. 11050bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11051 Type *Ty) const { 11052 // X86 supports extremely general addressing modes. 11053 CodeModel::Model M = getTargetMachine().getCodeModel(); 11054 Reloc::Model R = getTargetMachine().getRelocationModel(); 11055 11056 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11057 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11058 return false; 11059 11060 if (AM.BaseGV) { 11061 unsigned GVFlags = 11062 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11063 11064 // If a reference to this global requires an extra load, we can't fold it. 11065 if (isGlobalStubReference(GVFlags)) 11066 return false; 11067 11068 // If BaseGV requires a register for the PIC base, we cannot also have a 11069 // BaseReg specified. 11070 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11071 return false; 11072 11073 // If lower 4G is not available, then we must use rip-relative addressing. 11074 if ((M != CodeModel::Small || R != Reloc::Static) && 11075 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11076 return false; 11077 } 11078 11079 switch (AM.Scale) { 11080 case 0: 11081 case 1: 11082 case 2: 11083 case 4: 11084 case 8: 11085 // These scales always work. 11086 break; 11087 case 3: 11088 case 5: 11089 case 9: 11090 // These scales are formed with basereg+scalereg. Only accept if there is 11091 // no basereg yet. 11092 if (AM.HasBaseReg) 11093 return false; 11094 break; 11095 default: // Other stuff never works. 11096 return false; 11097 } 11098 11099 return true; 11100} 11101 11102 11103bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11104 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11105 return false; 11106 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11107 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11108 if (NumBits1 <= NumBits2) 11109 return false; 11110 return true; 11111} 11112 11113bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11114 if (!VT1.isInteger() || !VT2.isInteger()) 11115 return false; 11116 unsigned NumBits1 = VT1.getSizeInBits(); 11117 unsigned NumBits2 = VT2.getSizeInBits(); 11118 if (NumBits1 <= NumBits2) 11119 return false; 11120 return true; 11121} 11122 11123bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11124 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11125 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11126} 11127 11128bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11129 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11130 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11131} 11132 11133bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11134 // i16 instructions are longer (0x66 prefix) and potentially slower. 11135 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11136} 11137 11138/// isShuffleMaskLegal - Targets can use this to indicate that they only 11139/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11140/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11141/// are assumed to be legal. 11142bool 11143X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11144 EVT VT) const { 11145 // Very little shuffling can be done for 64-bit vectors right now. 11146 if (VT.getSizeInBits() == 64) 11147 return false; 11148 11149 // FIXME: pshufb, blends, shifts. 11150 return (VT.getVectorNumElements() == 2 || 11151 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11152 isMOVLMask(M, VT) || 11153 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11154 isPSHUFDMask(M, VT) || 11155 isPSHUFHWMask(M, VT) || 11156 isPSHUFLWMask(M, VT) || 11157 isPALIGNRMask(M, VT, Subtarget) || 11158 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11159 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11160 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11161 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11162} 11163 11164bool 11165X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11166 EVT VT) const { 11167 unsigned NumElts = VT.getVectorNumElements(); 11168 // FIXME: This collection of masks seems suspect. 11169 if (NumElts == 2) 11170 return true; 11171 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11172 return (isMOVLMask(Mask, VT) || 11173 isCommutedMOVLMask(Mask, VT, true) || 11174 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11175 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11176 } 11177 return false; 11178} 11179 11180//===----------------------------------------------------------------------===// 11181// X86 Scheduler Hooks 11182//===----------------------------------------------------------------------===// 11183 11184// private utility function 11185MachineBasicBlock * 11186X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11187 MachineBasicBlock *MBB, 11188 unsigned regOpc, 11189 unsigned immOpc, 11190 unsigned LoadOpc, 11191 unsigned CXchgOpc, 11192 unsigned notOpc, 11193 unsigned EAXreg, 11194 const TargetRegisterClass *RC, 11195 bool invSrc) const { 11196 // For the atomic bitwise operator, we generate 11197 // thisMBB: 11198 // newMBB: 11199 // ld t1 = [bitinstr.addr] 11200 // op t2 = t1, [bitinstr.val] 11201 // mov EAX = t1 11202 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11203 // bz newMBB 11204 // fallthrough -->nextMBB 11205 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11206 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11207 MachineFunction::iterator MBBIter = MBB; 11208 ++MBBIter; 11209 11210 /// First build the CFG 11211 MachineFunction *F = MBB->getParent(); 11212 MachineBasicBlock *thisMBB = MBB; 11213 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11214 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11215 F->insert(MBBIter, newMBB); 11216 F->insert(MBBIter, nextMBB); 11217 11218 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11219 nextMBB->splice(nextMBB->begin(), thisMBB, 11220 llvm::next(MachineBasicBlock::iterator(bInstr)), 11221 thisMBB->end()); 11222 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11223 11224 // Update thisMBB to fall through to newMBB 11225 thisMBB->addSuccessor(newMBB); 11226 11227 // newMBB jumps to itself and fall through to nextMBB 11228 newMBB->addSuccessor(nextMBB); 11229 newMBB->addSuccessor(newMBB); 11230 11231 // Insert instructions into newMBB based on incoming instruction 11232 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11233 "unexpected number of operands"); 11234 DebugLoc dl = bInstr->getDebugLoc(); 11235 MachineOperand& destOper = bInstr->getOperand(0); 11236 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11237 int numArgs = bInstr->getNumOperands() - 1; 11238 for (int i=0; i < numArgs; ++i) 11239 argOpers[i] = &bInstr->getOperand(i+1); 11240 11241 // x86 address has 4 operands: base, index, scale, and displacement 11242 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11243 int valArgIndx = lastAddrIndx + 1; 11244 11245 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11246 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11247 for (int i=0; i <= lastAddrIndx; ++i) 11248 (*MIB).addOperand(*argOpers[i]); 11249 11250 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11251 if (invSrc) { 11252 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11253 } 11254 else 11255 tt = t1; 11256 11257 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11258 assert((argOpers[valArgIndx]->isReg() || 11259 argOpers[valArgIndx]->isImm()) && 11260 "invalid operand"); 11261 if (argOpers[valArgIndx]->isReg()) 11262 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11263 else 11264 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11265 MIB.addReg(tt); 11266 (*MIB).addOperand(*argOpers[valArgIndx]); 11267 11268 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11269 MIB.addReg(t1); 11270 11271 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11272 for (int i=0; i <= lastAddrIndx; ++i) 11273 (*MIB).addOperand(*argOpers[i]); 11274 MIB.addReg(t2); 11275 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11276 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11277 bInstr->memoperands_end()); 11278 11279 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11280 MIB.addReg(EAXreg); 11281 11282 // insert branch 11283 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11284 11285 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11286 return nextMBB; 11287} 11288 11289// private utility function: 64 bit atomics on 32 bit host. 11290MachineBasicBlock * 11291X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11292 MachineBasicBlock *MBB, 11293 unsigned regOpcL, 11294 unsigned regOpcH, 11295 unsigned immOpcL, 11296 unsigned immOpcH, 11297 bool invSrc) const { 11298 // For the atomic bitwise operator, we generate 11299 // thisMBB (instructions are in pairs, except cmpxchg8b) 11300 // ld t1,t2 = [bitinstr.addr] 11301 // newMBB: 11302 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11303 // op t5, t6 <- out1, out2, [bitinstr.val] 11304 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11305 // mov ECX, EBX <- t5, t6 11306 // mov EAX, EDX <- t1, t2 11307 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11308 // mov t3, t4 <- EAX, EDX 11309 // bz newMBB 11310 // result in out1, out2 11311 // fallthrough -->nextMBB 11312 11313 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11314 const unsigned LoadOpc = X86::MOV32rm; 11315 const unsigned NotOpc = X86::NOT32r; 11316 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11317 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11318 MachineFunction::iterator MBBIter = MBB; 11319 ++MBBIter; 11320 11321 /// First build the CFG 11322 MachineFunction *F = MBB->getParent(); 11323 MachineBasicBlock *thisMBB = MBB; 11324 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11325 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11326 F->insert(MBBIter, newMBB); 11327 F->insert(MBBIter, nextMBB); 11328 11329 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11330 nextMBB->splice(nextMBB->begin(), thisMBB, 11331 llvm::next(MachineBasicBlock::iterator(bInstr)), 11332 thisMBB->end()); 11333 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11334 11335 // Update thisMBB to fall through to newMBB 11336 thisMBB->addSuccessor(newMBB); 11337 11338 // newMBB jumps to itself and fall through to nextMBB 11339 newMBB->addSuccessor(nextMBB); 11340 newMBB->addSuccessor(newMBB); 11341 11342 DebugLoc dl = bInstr->getDebugLoc(); 11343 // Insert instructions into newMBB based on incoming instruction 11344 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11345 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11346 "unexpected number of operands"); 11347 MachineOperand& dest1Oper = bInstr->getOperand(0); 11348 MachineOperand& dest2Oper = bInstr->getOperand(1); 11349 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11350 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11351 argOpers[i] = &bInstr->getOperand(i+2); 11352 11353 // We use some of the operands multiple times, so conservatively just 11354 // clear any kill flags that might be present. 11355 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11356 argOpers[i]->setIsKill(false); 11357 } 11358 11359 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11360 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11361 11362 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11363 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11364 for (int i=0; i <= lastAddrIndx; ++i) 11365 (*MIB).addOperand(*argOpers[i]); 11366 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11367 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11368 // add 4 to displacement. 11369 for (int i=0; i <= lastAddrIndx-2; ++i) 11370 (*MIB).addOperand(*argOpers[i]); 11371 MachineOperand newOp3 = *(argOpers[3]); 11372 if (newOp3.isImm()) 11373 newOp3.setImm(newOp3.getImm()+4); 11374 else 11375 newOp3.setOffset(newOp3.getOffset()+4); 11376 (*MIB).addOperand(newOp3); 11377 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11378 11379 // t3/4 are defined later, at the bottom of the loop 11380 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11381 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11382 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11383 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11384 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11385 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11386 11387 // The subsequent operations should be using the destination registers of 11388 //the PHI instructions. 11389 if (invSrc) { 11390 t1 = F->getRegInfo().createVirtualRegister(RC); 11391 t2 = F->getRegInfo().createVirtualRegister(RC); 11392 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11393 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11394 } else { 11395 t1 = dest1Oper.getReg(); 11396 t2 = dest2Oper.getReg(); 11397 } 11398 11399 int valArgIndx = lastAddrIndx + 1; 11400 assert((argOpers[valArgIndx]->isReg() || 11401 argOpers[valArgIndx]->isImm()) && 11402 "invalid operand"); 11403 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11404 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11405 if (argOpers[valArgIndx]->isReg()) 11406 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11407 else 11408 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11409 if (regOpcL != X86::MOV32rr) 11410 MIB.addReg(t1); 11411 (*MIB).addOperand(*argOpers[valArgIndx]); 11412 assert(argOpers[valArgIndx + 1]->isReg() == 11413 argOpers[valArgIndx]->isReg()); 11414 assert(argOpers[valArgIndx + 1]->isImm() == 11415 argOpers[valArgIndx]->isImm()); 11416 if (argOpers[valArgIndx + 1]->isReg()) 11417 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11418 else 11419 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11420 if (regOpcH != X86::MOV32rr) 11421 MIB.addReg(t2); 11422 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11423 11424 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11425 MIB.addReg(t1); 11426 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11427 MIB.addReg(t2); 11428 11429 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11430 MIB.addReg(t5); 11431 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11432 MIB.addReg(t6); 11433 11434 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11435 for (int i=0; i <= lastAddrIndx; ++i) 11436 (*MIB).addOperand(*argOpers[i]); 11437 11438 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11439 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11440 bInstr->memoperands_end()); 11441 11442 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11443 MIB.addReg(X86::EAX); 11444 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11445 MIB.addReg(X86::EDX); 11446 11447 // insert branch 11448 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11449 11450 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11451 return nextMBB; 11452} 11453 11454// private utility function 11455MachineBasicBlock * 11456X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11457 MachineBasicBlock *MBB, 11458 unsigned cmovOpc) const { 11459 // For the atomic min/max operator, we generate 11460 // thisMBB: 11461 // newMBB: 11462 // ld t1 = [min/max.addr] 11463 // mov t2 = [min/max.val] 11464 // cmp t1, t2 11465 // cmov[cond] t2 = t1 11466 // mov EAX = t1 11467 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11468 // bz newMBB 11469 // fallthrough -->nextMBB 11470 // 11471 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11472 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11473 MachineFunction::iterator MBBIter = MBB; 11474 ++MBBIter; 11475 11476 /// First build the CFG 11477 MachineFunction *F = MBB->getParent(); 11478 MachineBasicBlock *thisMBB = MBB; 11479 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11480 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11481 F->insert(MBBIter, newMBB); 11482 F->insert(MBBIter, nextMBB); 11483 11484 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11485 nextMBB->splice(nextMBB->begin(), thisMBB, 11486 llvm::next(MachineBasicBlock::iterator(mInstr)), 11487 thisMBB->end()); 11488 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11489 11490 // Update thisMBB to fall through to newMBB 11491 thisMBB->addSuccessor(newMBB); 11492 11493 // newMBB jumps to newMBB and fall through to nextMBB 11494 newMBB->addSuccessor(nextMBB); 11495 newMBB->addSuccessor(newMBB); 11496 11497 DebugLoc dl = mInstr->getDebugLoc(); 11498 // Insert instructions into newMBB based on incoming instruction 11499 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11500 "unexpected number of operands"); 11501 MachineOperand& destOper = mInstr->getOperand(0); 11502 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11503 int numArgs = mInstr->getNumOperands() - 1; 11504 for (int i=0; i < numArgs; ++i) 11505 argOpers[i] = &mInstr->getOperand(i+1); 11506 11507 // x86 address has 4 operands: base, index, scale, and displacement 11508 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11509 int valArgIndx = lastAddrIndx + 1; 11510 11511 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11512 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11513 for (int i=0; i <= lastAddrIndx; ++i) 11514 (*MIB).addOperand(*argOpers[i]); 11515 11516 // We only support register and immediate values 11517 assert((argOpers[valArgIndx]->isReg() || 11518 argOpers[valArgIndx]->isImm()) && 11519 "invalid operand"); 11520 11521 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11522 if (argOpers[valArgIndx]->isReg()) 11523 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11524 else 11525 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11526 (*MIB).addOperand(*argOpers[valArgIndx]); 11527 11528 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11529 MIB.addReg(t1); 11530 11531 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11532 MIB.addReg(t1); 11533 MIB.addReg(t2); 11534 11535 // Generate movc 11536 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11537 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11538 MIB.addReg(t2); 11539 MIB.addReg(t1); 11540 11541 // Cmp and exchange if none has modified the memory location 11542 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11543 for (int i=0; i <= lastAddrIndx; ++i) 11544 (*MIB).addOperand(*argOpers[i]); 11545 MIB.addReg(t3); 11546 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11547 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11548 mInstr->memoperands_end()); 11549 11550 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11551 MIB.addReg(X86::EAX); 11552 11553 // insert branch 11554 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11555 11556 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11557 return nextMBB; 11558} 11559 11560// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11561// or XMM0_V32I8 in AVX all of this code can be replaced with that 11562// in the .td file. 11563MachineBasicBlock * 11564X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11565 unsigned numArgs, bool memArg) const { 11566 assert(Subtarget->hasSSE42() && 11567 "Target must have SSE4.2 or AVX features enabled"); 11568 11569 DebugLoc dl = MI->getDebugLoc(); 11570 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11571 unsigned Opc; 11572 if (!Subtarget->hasAVX()) { 11573 if (memArg) 11574 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11575 else 11576 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11577 } else { 11578 if (memArg) 11579 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11580 else 11581 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11582 } 11583 11584 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11585 for (unsigned i = 0; i < numArgs; ++i) { 11586 MachineOperand &Op = MI->getOperand(i+1); 11587 if (!(Op.isReg() && Op.isImplicit())) 11588 MIB.addOperand(Op); 11589 } 11590 BuildMI(*BB, MI, dl, 11591 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11592 MI->getOperand(0).getReg()) 11593 .addReg(X86::XMM0); 11594 11595 MI->eraseFromParent(); 11596 return BB; 11597} 11598 11599MachineBasicBlock * 11600X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11601 DebugLoc dl = MI->getDebugLoc(); 11602 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11603 11604 // Address into RAX/EAX, other two args into ECX, EDX. 11605 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11606 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11607 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11608 for (int i = 0; i < X86::AddrNumOperands; ++i) 11609 MIB.addOperand(MI->getOperand(i)); 11610 11611 unsigned ValOps = X86::AddrNumOperands; 11612 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11613 .addReg(MI->getOperand(ValOps).getReg()); 11614 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11615 .addReg(MI->getOperand(ValOps+1).getReg()); 11616 11617 // The instruction doesn't actually take any operands though. 11618 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11619 11620 MI->eraseFromParent(); // The pseudo is gone now. 11621 return BB; 11622} 11623 11624MachineBasicBlock * 11625X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11626 DebugLoc dl = MI->getDebugLoc(); 11627 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11628 11629 // First arg in ECX, the second in EAX. 11630 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11631 .addReg(MI->getOperand(0).getReg()); 11632 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11633 .addReg(MI->getOperand(1).getReg()); 11634 11635 // The instruction doesn't actually take any operands though. 11636 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11637 11638 MI->eraseFromParent(); // The pseudo is gone now. 11639 return BB; 11640} 11641 11642MachineBasicBlock * 11643X86TargetLowering::EmitVAARG64WithCustomInserter( 11644 MachineInstr *MI, 11645 MachineBasicBlock *MBB) const { 11646 // Emit va_arg instruction on X86-64. 11647 11648 // Operands to this pseudo-instruction: 11649 // 0 ) Output : destination address (reg) 11650 // 1-5) Input : va_list address (addr, i64mem) 11651 // 6 ) ArgSize : Size (in bytes) of vararg type 11652 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11653 // 8 ) Align : Alignment of type 11654 // 9 ) EFLAGS (implicit-def) 11655 11656 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11657 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11658 11659 unsigned DestReg = MI->getOperand(0).getReg(); 11660 MachineOperand &Base = MI->getOperand(1); 11661 MachineOperand &Scale = MI->getOperand(2); 11662 MachineOperand &Index = MI->getOperand(3); 11663 MachineOperand &Disp = MI->getOperand(4); 11664 MachineOperand &Segment = MI->getOperand(5); 11665 unsigned ArgSize = MI->getOperand(6).getImm(); 11666 unsigned ArgMode = MI->getOperand(7).getImm(); 11667 unsigned Align = MI->getOperand(8).getImm(); 11668 11669 // Memory Reference 11670 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11671 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11672 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11673 11674 // Machine Information 11675 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11676 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11677 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11678 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11679 DebugLoc DL = MI->getDebugLoc(); 11680 11681 // struct va_list { 11682 // i32 gp_offset 11683 // i32 fp_offset 11684 // i64 overflow_area (address) 11685 // i64 reg_save_area (address) 11686 // } 11687 // sizeof(va_list) = 24 11688 // alignment(va_list) = 8 11689 11690 unsigned TotalNumIntRegs = 6; 11691 unsigned TotalNumXMMRegs = 8; 11692 bool UseGPOffset = (ArgMode == 1); 11693 bool UseFPOffset = (ArgMode == 2); 11694 unsigned MaxOffset = TotalNumIntRegs * 8 + 11695 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11696 11697 /* Align ArgSize to a multiple of 8 */ 11698 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11699 bool NeedsAlign = (Align > 8); 11700 11701 MachineBasicBlock *thisMBB = MBB; 11702 MachineBasicBlock *overflowMBB; 11703 MachineBasicBlock *offsetMBB; 11704 MachineBasicBlock *endMBB; 11705 11706 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11707 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11708 unsigned OffsetReg = 0; 11709 11710 if (!UseGPOffset && !UseFPOffset) { 11711 // If we only pull from the overflow region, we don't create a branch. 11712 // We don't need to alter control flow. 11713 OffsetDestReg = 0; // unused 11714 OverflowDestReg = DestReg; 11715 11716 offsetMBB = NULL; 11717 overflowMBB = thisMBB; 11718 endMBB = thisMBB; 11719 } else { 11720 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11721 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11722 // If not, pull from overflow_area. (branch to overflowMBB) 11723 // 11724 // thisMBB 11725 // | . 11726 // | . 11727 // offsetMBB overflowMBB 11728 // | . 11729 // | . 11730 // endMBB 11731 11732 // Registers for the PHI in endMBB 11733 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11734 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11735 11736 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11737 MachineFunction *MF = MBB->getParent(); 11738 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11739 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11740 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11741 11742 MachineFunction::iterator MBBIter = MBB; 11743 ++MBBIter; 11744 11745 // Insert the new basic blocks 11746 MF->insert(MBBIter, offsetMBB); 11747 MF->insert(MBBIter, overflowMBB); 11748 MF->insert(MBBIter, endMBB); 11749 11750 // Transfer the remainder of MBB and its successor edges to endMBB. 11751 endMBB->splice(endMBB->begin(), thisMBB, 11752 llvm::next(MachineBasicBlock::iterator(MI)), 11753 thisMBB->end()); 11754 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11755 11756 // Make offsetMBB and overflowMBB successors of thisMBB 11757 thisMBB->addSuccessor(offsetMBB); 11758 thisMBB->addSuccessor(overflowMBB); 11759 11760 // endMBB is a successor of both offsetMBB and overflowMBB 11761 offsetMBB->addSuccessor(endMBB); 11762 overflowMBB->addSuccessor(endMBB); 11763 11764 // Load the offset value into a register 11765 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11766 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11767 .addOperand(Base) 11768 .addOperand(Scale) 11769 .addOperand(Index) 11770 .addDisp(Disp, UseFPOffset ? 4 : 0) 11771 .addOperand(Segment) 11772 .setMemRefs(MMOBegin, MMOEnd); 11773 11774 // Check if there is enough room left to pull this argument. 11775 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11776 .addReg(OffsetReg) 11777 .addImm(MaxOffset + 8 - ArgSizeA8); 11778 11779 // Branch to "overflowMBB" if offset >= max 11780 // Fall through to "offsetMBB" otherwise 11781 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11782 .addMBB(overflowMBB); 11783 } 11784 11785 // In offsetMBB, emit code to use the reg_save_area. 11786 if (offsetMBB) { 11787 assert(OffsetReg != 0); 11788 11789 // Read the reg_save_area address. 11790 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11791 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11792 .addOperand(Base) 11793 .addOperand(Scale) 11794 .addOperand(Index) 11795 .addDisp(Disp, 16) 11796 .addOperand(Segment) 11797 .setMemRefs(MMOBegin, MMOEnd); 11798 11799 // Zero-extend the offset 11800 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11801 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11802 .addImm(0) 11803 .addReg(OffsetReg) 11804 .addImm(X86::sub_32bit); 11805 11806 // Add the offset to the reg_save_area to get the final address. 11807 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11808 .addReg(OffsetReg64) 11809 .addReg(RegSaveReg); 11810 11811 // Compute the offset for the next argument 11812 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11813 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11814 .addReg(OffsetReg) 11815 .addImm(UseFPOffset ? 16 : 8); 11816 11817 // Store it back into the va_list. 11818 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11819 .addOperand(Base) 11820 .addOperand(Scale) 11821 .addOperand(Index) 11822 .addDisp(Disp, UseFPOffset ? 4 : 0) 11823 .addOperand(Segment) 11824 .addReg(NextOffsetReg) 11825 .setMemRefs(MMOBegin, MMOEnd); 11826 11827 // Jump to endMBB 11828 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11829 .addMBB(endMBB); 11830 } 11831 11832 // 11833 // Emit code to use overflow area 11834 // 11835 11836 // Load the overflow_area address into a register. 11837 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11838 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11839 .addOperand(Base) 11840 .addOperand(Scale) 11841 .addOperand(Index) 11842 .addDisp(Disp, 8) 11843 .addOperand(Segment) 11844 .setMemRefs(MMOBegin, MMOEnd); 11845 11846 // If we need to align it, do so. Otherwise, just copy the address 11847 // to OverflowDestReg. 11848 if (NeedsAlign) { 11849 // Align the overflow address 11850 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11851 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11852 11853 // aligned_addr = (addr + (align-1)) & ~(align-1) 11854 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11855 .addReg(OverflowAddrReg) 11856 .addImm(Align-1); 11857 11858 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11859 .addReg(TmpReg) 11860 .addImm(~(uint64_t)(Align-1)); 11861 } else { 11862 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11863 .addReg(OverflowAddrReg); 11864 } 11865 11866 // Compute the next overflow address after this argument. 11867 // (the overflow address should be kept 8-byte aligned) 11868 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11869 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11870 .addReg(OverflowDestReg) 11871 .addImm(ArgSizeA8); 11872 11873 // Store the new overflow address. 11874 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11875 .addOperand(Base) 11876 .addOperand(Scale) 11877 .addOperand(Index) 11878 .addDisp(Disp, 8) 11879 .addOperand(Segment) 11880 .addReg(NextAddrReg) 11881 .setMemRefs(MMOBegin, MMOEnd); 11882 11883 // If we branched, emit the PHI to the front of endMBB. 11884 if (offsetMBB) { 11885 BuildMI(*endMBB, endMBB->begin(), DL, 11886 TII->get(X86::PHI), DestReg) 11887 .addReg(OffsetDestReg).addMBB(offsetMBB) 11888 .addReg(OverflowDestReg).addMBB(overflowMBB); 11889 } 11890 11891 // Erase the pseudo instruction 11892 MI->eraseFromParent(); 11893 11894 return endMBB; 11895} 11896 11897MachineBasicBlock * 11898X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11899 MachineInstr *MI, 11900 MachineBasicBlock *MBB) const { 11901 // Emit code to save XMM registers to the stack. The ABI says that the 11902 // number of registers to save is given in %al, so it's theoretically 11903 // possible to do an indirect jump trick to avoid saving all of them, 11904 // however this code takes a simpler approach and just executes all 11905 // of the stores if %al is non-zero. It's less code, and it's probably 11906 // easier on the hardware branch predictor, and stores aren't all that 11907 // expensive anyway. 11908 11909 // Create the new basic blocks. One block contains all the XMM stores, 11910 // and one block is the final destination regardless of whether any 11911 // stores were performed. 11912 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11913 MachineFunction *F = MBB->getParent(); 11914 MachineFunction::iterator MBBIter = MBB; 11915 ++MBBIter; 11916 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11917 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11918 F->insert(MBBIter, XMMSaveMBB); 11919 F->insert(MBBIter, EndMBB); 11920 11921 // Transfer the remainder of MBB and its successor edges to EndMBB. 11922 EndMBB->splice(EndMBB->begin(), MBB, 11923 llvm::next(MachineBasicBlock::iterator(MI)), 11924 MBB->end()); 11925 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11926 11927 // The original block will now fall through to the XMM save block. 11928 MBB->addSuccessor(XMMSaveMBB); 11929 // The XMMSaveMBB will fall through to the end block. 11930 XMMSaveMBB->addSuccessor(EndMBB); 11931 11932 // Now add the instructions. 11933 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11934 DebugLoc DL = MI->getDebugLoc(); 11935 11936 unsigned CountReg = MI->getOperand(0).getReg(); 11937 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11938 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11939 11940 if (!Subtarget->isTargetWin64()) { 11941 // If %al is 0, branch around the XMM save block. 11942 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11943 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11944 MBB->addSuccessor(EndMBB); 11945 } 11946 11947 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11948 // In the XMM save block, save all the XMM argument registers. 11949 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11950 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11951 MachineMemOperand *MMO = 11952 F->getMachineMemOperand( 11953 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11954 MachineMemOperand::MOStore, 11955 /*Size=*/16, /*Align=*/16); 11956 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11957 .addFrameIndex(RegSaveFrameIndex) 11958 .addImm(/*Scale=*/1) 11959 .addReg(/*IndexReg=*/0) 11960 .addImm(/*Disp=*/Offset) 11961 .addReg(/*Segment=*/0) 11962 .addReg(MI->getOperand(i).getReg()) 11963 .addMemOperand(MMO); 11964 } 11965 11966 MI->eraseFromParent(); // The pseudo instruction is gone now. 11967 11968 return EndMBB; 11969} 11970 11971// The EFLAGS operand of SelectItr might be missing a kill marker 11972// because there were multiple uses of EFLAGS, and ISel didn't know 11973// which to mark. Figure out whether SelectItr should have had a 11974// kill marker, and set it if it should. Returns the correct kill 11975// marker value. 11976static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 11977 MachineBasicBlock* BB, 11978 const TargetRegisterInfo* TRI) { 11979 // Scan forward through BB for a use/def of EFLAGS. 11980 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 11981 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 11982 const MachineInstr& mi = *miI; 11983 if (mi.readsRegister(X86::EFLAGS)) 11984 return false; 11985 if (mi.definesRegister(X86::EFLAGS)) 11986 break; // Should have kill-flag - update below. 11987 } 11988 11989 // If we hit the end of the block, check whether EFLAGS is live into a 11990 // successor. 11991 if (miI == BB->end()) { 11992 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 11993 sEnd = BB->succ_end(); 11994 sItr != sEnd; ++sItr) { 11995 MachineBasicBlock* succ = *sItr; 11996 if (succ->isLiveIn(X86::EFLAGS)) 11997 return false; 11998 } 11999 } 12000 12001 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12002 // out. SelectMI should have a kill flag on EFLAGS. 12003 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12004 return true; 12005} 12006 12007MachineBasicBlock * 12008X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12009 MachineBasicBlock *BB) const { 12010 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12011 DebugLoc DL = MI->getDebugLoc(); 12012 12013 // To "insert" a SELECT_CC instruction, we actually have to insert the 12014 // diamond control-flow pattern. The incoming instruction knows the 12015 // destination vreg to set, the condition code register to branch on, the 12016 // true/false values to select between, and a branch opcode to use. 12017 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12018 MachineFunction::iterator It = BB; 12019 ++It; 12020 12021 // thisMBB: 12022 // ... 12023 // TrueVal = ... 12024 // cmpTY ccX, r1, r2 12025 // bCC copy1MBB 12026 // fallthrough --> copy0MBB 12027 MachineBasicBlock *thisMBB = BB; 12028 MachineFunction *F = BB->getParent(); 12029 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12030 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12031 F->insert(It, copy0MBB); 12032 F->insert(It, sinkMBB); 12033 12034 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12035 // live into the sink and copy blocks. 12036 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12037 if (!MI->killsRegister(X86::EFLAGS) && 12038 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12039 copy0MBB->addLiveIn(X86::EFLAGS); 12040 sinkMBB->addLiveIn(X86::EFLAGS); 12041 } 12042 12043 // Transfer the remainder of BB and its successor edges to sinkMBB. 12044 sinkMBB->splice(sinkMBB->begin(), BB, 12045 llvm::next(MachineBasicBlock::iterator(MI)), 12046 BB->end()); 12047 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12048 12049 // Add the true and fallthrough blocks as its successors. 12050 BB->addSuccessor(copy0MBB); 12051 BB->addSuccessor(sinkMBB); 12052 12053 // Create the conditional branch instruction. 12054 unsigned Opc = 12055 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12056 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12057 12058 // copy0MBB: 12059 // %FalseValue = ... 12060 // # fallthrough to sinkMBB 12061 copy0MBB->addSuccessor(sinkMBB); 12062 12063 // sinkMBB: 12064 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12065 // ... 12066 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12067 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12068 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12069 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12070 12071 MI->eraseFromParent(); // The pseudo instruction is gone now. 12072 return sinkMBB; 12073} 12074 12075MachineBasicBlock * 12076X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12077 bool Is64Bit) const { 12078 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12079 DebugLoc DL = MI->getDebugLoc(); 12080 MachineFunction *MF = BB->getParent(); 12081 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12082 12083 assert(getTargetMachine().Options.EnableSegmentedStacks); 12084 12085 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12086 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12087 12088 // BB: 12089 // ... [Till the alloca] 12090 // If stacklet is not large enough, jump to mallocMBB 12091 // 12092 // bumpMBB: 12093 // Allocate by subtracting from RSP 12094 // Jump to continueMBB 12095 // 12096 // mallocMBB: 12097 // Allocate by call to runtime 12098 // 12099 // continueMBB: 12100 // ... 12101 // [rest of original BB] 12102 // 12103 12104 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12105 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12106 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12107 12108 MachineRegisterInfo &MRI = MF->getRegInfo(); 12109 const TargetRegisterClass *AddrRegClass = 12110 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12111 12112 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12113 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12114 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12115 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12116 sizeVReg = MI->getOperand(1).getReg(), 12117 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12118 12119 MachineFunction::iterator MBBIter = BB; 12120 ++MBBIter; 12121 12122 MF->insert(MBBIter, bumpMBB); 12123 MF->insert(MBBIter, mallocMBB); 12124 MF->insert(MBBIter, continueMBB); 12125 12126 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12127 (MachineBasicBlock::iterator(MI)), BB->end()); 12128 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12129 12130 // Add code to the main basic block to check if the stack limit has been hit, 12131 // and if so, jump to mallocMBB otherwise to bumpMBB. 12132 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12133 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12134 .addReg(tmpSPVReg).addReg(sizeVReg); 12135 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12136 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12137 .addReg(SPLimitVReg); 12138 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12139 12140 // bumpMBB simply decreases the stack pointer, since we know the current 12141 // stacklet has enough space. 12142 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12143 .addReg(SPLimitVReg); 12144 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12145 .addReg(SPLimitVReg); 12146 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12147 12148 // Calls into a routine in libgcc to allocate more space from the heap. 12149 const uint32_t *RegMask = 12150 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12151 if (Is64Bit) { 12152 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12153 .addReg(sizeVReg); 12154 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12155 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12156 .addRegMask(RegMask) 12157 .addReg(X86::RAX, RegState::ImplicitDefine); 12158 } else { 12159 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12160 .addImm(12); 12161 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12162 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12163 .addExternalSymbol("__morestack_allocate_stack_space") 12164 .addRegMask(RegMask) 12165 .addReg(X86::EAX, RegState::ImplicitDefine); 12166 } 12167 12168 if (!Is64Bit) 12169 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12170 .addImm(16); 12171 12172 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12173 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12174 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12175 12176 // Set up the CFG correctly. 12177 BB->addSuccessor(bumpMBB); 12178 BB->addSuccessor(mallocMBB); 12179 mallocMBB->addSuccessor(continueMBB); 12180 bumpMBB->addSuccessor(continueMBB); 12181 12182 // Take care of the PHI nodes. 12183 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12184 MI->getOperand(0).getReg()) 12185 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12186 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12187 12188 // Delete the original pseudo instruction. 12189 MI->eraseFromParent(); 12190 12191 // And we're done. 12192 return continueMBB; 12193} 12194 12195MachineBasicBlock * 12196X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12197 MachineBasicBlock *BB) const { 12198 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12199 DebugLoc DL = MI->getDebugLoc(); 12200 12201 assert(!Subtarget->isTargetEnvMacho()); 12202 12203 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12204 // non-trivial part is impdef of ESP. 12205 12206 if (Subtarget->isTargetWin64()) { 12207 if (Subtarget->isTargetCygMing()) { 12208 // ___chkstk(Mingw64): 12209 // Clobbers R10, R11, RAX and EFLAGS. 12210 // Updates RSP. 12211 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12212 .addExternalSymbol("___chkstk") 12213 .addReg(X86::RAX, RegState::Implicit) 12214 .addReg(X86::RSP, RegState::Implicit) 12215 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12216 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12217 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12218 } else { 12219 // __chkstk(MSVCRT): does not update stack pointer. 12220 // Clobbers R10, R11 and EFLAGS. 12221 // FIXME: RAX(allocated size) might be reused and not killed. 12222 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12223 .addExternalSymbol("__chkstk") 12224 .addReg(X86::RAX, RegState::Implicit) 12225 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12226 // RAX has the offset to subtracted from RSP. 12227 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12228 .addReg(X86::RSP) 12229 .addReg(X86::RAX); 12230 } 12231 } else { 12232 const char *StackProbeSymbol = 12233 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12234 12235 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12236 .addExternalSymbol(StackProbeSymbol) 12237 .addReg(X86::EAX, RegState::Implicit) 12238 .addReg(X86::ESP, RegState::Implicit) 12239 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12240 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12241 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12242 } 12243 12244 MI->eraseFromParent(); // The pseudo instruction is gone now. 12245 return BB; 12246} 12247 12248MachineBasicBlock * 12249X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12250 MachineBasicBlock *BB) const { 12251 // This is pretty easy. We're taking the value that we received from 12252 // our load from the relocation, sticking it in either RDI (x86-64) 12253 // or EAX and doing an indirect call. The return value will then 12254 // be in the normal return register. 12255 const X86InstrInfo *TII 12256 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12257 DebugLoc DL = MI->getDebugLoc(); 12258 MachineFunction *F = BB->getParent(); 12259 12260 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12261 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12262 12263 // Get a register mask for the lowered call. 12264 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12265 // proper register mask. 12266 const uint32_t *RegMask = 12267 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12268 if (Subtarget->is64Bit()) { 12269 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12270 TII->get(X86::MOV64rm), X86::RDI) 12271 .addReg(X86::RIP) 12272 .addImm(0).addReg(0) 12273 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12274 MI->getOperand(3).getTargetFlags()) 12275 .addReg(0); 12276 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12277 addDirectMem(MIB, X86::RDI); 12278 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12279 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12280 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12281 TII->get(X86::MOV32rm), X86::EAX) 12282 .addReg(0) 12283 .addImm(0).addReg(0) 12284 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12285 MI->getOperand(3).getTargetFlags()) 12286 .addReg(0); 12287 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12288 addDirectMem(MIB, X86::EAX); 12289 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12290 } else { 12291 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12292 TII->get(X86::MOV32rm), X86::EAX) 12293 .addReg(TII->getGlobalBaseReg(F)) 12294 .addImm(0).addReg(0) 12295 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12296 MI->getOperand(3).getTargetFlags()) 12297 .addReg(0); 12298 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12299 addDirectMem(MIB, X86::EAX); 12300 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12301 } 12302 12303 MI->eraseFromParent(); // The pseudo instruction is gone now. 12304 return BB; 12305} 12306 12307MachineBasicBlock * 12308X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12309 MachineBasicBlock *BB) const { 12310 switch (MI->getOpcode()) { 12311 default: llvm_unreachable("Unexpected instr type to insert"); 12312 case X86::TAILJMPd64: 12313 case X86::TAILJMPr64: 12314 case X86::TAILJMPm64: 12315 llvm_unreachable("TAILJMP64 would not be touched here."); 12316 case X86::TCRETURNdi64: 12317 case X86::TCRETURNri64: 12318 case X86::TCRETURNmi64: 12319 return BB; 12320 case X86::WIN_ALLOCA: 12321 return EmitLoweredWinAlloca(MI, BB); 12322 case X86::SEG_ALLOCA_32: 12323 return EmitLoweredSegAlloca(MI, BB, false); 12324 case X86::SEG_ALLOCA_64: 12325 return EmitLoweredSegAlloca(MI, BB, true); 12326 case X86::TLSCall_32: 12327 case X86::TLSCall_64: 12328 return EmitLoweredTLSCall(MI, BB); 12329 case X86::CMOV_GR8: 12330 case X86::CMOV_FR32: 12331 case X86::CMOV_FR64: 12332 case X86::CMOV_V4F32: 12333 case X86::CMOV_V2F64: 12334 case X86::CMOV_V2I64: 12335 case X86::CMOV_V8F32: 12336 case X86::CMOV_V4F64: 12337 case X86::CMOV_V4I64: 12338 case X86::CMOV_GR16: 12339 case X86::CMOV_GR32: 12340 case X86::CMOV_RFP32: 12341 case X86::CMOV_RFP64: 12342 case X86::CMOV_RFP80: 12343 return EmitLoweredSelect(MI, BB); 12344 12345 case X86::FP32_TO_INT16_IN_MEM: 12346 case X86::FP32_TO_INT32_IN_MEM: 12347 case X86::FP32_TO_INT64_IN_MEM: 12348 case X86::FP64_TO_INT16_IN_MEM: 12349 case X86::FP64_TO_INT32_IN_MEM: 12350 case X86::FP64_TO_INT64_IN_MEM: 12351 case X86::FP80_TO_INT16_IN_MEM: 12352 case X86::FP80_TO_INT32_IN_MEM: 12353 case X86::FP80_TO_INT64_IN_MEM: { 12354 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12355 DebugLoc DL = MI->getDebugLoc(); 12356 12357 // Change the floating point control register to use "round towards zero" 12358 // mode when truncating to an integer value. 12359 MachineFunction *F = BB->getParent(); 12360 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12361 addFrameReference(BuildMI(*BB, MI, DL, 12362 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12363 12364 // Load the old value of the high byte of the control word... 12365 unsigned OldCW = 12366 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12367 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12368 CWFrameIdx); 12369 12370 // Set the high part to be round to zero... 12371 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12372 .addImm(0xC7F); 12373 12374 // Reload the modified control word now... 12375 addFrameReference(BuildMI(*BB, MI, DL, 12376 TII->get(X86::FLDCW16m)), CWFrameIdx); 12377 12378 // Restore the memory image of control word to original value 12379 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12380 .addReg(OldCW); 12381 12382 // Get the X86 opcode to use. 12383 unsigned Opc; 12384 switch (MI->getOpcode()) { 12385 default: llvm_unreachable("illegal opcode!"); 12386 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12387 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12388 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12389 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12390 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12391 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12392 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12393 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12394 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12395 } 12396 12397 X86AddressMode AM; 12398 MachineOperand &Op = MI->getOperand(0); 12399 if (Op.isReg()) { 12400 AM.BaseType = X86AddressMode::RegBase; 12401 AM.Base.Reg = Op.getReg(); 12402 } else { 12403 AM.BaseType = X86AddressMode::FrameIndexBase; 12404 AM.Base.FrameIndex = Op.getIndex(); 12405 } 12406 Op = MI->getOperand(1); 12407 if (Op.isImm()) 12408 AM.Scale = Op.getImm(); 12409 Op = MI->getOperand(2); 12410 if (Op.isImm()) 12411 AM.IndexReg = Op.getImm(); 12412 Op = MI->getOperand(3); 12413 if (Op.isGlobal()) { 12414 AM.GV = Op.getGlobal(); 12415 } else { 12416 AM.Disp = Op.getImm(); 12417 } 12418 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12419 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12420 12421 // Reload the original control word now. 12422 addFrameReference(BuildMI(*BB, MI, DL, 12423 TII->get(X86::FLDCW16m)), CWFrameIdx); 12424 12425 MI->eraseFromParent(); // The pseudo instruction is gone now. 12426 return BB; 12427 } 12428 // String/text processing lowering. 12429 case X86::PCMPISTRM128REG: 12430 case X86::VPCMPISTRM128REG: 12431 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12432 case X86::PCMPISTRM128MEM: 12433 case X86::VPCMPISTRM128MEM: 12434 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12435 case X86::PCMPESTRM128REG: 12436 case X86::VPCMPESTRM128REG: 12437 return EmitPCMP(MI, BB, 5, false /* in mem */); 12438 case X86::PCMPESTRM128MEM: 12439 case X86::VPCMPESTRM128MEM: 12440 return EmitPCMP(MI, BB, 5, true /* in mem */); 12441 12442 // Thread synchronization. 12443 case X86::MONITOR: 12444 return EmitMonitor(MI, BB); 12445 case X86::MWAIT: 12446 return EmitMwait(MI, BB); 12447 12448 // Atomic Lowering. 12449 case X86::ATOMAND32: 12450 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12451 X86::AND32ri, X86::MOV32rm, 12452 X86::LCMPXCHG32, 12453 X86::NOT32r, X86::EAX, 12454 X86::GR32RegisterClass); 12455 case X86::ATOMOR32: 12456 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12457 X86::OR32ri, X86::MOV32rm, 12458 X86::LCMPXCHG32, 12459 X86::NOT32r, X86::EAX, 12460 X86::GR32RegisterClass); 12461 case X86::ATOMXOR32: 12462 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12463 X86::XOR32ri, X86::MOV32rm, 12464 X86::LCMPXCHG32, 12465 X86::NOT32r, X86::EAX, 12466 X86::GR32RegisterClass); 12467 case X86::ATOMNAND32: 12468 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12469 X86::AND32ri, X86::MOV32rm, 12470 X86::LCMPXCHG32, 12471 X86::NOT32r, X86::EAX, 12472 X86::GR32RegisterClass, true); 12473 case X86::ATOMMIN32: 12474 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12475 case X86::ATOMMAX32: 12476 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12477 case X86::ATOMUMIN32: 12478 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12479 case X86::ATOMUMAX32: 12480 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12481 12482 case X86::ATOMAND16: 12483 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12484 X86::AND16ri, X86::MOV16rm, 12485 X86::LCMPXCHG16, 12486 X86::NOT16r, X86::AX, 12487 X86::GR16RegisterClass); 12488 case X86::ATOMOR16: 12489 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12490 X86::OR16ri, X86::MOV16rm, 12491 X86::LCMPXCHG16, 12492 X86::NOT16r, X86::AX, 12493 X86::GR16RegisterClass); 12494 case X86::ATOMXOR16: 12495 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12496 X86::XOR16ri, X86::MOV16rm, 12497 X86::LCMPXCHG16, 12498 X86::NOT16r, X86::AX, 12499 X86::GR16RegisterClass); 12500 case X86::ATOMNAND16: 12501 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12502 X86::AND16ri, X86::MOV16rm, 12503 X86::LCMPXCHG16, 12504 X86::NOT16r, X86::AX, 12505 X86::GR16RegisterClass, true); 12506 case X86::ATOMMIN16: 12507 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12508 case X86::ATOMMAX16: 12509 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12510 case X86::ATOMUMIN16: 12511 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12512 case X86::ATOMUMAX16: 12513 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12514 12515 case X86::ATOMAND8: 12516 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12517 X86::AND8ri, X86::MOV8rm, 12518 X86::LCMPXCHG8, 12519 X86::NOT8r, X86::AL, 12520 X86::GR8RegisterClass); 12521 case X86::ATOMOR8: 12522 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12523 X86::OR8ri, X86::MOV8rm, 12524 X86::LCMPXCHG8, 12525 X86::NOT8r, X86::AL, 12526 X86::GR8RegisterClass); 12527 case X86::ATOMXOR8: 12528 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12529 X86::XOR8ri, X86::MOV8rm, 12530 X86::LCMPXCHG8, 12531 X86::NOT8r, X86::AL, 12532 X86::GR8RegisterClass); 12533 case X86::ATOMNAND8: 12534 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12535 X86::AND8ri, X86::MOV8rm, 12536 X86::LCMPXCHG8, 12537 X86::NOT8r, X86::AL, 12538 X86::GR8RegisterClass, true); 12539 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12540 // This group is for 64-bit host. 12541 case X86::ATOMAND64: 12542 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12543 X86::AND64ri32, X86::MOV64rm, 12544 X86::LCMPXCHG64, 12545 X86::NOT64r, X86::RAX, 12546 X86::GR64RegisterClass); 12547 case X86::ATOMOR64: 12548 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12549 X86::OR64ri32, X86::MOV64rm, 12550 X86::LCMPXCHG64, 12551 X86::NOT64r, X86::RAX, 12552 X86::GR64RegisterClass); 12553 case X86::ATOMXOR64: 12554 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12555 X86::XOR64ri32, X86::MOV64rm, 12556 X86::LCMPXCHG64, 12557 X86::NOT64r, X86::RAX, 12558 X86::GR64RegisterClass); 12559 case X86::ATOMNAND64: 12560 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12561 X86::AND64ri32, X86::MOV64rm, 12562 X86::LCMPXCHG64, 12563 X86::NOT64r, X86::RAX, 12564 X86::GR64RegisterClass, true); 12565 case X86::ATOMMIN64: 12566 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12567 case X86::ATOMMAX64: 12568 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12569 case X86::ATOMUMIN64: 12570 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12571 case X86::ATOMUMAX64: 12572 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12573 12574 // This group does 64-bit operations on a 32-bit host. 12575 case X86::ATOMAND6432: 12576 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12577 X86::AND32rr, X86::AND32rr, 12578 X86::AND32ri, X86::AND32ri, 12579 false); 12580 case X86::ATOMOR6432: 12581 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12582 X86::OR32rr, X86::OR32rr, 12583 X86::OR32ri, X86::OR32ri, 12584 false); 12585 case X86::ATOMXOR6432: 12586 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12587 X86::XOR32rr, X86::XOR32rr, 12588 X86::XOR32ri, X86::XOR32ri, 12589 false); 12590 case X86::ATOMNAND6432: 12591 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12592 X86::AND32rr, X86::AND32rr, 12593 X86::AND32ri, X86::AND32ri, 12594 true); 12595 case X86::ATOMADD6432: 12596 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12597 X86::ADD32rr, X86::ADC32rr, 12598 X86::ADD32ri, X86::ADC32ri, 12599 false); 12600 case X86::ATOMSUB6432: 12601 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12602 X86::SUB32rr, X86::SBB32rr, 12603 X86::SUB32ri, X86::SBB32ri, 12604 false); 12605 case X86::ATOMSWAP6432: 12606 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12607 X86::MOV32rr, X86::MOV32rr, 12608 X86::MOV32ri, X86::MOV32ri, 12609 false); 12610 case X86::VASTART_SAVE_XMM_REGS: 12611 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12612 12613 case X86::VAARG_64: 12614 return EmitVAARG64WithCustomInserter(MI, BB); 12615 } 12616} 12617 12618//===----------------------------------------------------------------------===// 12619// X86 Optimization Hooks 12620//===----------------------------------------------------------------------===// 12621 12622void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12623 const APInt &Mask, 12624 APInt &KnownZero, 12625 APInt &KnownOne, 12626 const SelectionDAG &DAG, 12627 unsigned Depth) const { 12628 unsigned Opc = Op.getOpcode(); 12629 assert((Opc >= ISD::BUILTIN_OP_END || 12630 Opc == ISD::INTRINSIC_WO_CHAIN || 12631 Opc == ISD::INTRINSIC_W_CHAIN || 12632 Opc == ISD::INTRINSIC_VOID) && 12633 "Should use MaskedValueIsZero if you don't know whether Op" 12634 " is a target node!"); 12635 12636 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12637 switch (Opc) { 12638 default: break; 12639 case X86ISD::ADD: 12640 case X86ISD::SUB: 12641 case X86ISD::ADC: 12642 case X86ISD::SBB: 12643 case X86ISD::SMUL: 12644 case X86ISD::UMUL: 12645 case X86ISD::INC: 12646 case X86ISD::DEC: 12647 case X86ISD::OR: 12648 case X86ISD::XOR: 12649 case X86ISD::AND: 12650 // These nodes' second result is a boolean. 12651 if (Op.getResNo() == 0) 12652 break; 12653 // Fallthrough 12654 case X86ISD::SETCC: 12655 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12656 Mask.getBitWidth() - 1); 12657 break; 12658 case ISD::INTRINSIC_WO_CHAIN: { 12659 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12660 unsigned NumLoBits = 0; 12661 switch (IntId) { 12662 default: break; 12663 case Intrinsic::x86_sse_movmsk_ps: 12664 case Intrinsic::x86_avx_movmsk_ps_256: 12665 case Intrinsic::x86_sse2_movmsk_pd: 12666 case Intrinsic::x86_avx_movmsk_pd_256: 12667 case Intrinsic::x86_mmx_pmovmskb: 12668 case Intrinsic::x86_sse2_pmovmskb_128: 12669 case Intrinsic::x86_avx2_pmovmskb: { 12670 // High bits of movmskp{s|d}, pmovmskb are known zero. 12671 switch (IntId) { 12672 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12673 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12674 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12675 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12676 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12677 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12678 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12679 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12680 } 12681 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12682 Mask.getBitWidth() - NumLoBits); 12683 break; 12684 } 12685 } 12686 break; 12687 } 12688 } 12689} 12690 12691unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12692 unsigned Depth) const { 12693 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12694 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12695 return Op.getValueType().getScalarType().getSizeInBits(); 12696 12697 // Fallback case. 12698 return 1; 12699} 12700 12701/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12702/// node is a GlobalAddress + offset. 12703bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12704 const GlobalValue* &GA, 12705 int64_t &Offset) const { 12706 if (N->getOpcode() == X86ISD::Wrapper) { 12707 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12708 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12709 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12710 return true; 12711 } 12712 } 12713 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12714} 12715 12716/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12717/// same as extracting the high 128-bit part of 256-bit vector and then 12718/// inserting the result into the low part of a new 256-bit vector 12719static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12720 EVT VT = SVOp->getValueType(0); 12721 int NumElems = VT.getVectorNumElements(); 12722 12723 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12724 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12725 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12726 SVOp->getMaskElt(j) >= 0) 12727 return false; 12728 12729 return true; 12730} 12731 12732/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12733/// same as extracting the low 128-bit part of 256-bit vector and then 12734/// inserting the result into the high part of a new 256-bit vector 12735static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12736 EVT VT = SVOp->getValueType(0); 12737 int NumElems = VT.getVectorNumElements(); 12738 12739 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12740 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12741 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12742 SVOp->getMaskElt(j) >= 0) 12743 return false; 12744 12745 return true; 12746} 12747 12748/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12749static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12750 TargetLowering::DAGCombinerInfo &DCI, 12751 const X86Subtarget* Subtarget) { 12752 DebugLoc dl = N->getDebugLoc(); 12753 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12754 SDValue V1 = SVOp->getOperand(0); 12755 SDValue V2 = SVOp->getOperand(1); 12756 EVT VT = SVOp->getValueType(0); 12757 int NumElems = VT.getVectorNumElements(); 12758 12759 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12760 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12761 // 12762 // 0,0,0,... 12763 // | 12764 // V UNDEF BUILD_VECTOR UNDEF 12765 // \ / \ / 12766 // CONCAT_VECTOR CONCAT_VECTOR 12767 // \ / 12768 // \ / 12769 // RESULT: V + zero extended 12770 // 12771 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12772 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12773 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12774 return SDValue(); 12775 12776 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12777 return SDValue(); 12778 12779 // To match the shuffle mask, the first half of the mask should 12780 // be exactly the first vector, and all the rest a splat with the 12781 // first element of the second one. 12782 for (int i = 0; i < NumElems/2; ++i) 12783 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12784 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12785 return SDValue(); 12786 12787 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12788 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12789 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12790 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12791 SDValue ResNode = 12792 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12793 Ld->getMemoryVT(), 12794 Ld->getPointerInfo(), 12795 Ld->getAlignment(), 12796 false/*isVolatile*/, true/*ReadMem*/, 12797 false/*WriteMem*/); 12798 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12799 } 12800 12801 // Emit a zeroed vector and insert the desired subvector on its 12802 // first half. 12803 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12804 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12805 DAG.getConstant(0, MVT::i32), DAG, dl); 12806 return DCI.CombineTo(N, InsV); 12807 } 12808 12809 //===--------------------------------------------------------------------===// 12810 // Combine some shuffles into subvector extracts and inserts: 12811 // 12812 12813 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12814 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12815 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12816 DAG, dl); 12817 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12818 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12819 return DCI.CombineTo(N, InsV); 12820 } 12821 12822 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12823 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12824 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12825 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12826 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12827 return DCI.CombineTo(N, InsV); 12828 } 12829 12830 return SDValue(); 12831} 12832 12833/// PerformShuffleCombine - Performs several different shuffle combines. 12834static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12835 TargetLowering::DAGCombinerInfo &DCI, 12836 const X86Subtarget *Subtarget) { 12837 DebugLoc dl = N->getDebugLoc(); 12838 EVT VT = N->getValueType(0); 12839 12840 // Don't create instructions with illegal types after legalize types has run. 12841 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12842 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12843 return SDValue(); 12844 12845 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12846 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12847 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12848 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 12849 12850 // Only handle 128 wide vector from here on. 12851 if (VT.getSizeInBits() != 128) 12852 return SDValue(); 12853 12854 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12855 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12856 // consecutive, non-overlapping, and in the right order. 12857 SmallVector<SDValue, 16> Elts; 12858 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12859 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12860 12861 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12862} 12863 12864 12865/// PerformTruncateCombine - Converts truncate operation to 12866/// a sequence of vector shuffle operations. 12867/// It is possible when we truncate 256-bit vector to 128-bit vector 12868 12869SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 12870 DAGCombinerInfo &DCI) const { 12871 if (!DCI.isBeforeLegalizeOps()) 12872 return SDValue(); 12873 12874 if (!Subtarget->hasAVX()) return SDValue(); 12875 12876 EVT VT = N->getValueType(0); 12877 SDValue Op = N->getOperand(0); 12878 EVT OpVT = Op.getValueType(); 12879 DebugLoc dl = N->getDebugLoc(); 12880 12881 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 12882 12883 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12884 DAG.getIntPtrConstant(0)); 12885 12886 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12887 DAG.getIntPtrConstant(2)); 12888 12889 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12890 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12891 12892 // PSHUFD 12893 int ShufMask1[] = {0, 2, 0, 0}; 12894 12895 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), 12896 ShufMask1); 12897 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), 12898 ShufMask1); 12899 12900 // MOVLHPS 12901 int ShufMask2[] = {0, 1, 4, 5}; 12902 12903 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 12904 } 12905 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 12906 12907 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12908 DAG.getIntPtrConstant(0)); 12909 12910 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12911 DAG.getIntPtrConstant(4)); 12912 12913 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 12914 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 12915 12916 // PSHUFB 12917 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 12918 -1, -1, -1, -1, -1, -1, -1, -1}; 12919 12920 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, 12921 DAG.getUNDEF(MVT::v16i8), 12922 ShufMask1); 12923 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, 12924 DAG.getUNDEF(MVT::v16i8), 12925 ShufMask1); 12926 12927 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12928 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12929 12930 // MOVLHPS 12931 int ShufMask2[] = {0, 1, 4, 5}; 12932 12933 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 12934 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 12935 } 12936 12937 return SDValue(); 12938} 12939 12940/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 12941/// specific shuffle of a load can be folded into a single element load. 12942/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 12943/// shuffles have been customed lowered so we need to handle those here. 12944static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 12945 TargetLowering::DAGCombinerInfo &DCI) { 12946 if (DCI.isBeforeLegalizeOps()) 12947 return SDValue(); 12948 12949 SDValue InVec = N->getOperand(0); 12950 SDValue EltNo = N->getOperand(1); 12951 12952 if (!isa<ConstantSDNode>(EltNo)) 12953 return SDValue(); 12954 12955 EVT VT = InVec.getValueType(); 12956 12957 bool HasShuffleIntoBitcast = false; 12958 if (InVec.getOpcode() == ISD::BITCAST) { 12959 // Don't duplicate a load with other uses. 12960 if (!InVec.hasOneUse()) 12961 return SDValue(); 12962 EVT BCVT = InVec.getOperand(0).getValueType(); 12963 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 12964 return SDValue(); 12965 InVec = InVec.getOperand(0); 12966 HasShuffleIntoBitcast = true; 12967 } 12968 12969 if (!isTargetShuffle(InVec.getOpcode())) 12970 return SDValue(); 12971 12972 // Don't duplicate a load with other uses. 12973 if (!InVec.hasOneUse()) 12974 return SDValue(); 12975 12976 SmallVector<int, 16> ShuffleMask; 12977 bool UnaryShuffle; 12978 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle)) 12979 return SDValue(); 12980 12981 // Select the input vector, guarding against out of range extract vector. 12982 unsigned NumElems = VT.getVectorNumElements(); 12983 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 12984 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 12985 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 12986 : InVec.getOperand(1); 12987 12988 // If inputs to shuffle are the same for both ops, then allow 2 uses 12989 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 12990 12991 if (LdNode.getOpcode() == ISD::BITCAST) { 12992 // Don't duplicate a load with other uses. 12993 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 12994 return SDValue(); 12995 12996 AllowedUses = 1; // only allow 1 load use if we have a bitcast 12997 LdNode = LdNode.getOperand(0); 12998 } 12999 13000 if (!ISD::isNormalLoad(LdNode.getNode())) 13001 return SDValue(); 13002 13003 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13004 13005 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13006 return SDValue(); 13007 13008 if (HasShuffleIntoBitcast) { 13009 // If there's a bitcast before the shuffle, check if the load type and 13010 // alignment is valid. 13011 unsigned Align = LN0->getAlignment(); 13012 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13013 unsigned NewAlign = TLI.getTargetData()-> 13014 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13015 13016 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13017 return SDValue(); 13018 } 13019 13020 // All checks match so transform back to vector_shuffle so that DAG combiner 13021 // can finish the job 13022 DebugLoc dl = N->getDebugLoc(); 13023 13024 // Create shuffle node taking into account the case that its a unary shuffle 13025 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13026 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13027 InVec.getOperand(0), Shuffle, 13028 &ShuffleMask[0]); 13029 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13030 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13031 EltNo); 13032} 13033 13034/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13035/// generation and convert it from being a bunch of shuffles and extracts 13036/// to a simple store and scalar loads to extract the elements. 13037static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13038 TargetLowering::DAGCombinerInfo &DCI) { 13039 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13040 if (NewOp.getNode()) 13041 return NewOp; 13042 13043 SDValue InputVector = N->getOperand(0); 13044 13045 // Only operate on vectors of 4 elements, where the alternative shuffling 13046 // gets to be more expensive. 13047 if (InputVector.getValueType() != MVT::v4i32) 13048 return SDValue(); 13049 13050 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13051 // single use which is a sign-extend or zero-extend, and all elements are 13052 // used. 13053 SmallVector<SDNode *, 4> Uses; 13054 unsigned ExtractedElements = 0; 13055 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13056 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13057 if (UI.getUse().getResNo() != InputVector.getResNo()) 13058 return SDValue(); 13059 13060 SDNode *Extract = *UI; 13061 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13062 return SDValue(); 13063 13064 if (Extract->getValueType(0) != MVT::i32) 13065 return SDValue(); 13066 if (!Extract->hasOneUse()) 13067 return SDValue(); 13068 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13069 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13070 return SDValue(); 13071 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13072 return SDValue(); 13073 13074 // Record which element was extracted. 13075 ExtractedElements |= 13076 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13077 13078 Uses.push_back(Extract); 13079 } 13080 13081 // If not all the elements were used, this may not be worthwhile. 13082 if (ExtractedElements != 15) 13083 return SDValue(); 13084 13085 // Ok, we've now decided to do the transformation. 13086 DebugLoc dl = InputVector.getDebugLoc(); 13087 13088 // Store the value to a temporary stack slot. 13089 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13090 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13091 MachinePointerInfo(), false, false, 0); 13092 13093 // Replace each use (extract) with a load of the appropriate element. 13094 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13095 UE = Uses.end(); UI != UE; ++UI) { 13096 SDNode *Extract = *UI; 13097 13098 // cOMpute the element's address. 13099 SDValue Idx = Extract->getOperand(1); 13100 unsigned EltSize = 13101 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13102 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13103 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13104 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13105 13106 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13107 StackPtr, OffsetVal); 13108 13109 // Load the scalar. 13110 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13111 ScalarAddr, MachinePointerInfo(), 13112 false, false, false, 0); 13113 13114 // Replace the exact with the load. 13115 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13116 } 13117 13118 // The replacement was made in place; don't return anything. 13119 return SDValue(); 13120} 13121 13122/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13123/// nodes. 13124static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13125 TargetLowering::DAGCombinerInfo &DCI, 13126 const X86Subtarget *Subtarget) { 13127 13128 13129 DebugLoc DL = N->getDebugLoc(); 13130 SDValue Cond = N->getOperand(0); 13131 // Get the LHS/RHS of the select. 13132 SDValue LHS = N->getOperand(1); 13133 SDValue RHS = N->getOperand(2); 13134 EVT VT = LHS.getValueType(); 13135 13136 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13137 // instructions match the semantics of the common C idiom x<y?x:y but not 13138 // x<=y?x:y, because of how they handle negative zero (which can be 13139 // ignored in unsafe-math mode). 13140 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13141 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13142 (Subtarget->hasSSE2() || 13143 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13144 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13145 13146 unsigned Opcode = 0; 13147 // Check for x CC y ? x : y. 13148 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13149 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13150 switch (CC) { 13151 default: break; 13152 case ISD::SETULT: 13153 // Converting this to a min would handle NaNs incorrectly, and swapping 13154 // the operands would cause it to handle comparisons between positive 13155 // and negative zero incorrectly. 13156 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13157 if (!DAG.getTarget().Options.UnsafeFPMath && 13158 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13159 break; 13160 std::swap(LHS, RHS); 13161 } 13162 Opcode = X86ISD::FMIN; 13163 break; 13164 case ISD::SETOLE: 13165 // Converting this to a min would handle comparisons between positive 13166 // and negative zero incorrectly. 13167 if (!DAG.getTarget().Options.UnsafeFPMath && 13168 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13169 break; 13170 Opcode = X86ISD::FMIN; 13171 break; 13172 case ISD::SETULE: 13173 // Converting this to a min would handle both negative zeros and NaNs 13174 // incorrectly, but we can swap the operands to fix both. 13175 std::swap(LHS, RHS); 13176 case ISD::SETOLT: 13177 case ISD::SETLT: 13178 case ISD::SETLE: 13179 Opcode = X86ISD::FMIN; 13180 break; 13181 13182 case ISD::SETOGE: 13183 // Converting this to a max would handle comparisons between positive 13184 // and negative zero incorrectly. 13185 if (!DAG.getTarget().Options.UnsafeFPMath && 13186 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13187 break; 13188 Opcode = X86ISD::FMAX; 13189 break; 13190 case ISD::SETUGT: 13191 // Converting this to a max would handle NaNs incorrectly, and swapping 13192 // the operands would cause it to handle comparisons between positive 13193 // and negative zero incorrectly. 13194 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13195 if (!DAG.getTarget().Options.UnsafeFPMath && 13196 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13197 break; 13198 std::swap(LHS, RHS); 13199 } 13200 Opcode = X86ISD::FMAX; 13201 break; 13202 case ISD::SETUGE: 13203 // Converting this to a max would handle both negative zeros and NaNs 13204 // incorrectly, but we can swap the operands to fix both. 13205 std::swap(LHS, RHS); 13206 case ISD::SETOGT: 13207 case ISD::SETGT: 13208 case ISD::SETGE: 13209 Opcode = X86ISD::FMAX; 13210 break; 13211 } 13212 // Check for x CC y ? y : x -- a min/max with reversed arms. 13213 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13214 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13215 switch (CC) { 13216 default: break; 13217 case ISD::SETOGE: 13218 // Converting this to a min would handle comparisons between positive 13219 // and negative zero incorrectly, and swapping the operands would 13220 // cause it to handle NaNs incorrectly. 13221 if (!DAG.getTarget().Options.UnsafeFPMath && 13222 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13223 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13224 break; 13225 std::swap(LHS, RHS); 13226 } 13227 Opcode = X86ISD::FMIN; 13228 break; 13229 case ISD::SETUGT: 13230 // Converting this to a min would handle NaNs incorrectly. 13231 if (!DAG.getTarget().Options.UnsafeFPMath && 13232 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13233 break; 13234 Opcode = X86ISD::FMIN; 13235 break; 13236 case ISD::SETUGE: 13237 // Converting this to a min would handle both negative zeros and NaNs 13238 // incorrectly, but we can swap the operands to fix both. 13239 std::swap(LHS, RHS); 13240 case ISD::SETOGT: 13241 case ISD::SETGT: 13242 case ISD::SETGE: 13243 Opcode = X86ISD::FMIN; 13244 break; 13245 13246 case ISD::SETULT: 13247 // Converting this to a max would handle NaNs incorrectly. 13248 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13249 break; 13250 Opcode = X86ISD::FMAX; 13251 break; 13252 case ISD::SETOLE: 13253 // Converting this to a max would handle comparisons between positive 13254 // and negative zero incorrectly, and swapping the operands would 13255 // cause it to handle NaNs incorrectly. 13256 if (!DAG.getTarget().Options.UnsafeFPMath && 13257 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13258 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13259 break; 13260 std::swap(LHS, RHS); 13261 } 13262 Opcode = X86ISD::FMAX; 13263 break; 13264 case ISD::SETULE: 13265 // Converting this to a max would handle both negative zeros and NaNs 13266 // incorrectly, but we can swap the operands to fix both. 13267 std::swap(LHS, RHS); 13268 case ISD::SETOLT: 13269 case ISD::SETLT: 13270 case ISD::SETLE: 13271 Opcode = X86ISD::FMAX; 13272 break; 13273 } 13274 } 13275 13276 if (Opcode) 13277 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13278 } 13279 13280 // If this is a select between two integer constants, try to do some 13281 // optimizations. 13282 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13283 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13284 // Don't do this for crazy integer types. 13285 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13286 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13287 // so that TrueC (the true value) is larger than FalseC. 13288 bool NeedsCondInvert = false; 13289 13290 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13291 // Efficiently invertible. 13292 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13293 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13294 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13295 NeedsCondInvert = true; 13296 std::swap(TrueC, FalseC); 13297 } 13298 13299 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13300 if (FalseC->getAPIntValue() == 0 && 13301 TrueC->getAPIntValue().isPowerOf2()) { 13302 if (NeedsCondInvert) // Invert the condition if needed. 13303 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13304 DAG.getConstant(1, Cond.getValueType())); 13305 13306 // Zero extend the condition if needed. 13307 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13308 13309 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13310 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13311 DAG.getConstant(ShAmt, MVT::i8)); 13312 } 13313 13314 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13315 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13316 if (NeedsCondInvert) // Invert the condition if needed. 13317 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13318 DAG.getConstant(1, Cond.getValueType())); 13319 13320 // Zero extend the condition if needed. 13321 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13322 FalseC->getValueType(0), Cond); 13323 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13324 SDValue(FalseC, 0)); 13325 } 13326 13327 // Optimize cases that will turn into an LEA instruction. This requires 13328 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13329 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13330 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13331 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13332 13333 bool isFastMultiplier = false; 13334 if (Diff < 10) { 13335 switch ((unsigned char)Diff) { 13336 default: break; 13337 case 1: // result = add base, cond 13338 case 2: // result = lea base( , cond*2) 13339 case 3: // result = lea base(cond, cond*2) 13340 case 4: // result = lea base( , cond*4) 13341 case 5: // result = lea base(cond, cond*4) 13342 case 8: // result = lea base( , cond*8) 13343 case 9: // result = lea base(cond, cond*8) 13344 isFastMultiplier = true; 13345 break; 13346 } 13347 } 13348 13349 if (isFastMultiplier) { 13350 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13351 if (NeedsCondInvert) // Invert the condition if needed. 13352 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13353 DAG.getConstant(1, Cond.getValueType())); 13354 13355 // Zero extend the condition if needed. 13356 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13357 Cond); 13358 // Scale the condition by the difference. 13359 if (Diff != 1) 13360 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13361 DAG.getConstant(Diff, Cond.getValueType())); 13362 13363 // Add the base if non-zero. 13364 if (FalseC->getAPIntValue() != 0) 13365 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13366 SDValue(FalseC, 0)); 13367 return Cond; 13368 } 13369 } 13370 } 13371 } 13372 13373 // Canonicalize max and min: 13374 // (x > y) ? x : y -> (x >= y) ? x : y 13375 // (x < y) ? x : y -> (x <= y) ? x : y 13376 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13377 // the need for an extra compare 13378 // against zero. e.g. 13379 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13380 // subl %esi, %edi 13381 // testl %edi, %edi 13382 // movl $0, %eax 13383 // cmovgl %edi, %eax 13384 // => 13385 // xorl %eax, %eax 13386 // subl %esi, $edi 13387 // cmovsl %eax, %edi 13388 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13389 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13390 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13391 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13392 switch (CC) { 13393 default: break; 13394 case ISD::SETLT: 13395 case ISD::SETGT: { 13396 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13397 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13398 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13399 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13400 } 13401 } 13402 } 13403 13404 // If we know that this node is legal then we know that it is going to be 13405 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13406 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13407 // to simplify previous instructions. 13408 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13409 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13410 !DCI.isBeforeLegalize() && 13411 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13412 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13413 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13414 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13415 13416 APInt KnownZero, KnownOne; 13417 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13418 DCI.isBeforeLegalizeOps()); 13419 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13420 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13421 DCI.CommitTargetLoweringOpt(TLO); 13422 } 13423 13424 return SDValue(); 13425} 13426 13427/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13428static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13429 TargetLowering::DAGCombinerInfo &DCI) { 13430 DebugLoc DL = N->getDebugLoc(); 13431 13432 // If the flag operand isn't dead, don't touch this CMOV. 13433 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13434 return SDValue(); 13435 13436 SDValue FalseOp = N->getOperand(0); 13437 SDValue TrueOp = N->getOperand(1); 13438 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13439 SDValue Cond = N->getOperand(3); 13440 if (CC == X86::COND_E || CC == X86::COND_NE) { 13441 switch (Cond.getOpcode()) { 13442 default: break; 13443 case X86ISD::BSR: 13444 case X86ISD::BSF: 13445 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13446 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13447 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13448 } 13449 } 13450 13451 // If this is a select between two integer constants, try to do some 13452 // optimizations. Note that the operands are ordered the opposite of SELECT 13453 // operands. 13454 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13455 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13456 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13457 // larger than FalseC (the false value). 13458 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13459 CC = X86::GetOppositeBranchCondition(CC); 13460 std::swap(TrueC, FalseC); 13461 } 13462 13463 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13464 // This is efficient for any integer data type (including i8/i16) and 13465 // shift amount. 13466 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13467 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13468 DAG.getConstant(CC, MVT::i8), Cond); 13469 13470 // Zero extend the condition if needed. 13471 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13472 13473 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13474 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13475 DAG.getConstant(ShAmt, MVT::i8)); 13476 if (N->getNumValues() == 2) // Dead flag value? 13477 return DCI.CombineTo(N, Cond, SDValue()); 13478 return Cond; 13479 } 13480 13481 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13482 // for any integer data type, including i8/i16. 13483 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13484 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13485 DAG.getConstant(CC, MVT::i8), Cond); 13486 13487 // Zero extend the condition if needed. 13488 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13489 FalseC->getValueType(0), Cond); 13490 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13491 SDValue(FalseC, 0)); 13492 13493 if (N->getNumValues() == 2) // Dead flag value? 13494 return DCI.CombineTo(N, Cond, SDValue()); 13495 return Cond; 13496 } 13497 13498 // Optimize cases that will turn into an LEA instruction. This requires 13499 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13500 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13501 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13502 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13503 13504 bool isFastMultiplier = false; 13505 if (Diff < 10) { 13506 switch ((unsigned char)Diff) { 13507 default: break; 13508 case 1: // result = add base, cond 13509 case 2: // result = lea base( , cond*2) 13510 case 3: // result = lea base(cond, cond*2) 13511 case 4: // result = lea base( , cond*4) 13512 case 5: // result = lea base(cond, cond*4) 13513 case 8: // result = lea base( , cond*8) 13514 case 9: // result = lea base(cond, cond*8) 13515 isFastMultiplier = true; 13516 break; 13517 } 13518 } 13519 13520 if (isFastMultiplier) { 13521 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13522 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13523 DAG.getConstant(CC, MVT::i8), Cond); 13524 // Zero extend the condition if needed. 13525 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13526 Cond); 13527 // Scale the condition by the difference. 13528 if (Diff != 1) 13529 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13530 DAG.getConstant(Diff, Cond.getValueType())); 13531 13532 // Add the base if non-zero. 13533 if (FalseC->getAPIntValue() != 0) 13534 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13535 SDValue(FalseC, 0)); 13536 if (N->getNumValues() == 2) // Dead flag value? 13537 return DCI.CombineTo(N, Cond, SDValue()); 13538 return Cond; 13539 } 13540 } 13541 } 13542 } 13543 return SDValue(); 13544} 13545 13546 13547/// PerformMulCombine - Optimize a single multiply with constant into two 13548/// in order to implement it with two cheaper instructions, e.g. 13549/// LEA + SHL, LEA + LEA. 13550static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13551 TargetLowering::DAGCombinerInfo &DCI) { 13552 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13553 return SDValue(); 13554 13555 EVT VT = N->getValueType(0); 13556 if (VT != MVT::i64) 13557 return SDValue(); 13558 13559 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13560 if (!C) 13561 return SDValue(); 13562 uint64_t MulAmt = C->getZExtValue(); 13563 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13564 return SDValue(); 13565 13566 uint64_t MulAmt1 = 0; 13567 uint64_t MulAmt2 = 0; 13568 if ((MulAmt % 9) == 0) { 13569 MulAmt1 = 9; 13570 MulAmt2 = MulAmt / 9; 13571 } else if ((MulAmt % 5) == 0) { 13572 MulAmt1 = 5; 13573 MulAmt2 = MulAmt / 5; 13574 } else if ((MulAmt % 3) == 0) { 13575 MulAmt1 = 3; 13576 MulAmt2 = MulAmt / 3; 13577 } 13578 if (MulAmt2 && 13579 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13580 DebugLoc DL = N->getDebugLoc(); 13581 13582 if (isPowerOf2_64(MulAmt2) && 13583 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13584 // If second multiplifer is pow2, issue it first. We want the multiply by 13585 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13586 // is an add. 13587 std::swap(MulAmt1, MulAmt2); 13588 13589 SDValue NewMul; 13590 if (isPowerOf2_64(MulAmt1)) 13591 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13592 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13593 else 13594 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13595 DAG.getConstant(MulAmt1, VT)); 13596 13597 if (isPowerOf2_64(MulAmt2)) 13598 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13599 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13600 else 13601 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13602 DAG.getConstant(MulAmt2, VT)); 13603 13604 // Do not add new nodes to DAG combiner worklist. 13605 DCI.CombineTo(N, NewMul, false); 13606 } 13607 return SDValue(); 13608} 13609 13610static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13611 SDValue N0 = N->getOperand(0); 13612 SDValue N1 = N->getOperand(1); 13613 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13614 EVT VT = N0.getValueType(); 13615 13616 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13617 // since the result of setcc_c is all zero's or all ones. 13618 if (VT.isInteger() && !VT.isVector() && 13619 N1C && N0.getOpcode() == ISD::AND && 13620 N0.getOperand(1).getOpcode() == ISD::Constant) { 13621 SDValue N00 = N0.getOperand(0); 13622 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13623 ((N00.getOpcode() == ISD::ANY_EXTEND || 13624 N00.getOpcode() == ISD::ZERO_EXTEND) && 13625 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13626 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13627 APInt ShAmt = N1C->getAPIntValue(); 13628 Mask = Mask.shl(ShAmt); 13629 if (Mask != 0) 13630 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13631 N00, DAG.getConstant(Mask, VT)); 13632 } 13633 } 13634 13635 13636 // Hardware support for vector shifts is sparse which makes us scalarize the 13637 // vector operations in many cases. Also, on sandybridge ADD is faster than 13638 // shl. 13639 // (shl V, 1) -> add V,V 13640 if (isSplatVector(N1.getNode())) { 13641 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13642 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13643 // We shift all of the values by one. In many cases we do not have 13644 // hardware support for this operation. This is better expressed as an ADD 13645 // of two values. 13646 if (N1C && (1 == N1C->getZExtValue())) { 13647 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13648 } 13649 } 13650 13651 return SDValue(); 13652} 13653 13654/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13655/// when possible. 13656static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13657 TargetLowering::DAGCombinerInfo &DCI, 13658 const X86Subtarget *Subtarget) { 13659 EVT VT = N->getValueType(0); 13660 if (N->getOpcode() == ISD::SHL) { 13661 SDValue V = PerformSHLCombine(N, DAG); 13662 if (V.getNode()) return V; 13663 } 13664 13665 // On X86 with SSE2 support, we can transform this to a vector shift if 13666 // all elements are shifted by the same amount. We can't do this in legalize 13667 // because the a constant vector is typically transformed to a constant pool 13668 // so we have no knowledge of the shift amount. 13669 if (!Subtarget->hasSSE2()) 13670 return SDValue(); 13671 13672 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13673 (!Subtarget->hasAVX2() || 13674 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13675 return SDValue(); 13676 13677 SDValue ShAmtOp = N->getOperand(1); 13678 EVT EltVT = VT.getVectorElementType(); 13679 DebugLoc DL = N->getDebugLoc(); 13680 SDValue BaseShAmt = SDValue(); 13681 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13682 unsigned NumElts = VT.getVectorNumElements(); 13683 unsigned i = 0; 13684 for (; i != NumElts; ++i) { 13685 SDValue Arg = ShAmtOp.getOperand(i); 13686 if (Arg.getOpcode() == ISD::UNDEF) continue; 13687 BaseShAmt = Arg; 13688 break; 13689 } 13690 // Handle the case where the build_vector is all undef 13691 // FIXME: Should DAG allow this? 13692 if (i == NumElts) 13693 return SDValue(); 13694 13695 for (; i != NumElts; ++i) { 13696 SDValue Arg = ShAmtOp.getOperand(i); 13697 if (Arg.getOpcode() == ISD::UNDEF) continue; 13698 if (Arg != BaseShAmt) { 13699 return SDValue(); 13700 } 13701 } 13702 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13703 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13704 SDValue InVec = ShAmtOp.getOperand(0); 13705 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13706 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13707 unsigned i = 0; 13708 for (; i != NumElts; ++i) { 13709 SDValue Arg = InVec.getOperand(i); 13710 if (Arg.getOpcode() == ISD::UNDEF) continue; 13711 BaseShAmt = Arg; 13712 break; 13713 } 13714 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13715 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13716 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13717 if (C->getZExtValue() == SplatIdx) 13718 BaseShAmt = InVec.getOperand(1); 13719 } 13720 } 13721 if (BaseShAmt.getNode() == 0) { 13722 // Don't create instructions with illegal types after legalize 13723 // types has run. 13724 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13725 !DCI.isBeforeLegalize()) 13726 return SDValue(); 13727 13728 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13729 DAG.getIntPtrConstant(0)); 13730 } 13731 } else 13732 return SDValue(); 13733 13734 // The shift amount is an i32. 13735 if (EltVT.bitsGT(MVT::i32)) 13736 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13737 else if (EltVT.bitsLT(MVT::i32)) 13738 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13739 13740 // The shift amount is identical so we can do a vector shift. 13741 SDValue ValOp = N->getOperand(0); 13742 switch (N->getOpcode()) { 13743 default: 13744 llvm_unreachable("Unknown shift opcode!"); 13745 case ISD::SHL: 13746 switch (VT.getSimpleVT().SimpleTy) { 13747 default: return SDValue(); 13748 case MVT::v2i64: 13749 case MVT::v4i32: 13750 case MVT::v8i16: 13751 case MVT::v4i64: 13752 case MVT::v8i32: 13753 case MVT::v16i16: 13754 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13755 } 13756 case ISD::SRA: 13757 switch (VT.getSimpleVT().SimpleTy) { 13758 default: return SDValue(); 13759 case MVT::v4i32: 13760 case MVT::v8i16: 13761 case MVT::v8i32: 13762 case MVT::v16i16: 13763 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13764 } 13765 case ISD::SRL: 13766 switch (VT.getSimpleVT().SimpleTy) { 13767 default: return SDValue(); 13768 case MVT::v2i64: 13769 case MVT::v4i32: 13770 case MVT::v8i16: 13771 case MVT::v4i64: 13772 case MVT::v8i32: 13773 case MVT::v16i16: 13774 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13775 } 13776 } 13777} 13778 13779 13780// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13781// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13782// and friends. Likewise for OR -> CMPNEQSS. 13783static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13784 TargetLowering::DAGCombinerInfo &DCI, 13785 const X86Subtarget *Subtarget) { 13786 unsigned opcode; 13787 13788 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13789 // we're requiring SSE2 for both. 13790 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13791 SDValue N0 = N->getOperand(0); 13792 SDValue N1 = N->getOperand(1); 13793 SDValue CMP0 = N0->getOperand(1); 13794 SDValue CMP1 = N1->getOperand(1); 13795 DebugLoc DL = N->getDebugLoc(); 13796 13797 // The SETCCs should both refer to the same CMP. 13798 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13799 return SDValue(); 13800 13801 SDValue CMP00 = CMP0->getOperand(0); 13802 SDValue CMP01 = CMP0->getOperand(1); 13803 EVT VT = CMP00.getValueType(); 13804 13805 if (VT == MVT::f32 || VT == MVT::f64) { 13806 bool ExpectingFlags = false; 13807 // Check for any users that want flags: 13808 for (SDNode::use_iterator UI = N->use_begin(), 13809 UE = N->use_end(); 13810 !ExpectingFlags && UI != UE; ++UI) 13811 switch (UI->getOpcode()) { 13812 default: 13813 case ISD::BR_CC: 13814 case ISD::BRCOND: 13815 case ISD::SELECT: 13816 ExpectingFlags = true; 13817 break; 13818 case ISD::CopyToReg: 13819 case ISD::SIGN_EXTEND: 13820 case ISD::ZERO_EXTEND: 13821 case ISD::ANY_EXTEND: 13822 break; 13823 } 13824 13825 if (!ExpectingFlags) { 13826 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13827 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13828 13829 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13830 X86::CondCode tmp = cc0; 13831 cc0 = cc1; 13832 cc1 = tmp; 13833 } 13834 13835 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13836 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13837 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13838 X86ISD::NodeType NTOperator = is64BitFP ? 13839 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13840 // FIXME: need symbolic constants for these magic numbers. 13841 // See X86ATTInstPrinter.cpp:printSSECC(). 13842 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13843 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13844 DAG.getConstant(x86cc, MVT::i8)); 13845 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13846 OnesOrZeroesF); 13847 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13848 DAG.getConstant(1, MVT::i32)); 13849 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13850 return OneBitOfTruth; 13851 } 13852 } 13853 } 13854 } 13855 return SDValue(); 13856} 13857 13858/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13859/// so it can be folded inside ANDNP. 13860static bool CanFoldXORWithAllOnes(const SDNode *N) { 13861 EVT VT = N->getValueType(0); 13862 13863 // Match direct AllOnes for 128 and 256-bit vectors 13864 if (ISD::isBuildVectorAllOnes(N)) 13865 return true; 13866 13867 // Look through a bit convert. 13868 if (N->getOpcode() == ISD::BITCAST) 13869 N = N->getOperand(0).getNode(); 13870 13871 // Sometimes the operand may come from a insert_subvector building a 256-bit 13872 // allones vector 13873 if (VT.getSizeInBits() == 256 && 13874 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13875 SDValue V1 = N->getOperand(0); 13876 SDValue V2 = N->getOperand(1); 13877 13878 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13879 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13880 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13881 ISD::isBuildVectorAllOnes(V2.getNode())) 13882 return true; 13883 } 13884 13885 return false; 13886} 13887 13888static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13889 TargetLowering::DAGCombinerInfo &DCI, 13890 const X86Subtarget *Subtarget) { 13891 if (DCI.isBeforeLegalizeOps()) 13892 return SDValue(); 13893 13894 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13895 if (R.getNode()) 13896 return R; 13897 13898 EVT VT = N->getValueType(0); 13899 13900 // Create ANDN, BLSI, and BLSR instructions 13901 // BLSI is X & (-X) 13902 // BLSR is X & (X-1) 13903 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13904 SDValue N0 = N->getOperand(0); 13905 SDValue N1 = N->getOperand(1); 13906 DebugLoc DL = N->getDebugLoc(); 13907 13908 // Check LHS for not 13909 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13910 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13911 // Check RHS for not 13912 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13913 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13914 13915 // Check LHS for neg 13916 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13917 isZero(N0.getOperand(0))) 13918 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13919 13920 // Check RHS for neg 13921 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13922 isZero(N1.getOperand(0))) 13923 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13924 13925 // Check LHS for X-1 13926 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13927 isAllOnes(N0.getOperand(1))) 13928 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13929 13930 // Check RHS for X-1 13931 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13932 isAllOnes(N1.getOperand(1))) 13933 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13934 13935 return SDValue(); 13936 } 13937 13938 // Want to form ANDNP nodes: 13939 // 1) In the hopes of then easily combining them with OR and AND nodes 13940 // to form PBLEND/PSIGN. 13941 // 2) To match ANDN packed intrinsics 13942 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13943 return SDValue(); 13944 13945 SDValue N0 = N->getOperand(0); 13946 SDValue N1 = N->getOperand(1); 13947 DebugLoc DL = N->getDebugLoc(); 13948 13949 // Check LHS for vnot 13950 if (N0.getOpcode() == ISD::XOR && 13951 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13952 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13953 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13954 13955 // Check RHS for vnot 13956 if (N1.getOpcode() == ISD::XOR && 13957 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13958 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13959 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13960 13961 return SDValue(); 13962} 13963 13964static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13965 TargetLowering::DAGCombinerInfo &DCI, 13966 const X86Subtarget *Subtarget) { 13967 if (DCI.isBeforeLegalizeOps()) 13968 return SDValue(); 13969 13970 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13971 if (R.getNode()) 13972 return R; 13973 13974 EVT VT = N->getValueType(0); 13975 13976 SDValue N0 = N->getOperand(0); 13977 SDValue N1 = N->getOperand(1); 13978 13979 // look for psign/blend 13980 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13981 if (!Subtarget->hasSSSE3() || 13982 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13983 return SDValue(); 13984 13985 // Canonicalize pandn to RHS 13986 if (N0.getOpcode() == X86ISD::ANDNP) 13987 std::swap(N0, N1); 13988 // or (and (m, y), (pandn m, x)) 13989 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13990 SDValue Mask = N1.getOperand(0); 13991 SDValue X = N1.getOperand(1); 13992 SDValue Y; 13993 if (N0.getOperand(0) == Mask) 13994 Y = N0.getOperand(1); 13995 if (N0.getOperand(1) == Mask) 13996 Y = N0.getOperand(0); 13997 13998 // Check to see if the mask appeared in both the AND and ANDNP and 13999 if (!Y.getNode()) 14000 return SDValue(); 14001 14002 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14003 if (Mask.getOpcode() != ISD::BITCAST || 14004 X.getOpcode() != ISD::BITCAST || 14005 Y.getOpcode() != ISD::BITCAST) 14006 return SDValue(); 14007 14008 // Look through mask bitcast. 14009 Mask = Mask.getOperand(0); 14010 EVT MaskVT = Mask.getValueType(); 14011 14012 // Validate that the Mask operand is a vector sra node. 14013 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14014 // there is no psrai.b 14015 if (Mask.getOpcode() != X86ISD::VSRAI) 14016 return SDValue(); 14017 14018 // Check that the SRA is all signbits. 14019 SDValue SraC = Mask.getOperand(1); 14020 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14021 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14022 if ((SraAmt + 1) != EltBits) 14023 return SDValue(); 14024 14025 DebugLoc DL = N->getDebugLoc(); 14026 14027 // Now we know we at least have a plendvb with the mask val. See if 14028 // we can form a psignb/w/d. 14029 // psign = x.type == y.type == mask.type && y = sub(0, x); 14030 X = X.getOperand(0); 14031 Y = Y.getOperand(0); 14032 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14033 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14034 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14035 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14036 "Unsupported VT for PSIGN"); 14037 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14038 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14039 } 14040 // PBLENDVB only available on SSE 4.1 14041 if (!Subtarget->hasSSE41()) 14042 return SDValue(); 14043 14044 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14045 14046 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14047 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14048 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14049 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14050 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14051 } 14052 } 14053 14054 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14055 return SDValue(); 14056 14057 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14058 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14059 std::swap(N0, N1); 14060 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14061 return SDValue(); 14062 if (!N0.hasOneUse() || !N1.hasOneUse()) 14063 return SDValue(); 14064 14065 SDValue ShAmt0 = N0.getOperand(1); 14066 if (ShAmt0.getValueType() != MVT::i8) 14067 return SDValue(); 14068 SDValue ShAmt1 = N1.getOperand(1); 14069 if (ShAmt1.getValueType() != MVT::i8) 14070 return SDValue(); 14071 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14072 ShAmt0 = ShAmt0.getOperand(0); 14073 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14074 ShAmt1 = ShAmt1.getOperand(0); 14075 14076 DebugLoc DL = N->getDebugLoc(); 14077 unsigned Opc = X86ISD::SHLD; 14078 SDValue Op0 = N0.getOperand(0); 14079 SDValue Op1 = N1.getOperand(0); 14080 if (ShAmt0.getOpcode() == ISD::SUB) { 14081 Opc = X86ISD::SHRD; 14082 std::swap(Op0, Op1); 14083 std::swap(ShAmt0, ShAmt1); 14084 } 14085 14086 unsigned Bits = VT.getSizeInBits(); 14087 if (ShAmt1.getOpcode() == ISD::SUB) { 14088 SDValue Sum = ShAmt1.getOperand(0); 14089 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14090 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14091 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14092 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14093 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14094 return DAG.getNode(Opc, DL, VT, 14095 Op0, Op1, 14096 DAG.getNode(ISD::TRUNCATE, DL, 14097 MVT::i8, ShAmt0)); 14098 } 14099 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14100 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14101 if (ShAmt0C && 14102 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14103 return DAG.getNode(Opc, DL, VT, 14104 N0.getOperand(0), N1.getOperand(0), 14105 DAG.getNode(ISD::TRUNCATE, DL, 14106 MVT::i8, ShAmt0)); 14107 } 14108 14109 return SDValue(); 14110} 14111 14112// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14113static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14114 TargetLowering::DAGCombinerInfo &DCI, 14115 const X86Subtarget *Subtarget) { 14116 if (DCI.isBeforeLegalizeOps()) 14117 return SDValue(); 14118 14119 EVT VT = N->getValueType(0); 14120 14121 if (VT != MVT::i32 && VT != MVT::i64) 14122 return SDValue(); 14123 14124 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14125 14126 // Create BLSMSK instructions by finding X ^ (X-1) 14127 SDValue N0 = N->getOperand(0); 14128 SDValue N1 = N->getOperand(1); 14129 DebugLoc DL = N->getDebugLoc(); 14130 14131 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14132 isAllOnes(N0.getOperand(1))) 14133 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14134 14135 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14136 isAllOnes(N1.getOperand(1))) 14137 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14138 14139 return SDValue(); 14140} 14141 14142/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14143static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14144 const X86Subtarget *Subtarget) { 14145 LoadSDNode *Ld = cast<LoadSDNode>(N); 14146 EVT RegVT = Ld->getValueType(0); 14147 EVT MemVT = Ld->getMemoryVT(); 14148 DebugLoc dl = Ld->getDebugLoc(); 14149 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14150 14151 ISD::LoadExtType Ext = Ld->getExtensionType(); 14152 14153 // If this is a vector EXT Load then attempt to optimize it using a 14154 // shuffle. We need SSE4 for the shuffles. 14155 // TODO: It is possible to support ZExt by zeroing the undef values 14156 // during the shuffle phase or after the shuffle. 14157 if (RegVT.isVector() && RegVT.isInteger() && 14158 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14159 assert(MemVT != RegVT && "Cannot extend to the same type"); 14160 assert(MemVT.isVector() && "Must load a vector from memory"); 14161 14162 unsigned NumElems = RegVT.getVectorNumElements(); 14163 unsigned RegSz = RegVT.getSizeInBits(); 14164 unsigned MemSz = MemVT.getSizeInBits(); 14165 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14166 // All sizes must be a power of two 14167 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14168 14169 // Attempt to load the original value using a single load op. 14170 // Find a scalar type which is equal to the loaded word size. 14171 MVT SclrLoadTy = MVT::i8; 14172 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14173 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14174 MVT Tp = (MVT::SimpleValueType)tp; 14175 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14176 SclrLoadTy = Tp; 14177 break; 14178 } 14179 } 14180 14181 // Proceed if a load word is found. 14182 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14183 14184 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14185 RegSz/SclrLoadTy.getSizeInBits()); 14186 14187 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14188 RegSz/MemVT.getScalarType().getSizeInBits()); 14189 // Can't shuffle using an illegal type. 14190 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14191 14192 // Perform a single load. 14193 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14194 Ld->getBasePtr(), 14195 Ld->getPointerInfo(), Ld->isVolatile(), 14196 Ld->isNonTemporal(), Ld->isInvariant(), 14197 Ld->getAlignment()); 14198 14199 // Insert the word loaded into a vector. 14200 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14201 LoadUnitVecVT, ScalarLoad); 14202 14203 // Bitcast the loaded value to a vector of the original element type, in 14204 // the size of the target vector type. 14205 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14206 ScalarInVector); 14207 unsigned SizeRatio = RegSz/MemSz; 14208 14209 // Redistribute the loaded elements into the different locations. 14210 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14211 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14212 14213 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14214 DAG.getUNDEF(SlicedVec.getValueType()), 14215 ShuffleVec.data()); 14216 14217 // Bitcast to the requested type. 14218 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14219 // Replace the original load with the new sequence 14220 // and return the new chain. 14221 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14222 return SDValue(ScalarLoad.getNode(), 1); 14223 } 14224 14225 return SDValue(); 14226} 14227 14228/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14229static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14230 const X86Subtarget *Subtarget) { 14231 StoreSDNode *St = cast<StoreSDNode>(N); 14232 EVT VT = St->getValue().getValueType(); 14233 EVT StVT = St->getMemoryVT(); 14234 DebugLoc dl = St->getDebugLoc(); 14235 SDValue StoredVal = St->getOperand(1); 14236 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14237 14238 // If we are saving a concatenation of two XMM registers, perform two stores. 14239 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14240 // 128-bit ones. If in the future the cost becomes only one memory access the 14241 // first version would be better. 14242 if (VT.getSizeInBits() == 256 && 14243 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14244 StoredVal.getNumOperands() == 2) { 14245 14246 SDValue Value0 = StoredVal.getOperand(0); 14247 SDValue Value1 = StoredVal.getOperand(1); 14248 14249 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14250 SDValue Ptr0 = St->getBasePtr(); 14251 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14252 14253 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14254 St->getPointerInfo(), St->isVolatile(), 14255 St->isNonTemporal(), St->getAlignment()); 14256 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14257 St->getPointerInfo(), St->isVolatile(), 14258 St->isNonTemporal(), St->getAlignment()); 14259 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14260 } 14261 14262 // Optimize trunc store (of multiple scalars) to shuffle and store. 14263 // First, pack all of the elements in one place. Next, store to memory 14264 // in fewer chunks. 14265 if (St->isTruncatingStore() && VT.isVector()) { 14266 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14267 unsigned NumElems = VT.getVectorNumElements(); 14268 assert(StVT != VT && "Cannot truncate to the same type"); 14269 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14270 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14271 14272 // From, To sizes and ElemCount must be pow of two 14273 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14274 // We are going to use the original vector elt for storing. 14275 // Accumulated smaller vector elements must be a multiple of the store size. 14276 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14277 14278 unsigned SizeRatio = FromSz / ToSz; 14279 14280 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14281 14282 // Create a type on which we perform the shuffle 14283 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14284 StVT.getScalarType(), NumElems*SizeRatio); 14285 14286 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14287 14288 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14289 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14290 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14291 14292 // Can't shuffle using an illegal type 14293 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14294 14295 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14296 DAG.getUNDEF(WideVec.getValueType()), 14297 ShuffleVec.data()); 14298 // At this point all of the data is stored at the bottom of the 14299 // register. We now need to save it to mem. 14300 14301 // Find the largest store unit 14302 MVT StoreType = MVT::i8; 14303 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14304 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14305 MVT Tp = (MVT::SimpleValueType)tp; 14306 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14307 StoreType = Tp; 14308 } 14309 14310 // Bitcast the original vector into a vector of store-size units 14311 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14312 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14313 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14314 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14315 SmallVector<SDValue, 8> Chains; 14316 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14317 TLI.getPointerTy()); 14318 SDValue Ptr = St->getBasePtr(); 14319 14320 // Perform one or more big stores into memory. 14321 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14322 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14323 StoreType, ShuffWide, 14324 DAG.getIntPtrConstant(i)); 14325 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14326 St->getPointerInfo(), St->isVolatile(), 14327 St->isNonTemporal(), St->getAlignment()); 14328 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14329 Chains.push_back(Ch); 14330 } 14331 14332 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14333 Chains.size()); 14334 } 14335 14336 14337 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14338 // the FP state in cases where an emms may be missing. 14339 // A preferable solution to the general problem is to figure out the right 14340 // places to insert EMMS. This qualifies as a quick hack. 14341 14342 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14343 if (VT.getSizeInBits() != 64) 14344 return SDValue(); 14345 14346 const Function *F = DAG.getMachineFunction().getFunction(); 14347 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14348 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14349 && Subtarget->hasSSE2(); 14350 if ((VT.isVector() || 14351 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14352 isa<LoadSDNode>(St->getValue()) && 14353 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14354 St->getChain().hasOneUse() && !St->isVolatile()) { 14355 SDNode* LdVal = St->getValue().getNode(); 14356 LoadSDNode *Ld = 0; 14357 int TokenFactorIndex = -1; 14358 SmallVector<SDValue, 8> Ops; 14359 SDNode* ChainVal = St->getChain().getNode(); 14360 // Must be a store of a load. We currently handle two cases: the load 14361 // is a direct child, and it's under an intervening TokenFactor. It is 14362 // possible to dig deeper under nested TokenFactors. 14363 if (ChainVal == LdVal) 14364 Ld = cast<LoadSDNode>(St->getChain()); 14365 else if (St->getValue().hasOneUse() && 14366 ChainVal->getOpcode() == ISD::TokenFactor) { 14367 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14368 if (ChainVal->getOperand(i).getNode() == LdVal) { 14369 TokenFactorIndex = i; 14370 Ld = cast<LoadSDNode>(St->getValue()); 14371 } else 14372 Ops.push_back(ChainVal->getOperand(i)); 14373 } 14374 } 14375 14376 if (!Ld || !ISD::isNormalLoad(Ld)) 14377 return SDValue(); 14378 14379 // If this is not the MMX case, i.e. we are just turning i64 load/store 14380 // into f64 load/store, avoid the transformation if there are multiple 14381 // uses of the loaded value. 14382 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14383 return SDValue(); 14384 14385 DebugLoc LdDL = Ld->getDebugLoc(); 14386 DebugLoc StDL = N->getDebugLoc(); 14387 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14388 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14389 // pair instead. 14390 if (Subtarget->is64Bit() || F64IsLegal) { 14391 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14392 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14393 Ld->getPointerInfo(), Ld->isVolatile(), 14394 Ld->isNonTemporal(), Ld->isInvariant(), 14395 Ld->getAlignment()); 14396 SDValue NewChain = NewLd.getValue(1); 14397 if (TokenFactorIndex != -1) { 14398 Ops.push_back(NewChain); 14399 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14400 Ops.size()); 14401 } 14402 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14403 St->getPointerInfo(), 14404 St->isVolatile(), St->isNonTemporal(), 14405 St->getAlignment()); 14406 } 14407 14408 // Otherwise, lower to two pairs of 32-bit loads / stores. 14409 SDValue LoAddr = Ld->getBasePtr(); 14410 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14411 DAG.getConstant(4, MVT::i32)); 14412 14413 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14414 Ld->getPointerInfo(), 14415 Ld->isVolatile(), Ld->isNonTemporal(), 14416 Ld->isInvariant(), Ld->getAlignment()); 14417 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14418 Ld->getPointerInfo().getWithOffset(4), 14419 Ld->isVolatile(), Ld->isNonTemporal(), 14420 Ld->isInvariant(), 14421 MinAlign(Ld->getAlignment(), 4)); 14422 14423 SDValue NewChain = LoLd.getValue(1); 14424 if (TokenFactorIndex != -1) { 14425 Ops.push_back(LoLd); 14426 Ops.push_back(HiLd); 14427 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14428 Ops.size()); 14429 } 14430 14431 LoAddr = St->getBasePtr(); 14432 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14433 DAG.getConstant(4, MVT::i32)); 14434 14435 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14436 St->getPointerInfo(), 14437 St->isVolatile(), St->isNonTemporal(), 14438 St->getAlignment()); 14439 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14440 St->getPointerInfo().getWithOffset(4), 14441 St->isVolatile(), 14442 St->isNonTemporal(), 14443 MinAlign(St->getAlignment(), 4)); 14444 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14445 } 14446 return SDValue(); 14447} 14448 14449/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14450/// and return the operands for the horizontal operation in LHS and RHS. A 14451/// horizontal operation performs the binary operation on successive elements 14452/// of its first operand, then on successive elements of its second operand, 14453/// returning the resulting values in a vector. For example, if 14454/// A = < float a0, float a1, float a2, float a3 > 14455/// and 14456/// B = < float b0, float b1, float b2, float b3 > 14457/// then the result of doing a horizontal operation on A and B is 14458/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14459/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14460/// A horizontal-op B, for some already available A and B, and if so then LHS is 14461/// set to A, RHS to B, and the routine returns 'true'. 14462/// Note that the binary operation should have the property that if one of the 14463/// operands is UNDEF then the result is UNDEF. 14464static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14465 // Look for the following pattern: if 14466 // A = < float a0, float a1, float a2, float a3 > 14467 // B = < float b0, float b1, float b2, float b3 > 14468 // and 14469 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14470 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14471 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14472 // which is A horizontal-op B. 14473 14474 // At least one of the operands should be a vector shuffle. 14475 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14476 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14477 return false; 14478 14479 EVT VT = LHS.getValueType(); 14480 14481 assert((VT.is128BitVector() || VT.is256BitVector()) && 14482 "Unsupported vector type for horizontal add/sub"); 14483 14484 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14485 // operate independently on 128-bit lanes. 14486 unsigned NumElts = VT.getVectorNumElements(); 14487 unsigned NumLanes = VT.getSizeInBits()/128; 14488 unsigned NumLaneElts = NumElts / NumLanes; 14489 assert((NumLaneElts % 2 == 0) && 14490 "Vector type should have an even number of elements in each lane"); 14491 unsigned HalfLaneElts = NumLaneElts/2; 14492 14493 // View LHS in the form 14494 // LHS = VECTOR_SHUFFLE A, B, LMask 14495 // If LHS is not a shuffle then pretend it is the shuffle 14496 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14497 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14498 // type VT. 14499 SDValue A, B; 14500 SmallVector<int, 16> LMask(NumElts); 14501 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14502 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14503 A = LHS.getOperand(0); 14504 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14505 B = LHS.getOperand(1); 14506 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14507 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14508 } else { 14509 if (LHS.getOpcode() != ISD::UNDEF) 14510 A = LHS; 14511 for (unsigned i = 0; i != NumElts; ++i) 14512 LMask[i] = i; 14513 } 14514 14515 // Likewise, view RHS in the form 14516 // RHS = VECTOR_SHUFFLE C, D, RMask 14517 SDValue C, D; 14518 SmallVector<int, 16> RMask(NumElts); 14519 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14520 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14521 C = RHS.getOperand(0); 14522 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14523 D = RHS.getOperand(1); 14524 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14525 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14526 } else { 14527 if (RHS.getOpcode() != ISD::UNDEF) 14528 C = RHS; 14529 for (unsigned i = 0; i != NumElts; ++i) 14530 RMask[i] = i; 14531 } 14532 14533 // Check that the shuffles are both shuffling the same vectors. 14534 if (!(A == C && B == D) && !(A == D && B == C)) 14535 return false; 14536 14537 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14538 if (!A.getNode() && !B.getNode()) 14539 return false; 14540 14541 // If A and B occur in reverse order in RHS, then "swap" them (which means 14542 // rewriting the mask). 14543 if (A != C) 14544 CommuteVectorShuffleMask(RMask, NumElts); 14545 14546 // At this point LHS and RHS are equivalent to 14547 // LHS = VECTOR_SHUFFLE A, B, LMask 14548 // RHS = VECTOR_SHUFFLE A, B, RMask 14549 // Check that the masks correspond to performing a horizontal operation. 14550 for (unsigned i = 0; i != NumElts; ++i) { 14551 int LIdx = LMask[i], RIdx = RMask[i]; 14552 14553 // Ignore any UNDEF components. 14554 if (LIdx < 0 || RIdx < 0 || 14555 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14556 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14557 continue; 14558 14559 // Check that successive elements are being operated on. If not, this is 14560 // not a horizontal operation. 14561 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14562 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14563 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14564 if (!(LIdx == Index && RIdx == Index + 1) && 14565 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14566 return false; 14567 } 14568 14569 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14570 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14571 return true; 14572} 14573 14574/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14575static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14576 const X86Subtarget *Subtarget) { 14577 EVT VT = N->getValueType(0); 14578 SDValue LHS = N->getOperand(0); 14579 SDValue RHS = N->getOperand(1); 14580 14581 // Try to synthesize horizontal adds from adds of shuffles. 14582 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14583 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14584 isHorizontalBinOp(LHS, RHS, true)) 14585 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14586 return SDValue(); 14587} 14588 14589/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14590static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14591 const X86Subtarget *Subtarget) { 14592 EVT VT = N->getValueType(0); 14593 SDValue LHS = N->getOperand(0); 14594 SDValue RHS = N->getOperand(1); 14595 14596 // Try to synthesize horizontal subs from subs of shuffles. 14597 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14598 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14599 isHorizontalBinOp(LHS, RHS, false)) 14600 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14601 return SDValue(); 14602} 14603 14604/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14605/// X86ISD::FXOR nodes. 14606static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14607 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14608 // F[X]OR(0.0, x) -> x 14609 // F[X]OR(x, 0.0) -> x 14610 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14611 if (C->getValueAPF().isPosZero()) 14612 return N->getOperand(1); 14613 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14614 if (C->getValueAPF().isPosZero()) 14615 return N->getOperand(0); 14616 return SDValue(); 14617} 14618 14619/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14620static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14621 // FAND(0.0, x) -> 0.0 14622 // FAND(x, 0.0) -> 0.0 14623 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14624 if (C->getValueAPF().isPosZero()) 14625 return N->getOperand(0); 14626 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14627 if (C->getValueAPF().isPosZero()) 14628 return N->getOperand(1); 14629 return SDValue(); 14630} 14631 14632static SDValue PerformBTCombine(SDNode *N, 14633 SelectionDAG &DAG, 14634 TargetLowering::DAGCombinerInfo &DCI) { 14635 // BT ignores high bits in the bit index operand. 14636 SDValue Op1 = N->getOperand(1); 14637 if (Op1.hasOneUse()) { 14638 unsigned BitWidth = Op1.getValueSizeInBits(); 14639 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14640 APInt KnownZero, KnownOne; 14641 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14642 !DCI.isBeforeLegalizeOps()); 14643 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14644 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14645 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14646 DCI.CommitTargetLoweringOpt(TLO); 14647 } 14648 return SDValue(); 14649} 14650 14651static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14652 SDValue Op = N->getOperand(0); 14653 if (Op.getOpcode() == ISD::BITCAST) 14654 Op = Op.getOperand(0); 14655 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14656 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14657 VT.getVectorElementType().getSizeInBits() == 14658 OpVT.getVectorElementType().getSizeInBits()) { 14659 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14660 } 14661 return SDValue(); 14662} 14663 14664static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14665 TargetLowering::DAGCombinerInfo &DCI, 14666 const X86Subtarget *Subtarget) { 14667 if (!DCI.isBeforeLegalizeOps()) 14668 return SDValue(); 14669 14670 if (!Subtarget->hasAVX()) 14671 return SDValue(); 14672 14673 // Optimize vectors in AVX mode 14674 // Sign extend v8i16 to v8i32 and 14675 // v4i32 to v4i64 14676 // 14677 // Divide input vector into two parts 14678 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14679 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14680 // concat the vectors to original VT 14681 14682 EVT VT = N->getValueType(0); 14683 SDValue Op = N->getOperand(0); 14684 EVT OpVT = Op.getValueType(); 14685 DebugLoc dl = N->getDebugLoc(); 14686 14687 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14688 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14689 14690 unsigned NumElems = OpVT.getVectorNumElements(); 14691 SmallVector<int,8> ShufMask1(NumElems, -1); 14692 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i; 14693 14694 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14695 ShufMask1.data()); 14696 14697 SmallVector<int,8> ShufMask2(NumElems, -1); 14698 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2; 14699 14700 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14701 ShufMask2.data()); 14702 14703 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14704 VT.getVectorNumElements()/2); 14705 14706 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14707 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14708 14709 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14710 } 14711 return SDValue(); 14712} 14713 14714static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14715 const X86Subtarget *Subtarget) { 14716 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14717 // (and (i32 x86isd::setcc_carry), 1) 14718 // This eliminates the zext. This transformation is necessary because 14719 // ISD::SETCC is always legalized to i8. 14720 DebugLoc dl = N->getDebugLoc(); 14721 SDValue N0 = N->getOperand(0); 14722 EVT VT = N->getValueType(0); 14723 EVT OpVT = N0.getValueType(); 14724 14725 if (N0.getOpcode() == ISD::AND && 14726 N0.hasOneUse() && 14727 N0.getOperand(0).hasOneUse()) { 14728 SDValue N00 = N0.getOperand(0); 14729 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14730 return SDValue(); 14731 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14732 if (!C || C->getZExtValue() != 1) 14733 return SDValue(); 14734 return DAG.getNode(ISD::AND, dl, VT, 14735 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14736 N00.getOperand(0), N00.getOperand(1)), 14737 DAG.getConstant(1, VT)); 14738 } 14739 // Optimize vectors in AVX mode: 14740 // 14741 // v8i16 -> v8i32 14742 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14743 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14744 // Concat upper and lower parts. 14745 // 14746 // v4i32 -> v4i64 14747 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14748 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14749 // Concat upper and lower parts. 14750 // 14751 if (Subtarget->hasAVX()) { 14752 14753 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14754 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14755 14756 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14757 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG); 14758 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG); 14759 14760 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14761 VT.getVectorNumElements()/2); 14762 14763 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14764 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14765 14766 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14767 } 14768 } 14769 14770 14771 return SDValue(); 14772} 14773 14774// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14775static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14776 unsigned X86CC = N->getConstantOperandVal(0); 14777 SDValue EFLAG = N->getOperand(1); 14778 DebugLoc DL = N->getDebugLoc(); 14779 14780 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14781 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14782 // cases. 14783 if (X86CC == X86::COND_B) 14784 return DAG.getNode(ISD::AND, DL, MVT::i8, 14785 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14786 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14787 DAG.getConstant(1, MVT::i8)); 14788 14789 return SDValue(); 14790} 14791 14792static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14793 const X86TargetLowering *XTLI) { 14794 SDValue Op0 = N->getOperand(0); 14795 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14796 // a 32-bit target where SSE doesn't support i64->FP operations. 14797 if (Op0.getOpcode() == ISD::LOAD) { 14798 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14799 EVT VT = Ld->getValueType(0); 14800 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14801 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14802 !XTLI->getSubtarget()->is64Bit() && 14803 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14804 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14805 Ld->getChain(), Op0, DAG); 14806 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14807 return FILDChain; 14808 } 14809 } 14810 return SDValue(); 14811} 14812 14813// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14814static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14815 X86TargetLowering::DAGCombinerInfo &DCI) { 14816 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14817 // the result is either zero or one (depending on the input carry bit). 14818 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14819 if (X86::isZeroNode(N->getOperand(0)) && 14820 X86::isZeroNode(N->getOperand(1)) && 14821 // We don't have a good way to replace an EFLAGS use, so only do this when 14822 // dead right now. 14823 SDValue(N, 1).use_empty()) { 14824 DebugLoc DL = N->getDebugLoc(); 14825 EVT VT = N->getValueType(0); 14826 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14827 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14828 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14829 DAG.getConstant(X86::COND_B,MVT::i8), 14830 N->getOperand(2)), 14831 DAG.getConstant(1, VT)); 14832 return DCI.CombineTo(N, Res1, CarryOut); 14833 } 14834 14835 return SDValue(); 14836} 14837 14838// fold (add Y, (sete X, 0)) -> adc 0, Y 14839// (add Y, (setne X, 0)) -> sbb -1, Y 14840// (sub (sete X, 0), Y) -> sbb 0, Y 14841// (sub (setne X, 0), Y) -> adc -1, Y 14842static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14843 DebugLoc DL = N->getDebugLoc(); 14844 14845 // Look through ZExts. 14846 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14847 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14848 return SDValue(); 14849 14850 SDValue SetCC = Ext.getOperand(0); 14851 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14852 return SDValue(); 14853 14854 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14855 if (CC != X86::COND_E && CC != X86::COND_NE) 14856 return SDValue(); 14857 14858 SDValue Cmp = SetCC.getOperand(1); 14859 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14860 !X86::isZeroNode(Cmp.getOperand(1)) || 14861 !Cmp.getOperand(0).getValueType().isInteger()) 14862 return SDValue(); 14863 14864 SDValue CmpOp0 = Cmp.getOperand(0); 14865 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14866 DAG.getConstant(1, CmpOp0.getValueType())); 14867 14868 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14869 if (CC == X86::COND_NE) 14870 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14871 DL, OtherVal.getValueType(), OtherVal, 14872 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14873 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14874 DL, OtherVal.getValueType(), OtherVal, 14875 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14876} 14877 14878/// PerformADDCombine - Do target-specific dag combines on integer adds. 14879static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14880 const X86Subtarget *Subtarget) { 14881 EVT VT = N->getValueType(0); 14882 SDValue Op0 = N->getOperand(0); 14883 SDValue Op1 = N->getOperand(1); 14884 14885 // Try to synthesize horizontal adds from adds of shuffles. 14886 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14887 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14888 isHorizontalBinOp(Op0, Op1, true)) 14889 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14890 14891 return OptimizeConditionalInDecrement(N, DAG); 14892} 14893 14894static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14895 const X86Subtarget *Subtarget) { 14896 SDValue Op0 = N->getOperand(0); 14897 SDValue Op1 = N->getOperand(1); 14898 14899 // X86 can't encode an immediate LHS of a sub. See if we can push the 14900 // negation into a preceding instruction. 14901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14902 // If the RHS of the sub is a XOR with one use and a constant, invert the 14903 // immediate. Then add one to the LHS of the sub so we can turn 14904 // X-Y -> X+~Y+1, saving one register. 14905 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14906 isa<ConstantSDNode>(Op1.getOperand(1))) { 14907 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14908 EVT VT = Op0.getValueType(); 14909 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14910 Op1.getOperand(0), 14911 DAG.getConstant(~XorC, VT)); 14912 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14913 DAG.getConstant(C->getAPIntValue()+1, VT)); 14914 } 14915 } 14916 14917 // Try to synthesize horizontal adds from adds of shuffles. 14918 EVT VT = N->getValueType(0); 14919 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14920 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14921 isHorizontalBinOp(Op0, Op1, true)) 14922 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14923 14924 return OptimizeConditionalInDecrement(N, DAG); 14925} 14926 14927SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14928 DAGCombinerInfo &DCI) const { 14929 SelectionDAG &DAG = DCI.DAG; 14930 switch (N->getOpcode()) { 14931 default: break; 14932 case ISD::EXTRACT_VECTOR_ELT: 14933 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 14934 case ISD::VSELECT: 14935 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 14936 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14937 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14938 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14939 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14940 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14941 case ISD::SHL: 14942 case ISD::SRA: 14943 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 14944 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14945 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14946 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14947 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14948 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14949 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14950 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14951 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14952 case X86ISD::FXOR: 14953 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14954 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14955 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14956 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14957 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); 14958 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 14959 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 14960 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14961 case X86ISD::SHUFP: // Handle all target specific shuffles 14962 case X86ISD::PALIGN: 14963 case X86ISD::UNPCKH: 14964 case X86ISD::UNPCKL: 14965 case X86ISD::MOVHLPS: 14966 case X86ISD::MOVLHPS: 14967 case X86ISD::PSHUFD: 14968 case X86ISD::PSHUFHW: 14969 case X86ISD::PSHUFLW: 14970 case X86ISD::MOVSS: 14971 case X86ISD::MOVSD: 14972 case X86ISD::VPERMILP: 14973 case X86ISD::VPERM2X128: 14974 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14975 } 14976 14977 return SDValue(); 14978} 14979 14980/// isTypeDesirableForOp - Return true if the target has native support for 14981/// the specified value type and it is 'desirable' to use the type for the 14982/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14983/// instruction encodings are longer and some i16 instructions are slow. 14984bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14985 if (!isTypeLegal(VT)) 14986 return false; 14987 if (VT != MVT::i16) 14988 return true; 14989 14990 switch (Opc) { 14991 default: 14992 return true; 14993 case ISD::LOAD: 14994 case ISD::SIGN_EXTEND: 14995 case ISD::ZERO_EXTEND: 14996 case ISD::ANY_EXTEND: 14997 case ISD::SHL: 14998 case ISD::SRL: 14999 case ISD::SUB: 15000 case ISD::ADD: 15001 case ISD::MUL: 15002 case ISD::AND: 15003 case ISD::OR: 15004 case ISD::XOR: 15005 return false; 15006 } 15007} 15008 15009/// IsDesirableToPromoteOp - This method query the target whether it is 15010/// beneficial for dag combiner to promote the specified node. If true, it 15011/// should return the desired promotion type by reference. 15012bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15013 EVT VT = Op.getValueType(); 15014 if (VT != MVT::i16) 15015 return false; 15016 15017 bool Promote = false; 15018 bool Commute = false; 15019 switch (Op.getOpcode()) { 15020 default: break; 15021 case ISD::LOAD: { 15022 LoadSDNode *LD = cast<LoadSDNode>(Op); 15023 // If the non-extending load has a single use and it's not live out, then it 15024 // might be folded. 15025 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15026 Op.hasOneUse()*/) { 15027 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15028 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15029 // The only case where we'd want to promote LOAD (rather then it being 15030 // promoted as an operand is when it's only use is liveout. 15031 if (UI->getOpcode() != ISD::CopyToReg) 15032 return false; 15033 } 15034 } 15035 Promote = true; 15036 break; 15037 } 15038 case ISD::SIGN_EXTEND: 15039 case ISD::ZERO_EXTEND: 15040 case ISD::ANY_EXTEND: 15041 Promote = true; 15042 break; 15043 case ISD::SHL: 15044 case ISD::SRL: { 15045 SDValue N0 = Op.getOperand(0); 15046 // Look out for (store (shl (load), x)). 15047 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15048 return false; 15049 Promote = true; 15050 break; 15051 } 15052 case ISD::ADD: 15053 case ISD::MUL: 15054 case ISD::AND: 15055 case ISD::OR: 15056 case ISD::XOR: 15057 Commute = true; 15058 // fallthrough 15059 case ISD::SUB: { 15060 SDValue N0 = Op.getOperand(0); 15061 SDValue N1 = Op.getOperand(1); 15062 if (!Commute && MayFoldLoad(N1)) 15063 return false; 15064 // Avoid disabling potential load folding opportunities. 15065 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15066 return false; 15067 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15068 return false; 15069 Promote = true; 15070 } 15071 } 15072 15073 PVT = MVT::i32; 15074 return Promote; 15075} 15076 15077//===----------------------------------------------------------------------===// 15078// X86 Inline Assembly Support 15079//===----------------------------------------------------------------------===// 15080 15081namespace { 15082 // Helper to match a string separated by whitespace. 15083 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15084 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15085 15086 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15087 StringRef piece(*args[i]); 15088 if (!s.startswith(piece)) // Check if the piece matches. 15089 return false; 15090 15091 s = s.substr(piece.size()); 15092 StringRef::size_type pos = s.find_first_not_of(" \t"); 15093 if (pos == 0) // We matched a prefix. 15094 return false; 15095 15096 s = s.substr(pos); 15097 } 15098 15099 return s.empty(); 15100 } 15101 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15102} 15103 15104bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15105 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15106 15107 std::string AsmStr = IA->getAsmString(); 15108 15109 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15110 if (!Ty || Ty->getBitWidth() % 16 != 0) 15111 return false; 15112 15113 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15114 SmallVector<StringRef, 4> AsmPieces; 15115 SplitString(AsmStr, AsmPieces, ";\n"); 15116 15117 switch (AsmPieces.size()) { 15118 default: return false; 15119 case 1: 15120 // FIXME: this should verify that we are targeting a 486 or better. If not, 15121 // we will turn this bswap into something that will be lowered to logical 15122 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15123 // lower so don't worry about this. 15124 // bswap $0 15125 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15126 matchAsm(AsmPieces[0], "bswapl", "$0") || 15127 matchAsm(AsmPieces[0], "bswapq", "$0") || 15128 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15129 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15130 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15131 // No need to check constraints, nothing other than the equivalent of 15132 // "=r,0" would be valid here. 15133 return IntrinsicLowering::LowerToByteSwap(CI); 15134 } 15135 15136 // rorw $$8, ${0:w} --> llvm.bswap.i16 15137 if (CI->getType()->isIntegerTy(16) && 15138 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15139 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15140 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15141 AsmPieces.clear(); 15142 const std::string &ConstraintsStr = IA->getConstraintString(); 15143 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15144 std::sort(AsmPieces.begin(), AsmPieces.end()); 15145 if (AsmPieces.size() == 4 && 15146 AsmPieces[0] == "~{cc}" && 15147 AsmPieces[1] == "~{dirflag}" && 15148 AsmPieces[2] == "~{flags}" && 15149 AsmPieces[3] == "~{fpsr}") 15150 return IntrinsicLowering::LowerToByteSwap(CI); 15151 } 15152 break; 15153 case 3: 15154 if (CI->getType()->isIntegerTy(32) && 15155 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15156 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15157 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15158 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15159 AsmPieces.clear(); 15160 const std::string &ConstraintsStr = IA->getConstraintString(); 15161 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15162 std::sort(AsmPieces.begin(), AsmPieces.end()); 15163 if (AsmPieces.size() == 4 && 15164 AsmPieces[0] == "~{cc}" && 15165 AsmPieces[1] == "~{dirflag}" && 15166 AsmPieces[2] == "~{flags}" && 15167 AsmPieces[3] == "~{fpsr}") 15168 return IntrinsicLowering::LowerToByteSwap(CI); 15169 } 15170 15171 if (CI->getType()->isIntegerTy(64)) { 15172 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15173 if (Constraints.size() >= 2 && 15174 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15175 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15176 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15177 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15178 matchAsm(AsmPieces[1], "bswap", "%edx") && 15179 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15180 return IntrinsicLowering::LowerToByteSwap(CI); 15181 } 15182 } 15183 break; 15184 } 15185 return false; 15186} 15187 15188 15189 15190/// getConstraintType - Given a constraint letter, return the type of 15191/// constraint it is for this target. 15192X86TargetLowering::ConstraintType 15193X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15194 if (Constraint.size() == 1) { 15195 switch (Constraint[0]) { 15196 case 'R': 15197 case 'q': 15198 case 'Q': 15199 case 'f': 15200 case 't': 15201 case 'u': 15202 case 'y': 15203 case 'x': 15204 case 'Y': 15205 case 'l': 15206 return C_RegisterClass; 15207 case 'a': 15208 case 'b': 15209 case 'c': 15210 case 'd': 15211 case 'S': 15212 case 'D': 15213 case 'A': 15214 return C_Register; 15215 case 'I': 15216 case 'J': 15217 case 'K': 15218 case 'L': 15219 case 'M': 15220 case 'N': 15221 case 'G': 15222 case 'C': 15223 case 'e': 15224 case 'Z': 15225 return C_Other; 15226 default: 15227 break; 15228 } 15229 } 15230 return TargetLowering::getConstraintType(Constraint); 15231} 15232 15233/// Examine constraint type and operand type and determine a weight value. 15234/// This object must already have been set up with the operand type 15235/// and the current alternative constraint selected. 15236TargetLowering::ConstraintWeight 15237 X86TargetLowering::getSingleConstraintMatchWeight( 15238 AsmOperandInfo &info, const char *constraint) const { 15239 ConstraintWeight weight = CW_Invalid; 15240 Value *CallOperandVal = info.CallOperandVal; 15241 // If we don't have a value, we can't do a match, 15242 // but allow it at the lowest weight. 15243 if (CallOperandVal == NULL) 15244 return CW_Default; 15245 Type *type = CallOperandVal->getType(); 15246 // Look at the constraint type. 15247 switch (*constraint) { 15248 default: 15249 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15250 case 'R': 15251 case 'q': 15252 case 'Q': 15253 case 'a': 15254 case 'b': 15255 case 'c': 15256 case 'd': 15257 case 'S': 15258 case 'D': 15259 case 'A': 15260 if (CallOperandVal->getType()->isIntegerTy()) 15261 weight = CW_SpecificReg; 15262 break; 15263 case 'f': 15264 case 't': 15265 case 'u': 15266 if (type->isFloatingPointTy()) 15267 weight = CW_SpecificReg; 15268 break; 15269 case 'y': 15270 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15271 weight = CW_SpecificReg; 15272 break; 15273 case 'x': 15274 case 'Y': 15275 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15276 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15277 weight = CW_Register; 15278 break; 15279 case 'I': 15280 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15281 if (C->getZExtValue() <= 31) 15282 weight = CW_Constant; 15283 } 15284 break; 15285 case 'J': 15286 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15287 if (C->getZExtValue() <= 63) 15288 weight = CW_Constant; 15289 } 15290 break; 15291 case 'K': 15292 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15293 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15294 weight = CW_Constant; 15295 } 15296 break; 15297 case 'L': 15298 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15299 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15300 weight = CW_Constant; 15301 } 15302 break; 15303 case 'M': 15304 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15305 if (C->getZExtValue() <= 3) 15306 weight = CW_Constant; 15307 } 15308 break; 15309 case 'N': 15310 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15311 if (C->getZExtValue() <= 0xff) 15312 weight = CW_Constant; 15313 } 15314 break; 15315 case 'G': 15316 case 'C': 15317 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15318 weight = CW_Constant; 15319 } 15320 break; 15321 case 'e': 15322 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15323 if ((C->getSExtValue() >= -0x80000000LL) && 15324 (C->getSExtValue() <= 0x7fffffffLL)) 15325 weight = CW_Constant; 15326 } 15327 break; 15328 case 'Z': 15329 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15330 if (C->getZExtValue() <= 0xffffffff) 15331 weight = CW_Constant; 15332 } 15333 break; 15334 } 15335 return weight; 15336} 15337 15338/// LowerXConstraint - try to replace an X constraint, which matches anything, 15339/// with another that has more specific requirements based on the type of the 15340/// corresponding operand. 15341const char *X86TargetLowering:: 15342LowerXConstraint(EVT ConstraintVT) const { 15343 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15344 // 'f' like normal targets. 15345 if (ConstraintVT.isFloatingPoint()) { 15346 if (Subtarget->hasSSE2()) 15347 return "Y"; 15348 if (Subtarget->hasSSE1()) 15349 return "x"; 15350 } 15351 15352 return TargetLowering::LowerXConstraint(ConstraintVT); 15353} 15354 15355/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15356/// vector. If it is invalid, don't add anything to Ops. 15357void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15358 std::string &Constraint, 15359 std::vector<SDValue>&Ops, 15360 SelectionDAG &DAG) const { 15361 SDValue Result(0, 0); 15362 15363 // Only support length 1 constraints for now. 15364 if (Constraint.length() > 1) return; 15365 15366 char ConstraintLetter = Constraint[0]; 15367 switch (ConstraintLetter) { 15368 default: break; 15369 case 'I': 15370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15371 if (C->getZExtValue() <= 31) { 15372 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15373 break; 15374 } 15375 } 15376 return; 15377 case 'J': 15378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15379 if (C->getZExtValue() <= 63) { 15380 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15381 break; 15382 } 15383 } 15384 return; 15385 case 'K': 15386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15387 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15388 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15389 break; 15390 } 15391 } 15392 return; 15393 case 'N': 15394 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15395 if (C->getZExtValue() <= 255) { 15396 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15397 break; 15398 } 15399 } 15400 return; 15401 case 'e': { 15402 // 32-bit signed value 15403 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15404 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15405 C->getSExtValue())) { 15406 // Widen to 64 bits here to get it sign extended. 15407 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15408 break; 15409 } 15410 // FIXME gcc accepts some relocatable values here too, but only in certain 15411 // memory models; it's complicated. 15412 } 15413 return; 15414 } 15415 case 'Z': { 15416 // 32-bit unsigned value 15417 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15418 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15419 C->getZExtValue())) { 15420 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15421 break; 15422 } 15423 } 15424 // FIXME gcc accepts some relocatable values here too, but only in certain 15425 // memory models; it's complicated. 15426 return; 15427 } 15428 case 'i': { 15429 // Literal immediates are always ok. 15430 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15431 // Widen to 64 bits here to get it sign extended. 15432 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15433 break; 15434 } 15435 15436 // In any sort of PIC mode addresses need to be computed at runtime by 15437 // adding in a register or some sort of table lookup. These can't 15438 // be used as immediates. 15439 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15440 return; 15441 15442 // If we are in non-pic codegen mode, we allow the address of a global (with 15443 // an optional displacement) to be used with 'i'. 15444 GlobalAddressSDNode *GA = 0; 15445 int64_t Offset = 0; 15446 15447 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15448 while (1) { 15449 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15450 Offset += GA->getOffset(); 15451 break; 15452 } else if (Op.getOpcode() == ISD::ADD) { 15453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15454 Offset += C->getZExtValue(); 15455 Op = Op.getOperand(0); 15456 continue; 15457 } 15458 } else if (Op.getOpcode() == ISD::SUB) { 15459 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15460 Offset += -C->getZExtValue(); 15461 Op = Op.getOperand(0); 15462 continue; 15463 } 15464 } 15465 15466 // Otherwise, this isn't something we can handle, reject it. 15467 return; 15468 } 15469 15470 const GlobalValue *GV = GA->getGlobal(); 15471 // If we require an extra load to get this address, as in PIC mode, we 15472 // can't accept it. 15473 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15474 getTargetMachine()))) 15475 return; 15476 15477 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15478 GA->getValueType(0), Offset); 15479 break; 15480 } 15481 } 15482 15483 if (Result.getNode()) { 15484 Ops.push_back(Result); 15485 return; 15486 } 15487 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15488} 15489 15490std::pair<unsigned, const TargetRegisterClass*> 15491X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15492 EVT VT) const { 15493 // First, see if this is a constraint that directly corresponds to an LLVM 15494 // register class. 15495 if (Constraint.size() == 1) { 15496 // GCC Constraint Letters 15497 switch (Constraint[0]) { 15498 default: break; 15499 // TODO: Slight differences here in allocation order and leaving 15500 // RIP in the class. Do they matter any more here than they do 15501 // in the normal allocation? 15502 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15503 if (Subtarget->is64Bit()) { 15504 if (VT == MVT::i32 || VT == MVT::f32) 15505 return std::make_pair(0U, X86::GR32RegisterClass); 15506 else if (VT == MVT::i16) 15507 return std::make_pair(0U, X86::GR16RegisterClass); 15508 else if (VT == MVT::i8 || VT == MVT::i1) 15509 return std::make_pair(0U, X86::GR8RegisterClass); 15510 else if (VT == MVT::i64 || VT == MVT::f64) 15511 return std::make_pair(0U, X86::GR64RegisterClass); 15512 break; 15513 } 15514 // 32-bit fallthrough 15515 case 'Q': // Q_REGS 15516 if (VT == MVT::i32 || VT == MVT::f32) 15517 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15518 else if (VT == MVT::i16) 15519 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15520 else if (VT == MVT::i8 || VT == MVT::i1) 15521 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15522 else if (VT == MVT::i64) 15523 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15524 break; 15525 case 'r': // GENERAL_REGS 15526 case 'l': // INDEX_REGS 15527 if (VT == MVT::i8 || VT == MVT::i1) 15528 return std::make_pair(0U, X86::GR8RegisterClass); 15529 if (VT == MVT::i16) 15530 return std::make_pair(0U, X86::GR16RegisterClass); 15531 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15532 return std::make_pair(0U, X86::GR32RegisterClass); 15533 return std::make_pair(0U, X86::GR64RegisterClass); 15534 case 'R': // LEGACY_REGS 15535 if (VT == MVT::i8 || VT == MVT::i1) 15536 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15537 if (VT == MVT::i16) 15538 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15539 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15540 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15541 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15542 case 'f': // FP Stack registers. 15543 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15544 // value to the correct fpstack register class. 15545 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15546 return std::make_pair(0U, X86::RFP32RegisterClass); 15547 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15548 return std::make_pair(0U, X86::RFP64RegisterClass); 15549 return std::make_pair(0U, X86::RFP80RegisterClass); 15550 case 'y': // MMX_REGS if MMX allowed. 15551 if (!Subtarget->hasMMX()) break; 15552 return std::make_pair(0U, X86::VR64RegisterClass); 15553 case 'Y': // SSE_REGS if SSE2 allowed 15554 if (!Subtarget->hasSSE2()) break; 15555 // FALL THROUGH. 15556 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15557 if (!Subtarget->hasSSE1()) break; 15558 15559 switch (VT.getSimpleVT().SimpleTy) { 15560 default: break; 15561 // Scalar SSE types. 15562 case MVT::f32: 15563 case MVT::i32: 15564 return std::make_pair(0U, X86::FR32RegisterClass); 15565 case MVT::f64: 15566 case MVT::i64: 15567 return std::make_pair(0U, X86::FR64RegisterClass); 15568 // Vector types. 15569 case MVT::v16i8: 15570 case MVT::v8i16: 15571 case MVT::v4i32: 15572 case MVT::v2i64: 15573 case MVT::v4f32: 15574 case MVT::v2f64: 15575 return std::make_pair(0U, X86::VR128RegisterClass); 15576 // AVX types. 15577 case MVT::v32i8: 15578 case MVT::v16i16: 15579 case MVT::v8i32: 15580 case MVT::v4i64: 15581 case MVT::v8f32: 15582 case MVT::v4f64: 15583 return std::make_pair(0U, X86::VR256RegisterClass); 15584 15585 } 15586 break; 15587 } 15588 } 15589 15590 // Use the default implementation in TargetLowering to convert the register 15591 // constraint into a member of a register class. 15592 std::pair<unsigned, const TargetRegisterClass*> Res; 15593 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15594 15595 // Not found as a standard register? 15596 if (Res.second == 0) { 15597 // Map st(0) -> st(7) -> ST0 15598 if (Constraint.size() == 7 && Constraint[0] == '{' && 15599 tolower(Constraint[1]) == 's' && 15600 tolower(Constraint[2]) == 't' && 15601 Constraint[3] == '(' && 15602 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15603 Constraint[5] == ')' && 15604 Constraint[6] == '}') { 15605 15606 Res.first = X86::ST0+Constraint[4]-'0'; 15607 Res.second = X86::RFP80RegisterClass; 15608 return Res; 15609 } 15610 15611 // GCC allows "st(0)" to be called just plain "st". 15612 if (StringRef("{st}").equals_lower(Constraint)) { 15613 Res.first = X86::ST0; 15614 Res.second = X86::RFP80RegisterClass; 15615 return Res; 15616 } 15617 15618 // flags -> EFLAGS 15619 if (StringRef("{flags}").equals_lower(Constraint)) { 15620 Res.first = X86::EFLAGS; 15621 Res.second = X86::CCRRegisterClass; 15622 return Res; 15623 } 15624 15625 // 'A' means EAX + EDX. 15626 if (Constraint == "A") { 15627 Res.first = X86::EAX; 15628 Res.second = X86::GR32_ADRegisterClass; 15629 return Res; 15630 } 15631 return Res; 15632 } 15633 15634 // Otherwise, check to see if this is a register class of the wrong value 15635 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15636 // turn into {ax},{dx}. 15637 if (Res.second->hasType(VT)) 15638 return Res; // Correct type already, nothing to do. 15639 15640 // All of the single-register GCC register classes map their values onto 15641 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15642 // really want an 8-bit or 32-bit register, map to the appropriate register 15643 // class and return the appropriate register. 15644 if (Res.second == X86::GR16RegisterClass) { 15645 if (VT == MVT::i8) { 15646 unsigned DestReg = 0; 15647 switch (Res.first) { 15648 default: break; 15649 case X86::AX: DestReg = X86::AL; break; 15650 case X86::DX: DestReg = X86::DL; break; 15651 case X86::CX: DestReg = X86::CL; break; 15652 case X86::BX: DestReg = X86::BL; break; 15653 } 15654 if (DestReg) { 15655 Res.first = DestReg; 15656 Res.second = X86::GR8RegisterClass; 15657 } 15658 } else if (VT == MVT::i32) { 15659 unsigned DestReg = 0; 15660 switch (Res.first) { 15661 default: break; 15662 case X86::AX: DestReg = X86::EAX; break; 15663 case X86::DX: DestReg = X86::EDX; break; 15664 case X86::CX: DestReg = X86::ECX; break; 15665 case X86::BX: DestReg = X86::EBX; break; 15666 case X86::SI: DestReg = X86::ESI; break; 15667 case X86::DI: DestReg = X86::EDI; break; 15668 case X86::BP: DestReg = X86::EBP; break; 15669 case X86::SP: DestReg = X86::ESP; break; 15670 } 15671 if (DestReg) { 15672 Res.first = DestReg; 15673 Res.second = X86::GR32RegisterClass; 15674 } 15675 } else if (VT == MVT::i64) { 15676 unsigned DestReg = 0; 15677 switch (Res.first) { 15678 default: break; 15679 case X86::AX: DestReg = X86::RAX; break; 15680 case X86::DX: DestReg = X86::RDX; break; 15681 case X86::CX: DestReg = X86::RCX; break; 15682 case X86::BX: DestReg = X86::RBX; break; 15683 case X86::SI: DestReg = X86::RSI; break; 15684 case X86::DI: DestReg = X86::RDI; break; 15685 case X86::BP: DestReg = X86::RBP; break; 15686 case X86::SP: DestReg = X86::RSP; break; 15687 } 15688 if (DestReg) { 15689 Res.first = DestReg; 15690 Res.second = X86::GR64RegisterClass; 15691 } 15692 } 15693 } else if (Res.second == X86::FR32RegisterClass || 15694 Res.second == X86::FR64RegisterClass || 15695 Res.second == X86::VR128RegisterClass) { 15696 // Handle references to XMM physical registers that got mapped into the 15697 // wrong class. This can happen with constraints like {xmm0} where the 15698 // target independent register mapper will just pick the first match it can 15699 // find, ignoring the required type. 15700 if (VT == MVT::f32) 15701 Res.second = X86::FR32RegisterClass; 15702 else if (VT == MVT::f64) 15703 Res.second = X86::FR64RegisterClass; 15704 else if (X86::VR128RegisterClass->hasType(VT)) 15705 Res.second = X86::VR128RegisterClass; 15706 } 15707 15708 return Res; 15709} 15710