X86ISelLowering.cpp revision 3ea97550e361bc6ae23e9415abc7b0a34c540f53
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalAlias.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/Function.h" 27#include "llvm/Instructions.h" 28#include "llvm/Intrinsics.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/MC/MCAsmInfo.h" 38#include "llvm/MC/MCContext.h" 39#include "llvm/MC/MCExpr.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52using namespace llvm; 53using namespace dwarf; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56 57static cl::opt<bool> 58DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 59 60// Disable16Bit - 16-bit operations typically have a larger encoding than 61// corresponding 32-bit instructions, and 16-bit code is slow on some 62// processors. This is an experimental flag to disable 16-bit operations 63// (which forces them to be Legalized to 32-bit operations). 64static cl::opt<bool> 65Disable16Bit("disable-16bit", cl::Hidden, 66 cl::desc("Disable use of 16-bit instructions")); 67 68// Forward declarations. 69static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 70 SDValue V2); 71 72static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 73 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 74 default: llvm_unreachable("unknown subtarget type"); 75 case X86Subtarget::isDarwin: 76 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 77 return new X8664_MachoTargetObjectFile(); 78 return new TargetLoweringObjectFileMachO(); 79 case X86Subtarget::isELF: 80 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 81 return new X8664_ELFTargetObjectFile(TM); 82 return new X8632_ELFTargetObjectFile(TM); 83 case X86Subtarget::isMingw: 84 case X86Subtarget::isCygwin: 85 case X86Subtarget::isWindows: 86 return new TargetLoweringObjectFileCOFF(); 87 } 88} 89 90X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 91 : TargetLowering(TM, createTLOF(TM)) { 92 Subtarget = &TM.getSubtarget<X86Subtarget>(); 93 X86ScalarSSEf64 = Subtarget->hasSSE2(); 94 X86ScalarSSEf32 = Subtarget->hasSSE1(); 95 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 96 97 RegInfo = TM.getRegisterInfo(); 98 TD = getTargetData(); 99 100 // Set up the TargetLowering object. 101 102 // X86 is weird, it always uses i8 for shift amounts and setcc results. 103 setShiftAmountType(MVT::i8); 104 setBooleanContents(ZeroOrOneBooleanContent); 105 setSchedulingPreference(SchedulingForRegPressure); 106 setStackPointerRegisterToSaveRestore(X86StackPtr); 107 108 if (Subtarget->isTargetDarwin()) { 109 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 110 setUseUnderscoreSetJmp(false); 111 setUseUnderscoreLongJmp(false); 112 } else if (Subtarget->isTargetMingw()) { 113 // MS runtime is weird: it exports _setjmp, but longjmp! 114 setUseUnderscoreSetJmp(true); 115 setUseUnderscoreLongJmp(false); 116 } else { 117 setUseUnderscoreSetJmp(true); 118 setUseUnderscoreLongJmp(true); 119 } 120 121 // Set up the register classes. 122 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 123 if (!Disable16Bit) 124 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 125 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 126 if (Subtarget->is64Bit()) 127 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 128 129 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 130 131 // We don't accept any truncstore of integer registers. 132 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 133 if (!Disable16Bit) 134 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 135 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 136 if (!Disable16Bit) 137 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 139 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 140 141 // SETOEQ and SETUNE require checking two conditions. 142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 148 149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 150 // operation. 151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 154 155 if (Subtarget->is64Bit()) { 156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 158 } else if (!UseSoftFloat) { 159 if (X86ScalarSSEf64) { 160 // We have an impenetrably clever algorithm for ui64->double only. 161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 162 } 163 // We have an algorithm for SSE2, and we turn this into a 64-bit 164 // FILD for other targets. 165 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 166 } 167 168 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 169 // this operation. 170 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 171 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 172 173 if (!UseSoftFloat) { 174 // SSE has no i16 to fp conversion, only i32 175 if (X86ScalarSSEf32) { 176 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 177 // f32 and f64 cases are Legal, f80 case is not 178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 179 } else { 180 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 181 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 182 } 183 } else { 184 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 185 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 186 } 187 188 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 189 // are Legal, f80 is custom lowered. 190 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 191 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 192 193 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 194 // this operation. 195 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 196 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 197 198 if (X86ScalarSSEf32) { 199 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 200 // f32 and f64 cases are Legal, f80 case is not 201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 202 } else { 203 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 204 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 205 } 206 207 // Handle FP_TO_UINT by promoting the destination to a larger signed 208 // conversion. 209 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 210 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 211 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 212 213 if (Subtarget->is64Bit()) { 214 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 215 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 216 } else if (!UseSoftFloat) { 217 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 218 // Expand FP_TO_UINT into a select. 219 // FIXME: We would like to use a Custom expander here eventually to do 220 // the optimal thing for SSE vs. the default expansion in the legalizer. 221 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 222 else 223 // With SSE3 we can use fisttpll to convert to a signed i64; without 224 // SSE, we're stuck with a fistpll. 225 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 226 } 227 228 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 229 if (!X86ScalarSSEf64) { 230 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 231 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 232 } 233 234 // Scalar integer divide and remainder are lowered to use operations that 235 // produce two results, to match the available instructions. This exposes 236 // the two-result form to trivial CSE, which is able to combine x/y and x%y 237 // into a single instruction. 238 // 239 // Scalar integer multiply-high is also lowered to use two-result 240 // operations, to match the available instructions. However, plain multiply 241 // (low) operations are left as Legal, as there are single-result 242 // instructions for this in x86. Using the two-result multiply instructions 243 // when both high and low results are needed must be arranged by dagcombine. 244 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 245 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 246 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 247 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 248 setOperationAction(ISD::SREM , MVT::i8 , Expand); 249 setOperationAction(ISD::UREM , MVT::i8 , Expand); 250 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 251 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 252 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 253 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 254 setOperationAction(ISD::SREM , MVT::i16 , Expand); 255 setOperationAction(ISD::UREM , MVT::i16 , Expand); 256 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 257 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 258 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 259 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 260 setOperationAction(ISD::SREM , MVT::i32 , Expand); 261 setOperationAction(ISD::UREM , MVT::i32 , Expand); 262 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 263 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 264 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 265 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 266 setOperationAction(ISD::SREM , MVT::i64 , Expand); 267 setOperationAction(ISD::UREM , MVT::i64 , Expand); 268 269 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 270 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 271 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 272 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 273 if (Subtarget->is64Bit()) 274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 276 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 278 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 279 setOperationAction(ISD::FREM , MVT::f32 , Expand); 280 setOperationAction(ISD::FREM , MVT::f64 , Expand); 281 setOperationAction(ISD::FREM , MVT::f80 , Expand); 282 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 283 284 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 287 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 288 if (Disable16Bit) { 289 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 290 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 291 } else { 292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 294 } 295 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 296 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 297 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 298 if (Subtarget->is64Bit()) { 299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 300 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 301 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 302 } 303 304 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 305 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 306 307 // These should be promoted to a larger select which is supported. 308 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 309 // X86 wants to expand cmov itself. 310 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 311 if (Disable16Bit) 312 setOperationAction(ISD::SELECT , MVT::i16 , Expand); 313 else 314 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 315 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 316 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 317 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 318 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 319 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 320 if (Disable16Bit) 321 setOperationAction(ISD::SETCC , MVT::i16 , Expand); 322 else 323 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 324 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 325 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 326 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 327 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 328 if (Subtarget->is64Bit()) { 329 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 330 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 331 } 332 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 333 334 // Darwin ABI issue. 335 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 336 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 337 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 338 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 339 if (Subtarget->is64Bit()) 340 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 341 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 342 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 343 if (Subtarget->is64Bit()) { 344 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 345 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 346 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 347 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 348 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 349 } 350 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 351 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 352 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 353 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 354 if (Subtarget->is64Bit()) { 355 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 356 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 357 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 358 } 359 360 if (Subtarget->hasSSE1()) 361 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 362 363 if (!Subtarget->hasSSE2()) 364 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 365 366 // Expand certain atomics 367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 371 372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 376 377 if (!Subtarget->is64Bit()) { 378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 385 } 386 387 // FIXME - use subtarget debug flags 388 if (!Subtarget->isTargetDarwin() && 389 !Subtarget->isTargetELF() && 390 !Subtarget->isTargetCygMing()) { 391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 392 } 393 394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 398 if (Subtarget->is64Bit()) { 399 setExceptionPointerRegister(X86::RAX); 400 setExceptionSelectorRegister(X86::RDX); 401 } else { 402 setExceptionPointerRegister(X86::EAX); 403 setExceptionSelectorRegister(X86::EDX); 404 } 405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 407 408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 409 410 setOperationAction(ISD::TRAP, MVT::Other, Legal); 411 412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 413 setOperationAction(ISD::VASTART , MVT::Other, Custom); 414 setOperationAction(ISD::VAEND , MVT::Other, Expand); 415 if (Subtarget->is64Bit()) { 416 setOperationAction(ISD::VAARG , MVT::Other, Custom); 417 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 418 } else { 419 setOperationAction(ISD::VAARG , MVT::Other, Expand); 420 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 421 } 422 423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 425 if (Subtarget->is64Bit()) 426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 427 if (Subtarget->isTargetCygMing()) 428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 429 else 430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 431 432 if (!UseSoftFloat && X86ScalarSSEf64) { 433 // f32 and f64 use SSE. 434 // Set up the FP register classes. 435 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 436 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 437 438 // Use ANDPD to simulate FABS. 439 setOperationAction(ISD::FABS , MVT::f64, Custom); 440 setOperationAction(ISD::FABS , MVT::f32, Custom); 441 442 // Use XORP to simulate FNEG. 443 setOperationAction(ISD::FNEG , MVT::f64, Custom); 444 setOperationAction(ISD::FNEG , MVT::f32, Custom); 445 446 // Use ANDPD and ORPD to simulate FCOPYSIGN. 447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 449 450 // We don't support sin/cos/fmod 451 setOperationAction(ISD::FSIN , MVT::f64, Expand); 452 setOperationAction(ISD::FCOS , MVT::f64, Expand); 453 setOperationAction(ISD::FSIN , MVT::f32, Expand); 454 setOperationAction(ISD::FCOS , MVT::f32, Expand); 455 456 // Expand FP immediates into loads from the stack, except for the special 457 // cases we handle. 458 addLegalFPImmediate(APFloat(+0.0)); // xorpd 459 addLegalFPImmediate(APFloat(+0.0f)); // xorps 460 } else if (!UseSoftFloat && X86ScalarSSEf32) { 461 // Use SSE for f32, x87 for f64. 462 // Set up the FP register classes. 463 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 465 466 // Use ANDPS to simulate FABS. 467 setOperationAction(ISD::FABS , MVT::f32, Custom); 468 469 // Use XORP to simulate FNEG. 470 setOperationAction(ISD::FNEG , MVT::f32, Custom); 471 472 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 473 474 // Use ANDPS and ORPS to simulate FCOPYSIGN. 475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 477 478 // We don't support sin/cos/fmod 479 setOperationAction(ISD::FSIN , MVT::f32, Expand); 480 setOperationAction(ISD::FCOS , MVT::f32, Expand); 481 482 // Special cases we handle for FP constants. 483 addLegalFPImmediate(APFloat(+0.0f)); // xorps 484 addLegalFPImmediate(APFloat(+0.0)); // FLD0 485 addLegalFPImmediate(APFloat(+1.0)); // FLD1 486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 488 489 if (!UnsafeFPMath) { 490 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 491 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 492 } 493 } else if (!UseSoftFloat) { 494 // f32 and f64 in x87. 495 // Set up the FP register classes. 496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 498 499 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 500 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 503 504 if (!UnsafeFPMath) { 505 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 506 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 507 } 508 addLegalFPImmediate(APFloat(+0.0)); // FLD0 509 addLegalFPImmediate(APFloat(+1.0)); // FLD1 510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 516 } 517 518 // Long double always uses X87. 519 if (!UseSoftFloat) { 520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 521 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 523 { 524 bool ignored; 525 APFloat TmpFlt(+0.0); 526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 527 &ignored); 528 addLegalFPImmediate(TmpFlt); // FLD0 529 TmpFlt.changeSign(); 530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 531 APFloat TmpFlt2(+1.0); 532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 533 &ignored); 534 addLegalFPImmediate(TmpFlt2); // FLD1 535 TmpFlt2.changeSign(); 536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 537 } 538 539 if (!UnsafeFPMath) { 540 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 541 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 542 } 543 } 544 545 // Always use a library call for pow. 546 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 547 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 548 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 549 550 setOperationAction(ISD::FLOG, MVT::f80, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 552 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 553 setOperationAction(ISD::FEXP, MVT::f80, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 555 556 // First set operation action for all vector types to either promote 557 // (for widening) or expand (for scalarization). Then we will selectively 558 // turn on ones that can be effectively codegen'd. 559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 616 setTruncStoreAction((MVT::SimpleValueType)VT, 617 (MVT::SimpleValueType)InnerVT, Expand); 618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 621 } 622 623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 624 // with -msoft-float, disable use of MMX as well. 625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 626 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 627 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 628 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 629 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 630 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 631 632 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 633 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 634 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 635 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 636 637 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 638 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 639 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 640 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 641 642 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 643 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 644 645 setOperationAction(ISD::AND, MVT::v8i8, Promote); 646 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 647 setOperationAction(ISD::AND, MVT::v4i16, Promote); 648 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 649 setOperationAction(ISD::AND, MVT::v2i32, Promote); 650 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 651 setOperationAction(ISD::AND, MVT::v1i64, Legal); 652 653 setOperationAction(ISD::OR, MVT::v8i8, Promote); 654 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 655 setOperationAction(ISD::OR, MVT::v4i16, Promote); 656 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 657 setOperationAction(ISD::OR, MVT::v2i32, Promote); 658 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 659 setOperationAction(ISD::OR, MVT::v1i64, Legal); 660 661 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 662 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 663 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 664 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 665 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 666 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 667 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 668 669 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 670 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 671 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 672 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 673 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 674 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 675 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 676 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 677 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 678 679 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 680 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 681 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 682 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 683 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 684 685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 689 690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 692 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 694 695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 696 697 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 698 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 699 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 700 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 701 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 702 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 703 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 704 } 705 706 if (!UseSoftFloat && Subtarget->hasSSE1()) { 707 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 708 709 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 710 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 711 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 712 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 713 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 714 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 715 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 716 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 717 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 719 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 720 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 721 } 722 723 if (!UseSoftFloat && Subtarget->hasSSE2()) { 724 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 725 726 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 727 // registers cannot be used even for integer operations. 728 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 729 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 730 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 731 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 732 733 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 734 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 735 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 736 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 737 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 738 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 739 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 740 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 741 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 742 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 743 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 744 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 745 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 746 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 747 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 748 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 749 750 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 751 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 752 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 753 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 754 755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 758 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 760 761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 764 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 765 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 766 767 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 768 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 769 EVT VT = (MVT::SimpleValueType)i; 770 // Do not attempt to custom lower non-power-of-2 vectors 771 if (!isPowerOf2_32(VT.getVectorNumElements())) 772 continue; 773 // Do not attempt to custom lower non-128-bit vectors 774 if (!VT.is128BitVector()) 775 continue; 776 setOperationAction(ISD::BUILD_VECTOR, 777 VT.getSimpleVT().SimpleTy, Custom); 778 setOperationAction(ISD::VECTOR_SHUFFLE, 779 VT.getSimpleVT().SimpleTy, Custom); 780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 781 VT.getSimpleVT().SimpleTy, Custom); 782 } 783 784 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 785 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 790 791 if (Subtarget->is64Bit()) { 792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 794 } 795 796 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 797 // FIXME: This produces lots of inefficiencies in isel since 798 // we then need notice that most of our operands have been implicitly 799 // converted to v2i64. 800 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 801 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 802 EVT VT = SVT; 803 804 // Do not attempt to promote non-128-bit vectors 805 if (!VT.is128BitVector()) { 806 continue; 807 } 808 809 setOperationAction(ISD::AND, SVT, Promote); 810 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 811 setOperationAction(ISD::OR, SVT, Promote); 812 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 813 setOperationAction(ISD::XOR, SVT, Promote); 814 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 815 setOperationAction(ISD::LOAD, SVT, Promote); 816 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 817 setOperationAction(ISD::SELECT, SVT, Promote); 818 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 819 } 820 821 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 822 823 // Custom lower v2i64 and v2f64 selects. 824 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 825 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 826 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 827 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 828 829 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 830 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 831 if (!DisableMMX && Subtarget->hasMMX()) { 832 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 833 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 834 } 835 } 836 837 if (Subtarget->hasSSE41()) { 838 // FIXME: Do we need to handle scalar-to-vector here? 839 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 840 841 // i8 and i16 vectors are custom , because the source register and source 842 // source memory operand types are not the same width. f32 vectors are 843 // custom since the immediate controlling the insert encodes additional 844 // information. 845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 849 850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 853 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 854 855 if (Subtarget->is64Bit()) { 856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 858 } 859 } 860 861 if (Subtarget->hasSSE42()) { 862 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 863 } 864 865 if (!UseSoftFloat && Subtarget->hasAVX()) { 866 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 867 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 868 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 869 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 870 871 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 872 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 873 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 874 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 875 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 876 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 877 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 878 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 879 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 880 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 881 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 882 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 883 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 884 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 885 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 886 887 // Operations to consider commented out -v16i16 v32i8 888 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 889 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 890 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 891 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 892 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 893 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 894 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 895 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 896 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 897 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 898 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 899 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 900 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 901 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 902 903 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 904 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 905 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 906 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 907 908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 909 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 910 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 913 914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 915 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 917 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 920 921#if 0 922 // Not sure we want to do this since there are no 256-bit integer 923 // operations in AVX 924 925 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 926 // This includes 256-bit vectors 927 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 928 EVT VT = (MVT::SimpleValueType)i; 929 930 // Do not attempt to custom lower non-power-of-2 vectors 931 if (!isPowerOf2_32(VT.getVectorNumElements())) 932 continue; 933 934 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 935 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 937 } 938 939 if (Subtarget->is64Bit()) { 940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 942 } 943#endif 944 945#if 0 946 // Not sure we want to do this since there are no 256-bit integer 947 // operations in AVX 948 949 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 950 // Including 256-bit vectors 951 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 952 EVT VT = (MVT::SimpleValueType)i; 953 954 if (!VT.is256BitVector()) { 955 continue; 956 } 957 setOperationAction(ISD::AND, VT, Promote); 958 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 959 setOperationAction(ISD::OR, VT, Promote); 960 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 961 setOperationAction(ISD::XOR, VT, Promote); 962 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 963 setOperationAction(ISD::LOAD, VT, Promote); 964 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 965 setOperationAction(ISD::SELECT, VT, Promote); 966 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 967 } 968 969 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 970#endif 971 } 972 973 // We want to custom lower some of our intrinsics. 974 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 975 976 // Add/Sub/Mul with overflow operations are custom lowered. 977 setOperationAction(ISD::SADDO, MVT::i32, Custom); 978 setOperationAction(ISD::SADDO, MVT::i64, Custom); 979 setOperationAction(ISD::UADDO, MVT::i32, Custom); 980 setOperationAction(ISD::UADDO, MVT::i64, Custom); 981 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 982 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 983 setOperationAction(ISD::USUBO, MVT::i32, Custom); 984 setOperationAction(ISD::USUBO, MVT::i64, Custom); 985 setOperationAction(ISD::SMULO, MVT::i32, Custom); 986 setOperationAction(ISD::SMULO, MVT::i64, Custom); 987 988 if (!Subtarget->is64Bit()) { 989 // These libcalls are not available in 32-bit. 990 setLibcallName(RTLIB::SHL_I128, 0); 991 setLibcallName(RTLIB::SRL_I128, 0); 992 setLibcallName(RTLIB::SRA_I128, 0); 993 } 994 995 // We have target-specific dag combine patterns for the following nodes: 996 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 997 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 998 setTargetDAGCombine(ISD::BUILD_VECTOR); 999 setTargetDAGCombine(ISD::SELECT); 1000 setTargetDAGCombine(ISD::SHL); 1001 setTargetDAGCombine(ISD::SRA); 1002 setTargetDAGCombine(ISD::SRL); 1003 setTargetDAGCombine(ISD::OR); 1004 setTargetDAGCombine(ISD::STORE); 1005 setTargetDAGCombine(ISD::MEMBARRIER); 1006 setTargetDAGCombine(ISD::ZERO_EXTEND); 1007 if (Subtarget->is64Bit()) 1008 setTargetDAGCombine(ISD::MUL); 1009 1010 computeRegisterProperties(); 1011 1012 // FIXME: These should be based on subtarget info. Plus, the values should 1013 // be smaller when we are in optimizing for size mode. 1014 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1015 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1016 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1017 setPrefLoopAlignment(16); 1018 benefitFromCodePlacementOpt = true; 1019} 1020 1021 1022MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1023 return MVT::i8; 1024} 1025 1026 1027/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1028/// the desired ByVal argument alignment. 1029static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1030 if (MaxAlign == 16) 1031 return; 1032 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1033 if (VTy->getBitWidth() == 128) 1034 MaxAlign = 16; 1035 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1036 unsigned EltAlign = 0; 1037 getMaxByValAlign(ATy->getElementType(), EltAlign); 1038 if (EltAlign > MaxAlign) 1039 MaxAlign = EltAlign; 1040 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1041 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1042 unsigned EltAlign = 0; 1043 getMaxByValAlign(STy->getElementType(i), EltAlign); 1044 if (EltAlign > MaxAlign) 1045 MaxAlign = EltAlign; 1046 if (MaxAlign == 16) 1047 break; 1048 } 1049 } 1050 return; 1051} 1052 1053/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1054/// function arguments in the caller parameter area. For X86, aggregates 1055/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1056/// are at 4-byte boundaries. 1057unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1058 if (Subtarget->is64Bit()) { 1059 // Max of 8 and alignment of type. 1060 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1061 if (TyAlign > 8) 1062 return TyAlign; 1063 return 8; 1064 } 1065 1066 unsigned Align = 4; 1067 if (Subtarget->hasSSE1()) 1068 getMaxByValAlign(Ty, Align); 1069 return Align; 1070} 1071 1072/// getOptimalMemOpType - Returns the target specific optimal type for load 1073/// and store operations as a result of memset, memcpy, and memmove lowering. 1074/// If DstAlign is zero that means it's safe to destination alignment can 1075/// satisfy any constraint. Similarly if SrcAlign is zero it means there 1076/// isn't a need to check it against alignment requirement, probably because 1077/// the source does not need to be loaded. It returns EVT::Other if 1078/// SelectionDAG should be responsible for determining it. 1079EVT 1080X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1081 unsigned DstAlign, unsigned SrcAlign, 1082 bool SafeToUseFP, 1083 SelectionDAG &DAG) const { 1084 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1085 // linux. This is because the stack realignment code can't handle certain 1086 // cases like PR2962. This should be removed when PR2962 is fixed. 1087 const Function *F = DAG.getMachineFunction().getFunction(); 1088 if (!F->hasFnAttr(Attribute::NoImplicitFloat)) { 1089 if (Size >= 16 && 1090 (Subtarget->isUnalignedMemAccessFast() || 1091 (DstAlign == 0 || DstAlign >= 16) && 1092 (SrcAlign == 0 || SrcAlign >= 16)) && 1093 Subtarget->getStackAlignment() >= 16) { 1094 if (Subtarget->hasSSE2()) 1095 return MVT::v4i32; 1096 if (SafeToUseFP && Subtarget->hasSSE1()) 1097 return MVT::v4f32; 1098 } else if (SafeToUseFP && 1099 Size >= 8 && 1100 !Subtarget->is64Bit() && 1101 Subtarget->getStackAlignment() >= 8 && 1102 Subtarget->hasSSE2()) 1103 return MVT::f64; 1104 } 1105 if (Subtarget->is64Bit() && Size >= 8) 1106 return MVT::i64; 1107 return MVT::i32; 1108} 1109 1110/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1111/// current function. The returned value is a member of the 1112/// MachineJumpTableInfo::JTEntryKind enum. 1113unsigned X86TargetLowering::getJumpTableEncoding() const { 1114 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1115 // symbol. 1116 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1117 Subtarget->isPICStyleGOT()) 1118 return MachineJumpTableInfo::EK_Custom32; 1119 1120 // Otherwise, use the normal jump table encoding heuristics. 1121 return TargetLowering::getJumpTableEncoding(); 1122} 1123 1124/// getPICBaseSymbol - Return the X86-32 PIC base. 1125MCSymbol * 1126X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1127 MCContext &Ctx) const { 1128 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1129 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1130 Twine(MF->getFunctionNumber())+"$pb"); 1131} 1132 1133 1134const MCExpr * 1135X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1136 const MachineBasicBlock *MBB, 1137 unsigned uid,MCContext &Ctx) const{ 1138 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1139 Subtarget->isPICStyleGOT()); 1140 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1141 // entries. 1142 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1143 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1144} 1145 1146/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1147/// jumptable. 1148SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1149 SelectionDAG &DAG) const { 1150 if (!Subtarget->is64Bit()) 1151 // This doesn't have DebugLoc associated with it, but is not really the 1152 // same as a Register. 1153 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1154 getPointerTy()); 1155 return Table; 1156} 1157 1158/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1159/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1160/// MCExpr. 1161const MCExpr *X86TargetLowering:: 1162getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1163 MCContext &Ctx) const { 1164 // X86-64 uses RIP relative addressing based on the jump table label. 1165 if (Subtarget->isPICStyleRIPRel()) 1166 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1167 1168 // Otherwise, the reference is relative to the PIC base. 1169 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1170} 1171 1172/// getFunctionAlignment - Return the Log2 alignment of this function. 1173unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1174 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1175} 1176 1177//===----------------------------------------------------------------------===// 1178// Return Value Calling Convention Implementation 1179//===----------------------------------------------------------------------===// 1180 1181#include "X86GenCallingConv.inc" 1182 1183bool 1184X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1185 const SmallVectorImpl<EVT> &OutTys, 1186 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1187 SelectionDAG &DAG) { 1188 SmallVector<CCValAssign, 16> RVLocs; 1189 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1190 RVLocs, *DAG.getContext()); 1191 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86); 1192} 1193 1194SDValue 1195X86TargetLowering::LowerReturn(SDValue Chain, 1196 CallingConv::ID CallConv, bool isVarArg, 1197 const SmallVectorImpl<ISD::OutputArg> &Outs, 1198 DebugLoc dl, SelectionDAG &DAG) { 1199 1200 SmallVector<CCValAssign, 16> RVLocs; 1201 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1202 RVLocs, *DAG.getContext()); 1203 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1204 1205 // Add the regs to the liveout set for the function. 1206 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1207 for (unsigned i = 0; i != RVLocs.size(); ++i) 1208 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1209 MRI.addLiveOut(RVLocs[i].getLocReg()); 1210 1211 SDValue Flag; 1212 1213 SmallVector<SDValue, 6> RetOps; 1214 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1215 // Operand #1 = Bytes To Pop 1216 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16)); 1217 1218 // Copy the result values into the output registers. 1219 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1220 CCValAssign &VA = RVLocs[i]; 1221 assert(VA.isRegLoc() && "Can only return in registers!"); 1222 SDValue ValToCopy = Outs[i].Val; 1223 1224 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1225 // the RET instruction and handled by the FP Stackifier. 1226 if (VA.getLocReg() == X86::ST0 || 1227 VA.getLocReg() == X86::ST1) { 1228 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1229 // change the value to the FP stack register class. 1230 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1231 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1232 RetOps.push_back(ValToCopy); 1233 // Don't emit a copytoreg. 1234 continue; 1235 } 1236 1237 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1238 // which is returned in RAX / RDX. 1239 if (Subtarget->is64Bit()) { 1240 EVT ValVT = ValToCopy.getValueType(); 1241 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1242 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1243 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1244 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1245 } 1246 } 1247 1248 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1249 Flag = Chain.getValue(1); 1250 } 1251 1252 // The x86-64 ABI for returning structs by value requires that we copy 1253 // the sret argument into %rax for the return. We saved the argument into 1254 // a virtual register in the entry block, so now we copy the value out 1255 // and into %rax. 1256 if (Subtarget->is64Bit() && 1257 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1258 MachineFunction &MF = DAG.getMachineFunction(); 1259 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1260 unsigned Reg = FuncInfo->getSRetReturnReg(); 1261 if (!Reg) { 1262 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64)); 1263 FuncInfo->setSRetReturnReg(Reg); 1264 } 1265 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1266 1267 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1268 Flag = Chain.getValue(1); 1269 1270 // RAX now acts like a return value. 1271 MRI.addLiveOut(X86::RAX); 1272 } 1273 1274 RetOps[0] = Chain; // Update chain. 1275 1276 // Add the flag if we have it. 1277 if (Flag.getNode()) 1278 RetOps.push_back(Flag); 1279 1280 return DAG.getNode(X86ISD::RET_FLAG, dl, 1281 MVT::Other, &RetOps[0], RetOps.size()); 1282} 1283 1284/// LowerCallResult - Lower the result values of a call into the 1285/// appropriate copies out of appropriate physical registers. 1286/// 1287SDValue 1288X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1289 CallingConv::ID CallConv, bool isVarArg, 1290 const SmallVectorImpl<ISD::InputArg> &Ins, 1291 DebugLoc dl, SelectionDAG &DAG, 1292 SmallVectorImpl<SDValue> &InVals) { 1293 1294 // Assign locations to each value returned by this call. 1295 SmallVector<CCValAssign, 16> RVLocs; 1296 bool Is64Bit = Subtarget->is64Bit(); 1297 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1298 RVLocs, *DAG.getContext()); 1299 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1300 1301 // Copy all of the result registers out of their specified physreg. 1302 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1303 CCValAssign &VA = RVLocs[i]; 1304 EVT CopyVT = VA.getValVT(); 1305 1306 // If this is x86-64, and we disabled SSE, we can't return FP values 1307 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1308 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1309 llvm_report_error("SSE register return with SSE disabled"); 1310 } 1311 1312 // If this is a call to a function that returns an fp value on the floating 1313 // point stack, but where we prefer to use the value in xmm registers, copy 1314 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1315 if ((VA.getLocReg() == X86::ST0 || 1316 VA.getLocReg() == X86::ST1) && 1317 isScalarFPTypeInSSEReg(VA.getValVT())) { 1318 CopyVT = MVT::f80; 1319 } 1320 1321 SDValue Val; 1322 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1323 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1324 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1325 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1326 MVT::v2i64, InFlag).getValue(1); 1327 Val = Chain.getValue(0); 1328 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1329 Val, DAG.getConstant(0, MVT::i64)); 1330 } else { 1331 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1332 MVT::i64, InFlag).getValue(1); 1333 Val = Chain.getValue(0); 1334 } 1335 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1336 } else { 1337 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1338 CopyVT, InFlag).getValue(1); 1339 Val = Chain.getValue(0); 1340 } 1341 InFlag = Chain.getValue(2); 1342 1343 if (CopyVT != VA.getValVT()) { 1344 // Round the F80 the right size, which also moves to the appropriate xmm 1345 // register. 1346 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1347 // This truncation won't change the value. 1348 DAG.getIntPtrConstant(1)); 1349 } 1350 1351 InVals.push_back(Val); 1352 } 1353 1354 return Chain; 1355} 1356 1357 1358//===----------------------------------------------------------------------===// 1359// C & StdCall & Fast Calling Convention implementation 1360//===----------------------------------------------------------------------===// 1361// StdCall calling convention seems to be standard for many Windows' API 1362// routines and around. It differs from C calling convention just a little: 1363// callee should clean up the stack, not caller. Symbols should be also 1364// decorated in some fancy way :) It doesn't support any vector arguments. 1365// For info on fast calling convention see Fast Calling Convention (tail call) 1366// implementation LowerX86_32FastCCCallTo. 1367 1368/// CallIsStructReturn - Determines whether a call uses struct return 1369/// semantics. 1370static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1371 if (Outs.empty()) 1372 return false; 1373 1374 return Outs[0].Flags.isSRet(); 1375} 1376 1377/// ArgsAreStructReturn - Determines whether a function uses struct 1378/// return semantics. 1379static bool 1380ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1381 if (Ins.empty()) 1382 return false; 1383 1384 return Ins[0].Flags.isSRet(); 1385} 1386 1387/// IsCalleePop - Determines whether the callee is required to pop its 1388/// own arguments. Callee pop is necessary to support tail calls. 1389bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ 1390 if (IsVarArg) 1391 return false; 1392 1393 switch (CallingConv) { 1394 default: 1395 return false; 1396 case CallingConv::X86_StdCall: 1397 return !Subtarget->is64Bit(); 1398 case CallingConv::X86_FastCall: 1399 return !Subtarget->is64Bit(); 1400 case CallingConv::Fast: 1401 return GuaranteedTailCallOpt; 1402 case CallingConv::GHC: 1403 return GuaranteedTailCallOpt; 1404 } 1405} 1406 1407/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1408/// given CallingConvention value. 1409CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1410 if (Subtarget->is64Bit()) { 1411 if (CC == CallingConv::GHC) 1412 return CC_X86_64_GHC; 1413 else if (Subtarget->isTargetWin64()) 1414 return CC_X86_Win64_C; 1415 else 1416 return CC_X86_64_C; 1417 } 1418 1419 if (CC == CallingConv::X86_FastCall) 1420 return CC_X86_32_FastCall; 1421 else if (CC == CallingConv::Fast) 1422 return CC_X86_32_FastCC; 1423 else if (CC == CallingConv::GHC) 1424 return CC_X86_32_GHC; 1425 else 1426 return CC_X86_32_C; 1427} 1428 1429/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1430/// by "Src" to address "Dst" with size and alignment information specified by 1431/// the specific parameter attribute. The copy will be passed as a byval 1432/// function parameter. 1433static SDValue 1434CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1435 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1436 DebugLoc dl) { 1437 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1438 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1439 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1440} 1441 1442/// IsTailCallConvention - Return true if the calling convention is one that 1443/// supports tail call optimization. 1444static bool IsTailCallConvention(CallingConv::ID CC) { 1445 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1446} 1447 1448/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1449/// a tailcall target by changing its ABI. 1450static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1451 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1452} 1453 1454SDValue 1455X86TargetLowering::LowerMemArgument(SDValue Chain, 1456 CallingConv::ID CallConv, 1457 const SmallVectorImpl<ISD::InputArg> &Ins, 1458 DebugLoc dl, SelectionDAG &DAG, 1459 const CCValAssign &VA, 1460 MachineFrameInfo *MFI, 1461 unsigned i) { 1462 // Create the nodes corresponding to a load from this parameter slot. 1463 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1464 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1465 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1466 EVT ValVT; 1467 1468 // If value is passed by pointer we have address passed instead of the value 1469 // itself. 1470 if (VA.getLocInfo() == CCValAssign::Indirect) 1471 ValVT = VA.getLocVT(); 1472 else 1473 ValVT = VA.getValVT(); 1474 1475 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1476 // changed with more analysis. 1477 // In case of tail call optimization mark all arguments mutable. Since they 1478 // could be overwritten by lowering of arguments in case of a tail call. 1479 if (Flags.isByVal()) { 1480 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1481 VA.getLocMemOffset(), isImmutable, false); 1482 return DAG.getFrameIndex(FI, getPointerTy()); 1483 } else { 1484 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1485 VA.getLocMemOffset(), isImmutable, false); 1486 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1487 return DAG.getLoad(ValVT, dl, Chain, FIN, 1488 PseudoSourceValue::getFixedStack(FI), 0, 1489 false, false, 0); 1490 } 1491} 1492 1493SDValue 1494X86TargetLowering::LowerFormalArguments(SDValue Chain, 1495 CallingConv::ID CallConv, 1496 bool isVarArg, 1497 const SmallVectorImpl<ISD::InputArg> &Ins, 1498 DebugLoc dl, 1499 SelectionDAG &DAG, 1500 SmallVectorImpl<SDValue> &InVals) { 1501 MachineFunction &MF = DAG.getMachineFunction(); 1502 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1503 1504 const Function* Fn = MF.getFunction(); 1505 if (Fn->hasExternalLinkage() && 1506 Subtarget->isTargetCygMing() && 1507 Fn->getName() == "main") 1508 FuncInfo->setForceFramePointer(true); 1509 1510 MachineFrameInfo *MFI = MF.getFrameInfo(); 1511 bool Is64Bit = Subtarget->is64Bit(); 1512 bool IsWin64 = Subtarget->isTargetWin64(); 1513 1514 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1515 "Var args not supported with calling convention fastcc or ghc"); 1516 1517 // Assign locations to all of the incoming arguments. 1518 SmallVector<CCValAssign, 16> ArgLocs; 1519 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1520 ArgLocs, *DAG.getContext()); 1521 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1522 1523 unsigned LastVal = ~0U; 1524 SDValue ArgValue; 1525 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1526 CCValAssign &VA = ArgLocs[i]; 1527 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1528 // places. 1529 assert(VA.getValNo() != LastVal && 1530 "Don't support value assigned to multiple locs yet"); 1531 LastVal = VA.getValNo(); 1532 1533 if (VA.isRegLoc()) { 1534 EVT RegVT = VA.getLocVT(); 1535 TargetRegisterClass *RC = NULL; 1536 if (RegVT == MVT::i32) 1537 RC = X86::GR32RegisterClass; 1538 else if (Is64Bit && RegVT == MVT::i64) 1539 RC = X86::GR64RegisterClass; 1540 else if (RegVT == MVT::f32) 1541 RC = X86::FR32RegisterClass; 1542 else if (RegVT == MVT::f64) 1543 RC = X86::FR64RegisterClass; 1544 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1545 RC = X86::VR128RegisterClass; 1546 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1547 RC = X86::VR64RegisterClass; 1548 else 1549 llvm_unreachable("Unknown argument type!"); 1550 1551 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1552 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1553 1554 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1555 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1556 // right size. 1557 if (VA.getLocInfo() == CCValAssign::SExt) 1558 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1559 DAG.getValueType(VA.getValVT())); 1560 else if (VA.getLocInfo() == CCValAssign::ZExt) 1561 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1562 DAG.getValueType(VA.getValVT())); 1563 else if (VA.getLocInfo() == CCValAssign::BCvt) 1564 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1565 1566 if (VA.isExtInLoc()) { 1567 // Handle MMX values passed in XMM regs. 1568 if (RegVT.isVector()) { 1569 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1570 ArgValue, DAG.getConstant(0, MVT::i64)); 1571 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1572 } else 1573 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1574 } 1575 } else { 1576 assert(VA.isMemLoc()); 1577 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1578 } 1579 1580 // If value is passed via pointer - do a load. 1581 if (VA.getLocInfo() == CCValAssign::Indirect) 1582 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1583 false, false, 0); 1584 1585 InVals.push_back(ArgValue); 1586 } 1587 1588 // The x86-64 ABI for returning structs by value requires that we copy 1589 // the sret argument into %rax for the return. Save the argument into 1590 // a virtual register so that we can access it from the return points. 1591 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1592 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1593 unsigned Reg = FuncInfo->getSRetReturnReg(); 1594 if (!Reg) { 1595 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1596 FuncInfo->setSRetReturnReg(Reg); 1597 } 1598 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1599 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1600 } 1601 1602 unsigned StackSize = CCInfo.getNextStackOffset(); 1603 // Align stack specially for tail calls. 1604 if (FuncIsMadeTailCallSafe(CallConv)) 1605 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1606 1607 // If the function takes variable number of arguments, make a frame index for 1608 // the start of the first vararg value... for expansion of llvm.va_start. 1609 if (isVarArg) { 1610 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1611 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false); 1612 } 1613 if (Is64Bit) { 1614 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1615 1616 // FIXME: We should really autogenerate these arrays 1617 static const unsigned GPR64ArgRegsWin64[] = { 1618 X86::RCX, X86::RDX, X86::R8, X86::R9 1619 }; 1620 static const unsigned XMMArgRegsWin64[] = { 1621 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1622 }; 1623 static const unsigned GPR64ArgRegs64Bit[] = { 1624 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1625 }; 1626 static const unsigned XMMArgRegs64Bit[] = { 1627 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1628 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1629 }; 1630 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1631 1632 if (IsWin64) { 1633 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1634 GPR64ArgRegs = GPR64ArgRegsWin64; 1635 XMMArgRegs = XMMArgRegsWin64; 1636 } else { 1637 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1638 GPR64ArgRegs = GPR64ArgRegs64Bit; 1639 XMMArgRegs = XMMArgRegs64Bit; 1640 } 1641 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1642 TotalNumIntRegs); 1643 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1644 TotalNumXMMRegs); 1645 1646 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1647 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1648 "SSE register cannot be used when SSE is disabled!"); 1649 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1650 "SSE register cannot be used when SSE is disabled!"); 1651 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1652 // Kernel mode asks for SSE to be disabled, so don't push them 1653 // on the stack. 1654 TotalNumXMMRegs = 0; 1655 1656 // For X86-64, if there are vararg parameters that are passed via 1657 // registers, then we must store them to their spots on the stack so they 1658 // may be loaded by deferencing the result of va_next. 1659 VarArgsGPOffset = NumIntRegs * 8; 1660 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1661 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1662 TotalNumXMMRegs * 16, 16, 1663 false); 1664 1665 // Store the integer parameter registers. 1666 SmallVector<SDValue, 8> MemOps; 1667 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1668 unsigned Offset = VarArgsGPOffset; 1669 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1670 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1671 DAG.getIntPtrConstant(Offset)); 1672 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1673 X86::GR64RegisterClass); 1674 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1675 SDValue Store = 1676 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1677 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1678 Offset, false, false, 0); 1679 MemOps.push_back(Store); 1680 Offset += 8; 1681 } 1682 1683 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1684 // Now store the XMM (fp + vector) parameter registers. 1685 SmallVector<SDValue, 11> SaveXMMOps; 1686 SaveXMMOps.push_back(Chain); 1687 1688 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1689 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1690 SaveXMMOps.push_back(ALVal); 1691 1692 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1693 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1694 1695 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1696 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1697 X86::VR128RegisterClass); 1698 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1699 SaveXMMOps.push_back(Val); 1700 } 1701 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1702 MVT::Other, 1703 &SaveXMMOps[0], SaveXMMOps.size())); 1704 } 1705 1706 if (!MemOps.empty()) 1707 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1708 &MemOps[0], MemOps.size()); 1709 } 1710 } 1711 1712 // Some CCs need callee pop. 1713 if (IsCalleePop(isVarArg, CallConv)) { 1714 BytesToPopOnReturn = StackSize; // Callee pops everything. 1715 } else { 1716 BytesToPopOnReturn = 0; // Callee pops nothing. 1717 // If this is an sret function, the return should pop the hidden pointer. 1718 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1719 BytesToPopOnReturn = 4; 1720 } 1721 1722 if (!Is64Bit) { 1723 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1724 if (CallConv == CallingConv::X86_FastCall) 1725 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1726 } 1727 1728 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1729 1730 return Chain; 1731} 1732 1733SDValue 1734X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1735 SDValue StackPtr, SDValue Arg, 1736 DebugLoc dl, SelectionDAG &DAG, 1737 const CCValAssign &VA, 1738 ISD::ArgFlagsTy Flags) { 1739 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1740 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1741 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1742 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1743 if (Flags.isByVal()) { 1744 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1745 } 1746 return DAG.getStore(Chain, dl, Arg, PtrOff, 1747 PseudoSourceValue::getStack(), LocMemOffset, 1748 false, false, 0); 1749} 1750 1751/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1752/// optimization is performed and it is required. 1753SDValue 1754X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1755 SDValue &OutRetAddr, SDValue Chain, 1756 bool IsTailCall, bool Is64Bit, 1757 int FPDiff, DebugLoc dl) { 1758 // Adjust the Return address stack slot. 1759 EVT VT = getPointerTy(); 1760 OutRetAddr = getReturnAddressFrameIndex(DAG); 1761 1762 // Load the "old" Return address. 1763 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1764 return SDValue(OutRetAddr.getNode(), 1); 1765} 1766 1767/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1768/// optimization is performed and it is required (FPDiff!=0). 1769static SDValue 1770EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1771 SDValue Chain, SDValue RetAddrFrIdx, 1772 bool Is64Bit, int FPDiff, DebugLoc dl) { 1773 // Store the return address to the appropriate stack slot. 1774 if (!FPDiff) return Chain; 1775 // Calculate the new stack slot for the return address. 1776 int SlotSize = Is64Bit ? 8 : 4; 1777 int NewReturnAddrFI = 1778 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false); 1779 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1780 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1781 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1782 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1783 false, false, 0); 1784 return Chain; 1785} 1786 1787SDValue 1788X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1789 CallingConv::ID CallConv, bool isVarArg, 1790 bool &isTailCall, 1791 const SmallVectorImpl<ISD::OutputArg> &Outs, 1792 const SmallVectorImpl<ISD::InputArg> &Ins, 1793 DebugLoc dl, SelectionDAG &DAG, 1794 SmallVectorImpl<SDValue> &InVals) { 1795 MachineFunction &MF = DAG.getMachineFunction(); 1796 bool Is64Bit = Subtarget->is64Bit(); 1797 bool IsStructRet = CallIsStructReturn(Outs); 1798 bool IsSibcall = false; 1799 1800 if (isTailCall) { 1801 // Check if it's really possible to do a tail call. 1802 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1803 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1804 Outs, Ins, DAG); 1805 1806 // Sibcalls are automatically detected tailcalls which do not require 1807 // ABI changes. 1808 if (!GuaranteedTailCallOpt && isTailCall) 1809 IsSibcall = true; 1810 1811 if (isTailCall) 1812 ++NumTailCalls; 1813 } 1814 1815 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1816 "Var args not supported with calling convention fastcc or ghc"); 1817 1818 // Analyze operands of the call, assigning locations to each operand. 1819 SmallVector<CCValAssign, 16> ArgLocs; 1820 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1821 ArgLocs, *DAG.getContext()); 1822 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1823 1824 // Get a count of how many bytes are to be pushed on the stack. 1825 unsigned NumBytes = CCInfo.getNextStackOffset(); 1826 if (IsSibcall) 1827 // This is a sibcall. The memory operands are available in caller's 1828 // own caller's stack. 1829 NumBytes = 0; 1830 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 1831 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1832 1833 int FPDiff = 0; 1834 if (isTailCall && !IsSibcall) { 1835 // Lower arguments at fp - stackoffset + fpdiff. 1836 unsigned NumBytesCallerPushed = 1837 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1838 FPDiff = NumBytesCallerPushed - NumBytes; 1839 1840 // Set the delta of movement of the returnaddr stackslot. 1841 // But only set if delta is greater than previous delta. 1842 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1843 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1844 } 1845 1846 if (!IsSibcall) 1847 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1848 1849 SDValue RetAddrFrIdx; 1850 // Load return adress for tail calls. 1851 if (isTailCall && FPDiff) 1852 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1853 Is64Bit, FPDiff, dl); 1854 1855 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1856 SmallVector<SDValue, 8> MemOpChains; 1857 SDValue StackPtr; 1858 1859 // Walk the register/memloc assignments, inserting copies/loads. In the case 1860 // of tail call optimization arguments are handle later. 1861 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1862 CCValAssign &VA = ArgLocs[i]; 1863 EVT RegVT = VA.getLocVT(); 1864 SDValue Arg = Outs[i].Val; 1865 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1866 bool isByVal = Flags.isByVal(); 1867 1868 // Promote the value if needed. 1869 switch (VA.getLocInfo()) { 1870 default: llvm_unreachable("Unknown loc info!"); 1871 case CCValAssign::Full: break; 1872 case CCValAssign::SExt: 1873 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1874 break; 1875 case CCValAssign::ZExt: 1876 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1877 break; 1878 case CCValAssign::AExt: 1879 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1880 // Special case: passing MMX values in XMM registers. 1881 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1882 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1883 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1884 } else 1885 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1886 break; 1887 case CCValAssign::BCvt: 1888 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1889 break; 1890 case CCValAssign::Indirect: { 1891 // Store the argument. 1892 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1893 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1894 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1895 PseudoSourceValue::getFixedStack(FI), 0, 1896 false, false, 0); 1897 Arg = SpillSlot; 1898 break; 1899 } 1900 } 1901 1902 if (VA.isRegLoc()) { 1903 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1904 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1905 assert(VA.isMemLoc()); 1906 if (StackPtr.getNode() == 0) 1907 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1909 dl, DAG, VA, Flags)); 1910 } 1911 } 1912 1913 if (!MemOpChains.empty()) 1914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1915 &MemOpChains[0], MemOpChains.size()); 1916 1917 // Build a sequence of copy-to-reg nodes chained together with token chain 1918 // and flag operands which copy the outgoing args into registers. 1919 SDValue InFlag; 1920 // Tail call byval lowering might overwrite argument registers so in case of 1921 // tail call optimization the copies to registers are lowered later. 1922 if (!isTailCall) 1923 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1924 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1925 RegsToPass[i].second, InFlag); 1926 InFlag = Chain.getValue(1); 1927 } 1928 1929 if (Subtarget->isPICStyleGOT()) { 1930 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1931 // GOT pointer. 1932 if (!isTailCall) { 1933 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1934 DAG.getNode(X86ISD::GlobalBaseReg, 1935 DebugLoc::getUnknownLoc(), 1936 getPointerTy()), 1937 InFlag); 1938 InFlag = Chain.getValue(1); 1939 } else { 1940 // If we are tail calling and generating PIC/GOT style code load the 1941 // address of the callee into ECX. The value in ecx is used as target of 1942 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1943 // for tail calls on PIC/GOT architectures. Normally we would just put the 1944 // address of GOT into ebx and then call target@PLT. But for tail calls 1945 // ebx would be restored (since ebx is callee saved) before jumping to the 1946 // target@PLT. 1947 1948 // Note: The actual moving to ECX is done further down. 1949 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1950 if (G && !G->getGlobal()->hasHiddenVisibility() && 1951 !G->getGlobal()->hasProtectedVisibility()) 1952 Callee = LowerGlobalAddress(Callee, DAG); 1953 else if (isa<ExternalSymbolSDNode>(Callee)) 1954 Callee = LowerExternalSymbol(Callee, DAG); 1955 } 1956 } 1957 1958 if (Is64Bit && isVarArg) { 1959 // From AMD64 ABI document: 1960 // For calls that may call functions that use varargs or stdargs 1961 // (prototype-less calls or calls to functions containing ellipsis (...) in 1962 // the declaration) %al is used as hidden argument to specify the number 1963 // of SSE registers used. The contents of %al do not need to match exactly 1964 // the number of registers, but must be an ubound on the number of SSE 1965 // registers used and is in the range 0 - 8 inclusive. 1966 1967 // FIXME: Verify this on Win64 1968 // Count the number of XMM registers allocated. 1969 static const unsigned XMMArgRegs[] = { 1970 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1971 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1972 }; 1973 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1974 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1975 && "SSE registers cannot be used when SSE is disabled"); 1976 1977 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1978 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1979 InFlag = Chain.getValue(1); 1980 } 1981 1982 1983 // For tail calls lower the arguments to the 'real' stack slot. 1984 if (isTailCall) { 1985 // Force all the incoming stack arguments to be loaded from the stack 1986 // before any new outgoing arguments are stored to the stack, because the 1987 // outgoing stack slots may alias the incoming argument stack slots, and 1988 // the alias isn't otherwise explicit. This is slightly more conservative 1989 // than necessary, because it means that each store effectively depends 1990 // on every argument instead of just those arguments it would clobber. 1991 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1992 1993 SmallVector<SDValue, 8> MemOpChains2; 1994 SDValue FIN; 1995 int FI = 0; 1996 // Do not flag preceeding copytoreg stuff together with the following stuff. 1997 InFlag = SDValue(); 1998 if (GuaranteedTailCallOpt) { 1999 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2000 CCValAssign &VA = ArgLocs[i]; 2001 if (VA.isRegLoc()) 2002 continue; 2003 assert(VA.isMemLoc()); 2004 SDValue Arg = Outs[i].Val; 2005 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2006 // Create frame index. 2007 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2008 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2009 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false); 2010 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2011 2012 if (Flags.isByVal()) { 2013 // Copy relative to framepointer. 2014 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2015 if (StackPtr.getNode() == 0) 2016 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2017 getPointerTy()); 2018 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2019 2020 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2021 ArgChain, 2022 Flags, DAG, dl)); 2023 } else { 2024 // Store relative to framepointer. 2025 MemOpChains2.push_back( 2026 DAG.getStore(ArgChain, dl, Arg, FIN, 2027 PseudoSourceValue::getFixedStack(FI), 0, 2028 false, false, 0)); 2029 } 2030 } 2031 } 2032 2033 if (!MemOpChains2.empty()) 2034 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2035 &MemOpChains2[0], MemOpChains2.size()); 2036 2037 // Copy arguments to their registers. 2038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2040 RegsToPass[i].second, InFlag); 2041 InFlag = Chain.getValue(1); 2042 } 2043 InFlag =SDValue(); 2044 2045 // Store the return address to the appropriate stack slot. 2046 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2047 FPDiff, dl); 2048 } 2049 2050 bool WasGlobalOrExternal = false; 2051 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2052 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2053 // In the 64-bit large code model, we have to make all calls 2054 // through a register, since the call instruction's 32-bit 2055 // pc-relative offset may not be large enough to hold the whole 2056 // address. 2057 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2058 WasGlobalOrExternal = true; 2059 // If the callee is a GlobalAddress node (quite common, every direct call 2060 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2061 // it. 2062 2063 // We should use extra load for direct calls to dllimported functions in 2064 // non-JIT mode. 2065 GlobalValue *GV = G->getGlobal(); 2066 if (!GV->hasDLLImportLinkage()) { 2067 unsigned char OpFlags = 0; 2068 2069 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2070 // external symbols most go through the PLT in PIC mode. If the symbol 2071 // has hidden or protected visibility, or if it is static or local, then 2072 // we don't need to use the PLT - we can directly call it. 2073 if (Subtarget->isTargetELF() && 2074 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2075 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2076 OpFlags = X86II::MO_PLT; 2077 } else if (Subtarget->isPICStyleStubAny() && 2078 (GV->isDeclaration() || GV->isWeakForLinker()) && 2079 Subtarget->getDarwinVers() < 9) { 2080 // PC-relative references to external symbols should go through $stub, 2081 // unless we're building with the leopard linker or later, which 2082 // automatically synthesizes these stubs. 2083 OpFlags = X86II::MO_DARWIN_STUB; 2084 } 2085 2086 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 2087 G->getOffset(), OpFlags); 2088 } 2089 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2090 WasGlobalOrExternal = true; 2091 unsigned char OpFlags = 0; 2092 2093 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2094 // symbols should go through the PLT. 2095 if (Subtarget->isTargetELF() && 2096 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2097 OpFlags = X86II::MO_PLT; 2098 } else if (Subtarget->isPICStyleStubAny() && 2099 Subtarget->getDarwinVers() < 9) { 2100 // PC-relative references to external symbols should go through $stub, 2101 // unless we're building with the leopard linker or later, which 2102 // automatically synthesizes these stubs. 2103 OpFlags = X86II::MO_DARWIN_STUB; 2104 } 2105 2106 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2107 OpFlags); 2108 } 2109 2110 // Returns a chain & a flag for retval copy to use. 2111 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2112 SmallVector<SDValue, 8> Ops; 2113 2114 if (!IsSibcall && isTailCall) { 2115 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2116 DAG.getIntPtrConstant(0, true), InFlag); 2117 InFlag = Chain.getValue(1); 2118 } 2119 2120 Ops.push_back(Chain); 2121 Ops.push_back(Callee); 2122 2123 if (isTailCall) 2124 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2125 2126 // Add argument registers to the end of the list so that they are known live 2127 // into the call. 2128 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2129 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2130 RegsToPass[i].second.getValueType())); 2131 2132 // Add an implicit use GOT pointer in EBX. 2133 if (!isTailCall && Subtarget->isPICStyleGOT()) 2134 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2135 2136 // Add an implicit use of AL for x86 vararg functions. 2137 if (Is64Bit && isVarArg) 2138 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2139 2140 if (InFlag.getNode()) 2141 Ops.push_back(InFlag); 2142 2143 if (isTailCall) { 2144 // If this is the first return lowered for this function, add the regs 2145 // to the liveout set for the function. 2146 if (MF.getRegInfo().liveout_empty()) { 2147 SmallVector<CCValAssign, 16> RVLocs; 2148 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2149 *DAG.getContext()); 2150 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2151 for (unsigned i = 0; i != RVLocs.size(); ++i) 2152 if (RVLocs[i].isRegLoc()) 2153 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2154 } 2155 return DAG.getNode(X86ISD::TC_RETURN, dl, 2156 NodeTys, &Ops[0], Ops.size()); 2157 } 2158 2159 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2160 InFlag = Chain.getValue(1); 2161 2162 // Create the CALLSEQ_END node. 2163 unsigned NumBytesForCalleeToPush; 2164 if (IsCalleePop(isVarArg, CallConv)) 2165 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2166 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2167 // If this is a call to a struct-return function, the callee 2168 // pops the hidden struct pointer, so we have to push it back. 2169 // This is common for Darwin/X86, Linux & Mingw32 targets. 2170 NumBytesForCalleeToPush = 4; 2171 else 2172 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2173 2174 // Returns a flag for retval copy to use. 2175 if (!IsSibcall) { 2176 Chain = DAG.getCALLSEQ_END(Chain, 2177 DAG.getIntPtrConstant(NumBytes, true), 2178 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2179 true), 2180 InFlag); 2181 InFlag = Chain.getValue(1); 2182 } 2183 2184 // Handle result values, copying them out of physregs into vregs that we 2185 // return. 2186 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2187 Ins, dl, DAG, InVals); 2188} 2189 2190 2191//===----------------------------------------------------------------------===// 2192// Fast Calling Convention (tail call) implementation 2193//===----------------------------------------------------------------------===// 2194 2195// Like std call, callee cleans arguments, convention except that ECX is 2196// reserved for storing the tail called function address. Only 2 registers are 2197// free for argument passing (inreg). Tail call optimization is performed 2198// provided: 2199// * tailcallopt is enabled 2200// * caller/callee are fastcc 2201// On X86_64 architecture with GOT-style position independent code only local 2202// (within module) calls are supported at the moment. 2203// To keep the stack aligned according to platform abi the function 2204// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2205// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2206// If a tail called function callee has more arguments than the caller the 2207// caller needs to make sure that there is room to move the RETADDR to. This is 2208// achieved by reserving an area the size of the argument delta right after the 2209// original REtADDR, but before the saved framepointer or the spilled registers 2210// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2211// stack layout: 2212// arg1 2213// arg2 2214// RETADDR 2215// [ new RETADDR 2216// move area ] 2217// (possible EBP) 2218// ESI 2219// EDI 2220// local1 .. 2221 2222/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2223/// for a 16 byte align requirement. 2224unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2225 SelectionDAG& DAG) { 2226 MachineFunction &MF = DAG.getMachineFunction(); 2227 const TargetMachine &TM = MF.getTarget(); 2228 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2229 unsigned StackAlignment = TFI.getStackAlignment(); 2230 uint64_t AlignMask = StackAlignment - 1; 2231 int64_t Offset = StackSize; 2232 uint64_t SlotSize = TD->getPointerSize(); 2233 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2234 // Number smaller than 12 so just add the difference. 2235 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2236 } else { 2237 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2238 Offset = ((~AlignMask) & Offset) + StackAlignment + 2239 (StackAlignment-SlotSize); 2240 } 2241 return Offset; 2242} 2243 2244/// MatchingStackOffset - Return true if the given stack call argument is 2245/// already available in the same position (relatively) of the caller's 2246/// incoming argument stack. 2247static 2248bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2249 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2250 const X86InstrInfo *TII) { 2251 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2252 int FI = INT_MAX; 2253 if (Arg.getOpcode() == ISD::CopyFromReg) { 2254 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2255 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2256 return false; 2257 MachineInstr *Def = MRI->getVRegDef(VR); 2258 if (!Def) 2259 return false; 2260 if (!Flags.isByVal()) { 2261 if (!TII->isLoadFromStackSlot(Def, FI)) 2262 return false; 2263 } else { 2264 unsigned Opcode = Def->getOpcode(); 2265 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2266 Def->getOperand(1).isFI()) { 2267 FI = Def->getOperand(1).getIndex(); 2268 Bytes = Flags.getByValSize(); 2269 } else 2270 return false; 2271 } 2272 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2273 if (Flags.isByVal()) 2274 // ByVal argument is passed in as a pointer but it's now being 2275 // dereferenced. e.g. 2276 // define @foo(%struct.X* %A) { 2277 // tail call @bar(%struct.X* byval %A) 2278 // } 2279 return false; 2280 SDValue Ptr = Ld->getBasePtr(); 2281 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2282 if (!FINode) 2283 return false; 2284 FI = FINode->getIndex(); 2285 } else 2286 return false; 2287 2288 assert(FI != INT_MAX); 2289 if (!MFI->isFixedObjectIndex(FI)) 2290 return false; 2291 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2292} 2293 2294/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2295/// for tail call optimization. Targets which want to do tail call 2296/// optimization should implement this function. 2297bool 2298X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2299 CallingConv::ID CalleeCC, 2300 bool isVarArg, 2301 bool isCalleeStructRet, 2302 bool isCallerStructRet, 2303 const SmallVectorImpl<ISD::OutputArg> &Outs, 2304 const SmallVectorImpl<ISD::InputArg> &Ins, 2305 SelectionDAG& DAG) const { 2306 if (!IsTailCallConvention(CalleeCC) && 2307 CalleeCC != CallingConv::C) 2308 return false; 2309 2310 // If -tailcallopt is specified, make fastcc functions tail-callable. 2311 const MachineFunction &MF = DAG.getMachineFunction(); 2312 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2313 if (GuaranteedTailCallOpt) { 2314 if (IsTailCallConvention(CalleeCC) && 2315 CallerF->getCallingConv() == CalleeCC) 2316 return true; 2317 return false; 2318 } 2319 2320 // Look for obvious safe cases to perform tail call optimization that does not 2321 // requite ABI changes. This is what gcc calls sibcall. 2322 2323 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2324 // emit a special epilogue. 2325 if (RegInfo->needsStackRealignment(MF)) 2326 return false; 2327 2328 // Do not sibcall optimize vararg calls unless the call site is not passing any 2329 // arguments. 2330 if (isVarArg && !Outs.empty()) 2331 return false; 2332 2333 // Also avoid sibcall optimization if either caller or callee uses struct 2334 // return semantics. 2335 if (isCalleeStructRet || isCallerStructRet) 2336 return false; 2337 2338 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2339 // Therefore if it's not used by the call it is not safe to optimize this into 2340 // a sibcall. 2341 bool Unused = false; 2342 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2343 if (!Ins[i].Used) { 2344 Unused = true; 2345 break; 2346 } 2347 } 2348 if (Unused) { 2349 SmallVector<CCValAssign, 16> RVLocs; 2350 CCState CCInfo(CalleeCC, false, getTargetMachine(), 2351 RVLocs, *DAG.getContext()); 2352 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2353 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2354 CCValAssign &VA = RVLocs[i]; 2355 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2356 return false; 2357 } 2358 } 2359 2360 // If the callee takes no arguments then go on to check the results of the 2361 // call. 2362 if (!Outs.empty()) { 2363 // Check if stack adjustment is needed. For now, do not do this if any 2364 // argument is passed on the stack. 2365 SmallVector<CCValAssign, 16> ArgLocs; 2366 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2367 ArgLocs, *DAG.getContext()); 2368 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2369 if (CCInfo.getNextStackOffset()) { 2370 MachineFunction &MF = DAG.getMachineFunction(); 2371 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2372 return false; 2373 if (Subtarget->isTargetWin64()) 2374 // Win64 ABI has additional complications. 2375 return false; 2376 2377 // Check if the arguments are already laid out in the right way as 2378 // the caller's fixed stack objects. 2379 MachineFrameInfo *MFI = MF.getFrameInfo(); 2380 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2381 const X86InstrInfo *TII = 2382 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2383 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2384 CCValAssign &VA = ArgLocs[i]; 2385 EVT RegVT = VA.getLocVT(); 2386 SDValue Arg = Outs[i].Val; 2387 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2388 if (VA.getLocInfo() == CCValAssign::Indirect) 2389 return false; 2390 if (!VA.isRegLoc()) { 2391 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2392 MFI, MRI, TII)) 2393 return false; 2394 } 2395 } 2396 } 2397 } 2398 2399 return true; 2400} 2401 2402FastISel * 2403X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, 2404 DwarfWriter *dw, 2405 DenseMap<const Value *, unsigned> &vm, 2406 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm, 2407 DenseMap<const AllocaInst *, int> &am 2408#ifndef NDEBUG 2409 , SmallSet<Instruction*, 8> &cil 2410#endif 2411 ) { 2412 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2413#ifndef NDEBUG 2414 , cil 2415#endif 2416 ); 2417} 2418 2419 2420//===----------------------------------------------------------------------===// 2421// Other Lowering Hooks 2422//===----------------------------------------------------------------------===// 2423 2424 2425SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2426 MachineFunction &MF = DAG.getMachineFunction(); 2427 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2428 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2429 2430 if (ReturnAddrIndex == 0) { 2431 // Set up a frame object for the return address. 2432 uint64_t SlotSize = TD->getPointerSize(); 2433 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2434 false, false); 2435 FuncInfo->setRAIndex(ReturnAddrIndex); 2436 } 2437 2438 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2439} 2440 2441 2442bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2443 bool hasSymbolicDisplacement) { 2444 // Offset should fit into 32 bit immediate field. 2445 if (!isInt<32>(Offset)) 2446 return false; 2447 2448 // If we don't have a symbolic displacement - we don't have any extra 2449 // restrictions. 2450 if (!hasSymbolicDisplacement) 2451 return true; 2452 2453 // FIXME: Some tweaks might be needed for medium code model. 2454 if (M != CodeModel::Small && M != CodeModel::Kernel) 2455 return false; 2456 2457 // For small code model we assume that latest object is 16MB before end of 31 2458 // bits boundary. We may also accept pretty large negative constants knowing 2459 // that all objects are in the positive half of address space. 2460 if (M == CodeModel::Small && Offset < 16*1024*1024) 2461 return true; 2462 2463 // For kernel code model we know that all object resist in the negative half 2464 // of 32bits address space. We may not accept negative offsets, since they may 2465 // be just off and we may accept pretty large positive ones. 2466 if (M == CodeModel::Kernel && Offset > 0) 2467 return true; 2468 2469 return false; 2470} 2471 2472/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2473/// specific condition code, returning the condition code and the LHS/RHS of the 2474/// comparison to make. 2475static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2476 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2477 if (!isFP) { 2478 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2479 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2480 // X > -1 -> X == 0, jump !sign. 2481 RHS = DAG.getConstant(0, RHS.getValueType()); 2482 return X86::COND_NS; 2483 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2484 // X < 0 -> X == 0, jump on sign. 2485 return X86::COND_S; 2486 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2487 // X < 1 -> X <= 0 2488 RHS = DAG.getConstant(0, RHS.getValueType()); 2489 return X86::COND_LE; 2490 } 2491 } 2492 2493 switch (SetCCOpcode) { 2494 default: llvm_unreachable("Invalid integer condition!"); 2495 case ISD::SETEQ: return X86::COND_E; 2496 case ISD::SETGT: return X86::COND_G; 2497 case ISD::SETGE: return X86::COND_GE; 2498 case ISD::SETLT: return X86::COND_L; 2499 case ISD::SETLE: return X86::COND_LE; 2500 case ISD::SETNE: return X86::COND_NE; 2501 case ISD::SETULT: return X86::COND_B; 2502 case ISD::SETUGT: return X86::COND_A; 2503 case ISD::SETULE: return X86::COND_BE; 2504 case ISD::SETUGE: return X86::COND_AE; 2505 } 2506 } 2507 2508 // First determine if it is required or is profitable to flip the operands. 2509 2510 // If LHS is a foldable load, but RHS is not, flip the condition. 2511 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2512 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2513 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2514 std::swap(LHS, RHS); 2515 } 2516 2517 switch (SetCCOpcode) { 2518 default: break; 2519 case ISD::SETOLT: 2520 case ISD::SETOLE: 2521 case ISD::SETUGT: 2522 case ISD::SETUGE: 2523 std::swap(LHS, RHS); 2524 break; 2525 } 2526 2527 // On a floating point condition, the flags are set as follows: 2528 // ZF PF CF op 2529 // 0 | 0 | 0 | X > Y 2530 // 0 | 0 | 1 | X < Y 2531 // 1 | 0 | 0 | X == Y 2532 // 1 | 1 | 1 | unordered 2533 switch (SetCCOpcode) { 2534 default: llvm_unreachable("Condcode should be pre-legalized away"); 2535 case ISD::SETUEQ: 2536 case ISD::SETEQ: return X86::COND_E; 2537 case ISD::SETOLT: // flipped 2538 case ISD::SETOGT: 2539 case ISD::SETGT: return X86::COND_A; 2540 case ISD::SETOLE: // flipped 2541 case ISD::SETOGE: 2542 case ISD::SETGE: return X86::COND_AE; 2543 case ISD::SETUGT: // flipped 2544 case ISD::SETULT: 2545 case ISD::SETLT: return X86::COND_B; 2546 case ISD::SETUGE: // flipped 2547 case ISD::SETULE: 2548 case ISD::SETLE: return X86::COND_BE; 2549 case ISD::SETONE: 2550 case ISD::SETNE: return X86::COND_NE; 2551 case ISD::SETUO: return X86::COND_P; 2552 case ISD::SETO: return X86::COND_NP; 2553 case ISD::SETOEQ: 2554 case ISD::SETUNE: return X86::COND_INVALID; 2555 } 2556} 2557 2558/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2559/// code. Current x86 isa includes the following FP cmov instructions: 2560/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2561static bool hasFPCMov(unsigned X86CC) { 2562 switch (X86CC) { 2563 default: 2564 return false; 2565 case X86::COND_B: 2566 case X86::COND_BE: 2567 case X86::COND_E: 2568 case X86::COND_P: 2569 case X86::COND_A: 2570 case X86::COND_AE: 2571 case X86::COND_NE: 2572 case X86::COND_NP: 2573 return true; 2574 } 2575} 2576 2577/// isFPImmLegal - Returns true if the target can instruction select the 2578/// specified FP immediate natively. If false, the legalizer will 2579/// materialize the FP immediate as a load from a constant pool. 2580bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2581 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2582 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2583 return true; 2584 } 2585 return false; 2586} 2587 2588/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2589/// the specified range (L, H]. 2590static bool isUndefOrInRange(int Val, int Low, int Hi) { 2591 return (Val < 0) || (Val >= Low && Val < Hi); 2592} 2593 2594/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2595/// specified value. 2596static bool isUndefOrEqual(int Val, int CmpVal) { 2597 if (Val < 0 || Val == CmpVal) 2598 return true; 2599 return false; 2600} 2601 2602/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2603/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2604/// the second operand. 2605static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2606 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2607 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2608 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2609 return (Mask[0] < 2 && Mask[1] < 2); 2610 return false; 2611} 2612 2613bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2614 SmallVector<int, 8> M; 2615 N->getMask(M); 2616 return ::isPSHUFDMask(M, N->getValueType(0)); 2617} 2618 2619/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2620/// is suitable for input to PSHUFHW. 2621static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2622 if (VT != MVT::v8i16) 2623 return false; 2624 2625 // Lower quadword copied in order or undef. 2626 for (int i = 0; i != 4; ++i) 2627 if (Mask[i] >= 0 && Mask[i] != i) 2628 return false; 2629 2630 // Upper quadword shuffled. 2631 for (int i = 4; i != 8; ++i) 2632 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2633 return false; 2634 2635 return true; 2636} 2637 2638bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2639 SmallVector<int, 8> M; 2640 N->getMask(M); 2641 return ::isPSHUFHWMask(M, N->getValueType(0)); 2642} 2643 2644/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2645/// is suitable for input to PSHUFLW. 2646static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2647 if (VT != MVT::v8i16) 2648 return false; 2649 2650 // Upper quadword copied in order. 2651 for (int i = 4; i != 8; ++i) 2652 if (Mask[i] >= 0 && Mask[i] != i) 2653 return false; 2654 2655 // Lower quadword shuffled. 2656 for (int i = 0; i != 4; ++i) 2657 if (Mask[i] >= 4) 2658 return false; 2659 2660 return true; 2661} 2662 2663bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2664 SmallVector<int, 8> M; 2665 N->getMask(M); 2666 return ::isPSHUFLWMask(M, N->getValueType(0)); 2667} 2668 2669/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2670/// is suitable for input to PALIGNR. 2671static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2672 bool hasSSSE3) { 2673 int i, e = VT.getVectorNumElements(); 2674 2675 // Do not handle v2i64 / v2f64 shuffles with palignr. 2676 if (e < 4 || !hasSSSE3) 2677 return false; 2678 2679 for (i = 0; i != e; ++i) 2680 if (Mask[i] >= 0) 2681 break; 2682 2683 // All undef, not a palignr. 2684 if (i == e) 2685 return false; 2686 2687 // Determine if it's ok to perform a palignr with only the LHS, since we 2688 // don't have access to the actual shuffle elements to see if RHS is undef. 2689 bool Unary = Mask[i] < (int)e; 2690 bool NeedsUnary = false; 2691 2692 int s = Mask[i] - i; 2693 2694 // Check the rest of the elements to see if they are consecutive. 2695 for (++i; i != e; ++i) { 2696 int m = Mask[i]; 2697 if (m < 0) 2698 continue; 2699 2700 Unary = Unary && (m < (int)e); 2701 NeedsUnary = NeedsUnary || (m < s); 2702 2703 if (NeedsUnary && !Unary) 2704 return false; 2705 if (Unary && m != ((s+i) & (e-1))) 2706 return false; 2707 if (!Unary && m != (s+i)) 2708 return false; 2709 } 2710 return true; 2711} 2712 2713bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2714 SmallVector<int, 8> M; 2715 N->getMask(M); 2716 return ::isPALIGNRMask(M, N->getValueType(0), true); 2717} 2718 2719/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2720/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2721static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2722 int NumElems = VT.getVectorNumElements(); 2723 if (NumElems != 2 && NumElems != 4) 2724 return false; 2725 2726 int Half = NumElems / 2; 2727 for (int i = 0; i < Half; ++i) 2728 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2729 return false; 2730 for (int i = Half; i < NumElems; ++i) 2731 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2732 return false; 2733 2734 return true; 2735} 2736 2737bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2738 SmallVector<int, 8> M; 2739 N->getMask(M); 2740 return ::isSHUFPMask(M, N->getValueType(0)); 2741} 2742 2743/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2744/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2745/// half elements to come from vector 1 (which would equal the dest.) and 2746/// the upper half to come from vector 2. 2747static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2748 int NumElems = VT.getVectorNumElements(); 2749 2750 if (NumElems != 2 && NumElems != 4) 2751 return false; 2752 2753 int Half = NumElems / 2; 2754 for (int i = 0; i < Half; ++i) 2755 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2756 return false; 2757 for (int i = Half; i < NumElems; ++i) 2758 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2759 return false; 2760 return true; 2761} 2762 2763static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2764 SmallVector<int, 8> M; 2765 N->getMask(M); 2766 return isCommutedSHUFPMask(M, N->getValueType(0)); 2767} 2768 2769/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2770/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2771bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2772 if (N->getValueType(0).getVectorNumElements() != 4) 2773 return false; 2774 2775 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2776 return isUndefOrEqual(N->getMaskElt(0), 6) && 2777 isUndefOrEqual(N->getMaskElt(1), 7) && 2778 isUndefOrEqual(N->getMaskElt(2), 2) && 2779 isUndefOrEqual(N->getMaskElt(3), 3); 2780} 2781 2782/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2783/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2784/// <2, 3, 2, 3> 2785bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2786 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2787 2788 if (NumElems != 4) 2789 return false; 2790 2791 return isUndefOrEqual(N->getMaskElt(0), 2) && 2792 isUndefOrEqual(N->getMaskElt(1), 3) && 2793 isUndefOrEqual(N->getMaskElt(2), 2) && 2794 isUndefOrEqual(N->getMaskElt(3), 3); 2795} 2796 2797/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2798/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2799bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2800 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2801 2802 if (NumElems != 2 && NumElems != 4) 2803 return false; 2804 2805 for (unsigned i = 0; i < NumElems/2; ++i) 2806 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2807 return false; 2808 2809 for (unsigned i = NumElems/2; i < NumElems; ++i) 2810 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2811 return false; 2812 2813 return true; 2814} 2815 2816/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 2817/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 2818bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 2819 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2820 2821 if (NumElems != 2 && NumElems != 4) 2822 return false; 2823 2824 for (unsigned i = 0; i < NumElems/2; ++i) 2825 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2826 return false; 2827 2828 for (unsigned i = 0; i < NumElems/2; ++i) 2829 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2830 return false; 2831 2832 return true; 2833} 2834 2835/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2836/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2837static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2838 bool V2IsSplat = false) { 2839 int NumElts = VT.getVectorNumElements(); 2840 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2841 return false; 2842 2843 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2844 int BitI = Mask[i]; 2845 int BitI1 = Mask[i+1]; 2846 if (!isUndefOrEqual(BitI, j)) 2847 return false; 2848 if (V2IsSplat) { 2849 if (!isUndefOrEqual(BitI1, NumElts)) 2850 return false; 2851 } else { 2852 if (!isUndefOrEqual(BitI1, j + NumElts)) 2853 return false; 2854 } 2855 } 2856 return true; 2857} 2858 2859bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2860 SmallVector<int, 8> M; 2861 N->getMask(M); 2862 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2863} 2864 2865/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2866/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2867static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2868 bool V2IsSplat = false) { 2869 int NumElts = VT.getVectorNumElements(); 2870 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2871 return false; 2872 2873 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2874 int BitI = Mask[i]; 2875 int BitI1 = Mask[i+1]; 2876 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2877 return false; 2878 if (V2IsSplat) { 2879 if (isUndefOrEqual(BitI1, NumElts)) 2880 return false; 2881 } else { 2882 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2883 return false; 2884 } 2885 } 2886 return true; 2887} 2888 2889bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2890 SmallVector<int, 8> M; 2891 N->getMask(M); 2892 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2893} 2894 2895/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2896/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2897/// <0, 0, 1, 1> 2898static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2899 int NumElems = VT.getVectorNumElements(); 2900 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2901 return false; 2902 2903 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2904 int BitI = Mask[i]; 2905 int BitI1 = Mask[i+1]; 2906 if (!isUndefOrEqual(BitI, j)) 2907 return false; 2908 if (!isUndefOrEqual(BitI1, j)) 2909 return false; 2910 } 2911 return true; 2912} 2913 2914bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2915 SmallVector<int, 8> M; 2916 N->getMask(M); 2917 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2918} 2919 2920/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2921/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2922/// <2, 2, 3, 3> 2923static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2924 int NumElems = VT.getVectorNumElements(); 2925 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2926 return false; 2927 2928 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2929 int BitI = Mask[i]; 2930 int BitI1 = Mask[i+1]; 2931 if (!isUndefOrEqual(BitI, j)) 2932 return false; 2933 if (!isUndefOrEqual(BitI1, j)) 2934 return false; 2935 } 2936 return true; 2937} 2938 2939bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2940 SmallVector<int, 8> M; 2941 N->getMask(M); 2942 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2943} 2944 2945/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2946/// specifies a shuffle of elements that is suitable for input to MOVSS, 2947/// MOVSD, and MOVD, i.e. setting the lowest element. 2948static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2949 if (VT.getVectorElementType().getSizeInBits() < 32) 2950 return false; 2951 2952 int NumElts = VT.getVectorNumElements(); 2953 2954 if (!isUndefOrEqual(Mask[0], NumElts)) 2955 return false; 2956 2957 for (int i = 1; i < NumElts; ++i) 2958 if (!isUndefOrEqual(Mask[i], i)) 2959 return false; 2960 2961 return true; 2962} 2963 2964bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2965 SmallVector<int, 8> M; 2966 N->getMask(M); 2967 return ::isMOVLMask(M, N->getValueType(0)); 2968} 2969 2970/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2971/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2972/// element of vector 2 and the other elements to come from vector 1 in order. 2973static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2974 bool V2IsSplat = false, bool V2IsUndef = false) { 2975 int NumOps = VT.getVectorNumElements(); 2976 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2977 return false; 2978 2979 if (!isUndefOrEqual(Mask[0], 0)) 2980 return false; 2981 2982 for (int i = 1; i < NumOps; ++i) 2983 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2984 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2985 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2986 return false; 2987 2988 return true; 2989} 2990 2991static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2992 bool V2IsUndef = false) { 2993 SmallVector<int, 8> M; 2994 N->getMask(M); 2995 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2996} 2997 2998/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2999/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3000bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 3001 if (N->getValueType(0).getVectorNumElements() != 4) 3002 return false; 3003 3004 // Expect 1, 1, 3, 3 3005 for (unsigned i = 0; i < 2; ++i) { 3006 int Elt = N->getMaskElt(i); 3007 if (Elt >= 0 && Elt != 1) 3008 return false; 3009 } 3010 3011 bool HasHi = false; 3012 for (unsigned i = 2; i < 4; ++i) { 3013 int Elt = N->getMaskElt(i); 3014 if (Elt >= 0 && Elt != 3) 3015 return false; 3016 if (Elt == 3) 3017 HasHi = true; 3018 } 3019 // Don't use movshdup if it can be done with a shufps. 3020 // FIXME: verify that matching u, u, 3, 3 is what we want. 3021 return HasHi; 3022} 3023 3024/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3025/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3026bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 3027 if (N->getValueType(0).getVectorNumElements() != 4) 3028 return false; 3029 3030 // Expect 0, 0, 2, 2 3031 for (unsigned i = 0; i < 2; ++i) 3032 if (N->getMaskElt(i) > 0) 3033 return false; 3034 3035 bool HasHi = false; 3036 for (unsigned i = 2; i < 4; ++i) { 3037 int Elt = N->getMaskElt(i); 3038 if (Elt >= 0 && Elt != 2) 3039 return false; 3040 if (Elt == 2) 3041 HasHi = true; 3042 } 3043 // Don't use movsldup if it can be done with a shufps. 3044 return HasHi; 3045} 3046 3047/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3048/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3049bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3050 int e = N->getValueType(0).getVectorNumElements() / 2; 3051 3052 for (int i = 0; i < e; ++i) 3053 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3054 return false; 3055 for (int i = 0; i < e; ++i) 3056 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3057 return false; 3058 return true; 3059} 3060 3061/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3062/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3063unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3064 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3065 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3066 3067 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3068 unsigned Mask = 0; 3069 for (int i = 0; i < NumOperands; ++i) { 3070 int Val = SVOp->getMaskElt(NumOperands-i-1); 3071 if (Val < 0) Val = 0; 3072 if (Val >= NumOperands) Val -= NumOperands; 3073 Mask |= Val; 3074 if (i != NumOperands - 1) 3075 Mask <<= Shift; 3076 } 3077 return Mask; 3078} 3079 3080/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3081/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3082unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3084 unsigned Mask = 0; 3085 // 8 nodes, but we only care about the last 4. 3086 for (unsigned i = 7; i >= 4; --i) { 3087 int Val = SVOp->getMaskElt(i); 3088 if (Val >= 0) 3089 Mask |= (Val - 4); 3090 if (i != 4) 3091 Mask <<= 2; 3092 } 3093 return Mask; 3094} 3095 3096/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3097/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3098unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3099 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3100 unsigned Mask = 0; 3101 // 8 nodes, but we only care about the first 4. 3102 for (int i = 3; i >= 0; --i) { 3103 int Val = SVOp->getMaskElt(i); 3104 if (Val >= 0) 3105 Mask |= Val; 3106 if (i != 0) 3107 Mask <<= 2; 3108 } 3109 return Mask; 3110} 3111 3112/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3113/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3114unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3115 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3116 EVT VVT = N->getValueType(0); 3117 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3118 int Val = 0; 3119 3120 unsigned i, e; 3121 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3122 Val = SVOp->getMaskElt(i); 3123 if (Val >= 0) 3124 break; 3125 } 3126 return (Val - i) * EltSize; 3127} 3128 3129/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3130/// constant +0.0. 3131bool X86::isZeroNode(SDValue Elt) { 3132 return ((isa<ConstantSDNode>(Elt) && 3133 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 3134 (isa<ConstantFPSDNode>(Elt) && 3135 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3136} 3137 3138/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3139/// their permute mask. 3140static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3141 SelectionDAG &DAG) { 3142 EVT VT = SVOp->getValueType(0); 3143 unsigned NumElems = VT.getVectorNumElements(); 3144 SmallVector<int, 8> MaskVec; 3145 3146 for (unsigned i = 0; i != NumElems; ++i) { 3147 int idx = SVOp->getMaskElt(i); 3148 if (idx < 0) 3149 MaskVec.push_back(idx); 3150 else if (idx < (int)NumElems) 3151 MaskVec.push_back(idx + NumElems); 3152 else 3153 MaskVec.push_back(idx - NumElems); 3154 } 3155 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3156 SVOp->getOperand(0), &MaskVec[0]); 3157} 3158 3159/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3160/// the two vector operands have swapped position. 3161static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3162 unsigned NumElems = VT.getVectorNumElements(); 3163 for (unsigned i = 0; i != NumElems; ++i) { 3164 int idx = Mask[i]; 3165 if (idx < 0) 3166 continue; 3167 else if (idx < (int)NumElems) 3168 Mask[i] = idx + NumElems; 3169 else 3170 Mask[i] = idx - NumElems; 3171 } 3172} 3173 3174/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3175/// match movhlps. The lower half elements should come from upper half of 3176/// V1 (and in order), and the upper half elements should come from the upper 3177/// half of V2 (and in order). 3178static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3179 if (Op->getValueType(0).getVectorNumElements() != 4) 3180 return false; 3181 for (unsigned i = 0, e = 2; i != e; ++i) 3182 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3183 return false; 3184 for (unsigned i = 2; i != 4; ++i) 3185 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3186 return false; 3187 return true; 3188} 3189 3190/// isScalarLoadToVector - Returns true if the node is a scalar load that 3191/// is promoted to a vector. It also returns the LoadSDNode by reference if 3192/// required. 3193static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3194 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3195 return false; 3196 N = N->getOperand(0).getNode(); 3197 if (!ISD::isNON_EXTLoad(N)) 3198 return false; 3199 if (LD) 3200 *LD = cast<LoadSDNode>(N); 3201 return true; 3202} 3203 3204/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3205/// match movlp{s|d}. The lower half elements should come from lower half of 3206/// V1 (and in order), and the upper half elements should come from the upper 3207/// half of V2 (and in order). And since V1 will become the source of the 3208/// MOVLP, it must be either a vector load or a scalar load to vector. 3209static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3210 ShuffleVectorSDNode *Op) { 3211 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3212 return false; 3213 // Is V2 is a vector load, don't do this transformation. We will try to use 3214 // load folding shufps op. 3215 if (ISD::isNON_EXTLoad(V2)) 3216 return false; 3217 3218 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3219 3220 if (NumElems != 2 && NumElems != 4) 3221 return false; 3222 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3223 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3224 return false; 3225 for (unsigned i = NumElems/2; i != NumElems; ++i) 3226 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3227 return false; 3228 return true; 3229} 3230 3231/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3232/// all the same. 3233static bool isSplatVector(SDNode *N) { 3234 if (N->getOpcode() != ISD::BUILD_VECTOR) 3235 return false; 3236 3237 SDValue SplatValue = N->getOperand(0); 3238 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3239 if (N->getOperand(i) != SplatValue) 3240 return false; 3241 return true; 3242} 3243 3244/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3245/// to an zero vector. 3246/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3247static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3248 SDValue V1 = N->getOperand(0); 3249 SDValue V2 = N->getOperand(1); 3250 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3251 for (unsigned i = 0; i != NumElems; ++i) { 3252 int Idx = N->getMaskElt(i); 3253 if (Idx >= (int)NumElems) { 3254 unsigned Opc = V2.getOpcode(); 3255 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3256 continue; 3257 if (Opc != ISD::BUILD_VECTOR || 3258 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3259 return false; 3260 } else if (Idx >= 0) { 3261 unsigned Opc = V1.getOpcode(); 3262 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3263 continue; 3264 if (Opc != ISD::BUILD_VECTOR || 3265 !X86::isZeroNode(V1.getOperand(Idx))) 3266 return false; 3267 } 3268 } 3269 return true; 3270} 3271 3272/// getZeroVector - Returns a vector of specified type with all zero elements. 3273/// 3274static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3275 DebugLoc dl) { 3276 assert(VT.isVector() && "Expected a vector type"); 3277 3278 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3279 // type. This ensures they get CSE'd. 3280 SDValue Vec; 3281 if (VT.getSizeInBits() == 64) { // MMX 3282 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3283 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3284 } else if (HasSSE2) { // SSE2 3285 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3286 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3287 } else { // SSE1 3288 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3289 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3290 } 3291 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3292} 3293 3294/// getOnesVector - Returns a vector of specified type with all bits set. 3295/// 3296static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3297 assert(VT.isVector() && "Expected a vector type"); 3298 3299 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3300 // type. This ensures they get CSE'd. 3301 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3302 SDValue Vec; 3303 if (VT.getSizeInBits() == 64) // MMX 3304 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3305 else // SSE 3306 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3307 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3308} 3309 3310 3311/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3312/// that point to V2 points to its first element. 3313static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3314 EVT VT = SVOp->getValueType(0); 3315 unsigned NumElems = VT.getVectorNumElements(); 3316 3317 bool Changed = false; 3318 SmallVector<int, 8> MaskVec; 3319 SVOp->getMask(MaskVec); 3320 3321 for (unsigned i = 0; i != NumElems; ++i) { 3322 if (MaskVec[i] > (int)NumElems) { 3323 MaskVec[i] = NumElems; 3324 Changed = true; 3325 } 3326 } 3327 if (Changed) 3328 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3329 SVOp->getOperand(1), &MaskVec[0]); 3330 return SDValue(SVOp, 0); 3331} 3332 3333/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3334/// operation of specified width. 3335static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3336 SDValue V2) { 3337 unsigned NumElems = VT.getVectorNumElements(); 3338 SmallVector<int, 8> Mask; 3339 Mask.push_back(NumElems); 3340 for (unsigned i = 1; i != NumElems; ++i) 3341 Mask.push_back(i); 3342 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3343} 3344 3345/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3346static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3347 SDValue V2) { 3348 unsigned NumElems = VT.getVectorNumElements(); 3349 SmallVector<int, 8> Mask; 3350 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3351 Mask.push_back(i); 3352 Mask.push_back(i + NumElems); 3353 } 3354 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3355} 3356 3357/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3358static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3359 SDValue V2) { 3360 unsigned NumElems = VT.getVectorNumElements(); 3361 unsigned Half = NumElems/2; 3362 SmallVector<int, 8> Mask; 3363 for (unsigned i = 0; i != Half; ++i) { 3364 Mask.push_back(i + Half); 3365 Mask.push_back(i + NumElems + Half); 3366 } 3367 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3368} 3369 3370/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3371static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3372 bool HasSSE2) { 3373 if (SV->getValueType(0).getVectorNumElements() <= 4) 3374 return SDValue(SV, 0); 3375 3376 EVT PVT = MVT::v4f32; 3377 EVT VT = SV->getValueType(0); 3378 DebugLoc dl = SV->getDebugLoc(); 3379 SDValue V1 = SV->getOperand(0); 3380 int NumElems = VT.getVectorNumElements(); 3381 int EltNo = SV->getSplatIndex(); 3382 3383 // unpack elements to the correct location 3384 while (NumElems > 4) { 3385 if (EltNo < NumElems/2) { 3386 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3387 } else { 3388 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3389 EltNo -= NumElems/2; 3390 } 3391 NumElems >>= 1; 3392 } 3393 3394 // Perform the splat. 3395 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3396 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3397 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3398 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3399} 3400 3401/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3402/// vector of zero or undef vector. This produces a shuffle where the low 3403/// element of V2 is swizzled into the zero/undef vector, landing at element 3404/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3405static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3406 bool isZero, bool HasSSE2, 3407 SelectionDAG &DAG) { 3408 EVT VT = V2.getValueType(); 3409 SDValue V1 = isZero 3410 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3411 unsigned NumElems = VT.getVectorNumElements(); 3412 SmallVector<int, 16> MaskVec; 3413 for (unsigned i = 0; i != NumElems; ++i) 3414 // If this is the insertion idx, put the low elt of V2 here. 3415 MaskVec.push_back(i == Idx ? NumElems : i); 3416 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3417} 3418 3419/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3420/// a shuffle that is zero. 3421static 3422unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3423 bool Low, SelectionDAG &DAG) { 3424 unsigned NumZeros = 0; 3425 for (int i = 0; i < NumElems; ++i) { 3426 unsigned Index = Low ? i : NumElems-i-1; 3427 int Idx = SVOp->getMaskElt(Index); 3428 if (Idx < 0) { 3429 ++NumZeros; 3430 continue; 3431 } 3432 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3433 if (Elt.getNode() && X86::isZeroNode(Elt)) 3434 ++NumZeros; 3435 else 3436 break; 3437 } 3438 return NumZeros; 3439} 3440 3441/// isVectorShift - Returns true if the shuffle can be implemented as a 3442/// logical left or right shift of a vector. 3443/// FIXME: split into pslldqi, psrldqi, palignr variants. 3444static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3445 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3446 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3447 3448 isLeft = true; 3449 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3450 if (!NumZeros) { 3451 isLeft = false; 3452 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3453 if (!NumZeros) 3454 return false; 3455 } 3456 bool SeenV1 = false; 3457 bool SeenV2 = false; 3458 for (int i = NumZeros; i < NumElems; ++i) { 3459 int Val = isLeft ? (i - NumZeros) : i; 3460 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3461 if (Idx < 0) 3462 continue; 3463 if (Idx < NumElems) 3464 SeenV1 = true; 3465 else { 3466 Idx -= NumElems; 3467 SeenV2 = true; 3468 } 3469 if (Idx != Val) 3470 return false; 3471 } 3472 if (SeenV1 && SeenV2) 3473 return false; 3474 3475 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3476 ShAmt = NumZeros; 3477 return true; 3478} 3479 3480 3481/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3482/// 3483static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3484 unsigned NumNonZero, unsigned NumZero, 3485 SelectionDAG &DAG, TargetLowering &TLI) { 3486 if (NumNonZero > 8) 3487 return SDValue(); 3488 3489 DebugLoc dl = Op.getDebugLoc(); 3490 SDValue V(0, 0); 3491 bool First = true; 3492 for (unsigned i = 0; i < 16; ++i) { 3493 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3494 if (ThisIsNonZero && First) { 3495 if (NumZero) 3496 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3497 else 3498 V = DAG.getUNDEF(MVT::v8i16); 3499 First = false; 3500 } 3501 3502 if ((i & 1) != 0) { 3503 SDValue ThisElt(0, 0), LastElt(0, 0); 3504 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3505 if (LastIsNonZero) { 3506 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3507 MVT::i16, Op.getOperand(i-1)); 3508 } 3509 if (ThisIsNonZero) { 3510 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3511 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3512 ThisElt, DAG.getConstant(8, MVT::i8)); 3513 if (LastIsNonZero) 3514 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3515 } else 3516 ThisElt = LastElt; 3517 3518 if (ThisElt.getNode()) 3519 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3520 DAG.getIntPtrConstant(i/2)); 3521 } 3522 } 3523 3524 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3525} 3526 3527/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3528/// 3529static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3530 unsigned NumNonZero, unsigned NumZero, 3531 SelectionDAG &DAG, TargetLowering &TLI) { 3532 if (NumNonZero > 4) 3533 return SDValue(); 3534 3535 DebugLoc dl = Op.getDebugLoc(); 3536 SDValue V(0, 0); 3537 bool First = true; 3538 for (unsigned i = 0; i < 8; ++i) { 3539 bool isNonZero = (NonZeros & (1 << i)) != 0; 3540 if (isNonZero) { 3541 if (First) { 3542 if (NumZero) 3543 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3544 else 3545 V = DAG.getUNDEF(MVT::v8i16); 3546 First = false; 3547 } 3548 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3549 MVT::v8i16, V, Op.getOperand(i), 3550 DAG.getIntPtrConstant(i)); 3551 } 3552 } 3553 3554 return V; 3555} 3556 3557/// getVShift - Return a vector logical shift node. 3558/// 3559static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3560 unsigned NumBits, SelectionDAG &DAG, 3561 const TargetLowering &TLI, DebugLoc dl) { 3562 bool isMMX = VT.getSizeInBits() == 64; 3563 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3564 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3565 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3566 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3567 DAG.getNode(Opc, dl, ShVT, SrcOp, 3568 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3569} 3570 3571SDValue 3572X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3573 SelectionDAG &DAG) { 3574 3575 // Check if the scalar load can be widened into a vector load. And if 3576 // the address is "base + cst" see if the cst can be "absorbed" into 3577 // the shuffle mask. 3578 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3579 SDValue Ptr = LD->getBasePtr(); 3580 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3581 return SDValue(); 3582 EVT PVT = LD->getValueType(0); 3583 if (PVT != MVT::i32 && PVT != MVT::f32) 3584 return SDValue(); 3585 3586 int FI = -1; 3587 int64_t Offset = 0; 3588 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3589 FI = FINode->getIndex(); 3590 Offset = 0; 3591 } else if (Ptr.getOpcode() == ISD::ADD && 3592 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3593 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3594 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3595 Offset = Ptr.getConstantOperandVal(1); 3596 Ptr = Ptr.getOperand(0); 3597 } else { 3598 return SDValue(); 3599 } 3600 3601 SDValue Chain = LD->getChain(); 3602 // Make sure the stack object alignment is at least 16. 3603 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3604 if (DAG.InferPtrAlignment(Ptr) < 16) { 3605 if (MFI->isFixedObjectIndex(FI)) { 3606 // Can't change the alignment. FIXME: It's possible to compute 3607 // the exact stack offset and reference FI + adjust offset instead. 3608 // If someone *really* cares about this. That's the way to implement it. 3609 return SDValue(); 3610 } else { 3611 MFI->setObjectAlignment(FI, 16); 3612 } 3613 } 3614 3615 // (Offset % 16) must be multiple of 4. Then address is then 3616 // Ptr + (Offset & ~15). 3617 if (Offset < 0) 3618 return SDValue(); 3619 if ((Offset % 16) & 3) 3620 return SDValue(); 3621 int64_t StartOffset = Offset & ~15; 3622 if (StartOffset) 3623 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3624 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3625 3626 int EltNo = (Offset - StartOffset) >> 2; 3627 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3628 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3629 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3630 false, false, 0); 3631 // Canonicalize it to a v4i32 shuffle. 3632 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3633 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3634 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3635 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3636 } 3637 3638 return SDValue(); 3639} 3640 3641/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 3642/// vector of type 'VT', see if the elements can be replaced by a single large 3643/// load which has the same value as a build_vector whose operands are 'elts'. 3644/// 3645/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 3646/// 3647/// FIXME: we'd also like to handle the case where the last elements are zero 3648/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 3649/// There's even a handy isZeroNode for that purpose. 3650static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 3651 DebugLoc &dl, SelectionDAG &DAG) { 3652 EVT EltVT = VT.getVectorElementType(); 3653 unsigned NumElems = Elts.size(); 3654 3655 LoadSDNode *LDBase = NULL; 3656 unsigned LastLoadedElt = -1U; 3657 3658 // For each element in the initializer, see if we've found a load or an undef. 3659 // If we don't find an initial load element, or later load elements are 3660 // non-consecutive, bail out. 3661 for (unsigned i = 0; i < NumElems; ++i) { 3662 SDValue Elt = Elts[i]; 3663 3664 if (!Elt.getNode() || 3665 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 3666 return SDValue(); 3667 if (!LDBase) { 3668 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 3669 return SDValue(); 3670 LDBase = cast<LoadSDNode>(Elt.getNode()); 3671 LastLoadedElt = i; 3672 continue; 3673 } 3674 if (Elt.getOpcode() == ISD::UNDEF) 3675 continue; 3676 3677 LoadSDNode *LD = cast<LoadSDNode>(Elt); 3678 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 3679 return SDValue(); 3680 LastLoadedElt = i; 3681 } 3682 3683 // If we have found an entire vector of loads and undefs, then return a large 3684 // load of the entire vector width starting at the base pointer. If we found 3685 // consecutive loads for the low half, generate a vzext_load node. 3686 if (LastLoadedElt == NumElems - 1) { 3687 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 3688 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 3689 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 3690 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 3691 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(), 3692 LDBase->getSrcValue(), LDBase->getSrcValueOffset(), 3693 LDBase->isVolatile(), LDBase->isNonTemporal(), 3694 LDBase->getAlignment()); 3695 } else if (NumElems == 4 && LastLoadedElt == 1) { 3696 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 3697 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 3698 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 3699 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 3700 } 3701 return SDValue(); 3702} 3703 3704SDValue 3705X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3706 DebugLoc dl = Op.getDebugLoc(); 3707 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3708 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3709 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3710 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3711 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3712 // eliminated on x86-32 hosts. 3713 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3714 return Op; 3715 3716 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3717 return getOnesVector(Op.getValueType(), DAG, dl); 3718 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3719 } 3720 3721 EVT VT = Op.getValueType(); 3722 EVT ExtVT = VT.getVectorElementType(); 3723 unsigned EVTBits = ExtVT.getSizeInBits(); 3724 3725 unsigned NumElems = Op.getNumOperands(); 3726 unsigned NumZero = 0; 3727 unsigned NumNonZero = 0; 3728 unsigned NonZeros = 0; 3729 bool IsAllConstants = true; 3730 SmallSet<SDValue, 8> Values; 3731 for (unsigned i = 0; i < NumElems; ++i) { 3732 SDValue Elt = Op.getOperand(i); 3733 if (Elt.getOpcode() == ISD::UNDEF) 3734 continue; 3735 Values.insert(Elt); 3736 if (Elt.getOpcode() != ISD::Constant && 3737 Elt.getOpcode() != ISD::ConstantFP) 3738 IsAllConstants = false; 3739 if (X86::isZeroNode(Elt)) 3740 NumZero++; 3741 else { 3742 NonZeros |= (1 << i); 3743 NumNonZero++; 3744 } 3745 } 3746 3747 if (NumNonZero == 0) { 3748 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3749 return DAG.getUNDEF(VT); 3750 } 3751 3752 // Special case for single non-zero, non-undef, element. 3753 if (NumNonZero == 1) { 3754 unsigned Idx = CountTrailingZeros_32(NonZeros); 3755 SDValue Item = Op.getOperand(Idx); 3756 3757 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3758 // the value are obviously zero, truncate the value to i32 and do the 3759 // insertion that way. Only do this if the value is non-constant or if the 3760 // value is a constant being inserted into element 0. It is cheaper to do 3761 // a constant pool load than it is to do a movd + shuffle. 3762 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3763 (!IsAllConstants || Idx == 0)) { 3764 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3765 // Handle MMX and SSE both. 3766 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3767 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3768 3769 // Truncate the value (which may itself be a constant) to i32, and 3770 // convert it to a vector with movd (S2V+shuffle to zero extend). 3771 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3772 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3773 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3774 Subtarget->hasSSE2(), DAG); 3775 3776 // Now we have our 32-bit value zero extended in the low element of 3777 // a vector. If Idx != 0, swizzle it into place. 3778 if (Idx != 0) { 3779 SmallVector<int, 4> Mask; 3780 Mask.push_back(Idx); 3781 for (unsigned i = 1; i != VecElts; ++i) 3782 Mask.push_back(i); 3783 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3784 DAG.getUNDEF(Item.getValueType()), 3785 &Mask[0]); 3786 } 3787 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3788 } 3789 } 3790 3791 // If we have a constant or non-constant insertion into the low element of 3792 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3793 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3794 // depending on what the source datatype is. 3795 if (Idx == 0) { 3796 if (NumZero == 0) { 3797 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3798 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3799 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3800 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3801 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3802 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3803 DAG); 3804 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3805 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3806 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3807 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3808 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3809 Subtarget->hasSSE2(), DAG); 3810 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3811 } 3812 } 3813 3814 // Is it a vector logical left shift? 3815 if (NumElems == 2 && Idx == 1 && 3816 X86::isZeroNode(Op.getOperand(0)) && 3817 !X86::isZeroNode(Op.getOperand(1))) { 3818 unsigned NumBits = VT.getSizeInBits(); 3819 return getVShift(true, VT, 3820 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3821 VT, Op.getOperand(1)), 3822 NumBits/2, DAG, *this, dl); 3823 } 3824 3825 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3826 return SDValue(); 3827 3828 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3829 // is a non-constant being inserted into an element other than the low one, 3830 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3831 // movd/movss) to move this into the low element, then shuffle it into 3832 // place. 3833 if (EVTBits == 32) { 3834 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3835 3836 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3837 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3838 Subtarget->hasSSE2(), DAG); 3839 SmallVector<int, 8> MaskVec; 3840 for (unsigned i = 0; i < NumElems; i++) 3841 MaskVec.push_back(i == Idx ? 0 : 1); 3842 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3843 } 3844 } 3845 3846 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3847 if (Values.size() == 1) { 3848 if (EVTBits == 32) { 3849 // Instead of a shuffle like this: 3850 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 3851 // Check if it's possible to issue this instead. 3852 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 3853 unsigned Idx = CountTrailingZeros_32(NonZeros); 3854 SDValue Item = Op.getOperand(Idx); 3855 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 3856 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 3857 } 3858 return SDValue(); 3859 } 3860 3861 // A vector full of immediates; various special cases are already 3862 // handled, so this is best done with a single constant-pool load. 3863 if (IsAllConstants) 3864 return SDValue(); 3865 3866 // Let legalizer expand 2-wide build_vectors. 3867 if (EVTBits == 64) { 3868 if (NumNonZero == 1) { 3869 // One half is zero or undef. 3870 unsigned Idx = CountTrailingZeros_32(NonZeros); 3871 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3872 Op.getOperand(Idx)); 3873 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3874 Subtarget->hasSSE2(), DAG); 3875 } 3876 return SDValue(); 3877 } 3878 3879 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3880 if (EVTBits == 8 && NumElems == 16) { 3881 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3882 *this); 3883 if (V.getNode()) return V; 3884 } 3885 3886 if (EVTBits == 16 && NumElems == 8) { 3887 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3888 *this); 3889 if (V.getNode()) return V; 3890 } 3891 3892 // If element VT is == 32 bits, turn it into a number of shuffles. 3893 SmallVector<SDValue, 8> V; 3894 V.resize(NumElems); 3895 if (NumElems == 4 && NumZero > 0) { 3896 for (unsigned i = 0; i < 4; ++i) { 3897 bool isZero = !(NonZeros & (1 << i)); 3898 if (isZero) 3899 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3900 else 3901 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3902 } 3903 3904 for (unsigned i = 0; i < 2; ++i) { 3905 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3906 default: break; 3907 case 0: 3908 V[i] = V[i*2]; // Must be a zero vector. 3909 break; 3910 case 1: 3911 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3912 break; 3913 case 2: 3914 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3915 break; 3916 case 3: 3917 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3918 break; 3919 } 3920 } 3921 3922 SmallVector<int, 8> MaskVec; 3923 bool Reverse = (NonZeros & 0x3) == 2; 3924 for (unsigned i = 0; i < 2; ++i) 3925 MaskVec.push_back(Reverse ? 1-i : i); 3926 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3927 for (unsigned i = 0; i < 2; ++i) 3928 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3929 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3930 } 3931 3932 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 3933 // Check for a build vector of consecutive loads. 3934 for (unsigned i = 0; i < NumElems; ++i) 3935 V[i] = Op.getOperand(i); 3936 3937 // Check for elements which are consecutive loads. 3938 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 3939 if (LD.getNode()) 3940 return LD; 3941 3942 // For SSE 4.1, use inserts into undef. 3943 if (getSubtarget()->hasSSE41()) { 3944 V[0] = DAG.getUNDEF(VT); 3945 for (unsigned i = 0; i < NumElems; ++i) 3946 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3947 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3948 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3949 return V[0]; 3950 } 3951 3952 // Otherwise, expand into a number of unpckl* 3953 // e.g. for v4f32 3954 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3955 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3956 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3957 for (unsigned i = 0; i < NumElems; ++i) 3958 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3959 NumElems >>= 1; 3960 while (NumElems != 0) { 3961 for (unsigned i = 0; i < NumElems; ++i) 3962 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3963 NumElems >>= 1; 3964 } 3965 return V[0]; 3966 } 3967 return SDValue(); 3968} 3969 3970SDValue 3971X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3972 // We support concatenate two MMX registers and place them in a MMX 3973 // register. This is better than doing a stack convert. 3974 DebugLoc dl = Op.getDebugLoc(); 3975 EVT ResVT = Op.getValueType(); 3976 assert(Op.getNumOperands() == 2); 3977 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 3978 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 3979 int Mask[2]; 3980 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 3981 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3982 InVec = Op.getOperand(1); 3983 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3984 unsigned NumElts = ResVT.getVectorNumElements(); 3985 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3986 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 3987 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 3988 } else { 3989 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 3990 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3991 Mask[0] = 0; Mask[1] = 2; 3992 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 3993 } 3994 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3995} 3996 3997// v8i16 shuffles - Prefer shuffles in the following order: 3998// 1. [all] pshuflw, pshufhw, optional move 3999// 2. [ssse3] 1 x pshufb 4000// 3. [ssse3] 2 x pshufb + 1 x por 4001// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 4002static 4003SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 4004 SelectionDAG &DAG, X86TargetLowering &TLI) { 4005 SDValue V1 = SVOp->getOperand(0); 4006 SDValue V2 = SVOp->getOperand(1); 4007 DebugLoc dl = SVOp->getDebugLoc(); 4008 SmallVector<int, 8> MaskVals; 4009 4010 // Determine if more than 1 of the words in each of the low and high quadwords 4011 // of the result come from the same quadword of one of the two inputs. Undef 4012 // mask values count as coming from any quadword, for better codegen. 4013 SmallVector<unsigned, 4> LoQuad(4); 4014 SmallVector<unsigned, 4> HiQuad(4); 4015 BitVector InputQuads(4); 4016 for (unsigned i = 0; i < 8; ++i) { 4017 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 4018 int EltIdx = SVOp->getMaskElt(i); 4019 MaskVals.push_back(EltIdx); 4020 if (EltIdx < 0) { 4021 ++Quad[0]; 4022 ++Quad[1]; 4023 ++Quad[2]; 4024 ++Quad[3]; 4025 continue; 4026 } 4027 ++Quad[EltIdx / 4]; 4028 InputQuads.set(EltIdx / 4); 4029 } 4030 4031 int BestLoQuad = -1; 4032 unsigned MaxQuad = 1; 4033 for (unsigned i = 0; i < 4; ++i) { 4034 if (LoQuad[i] > MaxQuad) { 4035 BestLoQuad = i; 4036 MaxQuad = LoQuad[i]; 4037 } 4038 } 4039 4040 int BestHiQuad = -1; 4041 MaxQuad = 1; 4042 for (unsigned i = 0; i < 4; ++i) { 4043 if (HiQuad[i] > MaxQuad) { 4044 BestHiQuad = i; 4045 MaxQuad = HiQuad[i]; 4046 } 4047 } 4048 4049 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 4050 // of the two input vectors, shuffle them into one input vector so only a 4051 // single pshufb instruction is necessary. If There are more than 2 input 4052 // quads, disable the next transformation since it does not help SSSE3. 4053 bool V1Used = InputQuads[0] || InputQuads[1]; 4054 bool V2Used = InputQuads[2] || InputQuads[3]; 4055 if (TLI.getSubtarget()->hasSSSE3()) { 4056 if (InputQuads.count() == 2 && V1Used && V2Used) { 4057 BestLoQuad = InputQuads.find_first(); 4058 BestHiQuad = InputQuads.find_next(BestLoQuad); 4059 } 4060 if (InputQuads.count() > 2) { 4061 BestLoQuad = -1; 4062 BestHiQuad = -1; 4063 } 4064 } 4065 4066 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 4067 // the shuffle mask. If a quad is scored as -1, that means that it contains 4068 // words from all 4 input quadwords. 4069 SDValue NewV; 4070 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 4071 SmallVector<int, 8> MaskV; 4072 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 4073 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 4074 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 4075 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 4076 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 4077 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 4078 4079 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 4080 // source words for the shuffle, to aid later transformations. 4081 bool AllWordsInNewV = true; 4082 bool InOrder[2] = { true, true }; 4083 for (unsigned i = 0; i != 8; ++i) { 4084 int idx = MaskVals[i]; 4085 if (idx != (int)i) 4086 InOrder[i/4] = false; 4087 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 4088 continue; 4089 AllWordsInNewV = false; 4090 break; 4091 } 4092 4093 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 4094 if (AllWordsInNewV) { 4095 for (int i = 0; i != 8; ++i) { 4096 int idx = MaskVals[i]; 4097 if (idx < 0) 4098 continue; 4099 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 4100 if ((idx != i) && idx < 4) 4101 pshufhw = false; 4102 if ((idx != i) && idx > 3) 4103 pshuflw = false; 4104 } 4105 V1 = NewV; 4106 V2Used = false; 4107 BestLoQuad = 0; 4108 BestHiQuad = 1; 4109 } 4110 4111 // If we've eliminated the use of V2, and the new mask is a pshuflw or 4112 // pshufhw, that's as cheap as it gets. Return the new shuffle. 4113 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 4114 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 4115 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 4116 } 4117 } 4118 4119 // If we have SSSE3, and all words of the result are from 1 input vector, 4120 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 4121 // is present, fall back to case 4. 4122 if (TLI.getSubtarget()->hasSSSE3()) { 4123 SmallVector<SDValue,16> pshufbMask; 4124 4125 // If we have elements from both input vectors, set the high bit of the 4126 // shuffle mask element to zero out elements that come from V2 in the V1 4127 // mask, and elements that come from V1 in the V2 mask, so that the two 4128 // results can be OR'd together. 4129 bool TwoInputs = V1Used && V2Used; 4130 for (unsigned i = 0; i != 8; ++i) { 4131 int EltIdx = MaskVals[i] * 2; 4132 if (TwoInputs && (EltIdx >= 16)) { 4133 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4134 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4135 continue; 4136 } 4137 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4138 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4139 } 4140 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4141 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4142 DAG.getNode(ISD::BUILD_VECTOR, dl, 4143 MVT::v16i8, &pshufbMask[0], 16)); 4144 if (!TwoInputs) 4145 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4146 4147 // Calculate the shuffle mask for the second input, shuffle it, and 4148 // OR it with the first shuffled input. 4149 pshufbMask.clear(); 4150 for (unsigned i = 0; i != 8; ++i) { 4151 int EltIdx = MaskVals[i] * 2; 4152 if (EltIdx < 16) { 4153 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4154 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4155 continue; 4156 } 4157 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4158 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4159 } 4160 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4161 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4162 DAG.getNode(ISD::BUILD_VECTOR, dl, 4163 MVT::v16i8, &pshufbMask[0], 16)); 4164 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4165 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4166 } 4167 4168 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4169 // and update MaskVals with new element order. 4170 BitVector InOrder(8); 4171 if (BestLoQuad >= 0) { 4172 SmallVector<int, 8> MaskV; 4173 for (int i = 0; i != 4; ++i) { 4174 int idx = MaskVals[i]; 4175 if (idx < 0) { 4176 MaskV.push_back(-1); 4177 InOrder.set(i); 4178 } else if ((idx / 4) == BestLoQuad) { 4179 MaskV.push_back(idx & 3); 4180 InOrder.set(i); 4181 } else { 4182 MaskV.push_back(-1); 4183 } 4184 } 4185 for (unsigned i = 4; i != 8; ++i) 4186 MaskV.push_back(i); 4187 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4188 &MaskV[0]); 4189 } 4190 4191 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4192 // and update MaskVals with the new element order. 4193 if (BestHiQuad >= 0) { 4194 SmallVector<int, 8> MaskV; 4195 for (unsigned i = 0; i != 4; ++i) 4196 MaskV.push_back(i); 4197 for (unsigned i = 4; i != 8; ++i) { 4198 int idx = MaskVals[i]; 4199 if (idx < 0) { 4200 MaskV.push_back(-1); 4201 InOrder.set(i); 4202 } else if ((idx / 4) == BestHiQuad) { 4203 MaskV.push_back((idx & 3) + 4); 4204 InOrder.set(i); 4205 } else { 4206 MaskV.push_back(-1); 4207 } 4208 } 4209 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4210 &MaskV[0]); 4211 } 4212 4213 // In case BestHi & BestLo were both -1, which means each quadword has a word 4214 // from each of the four input quadwords, calculate the InOrder bitvector now 4215 // before falling through to the insert/extract cleanup. 4216 if (BestLoQuad == -1 && BestHiQuad == -1) { 4217 NewV = V1; 4218 for (int i = 0; i != 8; ++i) 4219 if (MaskVals[i] < 0 || MaskVals[i] == i) 4220 InOrder.set(i); 4221 } 4222 4223 // The other elements are put in the right place using pextrw and pinsrw. 4224 for (unsigned i = 0; i != 8; ++i) { 4225 if (InOrder[i]) 4226 continue; 4227 int EltIdx = MaskVals[i]; 4228 if (EltIdx < 0) 4229 continue; 4230 SDValue ExtOp = (EltIdx < 8) 4231 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4232 DAG.getIntPtrConstant(EltIdx)) 4233 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4234 DAG.getIntPtrConstant(EltIdx - 8)); 4235 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4236 DAG.getIntPtrConstant(i)); 4237 } 4238 return NewV; 4239} 4240 4241// v16i8 shuffles - Prefer shuffles in the following order: 4242// 1. [ssse3] 1 x pshufb 4243// 2. [ssse3] 2 x pshufb + 1 x por 4244// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4245static 4246SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4247 SelectionDAG &DAG, X86TargetLowering &TLI) { 4248 SDValue V1 = SVOp->getOperand(0); 4249 SDValue V2 = SVOp->getOperand(1); 4250 DebugLoc dl = SVOp->getDebugLoc(); 4251 SmallVector<int, 16> MaskVals; 4252 SVOp->getMask(MaskVals); 4253 4254 // If we have SSSE3, case 1 is generated when all result bytes come from 4255 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4256 // present, fall back to case 3. 4257 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4258 bool V1Only = true; 4259 bool V2Only = true; 4260 for (unsigned i = 0; i < 16; ++i) { 4261 int EltIdx = MaskVals[i]; 4262 if (EltIdx < 0) 4263 continue; 4264 if (EltIdx < 16) 4265 V2Only = false; 4266 else 4267 V1Only = false; 4268 } 4269 4270 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4271 if (TLI.getSubtarget()->hasSSSE3()) { 4272 SmallVector<SDValue,16> pshufbMask; 4273 4274 // If all result elements are from one input vector, then only translate 4275 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4276 // 4277 // Otherwise, we have elements from both input vectors, and must zero out 4278 // elements that come from V2 in the first mask, and V1 in the second mask 4279 // so that we can OR them together. 4280 bool TwoInputs = !(V1Only || V2Only); 4281 for (unsigned i = 0; i != 16; ++i) { 4282 int EltIdx = MaskVals[i]; 4283 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4284 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4285 continue; 4286 } 4287 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4288 } 4289 // If all the elements are from V2, assign it to V1 and return after 4290 // building the first pshufb. 4291 if (V2Only) 4292 V1 = V2; 4293 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4294 DAG.getNode(ISD::BUILD_VECTOR, dl, 4295 MVT::v16i8, &pshufbMask[0], 16)); 4296 if (!TwoInputs) 4297 return V1; 4298 4299 // Calculate the shuffle mask for the second input, shuffle it, and 4300 // OR it with the first shuffled input. 4301 pshufbMask.clear(); 4302 for (unsigned i = 0; i != 16; ++i) { 4303 int EltIdx = MaskVals[i]; 4304 if (EltIdx < 16) { 4305 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4306 continue; 4307 } 4308 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4309 } 4310 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4311 DAG.getNode(ISD::BUILD_VECTOR, dl, 4312 MVT::v16i8, &pshufbMask[0], 16)); 4313 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4314 } 4315 4316 // No SSSE3 - Calculate in place words and then fix all out of place words 4317 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4318 // the 16 different words that comprise the two doublequadword input vectors. 4319 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4320 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4321 SDValue NewV = V2Only ? V2 : V1; 4322 for (int i = 0; i != 8; ++i) { 4323 int Elt0 = MaskVals[i*2]; 4324 int Elt1 = MaskVals[i*2+1]; 4325 4326 // This word of the result is all undef, skip it. 4327 if (Elt0 < 0 && Elt1 < 0) 4328 continue; 4329 4330 // This word of the result is already in the correct place, skip it. 4331 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4332 continue; 4333 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4334 continue; 4335 4336 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4337 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4338 SDValue InsElt; 4339 4340 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4341 // using a single extract together, load it and store it. 4342 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4343 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4344 DAG.getIntPtrConstant(Elt1 / 2)); 4345 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4346 DAG.getIntPtrConstant(i)); 4347 continue; 4348 } 4349 4350 // If Elt1 is defined, extract it from the appropriate source. If the 4351 // source byte is not also odd, shift the extracted word left 8 bits 4352 // otherwise clear the bottom 8 bits if we need to do an or. 4353 if (Elt1 >= 0) { 4354 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4355 DAG.getIntPtrConstant(Elt1 / 2)); 4356 if ((Elt1 & 1) == 0) 4357 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4358 DAG.getConstant(8, TLI.getShiftAmountTy())); 4359 else if (Elt0 >= 0) 4360 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4361 DAG.getConstant(0xFF00, MVT::i16)); 4362 } 4363 // If Elt0 is defined, extract it from the appropriate source. If the 4364 // source byte is not also even, shift the extracted word right 8 bits. If 4365 // Elt1 was also defined, OR the extracted values together before 4366 // inserting them in the result. 4367 if (Elt0 >= 0) { 4368 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4369 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4370 if ((Elt0 & 1) != 0) 4371 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4372 DAG.getConstant(8, TLI.getShiftAmountTy())); 4373 else if (Elt1 >= 0) 4374 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4375 DAG.getConstant(0x00FF, MVT::i16)); 4376 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4377 : InsElt0; 4378 } 4379 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4380 DAG.getIntPtrConstant(i)); 4381 } 4382 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4383} 4384 4385/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4386/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 4387/// done when every pair / quad of shuffle mask elements point to elements in 4388/// the right sequence. e.g. 4389/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4390static 4391SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4392 SelectionDAG &DAG, 4393 TargetLowering &TLI, DebugLoc dl) { 4394 EVT VT = SVOp->getValueType(0); 4395 SDValue V1 = SVOp->getOperand(0); 4396 SDValue V2 = SVOp->getOperand(1); 4397 unsigned NumElems = VT.getVectorNumElements(); 4398 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4399 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 4400 EVT MaskEltVT = MaskVT.getVectorElementType(); 4401 EVT NewVT = MaskVT; 4402 switch (VT.getSimpleVT().SimpleTy) { 4403 default: assert(false && "Unexpected!"); 4404 case MVT::v4f32: NewVT = MVT::v2f64; break; 4405 case MVT::v4i32: NewVT = MVT::v2i64; break; 4406 case MVT::v8i16: NewVT = MVT::v4i32; break; 4407 case MVT::v16i8: NewVT = MVT::v4i32; break; 4408 } 4409 4410 if (NewWidth == 2) { 4411 if (VT.isInteger()) 4412 NewVT = MVT::v2i64; 4413 else 4414 NewVT = MVT::v2f64; 4415 } 4416 int Scale = NumElems / NewWidth; 4417 SmallVector<int, 8> MaskVec; 4418 for (unsigned i = 0; i < NumElems; i += Scale) { 4419 int StartIdx = -1; 4420 for (int j = 0; j < Scale; ++j) { 4421 int EltIdx = SVOp->getMaskElt(i+j); 4422 if (EltIdx < 0) 4423 continue; 4424 if (StartIdx == -1) 4425 StartIdx = EltIdx - (EltIdx % Scale); 4426 if (EltIdx != StartIdx + j) 4427 return SDValue(); 4428 } 4429 if (StartIdx == -1) 4430 MaskVec.push_back(-1); 4431 else 4432 MaskVec.push_back(StartIdx / Scale); 4433 } 4434 4435 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4436 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4437 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4438} 4439 4440/// getVZextMovL - Return a zero-extending vector move low node. 4441/// 4442static SDValue getVZextMovL(EVT VT, EVT OpVT, 4443 SDValue SrcOp, SelectionDAG &DAG, 4444 const X86Subtarget *Subtarget, DebugLoc dl) { 4445 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4446 LoadSDNode *LD = NULL; 4447 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4448 LD = dyn_cast<LoadSDNode>(SrcOp); 4449 if (!LD) { 4450 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4451 // instead. 4452 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4453 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4454 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4455 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4456 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4457 // PR2108 4458 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4459 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4460 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4461 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4462 OpVT, 4463 SrcOp.getOperand(0) 4464 .getOperand(0)))); 4465 } 4466 } 4467 } 4468 4469 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4470 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4471 DAG.getNode(ISD::BIT_CONVERT, dl, 4472 OpVT, SrcOp))); 4473} 4474 4475/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4476/// shuffles. 4477static SDValue 4478LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4479 SDValue V1 = SVOp->getOperand(0); 4480 SDValue V2 = SVOp->getOperand(1); 4481 DebugLoc dl = SVOp->getDebugLoc(); 4482 EVT VT = SVOp->getValueType(0); 4483 4484 SmallVector<std::pair<int, int>, 8> Locs; 4485 Locs.resize(4); 4486 SmallVector<int, 8> Mask1(4U, -1); 4487 SmallVector<int, 8> PermMask; 4488 SVOp->getMask(PermMask); 4489 4490 unsigned NumHi = 0; 4491 unsigned NumLo = 0; 4492 for (unsigned i = 0; i != 4; ++i) { 4493 int Idx = PermMask[i]; 4494 if (Idx < 0) { 4495 Locs[i] = std::make_pair(-1, -1); 4496 } else { 4497 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4498 if (Idx < 4) { 4499 Locs[i] = std::make_pair(0, NumLo); 4500 Mask1[NumLo] = Idx; 4501 NumLo++; 4502 } else { 4503 Locs[i] = std::make_pair(1, NumHi); 4504 if (2+NumHi < 4) 4505 Mask1[2+NumHi] = Idx; 4506 NumHi++; 4507 } 4508 } 4509 } 4510 4511 if (NumLo <= 2 && NumHi <= 2) { 4512 // If no more than two elements come from either vector. This can be 4513 // implemented with two shuffles. First shuffle gather the elements. 4514 // The second shuffle, which takes the first shuffle as both of its 4515 // vector operands, put the elements into the right order. 4516 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4517 4518 SmallVector<int, 8> Mask2(4U, -1); 4519 4520 for (unsigned i = 0; i != 4; ++i) { 4521 if (Locs[i].first == -1) 4522 continue; 4523 else { 4524 unsigned Idx = (i < 2) ? 0 : 4; 4525 Idx += Locs[i].first * 2 + Locs[i].second; 4526 Mask2[i] = Idx; 4527 } 4528 } 4529 4530 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4531 } else if (NumLo == 3 || NumHi == 3) { 4532 // Otherwise, we must have three elements from one vector, call it X, and 4533 // one element from the other, call it Y. First, use a shufps to build an 4534 // intermediate vector with the one element from Y and the element from X 4535 // that will be in the same half in the final destination (the indexes don't 4536 // matter). Then, use a shufps to build the final vector, taking the half 4537 // containing the element from Y from the intermediate, and the other half 4538 // from X. 4539 if (NumHi == 3) { 4540 // Normalize it so the 3 elements come from V1. 4541 CommuteVectorShuffleMask(PermMask, VT); 4542 std::swap(V1, V2); 4543 } 4544 4545 // Find the element from V2. 4546 unsigned HiIndex; 4547 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4548 int Val = PermMask[HiIndex]; 4549 if (Val < 0) 4550 continue; 4551 if (Val >= 4) 4552 break; 4553 } 4554 4555 Mask1[0] = PermMask[HiIndex]; 4556 Mask1[1] = -1; 4557 Mask1[2] = PermMask[HiIndex^1]; 4558 Mask1[3] = -1; 4559 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4560 4561 if (HiIndex >= 2) { 4562 Mask1[0] = PermMask[0]; 4563 Mask1[1] = PermMask[1]; 4564 Mask1[2] = HiIndex & 1 ? 6 : 4; 4565 Mask1[3] = HiIndex & 1 ? 4 : 6; 4566 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4567 } else { 4568 Mask1[0] = HiIndex & 1 ? 2 : 0; 4569 Mask1[1] = HiIndex & 1 ? 0 : 2; 4570 Mask1[2] = PermMask[2]; 4571 Mask1[3] = PermMask[3]; 4572 if (Mask1[2] >= 0) 4573 Mask1[2] += 4; 4574 if (Mask1[3] >= 0) 4575 Mask1[3] += 4; 4576 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4577 } 4578 } 4579 4580 // Break it into (shuffle shuffle_hi, shuffle_lo). 4581 Locs.clear(); 4582 SmallVector<int,8> LoMask(4U, -1); 4583 SmallVector<int,8> HiMask(4U, -1); 4584 4585 SmallVector<int,8> *MaskPtr = &LoMask; 4586 unsigned MaskIdx = 0; 4587 unsigned LoIdx = 0; 4588 unsigned HiIdx = 2; 4589 for (unsigned i = 0; i != 4; ++i) { 4590 if (i == 2) { 4591 MaskPtr = &HiMask; 4592 MaskIdx = 1; 4593 LoIdx = 0; 4594 HiIdx = 2; 4595 } 4596 int Idx = PermMask[i]; 4597 if (Idx < 0) { 4598 Locs[i] = std::make_pair(-1, -1); 4599 } else if (Idx < 4) { 4600 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4601 (*MaskPtr)[LoIdx] = Idx; 4602 LoIdx++; 4603 } else { 4604 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4605 (*MaskPtr)[HiIdx] = Idx; 4606 HiIdx++; 4607 } 4608 } 4609 4610 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4611 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4612 SmallVector<int, 8> MaskOps; 4613 for (unsigned i = 0; i != 4; ++i) { 4614 if (Locs[i].first == -1) { 4615 MaskOps.push_back(-1); 4616 } else { 4617 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4618 MaskOps.push_back(Idx); 4619 } 4620 } 4621 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4622} 4623 4624SDValue 4625X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4626 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4627 SDValue V1 = Op.getOperand(0); 4628 SDValue V2 = Op.getOperand(1); 4629 EVT VT = Op.getValueType(); 4630 DebugLoc dl = Op.getDebugLoc(); 4631 unsigned NumElems = VT.getVectorNumElements(); 4632 bool isMMX = VT.getSizeInBits() == 64; 4633 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4634 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4635 bool V1IsSplat = false; 4636 bool V2IsSplat = false; 4637 4638 if (isZeroShuffle(SVOp)) 4639 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4640 4641 // Promote splats to v4f32. 4642 if (SVOp->isSplat()) { 4643 if (isMMX || NumElems < 4) 4644 return Op; 4645 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4646 } 4647 4648 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4649 // do it! 4650 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4651 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4652 if (NewOp.getNode()) 4653 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4654 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4655 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4656 // FIXME: Figure out a cleaner way to do this. 4657 // Try to make use of movq to zero out the top part. 4658 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4659 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4660 if (NewOp.getNode()) { 4661 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4662 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4663 DAG, Subtarget, dl); 4664 } 4665 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4666 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4667 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4668 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4669 DAG, Subtarget, dl); 4670 } 4671 } 4672 4673 if (X86::isPSHUFDMask(SVOp)) 4674 return Op; 4675 4676 // Check if this can be converted into a logical shift. 4677 bool isLeft = false; 4678 unsigned ShAmt = 0; 4679 SDValue ShVal; 4680 bool isShift = getSubtarget()->hasSSE2() && 4681 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4682 if (isShift && ShVal.hasOneUse()) { 4683 // If the shifted value has multiple uses, it may be cheaper to use 4684 // v_set0 + movlhps or movhlps, etc. 4685 EVT EltVT = VT.getVectorElementType(); 4686 ShAmt *= EltVT.getSizeInBits(); 4687 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4688 } 4689 4690 if (X86::isMOVLMask(SVOp)) { 4691 if (V1IsUndef) 4692 return V2; 4693 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4694 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4695 if (!isMMX) 4696 return Op; 4697 } 4698 4699 // FIXME: fold these into legal mask. 4700 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4701 X86::isMOVSLDUPMask(SVOp) || 4702 X86::isMOVHLPSMask(SVOp) || 4703 X86::isMOVLHPSMask(SVOp) || 4704 X86::isMOVLPMask(SVOp))) 4705 return Op; 4706 4707 if (ShouldXformToMOVHLPS(SVOp) || 4708 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4709 return CommuteVectorShuffle(SVOp, DAG); 4710 4711 if (isShift) { 4712 // No better options. Use a vshl / vsrl. 4713 EVT EltVT = VT.getVectorElementType(); 4714 ShAmt *= EltVT.getSizeInBits(); 4715 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4716 } 4717 4718 bool Commuted = false; 4719 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4720 // 1,1,1,1 -> v8i16 though. 4721 V1IsSplat = isSplatVector(V1.getNode()); 4722 V2IsSplat = isSplatVector(V2.getNode()); 4723 4724 // Canonicalize the splat or undef, if present, to be on the RHS. 4725 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4726 Op = CommuteVectorShuffle(SVOp, DAG); 4727 SVOp = cast<ShuffleVectorSDNode>(Op); 4728 V1 = SVOp->getOperand(0); 4729 V2 = SVOp->getOperand(1); 4730 std::swap(V1IsSplat, V2IsSplat); 4731 std::swap(V1IsUndef, V2IsUndef); 4732 Commuted = true; 4733 } 4734 4735 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4736 // Shuffling low element of v1 into undef, just return v1. 4737 if (V2IsUndef) 4738 return V1; 4739 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4740 // the instruction selector will not match, so get a canonical MOVL with 4741 // swapped operands to undo the commute. 4742 return getMOVL(DAG, dl, VT, V2, V1); 4743 } 4744 4745 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4746 X86::isUNPCKH_v_undef_Mask(SVOp) || 4747 X86::isUNPCKLMask(SVOp) || 4748 X86::isUNPCKHMask(SVOp)) 4749 return Op; 4750 4751 if (V2IsSplat) { 4752 // Normalize mask so all entries that point to V2 points to its first 4753 // element then try to match unpck{h|l} again. If match, return a 4754 // new vector_shuffle with the corrected mask. 4755 SDValue NewMask = NormalizeMask(SVOp, DAG); 4756 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4757 if (NSVOp != SVOp) { 4758 if (X86::isUNPCKLMask(NSVOp, true)) { 4759 return NewMask; 4760 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4761 return NewMask; 4762 } 4763 } 4764 } 4765 4766 if (Commuted) { 4767 // Commute is back and try unpck* again. 4768 // FIXME: this seems wrong. 4769 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4770 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4771 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4772 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4773 X86::isUNPCKLMask(NewSVOp) || 4774 X86::isUNPCKHMask(NewSVOp)) 4775 return NewOp; 4776 } 4777 4778 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4779 4780 // Normalize the node to match x86 shuffle ops if needed 4781 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4782 return CommuteVectorShuffle(SVOp, DAG); 4783 4784 // Check for legal shuffle and return? 4785 SmallVector<int, 16> PermMask; 4786 SVOp->getMask(PermMask); 4787 if (isShuffleMaskLegal(PermMask, VT)) 4788 return Op; 4789 4790 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4791 if (VT == MVT::v8i16) { 4792 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4793 if (NewOp.getNode()) 4794 return NewOp; 4795 } 4796 4797 if (VT == MVT::v16i8) { 4798 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4799 if (NewOp.getNode()) 4800 return NewOp; 4801 } 4802 4803 // Handle all 4 wide cases with a number of shuffles except for MMX. 4804 if (NumElems == 4 && !isMMX) 4805 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4806 4807 return SDValue(); 4808} 4809 4810SDValue 4811X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4812 SelectionDAG &DAG) { 4813 EVT VT = Op.getValueType(); 4814 DebugLoc dl = Op.getDebugLoc(); 4815 if (VT.getSizeInBits() == 8) { 4816 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4817 Op.getOperand(0), Op.getOperand(1)); 4818 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4819 DAG.getValueType(VT)); 4820 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4821 } else if (VT.getSizeInBits() == 16) { 4822 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4823 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4824 if (Idx == 0) 4825 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4826 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4827 DAG.getNode(ISD::BIT_CONVERT, dl, 4828 MVT::v4i32, 4829 Op.getOperand(0)), 4830 Op.getOperand(1))); 4831 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4832 Op.getOperand(0), Op.getOperand(1)); 4833 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4834 DAG.getValueType(VT)); 4835 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4836 } else if (VT == MVT::f32) { 4837 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4838 // the result back to FR32 register. It's only worth matching if the 4839 // result has a single use which is a store or a bitcast to i32. And in 4840 // the case of a store, it's not worth it if the index is a constant 0, 4841 // because a MOVSSmr can be used instead, which is smaller and faster. 4842 if (!Op.hasOneUse()) 4843 return SDValue(); 4844 SDNode *User = *Op.getNode()->use_begin(); 4845 if ((User->getOpcode() != ISD::STORE || 4846 (isa<ConstantSDNode>(Op.getOperand(1)) && 4847 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4848 (User->getOpcode() != ISD::BIT_CONVERT || 4849 User->getValueType(0) != MVT::i32)) 4850 return SDValue(); 4851 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4852 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4853 Op.getOperand(0)), 4854 Op.getOperand(1)); 4855 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4856 } else if (VT == MVT::i32) { 4857 // ExtractPS works with constant index. 4858 if (isa<ConstantSDNode>(Op.getOperand(1))) 4859 return Op; 4860 } 4861 return SDValue(); 4862} 4863 4864 4865SDValue 4866X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4867 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4868 return SDValue(); 4869 4870 if (Subtarget->hasSSE41()) { 4871 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4872 if (Res.getNode()) 4873 return Res; 4874 } 4875 4876 EVT VT = Op.getValueType(); 4877 DebugLoc dl = Op.getDebugLoc(); 4878 // TODO: handle v16i8. 4879 if (VT.getSizeInBits() == 16) { 4880 SDValue Vec = Op.getOperand(0); 4881 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4882 if (Idx == 0) 4883 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4884 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4885 DAG.getNode(ISD::BIT_CONVERT, dl, 4886 MVT::v4i32, Vec), 4887 Op.getOperand(1))); 4888 // Transform it so it match pextrw which produces a 32-bit result. 4889 EVT EltVT = MVT::i32; 4890 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 4891 Op.getOperand(0), Op.getOperand(1)); 4892 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 4893 DAG.getValueType(VT)); 4894 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4895 } else if (VT.getSizeInBits() == 32) { 4896 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4897 if (Idx == 0) 4898 return Op; 4899 4900 // SHUFPS the element to the lowest double word, then movss. 4901 int Mask[4] = { Idx, -1, -1, -1 }; 4902 EVT VVT = Op.getOperand(0).getValueType(); 4903 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4904 DAG.getUNDEF(VVT), Mask); 4905 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4906 DAG.getIntPtrConstant(0)); 4907 } else if (VT.getSizeInBits() == 64) { 4908 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4909 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4910 // to match extract_elt for f64. 4911 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4912 if (Idx == 0) 4913 return Op; 4914 4915 // UNPCKHPD the element to the lowest double word, then movsd. 4916 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4917 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4918 int Mask[2] = { 1, -1 }; 4919 EVT VVT = Op.getOperand(0).getValueType(); 4920 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4921 DAG.getUNDEF(VVT), Mask); 4922 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4923 DAG.getIntPtrConstant(0)); 4924 } 4925 4926 return SDValue(); 4927} 4928 4929SDValue 4930X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4931 EVT VT = Op.getValueType(); 4932 EVT EltVT = VT.getVectorElementType(); 4933 DebugLoc dl = Op.getDebugLoc(); 4934 4935 SDValue N0 = Op.getOperand(0); 4936 SDValue N1 = Op.getOperand(1); 4937 SDValue N2 = Op.getOperand(2); 4938 4939 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 4940 isa<ConstantSDNode>(N2)) { 4941 unsigned Opc; 4942 if (VT == MVT::v8i16) 4943 Opc = X86ISD::PINSRW; 4944 else if (VT == MVT::v4i16) 4945 Opc = X86ISD::MMX_PINSRW; 4946 else if (VT == MVT::v16i8) 4947 Opc = X86ISD::PINSRB; 4948 else 4949 Opc = X86ISD::PINSRB; 4950 4951 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4952 // argument. 4953 if (N1.getValueType() != MVT::i32) 4954 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4955 if (N2.getValueType() != MVT::i32) 4956 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4957 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4958 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4959 // Bits [7:6] of the constant are the source select. This will always be 4960 // zero here. The DAG Combiner may combine an extract_elt index into these 4961 // bits. For example (insert (extract, 3), 2) could be matched by putting 4962 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4963 // Bits [5:4] of the constant are the destination select. This is the 4964 // value of the incoming immediate. 4965 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4966 // combine either bitwise AND or insert of float 0.0 to set these bits. 4967 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4968 // Create this as a scalar to vector.. 4969 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4970 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4971 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4972 // PINSR* works with constant index. 4973 return Op; 4974 } 4975 return SDValue(); 4976} 4977 4978SDValue 4979X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4980 EVT VT = Op.getValueType(); 4981 EVT EltVT = VT.getVectorElementType(); 4982 4983 if (Subtarget->hasSSE41()) 4984 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4985 4986 if (EltVT == MVT::i8) 4987 return SDValue(); 4988 4989 DebugLoc dl = Op.getDebugLoc(); 4990 SDValue N0 = Op.getOperand(0); 4991 SDValue N1 = Op.getOperand(1); 4992 SDValue N2 = Op.getOperand(2); 4993 4994 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4995 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4996 // as its second argument. 4997 if (N1.getValueType() != MVT::i32) 4998 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4999 if (N2.getValueType() != MVT::i32) 5000 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 5001 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW, 5002 dl, VT, N0, N1, N2); 5003 } 5004 return SDValue(); 5005} 5006 5007SDValue 5008X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 5009 DebugLoc dl = Op.getDebugLoc(); 5010 if (Op.getValueType() == MVT::v2f32) 5011 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 5012 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 5013 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 5014 Op.getOperand(0)))); 5015 5016 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 5017 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 5018 5019 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 5020 EVT VT = MVT::v2i32; 5021 switch (Op.getValueType().getSimpleVT().SimpleTy) { 5022 default: break; 5023 case MVT::v16i8: 5024 case MVT::v8i16: 5025 VT = MVT::v4i32; 5026 break; 5027 } 5028 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 5029 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 5030} 5031 5032// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 5033// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 5034// one of the above mentioned nodes. It has to be wrapped because otherwise 5035// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 5036// be used to form addressing mode. These wrapped nodes will be selected 5037// into MOV32ri. 5038SDValue 5039X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 5040 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5041 5042 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5043 // global base reg. 5044 unsigned char OpFlag = 0; 5045 unsigned WrapperKind = X86ISD::Wrapper; 5046 CodeModel::Model M = getTargetMachine().getCodeModel(); 5047 5048 if (Subtarget->isPICStyleRIPRel() && 5049 (M == CodeModel::Small || M == CodeModel::Kernel)) 5050 WrapperKind = X86ISD::WrapperRIP; 5051 else if (Subtarget->isPICStyleGOT()) 5052 OpFlag = X86II::MO_GOTOFF; 5053 else if (Subtarget->isPICStyleStubPIC()) 5054 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5055 5056 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 5057 CP->getAlignment(), 5058 CP->getOffset(), OpFlag); 5059 DebugLoc DL = CP->getDebugLoc(); 5060 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5061 // With PIC, the address is actually $g + Offset. 5062 if (OpFlag) { 5063 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5064 DAG.getNode(X86ISD::GlobalBaseReg, 5065 DebugLoc::getUnknownLoc(), getPointerTy()), 5066 Result); 5067 } 5068 5069 return Result; 5070} 5071 5072SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 5073 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 5074 5075 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5076 // global base reg. 5077 unsigned char OpFlag = 0; 5078 unsigned WrapperKind = X86ISD::Wrapper; 5079 CodeModel::Model M = getTargetMachine().getCodeModel(); 5080 5081 if (Subtarget->isPICStyleRIPRel() && 5082 (M == CodeModel::Small || M == CodeModel::Kernel)) 5083 WrapperKind = X86ISD::WrapperRIP; 5084 else if (Subtarget->isPICStyleGOT()) 5085 OpFlag = X86II::MO_GOTOFF; 5086 else if (Subtarget->isPICStyleStubPIC()) 5087 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5088 5089 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 5090 OpFlag); 5091 DebugLoc DL = JT->getDebugLoc(); 5092 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5093 5094 // With PIC, the address is actually $g + Offset. 5095 if (OpFlag) { 5096 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5097 DAG.getNode(X86ISD::GlobalBaseReg, 5098 DebugLoc::getUnknownLoc(), getPointerTy()), 5099 Result); 5100 } 5101 5102 return Result; 5103} 5104 5105SDValue 5106X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 5107 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 5108 5109 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 5110 // global base reg. 5111 unsigned char OpFlag = 0; 5112 unsigned WrapperKind = X86ISD::Wrapper; 5113 CodeModel::Model M = getTargetMachine().getCodeModel(); 5114 5115 if (Subtarget->isPICStyleRIPRel() && 5116 (M == CodeModel::Small || M == CodeModel::Kernel)) 5117 WrapperKind = X86ISD::WrapperRIP; 5118 else if (Subtarget->isPICStyleGOT()) 5119 OpFlag = X86II::MO_GOTOFF; 5120 else if (Subtarget->isPICStyleStubPIC()) 5121 OpFlag = X86II::MO_PIC_BASE_OFFSET; 5122 5123 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 5124 5125 DebugLoc DL = Op.getDebugLoc(); 5126 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 5127 5128 5129 // With PIC, the address is actually $g + Offset. 5130 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 5131 !Subtarget->is64Bit()) { 5132 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5133 DAG.getNode(X86ISD::GlobalBaseReg, 5134 DebugLoc::getUnknownLoc(), 5135 getPointerTy()), 5136 Result); 5137 } 5138 5139 return Result; 5140} 5141 5142SDValue 5143X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 5144 // Create the TargetBlockAddressAddress node. 5145 unsigned char OpFlags = 5146 Subtarget->ClassifyBlockAddressReference(); 5147 CodeModel::Model M = getTargetMachine().getCodeModel(); 5148 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5149 DebugLoc dl = Op.getDebugLoc(); 5150 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5151 /*isTarget=*/true, OpFlags); 5152 5153 if (Subtarget->isPICStyleRIPRel() && 5154 (M == CodeModel::Small || M == CodeModel::Kernel)) 5155 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5156 else 5157 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5158 5159 // With PIC, the address is actually $g + Offset. 5160 if (isGlobalRelativeToPICBase(OpFlags)) { 5161 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5162 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5163 Result); 5164 } 5165 5166 return Result; 5167} 5168 5169SDValue 5170X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5171 int64_t Offset, 5172 SelectionDAG &DAG) const { 5173 // Create the TargetGlobalAddress node, folding in the constant 5174 // offset if it is legal. 5175 unsigned char OpFlags = 5176 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5177 CodeModel::Model M = getTargetMachine().getCodeModel(); 5178 SDValue Result; 5179 if (OpFlags == X86II::MO_NO_FLAG && 5180 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5181 // A direct static reference to a global. 5182 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 5183 Offset = 0; 5184 } else { 5185 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 5186 } 5187 5188 if (Subtarget->isPICStyleRIPRel() && 5189 (M == CodeModel::Small || M == CodeModel::Kernel)) 5190 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5191 else 5192 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5193 5194 // With PIC, the address is actually $g + Offset. 5195 if (isGlobalRelativeToPICBase(OpFlags)) { 5196 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5197 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5198 Result); 5199 } 5200 5201 // For globals that require a load from a stub to get the address, emit the 5202 // load. 5203 if (isGlobalStubReference(OpFlags)) 5204 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5205 PseudoSourceValue::getGOT(), 0, false, false, 0); 5206 5207 // If there was a non-zero offset that we didn't fold, create an explicit 5208 // addition for it. 5209 if (Offset != 0) 5210 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5211 DAG.getConstant(Offset, getPointerTy())); 5212 5213 return Result; 5214} 5215 5216SDValue 5217X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 5218 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5219 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5220 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5221} 5222 5223static SDValue 5224GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5225 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5226 unsigned char OperandFlags) { 5227 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5228 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5229 DebugLoc dl = GA->getDebugLoc(); 5230 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 5231 GA->getValueType(0), 5232 GA->getOffset(), 5233 OperandFlags); 5234 if (InFlag) { 5235 SDValue Ops[] = { Chain, TGA, *InFlag }; 5236 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5237 } else { 5238 SDValue Ops[] = { Chain, TGA }; 5239 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5240 } 5241 5242 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5243 MFI->setHasCalls(true); 5244 5245 SDValue Flag = Chain.getValue(1); 5246 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5247} 5248 5249// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5250static SDValue 5251LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5252 const EVT PtrVT) { 5253 SDValue InFlag; 5254 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5255 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5256 DAG.getNode(X86ISD::GlobalBaseReg, 5257 DebugLoc::getUnknownLoc(), 5258 PtrVT), InFlag); 5259 InFlag = Chain.getValue(1); 5260 5261 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5262} 5263 5264// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5265static SDValue 5266LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5267 const EVT PtrVT) { 5268 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5269 X86::RAX, X86II::MO_TLSGD); 5270} 5271 5272// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5273// "local exec" model. 5274static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5275 const EVT PtrVT, TLSModel::Model model, 5276 bool is64Bit) { 5277 DebugLoc dl = GA->getDebugLoc(); 5278 // Get the Thread Pointer 5279 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5280 DebugLoc::getUnknownLoc(), PtrVT, 5281 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5282 MVT::i32)); 5283 5284 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5285 NULL, 0, false, false, 0); 5286 5287 unsigned char OperandFlags = 0; 5288 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5289 // initialexec. 5290 unsigned WrapperKind = X86ISD::Wrapper; 5291 if (model == TLSModel::LocalExec) { 5292 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5293 } else if (is64Bit) { 5294 assert(model == TLSModel::InitialExec); 5295 OperandFlags = X86II::MO_GOTTPOFF; 5296 WrapperKind = X86ISD::WrapperRIP; 5297 } else { 5298 assert(model == TLSModel::InitialExec); 5299 OperandFlags = X86II::MO_INDNTPOFF; 5300 } 5301 5302 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5303 // exec) 5304 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 5305 GA->getOffset(), OperandFlags); 5306 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5307 5308 if (model == TLSModel::InitialExec) 5309 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5310 PseudoSourceValue::getGOT(), 0, false, false, 0); 5311 5312 // The address of the thread local variable is the add of the thread 5313 // pointer with the offset of the variable. 5314 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5315} 5316 5317SDValue 5318X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 5319 // TODO: implement the "local dynamic" model 5320 // TODO: implement the "initial exec"model for pic executables 5321 assert(Subtarget->isTargetELF() && 5322 "TLS not implemented for non-ELF targets"); 5323 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5324 const GlobalValue *GV = GA->getGlobal(); 5325 5326 // If GV is an alias then use the aliasee for determining 5327 // thread-localness. 5328 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5329 GV = GA->resolveAliasedGlobal(false); 5330 5331 TLSModel::Model model = getTLSModel(GV, 5332 getTargetMachine().getRelocationModel()); 5333 5334 switch (model) { 5335 case TLSModel::GeneralDynamic: 5336 case TLSModel::LocalDynamic: // not implemented 5337 if (Subtarget->is64Bit()) 5338 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5339 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5340 5341 case TLSModel::InitialExec: 5342 case TLSModel::LocalExec: 5343 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5344 Subtarget->is64Bit()); 5345 } 5346 5347 llvm_unreachable("Unreachable"); 5348 return SDValue(); 5349} 5350 5351 5352/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5353/// take a 2 x i32 value to shift plus a shift amount. 5354SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 5355 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5356 EVT VT = Op.getValueType(); 5357 unsigned VTBits = VT.getSizeInBits(); 5358 DebugLoc dl = Op.getDebugLoc(); 5359 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5360 SDValue ShOpLo = Op.getOperand(0); 5361 SDValue ShOpHi = Op.getOperand(1); 5362 SDValue ShAmt = Op.getOperand(2); 5363 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5364 DAG.getConstant(VTBits - 1, MVT::i8)) 5365 : DAG.getConstant(0, VT); 5366 5367 SDValue Tmp2, Tmp3; 5368 if (Op.getOpcode() == ISD::SHL_PARTS) { 5369 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5370 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5371 } else { 5372 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5373 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5374 } 5375 5376 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5377 DAG.getConstant(VTBits, MVT::i8)); 5378 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 5379 AndNode, DAG.getConstant(0, MVT::i8)); 5380 5381 SDValue Hi, Lo; 5382 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5383 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5384 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5385 5386 if (Op.getOpcode() == ISD::SHL_PARTS) { 5387 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5388 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5389 } else { 5390 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5391 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5392 } 5393 5394 SDValue Ops[2] = { Lo, Hi }; 5395 return DAG.getMergeValues(Ops, 2, dl); 5396} 5397 5398SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5399 EVT SrcVT = Op.getOperand(0).getValueType(); 5400 5401 if (SrcVT.isVector()) { 5402 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5403 return Op; 5404 } 5405 return SDValue(); 5406 } 5407 5408 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5409 "Unknown SINT_TO_FP to lower!"); 5410 5411 // These are really Legal; return the operand so the caller accepts it as 5412 // Legal. 5413 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5414 return Op; 5415 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5416 Subtarget->is64Bit()) { 5417 return Op; 5418 } 5419 5420 DebugLoc dl = Op.getDebugLoc(); 5421 unsigned Size = SrcVT.getSizeInBits()/8; 5422 MachineFunction &MF = DAG.getMachineFunction(); 5423 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5424 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5425 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5426 StackSlot, 5427 PseudoSourceValue::getFixedStack(SSFI), 0, 5428 false, false, 0); 5429 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5430} 5431 5432SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5433 SDValue StackSlot, 5434 SelectionDAG &DAG) { 5435 // Build the FILD 5436 DebugLoc dl = Op.getDebugLoc(); 5437 SDVTList Tys; 5438 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5439 if (useSSE) 5440 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5441 else 5442 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5443 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5444 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5445 Tys, Ops, array_lengthof(Ops)); 5446 5447 if (useSSE) { 5448 Chain = Result.getValue(1); 5449 SDValue InFlag = Result.getValue(2); 5450 5451 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5452 // shouldn't be necessary except that RFP cannot be live across 5453 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5454 MachineFunction &MF = DAG.getMachineFunction(); 5455 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5456 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5457 Tys = DAG.getVTList(MVT::Other); 5458 SDValue Ops[] = { 5459 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5460 }; 5461 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5462 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5463 PseudoSourceValue::getFixedStack(SSFI), 0, 5464 false, false, 0); 5465 } 5466 5467 return Result; 5468} 5469 5470// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5471SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 5472 // This algorithm is not obvious. Here it is in C code, more or less: 5473 /* 5474 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5475 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5476 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5477 5478 // Copy ints to xmm registers. 5479 __m128i xh = _mm_cvtsi32_si128( hi ); 5480 __m128i xl = _mm_cvtsi32_si128( lo ); 5481 5482 // Combine into low half of a single xmm register. 5483 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5484 __m128d d; 5485 double sd; 5486 5487 // Merge in appropriate exponents to give the integer bits the right 5488 // magnitude. 5489 x = _mm_unpacklo_epi32( x, exp ); 5490 5491 // Subtract away the biases to deal with the IEEE-754 double precision 5492 // implicit 1. 5493 d = _mm_sub_pd( (__m128d) x, bias ); 5494 5495 // All conversions up to here are exact. The correctly rounded result is 5496 // calculated using the current rounding mode using the following 5497 // horizontal add. 5498 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5499 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5500 // store doesn't really need to be here (except 5501 // maybe to zero the other double) 5502 return sd; 5503 } 5504 */ 5505 5506 DebugLoc dl = Op.getDebugLoc(); 5507 LLVMContext *Context = DAG.getContext(); 5508 5509 // Build some magic constants. 5510 std::vector<Constant*> CV0; 5511 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5512 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5513 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5514 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5515 Constant *C0 = ConstantVector::get(CV0); 5516 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5517 5518 std::vector<Constant*> CV1; 5519 CV1.push_back( 5520 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5521 CV1.push_back( 5522 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 5523 Constant *C1 = ConstantVector::get(CV1); 5524 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 5525 5526 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5527 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5528 Op.getOperand(0), 5529 DAG.getIntPtrConstant(1))); 5530 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5531 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5532 Op.getOperand(0), 5533 DAG.getIntPtrConstant(0))); 5534 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 5535 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5536 PseudoSourceValue::getConstantPool(), 0, 5537 false, false, 16); 5538 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 5539 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5540 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5541 PseudoSourceValue::getConstantPool(), 0, 5542 false, false, 16); 5543 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5544 5545 // Add the halves; easiest way is to swap them into another reg first. 5546 int ShufMask[2] = { 1, -1 }; 5547 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 5548 DAG.getUNDEF(MVT::v2f64), ShufMask); 5549 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5550 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5551 DAG.getIntPtrConstant(0)); 5552} 5553 5554// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5555SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5556 DebugLoc dl = Op.getDebugLoc(); 5557 // FP constant to bias correct the final result. 5558 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5559 MVT::f64); 5560 5561 // Load the 32-bit value into an XMM register. 5562 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5563 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5564 Op.getOperand(0), 5565 DAG.getIntPtrConstant(0))); 5566 5567 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5568 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5569 DAG.getIntPtrConstant(0)); 5570 5571 // Or the load with the bias. 5572 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5573 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5574 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5575 MVT::v2f64, Load)), 5576 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5577 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5578 MVT::v2f64, Bias))); 5579 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5580 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5581 DAG.getIntPtrConstant(0)); 5582 5583 // Subtract the bias. 5584 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5585 5586 // Handle final rounding. 5587 EVT DestVT = Op.getValueType(); 5588 5589 if (DestVT.bitsLT(MVT::f64)) { 5590 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5591 DAG.getIntPtrConstant(0)); 5592 } else if (DestVT.bitsGT(MVT::f64)) { 5593 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5594 } 5595 5596 // Handle final rounding. 5597 return Sub; 5598} 5599 5600SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5601 SDValue N0 = Op.getOperand(0); 5602 DebugLoc dl = Op.getDebugLoc(); 5603 5604 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5605 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5606 // the optimization here. 5607 if (DAG.SignBitIsZero(N0)) 5608 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5609 5610 EVT SrcVT = N0.getValueType(); 5611 if (SrcVT == MVT::i64) { 5612 // We only handle SSE2 f64 target here; caller can expand the rest. 5613 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5614 return SDValue(); 5615 5616 return LowerUINT_TO_FP_i64(Op, DAG); 5617 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5618 return LowerUINT_TO_FP_i32(Op, DAG); 5619 } 5620 5621 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5622 5623 // Make a 64-bit buffer, and use it to build an FILD. 5624 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5625 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5626 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5627 getPointerTy(), StackSlot, WordOff); 5628 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5629 StackSlot, NULL, 0, false, false, 0); 5630 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5631 OffsetSlot, NULL, 0, false, false, 0); 5632 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5633} 5634 5635std::pair<SDValue,SDValue> X86TargetLowering:: 5636FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5637 DebugLoc dl = Op.getDebugLoc(); 5638 5639 EVT DstTy = Op.getValueType(); 5640 5641 if (!IsSigned) { 5642 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5643 DstTy = MVT::i64; 5644 } 5645 5646 assert(DstTy.getSimpleVT() <= MVT::i64 && 5647 DstTy.getSimpleVT() >= MVT::i16 && 5648 "Unknown FP_TO_SINT to lower!"); 5649 5650 // These are really Legal. 5651 if (DstTy == MVT::i32 && 5652 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5653 return std::make_pair(SDValue(), SDValue()); 5654 if (Subtarget->is64Bit() && 5655 DstTy == MVT::i64 && 5656 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5657 return std::make_pair(SDValue(), SDValue()); 5658 5659 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5660 // stack slot. 5661 MachineFunction &MF = DAG.getMachineFunction(); 5662 unsigned MemSize = DstTy.getSizeInBits()/8; 5663 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5664 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5665 5666 unsigned Opc; 5667 switch (DstTy.getSimpleVT().SimpleTy) { 5668 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5669 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5670 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5671 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5672 } 5673 5674 SDValue Chain = DAG.getEntryNode(); 5675 SDValue Value = Op.getOperand(0); 5676 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5677 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5678 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5679 PseudoSourceValue::getFixedStack(SSFI), 0, 5680 false, false, 0); 5681 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5682 SDValue Ops[] = { 5683 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5684 }; 5685 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5686 Chain = Value.getValue(1); 5687 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5688 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5689 } 5690 5691 // Build the FP_TO_INT*_IN_MEM 5692 SDValue Ops[] = { Chain, Value, StackSlot }; 5693 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5694 5695 return std::make_pair(FIST, StackSlot); 5696} 5697 5698SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5699 if (Op.getValueType().isVector()) { 5700 if (Op.getValueType() == MVT::v2i32 && 5701 Op.getOperand(0).getValueType() == MVT::v2f64) { 5702 return Op; 5703 } 5704 return SDValue(); 5705 } 5706 5707 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5708 SDValue FIST = Vals.first, StackSlot = Vals.second; 5709 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5710 if (FIST.getNode() == 0) return Op; 5711 5712 // Load the result. 5713 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5714 FIST, StackSlot, NULL, 0, false, false, 0); 5715} 5716 5717SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5718 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5719 SDValue FIST = Vals.first, StackSlot = Vals.second; 5720 assert(FIST.getNode() && "Unexpected failure"); 5721 5722 // Load the result. 5723 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5724 FIST, StackSlot, NULL, 0, false, false, 0); 5725} 5726 5727SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5728 LLVMContext *Context = DAG.getContext(); 5729 DebugLoc dl = Op.getDebugLoc(); 5730 EVT VT = Op.getValueType(); 5731 EVT EltVT = VT; 5732 if (VT.isVector()) 5733 EltVT = VT.getVectorElementType(); 5734 std::vector<Constant*> CV; 5735 if (EltVT == MVT::f64) { 5736 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5737 CV.push_back(C); 5738 CV.push_back(C); 5739 } else { 5740 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5741 CV.push_back(C); 5742 CV.push_back(C); 5743 CV.push_back(C); 5744 CV.push_back(C); 5745 } 5746 Constant *C = ConstantVector::get(CV); 5747 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5748 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5749 PseudoSourceValue::getConstantPool(), 0, 5750 false, false, 16); 5751 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5752} 5753 5754SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5755 LLVMContext *Context = DAG.getContext(); 5756 DebugLoc dl = Op.getDebugLoc(); 5757 EVT VT = Op.getValueType(); 5758 EVT EltVT = VT; 5759 if (VT.isVector()) 5760 EltVT = VT.getVectorElementType(); 5761 std::vector<Constant*> CV; 5762 if (EltVT == MVT::f64) { 5763 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5764 CV.push_back(C); 5765 CV.push_back(C); 5766 } else { 5767 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5768 CV.push_back(C); 5769 CV.push_back(C); 5770 CV.push_back(C); 5771 CV.push_back(C); 5772 } 5773 Constant *C = ConstantVector::get(CV); 5774 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5775 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5776 PseudoSourceValue::getConstantPool(), 0, 5777 false, false, 16); 5778 if (VT.isVector()) { 5779 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5780 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5781 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5782 Op.getOperand(0)), 5783 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5784 } else { 5785 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5786 } 5787} 5788 5789SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5790 LLVMContext *Context = DAG.getContext(); 5791 SDValue Op0 = Op.getOperand(0); 5792 SDValue Op1 = Op.getOperand(1); 5793 DebugLoc dl = Op.getDebugLoc(); 5794 EVT VT = Op.getValueType(); 5795 EVT SrcVT = Op1.getValueType(); 5796 5797 // If second operand is smaller, extend it first. 5798 if (SrcVT.bitsLT(VT)) { 5799 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5800 SrcVT = VT; 5801 } 5802 // And if it is bigger, shrink it first. 5803 if (SrcVT.bitsGT(VT)) { 5804 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5805 SrcVT = VT; 5806 } 5807 5808 // At this point the operands and the result should have the same 5809 // type, and that won't be f80 since that is not custom lowered. 5810 5811 // First get the sign bit of second operand. 5812 std::vector<Constant*> CV; 5813 if (SrcVT == MVT::f64) { 5814 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5815 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5816 } else { 5817 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5818 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5819 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5820 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5821 } 5822 Constant *C = ConstantVector::get(CV); 5823 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5824 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5825 PseudoSourceValue::getConstantPool(), 0, 5826 false, false, 16); 5827 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5828 5829 // Shift sign bit right or left if the two operands have different types. 5830 if (SrcVT.bitsGT(VT)) { 5831 // Op0 is MVT::f32, Op1 is MVT::f64. 5832 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5833 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5834 DAG.getConstant(32, MVT::i32)); 5835 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5836 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5837 DAG.getIntPtrConstant(0)); 5838 } 5839 5840 // Clear first operand sign bit. 5841 CV.clear(); 5842 if (VT == MVT::f64) { 5843 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5844 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5845 } else { 5846 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5847 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5848 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5849 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5850 } 5851 C = ConstantVector::get(CV); 5852 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5853 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5854 PseudoSourceValue::getConstantPool(), 0, 5855 false, false, 16); 5856 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5857 5858 // Or the value with the sign bit. 5859 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5860} 5861 5862/// Emit nodes that will be selected as "test Op0,Op0", or something 5863/// equivalent. 5864SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5865 SelectionDAG &DAG) { 5866 DebugLoc dl = Op.getDebugLoc(); 5867 5868 // CF and OF aren't always set the way we want. Determine which 5869 // of these we need. 5870 bool NeedCF = false; 5871 bool NeedOF = false; 5872 switch (X86CC) { 5873 case X86::COND_A: case X86::COND_AE: 5874 case X86::COND_B: case X86::COND_BE: 5875 NeedCF = true; 5876 break; 5877 case X86::COND_G: case X86::COND_GE: 5878 case X86::COND_L: case X86::COND_LE: 5879 case X86::COND_O: case X86::COND_NO: 5880 NeedOF = true; 5881 break; 5882 default: break; 5883 } 5884 5885 // See if we can use the EFLAGS value from the operand instead of 5886 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5887 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5888 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5889 unsigned Opcode = 0; 5890 unsigned NumOperands = 0; 5891 switch (Op.getNode()->getOpcode()) { 5892 case ISD::ADD: 5893 // Due to an isel shortcoming, be conservative if this add is likely to 5894 // be selected as part of a load-modify-store instruction. When the root 5895 // node in a match is a store, isel doesn't know how to remap non-chain 5896 // non-flag uses of other nodes in the match, such as the ADD in this 5897 // case. This leads to the ADD being left around and reselected, with 5898 // the result being two adds in the output. 5899 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5900 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5901 if (UI->getOpcode() == ISD::STORE) 5902 goto default_case; 5903 if (ConstantSDNode *C = 5904 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5905 // An add of one will be selected as an INC. 5906 if (C->getAPIntValue() == 1) { 5907 Opcode = X86ISD::INC; 5908 NumOperands = 1; 5909 break; 5910 } 5911 // An add of negative one (subtract of one) will be selected as a DEC. 5912 if (C->getAPIntValue().isAllOnesValue()) { 5913 Opcode = X86ISD::DEC; 5914 NumOperands = 1; 5915 break; 5916 } 5917 } 5918 // Otherwise use a regular EFLAGS-setting add. 5919 Opcode = X86ISD::ADD; 5920 NumOperands = 2; 5921 break; 5922 case ISD::AND: { 5923 // If the primary and result isn't used, don't bother using X86ISD::AND, 5924 // because a TEST instruction will be better. 5925 bool NonFlagUse = false; 5926 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5927 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 5928 SDNode *User = *UI; 5929 unsigned UOpNo = UI.getOperandNo(); 5930 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 5931 // Look pass truncate. 5932 UOpNo = User->use_begin().getOperandNo(); 5933 User = *User->use_begin(); 5934 } 5935 if (User->getOpcode() != ISD::BRCOND && 5936 User->getOpcode() != ISD::SETCC && 5937 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 5938 NonFlagUse = true; 5939 break; 5940 } 5941 } 5942 if (!NonFlagUse) 5943 break; 5944 } 5945 // FALL THROUGH 5946 case ISD::SUB: 5947 case ISD::OR: 5948 case ISD::XOR: 5949 // Due to the ISEL shortcoming noted above, be conservative if this op is 5950 // likely to be selected as part of a load-modify-store instruction. 5951 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5952 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5953 if (UI->getOpcode() == ISD::STORE) 5954 goto default_case; 5955 // Otherwise use a regular EFLAGS-setting instruction. 5956 switch (Op.getNode()->getOpcode()) { 5957 case ISD::SUB: Opcode = X86ISD::SUB; break; 5958 case ISD::OR: Opcode = X86ISD::OR; break; 5959 case ISD::XOR: Opcode = X86ISD::XOR; break; 5960 case ISD::AND: Opcode = X86ISD::AND; break; 5961 default: llvm_unreachable("unexpected operator!"); 5962 } 5963 NumOperands = 2; 5964 break; 5965 case X86ISD::ADD: 5966 case X86ISD::SUB: 5967 case X86ISD::INC: 5968 case X86ISD::DEC: 5969 case X86ISD::OR: 5970 case X86ISD::XOR: 5971 case X86ISD::AND: 5972 return SDValue(Op.getNode(), 1); 5973 default: 5974 default_case: 5975 break; 5976 } 5977 if (Opcode != 0) { 5978 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5979 SmallVector<SDValue, 4> Ops; 5980 for (unsigned i = 0; i != NumOperands; ++i) 5981 Ops.push_back(Op.getOperand(i)); 5982 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5983 DAG.ReplaceAllUsesWith(Op, New); 5984 return SDValue(New.getNode(), 1); 5985 } 5986 } 5987 5988 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5989 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5990 DAG.getConstant(0, Op.getValueType())); 5991} 5992 5993/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5994/// equivalent. 5995SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5996 SelectionDAG &DAG) { 5997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5998 if (C->getAPIntValue() == 0) 5999 return EmitTest(Op0, X86CC, DAG); 6000 6001 DebugLoc dl = Op0.getDebugLoc(); 6002 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 6003} 6004 6005/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 6006/// if it's possible. 6007static SDValue LowerToBT(SDValue And, ISD::CondCode CC, 6008 DebugLoc dl, SelectionDAG &DAG) { 6009 SDValue Op0 = And.getOperand(0); 6010 SDValue Op1 = And.getOperand(1); 6011 if (Op0.getOpcode() == ISD::TRUNCATE) 6012 Op0 = Op0.getOperand(0); 6013 if (Op1.getOpcode() == ISD::TRUNCATE) 6014 Op1 = Op1.getOperand(0); 6015 6016 SDValue LHS, RHS; 6017 if (Op1.getOpcode() == ISD::SHL) { 6018 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0))) 6019 if (And10C->getZExtValue() == 1) { 6020 LHS = Op0; 6021 RHS = Op1.getOperand(1); 6022 } 6023 } else if (Op0.getOpcode() == ISD::SHL) { 6024 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 6025 if (And00C->getZExtValue() == 1) { 6026 LHS = Op1; 6027 RHS = Op0.getOperand(1); 6028 } 6029 } else if (Op1.getOpcode() == ISD::Constant) { 6030 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 6031 SDValue AndLHS = Op0; 6032 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 6033 LHS = AndLHS.getOperand(0); 6034 RHS = AndLHS.getOperand(1); 6035 } 6036 } 6037 6038 if (LHS.getNode()) { 6039 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 6040 // instruction. Since the shift amount is in-range-or-undefined, we know 6041 // that doing a bittest on the i16 value is ok. We extend to i32 because 6042 // the encoding for the i16 version is larger than the i32 version. 6043 if (LHS.getValueType() == MVT::i8) 6044 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 6045 6046 // If the operand types disagree, extend the shift amount to match. Since 6047 // BT ignores high bits (like shifts) we can use anyextend. 6048 if (LHS.getValueType() != RHS.getValueType()) 6049 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 6050 6051 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 6052 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 6053 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6054 DAG.getConstant(Cond, MVT::i8), BT); 6055 } 6056 6057 return SDValue(); 6058} 6059 6060SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 6061 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 6062 SDValue Op0 = Op.getOperand(0); 6063 SDValue Op1 = Op.getOperand(1); 6064 DebugLoc dl = Op.getDebugLoc(); 6065 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6066 6067 // Optimize to BT if possible. 6068 // Lower (X & (1 << N)) == 0 to BT(X, N). 6069 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 6070 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 6071 if (Op0.getOpcode() == ISD::AND && 6072 Op0.hasOneUse() && 6073 Op1.getOpcode() == ISD::Constant && 6074 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 6075 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6076 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 6077 if (NewSetCC.getNode()) 6078 return NewSetCC; 6079 } 6080 6081 // Look for "(setcc) == / != 1" to avoid unncessary setcc. 6082 if (Op0.getOpcode() == X86ISD::SETCC && 6083 Op1.getOpcode() == ISD::Constant && 6084 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 6085 cast<ConstantSDNode>(Op1)->isNullValue()) && 6086 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6087 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 6088 bool Invert = (CC == ISD::SETNE) ^ 6089 cast<ConstantSDNode>(Op1)->isNullValue(); 6090 if (Invert) 6091 CCode = X86::GetOppositeBranchCondition(CCode); 6092 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6093 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 6094 } 6095 6096 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6097 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 6098 if (X86CC == X86::COND_INVALID) 6099 return SDValue(); 6100 6101 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 6102 6103 // Use sbb x, x to materialize carry bit into a GPR. 6104 if (X86CC == X86::COND_B) 6105 return DAG.getNode(ISD::AND, dl, MVT::i8, 6106 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 6107 DAG.getConstant(X86CC, MVT::i8), Cond), 6108 DAG.getConstant(1, MVT::i8)); 6109 6110 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6111 DAG.getConstant(X86CC, MVT::i8), Cond); 6112} 6113 6114SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 6115 SDValue Cond; 6116 SDValue Op0 = Op.getOperand(0); 6117 SDValue Op1 = Op.getOperand(1); 6118 SDValue CC = Op.getOperand(2); 6119 EVT VT = Op.getValueType(); 6120 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 6121 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 6122 DebugLoc dl = Op.getDebugLoc(); 6123 6124 if (isFP) { 6125 unsigned SSECC = 8; 6126 EVT VT0 = Op0.getValueType(); 6127 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 6128 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 6129 bool Swap = false; 6130 6131 switch (SetCCOpcode) { 6132 default: break; 6133 case ISD::SETOEQ: 6134 case ISD::SETEQ: SSECC = 0; break; 6135 case ISD::SETOGT: 6136 case ISD::SETGT: Swap = true; // Fallthrough 6137 case ISD::SETLT: 6138 case ISD::SETOLT: SSECC = 1; break; 6139 case ISD::SETOGE: 6140 case ISD::SETGE: Swap = true; // Fallthrough 6141 case ISD::SETLE: 6142 case ISD::SETOLE: SSECC = 2; break; 6143 case ISD::SETUO: SSECC = 3; break; 6144 case ISD::SETUNE: 6145 case ISD::SETNE: SSECC = 4; break; 6146 case ISD::SETULE: Swap = true; 6147 case ISD::SETUGE: SSECC = 5; break; 6148 case ISD::SETULT: Swap = true; 6149 case ISD::SETUGT: SSECC = 6; break; 6150 case ISD::SETO: SSECC = 7; break; 6151 } 6152 if (Swap) 6153 std::swap(Op0, Op1); 6154 6155 // In the two special cases we can't handle, emit two comparisons. 6156 if (SSECC == 8) { 6157 if (SetCCOpcode == ISD::SETUEQ) { 6158 SDValue UNORD, EQ; 6159 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6160 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6161 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6162 } 6163 else if (SetCCOpcode == ISD::SETONE) { 6164 SDValue ORD, NEQ; 6165 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6166 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6167 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6168 } 6169 llvm_unreachable("Illegal FP comparison"); 6170 } 6171 // Handle all other FP comparisons here. 6172 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6173 } 6174 6175 // We are handling one of the integer comparisons here. Since SSE only has 6176 // GT and EQ comparisons for integer, swapping operands and multiple 6177 // operations may be required for some comparisons. 6178 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6179 bool Swap = false, Invert = false, FlipSigns = false; 6180 6181 switch (VT.getSimpleVT().SimpleTy) { 6182 default: break; 6183 case MVT::v8i8: 6184 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6185 case MVT::v4i16: 6186 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6187 case MVT::v2i32: 6188 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6189 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6190 } 6191 6192 switch (SetCCOpcode) { 6193 default: break; 6194 case ISD::SETNE: Invert = true; 6195 case ISD::SETEQ: Opc = EQOpc; break; 6196 case ISD::SETLT: Swap = true; 6197 case ISD::SETGT: Opc = GTOpc; break; 6198 case ISD::SETGE: Swap = true; 6199 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6200 case ISD::SETULT: Swap = true; 6201 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6202 case ISD::SETUGE: Swap = true; 6203 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6204 } 6205 if (Swap) 6206 std::swap(Op0, Op1); 6207 6208 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6209 // bits of the inputs before performing those operations. 6210 if (FlipSigns) { 6211 EVT EltVT = VT.getVectorElementType(); 6212 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6213 EltVT); 6214 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6215 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6216 SignBits.size()); 6217 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6218 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6219 } 6220 6221 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6222 6223 // If the logical-not of the result is required, perform that now. 6224 if (Invert) 6225 Result = DAG.getNOT(dl, Result, VT); 6226 6227 return Result; 6228} 6229 6230// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6231static bool isX86LogicalCmp(SDValue Op) { 6232 unsigned Opc = Op.getNode()->getOpcode(); 6233 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6234 return true; 6235 if (Op.getResNo() == 1 && 6236 (Opc == X86ISD::ADD || 6237 Opc == X86ISD::SUB || 6238 Opc == X86ISD::SMUL || 6239 Opc == X86ISD::UMUL || 6240 Opc == X86ISD::INC || 6241 Opc == X86ISD::DEC || 6242 Opc == X86ISD::OR || 6243 Opc == X86ISD::XOR || 6244 Opc == X86ISD::AND)) 6245 return true; 6246 6247 return false; 6248} 6249 6250SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 6251 bool addTest = true; 6252 SDValue Cond = Op.getOperand(0); 6253 DebugLoc dl = Op.getDebugLoc(); 6254 SDValue CC; 6255 6256 if (Cond.getOpcode() == ISD::SETCC) { 6257 SDValue NewCond = LowerSETCC(Cond, DAG); 6258 if (NewCond.getNode()) 6259 Cond = NewCond; 6260 } 6261 6262 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6263 SDValue Op1 = Op.getOperand(1); 6264 SDValue Op2 = Op.getOperand(2); 6265 if (Cond.getOpcode() == X86ISD::SETCC && 6266 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6267 SDValue Cmp = Cond.getOperand(1); 6268 if (Cmp.getOpcode() == X86ISD::CMP) { 6269 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6270 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6271 ConstantSDNode *RHSC = 6272 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6273 if (N1C && N1C->isAllOnesValue() && 6274 N2C && N2C->isNullValue() && 6275 RHSC && RHSC->isNullValue()) { 6276 SDValue CmpOp0 = Cmp.getOperand(0); 6277 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 6278 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6279 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6280 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6281 } 6282 } 6283 } 6284 6285 // Look pass (and (setcc_carry (cmp ...)), 1). 6286 if (Cond.getOpcode() == ISD::AND && 6287 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6288 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6289 if (C && C->getAPIntValue() == 1) 6290 Cond = Cond.getOperand(0); 6291 } 6292 6293 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6294 // setting operand in place of the X86ISD::SETCC. 6295 if (Cond.getOpcode() == X86ISD::SETCC || 6296 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6297 CC = Cond.getOperand(0); 6298 6299 SDValue Cmp = Cond.getOperand(1); 6300 unsigned Opc = Cmp.getOpcode(); 6301 EVT VT = Op.getValueType(); 6302 6303 bool IllegalFPCMov = false; 6304 if (VT.isFloatingPoint() && !VT.isVector() && 6305 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6306 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6307 6308 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6309 Opc == X86ISD::BT) { // FIXME 6310 Cond = Cmp; 6311 addTest = false; 6312 } 6313 } 6314 6315 if (addTest) { 6316 // Look pass the truncate. 6317 if (Cond.getOpcode() == ISD::TRUNCATE) 6318 Cond = Cond.getOperand(0); 6319 6320 // We know the result of AND is compared against zero. Try to match 6321 // it to BT. 6322 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6323 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6324 if (NewSetCC.getNode()) { 6325 CC = NewSetCC.getOperand(0); 6326 Cond = NewSetCC.getOperand(1); 6327 addTest = false; 6328 } 6329 } 6330 } 6331 6332 if (addTest) { 6333 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6334 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6335 } 6336 6337 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6338 // condition is true. 6339 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6340 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6341 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6342} 6343 6344// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6345// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6346// from the AND / OR. 6347static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6348 Opc = Op.getOpcode(); 6349 if (Opc != ISD::OR && Opc != ISD::AND) 6350 return false; 6351 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6352 Op.getOperand(0).hasOneUse() && 6353 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6354 Op.getOperand(1).hasOneUse()); 6355} 6356 6357// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6358// 1 and that the SETCC node has a single use. 6359static bool isXor1OfSetCC(SDValue Op) { 6360 if (Op.getOpcode() != ISD::XOR) 6361 return false; 6362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6363 if (N1C && N1C->getAPIntValue() == 1) { 6364 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6365 Op.getOperand(0).hasOneUse(); 6366 } 6367 return false; 6368} 6369 6370SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 6371 bool addTest = true; 6372 SDValue Chain = Op.getOperand(0); 6373 SDValue Cond = Op.getOperand(1); 6374 SDValue Dest = Op.getOperand(2); 6375 DebugLoc dl = Op.getDebugLoc(); 6376 SDValue CC; 6377 6378 if (Cond.getOpcode() == ISD::SETCC) { 6379 SDValue NewCond = LowerSETCC(Cond, DAG); 6380 if (NewCond.getNode()) 6381 Cond = NewCond; 6382 } 6383#if 0 6384 // FIXME: LowerXALUO doesn't handle these!! 6385 else if (Cond.getOpcode() == X86ISD::ADD || 6386 Cond.getOpcode() == X86ISD::SUB || 6387 Cond.getOpcode() == X86ISD::SMUL || 6388 Cond.getOpcode() == X86ISD::UMUL) 6389 Cond = LowerXALUO(Cond, DAG); 6390#endif 6391 6392 // Look pass (and (setcc_carry (cmp ...)), 1). 6393 if (Cond.getOpcode() == ISD::AND && 6394 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6395 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6396 if (C && C->getAPIntValue() == 1) 6397 Cond = Cond.getOperand(0); 6398 } 6399 6400 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6401 // setting operand in place of the X86ISD::SETCC. 6402 if (Cond.getOpcode() == X86ISD::SETCC || 6403 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6404 CC = Cond.getOperand(0); 6405 6406 SDValue Cmp = Cond.getOperand(1); 6407 unsigned Opc = Cmp.getOpcode(); 6408 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6409 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6410 Cond = Cmp; 6411 addTest = false; 6412 } else { 6413 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6414 default: break; 6415 case X86::COND_O: 6416 case X86::COND_B: 6417 // These can only come from an arithmetic instruction with overflow, 6418 // e.g. SADDO, UADDO. 6419 Cond = Cond.getNode()->getOperand(1); 6420 addTest = false; 6421 break; 6422 } 6423 } 6424 } else { 6425 unsigned CondOpc; 6426 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6427 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6428 if (CondOpc == ISD::OR) { 6429 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6430 // two branches instead of an explicit OR instruction with a 6431 // separate test. 6432 if (Cmp == Cond.getOperand(1).getOperand(1) && 6433 isX86LogicalCmp(Cmp)) { 6434 CC = Cond.getOperand(0).getOperand(0); 6435 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6436 Chain, Dest, CC, Cmp); 6437 CC = Cond.getOperand(1).getOperand(0); 6438 Cond = Cmp; 6439 addTest = false; 6440 } 6441 } else { // ISD::AND 6442 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6443 // two branches instead of an explicit AND instruction with a 6444 // separate test. However, we only do this if this block doesn't 6445 // have a fall-through edge, because this requires an explicit 6446 // jmp when the condition is false. 6447 if (Cmp == Cond.getOperand(1).getOperand(1) && 6448 isX86LogicalCmp(Cmp) && 6449 Op.getNode()->hasOneUse()) { 6450 X86::CondCode CCode = 6451 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6452 CCode = X86::GetOppositeBranchCondition(CCode); 6453 CC = DAG.getConstant(CCode, MVT::i8); 6454 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 6455 // Look for an unconditional branch following this conditional branch. 6456 // We need this because we need to reverse the successors in order 6457 // to implement FCMP_OEQ. 6458 if (User.getOpcode() == ISD::BR) { 6459 SDValue FalseBB = User.getOperand(1); 6460 SDValue NewBR = 6461 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 6462 assert(NewBR == User); 6463 Dest = FalseBB; 6464 6465 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6466 Chain, Dest, CC, Cmp); 6467 X86::CondCode CCode = 6468 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 6469 CCode = X86::GetOppositeBranchCondition(CCode); 6470 CC = DAG.getConstant(CCode, MVT::i8); 6471 Cond = Cmp; 6472 addTest = false; 6473 } 6474 } 6475 } 6476 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 6477 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 6478 // It should be transformed during dag combiner except when the condition 6479 // is set by a arithmetics with overflow node. 6480 X86::CondCode CCode = 6481 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6482 CCode = X86::GetOppositeBranchCondition(CCode); 6483 CC = DAG.getConstant(CCode, MVT::i8); 6484 Cond = Cond.getOperand(0).getOperand(1); 6485 addTest = false; 6486 } 6487 } 6488 6489 if (addTest) { 6490 // Look pass the truncate. 6491 if (Cond.getOpcode() == ISD::TRUNCATE) 6492 Cond = Cond.getOperand(0); 6493 6494 // We know the result of AND is compared against zero. Try to match 6495 // it to BT. 6496 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6497 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6498 if (NewSetCC.getNode()) { 6499 CC = NewSetCC.getOperand(0); 6500 Cond = NewSetCC.getOperand(1); 6501 addTest = false; 6502 } 6503 } 6504 } 6505 6506 if (addTest) { 6507 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6508 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6509 } 6510 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6511 Chain, Dest, CC, Cond); 6512} 6513 6514 6515// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 6516// Calls to _alloca is needed to probe the stack when allocating more than 4k 6517// bytes in one go. Touching the stack at 4K increments is necessary to ensure 6518// that the guard pages used by the OS virtual memory manager are allocated in 6519// correct sequence. 6520SDValue 6521X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 6522 SelectionDAG &DAG) { 6523 assert(Subtarget->isTargetCygMing() && 6524 "This should be used only on Cygwin/Mingw targets"); 6525 DebugLoc dl = Op.getDebugLoc(); 6526 6527 // Get the inputs. 6528 SDValue Chain = Op.getOperand(0); 6529 SDValue Size = Op.getOperand(1); 6530 // FIXME: Ensure alignment here 6531 6532 SDValue Flag; 6533 6534 EVT IntPtr = getPointerTy(); 6535 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 6536 6537 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 6538 Flag = Chain.getValue(1); 6539 6540 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6541 6542 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag); 6543 Flag = Chain.getValue(1); 6544 6545 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 6546 6547 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 6548 return DAG.getMergeValues(Ops1, 2, dl); 6549} 6550 6551SDValue 6552X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 6553 SDValue Chain, 6554 SDValue Dst, SDValue Src, 6555 SDValue Size, unsigned Align, 6556 const Value *DstSV, 6557 uint64_t DstSVOff) { 6558 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6559 6560 // If not DWORD aligned or size is more than the threshold, call the library. 6561 // The libc version is likely to be faster for these cases. It can use the 6562 // address value and run time information about the CPU. 6563 if ((Align & 3) != 0 || 6564 !ConstantSize || 6565 ConstantSize->getZExtValue() > 6566 getSubtarget()->getMaxInlineSizeThreshold()) { 6567 SDValue InFlag(0, 0); 6568 6569 // Check to see if there is a specialized entry-point for memory zeroing. 6570 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 6571 6572 if (const char *bzeroEntry = V && 6573 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 6574 EVT IntPtr = getPointerTy(); 6575 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 6576 TargetLowering::ArgListTy Args; 6577 TargetLowering::ArgListEntry Entry; 6578 Entry.Node = Dst; 6579 Entry.Ty = IntPtrTy; 6580 Args.push_back(Entry); 6581 Entry.Node = Size; 6582 Args.push_back(Entry); 6583 std::pair<SDValue,SDValue> CallResult = 6584 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 6585 false, false, false, false, 6586 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 6587 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 6588 return CallResult.second; 6589 } 6590 6591 // Otherwise have the target-independent code call memset. 6592 return SDValue(); 6593 } 6594 6595 uint64_t SizeVal = ConstantSize->getZExtValue(); 6596 SDValue InFlag(0, 0); 6597 EVT AVT; 6598 SDValue Count; 6599 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 6600 unsigned BytesLeft = 0; 6601 bool TwoRepStos = false; 6602 if (ValC) { 6603 unsigned ValReg; 6604 uint64_t Val = ValC->getZExtValue() & 255; 6605 6606 // If the value is a constant, then we can potentially use larger sets. 6607 switch (Align & 3) { 6608 case 2: // WORD aligned 6609 AVT = MVT::i16; 6610 ValReg = X86::AX; 6611 Val = (Val << 8) | Val; 6612 break; 6613 case 0: // DWORD aligned 6614 AVT = MVT::i32; 6615 ValReg = X86::EAX; 6616 Val = (Val << 8) | Val; 6617 Val = (Val << 16) | Val; 6618 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 6619 AVT = MVT::i64; 6620 ValReg = X86::RAX; 6621 Val = (Val << 32) | Val; 6622 } 6623 break; 6624 default: // Byte aligned 6625 AVT = MVT::i8; 6626 ValReg = X86::AL; 6627 Count = DAG.getIntPtrConstant(SizeVal); 6628 break; 6629 } 6630 6631 if (AVT.bitsGT(MVT::i8)) { 6632 unsigned UBytes = AVT.getSizeInBits() / 8; 6633 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 6634 BytesLeft = SizeVal % UBytes; 6635 } 6636 6637 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 6638 InFlag); 6639 InFlag = Chain.getValue(1); 6640 } else { 6641 AVT = MVT::i8; 6642 Count = DAG.getIntPtrConstant(SizeVal); 6643 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 6644 InFlag = Chain.getValue(1); 6645 } 6646 6647 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6648 X86::ECX, 6649 Count, InFlag); 6650 InFlag = Chain.getValue(1); 6651 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6652 X86::EDI, 6653 Dst, InFlag); 6654 InFlag = Chain.getValue(1); 6655 6656 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6657 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6658 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6659 6660 if (TwoRepStos) { 6661 InFlag = Chain.getValue(1); 6662 Count = Size; 6663 EVT CVT = Count.getValueType(); 6664 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 6665 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 6666 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 6667 X86::ECX, 6668 Left, InFlag); 6669 InFlag = Chain.getValue(1); 6670 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6671 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; 6672 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6673 } else if (BytesLeft) { 6674 // Handle the last 1 - 7 bytes. 6675 unsigned Offset = SizeVal - BytesLeft; 6676 EVT AddrVT = Dst.getValueType(); 6677 EVT SizeVT = Size.getValueType(); 6678 6679 Chain = DAG.getMemset(Chain, dl, 6680 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 6681 DAG.getConstant(Offset, AddrVT)), 6682 Src, 6683 DAG.getConstant(BytesLeft, SizeVT), 6684 Align, DstSV, DstSVOff + Offset); 6685 } 6686 6687 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 6688 return Chain; 6689} 6690 6691SDValue 6692X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 6693 SDValue Chain, SDValue Dst, SDValue Src, 6694 SDValue Size, unsigned Align, 6695 bool AlwaysInline, 6696 const Value *DstSV, uint64_t DstSVOff, 6697 const Value *SrcSV, uint64_t SrcSVOff) { 6698 // This requires the copy size to be a constant, preferrably 6699 // within a subtarget-specific limit. 6700 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6701 if (!ConstantSize) 6702 return SDValue(); 6703 uint64_t SizeVal = ConstantSize->getZExtValue(); 6704 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 6705 return SDValue(); 6706 6707 /// If not DWORD aligned, call the library. 6708 if ((Align & 3) != 0) 6709 return SDValue(); 6710 6711 // DWORD aligned 6712 EVT AVT = MVT::i32; 6713 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 6714 AVT = MVT::i64; 6715 6716 unsigned UBytes = AVT.getSizeInBits() / 8; 6717 unsigned CountVal = SizeVal / UBytes; 6718 SDValue Count = DAG.getIntPtrConstant(CountVal); 6719 unsigned BytesLeft = SizeVal % UBytes; 6720 6721 SDValue InFlag(0, 0); 6722 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6723 X86::ECX, 6724 Count, InFlag); 6725 InFlag = Chain.getValue(1); 6726 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6727 X86::EDI, 6728 Dst, InFlag); 6729 InFlag = Chain.getValue(1); 6730 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6731 X86::ESI, 6732 Src, InFlag); 6733 InFlag = Chain.getValue(1); 6734 6735 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6736 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6737 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops, 6738 array_lengthof(Ops)); 6739 6740 SmallVector<SDValue, 4> Results; 6741 Results.push_back(RepMovs); 6742 if (BytesLeft) { 6743 // Handle the last 1 - 7 bytes. 6744 unsigned Offset = SizeVal - BytesLeft; 6745 EVT DstVT = Dst.getValueType(); 6746 EVT SrcVT = Src.getValueType(); 6747 EVT SizeVT = Size.getValueType(); 6748 Results.push_back(DAG.getMemcpy(Chain, dl, 6749 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6750 DAG.getConstant(Offset, DstVT)), 6751 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6752 DAG.getConstant(Offset, SrcVT)), 6753 DAG.getConstant(BytesLeft, SizeVT), 6754 Align, AlwaysInline, 6755 DstSV, DstSVOff + Offset, 6756 SrcSV, SrcSVOff + Offset)); 6757 } 6758 6759 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6760 &Results[0], Results.size()); 6761} 6762 6763SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6764 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6765 DebugLoc dl = Op.getDebugLoc(); 6766 6767 if (!Subtarget->is64Bit()) { 6768 // vastart just stores the address of the VarArgsFrameIndex slot into the 6769 // memory location argument. 6770 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6771 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 6772 false, false, 0); 6773 } 6774 6775 // __va_list_tag: 6776 // gp_offset (0 - 6 * 8) 6777 // fp_offset (48 - 48 + 8 * 16) 6778 // overflow_arg_area (point to parameters coming in memory). 6779 // reg_save_area 6780 SmallVector<SDValue, 8> MemOps; 6781 SDValue FIN = Op.getOperand(1); 6782 // Store gp_offset 6783 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6784 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6785 FIN, SV, 0, false, false, 0); 6786 MemOps.push_back(Store); 6787 6788 // Store fp_offset 6789 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6790 FIN, DAG.getIntPtrConstant(4)); 6791 Store = DAG.getStore(Op.getOperand(0), dl, 6792 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6793 FIN, SV, 0, false, false, 0); 6794 MemOps.push_back(Store); 6795 6796 // Store ptr to overflow_arg_area 6797 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6798 FIN, DAG.getIntPtrConstant(4)); 6799 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6800 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0, 6801 false, false, 0); 6802 MemOps.push_back(Store); 6803 6804 // Store ptr to reg_save_area. 6805 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6806 FIN, DAG.getIntPtrConstant(8)); 6807 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6808 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0, 6809 false, false, 0); 6810 MemOps.push_back(Store); 6811 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6812 &MemOps[0], MemOps.size()); 6813} 6814 6815SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6816 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6817 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6818 SDValue Chain = Op.getOperand(0); 6819 SDValue SrcPtr = Op.getOperand(1); 6820 SDValue SrcSV = Op.getOperand(2); 6821 6822 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6823 return SDValue(); 6824} 6825 6826SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6827 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6828 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6829 SDValue Chain = Op.getOperand(0); 6830 SDValue DstPtr = Op.getOperand(1); 6831 SDValue SrcPtr = Op.getOperand(2); 6832 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6833 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6834 DebugLoc dl = Op.getDebugLoc(); 6835 6836 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6837 DAG.getIntPtrConstant(24), 8, false, 6838 DstSV, 0, SrcSV, 0); 6839} 6840 6841SDValue 6842X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6843 DebugLoc dl = Op.getDebugLoc(); 6844 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6845 switch (IntNo) { 6846 default: return SDValue(); // Don't custom lower most intrinsics. 6847 // Comparison intrinsics. 6848 case Intrinsic::x86_sse_comieq_ss: 6849 case Intrinsic::x86_sse_comilt_ss: 6850 case Intrinsic::x86_sse_comile_ss: 6851 case Intrinsic::x86_sse_comigt_ss: 6852 case Intrinsic::x86_sse_comige_ss: 6853 case Intrinsic::x86_sse_comineq_ss: 6854 case Intrinsic::x86_sse_ucomieq_ss: 6855 case Intrinsic::x86_sse_ucomilt_ss: 6856 case Intrinsic::x86_sse_ucomile_ss: 6857 case Intrinsic::x86_sse_ucomigt_ss: 6858 case Intrinsic::x86_sse_ucomige_ss: 6859 case Intrinsic::x86_sse_ucomineq_ss: 6860 case Intrinsic::x86_sse2_comieq_sd: 6861 case Intrinsic::x86_sse2_comilt_sd: 6862 case Intrinsic::x86_sse2_comile_sd: 6863 case Intrinsic::x86_sse2_comigt_sd: 6864 case Intrinsic::x86_sse2_comige_sd: 6865 case Intrinsic::x86_sse2_comineq_sd: 6866 case Intrinsic::x86_sse2_ucomieq_sd: 6867 case Intrinsic::x86_sse2_ucomilt_sd: 6868 case Intrinsic::x86_sse2_ucomile_sd: 6869 case Intrinsic::x86_sse2_ucomigt_sd: 6870 case Intrinsic::x86_sse2_ucomige_sd: 6871 case Intrinsic::x86_sse2_ucomineq_sd: { 6872 unsigned Opc = 0; 6873 ISD::CondCode CC = ISD::SETCC_INVALID; 6874 switch (IntNo) { 6875 default: break; 6876 case Intrinsic::x86_sse_comieq_ss: 6877 case Intrinsic::x86_sse2_comieq_sd: 6878 Opc = X86ISD::COMI; 6879 CC = ISD::SETEQ; 6880 break; 6881 case Intrinsic::x86_sse_comilt_ss: 6882 case Intrinsic::x86_sse2_comilt_sd: 6883 Opc = X86ISD::COMI; 6884 CC = ISD::SETLT; 6885 break; 6886 case Intrinsic::x86_sse_comile_ss: 6887 case Intrinsic::x86_sse2_comile_sd: 6888 Opc = X86ISD::COMI; 6889 CC = ISD::SETLE; 6890 break; 6891 case Intrinsic::x86_sse_comigt_ss: 6892 case Intrinsic::x86_sse2_comigt_sd: 6893 Opc = X86ISD::COMI; 6894 CC = ISD::SETGT; 6895 break; 6896 case Intrinsic::x86_sse_comige_ss: 6897 case Intrinsic::x86_sse2_comige_sd: 6898 Opc = X86ISD::COMI; 6899 CC = ISD::SETGE; 6900 break; 6901 case Intrinsic::x86_sse_comineq_ss: 6902 case Intrinsic::x86_sse2_comineq_sd: 6903 Opc = X86ISD::COMI; 6904 CC = ISD::SETNE; 6905 break; 6906 case Intrinsic::x86_sse_ucomieq_ss: 6907 case Intrinsic::x86_sse2_ucomieq_sd: 6908 Opc = X86ISD::UCOMI; 6909 CC = ISD::SETEQ; 6910 break; 6911 case Intrinsic::x86_sse_ucomilt_ss: 6912 case Intrinsic::x86_sse2_ucomilt_sd: 6913 Opc = X86ISD::UCOMI; 6914 CC = ISD::SETLT; 6915 break; 6916 case Intrinsic::x86_sse_ucomile_ss: 6917 case Intrinsic::x86_sse2_ucomile_sd: 6918 Opc = X86ISD::UCOMI; 6919 CC = ISD::SETLE; 6920 break; 6921 case Intrinsic::x86_sse_ucomigt_ss: 6922 case Intrinsic::x86_sse2_ucomigt_sd: 6923 Opc = X86ISD::UCOMI; 6924 CC = ISD::SETGT; 6925 break; 6926 case Intrinsic::x86_sse_ucomige_ss: 6927 case Intrinsic::x86_sse2_ucomige_sd: 6928 Opc = X86ISD::UCOMI; 6929 CC = ISD::SETGE; 6930 break; 6931 case Intrinsic::x86_sse_ucomineq_ss: 6932 case Intrinsic::x86_sse2_ucomineq_sd: 6933 Opc = X86ISD::UCOMI; 6934 CC = ISD::SETNE; 6935 break; 6936 } 6937 6938 SDValue LHS = Op.getOperand(1); 6939 SDValue RHS = Op.getOperand(2); 6940 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6941 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 6942 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6943 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6944 DAG.getConstant(X86CC, MVT::i8), Cond); 6945 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6946 } 6947 // ptest intrinsics. The intrinsic these come from are designed to return 6948 // an integer value, not just an instruction so lower it to the ptest 6949 // pattern and a setcc for the result. 6950 case Intrinsic::x86_sse41_ptestz: 6951 case Intrinsic::x86_sse41_ptestc: 6952 case Intrinsic::x86_sse41_ptestnzc:{ 6953 unsigned X86CC = 0; 6954 switch (IntNo) { 6955 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6956 case Intrinsic::x86_sse41_ptestz: 6957 // ZF = 1 6958 X86CC = X86::COND_E; 6959 break; 6960 case Intrinsic::x86_sse41_ptestc: 6961 // CF = 1 6962 X86CC = X86::COND_B; 6963 break; 6964 case Intrinsic::x86_sse41_ptestnzc: 6965 // ZF and CF = 0 6966 X86CC = X86::COND_A; 6967 break; 6968 } 6969 6970 SDValue LHS = Op.getOperand(1); 6971 SDValue RHS = Op.getOperand(2); 6972 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6973 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6974 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6975 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6976 } 6977 6978 // Fix vector shift instructions where the last operand is a non-immediate 6979 // i32 value. 6980 case Intrinsic::x86_sse2_pslli_w: 6981 case Intrinsic::x86_sse2_pslli_d: 6982 case Intrinsic::x86_sse2_pslli_q: 6983 case Intrinsic::x86_sse2_psrli_w: 6984 case Intrinsic::x86_sse2_psrli_d: 6985 case Intrinsic::x86_sse2_psrli_q: 6986 case Intrinsic::x86_sse2_psrai_w: 6987 case Intrinsic::x86_sse2_psrai_d: 6988 case Intrinsic::x86_mmx_pslli_w: 6989 case Intrinsic::x86_mmx_pslli_d: 6990 case Intrinsic::x86_mmx_pslli_q: 6991 case Intrinsic::x86_mmx_psrli_w: 6992 case Intrinsic::x86_mmx_psrli_d: 6993 case Intrinsic::x86_mmx_psrli_q: 6994 case Intrinsic::x86_mmx_psrai_w: 6995 case Intrinsic::x86_mmx_psrai_d: { 6996 SDValue ShAmt = Op.getOperand(2); 6997 if (isa<ConstantSDNode>(ShAmt)) 6998 return SDValue(); 6999 7000 unsigned NewIntNo = 0; 7001 EVT ShAmtVT = MVT::v4i32; 7002 switch (IntNo) { 7003 case Intrinsic::x86_sse2_pslli_w: 7004 NewIntNo = Intrinsic::x86_sse2_psll_w; 7005 break; 7006 case Intrinsic::x86_sse2_pslli_d: 7007 NewIntNo = Intrinsic::x86_sse2_psll_d; 7008 break; 7009 case Intrinsic::x86_sse2_pslli_q: 7010 NewIntNo = Intrinsic::x86_sse2_psll_q; 7011 break; 7012 case Intrinsic::x86_sse2_psrli_w: 7013 NewIntNo = Intrinsic::x86_sse2_psrl_w; 7014 break; 7015 case Intrinsic::x86_sse2_psrli_d: 7016 NewIntNo = Intrinsic::x86_sse2_psrl_d; 7017 break; 7018 case Intrinsic::x86_sse2_psrli_q: 7019 NewIntNo = Intrinsic::x86_sse2_psrl_q; 7020 break; 7021 case Intrinsic::x86_sse2_psrai_w: 7022 NewIntNo = Intrinsic::x86_sse2_psra_w; 7023 break; 7024 case Intrinsic::x86_sse2_psrai_d: 7025 NewIntNo = Intrinsic::x86_sse2_psra_d; 7026 break; 7027 default: { 7028 ShAmtVT = MVT::v2i32; 7029 switch (IntNo) { 7030 case Intrinsic::x86_mmx_pslli_w: 7031 NewIntNo = Intrinsic::x86_mmx_psll_w; 7032 break; 7033 case Intrinsic::x86_mmx_pslli_d: 7034 NewIntNo = Intrinsic::x86_mmx_psll_d; 7035 break; 7036 case Intrinsic::x86_mmx_pslli_q: 7037 NewIntNo = Intrinsic::x86_mmx_psll_q; 7038 break; 7039 case Intrinsic::x86_mmx_psrli_w: 7040 NewIntNo = Intrinsic::x86_mmx_psrl_w; 7041 break; 7042 case Intrinsic::x86_mmx_psrli_d: 7043 NewIntNo = Intrinsic::x86_mmx_psrl_d; 7044 break; 7045 case Intrinsic::x86_mmx_psrli_q: 7046 NewIntNo = Intrinsic::x86_mmx_psrl_q; 7047 break; 7048 case Intrinsic::x86_mmx_psrai_w: 7049 NewIntNo = Intrinsic::x86_mmx_psra_w; 7050 break; 7051 case Intrinsic::x86_mmx_psrai_d: 7052 NewIntNo = Intrinsic::x86_mmx_psra_d; 7053 break; 7054 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 7055 } 7056 break; 7057 } 7058 } 7059 7060 // The vector shift intrinsics with scalars uses 32b shift amounts but 7061 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 7062 // to be zero. 7063 SDValue ShOps[4]; 7064 ShOps[0] = ShAmt; 7065 ShOps[1] = DAG.getConstant(0, MVT::i32); 7066 if (ShAmtVT == MVT::v4i32) { 7067 ShOps[2] = DAG.getUNDEF(MVT::i32); 7068 ShOps[3] = DAG.getUNDEF(MVT::i32); 7069 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 7070 } else { 7071 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 7072 } 7073 7074 EVT VT = Op.getValueType(); 7075 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 7076 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7077 DAG.getConstant(NewIntNo, MVT::i32), 7078 Op.getOperand(1), ShAmt); 7079 } 7080 } 7081} 7082 7083SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 7084 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7085 DebugLoc dl = Op.getDebugLoc(); 7086 7087 if (Depth > 0) { 7088 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7089 SDValue Offset = 7090 DAG.getConstant(TD->getPointerSize(), 7091 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 7092 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7093 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7094 FrameAddr, Offset), 7095 NULL, 0, false, false, 0); 7096 } 7097 7098 // Just load the return address. 7099 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 7100 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7101 RetAddrFI, NULL, 0, false, false, 0); 7102} 7103 7104SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 7105 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7106 MFI->setFrameAddressIsTaken(true); 7107 EVT VT = Op.getValueType(); 7108 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 7109 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7110 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 7111 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 7112 while (Depth--) 7113 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 7114 false, false, 0); 7115 return FrameAddr; 7116} 7117 7118SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 7119 SelectionDAG &DAG) { 7120 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 7121} 7122 7123SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 7124{ 7125 MachineFunction &MF = DAG.getMachineFunction(); 7126 SDValue Chain = Op.getOperand(0); 7127 SDValue Offset = Op.getOperand(1); 7128 SDValue Handler = Op.getOperand(2); 7129 DebugLoc dl = Op.getDebugLoc(); 7130 7131 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 7132 getPointerTy()); 7133 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 7134 7135 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 7136 DAG.getIntPtrConstant(-TD->getPointerSize())); 7137 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 7138 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 7139 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7140 MF.getRegInfo().addLiveOut(StoreAddrReg); 7141 7142 return DAG.getNode(X86ISD::EH_RETURN, dl, 7143 MVT::Other, 7144 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7145} 7146 7147SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7148 SelectionDAG &DAG) { 7149 SDValue Root = Op.getOperand(0); 7150 SDValue Trmp = Op.getOperand(1); // trampoline 7151 SDValue FPtr = Op.getOperand(2); // nested function 7152 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7153 DebugLoc dl = Op.getDebugLoc(); 7154 7155 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7156 7157 if (Subtarget->is64Bit()) { 7158 SDValue OutChains[6]; 7159 7160 // Large code-model. 7161 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7162 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7163 7164 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7165 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7166 7167 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7168 7169 // Load the pointer to the nested function into R11. 7170 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7171 SDValue Addr = Trmp; 7172 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7173 Addr, TrmpAddr, 0, false, false, 0); 7174 7175 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7176 DAG.getConstant(2, MVT::i64)); 7177 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7178 false, false, 2); 7179 7180 // Load the 'nest' parameter value into R10. 7181 // R10 is specified in X86CallingConv.td 7182 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7183 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7184 DAG.getConstant(10, MVT::i64)); 7185 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7186 Addr, TrmpAddr, 10, false, false, 0); 7187 7188 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7189 DAG.getConstant(12, MVT::i64)); 7190 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7191 false, false, 2); 7192 7193 // Jump to the nested function. 7194 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7195 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7196 DAG.getConstant(20, MVT::i64)); 7197 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7198 Addr, TrmpAddr, 20, false, false, 0); 7199 7200 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7201 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7202 DAG.getConstant(22, MVT::i64)); 7203 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7204 TrmpAddr, 22, false, false, 0); 7205 7206 SDValue Ops[] = 7207 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7208 return DAG.getMergeValues(Ops, 2, dl); 7209 } else { 7210 const Function *Func = 7211 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7212 CallingConv::ID CC = Func->getCallingConv(); 7213 unsigned NestReg; 7214 7215 switch (CC) { 7216 default: 7217 llvm_unreachable("Unsupported calling convention"); 7218 case CallingConv::C: 7219 case CallingConv::X86_StdCall: { 7220 // Pass 'nest' parameter in ECX. 7221 // Must be kept in sync with X86CallingConv.td 7222 NestReg = X86::ECX; 7223 7224 // Check that ECX wasn't needed by an 'inreg' parameter. 7225 const FunctionType *FTy = Func->getFunctionType(); 7226 const AttrListPtr &Attrs = Func->getAttributes(); 7227 7228 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7229 unsigned InRegCount = 0; 7230 unsigned Idx = 1; 7231 7232 for (FunctionType::param_iterator I = FTy->param_begin(), 7233 E = FTy->param_end(); I != E; ++I, ++Idx) 7234 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7235 // FIXME: should only count parameters that are lowered to integers. 7236 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7237 7238 if (InRegCount > 2) { 7239 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 7240 } 7241 } 7242 break; 7243 } 7244 case CallingConv::X86_FastCall: 7245 case CallingConv::Fast: 7246 // Pass 'nest' parameter in EAX. 7247 // Must be kept in sync with X86CallingConv.td 7248 NestReg = X86::EAX; 7249 break; 7250 } 7251 7252 SDValue OutChains[4]; 7253 SDValue Addr, Disp; 7254 7255 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7256 DAG.getConstant(10, MVT::i32)); 7257 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7258 7259 // This is storing the opcode for MOV32ri. 7260 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7261 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7262 OutChains[0] = DAG.getStore(Root, dl, 7263 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7264 Trmp, TrmpAddr, 0, false, false, 0); 7265 7266 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7267 DAG.getConstant(1, MVT::i32)); 7268 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7269 false, false, 1); 7270 7271 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7272 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7273 DAG.getConstant(5, MVT::i32)); 7274 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7275 TrmpAddr, 5, false, false, 1); 7276 7277 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7278 DAG.getConstant(6, MVT::i32)); 7279 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7280 false, false, 1); 7281 7282 SDValue Ops[] = 7283 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7284 return DAG.getMergeValues(Ops, 2, dl); 7285 } 7286} 7287 7288SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 7289 /* 7290 The rounding mode is in bits 11:10 of FPSR, and has the following 7291 settings: 7292 00 Round to nearest 7293 01 Round to -inf 7294 10 Round to +inf 7295 11 Round to 0 7296 7297 FLT_ROUNDS, on the other hand, expects the following: 7298 -1 Undefined 7299 0 Round to 0 7300 1 Round to nearest 7301 2 Round to +inf 7302 3 Round to -inf 7303 7304 To perform the conversion, we do: 7305 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7306 */ 7307 7308 MachineFunction &MF = DAG.getMachineFunction(); 7309 const TargetMachine &TM = MF.getTarget(); 7310 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7311 unsigned StackAlignment = TFI.getStackAlignment(); 7312 EVT VT = Op.getValueType(); 7313 DebugLoc dl = Op.getDebugLoc(); 7314 7315 // Save FP Control Word to stack slot 7316 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7317 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7318 7319 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7320 DAG.getEntryNode(), StackSlot); 7321 7322 // Load FP Control Word from stack slot 7323 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7324 false, false, 0); 7325 7326 // Transform as necessary 7327 SDValue CWD1 = 7328 DAG.getNode(ISD::SRL, dl, MVT::i16, 7329 DAG.getNode(ISD::AND, dl, MVT::i16, 7330 CWD, DAG.getConstant(0x800, MVT::i16)), 7331 DAG.getConstant(11, MVT::i8)); 7332 SDValue CWD2 = 7333 DAG.getNode(ISD::SRL, dl, MVT::i16, 7334 DAG.getNode(ISD::AND, dl, MVT::i16, 7335 CWD, DAG.getConstant(0x400, MVT::i16)), 7336 DAG.getConstant(9, MVT::i8)); 7337 7338 SDValue RetVal = 7339 DAG.getNode(ISD::AND, dl, MVT::i16, 7340 DAG.getNode(ISD::ADD, dl, MVT::i16, 7341 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7342 DAG.getConstant(1, MVT::i16)), 7343 DAG.getConstant(3, MVT::i16)); 7344 7345 7346 return DAG.getNode((VT.getSizeInBits() < 16 ? 7347 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7348} 7349 7350SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 7351 EVT VT = Op.getValueType(); 7352 EVT OpVT = VT; 7353 unsigned NumBits = VT.getSizeInBits(); 7354 DebugLoc dl = Op.getDebugLoc(); 7355 7356 Op = Op.getOperand(0); 7357 if (VT == MVT::i8) { 7358 // Zero extend to i32 since there is not an i8 bsr. 7359 OpVT = MVT::i32; 7360 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7361 } 7362 7363 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7364 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7365 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7366 7367 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7368 SDValue Ops[] = { 7369 Op, 7370 DAG.getConstant(NumBits+NumBits-1, OpVT), 7371 DAG.getConstant(X86::COND_E, MVT::i8), 7372 Op.getValue(1) 7373 }; 7374 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7375 7376 // Finally xor with NumBits-1. 7377 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7378 7379 if (VT == MVT::i8) 7380 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7381 return Op; 7382} 7383 7384SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 7385 EVT VT = Op.getValueType(); 7386 EVT OpVT = VT; 7387 unsigned NumBits = VT.getSizeInBits(); 7388 DebugLoc dl = Op.getDebugLoc(); 7389 7390 Op = Op.getOperand(0); 7391 if (VT == MVT::i8) { 7392 OpVT = MVT::i32; 7393 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7394 } 7395 7396 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7397 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7398 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7399 7400 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7401 SDValue Ops[] = { 7402 Op, 7403 DAG.getConstant(NumBits, OpVT), 7404 DAG.getConstant(X86::COND_E, MVT::i8), 7405 Op.getValue(1) 7406 }; 7407 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7408 7409 if (VT == MVT::i8) 7410 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7411 return Op; 7412} 7413 7414SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 7415 EVT VT = Op.getValueType(); 7416 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7417 DebugLoc dl = Op.getDebugLoc(); 7418 7419 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7420 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7421 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7422 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7423 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7424 // 7425 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7426 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7427 // return AloBlo + AloBhi + AhiBlo; 7428 7429 SDValue A = Op.getOperand(0); 7430 SDValue B = Op.getOperand(1); 7431 7432 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7433 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7434 A, DAG.getConstant(32, MVT::i32)); 7435 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7436 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7437 B, DAG.getConstant(32, MVT::i32)); 7438 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7439 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7440 A, B); 7441 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7442 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7443 A, Bhi); 7444 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7445 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7446 Ahi, B); 7447 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7448 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7449 AloBhi, DAG.getConstant(32, MVT::i32)); 7450 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7451 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7452 AhiBlo, DAG.getConstant(32, MVT::i32)); 7453 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7454 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7455 return Res; 7456} 7457 7458 7459SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 7460 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7461 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7462 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7463 // has only one use. 7464 SDNode *N = Op.getNode(); 7465 SDValue LHS = N->getOperand(0); 7466 SDValue RHS = N->getOperand(1); 7467 unsigned BaseOp = 0; 7468 unsigned Cond = 0; 7469 DebugLoc dl = Op.getDebugLoc(); 7470 7471 switch (Op.getOpcode()) { 7472 default: llvm_unreachable("Unknown ovf instruction!"); 7473 case ISD::SADDO: 7474 // A subtract of one will be selected as a INC. Note that INC doesn't 7475 // set CF, so we can't do this for UADDO. 7476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7477 if (C->getAPIntValue() == 1) { 7478 BaseOp = X86ISD::INC; 7479 Cond = X86::COND_O; 7480 break; 7481 } 7482 BaseOp = X86ISD::ADD; 7483 Cond = X86::COND_O; 7484 break; 7485 case ISD::UADDO: 7486 BaseOp = X86ISD::ADD; 7487 Cond = X86::COND_B; 7488 break; 7489 case ISD::SSUBO: 7490 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7491 // set CF, so we can't do this for USUBO. 7492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7493 if (C->getAPIntValue() == 1) { 7494 BaseOp = X86ISD::DEC; 7495 Cond = X86::COND_O; 7496 break; 7497 } 7498 BaseOp = X86ISD::SUB; 7499 Cond = X86::COND_O; 7500 break; 7501 case ISD::USUBO: 7502 BaseOp = X86ISD::SUB; 7503 Cond = X86::COND_B; 7504 break; 7505 case ISD::SMULO: 7506 BaseOp = X86ISD::SMUL; 7507 Cond = X86::COND_O; 7508 break; 7509 case ISD::UMULO: 7510 BaseOp = X86ISD::UMUL; 7511 Cond = X86::COND_B; 7512 break; 7513 } 7514 7515 // Also sets EFLAGS. 7516 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7517 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7518 7519 SDValue SetCC = 7520 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7521 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7522 7523 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7524 return Sum; 7525} 7526 7527SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 7528 EVT T = Op.getValueType(); 7529 DebugLoc dl = Op.getDebugLoc(); 7530 unsigned Reg = 0; 7531 unsigned size = 0; 7532 switch(T.getSimpleVT().SimpleTy) { 7533 default: 7534 assert(false && "Invalid value type!"); 7535 case MVT::i8: Reg = X86::AL; size = 1; break; 7536 case MVT::i16: Reg = X86::AX; size = 2; break; 7537 case MVT::i32: Reg = X86::EAX; size = 4; break; 7538 case MVT::i64: 7539 assert(Subtarget->is64Bit() && "Node not type legal!"); 7540 Reg = X86::RAX; size = 8; 7541 break; 7542 } 7543 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 7544 Op.getOperand(2), SDValue()); 7545 SDValue Ops[] = { cpIn.getValue(0), 7546 Op.getOperand(1), 7547 Op.getOperand(3), 7548 DAG.getTargetConstant(size, MVT::i8), 7549 cpIn.getValue(1) }; 7550 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7551 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 7552 SDValue cpOut = 7553 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 7554 return cpOut; 7555} 7556 7557SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 7558 SelectionDAG &DAG) { 7559 assert(Subtarget->is64Bit() && "Result not type legalized?"); 7560 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7561 SDValue TheChain = Op.getOperand(0); 7562 DebugLoc dl = Op.getDebugLoc(); 7563 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7564 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 7565 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 7566 rax.getValue(2)); 7567 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 7568 DAG.getConstant(32, MVT::i8)); 7569 SDValue Ops[] = { 7570 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 7571 rdx.getValue(1) 7572 }; 7573 return DAG.getMergeValues(Ops, 2, dl); 7574} 7575 7576SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 7577 SDNode *Node = Op.getNode(); 7578 DebugLoc dl = Node->getDebugLoc(); 7579 EVT T = Node->getValueType(0); 7580 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 7581 DAG.getConstant(0, T), Node->getOperand(2)); 7582 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 7583 cast<AtomicSDNode>(Node)->getMemoryVT(), 7584 Node->getOperand(0), 7585 Node->getOperand(1), negOp, 7586 cast<AtomicSDNode>(Node)->getSrcValue(), 7587 cast<AtomicSDNode>(Node)->getAlignment()); 7588} 7589 7590/// LowerOperation - Provide custom lowering hooks for some operations. 7591/// 7592SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 7593 switch (Op.getOpcode()) { 7594 default: llvm_unreachable("Should not custom lower this!"); 7595 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 7596 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 7597 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 7598 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 7599 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 7600 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 7601 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 7602 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 7603 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 7604 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 7605 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 7606 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 7607 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 7608 case ISD::SHL_PARTS: 7609 case ISD::SRA_PARTS: 7610 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 7611 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 7612 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 7613 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 7614 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 7615 case ISD::FABS: return LowerFABS(Op, DAG); 7616 case ISD::FNEG: return LowerFNEG(Op, DAG); 7617 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 7618 case ISD::SETCC: return LowerSETCC(Op, DAG); 7619 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 7620 case ISD::SELECT: return LowerSELECT(Op, DAG); 7621 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 7622 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 7623 case ISD::VASTART: return LowerVASTART(Op, DAG); 7624 case ISD::VAARG: return LowerVAARG(Op, DAG); 7625 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 7626 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 7627 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 7628 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 7629 case ISD::FRAME_TO_ARGS_OFFSET: 7630 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 7631 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 7632 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 7633 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 7634 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 7635 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 7636 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 7637 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 7638 case ISD::SADDO: 7639 case ISD::UADDO: 7640 case ISD::SSUBO: 7641 case ISD::USUBO: 7642 case ISD::SMULO: 7643 case ISD::UMULO: return LowerXALUO(Op, DAG); 7644 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 7645 } 7646} 7647 7648void X86TargetLowering:: 7649ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 7650 SelectionDAG &DAG, unsigned NewOp) { 7651 EVT T = Node->getValueType(0); 7652 DebugLoc dl = Node->getDebugLoc(); 7653 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 7654 7655 SDValue Chain = Node->getOperand(0); 7656 SDValue In1 = Node->getOperand(1); 7657 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7658 Node->getOperand(2), DAG.getIntPtrConstant(0)); 7659 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7660 Node->getOperand(2), DAG.getIntPtrConstant(1)); 7661 SDValue Ops[] = { Chain, In1, In2L, In2H }; 7662 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 7663 SDValue Result = 7664 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 7665 cast<MemSDNode>(Node)->getMemOperand()); 7666 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 7667 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7668 Results.push_back(Result.getValue(2)); 7669} 7670 7671/// ReplaceNodeResults - Replace a node with an illegal result type 7672/// with a new node built out of custom code. 7673void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7674 SmallVectorImpl<SDValue>&Results, 7675 SelectionDAG &DAG) { 7676 DebugLoc dl = N->getDebugLoc(); 7677 switch (N->getOpcode()) { 7678 default: 7679 assert(false && "Do not know how to custom type legalize this operation!"); 7680 return; 7681 case ISD::FP_TO_SINT: { 7682 std::pair<SDValue,SDValue> Vals = 7683 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7684 SDValue FIST = Vals.first, StackSlot = Vals.second; 7685 if (FIST.getNode() != 0) { 7686 EVT VT = N->getValueType(0); 7687 // Return a load from the stack slot. 7688 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 7689 false, false, 0)); 7690 } 7691 return; 7692 } 7693 case ISD::READCYCLECOUNTER: { 7694 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7695 SDValue TheChain = N->getOperand(0); 7696 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7697 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7698 rd.getValue(1)); 7699 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7700 eax.getValue(2)); 7701 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7702 SDValue Ops[] = { eax, edx }; 7703 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7704 Results.push_back(edx.getValue(1)); 7705 return; 7706 } 7707 case ISD::ATOMIC_CMP_SWAP: { 7708 EVT T = N->getValueType(0); 7709 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7710 SDValue cpInL, cpInH; 7711 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7712 DAG.getConstant(0, MVT::i32)); 7713 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7714 DAG.getConstant(1, MVT::i32)); 7715 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7716 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7717 cpInL.getValue(1)); 7718 SDValue swapInL, swapInH; 7719 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7720 DAG.getConstant(0, MVT::i32)); 7721 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7722 DAG.getConstant(1, MVT::i32)); 7723 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7724 cpInH.getValue(1)); 7725 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7726 swapInL.getValue(1)); 7727 SDValue Ops[] = { swapInH.getValue(0), 7728 N->getOperand(1), 7729 swapInH.getValue(1) }; 7730 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7731 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7732 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7733 MVT::i32, Result.getValue(1)); 7734 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7735 MVT::i32, cpOutL.getValue(2)); 7736 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7737 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7738 Results.push_back(cpOutH.getValue(1)); 7739 return; 7740 } 7741 case ISD::ATOMIC_LOAD_ADD: 7742 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7743 return; 7744 case ISD::ATOMIC_LOAD_AND: 7745 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7746 return; 7747 case ISD::ATOMIC_LOAD_NAND: 7748 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7749 return; 7750 case ISD::ATOMIC_LOAD_OR: 7751 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7752 return; 7753 case ISD::ATOMIC_LOAD_SUB: 7754 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7755 return; 7756 case ISD::ATOMIC_LOAD_XOR: 7757 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7758 return; 7759 case ISD::ATOMIC_SWAP: 7760 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7761 return; 7762 } 7763} 7764 7765const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7766 switch (Opcode) { 7767 default: return NULL; 7768 case X86ISD::BSF: return "X86ISD::BSF"; 7769 case X86ISD::BSR: return "X86ISD::BSR"; 7770 case X86ISD::SHLD: return "X86ISD::SHLD"; 7771 case X86ISD::SHRD: return "X86ISD::SHRD"; 7772 case X86ISD::FAND: return "X86ISD::FAND"; 7773 case X86ISD::FOR: return "X86ISD::FOR"; 7774 case X86ISD::FXOR: return "X86ISD::FXOR"; 7775 case X86ISD::FSRL: return "X86ISD::FSRL"; 7776 case X86ISD::FILD: return "X86ISD::FILD"; 7777 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7778 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7779 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7780 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7781 case X86ISD::FLD: return "X86ISD::FLD"; 7782 case X86ISD::FST: return "X86ISD::FST"; 7783 case X86ISD::CALL: return "X86ISD::CALL"; 7784 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7785 case X86ISD::BT: return "X86ISD::BT"; 7786 case X86ISD::CMP: return "X86ISD::CMP"; 7787 case X86ISD::COMI: return "X86ISD::COMI"; 7788 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7789 case X86ISD::SETCC: return "X86ISD::SETCC"; 7790 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 7791 case X86ISD::CMOV: return "X86ISD::CMOV"; 7792 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7793 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7794 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7795 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7796 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7797 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7798 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7799 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7800 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7801 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7802 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7803 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7804 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW"; 7805 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7806 case X86ISD::FMAX: return "X86ISD::FMAX"; 7807 case X86ISD::FMIN: return "X86ISD::FMIN"; 7808 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7809 case X86ISD::FRCP: return "X86ISD::FRCP"; 7810 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7811 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7812 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7813 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7814 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7815 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7816 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7817 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7818 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7819 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7820 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7821 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7822 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7823 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7824 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7825 case X86ISD::VSHL: return "X86ISD::VSHL"; 7826 case X86ISD::VSRL: return "X86ISD::VSRL"; 7827 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7828 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7829 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7830 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7831 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7832 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7833 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7834 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7835 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7836 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7837 case X86ISD::ADD: return "X86ISD::ADD"; 7838 case X86ISD::SUB: return "X86ISD::SUB"; 7839 case X86ISD::SMUL: return "X86ISD::SMUL"; 7840 case X86ISD::UMUL: return "X86ISD::UMUL"; 7841 case X86ISD::INC: return "X86ISD::INC"; 7842 case X86ISD::DEC: return "X86ISD::DEC"; 7843 case X86ISD::OR: return "X86ISD::OR"; 7844 case X86ISD::XOR: return "X86ISD::XOR"; 7845 case X86ISD::AND: return "X86ISD::AND"; 7846 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7847 case X86ISD::PTEST: return "X86ISD::PTEST"; 7848 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7849 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA"; 7850 } 7851} 7852 7853// isLegalAddressingMode - Return true if the addressing mode represented 7854// by AM is legal for this target, for a load/store of the specified type. 7855bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7856 const Type *Ty) const { 7857 // X86 supports extremely general addressing modes. 7858 CodeModel::Model M = getTargetMachine().getCodeModel(); 7859 7860 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7861 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7862 return false; 7863 7864 if (AM.BaseGV) { 7865 unsigned GVFlags = 7866 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7867 7868 // If a reference to this global requires an extra load, we can't fold it. 7869 if (isGlobalStubReference(GVFlags)) 7870 return false; 7871 7872 // If BaseGV requires a register for the PIC base, we cannot also have a 7873 // BaseReg specified. 7874 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7875 return false; 7876 7877 // If lower 4G is not available, then we must use rip-relative addressing. 7878 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7879 return false; 7880 } 7881 7882 switch (AM.Scale) { 7883 case 0: 7884 case 1: 7885 case 2: 7886 case 4: 7887 case 8: 7888 // These scales always work. 7889 break; 7890 case 3: 7891 case 5: 7892 case 9: 7893 // These scales are formed with basereg+scalereg. Only accept if there is 7894 // no basereg yet. 7895 if (AM.HasBaseReg) 7896 return false; 7897 break; 7898 default: // Other stuff never works. 7899 return false; 7900 } 7901 7902 return true; 7903} 7904 7905 7906bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7907 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 7908 return false; 7909 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7910 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7911 if (NumBits1 <= NumBits2) 7912 return false; 7913 return true; 7914} 7915 7916bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7917 if (!VT1.isInteger() || !VT2.isInteger()) 7918 return false; 7919 unsigned NumBits1 = VT1.getSizeInBits(); 7920 unsigned NumBits2 = VT2.getSizeInBits(); 7921 if (NumBits1 <= NumBits2) 7922 return false; 7923 return true; 7924} 7925 7926bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7927 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7928 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 7929} 7930 7931bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7932 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7933 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7934} 7935 7936bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7937 // i16 instructions are longer (0x66 prefix) and potentially slower. 7938 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7939} 7940 7941/// isShuffleMaskLegal - Targets can use this to indicate that they only 7942/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7943/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7944/// are assumed to be legal. 7945bool 7946X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7947 EVT VT) const { 7948 // Only do shuffles on 128-bit vector types for now. 7949 if (VT.getSizeInBits() == 64) 7950 return false; 7951 7952 // FIXME: pshufb, blends, shifts. 7953 return (VT.getVectorNumElements() == 2 || 7954 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7955 isMOVLMask(M, VT) || 7956 isSHUFPMask(M, VT) || 7957 isPSHUFDMask(M, VT) || 7958 isPSHUFHWMask(M, VT) || 7959 isPSHUFLWMask(M, VT) || 7960 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 7961 isUNPCKLMask(M, VT) || 7962 isUNPCKHMask(M, VT) || 7963 isUNPCKL_v_undef_Mask(M, VT) || 7964 isUNPCKH_v_undef_Mask(M, VT)); 7965} 7966 7967bool 7968X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7969 EVT VT) const { 7970 unsigned NumElts = VT.getVectorNumElements(); 7971 // FIXME: This collection of masks seems suspect. 7972 if (NumElts == 2) 7973 return true; 7974 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7975 return (isMOVLMask(Mask, VT) || 7976 isCommutedMOVLMask(Mask, VT, true) || 7977 isSHUFPMask(Mask, VT) || 7978 isCommutedSHUFPMask(Mask, VT)); 7979 } 7980 return false; 7981} 7982 7983//===----------------------------------------------------------------------===// 7984// X86 Scheduler Hooks 7985//===----------------------------------------------------------------------===// 7986 7987// private utility function 7988MachineBasicBlock * 7989X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7990 MachineBasicBlock *MBB, 7991 unsigned regOpc, 7992 unsigned immOpc, 7993 unsigned LoadOpc, 7994 unsigned CXchgOpc, 7995 unsigned copyOpc, 7996 unsigned notOpc, 7997 unsigned EAXreg, 7998 TargetRegisterClass *RC, 7999 bool invSrc) const { 8000 // For the atomic bitwise operator, we generate 8001 // thisMBB: 8002 // newMBB: 8003 // ld t1 = [bitinstr.addr] 8004 // op t2 = t1, [bitinstr.val] 8005 // mov EAX = t1 8006 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8007 // bz newMBB 8008 // fallthrough -->nextMBB 8009 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8010 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8011 MachineFunction::iterator MBBIter = MBB; 8012 ++MBBIter; 8013 8014 /// First build the CFG 8015 MachineFunction *F = MBB->getParent(); 8016 MachineBasicBlock *thisMBB = MBB; 8017 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8018 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8019 F->insert(MBBIter, newMBB); 8020 F->insert(MBBIter, nextMBB); 8021 8022 // Move all successors to thisMBB to nextMBB 8023 nextMBB->transferSuccessors(thisMBB); 8024 8025 // Update thisMBB to fall through to newMBB 8026 thisMBB->addSuccessor(newMBB); 8027 8028 // newMBB jumps to itself and fall through to nextMBB 8029 newMBB->addSuccessor(nextMBB); 8030 newMBB->addSuccessor(newMBB); 8031 8032 // Insert instructions into newMBB based on incoming instruction 8033 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 8034 "unexpected number of operands"); 8035 DebugLoc dl = bInstr->getDebugLoc(); 8036 MachineOperand& destOper = bInstr->getOperand(0); 8037 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8038 int numArgs = bInstr->getNumOperands() - 1; 8039 for (int i=0; i < numArgs; ++i) 8040 argOpers[i] = &bInstr->getOperand(i+1); 8041 8042 // x86 address has 4 operands: base, index, scale, and displacement 8043 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8044 int valArgIndx = lastAddrIndx + 1; 8045 8046 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8047 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 8048 for (int i=0; i <= lastAddrIndx; ++i) 8049 (*MIB).addOperand(*argOpers[i]); 8050 8051 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 8052 if (invSrc) { 8053 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 8054 } 8055 else 8056 tt = t1; 8057 8058 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8059 assert((argOpers[valArgIndx]->isReg() || 8060 argOpers[valArgIndx]->isImm()) && 8061 "invalid operand"); 8062 if (argOpers[valArgIndx]->isReg()) 8063 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 8064 else 8065 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 8066 MIB.addReg(tt); 8067 (*MIB).addOperand(*argOpers[valArgIndx]); 8068 8069 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 8070 MIB.addReg(t1); 8071 8072 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 8073 for (int i=0; i <= lastAddrIndx; ++i) 8074 (*MIB).addOperand(*argOpers[i]); 8075 MIB.addReg(t2); 8076 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8077 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8078 bInstr->memoperands_end()); 8079 8080 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 8081 MIB.addReg(EAXreg); 8082 8083 // insert branch 8084 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8085 8086 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8087 return nextMBB; 8088} 8089 8090// private utility function: 64 bit atomics on 32 bit host. 8091MachineBasicBlock * 8092X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 8093 MachineBasicBlock *MBB, 8094 unsigned regOpcL, 8095 unsigned regOpcH, 8096 unsigned immOpcL, 8097 unsigned immOpcH, 8098 bool invSrc) const { 8099 // For the atomic bitwise operator, we generate 8100 // thisMBB (instructions are in pairs, except cmpxchg8b) 8101 // ld t1,t2 = [bitinstr.addr] 8102 // newMBB: 8103 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 8104 // op t5, t6 <- out1, out2, [bitinstr.val] 8105 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 8106 // mov ECX, EBX <- t5, t6 8107 // mov EAX, EDX <- t1, t2 8108 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 8109 // mov t3, t4 <- EAX, EDX 8110 // bz newMBB 8111 // result in out1, out2 8112 // fallthrough -->nextMBB 8113 8114 const TargetRegisterClass *RC = X86::GR32RegisterClass; 8115 const unsigned LoadOpc = X86::MOV32rm; 8116 const unsigned copyOpc = X86::MOV32rr; 8117 const unsigned NotOpc = X86::NOT32r; 8118 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8119 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8120 MachineFunction::iterator MBBIter = MBB; 8121 ++MBBIter; 8122 8123 /// First build the CFG 8124 MachineFunction *F = MBB->getParent(); 8125 MachineBasicBlock *thisMBB = MBB; 8126 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8127 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8128 F->insert(MBBIter, newMBB); 8129 F->insert(MBBIter, nextMBB); 8130 8131 // Move all successors to thisMBB to nextMBB 8132 nextMBB->transferSuccessors(thisMBB); 8133 8134 // Update thisMBB to fall through to newMBB 8135 thisMBB->addSuccessor(newMBB); 8136 8137 // newMBB jumps to itself and fall through to nextMBB 8138 newMBB->addSuccessor(nextMBB); 8139 newMBB->addSuccessor(newMBB); 8140 8141 DebugLoc dl = bInstr->getDebugLoc(); 8142 // Insert instructions into newMBB based on incoming instruction 8143 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8144 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 8145 "unexpected number of operands"); 8146 MachineOperand& dest1Oper = bInstr->getOperand(0); 8147 MachineOperand& dest2Oper = bInstr->getOperand(1); 8148 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8149 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 8150 argOpers[i] = &bInstr->getOperand(i+2); 8151 8152 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8153 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8154 8155 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8156 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8157 for (int i=0; i <= lastAddrIndx; ++i) 8158 (*MIB).addOperand(*argOpers[i]); 8159 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8160 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8161 // add 4 to displacement. 8162 for (int i=0; i <= lastAddrIndx-2; ++i) 8163 (*MIB).addOperand(*argOpers[i]); 8164 MachineOperand newOp3 = *(argOpers[3]); 8165 if (newOp3.isImm()) 8166 newOp3.setImm(newOp3.getImm()+4); 8167 else 8168 newOp3.setOffset(newOp3.getOffset()+4); 8169 (*MIB).addOperand(newOp3); 8170 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8171 8172 // t3/4 are defined later, at the bottom of the loop 8173 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8174 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8175 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8176 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8177 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8178 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8179 8180 // The subsequent operations should be using the destination registers of 8181 //the PHI instructions. 8182 if (invSrc) { 8183 t1 = F->getRegInfo().createVirtualRegister(RC); 8184 t2 = F->getRegInfo().createVirtualRegister(RC); 8185 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8186 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8187 } else { 8188 t1 = dest1Oper.getReg(); 8189 t2 = dest2Oper.getReg(); 8190 } 8191 8192 int valArgIndx = lastAddrIndx + 1; 8193 assert((argOpers[valArgIndx]->isReg() || 8194 argOpers[valArgIndx]->isImm()) && 8195 "invalid operand"); 8196 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8197 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8198 if (argOpers[valArgIndx]->isReg()) 8199 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8200 else 8201 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8202 if (regOpcL != X86::MOV32rr) 8203 MIB.addReg(t1); 8204 (*MIB).addOperand(*argOpers[valArgIndx]); 8205 assert(argOpers[valArgIndx + 1]->isReg() == 8206 argOpers[valArgIndx]->isReg()); 8207 assert(argOpers[valArgIndx + 1]->isImm() == 8208 argOpers[valArgIndx]->isImm()); 8209 if (argOpers[valArgIndx + 1]->isReg()) 8210 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8211 else 8212 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8213 if (regOpcH != X86::MOV32rr) 8214 MIB.addReg(t2); 8215 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8216 8217 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 8218 MIB.addReg(t1); 8219 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 8220 MIB.addReg(t2); 8221 8222 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 8223 MIB.addReg(t5); 8224 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 8225 MIB.addReg(t6); 8226 8227 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8228 for (int i=0; i <= lastAddrIndx; ++i) 8229 (*MIB).addOperand(*argOpers[i]); 8230 8231 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8232 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8233 bInstr->memoperands_end()); 8234 8235 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 8236 MIB.addReg(X86::EAX); 8237 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 8238 MIB.addReg(X86::EDX); 8239 8240 // insert branch 8241 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8242 8243 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8244 return nextMBB; 8245} 8246 8247// private utility function 8248MachineBasicBlock * 8249X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8250 MachineBasicBlock *MBB, 8251 unsigned cmovOpc) const { 8252 // For the atomic min/max operator, we generate 8253 // thisMBB: 8254 // newMBB: 8255 // ld t1 = [min/max.addr] 8256 // mov t2 = [min/max.val] 8257 // cmp t1, t2 8258 // cmov[cond] t2 = t1 8259 // mov EAX = t1 8260 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8261 // bz newMBB 8262 // fallthrough -->nextMBB 8263 // 8264 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8265 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8266 MachineFunction::iterator MBBIter = MBB; 8267 ++MBBIter; 8268 8269 /// First build the CFG 8270 MachineFunction *F = MBB->getParent(); 8271 MachineBasicBlock *thisMBB = MBB; 8272 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8273 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8274 F->insert(MBBIter, newMBB); 8275 F->insert(MBBIter, nextMBB); 8276 8277 // Move all successors of thisMBB to nextMBB 8278 nextMBB->transferSuccessors(thisMBB); 8279 8280 // Update thisMBB to fall through to newMBB 8281 thisMBB->addSuccessor(newMBB); 8282 8283 // newMBB jumps to newMBB and fall through to nextMBB 8284 newMBB->addSuccessor(nextMBB); 8285 newMBB->addSuccessor(newMBB); 8286 8287 DebugLoc dl = mInstr->getDebugLoc(); 8288 // Insert instructions into newMBB based on incoming instruction 8289 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 8290 "unexpected number of operands"); 8291 MachineOperand& destOper = mInstr->getOperand(0); 8292 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8293 int numArgs = mInstr->getNumOperands() - 1; 8294 for (int i=0; i < numArgs; ++i) 8295 argOpers[i] = &mInstr->getOperand(i+1); 8296 8297 // x86 address has 4 operands: base, index, scale, and displacement 8298 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8299 int valArgIndx = lastAddrIndx + 1; 8300 8301 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8302 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8303 for (int i=0; i <= lastAddrIndx; ++i) 8304 (*MIB).addOperand(*argOpers[i]); 8305 8306 // We only support register and immediate values 8307 assert((argOpers[valArgIndx]->isReg() || 8308 argOpers[valArgIndx]->isImm()) && 8309 "invalid operand"); 8310 8311 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8312 if (argOpers[valArgIndx]->isReg()) 8313 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8314 else 8315 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8316 (*MIB).addOperand(*argOpers[valArgIndx]); 8317 8318 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 8319 MIB.addReg(t1); 8320 8321 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8322 MIB.addReg(t1); 8323 MIB.addReg(t2); 8324 8325 // Generate movc 8326 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8327 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8328 MIB.addReg(t2); 8329 MIB.addReg(t1); 8330 8331 // Cmp and exchange if none has modified the memory location 8332 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8333 for (int i=0; i <= lastAddrIndx; ++i) 8334 (*MIB).addOperand(*argOpers[i]); 8335 MIB.addReg(t3); 8336 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8337 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8338 mInstr->memoperands_end()); 8339 8340 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 8341 MIB.addReg(X86::EAX); 8342 8343 // insert branch 8344 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8345 8346 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 8347 return nextMBB; 8348} 8349 8350// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8351// all of this code can be replaced with that in the .td file. 8352MachineBasicBlock * 8353X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8354 unsigned numArgs, bool memArg) const { 8355 8356 MachineFunction *F = BB->getParent(); 8357 DebugLoc dl = MI->getDebugLoc(); 8358 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8359 8360 unsigned Opc; 8361 if (memArg) 8362 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8363 else 8364 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8365 8366 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8367 8368 for (unsigned i = 0; i < numArgs; ++i) { 8369 MachineOperand &Op = MI->getOperand(i+1); 8370 8371 if (!(Op.isReg() && Op.isImplicit())) 8372 MIB.addOperand(Op); 8373 } 8374 8375 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8376 .addReg(X86::XMM0); 8377 8378 F->DeleteMachineInstr(MI); 8379 8380 return BB; 8381} 8382 8383MachineBasicBlock * 8384X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8385 MachineInstr *MI, 8386 MachineBasicBlock *MBB) const { 8387 // Emit code to save XMM registers to the stack. The ABI says that the 8388 // number of registers to save is given in %al, so it's theoretically 8389 // possible to do an indirect jump trick to avoid saving all of them, 8390 // however this code takes a simpler approach and just executes all 8391 // of the stores if %al is non-zero. It's less code, and it's probably 8392 // easier on the hardware branch predictor, and stores aren't all that 8393 // expensive anyway. 8394 8395 // Create the new basic blocks. One block contains all the XMM stores, 8396 // and one block is the final destination regardless of whether any 8397 // stores were performed. 8398 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8399 MachineFunction *F = MBB->getParent(); 8400 MachineFunction::iterator MBBIter = MBB; 8401 ++MBBIter; 8402 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8403 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8404 F->insert(MBBIter, XMMSaveMBB); 8405 F->insert(MBBIter, EndMBB); 8406 8407 // Set up the CFG. 8408 // Move any original successors of MBB to the end block. 8409 EndMBB->transferSuccessors(MBB); 8410 // The original block will now fall through to the XMM save block. 8411 MBB->addSuccessor(XMMSaveMBB); 8412 // The XMMSaveMBB will fall through to the end block. 8413 XMMSaveMBB->addSuccessor(EndMBB); 8414 8415 // Now add the instructions. 8416 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8417 DebugLoc DL = MI->getDebugLoc(); 8418 8419 unsigned CountReg = MI->getOperand(0).getReg(); 8420 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 8421 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 8422 8423 if (!Subtarget->isTargetWin64()) { 8424 // If %al is 0, branch around the XMM save block. 8425 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 8426 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 8427 MBB->addSuccessor(EndMBB); 8428 } 8429 8430 // In the XMM save block, save all the XMM argument registers. 8431 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 8432 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 8433 MachineMemOperand *MMO = 8434 F->getMachineMemOperand( 8435 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 8436 MachineMemOperand::MOStore, Offset, 8437 /*Size=*/16, /*Align=*/16); 8438 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 8439 .addFrameIndex(RegSaveFrameIndex) 8440 .addImm(/*Scale=*/1) 8441 .addReg(/*IndexReg=*/0) 8442 .addImm(/*Disp=*/Offset) 8443 .addReg(/*Segment=*/0) 8444 .addReg(MI->getOperand(i).getReg()) 8445 .addMemOperand(MMO); 8446 } 8447 8448 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8449 8450 return EndMBB; 8451} 8452 8453MachineBasicBlock * 8454X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 8455 MachineBasicBlock *BB, 8456 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8457 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8458 DebugLoc DL = MI->getDebugLoc(); 8459 8460 // To "insert" a SELECT_CC instruction, we actually have to insert the 8461 // diamond control-flow pattern. The incoming instruction knows the 8462 // destination vreg to set, the condition code register to branch on, the 8463 // true/false values to select between, and a branch opcode to use. 8464 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 8465 MachineFunction::iterator It = BB; 8466 ++It; 8467 8468 // thisMBB: 8469 // ... 8470 // TrueVal = ... 8471 // cmpTY ccX, r1, r2 8472 // bCC copy1MBB 8473 // fallthrough --> copy0MBB 8474 MachineBasicBlock *thisMBB = BB; 8475 MachineFunction *F = BB->getParent(); 8476 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 8477 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 8478 unsigned Opc = 8479 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 8480 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 8481 F->insert(It, copy0MBB); 8482 F->insert(It, sinkMBB); 8483 // Update machine-CFG edges by first adding all successors of the current 8484 // block to the new block which will contain the Phi node for the select. 8485 // Also inform sdisel of the edge changes. 8486 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 8487 E = BB->succ_end(); I != E; ++I) { 8488 EM->insert(std::make_pair(*I, sinkMBB)); 8489 sinkMBB->addSuccessor(*I); 8490 } 8491 // Next, remove all successors of the current block, and add the true 8492 // and fallthrough blocks as its successors. 8493 while (!BB->succ_empty()) 8494 BB->removeSuccessor(BB->succ_begin()); 8495 // Add the true and fallthrough blocks as its successors. 8496 BB->addSuccessor(copy0MBB); 8497 BB->addSuccessor(sinkMBB); 8498 8499 // copy0MBB: 8500 // %FalseValue = ... 8501 // # fallthrough to sinkMBB 8502 BB = copy0MBB; 8503 8504 // Update machine-CFG edges 8505 BB->addSuccessor(sinkMBB); 8506 8507 // sinkMBB: 8508 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 8509 // ... 8510 BB = sinkMBB; 8511 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) 8512 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 8513 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 8514 8515 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8516 return BB; 8517} 8518 8519MachineBasicBlock * 8520X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI, 8521 MachineBasicBlock *BB, 8522 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8523 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8524 DebugLoc DL = MI->getDebugLoc(); 8525 MachineFunction *F = BB->getParent(); 8526 8527 // The lowering is pretty easy: we're just emitting the call to _alloca. The 8528 // non-trivial part is impdef of ESP. 8529 // FIXME: The code should be tweaked as soon as we'll try to do codegen for 8530 // mingw-w64. 8531 8532 BuildMI(BB, DL, TII->get(X86::CALLpcrel32)) 8533 .addExternalSymbol("_alloca") 8534 .addReg(X86::EAX, RegState::Implicit) 8535 .addReg(X86::ESP, RegState::Implicit) 8536 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 8537 .addReg(X86::ESP, RegState::Define | RegState::Implicit); 8538 8539 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8540 return BB; 8541} 8542 8543MachineBasicBlock * 8544X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 8545 MachineBasicBlock *BB, 8546 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8547 switch (MI->getOpcode()) { 8548 default: assert(false && "Unexpected instr type to insert"); 8549 case X86::MINGW_ALLOCA: 8550 return EmitLoweredMingwAlloca(MI, BB, EM); 8551 case X86::CMOV_GR8: 8552 case X86::CMOV_V1I64: 8553 case X86::CMOV_FR32: 8554 case X86::CMOV_FR64: 8555 case X86::CMOV_V4F32: 8556 case X86::CMOV_V2F64: 8557 case X86::CMOV_V2I64: 8558 case X86::CMOV_GR16: 8559 case X86::CMOV_GR32: 8560 case X86::CMOV_RFP32: 8561 case X86::CMOV_RFP64: 8562 case X86::CMOV_RFP80: 8563 return EmitLoweredSelect(MI, BB, EM); 8564 8565 case X86::FP32_TO_INT16_IN_MEM: 8566 case X86::FP32_TO_INT32_IN_MEM: 8567 case X86::FP32_TO_INT64_IN_MEM: 8568 case X86::FP64_TO_INT16_IN_MEM: 8569 case X86::FP64_TO_INT32_IN_MEM: 8570 case X86::FP64_TO_INT64_IN_MEM: 8571 case X86::FP80_TO_INT16_IN_MEM: 8572 case X86::FP80_TO_INT32_IN_MEM: 8573 case X86::FP80_TO_INT64_IN_MEM: { 8574 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8575 DebugLoc DL = MI->getDebugLoc(); 8576 8577 // Change the floating point control register to use "round towards zero" 8578 // mode when truncating to an integer value. 8579 MachineFunction *F = BB->getParent(); 8580 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 8581 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); 8582 8583 // Load the old value of the high byte of the control word... 8584 unsigned OldCW = 8585 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 8586 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), 8587 CWFrameIdx); 8588 8589 // Set the high part to be round to zero... 8590 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 8591 .addImm(0xC7F); 8592 8593 // Reload the modified control word now... 8594 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8595 8596 // Restore the memory image of control word to original value 8597 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 8598 .addReg(OldCW); 8599 8600 // Get the X86 opcode to use. 8601 unsigned Opc; 8602 switch (MI->getOpcode()) { 8603 default: llvm_unreachable("illegal opcode!"); 8604 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 8605 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 8606 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 8607 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 8608 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 8609 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 8610 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 8611 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 8612 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 8613 } 8614 8615 X86AddressMode AM; 8616 MachineOperand &Op = MI->getOperand(0); 8617 if (Op.isReg()) { 8618 AM.BaseType = X86AddressMode::RegBase; 8619 AM.Base.Reg = Op.getReg(); 8620 } else { 8621 AM.BaseType = X86AddressMode::FrameIndexBase; 8622 AM.Base.FrameIndex = Op.getIndex(); 8623 } 8624 Op = MI->getOperand(1); 8625 if (Op.isImm()) 8626 AM.Scale = Op.getImm(); 8627 Op = MI->getOperand(2); 8628 if (Op.isImm()) 8629 AM.IndexReg = Op.getImm(); 8630 Op = MI->getOperand(3); 8631 if (Op.isGlobal()) { 8632 AM.GV = Op.getGlobal(); 8633 } else { 8634 AM.Disp = Op.getImm(); 8635 } 8636 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) 8637 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 8638 8639 // Reload the original control word now. 8640 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8641 8642 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8643 return BB; 8644 } 8645 // DBG_VALUE. Only the frame index case is done here. 8646 case X86::DBG_VALUE: { 8647 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8648 DebugLoc DL = MI->getDebugLoc(); 8649 X86AddressMode AM; 8650 MachineFunction *F = BB->getParent(); 8651 AM.BaseType = X86AddressMode::FrameIndexBase; 8652 AM.Base.FrameIndex = MI->getOperand(0).getImm(); 8653 addFullAddress(BuildMI(BB, DL, TII->get(X86::DBG_VALUE)), AM). 8654 addImm(MI->getOperand(1).getImm()). 8655 addMetadata(MI->getOperand(2).getMetadata()); 8656 F->DeleteMachineInstr(MI); // Remove pseudo. 8657 return BB; 8658 } 8659 8660 // String/text processing lowering. 8661 case X86::PCMPISTRM128REG: 8662 return EmitPCMP(MI, BB, 3, false /* in-mem */); 8663 case X86::PCMPISTRM128MEM: 8664 return EmitPCMP(MI, BB, 3, true /* in-mem */); 8665 case X86::PCMPESTRM128REG: 8666 return EmitPCMP(MI, BB, 5, false /* in mem */); 8667 case X86::PCMPESTRM128MEM: 8668 return EmitPCMP(MI, BB, 5, true /* in mem */); 8669 8670 // Atomic Lowering. 8671 case X86::ATOMAND32: 8672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8673 X86::AND32ri, X86::MOV32rm, 8674 X86::LCMPXCHG32, X86::MOV32rr, 8675 X86::NOT32r, X86::EAX, 8676 X86::GR32RegisterClass); 8677 case X86::ATOMOR32: 8678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 8679 X86::OR32ri, X86::MOV32rm, 8680 X86::LCMPXCHG32, X86::MOV32rr, 8681 X86::NOT32r, X86::EAX, 8682 X86::GR32RegisterClass); 8683 case X86::ATOMXOR32: 8684 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 8685 X86::XOR32ri, X86::MOV32rm, 8686 X86::LCMPXCHG32, X86::MOV32rr, 8687 X86::NOT32r, X86::EAX, 8688 X86::GR32RegisterClass); 8689 case X86::ATOMNAND32: 8690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8691 X86::AND32ri, X86::MOV32rm, 8692 X86::LCMPXCHG32, X86::MOV32rr, 8693 X86::NOT32r, X86::EAX, 8694 X86::GR32RegisterClass, true); 8695 case X86::ATOMMIN32: 8696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 8697 case X86::ATOMMAX32: 8698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 8699 case X86::ATOMUMIN32: 8700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 8701 case X86::ATOMUMAX32: 8702 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 8703 8704 case X86::ATOMAND16: 8705 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8706 X86::AND16ri, X86::MOV16rm, 8707 X86::LCMPXCHG16, X86::MOV16rr, 8708 X86::NOT16r, X86::AX, 8709 X86::GR16RegisterClass); 8710 case X86::ATOMOR16: 8711 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 8712 X86::OR16ri, X86::MOV16rm, 8713 X86::LCMPXCHG16, X86::MOV16rr, 8714 X86::NOT16r, X86::AX, 8715 X86::GR16RegisterClass); 8716 case X86::ATOMXOR16: 8717 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 8718 X86::XOR16ri, X86::MOV16rm, 8719 X86::LCMPXCHG16, X86::MOV16rr, 8720 X86::NOT16r, X86::AX, 8721 X86::GR16RegisterClass); 8722 case X86::ATOMNAND16: 8723 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8724 X86::AND16ri, X86::MOV16rm, 8725 X86::LCMPXCHG16, X86::MOV16rr, 8726 X86::NOT16r, X86::AX, 8727 X86::GR16RegisterClass, true); 8728 case X86::ATOMMIN16: 8729 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8730 case X86::ATOMMAX16: 8731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8732 case X86::ATOMUMIN16: 8733 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8734 case X86::ATOMUMAX16: 8735 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8736 8737 case X86::ATOMAND8: 8738 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8739 X86::AND8ri, X86::MOV8rm, 8740 X86::LCMPXCHG8, X86::MOV8rr, 8741 X86::NOT8r, X86::AL, 8742 X86::GR8RegisterClass); 8743 case X86::ATOMOR8: 8744 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8745 X86::OR8ri, X86::MOV8rm, 8746 X86::LCMPXCHG8, X86::MOV8rr, 8747 X86::NOT8r, X86::AL, 8748 X86::GR8RegisterClass); 8749 case X86::ATOMXOR8: 8750 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8751 X86::XOR8ri, X86::MOV8rm, 8752 X86::LCMPXCHG8, X86::MOV8rr, 8753 X86::NOT8r, X86::AL, 8754 X86::GR8RegisterClass); 8755 case X86::ATOMNAND8: 8756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8757 X86::AND8ri, X86::MOV8rm, 8758 X86::LCMPXCHG8, X86::MOV8rr, 8759 X86::NOT8r, X86::AL, 8760 X86::GR8RegisterClass, true); 8761 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8762 // This group is for 64-bit host. 8763 case X86::ATOMAND64: 8764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8765 X86::AND64ri32, X86::MOV64rm, 8766 X86::LCMPXCHG64, X86::MOV64rr, 8767 X86::NOT64r, X86::RAX, 8768 X86::GR64RegisterClass); 8769 case X86::ATOMOR64: 8770 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8771 X86::OR64ri32, X86::MOV64rm, 8772 X86::LCMPXCHG64, X86::MOV64rr, 8773 X86::NOT64r, X86::RAX, 8774 X86::GR64RegisterClass); 8775 case X86::ATOMXOR64: 8776 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8777 X86::XOR64ri32, X86::MOV64rm, 8778 X86::LCMPXCHG64, X86::MOV64rr, 8779 X86::NOT64r, X86::RAX, 8780 X86::GR64RegisterClass); 8781 case X86::ATOMNAND64: 8782 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8783 X86::AND64ri32, X86::MOV64rm, 8784 X86::LCMPXCHG64, X86::MOV64rr, 8785 X86::NOT64r, X86::RAX, 8786 X86::GR64RegisterClass, true); 8787 case X86::ATOMMIN64: 8788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8789 case X86::ATOMMAX64: 8790 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8791 case X86::ATOMUMIN64: 8792 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8793 case X86::ATOMUMAX64: 8794 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8795 8796 // This group does 64-bit operations on a 32-bit host. 8797 case X86::ATOMAND6432: 8798 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8799 X86::AND32rr, X86::AND32rr, 8800 X86::AND32ri, X86::AND32ri, 8801 false); 8802 case X86::ATOMOR6432: 8803 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8804 X86::OR32rr, X86::OR32rr, 8805 X86::OR32ri, X86::OR32ri, 8806 false); 8807 case X86::ATOMXOR6432: 8808 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8809 X86::XOR32rr, X86::XOR32rr, 8810 X86::XOR32ri, X86::XOR32ri, 8811 false); 8812 case X86::ATOMNAND6432: 8813 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8814 X86::AND32rr, X86::AND32rr, 8815 X86::AND32ri, X86::AND32ri, 8816 true); 8817 case X86::ATOMADD6432: 8818 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8819 X86::ADD32rr, X86::ADC32rr, 8820 X86::ADD32ri, X86::ADC32ri, 8821 false); 8822 case X86::ATOMSUB6432: 8823 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8824 X86::SUB32rr, X86::SBB32rr, 8825 X86::SUB32ri, X86::SBB32ri, 8826 false); 8827 case X86::ATOMSWAP6432: 8828 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8829 X86::MOV32rr, X86::MOV32rr, 8830 X86::MOV32ri, X86::MOV32ri, 8831 false); 8832 case X86::VASTART_SAVE_XMM_REGS: 8833 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8834 } 8835} 8836 8837//===----------------------------------------------------------------------===// 8838// X86 Optimization Hooks 8839//===----------------------------------------------------------------------===// 8840 8841void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8842 const APInt &Mask, 8843 APInt &KnownZero, 8844 APInt &KnownOne, 8845 const SelectionDAG &DAG, 8846 unsigned Depth) const { 8847 unsigned Opc = Op.getOpcode(); 8848 assert((Opc >= ISD::BUILTIN_OP_END || 8849 Opc == ISD::INTRINSIC_WO_CHAIN || 8850 Opc == ISD::INTRINSIC_W_CHAIN || 8851 Opc == ISD::INTRINSIC_VOID) && 8852 "Should use MaskedValueIsZero if you don't know whether Op" 8853 " is a target node!"); 8854 8855 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8856 switch (Opc) { 8857 default: break; 8858 case X86ISD::ADD: 8859 case X86ISD::SUB: 8860 case X86ISD::SMUL: 8861 case X86ISD::UMUL: 8862 case X86ISD::INC: 8863 case X86ISD::DEC: 8864 case X86ISD::OR: 8865 case X86ISD::XOR: 8866 case X86ISD::AND: 8867 // These nodes' second result is a boolean. 8868 if (Op.getResNo() == 0) 8869 break; 8870 // Fallthrough 8871 case X86ISD::SETCC: 8872 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8873 Mask.getBitWidth() - 1); 8874 break; 8875 } 8876} 8877 8878/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8879/// node is a GlobalAddress + offset. 8880bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8881 GlobalValue* &GA, int64_t &Offset) const{ 8882 if (N->getOpcode() == X86ISD::Wrapper) { 8883 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8884 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8885 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8886 return true; 8887 } 8888 } 8889 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8890} 8891 8892/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8893/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8894/// if the load addresses are consecutive, non-overlapping, and in the right 8895/// order. 8896static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8897 const TargetLowering &TLI) { 8898 DebugLoc dl = N->getDebugLoc(); 8899 EVT VT = N->getValueType(0); 8900 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8901 8902 if (VT.getSizeInBits() != 128) 8903 return SDValue(); 8904 8905 SmallVector<SDValue, 16> Elts; 8906 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 8907 Elts.push_back(DAG.getShuffleScalarElt(SVN, i)); 8908 8909 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 8910} 8911 8912/// PerformShuffleCombine - Detect vector gather/scatter index generation 8913/// and convert it from being a bunch of shuffles and extracts to a simple 8914/// store and scalar loads to extract the elements. 8915static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 8916 const TargetLowering &TLI) { 8917 SDValue InputVector = N->getOperand(0); 8918 8919 // Only operate on vectors of 4 elements, where the alternative shuffling 8920 // gets to be more expensive. 8921 if (InputVector.getValueType() != MVT::v4i32) 8922 return SDValue(); 8923 8924 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 8925 // single use which is a sign-extend or zero-extend, and all elements are 8926 // used. 8927 SmallVector<SDNode *, 4> Uses; 8928 unsigned ExtractedElements = 0; 8929 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 8930 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 8931 if (UI.getUse().getResNo() != InputVector.getResNo()) 8932 return SDValue(); 8933 8934 SDNode *Extract = *UI; 8935 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 8936 return SDValue(); 8937 8938 if (Extract->getValueType(0) != MVT::i32) 8939 return SDValue(); 8940 if (!Extract->hasOneUse()) 8941 return SDValue(); 8942 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 8943 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 8944 return SDValue(); 8945 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 8946 return SDValue(); 8947 8948 // Record which element was extracted. 8949 ExtractedElements |= 8950 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 8951 8952 Uses.push_back(Extract); 8953 } 8954 8955 // If not all the elements were used, this may not be worthwhile. 8956 if (ExtractedElements != 15) 8957 return SDValue(); 8958 8959 // Ok, we've now decided to do the transformation. 8960 DebugLoc dl = InputVector.getDebugLoc(); 8961 8962 // Store the value to a temporary stack slot. 8963 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 8964 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0, 8965 false, false, 0); 8966 8967 // Replace each use (extract) with a load of the appropriate element. 8968 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 8969 UE = Uses.end(); UI != UE; ++UI) { 8970 SDNode *Extract = *UI; 8971 8972 // Compute the element's address. 8973 SDValue Idx = Extract->getOperand(1); 8974 unsigned EltSize = 8975 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 8976 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 8977 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 8978 8979 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr); 8980 8981 // Load the scalar. 8982 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr, 8983 NULL, 0, false, false, 0); 8984 8985 // Replace the exact with the load. 8986 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 8987 } 8988 8989 // The replacement was made in place; don't return anything. 8990 return SDValue(); 8991} 8992 8993/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8994static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8995 const X86Subtarget *Subtarget) { 8996 DebugLoc DL = N->getDebugLoc(); 8997 SDValue Cond = N->getOperand(0); 8998 // Get the LHS/RHS of the select. 8999 SDValue LHS = N->getOperand(1); 9000 SDValue RHS = N->getOperand(2); 9001 9002 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 9003 // instructions match the semantics of the common C idiom x<y?x:y but not 9004 // x<=y?x:y, because of how they handle negative zero (which can be 9005 // ignored in unsafe-math mode). 9006 if (Subtarget->hasSSE2() && 9007 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 9008 Cond.getOpcode() == ISD::SETCC) { 9009 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 9010 9011 unsigned Opcode = 0; 9012 // Check for x CC y ? x : y. 9013 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 9014 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 9015 switch (CC) { 9016 default: break; 9017 case ISD::SETULT: 9018 // Converting this to a min would handle NaNs incorrectly, and swapping 9019 // the operands would cause it to handle comparisons between positive 9020 // and negative zero incorrectly. 9021 if (!FiniteOnlyFPMath() && 9022 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { 9023 if (!UnsafeFPMath && 9024 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9025 break; 9026 std::swap(LHS, RHS); 9027 } 9028 Opcode = X86ISD::FMIN; 9029 break; 9030 case ISD::SETOLE: 9031 // Converting this to a min would handle comparisons between positive 9032 // and negative zero incorrectly. 9033 if (!UnsafeFPMath && 9034 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 9035 break; 9036 Opcode = X86ISD::FMIN; 9037 break; 9038 case ISD::SETULE: 9039 // Converting this to a min would handle both negative zeros and NaNs 9040 // incorrectly, but we can swap the operands to fix both. 9041 std::swap(LHS, RHS); 9042 case ISD::SETOLT: 9043 case ISD::SETLT: 9044 case ISD::SETLE: 9045 Opcode = X86ISD::FMIN; 9046 break; 9047 9048 case ISD::SETOGE: 9049 // Converting this to a max would handle comparisons between positive 9050 // and negative zero incorrectly. 9051 if (!UnsafeFPMath && 9052 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS)) 9053 break; 9054 Opcode = X86ISD::FMAX; 9055 break; 9056 case ISD::SETUGT: 9057 // Converting this to a max would handle NaNs incorrectly, and swapping 9058 // the operands would cause it to handle comparisons between positive 9059 // and negative zero incorrectly. 9060 if (!FiniteOnlyFPMath() && 9061 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { 9062 if (!UnsafeFPMath && 9063 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 9064 break; 9065 std::swap(LHS, RHS); 9066 } 9067 Opcode = X86ISD::FMAX; 9068 break; 9069 case ISD::SETUGE: 9070 // Converting this to a max would handle both negative zeros and NaNs 9071 // incorrectly, but we can swap the operands to fix both. 9072 std::swap(LHS, RHS); 9073 case ISD::SETOGT: 9074 case ISD::SETGT: 9075 case ISD::SETGE: 9076 Opcode = X86ISD::FMAX; 9077 break; 9078 } 9079 // Check for x CC y ? y : x -- a min/max with reversed arms. 9080 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 9081 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 9082 switch (CC) { 9083 default: break; 9084 case ISD::SETOGE: 9085 // Converting this to a min would handle comparisons between positive 9086 // and negative zero incorrectly, and swapping the operands would 9087 // cause it to handle NaNs incorrectly. 9088 if (!UnsafeFPMath && 9089 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 9090 if (!FiniteOnlyFPMath() && 9091 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9092 break; 9093 std::swap(LHS, RHS); 9094 } 9095 Opcode = X86ISD::FMIN; 9096 break; 9097 case ISD::SETUGT: 9098 // Converting this to a min would handle NaNs incorrectly. 9099 if (!UnsafeFPMath && 9100 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9101 break; 9102 Opcode = X86ISD::FMIN; 9103 break; 9104 case ISD::SETUGE: 9105 // Converting this to a min would handle both negative zeros and NaNs 9106 // incorrectly, but we can swap the operands to fix both. 9107 std::swap(LHS, RHS); 9108 case ISD::SETOGT: 9109 case ISD::SETGT: 9110 case ISD::SETGE: 9111 Opcode = X86ISD::FMIN; 9112 break; 9113 9114 case ISD::SETULT: 9115 // Converting this to a max would handle NaNs incorrectly. 9116 if (!FiniteOnlyFPMath() && 9117 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9118 break; 9119 Opcode = X86ISD::FMAX; 9120 break; 9121 case ISD::SETOLE: 9122 // Converting this to a max would handle comparisons between positive 9123 // and negative zero incorrectly, and swapping the operands would 9124 // cause it to handle NaNs incorrectly. 9125 if (!UnsafeFPMath && 9126 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 9127 if (!FiniteOnlyFPMath() && 9128 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 9129 break; 9130 std::swap(LHS, RHS); 9131 } 9132 Opcode = X86ISD::FMAX; 9133 break; 9134 case ISD::SETULE: 9135 // Converting this to a max would handle both negative zeros and NaNs 9136 // incorrectly, but we can swap the operands to fix both. 9137 std::swap(LHS, RHS); 9138 case ISD::SETOLT: 9139 case ISD::SETLT: 9140 case ISD::SETLE: 9141 Opcode = X86ISD::FMAX; 9142 break; 9143 } 9144 } 9145 9146 if (Opcode) 9147 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 9148 } 9149 9150 // If this is a select between two integer constants, try to do some 9151 // optimizations. 9152 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 9153 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 9154 // Don't do this for crazy integer types. 9155 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 9156 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 9157 // so that TrueC (the true value) is larger than FalseC. 9158 bool NeedsCondInvert = false; 9159 9160 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 9161 // Efficiently invertible. 9162 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 9163 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 9164 isa<ConstantSDNode>(Cond.getOperand(1))))) { 9165 NeedsCondInvert = true; 9166 std::swap(TrueC, FalseC); 9167 } 9168 9169 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 9170 if (FalseC->getAPIntValue() == 0 && 9171 TrueC->getAPIntValue().isPowerOf2()) { 9172 if (NeedsCondInvert) // Invert the condition if needed. 9173 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9174 DAG.getConstant(1, Cond.getValueType())); 9175 9176 // Zero extend the condition if needed. 9177 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 9178 9179 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9180 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 9181 DAG.getConstant(ShAmt, MVT::i8)); 9182 } 9183 9184 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 9185 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9186 if (NeedsCondInvert) // Invert the condition if needed. 9187 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9188 DAG.getConstant(1, Cond.getValueType())); 9189 9190 // Zero extend the condition if needed. 9191 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9192 FalseC->getValueType(0), Cond); 9193 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9194 SDValue(FalseC, 0)); 9195 } 9196 9197 // Optimize cases that will turn into an LEA instruction. This requires 9198 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9199 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9200 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9201 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9202 9203 bool isFastMultiplier = false; 9204 if (Diff < 10) { 9205 switch ((unsigned char)Diff) { 9206 default: break; 9207 case 1: // result = add base, cond 9208 case 2: // result = lea base( , cond*2) 9209 case 3: // result = lea base(cond, cond*2) 9210 case 4: // result = lea base( , cond*4) 9211 case 5: // result = lea base(cond, cond*4) 9212 case 8: // result = lea base( , cond*8) 9213 case 9: // result = lea base(cond, cond*8) 9214 isFastMultiplier = true; 9215 break; 9216 } 9217 } 9218 9219 if (isFastMultiplier) { 9220 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9221 if (NeedsCondInvert) // Invert the condition if needed. 9222 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9223 DAG.getConstant(1, Cond.getValueType())); 9224 9225 // Zero extend the condition if needed. 9226 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9227 Cond); 9228 // Scale the condition by the difference. 9229 if (Diff != 1) 9230 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9231 DAG.getConstant(Diff, Cond.getValueType())); 9232 9233 // Add the base if non-zero. 9234 if (FalseC->getAPIntValue() != 0) 9235 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9236 SDValue(FalseC, 0)); 9237 return Cond; 9238 } 9239 } 9240 } 9241 } 9242 9243 return SDValue(); 9244} 9245 9246/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9247static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9248 TargetLowering::DAGCombinerInfo &DCI) { 9249 DebugLoc DL = N->getDebugLoc(); 9250 9251 // If the flag operand isn't dead, don't touch this CMOV. 9252 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9253 return SDValue(); 9254 9255 // If this is a select between two integer constants, try to do some 9256 // optimizations. Note that the operands are ordered the opposite of SELECT 9257 // operands. 9258 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9259 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9260 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9261 // larger than FalseC (the false value). 9262 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9263 9264 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9265 CC = X86::GetOppositeBranchCondition(CC); 9266 std::swap(TrueC, FalseC); 9267 } 9268 9269 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9270 // This is efficient for any integer data type (including i8/i16) and 9271 // shift amount. 9272 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9273 SDValue Cond = N->getOperand(3); 9274 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9275 DAG.getConstant(CC, MVT::i8), Cond); 9276 9277 // Zero extend the condition if needed. 9278 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9279 9280 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9281 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9282 DAG.getConstant(ShAmt, MVT::i8)); 9283 if (N->getNumValues() == 2) // Dead flag value? 9284 return DCI.CombineTo(N, Cond, SDValue()); 9285 return Cond; 9286 } 9287 9288 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9289 // for any integer data type, including i8/i16. 9290 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9291 SDValue Cond = N->getOperand(3); 9292 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9293 DAG.getConstant(CC, MVT::i8), Cond); 9294 9295 // Zero extend the condition if needed. 9296 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9297 FalseC->getValueType(0), Cond); 9298 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9299 SDValue(FalseC, 0)); 9300 9301 if (N->getNumValues() == 2) // Dead flag value? 9302 return DCI.CombineTo(N, Cond, SDValue()); 9303 return Cond; 9304 } 9305 9306 // Optimize cases that will turn into an LEA instruction. This requires 9307 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9308 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9309 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9310 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9311 9312 bool isFastMultiplier = false; 9313 if (Diff < 10) { 9314 switch ((unsigned char)Diff) { 9315 default: break; 9316 case 1: // result = add base, cond 9317 case 2: // result = lea base( , cond*2) 9318 case 3: // result = lea base(cond, cond*2) 9319 case 4: // result = lea base( , cond*4) 9320 case 5: // result = lea base(cond, cond*4) 9321 case 8: // result = lea base( , cond*8) 9322 case 9: // result = lea base(cond, cond*8) 9323 isFastMultiplier = true; 9324 break; 9325 } 9326 } 9327 9328 if (isFastMultiplier) { 9329 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9330 SDValue Cond = N->getOperand(3); 9331 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9332 DAG.getConstant(CC, MVT::i8), Cond); 9333 // Zero extend the condition if needed. 9334 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9335 Cond); 9336 // Scale the condition by the difference. 9337 if (Diff != 1) 9338 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9339 DAG.getConstant(Diff, Cond.getValueType())); 9340 9341 // Add the base if non-zero. 9342 if (FalseC->getAPIntValue() != 0) 9343 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9344 SDValue(FalseC, 0)); 9345 if (N->getNumValues() == 2) // Dead flag value? 9346 return DCI.CombineTo(N, Cond, SDValue()); 9347 return Cond; 9348 } 9349 } 9350 } 9351 } 9352 return SDValue(); 9353} 9354 9355 9356/// PerformMulCombine - Optimize a single multiply with constant into two 9357/// in order to implement it with two cheaper instructions, e.g. 9358/// LEA + SHL, LEA + LEA. 9359static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9360 TargetLowering::DAGCombinerInfo &DCI) { 9361 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9362 return SDValue(); 9363 9364 EVT VT = N->getValueType(0); 9365 if (VT != MVT::i64) 9366 return SDValue(); 9367 9368 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9369 if (!C) 9370 return SDValue(); 9371 uint64_t MulAmt = C->getZExtValue(); 9372 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 9373 return SDValue(); 9374 9375 uint64_t MulAmt1 = 0; 9376 uint64_t MulAmt2 = 0; 9377 if ((MulAmt % 9) == 0) { 9378 MulAmt1 = 9; 9379 MulAmt2 = MulAmt / 9; 9380 } else if ((MulAmt % 5) == 0) { 9381 MulAmt1 = 5; 9382 MulAmt2 = MulAmt / 5; 9383 } else if ((MulAmt % 3) == 0) { 9384 MulAmt1 = 3; 9385 MulAmt2 = MulAmt / 3; 9386 } 9387 if (MulAmt2 && 9388 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 9389 DebugLoc DL = N->getDebugLoc(); 9390 9391 if (isPowerOf2_64(MulAmt2) && 9392 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 9393 // If second multiplifer is pow2, issue it first. We want the multiply by 9394 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 9395 // is an add. 9396 std::swap(MulAmt1, MulAmt2); 9397 9398 SDValue NewMul; 9399 if (isPowerOf2_64(MulAmt1)) 9400 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 9401 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 9402 else 9403 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 9404 DAG.getConstant(MulAmt1, VT)); 9405 9406 if (isPowerOf2_64(MulAmt2)) 9407 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 9408 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 9409 else 9410 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 9411 DAG.getConstant(MulAmt2, VT)); 9412 9413 // Do not add new nodes to DAG combiner worklist. 9414 DCI.CombineTo(N, NewMul, false); 9415 } 9416 return SDValue(); 9417} 9418 9419static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 9420 SDValue N0 = N->getOperand(0); 9421 SDValue N1 = N->getOperand(1); 9422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 9423 EVT VT = N0.getValueType(); 9424 9425 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 9426 // since the result of setcc_c is all zero's or all ones. 9427 if (N1C && N0.getOpcode() == ISD::AND && 9428 N0.getOperand(1).getOpcode() == ISD::Constant) { 9429 SDValue N00 = N0.getOperand(0); 9430 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 9431 ((N00.getOpcode() == ISD::ANY_EXTEND || 9432 N00.getOpcode() == ISD::ZERO_EXTEND) && 9433 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 9434 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 9435 APInt ShAmt = N1C->getAPIntValue(); 9436 Mask = Mask.shl(ShAmt); 9437 if (Mask != 0) 9438 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9439 N00, DAG.getConstant(Mask, VT)); 9440 } 9441 } 9442 9443 return SDValue(); 9444} 9445 9446/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 9447/// when possible. 9448static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 9449 const X86Subtarget *Subtarget) { 9450 EVT VT = N->getValueType(0); 9451 if (!VT.isVector() && VT.isInteger() && 9452 N->getOpcode() == ISD::SHL) 9453 return PerformSHLCombine(N, DAG); 9454 9455 // On X86 with SSE2 support, we can transform this to a vector shift if 9456 // all elements are shifted by the same amount. We can't do this in legalize 9457 // because the a constant vector is typically transformed to a constant pool 9458 // so we have no knowledge of the shift amount. 9459 if (!Subtarget->hasSSE2()) 9460 return SDValue(); 9461 9462 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 9463 return SDValue(); 9464 9465 SDValue ShAmtOp = N->getOperand(1); 9466 EVT EltVT = VT.getVectorElementType(); 9467 DebugLoc DL = N->getDebugLoc(); 9468 SDValue BaseShAmt = SDValue(); 9469 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 9470 unsigned NumElts = VT.getVectorNumElements(); 9471 unsigned i = 0; 9472 for (; i != NumElts; ++i) { 9473 SDValue Arg = ShAmtOp.getOperand(i); 9474 if (Arg.getOpcode() == ISD::UNDEF) continue; 9475 BaseShAmt = Arg; 9476 break; 9477 } 9478 for (; i != NumElts; ++i) { 9479 SDValue Arg = ShAmtOp.getOperand(i); 9480 if (Arg.getOpcode() == ISD::UNDEF) continue; 9481 if (Arg != BaseShAmt) { 9482 return SDValue(); 9483 } 9484 } 9485 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 9486 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 9487 SDValue InVec = ShAmtOp.getOperand(0); 9488 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 9489 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 9490 unsigned i = 0; 9491 for (; i != NumElts; ++i) { 9492 SDValue Arg = InVec.getOperand(i); 9493 if (Arg.getOpcode() == ISD::UNDEF) continue; 9494 BaseShAmt = Arg; 9495 break; 9496 } 9497 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 9498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 9499 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 9500 if (C->getZExtValue() == SplatIdx) 9501 BaseShAmt = InVec.getOperand(1); 9502 } 9503 } 9504 if (BaseShAmt.getNode() == 0) 9505 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 9506 DAG.getIntPtrConstant(0)); 9507 } else 9508 return SDValue(); 9509 9510 // The shift amount is an i32. 9511 if (EltVT.bitsGT(MVT::i32)) 9512 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 9513 else if (EltVT.bitsLT(MVT::i32)) 9514 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 9515 9516 // The shift amount is identical so we can do a vector shift. 9517 SDValue ValOp = N->getOperand(0); 9518 switch (N->getOpcode()) { 9519 default: 9520 llvm_unreachable("Unknown shift opcode!"); 9521 break; 9522 case ISD::SHL: 9523 if (VT == MVT::v2i64) 9524 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9525 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9526 ValOp, BaseShAmt); 9527 if (VT == MVT::v4i32) 9528 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9529 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9530 ValOp, BaseShAmt); 9531 if (VT == MVT::v8i16) 9532 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9533 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9534 ValOp, BaseShAmt); 9535 break; 9536 case ISD::SRA: 9537 if (VT == MVT::v4i32) 9538 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9539 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9540 ValOp, BaseShAmt); 9541 if (VT == MVT::v8i16) 9542 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9543 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9544 ValOp, BaseShAmt); 9545 break; 9546 case ISD::SRL: 9547 if (VT == MVT::v2i64) 9548 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9549 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9550 ValOp, BaseShAmt); 9551 if (VT == MVT::v4i32) 9552 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9553 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9554 ValOp, BaseShAmt); 9555 if (VT == MVT::v8i16) 9556 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9557 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9558 ValOp, BaseShAmt); 9559 break; 9560 } 9561 return SDValue(); 9562} 9563 9564static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 9565 const X86Subtarget *Subtarget) { 9566 EVT VT = N->getValueType(0); 9567 if (VT != MVT::i64 || !Subtarget->is64Bit()) 9568 return SDValue(); 9569 9570 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 9571 SDValue N0 = N->getOperand(0); 9572 SDValue N1 = N->getOperand(1); 9573 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 9574 std::swap(N0, N1); 9575 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 9576 return SDValue(); 9577 9578 SDValue ShAmt0 = N0.getOperand(1); 9579 if (ShAmt0.getValueType() != MVT::i8) 9580 return SDValue(); 9581 SDValue ShAmt1 = N1.getOperand(1); 9582 if (ShAmt1.getValueType() != MVT::i8) 9583 return SDValue(); 9584 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 9585 ShAmt0 = ShAmt0.getOperand(0); 9586 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 9587 ShAmt1 = ShAmt1.getOperand(0); 9588 9589 DebugLoc DL = N->getDebugLoc(); 9590 unsigned Opc = X86ISD::SHLD; 9591 SDValue Op0 = N0.getOperand(0); 9592 SDValue Op1 = N1.getOperand(0); 9593 if (ShAmt0.getOpcode() == ISD::SUB) { 9594 Opc = X86ISD::SHRD; 9595 std::swap(Op0, Op1); 9596 std::swap(ShAmt0, ShAmt1); 9597 } 9598 9599 if (ShAmt1.getOpcode() == ISD::SUB) { 9600 SDValue Sum = ShAmt1.getOperand(0); 9601 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 9602 if (SumC->getSExtValue() == 64 && 9603 ShAmt1.getOperand(1) == ShAmt0) 9604 return DAG.getNode(Opc, DL, VT, 9605 Op0, Op1, 9606 DAG.getNode(ISD::TRUNCATE, DL, 9607 MVT::i8, ShAmt0)); 9608 } 9609 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 9610 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 9611 if (ShAmt0C && 9612 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64) 9613 return DAG.getNode(Opc, DL, VT, 9614 N0.getOperand(0), N1.getOperand(0), 9615 DAG.getNode(ISD::TRUNCATE, DL, 9616 MVT::i8, ShAmt0)); 9617 } 9618 9619 return SDValue(); 9620} 9621 9622/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 9623static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 9624 const X86Subtarget *Subtarget) { 9625 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 9626 // the FP state in cases where an emms may be missing. 9627 // A preferable solution to the general problem is to figure out the right 9628 // places to insert EMMS. This qualifies as a quick hack. 9629 9630 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 9631 StoreSDNode *St = cast<StoreSDNode>(N); 9632 EVT VT = St->getValue().getValueType(); 9633 if (VT.getSizeInBits() != 64) 9634 return SDValue(); 9635 9636 const Function *F = DAG.getMachineFunction().getFunction(); 9637 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 9638 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 9639 && Subtarget->hasSSE2(); 9640 if ((VT.isVector() || 9641 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 9642 isa<LoadSDNode>(St->getValue()) && 9643 !cast<LoadSDNode>(St->getValue())->isVolatile() && 9644 St->getChain().hasOneUse() && !St->isVolatile()) { 9645 SDNode* LdVal = St->getValue().getNode(); 9646 LoadSDNode *Ld = 0; 9647 int TokenFactorIndex = -1; 9648 SmallVector<SDValue, 8> Ops; 9649 SDNode* ChainVal = St->getChain().getNode(); 9650 // Must be a store of a load. We currently handle two cases: the load 9651 // is a direct child, and it's under an intervening TokenFactor. It is 9652 // possible to dig deeper under nested TokenFactors. 9653 if (ChainVal == LdVal) 9654 Ld = cast<LoadSDNode>(St->getChain()); 9655 else if (St->getValue().hasOneUse() && 9656 ChainVal->getOpcode() == ISD::TokenFactor) { 9657 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 9658 if (ChainVal->getOperand(i).getNode() == LdVal) { 9659 TokenFactorIndex = i; 9660 Ld = cast<LoadSDNode>(St->getValue()); 9661 } else 9662 Ops.push_back(ChainVal->getOperand(i)); 9663 } 9664 } 9665 9666 if (!Ld || !ISD::isNormalLoad(Ld)) 9667 return SDValue(); 9668 9669 // If this is not the MMX case, i.e. we are just turning i64 load/store 9670 // into f64 load/store, avoid the transformation if there are multiple 9671 // uses of the loaded value. 9672 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 9673 return SDValue(); 9674 9675 DebugLoc LdDL = Ld->getDebugLoc(); 9676 DebugLoc StDL = N->getDebugLoc(); 9677 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 9678 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 9679 // pair instead. 9680 if (Subtarget->is64Bit() || F64IsLegal) { 9681 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 9682 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 9683 Ld->getBasePtr(), Ld->getSrcValue(), 9684 Ld->getSrcValueOffset(), Ld->isVolatile(), 9685 Ld->isNonTemporal(), Ld->getAlignment()); 9686 SDValue NewChain = NewLd.getValue(1); 9687 if (TokenFactorIndex != -1) { 9688 Ops.push_back(NewChain); 9689 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9690 Ops.size()); 9691 } 9692 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 9693 St->getSrcValue(), St->getSrcValueOffset(), 9694 St->isVolatile(), St->isNonTemporal(), 9695 St->getAlignment()); 9696 } 9697 9698 // Otherwise, lower to two pairs of 32-bit loads / stores. 9699 SDValue LoAddr = Ld->getBasePtr(); 9700 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 9701 DAG.getConstant(4, MVT::i32)); 9702 9703 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 9704 Ld->getSrcValue(), Ld->getSrcValueOffset(), 9705 Ld->isVolatile(), Ld->isNonTemporal(), 9706 Ld->getAlignment()); 9707 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 9708 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 9709 Ld->isVolatile(), Ld->isNonTemporal(), 9710 MinAlign(Ld->getAlignment(), 4)); 9711 9712 SDValue NewChain = LoLd.getValue(1); 9713 if (TokenFactorIndex != -1) { 9714 Ops.push_back(LoLd); 9715 Ops.push_back(HiLd); 9716 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9717 Ops.size()); 9718 } 9719 9720 LoAddr = St->getBasePtr(); 9721 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 9722 DAG.getConstant(4, MVT::i32)); 9723 9724 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 9725 St->getSrcValue(), St->getSrcValueOffset(), 9726 St->isVolatile(), St->isNonTemporal(), 9727 St->getAlignment()); 9728 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 9729 St->getSrcValue(), 9730 St->getSrcValueOffset() + 4, 9731 St->isVolatile(), 9732 St->isNonTemporal(), 9733 MinAlign(St->getAlignment(), 4)); 9734 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 9735 } 9736 return SDValue(); 9737} 9738 9739/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 9740/// X86ISD::FXOR nodes. 9741static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 9742 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 9743 // F[X]OR(0.0, x) -> x 9744 // F[X]OR(x, 0.0) -> x 9745 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9746 if (C->getValueAPF().isPosZero()) 9747 return N->getOperand(1); 9748 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9749 if (C->getValueAPF().isPosZero()) 9750 return N->getOperand(0); 9751 return SDValue(); 9752} 9753 9754/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 9755static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 9756 // FAND(0.0, x) -> 0.0 9757 // FAND(x, 0.0) -> 0.0 9758 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9759 if (C->getValueAPF().isPosZero()) 9760 return N->getOperand(0); 9761 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9762 if (C->getValueAPF().isPosZero()) 9763 return N->getOperand(1); 9764 return SDValue(); 9765} 9766 9767static SDValue PerformBTCombine(SDNode *N, 9768 SelectionDAG &DAG, 9769 TargetLowering::DAGCombinerInfo &DCI) { 9770 // BT ignores high bits in the bit index operand. 9771 SDValue Op1 = N->getOperand(1); 9772 if (Op1.hasOneUse()) { 9773 unsigned BitWidth = Op1.getValueSizeInBits(); 9774 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 9775 APInt KnownZero, KnownOne; 9776 TargetLowering::TargetLoweringOpt TLO(DAG); 9777 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9778 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 9779 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 9780 DCI.CommitTargetLoweringOpt(TLO); 9781 } 9782 return SDValue(); 9783} 9784 9785static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 9786 SDValue Op = N->getOperand(0); 9787 if (Op.getOpcode() == ISD::BIT_CONVERT) 9788 Op = Op.getOperand(0); 9789 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 9790 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 9791 VT.getVectorElementType().getSizeInBits() == 9792 OpVT.getVectorElementType().getSizeInBits()) { 9793 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 9794 } 9795 return SDValue(); 9796} 9797 9798// On X86 and X86-64, atomic operations are lowered to locked instructions. 9799// Locked instructions, in turn, have implicit fence semantics (all memory 9800// operations are flushed before issuing the locked instruction, and the 9801// are not buffered), so we can fold away the common pattern of 9802// fence-atomic-fence. 9803static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 9804 SDValue atomic = N->getOperand(0); 9805 switch (atomic.getOpcode()) { 9806 case ISD::ATOMIC_CMP_SWAP: 9807 case ISD::ATOMIC_SWAP: 9808 case ISD::ATOMIC_LOAD_ADD: 9809 case ISD::ATOMIC_LOAD_SUB: 9810 case ISD::ATOMIC_LOAD_AND: 9811 case ISD::ATOMIC_LOAD_OR: 9812 case ISD::ATOMIC_LOAD_XOR: 9813 case ISD::ATOMIC_LOAD_NAND: 9814 case ISD::ATOMIC_LOAD_MIN: 9815 case ISD::ATOMIC_LOAD_MAX: 9816 case ISD::ATOMIC_LOAD_UMIN: 9817 case ISD::ATOMIC_LOAD_UMAX: 9818 break; 9819 default: 9820 return SDValue(); 9821 } 9822 9823 SDValue fence = atomic.getOperand(0); 9824 if (fence.getOpcode() != ISD::MEMBARRIER) 9825 return SDValue(); 9826 9827 switch (atomic.getOpcode()) { 9828 case ISD::ATOMIC_CMP_SWAP: 9829 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9830 atomic.getOperand(1), atomic.getOperand(2), 9831 atomic.getOperand(3)); 9832 case ISD::ATOMIC_SWAP: 9833 case ISD::ATOMIC_LOAD_ADD: 9834 case ISD::ATOMIC_LOAD_SUB: 9835 case ISD::ATOMIC_LOAD_AND: 9836 case ISD::ATOMIC_LOAD_OR: 9837 case ISD::ATOMIC_LOAD_XOR: 9838 case ISD::ATOMIC_LOAD_NAND: 9839 case ISD::ATOMIC_LOAD_MIN: 9840 case ISD::ATOMIC_LOAD_MAX: 9841 case ISD::ATOMIC_LOAD_UMIN: 9842 case ISD::ATOMIC_LOAD_UMAX: 9843 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9844 atomic.getOperand(1), atomic.getOperand(2)); 9845 default: 9846 return SDValue(); 9847 } 9848} 9849 9850static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 9851 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 9852 // (and (i32 x86isd::setcc_carry), 1) 9853 // This eliminates the zext. This transformation is necessary because 9854 // ISD::SETCC is always legalized to i8. 9855 DebugLoc dl = N->getDebugLoc(); 9856 SDValue N0 = N->getOperand(0); 9857 EVT VT = N->getValueType(0); 9858 if (N0.getOpcode() == ISD::AND && 9859 N0.hasOneUse() && 9860 N0.getOperand(0).hasOneUse()) { 9861 SDValue N00 = N0.getOperand(0); 9862 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 9863 return SDValue(); 9864 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 9865 if (!C || C->getZExtValue() != 1) 9866 return SDValue(); 9867 return DAG.getNode(ISD::AND, dl, VT, 9868 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 9869 N00.getOperand(0), N00.getOperand(1)), 9870 DAG.getConstant(1, VT)); 9871 } 9872 9873 return SDValue(); 9874} 9875 9876SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9877 DAGCombinerInfo &DCI) const { 9878 SelectionDAG &DAG = DCI.DAG; 9879 switch (N->getOpcode()) { 9880 default: break; 9881 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9882 case ISD::EXTRACT_VECTOR_ELT: 9883 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 9884 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9885 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9886 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9887 case ISD::SHL: 9888 case ISD::SRA: 9889 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9890 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget); 9891 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9892 case X86ISD::FXOR: 9893 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9894 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9895 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9896 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9897 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 9898 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 9899 } 9900 9901 return SDValue(); 9902} 9903 9904//===----------------------------------------------------------------------===// 9905// X86 Inline Assembly Support 9906//===----------------------------------------------------------------------===// 9907 9908static bool LowerToBSwap(CallInst *CI) { 9909 // FIXME: this should verify that we are targetting a 486 or better. If not, 9910 // we will turn this bswap into something that will be lowered to logical ops 9911 // instead of emitting the bswap asm. For now, we don't support 486 or lower 9912 // so don't worry about this. 9913 9914 // Verify this is a simple bswap. 9915 if (CI->getNumOperands() != 2 || 9916 CI->getType() != CI->getOperand(1)->getType() || 9917 !CI->getType()->isIntegerTy()) 9918 return false; 9919 9920 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9921 if (!Ty || Ty->getBitWidth() % 16 != 0) 9922 return false; 9923 9924 // Okay, we can do this xform, do so now. 9925 const Type *Tys[] = { Ty }; 9926 Module *M = CI->getParent()->getParent()->getParent(); 9927 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 9928 9929 Value *Op = CI->getOperand(1); 9930 Op = CallInst::Create(Int, Op, CI->getName(), CI); 9931 9932 CI->replaceAllUsesWith(Op); 9933 CI->eraseFromParent(); 9934 return true; 9935} 9936 9937bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 9938 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9939 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 9940 9941 std::string AsmStr = IA->getAsmString(); 9942 9943 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 9944 SmallVector<StringRef, 4> AsmPieces; 9945 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 9946 9947 switch (AsmPieces.size()) { 9948 default: return false; 9949 case 1: 9950 AsmStr = AsmPieces[0]; 9951 AsmPieces.clear(); 9952 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 9953 9954 // bswap $0 9955 if (AsmPieces.size() == 2 && 9956 (AsmPieces[0] == "bswap" || 9957 AsmPieces[0] == "bswapq" || 9958 AsmPieces[0] == "bswapl") && 9959 (AsmPieces[1] == "$0" || 9960 AsmPieces[1] == "${0:q}")) { 9961 // No need to check constraints, nothing other than the equivalent of 9962 // "=r,0" would be valid here. 9963 return LowerToBSwap(CI); 9964 } 9965 // rorw $$8, ${0:w} --> llvm.bswap.i16 9966 if (CI->getType()->isIntegerTy(16) && 9967 AsmPieces.size() == 3 && 9968 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 9969 AsmPieces[1] == "$$8," && 9970 AsmPieces[2] == "${0:w}" && 9971 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 9972 AsmPieces.clear(); 9973 const std::string &Constraints = IA->getConstraintString(); 9974 SplitString(StringRef(Constraints).substr(5), AsmPieces, ","); 9975 std::sort(AsmPieces.begin(), AsmPieces.end()); 9976 if (AsmPieces.size() == 4 && 9977 AsmPieces[0] == "~{cc}" && 9978 AsmPieces[1] == "~{dirflag}" && 9979 AsmPieces[2] == "~{flags}" && 9980 AsmPieces[3] == "~{fpsr}") { 9981 return LowerToBSwap(CI); 9982 } 9983 } 9984 break; 9985 case 3: 9986 if (CI->getType()->isIntegerTy(64) && 9987 Constraints.size() >= 2 && 9988 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 9989 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 9990 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 9991 SmallVector<StringRef, 4> Words; 9992 SplitString(AsmPieces[0], Words, " \t"); 9993 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 9994 Words.clear(); 9995 SplitString(AsmPieces[1], Words, " \t"); 9996 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 9997 Words.clear(); 9998 SplitString(AsmPieces[2], Words, " \t,"); 9999 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 10000 Words[2] == "%edx") { 10001 return LowerToBSwap(CI); 10002 } 10003 } 10004 } 10005 } 10006 break; 10007 } 10008 return false; 10009} 10010 10011 10012 10013/// getConstraintType - Given a constraint letter, return the type of 10014/// constraint it is for this target. 10015X86TargetLowering::ConstraintType 10016X86TargetLowering::getConstraintType(const std::string &Constraint) const { 10017 if (Constraint.size() == 1) { 10018 switch (Constraint[0]) { 10019 case 'A': 10020 return C_Register; 10021 case 'f': 10022 case 'r': 10023 case 'R': 10024 case 'l': 10025 case 'q': 10026 case 'Q': 10027 case 'x': 10028 case 'y': 10029 case 'Y': 10030 return C_RegisterClass; 10031 case 'e': 10032 case 'Z': 10033 return C_Other; 10034 default: 10035 break; 10036 } 10037 } 10038 return TargetLowering::getConstraintType(Constraint); 10039} 10040 10041/// LowerXConstraint - try to replace an X constraint, which matches anything, 10042/// with another that has more specific requirements based on the type of the 10043/// corresponding operand. 10044const char *X86TargetLowering:: 10045LowerXConstraint(EVT ConstraintVT) const { 10046 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 10047 // 'f' like normal targets. 10048 if (ConstraintVT.isFloatingPoint()) { 10049 if (Subtarget->hasSSE2()) 10050 return "Y"; 10051 if (Subtarget->hasSSE1()) 10052 return "x"; 10053 } 10054 10055 return TargetLowering::LowerXConstraint(ConstraintVT); 10056} 10057 10058/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 10059/// vector. If it is invalid, don't add anything to Ops. 10060void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 10061 char Constraint, 10062 bool hasMemory, 10063 std::vector<SDValue>&Ops, 10064 SelectionDAG &DAG) const { 10065 SDValue Result(0, 0); 10066 10067 switch (Constraint) { 10068 default: break; 10069 case 'I': 10070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10071 if (C->getZExtValue() <= 31) { 10072 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10073 break; 10074 } 10075 } 10076 return; 10077 case 'J': 10078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10079 if (C->getZExtValue() <= 63) { 10080 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10081 break; 10082 } 10083 } 10084 return; 10085 case 'K': 10086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10087 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 10088 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10089 break; 10090 } 10091 } 10092 return; 10093 case 'N': 10094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10095 if (C->getZExtValue() <= 255) { 10096 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10097 break; 10098 } 10099 } 10100 return; 10101 case 'e': { 10102 // 32-bit signed value 10103 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10104 const ConstantInt *CI = C->getConstantIntValue(); 10105 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10106 C->getSExtValue())) { 10107 // Widen to 64 bits here to get it sign extended. 10108 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 10109 break; 10110 } 10111 // FIXME gcc accepts some relocatable values here too, but only in certain 10112 // memory models; it's complicated. 10113 } 10114 return; 10115 } 10116 case 'Z': { 10117 // 32-bit unsigned value 10118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 10119 const ConstantInt *CI = C->getConstantIntValue(); 10120 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 10121 C->getZExtValue())) { 10122 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 10123 break; 10124 } 10125 } 10126 // FIXME gcc accepts some relocatable values here too, but only in certain 10127 // memory models; it's complicated. 10128 return; 10129 } 10130 case 'i': { 10131 // Literal immediates are always ok. 10132 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 10133 // Widen to 64 bits here to get it sign extended. 10134 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 10135 break; 10136 } 10137 10138 // If we are in non-pic codegen mode, we allow the address of a global (with 10139 // an optional displacement) to be used with 'i'. 10140 GlobalAddressSDNode *GA = 0; 10141 int64_t Offset = 0; 10142 10143 // Match either (GA), (GA+C), (GA+C1+C2), etc. 10144 while (1) { 10145 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 10146 Offset += GA->getOffset(); 10147 break; 10148 } else if (Op.getOpcode() == ISD::ADD) { 10149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10150 Offset += C->getZExtValue(); 10151 Op = Op.getOperand(0); 10152 continue; 10153 } 10154 } else if (Op.getOpcode() == ISD::SUB) { 10155 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 10156 Offset += -C->getZExtValue(); 10157 Op = Op.getOperand(0); 10158 continue; 10159 } 10160 } 10161 10162 // Otherwise, this isn't something we can handle, reject it. 10163 return; 10164 } 10165 10166 GlobalValue *GV = GA->getGlobal(); 10167 // If we require an extra load to get this address, as in PIC mode, we 10168 // can't accept it. 10169 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 10170 getTargetMachine()))) 10171 return; 10172 10173 if (hasMemory) 10174 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 10175 else 10176 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 10177 Result = Op; 10178 break; 10179 } 10180 } 10181 10182 if (Result.getNode()) { 10183 Ops.push_back(Result); 10184 return; 10185 } 10186 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 10187 Ops, DAG); 10188} 10189 10190std::vector<unsigned> X86TargetLowering:: 10191getRegClassForInlineAsmConstraint(const std::string &Constraint, 10192 EVT VT) const { 10193 if (Constraint.size() == 1) { 10194 // FIXME: not handling fp-stack yet! 10195 switch (Constraint[0]) { // GCC X86 Constraint Letters 10196 default: break; // Unknown constraint letter 10197 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 10198 if (Subtarget->is64Bit()) { 10199 if (VT == MVT::i32) 10200 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 10201 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 10202 X86::R10D,X86::R11D,X86::R12D, 10203 X86::R13D,X86::R14D,X86::R15D, 10204 X86::EBP, X86::ESP, 0); 10205 else if (VT == MVT::i16) 10206 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10207 X86::SI, X86::DI, X86::R8W,X86::R9W, 10208 X86::R10W,X86::R11W,X86::R12W, 10209 X86::R13W,X86::R14W,X86::R15W, 10210 X86::BP, X86::SP, 0); 10211 else if (VT == MVT::i8) 10212 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10213 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10214 X86::R10B,X86::R11B,X86::R12B, 10215 X86::R13B,X86::R14B,X86::R15B, 10216 X86::BPL, X86::SPL, 0); 10217 10218 else if (VT == MVT::i64) 10219 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10220 X86::RSI, X86::RDI, X86::R8, X86::R9, 10221 X86::R10, X86::R11, X86::R12, 10222 X86::R13, X86::R14, X86::R15, 10223 X86::RBP, X86::RSP, 0); 10224 10225 break; 10226 } 10227 // 32-bit fallthrough 10228 case 'Q': // Q_REGS 10229 if (VT == MVT::i32) 10230 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10231 else if (VT == MVT::i16) 10232 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10233 else if (VT == MVT::i8) 10234 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10235 else if (VT == MVT::i64) 10236 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10237 break; 10238 } 10239 } 10240 10241 return std::vector<unsigned>(); 10242} 10243 10244std::pair<unsigned, const TargetRegisterClass*> 10245X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10246 EVT VT) const { 10247 // First, see if this is a constraint that directly corresponds to an LLVM 10248 // register class. 10249 if (Constraint.size() == 1) { 10250 // GCC Constraint Letters 10251 switch (Constraint[0]) { 10252 default: break; 10253 case 'r': // GENERAL_REGS 10254 case 'l': // INDEX_REGS 10255 if (VT == MVT::i8) 10256 return std::make_pair(0U, X86::GR8RegisterClass); 10257 if (VT == MVT::i16) 10258 return std::make_pair(0U, X86::GR16RegisterClass); 10259 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10260 return std::make_pair(0U, X86::GR32RegisterClass); 10261 return std::make_pair(0U, X86::GR64RegisterClass); 10262 case 'R': // LEGACY_REGS 10263 if (VT == MVT::i8) 10264 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10265 if (VT == MVT::i16) 10266 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10267 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10268 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10269 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10270 case 'f': // FP Stack registers. 10271 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10272 // value to the correct fpstack register class. 10273 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10274 return std::make_pair(0U, X86::RFP32RegisterClass); 10275 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10276 return std::make_pair(0U, X86::RFP64RegisterClass); 10277 return std::make_pair(0U, X86::RFP80RegisterClass); 10278 case 'y': // MMX_REGS if MMX allowed. 10279 if (!Subtarget->hasMMX()) break; 10280 return std::make_pair(0U, X86::VR64RegisterClass); 10281 case 'Y': // SSE_REGS if SSE2 allowed 10282 if (!Subtarget->hasSSE2()) break; 10283 // FALL THROUGH. 10284 case 'x': // SSE_REGS if SSE1 allowed 10285 if (!Subtarget->hasSSE1()) break; 10286 10287 switch (VT.getSimpleVT().SimpleTy) { 10288 default: break; 10289 // Scalar SSE types. 10290 case MVT::f32: 10291 case MVT::i32: 10292 return std::make_pair(0U, X86::FR32RegisterClass); 10293 case MVT::f64: 10294 case MVT::i64: 10295 return std::make_pair(0U, X86::FR64RegisterClass); 10296 // Vector types. 10297 case MVT::v16i8: 10298 case MVT::v8i16: 10299 case MVT::v4i32: 10300 case MVT::v2i64: 10301 case MVT::v4f32: 10302 case MVT::v2f64: 10303 return std::make_pair(0U, X86::VR128RegisterClass); 10304 } 10305 break; 10306 } 10307 } 10308 10309 // Use the default implementation in TargetLowering to convert the register 10310 // constraint into a member of a register class. 10311 std::pair<unsigned, const TargetRegisterClass*> Res; 10312 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 10313 10314 // Not found as a standard register? 10315 if (Res.second == 0) { 10316 // Map st(0) -> st(7) -> ST0 10317 if (Constraint.size() == 7 && Constraint[0] == '{' && 10318 tolower(Constraint[1]) == 's' && 10319 tolower(Constraint[2]) == 't' && 10320 Constraint[3] == '(' && 10321 (Constraint[4] >= '0' && Constraint[4] <= '7') && 10322 Constraint[5] == ')' && 10323 Constraint[6] == '}') { 10324 10325 Res.first = X86::ST0+Constraint[4]-'0'; 10326 Res.second = X86::RFP80RegisterClass; 10327 return Res; 10328 } 10329 10330 // GCC allows "st(0)" to be called just plain "st". 10331 if (StringRef("{st}").equals_lower(Constraint)) { 10332 Res.first = X86::ST0; 10333 Res.second = X86::RFP80RegisterClass; 10334 return Res; 10335 } 10336 10337 // flags -> EFLAGS 10338 if (StringRef("{flags}").equals_lower(Constraint)) { 10339 Res.first = X86::EFLAGS; 10340 Res.second = X86::CCRRegisterClass; 10341 return Res; 10342 } 10343 10344 // 'A' means EAX + EDX. 10345 if (Constraint == "A") { 10346 Res.first = X86::EAX; 10347 Res.second = X86::GR32_ADRegisterClass; 10348 return Res; 10349 } 10350 return Res; 10351 } 10352 10353 // Otherwise, check to see if this is a register class of the wrong value 10354 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 10355 // turn into {ax},{dx}. 10356 if (Res.second->hasType(VT)) 10357 return Res; // Correct type already, nothing to do. 10358 10359 // All of the single-register GCC register classes map their values onto 10360 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 10361 // really want an 8-bit or 32-bit register, map to the appropriate register 10362 // class and return the appropriate register. 10363 if (Res.second == X86::GR16RegisterClass) { 10364 if (VT == MVT::i8) { 10365 unsigned DestReg = 0; 10366 switch (Res.first) { 10367 default: break; 10368 case X86::AX: DestReg = X86::AL; break; 10369 case X86::DX: DestReg = X86::DL; break; 10370 case X86::CX: DestReg = X86::CL; break; 10371 case X86::BX: DestReg = X86::BL; break; 10372 } 10373 if (DestReg) { 10374 Res.first = DestReg; 10375 Res.second = X86::GR8RegisterClass; 10376 } 10377 } else if (VT == MVT::i32) { 10378 unsigned DestReg = 0; 10379 switch (Res.first) { 10380 default: break; 10381 case X86::AX: DestReg = X86::EAX; break; 10382 case X86::DX: DestReg = X86::EDX; break; 10383 case X86::CX: DestReg = X86::ECX; break; 10384 case X86::BX: DestReg = X86::EBX; break; 10385 case X86::SI: DestReg = X86::ESI; break; 10386 case X86::DI: DestReg = X86::EDI; break; 10387 case X86::BP: DestReg = X86::EBP; break; 10388 case X86::SP: DestReg = X86::ESP; break; 10389 } 10390 if (DestReg) { 10391 Res.first = DestReg; 10392 Res.second = X86::GR32RegisterClass; 10393 } 10394 } else if (VT == MVT::i64) { 10395 unsigned DestReg = 0; 10396 switch (Res.first) { 10397 default: break; 10398 case X86::AX: DestReg = X86::RAX; break; 10399 case X86::DX: DestReg = X86::RDX; break; 10400 case X86::CX: DestReg = X86::RCX; break; 10401 case X86::BX: DestReg = X86::RBX; break; 10402 case X86::SI: DestReg = X86::RSI; break; 10403 case X86::DI: DestReg = X86::RDI; break; 10404 case X86::BP: DestReg = X86::RBP; break; 10405 case X86::SP: DestReg = X86::RSP; break; 10406 } 10407 if (DestReg) { 10408 Res.first = DestReg; 10409 Res.second = X86::GR64RegisterClass; 10410 } 10411 } 10412 } else if (Res.second == X86::FR32RegisterClass || 10413 Res.second == X86::FR64RegisterClass || 10414 Res.second == X86::VR128RegisterClass) { 10415 // Handle references to XMM physical registers that got mapped into the 10416 // wrong class. This can happen with constraints like {xmm0} where the 10417 // target independent register mapper will just pick the first match it can 10418 // find, ignoring the required type. 10419 if (VT == MVT::f32) 10420 Res.second = X86::FR32RegisterClass; 10421 else if (VT == MVT::f64) 10422 Res.second = X86::FR64RegisterClass; 10423 else if (X86::VR128RegisterClass->hasType(VT)) 10424 Res.second = X86::VR128RegisterClass; 10425 } 10426 10427 return Res; 10428} 10429