X86ISelLowering.cpp revision 433dbdaa636d1c6e06acb2de22bcc83721cacac8
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86ISelLowering.h" 17#include "X86TargetMachine.h" 18#include "llvm/CallingConv.h" 19#include "llvm/Function.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetOptions.h" 25using namespace llvm; 26 27// FIXME: temporary. 28#include "llvm/Support/CommandLine.h" 29static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden, 30 cl::desc("Enable fastcc on X86")); 31 32X86TargetLowering::X86TargetLowering(TargetMachine &TM) 33 : TargetLowering(TM) { 34 35 // Set up the TargetLowering object. 36 37 // X86 is weird, it always uses i8 for shift amounts and setcc results. 38 setShiftAmountType(MVT::i8); 39 setSetCCResultType(MVT::i8); 40 setSetCCResultContents(ZeroOrOneSetCCResult); 41 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 42 43 // Set up the register classes. 44 addRegisterClass(MVT::i8, X86::R8RegisterClass); 45 addRegisterClass(MVT::i16, X86::R16RegisterClass); 46 addRegisterClass(MVT::i32, X86::R32RegisterClass); 47 48 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 49 // operation. 50 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 51 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 52 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 53 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 54 55 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 56 // this operation. 57 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 58 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 59 60 if (!X86ScalarSSE) { 61 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64 62 // isn't legal. 63 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 64 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 65 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 66 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 67 } 68 69 // Handle FP_TO_UINT by promoting the destination to a larger signed 70 // conversion. 71 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 72 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 73 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 74 75 if (!X86ScalarSSE) 76 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 77 78 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 79 // this operation. 80 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 81 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 82 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 83 84 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); 85 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand); 86 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 87 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); 88 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 89 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 90 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 91 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); 92 setOperationAction(ISD::FREM , MVT::f64 , Expand); 93 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 94 setOperationAction(ISD::CTTZ , MVT::i8 , Expand); 95 setOperationAction(ISD::CTLZ , MVT::i8 , Expand); 96 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 97 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 98 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 99 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 100 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 101 setOperationAction(ISD::CTLZ , MVT::i32 , Expand); 102 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 103 104 setOperationAction(ISD::READIO , MVT::i1 , Expand); 105 setOperationAction(ISD::READIO , MVT::i8 , Expand); 106 setOperationAction(ISD::READIO , MVT::i16 , Expand); 107 setOperationAction(ISD::READIO , MVT::i32 , Expand); 108 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand); 109 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand); 110 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand); 111 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand); 112 113 // These should be promoted to a larger select which is supported. 114 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 115 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 116 // X86 wants to expand cmov itself. 117 if (X86DAGIsel) { 118 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 119 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 120 } 121 122 // We don't have line number support yet. 123 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 124 125 if (X86ScalarSSE) { 126 // Set up the FP register classes. 127 addRegisterClass(MVT::f32, X86::V4F4RegisterClass); 128 addRegisterClass(MVT::f64, X86::V2F8RegisterClass); 129 130 // SSE has no load+extend ops 131 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 132 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand); 133 134 // SSE has no i16 to fp conversion, only i32 135 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 136 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 137 138 // Expand FP_TO_UINT into a select. 139 // FIXME: We would like to use a Custom expander here eventually to do 140 // the optimal thing for SSE vs. the default expansion in the legalizer. 141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 142 143 // We don't support sin/cos/sqrt/fmod 144 setOperationAction(ISD::FSIN , MVT::f64, Expand); 145 setOperationAction(ISD::FCOS , MVT::f64, Expand); 146 setOperationAction(ISD::FABS , MVT::f64, Expand); 147 setOperationAction(ISD::FNEG , MVT::f64, Expand); 148 setOperationAction(ISD::FREM , MVT::f64, Expand); 149 setOperationAction(ISD::FSIN , MVT::f32, Expand); 150 setOperationAction(ISD::FCOS , MVT::f32, Expand); 151 setOperationAction(ISD::FABS , MVT::f32, Expand); 152 setOperationAction(ISD::FNEG , MVT::f32, Expand); 153 setOperationAction(ISD::FREM , MVT::f32, Expand); 154 155 addLegalFPImmediate(+0.0); // xorps / xorpd 156 } else { 157 // Set up the FP register classes. 158 addRegisterClass(MVT::f64, X86::RFPRegisterClass); 159 160 if (!UnsafeFPMath) { 161 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 162 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 163 } 164 165 addLegalFPImmediate(+0.0); // FLD0 166 addLegalFPImmediate(+1.0); // FLD1 167 addLegalFPImmediate(-0.0); // FLD0/FCHS 168 addLegalFPImmediate(-1.0); // FLD1/FCHS 169 } 170 computeRegisterProperties(); 171 172 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores 173 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores 174 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores 175 allowUnalignedMemoryAccesses = true; // x86 supports it! 176} 177 178std::vector<SDOperand> 179X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 180 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC) 181 return LowerFastCCArguments(F, DAG); 182 return LowerCCCArguments(F, DAG); 183} 184 185std::pair<SDOperand, SDOperand> 186X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 187 bool isVarArg, unsigned CallingConv, 188 bool isTailCall, 189 SDOperand Callee, ArgListTy &Args, 190 SelectionDAG &DAG) { 191 assert((!isVarArg || CallingConv == CallingConv::C) && 192 "Only C takes varargs!"); 193 if (CallingConv == CallingConv::Fast && EnableFastCC) 194 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG); 195 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG); 196} 197 198//===----------------------------------------------------------------------===// 199// C Calling Convention implementation 200//===----------------------------------------------------------------------===// 201 202std::vector<SDOperand> 203X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) { 204 std::vector<SDOperand> ArgValues; 205 206 MachineFunction &MF = DAG.getMachineFunction(); 207 MachineFrameInfo *MFI = MF.getFrameInfo(); 208 209 // Add DAG nodes to load the arguments... On entry to a function on the X86, 210 // the stack frame looks like this: 211 // 212 // [ESP] -- return address 213 // [ESP + 4] -- first argument (leftmost lexically) 214 // [ESP + 8] -- second argument, if first argument is four bytes in size 215 // ... 216 // 217 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 218 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 219 MVT::ValueType ObjectVT = getValueType(I->getType()); 220 unsigned ArgIncrement = 4; 221 unsigned ObjSize; 222 switch (ObjectVT) { 223 default: assert(0 && "Unhandled argument type!"); 224 case MVT::i1: 225 case MVT::i8: ObjSize = 1; break; 226 case MVT::i16: ObjSize = 2; break; 227 case MVT::i32: ObjSize = 4; break; 228 case MVT::i64: ObjSize = ArgIncrement = 8; break; 229 case MVT::f32: ObjSize = 4; break; 230 case MVT::f64: ObjSize = ArgIncrement = 8; break; 231 } 232 // Create the frame index object for this incoming parameter... 233 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 234 235 // Create the SelectionDAG nodes corresponding to a load from this parameter 236 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 237 238 // Don't codegen dead arguments. FIXME: remove this check when we can nuke 239 // dead loads. 240 SDOperand ArgValue; 241 if (!I->use_empty()) 242 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 243 DAG.getSrcValue(NULL)); 244 else { 245 if (MVT::isInteger(ObjectVT)) 246 ArgValue = DAG.getConstant(0, ObjectVT); 247 else 248 ArgValue = DAG.getConstantFP(0, ObjectVT); 249 } 250 ArgValues.push_back(ArgValue); 251 252 ArgOffset += ArgIncrement; // Move on to the next argument... 253 } 254 255 // If the function takes variable number of arguments, make a frame index for 256 // the start of the first vararg value... for expansion of llvm.va_start. 257 if (F.isVarArg()) 258 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset); 259 ReturnAddrIndex = 0; // No return address slot generated yet. 260 BytesToPopOnReturn = 0; // Callee pops nothing. 261 BytesCallerReserves = ArgOffset; 262 263 // Finally, inform the code generator which regs we return values in. 264 switch (getValueType(F.getReturnType())) { 265 default: assert(0 && "Unknown type!"); 266 case MVT::isVoid: break; 267 case MVT::i1: 268 case MVT::i8: 269 case MVT::i16: 270 case MVT::i32: 271 MF.addLiveOut(X86::EAX); 272 break; 273 case MVT::i64: 274 MF.addLiveOut(X86::EAX); 275 MF.addLiveOut(X86::EDX); 276 break; 277 case MVT::f32: 278 case MVT::f64: 279 MF.addLiveOut(X86::ST0); 280 break; 281 } 282 return ArgValues; 283} 284 285std::pair<SDOperand, SDOperand> 286X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy, 287 bool isVarArg, bool isTailCall, 288 SDOperand Callee, ArgListTy &Args, 289 SelectionDAG &DAG) { 290 // Count how many bytes are to be pushed on the stack. 291 unsigned NumBytes = 0; 292 293 if (Args.empty()) { 294 // Save zero bytes. 295 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 296 DAG.getConstant(0, getPointerTy())); 297 } else { 298 for (unsigned i = 0, e = Args.size(); i != e; ++i) 299 switch (getValueType(Args[i].second)) { 300 default: assert(0 && "Unknown value type!"); 301 case MVT::i1: 302 case MVT::i8: 303 case MVT::i16: 304 case MVT::i32: 305 case MVT::f32: 306 NumBytes += 4; 307 break; 308 case MVT::i64: 309 case MVT::f64: 310 NumBytes += 8; 311 break; 312 } 313 314 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 315 DAG.getConstant(NumBytes, getPointerTy())); 316 317 // Arguments go on the stack in reverse order, as specified by the ABI. 318 unsigned ArgOffset = 0; 319 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 320 X86::ESP, MVT::i32); 321 std::vector<SDOperand> Stores; 322 323 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 324 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 325 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 326 327 switch (getValueType(Args[i].second)) { 328 default: assert(0 && "Unexpected ValueType for argument!"); 329 case MVT::i1: 330 case MVT::i8: 331 case MVT::i16: 332 // Promote the integer to 32 bits. If the input type is signed use a 333 // sign extend, otherwise use a zero extend. 334 if (Args[i].second->isSigned()) 335 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 336 else 337 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 338 339 // FALL THROUGH 340 case MVT::i32: 341 case MVT::f32: 342 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 343 Args[i].first, PtrOff, 344 DAG.getSrcValue(NULL))); 345 ArgOffset += 4; 346 break; 347 case MVT::i64: 348 case MVT::f64: 349 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 350 Args[i].first, PtrOff, 351 DAG.getSrcValue(NULL))); 352 ArgOffset += 8; 353 break; 354 } 355 } 356 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 357 } 358 359 std::vector<MVT::ValueType> RetVals; 360 MVT::ValueType RetTyVT = getValueType(RetTy); 361 RetVals.push_back(MVT::Other); 362 363 // The result values produced have to be legal. Promote the result. 364 switch (RetTyVT) { 365 case MVT::isVoid: break; 366 default: 367 RetVals.push_back(RetTyVT); 368 break; 369 case MVT::i1: 370 case MVT::i8: 371 case MVT::i16: 372 RetVals.push_back(MVT::i32); 373 break; 374 case MVT::f32: 375 if (X86ScalarSSE) 376 RetVals.push_back(MVT::f32); 377 else 378 RetVals.push_back(MVT::f64); 379 break; 380 case MVT::i64: 381 RetVals.push_back(MVT::i32); 382 RetVals.push_back(MVT::i32); 383 break; 384 } 385 std::vector<SDOperand> Ops; 386 Ops.push_back(Chain); 387 Ops.push_back(Callee); 388 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy())); 389 Ops.push_back(DAG.getConstant(0, getPointerTy())); 390 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 391 RetVals, Ops); 392 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); 393 394 SDOperand ResultVal; 395 switch (RetTyVT) { 396 case MVT::isVoid: break; 397 default: 398 ResultVal = TheCall.getValue(1); 399 break; 400 case MVT::i1: 401 case MVT::i8: 402 case MVT::i16: 403 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); 404 break; 405 case MVT::f32: 406 // FIXME: we would really like to remember that this FP_ROUND operation is 407 // okay to eliminate if we allow excess FP precision. 408 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); 409 break; 410 case MVT::i64: 411 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), 412 TheCall.getValue(2)); 413 break; 414 } 415 416 return std::make_pair(ResultVal, Chain); 417} 418 419SDOperand 420X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, 421 Value *VAListV, SelectionDAG &DAG) { 422 // vastart just stores the address of the VarArgsFrameIndex slot. 423 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 424 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 425 DAG.getSrcValue(VAListV)); 426} 427 428 429std::pair<SDOperand,SDOperand> 430X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, 431 Value *VAListV, const Type *ArgTy, 432 SelectionDAG &DAG) { 433 MVT::ValueType ArgVT = getValueType(ArgTy); 434 SDOperand Val = DAG.getLoad(MVT::i32, Chain, 435 VAListP, DAG.getSrcValue(VAListV)); 436 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val, 437 DAG.getSrcValue(NULL)); 438 unsigned Amt; 439 if (ArgVT == MVT::i32) 440 Amt = 4; 441 else { 442 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && 443 "Other types should have been promoted for varargs!"); 444 Amt = 8; 445 } 446 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val, 447 DAG.getConstant(Amt, Val.getValueType())); 448 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, 449 Val, VAListP, DAG.getSrcValue(VAListV)); 450 return std::make_pair(Result, Chain); 451} 452 453//===----------------------------------------------------------------------===// 454// Fast Calling Convention implementation 455//===----------------------------------------------------------------------===// 456// 457// The X86 'fast' calling convention passes up to two integer arguments in 458// registers (an appropriate portion of EAX/EDX), passes arguments in C order, 459// and requires that the callee pop its arguments off the stack (allowing proper 460// tail calls), and has the same return value conventions as C calling convs. 461// 462// This calling convention always arranges for the callee pop value to be 8n+4 463// bytes, which is needed for tail recursion elimination and stack alignment 464// reasons. 465// 466// Note that this can be enhanced in the future to pass fp vals in registers 467// (when we have a global fp allocator) and do other tricks. 468// 469 470/// AddLiveIn - This helper function adds the specified physical register to the 471/// MachineFunction as a live in value. It also creates a corresponding virtual 472/// register for it. 473static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 474 TargetRegisterClass *RC) { 475 assert(RC->contains(PReg) && "Not the correct regclass!"); 476 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); 477 MF.addLiveIn(PReg, VReg); 478 return VReg; 479} 480 481 482std::vector<SDOperand> 483X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) { 484 std::vector<SDOperand> ArgValues; 485 486 MachineFunction &MF = DAG.getMachineFunction(); 487 MachineFrameInfo *MFI = MF.getFrameInfo(); 488 489 // Add DAG nodes to load the arguments... On entry to a function the stack 490 // frame looks like this: 491 // 492 // [ESP] -- return address 493 // [ESP + 4] -- first nonreg argument (leftmost lexically) 494 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size 495 // ... 496 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 497 498 // Keep track of the number of integer regs passed so far. This can be either 499 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 500 // used). 501 unsigned NumIntRegs = 0; 502 503 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 504 MVT::ValueType ObjectVT = getValueType(I->getType()); 505 unsigned ArgIncrement = 4; 506 unsigned ObjSize = 0; 507 SDOperand ArgValue; 508 509 switch (ObjectVT) { 510 default: assert(0 && "Unhandled argument type!"); 511 case MVT::i1: 512 case MVT::i8: 513 if (NumIntRegs < 2) { 514 if (!I->use_empty()) { 515 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL, 516 X86::R8RegisterClass); 517 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8); 518 DAG.setRoot(ArgValue.getValue(1)); 519 } 520 ++NumIntRegs; 521 break; 522 } 523 524 ObjSize = 1; 525 break; 526 case MVT::i16: 527 if (NumIntRegs < 2) { 528 if (!I->use_empty()) { 529 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX, 530 X86::R16RegisterClass); 531 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16); 532 DAG.setRoot(ArgValue.getValue(1)); 533 } 534 ++NumIntRegs; 535 break; 536 } 537 ObjSize = 2; 538 break; 539 case MVT::i32: 540 if (NumIntRegs < 2) { 541 if (!I->use_empty()) { 542 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX, 543 X86::R32RegisterClass); 544 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 545 DAG.setRoot(ArgValue.getValue(1)); 546 } 547 ++NumIntRegs; 548 break; 549 } 550 ObjSize = 4; 551 break; 552 case MVT::i64: 553 if (NumIntRegs == 0) { 554 if (!I->use_empty()) { 555 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass); 556 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); 557 558 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); 559 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32); 560 DAG.setRoot(Hi.getValue(1)); 561 562 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); 563 } 564 NumIntRegs = 2; 565 break; 566 } else if (NumIntRegs == 1) { 567 if (!I->use_empty()) { 568 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass); 569 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32); 570 DAG.setRoot(Low.getValue(1)); 571 572 // Load the high part from memory. 573 // Create the frame index object for this incoming parameter... 574 int FI = MFI->CreateFixedObject(4, ArgOffset); 575 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 576 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 577 DAG.getSrcValue(NULL)); 578 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi); 579 } 580 ArgOffset += 4; 581 NumIntRegs = 2; 582 break; 583 } 584 ObjSize = ArgIncrement = 8; 585 break; 586 case MVT::f32: ObjSize = 4; break; 587 case MVT::f64: ObjSize = ArgIncrement = 8; break; 588 } 589 590 // Don't codegen dead arguments. FIXME: remove this check when we can nuke 591 // dead loads. 592 if (ObjSize && !I->use_empty()) { 593 // Create the frame index object for this incoming parameter... 594 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 595 596 // Create the SelectionDAG nodes corresponding to a load from this 597 // parameter. 598 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 599 600 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 601 DAG.getSrcValue(NULL)); 602 } else if (ArgValue.Val == 0) { 603 if (MVT::isInteger(ObjectVT)) 604 ArgValue = DAG.getConstant(0, ObjectVT); 605 else 606 ArgValue = DAG.getConstantFP(0, ObjectVT); 607 } 608 ArgValues.push_back(ArgValue); 609 610 if (ObjSize) 611 ArgOffset += ArgIncrement; // Move on to the next argument. 612 } 613 614 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 615 // arguments and the arguments after the retaddr has been pushed are aligned. 616 if ((ArgOffset & 7) == 0) 617 ArgOffset += 4; 618 619 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 620 ReturnAddrIndex = 0; // No return address slot generated yet. 621 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments. 622 BytesCallerReserves = 0; 623 624 // Finally, inform the code generator which regs we return values in. 625 switch (getValueType(F.getReturnType())) { 626 default: assert(0 && "Unknown type!"); 627 case MVT::isVoid: break; 628 case MVT::i1: 629 case MVT::i8: 630 case MVT::i16: 631 case MVT::i32: 632 MF.addLiveOut(X86::EAX); 633 break; 634 case MVT::i64: 635 MF.addLiveOut(X86::EAX); 636 MF.addLiveOut(X86::EDX); 637 break; 638 case MVT::f32: 639 case MVT::f64: 640 MF.addLiveOut(X86::ST0); 641 break; 642 } 643 return ArgValues; 644} 645 646std::pair<SDOperand, SDOperand> 647X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, 648 bool isTailCall, SDOperand Callee, 649 ArgListTy &Args, SelectionDAG &DAG) { 650 // Count how many bytes are to be pushed on the stack. 651 unsigned NumBytes = 0; 652 653 // Keep track of the number of integer regs passed so far. This can be either 654 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both 655 // used). 656 unsigned NumIntRegs = 0; 657 658 for (unsigned i = 0, e = Args.size(); i != e; ++i) 659 switch (getValueType(Args[i].second)) { 660 default: assert(0 && "Unknown value type!"); 661 case MVT::i1: 662 case MVT::i8: 663 case MVT::i16: 664 case MVT::i32: 665 if (NumIntRegs < 2) { 666 ++NumIntRegs; 667 break; 668 } 669 // fall through 670 case MVT::f32: 671 NumBytes += 4; 672 break; 673 case MVT::i64: 674 if (NumIntRegs == 0) { 675 NumIntRegs = 2; 676 break; 677 } else if (NumIntRegs == 1) { 678 NumIntRegs = 2; 679 NumBytes += 4; 680 break; 681 } 682 683 // fall through 684 case MVT::f64: 685 NumBytes += 8; 686 break; 687 } 688 689 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 690 // arguments and the arguments after the retaddr has been pushed are aligned. 691 if ((NumBytes & 7) == 0) 692 NumBytes += 4; 693 694 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 695 DAG.getConstant(NumBytes, getPointerTy())); 696 697 // Arguments go on the stack in reverse order, as specified by the ABI. 698 unsigned ArgOffset = 0; 699 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 700 X86::ESP, MVT::i32); 701 NumIntRegs = 0; 702 std::vector<SDOperand> Stores; 703 std::vector<SDOperand> RegValuesToPass; 704 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 705 switch (getValueType(Args[i].second)) { 706 default: assert(0 && "Unexpected ValueType for argument!"); 707 case MVT::i1: 708 case MVT::i8: 709 case MVT::i16: 710 case MVT::i32: 711 if (NumIntRegs < 2) { 712 RegValuesToPass.push_back(Args[i].first); 713 ++NumIntRegs; 714 break; 715 } 716 // Fall through 717 case MVT::f32: { 718 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 719 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 720 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 721 Args[i].first, PtrOff, 722 DAG.getSrcValue(NULL))); 723 ArgOffset += 4; 724 break; 725 } 726 case MVT::i64: 727 if (NumIntRegs < 2) { // Can pass part of it in regs? 728 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 729 Args[i].first, DAG.getConstant(1, MVT::i32)); 730 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 731 Args[i].first, DAG.getConstant(0, MVT::i32)); 732 RegValuesToPass.push_back(Lo); 733 ++NumIntRegs; 734 if (NumIntRegs < 2) { // Pass both parts in regs? 735 RegValuesToPass.push_back(Hi); 736 ++NumIntRegs; 737 } else { 738 // Pass the high part in memory. 739 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 740 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 741 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 742 Hi, PtrOff, DAG.getSrcValue(NULL))); 743 ArgOffset += 4; 744 } 745 break; 746 } 747 // Fall through 748 case MVT::f64: 749 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 750 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 751 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 752 Args[i].first, PtrOff, 753 DAG.getSrcValue(NULL))); 754 ArgOffset += 8; 755 break; 756 } 757 } 758 if (!Stores.empty()) 759 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 760 761 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 762 // arguments and the arguments after the retaddr has been pushed are aligned. 763 if ((ArgOffset & 7) == 0) 764 ArgOffset += 4; 765 766 std::vector<MVT::ValueType> RetVals; 767 MVT::ValueType RetTyVT = getValueType(RetTy); 768 769 RetVals.push_back(MVT::Other); 770 771 // The result values produced have to be legal. Promote the result. 772 switch (RetTyVT) { 773 case MVT::isVoid: break; 774 default: 775 RetVals.push_back(RetTyVT); 776 break; 777 case MVT::i1: 778 case MVT::i8: 779 case MVT::i16: 780 RetVals.push_back(MVT::i32); 781 break; 782 case MVT::f32: 783 if (X86ScalarSSE) 784 RetVals.push_back(MVT::f32); 785 else 786 RetVals.push_back(MVT::f64); 787 break; 788 case MVT::i64: 789 RetVals.push_back(MVT::i32); 790 RetVals.push_back(MVT::i32); 791 break; 792 } 793 794 std::vector<SDOperand> Ops; 795 Ops.push_back(Chain); 796 Ops.push_back(Callee); 797 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 798 // Callee pops all arg values on the stack. 799 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy())); 800 801 // Pass register arguments as needed. 802 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end()); 803 804 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL, 805 RetVals, Ops); 806 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall); 807 808 SDOperand ResultVal; 809 switch (RetTyVT) { 810 case MVT::isVoid: break; 811 default: 812 ResultVal = TheCall.getValue(1); 813 break; 814 case MVT::i1: 815 case MVT::i8: 816 case MVT::i16: 817 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1)); 818 break; 819 case MVT::f32: 820 // FIXME: we would really like to remember that this FP_ROUND operation is 821 // okay to eliminate if we allow excess FP precision. 822 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1)); 823 break; 824 case MVT::i64: 825 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1), 826 TheCall.getValue(2)); 827 break; 828 } 829 830 return std::make_pair(ResultVal, Chain); 831} 832 833SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 834 if (ReturnAddrIndex == 0) { 835 // Set up a frame object for the return address. 836 MachineFunction &MF = DAG.getMachineFunction(); 837 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 838 } 839 840 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32); 841} 842 843 844 845std::pair<SDOperand, SDOperand> X86TargetLowering:: 846LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 847 SelectionDAG &DAG) { 848 SDOperand Result; 849 if (Depth) // Depths > 0 not supported yet! 850 Result = DAG.getConstant(0, getPointerTy()); 851 else { 852 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 853 if (!isFrameAddress) 854 // Just load the return address 855 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI, 856 DAG.getSrcValue(NULL)); 857 else 858 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI, 859 DAG.getConstant(4, MVT::i32)); 860 } 861 return std::make_pair(Result, Chain); 862} 863 864//===----------------------------------------------------------------------===// 865// X86 Custom Lowering Hooks 866//===----------------------------------------------------------------------===// 867 868/// LowerOperation - Provide custom lowering hooks for some operations. 869/// 870SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 871 switch (Op.getOpcode()) { 872 default: assert(0 && "Should not custom lower this!"); 873 case ISD::SINT_TO_FP: { 874 assert(Op.getValueType() == MVT::f64 && 875 Op.getOperand(0).getValueType() == MVT::i64 && 876 "Unknown SINT_TO_FP to lower!"); 877 // We lower sint64->FP into a store to a temporary stack slot, followed by a 878 // FILD64m node. 879 MachineFunction &MF = DAG.getMachineFunction(); 880 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 881 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 882 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 883 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL)); 884 std::vector<MVT::ValueType> RTs; 885 RTs.push_back(MVT::f64); 886 RTs.push_back(MVT::Other); 887 std::vector<SDOperand> Ops; 888 Ops.push_back(Store); 889 Ops.push_back(StackSlot); 890 return DAG.getNode(X86ISD::FILD64m, RTs, Ops); 891 } 892 case ISD::FP_TO_SINT: { 893 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 894 Op.getOperand(0).getValueType() == MVT::f64 && 895 "Unknown FP_TO_SINT to lower!"); 896 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 897 // stack slot. 898 MachineFunction &MF = DAG.getMachineFunction(); 899 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 900 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 901 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 902 903 unsigned Opc; 904 switch (Op.getValueType()) { 905 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 906 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 907 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 908 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 909 } 910 911 // Build the FP_TO_INT*_IN_MEM 912 std::vector<SDOperand> Ops; 913 Ops.push_back(DAG.getEntryNode()); 914 Ops.push_back(Op.getOperand(0)); 915 Ops.push_back(StackSlot); 916 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops); 917 918 // Load the result. 919 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, 920 DAG.getSrcValue(NULL)); 921 } 922 case ISD::READCYCLECOUNTER: { 923 std::vector<MVT::ValueType> Tys; 924 Tys.push_back(MVT::Other); 925 Tys.push_back(MVT::Flag); 926 std::vector<SDOperand> Ops; 927 Ops.push_back(Op.getOperand(0)); 928 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops); 929 Ops.clear(); 930 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1))); 931 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX, 932 MVT::i32, Ops[0].getValue(2))); 933 Ops.push_back(Ops[1].getValue(1)); 934 Tys[0] = Tys[1] = MVT::i32; 935 Tys.push_back(MVT::Other); 936 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 937 } 938 case ISD::SELECT: { 939 SDOperand Cond = Op.getOperand(0); 940 SDOperand CC; 941 if (Cond.getOpcode() == ISD::SETCC) { 942 CC = Cond.getOperand(2); 943 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, 944 Cond.getOperand(0), Cond.getOperand(1)); 945 } else { 946 CC = DAG.getCondCode(ISD::SETEQ); 947 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); 948 } 949 return DAG.getNode(X86ISD::CMOV, Op.getValueType(), 950 Op.getOperand(1), Op.getOperand(2), CC, Cond); 951 } 952 } 953} 954