X86ISelLowering.cpp revision 4aa21aa6d13b8ea00eb0817e53f24e5416ed3038
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86TargetMachine.h" 19#include "llvm/CallingConv.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/GlobalAlias.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Function.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/ADT/BitVector.h" 27#include "llvm/ADT/VectorExtras.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/PseudoSourceValue.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallSet.h" 39#include "llvm/ADT/StringExtras.h" 40#include "llvm/Support/CommandLine.h" 41#include "llvm/Support/raw_ostream.h" 42using namespace llvm; 43 44static cl::opt<bool> 45DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 46 47// Forward declarations. 48static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, 49 SDValue V2); 50 51X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 52 : TargetLowering(TM) { 53 Subtarget = &TM.getSubtarget<X86Subtarget>(); 54 X86ScalarSSEf64 = Subtarget->hasSSE2(); 55 X86ScalarSSEf32 = Subtarget->hasSSE1(); 56 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 57 58 RegInfo = TM.getRegisterInfo(); 59 TD = getTargetData(); 60 61 // Set up the TargetLowering object. 62 63 // X86 is weird, it always uses i8 for shift amounts and setcc results. 64 setShiftAmountType(MVT::i8); 65 setBooleanContents(ZeroOrOneBooleanContent); 66 setSchedulingPreference(SchedulingForRegPressure); 67 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 68 setStackPointerRegisterToSaveRestore(X86StackPtr); 69 70 if (Subtarget->isTargetDarwin()) { 71 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 72 setUseUnderscoreSetJmp(false); 73 setUseUnderscoreLongJmp(false); 74 } else if (Subtarget->isTargetMingw()) { 75 // MS runtime is weird: it exports _setjmp, but longjmp! 76 setUseUnderscoreSetJmp(true); 77 setUseUnderscoreLongJmp(false); 78 } else { 79 setUseUnderscoreSetJmp(true); 80 setUseUnderscoreLongJmp(true); 81 } 82 83 // Set up the register classes. 84 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 85 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 86 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 87 if (Subtarget->is64Bit()) 88 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 89 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 91 92 // We don't accept any truncstore of integer registers. 93 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 94 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 95 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 96 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 97 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 98 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 99 100 // SETOEQ and SETUNE require checking two conditions. 101 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 102 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 103 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 104 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 105 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 106 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 107 108 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 109 // operation. 110 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 111 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 112 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 113 114 if (Subtarget->is64Bit()) { 115 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 117 } else if (!UseSoftFloat) { 118 if (X86ScalarSSEf64) { 119 // We have an impenetrably clever algorithm for ui64->double only. 120 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 121 } 122 // We have an algorithm for SSE2, and we turn this into a 64-bit 123 // FILD for other targets. 124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 125 } 126 127 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 128 // this operation. 129 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 130 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 131 132 if (!UseSoftFloat) { 133 // SSE has no i16 to fp conversion, only i32 134 if (X86ScalarSSEf32) { 135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 136 // f32 and f64 cases are Legal, f80 case is not 137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 138 } else { 139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 141 } 142 } else { 143 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 144 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 145 } 146 147 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 148 // are Legal, f80 is custom lowered. 149 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 150 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 151 152 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 153 // this operation. 154 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 155 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 156 157 if (X86ScalarSSEf32) { 158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 159 // f32 and f64 cases are Legal, f80 case is not 160 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 161 } else { 162 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 163 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 164 } 165 166 // Handle FP_TO_UINT by promoting the destination to a larger signed 167 // conversion. 168 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 169 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 170 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 171 172 if (Subtarget->is64Bit()) { 173 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 174 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 175 } else if (!UseSoftFloat) { 176 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 177 // Expand FP_TO_UINT into a select. 178 // FIXME: We would like to use a Custom expander here eventually to do 179 // the optimal thing for SSE vs. the default expansion in the legalizer. 180 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 181 else 182 // With SSE3 we can use fisttpll to convert to a signed i64; without 183 // SSE, we're stuck with a fistpll. 184 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 185 } 186 187 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 188 if (!X86ScalarSSEf64) { 189 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 190 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 191 } 192 193 // Scalar integer divide and remainder are lowered to use operations that 194 // produce two results, to match the available instructions. This exposes 195 // the two-result form to trivial CSE, which is able to combine x/y and x%y 196 // into a single instruction. 197 // 198 // Scalar integer multiply-high is also lowered to use two-result 199 // operations, to match the available instructions. However, plain multiply 200 // (low) operations are left as Legal, as there are single-result 201 // instructions for this in x86. Using the two-result multiply instructions 202 // when both high and low results are needed must be arranged by dagcombine. 203 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 204 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 205 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 206 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 207 setOperationAction(ISD::SREM , MVT::i8 , Expand); 208 setOperationAction(ISD::UREM , MVT::i8 , Expand); 209 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 210 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 211 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 212 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 213 setOperationAction(ISD::SREM , MVT::i16 , Expand); 214 setOperationAction(ISD::UREM , MVT::i16 , Expand); 215 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 216 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 217 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 218 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 219 setOperationAction(ISD::SREM , MVT::i32 , Expand); 220 setOperationAction(ISD::UREM , MVT::i32 , Expand); 221 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 222 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 223 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 224 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 225 setOperationAction(ISD::SREM , MVT::i64 , Expand); 226 setOperationAction(ISD::UREM , MVT::i64 , Expand); 227 228 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 229 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 230 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 231 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 232 if (Subtarget->is64Bit()) 233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 236 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 237 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 238 setOperationAction(ISD::FREM , MVT::f32 , Expand); 239 setOperationAction(ISD::FREM , MVT::f64 , Expand); 240 setOperationAction(ISD::FREM , MVT::f80 , Expand); 241 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 242 243 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 244 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 245 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 246 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 247 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 248 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 249 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 250 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 251 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 252 if (Subtarget->is64Bit()) { 253 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 254 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 255 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 256 } 257 258 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 259 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 260 261 // These should be promoted to a larger select which is supported. 262 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 263 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 264 // X86 wants to expand cmov itself. 265 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 266 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 267 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 268 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 269 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 270 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 271 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 272 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 273 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 274 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 275 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 276 if (Subtarget->is64Bit()) { 277 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 278 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 279 } 280 // X86 ret instruction may pop stack. 281 setOperationAction(ISD::RET , MVT::Other, Custom); 282 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 283 284 // Darwin ABI issue. 285 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 286 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 287 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 288 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 289 if (Subtarget->is64Bit()) 290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 291 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 292 if (Subtarget->is64Bit()) { 293 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 294 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 295 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 296 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 297 } 298 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 299 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 300 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 301 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 302 if (Subtarget->is64Bit()) { 303 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 304 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 305 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 306 } 307 308 if (Subtarget->hasSSE1()) 309 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 310 311 if (!Subtarget->hasSSE2()) 312 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 313 314 // Expand certain atomics 315 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 316 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 317 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 318 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 319 320 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 321 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 323 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 324 325 if (!Subtarget->is64Bit()) { 326 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 327 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 328 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 329 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 330 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 331 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 332 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 333 } 334 335 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. 336 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 337 // FIXME - use subtarget debug flags 338 if (!Subtarget->isTargetDarwin() && 339 !Subtarget->isTargetELF() && 340 !Subtarget->isTargetCygMing()) { 341 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 342 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 343 } 344 345 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 346 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 347 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 348 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 349 if (Subtarget->is64Bit()) { 350 setExceptionPointerRegister(X86::RAX); 351 setExceptionSelectorRegister(X86::RDX); 352 } else { 353 setExceptionPointerRegister(X86::EAX); 354 setExceptionSelectorRegister(X86::EDX); 355 } 356 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 357 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 358 359 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 360 361 setOperationAction(ISD::TRAP, MVT::Other, Legal); 362 363 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 364 setOperationAction(ISD::VASTART , MVT::Other, Custom); 365 setOperationAction(ISD::VAEND , MVT::Other, Expand); 366 if (Subtarget->is64Bit()) { 367 setOperationAction(ISD::VAARG , MVT::Other, Custom); 368 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 369 } else { 370 setOperationAction(ISD::VAARG , MVT::Other, Expand); 371 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 372 } 373 374 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 375 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 376 if (Subtarget->is64Bit()) 377 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 378 if (Subtarget->isTargetCygMing()) 379 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 380 else 381 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 382 383 if (!UseSoftFloat && X86ScalarSSEf64) { 384 // f32 and f64 use SSE. 385 // Set up the FP register classes. 386 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 387 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 388 389 // Use ANDPD to simulate FABS. 390 setOperationAction(ISD::FABS , MVT::f64, Custom); 391 setOperationAction(ISD::FABS , MVT::f32, Custom); 392 393 // Use XORP to simulate FNEG. 394 setOperationAction(ISD::FNEG , MVT::f64, Custom); 395 setOperationAction(ISD::FNEG , MVT::f32, Custom); 396 397 // Use ANDPD and ORPD to simulate FCOPYSIGN. 398 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 399 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 400 401 // We don't support sin/cos/fmod 402 setOperationAction(ISD::FSIN , MVT::f64, Expand); 403 setOperationAction(ISD::FCOS , MVT::f64, Expand); 404 setOperationAction(ISD::FSIN , MVT::f32, Expand); 405 setOperationAction(ISD::FCOS , MVT::f32, Expand); 406 407 // Expand FP immediates into loads from the stack, except for the special 408 // cases we handle. 409 addLegalFPImmediate(APFloat(+0.0)); // xorpd 410 addLegalFPImmediate(APFloat(+0.0f)); // xorps 411 } else if (!UseSoftFloat && X86ScalarSSEf32) { 412 // Use SSE for f32, x87 for f64. 413 // Set up the FP register classes. 414 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 415 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 416 417 // Use ANDPS to simulate FABS. 418 setOperationAction(ISD::FABS , MVT::f32, Custom); 419 420 // Use XORP to simulate FNEG. 421 setOperationAction(ISD::FNEG , MVT::f32, Custom); 422 423 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 424 425 // Use ANDPS and ORPS to simulate FCOPYSIGN. 426 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 427 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 428 429 // We don't support sin/cos/fmod 430 setOperationAction(ISD::FSIN , MVT::f32, Expand); 431 setOperationAction(ISD::FCOS , MVT::f32, Expand); 432 433 // Special cases we handle for FP constants. 434 addLegalFPImmediate(APFloat(+0.0f)); // xorps 435 addLegalFPImmediate(APFloat(+0.0)); // FLD0 436 addLegalFPImmediate(APFloat(+1.0)); // FLD1 437 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 438 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 439 440 if (!UnsafeFPMath) { 441 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 442 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 443 } 444 } else if (!UseSoftFloat) { 445 // f32 and f64 in x87. 446 // Set up the FP register classes. 447 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 448 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 449 450 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 451 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 452 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 453 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 454 455 if (!UnsafeFPMath) { 456 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 457 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 458 } 459 addLegalFPImmediate(APFloat(+0.0)); // FLD0 460 addLegalFPImmediate(APFloat(+1.0)); // FLD1 461 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 462 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 463 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 464 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 465 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 466 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 467 } 468 469 // Long double always uses X87. 470 if (!UseSoftFloat) { 471 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 472 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 473 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 474 { 475 bool ignored; 476 APFloat TmpFlt(+0.0); 477 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 478 &ignored); 479 addLegalFPImmediate(TmpFlt); // FLD0 480 TmpFlt.changeSign(); 481 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 482 APFloat TmpFlt2(+1.0); 483 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 484 &ignored); 485 addLegalFPImmediate(TmpFlt2); // FLD1 486 TmpFlt2.changeSign(); 487 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 488 } 489 490 if (!UnsafeFPMath) { 491 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 492 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 493 } 494 } 495 496 // Always use a library call for pow. 497 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 498 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 499 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 500 501 setOperationAction(ISD::FLOG, MVT::f80, Expand); 502 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 503 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 504 setOperationAction(ISD::FEXP, MVT::f80, Expand); 505 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 506 507 // First set operation action for all vector types to either promote 508 // (for widening) or expand (for scalarization). Then we will selectively 509 // turn on ones that can be effectively codegen'd. 510 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 511 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 512 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 513 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 514 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 515 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 516 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 517 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 518 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 519 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 520 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 521 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 522 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 523 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 524 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 525 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 526 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 527 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 528 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 529 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 530 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 531 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 532 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 533 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 534 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 535 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 537 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 538 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 539 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 540 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 541 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 542 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 543 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 544 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 545 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 546 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 547 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 548 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 549 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 550 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 551 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 560 } 561 562 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 563 // with -msoft-float, disable use of MMX as well. 564 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 565 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 566 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 567 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 568 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 569 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 570 571 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 572 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 573 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 574 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 575 576 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 577 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 578 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 579 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 580 581 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 582 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 583 584 setOperationAction(ISD::AND, MVT::v8i8, Promote); 585 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 586 setOperationAction(ISD::AND, MVT::v4i16, Promote); 587 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 588 setOperationAction(ISD::AND, MVT::v2i32, Promote); 589 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 590 setOperationAction(ISD::AND, MVT::v1i64, Legal); 591 592 setOperationAction(ISD::OR, MVT::v8i8, Promote); 593 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 594 setOperationAction(ISD::OR, MVT::v4i16, Promote); 595 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 596 setOperationAction(ISD::OR, MVT::v2i32, Promote); 597 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 598 setOperationAction(ISD::OR, MVT::v1i64, Legal); 599 600 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 601 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 602 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 603 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 604 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 605 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 606 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 607 608 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 609 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 610 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 611 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 612 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 613 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 614 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 615 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 616 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 617 618 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 619 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 620 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 621 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 622 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 623 624 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 625 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 628 629 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 630 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 631 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 632 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 633 634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 635 636 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); 637 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); 638 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 639 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 640 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 641 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 642 } 643 644 if (!UseSoftFloat && Subtarget->hasSSE1()) { 645 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 646 647 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 648 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 649 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 650 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 651 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 652 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 653 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 654 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 656 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 657 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 658 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 659 } 660 661 if (!UseSoftFloat && Subtarget->hasSSE2()) { 662 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 663 664 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 665 // registers cannot be used even for integer operations. 666 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 667 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 668 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 669 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 670 671 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 672 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 673 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 674 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 675 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 676 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 677 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 678 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 679 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 680 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 681 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 682 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 683 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 684 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 685 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 686 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 687 688 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 689 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 690 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 691 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 692 693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 694 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 696 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 698 699 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 700 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 701 MVT VT = (MVT::SimpleValueType)i; 702 // Do not attempt to custom lower non-power-of-2 vectors 703 if (!isPowerOf2_32(VT.getVectorNumElements())) 704 continue; 705 // Do not attempt to custom lower non-128-bit vectors 706 if (!VT.is128BitVector()) 707 continue; 708 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 709 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 710 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 711 } 712 713 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 714 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 715 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 716 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 717 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 719 720 if (Subtarget->is64Bit()) { 721 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 723 } 724 725 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 726 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 727 MVT VT = (MVT::SimpleValueType)i; 728 729 // Do not attempt to promote non-128-bit vectors 730 if (!VT.is128BitVector()) { 731 continue; 732 } 733 setOperationAction(ISD::AND, VT, Promote); 734 AddPromotedToType (ISD::AND, VT, MVT::v2i64); 735 setOperationAction(ISD::OR, VT, Promote); 736 AddPromotedToType (ISD::OR, VT, MVT::v2i64); 737 setOperationAction(ISD::XOR, VT, Promote); 738 AddPromotedToType (ISD::XOR, VT, MVT::v2i64); 739 setOperationAction(ISD::LOAD, VT, Promote); 740 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64); 741 setOperationAction(ISD::SELECT, VT, Promote); 742 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64); 743 } 744 745 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 746 747 // Custom lower v2i64 and v2f64 selects. 748 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 749 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 750 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 751 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 752 753 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 754 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 755 if (!DisableMMX && Subtarget->hasMMX()) { 756 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 757 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 758 } 759 } 760 761 if (Subtarget->hasSSE41()) { 762 // FIXME: Do we need to handle scalar-to-vector here? 763 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 764 765 // i8 and i16 vectors are custom , because the source register and source 766 // source memory operand types are not the same width. f32 vectors are 767 // custom since the immediate controlling the insert encodes additional 768 // information. 769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 772 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 773 774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 777 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 778 779 if (Subtarget->is64Bit()) { 780 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 782 } 783 } 784 785 if (Subtarget->hasSSE42()) { 786 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 787 } 788 789 if (!UseSoftFloat && Subtarget->hasAVX()) { 790 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 791 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 792 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 793 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 794 795 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 796 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 797 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 798 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 799 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 800 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 801 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 802 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 803 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 804 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 805 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 806 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 807 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 808 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 809 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 810 811 // Operations to consider commented out -v16i16 v32i8 812 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 813 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 814 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 815 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 816 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 817 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 818 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 819 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 820 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 821 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 822 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 823 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 824 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 825 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 826 827 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 828 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 829 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 830 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 831 832 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 833 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 834 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 837 838 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 839 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 840 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 841 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 844 845#if 0 846 // Not sure we want to do this since there are no 256-bit integer 847 // operations in AVX 848 849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 850 // This includes 256-bit vectors 851 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 852 MVT VT = (MVT::SimpleValueType)i; 853 854 // Do not attempt to custom lower non-power-of-2 vectors 855 if (!isPowerOf2_32(VT.getVectorNumElements())) 856 continue; 857 858 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 859 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 860 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 861 } 862 863 if (Subtarget->is64Bit()) { 864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 866 } 867#endif 868 869#if 0 870 // Not sure we want to do this since there are no 256-bit integer 871 // operations in AVX 872 873 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 874 // Including 256-bit vectors 875 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 876 MVT VT = (MVT::SimpleValueType)i; 877 878 if (!VT.is256BitVector()) { 879 continue; 880 } 881 setOperationAction(ISD::AND, VT, Promote); 882 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 883 setOperationAction(ISD::OR, VT, Promote); 884 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 885 setOperationAction(ISD::XOR, VT, Promote); 886 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 887 setOperationAction(ISD::LOAD, VT, Promote); 888 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 889 setOperationAction(ISD::SELECT, VT, Promote); 890 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 891 } 892 893 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 894#endif 895 } 896 897 // We want to custom lower some of our intrinsics. 898 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 899 900 // Add/Sub/Mul with overflow operations are custom lowered. 901 setOperationAction(ISD::SADDO, MVT::i32, Custom); 902 setOperationAction(ISD::SADDO, MVT::i64, Custom); 903 setOperationAction(ISD::UADDO, MVT::i32, Custom); 904 setOperationAction(ISD::UADDO, MVT::i64, Custom); 905 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 906 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 907 setOperationAction(ISD::USUBO, MVT::i32, Custom); 908 setOperationAction(ISD::USUBO, MVT::i64, Custom); 909 setOperationAction(ISD::SMULO, MVT::i32, Custom); 910 setOperationAction(ISD::SMULO, MVT::i64, Custom); 911 912 if (!Subtarget->is64Bit()) { 913 // These libcalls are not available in 32-bit. 914 setLibcallName(RTLIB::SHL_I128, 0); 915 setLibcallName(RTLIB::SRL_I128, 0); 916 setLibcallName(RTLIB::SRA_I128, 0); 917 } 918 919 // We have target-specific dag combine patterns for the following nodes: 920 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 921 setTargetDAGCombine(ISD::BUILD_VECTOR); 922 setTargetDAGCombine(ISD::SELECT); 923 setTargetDAGCombine(ISD::SHL); 924 setTargetDAGCombine(ISD::SRA); 925 setTargetDAGCombine(ISD::SRL); 926 setTargetDAGCombine(ISD::STORE); 927 setTargetDAGCombine(ISD::MEMBARRIER); 928 if (Subtarget->is64Bit()) 929 setTargetDAGCombine(ISD::MUL); 930 931 computeRegisterProperties(); 932 933 // FIXME: These should be based on subtarget info. Plus, the values should 934 // be smaller when we are in optimizing for size mode. 935 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 936 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 937 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 938 allowUnalignedMemoryAccesses = true; // x86 supports it! 939 setPrefLoopAlignment(16); 940 benefitFromCodePlacementOpt = true; 941} 942 943 944MVT X86TargetLowering::getSetCCResultType(MVT VT) const { 945 return MVT::i8; 946} 947 948 949/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 950/// the desired ByVal argument alignment. 951static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 952 if (MaxAlign == 16) 953 return; 954 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 955 if (VTy->getBitWidth() == 128) 956 MaxAlign = 16; 957 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 958 unsigned EltAlign = 0; 959 getMaxByValAlign(ATy->getElementType(), EltAlign); 960 if (EltAlign > MaxAlign) 961 MaxAlign = EltAlign; 962 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 963 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 964 unsigned EltAlign = 0; 965 getMaxByValAlign(STy->getElementType(i), EltAlign); 966 if (EltAlign > MaxAlign) 967 MaxAlign = EltAlign; 968 if (MaxAlign == 16) 969 break; 970 } 971 } 972 return; 973} 974 975/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 976/// function arguments in the caller parameter area. For X86, aggregates 977/// that contain SSE vectors are placed at 16-byte boundaries while the rest 978/// are at 4-byte boundaries. 979unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 980 if (Subtarget->is64Bit()) { 981 // Max of 8 and alignment of type. 982 unsigned TyAlign = TD->getABITypeAlignment(Ty); 983 if (TyAlign > 8) 984 return TyAlign; 985 return 8; 986 } 987 988 unsigned Align = 4; 989 if (Subtarget->hasSSE1()) 990 getMaxByValAlign(Ty, Align); 991 return Align; 992} 993 994/// getOptimalMemOpType - Returns the target specific optimal type for load 995/// and store operations as a result of memset, memcpy, and memmove 996/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 997/// determining it. 998MVT 999X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1000 bool isSrcConst, bool isSrcStr, 1001 SelectionDAG &DAG) const { 1002 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1003 // linux. This is because the stack realignment code can't handle certain 1004 // cases like PR2962. This should be removed when PR2962 is fixed. 1005 const Function *F = DAG.getMachineFunction().getFunction(); 1006 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1007 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1008 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1009 return MVT::v4i32; 1010 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1011 return MVT::v4f32; 1012 } 1013 if (Subtarget->is64Bit() && Size >= 8) 1014 return MVT::i64; 1015 return MVT::i32; 1016} 1017 1018/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1019/// jumptable. 1020SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1021 SelectionDAG &DAG) const { 1022 if (usesGlobalOffsetTable()) 1023 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1024 if (!Subtarget->isPICStyleRIPRel()) 1025 // This doesn't have DebugLoc associated with it, but is not really the 1026 // same as a Register. 1027 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1028 getPointerTy()); 1029 return Table; 1030} 1031 1032/// getFunctionAlignment - Return the Log2 alignment of this function. 1033unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1034 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4; 1035} 1036 1037//===----------------------------------------------------------------------===// 1038// Return Value Calling Convention Implementation 1039//===----------------------------------------------------------------------===// 1040 1041#include "X86GenCallingConv.inc" 1042 1043/// LowerRET - Lower an ISD::RET node. 1044SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 1045 DebugLoc dl = Op.getDebugLoc(); 1046 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 1047 1048 SmallVector<CCValAssign, 16> RVLocs; 1049 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1050 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1051 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 1052 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86); 1053 1054 // If this is the first return lowered for this function, add the regs to the 1055 // liveout set for the function. 1056 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1057 for (unsigned i = 0; i != RVLocs.size(); ++i) 1058 if (RVLocs[i].isRegLoc()) 1059 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1060 } 1061 SDValue Chain = Op.getOperand(0); 1062 1063 // Handle tail call return. 1064 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL); 1065 if (Chain.getOpcode() == X86ISD::TAILCALL) { 1066 SDValue TailCall = Chain; 1067 SDValue TargetAddress = TailCall.getOperand(1); 1068 SDValue StackAdjustment = TailCall.getOperand(2); 1069 assert(((TargetAddress.getOpcode() == ISD::Register && 1070 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX || 1071 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R11)) || 1072 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 1073 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 1074 "Expecting an global address, external symbol, or register"); 1075 assert(StackAdjustment.getOpcode() == ISD::Constant && 1076 "Expecting a const value"); 1077 1078 SmallVector<SDValue,8> Operands; 1079 Operands.push_back(Chain.getOperand(0)); 1080 Operands.push_back(TargetAddress); 1081 Operands.push_back(StackAdjustment); 1082 // Copy registers used by the call. Last operand is a flag so it is not 1083 // copied. 1084 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 1085 Operands.push_back(Chain.getOperand(i)); 1086 } 1087 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0], 1088 Operands.size()); 1089 } 1090 1091 // Regular return. 1092 SDValue Flag; 1093 1094 SmallVector<SDValue, 6> RetOps; 1095 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1096 // Operand #1 = Bytes To Pop 1097 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 1098 1099 // Copy the result values into the output registers. 1100 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1101 CCValAssign &VA = RVLocs[i]; 1102 assert(VA.isRegLoc() && "Can only return in registers!"); 1103 SDValue ValToCopy = Op.getOperand(i*2+1); 1104 1105 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1106 // the RET instruction and handled by the FP Stackifier. 1107 if (VA.getLocReg() == X86::ST0 || 1108 VA.getLocReg() == X86::ST1) { 1109 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1110 // change the value to the FP stack register class. 1111 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1112 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1113 RetOps.push_back(ValToCopy); 1114 // Don't emit a copytoreg. 1115 continue; 1116 } 1117 1118 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1119 // which is returned in RAX / RDX. 1120 if (Subtarget->is64Bit()) { 1121 MVT ValVT = ValToCopy.getValueType(); 1122 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1123 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1124 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1125 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1126 } 1127 } 1128 1129 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1130 Flag = Chain.getValue(1); 1131 } 1132 1133 // The x86-64 ABI for returning structs by value requires that we copy 1134 // the sret argument into %rax for the return. We saved the argument into 1135 // a virtual register in the entry block, so now we copy the value out 1136 // and into %rax. 1137 if (Subtarget->is64Bit() && 1138 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1139 MachineFunction &MF = DAG.getMachineFunction(); 1140 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1141 unsigned Reg = FuncInfo->getSRetReturnReg(); 1142 if (!Reg) { 1143 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1144 FuncInfo->setSRetReturnReg(Reg); 1145 } 1146 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1147 1148 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1149 Flag = Chain.getValue(1); 1150 } 1151 1152 RetOps[0] = Chain; // Update chain. 1153 1154 // Add the flag if we have it. 1155 if (Flag.getNode()) 1156 RetOps.push_back(Flag); 1157 1158 return DAG.getNode(X86ISD::RET_FLAG, dl, 1159 MVT::Other, &RetOps[0], RetOps.size()); 1160} 1161 1162 1163/// LowerCallResult - Lower the result values of an ISD::CALL into the 1164/// appropriate copies out of appropriate physical registers. This assumes that 1165/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 1166/// being lowered. The returns a SDNode with the same number of values as the 1167/// ISD::CALL. 1168SDNode *X86TargetLowering:: 1169LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 1170 unsigned CallingConv, SelectionDAG &DAG) { 1171 1172 DebugLoc dl = TheCall->getDebugLoc(); 1173 // Assign locations to each value returned by this call. 1174 SmallVector<CCValAssign, 16> RVLocs; 1175 bool isVarArg = TheCall->isVarArg(); 1176 bool Is64Bit = Subtarget->is64Bit(); 1177 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 1178 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); 1179 1180 SmallVector<SDValue, 8> ResultVals; 1181 1182 // Copy all of the result registers out of their specified physreg. 1183 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1184 CCValAssign &VA = RVLocs[i]; 1185 MVT CopyVT = VA.getValVT(); 1186 1187 // If this is x86-64, and we disabled SSE, we can't return FP values 1188 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1189 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) { 1190 llvm_report_error("SSE register return with SSE disabled"); 1191 } 1192 1193 // If this is a call to a function that returns an fp value on the floating 1194 // point stack, but where we prefer to use the value in xmm registers, copy 1195 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1196 if ((VA.getLocReg() == X86::ST0 || 1197 VA.getLocReg() == X86::ST1) && 1198 isScalarFPTypeInSSEReg(VA.getValVT())) { 1199 CopyVT = MVT::f80; 1200 } 1201 1202 SDValue Val; 1203 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1204 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1205 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1207 MVT::v2i64, InFlag).getValue(1); 1208 Val = Chain.getValue(0); 1209 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1210 Val, DAG.getConstant(0, MVT::i64)); 1211 } else { 1212 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1213 MVT::i64, InFlag).getValue(1); 1214 Val = Chain.getValue(0); 1215 } 1216 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1217 } else { 1218 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1219 CopyVT, InFlag).getValue(1); 1220 Val = Chain.getValue(0); 1221 } 1222 InFlag = Chain.getValue(2); 1223 1224 if (CopyVT != VA.getValVT()) { 1225 // Round the F80 the right size, which also moves to the appropriate xmm 1226 // register. 1227 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1228 // This truncation won't change the value. 1229 DAG.getIntPtrConstant(1)); 1230 } 1231 1232 ResultVals.push_back(Val); 1233 } 1234 1235 // Merge everything together with a MERGE_VALUES node. 1236 ResultVals.push_back(Chain); 1237 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), 1238 &ResultVals[0], ResultVals.size()).getNode(); 1239} 1240 1241 1242//===----------------------------------------------------------------------===// 1243// C & StdCall & Fast Calling Convention implementation 1244//===----------------------------------------------------------------------===// 1245// StdCall calling convention seems to be standard for many Windows' API 1246// routines and around. It differs from C calling convention just a little: 1247// callee should clean up the stack, not caller. Symbols should be also 1248// decorated in some fancy way :) It doesn't support any vector arguments. 1249// For info on fast calling convention see Fast Calling Convention (tail call) 1250// implementation LowerX86_32FastCCCallTo. 1251 1252/// CallIsStructReturn - Determines whether a CALL node uses struct return 1253/// semantics. 1254static bool CallIsStructReturn(CallSDNode *TheCall) { 1255 unsigned NumOps = TheCall->getNumArgs(); 1256 if (!NumOps) 1257 return false; 1258 1259 return TheCall->getArgFlags(0).isSRet(); 1260} 1261 1262/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct 1263/// return semantics. 1264static bool ArgsAreStructReturn(SDValue Op) { 1265 unsigned NumArgs = Op.getNode()->getNumValues() - 1; 1266 if (!NumArgs) 1267 return false; 1268 1269 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); 1270} 1271 1272/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires 1273/// the callee to pop its own arguments. Callee pop is necessary to support tail 1274/// calls. 1275bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) { 1276 if (IsVarArg) 1277 return false; 1278 1279 switch (CallingConv) { 1280 default: 1281 return false; 1282 case CallingConv::X86_StdCall: 1283 return !Subtarget->is64Bit(); 1284 case CallingConv::X86_FastCall: 1285 return !Subtarget->is64Bit(); 1286 case CallingConv::Fast: 1287 return PerformTailCallOpt; 1288 } 1289} 1290 1291/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1292/// given CallingConvention value. 1293CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const { 1294 if (Subtarget->is64Bit()) { 1295 if (Subtarget->isTargetWin64()) 1296 return CC_X86_Win64_C; 1297 else 1298 return CC_X86_64_C; 1299 } 1300 1301 if (CC == CallingConv::X86_FastCall) 1302 return CC_X86_32_FastCall; 1303 else if (CC == CallingConv::Fast) 1304 return CC_X86_32_FastCC; 1305 else 1306 return CC_X86_32_C; 1307} 1308 1309/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to 1310/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. 1311NameDecorationStyle 1312X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) { 1313 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 1314 if (CC == CallingConv::X86_FastCall) 1315 return FastCall; 1316 else if (CC == CallingConv::X86_StdCall) 1317 return StdCall; 1318 return None; 1319} 1320 1321 1322/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer 1323/// in a register before calling. 1324bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { 1325 return !IsTailCall && !Is64Bit && 1326 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1327 Subtarget->isPICStyleGOT(); 1328} 1329 1330/// CallRequiresFnAddressInReg - Check whether the call requires the function 1331/// address to be loaded in a register. 1332bool 1333X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { 1334 return !Is64Bit && IsTailCall && 1335 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1336 Subtarget->isPICStyleGOT(); 1337} 1338 1339/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1340/// by "Src" to address "Dst" with size and alignment information specified by 1341/// the specific parameter attribute. The copy will be passed as a byval 1342/// function parameter. 1343static SDValue 1344CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1345 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1346 DebugLoc dl) { 1347 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1348 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1349 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1350} 1351 1352SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG, 1353 const CCValAssign &VA, 1354 MachineFrameInfo *MFI, 1355 unsigned CC, 1356 SDValue Root, unsigned i) { 1357 // Create the nodes corresponding to a load from this parameter slot. 1358 ISD::ArgFlagsTy Flags = 1359 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); 1360 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; 1361 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1362 1363 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1364 // changed with more analysis. 1365 // In case of tail call optimization mark all arguments mutable. Since they 1366 // could be overwritten by lowering of arguments in case of a tail call. 1367 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 1368 VA.getLocMemOffset(), isImmutable); 1369 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1370 if (Flags.isByVal()) 1371 return FIN; 1372 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN, 1373 PseudoSourceValue::getFixedStack(FI), 0); 1374} 1375 1376SDValue 1377X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 1378 MachineFunction &MF = DAG.getMachineFunction(); 1379 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1380 DebugLoc dl = Op.getDebugLoc(); 1381 1382 const Function* Fn = MF.getFunction(); 1383 if (Fn->hasExternalLinkage() && 1384 Subtarget->isTargetCygMing() && 1385 Fn->getName() == "main") 1386 FuncInfo->setForceFramePointer(true); 1387 1388 // Decorate the function name. 1389 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); 1390 1391 MachineFrameInfo *MFI = MF.getFrameInfo(); 1392 SDValue Root = Op.getOperand(0); 1393 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1394 unsigned CC = MF.getFunction()->getCallingConv(); 1395 bool Is64Bit = Subtarget->is64Bit(); 1396 bool IsWin64 = Subtarget->isTargetWin64(); 1397 1398 assert(!(isVarArg && CC == CallingConv::Fast) && 1399 "Var args not supported with calling convention fastcc"); 1400 1401 // Assign locations to all of the incoming arguments. 1402 SmallVector<CCValAssign, 16> ArgLocs; 1403 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1404 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC)); 1405 1406 SmallVector<SDValue, 8> ArgValues; 1407 unsigned LastVal = ~0U; 1408 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1409 CCValAssign &VA = ArgLocs[i]; 1410 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1411 // places. 1412 assert(VA.getValNo() != LastVal && 1413 "Don't support value assigned to multiple locs yet"); 1414 LastVal = VA.getValNo(); 1415 1416 if (VA.isRegLoc()) { 1417 MVT RegVT = VA.getLocVT(); 1418 TargetRegisterClass *RC = NULL; 1419 if (RegVT == MVT::i32) 1420 RC = X86::GR32RegisterClass; 1421 else if (Is64Bit && RegVT == MVT::i64) 1422 RC = X86::GR64RegisterClass; 1423 else if (RegVT == MVT::f32) 1424 RC = X86::FR32RegisterClass; 1425 else if (RegVT == MVT::f64) 1426 RC = X86::FR64RegisterClass; 1427 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1428 RC = X86::VR128RegisterClass; 1429 else if (RegVT.isVector()) { 1430 assert(RegVT.getSizeInBits() == 64); 1431 if (!Is64Bit) 1432 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs. 1433 else { 1434 // Darwin calling convention passes MMX values in either GPRs or 1435 // XMMs in x86-64. Other targets pass them in memory. 1436 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) { 1437 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs. 1438 RegVT = MVT::v2i64; 1439 } else { 1440 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs. 1441 RegVT = MVT::i64; 1442 } 1443 } 1444 } else { 1445 assert(0 && "Unknown argument type!"); 1446 } 1447 1448 unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC); 1449 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); 1450 1451 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1452 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1453 // right size. 1454 if (VA.getLocInfo() == CCValAssign::SExt) 1455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1456 DAG.getValueType(VA.getValVT())); 1457 else if (VA.getLocInfo() == CCValAssign::ZExt) 1458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1459 DAG.getValueType(VA.getValVT())); 1460 1461 if (VA.getLocInfo() != CCValAssign::Full) 1462 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1463 1464 // Handle MMX values passed in GPRs. 1465 if (Is64Bit && RegVT != VA.getLocVT()) { 1466 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass) 1467 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue); 1468 else if (RC == X86::VR128RegisterClass) { 1469 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1470 ArgValue, DAG.getConstant(0, MVT::i64)); 1471 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue); 1472 } 1473 } 1474 1475 ArgValues.push_back(ArgValue); 1476 } else { 1477 assert(VA.isMemLoc()); 1478 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); 1479 } 1480 } 1481 1482 // The x86-64 ABI for returning structs by value requires that we copy 1483 // the sret argument into %rax for the return. Save the argument into 1484 // a virtual register so that we can access it from the return points. 1485 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1486 MachineFunction &MF = DAG.getMachineFunction(); 1487 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1488 unsigned Reg = FuncInfo->getSRetReturnReg(); 1489 if (!Reg) { 1490 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1491 FuncInfo->setSRetReturnReg(Reg); 1492 } 1493 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]); 1494 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root); 1495 } 1496 1497 unsigned StackSize = CCInfo.getNextStackOffset(); 1498 // align stack specially for tail calls 1499 if (PerformTailCallOpt && CC == CallingConv::Fast) 1500 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1501 1502 // If the function takes variable number of arguments, make a frame index for 1503 // the start of the first vararg value... for expansion of llvm.va_start. 1504 if (isVarArg) { 1505 if (Is64Bit || CC != CallingConv::X86_FastCall) { 1506 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1507 } 1508 if (Is64Bit) { 1509 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1510 1511 // FIXME: We should really autogenerate these arrays 1512 static const unsigned GPR64ArgRegsWin64[] = { 1513 X86::RCX, X86::RDX, X86::R8, X86::R9 1514 }; 1515 static const unsigned XMMArgRegsWin64[] = { 1516 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1517 }; 1518 static const unsigned GPR64ArgRegs64Bit[] = { 1519 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1520 }; 1521 static const unsigned XMMArgRegs64Bit[] = { 1522 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1523 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1524 }; 1525 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1526 1527 if (IsWin64) { 1528 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1529 GPR64ArgRegs = GPR64ArgRegsWin64; 1530 XMMArgRegs = XMMArgRegsWin64; 1531 } else { 1532 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1533 GPR64ArgRegs = GPR64ArgRegs64Bit; 1534 XMMArgRegs = XMMArgRegs64Bit; 1535 } 1536 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1537 TotalNumIntRegs); 1538 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1539 TotalNumXMMRegs); 1540 1541 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1543 "SSE register cannot be used when SSE is disabled!"); 1544 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1545 "SSE register cannot be used when SSE is disabled!"); 1546 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1547 // Kernel mode asks for SSE to be disabled, so don't push them 1548 // on the stack. 1549 TotalNumXMMRegs = 0; 1550 1551 // For X86-64, if there are vararg parameters that are passed via 1552 // registers, then we must store them to their spots on the stack so they 1553 // may be loaded by deferencing the result of va_next. 1554 VarArgsGPOffset = NumIntRegs * 8; 1555 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1556 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1557 TotalNumXMMRegs * 16, 16); 1558 1559 // Store the integer parameter registers. 1560 SmallVector<SDValue, 8> MemOps; 1561 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1562 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1563 DAG.getIntPtrConstant(VarArgsGPOffset)); 1564 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1565 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1566 X86::GR64RegisterClass); 1567 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); 1568 SDValue Store = 1569 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1570 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1571 MemOps.push_back(Store); 1572 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 1573 DAG.getIntPtrConstant(8)); 1574 } 1575 1576 // Now store the XMM (fp + vector) parameter registers. 1577 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1578 DAG.getIntPtrConstant(VarArgsFPOffset)); 1579 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1580 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1581 X86::VR128RegisterClass); 1582 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32); 1583 SDValue Store = 1584 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1585 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); 1586 MemOps.push_back(Store); 1587 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 1588 DAG.getIntPtrConstant(16)); 1589 } 1590 if (!MemOps.empty()) 1591 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1592 &MemOps[0], MemOps.size()); 1593 } 1594 } 1595 1596 ArgValues.push_back(Root); 1597 1598 // Some CCs need callee pop. 1599 if (IsCalleePop(isVarArg, CC)) { 1600 BytesToPopOnReturn = StackSize; // Callee pops everything. 1601 BytesCallerReserves = 0; 1602 } else { 1603 BytesToPopOnReturn = 0; // Callee pops nothing. 1604 // If this is an sret function, the return should pop the hidden pointer. 1605 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op)) 1606 BytesToPopOnReturn = 4; 1607 BytesCallerReserves = StackSize; 1608 } 1609 1610 if (!Is64Bit) { 1611 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1612 if (CC == CallingConv::X86_FastCall) 1613 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1614 } 1615 1616 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1617 1618 // Return the new list of results. 1619 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 1620 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 1621} 1622 1623SDValue 1624X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 1625 const SDValue &StackPtr, 1626 const CCValAssign &VA, 1627 SDValue Chain, 1628 SDValue Arg, ISD::ArgFlagsTy Flags) { 1629 DebugLoc dl = TheCall->getDebugLoc(); 1630 unsigned LocMemOffset = VA.getLocMemOffset(); 1631 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1632 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1633 if (Flags.isByVal()) { 1634 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1635 } 1636 return DAG.getStore(Chain, dl, Arg, PtrOff, 1637 PseudoSourceValue::getStack(), LocMemOffset); 1638} 1639 1640/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1641/// optimization is performed and it is required. 1642SDValue 1643X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1644 SDValue &OutRetAddr, 1645 SDValue Chain, 1646 bool IsTailCall, 1647 bool Is64Bit, 1648 int FPDiff, 1649 DebugLoc dl) { 1650 if (!IsTailCall || FPDiff==0) return Chain; 1651 1652 // Adjust the Return address stack slot. 1653 MVT VT = getPointerTy(); 1654 OutRetAddr = getReturnAddressFrameIndex(DAG); 1655 1656 // Load the "old" Return address. 1657 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0); 1658 return SDValue(OutRetAddr.getNode(), 1); 1659} 1660 1661/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1662/// optimization is performed and it is required (FPDiff!=0). 1663static SDValue 1664EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1665 SDValue Chain, SDValue RetAddrFrIdx, 1666 bool Is64Bit, int FPDiff, DebugLoc dl) { 1667 // Store the return address to the appropriate stack slot. 1668 if (!FPDiff) return Chain; 1669 // Calculate the new stack slot for the return address. 1670 int SlotSize = Is64Bit ? 8 : 4; 1671 int NewReturnAddrFI = 1672 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1673 MVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1674 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1675 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1676 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1677 return Chain; 1678} 1679 1680SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 1681 MachineFunction &MF = DAG.getMachineFunction(); 1682 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 1683 SDValue Chain = TheCall->getChain(); 1684 unsigned CC = TheCall->getCallingConv(); 1685 bool isVarArg = TheCall->isVarArg(); 1686 bool IsTailCall = TheCall->isTailCall() && 1687 CC == CallingConv::Fast && PerformTailCallOpt; 1688 SDValue Callee = TheCall->getCallee(); 1689 bool Is64Bit = Subtarget->is64Bit(); 1690 bool IsStructRet = CallIsStructReturn(TheCall); 1691 DebugLoc dl = TheCall->getDebugLoc(); 1692 1693 assert(!(isVarArg && CC == CallingConv::Fast) && 1694 "Var args not supported with calling convention fastcc"); 1695 1696 // Analyze operands of the call, assigning locations to each operand. 1697 SmallVector<CCValAssign, 16> ArgLocs; 1698 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1699 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC)); 1700 1701 // Get a count of how many bytes are to be pushed on the stack. 1702 unsigned NumBytes = CCInfo.getNextStackOffset(); 1703 if (PerformTailCallOpt && CC == CallingConv::Fast) 1704 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1705 1706 int FPDiff = 0; 1707 if (IsTailCall) { 1708 // Lower arguments at fp - stackoffset + fpdiff. 1709 unsigned NumBytesCallerPushed = 1710 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1711 FPDiff = NumBytesCallerPushed - NumBytes; 1712 1713 // Set the delta of movement of the returnaddr stackslot. 1714 // But only set if delta is greater than previous delta. 1715 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1716 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1717 } 1718 1719 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1720 1721 SDValue RetAddrFrIdx; 1722 // Load return adress for tail calls. 1723 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit, 1724 FPDiff, dl); 1725 1726 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1727 SmallVector<SDValue, 8> MemOpChains; 1728 SDValue StackPtr; 1729 1730 // Walk the register/memloc assignments, inserting copies/loads. In the case 1731 // of tail call optimization arguments are handle later. 1732 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1733 CCValAssign &VA = ArgLocs[i]; 1734 SDValue Arg = TheCall->getArg(i); 1735 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1736 bool isByVal = Flags.isByVal(); 1737 1738 // Promote the value if needed. 1739 switch (VA.getLocInfo()) { 1740 default: assert(0 && "Unknown loc info!"); 1741 case CCValAssign::Full: break; 1742 case CCValAssign::SExt: 1743 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1744 break; 1745 case CCValAssign::ZExt: 1746 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1747 break; 1748 case CCValAssign::AExt: 1749 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1750 break; 1751 } 1752 1753 if (VA.isRegLoc()) { 1754 if (Is64Bit) { 1755 MVT RegVT = VA.getLocVT(); 1756 if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1757 switch (VA.getLocReg()) { 1758 default: 1759 break; 1760 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX: 1761 case X86::R8: { 1762 // Special case: passing MMX values in GPR registers. 1763 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1764 break; 1765 } 1766 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3: 1767 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: { 1768 // Special case: passing MMX values in XMM registers. 1769 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1770 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1771 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1772 break; 1773 } 1774 } 1775 } 1776 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1777 } else { 1778 if (!IsTailCall || (IsTailCall && isByVal)) { 1779 assert(VA.isMemLoc()); 1780 if (StackPtr.getNode() == 0) 1781 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1782 1783 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, 1784 Chain, Arg, Flags)); 1785 } 1786 } 1787 } 1788 1789 if (!MemOpChains.empty()) 1790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1791 &MemOpChains[0], MemOpChains.size()); 1792 1793 // Build a sequence of copy-to-reg nodes chained together with token chain 1794 // and flag operands which copy the outgoing args into registers. 1795 SDValue InFlag; 1796 // Tail call byval lowering might overwrite argument registers so in case of 1797 // tail call optimization the copies to registers are lowered later. 1798 if (!IsTailCall) 1799 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1800 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1801 RegsToPass[i].second, InFlag); 1802 InFlag = Chain.getValue(1); 1803 } 1804 1805 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1806 // GOT pointer. 1807 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { 1808 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1809 DAG.getNode(X86ISD::GlobalBaseReg, 1810 DebugLoc::getUnknownLoc(), 1811 getPointerTy()), 1812 InFlag); 1813 InFlag = Chain.getValue(1); 1814 } 1815 // If we are tail calling and generating PIC/GOT style code load the address 1816 // of the callee into ecx. The value in ecx is used as target of the tail 1817 // jump. This is done to circumvent the ebx/callee-saved problem for tail 1818 // calls on PIC/GOT architectures. Normally we would just put the address of 1819 // GOT into ebx and then call target@PLT. But for tail callss ebx would be 1820 // restored (since ebx is callee saved) before jumping to the target@PLT. 1821 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { 1822 // Note: The actual moving to ecx is done further down. 1823 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1824 if (G && !G->getGlobal()->hasHiddenVisibility() && 1825 !G->getGlobal()->hasProtectedVisibility()) 1826 Callee = LowerGlobalAddress(Callee, DAG); 1827 else if (isa<ExternalSymbolSDNode>(Callee)) 1828 Callee = LowerExternalSymbol(Callee,DAG); 1829 } 1830 1831 if (Is64Bit && isVarArg) { 1832 // From AMD64 ABI document: 1833 // For calls that may call functions that use varargs or stdargs 1834 // (prototype-less calls or calls to functions containing ellipsis (...) in 1835 // the declaration) %al is used as hidden argument to specify the number 1836 // of SSE registers used. The contents of %al do not need to match exactly 1837 // the number of registers, but must be an ubound on the number of SSE 1838 // registers used and is in the range 0 - 8 inclusive. 1839 1840 // FIXME: Verify this on Win64 1841 // Count the number of XMM registers allocated. 1842 static const unsigned XMMArgRegs[] = { 1843 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1844 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1845 }; 1846 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1847 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1848 && "SSE registers cannot be used when SSE is disabled"); 1849 1850 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1851 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1852 InFlag = Chain.getValue(1); 1853 } 1854 1855 1856 // For tail calls lower the arguments to the 'real' stack slot. 1857 if (IsTailCall) { 1858 SmallVector<SDValue, 8> MemOpChains2; 1859 SDValue FIN; 1860 int FI = 0; 1861 // Do not flag preceeding copytoreg stuff together with the following stuff. 1862 InFlag = SDValue(); 1863 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1864 CCValAssign &VA = ArgLocs[i]; 1865 if (!VA.isRegLoc()) { 1866 assert(VA.isMemLoc()); 1867 SDValue Arg = TheCall->getArg(i); 1868 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 1869 // Create frame index. 1870 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1871 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1872 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1873 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1874 1875 if (Flags.isByVal()) { 1876 // Copy relative to framepointer. 1877 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1878 if (StackPtr.getNode() == 0) 1879 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1880 getPointerTy()); 1881 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 1882 1883 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain, 1884 Flags, DAG, dl)); 1885 } else { 1886 // Store relative to framepointer. 1887 MemOpChains2.push_back( 1888 DAG.getStore(Chain, dl, Arg, FIN, 1889 PseudoSourceValue::getFixedStack(FI), 0)); 1890 } 1891 } 1892 } 1893 1894 if (!MemOpChains2.empty()) 1895 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1896 &MemOpChains2[0], MemOpChains2.size()); 1897 1898 // Copy arguments to their registers. 1899 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1900 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1901 RegsToPass[i].second, InFlag); 1902 InFlag = Chain.getValue(1); 1903 } 1904 InFlag =SDValue(); 1905 1906 // Store the return address to the appropriate stack slot. 1907 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1908 FPDiff, dl); 1909 } 1910 1911 // If the callee is a GlobalAddress node (quite common, every direct call is) 1912 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1913 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1914 // We should use extra load for direct calls to dllimported functions in 1915 // non-JIT mode. 1916 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1917 getTargetMachine(), true)) 1918 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(), 1919 G->getOffset()); 1920 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1921 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1922 } else if (IsTailCall) { 1923 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX; 1924 1925 Chain = DAG.getCopyToReg(Chain, dl, 1926 DAG.getRegister(Opc, getPointerTy()), 1927 Callee,InFlag); 1928 Callee = DAG.getRegister(Opc, getPointerTy()); 1929 // Add register as live out. 1930 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); 1931 } 1932 1933 // Returns a chain & a flag for retval copy to use. 1934 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1935 SmallVector<SDValue, 8> Ops; 1936 1937 if (IsTailCall) { 1938 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1939 DAG.getIntPtrConstant(0, true), InFlag); 1940 InFlag = Chain.getValue(1); 1941 1942 // Returns a chain & a flag for retval copy to use. 1943 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1944 Ops.clear(); 1945 } 1946 1947 Ops.push_back(Chain); 1948 Ops.push_back(Callee); 1949 1950 if (IsTailCall) 1951 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1952 1953 // Add argument registers to the end of the list so that they are known live 1954 // into the call. 1955 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1956 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1957 RegsToPass[i].second.getValueType())); 1958 1959 // Add an implicit use GOT pointer in EBX. 1960 if (!IsTailCall && !Is64Bit && 1961 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1962 Subtarget->isPICStyleGOT()) 1963 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1964 1965 // Add an implicit use of AL for x86 vararg functions. 1966 if (Is64Bit && isVarArg) 1967 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1968 1969 if (InFlag.getNode()) 1970 Ops.push_back(InFlag); 1971 1972 if (IsTailCall) { 1973 assert(InFlag.getNode() && 1974 "Flag must be set. Depend on flag being set in LowerRET"); 1975 Chain = DAG.getNode(X86ISD::TAILCALL, dl, 1976 TheCall->getVTList(), &Ops[0], Ops.size()); 1977 1978 return SDValue(Chain.getNode(), Op.getResNo()); 1979 } 1980 1981 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 1982 InFlag = Chain.getValue(1); 1983 1984 // Create the CALLSEQ_END node. 1985 unsigned NumBytesForCalleeToPush; 1986 if (IsCalleePop(isVarArg, CC)) 1987 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 1988 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet) 1989 // If this is is a call to a struct-return function, the callee 1990 // pops the hidden struct pointer, so we have to push it back. 1991 // This is common for Darwin/X86, Linux & Mingw32 targets. 1992 NumBytesForCalleeToPush = 4; 1993 else 1994 NumBytesForCalleeToPush = 0; // Callee pops nothing. 1995 1996 // Returns a flag for retval copy to use. 1997 Chain = DAG.getCALLSEQ_END(Chain, 1998 DAG.getIntPtrConstant(NumBytes, true), 1999 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2000 true), 2001 InFlag); 2002 InFlag = Chain.getValue(1); 2003 2004 // Handle result values, copying them out of physregs into vregs that we 2005 // return. 2006 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 2007 Op.getResNo()); 2008} 2009 2010 2011//===----------------------------------------------------------------------===// 2012// Fast Calling Convention (tail call) implementation 2013//===----------------------------------------------------------------------===// 2014 2015// Like std call, callee cleans arguments, convention except that ECX is 2016// reserved for storing the tail called function address. Only 2 registers are 2017// free for argument passing (inreg). Tail call optimization is performed 2018// provided: 2019// * tailcallopt is enabled 2020// * caller/callee are fastcc 2021// On X86_64 architecture with GOT-style position independent code only local 2022// (within module) calls are supported at the moment. 2023// To keep the stack aligned according to platform abi the function 2024// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2025// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2026// If a tail called function callee has more arguments than the caller the 2027// caller needs to make sure that there is room to move the RETADDR to. This is 2028// achieved by reserving an area the size of the argument delta right after the 2029// original REtADDR, but before the saved framepointer or the spilled registers 2030// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2031// stack layout: 2032// arg1 2033// arg2 2034// RETADDR 2035// [ new RETADDR 2036// move area ] 2037// (possible EBP) 2038// ESI 2039// EDI 2040// local1 .. 2041 2042/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2043/// for a 16 byte align requirement. 2044unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2045 SelectionDAG& DAG) { 2046 MachineFunction &MF = DAG.getMachineFunction(); 2047 const TargetMachine &TM = MF.getTarget(); 2048 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2049 unsigned StackAlignment = TFI.getStackAlignment(); 2050 uint64_t AlignMask = StackAlignment - 1; 2051 int64_t Offset = StackSize; 2052 uint64_t SlotSize = TD->getPointerSize(); 2053 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2054 // Number smaller than 12 so just add the difference. 2055 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2056 } else { 2057 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2058 Offset = ((~AlignMask) & Offset) + StackAlignment + 2059 (StackAlignment-SlotSize); 2060 } 2061 return Offset; 2062} 2063 2064/// IsEligibleForTailCallElimination - Check to see whether the next instruction 2065/// following the call is a return. A function is eligible if caller/callee 2066/// calling conventions match, currently only fastcc supports tail calls, and 2067/// the function CALL is immediatly followed by a RET. 2068bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall, 2069 SDValue Ret, 2070 SelectionDAG& DAG) const { 2071 if (!PerformTailCallOpt) 2072 return false; 2073 2074 if (CheckTailCallReturnConstraints(TheCall, Ret)) { 2075 MachineFunction &MF = DAG.getMachineFunction(); 2076 unsigned CallerCC = MF.getFunction()->getCallingConv(); 2077 unsigned CalleeCC= TheCall->getCallingConv(); 2078 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2079 SDValue Callee = TheCall->getCallee(); 2080 // On x86/32Bit PIC/GOT tail calls are supported. 2081 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || 2082 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) 2083 return true; 2084 2085 // Can only do local tail calls (in same module, hidden or protected) on 2086 // x86_64 PIC/GOT at the moment. 2087 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2088 return G->getGlobal()->hasHiddenVisibility() 2089 || G->getGlobal()->hasProtectedVisibility(); 2090 } 2091 } 2092 2093 return false; 2094} 2095 2096FastISel * 2097X86TargetLowering::createFastISel(MachineFunction &mf, 2098 MachineModuleInfo *mmo, 2099 DwarfWriter *dw, 2100 DenseMap<const Value *, unsigned> &vm, 2101 DenseMap<const BasicBlock *, 2102 MachineBasicBlock *> &bm, 2103 DenseMap<const AllocaInst *, int> &am 2104#ifndef NDEBUG 2105 , SmallSet<Instruction*, 8> &cil 2106#endif 2107 ) { 2108 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2109#ifndef NDEBUG 2110 , cil 2111#endif 2112 ); 2113} 2114 2115 2116//===----------------------------------------------------------------------===// 2117// Other Lowering Hooks 2118//===----------------------------------------------------------------------===// 2119 2120 2121SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2122 MachineFunction &MF = DAG.getMachineFunction(); 2123 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2124 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2125 2126 if (ReturnAddrIndex == 0) { 2127 // Set up a frame object for the return address. 2128 uint64_t SlotSize = TD->getPointerSize(); 2129 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize); 2130 FuncInfo->setRAIndex(ReturnAddrIndex); 2131 } 2132 2133 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2134} 2135 2136 2137/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2138/// specific condition code, returning the condition code and the LHS/RHS of the 2139/// comparison to make. 2140static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2141 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2142 if (!isFP) { 2143 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2144 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2145 // X > -1 -> X == 0, jump !sign. 2146 RHS = DAG.getConstant(0, RHS.getValueType()); 2147 return X86::COND_NS; 2148 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2149 // X < 0 -> X == 0, jump on sign. 2150 return X86::COND_S; 2151 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2152 // X < 1 -> X <= 0 2153 RHS = DAG.getConstant(0, RHS.getValueType()); 2154 return X86::COND_LE; 2155 } 2156 } 2157 2158 switch (SetCCOpcode) { 2159 default: assert(0 && "Invalid integer condition!"); 2160 case ISD::SETEQ: return X86::COND_E; 2161 case ISD::SETGT: return X86::COND_G; 2162 case ISD::SETGE: return X86::COND_GE; 2163 case ISD::SETLT: return X86::COND_L; 2164 case ISD::SETLE: return X86::COND_LE; 2165 case ISD::SETNE: return X86::COND_NE; 2166 case ISD::SETULT: return X86::COND_B; 2167 case ISD::SETUGT: return X86::COND_A; 2168 case ISD::SETULE: return X86::COND_BE; 2169 case ISD::SETUGE: return X86::COND_AE; 2170 } 2171 } 2172 2173 // First determine if it is required or is profitable to flip the operands. 2174 2175 // If LHS is a foldable load, but RHS is not, flip the condition. 2176 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2177 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2178 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2179 std::swap(LHS, RHS); 2180 } 2181 2182 switch (SetCCOpcode) { 2183 default: break; 2184 case ISD::SETOLT: 2185 case ISD::SETOLE: 2186 case ISD::SETUGT: 2187 case ISD::SETUGE: 2188 std::swap(LHS, RHS); 2189 break; 2190 } 2191 2192 // On a floating point condition, the flags are set as follows: 2193 // ZF PF CF op 2194 // 0 | 0 | 0 | X > Y 2195 // 0 | 0 | 1 | X < Y 2196 // 1 | 0 | 0 | X == Y 2197 // 1 | 1 | 1 | unordered 2198 switch (SetCCOpcode) { 2199 default: assert(0 && "Condcode should be pre-legalized away"); 2200 case ISD::SETUEQ: 2201 case ISD::SETEQ: return X86::COND_E; 2202 case ISD::SETOLT: // flipped 2203 case ISD::SETOGT: 2204 case ISD::SETGT: return X86::COND_A; 2205 case ISD::SETOLE: // flipped 2206 case ISD::SETOGE: 2207 case ISD::SETGE: return X86::COND_AE; 2208 case ISD::SETUGT: // flipped 2209 case ISD::SETULT: 2210 case ISD::SETLT: return X86::COND_B; 2211 case ISD::SETUGE: // flipped 2212 case ISD::SETULE: 2213 case ISD::SETLE: return X86::COND_BE; 2214 case ISD::SETONE: 2215 case ISD::SETNE: return X86::COND_NE; 2216 case ISD::SETUO: return X86::COND_P; 2217 case ISD::SETO: return X86::COND_NP; 2218 } 2219} 2220 2221/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2222/// code. Current x86 isa includes the following FP cmov instructions: 2223/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2224static bool hasFPCMov(unsigned X86CC) { 2225 switch (X86CC) { 2226 default: 2227 return false; 2228 case X86::COND_B: 2229 case X86::COND_BE: 2230 case X86::COND_E: 2231 case X86::COND_P: 2232 case X86::COND_A: 2233 case X86::COND_AE: 2234 case X86::COND_NE: 2235 case X86::COND_NP: 2236 return true; 2237 } 2238} 2239 2240/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2241/// the specified range (L, H]. 2242static bool isUndefOrInRange(int Val, int Low, int Hi) { 2243 return (Val < 0) || (Val >= Low && Val < Hi); 2244} 2245 2246/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2247/// specified value. 2248static bool isUndefOrEqual(int Val, int CmpVal) { 2249 if (Val < 0 || Val == CmpVal) 2250 return true; 2251 return false; 2252} 2253 2254/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2255/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2256/// the second operand. 2257static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) { 2258 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2259 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2260 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2261 return (Mask[0] < 2 && Mask[1] < 2); 2262 return false; 2263} 2264 2265bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2266 SmallVector<int, 8> M; 2267 N->getMask(M); 2268 return ::isPSHUFDMask(M, N->getValueType(0)); 2269} 2270 2271/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2272/// is suitable for input to PSHUFHW. 2273static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) { 2274 if (VT != MVT::v8i16) 2275 return false; 2276 2277 // Lower quadword copied in order or undef. 2278 for (int i = 0; i != 4; ++i) 2279 if (Mask[i] >= 0 && Mask[i] != i) 2280 return false; 2281 2282 // Upper quadword shuffled. 2283 for (int i = 4; i != 8; ++i) 2284 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2285 return false; 2286 2287 return true; 2288} 2289 2290bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2291 SmallVector<int, 8> M; 2292 N->getMask(M); 2293 return ::isPSHUFHWMask(M, N->getValueType(0)); 2294} 2295 2296/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2297/// is suitable for input to PSHUFLW. 2298static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) { 2299 if (VT != MVT::v8i16) 2300 return false; 2301 2302 // Upper quadword copied in order. 2303 for (int i = 4; i != 8; ++i) 2304 if (Mask[i] >= 0 && Mask[i] != i) 2305 return false; 2306 2307 // Lower quadword shuffled. 2308 for (int i = 0; i != 4; ++i) 2309 if (Mask[i] >= 4) 2310 return false; 2311 2312 return true; 2313} 2314 2315bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2316 SmallVector<int, 8> M; 2317 N->getMask(M); 2318 return ::isPSHUFLWMask(M, N->getValueType(0)); 2319} 2320 2321/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2322/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2323static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) { 2324 int NumElems = VT.getVectorNumElements(); 2325 if (NumElems != 2 && NumElems != 4) 2326 return false; 2327 2328 int Half = NumElems / 2; 2329 for (int i = 0; i < Half; ++i) 2330 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2331 return false; 2332 for (int i = Half; i < NumElems; ++i) 2333 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2334 return false; 2335 2336 return true; 2337} 2338 2339bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2340 SmallVector<int, 8> M; 2341 N->getMask(M); 2342 return ::isSHUFPMask(M, N->getValueType(0)); 2343} 2344 2345/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2346/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2347/// half elements to come from vector 1 (which would equal the dest.) and 2348/// the upper half to come from vector 2. 2349static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) { 2350 int NumElems = VT.getVectorNumElements(); 2351 2352 if (NumElems != 2 && NumElems != 4) 2353 return false; 2354 2355 int Half = NumElems / 2; 2356 for (int i = 0; i < Half; ++i) 2357 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2358 return false; 2359 for (int i = Half; i < NumElems; ++i) 2360 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2361 return false; 2362 return true; 2363} 2364 2365static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2366 SmallVector<int, 8> M; 2367 N->getMask(M); 2368 return isCommutedSHUFPMask(M, N->getValueType(0)); 2369} 2370 2371/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2372/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2373bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2374 if (N->getValueType(0).getVectorNumElements() != 4) 2375 return false; 2376 2377 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2378 return isUndefOrEqual(N->getMaskElt(0), 6) && 2379 isUndefOrEqual(N->getMaskElt(1), 7) && 2380 isUndefOrEqual(N->getMaskElt(2), 2) && 2381 isUndefOrEqual(N->getMaskElt(3), 3); 2382} 2383 2384/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2385/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2386bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2387 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2388 2389 if (NumElems != 2 && NumElems != 4) 2390 return false; 2391 2392 for (unsigned i = 0; i < NumElems/2; ++i) 2393 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2394 return false; 2395 2396 for (unsigned i = NumElems/2; i < NumElems; ++i) 2397 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2398 return false; 2399 2400 return true; 2401} 2402 2403/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2404/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2405/// and MOVLHPS. 2406bool X86::isMOVHPMask(ShuffleVectorSDNode *N) { 2407 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2408 2409 if (NumElems != 2 && NumElems != 4) 2410 return false; 2411 2412 for (unsigned i = 0; i < NumElems/2; ++i) 2413 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2414 return false; 2415 2416 for (unsigned i = 0; i < NumElems/2; ++i) 2417 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2418 return false; 2419 2420 return true; 2421} 2422 2423/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2424/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2425/// <2, 3, 2, 3> 2426bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2427 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2428 2429 if (NumElems != 4) 2430 return false; 2431 2432 return isUndefOrEqual(N->getMaskElt(0), 2) && 2433 isUndefOrEqual(N->getMaskElt(1), 3) && 2434 isUndefOrEqual(N->getMaskElt(2), 2) && 2435 isUndefOrEqual(N->getMaskElt(3), 3); 2436} 2437 2438/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2439/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2440static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT, 2441 bool V2IsSplat = false) { 2442 int NumElts = VT.getVectorNumElements(); 2443 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2444 return false; 2445 2446 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2447 int BitI = Mask[i]; 2448 int BitI1 = Mask[i+1]; 2449 if (!isUndefOrEqual(BitI, j)) 2450 return false; 2451 if (V2IsSplat) { 2452 if (!isUndefOrEqual(BitI1, NumElts)) 2453 return false; 2454 } else { 2455 if (!isUndefOrEqual(BitI1, j + NumElts)) 2456 return false; 2457 } 2458 } 2459 return true; 2460} 2461 2462bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2463 SmallVector<int, 8> M; 2464 N->getMask(M); 2465 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2466} 2467 2468/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2469/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2470static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT, 2471 bool V2IsSplat = false) { 2472 int NumElts = VT.getVectorNumElements(); 2473 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2474 return false; 2475 2476 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2477 int BitI = Mask[i]; 2478 int BitI1 = Mask[i+1]; 2479 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2480 return false; 2481 if (V2IsSplat) { 2482 if (isUndefOrEqual(BitI1, NumElts)) 2483 return false; 2484 } else { 2485 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2486 return false; 2487 } 2488 } 2489 return true; 2490} 2491 2492bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2493 SmallVector<int, 8> M; 2494 N->getMask(M); 2495 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2496} 2497 2498/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2499/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2500/// <0, 0, 1, 1> 2501static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) { 2502 int NumElems = VT.getVectorNumElements(); 2503 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2504 return false; 2505 2506 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2507 int BitI = Mask[i]; 2508 int BitI1 = Mask[i+1]; 2509 if (!isUndefOrEqual(BitI, j)) 2510 return false; 2511 if (!isUndefOrEqual(BitI1, j)) 2512 return false; 2513 } 2514 return true; 2515} 2516 2517bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2518 SmallVector<int, 8> M; 2519 N->getMask(M); 2520 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2521} 2522 2523/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2524/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2525/// <2, 2, 3, 3> 2526static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) { 2527 int NumElems = VT.getVectorNumElements(); 2528 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2529 return false; 2530 2531 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2532 int BitI = Mask[i]; 2533 int BitI1 = Mask[i+1]; 2534 if (!isUndefOrEqual(BitI, j)) 2535 return false; 2536 if (!isUndefOrEqual(BitI1, j)) 2537 return false; 2538 } 2539 return true; 2540} 2541 2542bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2543 SmallVector<int, 8> M; 2544 N->getMask(M); 2545 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2546} 2547 2548/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2549/// specifies a shuffle of elements that is suitable for input to MOVSS, 2550/// MOVSD, and MOVD, i.e. setting the lowest element. 2551static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) { 2552 if (VT.getVectorElementType().getSizeInBits() < 32) 2553 return false; 2554 2555 int NumElts = VT.getVectorNumElements(); 2556 2557 if (!isUndefOrEqual(Mask[0], NumElts)) 2558 return false; 2559 2560 for (int i = 1; i < NumElts; ++i) 2561 if (!isUndefOrEqual(Mask[i], i)) 2562 return false; 2563 2564 return true; 2565} 2566 2567bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2568 SmallVector<int, 8> M; 2569 N->getMask(M); 2570 return ::isMOVLMask(M, N->getValueType(0)); 2571} 2572 2573/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2574/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2575/// element of vector 2 and the other elements to come from vector 1 in order. 2576static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT, 2577 bool V2IsSplat = false, bool V2IsUndef = false) { 2578 int NumOps = VT.getVectorNumElements(); 2579 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2580 return false; 2581 2582 if (!isUndefOrEqual(Mask[0], 0)) 2583 return false; 2584 2585 for (int i = 1; i < NumOps; ++i) 2586 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2587 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2588 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2589 return false; 2590 2591 return true; 2592} 2593 2594static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2595 bool V2IsUndef = false) { 2596 SmallVector<int, 8> M; 2597 N->getMask(M); 2598 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2599} 2600 2601/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2602/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2603bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2604 if (N->getValueType(0).getVectorNumElements() != 4) 2605 return false; 2606 2607 // Expect 1, 1, 3, 3 2608 for (unsigned i = 0; i < 2; ++i) { 2609 int Elt = N->getMaskElt(i); 2610 if (Elt >= 0 && Elt != 1) 2611 return false; 2612 } 2613 2614 bool HasHi = false; 2615 for (unsigned i = 2; i < 4; ++i) { 2616 int Elt = N->getMaskElt(i); 2617 if (Elt >= 0 && Elt != 3) 2618 return false; 2619 if (Elt == 3) 2620 HasHi = true; 2621 } 2622 // Don't use movshdup if it can be done with a shufps. 2623 // FIXME: verify that matching u, u, 3, 3 is what we want. 2624 return HasHi; 2625} 2626 2627/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2628/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2629bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 2630 if (N->getValueType(0).getVectorNumElements() != 4) 2631 return false; 2632 2633 // Expect 0, 0, 2, 2 2634 for (unsigned i = 0; i < 2; ++i) 2635 if (N->getMaskElt(i) > 0) 2636 return false; 2637 2638 bool HasHi = false; 2639 for (unsigned i = 2; i < 4; ++i) { 2640 int Elt = N->getMaskElt(i); 2641 if (Elt >= 0 && Elt != 2) 2642 return false; 2643 if (Elt == 2) 2644 HasHi = true; 2645 } 2646 // Don't use movsldup if it can be done with a shufps. 2647 return HasHi; 2648} 2649 2650/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2651/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2652bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 2653 int e = N->getValueType(0).getVectorNumElements() / 2; 2654 2655 for (int i = 0; i < e; ++i) 2656 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2657 return false; 2658 for (int i = 0; i < e; ++i) 2659 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 2660 return false; 2661 return true; 2662} 2663 2664/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2665/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2666/// instructions. 2667unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2668 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2669 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 2670 2671 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2672 unsigned Mask = 0; 2673 for (int i = 0; i < NumOperands; ++i) { 2674 int Val = SVOp->getMaskElt(NumOperands-i-1); 2675 if (Val < 0) Val = 0; 2676 if (Val >= NumOperands) Val -= NumOperands; 2677 Mask |= Val; 2678 if (i != NumOperands - 1) 2679 Mask <<= Shift; 2680 } 2681 return Mask; 2682} 2683 2684/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2685/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2686/// instructions. 2687unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2689 unsigned Mask = 0; 2690 // 8 nodes, but we only care about the last 4. 2691 for (unsigned i = 7; i >= 4; --i) { 2692 int Val = SVOp->getMaskElt(i); 2693 if (Val >= 0) 2694 Mask |= (Val - 4); 2695 if (i != 4) 2696 Mask <<= 2; 2697 } 2698 return Mask; 2699} 2700 2701/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2702/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2703/// instructions. 2704unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2705 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2706 unsigned Mask = 0; 2707 // 8 nodes, but we only care about the first 4. 2708 for (int i = 3; i >= 0; --i) { 2709 int Val = SVOp->getMaskElt(i); 2710 if (Val >= 0) 2711 Mask |= Val; 2712 if (i != 0) 2713 Mask <<= 2; 2714 } 2715 return Mask; 2716} 2717 2718/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 2719/// their permute mask. 2720static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 2721 SelectionDAG &DAG) { 2722 MVT VT = SVOp->getValueType(0); 2723 unsigned NumElems = VT.getVectorNumElements(); 2724 SmallVector<int, 8> MaskVec; 2725 2726 for (unsigned i = 0; i != NumElems; ++i) { 2727 int idx = SVOp->getMaskElt(i); 2728 if (idx < 0) 2729 MaskVec.push_back(idx); 2730 else if (idx < (int)NumElems) 2731 MaskVec.push_back(idx + NumElems); 2732 else 2733 MaskVec.push_back(idx - NumElems); 2734 } 2735 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 2736 SVOp->getOperand(0), &MaskVec[0]); 2737} 2738 2739/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2740/// the two vector operands have swapped position. 2741static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) { 2742 unsigned NumElems = VT.getVectorNumElements(); 2743 for (unsigned i = 0; i != NumElems; ++i) { 2744 int idx = Mask[i]; 2745 if (idx < 0) 2746 continue; 2747 else if (idx < (int)NumElems) 2748 Mask[i] = idx + NumElems; 2749 else 2750 Mask[i] = idx - NumElems; 2751 } 2752} 2753 2754/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2755/// match movhlps. The lower half elements should come from upper half of 2756/// V1 (and in order), and the upper half elements should come from the upper 2757/// half of V2 (and in order). 2758static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 2759 if (Op->getValueType(0).getVectorNumElements() != 4) 2760 return false; 2761 for (unsigned i = 0, e = 2; i != e; ++i) 2762 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 2763 return false; 2764 for (unsigned i = 2; i != 4; ++i) 2765 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 2766 return false; 2767 return true; 2768} 2769 2770/// isScalarLoadToVector - Returns true if the node is a scalar load that 2771/// is promoted to a vector. It also returns the LoadSDNode by reference if 2772/// required. 2773static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2774 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 2775 return false; 2776 N = N->getOperand(0).getNode(); 2777 if (!ISD::isNON_EXTLoad(N)) 2778 return false; 2779 if (LD) 2780 *LD = cast<LoadSDNode>(N); 2781 return true; 2782} 2783 2784/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2785/// match movlp{s|d}. The lower half elements should come from lower half of 2786/// V1 (and in order), and the upper half elements should come from the upper 2787/// half of V2 (and in order). And since V1 will become the source of the 2788/// MOVLP, it must be either a vector load or a scalar load to vector. 2789static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 2790 ShuffleVectorSDNode *Op) { 2791 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2792 return false; 2793 // Is V2 is a vector load, don't do this transformation. We will try to use 2794 // load folding shufps op. 2795 if (ISD::isNON_EXTLoad(V2)) 2796 return false; 2797 2798 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 2799 2800 if (NumElems != 2 && NumElems != 4) 2801 return false; 2802 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2803 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 2804 return false; 2805 for (unsigned i = NumElems/2; i != NumElems; ++i) 2806 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 2807 return false; 2808 return true; 2809} 2810 2811/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2812/// all the same. 2813static bool isSplatVector(SDNode *N) { 2814 if (N->getOpcode() != ISD::BUILD_VECTOR) 2815 return false; 2816 2817 SDValue SplatValue = N->getOperand(0); 2818 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2819 if (N->getOperand(i) != SplatValue) 2820 return false; 2821 return true; 2822} 2823 2824/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2825/// constant +0.0. 2826static inline bool isZeroNode(SDValue Elt) { 2827 return ((isa<ConstantSDNode>(Elt) && 2828 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 2829 (isa<ConstantFPSDNode>(Elt) && 2830 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2831} 2832 2833/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2834/// to an zero vector. 2835/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 2836static bool isZeroShuffle(ShuffleVectorSDNode *N) { 2837 SDValue V1 = N->getOperand(0); 2838 SDValue V2 = N->getOperand(1); 2839 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2840 for (unsigned i = 0; i != NumElems; ++i) { 2841 int Idx = N->getMaskElt(i); 2842 if (Idx >= (int)NumElems) { 2843 unsigned Opc = V2.getOpcode(); 2844 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 2845 continue; 2846 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V2.getOperand(Idx-NumElems))) 2847 return false; 2848 } else if (Idx >= 0) { 2849 unsigned Opc = V1.getOpcode(); 2850 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 2851 continue; 2852 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V1.getOperand(Idx))) 2853 return false; 2854 } 2855 } 2856 return true; 2857} 2858 2859/// getZeroVector - Returns a vector of specified type with all zero elements. 2860/// 2861static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG, 2862 DebugLoc dl) { 2863 assert(VT.isVector() && "Expected a vector type"); 2864 2865 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2866 // type. This ensures they get CSE'd. 2867 SDValue Vec; 2868 if (VT.getSizeInBits() == 64) { // MMX 2869 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2870 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2871 } else if (HasSSE2) { // SSE2 2872 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2873 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2874 } else { // SSE1 2875 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2876 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 2877 } 2878 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2879} 2880 2881/// getOnesVector - Returns a vector of specified type with all bits set. 2882/// 2883static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { 2884 assert(VT.isVector() && "Expected a vector type"); 2885 2886 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2887 // type. This ensures they get CSE'd. 2888 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2889 SDValue Vec; 2890 if (VT.getSizeInBits() == 64) // MMX 2891 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2892 else // SSE 2893 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2894 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2895} 2896 2897 2898/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2899/// that point to V2 points to its first element. 2900static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 2901 MVT VT = SVOp->getValueType(0); 2902 unsigned NumElems = VT.getVectorNumElements(); 2903 2904 bool Changed = false; 2905 SmallVector<int, 8> MaskVec; 2906 SVOp->getMask(MaskVec); 2907 2908 for (unsigned i = 0; i != NumElems; ++i) { 2909 if (MaskVec[i] > (int)NumElems) { 2910 MaskVec[i] = NumElems; 2911 Changed = true; 2912 } 2913 } 2914 if (Changed) 2915 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 2916 SVOp->getOperand(1), &MaskVec[0]); 2917 return SDValue(SVOp, 0); 2918} 2919 2920/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2921/// operation of specified width. 2922static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, 2923 SDValue V2) { 2924 unsigned NumElems = VT.getVectorNumElements(); 2925 SmallVector<int, 8> Mask; 2926 Mask.push_back(NumElems); 2927 for (unsigned i = 1; i != NumElems; ++i) 2928 Mask.push_back(i); 2929 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 2930} 2931 2932/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 2933static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, 2934 SDValue V2) { 2935 unsigned NumElems = VT.getVectorNumElements(); 2936 SmallVector<int, 8> Mask; 2937 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2938 Mask.push_back(i); 2939 Mask.push_back(i + NumElems); 2940 } 2941 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 2942} 2943 2944/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 2945static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, 2946 SDValue V2) { 2947 unsigned NumElems = VT.getVectorNumElements(); 2948 unsigned Half = NumElems/2; 2949 SmallVector<int, 8> Mask; 2950 for (unsigned i = 0; i != Half; ++i) { 2951 Mask.push_back(i + Half); 2952 Mask.push_back(i + NumElems + Half); 2953 } 2954 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 2955} 2956 2957/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 2958static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 2959 bool HasSSE2) { 2960 if (SV->getValueType(0).getVectorNumElements() <= 4) 2961 return SDValue(SV, 0); 2962 2963 MVT PVT = MVT::v4f32; 2964 MVT VT = SV->getValueType(0); 2965 DebugLoc dl = SV->getDebugLoc(); 2966 SDValue V1 = SV->getOperand(0); 2967 int NumElems = VT.getVectorNumElements(); 2968 int EltNo = SV->getSplatIndex(); 2969 2970 // unpack elements to the correct location 2971 while (NumElems > 4) { 2972 if (EltNo < NumElems/2) { 2973 V1 = getUnpackl(DAG, dl, VT, V1, V1); 2974 } else { 2975 V1 = getUnpackh(DAG, dl, VT, V1, V1); 2976 EltNo -= NumElems/2; 2977 } 2978 NumElems >>= 1; 2979 } 2980 2981 // Perform the splat. 2982 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 2983 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 2984 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 2985 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 2986} 2987 2988/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 2989/// vector of zero or undef vector. This produces a shuffle where the low 2990/// element of V2 is swizzled into the zero/undef vector, landing at element 2991/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 2992static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 2993 bool isZero, bool HasSSE2, 2994 SelectionDAG &DAG) { 2995 MVT VT = V2.getValueType(); 2996 SDValue V1 = isZero 2997 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 2998 unsigned NumElems = VT.getVectorNumElements(); 2999 SmallVector<int, 16> MaskVec; 3000 for (unsigned i = 0; i != NumElems; ++i) 3001 // If this is the insertion idx, put the low elt of V2 here. 3002 MaskVec.push_back(i == Idx ? NumElems : i); 3003 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3004} 3005 3006/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3007/// a shuffle that is zero. 3008static 3009unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3010 bool Low, SelectionDAG &DAG) { 3011 unsigned NumZeros = 0; 3012 for (int i = 0; i < NumElems; ++i) { 3013 unsigned Index = Low ? i : NumElems-i-1; 3014 int Idx = SVOp->getMaskElt(Index); 3015 if (Idx < 0) { 3016 ++NumZeros; 3017 continue; 3018 } 3019 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3020 if (Elt.getNode() && isZeroNode(Elt)) 3021 ++NumZeros; 3022 else 3023 break; 3024 } 3025 return NumZeros; 3026} 3027 3028/// isVectorShift - Returns true if the shuffle can be implemented as a 3029/// logical left or right shift of a vector. 3030/// FIXME: split into pslldqi, psrldqi, palignr variants. 3031static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3032 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3033 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3034 3035 isLeft = true; 3036 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3037 if (!NumZeros) { 3038 isLeft = false; 3039 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3040 if (!NumZeros) 3041 return false; 3042 } 3043 bool SeenV1 = false; 3044 bool SeenV2 = false; 3045 for (int i = NumZeros; i < NumElems; ++i) { 3046 int Val = isLeft ? (i - NumZeros) : i; 3047 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3048 if (Idx < 0) 3049 continue; 3050 if (Idx < NumElems) 3051 SeenV1 = true; 3052 else { 3053 Idx -= NumElems; 3054 SeenV2 = true; 3055 } 3056 if (Idx != Val) 3057 return false; 3058 } 3059 if (SeenV1 && SeenV2) 3060 return false; 3061 3062 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3063 ShAmt = NumZeros; 3064 return true; 3065} 3066 3067 3068/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3069/// 3070static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3071 unsigned NumNonZero, unsigned NumZero, 3072 SelectionDAG &DAG, TargetLowering &TLI) { 3073 if (NumNonZero > 8) 3074 return SDValue(); 3075 3076 DebugLoc dl = Op.getDebugLoc(); 3077 SDValue V(0, 0); 3078 bool First = true; 3079 for (unsigned i = 0; i < 16; ++i) { 3080 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3081 if (ThisIsNonZero && First) { 3082 if (NumZero) 3083 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3084 else 3085 V = DAG.getUNDEF(MVT::v8i16); 3086 First = false; 3087 } 3088 3089 if ((i & 1) != 0) { 3090 SDValue ThisElt(0, 0), LastElt(0, 0); 3091 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3092 if (LastIsNonZero) { 3093 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3094 MVT::i16, Op.getOperand(i-1)); 3095 } 3096 if (ThisIsNonZero) { 3097 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3098 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3099 ThisElt, DAG.getConstant(8, MVT::i8)); 3100 if (LastIsNonZero) 3101 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3102 } else 3103 ThisElt = LastElt; 3104 3105 if (ThisElt.getNode()) 3106 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3107 DAG.getIntPtrConstant(i/2)); 3108 } 3109 } 3110 3111 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3112} 3113 3114/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3115/// 3116static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3117 unsigned NumNonZero, unsigned NumZero, 3118 SelectionDAG &DAG, TargetLowering &TLI) { 3119 if (NumNonZero > 4) 3120 return SDValue(); 3121 3122 DebugLoc dl = Op.getDebugLoc(); 3123 SDValue V(0, 0); 3124 bool First = true; 3125 for (unsigned i = 0; i < 8; ++i) { 3126 bool isNonZero = (NonZeros & (1 << i)) != 0; 3127 if (isNonZero) { 3128 if (First) { 3129 if (NumZero) 3130 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3131 else 3132 V = DAG.getUNDEF(MVT::v8i16); 3133 First = false; 3134 } 3135 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3136 MVT::v8i16, V, Op.getOperand(i), 3137 DAG.getIntPtrConstant(i)); 3138 } 3139 } 3140 3141 return V; 3142} 3143 3144/// getVShift - Return a vector logical shift node. 3145/// 3146static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, 3147 unsigned NumBits, SelectionDAG &DAG, 3148 const TargetLowering &TLI, DebugLoc dl) { 3149 bool isMMX = VT.getSizeInBits() == 64; 3150 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3151 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3152 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3153 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3154 DAG.getNode(Opc, dl, ShVT, SrcOp, 3155 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3156} 3157 3158SDValue 3159X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3160 DebugLoc dl = Op.getDebugLoc(); 3161 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3162 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3163 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3164 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3165 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3166 // eliminated on x86-32 hosts. 3167 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3168 return Op; 3169 3170 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3171 return getOnesVector(Op.getValueType(), DAG, dl); 3172 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3173 } 3174 3175 MVT VT = Op.getValueType(); 3176 MVT EVT = VT.getVectorElementType(); 3177 unsigned EVTBits = EVT.getSizeInBits(); 3178 3179 unsigned NumElems = Op.getNumOperands(); 3180 unsigned NumZero = 0; 3181 unsigned NumNonZero = 0; 3182 unsigned NonZeros = 0; 3183 bool IsAllConstants = true; 3184 SmallSet<SDValue, 8> Values; 3185 for (unsigned i = 0; i < NumElems; ++i) { 3186 SDValue Elt = Op.getOperand(i); 3187 if (Elt.getOpcode() == ISD::UNDEF) 3188 continue; 3189 Values.insert(Elt); 3190 if (Elt.getOpcode() != ISD::Constant && 3191 Elt.getOpcode() != ISD::ConstantFP) 3192 IsAllConstants = false; 3193 if (isZeroNode(Elt)) 3194 NumZero++; 3195 else { 3196 NonZeros |= (1 << i); 3197 NumNonZero++; 3198 } 3199 } 3200 3201 if (NumNonZero == 0) { 3202 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3203 return DAG.getUNDEF(VT); 3204 } 3205 3206 // Special case for single non-zero, non-undef, element. 3207 if (NumNonZero == 1) { 3208 unsigned Idx = CountTrailingZeros_32(NonZeros); 3209 SDValue Item = Op.getOperand(Idx); 3210 3211 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3212 // the value are obviously zero, truncate the value to i32 and do the 3213 // insertion that way. Only do this if the value is non-constant or if the 3214 // value is a constant being inserted into element 0. It is cheaper to do 3215 // a constant pool load than it is to do a movd + shuffle. 3216 if (EVT == MVT::i64 && !Subtarget->is64Bit() && 3217 (!IsAllConstants || Idx == 0)) { 3218 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3219 // Handle MMX and SSE both. 3220 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3221 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3222 3223 // Truncate the value (which may itself be a constant) to i32, and 3224 // convert it to a vector with movd (S2V+shuffle to zero extend). 3225 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3226 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3227 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3228 Subtarget->hasSSE2(), DAG); 3229 3230 // Now we have our 32-bit value zero extended in the low element of 3231 // a vector. If Idx != 0, swizzle it into place. 3232 if (Idx != 0) { 3233 SmallVector<int, 4> Mask; 3234 Mask.push_back(Idx); 3235 for (unsigned i = 1; i != VecElts; ++i) 3236 Mask.push_back(i); 3237 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3238 DAG.getUNDEF(Item.getValueType()), 3239 &Mask[0]); 3240 } 3241 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3242 } 3243 } 3244 3245 // If we have a constant or non-constant insertion into the low element of 3246 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3247 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3248 // depending on what the source datatype is. 3249 if (Idx == 0) { 3250 if (NumZero == 0) { 3251 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3252 } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 || 3253 (EVT == MVT::i64 && Subtarget->is64Bit())) { 3254 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3255 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3256 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3257 DAG); 3258 } else if (EVT == MVT::i16 || EVT == MVT::i8) { 3259 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3260 MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3261 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3262 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3263 Subtarget->hasSSE2(), DAG); 3264 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3265 } 3266 } 3267 3268 // Is it a vector logical left shift? 3269 if (NumElems == 2 && Idx == 1 && 3270 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) { 3271 unsigned NumBits = VT.getSizeInBits(); 3272 return getVShift(true, VT, 3273 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3274 VT, Op.getOperand(1)), 3275 NumBits/2, DAG, *this, dl); 3276 } 3277 3278 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3279 return SDValue(); 3280 3281 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3282 // is a non-constant being inserted into an element other than the low one, 3283 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3284 // movd/movss) to move this into the low element, then shuffle it into 3285 // place. 3286 if (EVTBits == 32) { 3287 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3288 3289 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3290 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3291 Subtarget->hasSSE2(), DAG); 3292 SmallVector<int, 8> MaskVec; 3293 for (unsigned i = 0; i < NumElems; i++) 3294 MaskVec.push_back(i == Idx ? 0 : 1); 3295 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3296 } 3297 } 3298 3299 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3300 if (Values.size() == 1) 3301 return SDValue(); 3302 3303 // A vector full of immediates; various special cases are already 3304 // handled, so this is best done with a single constant-pool load. 3305 if (IsAllConstants) 3306 return SDValue(); 3307 3308 // Let legalizer expand 2-wide build_vectors. 3309 if (EVTBits == 64) { 3310 if (NumNonZero == 1) { 3311 // One half is zero or undef. 3312 unsigned Idx = CountTrailingZeros_32(NonZeros); 3313 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3314 Op.getOperand(Idx)); 3315 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3316 Subtarget->hasSSE2(), DAG); 3317 } 3318 return SDValue(); 3319 } 3320 3321 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3322 if (EVTBits == 8 && NumElems == 16) { 3323 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3324 *this); 3325 if (V.getNode()) return V; 3326 } 3327 3328 if (EVTBits == 16 && NumElems == 8) { 3329 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3330 *this); 3331 if (V.getNode()) return V; 3332 } 3333 3334 // If element VT is == 32 bits, turn it into a number of shuffles. 3335 SmallVector<SDValue, 8> V; 3336 V.resize(NumElems); 3337 if (NumElems == 4 && NumZero > 0) { 3338 for (unsigned i = 0; i < 4; ++i) { 3339 bool isZero = !(NonZeros & (1 << i)); 3340 if (isZero) 3341 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3342 else 3343 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3344 } 3345 3346 for (unsigned i = 0; i < 2; ++i) { 3347 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3348 default: break; 3349 case 0: 3350 V[i] = V[i*2]; // Must be a zero vector. 3351 break; 3352 case 1: 3353 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3354 break; 3355 case 2: 3356 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3357 break; 3358 case 3: 3359 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3360 break; 3361 } 3362 } 3363 3364 SmallVector<int, 8> MaskVec; 3365 bool Reverse = (NonZeros & 0x3) == 2; 3366 for (unsigned i = 0; i < 2; ++i) 3367 MaskVec.push_back(Reverse ? 1-i : i); 3368 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3369 for (unsigned i = 0; i < 2; ++i) 3370 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3371 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3372 } 3373 3374 if (Values.size() > 2) { 3375 // If we have SSE 4.1, Expand into a number of inserts unless the number of 3376 // values to be inserted is equal to the number of elements, in which case 3377 // use the unpack code below in the hopes of matching the consecutive elts 3378 // load merge pattern for shuffles. 3379 // FIXME: We could probably just check that here directly. 3380 if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 3381 getSubtarget()->hasSSE41()) { 3382 V[0] = DAG.getUNDEF(VT); 3383 for (unsigned i = 0; i < NumElems; ++i) 3384 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3385 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3386 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3387 return V[0]; 3388 } 3389 // Expand into a number of unpckl*. 3390 // e.g. for v4f32 3391 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3392 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3393 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3394 for (unsigned i = 0; i < NumElems; ++i) 3395 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3396 NumElems >>= 1; 3397 while (NumElems != 0) { 3398 for (unsigned i = 0; i < NumElems; ++i) 3399 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3400 NumElems >>= 1; 3401 } 3402 return V[0]; 3403 } 3404 3405 return SDValue(); 3406} 3407 3408// v8i16 shuffles - Prefer shuffles in the following order: 3409// 1. [all] pshuflw, pshufhw, optional move 3410// 2. [ssse3] 1 x pshufb 3411// 3. [ssse3] 2 x pshufb + 1 x por 3412// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3413static 3414SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3415 SelectionDAG &DAG, X86TargetLowering &TLI) { 3416 SDValue V1 = SVOp->getOperand(0); 3417 SDValue V2 = SVOp->getOperand(1); 3418 DebugLoc dl = SVOp->getDebugLoc(); 3419 SmallVector<int, 8> MaskVals; 3420 3421 // Determine if more than 1 of the words in each of the low and high quadwords 3422 // of the result come from the same quadword of one of the two inputs. Undef 3423 // mask values count as coming from any quadword, for better codegen. 3424 SmallVector<unsigned, 4> LoQuad(4); 3425 SmallVector<unsigned, 4> HiQuad(4); 3426 BitVector InputQuads(4); 3427 for (unsigned i = 0; i < 8; ++i) { 3428 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3429 int EltIdx = SVOp->getMaskElt(i); 3430 MaskVals.push_back(EltIdx); 3431 if (EltIdx < 0) { 3432 ++Quad[0]; 3433 ++Quad[1]; 3434 ++Quad[2]; 3435 ++Quad[3]; 3436 continue; 3437 } 3438 ++Quad[EltIdx / 4]; 3439 InputQuads.set(EltIdx / 4); 3440 } 3441 3442 int BestLoQuad = -1; 3443 unsigned MaxQuad = 1; 3444 for (unsigned i = 0; i < 4; ++i) { 3445 if (LoQuad[i] > MaxQuad) { 3446 BestLoQuad = i; 3447 MaxQuad = LoQuad[i]; 3448 } 3449 } 3450 3451 int BestHiQuad = -1; 3452 MaxQuad = 1; 3453 for (unsigned i = 0; i < 4; ++i) { 3454 if (HiQuad[i] > MaxQuad) { 3455 BestHiQuad = i; 3456 MaxQuad = HiQuad[i]; 3457 } 3458 } 3459 3460 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3461 // of the two input vectors, shuffle them into one input vector so only a 3462 // single pshufb instruction is necessary. If There are more than 2 input 3463 // quads, disable the next transformation since it does not help SSSE3. 3464 bool V1Used = InputQuads[0] || InputQuads[1]; 3465 bool V2Used = InputQuads[2] || InputQuads[3]; 3466 if (TLI.getSubtarget()->hasSSSE3()) { 3467 if (InputQuads.count() == 2 && V1Used && V2Used) { 3468 BestLoQuad = InputQuads.find_first(); 3469 BestHiQuad = InputQuads.find_next(BestLoQuad); 3470 } 3471 if (InputQuads.count() > 2) { 3472 BestLoQuad = -1; 3473 BestHiQuad = -1; 3474 } 3475 } 3476 3477 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3478 // the shuffle mask. If a quad is scored as -1, that means that it contains 3479 // words from all 4 input quadwords. 3480 SDValue NewV; 3481 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3482 SmallVector<int, 8> MaskV; 3483 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 3484 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 3485 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 3486 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3487 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 3488 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3489 3490 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3491 // source words for the shuffle, to aid later transformations. 3492 bool AllWordsInNewV = true; 3493 bool InOrder[2] = { true, true }; 3494 for (unsigned i = 0; i != 8; ++i) { 3495 int idx = MaskVals[i]; 3496 if (idx != (int)i) 3497 InOrder[i/4] = false; 3498 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3499 continue; 3500 AllWordsInNewV = false; 3501 break; 3502 } 3503 3504 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 3505 if (AllWordsInNewV) { 3506 for (int i = 0; i != 8; ++i) { 3507 int idx = MaskVals[i]; 3508 if (idx < 0) 3509 continue; 3510 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 3511 if ((idx != i) && idx < 4) 3512 pshufhw = false; 3513 if ((idx != i) && idx > 3) 3514 pshuflw = false; 3515 } 3516 V1 = NewV; 3517 V2Used = false; 3518 BestLoQuad = 0; 3519 BestHiQuad = 1; 3520 } 3521 3522 // If we've eliminated the use of V2, and the new mask is a pshuflw or 3523 // pshufhw, that's as cheap as it gets. Return the new shuffle. 3524 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 3525 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 3526 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 3527 } 3528 } 3529 3530 // If we have SSSE3, and all words of the result are from 1 input vector, 3531 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 3532 // is present, fall back to case 4. 3533 if (TLI.getSubtarget()->hasSSSE3()) { 3534 SmallVector<SDValue,16> pshufbMask; 3535 3536 // If we have elements from both input vectors, set the high bit of the 3537 // shuffle mask element to zero out elements that come from V2 in the V1 3538 // mask, and elements that come from V1 in the V2 mask, so that the two 3539 // results can be OR'd together. 3540 bool TwoInputs = V1Used && V2Used; 3541 for (unsigned i = 0; i != 8; ++i) { 3542 int EltIdx = MaskVals[i] * 2; 3543 if (TwoInputs && (EltIdx >= 16)) { 3544 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3545 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3546 continue; 3547 } 3548 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3549 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 3550 } 3551 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 3552 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3553 DAG.getNode(ISD::BUILD_VECTOR, dl, 3554 MVT::v16i8, &pshufbMask[0], 16)); 3555 if (!TwoInputs) 3556 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3557 3558 // Calculate the shuffle mask for the second input, shuffle it, and 3559 // OR it with the first shuffled input. 3560 pshufbMask.clear(); 3561 for (unsigned i = 0; i != 8; ++i) { 3562 int EltIdx = MaskVals[i] * 2; 3563 if (EltIdx < 16) { 3564 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3565 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3566 continue; 3567 } 3568 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3569 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 3570 } 3571 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 3572 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3573 DAG.getNode(ISD::BUILD_VECTOR, dl, 3574 MVT::v16i8, &pshufbMask[0], 16)); 3575 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3576 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3577 } 3578 3579 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 3580 // and update MaskVals with new element order. 3581 BitVector InOrder(8); 3582 if (BestLoQuad >= 0) { 3583 SmallVector<int, 8> MaskV; 3584 for (int i = 0; i != 4; ++i) { 3585 int idx = MaskVals[i]; 3586 if (idx < 0) { 3587 MaskV.push_back(-1); 3588 InOrder.set(i); 3589 } else if ((idx / 4) == BestLoQuad) { 3590 MaskV.push_back(idx & 3); 3591 InOrder.set(i); 3592 } else { 3593 MaskV.push_back(-1); 3594 } 3595 } 3596 for (unsigned i = 4; i != 8; ++i) 3597 MaskV.push_back(i); 3598 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 3599 &MaskV[0]); 3600 } 3601 3602 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 3603 // and update MaskVals with the new element order. 3604 if (BestHiQuad >= 0) { 3605 SmallVector<int, 8> MaskV; 3606 for (unsigned i = 0; i != 4; ++i) 3607 MaskV.push_back(i); 3608 for (unsigned i = 4; i != 8; ++i) { 3609 int idx = MaskVals[i]; 3610 if (idx < 0) { 3611 MaskV.push_back(-1); 3612 InOrder.set(i); 3613 } else if ((idx / 4) == BestHiQuad) { 3614 MaskV.push_back((idx & 3) + 4); 3615 InOrder.set(i); 3616 } else { 3617 MaskV.push_back(-1); 3618 } 3619 } 3620 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 3621 &MaskV[0]); 3622 } 3623 3624 // In case BestHi & BestLo were both -1, which means each quadword has a word 3625 // from each of the four input quadwords, calculate the InOrder bitvector now 3626 // before falling through to the insert/extract cleanup. 3627 if (BestLoQuad == -1 && BestHiQuad == -1) { 3628 NewV = V1; 3629 for (int i = 0; i != 8; ++i) 3630 if (MaskVals[i] < 0 || MaskVals[i] == i) 3631 InOrder.set(i); 3632 } 3633 3634 // The other elements are put in the right place using pextrw and pinsrw. 3635 for (unsigned i = 0; i != 8; ++i) { 3636 if (InOrder[i]) 3637 continue; 3638 int EltIdx = MaskVals[i]; 3639 if (EltIdx < 0) 3640 continue; 3641 SDValue ExtOp = (EltIdx < 8) 3642 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 3643 DAG.getIntPtrConstant(EltIdx)) 3644 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 3645 DAG.getIntPtrConstant(EltIdx - 8)); 3646 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 3647 DAG.getIntPtrConstant(i)); 3648 } 3649 return NewV; 3650} 3651 3652// v16i8 shuffles - Prefer shuffles in the following order: 3653// 1. [ssse3] 1 x pshufb 3654// 2. [ssse3] 2 x pshufb + 1 x por 3655// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 3656static 3657SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 3658 SelectionDAG &DAG, X86TargetLowering &TLI) { 3659 SDValue V1 = SVOp->getOperand(0); 3660 SDValue V2 = SVOp->getOperand(1); 3661 DebugLoc dl = SVOp->getDebugLoc(); 3662 SmallVector<int, 16> MaskVals; 3663 SVOp->getMask(MaskVals); 3664 3665 // If we have SSSE3, case 1 is generated when all result bytes come from 3666 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 3667 // present, fall back to case 3. 3668 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 3669 bool V1Only = true; 3670 bool V2Only = true; 3671 for (unsigned i = 0; i < 16; ++i) { 3672 int EltIdx = MaskVals[i]; 3673 if (EltIdx < 0) 3674 continue; 3675 if (EltIdx < 16) 3676 V2Only = false; 3677 else 3678 V1Only = false; 3679 } 3680 3681 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 3682 if (TLI.getSubtarget()->hasSSSE3()) { 3683 SmallVector<SDValue,16> pshufbMask; 3684 3685 // If all result elements are from one input vector, then only translate 3686 // undef mask values to 0x80 (zero out result) in the pshufb mask. 3687 // 3688 // Otherwise, we have elements from both input vectors, and must zero out 3689 // elements that come from V2 in the first mask, and V1 in the second mask 3690 // so that we can OR them together. 3691 bool TwoInputs = !(V1Only || V2Only); 3692 for (unsigned i = 0; i != 16; ++i) { 3693 int EltIdx = MaskVals[i]; 3694 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 3695 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3696 continue; 3697 } 3698 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3699 } 3700 // If all the elements are from V2, assign it to V1 and return after 3701 // building the first pshufb. 3702 if (V2Only) 3703 V1 = V2; 3704 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3705 DAG.getNode(ISD::BUILD_VECTOR, dl, 3706 MVT::v16i8, &pshufbMask[0], 16)); 3707 if (!TwoInputs) 3708 return V1; 3709 3710 // Calculate the shuffle mask for the second input, shuffle it, and 3711 // OR it with the first shuffled input. 3712 pshufbMask.clear(); 3713 for (unsigned i = 0; i != 16; ++i) { 3714 int EltIdx = MaskVals[i]; 3715 if (EltIdx < 16) { 3716 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3717 continue; 3718 } 3719 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3720 } 3721 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3722 DAG.getNode(ISD::BUILD_VECTOR, dl, 3723 MVT::v16i8, &pshufbMask[0], 16)); 3724 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3725 } 3726 3727 // No SSSE3 - Calculate in place words and then fix all out of place words 3728 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 3729 // the 16 different words that comprise the two doublequadword input vectors. 3730 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3731 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 3732 SDValue NewV = V2Only ? V2 : V1; 3733 for (int i = 0; i != 8; ++i) { 3734 int Elt0 = MaskVals[i*2]; 3735 int Elt1 = MaskVals[i*2+1]; 3736 3737 // This word of the result is all undef, skip it. 3738 if (Elt0 < 0 && Elt1 < 0) 3739 continue; 3740 3741 // This word of the result is already in the correct place, skip it. 3742 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 3743 continue; 3744 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 3745 continue; 3746 3747 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 3748 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 3749 SDValue InsElt; 3750 3751 // If Elt0 and Elt1 are defined, are consecutive, and can be load 3752 // using a single extract together, load it and store it. 3753 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 3754 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3755 DAG.getIntPtrConstant(Elt1 / 2)); 3756 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3757 DAG.getIntPtrConstant(i)); 3758 continue; 3759 } 3760 3761 // If Elt1 is defined, extract it from the appropriate source. If the 3762 // source byte is not also odd, shift the extracted word left 8 bits 3763 // otherwise clear the bottom 8 bits if we need to do an or. 3764 if (Elt1 >= 0) { 3765 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3766 DAG.getIntPtrConstant(Elt1 / 2)); 3767 if ((Elt1 & 1) == 0) 3768 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 3769 DAG.getConstant(8, TLI.getShiftAmountTy())); 3770 else if (Elt0 >= 0) 3771 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 3772 DAG.getConstant(0xFF00, MVT::i16)); 3773 } 3774 // If Elt0 is defined, extract it from the appropriate source. If the 3775 // source byte is not also even, shift the extracted word right 8 bits. If 3776 // Elt1 was also defined, OR the extracted values together before 3777 // inserting them in the result. 3778 if (Elt0 >= 0) { 3779 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 3780 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 3781 if ((Elt0 & 1) != 0) 3782 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 3783 DAG.getConstant(8, TLI.getShiftAmountTy())); 3784 else if (Elt1 >= 0) 3785 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 3786 DAG.getConstant(0x00FF, MVT::i16)); 3787 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 3788 : InsElt0; 3789 } 3790 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3791 DAG.getIntPtrConstant(i)); 3792 } 3793 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 3794} 3795 3796/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3797/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3798/// done when every pair / quad of shuffle mask elements point to elements in 3799/// the right sequence. e.g. 3800/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3801static 3802SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 3803 SelectionDAG &DAG, 3804 TargetLowering &TLI, DebugLoc dl) { 3805 MVT VT = SVOp->getValueType(0); 3806 SDValue V1 = SVOp->getOperand(0); 3807 SDValue V2 = SVOp->getOperand(1); 3808 unsigned NumElems = VT.getVectorNumElements(); 3809 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3810 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3811 MVT MaskEltVT = MaskVT.getVectorElementType(); 3812 MVT NewVT = MaskVT; 3813 switch (VT.getSimpleVT()) { 3814 default: assert(false && "Unexpected!"); 3815 case MVT::v4f32: NewVT = MVT::v2f64; break; 3816 case MVT::v4i32: NewVT = MVT::v2i64; break; 3817 case MVT::v8i16: NewVT = MVT::v4i32; break; 3818 case MVT::v16i8: NewVT = MVT::v4i32; break; 3819 } 3820 3821 if (NewWidth == 2) { 3822 if (VT.isInteger()) 3823 NewVT = MVT::v2i64; 3824 else 3825 NewVT = MVT::v2f64; 3826 } 3827 int Scale = NumElems / NewWidth; 3828 SmallVector<int, 8> MaskVec; 3829 for (unsigned i = 0; i < NumElems; i += Scale) { 3830 int StartIdx = -1; 3831 for (int j = 0; j < Scale; ++j) { 3832 int EltIdx = SVOp->getMaskElt(i+j); 3833 if (EltIdx < 0) 3834 continue; 3835 if (StartIdx == -1) 3836 StartIdx = EltIdx - (EltIdx % Scale); 3837 if (EltIdx != StartIdx + j) 3838 return SDValue(); 3839 } 3840 if (StartIdx == -1) 3841 MaskVec.push_back(-1); 3842 else 3843 MaskVec.push_back(StartIdx / Scale); 3844 } 3845 3846 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 3847 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 3848 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 3849} 3850 3851/// getVZextMovL - Return a zero-extending vector move low node. 3852/// 3853static SDValue getVZextMovL(MVT VT, MVT OpVT, 3854 SDValue SrcOp, SelectionDAG &DAG, 3855 const X86Subtarget *Subtarget, DebugLoc dl) { 3856 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3857 LoadSDNode *LD = NULL; 3858 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 3859 LD = dyn_cast<LoadSDNode>(SrcOp); 3860 if (!LD) { 3861 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3862 // instead. 3863 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3864 if ((EVT != MVT::i64 || Subtarget->is64Bit()) && 3865 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 3866 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 3867 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { 3868 // PR2108 3869 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 3870 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3871 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 3872 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3873 OpVT, 3874 SrcOp.getOperand(0) 3875 .getOperand(0)))); 3876 } 3877 } 3878 } 3879 3880 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3881 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 3882 DAG.getNode(ISD::BIT_CONVERT, dl, 3883 OpVT, SrcOp))); 3884} 3885 3886/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 3887/// shuffles. 3888static SDValue 3889LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3890 SDValue V1 = SVOp->getOperand(0); 3891 SDValue V2 = SVOp->getOperand(1); 3892 DebugLoc dl = SVOp->getDebugLoc(); 3893 MVT VT = SVOp->getValueType(0); 3894 3895 SmallVector<std::pair<int, int>, 8> Locs; 3896 Locs.resize(4); 3897 SmallVector<int, 8> Mask1(4U, -1); 3898 SmallVector<int, 8> PermMask; 3899 SVOp->getMask(PermMask); 3900 3901 unsigned NumHi = 0; 3902 unsigned NumLo = 0; 3903 for (unsigned i = 0; i != 4; ++i) { 3904 int Idx = PermMask[i]; 3905 if (Idx < 0) { 3906 Locs[i] = std::make_pair(-1, -1); 3907 } else { 3908 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 3909 if (Idx < 4) { 3910 Locs[i] = std::make_pair(0, NumLo); 3911 Mask1[NumLo] = Idx; 3912 NumLo++; 3913 } else { 3914 Locs[i] = std::make_pair(1, NumHi); 3915 if (2+NumHi < 4) 3916 Mask1[2+NumHi] = Idx; 3917 NumHi++; 3918 } 3919 } 3920 } 3921 3922 if (NumLo <= 2 && NumHi <= 2) { 3923 // If no more than two elements come from either vector. This can be 3924 // implemented with two shuffles. First shuffle gather the elements. 3925 // The second shuffle, which takes the first shuffle as both of its 3926 // vector operands, put the elements into the right order. 3927 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 3928 3929 SmallVector<int, 8> Mask2(4U, -1); 3930 3931 for (unsigned i = 0; i != 4; ++i) { 3932 if (Locs[i].first == -1) 3933 continue; 3934 else { 3935 unsigned Idx = (i < 2) ? 0 : 4; 3936 Idx += Locs[i].first * 2 + Locs[i].second; 3937 Mask2[i] = Idx; 3938 } 3939 } 3940 3941 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 3942 } else if (NumLo == 3 || NumHi == 3) { 3943 // Otherwise, we must have three elements from one vector, call it X, and 3944 // one element from the other, call it Y. First, use a shufps to build an 3945 // intermediate vector with the one element from Y and the element from X 3946 // that will be in the same half in the final destination (the indexes don't 3947 // matter). Then, use a shufps to build the final vector, taking the half 3948 // containing the element from Y from the intermediate, and the other half 3949 // from X. 3950 if (NumHi == 3) { 3951 // Normalize it so the 3 elements come from V1. 3952 CommuteVectorShuffleMask(PermMask, VT); 3953 std::swap(V1, V2); 3954 } 3955 3956 // Find the element from V2. 3957 unsigned HiIndex; 3958 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 3959 int Val = PermMask[HiIndex]; 3960 if (Val < 0) 3961 continue; 3962 if (Val >= 4) 3963 break; 3964 } 3965 3966 Mask1[0] = PermMask[HiIndex]; 3967 Mask1[1] = -1; 3968 Mask1[2] = PermMask[HiIndex^1]; 3969 Mask1[3] = -1; 3970 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 3971 3972 if (HiIndex >= 2) { 3973 Mask1[0] = PermMask[0]; 3974 Mask1[1] = PermMask[1]; 3975 Mask1[2] = HiIndex & 1 ? 6 : 4; 3976 Mask1[3] = HiIndex & 1 ? 4 : 6; 3977 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 3978 } else { 3979 Mask1[0] = HiIndex & 1 ? 2 : 0; 3980 Mask1[1] = HiIndex & 1 ? 0 : 2; 3981 Mask1[2] = PermMask[2]; 3982 Mask1[3] = PermMask[3]; 3983 if (Mask1[2] >= 0) 3984 Mask1[2] += 4; 3985 if (Mask1[3] >= 0) 3986 Mask1[3] += 4; 3987 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 3988 } 3989 } 3990 3991 // Break it into (shuffle shuffle_hi, shuffle_lo). 3992 Locs.clear(); 3993 SmallVector<int,8> LoMask(4U, -1); 3994 SmallVector<int,8> HiMask(4U, -1); 3995 3996 SmallVector<int,8> *MaskPtr = &LoMask; 3997 unsigned MaskIdx = 0; 3998 unsigned LoIdx = 0; 3999 unsigned HiIdx = 2; 4000 for (unsigned i = 0; i != 4; ++i) { 4001 if (i == 2) { 4002 MaskPtr = &HiMask; 4003 MaskIdx = 1; 4004 LoIdx = 0; 4005 HiIdx = 2; 4006 } 4007 int Idx = PermMask[i]; 4008 if (Idx < 0) { 4009 Locs[i] = std::make_pair(-1, -1); 4010 } else if (Idx < 4) { 4011 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4012 (*MaskPtr)[LoIdx] = Idx; 4013 LoIdx++; 4014 } else { 4015 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4016 (*MaskPtr)[HiIdx] = Idx; 4017 HiIdx++; 4018 } 4019 } 4020 4021 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4022 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4023 SmallVector<int, 8> MaskOps; 4024 for (unsigned i = 0; i != 4; ++i) { 4025 if (Locs[i].first == -1) { 4026 MaskOps.push_back(-1); 4027 } else { 4028 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4029 MaskOps.push_back(Idx); 4030 } 4031 } 4032 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4033} 4034 4035SDValue 4036X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4038 SDValue V1 = Op.getOperand(0); 4039 SDValue V2 = Op.getOperand(1); 4040 MVT VT = Op.getValueType(); 4041 DebugLoc dl = Op.getDebugLoc(); 4042 unsigned NumElems = VT.getVectorNumElements(); 4043 bool isMMX = VT.getSizeInBits() == 64; 4044 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4045 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4046 bool V1IsSplat = false; 4047 bool V2IsSplat = false; 4048 4049 if (isZeroShuffle(SVOp)) 4050 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4051 4052 // Promote splats to v4f32. 4053 if (SVOp->isSplat()) { 4054 if (isMMX || NumElems < 4) 4055 return Op; 4056 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4057 } 4058 4059 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4060 // do it! 4061 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4062 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4063 if (NewOp.getNode()) 4064 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4065 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4066 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4067 // FIXME: Figure out a cleaner way to do this. 4068 // Try to make use of movq to zero out the top part. 4069 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4070 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4071 if (NewOp.getNode()) { 4072 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4073 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4074 DAG, Subtarget, dl); 4075 } 4076 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4077 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4078 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4079 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4080 DAG, Subtarget, dl); 4081 } 4082 } 4083 4084 if (X86::isPSHUFDMask(SVOp)) 4085 return Op; 4086 4087 // Check if this can be converted into a logical shift. 4088 bool isLeft = false; 4089 unsigned ShAmt = 0; 4090 SDValue ShVal; 4091 bool isShift = getSubtarget()->hasSSE2() && 4092 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4093 if (isShift && ShVal.hasOneUse()) { 4094 // If the shifted value has multiple uses, it may be cheaper to use 4095 // v_set0 + movlhps or movhlps, etc. 4096 MVT EVT = VT.getVectorElementType(); 4097 ShAmt *= EVT.getSizeInBits(); 4098 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4099 } 4100 4101 if (X86::isMOVLMask(SVOp)) { 4102 if (V1IsUndef) 4103 return V2; 4104 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4105 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4106 if (!isMMX) 4107 return Op; 4108 } 4109 4110 // FIXME: fold these into legal mask. 4111 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4112 X86::isMOVSLDUPMask(SVOp) || 4113 X86::isMOVHLPSMask(SVOp) || 4114 X86::isMOVHPMask(SVOp) || 4115 X86::isMOVLPMask(SVOp))) 4116 return Op; 4117 4118 if (ShouldXformToMOVHLPS(SVOp) || 4119 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4120 return CommuteVectorShuffle(SVOp, DAG); 4121 4122 if (isShift) { 4123 // No better options. Use a vshl / vsrl. 4124 MVT EVT = VT.getVectorElementType(); 4125 ShAmt *= EVT.getSizeInBits(); 4126 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4127 } 4128 4129 bool Commuted = false; 4130 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4131 // 1,1,1,1 -> v8i16 though. 4132 V1IsSplat = isSplatVector(V1.getNode()); 4133 V2IsSplat = isSplatVector(V2.getNode()); 4134 4135 // Canonicalize the splat or undef, if present, to be on the RHS. 4136 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4137 Op = CommuteVectorShuffle(SVOp, DAG); 4138 SVOp = cast<ShuffleVectorSDNode>(Op); 4139 V1 = SVOp->getOperand(0); 4140 V2 = SVOp->getOperand(1); 4141 std::swap(V1IsSplat, V2IsSplat); 4142 std::swap(V1IsUndef, V2IsUndef); 4143 Commuted = true; 4144 } 4145 4146 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4147 // Shuffling low element of v1 into undef, just return v1. 4148 if (V2IsUndef) 4149 return V1; 4150 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4151 // the instruction selector will not match, so get a canonical MOVL with 4152 // swapped operands to undo the commute. 4153 return getMOVL(DAG, dl, VT, V2, V1); 4154 } 4155 4156 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4157 X86::isUNPCKH_v_undef_Mask(SVOp) || 4158 X86::isUNPCKLMask(SVOp) || 4159 X86::isUNPCKHMask(SVOp)) 4160 return Op; 4161 4162 if (V2IsSplat) { 4163 // Normalize mask so all entries that point to V2 points to its first 4164 // element then try to match unpck{h|l} again. If match, return a 4165 // new vector_shuffle with the corrected mask. 4166 SDValue NewMask = NormalizeMask(SVOp, DAG); 4167 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4168 if (NSVOp != SVOp) { 4169 if (X86::isUNPCKLMask(NSVOp, true)) { 4170 return NewMask; 4171 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4172 return NewMask; 4173 } 4174 } 4175 } 4176 4177 if (Commuted) { 4178 // Commute is back and try unpck* again. 4179 // FIXME: this seems wrong. 4180 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4181 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4182 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4183 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4184 X86::isUNPCKLMask(NewSVOp) || 4185 X86::isUNPCKHMask(NewSVOp)) 4186 return NewOp; 4187 } 4188 4189 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4190 4191 // Normalize the node to match x86 shuffle ops if needed 4192 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4193 return CommuteVectorShuffle(SVOp, DAG); 4194 4195 // Check for legal shuffle and return? 4196 SmallVector<int, 16> PermMask; 4197 SVOp->getMask(PermMask); 4198 if (isShuffleMaskLegal(PermMask, VT)) 4199 return Op; 4200 4201 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4202 if (VT == MVT::v8i16) { 4203 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4204 if (NewOp.getNode()) 4205 return NewOp; 4206 } 4207 4208 if (VT == MVT::v16i8) { 4209 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4210 if (NewOp.getNode()) 4211 return NewOp; 4212 } 4213 4214 // Handle all 4 wide cases with a number of shuffles except for MMX. 4215 if (NumElems == 4 && !isMMX) 4216 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4217 4218 return SDValue(); 4219} 4220 4221SDValue 4222X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4223 SelectionDAG &DAG) { 4224 MVT VT = Op.getValueType(); 4225 DebugLoc dl = Op.getDebugLoc(); 4226 if (VT.getSizeInBits() == 8) { 4227 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4228 Op.getOperand(0), Op.getOperand(1)); 4229 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4230 DAG.getValueType(VT)); 4231 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4232 } else if (VT.getSizeInBits() == 16) { 4233 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4234 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4235 if (Idx == 0) 4236 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4237 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4238 DAG.getNode(ISD::BIT_CONVERT, dl, 4239 MVT::v4i32, 4240 Op.getOperand(0)), 4241 Op.getOperand(1))); 4242 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4243 Op.getOperand(0), Op.getOperand(1)); 4244 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4245 DAG.getValueType(VT)); 4246 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4247 } else if (VT == MVT::f32) { 4248 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4249 // the result back to FR32 register. It's only worth matching if the 4250 // result has a single use which is a store or a bitcast to i32. And in 4251 // the case of a store, it's not worth it if the index is a constant 0, 4252 // because a MOVSSmr can be used instead, which is smaller and faster. 4253 if (!Op.hasOneUse()) 4254 return SDValue(); 4255 SDNode *User = *Op.getNode()->use_begin(); 4256 if ((User->getOpcode() != ISD::STORE || 4257 (isa<ConstantSDNode>(Op.getOperand(1)) && 4258 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4259 (User->getOpcode() != ISD::BIT_CONVERT || 4260 User->getValueType(0) != MVT::i32)) 4261 return SDValue(); 4262 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4263 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4264 Op.getOperand(0)), 4265 Op.getOperand(1)); 4266 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4267 } else if (VT == MVT::i32) { 4268 // ExtractPS works with constant index. 4269 if (isa<ConstantSDNode>(Op.getOperand(1))) 4270 return Op; 4271 } 4272 return SDValue(); 4273} 4274 4275 4276SDValue 4277X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4278 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4279 return SDValue(); 4280 4281 if (Subtarget->hasSSE41()) { 4282 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4283 if (Res.getNode()) 4284 return Res; 4285 } 4286 4287 MVT VT = Op.getValueType(); 4288 DebugLoc dl = Op.getDebugLoc(); 4289 // TODO: handle v16i8. 4290 if (VT.getSizeInBits() == 16) { 4291 SDValue Vec = Op.getOperand(0); 4292 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4293 if (Idx == 0) 4294 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4295 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4296 DAG.getNode(ISD::BIT_CONVERT, dl, 4297 MVT::v4i32, Vec), 4298 Op.getOperand(1))); 4299 // Transform it so it match pextrw which produces a 32-bit result. 4300 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); 4301 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT, 4302 Op.getOperand(0), Op.getOperand(1)); 4303 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract, 4304 DAG.getValueType(VT)); 4305 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4306 } else if (VT.getSizeInBits() == 32) { 4307 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4308 if (Idx == 0) 4309 return Op; 4310 4311 // SHUFPS the element to the lowest double word, then movss. 4312 int Mask[4] = { Idx, -1, -1, -1 }; 4313 MVT VVT = Op.getOperand(0).getValueType(); 4314 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4315 DAG.getUNDEF(VVT), Mask); 4316 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4317 DAG.getIntPtrConstant(0)); 4318 } else if (VT.getSizeInBits() == 64) { 4319 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4320 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4321 // to match extract_elt for f64. 4322 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4323 if (Idx == 0) 4324 return Op; 4325 4326 // UNPCKHPD the element to the lowest double word, then movsd. 4327 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4328 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4329 int Mask[2] = { 1, -1 }; 4330 MVT VVT = Op.getOperand(0).getValueType(); 4331 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4332 DAG.getUNDEF(VVT), Mask); 4333 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4334 DAG.getIntPtrConstant(0)); 4335 } 4336 4337 return SDValue(); 4338} 4339 4340SDValue 4341X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4342 MVT VT = Op.getValueType(); 4343 MVT EVT = VT.getVectorElementType(); 4344 DebugLoc dl = Op.getDebugLoc(); 4345 4346 SDValue N0 = Op.getOperand(0); 4347 SDValue N1 = Op.getOperand(1); 4348 SDValue N2 = Op.getOperand(2); 4349 4350 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4351 isa<ConstantSDNode>(N2)) { 4352 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4353 : X86ISD::PINSRW; 4354 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4355 // argument. 4356 if (N1.getValueType() != MVT::i32) 4357 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4358 if (N2.getValueType() != MVT::i32) 4359 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4360 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4361 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4362 // Bits [7:6] of the constant are the source select. This will always be 4363 // zero here. The DAG Combiner may combine an extract_elt index into these 4364 // bits. For example (insert (extract, 3), 2) could be matched by putting 4365 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4366 // Bits [5:4] of the constant are the destination select. This is the 4367 // value of the incoming immediate. 4368 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4369 // combine either bitwise AND or insert of float 0.0 to set these bits. 4370 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4371 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4372 } else if (EVT == MVT::i32) { 4373 // InsertPS works with constant index. 4374 if (isa<ConstantSDNode>(N2)) 4375 return Op; 4376 } 4377 return SDValue(); 4378} 4379 4380SDValue 4381X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4382 MVT VT = Op.getValueType(); 4383 MVT EVT = VT.getVectorElementType(); 4384 4385 if (Subtarget->hasSSE41()) 4386 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4387 4388 if (EVT == MVT::i8) 4389 return SDValue(); 4390 4391 DebugLoc dl = Op.getDebugLoc(); 4392 SDValue N0 = Op.getOperand(0); 4393 SDValue N1 = Op.getOperand(1); 4394 SDValue N2 = Op.getOperand(2); 4395 4396 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4397 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4398 // as its second argument. 4399 if (N1.getValueType() != MVT::i32) 4400 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4401 if (N2.getValueType() != MVT::i32) 4402 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4403 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 4404 } 4405 return SDValue(); 4406} 4407 4408SDValue 4409X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4410 DebugLoc dl = Op.getDebugLoc(); 4411 if (Op.getValueType() == MVT::v2f32) 4412 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4413 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4414 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4415 Op.getOperand(0)))); 4416 4417 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4418 MVT VT = MVT::v2i32; 4419 switch (Op.getValueType().getSimpleVT()) { 4420 default: break; 4421 case MVT::v16i8: 4422 case MVT::v8i16: 4423 VT = MVT::v4i32; 4424 break; 4425 } 4426 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4427 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4428} 4429 4430// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4431// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4432// one of the above mentioned nodes. It has to be wrapped because otherwise 4433// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4434// be used to form addressing mode. These wrapped nodes will be selected 4435// into MOV32ri. 4436SDValue 4437X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4438 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4439 4440 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4441 // global base reg. 4442 unsigned char OpFlag = 0; 4443 unsigned WrapperKind = X86ISD::Wrapper; 4444 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 4445 if (Subtarget->isPICStyleStub()) 4446 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4447 else if (Subtarget->isPICStyleGOT()) 4448 OpFlag = X86II::MO_GOTOFF; 4449 else if (Subtarget->isPICStyleRIPRel() && 4450 getTargetMachine().getCodeModel() == CodeModel::Small) 4451 WrapperKind = X86ISD::WrapperRIP; 4452 } 4453 4454 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 4455 CP->getAlignment(), 4456 CP->getOffset(), OpFlag); 4457 DebugLoc DL = CP->getDebugLoc(); 4458 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4459 // With PIC, the address is actually $g + Offset. 4460 if (OpFlag) { 4461 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4462 DAG.getNode(X86ISD::GlobalBaseReg, 4463 DebugLoc::getUnknownLoc(), getPointerTy()), 4464 Result); 4465 } 4466 4467 return Result; 4468} 4469 4470SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4471 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4472 4473 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4474 // global base reg. 4475 unsigned char OpFlag = 0; 4476 unsigned WrapperKind = X86ISD::Wrapper; 4477 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 4478 if (Subtarget->isPICStyleStub()) 4479 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4480 else if (Subtarget->isPICStyleGOT()) 4481 OpFlag = X86II::MO_GOTOFF; 4482 else if (Subtarget->isPICStyleRIPRel()) 4483 WrapperKind = X86ISD::WrapperRIP; 4484 } 4485 4486 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 4487 OpFlag); 4488 DebugLoc DL = JT->getDebugLoc(); 4489 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4490 4491 // With PIC, the address is actually $g + Offset. 4492 if (OpFlag) { 4493 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4494 DAG.getNode(X86ISD::GlobalBaseReg, 4495 DebugLoc::getUnknownLoc(), getPointerTy()), 4496 Result); 4497 } 4498 4499 return Result; 4500} 4501 4502SDValue 4503X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4504 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4505 4506 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4507 // global base reg. 4508 unsigned char OpFlag = 0; 4509 unsigned WrapperKind = X86ISD::Wrapper; 4510 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 4511 if (Subtarget->isPICStyleStub()) 4512 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4513 else if (Subtarget->isPICStyleGOT()) 4514 OpFlag = X86II::MO_GOTOFF; 4515 else if (Subtarget->isPICStyleRIPRel()) 4516 WrapperKind = X86ISD::WrapperRIP; 4517 } 4518 4519 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 4520 4521 DebugLoc DL = Op.getDebugLoc(); 4522 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4523 4524 4525 // With PIC, the address is actually $g + Offset. 4526 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4527 !Subtarget->isPICStyleRIPRel()) { 4528 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4529 DAG.getNode(X86ISD::GlobalBaseReg, 4530 DebugLoc::getUnknownLoc(), 4531 getPointerTy()), 4532 Result); 4533 } 4534 4535 return Result; 4536} 4537 4538SDValue 4539X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 4540 int64_t Offset, 4541 SelectionDAG &DAG) const { 4542 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 4543 bool ExtraLoadRequired = 4544 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false); 4545 4546 // Create the TargetGlobalAddress node, folding in the constant 4547 // offset if it is legal. 4548 SDValue Result; 4549 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) { 4550 // A direct static reference to a global. 4551 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 4552 Offset = 0; 4553 } else { 4554 unsigned char OpFlags = 0; 4555 4556 if (GV->hasDLLImportLinkage()) 4557 OpFlags = X86II::MO_DLLIMPORT; 4558 else if (Subtarget->isPICStyleRIPRel() && 4559 getTargetMachine().getRelocationModel() != Reloc::Static) { 4560 if (ExtraLoadRequired) 4561 OpFlags = X86II::MO_GOTPCREL; 4562 } else if (Subtarget->isPICStyleGOT() && 4563 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 4564 if (ExtraLoadRequired) 4565 OpFlags = X86II::MO_GOT; 4566 else 4567 OpFlags = X86II::MO_GOTOFF; 4568 } 4569 4570 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 4571 } 4572 4573 if (Subtarget->isPICStyleRIPRel() && 4574 getTargetMachine().getCodeModel() == CodeModel::Small) 4575 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 4576 else 4577 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4578 4579 // With PIC, the address is actually $g + Offset. 4580 if (IsPic && !Subtarget->isPICStyleRIPRel()) { 4581 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4582 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 4583 Result); 4584 } 4585 4586 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 4587 // load the value at address GV, not the value of GV itself. This means that 4588 // the GlobalAddress must be in the base or index register of the address, not 4589 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 4590 // The same applies for external symbols during PIC codegen 4591 if (ExtraLoadRequired) 4592 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 4593 PseudoSourceValue::getGOT(), 0); 4594 4595 // If there was a non-zero offset that we didn't fold, create an explicit 4596 // addition for it. 4597 if (Offset != 0) 4598 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 4599 DAG.getConstant(Offset, getPointerTy())); 4600 4601 return Result; 4602} 4603 4604SDValue 4605X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4606 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4607 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 4608 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 4609} 4610 4611static SDValue 4612GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 4613 SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg, 4614 unsigned char OperandFlags) { 4615 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4616 DebugLoc dl = GA->getDebugLoc(); 4617 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4618 GA->getValueType(0), 4619 GA->getOffset(), 4620 OperandFlags); 4621 if (InFlag) { 4622 SDValue Ops[] = { Chain, TGA, *InFlag }; 4623 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 4624 } else { 4625 SDValue Ops[] = { Chain, TGA }; 4626 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 4627 } 4628 SDValue Flag = Chain.getValue(1); 4629 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 4630} 4631 4632// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4633static SDValue 4634LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4635 const MVT PtrVT) { 4636 SDValue InFlag; 4637 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 4638 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 4639 DAG.getNode(X86ISD::GlobalBaseReg, 4640 DebugLoc::getUnknownLoc(), 4641 PtrVT), InFlag); 4642 InFlag = Chain.getValue(1); 4643 4644 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 4645} 4646 4647// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4648static SDValue 4649LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4650 const MVT PtrVT) { 4651 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 4652 X86::RAX, X86II::MO_TLSGD); 4653} 4654 4655// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4656// "local exec" model. 4657static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4658 const MVT PtrVT, TLSModel::Model model, 4659 bool is64Bit) { 4660 DebugLoc dl = GA->getDebugLoc(); 4661 // Get the Thread Pointer 4662 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 4663 DebugLoc::getUnknownLoc(), PtrVT, 4664 DAG.getRegister(is64Bit? X86::FS : X86::GS, 4665 MVT::i32)); 4666 4667 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 4668 NULL, 0); 4669 4670 unsigned char OperandFlags = 0; 4671 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 4672 // initialexec. 4673 unsigned WrapperKind = X86ISD::Wrapper; 4674 if (model == TLSModel::LocalExec) { 4675 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 4676 } else if (is64Bit) { 4677 assert(model == TLSModel::InitialExec); 4678 OperandFlags = X86II::MO_GOTTPOFF; 4679 WrapperKind = X86ISD::WrapperRIP; 4680 } else { 4681 assert(model == TLSModel::InitialExec); 4682 OperandFlags = X86II::MO_INDNTPOFF; 4683 } 4684 4685 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4686 // exec) 4687 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 4688 GA->getOffset(), OperandFlags); 4689 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 4690 4691 if (model == TLSModel::InitialExec) 4692 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 4693 PseudoSourceValue::getGOT(), 0); 4694 4695 // The address of the thread local variable is the add of the thread 4696 // pointer with the offset of the variable. 4697 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 4698} 4699 4700SDValue 4701X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4702 // TODO: implement the "local dynamic" model 4703 // TODO: implement the "initial exec"model for pic executables 4704 assert(Subtarget->isTargetELF() && 4705 "TLS not implemented for non-ELF targets"); 4706 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4707 const GlobalValue *GV = GA->getGlobal(); 4708 4709 // If GV is an alias then use the aliasee for determining 4710 // thread-localness. 4711 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 4712 GV = GA->resolveAliasedGlobal(false); 4713 4714 TLSModel::Model model = getTLSModel(GV, 4715 getTargetMachine().getRelocationModel()); 4716 4717 switch (model) { 4718 case TLSModel::GeneralDynamic: 4719 case TLSModel::LocalDynamic: // not implemented 4720 if (Subtarget->is64Bit()) 4721 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4722 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4723 4724 case TLSModel::InitialExec: 4725 case TLSModel::LocalExec: 4726 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 4727 Subtarget->is64Bit()); 4728 } 4729 4730 assert(0 && "Unreachable"); 4731 return SDValue(); 4732} 4733 4734 4735/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4736/// take a 2 x i32 value to shift plus a shift amount. 4737SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4738 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4739 MVT VT = Op.getValueType(); 4740 unsigned VTBits = VT.getSizeInBits(); 4741 DebugLoc dl = Op.getDebugLoc(); 4742 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4743 SDValue ShOpLo = Op.getOperand(0); 4744 SDValue ShOpHi = Op.getOperand(1); 4745 SDValue ShAmt = Op.getOperand(2); 4746 SDValue Tmp1 = isSRA ? 4747 DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 4748 DAG.getConstant(VTBits - 1, MVT::i8)) : 4749 DAG.getConstant(0, VT); 4750 4751 SDValue Tmp2, Tmp3; 4752 if (Op.getOpcode() == ISD::SHL_PARTS) { 4753 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 4754 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 4755 } else { 4756 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 4757 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 4758 } 4759 4760 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 4761 DAG.getConstant(VTBits, MVT::i8)); 4762 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, 4763 AndNode, DAG.getConstant(0, MVT::i8)); 4764 4765 SDValue Hi, Lo; 4766 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4767 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4768 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4769 4770 if (Op.getOpcode() == ISD::SHL_PARTS) { 4771 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4772 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4773 } else { 4774 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4775 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4776 } 4777 4778 SDValue Ops[2] = { Lo, Hi }; 4779 return DAG.getMergeValues(Ops, 2, dl); 4780} 4781 4782SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4783 MVT SrcVT = Op.getOperand(0).getValueType(); 4784 4785 if (SrcVT.isVector()) { 4786 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 4787 return Op; 4788 } 4789 return SDValue(); 4790 } 4791 4792 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4793 "Unknown SINT_TO_FP to lower!"); 4794 4795 // These are really Legal; return the operand so the caller accepts it as 4796 // Legal. 4797 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4798 return Op; 4799 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 4800 Subtarget->is64Bit()) { 4801 return Op; 4802 } 4803 4804 DebugLoc dl = Op.getDebugLoc(); 4805 unsigned Size = SrcVT.getSizeInBits()/8; 4806 MachineFunction &MF = DAG.getMachineFunction(); 4807 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4808 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4809 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 4810 StackSlot, 4811 PseudoSourceValue::getFixedStack(SSFI), 0); 4812 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 4813} 4814 4815SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, 4816 SDValue StackSlot, 4817 SelectionDAG &DAG) { 4818 // Build the FILD 4819 DebugLoc dl = Op.getDebugLoc(); 4820 SDVTList Tys; 4821 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4822 if (useSSE) 4823 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4824 else 4825 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4826 SmallVector<SDValue, 8> Ops; 4827 Ops.push_back(Chain); 4828 Ops.push_back(StackSlot); 4829 Ops.push_back(DAG.getValueType(SrcVT)); 4830 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 4831 Tys, &Ops[0], Ops.size()); 4832 4833 if (useSSE) { 4834 Chain = Result.getValue(1); 4835 SDValue InFlag = Result.getValue(2); 4836 4837 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4838 // shouldn't be necessary except that RFP cannot be live across 4839 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4840 MachineFunction &MF = DAG.getMachineFunction(); 4841 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4842 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4843 Tys = DAG.getVTList(MVT::Other); 4844 SmallVector<SDValue, 8> Ops; 4845 Ops.push_back(Chain); 4846 Ops.push_back(Result); 4847 Ops.push_back(StackSlot); 4848 Ops.push_back(DAG.getValueType(Op.getValueType())); 4849 Ops.push_back(InFlag); 4850 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size()); 4851 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 4852 PseudoSourceValue::getFixedStack(SSFI), 0); 4853 } 4854 4855 return Result; 4856} 4857 4858// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 4859SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 4860 // This algorithm is not obvious. Here it is in C code, more or less: 4861 /* 4862 double uint64_to_double( uint32_t hi, uint32_t lo ) { 4863 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 4864 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 4865 4866 // Copy ints to xmm registers. 4867 __m128i xh = _mm_cvtsi32_si128( hi ); 4868 __m128i xl = _mm_cvtsi32_si128( lo ); 4869 4870 // Combine into low half of a single xmm register. 4871 __m128i x = _mm_unpacklo_epi32( xh, xl ); 4872 __m128d d; 4873 double sd; 4874 4875 // Merge in appropriate exponents to give the integer bits the right 4876 // magnitude. 4877 x = _mm_unpacklo_epi32( x, exp ); 4878 4879 // Subtract away the biases to deal with the IEEE-754 double precision 4880 // implicit 1. 4881 d = _mm_sub_pd( (__m128d) x, bias ); 4882 4883 // All conversions up to here are exact. The correctly rounded result is 4884 // calculated using the current rounding mode using the following 4885 // horizontal add. 4886 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 4887 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 4888 // store doesn't really need to be here (except 4889 // maybe to zero the other double) 4890 return sd; 4891 } 4892 */ 4893 4894 DebugLoc dl = Op.getDebugLoc(); 4895 4896 // Build some magic constants. 4897 std::vector<Constant*> CV0; 4898 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000))); 4899 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000))); 4900 CV0.push_back(ConstantInt::get(APInt(32, 0))); 4901 CV0.push_back(ConstantInt::get(APInt(32, 0))); 4902 Constant *C0 = ConstantVector::get(CV0); 4903 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 4904 4905 std::vector<Constant*> CV1; 4906 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL)))); 4907 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL)))); 4908 Constant *C1 = ConstantVector::get(CV1); 4909 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 4910 4911 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4912 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4913 Op.getOperand(0), 4914 DAG.getIntPtrConstant(1))); 4915 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4916 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4917 Op.getOperand(0), 4918 DAG.getIntPtrConstant(0))); 4919 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 4920 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 4921 PseudoSourceValue::getConstantPool(), 0, 4922 false, 16); 4923 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 4924 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 4925 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 4926 PseudoSourceValue::getConstantPool(), 0, 4927 false, 16); 4928 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 4929 4930 // Add the halves; easiest way is to swap them into another reg first. 4931 int ShufMask[2] = { 1, -1 }; 4932 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 4933 DAG.getUNDEF(MVT::v2f64), ShufMask); 4934 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 4935 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 4936 DAG.getIntPtrConstant(0)); 4937} 4938 4939// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 4940SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 4941 DebugLoc dl = Op.getDebugLoc(); 4942 // FP constant to bias correct the final result. 4943 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 4944 MVT::f64); 4945 4946 // Load the 32-bit value into an XMM register. 4947 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4948 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4949 Op.getOperand(0), 4950 DAG.getIntPtrConstant(0))); 4951 4952 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 4953 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 4954 DAG.getIntPtrConstant(0)); 4955 4956 // Or the load with the bias. 4957 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 4958 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 4959 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4960 MVT::v2f64, Load)), 4961 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 4962 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4963 MVT::v2f64, Bias))); 4964 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 4965 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 4966 DAG.getIntPtrConstant(0)); 4967 4968 // Subtract the bias. 4969 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 4970 4971 // Handle final rounding. 4972 MVT DestVT = Op.getValueType(); 4973 4974 if (DestVT.bitsLT(MVT::f64)) { 4975 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 4976 DAG.getIntPtrConstant(0)); 4977 } else if (DestVT.bitsGT(MVT::f64)) { 4978 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 4979 } 4980 4981 // Handle final rounding. 4982 return Sub; 4983} 4984 4985SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4986 SDValue N0 = Op.getOperand(0); 4987 DebugLoc dl = Op.getDebugLoc(); 4988 4989 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 4990 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 4991 // the optimization here. 4992 if (DAG.SignBitIsZero(N0)) 4993 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 4994 4995 MVT SrcVT = N0.getValueType(); 4996 if (SrcVT == MVT::i64) { 4997 // We only handle SSE2 f64 target here; caller can expand the rest. 4998 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 4999 return SDValue(); 5000 5001 return LowerUINT_TO_FP_i64(Op, DAG); 5002 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5003 return LowerUINT_TO_FP_i32(Op, DAG); 5004 } 5005 5006 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5007 5008 // Make a 64-bit buffer, and use it to build an FILD. 5009 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5010 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5011 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5012 getPointerTy(), StackSlot, WordOff); 5013 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5014 StackSlot, NULL, 0); 5015 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5016 OffsetSlot, NULL, 0); 5017 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5018} 5019 5020std::pair<SDValue,SDValue> X86TargetLowering:: 5021FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5022 DebugLoc dl = Op.getDebugLoc(); 5023 5024 MVT DstTy = Op.getValueType(); 5025 5026 if (!IsSigned) { 5027 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5028 DstTy = MVT::i64; 5029 } 5030 5031 assert(DstTy.getSimpleVT() <= MVT::i64 && 5032 DstTy.getSimpleVT() >= MVT::i16 && 5033 "Unknown FP_TO_SINT to lower!"); 5034 5035 // These are really Legal. 5036 if (DstTy == MVT::i32 && 5037 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5038 return std::make_pair(SDValue(), SDValue()); 5039 if (Subtarget->is64Bit() && 5040 DstTy == MVT::i64 && 5041 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5042 return std::make_pair(SDValue(), SDValue()); 5043 5044 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5045 // stack slot. 5046 MachineFunction &MF = DAG.getMachineFunction(); 5047 unsigned MemSize = DstTy.getSizeInBits()/8; 5048 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5049 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5050 5051 unsigned Opc; 5052 switch (DstTy.getSimpleVT()) { 5053 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 5054 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5055 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5056 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5057 } 5058 5059 SDValue Chain = DAG.getEntryNode(); 5060 SDValue Value = Op.getOperand(0); 5061 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5062 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5063 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5064 PseudoSourceValue::getFixedStack(SSFI), 0); 5065 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5066 SDValue Ops[] = { 5067 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5068 }; 5069 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5070 Chain = Value.getValue(1); 5071 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5072 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5073 } 5074 5075 // Build the FP_TO_INT*_IN_MEM 5076 SDValue Ops[] = { Chain, Value, StackSlot }; 5077 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5078 5079 return std::make_pair(FIST, StackSlot); 5080} 5081 5082SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5083 if (Op.getValueType().isVector()) { 5084 if (Op.getValueType() == MVT::v2i32 && 5085 Op.getOperand(0).getValueType() == MVT::v2f64) { 5086 return Op; 5087 } 5088 return SDValue(); 5089 } 5090 5091 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5092 SDValue FIST = Vals.first, StackSlot = Vals.second; 5093 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5094 if (FIST.getNode() == 0) return Op; 5095 5096 // Load the result. 5097 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5098 FIST, StackSlot, NULL, 0); 5099} 5100 5101SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5102 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5103 SDValue FIST = Vals.first, StackSlot = Vals.second; 5104 assert(FIST.getNode() && "Unexpected failure"); 5105 5106 // Load the result. 5107 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5108 FIST, StackSlot, NULL, 0); 5109} 5110 5111SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5112 DebugLoc dl = Op.getDebugLoc(); 5113 MVT VT = Op.getValueType(); 5114 MVT EltVT = VT; 5115 if (VT.isVector()) 5116 EltVT = VT.getVectorElementType(); 5117 std::vector<Constant*> CV; 5118 if (EltVT == MVT::f64) { 5119 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))); 5120 CV.push_back(C); 5121 CV.push_back(C); 5122 } else { 5123 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))); 5124 CV.push_back(C); 5125 CV.push_back(C); 5126 CV.push_back(C); 5127 CV.push_back(C); 5128 } 5129 Constant *C = ConstantVector::get(CV); 5130 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5131 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5132 PseudoSourceValue::getConstantPool(), 0, 5133 false, 16); 5134 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5135} 5136 5137SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5138 DebugLoc dl = Op.getDebugLoc(); 5139 MVT VT = Op.getValueType(); 5140 MVT EltVT = VT; 5141 unsigned EltNum = 1; 5142 if (VT.isVector()) { 5143 EltVT = VT.getVectorElementType(); 5144 EltNum = VT.getVectorNumElements(); 5145 } 5146 std::vector<Constant*> CV; 5147 if (EltVT == MVT::f64) { 5148 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63))); 5149 CV.push_back(C); 5150 CV.push_back(C); 5151 } else { 5152 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31))); 5153 CV.push_back(C); 5154 CV.push_back(C); 5155 CV.push_back(C); 5156 CV.push_back(C); 5157 } 5158 Constant *C = ConstantVector::get(CV); 5159 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5160 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5161 PseudoSourceValue::getConstantPool(), 0, 5162 false, 16); 5163 if (VT.isVector()) { 5164 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5165 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5166 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5167 Op.getOperand(0)), 5168 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5169 } else { 5170 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5171 } 5172} 5173 5174SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5175 SDValue Op0 = Op.getOperand(0); 5176 SDValue Op1 = Op.getOperand(1); 5177 DebugLoc dl = Op.getDebugLoc(); 5178 MVT VT = Op.getValueType(); 5179 MVT SrcVT = Op1.getValueType(); 5180 5181 // If second operand is smaller, extend it first. 5182 if (SrcVT.bitsLT(VT)) { 5183 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5184 SrcVT = VT; 5185 } 5186 // And if it is bigger, shrink it first. 5187 if (SrcVT.bitsGT(VT)) { 5188 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5189 SrcVT = VT; 5190 } 5191 5192 // At this point the operands and the result should have the same 5193 // type, and that won't be f80 since that is not custom lowered. 5194 5195 // First get the sign bit of second operand. 5196 std::vector<Constant*> CV; 5197 if (SrcVT == MVT::f64) { 5198 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63)))); 5199 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5200 } else { 5201 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31)))); 5202 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5203 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5204 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5205 } 5206 Constant *C = ConstantVector::get(CV); 5207 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5208 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5209 PseudoSourceValue::getConstantPool(), 0, 5210 false, 16); 5211 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5212 5213 // Shift sign bit right or left if the two operands have different types. 5214 if (SrcVT.bitsGT(VT)) { 5215 // Op0 is MVT::f32, Op1 is MVT::f64. 5216 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5217 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5218 DAG.getConstant(32, MVT::i32)); 5219 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5220 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5221 DAG.getIntPtrConstant(0)); 5222 } 5223 5224 // Clear first operand sign bit. 5225 CV.clear(); 5226 if (VT == MVT::f64) { 5227 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))))); 5228 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0)))); 5229 } else { 5230 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31))))); 5231 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5232 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5233 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0)))); 5234 } 5235 C = ConstantVector::get(CV); 5236 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5237 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5238 PseudoSourceValue::getConstantPool(), 0, 5239 false, 16); 5240 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5241 5242 // Or the value with the sign bit. 5243 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5244} 5245 5246/// Emit nodes that will be selected as "test Op0,Op0", or something 5247/// equivalent. 5248SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5249 SelectionDAG &DAG) { 5250 DebugLoc dl = Op.getDebugLoc(); 5251 5252 // CF and OF aren't always set the way we want. Determine which 5253 // of these we need. 5254 bool NeedCF = false; 5255 bool NeedOF = false; 5256 switch (X86CC) { 5257 case X86::COND_A: case X86::COND_AE: 5258 case X86::COND_B: case X86::COND_BE: 5259 NeedCF = true; 5260 break; 5261 case X86::COND_G: case X86::COND_GE: 5262 case X86::COND_L: case X86::COND_LE: 5263 case X86::COND_O: case X86::COND_NO: 5264 NeedOF = true; 5265 break; 5266 default: break; 5267 } 5268 5269 // See if we can use the EFLAGS value from the operand instead of 5270 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5271 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5272 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5273 unsigned Opcode = 0; 5274 unsigned NumOperands = 0; 5275 switch (Op.getNode()->getOpcode()) { 5276 case ISD::ADD: 5277 // Due to an isel shortcoming, be conservative if this add is likely to 5278 // be selected as part of a load-modify-store instruction. When the root 5279 // node in a match is a store, isel doesn't know how to remap non-chain 5280 // non-flag uses of other nodes in the match, such as the ADD in this 5281 // case. This leads to the ADD being left around and reselected, with 5282 // the result being two adds in the output. 5283 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5284 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5285 if (UI->getOpcode() == ISD::STORE) 5286 goto default_case; 5287 if (ConstantSDNode *C = 5288 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5289 // An add of one will be selected as an INC. 5290 if (C->getAPIntValue() == 1) { 5291 Opcode = X86ISD::INC; 5292 NumOperands = 1; 5293 break; 5294 } 5295 // An add of negative one (subtract of one) will be selected as a DEC. 5296 if (C->getAPIntValue().isAllOnesValue()) { 5297 Opcode = X86ISD::DEC; 5298 NumOperands = 1; 5299 break; 5300 } 5301 } 5302 // Otherwise use a regular EFLAGS-setting add. 5303 Opcode = X86ISD::ADD; 5304 NumOperands = 2; 5305 break; 5306 case ISD::SUB: 5307 // Due to the ISEL shortcoming noted above, be conservative if this sub is 5308 // likely to be selected as part of a load-modify-store instruction. 5309 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5310 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5311 if (UI->getOpcode() == ISD::STORE) 5312 goto default_case; 5313 // Otherwise use a regular EFLAGS-setting sub. 5314 Opcode = X86ISD::SUB; 5315 NumOperands = 2; 5316 break; 5317 case X86ISD::ADD: 5318 case X86ISD::SUB: 5319 case X86ISD::INC: 5320 case X86ISD::DEC: 5321 return SDValue(Op.getNode(), 1); 5322 default: 5323 default_case: 5324 break; 5325 } 5326 if (Opcode != 0) { 5327 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5328 SmallVector<SDValue, 4> Ops; 5329 for (unsigned i = 0; i != NumOperands; ++i) 5330 Ops.push_back(Op.getOperand(i)); 5331 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5332 DAG.ReplaceAllUsesWith(Op, New); 5333 return SDValue(New.getNode(), 1); 5334 } 5335 } 5336 5337 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5338 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5339 DAG.getConstant(0, Op.getValueType())); 5340} 5341 5342/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5343/// equivalent. 5344SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5345 SelectionDAG &DAG) { 5346 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5347 if (C->getAPIntValue() == 0) 5348 return EmitTest(Op0, X86CC, DAG); 5349 5350 DebugLoc dl = Op0.getDebugLoc(); 5351 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5352} 5353 5354SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5355 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5356 SDValue Op0 = Op.getOperand(0); 5357 SDValue Op1 = Op.getOperand(1); 5358 DebugLoc dl = Op.getDebugLoc(); 5359 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5360 5361 // Lower (X & (1 << N)) == 0 to BT(X, N). 5362 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5363 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5364 if (Op0.getOpcode() == ISD::AND && 5365 Op0.hasOneUse() && 5366 Op1.getOpcode() == ISD::Constant && 5367 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5368 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5369 SDValue LHS, RHS; 5370 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5371 if (ConstantSDNode *Op010C = 5372 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5373 if (Op010C->getZExtValue() == 1) { 5374 LHS = Op0.getOperand(0); 5375 RHS = Op0.getOperand(1).getOperand(1); 5376 } 5377 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5378 if (ConstantSDNode *Op000C = 5379 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5380 if (Op000C->getZExtValue() == 1) { 5381 LHS = Op0.getOperand(1); 5382 RHS = Op0.getOperand(0).getOperand(1); 5383 } 5384 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5385 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5386 SDValue AndLHS = Op0.getOperand(0); 5387 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5388 LHS = AndLHS.getOperand(0); 5389 RHS = AndLHS.getOperand(1); 5390 } 5391 } 5392 5393 if (LHS.getNode()) { 5394 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5395 // instruction. Since the shift amount is in-range-or-undefined, we know 5396 // that doing a bittest on the i16 value is ok. We extend to i32 because 5397 // the encoding for the i16 version is larger than the i32 version. 5398 if (LHS.getValueType() == MVT::i8) 5399 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5400 5401 // If the operand types disagree, extend the shift amount to match. Since 5402 // BT ignores high bits (like shifts) we can use anyextend. 5403 if (LHS.getValueType() != RHS.getValueType()) 5404 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5405 5406 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5407 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5408 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5409 DAG.getConstant(Cond, MVT::i8), BT); 5410 } 5411 } 5412 5413 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5414 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5415 5416 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 5417 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5418 DAG.getConstant(X86CC, MVT::i8), Cond); 5419} 5420 5421SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5422 SDValue Cond; 5423 SDValue Op0 = Op.getOperand(0); 5424 SDValue Op1 = Op.getOperand(1); 5425 SDValue CC = Op.getOperand(2); 5426 MVT VT = Op.getValueType(); 5427 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5428 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5429 DebugLoc dl = Op.getDebugLoc(); 5430 5431 if (isFP) { 5432 unsigned SSECC = 8; 5433 MVT VT0 = Op0.getValueType(); 5434 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5435 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5436 bool Swap = false; 5437 5438 switch (SetCCOpcode) { 5439 default: break; 5440 case ISD::SETOEQ: 5441 case ISD::SETEQ: SSECC = 0; break; 5442 case ISD::SETOGT: 5443 case ISD::SETGT: Swap = true; // Fallthrough 5444 case ISD::SETLT: 5445 case ISD::SETOLT: SSECC = 1; break; 5446 case ISD::SETOGE: 5447 case ISD::SETGE: Swap = true; // Fallthrough 5448 case ISD::SETLE: 5449 case ISD::SETOLE: SSECC = 2; break; 5450 case ISD::SETUO: SSECC = 3; break; 5451 case ISD::SETUNE: 5452 case ISD::SETNE: SSECC = 4; break; 5453 case ISD::SETULE: Swap = true; 5454 case ISD::SETUGE: SSECC = 5; break; 5455 case ISD::SETULT: Swap = true; 5456 case ISD::SETUGT: SSECC = 6; break; 5457 case ISD::SETO: SSECC = 7; break; 5458 } 5459 if (Swap) 5460 std::swap(Op0, Op1); 5461 5462 // In the two special cases we can't handle, emit two comparisons. 5463 if (SSECC == 8) { 5464 if (SetCCOpcode == ISD::SETUEQ) { 5465 SDValue UNORD, EQ; 5466 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 5467 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 5468 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 5469 } 5470 else if (SetCCOpcode == ISD::SETONE) { 5471 SDValue ORD, NEQ; 5472 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 5473 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 5474 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 5475 } 5476 assert(0 && "Illegal FP comparison"); 5477 } 5478 // Handle all other FP comparisons here. 5479 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 5480 } 5481 5482 // We are handling one of the integer comparisons here. Since SSE only has 5483 // GT and EQ comparisons for integer, swapping operands and multiple 5484 // operations may be required for some comparisons. 5485 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 5486 bool Swap = false, Invert = false, FlipSigns = false; 5487 5488 switch (VT.getSimpleVT()) { 5489 default: break; 5490 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 5491 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 5492 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 5493 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 5494 } 5495 5496 switch (SetCCOpcode) { 5497 default: break; 5498 case ISD::SETNE: Invert = true; 5499 case ISD::SETEQ: Opc = EQOpc; break; 5500 case ISD::SETLT: Swap = true; 5501 case ISD::SETGT: Opc = GTOpc; break; 5502 case ISD::SETGE: Swap = true; 5503 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 5504 case ISD::SETULT: Swap = true; 5505 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 5506 case ISD::SETUGE: Swap = true; 5507 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 5508 } 5509 if (Swap) 5510 std::swap(Op0, Op1); 5511 5512 // Since SSE has no unsigned integer comparisons, we need to flip the sign 5513 // bits of the inputs before performing those operations. 5514 if (FlipSigns) { 5515 MVT EltVT = VT.getVectorElementType(); 5516 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 5517 EltVT); 5518 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 5519 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 5520 SignBits.size()); 5521 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 5522 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 5523 } 5524 5525 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 5526 5527 // If the logical-not of the result is required, perform that now. 5528 if (Invert) 5529 Result = DAG.getNOT(dl, Result, VT); 5530 5531 return Result; 5532} 5533 5534// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 5535static bool isX86LogicalCmp(SDValue Op) { 5536 unsigned Opc = Op.getNode()->getOpcode(); 5537 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 5538 return true; 5539 if (Op.getResNo() == 1 && 5540 (Opc == X86ISD::ADD || 5541 Opc == X86ISD::SUB || 5542 Opc == X86ISD::SMUL || 5543 Opc == X86ISD::UMUL || 5544 Opc == X86ISD::INC || 5545 Opc == X86ISD::DEC)) 5546 return true; 5547 5548 return false; 5549} 5550 5551SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 5552 bool addTest = true; 5553 SDValue Cond = Op.getOperand(0); 5554 DebugLoc dl = Op.getDebugLoc(); 5555 SDValue CC; 5556 5557 if (Cond.getOpcode() == ISD::SETCC) 5558 Cond = LowerSETCC(Cond, DAG); 5559 5560 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5561 // setting operand in place of the X86ISD::SETCC. 5562 if (Cond.getOpcode() == X86ISD::SETCC) { 5563 CC = Cond.getOperand(0); 5564 5565 SDValue Cmp = Cond.getOperand(1); 5566 unsigned Opc = Cmp.getOpcode(); 5567 MVT VT = Op.getValueType(); 5568 5569 bool IllegalFPCMov = false; 5570 if (VT.isFloatingPoint() && !VT.isVector() && 5571 !isScalarFPTypeInSSEReg(VT)) // FPStack? 5572 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 5573 5574 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 5575 Opc == X86ISD::BT) { // FIXME 5576 Cond = Cmp; 5577 addTest = false; 5578 } 5579 } 5580 5581 if (addTest) { 5582 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5583 Cond = EmitTest(Cond, X86::COND_NE, DAG); 5584 } 5585 5586 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 5587 SmallVector<SDValue, 4> Ops; 5588 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 5589 // condition is true. 5590 Ops.push_back(Op.getOperand(2)); 5591 Ops.push_back(Op.getOperand(1)); 5592 Ops.push_back(CC); 5593 Ops.push_back(Cond); 5594 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size()); 5595} 5596 5597// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 5598// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 5599// from the AND / OR. 5600static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 5601 Opc = Op.getOpcode(); 5602 if (Opc != ISD::OR && Opc != ISD::AND) 5603 return false; 5604 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5605 Op.getOperand(0).hasOneUse() && 5606 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 5607 Op.getOperand(1).hasOneUse()); 5608} 5609 5610// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 5611// 1 and that the SETCC node has a single use. 5612static bool isXor1OfSetCC(SDValue Op) { 5613 if (Op.getOpcode() != ISD::XOR) 5614 return false; 5615 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5616 if (N1C && N1C->getAPIntValue() == 1) { 5617 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5618 Op.getOperand(0).hasOneUse(); 5619 } 5620 return false; 5621} 5622 5623SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 5624 bool addTest = true; 5625 SDValue Chain = Op.getOperand(0); 5626 SDValue Cond = Op.getOperand(1); 5627 SDValue Dest = Op.getOperand(2); 5628 DebugLoc dl = Op.getDebugLoc(); 5629 SDValue CC; 5630 5631 if (Cond.getOpcode() == ISD::SETCC) 5632 Cond = LowerSETCC(Cond, DAG); 5633#if 0 5634 // FIXME: LowerXALUO doesn't handle these!! 5635 else if (Cond.getOpcode() == X86ISD::ADD || 5636 Cond.getOpcode() == X86ISD::SUB || 5637 Cond.getOpcode() == X86ISD::SMUL || 5638 Cond.getOpcode() == X86ISD::UMUL) 5639 Cond = LowerXALUO(Cond, DAG); 5640#endif 5641 5642 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5643 // setting operand in place of the X86ISD::SETCC. 5644 if (Cond.getOpcode() == X86ISD::SETCC) { 5645 CC = Cond.getOperand(0); 5646 5647 SDValue Cmp = Cond.getOperand(1); 5648 unsigned Opc = Cmp.getOpcode(); 5649 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 5650 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 5651 Cond = Cmp; 5652 addTest = false; 5653 } else { 5654 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 5655 default: break; 5656 case X86::COND_O: 5657 case X86::COND_B: 5658 // These can only come from an arithmetic instruction with overflow, 5659 // e.g. SADDO, UADDO. 5660 Cond = Cond.getNode()->getOperand(1); 5661 addTest = false; 5662 break; 5663 } 5664 } 5665 } else { 5666 unsigned CondOpc; 5667 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 5668 SDValue Cmp = Cond.getOperand(0).getOperand(1); 5669 if (CondOpc == ISD::OR) { 5670 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 5671 // two branches instead of an explicit OR instruction with a 5672 // separate test. 5673 if (Cmp == Cond.getOperand(1).getOperand(1) && 5674 isX86LogicalCmp(Cmp)) { 5675 CC = Cond.getOperand(0).getOperand(0); 5676 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5677 Chain, Dest, CC, Cmp); 5678 CC = Cond.getOperand(1).getOperand(0); 5679 Cond = Cmp; 5680 addTest = false; 5681 } 5682 } else { // ISD::AND 5683 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 5684 // two branches instead of an explicit AND instruction with a 5685 // separate test. However, we only do this if this block doesn't 5686 // have a fall-through edge, because this requires an explicit 5687 // jmp when the condition is false. 5688 if (Cmp == Cond.getOperand(1).getOperand(1) && 5689 isX86LogicalCmp(Cmp) && 5690 Op.getNode()->hasOneUse()) { 5691 X86::CondCode CCode = 5692 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5693 CCode = X86::GetOppositeBranchCondition(CCode); 5694 CC = DAG.getConstant(CCode, MVT::i8); 5695 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 5696 // Look for an unconditional branch following this conditional branch. 5697 // We need this because we need to reverse the successors in order 5698 // to implement FCMP_OEQ. 5699 if (User.getOpcode() == ISD::BR) { 5700 SDValue FalseBB = User.getOperand(1); 5701 SDValue NewBR = 5702 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 5703 assert(NewBR == User); 5704 Dest = FalseBB; 5705 5706 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5707 Chain, Dest, CC, Cmp); 5708 X86::CondCode CCode = 5709 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 5710 CCode = X86::GetOppositeBranchCondition(CCode); 5711 CC = DAG.getConstant(CCode, MVT::i8); 5712 Cond = Cmp; 5713 addTest = false; 5714 } 5715 } 5716 } 5717 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 5718 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 5719 // It should be transformed during dag combiner except when the condition 5720 // is set by a arithmetics with overflow node. 5721 X86::CondCode CCode = 5722 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5723 CCode = X86::GetOppositeBranchCondition(CCode); 5724 CC = DAG.getConstant(CCode, MVT::i8); 5725 Cond = Cond.getOperand(0).getOperand(1); 5726 addTest = false; 5727 } 5728 } 5729 5730 if (addTest) { 5731 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5732 Cond = EmitTest(Cond, X86::COND_NE, DAG); 5733 } 5734 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5735 Chain, Dest, CC, Cond); 5736} 5737 5738 5739// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 5740// Calls to _alloca is needed to probe the stack when allocating more than 4k 5741// bytes in one go. Touching the stack at 4K increments is necessary to ensure 5742// that the guard pages used by the OS virtual memory manager are allocated in 5743// correct sequence. 5744SDValue 5745X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5746 SelectionDAG &DAG) { 5747 assert(Subtarget->isTargetCygMing() && 5748 "This should be used only on Cygwin/Mingw targets"); 5749 DebugLoc dl = Op.getDebugLoc(); 5750 5751 // Get the inputs. 5752 SDValue Chain = Op.getOperand(0); 5753 SDValue Size = Op.getOperand(1); 5754 // FIXME: Ensure alignment here 5755 5756 SDValue Flag; 5757 5758 MVT IntPtr = getPointerTy(); 5759 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5760 5761 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 5762 5763 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 5764 Flag = Chain.getValue(1); 5765 5766 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5767 SDValue Ops[] = { Chain, 5768 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5769 DAG.getRegister(X86::EAX, IntPtr), 5770 DAG.getRegister(X86StackPtr, SPTy), 5771 Flag }; 5772 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); 5773 Flag = Chain.getValue(1); 5774 5775 Chain = DAG.getCALLSEQ_END(Chain, 5776 DAG.getIntPtrConstant(0, true), 5777 DAG.getIntPtrConstant(0, true), 5778 Flag); 5779 5780 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 5781 5782 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5783 return DAG.getMergeValues(Ops1, 2, dl); 5784} 5785 5786SDValue 5787X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 5788 SDValue Chain, 5789 SDValue Dst, SDValue Src, 5790 SDValue Size, unsigned Align, 5791 const Value *DstSV, 5792 uint64_t DstSVOff) { 5793 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5794 5795 // If not DWORD aligned or size is more than the threshold, call the library. 5796 // The libc version is likely to be faster for these cases. It can use the 5797 // address value and run time information about the CPU. 5798 if ((Align & 3) != 0 || 5799 !ConstantSize || 5800 ConstantSize->getZExtValue() > 5801 getSubtarget()->getMaxInlineSizeThreshold()) { 5802 SDValue InFlag(0, 0); 5803 5804 // Check to see if there is a specialized entry-point for memory zeroing. 5805 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5806 5807 if (const char *bzeroEntry = V && 5808 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5809 MVT IntPtr = getPointerTy(); 5810 const Type *IntPtrTy = TD->getIntPtrType(); 5811 TargetLowering::ArgListTy Args; 5812 TargetLowering::ArgListEntry Entry; 5813 Entry.Node = Dst; 5814 Entry.Ty = IntPtrTy; 5815 Args.push_back(Entry); 5816 Entry.Node = Size; 5817 Args.push_back(Entry); 5818 std::pair<SDValue,SDValue> CallResult = 5819 LowerCallTo(Chain, Type::VoidTy, false, false, false, false, 5820 0, CallingConv::C, false, 5821 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 5822 return CallResult.second; 5823 } 5824 5825 // Otherwise have the target-independent code call memset. 5826 return SDValue(); 5827 } 5828 5829 uint64_t SizeVal = ConstantSize->getZExtValue(); 5830 SDValue InFlag(0, 0); 5831 MVT AVT; 5832 SDValue Count; 5833 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5834 unsigned BytesLeft = 0; 5835 bool TwoRepStos = false; 5836 if (ValC) { 5837 unsigned ValReg; 5838 uint64_t Val = ValC->getZExtValue() & 255; 5839 5840 // If the value is a constant, then we can potentially use larger sets. 5841 switch (Align & 3) { 5842 case 2: // WORD aligned 5843 AVT = MVT::i16; 5844 ValReg = X86::AX; 5845 Val = (Val << 8) | Val; 5846 break; 5847 case 0: // DWORD aligned 5848 AVT = MVT::i32; 5849 ValReg = X86::EAX; 5850 Val = (Val << 8) | Val; 5851 Val = (Val << 16) | Val; 5852 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5853 AVT = MVT::i64; 5854 ValReg = X86::RAX; 5855 Val = (Val << 32) | Val; 5856 } 5857 break; 5858 default: // Byte aligned 5859 AVT = MVT::i8; 5860 ValReg = X86::AL; 5861 Count = DAG.getIntPtrConstant(SizeVal); 5862 break; 5863 } 5864 5865 if (AVT.bitsGT(MVT::i8)) { 5866 unsigned UBytes = AVT.getSizeInBits() / 8; 5867 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5868 BytesLeft = SizeVal % UBytes; 5869 } 5870 5871 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 5872 InFlag); 5873 InFlag = Chain.getValue(1); 5874 } else { 5875 AVT = MVT::i8; 5876 Count = DAG.getIntPtrConstant(SizeVal); 5877 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 5878 InFlag = Chain.getValue(1); 5879 } 5880 5881 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 5882 X86::ECX, 5883 Count, InFlag); 5884 InFlag = Chain.getValue(1); 5885 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 5886 X86::EDI, 5887 Dst, InFlag); 5888 InFlag = Chain.getValue(1); 5889 5890 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5891 SmallVector<SDValue, 8> Ops; 5892 Ops.push_back(Chain); 5893 Ops.push_back(DAG.getValueType(AVT)); 5894 Ops.push_back(InFlag); 5895 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5896 5897 if (TwoRepStos) { 5898 InFlag = Chain.getValue(1); 5899 Count = Size; 5900 MVT CVT = Count.getValueType(); 5901 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 5902 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5903 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 5904 X86::ECX, 5905 Left, InFlag); 5906 InFlag = Chain.getValue(1); 5907 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5908 Ops.clear(); 5909 Ops.push_back(Chain); 5910 Ops.push_back(DAG.getValueType(MVT::i8)); 5911 Ops.push_back(InFlag); 5912 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5913 } else if (BytesLeft) { 5914 // Handle the last 1 - 7 bytes. 5915 unsigned Offset = SizeVal - BytesLeft; 5916 MVT AddrVT = Dst.getValueType(); 5917 MVT SizeVT = Size.getValueType(); 5918 5919 Chain = DAG.getMemset(Chain, dl, 5920 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 5921 DAG.getConstant(Offset, AddrVT)), 5922 Src, 5923 DAG.getConstant(BytesLeft, SizeVT), 5924 Align, DstSV, DstSVOff + Offset); 5925 } 5926 5927 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 5928 return Chain; 5929} 5930 5931SDValue 5932X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 5933 SDValue Chain, SDValue Dst, SDValue Src, 5934 SDValue Size, unsigned Align, 5935 bool AlwaysInline, 5936 const Value *DstSV, uint64_t DstSVOff, 5937 const Value *SrcSV, uint64_t SrcSVOff) { 5938 // This requires the copy size to be a constant, preferrably 5939 // within a subtarget-specific limit. 5940 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5941 if (!ConstantSize) 5942 return SDValue(); 5943 uint64_t SizeVal = ConstantSize->getZExtValue(); 5944 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 5945 return SDValue(); 5946 5947 /// If not DWORD aligned, call the library. 5948 if ((Align & 3) != 0) 5949 return SDValue(); 5950 5951 // DWORD aligned 5952 MVT AVT = MVT::i32; 5953 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 5954 AVT = MVT::i64; 5955 5956 unsigned UBytes = AVT.getSizeInBits() / 8; 5957 unsigned CountVal = SizeVal / UBytes; 5958 SDValue Count = DAG.getIntPtrConstant(CountVal); 5959 unsigned BytesLeft = SizeVal % UBytes; 5960 5961 SDValue InFlag(0, 0); 5962 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 5963 X86::ECX, 5964 Count, InFlag); 5965 InFlag = Chain.getValue(1); 5966 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 5967 X86::EDI, 5968 Dst, InFlag); 5969 InFlag = Chain.getValue(1); 5970 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 5971 X86::ESI, 5972 Src, InFlag); 5973 InFlag = Chain.getValue(1); 5974 5975 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5976 SmallVector<SDValue, 8> Ops; 5977 Ops.push_back(Chain); 5978 Ops.push_back(DAG.getValueType(AVT)); 5979 Ops.push_back(InFlag); 5980 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size()); 5981 5982 SmallVector<SDValue, 4> Results; 5983 Results.push_back(RepMovs); 5984 if (BytesLeft) { 5985 // Handle the last 1 - 7 bytes. 5986 unsigned Offset = SizeVal - BytesLeft; 5987 MVT DstVT = Dst.getValueType(); 5988 MVT SrcVT = Src.getValueType(); 5989 MVT SizeVT = Size.getValueType(); 5990 Results.push_back(DAG.getMemcpy(Chain, dl, 5991 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 5992 DAG.getConstant(Offset, DstVT)), 5993 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 5994 DAG.getConstant(Offset, SrcVT)), 5995 DAG.getConstant(BytesLeft, SizeVT), 5996 Align, AlwaysInline, 5997 DstSV, DstSVOff + Offset, 5998 SrcSV, SrcSVOff + Offset)); 5999 } 6000 6001 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6002 &Results[0], Results.size()); 6003} 6004 6005SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6006 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6007 DebugLoc dl = Op.getDebugLoc(); 6008 6009 if (!Subtarget->is64Bit()) { 6010 // vastart just stores the address of the VarArgsFrameIndex slot into the 6011 // memory location argument. 6012 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6013 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 6014 } 6015 6016 // __va_list_tag: 6017 // gp_offset (0 - 6 * 8) 6018 // fp_offset (48 - 48 + 8 * 16) 6019 // overflow_arg_area (point to parameters coming in memory). 6020 // reg_save_area 6021 SmallVector<SDValue, 8> MemOps; 6022 SDValue FIN = Op.getOperand(1); 6023 // Store gp_offset 6024 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6025 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6026 FIN, SV, 0); 6027 MemOps.push_back(Store); 6028 6029 // Store fp_offset 6030 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6031 FIN, DAG.getIntPtrConstant(4)); 6032 Store = DAG.getStore(Op.getOperand(0), dl, 6033 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6034 FIN, SV, 0); 6035 MemOps.push_back(Store); 6036 6037 // Store ptr to overflow_arg_area 6038 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6039 FIN, DAG.getIntPtrConstant(4)); 6040 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6041 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0); 6042 MemOps.push_back(Store); 6043 6044 // Store ptr to reg_save_area. 6045 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6046 FIN, DAG.getIntPtrConstant(8)); 6047 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6048 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0); 6049 MemOps.push_back(Store); 6050 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6051 &MemOps[0], MemOps.size()); 6052} 6053 6054SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6055 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6056 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6057 SDValue Chain = Op.getOperand(0); 6058 SDValue SrcPtr = Op.getOperand(1); 6059 SDValue SrcSV = Op.getOperand(2); 6060 6061 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6062 return SDValue(); 6063} 6064 6065SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6066 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6067 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6068 SDValue Chain = Op.getOperand(0); 6069 SDValue DstPtr = Op.getOperand(1); 6070 SDValue SrcPtr = Op.getOperand(2); 6071 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6072 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6073 DebugLoc dl = Op.getDebugLoc(); 6074 6075 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6076 DAG.getIntPtrConstant(24), 8, false, 6077 DstSV, 0, SrcSV, 0); 6078} 6079 6080SDValue 6081X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6082 DebugLoc dl = Op.getDebugLoc(); 6083 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6084 switch (IntNo) { 6085 default: return SDValue(); // Don't custom lower most intrinsics. 6086 // Comparison intrinsics. 6087 case Intrinsic::x86_sse_comieq_ss: 6088 case Intrinsic::x86_sse_comilt_ss: 6089 case Intrinsic::x86_sse_comile_ss: 6090 case Intrinsic::x86_sse_comigt_ss: 6091 case Intrinsic::x86_sse_comige_ss: 6092 case Intrinsic::x86_sse_comineq_ss: 6093 case Intrinsic::x86_sse_ucomieq_ss: 6094 case Intrinsic::x86_sse_ucomilt_ss: 6095 case Intrinsic::x86_sse_ucomile_ss: 6096 case Intrinsic::x86_sse_ucomigt_ss: 6097 case Intrinsic::x86_sse_ucomige_ss: 6098 case Intrinsic::x86_sse_ucomineq_ss: 6099 case Intrinsic::x86_sse2_comieq_sd: 6100 case Intrinsic::x86_sse2_comilt_sd: 6101 case Intrinsic::x86_sse2_comile_sd: 6102 case Intrinsic::x86_sse2_comigt_sd: 6103 case Intrinsic::x86_sse2_comige_sd: 6104 case Intrinsic::x86_sse2_comineq_sd: 6105 case Intrinsic::x86_sse2_ucomieq_sd: 6106 case Intrinsic::x86_sse2_ucomilt_sd: 6107 case Intrinsic::x86_sse2_ucomile_sd: 6108 case Intrinsic::x86_sse2_ucomigt_sd: 6109 case Intrinsic::x86_sse2_ucomige_sd: 6110 case Intrinsic::x86_sse2_ucomineq_sd: { 6111 unsigned Opc = 0; 6112 ISD::CondCode CC = ISD::SETCC_INVALID; 6113 switch (IntNo) { 6114 default: break; 6115 case Intrinsic::x86_sse_comieq_ss: 6116 case Intrinsic::x86_sse2_comieq_sd: 6117 Opc = X86ISD::COMI; 6118 CC = ISD::SETEQ; 6119 break; 6120 case Intrinsic::x86_sse_comilt_ss: 6121 case Intrinsic::x86_sse2_comilt_sd: 6122 Opc = X86ISD::COMI; 6123 CC = ISD::SETLT; 6124 break; 6125 case Intrinsic::x86_sse_comile_ss: 6126 case Intrinsic::x86_sse2_comile_sd: 6127 Opc = X86ISD::COMI; 6128 CC = ISD::SETLE; 6129 break; 6130 case Intrinsic::x86_sse_comigt_ss: 6131 case Intrinsic::x86_sse2_comigt_sd: 6132 Opc = X86ISD::COMI; 6133 CC = ISD::SETGT; 6134 break; 6135 case Intrinsic::x86_sse_comige_ss: 6136 case Intrinsic::x86_sse2_comige_sd: 6137 Opc = X86ISD::COMI; 6138 CC = ISD::SETGE; 6139 break; 6140 case Intrinsic::x86_sse_comineq_ss: 6141 case Intrinsic::x86_sse2_comineq_sd: 6142 Opc = X86ISD::COMI; 6143 CC = ISD::SETNE; 6144 break; 6145 case Intrinsic::x86_sse_ucomieq_ss: 6146 case Intrinsic::x86_sse2_ucomieq_sd: 6147 Opc = X86ISD::UCOMI; 6148 CC = ISD::SETEQ; 6149 break; 6150 case Intrinsic::x86_sse_ucomilt_ss: 6151 case Intrinsic::x86_sse2_ucomilt_sd: 6152 Opc = X86ISD::UCOMI; 6153 CC = ISD::SETLT; 6154 break; 6155 case Intrinsic::x86_sse_ucomile_ss: 6156 case Intrinsic::x86_sse2_ucomile_sd: 6157 Opc = X86ISD::UCOMI; 6158 CC = ISD::SETLE; 6159 break; 6160 case Intrinsic::x86_sse_ucomigt_ss: 6161 case Intrinsic::x86_sse2_ucomigt_sd: 6162 Opc = X86ISD::UCOMI; 6163 CC = ISD::SETGT; 6164 break; 6165 case Intrinsic::x86_sse_ucomige_ss: 6166 case Intrinsic::x86_sse2_ucomige_sd: 6167 Opc = X86ISD::UCOMI; 6168 CC = ISD::SETGE; 6169 break; 6170 case Intrinsic::x86_sse_ucomineq_ss: 6171 case Intrinsic::x86_sse2_ucomineq_sd: 6172 Opc = X86ISD::UCOMI; 6173 CC = ISD::SETNE; 6174 break; 6175 } 6176 6177 SDValue LHS = Op.getOperand(1); 6178 SDValue RHS = Op.getOperand(2); 6179 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6180 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6181 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6182 DAG.getConstant(X86CC, MVT::i8), Cond); 6183 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6184 } 6185 6186 // Fix vector shift instructions where the last operand is a non-immediate 6187 // i32 value. 6188 case Intrinsic::x86_sse2_pslli_w: 6189 case Intrinsic::x86_sse2_pslli_d: 6190 case Intrinsic::x86_sse2_pslli_q: 6191 case Intrinsic::x86_sse2_psrli_w: 6192 case Intrinsic::x86_sse2_psrli_d: 6193 case Intrinsic::x86_sse2_psrli_q: 6194 case Intrinsic::x86_sse2_psrai_w: 6195 case Intrinsic::x86_sse2_psrai_d: 6196 case Intrinsic::x86_mmx_pslli_w: 6197 case Intrinsic::x86_mmx_pslli_d: 6198 case Intrinsic::x86_mmx_pslli_q: 6199 case Intrinsic::x86_mmx_psrli_w: 6200 case Intrinsic::x86_mmx_psrli_d: 6201 case Intrinsic::x86_mmx_psrli_q: 6202 case Intrinsic::x86_mmx_psrai_w: 6203 case Intrinsic::x86_mmx_psrai_d: { 6204 SDValue ShAmt = Op.getOperand(2); 6205 if (isa<ConstantSDNode>(ShAmt)) 6206 return SDValue(); 6207 6208 unsigned NewIntNo = 0; 6209 MVT ShAmtVT = MVT::v4i32; 6210 switch (IntNo) { 6211 case Intrinsic::x86_sse2_pslli_w: 6212 NewIntNo = Intrinsic::x86_sse2_psll_w; 6213 break; 6214 case Intrinsic::x86_sse2_pslli_d: 6215 NewIntNo = Intrinsic::x86_sse2_psll_d; 6216 break; 6217 case Intrinsic::x86_sse2_pslli_q: 6218 NewIntNo = Intrinsic::x86_sse2_psll_q; 6219 break; 6220 case Intrinsic::x86_sse2_psrli_w: 6221 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6222 break; 6223 case Intrinsic::x86_sse2_psrli_d: 6224 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6225 break; 6226 case Intrinsic::x86_sse2_psrli_q: 6227 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6228 break; 6229 case Intrinsic::x86_sse2_psrai_w: 6230 NewIntNo = Intrinsic::x86_sse2_psra_w; 6231 break; 6232 case Intrinsic::x86_sse2_psrai_d: 6233 NewIntNo = Intrinsic::x86_sse2_psra_d; 6234 break; 6235 default: { 6236 ShAmtVT = MVT::v2i32; 6237 switch (IntNo) { 6238 case Intrinsic::x86_mmx_pslli_w: 6239 NewIntNo = Intrinsic::x86_mmx_psll_w; 6240 break; 6241 case Intrinsic::x86_mmx_pslli_d: 6242 NewIntNo = Intrinsic::x86_mmx_psll_d; 6243 break; 6244 case Intrinsic::x86_mmx_pslli_q: 6245 NewIntNo = Intrinsic::x86_mmx_psll_q; 6246 break; 6247 case Intrinsic::x86_mmx_psrli_w: 6248 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6249 break; 6250 case Intrinsic::x86_mmx_psrli_d: 6251 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6252 break; 6253 case Intrinsic::x86_mmx_psrli_q: 6254 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6255 break; 6256 case Intrinsic::x86_mmx_psrai_w: 6257 NewIntNo = Intrinsic::x86_mmx_psra_w; 6258 break; 6259 case Intrinsic::x86_mmx_psrai_d: 6260 NewIntNo = Intrinsic::x86_mmx_psra_d; 6261 break; 6262 default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here. 6263 } 6264 break; 6265 } 6266 } 6267 MVT VT = Op.getValueType(); 6268 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, 6269 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt)); 6270 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6271 DAG.getConstant(NewIntNo, MVT::i32), 6272 Op.getOperand(1), ShAmt); 6273 } 6274 } 6275} 6276 6277SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6278 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6279 DebugLoc dl = Op.getDebugLoc(); 6280 6281 if (Depth > 0) { 6282 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6283 SDValue Offset = 6284 DAG.getConstant(TD->getPointerSize(), 6285 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 6286 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6287 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6288 FrameAddr, Offset), 6289 NULL, 0); 6290 } 6291 6292 // Just load the return address. 6293 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 6294 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6295 RetAddrFI, NULL, 0); 6296} 6297 6298SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6299 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6300 MFI->setFrameAddressIsTaken(true); 6301 MVT VT = Op.getValueType(); 6302 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 6303 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6304 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6305 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 6306 while (Depth--) 6307 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 6308 return FrameAddr; 6309} 6310 6311SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6312 SelectionDAG &DAG) { 6313 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6314} 6315 6316SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6317{ 6318 MachineFunction &MF = DAG.getMachineFunction(); 6319 SDValue Chain = Op.getOperand(0); 6320 SDValue Offset = Op.getOperand(1); 6321 SDValue Handler = Op.getOperand(2); 6322 DebugLoc dl = Op.getDebugLoc(); 6323 6324 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6325 getPointerTy()); 6326 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6327 6328 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 6329 DAG.getIntPtrConstant(-TD->getPointerSize())); 6330 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 6331 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0); 6332 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 6333 MF.getRegInfo().addLiveOut(StoreAddrReg); 6334 6335 return DAG.getNode(X86ISD::EH_RETURN, dl, 6336 MVT::Other, 6337 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 6338} 6339 6340SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 6341 SelectionDAG &DAG) { 6342 SDValue Root = Op.getOperand(0); 6343 SDValue Trmp = Op.getOperand(1); // trampoline 6344 SDValue FPtr = Op.getOperand(2); // nested function 6345 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 6346 DebugLoc dl = Op.getDebugLoc(); 6347 6348 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6349 6350 const X86InstrInfo *TII = 6351 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 6352 6353 if (Subtarget->is64Bit()) { 6354 SDValue OutChains[6]; 6355 6356 // Large code-model. 6357 6358 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 6359 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 6360 6361 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 6362 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 6363 6364 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 6365 6366 // Load the pointer to the nested function into R11. 6367 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 6368 SDValue Addr = Trmp; 6369 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6370 Addr, TrmpAddr, 0); 6371 6372 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6373 DAG.getConstant(2, MVT::i64)); 6374 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2); 6375 6376 // Load the 'nest' parameter value into R10. 6377 // R10 is specified in X86CallingConv.td 6378 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 6379 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6380 DAG.getConstant(10, MVT::i64)); 6381 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6382 Addr, TrmpAddr, 10); 6383 6384 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6385 DAG.getConstant(12, MVT::i64)); 6386 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2); 6387 6388 // Jump to the nested function. 6389 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 6390 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6391 DAG.getConstant(20, MVT::i64)); 6392 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6393 Addr, TrmpAddr, 20); 6394 6395 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 6396 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6397 DAG.getConstant(22, MVT::i64)); 6398 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 6399 TrmpAddr, 22); 6400 6401 SDValue Ops[] = 6402 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 6403 return DAG.getMergeValues(Ops, 2, dl); 6404 } else { 6405 const Function *Func = 6406 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 6407 unsigned CC = Func->getCallingConv(); 6408 unsigned NestReg; 6409 6410 switch (CC) { 6411 default: 6412 assert(0 && "Unsupported calling convention"); 6413 case CallingConv::C: 6414 case CallingConv::X86_StdCall: { 6415 // Pass 'nest' parameter in ECX. 6416 // Must be kept in sync with X86CallingConv.td 6417 NestReg = X86::ECX; 6418 6419 // Check that ECX wasn't needed by an 'inreg' parameter. 6420 const FunctionType *FTy = Func->getFunctionType(); 6421 const AttrListPtr &Attrs = Func->getAttributes(); 6422 6423 if (!Attrs.isEmpty() && !Func->isVarArg()) { 6424 unsigned InRegCount = 0; 6425 unsigned Idx = 1; 6426 6427 for (FunctionType::param_iterator I = FTy->param_begin(), 6428 E = FTy->param_end(); I != E; ++I, ++Idx) 6429 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 6430 // FIXME: should only count parameters that are lowered to integers. 6431 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 6432 6433 if (InRegCount > 2) { 6434 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 6435 } 6436 } 6437 break; 6438 } 6439 case CallingConv::X86_FastCall: 6440 case CallingConv::Fast: 6441 // Pass 'nest' parameter in EAX. 6442 // Must be kept in sync with X86CallingConv.td 6443 NestReg = X86::EAX; 6444 break; 6445 } 6446 6447 SDValue OutChains[4]; 6448 SDValue Addr, Disp; 6449 6450 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6451 DAG.getConstant(10, MVT::i32)); 6452 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 6453 6454 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 6455 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 6456 OutChains[0] = DAG.getStore(Root, dl, 6457 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 6458 Trmp, TrmpAddr, 0); 6459 6460 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6461 DAG.getConstant(1, MVT::i32)); 6462 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1); 6463 6464 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 6465 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6466 DAG.getConstant(5, MVT::i32)); 6467 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 6468 TrmpAddr, 5, false, 1); 6469 6470 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6471 DAG.getConstant(6, MVT::i32)); 6472 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1); 6473 6474 SDValue Ops[] = 6475 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 6476 return DAG.getMergeValues(Ops, 2, dl); 6477 } 6478} 6479 6480SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 6481 /* 6482 The rounding mode is in bits 11:10 of FPSR, and has the following 6483 settings: 6484 00 Round to nearest 6485 01 Round to -inf 6486 10 Round to +inf 6487 11 Round to 0 6488 6489 FLT_ROUNDS, on the other hand, expects the following: 6490 -1 Undefined 6491 0 Round to 0 6492 1 Round to nearest 6493 2 Round to +inf 6494 3 Round to -inf 6495 6496 To perform the conversion, we do: 6497 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 6498 */ 6499 6500 MachineFunction &MF = DAG.getMachineFunction(); 6501 const TargetMachine &TM = MF.getTarget(); 6502 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 6503 unsigned StackAlignment = TFI.getStackAlignment(); 6504 MVT VT = Op.getValueType(); 6505 DebugLoc dl = Op.getDebugLoc(); 6506 6507 // Save FP Control Word to stack slot 6508 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 6509 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6510 6511 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 6512 DAG.getEntryNode(), StackSlot); 6513 6514 // Load FP Control Word from stack slot 6515 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0); 6516 6517 // Transform as necessary 6518 SDValue CWD1 = 6519 DAG.getNode(ISD::SRL, dl, MVT::i16, 6520 DAG.getNode(ISD::AND, dl, MVT::i16, 6521 CWD, DAG.getConstant(0x800, MVT::i16)), 6522 DAG.getConstant(11, MVT::i8)); 6523 SDValue CWD2 = 6524 DAG.getNode(ISD::SRL, dl, MVT::i16, 6525 DAG.getNode(ISD::AND, dl, MVT::i16, 6526 CWD, DAG.getConstant(0x400, MVT::i16)), 6527 DAG.getConstant(9, MVT::i8)); 6528 6529 SDValue RetVal = 6530 DAG.getNode(ISD::AND, dl, MVT::i16, 6531 DAG.getNode(ISD::ADD, dl, MVT::i16, 6532 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 6533 DAG.getConstant(1, MVT::i16)), 6534 DAG.getConstant(3, MVT::i16)); 6535 6536 6537 return DAG.getNode((VT.getSizeInBits() < 16 ? 6538 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 6539} 6540 6541SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 6542 MVT VT = Op.getValueType(); 6543 MVT OpVT = VT; 6544 unsigned NumBits = VT.getSizeInBits(); 6545 DebugLoc dl = Op.getDebugLoc(); 6546 6547 Op = Op.getOperand(0); 6548 if (VT == MVT::i8) { 6549 // Zero extend to i32 since there is not an i8 bsr. 6550 OpVT = MVT::i32; 6551 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6552 } 6553 6554 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 6555 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6556 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 6557 6558 // If src is zero (i.e. bsr sets ZF), returns NumBits. 6559 SmallVector<SDValue, 4> Ops; 6560 Ops.push_back(Op); 6561 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 6562 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6563 Ops.push_back(Op.getValue(1)); 6564 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6565 6566 // Finally xor with NumBits-1. 6567 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 6568 6569 if (VT == MVT::i8) 6570 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6571 return Op; 6572} 6573 6574SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 6575 MVT VT = Op.getValueType(); 6576 MVT OpVT = VT; 6577 unsigned NumBits = VT.getSizeInBits(); 6578 DebugLoc dl = Op.getDebugLoc(); 6579 6580 Op = Op.getOperand(0); 6581 if (VT == MVT::i8) { 6582 OpVT = MVT::i32; 6583 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6584 } 6585 6586 // Issue a bsf (scan bits forward) which also sets EFLAGS. 6587 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6588 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 6589 6590 // If src is zero (i.e. bsf sets ZF), returns NumBits. 6591 SmallVector<SDValue, 4> Ops; 6592 Ops.push_back(Op); 6593 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 6594 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6595 Ops.push_back(Op.getValue(1)); 6596 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6597 6598 if (VT == MVT::i8) 6599 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6600 return Op; 6601} 6602 6603SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 6604 MVT VT = Op.getValueType(); 6605 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 6606 DebugLoc dl = Op.getDebugLoc(); 6607 6608 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 6609 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 6610 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 6611 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 6612 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 6613 // 6614 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 6615 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 6616 // return AloBlo + AloBhi + AhiBlo; 6617 6618 SDValue A = Op.getOperand(0); 6619 SDValue B = Op.getOperand(1); 6620 6621 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6622 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6623 A, DAG.getConstant(32, MVT::i32)); 6624 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6625 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6626 B, DAG.getConstant(32, MVT::i32)); 6627 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6628 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6629 A, B); 6630 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6631 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6632 A, Bhi); 6633 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6634 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6635 Ahi, B); 6636 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6637 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6638 AloBhi, DAG.getConstant(32, MVT::i32)); 6639 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6640 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6641 AhiBlo, DAG.getConstant(32, MVT::i32)); 6642 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 6643 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 6644 return Res; 6645} 6646 6647 6648SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 6649 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 6650 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 6651 // looks for this combo and may remove the "setcc" instruction if the "setcc" 6652 // has only one use. 6653 SDNode *N = Op.getNode(); 6654 SDValue LHS = N->getOperand(0); 6655 SDValue RHS = N->getOperand(1); 6656 unsigned BaseOp = 0; 6657 unsigned Cond = 0; 6658 DebugLoc dl = Op.getDebugLoc(); 6659 6660 switch (Op.getOpcode()) { 6661 default: assert(0 && "Unknown ovf instruction!"); 6662 case ISD::SADDO: 6663 // A subtract of one will be selected as a INC. Note that INC doesn't 6664 // set CF, so we can't do this for UADDO. 6665 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 6666 if (C->getAPIntValue() == 1) { 6667 BaseOp = X86ISD::INC; 6668 Cond = X86::COND_O; 6669 break; 6670 } 6671 BaseOp = X86ISD::ADD; 6672 Cond = X86::COND_O; 6673 break; 6674 case ISD::UADDO: 6675 BaseOp = X86ISD::ADD; 6676 Cond = X86::COND_B; 6677 break; 6678 case ISD::SSUBO: 6679 // A subtract of one will be selected as a DEC. Note that DEC doesn't 6680 // set CF, so we can't do this for USUBO. 6681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 6682 if (C->getAPIntValue() == 1) { 6683 BaseOp = X86ISD::DEC; 6684 Cond = X86::COND_O; 6685 break; 6686 } 6687 BaseOp = X86ISD::SUB; 6688 Cond = X86::COND_O; 6689 break; 6690 case ISD::USUBO: 6691 BaseOp = X86ISD::SUB; 6692 Cond = X86::COND_B; 6693 break; 6694 case ISD::SMULO: 6695 BaseOp = X86ISD::SMUL; 6696 Cond = X86::COND_O; 6697 break; 6698 case ISD::UMULO: 6699 BaseOp = X86ISD::UMUL; 6700 Cond = X86::COND_B; 6701 break; 6702 } 6703 6704 // Also sets EFLAGS. 6705 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 6706 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 6707 6708 SDValue SetCC = 6709 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 6710 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 6711 6712 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 6713 return Sum; 6714} 6715 6716SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 6717 MVT T = Op.getValueType(); 6718 DebugLoc dl = Op.getDebugLoc(); 6719 unsigned Reg = 0; 6720 unsigned size = 0; 6721 switch(T.getSimpleVT()) { 6722 default: 6723 assert(false && "Invalid value type!"); 6724 case MVT::i8: Reg = X86::AL; size = 1; break; 6725 case MVT::i16: Reg = X86::AX; size = 2; break; 6726 case MVT::i32: Reg = X86::EAX; size = 4; break; 6727 case MVT::i64: 6728 assert(Subtarget->is64Bit() && "Node not type legal!"); 6729 Reg = X86::RAX; size = 8; 6730 break; 6731 } 6732 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 6733 Op.getOperand(2), SDValue()); 6734 SDValue Ops[] = { cpIn.getValue(0), 6735 Op.getOperand(1), 6736 Op.getOperand(3), 6737 DAG.getTargetConstant(size, MVT::i8), 6738 cpIn.getValue(1) }; 6739 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6740 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 6741 SDValue cpOut = 6742 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 6743 return cpOut; 6744} 6745 6746SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 6747 SelectionDAG &DAG) { 6748 assert(Subtarget->is64Bit() && "Result not type legalized?"); 6749 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6750 SDValue TheChain = Op.getOperand(0); 6751 DebugLoc dl = Op.getDebugLoc(); 6752 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6753 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 6754 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 6755 rax.getValue(2)); 6756 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 6757 DAG.getConstant(32, MVT::i8)); 6758 SDValue Ops[] = { 6759 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 6760 rdx.getValue(1) 6761 }; 6762 return DAG.getMergeValues(Ops, 2, dl); 6763} 6764 6765SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 6766 SDNode *Node = Op.getNode(); 6767 DebugLoc dl = Node->getDebugLoc(); 6768 MVT T = Node->getValueType(0); 6769 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 6770 DAG.getConstant(0, T), Node->getOperand(2)); 6771 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 6772 cast<AtomicSDNode>(Node)->getMemoryVT(), 6773 Node->getOperand(0), 6774 Node->getOperand(1), negOp, 6775 cast<AtomicSDNode>(Node)->getSrcValue(), 6776 cast<AtomicSDNode>(Node)->getAlignment()); 6777} 6778 6779/// LowerOperation - Provide custom lowering hooks for some operations. 6780/// 6781SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 6782 switch (Op.getOpcode()) { 6783 default: assert(0 && "Should not custom lower this!"); 6784 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 6785 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 6786 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 6787 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 6788 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 6789 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 6790 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 6791 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 6792 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 6793 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 6794 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 6795 case ISD::SHL_PARTS: 6796 case ISD::SRA_PARTS: 6797 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 6798 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 6799 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 6800 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 6801 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 6802 case ISD::FABS: return LowerFABS(Op, DAG); 6803 case ISD::FNEG: return LowerFNEG(Op, DAG); 6804 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 6805 case ISD::SETCC: return LowerSETCC(Op, DAG); 6806 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 6807 case ISD::SELECT: return LowerSELECT(Op, DAG); 6808 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 6809 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 6810 case ISD::CALL: return LowerCALL(Op, DAG); 6811 case ISD::RET: return LowerRET(Op, DAG); 6812 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 6813 case ISD::VASTART: return LowerVASTART(Op, DAG); 6814 case ISD::VAARG: return LowerVAARG(Op, DAG); 6815 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 6816 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 6817 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 6818 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 6819 case ISD::FRAME_TO_ARGS_OFFSET: 6820 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 6821 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 6822 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 6823 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 6824 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 6825 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 6826 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 6827 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 6828 case ISD::SADDO: 6829 case ISD::UADDO: 6830 case ISD::SSUBO: 6831 case ISD::USUBO: 6832 case ISD::SMULO: 6833 case ISD::UMULO: return LowerXALUO(Op, DAG); 6834 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 6835 } 6836} 6837 6838void X86TargetLowering:: 6839ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 6840 SelectionDAG &DAG, unsigned NewOp) { 6841 MVT T = Node->getValueType(0); 6842 DebugLoc dl = Node->getDebugLoc(); 6843 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 6844 6845 SDValue Chain = Node->getOperand(0); 6846 SDValue In1 = Node->getOperand(1); 6847 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6848 Node->getOperand(2), DAG.getIntPtrConstant(0)); 6849 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6850 Node->getOperand(2), DAG.getIntPtrConstant(1)); 6851 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't 6852 // have a MemOperand. Pass the info through as a normal operand. 6853 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); 6854 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; 6855 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 6856 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5); 6857 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 6858 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6859 Results.push_back(Result.getValue(2)); 6860} 6861 6862/// ReplaceNodeResults - Replace a node with an illegal result type 6863/// with a new node built out of custom code. 6864void X86TargetLowering::ReplaceNodeResults(SDNode *N, 6865 SmallVectorImpl<SDValue>&Results, 6866 SelectionDAG &DAG) { 6867 DebugLoc dl = N->getDebugLoc(); 6868 switch (N->getOpcode()) { 6869 default: 6870 assert(false && "Do not know how to custom type legalize this operation!"); 6871 return; 6872 case ISD::FP_TO_SINT: { 6873 std::pair<SDValue,SDValue> Vals = 6874 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 6875 SDValue FIST = Vals.first, StackSlot = Vals.second; 6876 if (FIST.getNode() != 0) { 6877 MVT VT = N->getValueType(0); 6878 // Return a load from the stack slot. 6879 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0)); 6880 } 6881 return; 6882 } 6883 case ISD::READCYCLECOUNTER: { 6884 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6885 SDValue TheChain = N->getOperand(0); 6886 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6887 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 6888 rd.getValue(1)); 6889 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 6890 eax.getValue(2)); 6891 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 6892 SDValue Ops[] = { eax, edx }; 6893 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 6894 Results.push_back(edx.getValue(1)); 6895 return; 6896 } 6897 case ISD::ATOMIC_CMP_SWAP: { 6898 MVT T = N->getValueType(0); 6899 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 6900 SDValue cpInL, cpInH; 6901 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 6902 DAG.getConstant(0, MVT::i32)); 6903 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 6904 DAG.getConstant(1, MVT::i32)); 6905 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 6906 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 6907 cpInL.getValue(1)); 6908 SDValue swapInL, swapInH; 6909 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 6910 DAG.getConstant(0, MVT::i32)); 6911 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 6912 DAG.getConstant(1, MVT::i32)); 6913 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 6914 cpInH.getValue(1)); 6915 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 6916 swapInL.getValue(1)); 6917 SDValue Ops[] = { swapInH.getValue(0), 6918 N->getOperand(1), 6919 swapInH.getValue(1) }; 6920 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6921 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 6922 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 6923 MVT::i32, Result.getValue(1)); 6924 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 6925 MVT::i32, cpOutL.getValue(2)); 6926 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 6927 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6928 Results.push_back(cpOutH.getValue(1)); 6929 return; 6930 } 6931 case ISD::ATOMIC_LOAD_ADD: 6932 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 6933 return; 6934 case ISD::ATOMIC_LOAD_AND: 6935 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 6936 return; 6937 case ISD::ATOMIC_LOAD_NAND: 6938 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 6939 return; 6940 case ISD::ATOMIC_LOAD_OR: 6941 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 6942 return; 6943 case ISD::ATOMIC_LOAD_SUB: 6944 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 6945 return; 6946 case ISD::ATOMIC_LOAD_XOR: 6947 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 6948 return; 6949 case ISD::ATOMIC_SWAP: 6950 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 6951 return; 6952 } 6953} 6954 6955const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 6956 switch (Opcode) { 6957 default: return NULL; 6958 case X86ISD::BSF: return "X86ISD::BSF"; 6959 case X86ISD::BSR: return "X86ISD::BSR"; 6960 case X86ISD::SHLD: return "X86ISD::SHLD"; 6961 case X86ISD::SHRD: return "X86ISD::SHRD"; 6962 case X86ISD::FAND: return "X86ISD::FAND"; 6963 case X86ISD::FOR: return "X86ISD::FOR"; 6964 case X86ISD::FXOR: return "X86ISD::FXOR"; 6965 case X86ISD::FSRL: return "X86ISD::FSRL"; 6966 case X86ISD::FILD: return "X86ISD::FILD"; 6967 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 6968 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 6969 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 6970 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 6971 case X86ISD::FLD: return "X86ISD::FLD"; 6972 case X86ISD::FST: return "X86ISD::FST"; 6973 case X86ISD::CALL: return "X86ISD::CALL"; 6974 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 6975 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 6976 case X86ISD::BT: return "X86ISD::BT"; 6977 case X86ISD::CMP: return "X86ISD::CMP"; 6978 case X86ISD::COMI: return "X86ISD::COMI"; 6979 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 6980 case X86ISD::SETCC: return "X86ISD::SETCC"; 6981 case X86ISD::CMOV: return "X86ISD::CMOV"; 6982 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 6983 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 6984 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 6985 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 6986 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 6987 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 6988 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 6989 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 6990 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 6991 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 6992 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 6993 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 6994 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 6995 case X86ISD::FMAX: return "X86ISD::FMAX"; 6996 case X86ISD::FMIN: return "X86ISD::FMIN"; 6997 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 6998 case X86ISD::FRCP: return "X86ISD::FRCP"; 6999 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7000 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7001 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7002 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7003 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7004 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7005 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7006 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7007 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7008 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7009 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7010 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7011 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7012 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7013 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7014 case X86ISD::VSHL: return "X86ISD::VSHL"; 7015 case X86ISD::VSRL: return "X86ISD::VSRL"; 7016 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7017 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7018 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7019 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7020 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7021 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7022 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7023 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7024 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7025 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7026 case X86ISD::ADD: return "X86ISD::ADD"; 7027 case X86ISD::SUB: return "X86ISD::SUB"; 7028 case X86ISD::SMUL: return "X86ISD::SMUL"; 7029 case X86ISD::UMUL: return "X86ISD::UMUL"; 7030 case X86ISD::INC: return "X86ISD::INC"; 7031 case X86ISD::DEC: return "X86ISD::DEC"; 7032 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7033 } 7034} 7035 7036// isLegalAddressingMode - Return true if the addressing mode represented 7037// by AM is legal for this target, for a load/store of the specified type. 7038bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7039 const Type *Ty) const { 7040 // X86 supports extremely general addressing modes. 7041 7042 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7043 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) 7044 return false; 7045 7046 if (AM.BaseGV) { 7047 // We can only fold this if we don't need an extra load. 7048 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) 7049 return false; 7050 // If BaseGV requires a register, we cannot also have a BaseReg. 7051 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) && 7052 AM.HasBaseReg) 7053 return false; 7054 7055 // X86-64 only supports addr of globals in small code model. 7056 if (Subtarget->is64Bit()) { 7057 if (getTargetMachine().getCodeModel() != CodeModel::Small) 7058 return false; 7059 // If lower 4G is not available, then we must use rip-relative addressing. 7060 if (AM.BaseOffs || AM.Scale > 1) 7061 return false; 7062 } 7063 } 7064 7065 switch (AM.Scale) { 7066 case 0: 7067 case 1: 7068 case 2: 7069 case 4: 7070 case 8: 7071 // These scales always work. 7072 break; 7073 case 3: 7074 case 5: 7075 case 9: 7076 // These scales are formed with basereg+scalereg. Only accept if there is 7077 // no basereg yet. 7078 if (AM.HasBaseReg) 7079 return false; 7080 break; 7081 default: // Other stuff never works. 7082 return false; 7083 } 7084 7085 return true; 7086} 7087 7088 7089bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7090 if (!Ty1->isInteger() || !Ty2->isInteger()) 7091 return false; 7092 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7093 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7094 if (NumBits1 <= NumBits2) 7095 return false; 7096 return Subtarget->is64Bit() || NumBits1 < 64; 7097} 7098 7099bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { 7100 if (!VT1.isInteger() || !VT2.isInteger()) 7101 return false; 7102 unsigned NumBits1 = VT1.getSizeInBits(); 7103 unsigned NumBits2 = VT2.getSizeInBits(); 7104 if (NumBits1 <= NumBits2) 7105 return false; 7106 return Subtarget->is64Bit() || NumBits1 < 64; 7107} 7108 7109bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7110 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7111 return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit(); 7112} 7113 7114bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const { 7115 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7116 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7117} 7118 7119bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const { 7120 // i16 instructions are longer (0x66 prefix) and potentially slower. 7121 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7122} 7123 7124/// isShuffleMaskLegal - Targets can use this to indicate that they only 7125/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7126/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7127/// are assumed to be legal. 7128bool 7129X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7130 MVT VT) const { 7131 // Only do shuffles on 128-bit vector types for now. 7132 if (VT.getSizeInBits() == 64) 7133 return false; 7134 7135 // FIXME: pshufb, blends, palignr, shifts. 7136 return (VT.getVectorNumElements() == 2 || 7137 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7138 isMOVLMask(M, VT) || 7139 isSHUFPMask(M, VT) || 7140 isPSHUFDMask(M, VT) || 7141 isPSHUFHWMask(M, VT) || 7142 isPSHUFLWMask(M, VT) || 7143 isUNPCKLMask(M, VT) || 7144 isUNPCKHMask(M, VT) || 7145 isUNPCKL_v_undef_Mask(M, VT) || 7146 isUNPCKH_v_undef_Mask(M, VT)); 7147} 7148 7149bool 7150X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7151 MVT VT) const { 7152 unsigned NumElts = VT.getVectorNumElements(); 7153 // FIXME: This collection of masks seems suspect. 7154 if (NumElts == 2) 7155 return true; 7156 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7157 return (isMOVLMask(Mask, VT) || 7158 isCommutedMOVLMask(Mask, VT, true) || 7159 isSHUFPMask(Mask, VT) || 7160 isCommutedSHUFPMask(Mask, VT)); 7161 } 7162 return false; 7163} 7164 7165//===----------------------------------------------------------------------===// 7166// X86 Scheduler Hooks 7167//===----------------------------------------------------------------------===// 7168 7169// private utility function 7170MachineBasicBlock * 7171X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7172 MachineBasicBlock *MBB, 7173 unsigned regOpc, 7174 unsigned immOpc, 7175 unsigned LoadOpc, 7176 unsigned CXchgOpc, 7177 unsigned copyOpc, 7178 unsigned notOpc, 7179 unsigned EAXreg, 7180 TargetRegisterClass *RC, 7181 bool invSrc) const { 7182 // For the atomic bitwise operator, we generate 7183 // thisMBB: 7184 // newMBB: 7185 // ld t1 = [bitinstr.addr] 7186 // op t2 = t1, [bitinstr.val] 7187 // mov EAX = t1 7188 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7189 // bz newMBB 7190 // fallthrough -->nextMBB 7191 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7192 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7193 MachineFunction::iterator MBBIter = MBB; 7194 ++MBBIter; 7195 7196 /// First build the CFG 7197 MachineFunction *F = MBB->getParent(); 7198 MachineBasicBlock *thisMBB = MBB; 7199 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7200 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7201 F->insert(MBBIter, newMBB); 7202 F->insert(MBBIter, nextMBB); 7203 7204 // Move all successors to thisMBB to nextMBB 7205 nextMBB->transferSuccessors(thisMBB); 7206 7207 // Update thisMBB to fall through to newMBB 7208 thisMBB->addSuccessor(newMBB); 7209 7210 // newMBB jumps to itself and fall through to nextMBB 7211 newMBB->addSuccessor(nextMBB); 7212 newMBB->addSuccessor(newMBB); 7213 7214 // Insert instructions into newMBB based on incoming instruction 7215 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 7216 "unexpected number of operands"); 7217 DebugLoc dl = bInstr->getDebugLoc(); 7218 MachineOperand& destOper = bInstr->getOperand(0); 7219 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7220 int numArgs = bInstr->getNumOperands() - 1; 7221 for (int i=0; i < numArgs; ++i) 7222 argOpers[i] = &bInstr->getOperand(i+1); 7223 7224 // x86 address has 4 operands: base, index, scale, and displacement 7225 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7226 int valArgIndx = lastAddrIndx + 1; 7227 7228 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7229 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7230 for (int i=0; i <= lastAddrIndx; ++i) 7231 (*MIB).addOperand(*argOpers[i]); 7232 7233 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7234 if (invSrc) { 7235 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7236 } 7237 else 7238 tt = t1; 7239 7240 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7241 assert((argOpers[valArgIndx]->isReg() || 7242 argOpers[valArgIndx]->isImm()) && 7243 "invalid operand"); 7244 if (argOpers[valArgIndx]->isReg()) 7245 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7246 else 7247 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7248 MIB.addReg(tt); 7249 (*MIB).addOperand(*argOpers[valArgIndx]); 7250 7251 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7252 MIB.addReg(t1); 7253 7254 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7255 for (int i=0; i <= lastAddrIndx; ++i) 7256 (*MIB).addOperand(*argOpers[i]); 7257 MIB.addReg(t2); 7258 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7259 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7260 7261 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7262 MIB.addReg(EAXreg); 7263 7264 // insert branch 7265 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7266 7267 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7268 return nextMBB; 7269} 7270 7271// private utility function: 64 bit atomics on 32 bit host. 7272MachineBasicBlock * 7273X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 7274 MachineBasicBlock *MBB, 7275 unsigned regOpcL, 7276 unsigned regOpcH, 7277 unsigned immOpcL, 7278 unsigned immOpcH, 7279 bool invSrc) const { 7280 // For the atomic bitwise operator, we generate 7281 // thisMBB (instructions are in pairs, except cmpxchg8b) 7282 // ld t1,t2 = [bitinstr.addr] 7283 // newMBB: 7284 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 7285 // op t5, t6 <- out1, out2, [bitinstr.val] 7286 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 7287 // mov ECX, EBX <- t5, t6 7288 // mov EAX, EDX <- t1, t2 7289 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 7290 // mov t3, t4 <- EAX, EDX 7291 // bz newMBB 7292 // result in out1, out2 7293 // fallthrough -->nextMBB 7294 7295 const TargetRegisterClass *RC = X86::GR32RegisterClass; 7296 const unsigned LoadOpc = X86::MOV32rm; 7297 const unsigned copyOpc = X86::MOV32rr; 7298 const unsigned NotOpc = X86::NOT32r; 7299 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7300 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7301 MachineFunction::iterator MBBIter = MBB; 7302 ++MBBIter; 7303 7304 /// First build the CFG 7305 MachineFunction *F = MBB->getParent(); 7306 MachineBasicBlock *thisMBB = MBB; 7307 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7308 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7309 F->insert(MBBIter, newMBB); 7310 F->insert(MBBIter, nextMBB); 7311 7312 // Move all successors to thisMBB to nextMBB 7313 nextMBB->transferSuccessors(thisMBB); 7314 7315 // Update thisMBB to fall through to newMBB 7316 thisMBB->addSuccessor(newMBB); 7317 7318 // newMBB jumps to itself and fall through to nextMBB 7319 newMBB->addSuccessor(nextMBB); 7320 newMBB->addSuccessor(newMBB); 7321 7322 DebugLoc dl = bInstr->getDebugLoc(); 7323 // Insert instructions into newMBB based on incoming instruction 7324 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 7325 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 7326 "unexpected number of operands"); 7327 MachineOperand& dest1Oper = bInstr->getOperand(0); 7328 MachineOperand& dest2Oper = bInstr->getOperand(1); 7329 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7330 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 7331 argOpers[i] = &bInstr->getOperand(i+2); 7332 7333 // x86 address has 4 operands: base, index, scale, and displacement 7334 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7335 7336 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7337 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 7338 for (int i=0; i <= lastAddrIndx; ++i) 7339 (*MIB).addOperand(*argOpers[i]); 7340 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7341 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 7342 // add 4 to displacement. 7343 for (int i=0; i <= lastAddrIndx-2; ++i) 7344 (*MIB).addOperand(*argOpers[i]); 7345 MachineOperand newOp3 = *(argOpers[3]); 7346 if (newOp3.isImm()) 7347 newOp3.setImm(newOp3.getImm()+4); 7348 else 7349 newOp3.setOffset(newOp3.getOffset()+4); 7350 (*MIB).addOperand(newOp3); 7351 (*MIB).addOperand(*argOpers[lastAddrIndx]); 7352 7353 // t3/4 are defined later, at the bottom of the loop 7354 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 7355 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 7356 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 7357 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 7358 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 7359 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 7360 7361 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); 7362 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); 7363 if (invSrc) { 7364 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1); 7365 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2); 7366 } else { 7367 tt1 = t1; 7368 tt2 = t2; 7369 } 7370 7371 int valArgIndx = lastAddrIndx + 1; 7372 assert((argOpers[valArgIndx]->isReg() || 7373 argOpers[valArgIndx]->isImm()) && 7374 "invalid operand"); 7375 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 7376 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 7377 if (argOpers[valArgIndx]->isReg()) 7378 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 7379 else 7380 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 7381 if (regOpcL != X86::MOV32rr) 7382 MIB.addReg(tt1); 7383 (*MIB).addOperand(*argOpers[valArgIndx]); 7384 assert(argOpers[valArgIndx + 1]->isReg() == 7385 argOpers[valArgIndx]->isReg()); 7386 assert(argOpers[valArgIndx + 1]->isImm() == 7387 argOpers[valArgIndx]->isImm()); 7388 if (argOpers[valArgIndx + 1]->isReg()) 7389 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 7390 else 7391 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 7392 if (regOpcH != X86::MOV32rr) 7393 MIB.addReg(tt2); 7394 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 7395 7396 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 7397 MIB.addReg(t1); 7398 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 7399 MIB.addReg(t2); 7400 7401 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 7402 MIB.addReg(t5); 7403 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 7404 MIB.addReg(t6); 7405 7406 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 7407 for (int i=0; i <= lastAddrIndx; ++i) 7408 (*MIB).addOperand(*argOpers[i]); 7409 7410 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7411 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7412 7413 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 7414 MIB.addReg(X86::EAX); 7415 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 7416 MIB.addReg(X86::EDX); 7417 7418 // insert branch 7419 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7420 7421 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7422 return nextMBB; 7423} 7424 7425// private utility function 7426MachineBasicBlock * 7427X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 7428 MachineBasicBlock *MBB, 7429 unsigned cmovOpc) const { 7430 // For the atomic min/max operator, we generate 7431 // thisMBB: 7432 // newMBB: 7433 // ld t1 = [min/max.addr] 7434 // mov t2 = [min/max.val] 7435 // cmp t1, t2 7436 // cmov[cond] t2 = t1 7437 // mov EAX = t1 7438 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7439 // bz newMBB 7440 // fallthrough -->nextMBB 7441 // 7442 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7443 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7444 MachineFunction::iterator MBBIter = MBB; 7445 ++MBBIter; 7446 7447 /// First build the CFG 7448 MachineFunction *F = MBB->getParent(); 7449 MachineBasicBlock *thisMBB = MBB; 7450 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7451 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7452 F->insert(MBBIter, newMBB); 7453 F->insert(MBBIter, nextMBB); 7454 7455 // Move all successors to thisMBB to nextMBB 7456 nextMBB->transferSuccessors(thisMBB); 7457 7458 // Update thisMBB to fall through to newMBB 7459 thisMBB->addSuccessor(newMBB); 7460 7461 // newMBB jumps to newMBB and fall through to nextMBB 7462 newMBB->addSuccessor(nextMBB); 7463 newMBB->addSuccessor(newMBB); 7464 7465 DebugLoc dl = mInstr->getDebugLoc(); 7466 // Insert instructions into newMBB based on incoming instruction 7467 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 7468 "unexpected number of operands"); 7469 MachineOperand& destOper = mInstr->getOperand(0); 7470 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7471 int numArgs = mInstr->getNumOperands() - 1; 7472 for (int i=0; i < numArgs; ++i) 7473 argOpers[i] = &mInstr->getOperand(i+1); 7474 7475 // x86 address has 4 operands: base, index, scale, and displacement 7476 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7477 int valArgIndx = lastAddrIndx + 1; 7478 7479 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7480 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 7481 for (int i=0; i <= lastAddrIndx; ++i) 7482 (*MIB).addOperand(*argOpers[i]); 7483 7484 // We only support register and immediate values 7485 assert((argOpers[valArgIndx]->isReg() || 7486 argOpers[valArgIndx]->isImm()) && 7487 "invalid operand"); 7488 7489 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7490 if (argOpers[valArgIndx]->isReg()) 7491 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7492 else 7493 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7494 (*MIB).addOperand(*argOpers[valArgIndx]); 7495 7496 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 7497 MIB.addReg(t1); 7498 7499 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 7500 MIB.addReg(t1); 7501 MIB.addReg(t2); 7502 7503 // Generate movc 7504 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7505 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 7506 MIB.addReg(t2); 7507 MIB.addReg(t1); 7508 7509 // Cmp and exchange if none has modified the memory location 7510 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 7511 for (int i=0; i <= lastAddrIndx; ++i) 7512 (*MIB).addOperand(*argOpers[i]); 7513 MIB.addReg(t3); 7514 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7515 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 7516 7517 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 7518 MIB.addReg(X86::EAX); 7519 7520 // insert branch 7521 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7522 7523 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 7524 return nextMBB; 7525} 7526 7527 7528MachineBasicBlock * 7529X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 7530 MachineBasicBlock *BB) const { 7531 DebugLoc dl = MI->getDebugLoc(); 7532 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7533 switch (MI->getOpcode()) { 7534 default: assert(false && "Unexpected instr type to insert"); 7535 case X86::CMOV_V1I64: 7536 case X86::CMOV_FR32: 7537 case X86::CMOV_FR64: 7538 case X86::CMOV_V4F32: 7539 case X86::CMOV_V2F64: 7540 case X86::CMOV_V2I64: { 7541 // To "insert" a SELECT_CC instruction, we actually have to insert the 7542 // diamond control-flow pattern. The incoming instruction knows the 7543 // destination vreg to set, the condition code register to branch on, the 7544 // true/false values to select between, and a branch opcode to use. 7545 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 7546 MachineFunction::iterator It = BB; 7547 ++It; 7548 7549 // thisMBB: 7550 // ... 7551 // TrueVal = ... 7552 // cmpTY ccX, r1, r2 7553 // bCC copy1MBB 7554 // fallthrough --> copy0MBB 7555 MachineBasicBlock *thisMBB = BB; 7556 MachineFunction *F = BB->getParent(); 7557 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 7558 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 7559 unsigned Opc = 7560 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 7561 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 7562 F->insert(It, copy0MBB); 7563 F->insert(It, sinkMBB); 7564 // Update machine-CFG edges by transferring all successors of the current 7565 // block to the new block which will contain the Phi node for the select. 7566 sinkMBB->transferSuccessors(BB); 7567 7568 // Add the true and fallthrough blocks as its successors. 7569 BB->addSuccessor(copy0MBB); 7570 BB->addSuccessor(sinkMBB); 7571 7572 // copy0MBB: 7573 // %FalseValue = ... 7574 // # fallthrough to sinkMBB 7575 BB = copy0MBB; 7576 7577 // Update machine-CFG edges 7578 BB->addSuccessor(sinkMBB); 7579 7580 // sinkMBB: 7581 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 7582 // ... 7583 BB = sinkMBB; 7584 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg()) 7585 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 7586 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 7587 7588 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7589 return BB; 7590 } 7591 7592 case X86::FP32_TO_INT16_IN_MEM: 7593 case X86::FP32_TO_INT32_IN_MEM: 7594 case X86::FP32_TO_INT64_IN_MEM: 7595 case X86::FP64_TO_INT16_IN_MEM: 7596 case X86::FP64_TO_INT32_IN_MEM: 7597 case X86::FP64_TO_INT64_IN_MEM: 7598 case X86::FP80_TO_INT16_IN_MEM: 7599 case X86::FP80_TO_INT32_IN_MEM: 7600 case X86::FP80_TO_INT64_IN_MEM: { 7601 // Change the floating point control register to use "round towards zero" 7602 // mode when truncating to an integer value. 7603 MachineFunction *F = BB->getParent(); 7604 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 7605 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx); 7606 7607 // Load the old value of the high byte of the control word... 7608 unsigned OldCW = 7609 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 7610 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW), 7611 CWFrameIdx); 7612 7613 // Set the high part to be round to zero... 7614 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx) 7615 .addImm(0xC7F); 7616 7617 // Reload the modified control word now... 7618 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); 7619 7620 // Restore the memory image of control word to original value 7621 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx) 7622 .addReg(OldCW); 7623 7624 // Get the X86 opcode to use. 7625 unsigned Opc; 7626 switch (MI->getOpcode()) { 7627 default: assert(0 && "illegal opcode!"); 7628 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 7629 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 7630 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 7631 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 7632 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 7633 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 7634 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 7635 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 7636 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 7637 } 7638 7639 X86AddressMode AM; 7640 MachineOperand &Op = MI->getOperand(0); 7641 if (Op.isReg()) { 7642 AM.BaseType = X86AddressMode::RegBase; 7643 AM.Base.Reg = Op.getReg(); 7644 } else { 7645 AM.BaseType = X86AddressMode::FrameIndexBase; 7646 AM.Base.FrameIndex = Op.getIndex(); 7647 } 7648 Op = MI->getOperand(1); 7649 if (Op.isImm()) 7650 AM.Scale = Op.getImm(); 7651 Op = MI->getOperand(2); 7652 if (Op.isImm()) 7653 AM.IndexReg = Op.getImm(); 7654 Op = MI->getOperand(3); 7655 if (Op.isGlobal()) { 7656 AM.GV = Op.getGlobal(); 7657 } else { 7658 AM.Disp = Op.getImm(); 7659 } 7660 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM) 7661 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 7662 7663 // Reload the original control word now. 7664 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx); 7665 7666 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7667 return BB; 7668 } 7669 case X86::ATOMAND32: 7670 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7671 X86::AND32ri, X86::MOV32rm, 7672 X86::LCMPXCHG32, X86::MOV32rr, 7673 X86::NOT32r, X86::EAX, 7674 X86::GR32RegisterClass); 7675 case X86::ATOMOR32: 7676 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 7677 X86::OR32ri, X86::MOV32rm, 7678 X86::LCMPXCHG32, X86::MOV32rr, 7679 X86::NOT32r, X86::EAX, 7680 X86::GR32RegisterClass); 7681 case X86::ATOMXOR32: 7682 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 7683 X86::XOR32ri, X86::MOV32rm, 7684 X86::LCMPXCHG32, X86::MOV32rr, 7685 X86::NOT32r, X86::EAX, 7686 X86::GR32RegisterClass); 7687 case X86::ATOMNAND32: 7688 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7689 X86::AND32ri, X86::MOV32rm, 7690 X86::LCMPXCHG32, X86::MOV32rr, 7691 X86::NOT32r, X86::EAX, 7692 X86::GR32RegisterClass, true); 7693 case X86::ATOMMIN32: 7694 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 7695 case X86::ATOMMAX32: 7696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 7697 case X86::ATOMUMIN32: 7698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 7699 case X86::ATOMUMAX32: 7700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 7701 7702 case X86::ATOMAND16: 7703 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7704 X86::AND16ri, X86::MOV16rm, 7705 X86::LCMPXCHG16, X86::MOV16rr, 7706 X86::NOT16r, X86::AX, 7707 X86::GR16RegisterClass); 7708 case X86::ATOMOR16: 7709 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 7710 X86::OR16ri, X86::MOV16rm, 7711 X86::LCMPXCHG16, X86::MOV16rr, 7712 X86::NOT16r, X86::AX, 7713 X86::GR16RegisterClass); 7714 case X86::ATOMXOR16: 7715 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 7716 X86::XOR16ri, X86::MOV16rm, 7717 X86::LCMPXCHG16, X86::MOV16rr, 7718 X86::NOT16r, X86::AX, 7719 X86::GR16RegisterClass); 7720 case X86::ATOMNAND16: 7721 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7722 X86::AND16ri, X86::MOV16rm, 7723 X86::LCMPXCHG16, X86::MOV16rr, 7724 X86::NOT16r, X86::AX, 7725 X86::GR16RegisterClass, true); 7726 case X86::ATOMMIN16: 7727 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 7728 case X86::ATOMMAX16: 7729 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 7730 case X86::ATOMUMIN16: 7731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 7732 case X86::ATOMUMAX16: 7733 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 7734 7735 case X86::ATOMAND8: 7736 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7737 X86::AND8ri, X86::MOV8rm, 7738 X86::LCMPXCHG8, X86::MOV8rr, 7739 X86::NOT8r, X86::AL, 7740 X86::GR8RegisterClass); 7741 case X86::ATOMOR8: 7742 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 7743 X86::OR8ri, X86::MOV8rm, 7744 X86::LCMPXCHG8, X86::MOV8rr, 7745 X86::NOT8r, X86::AL, 7746 X86::GR8RegisterClass); 7747 case X86::ATOMXOR8: 7748 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 7749 X86::XOR8ri, X86::MOV8rm, 7750 X86::LCMPXCHG8, X86::MOV8rr, 7751 X86::NOT8r, X86::AL, 7752 X86::GR8RegisterClass); 7753 case X86::ATOMNAND8: 7754 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 7755 X86::AND8ri, X86::MOV8rm, 7756 X86::LCMPXCHG8, X86::MOV8rr, 7757 X86::NOT8r, X86::AL, 7758 X86::GR8RegisterClass, true); 7759 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 7760 // This group is for 64-bit host. 7761 case X86::ATOMAND64: 7762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7763 X86::AND64ri32, X86::MOV64rm, 7764 X86::LCMPXCHG64, X86::MOV64rr, 7765 X86::NOT64r, X86::RAX, 7766 X86::GR64RegisterClass); 7767 case X86::ATOMOR64: 7768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 7769 X86::OR64ri32, X86::MOV64rm, 7770 X86::LCMPXCHG64, X86::MOV64rr, 7771 X86::NOT64r, X86::RAX, 7772 X86::GR64RegisterClass); 7773 case X86::ATOMXOR64: 7774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 7775 X86::XOR64ri32, X86::MOV64rm, 7776 X86::LCMPXCHG64, X86::MOV64rr, 7777 X86::NOT64r, X86::RAX, 7778 X86::GR64RegisterClass); 7779 case X86::ATOMNAND64: 7780 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 7781 X86::AND64ri32, X86::MOV64rm, 7782 X86::LCMPXCHG64, X86::MOV64rr, 7783 X86::NOT64r, X86::RAX, 7784 X86::GR64RegisterClass, true); 7785 case X86::ATOMMIN64: 7786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 7787 case X86::ATOMMAX64: 7788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 7789 case X86::ATOMUMIN64: 7790 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 7791 case X86::ATOMUMAX64: 7792 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 7793 7794 // This group does 64-bit operations on a 32-bit host. 7795 case X86::ATOMAND6432: 7796 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7797 X86::AND32rr, X86::AND32rr, 7798 X86::AND32ri, X86::AND32ri, 7799 false); 7800 case X86::ATOMOR6432: 7801 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7802 X86::OR32rr, X86::OR32rr, 7803 X86::OR32ri, X86::OR32ri, 7804 false); 7805 case X86::ATOMXOR6432: 7806 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7807 X86::XOR32rr, X86::XOR32rr, 7808 X86::XOR32ri, X86::XOR32ri, 7809 false); 7810 case X86::ATOMNAND6432: 7811 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7812 X86::AND32rr, X86::AND32rr, 7813 X86::AND32ri, X86::AND32ri, 7814 true); 7815 case X86::ATOMADD6432: 7816 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7817 X86::ADD32rr, X86::ADC32rr, 7818 X86::ADD32ri, X86::ADC32ri, 7819 false); 7820 case X86::ATOMSUB6432: 7821 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7822 X86::SUB32rr, X86::SBB32rr, 7823 X86::SUB32ri, X86::SBB32ri, 7824 false); 7825 case X86::ATOMSWAP6432: 7826 return EmitAtomicBit6432WithCustomInserter(MI, BB, 7827 X86::MOV32rr, X86::MOV32rr, 7828 X86::MOV32ri, X86::MOV32ri, 7829 false); 7830 } 7831} 7832 7833//===----------------------------------------------------------------------===// 7834// X86 Optimization Hooks 7835//===----------------------------------------------------------------------===// 7836 7837void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 7838 const APInt &Mask, 7839 APInt &KnownZero, 7840 APInt &KnownOne, 7841 const SelectionDAG &DAG, 7842 unsigned Depth) const { 7843 unsigned Opc = Op.getOpcode(); 7844 assert((Opc >= ISD::BUILTIN_OP_END || 7845 Opc == ISD::INTRINSIC_WO_CHAIN || 7846 Opc == ISD::INTRINSIC_W_CHAIN || 7847 Opc == ISD::INTRINSIC_VOID) && 7848 "Should use MaskedValueIsZero if you don't know whether Op" 7849 " is a target node!"); 7850 7851 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 7852 switch (Opc) { 7853 default: break; 7854 case X86ISD::ADD: 7855 case X86ISD::SUB: 7856 case X86ISD::SMUL: 7857 case X86ISD::UMUL: 7858 case X86ISD::INC: 7859 case X86ISD::DEC: 7860 // These nodes' second result is a boolean. 7861 if (Op.getResNo() == 0) 7862 break; 7863 // Fallthrough 7864 case X86ISD::SETCC: 7865 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 7866 Mask.getBitWidth() - 1); 7867 break; 7868 } 7869} 7870 7871/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 7872/// node is a GlobalAddress + offset. 7873bool X86TargetLowering::isGAPlusOffset(SDNode *N, 7874 GlobalValue* &GA, int64_t &Offset) const{ 7875 if (N->getOpcode() == X86ISD::Wrapper) { 7876 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 7877 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 7878 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 7879 return true; 7880 } 7881 } 7882 return TargetLowering::isGAPlusOffset(N, GA, Offset); 7883} 7884 7885static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 7886 const TargetLowering &TLI) { 7887 GlobalValue *GV; 7888 int64_t Offset = 0; 7889 if (TLI.isGAPlusOffset(Base, GV, Offset)) 7890 return (GV->getAlignment() >= N && (Offset % N) == 0); 7891 // DAG combine handles the stack object case. 7892 return false; 7893} 7894 7895static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, 7896 MVT EVT, LoadSDNode *&LDBase, 7897 unsigned &LastLoadedElt, 7898 SelectionDAG &DAG, MachineFrameInfo *MFI, 7899 const TargetLowering &TLI) { 7900 LDBase = NULL; 7901 LastLoadedElt = -1U; 7902 for (unsigned i = 0; i < NumElems; ++i) { 7903 if (N->getMaskElt(i) < 0) { 7904 if (!LDBase) 7905 return false; 7906 continue; 7907 } 7908 7909 SDValue Elt = DAG.getShuffleScalarElt(N, i); 7910 if (!Elt.getNode() || 7911 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 7912 return false; 7913 if (!LDBase) { 7914 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 7915 return false; 7916 LDBase = cast<LoadSDNode>(Elt.getNode()); 7917 LastLoadedElt = i; 7918 continue; 7919 } 7920 if (Elt.getOpcode() == ISD::UNDEF) 7921 continue; 7922 7923 LoadSDNode *LD = cast<LoadSDNode>(Elt); 7924 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI)) 7925 return false; 7926 LastLoadedElt = i; 7927 } 7928 return true; 7929} 7930 7931/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 7932/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 7933/// if the load addresses are consecutive, non-overlapping, and in the right 7934/// order. In the case of v2i64, it will see if it can rewrite the 7935/// shuffle to be an appropriate build vector so it can take advantage of 7936// performBuildVectorCombine. 7937static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 7938 const TargetLowering &TLI) { 7939 DebugLoc dl = N->getDebugLoc(); 7940 MVT VT = N->getValueType(0); 7941 MVT EVT = VT.getVectorElementType(); 7942 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7943 unsigned NumElems = VT.getVectorNumElements(); 7944 7945 if (VT.getSizeInBits() != 128) 7946 return SDValue(); 7947 7948 // Try to combine a vector_shuffle into a 128-bit load. 7949 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7950 LoadSDNode *LD = NULL; 7951 unsigned LastLoadedElt; 7952 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG, 7953 MFI, TLI)) 7954 return SDValue(); 7955 7956 if (LastLoadedElt == NumElems - 1) { 7957 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI)) 7958 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 7959 LD->getSrcValue(), LD->getSrcValueOffset(), 7960 LD->isVolatile()); 7961 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 7962 LD->getSrcValue(), LD->getSrcValueOffset(), 7963 LD->isVolatile(), LD->getAlignment()); 7964 } else if (NumElems == 4 && LastLoadedElt == 1) { 7965 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 7966 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 7967 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 7968 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 7969 } 7970 return SDValue(); 7971} 7972 7973/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 7974static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 7975 const X86Subtarget *Subtarget) { 7976 DebugLoc DL = N->getDebugLoc(); 7977 SDValue Cond = N->getOperand(0); 7978 // Get the LHS/RHS of the select. 7979 SDValue LHS = N->getOperand(1); 7980 SDValue RHS = N->getOperand(2); 7981 7982 // If we have SSE[12] support, try to form min/max nodes. 7983 if (Subtarget->hasSSE2() && 7984 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 7985 Cond.getOpcode() == ISD::SETCC) { 7986 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 7987 7988 unsigned Opcode = 0; 7989 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 7990 switch (CC) { 7991 default: break; 7992 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 7993 case ISD::SETULE: 7994 case ISD::SETLE: 7995 if (!UnsafeFPMath) break; 7996 // FALL THROUGH. 7997 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 7998 case ISD::SETLT: 7999 Opcode = X86ISD::FMIN; 8000 break; 8001 8002 case ISD::SETOGT: // (X > Y) ? X : Y -> max 8003 case ISD::SETUGT: 8004 case ISD::SETGT: 8005 if (!UnsafeFPMath) break; 8006 // FALL THROUGH. 8007 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 8008 case ISD::SETGE: 8009 Opcode = X86ISD::FMAX; 8010 break; 8011 } 8012 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 8013 switch (CC) { 8014 default: break; 8015 case ISD::SETOGT: // (X > Y) ? Y : X -> min 8016 case ISD::SETUGT: 8017 case ISD::SETGT: 8018 if (!UnsafeFPMath) break; 8019 // FALL THROUGH. 8020 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 8021 case ISD::SETGE: 8022 Opcode = X86ISD::FMIN; 8023 break; 8024 8025 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 8026 case ISD::SETULE: 8027 case ISD::SETLE: 8028 if (!UnsafeFPMath) break; 8029 // FALL THROUGH. 8030 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 8031 case ISD::SETLT: 8032 Opcode = X86ISD::FMAX; 8033 break; 8034 } 8035 } 8036 8037 if (Opcode) 8038 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 8039 } 8040 8041 // If this is a select between two integer constants, try to do some 8042 // optimizations. 8043 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 8044 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 8045 // Don't do this for crazy integer types. 8046 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 8047 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 8048 // so that TrueC (the true value) is larger than FalseC. 8049 bool NeedsCondInvert = false; 8050 8051 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 8052 // Efficiently invertible. 8053 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 8054 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 8055 isa<ConstantSDNode>(Cond.getOperand(1))))) { 8056 NeedsCondInvert = true; 8057 std::swap(TrueC, FalseC); 8058 } 8059 8060 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 8061 if (FalseC->getAPIntValue() == 0 && 8062 TrueC->getAPIntValue().isPowerOf2()) { 8063 if (NeedsCondInvert) // Invert the condition if needed. 8064 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8065 DAG.getConstant(1, Cond.getValueType())); 8066 8067 // Zero extend the condition if needed. 8068 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 8069 8070 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8071 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 8072 DAG.getConstant(ShAmt, MVT::i8)); 8073 } 8074 8075 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 8076 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8077 if (NeedsCondInvert) // Invert the condition if needed. 8078 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8079 DAG.getConstant(1, Cond.getValueType())); 8080 8081 // Zero extend the condition if needed. 8082 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8083 FalseC->getValueType(0), Cond); 8084 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8085 SDValue(FalseC, 0)); 8086 } 8087 8088 // Optimize cases that will turn into an LEA instruction. This requires 8089 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 8090 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 8091 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 8092 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 8093 8094 bool isFastMultiplier = false; 8095 if (Diff < 10) { 8096 switch ((unsigned char)Diff) { 8097 default: break; 8098 case 1: // result = add base, cond 8099 case 2: // result = lea base( , cond*2) 8100 case 3: // result = lea base(cond, cond*2) 8101 case 4: // result = lea base( , cond*4) 8102 case 5: // result = lea base(cond, cond*4) 8103 case 8: // result = lea base( , cond*8) 8104 case 9: // result = lea base(cond, cond*8) 8105 isFastMultiplier = true; 8106 break; 8107 } 8108 } 8109 8110 if (isFastMultiplier) { 8111 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 8112 if (NeedsCondInvert) // Invert the condition if needed. 8113 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8114 DAG.getConstant(1, Cond.getValueType())); 8115 8116 // Zero extend the condition if needed. 8117 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 8118 Cond); 8119 // Scale the condition by the difference. 8120 if (Diff != 1) 8121 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 8122 DAG.getConstant(Diff, Cond.getValueType())); 8123 8124 // Add the base if non-zero. 8125 if (FalseC->getAPIntValue() != 0) 8126 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8127 SDValue(FalseC, 0)); 8128 return Cond; 8129 } 8130 } 8131 } 8132 } 8133 8134 return SDValue(); 8135} 8136 8137/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 8138static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 8139 TargetLowering::DAGCombinerInfo &DCI) { 8140 DebugLoc DL = N->getDebugLoc(); 8141 8142 // If the flag operand isn't dead, don't touch this CMOV. 8143 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 8144 return SDValue(); 8145 8146 // If this is a select between two integer constants, try to do some 8147 // optimizations. Note that the operands are ordered the opposite of SELECT 8148 // operands. 8149 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 8150 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 8151 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 8152 // larger than FalseC (the false value). 8153 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 8154 8155 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 8156 CC = X86::GetOppositeBranchCondition(CC); 8157 std::swap(TrueC, FalseC); 8158 } 8159 8160 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 8161 // This is efficient for any integer data type (including i8/i16) and 8162 // shift amount. 8163 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 8164 SDValue Cond = N->getOperand(3); 8165 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8166 DAG.getConstant(CC, MVT::i8), Cond); 8167 8168 // Zero extend the condition if needed. 8169 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 8170 8171 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8172 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 8173 DAG.getConstant(ShAmt, MVT::i8)); 8174 if (N->getNumValues() == 2) // Dead flag value? 8175 return DCI.CombineTo(N, Cond, SDValue()); 8176 return Cond; 8177 } 8178 8179 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 8180 // for any integer data type, including i8/i16. 8181 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8182 SDValue Cond = N->getOperand(3); 8183 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8184 DAG.getConstant(CC, MVT::i8), Cond); 8185 8186 // Zero extend the condition if needed. 8187 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8188 FalseC->getValueType(0), Cond); 8189 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8190 SDValue(FalseC, 0)); 8191 8192 if (N->getNumValues() == 2) // Dead flag value? 8193 return DCI.CombineTo(N, Cond, SDValue()); 8194 return Cond; 8195 } 8196 8197 // Optimize cases that will turn into an LEA instruction. This requires 8198 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 8199 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 8200 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 8201 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 8202 8203 bool isFastMultiplier = false; 8204 if (Diff < 10) { 8205 switch ((unsigned char)Diff) { 8206 default: break; 8207 case 1: // result = add base, cond 8208 case 2: // result = lea base( , cond*2) 8209 case 3: // result = lea base(cond, cond*2) 8210 case 4: // result = lea base( , cond*4) 8211 case 5: // result = lea base(cond, cond*4) 8212 case 8: // result = lea base( , cond*8) 8213 case 9: // result = lea base(cond, cond*8) 8214 isFastMultiplier = true; 8215 break; 8216 } 8217 } 8218 8219 if (isFastMultiplier) { 8220 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 8221 SDValue Cond = N->getOperand(3); 8222 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8223 DAG.getConstant(CC, MVT::i8), Cond); 8224 // Zero extend the condition if needed. 8225 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 8226 Cond); 8227 // Scale the condition by the difference. 8228 if (Diff != 1) 8229 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 8230 DAG.getConstant(Diff, Cond.getValueType())); 8231 8232 // Add the base if non-zero. 8233 if (FalseC->getAPIntValue() != 0) 8234 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8235 SDValue(FalseC, 0)); 8236 if (N->getNumValues() == 2) // Dead flag value? 8237 return DCI.CombineTo(N, Cond, SDValue()); 8238 return Cond; 8239 } 8240 } 8241 } 8242 } 8243 return SDValue(); 8244} 8245 8246 8247/// PerformMulCombine - Optimize a single multiply with constant into two 8248/// in order to implement it with two cheaper instructions, e.g. 8249/// LEA + SHL, LEA + LEA. 8250static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 8251 TargetLowering::DAGCombinerInfo &DCI) { 8252 if (DAG.getMachineFunction(). 8253 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 8254 return SDValue(); 8255 8256 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 8257 return SDValue(); 8258 8259 MVT VT = N->getValueType(0); 8260 if (VT != MVT::i64) 8261 return SDValue(); 8262 8263 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8264 if (!C) 8265 return SDValue(); 8266 uint64_t MulAmt = C->getZExtValue(); 8267 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 8268 return SDValue(); 8269 8270 uint64_t MulAmt1 = 0; 8271 uint64_t MulAmt2 = 0; 8272 if ((MulAmt % 9) == 0) { 8273 MulAmt1 = 9; 8274 MulAmt2 = MulAmt / 9; 8275 } else if ((MulAmt % 5) == 0) { 8276 MulAmt1 = 5; 8277 MulAmt2 = MulAmt / 5; 8278 } else if ((MulAmt % 3) == 0) { 8279 MulAmt1 = 3; 8280 MulAmt2 = MulAmt / 3; 8281 } 8282 if (MulAmt2 && 8283 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 8284 DebugLoc DL = N->getDebugLoc(); 8285 8286 if (isPowerOf2_64(MulAmt2) && 8287 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 8288 // If second multiplifer is pow2, issue it first. We want the multiply by 8289 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 8290 // is an add. 8291 std::swap(MulAmt1, MulAmt2); 8292 8293 SDValue NewMul; 8294 if (isPowerOf2_64(MulAmt1)) 8295 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 8296 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 8297 else 8298 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 8299 DAG.getConstant(MulAmt1, VT)); 8300 8301 if (isPowerOf2_64(MulAmt2)) 8302 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 8303 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 8304 else 8305 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 8306 DAG.getConstant(MulAmt2, VT)); 8307 8308 // Do not add new nodes to DAG combiner worklist. 8309 DCI.CombineTo(N, NewMul, false); 8310 } 8311 return SDValue(); 8312} 8313 8314 8315/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 8316/// when possible. 8317static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 8318 const X86Subtarget *Subtarget) { 8319 // On X86 with SSE2 support, we can transform this to a vector shift if 8320 // all elements are shifted by the same amount. We can't do this in legalize 8321 // because the a constant vector is typically transformed to a constant pool 8322 // so we have no knowledge of the shift amount. 8323 if (!Subtarget->hasSSE2()) 8324 return SDValue(); 8325 8326 MVT VT = N->getValueType(0); 8327 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 8328 return SDValue(); 8329 8330 SDValue ShAmtOp = N->getOperand(1); 8331 MVT EltVT = VT.getVectorElementType(); 8332 DebugLoc DL = N->getDebugLoc(); 8333 SDValue BaseShAmt; 8334 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 8335 unsigned NumElts = VT.getVectorNumElements(); 8336 unsigned i = 0; 8337 for (; i != NumElts; ++i) { 8338 SDValue Arg = ShAmtOp.getOperand(i); 8339 if (Arg.getOpcode() == ISD::UNDEF) continue; 8340 BaseShAmt = Arg; 8341 break; 8342 } 8343 for (; i != NumElts; ++i) { 8344 SDValue Arg = ShAmtOp.getOperand(i); 8345 if (Arg.getOpcode() == ISD::UNDEF) continue; 8346 if (Arg != BaseShAmt) { 8347 return SDValue(); 8348 } 8349 } 8350 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 8351 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 8352 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 8353 DAG.getIntPtrConstant(0)); 8354 } else 8355 return SDValue(); 8356 8357 if (EltVT.bitsGT(MVT::i32)) 8358 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 8359 else if (EltVT.bitsLT(MVT::i32)) 8360 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt); 8361 8362 // The shift amount is identical so we can do a vector shift. 8363 SDValue ValOp = N->getOperand(0); 8364 switch (N->getOpcode()) { 8365 default: 8366 assert(0 && "Unknown shift opcode!"); 8367 break; 8368 case ISD::SHL: 8369 if (VT == MVT::v2i64) 8370 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8371 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8372 ValOp, BaseShAmt); 8373 if (VT == MVT::v4i32) 8374 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8375 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 8376 ValOp, BaseShAmt); 8377 if (VT == MVT::v8i16) 8378 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8379 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 8380 ValOp, BaseShAmt); 8381 break; 8382 case ISD::SRA: 8383 if (VT == MVT::v4i32) 8384 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8385 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 8386 ValOp, BaseShAmt); 8387 if (VT == MVT::v8i16) 8388 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8389 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 8390 ValOp, BaseShAmt); 8391 break; 8392 case ISD::SRL: 8393 if (VT == MVT::v2i64) 8394 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8395 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8396 ValOp, BaseShAmt); 8397 if (VT == MVT::v4i32) 8398 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8399 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 8400 ValOp, BaseShAmt); 8401 if (VT == MVT::v8i16) 8402 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8403 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 8404 ValOp, BaseShAmt); 8405 break; 8406 } 8407 return SDValue(); 8408} 8409 8410/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 8411static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 8412 const X86Subtarget *Subtarget) { 8413 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 8414 // the FP state in cases where an emms may be missing. 8415 // A preferable solution to the general problem is to figure out the right 8416 // places to insert EMMS. This qualifies as a quick hack. 8417 8418 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 8419 StoreSDNode *St = cast<StoreSDNode>(N); 8420 MVT VT = St->getValue().getValueType(); 8421 if (VT.getSizeInBits() != 64) 8422 return SDValue(); 8423 8424 const Function *F = DAG.getMachineFunction().getFunction(); 8425 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 8426 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 8427 && Subtarget->hasSSE2(); 8428 if ((VT.isVector() || 8429 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 8430 isa<LoadSDNode>(St->getValue()) && 8431 !cast<LoadSDNode>(St->getValue())->isVolatile() && 8432 St->getChain().hasOneUse() && !St->isVolatile()) { 8433 SDNode* LdVal = St->getValue().getNode(); 8434 LoadSDNode *Ld = 0; 8435 int TokenFactorIndex = -1; 8436 SmallVector<SDValue, 8> Ops; 8437 SDNode* ChainVal = St->getChain().getNode(); 8438 // Must be a store of a load. We currently handle two cases: the load 8439 // is a direct child, and it's under an intervening TokenFactor. It is 8440 // possible to dig deeper under nested TokenFactors. 8441 if (ChainVal == LdVal) 8442 Ld = cast<LoadSDNode>(St->getChain()); 8443 else if (St->getValue().hasOneUse() && 8444 ChainVal->getOpcode() == ISD::TokenFactor) { 8445 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 8446 if (ChainVal->getOperand(i).getNode() == LdVal) { 8447 TokenFactorIndex = i; 8448 Ld = cast<LoadSDNode>(St->getValue()); 8449 } else 8450 Ops.push_back(ChainVal->getOperand(i)); 8451 } 8452 } 8453 8454 if (!Ld || !ISD::isNormalLoad(Ld)) 8455 return SDValue(); 8456 8457 // If this is not the MMX case, i.e. we are just turning i64 load/store 8458 // into f64 load/store, avoid the transformation if there are multiple 8459 // uses of the loaded value. 8460 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 8461 return SDValue(); 8462 8463 DebugLoc LdDL = Ld->getDebugLoc(); 8464 DebugLoc StDL = N->getDebugLoc(); 8465 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 8466 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 8467 // pair instead. 8468 if (Subtarget->is64Bit() || F64IsLegal) { 8469 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 8470 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 8471 Ld->getBasePtr(), Ld->getSrcValue(), 8472 Ld->getSrcValueOffset(), Ld->isVolatile(), 8473 Ld->getAlignment()); 8474 SDValue NewChain = NewLd.getValue(1); 8475 if (TokenFactorIndex != -1) { 8476 Ops.push_back(NewChain); 8477 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 8478 Ops.size()); 8479 } 8480 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 8481 St->getSrcValue(), St->getSrcValueOffset(), 8482 St->isVolatile(), St->getAlignment()); 8483 } 8484 8485 // Otherwise, lower to two pairs of 32-bit loads / stores. 8486 SDValue LoAddr = Ld->getBasePtr(); 8487 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 8488 DAG.getConstant(4, MVT::i32)); 8489 8490 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 8491 Ld->getSrcValue(), Ld->getSrcValueOffset(), 8492 Ld->isVolatile(), Ld->getAlignment()); 8493 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 8494 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 8495 Ld->isVolatile(), 8496 MinAlign(Ld->getAlignment(), 4)); 8497 8498 SDValue NewChain = LoLd.getValue(1); 8499 if (TokenFactorIndex != -1) { 8500 Ops.push_back(LoLd); 8501 Ops.push_back(HiLd); 8502 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 8503 Ops.size()); 8504 } 8505 8506 LoAddr = St->getBasePtr(); 8507 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 8508 DAG.getConstant(4, MVT::i32)); 8509 8510 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 8511 St->getSrcValue(), St->getSrcValueOffset(), 8512 St->isVolatile(), St->getAlignment()); 8513 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 8514 St->getSrcValue(), 8515 St->getSrcValueOffset() + 4, 8516 St->isVolatile(), 8517 MinAlign(St->getAlignment(), 4)); 8518 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 8519 } 8520 return SDValue(); 8521} 8522 8523/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 8524/// X86ISD::FXOR nodes. 8525static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 8526 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 8527 // F[X]OR(0.0, x) -> x 8528 // F[X]OR(x, 0.0) -> x 8529 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8530 if (C->getValueAPF().isPosZero()) 8531 return N->getOperand(1); 8532 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8533 if (C->getValueAPF().isPosZero()) 8534 return N->getOperand(0); 8535 return SDValue(); 8536} 8537 8538/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 8539static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 8540 // FAND(0.0, x) -> 0.0 8541 // FAND(x, 0.0) -> 0.0 8542 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8543 if (C->getValueAPF().isPosZero()) 8544 return N->getOperand(0); 8545 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8546 if (C->getValueAPF().isPosZero()) 8547 return N->getOperand(1); 8548 return SDValue(); 8549} 8550 8551static SDValue PerformBTCombine(SDNode *N, 8552 SelectionDAG &DAG, 8553 TargetLowering::DAGCombinerInfo &DCI) { 8554 // BT ignores high bits in the bit index operand. 8555 SDValue Op1 = N->getOperand(1); 8556 if (Op1.hasOneUse()) { 8557 unsigned BitWidth = Op1.getValueSizeInBits(); 8558 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 8559 APInt KnownZero, KnownOne; 8560 TargetLowering::TargetLoweringOpt TLO(DAG); 8561 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8562 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 8563 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 8564 DCI.CommitTargetLoweringOpt(TLO); 8565 } 8566 return SDValue(); 8567} 8568 8569static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 8570 SDValue Op = N->getOperand(0); 8571 if (Op.getOpcode() == ISD::BIT_CONVERT) 8572 Op = Op.getOperand(0); 8573 MVT VT = N->getValueType(0), OpVT = Op.getValueType(); 8574 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 8575 VT.getVectorElementType().getSizeInBits() == 8576 OpVT.getVectorElementType().getSizeInBits()) { 8577 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 8578 } 8579 return SDValue(); 8580} 8581 8582// On X86 and X86-64, atomic operations are lowered to locked instructions. 8583// Locked instructions, in turn, have implicit fence semantics (all memory 8584// operations are flushed before issuing the locked instruction, and the 8585// are not buffered), so we can fold away the common pattern of 8586// fence-atomic-fence. 8587static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 8588 SDValue atomic = N->getOperand(0); 8589 switch (atomic.getOpcode()) { 8590 case ISD::ATOMIC_CMP_SWAP: 8591 case ISD::ATOMIC_SWAP: 8592 case ISD::ATOMIC_LOAD_ADD: 8593 case ISD::ATOMIC_LOAD_SUB: 8594 case ISD::ATOMIC_LOAD_AND: 8595 case ISD::ATOMIC_LOAD_OR: 8596 case ISD::ATOMIC_LOAD_XOR: 8597 case ISD::ATOMIC_LOAD_NAND: 8598 case ISD::ATOMIC_LOAD_MIN: 8599 case ISD::ATOMIC_LOAD_MAX: 8600 case ISD::ATOMIC_LOAD_UMIN: 8601 case ISD::ATOMIC_LOAD_UMAX: 8602 break; 8603 default: 8604 return SDValue(); 8605 } 8606 8607 SDValue fence = atomic.getOperand(0); 8608 if (fence.getOpcode() != ISD::MEMBARRIER) 8609 return SDValue(); 8610 8611 switch (atomic.getOpcode()) { 8612 case ISD::ATOMIC_CMP_SWAP: 8613 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 8614 atomic.getOperand(1), atomic.getOperand(2), 8615 atomic.getOperand(3)); 8616 case ISD::ATOMIC_SWAP: 8617 case ISD::ATOMIC_LOAD_ADD: 8618 case ISD::ATOMIC_LOAD_SUB: 8619 case ISD::ATOMIC_LOAD_AND: 8620 case ISD::ATOMIC_LOAD_OR: 8621 case ISD::ATOMIC_LOAD_XOR: 8622 case ISD::ATOMIC_LOAD_NAND: 8623 case ISD::ATOMIC_LOAD_MIN: 8624 case ISD::ATOMIC_LOAD_MAX: 8625 case ISD::ATOMIC_LOAD_UMIN: 8626 case ISD::ATOMIC_LOAD_UMAX: 8627 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 8628 atomic.getOperand(1), atomic.getOperand(2)); 8629 default: 8630 return SDValue(); 8631 } 8632} 8633 8634SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 8635 DAGCombinerInfo &DCI) const { 8636 SelectionDAG &DAG = DCI.DAG; 8637 switch (N->getOpcode()) { 8638 default: break; 8639 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 8640 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 8641 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 8642 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 8643 case ISD::SHL: 8644 case ISD::SRA: 8645 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 8646 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 8647 case X86ISD::FXOR: 8648 case X86ISD::FOR: return PerformFORCombine(N, DAG); 8649 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 8650 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 8651 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 8652 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 8653 } 8654 8655 return SDValue(); 8656} 8657 8658//===----------------------------------------------------------------------===// 8659// X86 Inline Assembly Support 8660//===----------------------------------------------------------------------===// 8661 8662/// getConstraintType - Given a constraint letter, return the type of 8663/// constraint it is for this target. 8664X86TargetLowering::ConstraintType 8665X86TargetLowering::getConstraintType(const std::string &Constraint) const { 8666 if (Constraint.size() == 1) { 8667 switch (Constraint[0]) { 8668 case 'A': 8669 return C_Register; 8670 case 'f': 8671 case 'r': 8672 case 'R': 8673 case 'l': 8674 case 'q': 8675 case 'Q': 8676 case 'x': 8677 case 'y': 8678 case 'Y': 8679 return C_RegisterClass; 8680 case 'e': 8681 case 'Z': 8682 return C_Other; 8683 default: 8684 break; 8685 } 8686 } 8687 return TargetLowering::getConstraintType(Constraint); 8688} 8689 8690/// LowerXConstraint - try to replace an X constraint, which matches anything, 8691/// with another that has more specific requirements based on the type of the 8692/// corresponding operand. 8693const char *X86TargetLowering:: 8694LowerXConstraint(MVT ConstraintVT) const { 8695 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 8696 // 'f' like normal targets. 8697 if (ConstraintVT.isFloatingPoint()) { 8698 if (Subtarget->hasSSE2()) 8699 return "Y"; 8700 if (Subtarget->hasSSE1()) 8701 return "x"; 8702 } 8703 8704 return TargetLowering::LowerXConstraint(ConstraintVT); 8705} 8706 8707/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8708/// vector. If it is invalid, don't add anything to Ops. 8709void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8710 char Constraint, 8711 bool hasMemory, 8712 std::vector<SDValue>&Ops, 8713 SelectionDAG &DAG) const { 8714 SDValue Result(0, 0); 8715 8716 switch (Constraint) { 8717 default: break; 8718 case 'I': 8719 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8720 if (C->getZExtValue() <= 31) { 8721 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8722 break; 8723 } 8724 } 8725 return; 8726 case 'J': 8727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8728 if (C->getZExtValue() <= 63) { 8729 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8730 break; 8731 } 8732 } 8733 return; 8734 case 'K': 8735 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8736 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 8737 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8738 break; 8739 } 8740 } 8741 return; 8742 case 'N': 8743 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8744 if (C->getZExtValue() <= 255) { 8745 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8746 break; 8747 } 8748 } 8749 return; 8750 case 'e': { 8751 // 32-bit signed value 8752 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8753 const ConstantInt *CI = C->getConstantIntValue(); 8754 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) { 8755 // Widen to 64 bits here to get it sign extended. 8756 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 8757 break; 8758 } 8759 // FIXME gcc accepts some relocatable values here too, but only in certain 8760 // memory models; it's complicated. 8761 } 8762 return; 8763 } 8764 case 'Z': { 8765 // 32-bit unsigned value 8766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 8767 const ConstantInt *CI = C->getConstantIntValue(); 8768 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) { 8769 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 8770 break; 8771 } 8772 } 8773 // FIXME gcc accepts some relocatable values here too, but only in certain 8774 // memory models; it's complicated. 8775 return; 8776 } 8777 case 'i': { 8778 // Literal immediates are always ok. 8779 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 8780 // Widen to 64 bits here to get it sign extended. 8781 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 8782 break; 8783 } 8784 8785 // If we are in non-pic codegen mode, we allow the address of a global (with 8786 // an optional displacement) to be used with 'i'. 8787 GlobalAddressSDNode *GA = 0; 8788 int64_t Offset = 0; 8789 8790 // Match either (GA), (GA+C), (GA+C1+C2), etc. 8791 while (1) { 8792 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 8793 Offset += GA->getOffset(); 8794 break; 8795 } else if (Op.getOpcode() == ISD::ADD) { 8796 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 8797 Offset += C->getZExtValue(); 8798 Op = Op.getOperand(0); 8799 continue; 8800 } 8801 } else if (Op.getOpcode() == ISD::SUB) { 8802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 8803 Offset += -C->getZExtValue(); 8804 Op = Op.getOperand(0); 8805 continue; 8806 } 8807 } 8808 8809 // Otherwise, this isn't something we can handle, reject it. 8810 return; 8811 } 8812 // If we require an extra load to get this address, as in PIC mode, we 8813 // can't accept it. 8814 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), 8815 getTargetMachine(), false)) 8816 return; 8817 8818 if (hasMemory) 8819 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(), Offset, DAG); 8820 else 8821 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 8822 Offset); 8823 Result = Op; 8824 break; 8825 } 8826 } 8827 8828 if (Result.getNode()) { 8829 Ops.push_back(Result); 8830 return; 8831 } 8832 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 8833 Ops, DAG); 8834} 8835 8836std::vector<unsigned> X86TargetLowering:: 8837getRegClassForInlineAsmConstraint(const std::string &Constraint, 8838 MVT VT) const { 8839 if (Constraint.size() == 1) { 8840 // FIXME: not handling fp-stack yet! 8841 switch (Constraint[0]) { // GCC X86 Constraint Letters 8842 default: break; // Unknown constraint letter 8843 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 8844 case 'Q': // Q_REGS 8845 if (VT == MVT::i32) 8846 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 8847 else if (VT == MVT::i16) 8848 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 8849 else if (VT == MVT::i8) 8850 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 8851 else if (VT == MVT::i64) 8852 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 8853 break; 8854 } 8855 } 8856 8857 return std::vector<unsigned>(); 8858} 8859 8860std::pair<unsigned, const TargetRegisterClass*> 8861X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8862 MVT VT) const { 8863 // First, see if this is a constraint that directly corresponds to an LLVM 8864 // register class. 8865 if (Constraint.size() == 1) { 8866 // GCC Constraint Letters 8867 switch (Constraint[0]) { 8868 default: break; 8869 case 'r': // GENERAL_REGS 8870 case 'R': // LEGACY_REGS 8871 case 'l': // INDEX_REGS 8872 if (VT == MVT::i8) 8873 return std::make_pair(0U, X86::GR8RegisterClass); 8874 if (VT == MVT::i16) 8875 return std::make_pair(0U, X86::GR16RegisterClass); 8876 if (VT == MVT::i32 || !Subtarget->is64Bit()) 8877 return std::make_pair(0U, X86::GR32RegisterClass); 8878 return std::make_pair(0U, X86::GR64RegisterClass); 8879 case 'f': // FP Stack registers. 8880 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 8881 // value to the correct fpstack register class. 8882 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 8883 return std::make_pair(0U, X86::RFP32RegisterClass); 8884 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 8885 return std::make_pair(0U, X86::RFP64RegisterClass); 8886 return std::make_pair(0U, X86::RFP80RegisterClass); 8887 case 'y': // MMX_REGS if MMX allowed. 8888 if (!Subtarget->hasMMX()) break; 8889 return std::make_pair(0U, X86::VR64RegisterClass); 8890 case 'Y': // SSE_REGS if SSE2 allowed 8891 if (!Subtarget->hasSSE2()) break; 8892 // FALL THROUGH. 8893 case 'x': // SSE_REGS if SSE1 allowed 8894 if (!Subtarget->hasSSE1()) break; 8895 8896 switch (VT.getSimpleVT()) { 8897 default: break; 8898 // Scalar SSE types. 8899 case MVT::f32: 8900 case MVT::i32: 8901 return std::make_pair(0U, X86::FR32RegisterClass); 8902 case MVT::f64: 8903 case MVT::i64: 8904 return std::make_pair(0U, X86::FR64RegisterClass); 8905 // Vector types. 8906 case MVT::v16i8: 8907 case MVT::v8i16: 8908 case MVT::v4i32: 8909 case MVT::v2i64: 8910 case MVT::v4f32: 8911 case MVT::v2f64: 8912 return std::make_pair(0U, X86::VR128RegisterClass); 8913 } 8914 break; 8915 } 8916 } 8917 8918 // Use the default implementation in TargetLowering to convert the register 8919 // constraint into a member of a register class. 8920 std::pair<unsigned, const TargetRegisterClass*> Res; 8921 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8922 8923 // Not found as a standard register? 8924 if (Res.second == 0) { 8925 // GCC calls "st(0)" just plain "st". 8926 if (StringsEqualNoCase("{st}", Constraint)) { 8927 Res.first = X86::ST0; 8928 Res.second = X86::RFP80RegisterClass; 8929 } 8930 // 'A' means EAX + EDX. 8931 if (Constraint == "A") { 8932 Res.first = X86::EAX; 8933 Res.second = X86::GRADRegisterClass; 8934 } 8935 return Res; 8936 } 8937 8938 // Otherwise, check to see if this is a register class of the wrong value 8939 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 8940 // turn into {ax},{dx}. 8941 if (Res.second->hasType(VT)) 8942 return Res; // Correct type already, nothing to do. 8943 8944 // All of the single-register GCC register classes map their values onto 8945 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 8946 // really want an 8-bit or 32-bit register, map to the appropriate register 8947 // class and return the appropriate register. 8948 if (Res.second == X86::GR16RegisterClass) { 8949 if (VT == MVT::i8) { 8950 unsigned DestReg = 0; 8951 switch (Res.first) { 8952 default: break; 8953 case X86::AX: DestReg = X86::AL; break; 8954 case X86::DX: DestReg = X86::DL; break; 8955 case X86::CX: DestReg = X86::CL; break; 8956 case X86::BX: DestReg = X86::BL; break; 8957 } 8958 if (DestReg) { 8959 Res.first = DestReg; 8960 Res.second = X86::GR8RegisterClass; 8961 } 8962 } else if (VT == MVT::i32) { 8963 unsigned DestReg = 0; 8964 switch (Res.first) { 8965 default: break; 8966 case X86::AX: DestReg = X86::EAX; break; 8967 case X86::DX: DestReg = X86::EDX; break; 8968 case X86::CX: DestReg = X86::ECX; break; 8969 case X86::BX: DestReg = X86::EBX; break; 8970 case X86::SI: DestReg = X86::ESI; break; 8971 case X86::DI: DestReg = X86::EDI; break; 8972 case X86::BP: DestReg = X86::EBP; break; 8973 case X86::SP: DestReg = X86::ESP; break; 8974 } 8975 if (DestReg) { 8976 Res.first = DestReg; 8977 Res.second = X86::GR32RegisterClass; 8978 } 8979 } else if (VT == MVT::i64) { 8980 unsigned DestReg = 0; 8981 switch (Res.first) { 8982 default: break; 8983 case X86::AX: DestReg = X86::RAX; break; 8984 case X86::DX: DestReg = X86::RDX; break; 8985 case X86::CX: DestReg = X86::RCX; break; 8986 case X86::BX: DestReg = X86::RBX; break; 8987 case X86::SI: DestReg = X86::RSI; break; 8988 case X86::DI: DestReg = X86::RDI; break; 8989 case X86::BP: DestReg = X86::RBP; break; 8990 case X86::SP: DestReg = X86::RSP; break; 8991 } 8992 if (DestReg) { 8993 Res.first = DestReg; 8994 Res.second = X86::GR64RegisterClass; 8995 } 8996 } 8997 } else if (Res.second == X86::FR32RegisterClass || 8998 Res.second == X86::FR64RegisterClass || 8999 Res.second == X86::VR128RegisterClass) { 9000 // Handle references to XMM physical registers that got mapped into the 9001 // wrong class. This can happen with constraints like {xmm0} where the 9002 // target independent register mapper will just pick the first match it can 9003 // find, ignoring the required type. 9004 if (VT == MVT::f32) 9005 Res.second = X86::FR32RegisterClass; 9006 else if (VT == MVT::f64) 9007 Res.second = X86::FR64RegisterClass; 9008 else if (X86::VR128RegisterClass->hasType(VT)) 9009 Res.second = X86::VR128RegisterClass; 9010 } 9011 9012 return Res; 9013} 9014 9015//===----------------------------------------------------------------------===// 9016// X86 Widen vector type 9017//===----------------------------------------------------------------------===// 9018 9019/// getWidenVectorType: given a vector type, returns the type to widen 9020/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 9021/// If there is no vector type that we want to widen to, returns MVT::Other 9022/// When and where to widen is target dependent based on the cost of 9023/// scalarizing vs using the wider vector type. 9024 9025MVT X86TargetLowering::getWidenVectorType(MVT VT) const { 9026 assert(VT.isVector()); 9027 if (isTypeLegal(VT)) 9028 return VT; 9029 9030 // TODO: In computeRegisterProperty, we can compute the list of legal vector 9031 // type based on element type. This would speed up our search (though 9032 // it may not be worth it since the size of the list is relatively 9033 // small). 9034 MVT EltVT = VT.getVectorElementType(); 9035 unsigned NElts = VT.getVectorNumElements(); 9036 9037 // On X86, it make sense to widen any vector wider than 1 9038 if (NElts <= 1) 9039 return MVT::Other; 9040 9041 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 9042 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 9043 MVT SVT = (MVT::SimpleValueType)nVT; 9044 9045 if (isTypeLegal(SVT) && 9046 SVT.getVectorElementType() == EltVT && 9047 SVT.getVectorNumElements() > NElts) 9048 return SVT; 9049 } 9050 return MVT::Other; 9051} 9052