X86ISelLowering.cpp revision 5aaffa84703debaba17650c5ca9eae9a49844cf1
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/Dwarf.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52#include "llvm/Target/TargetOptions.h" 53#include <bitset> 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 64/// sets things up to match to an AVX VEXTRACTF128 instruction or a 65/// simple subregister reference. Idx is an index in the 128 bits we 66/// want. It need not be aligned to a 128-bit bounday. That makes 67/// lowering EXTRACT_VECTOR_ELT operations easier. 68static SDValue Extract128BitVector(SDValue Vec, 69 SDValue Idx, 70 SelectionDAG &DAG, 71 DebugLoc dl) { 72 EVT VT = Vec.getValueType(); 73 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 74 EVT ElVT = VT.getVectorElementType(); 75 int Factor = VT.getSizeInBits()/128; 76 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 77 VT.getVectorNumElements()/Factor); 78 79 // Extract from UNDEF is UNDEF. 80 if (Vec.getOpcode() == ISD::UNDEF) 81 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 82 83 if (isa<ConstantSDNode>(Idx)) { 84 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 85 86 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 87 // we can match to VEXTRACTF128. 88 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 89 90 // This is the index of the first element of the 128-bit chunk 91 // we want. 92 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 93 * ElemsPerChunk); 94 95 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 96 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 97 VecIdx); 98 99 return Result; 100 } 101 102 return SDValue(); 103} 104 105/// Generate a DAG to put 128-bits into a vector > 128 bits. This 106/// sets things up to match to an AVX VINSERTF128 instruction or a 107/// simple superregister reference. Idx is an index in the 128 bits 108/// we want. It need not be aligned to a 128-bit bounday. That makes 109/// lowering INSERT_VECTOR_ELT operations easier. 110static SDValue Insert128BitVector(SDValue Result, 111 SDValue Vec, 112 SDValue Idx, 113 SelectionDAG &DAG, 114 DebugLoc dl) { 115 if (isa<ConstantSDNode>(Idx)) { 116 EVT VT = Vec.getValueType(); 117 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 118 119 EVT ElVT = VT.getVectorElementType(); 120 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 121 EVT ResultVT = Result.getValueType(); 122 123 // Insert the relevant 128 bits. 124 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 125 126 // This is the index of the first element of the 128-bit chunk 127 // we want. 128 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 129 * ElemsPerChunk); 130 131 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 132 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 133 VecIdx); 134 return Result; 135 } 136 137 return SDValue(); 138} 139 140static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 141 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 142 bool is64Bit = Subtarget->is64Bit(); 143 144 if (Subtarget->isTargetEnvMacho()) { 145 if (is64Bit) 146 return new X8664_MachoTargetObjectFile(); 147 return new TargetLoweringObjectFileMachO(); 148 } 149 150 if (Subtarget->isTargetELF()) 151 return new TargetLoweringObjectFileELF(); 152 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 153 return new TargetLoweringObjectFileCOFF(); 154 llvm_unreachable("unknown subtarget type"); 155} 156 157X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 158 : TargetLowering(TM, createTLOF(TM)) { 159 Subtarget = &TM.getSubtarget<X86Subtarget>(); 160 X86ScalarSSEf64 = Subtarget->hasSSE2(); 161 X86ScalarSSEf32 = Subtarget->hasSSE1(); 162 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 163 164 RegInfo = TM.getRegisterInfo(); 165 TD = getTargetData(); 166 167 // Set up the TargetLowering object. 168 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 169 170 // X86 is weird, it always uses i8 for shift amounts and setcc results. 171 setBooleanContents(ZeroOrOneBooleanContent); 172 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 173 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 174 175 // For 64-bit since we have so many registers use the ILP scheduler, for 176 // 32-bit code use the register pressure specific scheduling. 177 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 178 if (Subtarget->is64Bit()) 179 setSchedulingPreference(Sched::ILP); 180 else if (Subtarget->isAtom()) 181 setSchedulingPreference(Sched::Hybrid); 182 else 183 setSchedulingPreference(Sched::RegPressure); 184 setStackPointerRegisterToSaveRestore(X86StackPtr); 185 186 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 187 // Setup Windows compiler runtime calls. 188 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 189 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 190 setLibcallName(RTLIB::SREM_I64, "_allrem"); 191 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 192 setLibcallName(RTLIB::MUL_I64, "_allmul"); 193 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 194 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 200 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 201 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 202 } 203 204 if (Subtarget->isTargetDarwin()) { 205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 206 setUseUnderscoreSetJmp(false); 207 setUseUnderscoreLongJmp(false); 208 } else if (Subtarget->isTargetMingw()) { 209 // MS runtime is weird: it exports _setjmp, but longjmp! 210 setUseUnderscoreSetJmp(true); 211 setUseUnderscoreLongJmp(false); 212 } else { 213 setUseUnderscoreSetJmp(true); 214 setUseUnderscoreLongJmp(true); 215 } 216 217 // Set up the register classes. 218 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 219 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 220 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 221 if (Subtarget->is64Bit()) 222 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 223 224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 225 226 // We don't accept any truncstore of integer registers. 227 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 228 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 230 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 232 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 233 234 // SETOEQ and SETUNE require checking two conditions. 235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 241 242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 243 // operation. 244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 247 248 if (Subtarget->is64Bit()) { 249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 } else if (!TM.Options.UseSoftFloat) { 252 // We have an algorithm for SSE2->double, and we turn this into a 253 // 64-bit FILD followed by conditional FADD for other targets. 254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 255 // We have an algorithm for SSE2, and we turn this into a 64-bit 256 // FILD for other targets. 257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 258 } 259 260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 261 // this operation. 262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 264 265 if (!TM.Options.UseSoftFloat) { 266 // SSE has no i16 to fp conversion, only i32 267 if (X86ScalarSSEf32) { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 269 // f32 and f64 cases are Legal, f80 case is not 270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 274 } 275 } else { 276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 278 } 279 280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 281 // are Legal, f80 is custom lowered. 282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 284 285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 286 // this operation. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 289 290 if (X86ScalarSSEf32) { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 292 // f32 and f64 cases are Legal, f80 case is not 293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 294 } else { 295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 297 } 298 299 // Handle FP_TO_UINT by promoting the destination to a larger signed 300 // conversion. 301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 304 305 if (Subtarget->is64Bit()) { 306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 308 } else if (!TM.Options.UseSoftFloat) { 309 // Since AVX is a superset of SSE3, only check for SSE here. 310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 311 // Expand FP_TO_UINT into a select. 312 // FIXME: We would like to use a Custom expander here eventually to do 313 // the optimal thing for SSE vs. the default expansion in the legalizer. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 315 else 316 // With SSE3 we can use fisttpll to convert to a signed i64; without 317 // SSE, we're stuck with a fistpll. 318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 319 } 320 321 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 322 if (!X86ScalarSSEf64) { 323 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 324 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 325 if (Subtarget->is64Bit()) { 326 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 327 // Without SSE, i64->f64 goes through memory. 328 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 329 } 330 } 331 332 // Scalar integer divide and remainder are lowered to use operations that 333 // produce two results, to match the available instructions. This exposes 334 // the two-result form to trivial CSE, which is able to combine x/y and x%y 335 // into a single instruction. 336 // 337 // Scalar integer multiply-high is also lowered to use two-result 338 // operations, to match the available instructions. However, plain multiply 339 // (low) operations are left as Legal, as there are single-result 340 // instructions for this in x86. Using the two-result multiply instructions 341 // when both high and low results are needed must be arranged by dagcombine. 342 for (unsigned i = 0, e = 4; i != e; ++i) { 343 MVT VT = IntVTs[i]; 344 setOperationAction(ISD::MULHS, VT, Expand); 345 setOperationAction(ISD::MULHU, VT, Expand); 346 setOperationAction(ISD::SDIV, VT, Expand); 347 setOperationAction(ISD::UDIV, VT, Expand); 348 setOperationAction(ISD::SREM, VT, Expand); 349 setOperationAction(ISD::UREM, VT, Expand); 350 351 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 352 setOperationAction(ISD::ADDC, VT, Custom); 353 setOperationAction(ISD::ADDE, VT, Custom); 354 setOperationAction(ISD::SUBC, VT, Custom); 355 setOperationAction(ISD::SUBE, VT, Custom); 356 } 357 358 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 359 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 360 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 361 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 362 if (Subtarget->is64Bit()) 363 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 364 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 367 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 368 setOperationAction(ISD::FREM , MVT::f32 , Expand); 369 setOperationAction(ISD::FREM , MVT::f64 , Expand); 370 setOperationAction(ISD::FREM , MVT::f80 , Expand); 371 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 372 373 // Promote the i8 variants and force them on up to i32 which has a shorter 374 // encoding. 375 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 376 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 377 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 378 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 379 if (Subtarget->hasBMI()) { 380 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 381 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 382 if (Subtarget->is64Bit()) 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 384 } else { 385 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 386 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 387 if (Subtarget->is64Bit()) 388 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 389 } 390 391 if (Subtarget->hasLZCNT()) { 392 // When promoting the i8 variants, force them to i32 for a shorter 393 // encoding. 394 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 395 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 396 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 397 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 399 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 400 if (Subtarget->is64Bit()) 401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 402 } else { 403 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 404 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 405 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 409 if (Subtarget->is64Bit()) { 410 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 412 } 413 } 414 415 if (Subtarget->hasPOPCNT()) { 416 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 417 } else { 418 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 419 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 420 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 421 if (Subtarget->is64Bit()) 422 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 423 } 424 425 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 426 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 427 428 // These should be promoted to a larger select which is supported. 429 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 430 // X86 wants to expand cmov itself. 431 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 432 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 433 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 434 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 435 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 436 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 437 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 438 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 439 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 440 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 441 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 442 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 443 if (Subtarget->is64Bit()) { 444 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 445 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 446 } 447 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 448 449 // Darwin ABI issue. 450 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 451 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 452 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 453 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 454 if (Subtarget->is64Bit()) 455 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 456 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 457 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 458 if (Subtarget->is64Bit()) { 459 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 460 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 461 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 462 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 463 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 464 } 465 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 466 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 467 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 468 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 469 if (Subtarget->is64Bit()) { 470 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 471 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 472 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 473 } 474 475 if (Subtarget->hasSSE1()) 476 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 477 478 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 479 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 480 481 // On X86 and X86-64, atomic operations are lowered to locked instructions. 482 // Locked instructions, in turn, have implicit fence semantics (all memory 483 // operations are flushed before issuing the locked instruction, and they 484 // are not buffered), so we can fold away the common pattern of 485 // fence-atomic-fence. 486 setShouldFoldAtomicFences(true); 487 488 // Expand certain atomics 489 for (unsigned i = 0, e = 4; i != e; ++i) { 490 MVT VT = IntVTs[i]; 491 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 492 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 493 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 494 } 495 496 if (!Subtarget->is64Bit()) { 497 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 498 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 499 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 501 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 502 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 503 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 505 } 506 507 if (Subtarget->hasCmpxchg16b()) { 508 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 509 } 510 511 // FIXME - use subtarget debug flags 512 if (!Subtarget->isTargetDarwin() && 513 !Subtarget->isTargetELF() && 514 !Subtarget->isTargetCygMing()) { 515 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 516 } 517 518 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 519 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 521 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 522 if (Subtarget->is64Bit()) { 523 setExceptionPointerRegister(X86::RAX); 524 setExceptionSelectorRegister(X86::RDX); 525 } else { 526 setExceptionPointerRegister(X86::EAX); 527 setExceptionSelectorRegister(X86::EDX); 528 } 529 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 530 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 531 532 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 533 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 534 535 setOperationAction(ISD::TRAP, MVT::Other, Legal); 536 537 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 538 setOperationAction(ISD::VASTART , MVT::Other, Custom); 539 setOperationAction(ISD::VAEND , MVT::Other, Expand); 540 if (Subtarget->is64Bit()) { 541 setOperationAction(ISD::VAARG , MVT::Other, Custom); 542 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 543 } else { 544 setOperationAction(ISD::VAARG , MVT::Other, Expand); 545 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 546 } 547 548 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 549 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 550 551 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 552 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 553 MVT::i64 : MVT::i32, Custom); 554 else if (TM.Options.EnableSegmentedStacks) 555 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 556 MVT::i64 : MVT::i32, Custom); 557 else 558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 559 MVT::i64 : MVT::i32, Expand); 560 561 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 562 // f32 and f64 use SSE. 563 // Set up the FP register classes. 564 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 565 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 566 567 // Use ANDPD to simulate FABS. 568 setOperationAction(ISD::FABS , MVT::f64, Custom); 569 setOperationAction(ISD::FABS , MVT::f32, Custom); 570 571 // Use XORP to simulate FNEG. 572 setOperationAction(ISD::FNEG , MVT::f64, Custom); 573 setOperationAction(ISD::FNEG , MVT::f32, Custom); 574 575 // Use ANDPD and ORPD to simulate FCOPYSIGN. 576 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 577 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 578 579 // Lower this to FGETSIGNx86 plus an AND. 580 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 581 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 582 583 // We don't support sin/cos/fmod 584 setOperationAction(ISD::FSIN , MVT::f64, Expand); 585 setOperationAction(ISD::FCOS , MVT::f64, Expand); 586 setOperationAction(ISD::FSIN , MVT::f32, Expand); 587 setOperationAction(ISD::FCOS , MVT::f32, Expand); 588 589 // Expand FP immediates into loads from the stack, except for the special 590 // cases we handle. 591 addLegalFPImmediate(APFloat(+0.0)); // xorpd 592 addLegalFPImmediate(APFloat(+0.0f)); // xorps 593 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 594 // Use SSE for f32, x87 for f64. 595 // Set up the FP register classes. 596 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 597 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 598 599 // Use ANDPS to simulate FABS. 600 setOperationAction(ISD::FABS , MVT::f32, Custom); 601 602 // Use XORP to simulate FNEG. 603 setOperationAction(ISD::FNEG , MVT::f32, Custom); 604 605 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 606 607 // Use ANDPS and ORPS to simulate FCOPYSIGN. 608 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 609 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 610 611 // We don't support sin/cos/fmod 612 setOperationAction(ISD::FSIN , MVT::f32, Expand); 613 setOperationAction(ISD::FCOS , MVT::f32, Expand); 614 615 // Special cases we handle for FP constants. 616 addLegalFPImmediate(APFloat(+0.0f)); // xorps 617 addLegalFPImmediate(APFloat(+0.0)); // FLD0 618 addLegalFPImmediate(APFloat(+1.0)); // FLD1 619 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 620 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 621 622 if (!TM.Options.UnsafeFPMath) { 623 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 624 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 625 } 626 } else if (!TM.Options.UseSoftFloat) { 627 // f32 and f64 in x87. 628 // Set up the FP register classes. 629 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 630 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 631 632 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 633 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 634 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 635 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 636 637 if (!TM.Options.UnsafeFPMath) { 638 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 639 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 640 } 641 addLegalFPImmediate(APFloat(+0.0)); // FLD0 642 addLegalFPImmediate(APFloat(+1.0)); // FLD1 643 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 644 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 645 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 646 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 647 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 648 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 649 } 650 651 // We don't support FMA. 652 setOperationAction(ISD::FMA, MVT::f64, Expand); 653 setOperationAction(ISD::FMA, MVT::f32, Expand); 654 655 // Long double always uses X87. 656 if (!TM.Options.UseSoftFloat) { 657 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 658 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 659 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 660 { 661 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 662 addLegalFPImmediate(TmpFlt); // FLD0 663 TmpFlt.changeSign(); 664 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 665 666 bool ignored; 667 APFloat TmpFlt2(+1.0); 668 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 669 &ignored); 670 addLegalFPImmediate(TmpFlt2); // FLD1 671 TmpFlt2.changeSign(); 672 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 673 } 674 675 if (!TM.Options.UnsafeFPMath) { 676 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 677 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 678 } 679 680 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 681 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 682 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 683 setOperationAction(ISD::FRINT, MVT::f80, Expand); 684 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 685 setOperationAction(ISD::FMA, MVT::f80, Expand); 686 } 687 688 // Always use a library call for pow. 689 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 690 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 691 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 692 693 setOperationAction(ISD::FLOG, MVT::f80, Expand); 694 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 695 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 696 setOperationAction(ISD::FEXP, MVT::f80, Expand); 697 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 698 699 // First set operation action for all vector types to either promote 700 // (for widening) or expand (for scalarization). Then we will selectively 701 // turn on ones that can be effectively codegen'd. 702 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 703 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 704 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 719 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 721 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 722 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 756 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 761 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 762 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 763 setTruncStoreAction((MVT::SimpleValueType)VT, 764 (MVT::SimpleValueType)InnerVT, Expand); 765 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 766 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 767 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 768 } 769 770 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 771 // with -msoft-float, disable use of MMX as well. 772 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 773 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 774 // No operations on x86mmx supported, everything uses intrinsics. 775 } 776 777 // MMX-sized vectors (other than x86mmx) are expected to be expanded 778 // into smaller operations. 779 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 780 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 781 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 782 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 783 setOperationAction(ISD::AND, MVT::v8i8, Expand); 784 setOperationAction(ISD::AND, MVT::v4i16, Expand); 785 setOperationAction(ISD::AND, MVT::v2i32, Expand); 786 setOperationAction(ISD::AND, MVT::v1i64, Expand); 787 setOperationAction(ISD::OR, MVT::v8i8, Expand); 788 setOperationAction(ISD::OR, MVT::v4i16, Expand); 789 setOperationAction(ISD::OR, MVT::v2i32, Expand); 790 setOperationAction(ISD::OR, MVT::v1i64, Expand); 791 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 792 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 793 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 794 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 795 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 796 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 799 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 800 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 801 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 802 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 803 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 804 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 805 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 806 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 807 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 808 809 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 810 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 811 812 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 813 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 814 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 815 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 816 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 817 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 818 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 819 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 820 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 822 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 823 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 824 } 825 826 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 827 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 828 829 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 830 // registers cannot be used even for integer operations. 831 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 832 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 833 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 834 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 835 836 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 837 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 838 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 839 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 840 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 841 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 842 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 843 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 844 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 845 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 846 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 847 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 848 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 849 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 850 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 851 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 852 853 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 854 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 855 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 856 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 857 858 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 859 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 863 864 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 865 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 869 870 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 871 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 872 EVT VT = (MVT::SimpleValueType)i; 873 // Do not attempt to custom lower non-power-of-2 vectors 874 if (!isPowerOf2_32(VT.getVectorNumElements())) 875 continue; 876 // Do not attempt to custom lower non-128-bit vectors 877 if (!VT.is128BitVector()) 878 continue; 879 setOperationAction(ISD::BUILD_VECTOR, 880 VT.getSimpleVT().SimpleTy, Custom); 881 setOperationAction(ISD::VECTOR_SHUFFLE, 882 VT.getSimpleVT().SimpleTy, Custom); 883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 884 VT.getSimpleVT().SimpleTy, Custom); 885 } 886 887 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 891 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 892 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 893 894 if (Subtarget->is64Bit()) { 895 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 896 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 897 } 898 899 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 900 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 901 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 902 EVT VT = SVT; 903 904 // Do not attempt to promote non-128-bit vectors 905 if (!VT.is128BitVector()) 906 continue; 907 908 setOperationAction(ISD::AND, SVT, Promote); 909 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 910 setOperationAction(ISD::OR, SVT, Promote); 911 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 912 setOperationAction(ISD::XOR, SVT, Promote); 913 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 914 setOperationAction(ISD::LOAD, SVT, Promote); 915 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 916 setOperationAction(ISD::SELECT, SVT, Promote); 917 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 918 } 919 920 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 921 922 // Custom lower v2i64 and v2f64 selects. 923 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 924 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 925 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 926 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 927 928 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 929 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 930 } 931 932 if (Subtarget->hasSSE41()) { 933 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 934 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 935 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 936 setOperationAction(ISD::FRINT, MVT::f32, Legal); 937 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 938 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 939 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 940 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 941 setOperationAction(ISD::FRINT, MVT::f64, Legal); 942 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 943 944 // FIXME: Do we need to handle scalar-to-vector here? 945 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 946 947 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 948 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 949 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 950 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 951 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 952 953 // i8 and i16 vectors are custom , because the source register and source 954 // source memory operand types are not the same width. f32 vectors are 955 // custom since the immediate controlling the insert encodes additional 956 // information. 957 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 958 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 961 962 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 963 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 966 967 // FIXME: these should be Legal but thats only for the case where 968 // the index is constant. For now custom expand to deal with that. 969 if (Subtarget->is64Bit()) { 970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 972 } 973 } 974 975 if (Subtarget->hasSSE2()) { 976 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 977 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 978 979 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 980 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 981 982 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 983 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 984 985 if (Subtarget->hasAVX2()) { 986 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 987 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 988 989 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 990 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 991 992 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 993 } else { 994 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 995 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 996 997 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 998 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 999 1000 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1001 } 1002 } 1003 1004 if (Subtarget->hasSSE42()) 1005 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1006 1007 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1008 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1009 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1010 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1011 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1012 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1013 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1014 1015 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1016 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1017 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1018 1019 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1020 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1021 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1022 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1023 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1024 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1025 1026 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1027 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1028 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1029 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1030 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1031 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1032 1033 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1034 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1035 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1036 1037 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1038 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1043 1044 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1045 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1046 1047 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1048 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1049 1050 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1051 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1052 1053 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1054 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1055 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1056 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1057 1058 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1059 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1060 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1061 1062 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1063 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1064 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1065 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1066 1067 if (Subtarget->hasAVX2()) { 1068 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1069 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1070 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1071 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1072 1073 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1074 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1075 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1076 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1077 1078 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1079 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1080 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1081 // Don't lower v32i8 because there is no 128-bit byte mul 1082 1083 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1084 1085 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1086 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1087 1088 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1089 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1090 1091 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1092 } else { 1093 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1094 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1095 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1096 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1097 1098 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1099 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1100 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1101 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1102 1103 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1104 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1105 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1106 // Don't lower v32i8 because there is no 128-bit byte mul 1107 1108 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1109 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1110 1111 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1112 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1113 1114 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1115 } 1116 1117 // Custom lower several nodes for 256-bit types. 1118 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1119 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1120 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1121 EVT VT = SVT; 1122 1123 // Extract subvector is special because the value type 1124 // (result) is 128-bit but the source is 256-bit wide. 1125 if (VT.is128BitVector()) 1126 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1127 1128 // Do not attempt to custom lower other non-256-bit vectors 1129 if (!VT.is256BitVector()) 1130 continue; 1131 1132 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1133 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1134 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1136 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1137 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1138 } 1139 1140 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1141 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1142 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1143 EVT VT = SVT; 1144 1145 // Do not attempt to promote non-256-bit vectors 1146 if (!VT.is256BitVector()) 1147 continue; 1148 1149 setOperationAction(ISD::AND, SVT, Promote); 1150 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1151 setOperationAction(ISD::OR, SVT, Promote); 1152 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1153 setOperationAction(ISD::XOR, SVT, Promote); 1154 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1155 setOperationAction(ISD::LOAD, SVT, Promote); 1156 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1157 setOperationAction(ISD::SELECT, SVT, Promote); 1158 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1159 } 1160 } 1161 1162 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1163 // of this type with custom code. 1164 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1165 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1166 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1167 Custom); 1168 } 1169 1170 // We want to custom lower some of our intrinsics. 1171 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1172 1173 1174 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1175 // handle type legalization for these operations here. 1176 // 1177 // FIXME: We really should do custom legalization for addition and 1178 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1179 // than generic legalization for 64-bit multiplication-with-overflow, though. 1180 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1181 // Add/Sub/Mul with overflow operations are custom lowered. 1182 MVT VT = IntVTs[i]; 1183 setOperationAction(ISD::SADDO, VT, Custom); 1184 setOperationAction(ISD::UADDO, VT, Custom); 1185 setOperationAction(ISD::SSUBO, VT, Custom); 1186 setOperationAction(ISD::USUBO, VT, Custom); 1187 setOperationAction(ISD::SMULO, VT, Custom); 1188 setOperationAction(ISD::UMULO, VT, Custom); 1189 } 1190 1191 // There are no 8-bit 3-address imul/mul instructions 1192 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1193 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1194 1195 if (!Subtarget->is64Bit()) { 1196 // These libcalls are not available in 32-bit. 1197 setLibcallName(RTLIB::SHL_I128, 0); 1198 setLibcallName(RTLIB::SRL_I128, 0); 1199 setLibcallName(RTLIB::SRA_I128, 0); 1200 } 1201 1202 // We have target-specific dag combine patterns for the following nodes: 1203 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1204 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1205 setTargetDAGCombine(ISD::VSELECT); 1206 setTargetDAGCombine(ISD::SELECT); 1207 setTargetDAGCombine(ISD::SHL); 1208 setTargetDAGCombine(ISD::SRA); 1209 setTargetDAGCombine(ISD::SRL); 1210 setTargetDAGCombine(ISD::OR); 1211 setTargetDAGCombine(ISD::AND); 1212 setTargetDAGCombine(ISD::ADD); 1213 setTargetDAGCombine(ISD::FADD); 1214 setTargetDAGCombine(ISD::FSUB); 1215 setTargetDAGCombine(ISD::SUB); 1216 setTargetDAGCombine(ISD::LOAD); 1217 setTargetDAGCombine(ISD::STORE); 1218 setTargetDAGCombine(ISD::ZERO_EXTEND); 1219 setTargetDAGCombine(ISD::SIGN_EXTEND); 1220 setTargetDAGCombine(ISD::TRUNCATE); 1221 setTargetDAGCombine(ISD::SINT_TO_FP); 1222 if (Subtarget->is64Bit()) 1223 setTargetDAGCombine(ISD::MUL); 1224 if (Subtarget->hasBMI()) 1225 setTargetDAGCombine(ISD::XOR); 1226 1227 computeRegisterProperties(); 1228 1229 // On Darwin, -Os means optimize for size without hurting performance, 1230 // do not reduce the limit. 1231 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1232 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1233 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1234 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1235 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1236 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1237 setPrefLoopAlignment(4); // 2^4 bytes. 1238 benefitFromCodePlacementOpt = true; 1239 1240 setPrefFunctionAlignment(4); // 2^4 bytes. 1241} 1242 1243 1244EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1245 if (!VT.isVector()) return MVT::i8; 1246 return VT.changeVectorElementTypeToInteger(); 1247} 1248 1249 1250/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1251/// the desired ByVal argument alignment. 1252static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1253 if (MaxAlign == 16) 1254 return; 1255 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1256 if (VTy->getBitWidth() == 128) 1257 MaxAlign = 16; 1258 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1259 unsigned EltAlign = 0; 1260 getMaxByValAlign(ATy->getElementType(), EltAlign); 1261 if (EltAlign > MaxAlign) 1262 MaxAlign = EltAlign; 1263 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1264 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(STy->getElementType(i), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 if (MaxAlign == 16) 1270 break; 1271 } 1272 } 1273 return; 1274} 1275 1276/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1277/// function arguments in the caller parameter area. For X86, aggregates 1278/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1279/// are at 4-byte boundaries. 1280unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1281 if (Subtarget->is64Bit()) { 1282 // Max of 8 and alignment of type. 1283 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1284 if (TyAlign > 8) 1285 return TyAlign; 1286 return 8; 1287 } 1288 1289 unsigned Align = 4; 1290 if (Subtarget->hasSSE1()) 1291 getMaxByValAlign(Ty, Align); 1292 return Align; 1293} 1294 1295/// getOptimalMemOpType - Returns the target specific optimal type for load 1296/// and store operations as a result of memset, memcpy, and memmove 1297/// lowering. If DstAlign is zero that means it's safe to destination 1298/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1299/// means there isn't a need to check it against alignment requirement, 1300/// probably because the source does not need to be loaded. If 1301/// 'IsZeroVal' is true, that means it's safe to return a 1302/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1303/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1304/// constant so it does not need to be loaded. 1305/// It returns EVT::Other if the type should be determined using generic 1306/// target-independent logic. 1307EVT 1308X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1309 unsigned DstAlign, unsigned SrcAlign, 1310 bool IsZeroVal, 1311 bool MemcpyStrSrc, 1312 MachineFunction &MF) const { 1313 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1314 // linux. This is because the stack realignment code can't handle certain 1315 // cases like PR2962. This should be removed when PR2962 is fixed. 1316 const Function *F = MF.getFunction(); 1317 if (IsZeroVal && 1318 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1319 if (Size >= 16 && 1320 (Subtarget->isUnalignedMemAccessFast() || 1321 ((DstAlign == 0 || DstAlign >= 16) && 1322 (SrcAlign == 0 || SrcAlign >= 16))) && 1323 Subtarget->getStackAlignment() >= 16) { 1324 if (Subtarget->getStackAlignment() >= 32) { 1325 if (Subtarget->hasAVX2()) 1326 return MVT::v8i32; 1327 if (Subtarget->hasAVX()) 1328 return MVT::v8f32; 1329 } 1330 if (Subtarget->hasSSE2()) 1331 return MVT::v4i32; 1332 if (Subtarget->hasSSE1()) 1333 return MVT::v4f32; 1334 } else if (!MemcpyStrSrc && Size >= 8 && 1335 !Subtarget->is64Bit() && 1336 Subtarget->getStackAlignment() >= 8 && 1337 Subtarget->hasSSE2()) { 1338 // Do not use f64 to lower memcpy if source is string constant. It's 1339 // better to use i32 to avoid the loads. 1340 return MVT::f64; 1341 } 1342 } 1343 if (Subtarget->is64Bit() && Size >= 8) 1344 return MVT::i64; 1345 return MVT::i32; 1346} 1347 1348/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1349/// current function. The returned value is a member of the 1350/// MachineJumpTableInfo::JTEntryKind enum. 1351unsigned X86TargetLowering::getJumpTableEncoding() const { 1352 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1353 // symbol. 1354 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1355 Subtarget->isPICStyleGOT()) 1356 return MachineJumpTableInfo::EK_Custom32; 1357 1358 // Otherwise, use the normal jump table encoding heuristics. 1359 return TargetLowering::getJumpTableEncoding(); 1360} 1361 1362const MCExpr * 1363X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1364 const MachineBasicBlock *MBB, 1365 unsigned uid,MCContext &Ctx) const{ 1366 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1367 Subtarget->isPICStyleGOT()); 1368 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1369 // entries. 1370 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1371 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1372} 1373 1374/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1375/// jumptable. 1376SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1377 SelectionDAG &DAG) const { 1378 if (!Subtarget->is64Bit()) 1379 // This doesn't have DebugLoc associated with it, but is not really the 1380 // same as a Register. 1381 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1382 return Table; 1383} 1384 1385/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1386/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1387/// MCExpr. 1388const MCExpr *X86TargetLowering:: 1389getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1390 MCContext &Ctx) const { 1391 // X86-64 uses RIP relative addressing based on the jump table label. 1392 if (Subtarget->isPICStyleRIPRel()) 1393 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1394 1395 // Otherwise, the reference is relative to the PIC base. 1396 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1397} 1398 1399// FIXME: Why this routine is here? Move to RegInfo! 1400std::pair<const TargetRegisterClass*, uint8_t> 1401X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1402 const TargetRegisterClass *RRC = 0; 1403 uint8_t Cost = 1; 1404 switch (VT.getSimpleVT().SimpleTy) { 1405 default: 1406 return TargetLowering::findRepresentativeClass(VT); 1407 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1408 RRC = (Subtarget->is64Bit() 1409 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1410 break; 1411 case MVT::x86mmx: 1412 RRC = X86::VR64RegisterClass; 1413 break; 1414 case MVT::f32: case MVT::f64: 1415 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1416 case MVT::v4f32: case MVT::v2f64: 1417 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1418 case MVT::v4f64: 1419 RRC = X86::VR128RegisterClass; 1420 break; 1421 } 1422 return std::make_pair(RRC, Cost); 1423} 1424 1425bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1426 unsigned &Offset) const { 1427 if (!Subtarget->isTargetLinux()) 1428 return false; 1429 1430 if (Subtarget->is64Bit()) { 1431 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1432 Offset = 0x28; 1433 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1434 AddressSpace = 256; 1435 else 1436 AddressSpace = 257; 1437 } else { 1438 // %gs:0x14 on i386 1439 Offset = 0x14; 1440 AddressSpace = 256; 1441 } 1442 return true; 1443} 1444 1445 1446//===----------------------------------------------------------------------===// 1447// Return Value Calling Convention Implementation 1448//===----------------------------------------------------------------------===// 1449 1450#include "X86GenCallingConv.inc" 1451 1452bool 1453X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1454 MachineFunction &MF, bool isVarArg, 1455 const SmallVectorImpl<ISD::OutputArg> &Outs, 1456 LLVMContext &Context) const { 1457 SmallVector<CCValAssign, 16> RVLocs; 1458 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1459 RVLocs, Context); 1460 return CCInfo.CheckReturn(Outs, RetCC_X86); 1461} 1462 1463SDValue 1464X86TargetLowering::LowerReturn(SDValue Chain, 1465 CallingConv::ID CallConv, bool isVarArg, 1466 const SmallVectorImpl<ISD::OutputArg> &Outs, 1467 const SmallVectorImpl<SDValue> &OutVals, 1468 DebugLoc dl, SelectionDAG &DAG) const { 1469 MachineFunction &MF = DAG.getMachineFunction(); 1470 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1471 1472 SmallVector<CCValAssign, 16> RVLocs; 1473 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1474 RVLocs, *DAG.getContext()); 1475 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1476 1477 // Add the regs to the liveout set for the function. 1478 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1479 for (unsigned i = 0; i != RVLocs.size(); ++i) 1480 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1481 MRI.addLiveOut(RVLocs[i].getLocReg()); 1482 1483 SDValue Flag; 1484 1485 SmallVector<SDValue, 6> RetOps; 1486 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1487 // Operand #1 = Bytes To Pop 1488 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1489 MVT::i16)); 1490 1491 // Copy the result values into the output registers. 1492 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1493 CCValAssign &VA = RVLocs[i]; 1494 assert(VA.isRegLoc() && "Can only return in registers!"); 1495 SDValue ValToCopy = OutVals[i]; 1496 EVT ValVT = ValToCopy.getValueType(); 1497 1498 // If this is x86-64, and we disabled SSE, we can't return FP values, 1499 // or SSE or MMX vectors. 1500 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1501 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1502 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1503 report_fatal_error("SSE register return with SSE disabled"); 1504 } 1505 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1506 // llvm-gcc has never done it right and no one has noticed, so this 1507 // should be OK for now. 1508 if (ValVT == MVT::f64 && 1509 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1510 report_fatal_error("SSE2 register return with SSE2 disabled"); 1511 1512 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1513 // the RET instruction and handled by the FP Stackifier. 1514 if (VA.getLocReg() == X86::ST0 || 1515 VA.getLocReg() == X86::ST1) { 1516 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1517 // change the value to the FP stack register class. 1518 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1519 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1520 RetOps.push_back(ValToCopy); 1521 // Don't emit a copytoreg. 1522 continue; 1523 } 1524 1525 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1526 // which is returned in RAX / RDX. 1527 if (Subtarget->is64Bit()) { 1528 if (ValVT == MVT::x86mmx) { 1529 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1530 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1531 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1532 ValToCopy); 1533 // If we don't have SSE2 available, convert to v4f32 so the generated 1534 // register is legal. 1535 if (!Subtarget->hasSSE2()) 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1537 } 1538 } 1539 } 1540 1541 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1542 Flag = Chain.getValue(1); 1543 } 1544 1545 // The x86-64 ABI for returning structs by value requires that we copy 1546 // the sret argument into %rax for the return. We saved the argument into 1547 // a virtual register in the entry block, so now we copy the value out 1548 // and into %rax. 1549 if (Subtarget->is64Bit() && 1550 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1551 MachineFunction &MF = DAG.getMachineFunction(); 1552 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1553 unsigned Reg = FuncInfo->getSRetReturnReg(); 1554 assert(Reg && 1555 "SRetReturnReg should have been set in LowerFormalArguments()."); 1556 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1557 1558 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1559 Flag = Chain.getValue(1); 1560 1561 // RAX now acts like a return value. 1562 MRI.addLiveOut(X86::RAX); 1563 } 1564 1565 RetOps[0] = Chain; // Update chain. 1566 1567 // Add the flag if we have it. 1568 if (Flag.getNode()) 1569 RetOps.push_back(Flag); 1570 1571 return DAG.getNode(X86ISD::RET_FLAG, dl, 1572 MVT::Other, &RetOps[0], RetOps.size()); 1573} 1574 1575bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1576 if (N->getNumValues() != 1) 1577 return false; 1578 if (!N->hasNUsesOfValue(1, 0)) 1579 return false; 1580 1581 SDNode *Copy = *N->use_begin(); 1582 if (Copy->getOpcode() != ISD::CopyToReg && 1583 Copy->getOpcode() != ISD::FP_EXTEND) 1584 return false; 1585 1586 bool HasRet = false; 1587 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1588 UI != UE; ++UI) { 1589 if (UI->getOpcode() != X86ISD::RET_FLAG) 1590 return false; 1591 HasRet = true; 1592 } 1593 1594 return HasRet; 1595} 1596 1597EVT 1598X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1599 ISD::NodeType ExtendKind) const { 1600 MVT ReturnMVT; 1601 // TODO: Is this also valid on 32-bit? 1602 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1603 ReturnMVT = MVT::i8; 1604 else 1605 ReturnMVT = MVT::i32; 1606 1607 EVT MinVT = getRegisterType(Context, ReturnMVT); 1608 return VT.bitsLT(MinVT) ? MinVT : VT; 1609} 1610 1611/// LowerCallResult - Lower the result values of a call into the 1612/// appropriate copies out of appropriate physical registers. 1613/// 1614SDValue 1615X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1616 CallingConv::ID CallConv, bool isVarArg, 1617 const SmallVectorImpl<ISD::InputArg> &Ins, 1618 DebugLoc dl, SelectionDAG &DAG, 1619 SmallVectorImpl<SDValue> &InVals) const { 1620 1621 // Assign locations to each value returned by this call. 1622 SmallVector<CCValAssign, 16> RVLocs; 1623 bool Is64Bit = Subtarget->is64Bit(); 1624 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1625 getTargetMachine(), RVLocs, *DAG.getContext()); 1626 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1627 1628 // Copy all of the result registers out of their specified physreg. 1629 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1630 CCValAssign &VA = RVLocs[i]; 1631 EVT CopyVT = VA.getValVT(); 1632 1633 // If this is x86-64, and we disabled SSE, we can't return FP values 1634 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1635 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1636 report_fatal_error("SSE register return with SSE disabled"); 1637 } 1638 1639 SDValue Val; 1640 1641 // If this is a call to a function that returns an fp value on the floating 1642 // point stack, we must guarantee the the value is popped from the stack, so 1643 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1644 // if the return value is not used. We use the FpPOP_RETVAL instruction 1645 // instead. 1646 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1647 // If we prefer to use the value in xmm registers, copy it out as f80 and 1648 // use a truncate to move it from fp stack reg to xmm reg. 1649 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1650 SDValue Ops[] = { Chain, InFlag }; 1651 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1652 MVT::Other, MVT::Glue, Ops, 2), 1); 1653 Val = Chain.getValue(0); 1654 1655 // Round the f80 to the right size, which also moves it to the appropriate 1656 // xmm register. 1657 if (CopyVT != VA.getValVT()) 1658 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1659 // This truncation won't change the value. 1660 DAG.getIntPtrConstant(1)); 1661 } else { 1662 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1663 CopyVT, InFlag).getValue(1); 1664 Val = Chain.getValue(0); 1665 } 1666 InFlag = Chain.getValue(2); 1667 InVals.push_back(Val); 1668 } 1669 1670 return Chain; 1671} 1672 1673 1674//===----------------------------------------------------------------------===// 1675// C & StdCall & Fast Calling Convention implementation 1676//===----------------------------------------------------------------------===// 1677// StdCall calling convention seems to be standard for many Windows' API 1678// routines and around. It differs from C calling convention just a little: 1679// callee should clean up the stack, not caller. Symbols should be also 1680// decorated in some fancy way :) It doesn't support any vector arguments. 1681// For info on fast calling convention see Fast Calling Convention (tail call) 1682// implementation LowerX86_32FastCCCallTo. 1683 1684/// CallIsStructReturn - Determines whether a call uses struct return 1685/// semantics. 1686static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1687 if (Outs.empty()) 1688 return false; 1689 1690 return Outs[0].Flags.isSRet(); 1691} 1692 1693/// ArgsAreStructReturn - Determines whether a function uses struct 1694/// return semantics. 1695static bool 1696ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1697 if (Ins.empty()) 1698 return false; 1699 1700 return Ins[0].Flags.isSRet(); 1701} 1702 1703/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1704/// by "Src" to address "Dst" with size and alignment information specified by 1705/// the specific parameter attribute. The copy will be passed as a byval 1706/// function parameter. 1707static SDValue 1708CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1709 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1710 DebugLoc dl) { 1711 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1712 1713 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1714 /*isVolatile*/false, /*AlwaysInline=*/true, 1715 MachinePointerInfo(), MachinePointerInfo()); 1716} 1717 1718/// IsTailCallConvention - Return true if the calling convention is one that 1719/// supports tail call optimization. 1720static bool IsTailCallConvention(CallingConv::ID CC) { 1721 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1722} 1723 1724bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1725 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1726 return false; 1727 1728 CallSite CS(CI); 1729 CallingConv::ID CalleeCC = CS.getCallingConv(); 1730 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1731 return false; 1732 1733 return true; 1734} 1735 1736/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1737/// a tailcall target by changing its ABI. 1738static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1739 bool GuaranteedTailCallOpt) { 1740 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1741} 1742 1743SDValue 1744X86TargetLowering::LowerMemArgument(SDValue Chain, 1745 CallingConv::ID CallConv, 1746 const SmallVectorImpl<ISD::InputArg> &Ins, 1747 DebugLoc dl, SelectionDAG &DAG, 1748 const CCValAssign &VA, 1749 MachineFrameInfo *MFI, 1750 unsigned i) const { 1751 // Create the nodes corresponding to a load from this parameter slot. 1752 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1753 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1754 getTargetMachine().Options.GuaranteedTailCallOpt); 1755 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1756 EVT ValVT; 1757 1758 // If value is passed by pointer we have address passed instead of the value 1759 // itself. 1760 if (VA.getLocInfo() == CCValAssign::Indirect) 1761 ValVT = VA.getLocVT(); 1762 else 1763 ValVT = VA.getValVT(); 1764 1765 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1766 // changed with more analysis. 1767 // In case of tail call optimization mark all arguments mutable. Since they 1768 // could be overwritten by lowering of arguments in case of a tail call. 1769 if (Flags.isByVal()) { 1770 unsigned Bytes = Flags.getByValSize(); 1771 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1772 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1773 return DAG.getFrameIndex(FI, getPointerTy()); 1774 } else { 1775 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1776 VA.getLocMemOffset(), isImmutable); 1777 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1778 return DAG.getLoad(ValVT, dl, Chain, FIN, 1779 MachinePointerInfo::getFixedStack(FI), 1780 false, false, false, 0); 1781 } 1782} 1783 1784SDValue 1785X86TargetLowering::LowerFormalArguments(SDValue Chain, 1786 CallingConv::ID CallConv, 1787 bool isVarArg, 1788 const SmallVectorImpl<ISD::InputArg> &Ins, 1789 DebugLoc dl, 1790 SelectionDAG &DAG, 1791 SmallVectorImpl<SDValue> &InVals) 1792 const { 1793 MachineFunction &MF = DAG.getMachineFunction(); 1794 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1795 1796 const Function* Fn = MF.getFunction(); 1797 if (Fn->hasExternalLinkage() && 1798 Subtarget->isTargetCygMing() && 1799 Fn->getName() == "main") 1800 FuncInfo->setForceFramePointer(true); 1801 1802 MachineFrameInfo *MFI = MF.getFrameInfo(); 1803 bool Is64Bit = Subtarget->is64Bit(); 1804 bool IsWindows = Subtarget->isTargetWindows(); 1805 bool IsWin64 = Subtarget->isTargetWin64(); 1806 1807 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1808 "Var args not supported with calling convention fastcc or ghc"); 1809 1810 // Assign locations to all of the incoming arguments. 1811 SmallVector<CCValAssign, 16> ArgLocs; 1812 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1813 ArgLocs, *DAG.getContext()); 1814 1815 // Allocate shadow area for Win64 1816 if (IsWin64) { 1817 CCInfo.AllocateStack(32, 8); 1818 } 1819 1820 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1821 1822 unsigned LastVal = ~0U; 1823 SDValue ArgValue; 1824 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1825 CCValAssign &VA = ArgLocs[i]; 1826 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1827 // places. 1828 assert(VA.getValNo() != LastVal && 1829 "Don't support value assigned to multiple locs yet"); 1830 (void)LastVal; 1831 LastVal = VA.getValNo(); 1832 1833 if (VA.isRegLoc()) { 1834 EVT RegVT = VA.getLocVT(); 1835 TargetRegisterClass *RC = NULL; 1836 if (RegVT == MVT::i32) 1837 RC = X86::GR32RegisterClass; 1838 else if (Is64Bit && RegVT == MVT::i64) 1839 RC = X86::GR64RegisterClass; 1840 else if (RegVT == MVT::f32) 1841 RC = X86::FR32RegisterClass; 1842 else if (RegVT == MVT::f64) 1843 RC = X86::FR64RegisterClass; 1844 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1845 RC = X86::VR256RegisterClass; 1846 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1847 RC = X86::VR128RegisterClass; 1848 else if (RegVT == MVT::x86mmx) 1849 RC = X86::VR64RegisterClass; 1850 else 1851 llvm_unreachable("Unknown argument type!"); 1852 1853 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1854 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1855 1856 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1857 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1858 // right size. 1859 if (VA.getLocInfo() == CCValAssign::SExt) 1860 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1861 DAG.getValueType(VA.getValVT())); 1862 else if (VA.getLocInfo() == CCValAssign::ZExt) 1863 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1864 DAG.getValueType(VA.getValVT())); 1865 else if (VA.getLocInfo() == CCValAssign::BCvt) 1866 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1867 1868 if (VA.isExtInLoc()) { 1869 // Handle MMX values passed in XMM regs. 1870 if (RegVT.isVector()) { 1871 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1872 ArgValue); 1873 } else 1874 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1875 } 1876 } else { 1877 assert(VA.isMemLoc()); 1878 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1879 } 1880 1881 // If value is passed via pointer - do a load. 1882 if (VA.getLocInfo() == CCValAssign::Indirect) 1883 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1884 MachinePointerInfo(), false, false, false, 0); 1885 1886 InVals.push_back(ArgValue); 1887 } 1888 1889 // The x86-64 ABI for returning structs by value requires that we copy 1890 // the sret argument into %rax for the return. Save the argument into 1891 // a virtual register so that we can access it from the return points. 1892 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1893 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1894 unsigned Reg = FuncInfo->getSRetReturnReg(); 1895 if (!Reg) { 1896 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1897 FuncInfo->setSRetReturnReg(Reg); 1898 } 1899 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1900 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1901 } 1902 1903 unsigned StackSize = CCInfo.getNextStackOffset(); 1904 // Align stack specially for tail calls. 1905 if (FuncIsMadeTailCallSafe(CallConv, 1906 MF.getTarget().Options.GuaranteedTailCallOpt)) 1907 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1908 1909 // If the function takes variable number of arguments, make a frame index for 1910 // the start of the first vararg value... for expansion of llvm.va_start. 1911 if (isVarArg) { 1912 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1913 CallConv != CallingConv::X86_ThisCall)) { 1914 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1915 } 1916 if (Is64Bit) { 1917 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1918 1919 // FIXME: We should really autogenerate these arrays 1920 static const unsigned GPR64ArgRegsWin64[] = { 1921 X86::RCX, X86::RDX, X86::R8, X86::R9 1922 }; 1923 static const unsigned GPR64ArgRegs64Bit[] = { 1924 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1925 }; 1926 static const unsigned XMMArgRegs64Bit[] = { 1927 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1928 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1929 }; 1930 const unsigned *GPR64ArgRegs; 1931 unsigned NumXMMRegs = 0; 1932 1933 if (IsWin64) { 1934 // The XMM registers which might contain var arg parameters are shadowed 1935 // in their paired GPR. So we only need to save the GPR to their home 1936 // slots. 1937 TotalNumIntRegs = 4; 1938 GPR64ArgRegs = GPR64ArgRegsWin64; 1939 } else { 1940 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1941 GPR64ArgRegs = GPR64ArgRegs64Bit; 1942 1943 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1944 TotalNumXMMRegs); 1945 } 1946 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1947 TotalNumIntRegs); 1948 1949 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1950 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1951 "SSE register cannot be used when SSE is disabled!"); 1952 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1953 NoImplicitFloatOps) && 1954 "SSE register cannot be used when SSE is disabled!"); 1955 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1956 !Subtarget->hasSSE1()) 1957 // Kernel mode asks for SSE to be disabled, so don't push them 1958 // on the stack. 1959 TotalNumXMMRegs = 0; 1960 1961 if (IsWin64) { 1962 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1963 // Get to the caller-allocated home save location. Add 8 to account 1964 // for the return address. 1965 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1966 FuncInfo->setRegSaveFrameIndex( 1967 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1968 // Fixup to set vararg frame on shadow area (4 x i64). 1969 if (NumIntRegs < 4) 1970 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1971 } else { 1972 // For X86-64, if there are vararg parameters that are passed via 1973 // registers, then we must store them to their spots on the stack so 1974 // they may be loaded by deferencing the result of va_next. 1975 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1976 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1977 FuncInfo->setRegSaveFrameIndex( 1978 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1979 false)); 1980 } 1981 1982 // Store the integer parameter registers. 1983 SmallVector<SDValue, 8> MemOps; 1984 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1985 getPointerTy()); 1986 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1987 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1988 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1989 DAG.getIntPtrConstant(Offset)); 1990 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1991 X86::GR64RegisterClass); 1992 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1993 SDValue Store = 1994 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1995 MachinePointerInfo::getFixedStack( 1996 FuncInfo->getRegSaveFrameIndex(), Offset), 1997 false, false, 0); 1998 MemOps.push_back(Store); 1999 Offset += 8; 2000 } 2001 2002 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2003 // Now store the XMM (fp + vector) parameter registers. 2004 SmallVector<SDValue, 11> SaveXMMOps; 2005 SaveXMMOps.push_back(Chain); 2006 2007 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2008 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2009 SaveXMMOps.push_back(ALVal); 2010 2011 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2012 FuncInfo->getRegSaveFrameIndex())); 2013 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2014 FuncInfo->getVarArgsFPOffset())); 2015 2016 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2017 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2018 X86::VR128RegisterClass); 2019 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2020 SaveXMMOps.push_back(Val); 2021 } 2022 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2023 MVT::Other, 2024 &SaveXMMOps[0], SaveXMMOps.size())); 2025 } 2026 2027 if (!MemOps.empty()) 2028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2029 &MemOps[0], MemOps.size()); 2030 } 2031 } 2032 2033 // Some CCs need callee pop. 2034 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2035 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2036 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2037 } else { 2038 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2039 // If this is an sret function, the return should pop the hidden pointer. 2040 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2041 ArgsAreStructReturn(Ins)) 2042 FuncInfo->setBytesToPopOnReturn(4); 2043 } 2044 2045 if (!Is64Bit) { 2046 // RegSaveFrameIndex is X86-64 only. 2047 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2048 if (CallConv == CallingConv::X86_FastCall || 2049 CallConv == CallingConv::X86_ThisCall) 2050 // fastcc functions can't have varargs. 2051 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2052 } 2053 2054 FuncInfo->setArgumentStackSize(StackSize); 2055 2056 return Chain; 2057} 2058 2059SDValue 2060X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2061 SDValue StackPtr, SDValue Arg, 2062 DebugLoc dl, SelectionDAG &DAG, 2063 const CCValAssign &VA, 2064 ISD::ArgFlagsTy Flags) const { 2065 unsigned LocMemOffset = VA.getLocMemOffset(); 2066 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2067 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2068 if (Flags.isByVal()) 2069 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2070 2071 return DAG.getStore(Chain, dl, Arg, PtrOff, 2072 MachinePointerInfo::getStack(LocMemOffset), 2073 false, false, 0); 2074} 2075 2076/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2077/// optimization is performed and it is required. 2078SDValue 2079X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2080 SDValue &OutRetAddr, SDValue Chain, 2081 bool IsTailCall, bool Is64Bit, 2082 int FPDiff, DebugLoc dl) const { 2083 // Adjust the Return address stack slot. 2084 EVT VT = getPointerTy(); 2085 OutRetAddr = getReturnAddressFrameIndex(DAG); 2086 2087 // Load the "old" Return address. 2088 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2089 false, false, false, 0); 2090 return SDValue(OutRetAddr.getNode(), 1); 2091} 2092 2093/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2094/// optimization is performed and it is required (FPDiff!=0). 2095static SDValue 2096EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2097 SDValue Chain, SDValue RetAddrFrIdx, 2098 bool Is64Bit, int FPDiff, DebugLoc dl) { 2099 // Store the return address to the appropriate stack slot. 2100 if (!FPDiff) return Chain; 2101 // Calculate the new stack slot for the return address. 2102 int SlotSize = Is64Bit ? 8 : 4; 2103 int NewReturnAddrFI = 2104 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2105 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2106 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2107 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2108 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2109 false, false, 0); 2110 return Chain; 2111} 2112 2113SDValue 2114X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2115 CallingConv::ID CallConv, bool isVarArg, 2116 bool &isTailCall, 2117 const SmallVectorImpl<ISD::OutputArg> &Outs, 2118 const SmallVectorImpl<SDValue> &OutVals, 2119 const SmallVectorImpl<ISD::InputArg> &Ins, 2120 DebugLoc dl, SelectionDAG &DAG, 2121 SmallVectorImpl<SDValue> &InVals) const { 2122 MachineFunction &MF = DAG.getMachineFunction(); 2123 bool Is64Bit = Subtarget->is64Bit(); 2124 bool IsWin64 = Subtarget->isTargetWin64(); 2125 bool IsWindows = Subtarget->isTargetWindows(); 2126 bool IsStructRet = CallIsStructReturn(Outs); 2127 bool IsSibcall = false; 2128 2129 if (MF.getTarget().Options.DisableTailCalls) 2130 isTailCall = false; 2131 2132 if (isTailCall) { 2133 // Check if it's really possible to do a tail call. 2134 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2135 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2136 Outs, OutVals, Ins, DAG); 2137 2138 // Sibcalls are automatically detected tailcalls which do not require 2139 // ABI changes. 2140 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2141 IsSibcall = true; 2142 2143 if (isTailCall) 2144 ++NumTailCalls; 2145 } 2146 2147 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2148 "Var args not supported with calling convention fastcc or ghc"); 2149 2150 // Analyze operands of the call, assigning locations to each operand. 2151 SmallVector<CCValAssign, 16> ArgLocs; 2152 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2153 ArgLocs, *DAG.getContext()); 2154 2155 // Allocate shadow area for Win64 2156 if (IsWin64) { 2157 CCInfo.AllocateStack(32, 8); 2158 } 2159 2160 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2161 2162 // Get a count of how many bytes are to be pushed on the stack. 2163 unsigned NumBytes = CCInfo.getNextStackOffset(); 2164 if (IsSibcall) 2165 // This is a sibcall. The memory operands are available in caller's 2166 // own caller's stack. 2167 NumBytes = 0; 2168 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2169 IsTailCallConvention(CallConv)) 2170 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2171 2172 int FPDiff = 0; 2173 if (isTailCall && !IsSibcall) { 2174 // Lower arguments at fp - stackoffset + fpdiff. 2175 unsigned NumBytesCallerPushed = 2176 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2177 FPDiff = NumBytesCallerPushed - NumBytes; 2178 2179 // Set the delta of movement of the returnaddr stackslot. 2180 // But only set if delta is greater than previous delta. 2181 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2182 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2183 } 2184 2185 if (!IsSibcall) 2186 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2187 2188 SDValue RetAddrFrIdx; 2189 // Load return address for tail calls. 2190 if (isTailCall && FPDiff) 2191 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2192 Is64Bit, FPDiff, dl); 2193 2194 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2195 SmallVector<SDValue, 8> MemOpChains; 2196 SDValue StackPtr; 2197 2198 // Walk the register/memloc assignments, inserting copies/loads. In the case 2199 // of tail call optimization arguments are handle later. 2200 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2201 CCValAssign &VA = ArgLocs[i]; 2202 EVT RegVT = VA.getLocVT(); 2203 SDValue Arg = OutVals[i]; 2204 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2205 bool isByVal = Flags.isByVal(); 2206 2207 // Promote the value if needed. 2208 switch (VA.getLocInfo()) { 2209 default: llvm_unreachable("Unknown loc info!"); 2210 case CCValAssign::Full: break; 2211 case CCValAssign::SExt: 2212 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2213 break; 2214 case CCValAssign::ZExt: 2215 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2216 break; 2217 case CCValAssign::AExt: 2218 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2219 // Special case: passing MMX values in XMM registers. 2220 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2221 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2222 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2223 } else 2224 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2225 break; 2226 case CCValAssign::BCvt: 2227 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2228 break; 2229 case CCValAssign::Indirect: { 2230 // Store the argument. 2231 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2232 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2233 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2234 MachinePointerInfo::getFixedStack(FI), 2235 false, false, 0); 2236 Arg = SpillSlot; 2237 break; 2238 } 2239 } 2240 2241 if (VA.isRegLoc()) { 2242 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2243 if (isVarArg && IsWin64) { 2244 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2245 // shadow reg if callee is a varargs function. 2246 unsigned ShadowReg = 0; 2247 switch (VA.getLocReg()) { 2248 case X86::XMM0: ShadowReg = X86::RCX; break; 2249 case X86::XMM1: ShadowReg = X86::RDX; break; 2250 case X86::XMM2: ShadowReg = X86::R8; break; 2251 case X86::XMM3: ShadowReg = X86::R9; break; 2252 } 2253 if (ShadowReg) 2254 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2255 } 2256 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2257 assert(VA.isMemLoc()); 2258 if (StackPtr.getNode() == 0) 2259 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2260 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2261 dl, DAG, VA, Flags)); 2262 } 2263 } 2264 2265 if (!MemOpChains.empty()) 2266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2267 &MemOpChains[0], MemOpChains.size()); 2268 2269 // Build a sequence of copy-to-reg nodes chained together with token chain 2270 // and flag operands which copy the outgoing args into registers. 2271 SDValue InFlag; 2272 // Tail call byval lowering might overwrite argument registers so in case of 2273 // tail call optimization the copies to registers are lowered later. 2274 if (!isTailCall) 2275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2276 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2277 RegsToPass[i].second, InFlag); 2278 InFlag = Chain.getValue(1); 2279 } 2280 2281 if (Subtarget->isPICStyleGOT()) { 2282 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2283 // GOT pointer. 2284 if (!isTailCall) { 2285 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2286 DAG.getNode(X86ISD::GlobalBaseReg, 2287 DebugLoc(), getPointerTy()), 2288 InFlag); 2289 InFlag = Chain.getValue(1); 2290 } else { 2291 // If we are tail calling and generating PIC/GOT style code load the 2292 // address of the callee into ECX. The value in ecx is used as target of 2293 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2294 // for tail calls on PIC/GOT architectures. Normally we would just put the 2295 // address of GOT into ebx and then call target@PLT. But for tail calls 2296 // ebx would be restored (since ebx is callee saved) before jumping to the 2297 // target@PLT. 2298 2299 // Note: The actual moving to ECX is done further down. 2300 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2301 if (G && !G->getGlobal()->hasHiddenVisibility() && 2302 !G->getGlobal()->hasProtectedVisibility()) 2303 Callee = LowerGlobalAddress(Callee, DAG); 2304 else if (isa<ExternalSymbolSDNode>(Callee)) 2305 Callee = LowerExternalSymbol(Callee, DAG); 2306 } 2307 } 2308 2309 if (Is64Bit && isVarArg && !IsWin64) { 2310 // From AMD64 ABI document: 2311 // For calls that may call functions that use varargs or stdargs 2312 // (prototype-less calls or calls to functions containing ellipsis (...) in 2313 // the declaration) %al is used as hidden argument to specify the number 2314 // of SSE registers used. The contents of %al do not need to match exactly 2315 // the number of registers, but must be an ubound on the number of SSE 2316 // registers used and is in the range 0 - 8 inclusive. 2317 2318 // Count the number of XMM registers allocated. 2319 static const unsigned XMMArgRegs[] = { 2320 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2321 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2322 }; 2323 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2324 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2325 && "SSE registers cannot be used when SSE is disabled"); 2326 2327 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2328 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2329 InFlag = Chain.getValue(1); 2330 } 2331 2332 2333 // For tail calls lower the arguments to the 'real' stack slot. 2334 if (isTailCall) { 2335 // Force all the incoming stack arguments to be loaded from the stack 2336 // before any new outgoing arguments are stored to the stack, because the 2337 // outgoing stack slots may alias the incoming argument stack slots, and 2338 // the alias isn't otherwise explicit. This is slightly more conservative 2339 // than necessary, because it means that each store effectively depends 2340 // on every argument instead of just those arguments it would clobber. 2341 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2342 2343 SmallVector<SDValue, 8> MemOpChains2; 2344 SDValue FIN; 2345 int FI = 0; 2346 // Do not flag preceding copytoreg stuff together with the following stuff. 2347 InFlag = SDValue(); 2348 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2349 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2350 CCValAssign &VA = ArgLocs[i]; 2351 if (VA.isRegLoc()) 2352 continue; 2353 assert(VA.isMemLoc()); 2354 SDValue Arg = OutVals[i]; 2355 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2356 // Create frame index. 2357 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2358 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2359 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2360 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2361 2362 if (Flags.isByVal()) { 2363 // Copy relative to framepointer. 2364 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2365 if (StackPtr.getNode() == 0) 2366 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2367 getPointerTy()); 2368 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2369 2370 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2371 ArgChain, 2372 Flags, DAG, dl)); 2373 } else { 2374 // Store relative to framepointer. 2375 MemOpChains2.push_back( 2376 DAG.getStore(ArgChain, dl, Arg, FIN, 2377 MachinePointerInfo::getFixedStack(FI), 2378 false, false, 0)); 2379 } 2380 } 2381 } 2382 2383 if (!MemOpChains2.empty()) 2384 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2385 &MemOpChains2[0], MemOpChains2.size()); 2386 2387 // Copy arguments to their registers. 2388 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2389 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2390 RegsToPass[i].second, InFlag); 2391 InFlag = Chain.getValue(1); 2392 } 2393 InFlag =SDValue(); 2394 2395 // Store the return address to the appropriate stack slot. 2396 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2397 FPDiff, dl); 2398 } 2399 2400 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2401 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2402 // In the 64-bit large code model, we have to make all calls 2403 // through a register, since the call instruction's 32-bit 2404 // pc-relative offset may not be large enough to hold the whole 2405 // address. 2406 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2407 // If the callee is a GlobalAddress node (quite common, every direct call 2408 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2409 // it. 2410 2411 // We should use extra load for direct calls to dllimported functions in 2412 // non-JIT mode. 2413 const GlobalValue *GV = G->getGlobal(); 2414 if (!GV->hasDLLImportLinkage()) { 2415 unsigned char OpFlags = 0; 2416 bool ExtraLoad = false; 2417 unsigned WrapperKind = ISD::DELETED_NODE; 2418 2419 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2420 // external symbols most go through the PLT in PIC mode. If the symbol 2421 // has hidden or protected visibility, or if it is static or local, then 2422 // we don't need to use the PLT - we can directly call it. 2423 if (Subtarget->isTargetELF() && 2424 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2425 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2426 OpFlags = X86II::MO_PLT; 2427 } else if (Subtarget->isPICStyleStubAny() && 2428 (GV->isDeclaration() || GV->isWeakForLinker()) && 2429 (!Subtarget->getTargetTriple().isMacOSX() || 2430 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2431 // PC-relative references to external symbols should go through $stub, 2432 // unless we're building with the leopard linker or later, which 2433 // automatically synthesizes these stubs. 2434 OpFlags = X86II::MO_DARWIN_STUB; 2435 } else if (Subtarget->isPICStyleRIPRel() && 2436 isa<Function>(GV) && 2437 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2438 // If the function is marked as non-lazy, generate an indirect call 2439 // which loads from the GOT directly. This avoids runtime overhead 2440 // at the cost of eager binding (and one extra byte of encoding). 2441 OpFlags = X86II::MO_GOTPCREL; 2442 WrapperKind = X86ISD::WrapperRIP; 2443 ExtraLoad = true; 2444 } 2445 2446 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2447 G->getOffset(), OpFlags); 2448 2449 // Add a wrapper if needed. 2450 if (WrapperKind != ISD::DELETED_NODE) 2451 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2452 // Add extra indirection if needed. 2453 if (ExtraLoad) 2454 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2455 MachinePointerInfo::getGOT(), 2456 false, false, false, 0); 2457 } 2458 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2459 unsigned char OpFlags = 0; 2460 2461 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2462 // external symbols should go through the PLT. 2463 if (Subtarget->isTargetELF() && 2464 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2465 OpFlags = X86II::MO_PLT; 2466 } else if (Subtarget->isPICStyleStubAny() && 2467 (!Subtarget->getTargetTriple().isMacOSX() || 2468 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2469 // PC-relative references to external symbols should go through $stub, 2470 // unless we're building with the leopard linker or later, which 2471 // automatically synthesizes these stubs. 2472 OpFlags = X86II::MO_DARWIN_STUB; 2473 } 2474 2475 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2476 OpFlags); 2477 } 2478 2479 // Returns a chain & a flag for retval copy to use. 2480 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2481 SmallVector<SDValue, 8> Ops; 2482 2483 if (!IsSibcall && isTailCall) { 2484 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2485 DAG.getIntPtrConstant(0, true), InFlag); 2486 InFlag = Chain.getValue(1); 2487 } 2488 2489 Ops.push_back(Chain); 2490 Ops.push_back(Callee); 2491 2492 if (isTailCall) 2493 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2494 2495 // Add argument registers to the end of the list so that they are known live 2496 // into the call. 2497 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2498 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2499 RegsToPass[i].second.getValueType())); 2500 2501 // Add an implicit use GOT pointer in EBX. 2502 if (!isTailCall && Subtarget->isPICStyleGOT()) 2503 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2504 2505 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2506 if (Is64Bit && isVarArg && !IsWin64) 2507 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2508 2509 // Add a register mask operand representing the call-preserved registers. 2510 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2511 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2512 assert(Mask && "Missing call preserved mask for calling convention"); 2513 Ops.push_back(DAG.getRegisterMask(Mask)); 2514 2515 if (InFlag.getNode()) 2516 Ops.push_back(InFlag); 2517 2518 if (isTailCall) { 2519 // We used to do: 2520 //// If this is the first return lowered for this function, add the regs 2521 //// to the liveout set for the function. 2522 // This isn't right, although it's probably harmless on x86; liveouts 2523 // should be computed from returns not tail calls. Consider a void 2524 // function making a tail call to a function returning int. 2525 return DAG.getNode(X86ISD::TC_RETURN, dl, 2526 NodeTys, &Ops[0], Ops.size()); 2527 } 2528 2529 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2530 InFlag = Chain.getValue(1); 2531 2532 // Create the CALLSEQ_END node. 2533 unsigned NumBytesForCalleeToPush; 2534 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2535 getTargetMachine().Options.GuaranteedTailCallOpt)) 2536 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2537 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2538 IsStructRet) 2539 // If this is a call to a struct-return function, the callee 2540 // pops the hidden struct pointer, so we have to push it back. 2541 // This is common for Darwin/X86, Linux & Mingw32 targets. 2542 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2543 NumBytesForCalleeToPush = 4; 2544 else 2545 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2546 2547 // Returns a flag for retval copy to use. 2548 if (!IsSibcall) { 2549 Chain = DAG.getCALLSEQ_END(Chain, 2550 DAG.getIntPtrConstant(NumBytes, true), 2551 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2552 true), 2553 InFlag); 2554 InFlag = Chain.getValue(1); 2555 } 2556 2557 // Handle result values, copying them out of physregs into vregs that we 2558 // return. 2559 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2560 Ins, dl, DAG, InVals); 2561} 2562 2563 2564//===----------------------------------------------------------------------===// 2565// Fast Calling Convention (tail call) implementation 2566//===----------------------------------------------------------------------===// 2567 2568// Like std call, callee cleans arguments, convention except that ECX is 2569// reserved for storing the tail called function address. Only 2 registers are 2570// free for argument passing (inreg). Tail call optimization is performed 2571// provided: 2572// * tailcallopt is enabled 2573// * caller/callee are fastcc 2574// On X86_64 architecture with GOT-style position independent code only local 2575// (within module) calls are supported at the moment. 2576// To keep the stack aligned according to platform abi the function 2577// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2578// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2579// If a tail called function callee has more arguments than the caller the 2580// caller needs to make sure that there is room to move the RETADDR to. This is 2581// achieved by reserving an area the size of the argument delta right after the 2582// original REtADDR, but before the saved framepointer or the spilled registers 2583// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2584// stack layout: 2585// arg1 2586// arg2 2587// RETADDR 2588// [ new RETADDR 2589// move area ] 2590// (possible EBP) 2591// ESI 2592// EDI 2593// local1 .. 2594 2595/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2596/// for a 16 byte align requirement. 2597unsigned 2598X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2599 SelectionDAG& DAG) const { 2600 MachineFunction &MF = DAG.getMachineFunction(); 2601 const TargetMachine &TM = MF.getTarget(); 2602 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2603 unsigned StackAlignment = TFI.getStackAlignment(); 2604 uint64_t AlignMask = StackAlignment - 1; 2605 int64_t Offset = StackSize; 2606 uint64_t SlotSize = TD->getPointerSize(); 2607 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2608 // Number smaller than 12 so just add the difference. 2609 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2610 } else { 2611 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2612 Offset = ((~AlignMask) & Offset) + StackAlignment + 2613 (StackAlignment-SlotSize); 2614 } 2615 return Offset; 2616} 2617 2618/// MatchingStackOffset - Return true if the given stack call argument is 2619/// already available in the same position (relatively) of the caller's 2620/// incoming argument stack. 2621static 2622bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2623 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2624 const X86InstrInfo *TII) { 2625 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2626 int FI = INT_MAX; 2627 if (Arg.getOpcode() == ISD::CopyFromReg) { 2628 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2629 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2630 return false; 2631 MachineInstr *Def = MRI->getVRegDef(VR); 2632 if (!Def) 2633 return false; 2634 if (!Flags.isByVal()) { 2635 if (!TII->isLoadFromStackSlot(Def, FI)) 2636 return false; 2637 } else { 2638 unsigned Opcode = Def->getOpcode(); 2639 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2640 Def->getOperand(1).isFI()) { 2641 FI = Def->getOperand(1).getIndex(); 2642 Bytes = Flags.getByValSize(); 2643 } else 2644 return false; 2645 } 2646 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2647 if (Flags.isByVal()) 2648 // ByVal argument is passed in as a pointer but it's now being 2649 // dereferenced. e.g. 2650 // define @foo(%struct.X* %A) { 2651 // tail call @bar(%struct.X* byval %A) 2652 // } 2653 return false; 2654 SDValue Ptr = Ld->getBasePtr(); 2655 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2656 if (!FINode) 2657 return false; 2658 FI = FINode->getIndex(); 2659 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2660 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2661 FI = FINode->getIndex(); 2662 Bytes = Flags.getByValSize(); 2663 } else 2664 return false; 2665 2666 assert(FI != INT_MAX); 2667 if (!MFI->isFixedObjectIndex(FI)) 2668 return false; 2669 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2670} 2671 2672/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2673/// for tail call optimization. Targets which want to do tail call 2674/// optimization should implement this function. 2675bool 2676X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2677 CallingConv::ID CalleeCC, 2678 bool isVarArg, 2679 bool isCalleeStructRet, 2680 bool isCallerStructRet, 2681 const SmallVectorImpl<ISD::OutputArg> &Outs, 2682 const SmallVectorImpl<SDValue> &OutVals, 2683 const SmallVectorImpl<ISD::InputArg> &Ins, 2684 SelectionDAG& DAG) const { 2685 if (!IsTailCallConvention(CalleeCC) && 2686 CalleeCC != CallingConv::C) 2687 return false; 2688 2689 // If -tailcallopt is specified, make fastcc functions tail-callable. 2690 const MachineFunction &MF = DAG.getMachineFunction(); 2691 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2692 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2693 bool CCMatch = CallerCC == CalleeCC; 2694 2695 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2696 if (IsTailCallConvention(CalleeCC) && CCMatch) 2697 return true; 2698 return false; 2699 } 2700 2701 // Look for obvious safe cases to perform tail call optimization that do not 2702 // require ABI changes. This is what gcc calls sibcall. 2703 2704 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2705 // emit a special epilogue. 2706 if (RegInfo->needsStackRealignment(MF)) 2707 return false; 2708 2709 // Also avoid sibcall optimization if either caller or callee uses struct 2710 // return semantics. 2711 if (isCalleeStructRet || isCallerStructRet) 2712 return false; 2713 2714 // An stdcall caller is expected to clean up its arguments; the callee 2715 // isn't going to do that. 2716 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2717 return false; 2718 2719 // Do not sibcall optimize vararg calls unless all arguments are passed via 2720 // registers. 2721 if (isVarArg && !Outs.empty()) { 2722 2723 // Optimizing for varargs on Win64 is unlikely to be safe without 2724 // additional testing. 2725 if (Subtarget->isTargetWin64()) 2726 return false; 2727 2728 SmallVector<CCValAssign, 16> ArgLocs; 2729 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2730 getTargetMachine(), ArgLocs, *DAG.getContext()); 2731 2732 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2733 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2734 if (!ArgLocs[i].isRegLoc()) 2735 return false; 2736 } 2737 2738 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2739 // stack. Therefore, if it's not used by the call it is not safe to optimize 2740 // this into a sibcall. 2741 bool Unused = false; 2742 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2743 if (!Ins[i].Used) { 2744 Unused = true; 2745 break; 2746 } 2747 } 2748 if (Unused) { 2749 SmallVector<CCValAssign, 16> RVLocs; 2750 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2751 getTargetMachine(), RVLocs, *DAG.getContext()); 2752 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2753 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2754 CCValAssign &VA = RVLocs[i]; 2755 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2756 return false; 2757 } 2758 } 2759 2760 // If the calling conventions do not match, then we'd better make sure the 2761 // results are returned in the same way as what the caller expects. 2762 if (!CCMatch) { 2763 SmallVector<CCValAssign, 16> RVLocs1; 2764 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2765 getTargetMachine(), RVLocs1, *DAG.getContext()); 2766 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2767 2768 SmallVector<CCValAssign, 16> RVLocs2; 2769 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2770 getTargetMachine(), RVLocs2, *DAG.getContext()); 2771 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2772 2773 if (RVLocs1.size() != RVLocs2.size()) 2774 return false; 2775 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2776 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2777 return false; 2778 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2779 return false; 2780 if (RVLocs1[i].isRegLoc()) { 2781 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2782 return false; 2783 } else { 2784 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2785 return false; 2786 } 2787 } 2788 } 2789 2790 // If the callee takes no arguments then go on to check the results of the 2791 // call. 2792 if (!Outs.empty()) { 2793 // Check if stack adjustment is needed. For now, do not do this if any 2794 // argument is passed on the stack. 2795 SmallVector<CCValAssign, 16> ArgLocs; 2796 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2797 getTargetMachine(), ArgLocs, *DAG.getContext()); 2798 2799 // Allocate shadow area for Win64 2800 if (Subtarget->isTargetWin64()) { 2801 CCInfo.AllocateStack(32, 8); 2802 } 2803 2804 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2805 if (CCInfo.getNextStackOffset()) { 2806 MachineFunction &MF = DAG.getMachineFunction(); 2807 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2808 return false; 2809 2810 // Check if the arguments are already laid out in the right way as 2811 // the caller's fixed stack objects. 2812 MachineFrameInfo *MFI = MF.getFrameInfo(); 2813 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2814 const X86InstrInfo *TII = 2815 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2816 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2817 CCValAssign &VA = ArgLocs[i]; 2818 SDValue Arg = OutVals[i]; 2819 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2820 if (VA.getLocInfo() == CCValAssign::Indirect) 2821 return false; 2822 if (!VA.isRegLoc()) { 2823 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2824 MFI, MRI, TII)) 2825 return false; 2826 } 2827 } 2828 } 2829 2830 // If the tailcall address may be in a register, then make sure it's 2831 // possible to register allocate for it. In 32-bit, the call address can 2832 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2833 // callee-saved registers are restored. These happen to be the same 2834 // registers used to pass 'inreg' arguments so watch out for those. 2835 if (!Subtarget->is64Bit() && 2836 !isa<GlobalAddressSDNode>(Callee) && 2837 !isa<ExternalSymbolSDNode>(Callee)) { 2838 unsigned NumInRegs = 0; 2839 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2840 CCValAssign &VA = ArgLocs[i]; 2841 if (!VA.isRegLoc()) 2842 continue; 2843 unsigned Reg = VA.getLocReg(); 2844 switch (Reg) { 2845 default: break; 2846 case X86::EAX: case X86::EDX: case X86::ECX: 2847 if (++NumInRegs == 3) 2848 return false; 2849 break; 2850 } 2851 } 2852 } 2853 } 2854 2855 return true; 2856} 2857 2858FastISel * 2859X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2860 return X86::createFastISel(funcInfo); 2861} 2862 2863 2864//===----------------------------------------------------------------------===// 2865// Other Lowering Hooks 2866//===----------------------------------------------------------------------===// 2867 2868static bool MayFoldLoad(SDValue Op) { 2869 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2870} 2871 2872static bool MayFoldIntoStore(SDValue Op) { 2873 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2874} 2875 2876static bool isTargetShuffle(unsigned Opcode) { 2877 switch(Opcode) { 2878 default: return false; 2879 case X86ISD::PSHUFD: 2880 case X86ISD::PSHUFHW: 2881 case X86ISD::PSHUFLW: 2882 case X86ISD::SHUFP: 2883 case X86ISD::PALIGN: 2884 case X86ISD::MOVLHPS: 2885 case X86ISD::MOVLHPD: 2886 case X86ISD::MOVHLPS: 2887 case X86ISD::MOVLPS: 2888 case X86ISD::MOVLPD: 2889 case X86ISD::MOVSHDUP: 2890 case X86ISD::MOVSLDUP: 2891 case X86ISD::MOVDDUP: 2892 case X86ISD::MOVSS: 2893 case X86ISD::MOVSD: 2894 case X86ISD::UNPCKL: 2895 case X86ISD::UNPCKH: 2896 case X86ISD::VPERMILP: 2897 case X86ISD::VPERM2X128: 2898 return true; 2899 } 2900} 2901 2902static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2903 SDValue V1, SelectionDAG &DAG) { 2904 switch(Opc) { 2905 default: llvm_unreachable("Unknown x86 shuffle node"); 2906 case X86ISD::MOVSHDUP: 2907 case X86ISD::MOVSLDUP: 2908 case X86ISD::MOVDDUP: 2909 return DAG.getNode(Opc, dl, VT, V1); 2910 } 2911} 2912 2913static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2914 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2915 switch(Opc) { 2916 default: llvm_unreachable("Unknown x86 shuffle node"); 2917 case X86ISD::PSHUFD: 2918 case X86ISD::PSHUFHW: 2919 case X86ISD::PSHUFLW: 2920 case X86ISD::VPERMILP: 2921 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2922 } 2923} 2924 2925static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2926 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2927 switch(Opc) { 2928 default: llvm_unreachable("Unknown x86 shuffle node"); 2929 case X86ISD::PALIGN: 2930 case X86ISD::SHUFP: 2931 case X86ISD::VPERM2X128: 2932 return DAG.getNode(Opc, dl, VT, V1, V2, 2933 DAG.getConstant(TargetMask, MVT::i8)); 2934 } 2935} 2936 2937static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2938 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2939 switch(Opc) { 2940 default: llvm_unreachable("Unknown x86 shuffle node"); 2941 case X86ISD::MOVLHPS: 2942 case X86ISD::MOVLHPD: 2943 case X86ISD::MOVHLPS: 2944 case X86ISD::MOVLPS: 2945 case X86ISD::MOVLPD: 2946 case X86ISD::MOVSS: 2947 case X86ISD::MOVSD: 2948 case X86ISD::UNPCKL: 2949 case X86ISD::UNPCKH: 2950 return DAG.getNode(Opc, dl, VT, V1, V2); 2951 } 2952} 2953 2954SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2955 MachineFunction &MF = DAG.getMachineFunction(); 2956 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2957 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2958 2959 if (ReturnAddrIndex == 0) { 2960 // Set up a frame object for the return address. 2961 uint64_t SlotSize = TD->getPointerSize(); 2962 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2963 false); 2964 FuncInfo->setRAIndex(ReturnAddrIndex); 2965 } 2966 2967 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2968} 2969 2970 2971bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2972 bool hasSymbolicDisplacement) { 2973 // Offset should fit into 32 bit immediate field. 2974 if (!isInt<32>(Offset)) 2975 return false; 2976 2977 // If we don't have a symbolic displacement - we don't have any extra 2978 // restrictions. 2979 if (!hasSymbolicDisplacement) 2980 return true; 2981 2982 // FIXME: Some tweaks might be needed for medium code model. 2983 if (M != CodeModel::Small && M != CodeModel::Kernel) 2984 return false; 2985 2986 // For small code model we assume that latest object is 16MB before end of 31 2987 // bits boundary. We may also accept pretty large negative constants knowing 2988 // that all objects are in the positive half of address space. 2989 if (M == CodeModel::Small && Offset < 16*1024*1024) 2990 return true; 2991 2992 // For kernel code model we know that all object resist in the negative half 2993 // of 32bits address space. We may not accept negative offsets, since they may 2994 // be just off and we may accept pretty large positive ones. 2995 if (M == CodeModel::Kernel && Offset > 0) 2996 return true; 2997 2998 return false; 2999} 3000 3001/// isCalleePop - Determines whether the callee is required to pop its 3002/// own arguments. Callee pop is necessary to support tail calls. 3003bool X86::isCalleePop(CallingConv::ID CallingConv, 3004 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3005 if (IsVarArg) 3006 return false; 3007 3008 switch (CallingConv) { 3009 default: 3010 return false; 3011 case CallingConv::X86_StdCall: 3012 return !is64Bit; 3013 case CallingConv::X86_FastCall: 3014 return !is64Bit; 3015 case CallingConv::X86_ThisCall: 3016 return !is64Bit; 3017 case CallingConv::Fast: 3018 return TailCallOpt; 3019 case CallingConv::GHC: 3020 return TailCallOpt; 3021 } 3022} 3023 3024/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3025/// specific condition code, returning the condition code and the LHS/RHS of the 3026/// comparison to make. 3027static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3028 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3029 if (!isFP) { 3030 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3031 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3032 // X > -1 -> X == 0, jump !sign. 3033 RHS = DAG.getConstant(0, RHS.getValueType()); 3034 return X86::COND_NS; 3035 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3036 // X < 0 -> X == 0, jump on sign. 3037 return X86::COND_S; 3038 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3039 // X < 1 -> X <= 0 3040 RHS = DAG.getConstant(0, RHS.getValueType()); 3041 return X86::COND_LE; 3042 } 3043 } 3044 3045 switch (SetCCOpcode) { 3046 default: llvm_unreachable("Invalid integer condition!"); 3047 case ISD::SETEQ: return X86::COND_E; 3048 case ISD::SETGT: return X86::COND_G; 3049 case ISD::SETGE: return X86::COND_GE; 3050 case ISD::SETLT: return X86::COND_L; 3051 case ISD::SETLE: return X86::COND_LE; 3052 case ISD::SETNE: return X86::COND_NE; 3053 case ISD::SETULT: return X86::COND_B; 3054 case ISD::SETUGT: return X86::COND_A; 3055 case ISD::SETULE: return X86::COND_BE; 3056 case ISD::SETUGE: return X86::COND_AE; 3057 } 3058 } 3059 3060 // First determine if it is required or is profitable to flip the operands. 3061 3062 // If LHS is a foldable load, but RHS is not, flip the condition. 3063 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3064 !ISD::isNON_EXTLoad(RHS.getNode())) { 3065 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3066 std::swap(LHS, RHS); 3067 } 3068 3069 switch (SetCCOpcode) { 3070 default: break; 3071 case ISD::SETOLT: 3072 case ISD::SETOLE: 3073 case ISD::SETUGT: 3074 case ISD::SETUGE: 3075 std::swap(LHS, RHS); 3076 break; 3077 } 3078 3079 // On a floating point condition, the flags are set as follows: 3080 // ZF PF CF op 3081 // 0 | 0 | 0 | X > Y 3082 // 0 | 0 | 1 | X < Y 3083 // 1 | 0 | 0 | X == Y 3084 // 1 | 1 | 1 | unordered 3085 switch (SetCCOpcode) { 3086 default: llvm_unreachable("Condcode should be pre-legalized away"); 3087 case ISD::SETUEQ: 3088 case ISD::SETEQ: return X86::COND_E; 3089 case ISD::SETOLT: // flipped 3090 case ISD::SETOGT: 3091 case ISD::SETGT: return X86::COND_A; 3092 case ISD::SETOLE: // flipped 3093 case ISD::SETOGE: 3094 case ISD::SETGE: return X86::COND_AE; 3095 case ISD::SETUGT: // flipped 3096 case ISD::SETULT: 3097 case ISD::SETLT: return X86::COND_B; 3098 case ISD::SETUGE: // flipped 3099 case ISD::SETULE: 3100 case ISD::SETLE: return X86::COND_BE; 3101 case ISD::SETONE: 3102 case ISD::SETNE: return X86::COND_NE; 3103 case ISD::SETUO: return X86::COND_P; 3104 case ISD::SETO: return X86::COND_NP; 3105 case ISD::SETOEQ: 3106 case ISD::SETUNE: return X86::COND_INVALID; 3107 } 3108} 3109 3110/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3111/// code. Current x86 isa includes the following FP cmov instructions: 3112/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3113static bool hasFPCMov(unsigned X86CC) { 3114 switch (X86CC) { 3115 default: 3116 return false; 3117 case X86::COND_B: 3118 case X86::COND_BE: 3119 case X86::COND_E: 3120 case X86::COND_P: 3121 case X86::COND_A: 3122 case X86::COND_AE: 3123 case X86::COND_NE: 3124 case X86::COND_NP: 3125 return true; 3126 } 3127} 3128 3129/// isFPImmLegal - Returns true if the target can instruction select the 3130/// specified FP immediate natively. If false, the legalizer will 3131/// materialize the FP immediate as a load from a constant pool. 3132bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3133 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3134 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3135 return true; 3136 } 3137 return false; 3138} 3139 3140/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3141/// the specified range (L, H]. 3142static bool isUndefOrInRange(int Val, int Low, int Hi) { 3143 return (Val < 0) || (Val >= Low && Val < Hi); 3144} 3145 3146/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3147/// specified value. 3148static bool isUndefOrEqual(int Val, int CmpVal) { 3149 if (Val < 0 || Val == CmpVal) 3150 return true; 3151 return false; 3152} 3153 3154/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3155/// from position Pos and ending in Pos+Size, falls within the specified 3156/// sequential range (L, L+Pos]. or is undef. 3157static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3158 int Pos, int Size, int Low) { 3159 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3160 if (!isUndefOrEqual(Mask[i], Low)) 3161 return false; 3162 return true; 3163} 3164 3165/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3166/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3167/// the second operand. 3168static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3169 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3170 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3171 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3172 return (Mask[0] < 2 && Mask[1] < 2); 3173 return false; 3174} 3175 3176/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3177/// is suitable for input to PSHUFHW. 3178static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3179 if (VT != MVT::v8i16) 3180 return false; 3181 3182 // Lower quadword copied in order or undef. 3183 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3184 return false; 3185 3186 // Upper quadword shuffled. 3187 for (unsigned i = 4; i != 8; ++i) 3188 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3189 return false; 3190 3191 return true; 3192} 3193 3194/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3195/// is suitable for input to PSHUFLW. 3196static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3197 if (VT != MVT::v8i16) 3198 return false; 3199 3200 // Upper quadword copied in order. 3201 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3202 return false; 3203 3204 // Lower quadword shuffled. 3205 for (unsigned i = 0; i != 4; ++i) 3206 if (Mask[i] >= 4) 3207 return false; 3208 3209 return true; 3210} 3211 3212/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3213/// is suitable for input to PALIGNR. 3214static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3215 const X86Subtarget *Subtarget) { 3216 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3217 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3218 return false; 3219 3220 unsigned NumElts = VT.getVectorNumElements(); 3221 unsigned NumLanes = VT.getSizeInBits()/128; 3222 unsigned NumLaneElts = NumElts/NumLanes; 3223 3224 // Do not handle 64-bit element shuffles with palignr. 3225 if (NumLaneElts == 2) 3226 return false; 3227 3228 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3229 unsigned i; 3230 for (i = 0; i != NumLaneElts; ++i) { 3231 if (Mask[i+l] >= 0) 3232 break; 3233 } 3234 3235 // Lane is all undef, go to next lane 3236 if (i == NumLaneElts) 3237 continue; 3238 3239 int Start = Mask[i+l]; 3240 3241 // Make sure its in this lane in one of the sources 3242 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3243 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3244 return false; 3245 3246 // If not lane 0, then we must match lane 0 3247 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3248 return false; 3249 3250 // Correct second source to be contiguous with first source 3251 if (Start >= (int)NumElts) 3252 Start -= NumElts - NumLaneElts; 3253 3254 // Make sure we're shifting in the right direction. 3255 if (Start <= (int)(i+l)) 3256 return false; 3257 3258 Start -= i; 3259 3260 // Check the rest of the elements to see if they are consecutive. 3261 for (++i; i != NumLaneElts; ++i) { 3262 int Idx = Mask[i+l]; 3263 3264 // Make sure its in this lane 3265 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3266 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3267 return false; 3268 3269 // If not lane 0, then we must match lane 0 3270 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3271 return false; 3272 3273 if (Idx >= (int)NumElts) 3274 Idx -= NumElts - NumLaneElts; 3275 3276 if (!isUndefOrEqual(Idx, Start+i)) 3277 return false; 3278 3279 } 3280 } 3281 3282 return true; 3283} 3284 3285/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3286/// the two vector operands have swapped position. 3287static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3288 unsigned NumElems) { 3289 for (unsigned i = 0; i != NumElems; ++i) { 3290 int idx = Mask[i]; 3291 if (idx < 0) 3292 continue; 3293 else if (idx < (int)NumElems) 3294 Mask[i] = idx + NumElems; 3295 else 3296 Mask[i] = idx - NumElems; 3297 } 3298} 3299 3300/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3301/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3302/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3303/// reverse of what x86 shuffles want. 3304static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3305 bool Commuted = false) { 3306 if (!HasAVX && VT.getSizeInBits() == 256) 3307 return false; 3308 3309 unsigned NumElems = VT.getVectorNumElements(); 3310 unsigned NumLanes = VT.getSizeInBits()/128; 3311 unsigned NumLaneElems = NumElems/NumLanes; 3312 3313 if (NumLaneElems != 2 && NumLaneElems != 4) 3314 return false; 3315 3316 // VSHUFPSY divides the resulting vector into 4 chunks. 3317 // The sources are also splitted into 4 chunks, and each destination 3318 // chunk must come from a different source chunk. 3319 // 3320 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3321 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3322 // 3323 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3324 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3325 // 3326 // VSHUFPDY divides the resulting vector into 4 chunks. 3327 // The sources are also splitted into 4 chunks, and each destination 3328 // chunk must come from a different source chunk. 3329 // 3330 // SRC1 => X3 X2 X1 X0 3331 // SRC2 => Y3 Y2 Y1 Y0 3332 // 3333 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3334 // 3335 unsigned HalfLaneElems = NumLaneElems/2; 3336 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3337 for (unsigned i = 0; i != NumLaneElems; ++i) { 3338 int Idx = Mask[i+l]; 3339 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3340 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3341 return false; 3342 // For VSHUFPSY, the mask of the second half must be the same as the 3343 // first but with the appropriate offsets. This works in the same way as 3344 // VPERMILPS works with masks. 3345 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3346 continue; 3347 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3348 return false; 3349 } 3350 } 3351 3352 return true; 3353} 3354 3355/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3356/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3357static bool isMOVHLPSMask(ShuffleVectorSDNode *N) { 3358 EVT VT = N->getValueType(0); 3359 unsigned NumElems = VT.getVectorNumElements(); 3360 3361 if (VT.getSizeInBits() != 128) 3362 return false; 3363 3364 if (NumElems != 4) 3365 return false; 3366 3367 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3368 return isUndefOrEqual(N->getMaskElt(0), 6) && 3369 isUndefOrEqual(N->getMaskElt(1), 7) && 3370 isUndefOrEqual(N->getMaskElt(2), 2) && 3371 isUndefOrEqual(N->getMaskElt(3), 3); 3372} 3373 3374/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3375/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3376/// <2, 3, 2, 3> 3377static bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3378 EVT VT = N->getValueType(0); 3379 unsigned NumElems = VT.getVectorNumElements(); 3380 3381 if (VT.getSizeInBits() != 128) 3382 return false; 3383 3384 if (NumElems != 4) 3385 return false; 3386 3387 return isUndefOrEqual(N->getMaskElt(0), 2) && 3388 isUndefOrEqual(N->getMaskElt(1), 3) && 3389 isUndefOrEqual(N->getMaskElt(2), 2) && 3390 isUndefOrEqual(N->getMaskElt(3), 3); 3391} 3392 3393/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3394/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3395static bool isMOVLPMask(ShuffleVectorSDNode *N) { 3396 EVT VT = N->getValueType(0); 3397 3398 if (VT.getSizeInBits() != 128) 3399 return false; 3400 3401 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3402 3403 if (NumElems != 2 && NumElems != 4) 3404 return false; 3405 3406 for (unsigned i = 0; i < NumElems/2; ++i) 3407 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3408 return false; 3409 3410 for (unsigned i = NumElems/2; i < NumElems; ++i) 3411 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3412 return false; 3413 3414 return true; 3415} 3416 3417/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3418/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3419static bool isMOVLHPSMask(ShuffleVectorSDNode *N) { 3420 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3421 3422 if ((NumElems != 2 && NumElems != 4) 3423 || N->getValueType(0).getSizeInBits() > 128) 3424 return false; 3425 3426 for (unsigned i = 0; i < NumElems/2; ++i) 3427 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3428 return false; 3429 3430 for (unsigned i = 0; i < NumElems/2; ++i) 3431 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3432 return false; 3433 3434 return true; 3435} 3436 3437/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3438/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3439static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3440 bool HasAVX2, bool V2IsSplat = false) { 3441 unsigned NumElts = VT.getVectorNumElements(); 3442 3443 assert((VT.is128BitVector() || VT.is256BitVector()) && 3444 "Unsupported vector type for unpckh"); 3445 3446 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3447 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3448 return false; 3449 3450 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3451 // independently on 128-bit lanes. 3452 unsigned NumLanes = VT.getSizeInBits()/128; 3453 unsigned NumLaneElts = NumElts/NumLanes; 3454 3455 for (unsigned l = 0; l != NumLanes; ++l) { 3456 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3457 i != (l+1)*NumLaneElts; 3458 i += 2, ++j) { 3459 int BitI = Mask[i]; 3460 int BitI1 = Mask[i+1]; 3461 if (!isUndefOrEqual(BitI, j)) 3462 return false; 3463 if (V2IsSplat) { 3464 if (!isUndefOrEqual(BitI1, NumElts)) 3465 return false; 3466 } else { 3467 if (!isUndefOrEqual(BitI1, j + NumElts)) 3468 return false; 3469 } 3470 } 3471 } 3472 3473 return true; 3474} 3475 3476/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3477/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3478static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3479 bool HasAVX2, bool V2IsSplat = false) { 3480 unsigned NumElts = VT.getVectorNumElements(); 3481 3482 assert((VT.is128BitVector() || VT.is256BitVector()) && 3483 "Unsupported vector type for unpckh"); 3484 3485 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3486 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3487 return false; 3488 3489 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3490 // independently on 128-bit lanes. 3491 unsigned NumLanes = VT.getSizeInBits()/128; 3492 unsigned NumLaneElts = NumElts/NumLanes; 3493 3494 for (unsigned l = 0; l != NumLanes; ++l) { 3495 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3496 i != (l+1)*NumLaneElts; i += 2, ++j) { 3497 int BitI = Mask[i]; 3498 int BitI1 = Mask[i+1]; 3499 if (!isUndefOrEqual(BitI, j)) 3500 return false; 3501 if (V2IsSplat) { 3502 if (isUndefOrEqual(BitI1, NumElts)) 3503 return false; 3504 } else { 3505 if (!isUndefOrEqual(BitI1, j+NumElts)) 3506 return false; 3507 } 3508 } 3509 } 3510 return true; 3511} 3512 3513/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3514/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3515/// <0, 0, 1, 1> 3516static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3517 bool HasAVX2) { 3518 unsigned NumElts = VT.getVectorNumElements(); 3519 3520 assert((VT.is128BitVector() || VT.is256BitVector()) && 3521 "Unsupported vector type for unpckh"); 3522 3523 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3524 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3525 return false; 3526 3527 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3528 // FIXME: Need a better way to get rid of this, there's no latency difference 3529 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3530 // the former later. We should also remove the "_undef" special mask. 3531 if (NumElts == 4 && VT.getSizeInBits() == 256) 3532 return false; 3533 3534 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3535 // independently on 128-bit lanes. 3536 unsigned NumLanes = VT.getSizeInBits()/128; 3537 unsigned NumLaneElts = NumElts/NumLanes; 3538 3539 for (unsigned l = 0; l != NumLanes; ++l) { 3540 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3541 i != (l+1)*NumLaneElts; 3542 i += 2, ++j) { 3543 int BitI = Mask[i]; 3544 int BitI1 = Mask[i+1]; 3545 3546 if (!isUndefOrEqual(BitI, j)) 3547 return false; 3548 if (!isUndefOrEqual(BitI1, j)) 3549 return false; 3550 } 3551 } 3552 3553 return true; 3554} 3555 3556/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3557/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3558/// <2, 2, 3, 3> 3559static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3560 unsigned NumElts = VT.getVectorNumElements(); 3561 3562 assert((VT.is128BitVector() || VT.is256BitVector()) && 3563 "Unsupported vector type for unpckh"); 3564 3565 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3566 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3567 return false; 3568 3569 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3570 // independently on 128-bit lanes. 3571 unsigned NumLanes = VT.getSizeInBits()/128; 3572 unsigned NumLaneElts = NumElts/NumLanes; 3573 3574 for (unsigned l = 0; l != NumLanes; ++l) { 3575 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3576 i != (l+1)*NumLaneElts; i += 2, ++j) { 3577 int BitI = Mask[i]; 3578 int BitI1 = Mask[i+1]; 3579 if (!isUndefOrEqual(BitI, j)) 3580 return false; 3581 if (!isUndefOrEqual(BitI1, j)) 3582 return false; 3583 } 3584 } 3585 return true; 3586} 3587 3588/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3589/// specifies a shuffle of elements that is suitable for input to MOVSS, 3590/// MOVSD, and MOVD, i.e. setting the lowest element. 3591static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3592 if (VT.getVectorElementType().getSizeInBits() < 32) 3593 return false; 3594 if (VT.getSizeInBits() == 256) 3595 return false; 3596 3597 unsigned NumElts = VT.getVectorNumElements(); 3598 3599 if (!isUndefOrEqual(Mask[0], NumElts)) 3600 return false; 3601 3602 for (unsigned i = 1; i != NumElts; ++i) 3603 if (!isUndefOrEqual(Mask[i], i)) 3604 return false; 3605 3606 return true; 3607} 3608 3609/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3610/// as permutations between 128-bit chunks or halves. As an example: this 3611/// shuffle bellow: 3612/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3613/// The first half comes from the second half of V1 and the second half from the 3614/// the second half of V2. 3615static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3616 if (!HasAVX || VT.getSizeInBits() != 256) 3617 return false; 3618 3619 // The shuffle result is divided into half A and half B. In total the two 3620 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3621 // B must come from C, D, E or F. 3622 unsigned HalfSize = VT.getVectorNumElements()/2; 3623 bool MatchA = false, MatchB = false; 3624 3625 // Check if A comes from one of C, D, E, F. 3626 for (unsigned Half = 0; Half != 4; ++Half) { 3627 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3628 MatchA = true; 3629 break; 3630 } 3631 } 3632 3633 // Check if B comes from one of C, D, E, F. 3634 for (unsigned Half = 0; Half != 4; ++Half) { 3635 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3636 MatchB = true; 3637 break; 3638 } 3639 } 3640 3641 return MatchA && MatchB; 3642} 3643 3644/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3645/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3646static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3647 EVT VT = SVOp->getValueType(0); 3648 3649 unsigned HalfSize = VT.getVectorNumElements()/2; 3650 3651 unsigned FstHalf = 0, SndHalf = 0; 3652 for (unsigned i = 0; i < HalfSize; ++i) { 3653 if (SVOp->getMaskElt(i) > 0) { 3654 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3655 break; 3656 } 3657 } 3658 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3659 if (SVOp->getMaskElt(i) > 0) { 3660 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3661 break; 3662 } 3663 } 3664 3665 return (FstHalf | (SndHalf << 4)); 3666} 3667 3668/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3669/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3670/// Note that VPERMIL mask matching is different depending whether theunderlying 3671/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3672/// to the same elements of the low, but to the higher half of the source. 3673/// In VPERMILPD the two lanes could be shuffled independently of each other 3674/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3675static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3676 if (!HasAVX) 3677 return false; 3678 3679 unsigned NumElts = VT.getVectorNumElements(); 3680 // Only match 256-bit with 32/64-bit types 3681 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3682 return false; 3683 3684 unsigned NumLanes = VT.getSizeInBits()/128; 3685 unsigned LaneSize = NumElts/NumLanes; 3686 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3687 for (unsigned i = 0; i != LaneSize; ++i) { 3688 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3689 return false; 3690 if (NumElts != 8 || l == 0) 3691 continue; 3692 // VPERMILPS handling 3693 if (Mask[i] < 0) 3694 continue; 3695 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3696 return false; 3697 } 3698 } 3699 3700 return true; 3701} 3702 3703/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3704/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3705/// element of vector 2 and the other elements to come from vector 1 in order. 3706static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3707 bool V2IsSplat = false, bool V2IsUndef = false) { 3708 unsigned NumOps = VT.getVectorNumElements(); 3709 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3710 return false; 3711 3712 if (!isUndefOrEqual(Mask[0], 0)) 3713 return false; 3714 3715 for (unsigned i = 1; i != NumOps; ++i) 3716 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3717 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3718 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3719 return false; 3720 3721 return true; 3722} 3723 3724/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3725/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3726/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3727static bool isMOVSHDUPMask(ShuffleVectorSDNode *N, 3728 const X86Subtarget *Subtarget) { 3729 if (!Subtarget->hasSSE3()) 3730 return false; 3731 3732 // The second vector must be undef 3733 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3734 return false; 3735 3736 EVT VT = N->getValueType(0); 3737 unsigned NumElems = VT.getVectorNumElements(); 3738 3739 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3740 (VT.getSizeInBits() == 256 && NumElems != 8)) 3741 return false; 3742 3743 // "i+1" is the value the indexed mask element must have 3744 for (unsigned i = 0; i < NumElems; i += 2) 3745 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3746 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3747 return false; 3748 3749 return true; 3750} 3751 3752/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3753/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3754/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3755static bool isMOVSLDUPMask(ShuffleVectorSDNode *N, 3756 const X86Subtarget *Subtarget) { 3757 if (!Subtarget->hasSSE3()) 3758 return false; 3759 3760 // The second vector must be undef 3761 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3762 return false; 3763 3764 EVT VT = N->getValueType(0); 3765 unsigned NumElems = VT.getVectorNumElements(); 3766 3767 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3768 (VT.getSizeInBits() == 256 && NumElems != 8)) 3769 return false; 3770 3771 // "i" is the value the indexed mask element must have 3772 for (unsigned i = 0; i != NumElems; i += 2) 3773 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3774 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3775 return false; 3776 3777 return true; 3778} 3779 3780/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3781/// specifies a shuffle of elements that is suitable for input to 256-bit 3782/// version of MOVDDUP. 3783static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3784 unsigned NumElts = VT.getVectorNumElements(); 3785 3786 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3787 return false; 3788 3789 for (unsigned i = 0; i != NumElts/2; ++i) 3790 if (!isUndefOrEqual(Mask[i], 0)) 3791 return false; 3792 for (unsigned i = NumElts/2; i != NumElts; ++i) 3793 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3794 return false; 3795 return true; 3796} 3797 3798/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3799/// specifies a shuffle of elements that is suitable for input to 128-bit 3800/// version of MOVDDUP. 3801static bool isMOVDDUPMask(ShuffleVectorSDNode *N) { 3802 EVT VT = N->getValueType(0); 3803 3804 if (VT.getSizeInBits() != 128) 3805 return false; 3806 3807 unsigned e = VT.getVectorNumElements() / 2; 3808 for (unsigned i = 0; i != e; ++i) 3809 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3810 return false; 3811 for (unsigned i = 0; i != e; ++i) 3812 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3813 return false; 3814 return true; 3815} 3816 3817/// isVEXTRACTF128Index - Return true if the specified 3818/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3819/// suitable for input to VEXTRACTF128. 3820bool X86::isVEXTRACTF128Index(SDNode *N) { 3821 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3822 return false; 3823 3824 // The index should be aligned on a 128-bit boundary. 3825 uint64_t Index = 3826 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3827 3828 unsigned VL = N->getValueType(0).getVectorNumElements(); 3829 unsigned VBits = N->getValueType(0).getSizeInBits(); 3830 unsigned ElSize = VBits / VL; 3831 bool Result = (Index * ElSize) % 128 == 0; 3832 3833 return Result; 3834} 3835 3836/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3837/// operand specifies a subvector insert that is suitable for input to 3838/// VINSERTF128. 3839bool X86::isVINSERTF128Index(SDNode *N) { 3840 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3841 return false; 3842 3843 // The index should be aligned on a 128-bit boundary. 3844 uint64_t Index = 3845 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3846 3847 unsigned VL = N->getValueType(0).getVectorNumElements(); 3848 unsigned VBits = N->getValueType(0).getSizeInBits(); 3849 unsigned ElSize = VBits / VL; 3850 bool Result = (Index * ElSize) % 128 == 0; 3851 3852 return Result; 3853} 3854 3855/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3856/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3857/// Handles 128-bit and 256-bit. 3858static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3859 EVT VT = N->getValueType(0); 3860 3861 assert((VT.is128BitVector() || VT.is256BitVector()) && 3862 "Unsupported vector type for PSHUF/SHUFP"); 3863 3864 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3865 // independently on 128-bit lanes. 3866 unsigned NumElts = VT.getVectorNumElements(); 3867 unsigned NumLanes = VT.getSizeInBits()/128; 3868 unsigned NumLaneElts = NumElts/NumLanes; 3869 3870 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3871 "Only supports 2 or 4 elements per lane"); 3872 3873 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3874 unsigned Mask = 0; 3875 for (unsigned i = 0; i != NumElts; ++i) { 3876 int Elt = N->getMaskElt(i); 3877 if (Elt < 0) continue; 3878 Elt %= NumLaneElts; 3879 unsigned ShAmt = i << Shift; 3880 if (ShAmt >= 8) ShAmt -= 8; 3881 Mask |= Elt << ShAmt; 3882 } 3883 3884 return Mask; 3885} 3886 3887/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3888/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3889static unsigned getShufflePSHUFHWImmediate(SDNode *N) { 3890 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3891 unsigned Mask = 0; 3892 // 8 nodes, but we only care about the last 4. 3893 for (unsigned i = 7; i >= 4; --i) { 3894 int Val = SVOp->getMaskElt(i); 3895 if (Val >= 0) 3896 Mask |= (Val - 4); 3897 if (i != 4) 3898 Mask <<= 2; 3899 } 3900 return Mask; 3901} 3902 3903/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3904/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3905static unsigned getShufflePSHUFLWImmediate(SDNode *N) { 3906 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3907 unsigned Mask = 0; 3908 // 8 nodes, but we only care about the first 4. 3909 for (int i = 3; i >= 0; --i) { 3910 int Val = SVOp->getMaskElt(i); 3911 if (Val >= 0) 3912 Mask |= Val; 3913 if (i != 0) 3914 Mask <<= 2; 3915 } 3916 return Mask; 3917} 3918 3919/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3920/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3921static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3922 EVT VT = SVOp->getValueType(0); 3923 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3924 3925 unsigned NumElts = VT.getVectorNumElements(); 3926 unsigned NumLanes = VT.getSizeInBits()/128; 3927 unsigned NumLaneElts = NumElts/NumLanes; 3928 3929 int Val = 0; 3930 unsigned i; 3931 for (i = 0; i != NumElts; ++i) { 3932 Val = SVOp->getMaskElt(i); 3933 if (Val >= 0) 3934 break; 3935 } 3936 if (Val >= (int)NumElts) 3937 Val -= NumElts - NumLaneElts; 3938 3939 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3940 return (Val - i) * EltSize; 3941} 3942 3943/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3944/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3945/// instructions. 3946unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3947 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3948 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3949 3950 uint64_t Index = 3951 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3952 3953 EVT VecVT = N->getOperand(0).getValueType(); 3954 EVT ElVT = VecVT.getVectorElementType(); 3955 3956 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3957 return Index / NumElemsPerChunk; 3958} 3959 3960/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3961/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3962/// instructions. 3963unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3964 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3965 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3966 3967 uint64_t Index = 3968 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3969 3970 EVT VecVT = N->getValueType(0); 3971 EVT ElVT = VecVT.getVectorElementType(); 3972 3973 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3974 return Index / NumElemsPerChunk; 3975} 3976 3977/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3978/// constant +0.0. 3979bool X86::isZeroNode(SDValue Elt) { 3980 return ((isa<ConstantSDNode>(Elt) && 3981 cast<ConstantSDNode>(Elt)->isNullValue()) || 3982 (isa<ConstantFPSDNode>(Elt) && 3983 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3984} 3985 3986/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3987/// their permute mask. 3988static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3989 SelectionDAG &DAG) { 3990 EVT VT = SVOp->getValueType(0); 3991 unsigned NumElems = VT.getVectorNumElements(); 3992 SmallVector<int, 8> MaskVec; 3993 3994 for (unsigned i = 0; i != NumElems; ++i) { 3995 int idx = SVOp->getMaskElt(i); 3996 if (idx < 0) 3997 MaskVec.push_back(idx); 3998 else if (idx < (int)NumElems) 3999 MaskVec.push_back(idx + NumElems); 4000 else 4001 MaskVec.push_back(idx - NumElems); 4002 } 4003 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4004 SVOp->getOperand(0), &MaskVec[0]); 4005} 4006 4007/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4008/// match movhlps. The lower half elements should come from upper half of 4009/// V1 (and in order), and the upper half elements should come from the upper 4010/// half of V2 (and in order). 4011static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4012 EVT VT = Op->getValueType(0); 4013 if (VT.getSizeInBits() != 128) 4014 return false; 4015 if (VT.getVectorNumElements() != 4) 4016 return false; 4017 for (unsigned i = 0, e = 2; i != e; ++i) 4018 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4019 return false; 4020 for (unsigned i = 2; i != 4; ++i) 4021 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4022 return false; 4023 return true; 4024} 4025 4026/// isScalarLoadToVector - Returns true if the node is a scalar load that 4027/// is promoted to a vector. It also returns the LoadSDNode by reference if 4028/// required. 4029static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4030 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4031 return false; 4032 N = N->getOperand(0).getNode(); 4033 if (!ISD::isNON_EXTLoad(N)) 4034 return false; 4035 if (LD) 4036 *LD = cast<LoadSDNode>(N); 4037 return true; 4038} 4039 4040// Test whether the given value is a vector value which will be legalized 4041// into a load. 4042static bool WillBeConstantPoolLoad(SDNode *N) { 4043 if (N->getOpcode() != ISD::BUILD_VECTOR) 4044 return false; 4045 4046 // Check for any non-constant elements. 4047 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4048 switch (N->getOperand(i).getNode()->getOpcode()) { 4049 case ISD::UNDEF: 4050 case ISD::ConstantFP: 4051 case ISD::Constant: 4052 break; 4053 default: 4054 return false; 4055 } 4056 4057 // Vectors of all-zeros and all-ones are materialized with special 4058 // instructions rather than being loaded. 4059 return !ISD::isBuildVectorAllZeros(N) && 4060 !ISD::isBuildVectorAllOnes(N); 4061} 4062 4063/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4064/// match movlp{s|d}. The lower half elements should come from lower half of 4065/// V1 (and in order), and the upper half elements should come from the upper 4066/// half of V2 (and in order). And since V1 will become the source of the 4067/// MOVLP, it must be either a vector load or a scalar load to vector. 4068static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4069 ShuffleVectorSDNode *Op) { 4070 EVT VT = Op->getValueType(0); 4071 if (VT.getSizeInBits() != 128) 4072 return false; 4073 4074 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4075 return false; 4076 // Is V2 is a vector load, don't do this transformation. We will try to use 4077 // load folding shufps op. 4078 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4079 return false; 4080 4081 unsigned NumElems = VT.getVectorNumElements(); 4082 4083 if (NumElems != 2 && NumElems != 4) 4084 return false; 4085 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4086 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4087 return false; 4088 for (unsigned i = NumElems/2; i != NumElems; ++i) 4089 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4090 return false; 4091 return true; 4092} 4093 4094/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4095/// all the same. 4096static bool isSplatVector(SDNode *N) { 4097 if (N->getOpcode() != ISD::BUILD_VECTOR) 4098 return false; 4099 4100 SDValue SplatValue = N->getOperand(0); 4101 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4102 if (N->getOperand(i) != SplatValue) 4103 return false; 4104 return true; 4105} 4106 4107/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4108/// to an zero vector. 4109/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4110static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4111 SDValue V1 = N->getOperand(0); 4112 SDValue V2 = N->getOperand(1); 4113 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4114 for (unsigned i = 0; i != NumElems; ++i) { 4115 int Idx = N->getMaskElt(i); 4116 if (Idx >= (int)NumElems) { 4117 unsigned Opc = V2.getOpcode(); 4118 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4119 continue; 4120 if (Opc != ISD::BUILD_VECTOR || 4121 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4122 return false; 4123 } else if (Idx >= 0) { 4124 unsigned Opc = V1.getOpcode(); 4125 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4126 continue; 4127 if (Opc != ISD::BUILD_VECTOR || 4128 !X86::isZeroNode(V1.getOperand(Idx))) 4129 return false; 4130 } 4131 } 4132 return true; 4133} 4134 4135/// getZeroVector - Returns a vector of specified type with all zero elements. 4136/// 4137static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4138 SelectionDAG &DAG, DebugLoc dl) { 4139 assert(VT.isVector() && "Expected a vector type"); 4140 4141 // Always build SSE zero vectors as <4 x i32> bitcasted 4142 // to their dest type. This ensures they get CSE'd. 4143 SDValue Vec; 4144 if (VT.getSizeInBits() == 128) { // SSE 4145 if (Subtarget->hasSSE2()) { // SSE2 4146 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4148 } else { // SSE1 4149 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4150 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4151 } 4152 } else if (VT.getSizeInBits() == 256) { // AVX 4153 if (Subtarget->hasAVX2()) { // AVX2 4154 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4155 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4157 } else { 4158 // 256-bit logic and arithmetic instructions in AVX are all 4159 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4160 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4161 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4163 } 4164 } 4165 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4166} 4167 4168/// getOnesVector - Returns a vector of specified type with all bits set. 4169/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4170/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4171/// Then bitcast to their original type, ensuring they get CSE'd. 4172static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4173 DebugLoc dl) { 4174 assert(VT.isVector() && "Expected a vector type"); 4175 assert((VT.is128BitVector() || VT.is256BitVector()) 4176 && "Expected a 128-bit or 256-bit vector type"); 4177 4178 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4179 SDValue Vec; 4180 if (VT.getSizeInBits() == 256) { 4181 if (HasAVX2) { // AVX2 4182 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4183 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4184 } else { // AVX 4185 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4186 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4187 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4188 Vec = Insert128BitVector(InsV, Vec, 4189 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4190 } 4191 } else { 4192 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4193 } 4194 4195 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4196} 4197 4198/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4199/// that point to V2 points to its first element. 4200static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4201 for (unsigned i = 0; i != NumElems; ++i) { 4202 if (Mask[i] > (int)NumElems) { 4203 Mask[i] = NumElems; 4204 } 4205 } 4206} 4207 4208/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4209/// operation of specified width. 4210static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4211 SDValue V2) { 4212 unsigned NumElems = VT.getVectorNumElements(); 4213 SmallVector<int, 8> Mask; 4214 Mask.push_back(NumElems); 4215 for (unsigned i = 1; i != NumElems; ++i) 4216 Mask.push_back(i); 4217 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4218} 4219 4220/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4221static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4222 SDValue V2) { 4223 unsigned NumElems = VT.getVectorNumElements(); 4224 SmallVector<int, 8> Mask; 4225 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4226 Mask.push_back(i); 4227 Mask.push_back(i + NumElems); 4228 } 4229 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4230} 4231 4232/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4233static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4234 SDValue V2) { 4235 unsigned NumElems = VT.getVectorNumElements(); 4236 unsigned Half = NumElems/2; 4237 SmallVector<int, 8> Mask; 4238 for (unsigned i = 0; i != Half; ++i) { 4239 Mask.push_back(i + Half); 4240 Mask.push_back(i + NumElems + Half); 4241 } 4242 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4243} 4244 4245// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4246// a generic shuffle instruction because the target has no such instructions. 4247// Generate shuffles which repeat i16 and i8 several times until they can be 4248// represented by v4f32 and then be manipulated by target suported shuffles. 4249static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4250 EVT VT = V.getValueType(); 4251 int NumElems = VT.getVectorNumElements(); 4252 DebugLoc dl = V.getDebugLoc(); 4253 4254 while (NumElems > 4) { 4255 if (EltNo < NumElems/2) { 4256 V = getUnpackl(DAG, dl, VT, V, V); 4257 } else { 4258 V = getUnpackh(DAG, dl, VT, V, V); 4259 EltNo -= NumElems/2; 4260 } 4261 NumElems >>= 1; 4262 } 4263 return V; 4264} 4265 4266/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4267static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4268 EVT VT = V.getValueType(); 4269 DebugLoc dl = V.getDebugLoc(); 4270 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4271 && "Vector size not supported"); 4272 4273 if (VT.getSizeInBits() == 128) { 4274 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4275 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4276 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4277 &SplatMask[0]); 4278 } else { 4279 // To use VPERMILPS to splat scalars, the second half of indicies must 4280 // refer to the higher part, which is a duplication of the lower one, 4281 // because VPERMILPS can only handle in-lane permutations. 4282 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4283 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4284 4285 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4286 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4287 &SplatMask[0]); 4288 } 4289 4290 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4291} 4292 4293/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4294static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4295 EVT SrcVT = SV->getValueType(0); 4296 SDValue V1 = SV->getOperand(0); 4297 DebugLoc dl = SV->getDebugLoc(); 4298 4299 int EltNo = SV->getSplatIndex(); 4300 int NumElems = SrcVT.getVectorNumElements(); 4301 unsigned Size = SrcVT.getSizeInBits(); 4302 4303 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4304 "Unknown how to promote splat for type"); 4305 4306 // Extract the 128-bit part containing the splat element and update 4307 // the splat element index when it refers to the higher register. 4308 if (Size == 256) { 4309 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4310 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4311 if (Idx > 0) 4312 EltNo -= NumElems/2; 4313 } 4314 4315 // All i16 and i8 vector types can't be used directly by a generic shuffle 4316 // instruction because the target has no such instruction. Generate shuffles 4317 // which repeat i16 and i8 several times until they fit in i32, and then can 4318 // be manipulated by target suported shuffles. 4319 EVT EltVT = SrcVT.getVectorElementType(); 4320 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4321 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4322 4323 // Recreate the 256-bit vector and place the same 128-bit vector 4324 // into the low and high part. This is necessary because we want 4325 // to use VPERM* to shuffle the vectors 4326 if (Size == 256) { 4327 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4328 DAG.getConstant(0, MVT::i32), DAG, dl); 4329 V1 = Insert128BitVector(InsV, V1, 4330 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4331 } 4332 4333 return getLegalSplat(DAG, V1, EltNo); 4334} 4335 4336/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4337/// vector of zero or undef vector. This produces a shuffle where the low 4338/// element of V2 is swizzled into the zero/undef vector, landing at element 4339/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4340static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4341 bool IsZero, 4342 const X86Subtarget *Subtarget, 4343 SelectionDAG &DAG) { 4344 EVT VT = V2.getValueType(); 4345 SDValue V1 = IsZero 4346 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4347 unsigned NumElems = VT.getVectorNumElements(); 4348 SmallVector<int, 16> MaskVec; 4349 for (unsigned i = 0; i != NumElems; ++i) 4350 // If this is the insertion idx, put the low elt of V2 here. 4351 MaskVec.push_back(i == Idx ? NumElems : i); 4352 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4353} 4354 4355/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4356/// element of the result of the vector shuffle. 4357static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4358 unsigned Depth) { 4359 if (Depth == 6) 4360 return SDValue(); // Limit search depth. 4361 4362 SDValue V = SDValue(N, 0); 4363 EVT VT = V.getValueType(); 4364 unsigned Opcode = V.getOpcode(); 4365 4366 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4367 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4368 Index = SV->getMaskElt(Index); 4369 4370 if (Index < 0) 4371 return DAG.getUNDEF(VT.getVectorElementType()); 4372 4373 unsigned NumElems = VT.getVectorNumElements(); 4374 SDValue NewV = (Index < (int)NumElems) ? SV->getOperand(0) 4375 : SV->getOperand(1); 4376 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4377 } 4378 4379 // Recurse into target specific vector shuffles to find scalars. 4380 if (isTargetShuffle(Opcode)) { 4381 unsigned NumElems = VT.getVectorNumElements(); 4382 SmallVector<unsigned, 16> ShuffleMask; 4383 SDValue ImmN; 4384 4385 switch(Opcode) { 4386 case X86ISD::SHUFP: 4387 ImmN = N->getOperand(N->getNumOperands()-1); 4388 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4389 ShuffleMask); 4390 break; 4391 case X86ISD::UNPCKH: 4392 DecodeUNPCKHMask(VT, ShuffleMask); 4393 break; 4394 case X86ISD::UNPCKL: 4395 DecodeUNPCKLMask(VT, ShuffleMask); 4396 break; 4397 case X86ISD::MOVHLPS: 4398 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4399 break; 4400 case X86ISD::MOVLHPS: 4401 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4402 break; 4403 case X86ISD::PSHUFD: 4404 case X86ISD::VPERMILP: 4405 ImmN = N->getOperand(N->getNumOperands()-1); 4406 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4407 ShuffleMask); 4408 break; 4409 case X86ISD::PSHUFHW: 4410 ImmN = N->getOperand(N->getNumOperands()-1); 4411 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4412 ShuffleMask); 4413 break; 4414 case X86ISD::PSHUFLW: 4415 ImmN = N->getOperand(N->getNumOperands()-1); 4416 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4417 ShuffleMask); 4418 break; 4419 case X86ISD::MOVSS: 4420 case X86ISD::MOVSD: { 4421 // The index 0 always comes from the first element of the second source, 4422 // this is why MOVSS and MOVSD are used in the first place. The other 4423 // elements come from the other positions of the first source vector. 4424 unsigned OpNum = (Index == 0) ? 1 : 0; 4425 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4426 Depth+1); 4427 } 4428 case X86ISD::VPERM2X128: 4429 ImmN = N->getOperand(N->getNumOperands()-1); 4430 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4431 ShuffleMask); 4432 break; 4433 case X86ISD::MOVDDUP: 4434 case X86ISD::MOVLHPD: 4435 case X86ISD::MOVLPD: 4436 case X86ISD::MOVLPS: 4437 case X86ISD::MOVSHDUP: 4438 case X86ISD::MOVSLDUP: 4439 case X86ISD::PALIGN: 4440 return SDValue(); // Not yet implemented. 4441 default: llvm_unreachable("unknown target shuffle node"); 4442 } 4443 4444 Index = ShuffleMask[Index]; 4445 if (Index < 0) 4446 return DAG.getUNDEF(VT.getVectorElementType()); 4447 4448 SDValue NewV = (Index < (int)NumElems) ? N->getOperand(0) 4449 : N->getOperand(1); 4450 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4451 Depth+1); 4452 } 4453 4454 // Actual nodes that may contain scalar elements 4455 if (Opcode == ISD::BITCAST) { 4456 V = V.getOperand(0); 4457 EVT SrcVT = V.getValueType(); 4458 unsigned NumElems = VT.getVectorNumElements(); 4459 4460 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4461 return SDValue(); 4462 } 4463 4464 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4465 return (Index == 0) ? V.getOperand(0) 4466 : DAG.getUNDEF(VT.getVectorElementType()); 4467 4468 if (V.getOpcode() == ISD::BUILD_VECTOR) 4469 return V.getOperand(Index); 4470 4471 return SDValue(); 4472} 4473 4474/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4475/// shuffle operation which come from a consecutively from a zero. The 4476/// search can start in two different directions, from left or right. 4477static 4478unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4479 bool ZerosFromLeft, SelectionDAG &DAG) { 4480 int i = 0; 4481 4482 while (i < NumElems) { 4483 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4484 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4485 if (!(Elt.getNode() && 4486 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4487 break; 4488 ++i; 4489 } 4490 4491 return i; 4492} 4493 4494/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4495/// MaskE correspond consecutively to elements from one of the vector operands, 4496/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4497static 4498bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4499 int OpIdx, int NumElems, unsigned &OpNum) { 4500 bool SeenV1 = false; 4501 bool SeenV2 = false; 4502 4503 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4504 int Idx = SVOp->getMaskElt(i); 4505 // Ignore undef indicies 4506 if (Idx < 0) 4507 continue; 4508 4509 if (Idx < NumElems) 4510 SeenV1 = true; 4511 else 4512 SeenV2 = true; 4513 4514 // Only accept consecutive elements from the same vector 4515 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4516 return false; 4517 } 4518 4519 OpNum = SeenV1 ? 0 : 1; 4520 return true; 4521} 4522 4523/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4524/// logical left shift of a vector. 4525static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4526 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4527 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4528 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4529 false /* check zeros from right */, DAG); 4530 unsigned OpSrc; 4531 4532 if (!NumZeros) 4533 return false; 4534 4535 // Considering the elements in the mask that are not consecutive zeros, 4536 // check if they consecutively come from only one of the source vectors. 4537 // 4538 // V1 = {X, A, B, C} 0 4539 // \ \ \ / 4540 // vector_shuffle V1, V2 <1, 2, 3, X> 4541 // 4542 if (!isShuffleMaskConsecutive(SVOp, 4543 0, // Mask Start Index 4544 NumElems-NumZeros-1, // Mask End Index 4545 NumZeros, // Where to start looking in the src vector 4546 NumElems, // Number of elements in vector 4547 OpSrc)) // Which source operand ? 4548 return false; 4549 4550 isLeft = false; 4551 ShAmt = NumZeros; 4552 ShVal = SVOp->getOperand(OpSrc); 4553 return true; 4554} 4555 4556/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4557/// logical left shift of a vector. 4558static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4559 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4560 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4561 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4562 true /* check zeros from left */, DAG); 4563 unsigned OpSrc; 4564 4565 if (!NumZeros) 4566 return false; 4567 4568 // Considering the elements in the mask that are not consecutive zeros, 4569 // check if they consecutively come from only one of the source vectors. 4570 // 4571 // 0 { A, B, X, X } = V2 4572 // / \ / / 4573 // vector_shuffle V1, V2 <X, X, 4, 5> 4574 // 4575 if (!isShuffleMaskConsecutive(SVOp, 4576 NumZeros, // Mask Start Index 4577 NumElems-1, // Mask End Index 4578 0, // Where to start looking in the src vector 4579 NumElems, // Number of elements in vector 4580 OpSrc)) // Which source operand ? 4581 return false; 4582 4583 isLeft = true; 4584 ShAmt = NumZeros; 4585 ShVal = SVOp->getOperand(OpSrc); 4586 return true; 4587} 4588 4589/// isVectorShift - Returns true if the shuffle can be implemented as a 4590/// logical left or right shift of a vector. 4591static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4592 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4593 // Although the logic below support any bitwidth size, there are no 4594 // shift instructions which handle more than 128-bit vectors. 4595 if (SVOp->getValueType(0).getSizeInBits() > 128) 4596 return false; 4597 4598 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4599 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4600 return true; 4601 4602 return false; 4603} 4604 4605/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4606/// 4607static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4608 unsigned NumNonZero, unsigned NumZero, 4609 SelectionDAG &DAG, 4610 const X86Subtarget* Subtarget, 4611 const TargetLowering &TLI) { 4612 if (NumNonZero > 8) 4613 return SDValue(); 4614 4615 DebugLoc dl = Op.getDebugLoc(); 4616 SDValue V(0, 0); 4617 bool First = true; 4618 for (unsigned i = 0; i < 16; ++i) { 4619 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4620 if (ThisIsNonZero && First) { 4621 if (NumZero) 4622 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4623 else 4624 V = DAG.getUNDEF(MVT::v8i16); 4625 First = false; 4626 } 4627 4628 if ((i & 1) != 0) { 4629 SDValue ThisElt(0, 0), LastElt(0, 0); 4630 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4631 if (LastIsNonZero) { 4632 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4633 MVT::i16, Op.getOperand(i-1)); 4634 } 4635 if (ThisIsNonZero) { 4636 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4637 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4638 ThisElt, DAG.getConstant(8, MVT::i8)); 4639 if (LastIsNonZero) 4640 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4641 } else 4642 ThisElt = LastElt; 4643 4644 if (ThisElt.getNode()) 4645 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4646 DAG.getIntPtrConstant(i/2)); 4647 } 4648 } 4649 4650 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4651} 4652 4653/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4654/// 4655static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4656 unsigned NumNonZero, unsigned NumZero, 4657 SelectionDAG &DAG, 4658 const X86Subtarget* Subtarget, 4659 const TargetLowering &TLI) { 4660 if (NumNonZero > 4) 4661 return SDValue(); 4662 4663 DebugLoc dl = Op.getDebugLoc(); 4664 SDValue V(0, 0); 4665 bool First = true; 4666 for (unsigned i = 0; i < 8; ++i) { 4667 bool isNonZero = (NonZeros & (1 << i)) != 0; 4668 if (isNonZero) { 4669 if (First) { 4670 if (NumZero) 4671 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4672 else 4673 V = DAG.getUNDEF(MVT::v8i16); 4674 First = false; 4675 } 4676 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4677 MVT::v8i16, V, Op.getOperand(i), 4678 DAG.getIntPtrConstant(i)); 4679 } 4680 } 4681 4682 return V; 4683} 4684 4685/// getVShift - Return a vector logical shift node. 4686/// 4687static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4688 unsigned NumBits, SelectionDAG &DAG, 4689 const TargetLowering &TLI, DebugLoc dl) { 4690 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4691 EVT ShVT = MVT::v2i64; 4692 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4693 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4694 return DAG.getNode(ISD::BITCAST, dl, VT, 4695 DAG.getNode(Opc, dl, ShVT, SrcOp, 4696 DAG.getConstant(NumBits, 4697 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4698} 4699 4700SDValue 4701X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4702 SelectionDAG &DAG) const { 4703 4704 // Check if the scalar load can be widened into a vector load. And if 4705 // the address is "base + cst" see if the cst can be "absorbed" into 4706 // the shuffle mask. 4707 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4708 SDValue Ptr = LD->getBasePtr(); 4709 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4710 return SDValue(); 4711 EVT PVT = LD->getValueType(0); 4712 if (PVT != MVT::i32 && PVT != MVT::f32) 4713 return SDValue(); 4714 4715 int FI = -1; 4716 int64_t Offset = 0; 4717 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4718 FI = FINode->getIndex(); 4719 Offset = 0; 4720 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4721 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4722 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4723 Offset = Ptr.getConstantOperandVal(1); 4724 Ptr = Ptr.getOperand(0); 4725 } else { 4726 return SDValue(); 4727 } 4728 4729 // FIXME: 256-bit vector instructions don't require a strict alignment, 4730 // improve this code to support it better. 4731 unsigned RequiredAlign = VT.getSizeInBits()/8; 4732 SDValue Chain = LD->getChain(); 4733 // Make sure the stack object alignment is at least 16 or 32. 4734 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4735 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4736 if (MFI->isFixedObjectIndex(FI)) { 4737 // Can't change the alignment. FIXME: It's possible to compute 4738 // the exact stack offset and reference FI + adjust offset instead. 4739 // If someone *really* cares about this. That's the way to implement it. 4740 return SDValue(); 4741 } else { 4742 MFI->setObjectAlignment(FI, RequiredAlign); 4743 } 4744 } 4745 4746 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4747 // Ptr + (Offset & ~15). 4748 if (Offset < 0) 4749 return SDValue(); 4750 if ((Offset % RequiredAlign) & 3) 4751 return SDValue(); 4752 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4753 if (StartOffset) 4754 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4755 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4756 4757 int EltNo = (Offset - StartOffset) >> 2; 4758 int NumElems = VT.getVectorNumElements(); 4759 4760 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4761 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4762 LD->getPointerInfo().getWithOffset(StartOffset), 4763 false, false, false, 0); 4764 4765 SmallVector<int, 8> Mask; 4766 for (int i = 0; i < NumElems; ++i) 4767 Mask.push_back(EltNo); 4768 4769 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4770 } 4771 4772 return SDValue(); 4773} 4774 4775/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4776/// vector of type 'VT', see if the elements can be replaced by a single large 4777/// load which has the same value as a build_vector whose operands are 'elts'. 4778/// 4779/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4780/// 4781/// FIXME: we'd also like to handle the case where the last elements are zero 4782/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4783/// There's even a handy isZeroNode for that purpose. 4784static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4785 DebugLoc &DL, SelectionDAG &DAG) { 4786 EVT EltVT = VT.getVectorElementType(); 4787 unsigned NumElems = Elts.size(); 4788 4789 LoadSDNode *LDBase = NULL; 4790 unsigned LastLoadedElt = -1U; 4791 4792 // For each element in the initializer, see if we've found a load or an undef. 4793 // If we don't find an initial load element, or later load elements are 4794 // non-consecutive, bail out. 4795 for (unsigned i = 0; i < NumElems; ++i) { 4796 SDValue Elt = Elts[i]; 4797 4798 if (!Elt.getNode() || 4799 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4800 return SDValue(); 4801 if (!LDBase) { 4802 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4803 return SDValue(); 4804 LDBase = cast<LoadSDNode>(Elt.getNode()); 4805 LastLoadedElt = i; 4806 continue; 4807 } 4808 if (Elt.getOpcode() == ISD::UNDEF) 4809 continue; 4810 4811 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4812 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4813 return SDValue(); 4814 LastLoadedElt = i; 4815 } 4816 4817 // If we have found an entire vector of loads and undefs, then return a large 4818 // load of the entire vector width starting at the base pointer. If we found 4819 // consecutive loads for the low half, generate a vzext_load node. 4820 if (LastLoadedElt == NumElems - 1) { 4821 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4822 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4823 LDBase->getPointerInfo(), 4824 LDBase->isVolatile(), LDBase->isNonTemporal(), 4825 LDBase->isInvariant(), 0); 4826 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4827 LDBase->getPointerInfo(), 4828 LDBase->isVolatile(), LDBase->isNonTemporal(), 4829 LDBase->isInvariant(), LDBase->getAlignment()); 4830 } else if (NumElems == 4 && LastLoadedElt == 1 && 4831 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4832 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4833 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4834 SDValue ResNode = 4835 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4836 LDBase->getPointerInfo(), 4837 LDBase->getAlignment(), 4838 false/*isVolatile*/, true/*ReadMem*/, 4839 false/*WriteMem*/); 4840 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4841 } 4842 return SDValue(); 4843} 4844 4845/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4846/// a vbroadcast node. We support two patterns: 4847/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4848/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4849/// a scalar load. 4850/// The scalar load node is returned when a pattern is found, 4851/// or SDValue() otherwise. 4852static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) { 4853 if (!Subtarget->hasAVX()) 4854 return SDValue(); 4855 4856 EVT VT = Op.getValueType(); 4857 SDValue V = Op; 4858 4859 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4860 V = V.getOperand(0); 4861 4862 //A suspected load to be broadcasted. 4863 SDValue Ld; 4864 4865 switch (V.getOpcode()) { 4866 default: 4867 // Unknown pattern found. 4868 return SDValue(); 4869 4870 case ISD::BUILD_VECTOR: { 4871 // The BUILD_VECTOR node must be a splat. 4872 if (!isSplatVector(V.getNode())) 4873 return SDValue(); 4874 4875 Ld = V.getOperand(0); 4876 4877 // The suspected load node has several users. Make sure that all 4878 // of its users are from the BUILD_VECTOR node. 4879 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4880 return SDValue(); 4881 break; 4882 } 4883 4884 case ISD::VECTOR_SHUFFLE: { 4885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4886 4887 // Shuffles must have a splat mask where the first element is 4888 // broadcasted. 4889 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4890 return SDValue(); 4891 4892 SDValue Sc = Op.getOperand(0); 4893 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4894 return SDValue(); 4895 4896 Ld = Sc.getOperand(0); 4897 4898 // The scalar_to_vector node and the suspected 4899 // load node must have exactly one user. 4900 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 4901 return SDValue(); 4902 break; 4903 } 4904 } 4905 4906 // The scalar source must be a normal load. 4907 if (!ISD::isNormalLoad(Ld.getNode())) 4908 return SDValue(); 4909 4910 // Reject loads that have uses of the chain result 4911 if (Ld->hasAnyUseOfValue(1)) 4912 return SDValue(); 4913 4914 bool Is256 = VT.getSizeInBits() == 256; 4915 bool Is128 = VT.getSizeInBits() == 128; 4916 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4917 4918 // VBroadcast to YMM 4919 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4920 return Ld; 4921 4922 // VBroadcast to XMM 4923 if (Is128 && (ScalarSize == 32)) 4924 return Ld; 4925 4926 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 4927 // double since there is vbroadcastsd xmm 4928 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 4929 // VBroadcast to YMM 4930 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 4931 return Ld; 4932 4933 // VBroadcast to XMM 4934 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 4935 return Ld; 4936 } 4937 4938 // Unsupported broadcast. 4939 return SDValue(); 4940} 4941 4942SDValue 4943X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4944 DebugLoc dl = Op.getDebugLoc(); 4945 4946 EVT VT = Op.getValueType(); 4947 EVT ExtVT = VT.getVectorElementType(); 4948 unsigned NumElems = Op.getNumOperands(); 4949 4950 // Vectors containing all zeros can be matched by pxor and xorps later 4951 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 4952 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 4953 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 4954 if (VT == MVT::v4i32 || VT == MVT::v8i32) 4955 return Op; 4956 4957 return getZeroVector(VT, Subtarget, DAG, dl); 4958 } 4959 4960 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 4961 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 4962 // vpcmpeqd on 256-bit vectors. 4963 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 4964 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 4965 return Op; 4966 4967 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 4968 } 4969 4970 SDValue LD = isVectorBroadcast(Op, Subtarget); 4971 if (LD.getNode()) 4972 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 4973 4974 unsigned EVTBits = ExtVT.getSizeInBits(); 4975 4976 unsigned NumZero = 0; 4977 unsigned NumNonZero = 0; 4978 unsigned NonZeros = 0; 4979 bool IsAllConstants = true; 4980 SmallSet<SDValue, 8> Values; 4981 for (unsigned i = 0; i < NumElems; ++i) { 4982 SDValue Elt = Op.getOperand(i); 4983 if (Elt.getOpcode() == ISD::UNDEF) 4984 continue; 4985 Values.insert(Elt); 4986 if (Elt.getOpcode() != ISD::Constant && 4987 Elt.getOpcode() != ISD::ConstantFP) 4988 IsAllConstants = false; 4989 if (X86::isZeroNode(Elt)) 4990 NumZero++; 4991 else { 4992 NonZeros |= (1 << i); 4993 NumNonZero++; 4994 } 4995 } 4996 4997 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4998 if (NumNonZero == 0) 4999 return DAG.getUNDEF(VT); 5000 5001 // Special case for single non-zero, non-undef, element. 5002 if (NumNonZero == 1) { 5003 unsigned Idx = CountTrailingZeros_32(NonZeros); 5004 SDValue Item = Op.getOperand(Idx); 5005 5006 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5007 // the value are obviously zero, truncate the value to i32 and do the 5008 // insertion that way. Only do this if the value is non-constant or if the 5009 // value is a constant being inserted into element 0. It is cheaper to do 5010 // a constant pool load than it is to do a movd + shuffle. 5011 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5012 (!IsAllConstants || Idx == 0)) { 5013 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5014 // Handle SSE only. 5015 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5016 EVT VecVT = MVT::v4i32; 5017 unsigned VecElts = 4; 5018 5019 // Truncate the value (which may itself be a constant) to i32, and 5020 // convert it to a vector with movd (S2V+shuffle to zero extend). 5021 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5022 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5023 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5024 5025 // Now we have our 32-bit value zero extended in the low element of 5026 // a vector. If Idx != 0, swizzle it into place. 5027 if (Idx != 0) { 5028 SmallVector<int, 4> Mask; 5029 Mask.push_back(Idx); 5030 for (unsigned i = 1; i != VecElts; ++i) 5031 Mask.push_back(i); 5032 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5033 DAG.getUNDEF(Item.getValueType()), 5034 &Mask[0]); 5035 } 5036 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5037 } 5038 } 5039 5040 // If we have a constant or non-constant insertion into the low element of 5041 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5042 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5043 // depending on what the source datatype is. 5044 if (Idx == 0) { 5045 if (NumZero == 0) 5046 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5047 5048 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5049 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5050 if (VT.getSizeInBits() == 256) { 5051 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5052 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5053 Item, DAG.getIntPtrConstant(0)); 5054 } 5055 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5056 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5057 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5058 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5059 } 5060 5061 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5062 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5063 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5064 if (VT.getSizeInBits() == 256) { 5065 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5066 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5067 DAG, dl); 5068 } else { 5069 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5070 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5071 } 5072 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5073 } 5074 } 5075 5076 // Is it a vector logical left shift? 5077 if (NumElems == 2 && Idx == 1 && 5078 X86::isZeroNode(Op.getOperand(0)) && 5079 !X86::isZeroNode(Op.getOperand(1))) { 5080 unsigned NumBits = VT.getSizeInBits(); 5081 return getVShift(true, VT, 5082 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5083 VT, Op.getOperand(1)), 5084 NumBits/2, DAG, *this, dl); 5085 } 5086 5087 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5088 return SDValue(); 5089 5090 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5091 // is a non-constant being inserted into an element other than the low one, 5092 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5093 // movd/movss) to move this into the low element, then shuffle it into 5094 // place. 5095 if (EVTBits == 32) { 5096 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5097 5098 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5099 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5100 SmallVector<int, 8> MaskVec; 5101 for (unsigned i = 0; i < NumElems; i++) 5102 MaskVec.push_back(i == Idx ? 0 : 1); 5103 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5104 } 5105 } 5106 5107 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5108 if (Values.size() == 1) { 5109 if (EVTBits == 32) { 5110 // Instead of a shuffle like this: 5111 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5112 // Check if it's possible to issue this instead. 5113 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5114 unsigned Idx = CountTrailingZeros_32(NonZeros); 5115 SDValue Item = Op.getOperand(Idx); 5116 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5117 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5118 } 5119 return SDValue(); 5120 } 5121 5122 // A vector full of immediates; various special cases are already 5123 // handled, so this is best done with a single constant-pool load. 5124 if (IsAllConstants) 5125 return SDValue(); 5126 5127 // For AVX-length vectors, build the individual 128-bit pieces and use 5128 // shuffles to put them in place. 5129 if (VT.getSizeInBits() == 256) { 5130 SmallVector<SDValue, 32> V; 5131 for (unsigned i = 0; i != NumElems; ++i) 5132 V.push_back(Op.getOperand(i)); 5133 5134 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5135 5136 // Build both the lower and upper subvector. 5137 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5138 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5139 NumElems/2); 5140 5141 // Recreate the wider vector with the lower and upper part. 5142 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5143 DAG.getConstant(0, MVT::i32), DAG, dl); 5144 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5145 DAG, dl); 5146 } 5147 5148 // Let legalizer expand 2-wide build_vectors. 5149 if (EVTBits == 64) { 5150 if (NumNonZero == 1) { 5151 // One half is zero or undef. 5152 unsigned Idx = CountTrailingZeros_32(NonZeros); 5153 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5154 Op.getOperand(Idx)); 5155 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5156 } 5157 return SDValue(); 5158 } 5159 5160 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5161 if (EVTBits == 8 && NumElems == 16) { 5162 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5163 Subtarget, *this); 5164 if (V.getNode()) return V; 5165 } 5166 5167 if (EVTBits == 16 && NumElems == 8) { 5168 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5169 Subtarget, *this); 5170 if (V.getNode()) return V; 5171 } 5172 5173 // If element VT is == 32 bits, turn it into a number of shuffles. 5174 SmallVector<SDValue, 8> V(NumElems); 5175 if (NumElems == 4 && NumZero > 0) { 5176 for (unsigned i = 0; i < 4; ++i) { 5177 bool isZero = !(NonZeros & (1 << i)); 5178 if (isZero) 5179 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5180 else 5181 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5182 } 5183 5184 for (unsigned i = 0; i < 2; ++i) { 5185 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5186 default: break; 5187 case 0: 5188 V[i] = V[i*2]; // Must be a zero vector. 5189 break; 5190 case 1: 5191 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5192 break; 5193 case 2: 5194 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5195 break; 5196 case 3: 5197 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5198 break; 5199 } 5200 } 5201 5202 bool Reverse1 = (NonZeros & 0x3) == 2; 5203 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5204 int MaskVec[] = { 5205 Reverse1 ? 1 : 0, 5206 Reverse1 ? 0 : 1, 5207 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5208 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5209 }; 5210 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5211 } 5212 5213 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5214 // Check for a build vector of consecutive loads. 5215 for (unsigned i = 0; i < NumElems; ++i) 5216 V[i] = Op.getOperand(i); 5217 5218 // Check for elements which are consecutive loads. 5219 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5220 if (LD.getNode()) 5221 return LD; 5222 5223 // For SSE 4.1, use insertps to put the high elements into the low element. 5224 if (getSubtarget()->hasSSE41()) { 5225 SDValue Result; 5226 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5227 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5228 else 5229 Result = DAG.getUNDEF(VT); 5230 5231 for (unsigned i = 1; i < NumElems; ++i) { 5232 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5233 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5234 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5235 } 5236 return Result; 5237 } 5238 5239 // Otherwise, expand into a number of unpckl*, start by extending each of 5240 // our (non-undef) elements to the full vector width with the element in the 5241 // bottom slot of the vector (which generates no code for SSE). 5242 for (unsigned i = 0; i < NumElems; ++i) { 5243 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5244 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5245 else 5246 V[i] = DAG.getUNDEF(VT); 5247 } 5248 5249 // Next, we iteratively mix elements, e.g. for v4f32: 5250 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5251 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5252 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5253 unsigned EltStride = NumElems >> 1; 5254 while (EltStride != 0) { 5255 for (unsigned i = 0; i < EltStride; ++i) { 5256 // If V[i+EltStride] is undef and this is the first round of mixing, 5257 // then it is safe to just drop this shuffle: V[i] is already in the 5258 // right place, the one element (since it's the first round) being 5259 // inserted as undef can be dropped. This isn't safe for successive 5260 // rounds because they will permute elements within both vectors. 5261 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5262 EltStride == NumElems/2) 5263 continue; 5264 5265 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5266 } 5267 EltStride >>= 1; 5268 } 5269 return V[0]; 5270 } 5271 return SDValue(); 5272} 5273 5274// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5275// them in a MMX register. This is better than doing a stack convert. 5276static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5277 DebugLoc dl = Op.getDebugLoc(); 5278 EVT ResVT = Op.getValueType(); 5279 5280 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5281 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5282 int Mask[2]; 5283 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5284 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5285 InVec = Op.getOperand(1); 5286 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5287 unsigned NumElts = ResVT.getVectorNumElements(); 5288 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5289 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5290 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5291 } else { 5292 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5293 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5294 Mask[0] = 0; Mask[1] = 2; 5295 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5296 } 5297 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5298} 5299 5300// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5301// to create 256-bit vectors from two other 128-bit ones. 5302static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5303 DebugLoc dl = Op.getDebugLoc(); 5304 EVT ResVT = Op.getValueType(); 5305 5306 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5307 5308 SDValue V1 = Op.getOperand(0); 5309 SDValue V2 = Op.getOperand(1); 5310 unsigned NumElems = ResVT.getVectorNumElements(); 5311 5312 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5313 DAG.getConstant(0, MVT::i32), DAG, dl); 5314 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5315 DAG, dl); 5316} 5317 5318SDValue 5319X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5320 EVT ResVT = Op.getValueType(); 5321 5322 assert(Op.getNumOperands() == 2); 5323 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5324 "Unsupported CONCAT_VECTORS for value type"); 5325 5326 // We support concatenate two MMX registers and place them in a MMX register. 5327 // This is better than doing a stack convert. 5328 if (ResVT.is128BitVector()) 5329 return LowerMMXCONCAT_VECTORS(Op, DAG); 5330 5331 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5332 // from two other 128-bit ones. 5333 return LowerAVXCONCAT_VECTORS(Op, DAG); 5334} 5335 5336// v8i16 shuffles - Prefer shuffles in the following order: 5337// 1. [all] pshuflw, pshufhw, optional move 5338// 2. [ssse3] 1 x pshufb 5339// 3. [ssse3] 2 x pshufb + 1 x por 5340// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5341SDValue 5342X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5343 SelectionDAG &DAG) const { 5344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5345 SDValue V1 = SVOp->getOperand(0); 5346 SDValue V2 = SVOp->getOperand(1); 5347 DebugLoc dl = SVOp->getDebugLoc(); 5348 SmallVector<int, 8> MaskVals; 5349 5350 // Determine if more than 1 of the words in each of the low and high quadwords 5351 // of the result come from the same quadword of one of the two inputs. Undef 5352 // mask values count as coming from any quadword, for better codegen. 5353 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5354 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5355 std::bitset<4> InputQuads; 5356 for (unsigned i = 0; i < 8; ++i) { 5357 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5358 int EltIdx = SVOp->getMaskElt(i); 5359 MaskVals.push_back(EltIdx); 5360 if (EltIdx < 0) { 5361 ++Quad[0]; 5362 ++Quad[1]; 5363 ++Quad[2]; 5364 ++Quad[3]; 5365 continue; 5366 } 5367 ++Quad[EltIdx / 4]; 5368 InputQuads.set(EltIdx / 4); 5369 } 5370 5371 int BestLoQuad = -1; 5372 unsigned MaxQuad = 1; 5373 for (unsigned i = 0; i < 4; ++i) { 5374 if (LoQuad[i] > MaxQuad) { 5375 BestLoQuad = i; 5376 MaxQuad = LoQuad[i]; 5377 } 5378 } 5379 5380 int BestHiQuad = -1; 5381 MaxQuad = 1; 5382 for (unsigned i = 0; i < 4; ++i) { 5383 if (HiQuad[i] > MaxQuad) { 5384 BestHiQuad = i; 5385 MaxQuad = HiQuad[i]; 5386 } 5387 } 5388 5389 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5390 // of the two input vectors, shuffle them into one input vector so only a 5391 // single pshufb instruction is necessary. If There are more than 2 input 5392 // quads, disable the next transformation since it does not help SSSE3. 5393 bool V1Used = InputQuads[0] || InputQuads[1]; 5394 bool V2Used = InputQuads[2] || InputQuads[3]; 5395 if (Subtarget->hasSSSE3()) { 5396 if (InputQuads.count() == 2 && V1Used && V2Used) { 5397 BestLoQuad = InputQuads[0] ? 0 : 1; 5398 BestHiQuad = InputQuads[2] ? 2 : 3; 5399 } 5400 if (InputQuads.count() > 2) { 5401 BestLoQuad = -1; 5402 BestHiQuad = -1; 5403 } 5404 } 5405 5406 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5407 // the shuffle mask. If a quad is scored as -1, that means that it contains 5408 // words from all 4 input quadwords. 5409 SDValue NewV; 5410 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5411 int MaskV[] = { 5412 BestLoQuad < 0 ? 0 : BestLoQuad, 5413 BestHiQuad < 0 ? 1 : BestHiQuad 5414 }; 5415 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5416 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5417 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5418 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5419 5420 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5421 // source words for the shuffle, to aid later transformations. 5422 bool AllWordsInNewV = true; 5423 bool InOrder[2] = { true, true }; 5424 for (unsigned i = 0; i != 8; ++i) { 5425 int idx = MaskVals[i]; 5426 if (idx != (int)i) 5427 InOrder[i/4] = false; 5428 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5429 continue; 5430 AllWordsInNewV = false; 5431 break; 5432 } 5433 5434 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5435 if (AllWordsInNewV) { 5436 for (int i = 0; i != 8; ++i) { 5437 int idx = MaskVals[i]; 5438 if (idx < 0) 5439 continue; 5440 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5441 if ((idx != i) && idx < 4) 5442 pshufhw = false; 5443 if ((idx != i) && idx > 3) 5444 pshuflw = false; 5445 } 5446 V1 = NewV; 5447 V2Used = false; 5448 BestLoQuad = 0; 5449 BestHiQuad = 1; 5450 } 5451 5452 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5453 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5454 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5455 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5456 unsigned TargetMask = 0; 5457 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5458 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5459 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(NewV.getNode()): 5460 getShufflePSHUFLWImmediate(NewV.getNode()); 5461 V1 = NewV.getOperand(0); 5462 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5463 } 5464 } 5465 5466 // If we have SSSE3, and all words of the result are from 1 input vector, 5467 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5468 // is present, fall back to case 4. 5469 if (Subtarget->hasSSSE3()) { 5470 SmallVector<SDValue,16> pshufbMask; 5471 5472 // If we have elements from both input vectors, set the high bit of the 5473 // shuffle mask element to zero out elements that come from V2 in the V1 5474 // mask, and elements that come from V1 in the V2 mask, so that the two 5475 // results can be OR'd together. 5476 bool TwoInputs = V1Used && V2Used; 5477 for (unsigned i = 0; i != 8; ++i) { 5478 int EltIdx = MaskVals[i] * 2; 5479 if (TwoInputs && (EltIdx >= 16)) { 5480 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5481 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5482 continue; 5483 } 5484 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5485 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5486 } 5487 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5488 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5489 DAG.getNode(ISD::BUILD_VECTOR, dl, 5490 MVT::v16i8, &pshufbMask[0], 16)); 5491 if (!TwoInputs) 5492 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5493 5494 // Calculate the shuffle mask for the second input, shuffle it, and 5495 // OR it with the first shuffled input. 5496 pshufbMask.clear(); 5497 for (unsigned i = 0; i != 8; ++i) { 5498 int EltIdx = MaskVals[i] * 2; 5499 if (EltIdx < 16) { 5500 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5501 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5502 continue; 5503 } 5504 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5505 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5506 } 5507 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5508 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5509 DAG.getNode(ISD::BUILD_VECTOR, dl, 5510 MVT::v16i8, &pshufbMask[0], 16)); 5511 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5512 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5513 } 5514 5515 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5516 // and update MaskVals with new element order. 5517 std::bitset<8> InOrder; 5518 if (BestLoQuad >= 0) { 5519 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5520 for (int i = 0; i != 4; ++i) { 5521 int idx = MaskVals[i]; 5522 if (idx < 0) { 5523 InOrder.set(i); 5524 } else if ((idx / 4) == BestLoQuad) { 5525 MaskV[i] = idx & 3; 5526 InOrder.set(i); 5527 } 5528 } 5529 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5530 &MaskV[0]); 5531 5532 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5533 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5534 NewV.getOperand(0), 5535 getShufflePSHUFLWImmediate(NewV.getNode()), 5536 DAG); 5537 } 5538 5539 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5540 // and update MaskVals with the new element order. 5541 if (BestHiQuad >= 0) { 5542 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5543 for (unsigned i = 4; i != 8; ++i) { 5544 int idx = MaskVals[i]; 5545 if (idx < 0) { 5546 InOrder.set(i); 5547 } else if ((idx / 4) == BestHiQuad) { 5548 MaskV[i] = (idx & 3) + 4; 5549 InOrder.set(i); 5550 } 5551 } 5552 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5553 &MaskV[0]); 5554 5555 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5556 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5557 NewV.getOperand(0), 5558 getShufflePSHUFHWImmediate(NewV.getNode()), 5559 DAG); 5560 } 5561 5562 // In case BestHi & BestLo were both -1, which means each quadword has a word 5563 // from each of the four input quadwords, calculate the InOrder bitvector now 5564 // before falling through to the insert/extract cleanup. 5565 if (BestLoQuad == -1 && BestHiQuad == -1) { 5566 NewV = V1; 5567 for (int i = 0; i != 8; ++i) 5568 if (MaskVals[i] < 0 || MaskVals[i] == i) 5569 InOrder.set(i); 5570 } 5571 5572 // The other elements are put in the right place using pextrw and pinsrw. 5573 for (unsigned i = 0; i != 8; ++i) { 5574 if (InOrder[i]) 5575 continue; 5576 int EltIdx = MaskVals[i]; 5577 if (EltIdx < 0) 5578 continue; 5579 SDValue ExtOp = (EltIdx < 8) 5580 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5581 DAG.getIntPtrConstant(EltIdx)) 5582 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5583 DAG.getIntPtrConstant(EltIdx - 8)); 5584 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5585 DAG.getIntPtrConstant(i)); 5586 } 5587 return NewV; 5588} 5589 5590// v16i8 shuffles - Prefer shuffles in the following order: 5591// 1. [ssse3] 1 x pshufb 5592// 2. [ssse3] 2 x pshufb + 1 x por 5593// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5594static 5595SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5596 SelectionDAG &DAG, 5597 const X86TargetLowering &TLI) { 5598 SDValue V1 = SVOp->getOperand(0); 5599 SDValue V2 = SVOp->getOperand(1); 5600 DebugLoc dl = SVOp->getDebugLoc(); 5601 ArrayRef<int> MaskVals = SVOp->getMask(); 5602 5603 // If we have SSSE3, case 1 is generated when all result bytes come from 5604 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5605 // present, fall back to case 3. 5606 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5607 bool V1Only = true; 5608 bool V2Only = true; 5609 for (unsigned i = 0; i < 16; ++i) { 5610 int EltIdx = MaskVals[i]; 5611 if (EltIdx < 0) 5612 continue; 5613 if (EltIdx < 16) 5614 V2Only = false; 5615 else 5616 V1Only = false; 5617 } 5618 5619 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5620 if (TLI.getSubtarget()->hasSSSE3()) { 5621 SmallVector<SDValue,16> pshufbMask; 5622 5623 // If all result elements are from one input vector, then only translate 5624 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5625 // 5626 // Otherwise, we have elements from both input vectors, and must zero out 5627 // elements that come from V2 in the first mask, and V1 in the second mask 5628 // so that we can OR them together. 5629 bool TwoInputs = !(V1Only || V2Only); 5630 for (unsigned i = 0; i != 16; ++i) { 5631 int EltIdx = MaskVals[i]; 5632 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5633 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5634 continue; 5635 } 5636 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5637 } 5638 // If all the elements are from V2, assign it to V1 and return after 5639 // building the first pshufb. 5640 if (V2Only) 5641 V1 = V2; 5642 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5643 DAG.getNode(ISD::BUILD_VECTOR, dl, 5644 MVT::v16i8, &pshufbMask[0], 16)); 5645 if (!TwoInputs) 5646 return V1; 5647 5648 // Calculate the shuffle mask for the second input, shuffle it, and 5649 // OR it with the first shuffled input. 5650 pshufbMask.clear(); 5651 for (unsigned i = 0; i != 16; ++i) { 5652 int EltIdx = MaskVals[i]; 5653 if (EltIdx < 16) { 5654 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5655 continue; 5656 } 5657 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5658 } 5659 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5660 DAG.getNode(ISD::BUILD_VECTOR, dl, 5661 MVT::v16i8, &pshufbMask[0], 16)); 5662 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5663 } 5664 5665 // No SSSE3 - Calculate in place words and then fix all out of place words 5666 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5667 // the 16 different words that comprise the two doublequadword input vectors. 5668 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5669 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5670 SDValue NewV = V2Only ? V2 : V1; 5671 for (int i = 0; i != 8; ++i) { 5672 int Elt0 = MaskVals[i*2]; 5673 int Elt1 = MaskVals[i*2+1]; 5674 5675 // This word of the result is all undef, skip it. 5676 if (Elt0 < 0 && Elt1 < 0) 5677 continue; 5678 5679 // This word of the result is already in the correct place, skip it. 5680 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5681 continue; 5682 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5683 continue; 5684 5685 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5686 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5687 SDValue InsElt; 5688 5689 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5690 // using a single extract together, load it and store it. 5691 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5692 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5693 DAG.getIntPtrConstant(Elt1 / 2)); 5694 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5695 DAG.getIntPtrConstant(i)); 5696 continue; 5697 } 5698 5699 // If Elt1 is defined, extract it from the appropriate source. If the 5700 // source byte is not also odd, shift the extracted word left 8 bits 5701 // otherwise clear the bottom 8 bits if we need to do an or. 5702 if (Elt1 >= 0) { 5703 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5704 DAG.getIntPtrConstant(Elt1 / 2)); 5705 if ((Elt1 & 1) == 0) 5706 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5707 DAG.getConstant(8, 5708 TLI.getShiftAmountTy(InsElt.getValueType()))); 5709 else if (Elt0 >= 0) 5710 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5711 DAG.getConstant(0xFF00, MVT::i16)); 5712 } 5713 // If Elt0 is defined, extract it from the appropriate source. If the 5714 // source byte is not also even, shift the extracted word right 8 bits. If 5715 // Elt1 was also defined, OR the extracted values together before 5716 // inserting them in the result. 5717 if (Elt0 >= 0) { 5718 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5719 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5720 if ((Elt0 & 1) != 0) 5721 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5722 DAG.getConstant(8, 5723 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5724 else if (Elt1 >= 0) 5725 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5726 DAG.getConstant(0x00FF, MVT::i16)); 5727 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5728 : InsElt0; 5729 } 5730 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5731 DAG.getIntPtrConstant(i)); 5732 } 5733 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5734} 5735 5736/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5737/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5738/// done when every pair / quad of shuffle mask elements point to elements in 5739/// the right sequence. e.g. 5740/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5741static 5742SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5743 SelectionDAG &DAG, DebugLoc dl) { 5744 EVT VT = SVOp->getValueType(0); 5745 SDValue V1 = SVOp->getOperand(0); 5746 SDValue V2 = SVOp->getOperand(1); 5747 unsigned NumElems = VT.getVectorNumElements(); 5748 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5749 EVT NewVT; 5750 switch (VT.getSimpleVT().SimpleTy) { 5751 default: llvm_unreachable("Unexpected!"); 5752 case MVT::v4f32: NewVT = MVT::v2f64; break; 5753 case MVT::v4i32: NewVT = MVT::v2i64; break; 5754 case MVT::v8i16: NewVT = MVT::v4i32; break; 5755 case MVT::v16i8: NewVT = MVT::v4i32; break; 5756 } 5757 5758 int Scale = NumElems / NewWidth; 5759 SmallVector<int, 8> MaskVec; 5760 for (unsigned i = 0; i < NumElems; i += Scale) { 5761 int StartIdx = -1; 5762 for (int j = 0; j < Scale; ++j) { 5763 int EltIdx = SVOp->getMaskElt(i+j); 5764 if (EltIdx < 0) 5765 continue; 5766 if (StartIdx == -1) 5767 StartIdx = EltIdx - (EltIdx % Scale); 5768 if (EltIdx != StartIdx + j) 5769 return SDValue(); 5770 } 5771 if (StartIdx == -1) 5772 MaskVec.push_back(-1); 5773 else 5774 MaskVec.push_back(StartIdx / Scale); 5775 } 5776 5777 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5778 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5779 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5780} 5781 5782/// getVZextMovL - Return a zero-extending vector move low node. 5783/// 5784static SDValue getVZextMovL(EVT VT, EVT OpVT, 5785 SDValue SrcOp, SelectionDAG &DAG, 5786 const X86Subtarget *Subtarget, DebugLoc dl) { 5787 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5788 LoadSDNode *LD = NULL; 5789 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5790 LD = dyn_cast<LoadSDNode>(SrcOp); 5791 if (!LD) { 5792 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5793 // instead. 5794 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5795 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5796 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5797 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5798 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5799 // PR2108 5800 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5801 return DAG.getNode(ISD::BITCAST, dl, VT, 5802 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5803 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5804 OpVT, 5805 SrcOp.getOperand(0) 5806 .getOperand(0)))); 5807 } 5808 } 5809 } 5810 5811 return DAG.getNode(ISD::BITCAST, dl, VT, 5812 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5813 DAG.getNode(ISD::BITCAST, dl, 5814 OpVT, SrcOp))); 5815} 5816 5817/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5818/// which could not be matched by any known target speficic shuffle 5819static SDValue 5820LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5821 EVT VT = SVOp->getValueType(0); 5822 5823 unsigned NumElems = VT.getVectorNumElements(); 5824 unsigned NumLaneElems = NumElems / 2; 5825 5826 int MinRange[2][2] = { { static_cast<int>(NumElems), 5827 static_cast<int>(NumElems) }, 5828 { static_cast<int>(NumElems), 5829 static_cast<int>(NumElems) } }; 5830 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } }; 5831 5832 // Collect used ranges for each source in each lane 5833 for (unsigned l = 0; l < 2; ++l) { 5834 unsigned LaneStart = l*NumLaneElems; 5835 for (unsigned i = 0; i != NumLaneElems; ++i) { 5836 int Idx = SVOp->getMaskElt(i+LaneStart); 5837 if (Idx < 0) 5838 continue; 5839 5840 int Input = 0; 5841 if (Idx >= (int)NumElems) { 5842 Idx -= NumElems; 5843 Input = 1; 5844 } 5845 5846 if (Idx > MaxRange[l][Input]) 5847 MaxRange[l][Input] = Idx; 5848 if (Idx < MinRange[l][Input]) 5849 MinRange[l][Input] = Idx; 5850 } 5851 } 5852 5853 // Make sure each range is 128-bits 5854 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } }; 5855 for (unsigned l = 0; l < 2; ++l) { 5856 for (unsigned Input = 0; Input < 2; ++Input) { 5857 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0) 5858 continue; 5859 5860 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems) 5861 ExtractIdx[l][Input] = 0; 5862 else if (MinRange[l][Input] >= (int)NumLaneElems && 5863 MaxRange[l][Input] < (int)NumElems) 5864 ExtractIdx[l][Input] = NumLaneElems; 5865 else 5866 return SDValue(); 5867 } 5868 } 5869 5870 DebugLoc dl = SVOp->getDebugLoc(); 5871 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5872 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2); 5873 5874 SDValue Ops[2][2]; 5875 for (unsigned l = 0; l < 2; ++l) { 5876 for (unsigned Input = 0; Input < 2; ++Input) { 5877 if (ExtractIdx[l][Input] >= 0) 5878 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input), 5879 DAG.getConstant(ExtractIdx[l][Input], MVT::i32), 5880 DAG, dl); 5881 else 5882 Ops[l][Input] = DAG.getUNDEF(NVT); 5883 } 5884 } 5885 5886 // Generate 128-bit shuffles 5887 SmallVector<int, 16> Mask1, Mask2; 5888 for (unsigned i = 0; i != NumLaneElems; ++i) { 5889 int Elt = SVOp->getMaskElt(i); 5890 if (Elt >= (int)NumElems) { 5891 Elt %= NumLaneElems; 5892 Elt += NumLaneElems; 5893 } else if (Elt >= 0) { 5894 Elt %= NumLaneElems; 5895 } 5896 Mask1.push_back(Elt); 5897 } 5898 for (unsigned i = NumLaneElems; i != NumElems; ++i) { 5899 int Elt = SVOp->getMaskElt(i); 5900 if (Elt >= (int)NumElems) { 5901 Elt %= NumLaneElems; 5902 Elt += NumLaneElems; 5903 } else if (Elt >= 0) { 5904 Elt %= NumLaneElems; 5905 } 5906 Mask2.push_back(Elt); 5907 } 5908 5909 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]); 5910 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]); 5911 5912 // Concatenate the result back 5913 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1, 5914 DAG.getConstant(0, MVT::i32), DAG, dl); 5915 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32), 5916 DAG, dl); 5917} 5918 5919/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 5920/// 4 elements, and match them with several different shuffle types. 5921static SDValue 5922LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5923 SDValue V1 = SVOp->getOperand(0); 5924 SDValue V2 = SVOp->getOperand(1); 5925 DebugLoc dl = SVOp->getDebugLoc(); 5926 EVT VT = SVOp->getValueType(0); 5927 5928 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 5929 5930 std::pair<int, int> Locs[4]; 5931 int Mask1[] = { -1, -1, -1, -1 }; 5932 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 5933 5934 unsigned NumHi = 0; 5935 unsigned NumLo = 0; 5936 for (unsigned i = 0; i != 4; ++i) { 5937 int Idx = PermMask[i]; 5938 if (Idx < 0) { 5939 Locs[i] = std::make_pair(-1, -1); 5940 } else { 5941 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 5942 if (Idx < 4) { 5943 Locs[i] = std::make_pair(0, NumLo); 5944 Mask1[NumLo] = Idx; 5945 NumLo++; 5946 } else { 5947 Locs[i] = std::make_pair(1, NumHi); 5948 if (2+NumHi < 4) 5949 Mask1[2+NumHi] = Idx; 5950 NumHi++; 5951 } 5952 } 5953 } 5954 5955 if (NumLo <= 2 && NumHi <= 2) { 5956 // If no more than two elements come from either vector. This can be 5957 // implemented with two shuffles. First shuffle gather the elements. 5958 // The second shuffle, which takes the first shuffle as both of its 5959 // vector operands, put the elements into the right order. 5960 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5961 5962 int Mask2[] = { -1, -1, -1, -1 }; 5963 5964 for (unsigned i = 0; i != 4; ++i) 5965 if (Locs[i].first != -1) { 5966 unsigned Idx = (i < 2) ? 0 : 4; 5967 Idx += Locs[i].first * 2 + Locs[i].second; 5968 Mask2[i] = Idx; 5969 } 5970 5971 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 5972 } else if (NumLo == 3 || NumHi == 3) { 5973 // Otherwise, we must have three elements from one vector, call it X, and 5974 // one element from the other, call it Y. First, use a shufps to build an 5975 // intermediate vector with the one element from Y and the element from X 5976 // that will be in the same half in the final destination (the indexes don't 5977 // matter). Then, use a shufps to build the final vector, taking the half 5978 // containing the element from Y from the intermediate, and the other half 5979 // from X. 5980 if (NumHi == 3) { 5981 // Normalize it so the 3 elements come from V1. 5982 CommuteVectorShuffleMask(PermMask, 4); 5983 std::swap(V1, V2); 5984 } 5985 5986 // Find the element from V2. 5987 unsigned HiIndex; 5988 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 5989 int Val = PermMask[HiIndex]; 5990 if (Val < 0) 5991 continue; 5992 if (Val >= 4) 5993 break; 5994 } 5995 5996 Mask1[0] = PermMask[HiIndex]; 5997 Mask1[1] = -1; 5998 Mask1[2] = PermMask[HiIndex^1]; 5999 Mask1[3] = -1; 6000 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6001 6002 if (HiIndex >= 2) { 6003 Mask1[0] = PermMask[0]; 6004 Mask1[1] = PermMask[1]; 6005 Mask1[2] = HiIndex & 1 ? 6 : 4; 6006 Mask1[3] = HiIndex & 1 ? 4 : 6; 6007 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6008 } else { 6009 Mask1[0] = HiIndex & 1 ? 2 : 0; 6010 Mask1[1] = HiIndex & 1 ? 0 : 2; 6011 Mask1[2] = PermMask[2]; 6012 Mask1[3] = PermMask[3]; 6013 if (Mask1[2] >= 0) 6014 Mask1[2] += 4; 6015 if (Mask1[3] >= 0) 6016 Mask1[3] += 4; 6017 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6018 } 6019 } 6020 6021 // Break it into (shuffle shuffle_hi, shuffle_lo). 6022 int LoMask[] = { -1, -1, -1, -1 }; 6023 int HiMask[] = { -1, -1, -1, -1 }; 6024 6025 int *MaskPtr = LoMask; 6026 unsigned MaskIdx = 0; 6027 unsigned LoIdx = 0; 6028 unsigned HiIdx = 2; 6029 for (unsigned i = 0; i != 4; ++i) { 6030 if (i == 2) { 6031 MaskPtr = HiMask; 6032 MaskIdx = 1; 6033 LoIdx = 0; 6034 HiIdx = 2; 6035 } 6036 int Idx = PermMask[i]; 6037 if (Idx < 0) { 6038 Locs[i] = std::make_pair(-1, -1); 6039 } else if (Idx < 4) { 6040 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6041 MaskPtr[LoIdx] = Idx; 6042 LoIdx++; 6043 } else { 6044 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6045 MaskPtr[HiIdx] = Idx; 6046 HiIdx++; 6047 } 6048 } 6049 6050 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6051 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6052 int MaskOps[] = { -1, -1, -1, -1 }; 6053 for (unsigned i = 0; i != 4; ++i) 6054 if (Locs[i].first != -1) 6055 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6056 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6057} 6058 6059static bool MayFoldVectorLoad(SDValue V) { 6060 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6061 V = V.getOperand(0); 6062 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6063 V = V.getOperand(0); 6064 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6065 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6066 // BUILD_VECTOR (load), undef 6067 V = V.getOperand(0); 6068 if (MayFoldLoad(V)) 6069 return true; 6070 return false; 6071} 6072 6073// FIXME: the version above should always be used. Since there's 6074// a bug where several vector shuffles can't be folded because the 6075// DAG is not updated during lowering and a node claims to have two 6076// uses while it only has one, use this version, and let isel match 6077// another instruction if the load really happens to have more than 6078// one use. Remove this version after this bug get fixed. 6079// rdar://8434668, PR8156 6080static bool RelaxedMayFoldVectorLoad(SDValue V) { 6081 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6082 V = V.getOperand(0); 6083 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6084 V = V.getOperand(0); 6085 if (ISD::isNormalLoad(V.getNode())) 6086 return true; 6087 return false; 6088} 6089 6090/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6091/// a vector extract, and if both can be later optimized into a single load. 6092/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6093/// here because otherwise a target specific shuffle node is going to be 6094/// emitted for this shuffle, and the optimization not done. 6095/// FIXME: This is probably not the best approach, but fix the problem 6096/// until the right path is decided. 6097static 6098bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6099 const TargetLowering &TLI) { 6100 EVT VT = V.getValueType(); 6101 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6102 6103 // Be sure that the vector shuffle is present in a pattern like this: 6104 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6105 if (!V.hasOneUse()) 6106 return false; 6107 6108 SDNode *N = *V.getNode()->use_begin(); 6109 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6110 return false; 6111 6112 SDValue EltNo = N->getOperand(1); 6113 if (!isa<ConstantSDNode>(EltNo)) 6114 return false; 6115 6116 // If the bit convert changed the number of elements, it is unsafe 6117 // to examine the mask. 6118 bool HasShuffleIntoBitcast = false; 6119 if (V.getOpcode() == ISD::BITCAST) { 6120 EVT SrcVT = V.getOperand(0).getValueType(); 6121 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6122 return false; 6123 V = V.getOperand(0); 6124 HasShuffleIntoBitcast = true; 6125 } 6126 6127 // Select the input vector, guarding against out of range extract vector. 6128 unsigned NumElems = VT.getVectorNumElements(); 6129 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6130 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6131 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6132 6133 // If we are accessing the upper part of a YMM register 6134 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of 6135 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point 6136 // because the legalization of N did not happen yet. 6137 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256) 6138 return false; 6139 6140 // Skip one more bit_convert if necessary 6141 if (V.getOpcode() == ISD::BITCAST) { 6142 if (!V.hasOneUse()) 6143 return false; 6144 V = V.getOperand(0); 6145 } 6146 6147 if (!ISD::isNormalLoad(V.getNode())) 6148 return false; 6149 6150 // Is the original load suitable? 6151 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6152 6153 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6154 return false; 6155 6156 if (!HasShuffleIntoBitcast) 6157 return true; 6158 6159 // If there's a bitcast before the shuffle, check if the load type and 6160 // alignment is valid. 6161 unsigned Align = LN0->getAlignment(); 6162 unsigned NewAlign = 6163 TLI.getTargetData()->getABITypeAlignment( 6164 VT.getTypeForEVT(*DAG.getContext())); 6165 6166 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6167 return false; 6168 6169 return true; 6170} 6171 6172static 6173SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6174 EVT VT = Op.getValueType(); 6175 6176 // Canonizalize to v2f64. 6177 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6178 return DAG.getNode(ISD::BITCAST, dl, VT, 6179 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6180 V1, DAG)); 6181} 6182 6183static 6184SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6185 bool HasSSE2) { 6186 SDValue V1 = Op.getOperand(0); 6187 SDValue V2 = Op.getOperand(1); 6188 EVT VT = Op.getValueType(); 6189 6190 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6191 6192 if (HasSSE2 && VT == MVT::v2f64) 6193 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6194 6195 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6196 return DAG.getNode(ISD::BITCAST, dl, VT, 6197 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6198 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6199 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6200} 6201 6202static 6203SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6204 SDValue V1 = Op.getOperand(0); 6205 SDValue V2 = Op.getOperand(1); 6206 EVT VT = Op.getValueType(); 6207 6208 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6209 "unsupported shuffle type"); 6210 6211 if (V2.getOpcode() == ISD::UNDEF) 6212 V2 = V1; 6213 6214 // v4i32 or v4f32 6215 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6216} 6217 6218static 6219SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6220 SDValue V1 = Op.getOperand(0); 6221 SDValue V2 = Op.getOperand(1); 6222 EVT VT = Op.getValueType(); 6223 unsigned NumElems = VT.getVectorNumElements(); 6224 6225 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6226 // operand of these instructions is only memory, so check if there's a 6227 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6228 // same masks. 6229 bool CanFoldLoad = false; 6230 6231 // Trivial case, when V2 comes from a load. 6232 if (MayFoldVectorLoad(V2)) 6233 CanFoldLoad = true; 6234 6235 // When V1 is a load, it can be folded later into a store in isel, example: 6236 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6237 // turns into: 6238 // (MOVLPSmr addr:$src1, VR128:$src2) 6239 // So, recognize this potential and also use MOVLPS or MOVLPD 6240 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6241 CanFoldLoad = true; 6242 6243 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6244 if (CanFoldLoad) { 6245 if (HasSSE2 && NumElems == 2) 6246 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6247 6248 if (NumElems == 4) 6249 // If we don't care about the second element, procede to use movss. 6250 if (SVOp->getMaskElt(1) != -1) 6251 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6252 } 6253 6254 // movl and movlp will both match v2i64, but v2i64 is never matched by 6255 // movl earlier because we make it strict to avoid messing with the movlp load 6256 // folding logic (see the code above getMOVLP call). Match it here then, 6257 // this is horrible, but will stay like this until we move all shuffle 6258 // matching to x86 specific nodes. Note that for the 1st condition all 6259 // types are matched with movsd. 6260 if (HasSSE2) { 6261 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6262 // as to remove this logic from here, as much as possible 6263 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6264 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6265 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6266 } 6267 6268 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6269 6270 // Invert the operand order and use SHUFPS to match it. 6271 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6272 getShuffleSHUFImmediate(SVOp), DAG); 6273} 6274 6275static 6276SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6277 const TargetLowering &TLI, 6278 const X86Subtarget *Subtarget) { 6279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6280 EVT VT = Op.getValueType(); 6281 DebugLoc dl = Op.getDebugLoc(); 6282 SDValue V1 = Op.getOperand(0); 6283 SDValue V2 = Op.getOperand(1); 6284 6285 if (isZeroShuffle(SVOp)) 6286 return getZeroVector(VT, Subtarget, DAG, dl); 6287 6288 // Handle splat operations 6289 if (SVOp->isSplat()) { 6290 unsigned NumElem = VT.getVectorNumElements(); 6291 int Size = VT.getSizeInBits(); 6292 // Special case, this is the only place now where it's allowed to return 6293 // a vector_shuffle operation without using a target specific node, because 6294 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6295 // this be moved to DAGCombine instead? 6296 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6297 return Op; 6298 6299 // Use vbroadcast whenever the splat comes from a foldable load 6300 SDValue LD = isVectorBroadcast(Op, Subtarget); 6301 if (LD.getNode()) 6302 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6303 6304 // Handle splats by matching through known shuffle masks 6305 if ((Size == 128 && NumElem <= 4) || 6306 (Size == 256 && NumElem < 8)) 6307 return SDValue(); 6308 6309 // All remaning splats are promoted to target supported vector shuffles. 6310 return PromoteSplat(SVOp, DAG); 6311 } 6312 6313 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6314 // do it! 6315 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6316 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6317 if (NewOp.getNode()) 6318 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6319 } else if ((VT == MVT::v4i32 || 6320 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6321 // FIXME: Figure out a cleaner way to do this. 6322 // Try to make use of movq to zero out the top part. 6323 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6324 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6325 if (NewOp.getNode()) { 6326 EVT NewVT = NewOp.getValueType(); 6327 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6328 NewVT, true, false)) 6329 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6330 DAG, Subtarget, dl); 6331 } 6332 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6333 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6334 if (NewOp.getNode()) { 6335 EVT NewVT = NewOp.getValueType(); 6336 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6337 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6338 DAG, Subtarget, dl); 6339 } 6340 } 6341 } 6342 return SDValue(); 6343} 6344 6345SDValue 6346X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6348 SDValue V1 = Op.getOperand(0); 6349 SDValue V2 = Op.getOperand(1); 6350 EVT VT = Op.getValueType(); 6351 DebugLoc dl = Op.getDebugLoc(); 6352 unsigned NumElems = VT.getVectorNumElements(); 6353 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6354 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6355 bool V1IsSplat = false; 6356 bool V2IsSplat = false; 6357 bool HasSSE2 = Subtarget->hasSSE2(); 6358 bool HasAVX = Subtarget->hasAVX(); 6359 bool HasAVX2 = Subtarget->hasAVX2(); 6360 MachineFunction &MF = DAG.getMachineFunction(); 6361 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6362 6363 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6364 6365 if (V1IsUndef && V2IsUndef) 6366 return DAG.getUNDEF(VT); 6367 6368 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6369 6370 // Vector shuffle lowering takes 3 steps: 6371 // 6372 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6373 // narrowing and commutation of operands should be handled. 6374 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6375 // shuffle nodes. 6376 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6377 // so the shuffle can be broken into other shuffles and the legalizer can 6378 // try the lowering again. 6379 // 6380 // The general idea is that no vector_shuffle operation should be left to 6381 // be matched during isel, all of them must be converted to a target specific 6382 // node here. 6383 6384 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6385 // narrowing and commutation of operands should be handled. The actual code 6386 // doesn't include all of those, work in progress... 6387 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6388 if (NewOp.getNode()) 6389 return NewOp; 6390 6391 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6392 6393 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6394 // unpckh_undef). Only use pshufd if speed is more important than size. 6395 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6396 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6397 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6398 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6399 6400 if (isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() && 6401 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6402 return getMOVDDup(Op, dl, V1, DAG); 6403 6404 if (isMOVHLPS_v_undef_Mask(SVOp)) 6405 return getMOVHighToLow(Op, dl, DAG); 6406 6407 // Use to match splats 6408 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6409 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6410 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6411 6412 if (isPSHUFDMask(M, VT)) { 6413 // The actual implementation will match the mask in the if above and then 6414 // during isel it can match several different instructions, not only pshufd 6415 // as its name says, sad but true, emulate the behavior for now... 6416 if (isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6417 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6418 6419 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6420 6421 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6422 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6423 6424 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6425 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6426 6427 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6428 TargetMask, DAG); 6429 } 6430 6431 // Check if this can be converted into a logical shift. 6432 bool isLeft = false; 6433 unsigned ShAmt = 0; 6434 SDValue ShVal; 6435 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6436 if (isShift && ShVal.hasOneUse()) { 6437 // If the shifted value has multiple uses, it may be cheaper to use 6438 // v_set0 + movlhps or movhlps, etc. 6439 EVT EltVT = VT.getVectorElementType(); 6440 ShAmt *= EltVT.getSizeInBits(); 6441 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6442 } 6443 6444 if (isMOVLMask(M, VT)) { 6445 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6446 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6447 if (!isMOVLPMask(SVOp)) { 6448 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6449 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6450 6451 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6452 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6453 } 6454 } 6455 6456 // FIXME: fold these into legal mask. 6457 if (isMOVLHPSMask(SVOp) && !isUNPCKLMask(M, VT, HasAVX2)) 6458 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6459 6460 if (isMOVHLPSMask(SVOp)) 6461 return getMOVHighToLow(Op, dl, DAG); 6462 6463 if (isMOVSHDUPMask(SVOp, Subtarget)) 6464 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6465 6466 if (isMOVSLDUPMask(SVOp, Subtarget)) 6467 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6468 6469 if (isMOVLPMask(SVOp)) 6470 return getMOVLP(Op, dl, DAG, HasSSE2); 6471 6472 if (ShouldXformToMOVHLPS(SVOp) || 6473 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6474 return CommuteVectorShuffle(SVOp, DAG); 6475 6476 if (isShift) { 6477 // No better options. Use a vshldq / vsrldq. 6478 EVT EltVT = VT.getVectorElementType(); 6479 ShAmt *= EltVT.getSizeInBits(); 6480 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6481 } 6482 6483 bool Commuted = false; 6484 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6485 // 1,1,1,1 -> v8i16 though. 6486 V1IsSplat = isSplatVector(V1.getNode()); 6487 V2IsSplat = isSplatVector(V2.getNode()); 6488 6489 // Canonicalize the splat or undef, if present, to be on the RHS. 6490 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6491 CommuteVectorShuffleMask(M, NumElems); 6492 std::swap(V1, V2); 6493 std::swap(V1IsSplat, V2IsSplat); 6494 Commuted = true; 6495 } 6496 6497 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6498 // Shuffling low element of v1 into undef, just return v1. 6499 if (V2IsUndef) 6500 return V1; 6501 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6502 // the instruction selector will not match, so get a canonical MOVL with 6503 // swapped operands to undo the commute. 6504 return getMOVL(DAG, dl, VT, V2, V1); 6505 } 6506 6507 if (isUNPCKLMask(M, VT, HasAVX2)) 6508 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6509 6510 if (isUNPCKHMask(M, VT, HasAVX2)) 6511 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6512 6513 if (V2IsSplat) { 6514 // Normalize mask so all entries that point to V2 points to its first 6515 // element then try to match unpck{h|l} again. If match, return a 6516 // new vector_shuffle with the corrected mask.p 6517 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6518 NormalizeMask(NewMask, NumElems); 6519 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) { 6520 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6521 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) { 6522 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6523 } 6524 } 6525 6526 if (Commuted) { 6527 // Commute is back and try unpck* again. 6528 // FIXME: this seems wrong. 6529 CommuteVectorShuffleMask(M, NumElems); 6530 std::swap(V1, V2); 6531 std::swap(V1IsSplat, V2IsSplat); 6532 Commuted = false; 6533 6534 if (isUNPCKLMask(M, VT, HasAVX2)) 6535 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6536 6537 if (isUNPCKHMask(M, VT, HasAVX2)) 6538 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6539 } 6540 6541 // Normalize the node to match x86 shuffle ops if needed 6542 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6543 return CommuteVectorShuffle(SVOp, DAG); 6544 6545 // The checks below are all present in isShuffleMaskLegal, but they are 6546 // inlined here right now to enable us to directly emit target specific 6547 // nodes, and remove one by one until they don't return Op anymore. 6548 6549 if (isPALIGNRMask(M, VT, Subtarget)) 6550 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6551 getShufflePALIGNRImmediate(SVOp), 6552 DAG); 6553 6554 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6555 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6556 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6557 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6558 } 6559 6560 if (isPSHUFHWMask(M, VT)) 6561 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6562 getShufflePSHUFHWImmediate(SVOp), 6563 DAG); 6564 6565 if (isPSHUFLWMask(M, VT)) 6566 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6567 getShufflePSHUFLWImmediate(SVOp), 6568 DAG); 6569 6570 if (isSHUFPMask(M, VT, HasAVX)) 6571 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6572 getShuffleSHUFImmediate(SVOp), DAG); 6573 6574 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6575 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6576 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6577 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6578 6579 //===--------------------------------------------------------------------===// 6580 // Generate target specific nodes for 128 or 256-bit shuffles only 6581 // supported in the AVX instruction set. 6582 // 6583 6584 // Handle VMOVDDUPY permutations 6585 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6586 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6587 6588 // Handle VPERMILPS/D* permutations 6589 if (isVPERMILPMask(M, VT, HasAVX)) { 6590 if (HasAVX2 && VT == MVT::v8i32) 6591 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6592 getShuffleSHUFImmediate(SVOp), DAG); 6593 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6594 getShuffleSHUFImmediate(SVOp), DAG); 6595 } 6596 6597 // Handle VPERM2F128/VPERM2I128 permutations 6598 if (isVPERM2X128Mask(M, VT, HasAVX)) 6599 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6600 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6601 6602 //===--------------------------------------------------------------------===// 6603 // Since no target specific shuffle was selected for this generic one, 6604 // lower it into other known shuffles. FIXME: this isn't true yet, but 6605 // this is the plan. 6606 // 6607 6608 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6609 if (VT == MVT::v8i16) { 6610 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6611 if (NewOp.getNode()) 6612 return NewOp; 6613 } 6614 6615 if (VT == MVT::v16i8) { 6616 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6617 if (NewOp.getNode()) 6618 return NewOp; 6619 } 6620 6621 // Handle all 128-bit wide vectors with 4 elements, and match them with 6622 // several different shuffle types. 6623 if (NumElems == 4 && VT.getSizeInBits() == 128) 6624 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6625 6626 // Handle general 256-bit shuffles 6627 if (VT.is256BitVector()) 6628 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6629 6630 return SDValue(); 6631} 6632 6633SDValue 6634X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6635 SelectionDAG &DAG) const { 6636 EVT VT = Op.getValueType(); 6637 DebugLoc dl = Op.getDebugLoc(); 6638 6639 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6640 return SDValue(); 6641 6642 if (VT.getSizeInBits() == 8) { 6643 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6644 Op.getOperand(0), Op.getOperand(1)); 6645 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6646 DAG.getValueType(VT)); 6647 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6648 } else if (VT.getSizeInBits() == 16) { 6649 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6650 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6651 if (Idx == 0) 6652 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6654 DAG.getNode(ISD::BITCAST, dl, 6655 MVT::v4i32, 6656 Op.getOperand(0)), 6657 Op.getOperand(1))); 6658 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6659 Op.getOperand(0), Op.getOperand(1)); 6660 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6661 DAG.getValueType(VT)); 6662 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6663 } else if (VT == MVT::f32) { 6664 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6665 // the result back to FR32 register. It's only worth matching if the 6666 // result has a single use which is a store or a bitcast to i32. And in 6667 // the case of a store, it's not worth it if the index is a constant 0, 6668 // because a MOVSSmr can be used instead, which is smaller and faster. 6669 if (!Op.hasOneUse()) 6670 return SDValue(); 6671 SDNode *User = *Op.getNode()->use_begin(); 6672 if ((User->getOpcode() != ISD::STORE || 6673 (isa<ConstantSDNode>(Op.getOperand(1)) && 6674 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6675 (User->getOpcode() != ISD::BITCAST || 6676 User->getValueType(0) != MVT::i32)) 6677 return SDValue(); 6678 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6679 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6680 Op.getOperand(0)), 6681 Op.getOperand(1)); 6682 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6683 } else if (VT == MVT::i32 || VT == MVT::i64) { 6684 // ExtractPS/pextrq works with constant index. 6685 if (isa<ConstantSDNode>(Op.getOperand(1))) 6686 return Op; 6687 } 6688 return SDValue(); 6689} 6690 6691 6692SDValue 6693X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6694 SelectionDAG &DAG) const { 6695 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6696 return SDValue(); 6697 6698 SDValue Vec = Op.getOperand(0); 6699 EVT VecVT = Vec.getValueType(); 6700 6701 // If this is a 256-bit vector result, first extract the 128-bit vector and 6702 // then extract the element from the 128-bit vector. 6703 if (VecVT.getSizeInBits() == 256) { 6704 DebugLoc dl = Op.getNode()->getDebugLoc(); 6705 unsigned NumElems = VecVT.getVectorNumElements(); 6706 SDValue Idx = Op.getOperand(1); 6707 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6708 6709 // Get the 128-bit vector. 6710 bool Upper = IdxVal >= NumElems/2; 6711 Vec = Extract128BitVector(Vec, 6712 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6713 6714 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6715 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6716 } 6717 6718 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6719 6720 if (Subtarget->hasSSE41()) { 6721 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6722 if (Res.getNode()) 6723 return Res; 6724 } 6725 6726 EVT VT = Op.getValueType(); 6727 DebugLoc dl = Op.getDebugLoc(); 6728 // TODO: handle v16i8. 6729 if (VT.getSizeInBits() == 16) { 6730 SDValue Vec = Op.getOperand(0); 6731 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6732 if (Idx == 0) 6733 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6734 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6735 DAG.getNode(ISD::BITCAST, dl, 6736 MVT::v4i32, Vec), 6737 Op.getOperand(1))); 6738 // Transform it so it match pextrw which produces a 32-bit result. 6739 EVT EltVT = MVT::i32; 6740 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6741 Op.getOperand(0), Op.getOperand(1)); 6742 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6743 DAG.getValueType(VT)); 6744 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6745 } else if (VT.getSizeInBits() == 32) { 6746 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6747 if (Idx == 0) 6748 return Op; 6749 6750 // SHUFPS the element to the lowest double word, then movss. 6751 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6752 EVT VVT = Op.getOperand(0).getValueType(); 6753 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6754 DAG.getUNDEF(VVT), Mask); 6755 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6756 DAG.getIntPtrConstant(0)); 6757 } else if (VT.getSizeInBits() == 64) { 6758 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6759 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6760 // to match extract_elt for f64. 6761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6762 if (Idx == 0) 6763 return Op; 6764 6765 // UNPCKHPD the element to the lowest double word, then movsd. 6766 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6767 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6768 int Mask[2] = { 1, -1 }; 6769 EVT VVT = Op.getOperand(0).getValueType(); 6770 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6771 DAG.getUNDEF(VVT), Mask); 6772 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6773 DAG.getIntPtrConstant(0)); 6774 } 6775 6776 return SDValue(); 6777} 6778 6779SDValue 6780X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6781 SelectionDAG &DAG) const { 6782 EVT VT = Op.getValueType(); 6783 EVT EltVT = VT.getVectorElementType(); 6784 DebugLoc dl = Op.getDebugLoc(); 6785 6786 SDValue N0 = Op.getOperand(0); 6787 SDValue N1 = Op.getOperand(1); 6788 SDValue N2 = Op.getOperand(2); 6789 6790 if (VT.getSizeInBits() == 256) 6791 return SDValue(); 6792 6793 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6794 isa<ConstantSDNode>(N2)) { 6795 unsigned Opc; 6796 if (VT == MVT::v8i16) 6797 Opc = X86ISD::PINSRW; 6798 else if (VT == MVT::v16i8) 6799 Opc = X86ISD::PINSRB; 6800 else 6801 Opc = X86ISD::PINSRB; 6802 6803 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6804 // argument. 6805 if (N1.getValueType() != MVT::i32) 6806 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6807 if (N2.getValueType() != MVT::i32) 6808 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6809 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6810 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6811 // Bits [7:6] of the constant are the source select. This will always be 6812 // zero here. The DAG Combiner may combine an extract_elt index into these 6813 // bits. For example (insert (extract, 3), 2) could be matched by putting 6814 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6815 // Bits [5:4] of the constant are the destination select. This is the 6816 // value of the incoming immediate. 6817 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6818 // combine either bitwise AND or insert of float 0.0 to set these bits. 6819 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6820 // Create this as a scalar to vector.. 6821 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6822 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6823 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6824 isa<ConstantSDNode>(N2)) { 6825 // PINSR* works with constant index. 6826 return Op; 6827 } 6828 return SDValue(); 6829} 6830 6831SDValue 6832X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6833 EVT VT = Op.getValueType(); 6834 EVT EltVT = VT.getVectorElementType(); 6835 6836 DebugLoc dl = Op.getDebugLoc(); 6837 SDValue N0 = Op.getOperand(0); 6838 SDValue N1 = Op.getOperand(1); 6839 SDValue N2 = Op.getOperand(2); 6840 6841 // If this is a 256-bit vector result, first extract the 128-bit vector, 6842 // insert the element into the extracted half and then place it back. 6843 if (VT.getSizeInBits() == 256) { 6844 if (!isa<ConstantSDNode>(N2)) 6845 return SDValue(); 6846 6847 // Get the desired 128-bit vector half. 6848 unsigned NumElems = VT.getVectorNumElements(); 6849 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6850 bool Upper = IdxVal >= NumElems/2; 6851 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6852 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6853 6854 // Insert the element into the desired half. 6855 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6856 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6857 6858 // Insert the changed part back to the 256-bit vector 6859 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6860 } 6861 6862 if (Subtarget->hasSSE41()) 6863 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6864 6865 if (EltVT == MVT::i8) 6866 return SDValue(); 6867 6868 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6869 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6870 // as its second argument. 6871 if (N1.getValueType() != MVT::i32) 6872 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6873 if (N2.getValueType() != MVT::i32) 6874 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6875 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6876 } 6877 return SDValue(); 6878} 6879 6880SDValue 6881X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6882 LLVMContext *Context = DAG.getContext(); 6883 DebugLoc dl = Op.getDebugLoc(); 6884 EVT OpVT = Op.getValueType(); 6885 6886 // If this is a 256-bit vector result, first insert into a 128-bit 6887 // vector and then insert into the 256-bit vector. 6888 if (OpVT.getSizeInBits() > 128) { 6889 // Insert into a 128-bit vector. 6890 EVT VT128 = EVT::getVectorVT(*Context, 6891 OpVT.getVectorElementType(), 6892 OpVT.getVectorNumElements() / 2); 6893 6894 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6895 6896 // Insert the 128-bit vector. 6897 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6898 DAG.getConstant(0, MVT::i32), 6899 DAG, dl); 6900 } 6901 6902 if (Op.getValueType() == MVT::v1i64 && 6903 Op.getOperand(0).getValueType() == MVT::i64) 6904 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6905 6906 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6907 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6908 "Expected an SSE type!"); 6909 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6910 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6911} 6912 6913// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6914// a simple subregister reference or explicit instructions to grab 6915// upper bits of a vector. 6916SDValue 6917X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6918 if (Subtarget->hasAVX()) { 6919 DebugLoc dl = Op.getNode()->getDebugLoc(); 6920 SDValue Vec = Op.getNode()->getOperand(0); 6921 SDValue Idx = Op.getNode()->getOperand(1); 6922 6923 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6924 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6925 return Extract128BitVector(Vec, Idx, DAG, dl); 6926 } 6927 } 6928 return SDValue(); 6929} 6930 6931// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6932// simple superregister reference or explicit instructions to insert 6933// the upper bits of a vector. 6934SDValue 6935X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6936 if (Subtarget->hasAVX()) { 6937 DebugLoc dl = Op.getNode()->getDebugLoc(); 6938 SDValue Vec = Op.getNode()->getOperand(0); 6939 SDValue SubVec = Op.getNode()->getOperand(1); 6940 SDValue Idx = Op.getNode()->getOperand(2); 6941 6942 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6943 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6944 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6945 } 6946 } 6947 return SDValue(); 6948} 6949 6950// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6951// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6952// one of the above mentioned nodes. It has to be wrapped because otherwise 6953// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6954// be used to form addressing mode. These wrapped nodes will be selected 6955// into MOV32ri. 6956SDValue 6957X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6958 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6959 6960 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6961 // global base reg. 6962 unsigned char OpFlag = 0; 6963 unsigned WrapperKind = X86ISD::Wrapper; 6964 CodeModel::Model M = getTargetMachine().getCodeModel(); 6965 6966 if (Subtarget->isPICStyleRIPRel() && 6967 (M == CodeModel::Small || M == CodeModel::Kernel)) 6968 WrapperKind = X86ISD::WrapperRIP; 6969 else if (Subtarget->isPICStyleGOT()) 6970 OpFlag = X86II::MO_GOTOFF; 6971 else if (Subtarget->isPICStyleStubPIC()) 6972 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6973 6974 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6975 CP->getAlignment(), 6976 CP->getOffset(), OpFlag); 6977 DebugLoc DL = CP->getDebugLoc(); 6978 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6979 // With PIC, the address is actually $g + Offset. 6980 if (OpFlag) { 6981 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6982 DAG.getNode(X86ISD::GlobalBaseReg, 6983 DebugLoc(), getPointerTy()), 6984 Result); 6985 } 6986 6987 return Result; 6988} 6989 6990SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 6991 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 6992 6993 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6994 // global base reg. 6995 unsigned char OpFlag = 0; 6996 unsigned WrapperKind = X86ISD::Wrapper; 6997 CodeModel::Model M = getTargetMachine().getCodeModel(); 6998 6999 if (Subtarget->isPICStyleRIPRel() && 7000 (M == CodeModel::Small || M == CodeModel::Kernel)) 7001 WrapperKind = X86ISD::WrapperRIP; 7002 else if (Subtarget->isPICStyleGOT()) 7003 OpFlag = X86II::MO_GOTOFF; 7004 else if (Subtarget->isPICStyleStubPIC()) 7005 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7006 7007 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7008 OpFlag); 7009 DebugLoc DL = JT->getDebugLoc(); 7010 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7011 7012 // With PIC, the address is actually $g + Offset. 7013 if (OpFlag) 7014 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7015 DAG.getNode(X86ISD::GlobalBaseReg, 7016 DebugLoc(), getPointerTy()), 7017 Result); 7018 7019 return Result; 7020} 7021 7022SDValue 7023X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7024 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7025 7026 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7027 // global base reg. 7028 unsigned char OpFlag = 0; 7029 unsigned WrapperKind = X86ISD::Wrapper; 7030 CodeModel::Model M = getTargetMachine().getCodeModel(); 7031 7032 if (Subtarget->isPICStyleRIPRel() && 7033 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7034 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7035 OpFlag = X86II::MO_GOTPCREL; 7036 WrapperKind = X86ISD::WrapperRIP; 7037 } else if (Subtarget->isPICStyleGOT()) { 7038 OpFlag = X86II::MO_GOT; 7039 } else if (Subtarget->isPICStyleStubPIC()) { 7040 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7041 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7042 OpFlag = X86II::MO_DARWIN_NONLAZY; 7043 } 7044 7045 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7046 7047 DebugLoc DL = Op.getDebugLoc(); 7048 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7049 7050 7051 // With PIC, the address is actually $g + Offset. 7052 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7053 !Subtarget->is64Bit()) { 7054 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7055 DAG.getNode(X86ISD::GlobalBaseReg, 7056 DebugLoc(), getPointerTy()), 7057 Result); 7058 } 7059 7060 // For symbols that require a load from a stub to get the address, emit the 7061 // load. 7062 if (isGlobalStubReference(OpFlag)) 7063 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7064 MachinePointerInfo::getGOT(), false, false, false, 0); 7065 7066 return Result; 7067} 7068 7069SDValue 7070X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7071 // Create the TargetBlockAddressAddress node. 7072 unsigned char OpFlags = 7073 Subtarget->ClassifyBlockAddressReference(); 7074 CodeModel::Model M = getTargetMachine().getCodeModel(); 7075 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7076 DebugLoc dl = Op.getDebugLoc(); 7077 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7078 /*isTarget=*/true, OpFlags); 7079 7080 if (Subtarget->isPICStyleRIPRel() && 7081 (M == CodeModel::Small || M == CodeModel::Kernel)) 7082 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7083 else 7084 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7085 7086 // With PIC, the address is actually $g + Offset. 7087 if (isGlobalRelativeToPICBase(OpFlags)) { 7088 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7089 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7090 Result); 7091 } 7092 7093 return Result; 7094} 7095 7096SDValue 7097X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7098 int64_t Offset, 7099 SelectionDAG &DAG) const { 7100 // Create the TargetGlobalAddress node, folding in the constant 7101 // offset if it is legal. 7102 unsigned char OpFlags = 7103 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7104 CodeModel::Model M = getTargetMachine().getCodeModel(); 7105 SDValue Result; 7106 if (OpFlags == X86II::MO_NO_FLAG && 7107 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7108 // A direct static reference to a global. 7109 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7110 Offset = 0; 7111 } else { 7112 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7113 } 7114 7115 if (Subtarget->isPICStyleRIPRel() && 7116 (M == CodeModel::Small || M == CodeModel::Kernel)) 7117 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7118 else 7119 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7120 7121 // With PIC, the address is actually $g + Offset. 7122 if (isGlobalRelativeToPICBase(OpFlags)) { 7123 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7124 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7125 Result); 7126 } 7127 7128 // For globals that require a load from a stub to get the address, emit the 7129 // load. 7130 if (isGlobalStubReference(OpFlags)) 7131 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7132 MachinePointerInfo::getGOT(), false, false, false, 0); 7133 7134 // If there was a non-zero offset that we didn't fold, create an explicit 7135 // addition for it. 7136 if (Offset != 0) 7137 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7138 DAG.getConstant(Offset, getPointerTy())); 7139 7140 return Result; 7141} 7142 7143SDValue 7144X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7145 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7146 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7147 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7148} 7149 7150static SDValue 7151GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7152 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7153 unsigned char OperandFlags) { 7154 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7155 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7156 DebugLoc dl = GA->getDebugLoc(); 7157 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7158 GA->getValueType(0), 7159 GA->getOffset(), 7160 OperandFlags); 7161 if (InFlag) { 7162 SDValue Ops[] = { Chain, TGA, *InFlag }; 7163 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7164 } else { 7165 SDValue Ops[] = { Chain, TGA }; 7166 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7167 } 7168 7169 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7170 MFI->setAdjustsStack(true); 7171 7172 SDValue Flag = Chain.getValue(1); 7173 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7174} 7175 7176// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7177static SDValue 7178LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7179 const EVT PtrVT) { 7180 SDValue InFlag; 7181 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7182 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7183 DAG.getNode(X86ISD::GlobalBaseReg, 7184 DebugLoc(), PtrVT), InFlag); 7185 InFlag = Chain.getValue(1); 7186 7187 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7188} 7189 7190// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7191static SDValue 7192LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7193 const EVT PtrVT) { 7194 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7195 X86::RAX, X86II::MO_TLSGD); 7196} 7197 7198// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7199// "local exec" model. 7200static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7201 const EVT PtrVT, TLSModel::Model model, 7202 bool is64Bit) { 7203 DebugLoc dl = GA->getDebugLoc(); 7204 7205 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7206 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7207 is64Bit ? 257 : 256)); 7208 7209 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7210 DAG.getIntPtrConstant(0), 7211 MachinePointerInfo(Ptr), 7212 false, false, false, 0); 7213 7214 unsigned char OperandFlags = 0; 7215 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7216 // initialexec. 7217 unsigned WrapperKind = X86ISD::Wrapper; 7218 if (model == TLSModel::LocalExec) { 7219 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7220 } else if (is64Bit) { 7221 assert(model == TLSModel::InitialExec); 7222 OperandFlags = X86II::MO_GOTTPOFF; 7223 WrapperKind = X86ISD::WrapperRIP; 7224 } else { 7225 assert(model == TLSModel::InitialExec); 7226 OperandFlags = X86II::MO_INDNTPOFF; 7227 } 7228 7229 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7230 // exec) 7231 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7232 GA->getValueType(0), 7233 GA->getOffset(), OperandFlags); 7234 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7235 7236 if (model == TLSModel::InitialExec) 7237 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7238 MachinePointerInfo::getGOT(), false, false, false, 0); 7239 7240 // The address of the thread local variable is the add of the thread 7241 // pointer with the offset of the variable. 7242 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7243} 7244 7245SDValue 7246X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7247 7248 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7249 const GlobalValue *GV = GA->getGlobal(); 7250 7251 if (Subtarget->isTargetELF()) { 7252 // TODO: implement the "local dynamic" model 7253 // TODO: implement the "initial exec"model for pic executables 7254 7255 // If GV is an alias then use the aliasee for determining 7256 // thread-localness. 7257 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7258 GV = GA->resolveAliasedGlobal(false); 7259 7260 TLSModel::Model model 7261 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7262 7263 switch (model) { 7264 case TLSModel::GeneralDynamic: 7265 case TLSModel::LocalDynamic: // not implemented 7266 if (Subtarget->is64Bit()) 7267 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7268 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7269 7270 case TLSModel::InitialExec: 7271 case TLSModel::LocalExec: 7272 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7273 Subtarget->is64Bit()); 7274 } 7275 } else if (Subtarget->isTargetDarwin()) { 7276 // Darwin only has one model of TLS. Lower to that. 7277 unsigned char OpFlag = 0; 7278 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7279 X86ISD::WrapperRIP : X86ISD::Wrapper; 7280 7281 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7282 // global base reg. 7283 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7284 !Subtarget->is64Bit(); 7285 if (PIC32) 7286 OpFlag = X86II::MO_TLVP_PIC_BASE; 7287 else 7288 OpFlag = X86II::MO_TLVP; 7289 DebugLoc DL = Op.getDebugLoc(); 7290 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7291 GA->getValueType(0), 7292 GA->getOffset(), OpFlag); 7293 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7294 7295 // With PIC32, the address is actually $g + Offset. 7296 if (PIC32) 7297 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7298 DAG.getNode(X86ISD::GlobalBaseReg, 7299 DebugLoc(), getPointerTy()), 7300 Offset); 7301 7302 // Lowering the machine isd will make sure everything is in the right 7303 // location. 7304 SDValue Chain = DAG.getEntryNode(); 7305 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7306 SDValue Args[] = { Chain, Offset }; 7307 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7308 7309 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7310 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7311 MFI->setAdjustsStack(true); 7312 7313 // And our return value (tls address) is in the standard call return value 7314 // location. 7315 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7316 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7317 Chain.getValue(1)); 7318 } else if (Subtarget->isTargetWindows()) { 7319 // Just use the implicit TLS architecture 7320 // Need to generate someting similar to: 7321 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7322 // ; from TEB 7323 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7324 // mov rcx, qword [rdx+rcx*8] 7325 // mov eax, .tls$:tlsvar 7326 // [rax+rcx] contains the address 7327 // Windows 64bit: gs:0x58 7328 // Windows 32bit: fs:__tls_array 7329 7330 // If GV is an alias then use the aliasee for determining 7331 // thread-localness. 7332 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7333 GV = GA->resolveAliasedGlobal(false); 7334 DebugLoc dl = GA->getDebugLoc(); 7335 SDValue Chain = DAG.getEntryNode(); 7336 7337 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7338 // %gs:0x58 (64-bit). 7339 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7340 ? Type::getInt8PtrTy(*DAG.getContext(), 7341 256) 7342 : Type::getInt32PtrTy(*DAG.getContext(), 7343 257)); 7344 7345 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7346 Subtarget->is64Bit() 7347 ? DAG.getIntPtrConstant(0x58) 7348 : DAG.getExternalSymbol("_tls_array", 7349 getPointerTy()), 7350 MachinePointerInfo(Ptr), 7351 false, false, false, 0); 7352 7353 // Load the _tls_index variable 7354 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7355 if (Subtarget->is64Bit()) 7356 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7357 IDX, MachinePointerInfo(), MVT::i32, 7358 false, false, 0); 7359 else 7360 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7361 false, false, false, 0); 7362 7363 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7364 getPointerTy()); 7365 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7366 7367 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7368 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7369 false, false, false, 0); 7370 7371 // Get the offset of start of .tls section 7372 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7373 GA->getValueType(0), 7374 GA->getOffset(), X86II::MO_SECREL); 7375 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7376 7377 // The address of the thread local variable is the add of the thread 7378 // pointer with the offset of the variable. 7379 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7380 } 7381 7382 llvm_unreachable("TLS not implemented for this target."); 7383} 7384 7385 7386/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7387/// and take a 2 x i32 value to shift plus a shift amount. 7388SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7389 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7390 EVT VT = Op.getValueType(); 7391 unsigned VTBits = VT.getSizeInBits(); 7392 DebugLoc dl = Op.getDebugLoc(); 7393 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7394 SDValue ShOpLo = Op.getOperand(0); 7395 SDValue ShOpHi = Op.getOperand(1); 7396 SDValue ShAmt = Op.getOperand(2); 7397 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7398 DAG.getConstant(VTBits - 1, MVT::i8)) 7399 : DAG.getConstant(0, VT); 7400 7401 SDValue Tmp2, Tmp3; 7402 if (Op.getOpcode() == ISD::SHL_PARTS) { 7403 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7404 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7405 } else { 7406 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7407 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7408 } 7409 7410 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7411 DAG.getConstant(VTBits, MVT::i8)); 7412 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7413 AndNode, DAG.getConstant(0, MVT::i8)); 7414 7415 SDValue Hi, Lo; 7416 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7417 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7418 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7419 7420 if (Op.getOpcode() == ISD::SHL_PARTS) { 7421 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7422 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7423 } else { 7424 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7425 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7426 } 7427 7428 SDValue Ops[2] = { Lo, Hi }; 7429 return DAG.getMergeValues(Ops, 2, dl); 7430} 7431 7432SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7433 SelectionDAG &DAG) const { 7434 EVT SrcVT = Op.getOperand(0).getValueType(); 7435 7436 if (SrcVT.isVector()) 7437 return SDValue(); 7438 7439 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7440 "Unknown SINT_TO_FP to lower!"); 7441 7442 // These are really Legal; return the operand so the caller accepts it as 7443 // Legal. 7444 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7445 return Op; 7446 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7447 Subtarget->is64Bit()) { 7448 return Op; 7449 } 7450 7451 DebugLoc dl = Op.getDebugLoc(); 7452 unsigned Size = SrcVT.getSizeInBits()/8; 7453 MachineFunction &MF = DAG.getMachineFunction(); 7454 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7455 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7456 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7457 StackSlot, 7458 MachinePointerInfo::getFixedStack(SSFI), 7459 false, false, 0); 7460 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7461} 7462 7463SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7464 SDValue StackSlot, 7465 SelectionDAG &DAG) const { 7466 // Build the FILD 7467 DebugLoc DL = Op.getDebugLoc(); 7468 SDVTList Tys; 7469 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7470 if (useSSE) 7471 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7472 else 7473 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7474 7475 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7476 7477 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7478 MachineMemOperand *MMO; 7479 if (FI) { 7480 int SSFI = FI->getIndex(); 7481 MMO = 7482 DAG.getMachineFunction() 7483 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7484 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7485 } else { 7486 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7487 StackSlot = StackSlot.getOperand(1); 7488 } 7489 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7490 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7491 X86ISD::FILD, DL, 7492 Tys, Ops, array_lengthof(Ops), 7493 SrcVT, MMO); 7494 7495 if (useSSE) { 7496 Chain = Result.getValue(1); 7497 SDValue InFlag = Result.getValue(2); 7498 7499 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7500 // shouldn't be necessary except that RFP cannot be live across 7501 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7502 MachineFunction &MF = DAG.getMachineFunction(); 7503 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7504 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7505 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7506 Tys = DAG.getVTList(MVT::Other); 7507 SDValue Ops[] = { 7508 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7509 }; 7510 MachineMemOperand *MMO = 7511 DAG.getMachineFunction() 7512 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7513 MachineMemOperand::MOStore, SSFISize, SSFISize); 7514 7515 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7516 Ops, array_lengthof(Ops), 7517 Op.getValueType(), MMO); 7518 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7519 MachinePointerInfo::getFixedStack(SSFI), 7520 false, false, false, 0); 7521 } 7522 7523 return Result; 7524} 7525 7526// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7527SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7528 SelectionDAG &DAG) const { 7529 // This algorithm is not obvious. Here it is what we're trying to output: 7530 /* 7531 movq %rax, %xmm0 7532 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7533 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7534 #ifdef __SSE3__ 7535 haddpd %xmm0, %xmm0 7536 #else 7537 pshufd $0x4e, %xmm0, %xmm1 7538 addpd %xmm1, %xmm0 7539 #endif 7540 */ 7541 7542 DebugLoc dl = Op.getDebugLoc(); 7543 LLVMContext *Context = DAG.getContext(); 7544 7545 // Build some magic constants. 7546 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7547 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7548 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7549 7550 SmallVector<Constant*,2> CV1; 7551 CV1.push_back( 7552 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7553 CV1.push_back( 7554 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7555 Constant *C1 = ConstantVector::get(CV1); 7556 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7557 7558 // Load the 64-bit value into an XMM register. 7559 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7560 Op.getOperand(0)); 7561 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7562 MachinePointerInfo::getConstantPool(), 7563 false, false, false, 16); 7564 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7565 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7566 CLod0); 7567 7568 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7569 MachinePointerInfo::getConstantPool(), 7570 false, false, false, 16); 7571 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7572 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7573 SDValue Result; 7574 7575 if (Subtarget->hasSSE3()) { 7576 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7577 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7578 } else { 7579 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7580 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7581 S2F, 0x4E, DAG); 7582 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7583 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7584 Sub); 7585 } 7586 7587 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7588 DAG.getIntPtrConstant(0)); 7589} 7590 7591// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7592SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7593 SelectionDAG &DAG) const { 7594 DebugLoc dl = Op.getDebugLoc(); 7595 // FP constant to bias correct the final result. 7596 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7597 MVT::f64); 7598 7599 // Load the 32-bit value into an XMM register. 7600 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7601 Op.getOperand(0)); 7602 7603 // Zero out the upper parts of the register. 7604 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7605 7606 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7607 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7608 DAG.getIntPtrConstant(0)); 7609 7610 // Or the load with the bias. 7611 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7612 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7613 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7614 MVT::v2f64, Load)), 7615 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7616 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7617 MVT::v2f64, Bias))); 7618 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7619 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7620 DAG.getIntPtrConstant(0)); 7621 7622 // Subtract the bias. 7623 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7624 7625 // Handle final rounding. 7626 EVT DestVT = Op.getValueType(); 7627 7628 if (DestVT.bitsLT(MVT::f64)) { 7629 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7630 DAG.getIntPtrConstant(0)); 7631 } else if (DestVT.bitsGT(MVT::f64)) { 7632 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7633 } 7634 7635 // Handle final rounding. 7636 return Sub; 7637} 7638 7639SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7640 SelectionDAG &DAG) const { 7641 SDValue N0 = Op.getOperand(0); 7642 DebugLoc dl = Op.getDebugLoc(); 7643 7644 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7645 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7646 // the optimization here. 7647 if (DAG.SignBitIsZero(N0)) 7648 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7649 7650 EVT SrcVT = N0.getValueType(); 7651 EVT DstVT = Op.getValueType(); 7652 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7653 return LowerUINT_TO_FP_i64(Op, DAG); 7654 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7655 return LowerUINT_TO_FP_i32(Op, DAG); 7656 else if (Subtarget->is64Bit() && 7657 SrcVT == MVT::i64 && DstVT == MVT::f32) 7658 return SDValue(); 7659 7660 // Make a 64-bit buffer, and use it to build an FILD. 7661 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7662 if (SrcVT == MVT::i32) { 7663 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7664 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7665 getPointerTy(), StackSlot, WordOff); 7666 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7667 StackSlot, MachinePointerInfo(), 7668 false, false, 0); 7669 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7670 OffsetSlot, MachinePointerInfo(), 7671 false, false, 0); 7672 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7673 return Fild; 7674 } 7675 7676 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7677 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7678 StackSlot, MachinePointerInfo(), 7679 false, false, 0); 7680 // For i64 source, we need to add the appropriate power of 2 if the input 7681 // was negative. This is the same as the optimization in 7682 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7683 // we must be careful to do the computation in x87 extended precision, not 7684 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7685 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7686 MachineMemOperand *MMO = 7687 DAG.getMachineFunction() 7688 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7689 MachineMemOperand::MOLoad, 8, 8); 7690 7691 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7692 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7693 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7694 MVT::i64, MMO); 7695 7696 APInt FF(32, 0x5F800000ULL); 7697 7698 // Check whether the sign bit is set. 7699 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7700 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7701 ISD::SETLT); 7702 7703 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7704 SDValue FudgePtr = DAG.getConstantPool( 7705 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7706 getPointerTy()); 7707 7708 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7709 SDValue Zero = DAG.getIntPtrConstant(0); 7710 SDValue Four = DAG.getIntPtrConstant(4); 7711 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7712 Zero, Four); 7713 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7714 7715 // Load the value out, extending it from f32 to f80. 7716 // FIXME: Avoid the extend by constructing the right constant pool? 7717 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7718 FudgePtr, MachinePointerInfo::getConstantPool(), 7719 MVT::f32, false, false, 4); 7720 // Extend everything to 80 bits to force it to be done on x87. 7721 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7722 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7723} 7724 7725std::pair<SDValue,SDValue> X86TargetLowering:: 7726FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7727 DebugLoc DL = Op.getDebugLoc(); 7728 7729 EVT DstTy = Op.getValueType(); 7730 7731 if (!IsSigned) { 7732 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7733 DstTy = MVT::i64; 7734 } 7735 7736 assert(DstTy.getSimpleVT() <= MVT::i64 && 7737 DstTy.getSimpleVT() >= MVT::i16 && 7738 "Unknown FP_TO_SINT to lower!"); 7739 7740 // These are really Legal. 7741 if (DstTy == MVT::i32 && 7742 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7743 return std::make_pair(SDValue(), SDValue()); 7744 if (Subtarget->is64Bit() && 7745 DstTy == MVT::i64 && 7746 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7747 return std::make_pair(SDValue(), SDValue()); 7748 7749 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7750 // stack slot. 7751 MachineFunction &MF = DAG.getMachineFunction(); 7752 unsigned MemSize = DstTy.getSizeInBits()/8; 7753 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7754 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7755 7756 7757 7758 unsigned Opc; 7759 switch (DstTy.getSimpleVT().SimpleTy) { 7760 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7761 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7762 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7763 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7764 } 7765 7766 SDValue Chain = DAG.getEntryNode(); 7767 SDValue Value = Op.getOperand(0); 7768 EVT TheVT = Op.getOperand(0).getValueType(); 7769 if (isScalarFPTypeInSSEReg(TheVT)) { 7770 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7771 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7772 MachinePointerInfo::getFixedStack(SSFI), 7773 false, false, 0); 7774 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7775 SDValue Ops[] = { 7776 Chain, StackSlot, DAG.getValueType(TheVT) 7777 }; 7778 7779 MachineMemOperand *MMO = 7780 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7781 MachineMemOperand::MOLoad, MemSize, MemSize); 7782 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7783 DstTy, MMO); 7784 Chain = Value.getValue(1); 7785 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7786 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7787 } 7788 7789 MachineMemOperand *MMO = 7790 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7791 MachineMemOperand::MOStore, MemSize, MemSize); 7792 7793 // Build the FP_TO_INT*_IN_MEM 7794 SDValue Ops[] = { Chain, Value, StackSlot }; 7795 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7796 Ops, 3, DstTy, MMO); 7797 7798 return std::make_pair(FIST, StackSlot); 7799} 7800 7801SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7802 SelectionDAG &DAG) const { 7803 if (Op.getValueType().isVector()) 7804 return SDValue(); 7805 7806 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7807 SDValue FIST = Vals.first, StackSlot = Vals.second; 7808 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7809 if (FIST.getNode() == 0) return Op; 7810 7811 // Load the result. 7812 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7813 FIST, StackSlot, MachinePointerInfo(), 7814 false, false, false, 0); 7815} 7816 7817SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7818 SelectionDAG &DAG) const { 7819 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7820 SDValue FIST = Vals.first, StackSlot = Vals.second; 7821 assert(FIST.getNode() && "Unexpected failure"); 7822 7823 // Load the result. 7824 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7825 FIST, StackSlot, MachinePointerInfo(), 7826 false, false, false, 0); 7827} 7828 7829SDValue X86TargetLowering::LowerFABS(SDValue Op, 7830 SelectionDAG &DAG) const { 7831 LLVMContext *Context = DAG.getContext(); 7832 DebugLoc dl = Op.getDebugLoc(); 7833 EVT VT = Op.getValueType(); 7834 EVT EltVT = VT; 7835 if (VT.isVector()) 7836 EltVT = VT.getVectorElementType(); 7837 Constant *C; 7838 if (EltVT == MVT::f64) { 7839 C = ConstantVector::getSplat(2, 7840 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7841 } else { 7842 C = ConstantVector::getSplat(4, 7843 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7844 } 7845 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7846 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7847 MachinePointerInfo::getConstantPool(), 7848 false, false, false, 16); 7849 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7850} 7851 7852SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7853 LLVMContext *Context = DAG.getContext(); 7854 DebugLoc dl = Op.getDebugLoc(); 7855 EVT VT = Op.getValueType(); 7856 EVT EltVT = VT; 7857 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7858 if (VT.isVector()) { 7859 EltVT = VT.getVectorElementType(); 7860 NumElts = VT.getVectorNumElements(); 7861 } 7862 Constant *C; 7863 if (EltVT == MVT::f64) 7864 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7865 else 7866 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7867 C = ConstantVector::getSplat(NumElts, C); 7868 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7869 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7870 MachinePointerInfo::getConstantPool(), 7871 false, false, false, 16); 7872 if (VT.isVector()) { 7873 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7874 return DAG.getNode(ISD::BITCAST, dl, VT, 7875 DAG.getNode(ISD::XOR, dl, XORVT, 7876 DAG.getNode(ISD::BITCAST, dl, XORVT, 7877 Op.getOperand(0)), 7878 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7879 } else { 7880 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7881 } 7882} 7883 7884SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7885 LLVMContext *Context = DAG.getContext(); 7886 SDValue Op0 = Op.getOperand(0); 7887 SDValue Op1 = Op.getOperand(1); 7888 DebugLoc dl = Op.getDebugLoc(); 7889 EVT VT = Op.getValueType(); 7890 EVT SrcVT = Op1.getValueType(); 7891 7892 // If second operand is smaller, extend it first. 7893 if (SrcVT.bitsLT(VT)) { 7894 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7895 SrcVT = VT; 7896 } 7897 // And if it is bigger, shrink it first. 7898 if (SrcVT.bitsGT(VT)) { 7899 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7900 SrcVT = VT; 7901 } 7902 7903 // At this point the operands and the result should have the same 7904 // type, and that won't be f80 since that is not custom lowered. 7905 7906 // First get the sign bit of second operand. 7907 SmallVector<Constant*,4> CV; 7908 if (SrcVT == MVT::f64) { 7909 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7910 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7911 } else { 7912 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7913 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7914 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7915 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7916 } 7917 Constant *C = ConstantVector::get(CV); 7918 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7919 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7920 MachinePointerInfo::getConstantPool(), 7921 false, false, false, 16); 7922 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7923 7924 // Shift sign bit right or left if the two operands have different types. 7925 if (SrcVT.bitsGT(VT)) { 7926 // Op0 is MVT::f32, Op1 is MVT::f64. 7927 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7928 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7929 DAG.getConstant(32, MVT::i32)); 7930 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7931 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7932 DAG.getIntPtrConstant(0)); 7933 } 7934 7935 // Clear first operand sign bit. 7936 CV.clear(); 7937 if (VT == MVT::f64) { 7938 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7939 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7940 } else { 7941 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7942 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7943 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7944 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7945 } 7946 C = ConstantVector::get(CV); 7947 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7948 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7949 MachinePointerInfo::getConstantPool(), 7950 false, false, false, 16); 7951 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7952 7953 // Or the value with the sign bit. 7954 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7955} 7956 7957SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7958 SDValue N0 = Op.getOperand(0); 7959 DebugLoc dl = Op.getDebugLoc(); 7960 EVT VT = Op.getValueType(); 7961 7962 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 7963 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 7964 DAG.getConstant(1, VT)); 7965 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 7966} 7967 7968/// Emit nodes that will be selected as "test Op0,Op0", or something 7969/// equivalent. 7970SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 7971 SelectionDAG &DAG) const { 7972 DebugLoc dl = Op.getDebugLoc(); 7973 7974 // CF and OF aren't always set the way we want. Determine which 7975 // of these we need. 7976 bool NeedCF = false; 7977 bool NeedOF = false; 7978 switch (X86CC) { 7979 default: break; 7980 case X86::COND_A: case X86::COND_AE: 7981 case X86::COND_B: case X86::COND_BE: 7982 NeedCF = true; 7983 break; 7984 case X86::COND_G: case X86::COND_GE: 7985 case X86::COND_L: case X86::COND_LE: 7986 case X86::COND_O: case X86::COND_NO: 7987 NeedOF = true; 7988 break; 7989 } 7990 7991 // See if we can use the EFLAGS value from the operand instead of 7992 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 7993 // we prove that the arithmetic won't overflow, we can't use OF or CF. 7994 if (Op.getResNo() != 0 || NeedOF || NeedCF) 7995 // Emit a CMP with 0, which is the TEST pattern. 7996 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7997 DAG.getConstant(0, Op.getValueType())); 7998 7999 unsigned Opcode = 0; 8000 unsigned NumOperands = 0; 8001 switch (Op.getNode()->getOpcode()) { 8002 case ISD::ADD: 8003 // Due to an isel shortcoming, be conservative if this add is likely to be 8004 // selected as part of a load-modify-store instruction. When the root node 8005 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8006 // uses of other nodes in the match, such as the ADD in this case. This 8007 // leads to the ADD being left around and reselected, with the result being 8008 // two adds in the output. Alas, even if none our users are stores, that 8009 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8010 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8011 // climbing the DAG back to the root, and it doesn't seem to be worth the 8012 // effort. 8013 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8014 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8015 if (UI->getOpcode() != ISD::CopyToReg && 8016 UI->getOpcode() != ISD::SETCC && 8017 UI->getOpcode() != ISD::STORE) 8018 goto default_case; 8019 8020 if (ConstantSDNode *C = 8021 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8022 // An add of one will be selected as an INC. 8023 if (C->getAPIntValue() == 1) { 8024 Opcode = X86ISD::INC; 8025 NumOperands = 1; 8026 break; 8027 } 8028 8029 // An add of negative one (subtract of one) will be selected as a DEC. 8030 if (C->getAPIntValue().isAllOnesValue()) { 8031 Opcode = X86ISD::DEC; 8032 NumOperands = 1; 8033 break; 8034 } 8035 } 8036 8037 // Otherwise use a regular EFLAGS-setting add. 8038 Opcode = X86ISD::ADD; 8039 NumOperands = 2; 8040 break; 8041 case ISD::AND: { 8042 // If the primary and result isn't used, don't bother using X86ISD::AND, 8043 // because a TEST instruction will be better. 8044 bool NonFlagUse = false; 8045 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8046 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8047 SDNode *User = *UI; 8048 unsigned UOpNo = UI.getOperandNo(); 8049 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8050 // Look pass truncate. 8051 UOpNo = User->use_begin().getOperandNo(); 8052 User = *User->use_begin(); 8053 } 8054 8055 if (User->getOpcode() != ISD::BRCOND && 8056 User->getOpcode() != ISD::SETCC && 8057 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8058 NonFlagUse = true; 8059 break; 8060 } 8061 } 8062 8063 if (!NonFlagUse) 8064 break; 8065 } 8066 // FALL THROUGH 8067 case ISD::SUB: 8068 case ISD::OR: 8069 case ISD::XOR: 8070 // Due to the ISEL shortcoming noted above, be conservative if this op is 8071 // likely to be selected as part of a load-modify-store instruction. 8072 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8073 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8074 if (UI->getOpcode() == ISD::STORE) 8075 goto default_case; 8076 8077 // Otherwise use a regular EFLAGS-setting instruction. 8078 switch (Op.getNode()->getOpcode()) { 8079 default: llvm_unreachable("unexpected operator!"); 8080 case ISD::SUB: Opcode = X86ISD::SUB; break; 8081 case ISD::OR: Opcode = X86ISD::OR; break; 8082 case ISD::XOR: Opcode = X86ISD::XOR; break; 8083 case ISD::AND: Opcode = X86ISD::AND; break; 8084 } 8085 8086 NumOperands = 2; 8087 break; 8088 case X86ISD::ADD: 8089 case X86ISD::SUB: 8090 case X86ISD::INC: 8091 case X86ISD::DEC: 8092 case X86ISD::OR: 8093 case X86ISD::XOR: 8094 case X86ISD::AND: 8095 return SDValue(Op.getNode(), 1); 8096 default: 8097 default_case: 8098 break; 8099 } 8100 8101 if (Opcode == 0) 8102 // Emit a CMP with 0, which is the TEST pattern. 8103 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8104 DAG.getConstant(0, Op.getValueType())); 8105 8106 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8107 SmallVector<SDValue, 4> Ops; 8108 for (unsigned i = 0; i != NumOperands; ++i) 8109 Ops.push_back(Op.getOperand(i)); 8110 8111 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8112 DAG.ReplaceAllUsesWith(Op, New); 8113 return SDValue(New.getNode(), 1); 8114} 8115 8116/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8117/// equivalent. 8118SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8119 SelectionDAG &DAG) const { 8120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8121 if (C->getAPIntValue() == 0) 8122 return EmitTest(Op0, X86CC, DAG); 8123 8124 DebugLoc dl = Op0.getDebugLoc(); 8125 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8126} 8127 8128/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8129/// if it's possible. 8130SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8131 DebugLoc dl, SelectionDAG &DAG) const { 8132 SDValue Op0 = And.getOperand(0); 8133 SDValue Op1 = And.getOperand(1); 8134 if (Op0.getOpcode() == ISD::TRUNCATE) 8135 Op0 = Op0.getOperand(0); 8136 if (Op1.getOpcode() == ISD::TRUNCATE) 8137 Op1 = Op1.getOperand(0); 8138 8139 SDValue LHS, RHS; 8140 if (Op1.getOpcode() == ISD::SHL) 8141 std::swap(Op0, Op1); 8142 if (Op0.getOpcode() == ISD::SHL) { 8143 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8144 if (And00C->getZExtValue() == 1) { 8145 // If we looked past a truncate, check that it's only truncating away 8146 // known zeros. 8147 unsigned BitWidth = Op0.getValueSizeInBits(); 8148 unsigned AndBitWidth = And.getValueSizeInBits(); 8149 if (BitWidth > AndBitWidth) { 8150 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8151 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8152 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8153 return SDValue(); 8154 } 8155 LHS = Op1; 8156 RHS = Op0.getOperand(1); 8157 } 8158 } else if (Op1.getOpcode() == ISD::Constant) { 8159 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8160 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8161 SDValue AndLHS = Op0; 8162 8163 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8164 LHS = AndLHS.getOperand(0); 8165 RHS = AndLHS.getOperand(1); 8166 } 8167 8168 // Use BT if the immediate can't be encoded in a TEST instruction. 8169 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8170 LHS = AndLHS; 8171 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8172 } 8173 } 8174 8175 if (LHS.getNode()) { 8176 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8177 // instruction. Since the shift amount is in-range-or-undefined, we know 8178 // that doing a bittest on the i32 value is ok. We extend to i32 because 8179 // the encoding for the i16 version is larger than the i32 version. 8180 // Also promote i16 to i32 for performance / code size reason. 8181 if (LHS.getValueType() == MVT::i8 || 8182 LHS.getValueType() == MVT::i16) 8183 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8184 8185 // If the operand types disagree, extend the shift amount to match. Since 8186 // BT ignores high bits (like shifts) we can use anyextend. 8187 if (LHS.getValueType() != RHS.getValueType()) 8188 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8189 8190 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8191 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8192 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8193 DAG.getConstant(Cond, MVT::i8), BT); 8194 } 8195 8196 return SDValue(); 8197} 8198 8199SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8200 8201 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8202 8203 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8204 SDValue Op0 = Op.getOperand(0); 8205 SDValue Op1 = Op.getOperand(1); 8206 DebugLoc dl = Op.getDebugLoc(); 8207 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8208 8209 // Optimize to BT if possible. 8210 // Lower (X & (1 << N)) == 0 to BT(X, N). 8211 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8212 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8213 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8214 Op1.getOpcode() == ISD::Constant && 8215 cast<ConstantSDNode>(Op1)->isNullValue() && 8216 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8217 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8218 if (NewSetCC.getNode()) 8219 return NewSetCC; 8220 } 8221 8222 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8223 // these. 8224 if (Op1.getOpcode() == ISD::Constant && 8225 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8226 cast<ConstantSDNode>(Op1)->isNullValue()) && 8227 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8228 8229 // If the input is a setcc, then reuse the input setcc or use a new one with 8230 // the inverted condition. 8231 if (Op0.getOpcode() == X86ISD::SETCC) { 8232 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8233 bool Invert = (CC == ISD::SETNE) ^ 8234 cast<ConstantSDNode>(Op1)->isNullValue(); 8235 if (!Invert) return Op0; 8236 8237 CCode = X86::GetOppositeBranchCondition(CCode); 8238 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8239 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8240 } 8241 } 8242 8243 bool isFP = Op1.getValueType().isFloatingPoint(); 8244 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8245 if (X86CC == X86::COND_INVALID) 8246 return SDValue(); 8247 8248 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8249 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8250 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8251} 8252 8253// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8254// ones, and then concatenate the result back. 8255static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8256 EVT VT = Op.getValueType(); 8257 8258 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8259 "Unsupported value type for operation"); 8260 8261 int NumElems = VT.getVectorNumElements(); 8262 DebugLoc dl = Op.getDebugLoc(); 8263 SDValue CC = Op.getOperand(2); 8264 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8265 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8266 8267 // Extract the LHS vectors 8268 SDValue LHS = Op.getOperand(0); 8269 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8270 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8271 8272 // Extract the RHS vectors 8273 SDValue RHS = Op.getOperand(1); 8274 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8275 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8276 8277 // Issue the operation on the smaller types and concatenate the result back 8278 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8279 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8280 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8281 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8282 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8283} 8284 8285 8286SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8287 SDValue Cond; 8288 SDValue Op0 = Op.getOperand(0); 8289 SDValue Op1 = Op.getOperand(1); 8290 SDValue CC = Op.getOperand(2); 8291 EVT VT = Op.getValueType(); 8292 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8293 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8294 DebugLoc dl = Op.getDebugLoc(); 8295 8296 if (isFP) { 8297 unsigned SSECC = 8; 8298 EVT EltVT = Op0.getValueType().getVectorElementType(); 8299 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8300 8301 bool Swap = false; 8302 8303 // SSE Condition code mapping: 8304 // 0 - EQ 8305 // 1 - LT 8306 // 2 - LE 8307 // 3 - UNORD 8308 // 4 - NEQ 8309 // 5 - NLT 8310 // 6 - NLE 8311 // 7 - ORD 8312 switch (SetCCOpcode) { 8313 default: break; 8314 case ISD::SETOEQ: 8315 case ISD::SETEQ: SSECC = 0; break; 8316 case ISD::SETOGT: 8317 case ISD::SETGT: Swap = true; // Fallthrough 8318 case ISD::SETLT: 8319 case ISD::SETOLT: SSECC = 1; break; 8320 case ISD::SETOGE: 8321 case ISD::SETGE: Swap = true; // Fallthrough 8322 case ISD::SETLE: 8323 case ISD::SETOLE: SSECC = 2; break; 8324 case ISD::SETUO: SSECC = 3; break; 8325 case ISD::SETUNE: 8326 case ISD::SETNE: SSECC = 4; break; 8327 case ISD::SETULE: Swap = true; 8328 case ISD::SETUGE: SSECC = 5; break; 8329 case ISD::SETULT: Swap = true; 8330 case ISD::SETUGT: SSECC = 6; break; 8331 case ISD::SETO: SSECC = 7; break; 8332 } 8333 if (Swap) 8334 std::swap(Op0, Op1); 8335 8336 // In the two special cases we can't handle, emit two comparisons. 8337 if (SSECC == 8) { 8338 if (SetCCOpcode == ISD::SETUEQ) { 8339 SDValue UNORD, EQ; 8340 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8341 DAG.getConstant(3, MVT::i8)); 8342 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8343 DAG.getConstant(0, MVT::i8)); 8344 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8345 } else if (SetCCOpcode == ISD::SETONE) { 8346 SDValue ORD, NEQ; 8347 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8348 DAG.getConstant(7, MVT::i8)); 8349 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8350 DAG.getConstant(4, MVT::i8)); 8351 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8352 } 8353 llvm_unreachable("Illegal FP comparison"); 8354 } 8355 // Handle all other FP comparisons here. 8356 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8357 DAG.getConstant(SSECC, MVT::i8)); 8358 } 8359 8360 // Break 256-bit integer vector compare into smaller ones. 8361 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8362 return Lower256IntVSETCC(Op, DAG); 8363 8364 // We are handling one of the integer comparisons here. Since SSE only has 8365 // GT and EQ comparisons for integer, swapping operands and multiple 8366 // operations may be required for some comparisons. 8367 unsigned Opc = 0; 8368 bool Swap = false, Invert = false, FlipSigns = false; 8369 8370 switch (SetCCOpcode) { 8371 default: break; 8372 case ISD::SETNE: Invert = true; 8373 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8374 case ISD::SETLT: Swap = true; 8375 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8376 case ISD::SETGE: Swap = true; 8377 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8378 case ISD::SETULT: Swap = true; 8379 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8380 case ISD::SETUGE: Swap = true; 8381 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8382 } 8383 if (Swap) 8384 std::swap(Op0, Op1); 8385 8386 // Check that the operation in question is available (most are plain SSE2, 8387 // but PCMPGTQ and PCMPEQQ have different requirements). 8388 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8389 return SDValue(); 8390 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8391 return SDValue(); 8392 8393 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8394 // bits of the inputs before performing those operations. 8395 if (FlipSigns) { 8396 EVT EltVT = VT.getVectorElementType(); 8397 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8398 EltVT); 8399 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8400 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8401 SignBits.size()); 8402 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8403 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8404 } 8405 8406 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8407 8408 // If the logical-not of the result is required, perform that now. 8409 if (Invert) 8410 Result = DAG.getNOT(dl, Result, VT); 8411 8412 return Result; 8413} 8414 8415// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8416static bool isX86LogicalCmp(SDValue Op) { 8417 unsigned Opc = Op.getNode()->getOpcode(); 8418 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8419 return true; 8420 if (Op.getResNo() == 1 && 8421 (Opc == X86ISD::ADD || 8422 Opc == X86ISD::SUB || 8423 Opc == X86ISD::ADC || 8424 Opc == X86ISD::SBB || 8425 Opc == X86ISD::SMUL || 8426 Opc == X86ISD::UMUL || 8427 Opc == X86ISD::INC || 8428 Opc == X86ISD::DEC || 8429 Opc == X86ISD::OR || 8430 Opc == X86ISD::XOR || 8431 Opc == X86ISD::AND)) 8432 return true; 8433 8434 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8435 return true; 8436 8437 return false; 8438} 8439 8440static bool isZero(SDValue V) { 8441 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8442 return C && C->isNullValue(); 8443} 8444 8445static bool isAllOnes(SDValue V) { 8446 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8447 return C && C->isAllOnesValue(); 8448} 8449 8450SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8451 bool addTest = true; 8452 SDValue Cond = Op.getOperand(0); 8453 SDValue Op1 = Op.getOperand(1); 8454 SDValue Op2 = Op.getOperand(2); 8455 DebugLoc DL = Op.getDebugLoc(); 8456 SDValue CC; 8457 8458 if (Cond.getOpcode() == ISD::SETCC) { 8459 SDValue NewCond = LowerSETCC(Cond, DAG); 8460 if (NewCond.getNode()) 8461 Cond = NewCond; 8462 } 8463 8464 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8465 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8466 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8467 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8468 if (Cond.getOpcode() == X86ISD::SETCC && 8469 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8470 isZero(Cond.getOperand(1).getOperand(1))) { 8471 SDValue Cmp = Cond.getOperand(1); 8472 8473 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8474 8475 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8476 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8477 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8478 8479 SDValue CmpOp0 = Cmp.getOperand(0); 8480 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8481 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8482 8483 SDValue Res = // Res = 0 or -1. 8484 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8485 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8486 8487 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8488 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8489 8490 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8491 if (N2C == 0 || !N2C->isNullValue()) 8492 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8493 return Res; 8494 } 8495 } 8496 8497 // Look past (and (setcc_carry (cmp ...)), 1). 8498 if (Cond.getOpcode() == ISD::AND && 8499 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8501 if (C && C->getAPIntValue() == 1) 8502 Cond = Cond.getOperand(0); 8503 } 8504 8505 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8506 // setting operand in place of the X86ISD::SETCC. 8507 unsigned CondOpcode = Cond.getOpcode(); 8508 if (CondOpcode == X86ISD::SETCC || 8509 CondOpcode == X86ISD::SETCC_CARRY) { 8510 CC = Cond.getOperand(0); 8511 8512 SDValue Cmp = Cond.getOperand(1); 8513 unsigned Opc = Cmp.getOpcode(); 8514 EVT VT = Op.getValueType(); 8515 8516 bool IllegalFPCMov = false; 8517 if (VT.isFloatingPoint() && !VT.isVector() && 8518 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8519 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8520 8521 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8522 Opc == X86ISD::BT) { // FIXME 8523 Cond = Cmp; 8524 addTest = false; 8525 } 8526 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8527 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8528 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8529 Cond.getOperand(0).getValueType() != MVT::i8)) { 8530 SDValue LHS = Cond.getOperand(0); 8531 SDValue RHS = Cond.getOperand(1); 8532 unsigned X86Opcode; 8533 unsigned X86Cond; 8534 SDVTList VTs; 8535 switch (CondOpcode) { 8536 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8537 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8538 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8539 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8540 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8541 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8542 default: llvm_unreachable("unexpected overflowing operator"); 8543 } 8544 if (CondOpcode == ISD::UMULO) 8545 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8546 MVT::i32); 8547 else 8548 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8549 8550 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8551 8552 if (CondOpcode == ISD::UMULO) 8553 Cond = X86Op.getValue(2); 8554 else 8555 Cond = X86Op.getValue(1); 8556 8557 CC = DAG.getConstant(X86Cond, MVT::i8); 8558 addTest = false; 8559 } 8560 8561 if (addTest) { 8562 // Look pass the truncate. 8563 if (Cond.getOpcode() == ISD::TRUNCATE) 8564 Cond = Cond.getOperand(0); 8565 8566 // We know the result of AND is compared against zero. Try to match 8567 // it to BT. 8568 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8569 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8570 if (NewSetCC.getNode()) { 8571 CC = NewSetCC.getOperand(0); 8572 Cond = NewSetCC.getOperand(1); 8573 addTest = false; 8574 } 8575 } 8576 } 8577 8578 if (addTest) { 8579 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8580 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8581 } 8582 8583 // a < b ? -1 : 0 -> RES = ~setcc_carry 8584 // a < b ? 0 : -1 -> RES = setcc_carry 8585 // a >= b ? -1 : 0 -> RES = setcc_carry 8586 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8587 if (Cond.getOpcode() == X86ISD::CMP) { 8588 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8589 8590 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8591 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8592 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8593 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8594 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8595 return DAG.getNOT(DL, Res, Res.getValueType()); 8596 return Res; 8597 } 8598 } 8599 8600 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8601 // condition is true. 8602 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8603 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8604 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8605} 8606 8607// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8608// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8609// from the AND / OR. 8610static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8611 Opc = Op.getOpcode(); 8612 if (Opc != ISD::OR && Opc != ISD::AND) 8613 return false; 8614 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8615 Op.getOperand(0).hasOneUse() && 8616 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8617 Op.getOperand(1).hasOneUse()); 8618} 8619 8620// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8621// 1 and that the SETCC node has a single use. 8622static bool isXor1OfSetCC(SDValue Op) { 8623 if (Op.getOpcode() != ISD::XOR) 8624 return false; 8625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8626 if (N1C && N1C->getAPIntValue() == 1) { 8627 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8628 Op.getOperand(0).hasOneUse(); 8629 } 8630 return false; 8631} 8632 8633SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8634 bool addTest = true; 8635 SDValue Chain = Op.getOperand(0); 8636 SDValue Cond = Op.getOperand(1); 8637 SDValue Dest = Op.getOperand(2); 8638 DebugLoc dl = Op.getDebugLoc(); 8639 SDValue CC; 8640 bool Inverted = false; 8641 8642 if (Cond.getOpcode() == ISD::SETCC) { 8643 // Check for setcc([su]{add,sub,mul}o == 0). 8644 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8645 isa<ConstantSDNode>(Cond.getOperand(1)) && 8646 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8647 Cond.getOperand(0).getResNo() == 1 && 8648 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8649 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8650 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8651 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8652 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8653 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8654 Inverted = true; 8655 Cond = Cond.getOperand(0); 8656 } else { 8657 SDValue NewCond = LowerSETCC(Cond, DAG); 8658 if (NewCond.getNode()) 8659 Cond = NewCond; 8660 } 8661 } 8662#if 0 8663 // FIXME: LowerXALUO doesn't handle these!! 8664 else if (Cond.getOpcode() == X86ISD::ADD || 8665 Cond.getOpcode() == X86ISD::SUB || 8666 Cond.getOpcode() == X86ISD::SMUL || 8667 Cond.getOpcode() == X86ISD::UMUL) 8668 Cond = LowerXALUO(Cond, DAG); 8669#endif 8670 8671 // Look pass (and (setcc_carry (cmp ...)), 1). 8672 if (Cond.getOpcode() == ISD::AND && 8673 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8674 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8675 if (C && C->getAPIntValue() == 1) 8676 Cond = Cond.getOperand(0); 8677 } 8678 8679 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8680 // setting operand in place of the X86ISD::SETCC. 8681 unsigned CondOpcode = Cond.getOpcode(); 8682 if (CondOpcode == X86ISD::SETCC || 8683 CondOpcode == X86ISD::SETCC_CARRY) { 8684 CC = Cond.getOperand(0); 8685 8686 SDValue Cmp = Cond.getOperand(1); 8687 unsigned Opc = Cmp.getOpcode(); 8688 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8689 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8690 Cond = Cmp; 8691 addTest = false; 8692 } else { 8693 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8694 default: break; 8695 case X86::COND_O: 8696 case X86::COND_B: 8697 // These can only come from an arithmetic instruction with overflow, 8698 // e.g. SADDO, UADDO. 8699 Cond = Cond.getNode()->getOperand(1); 8700 addTest = false; 8701 break; 8702 } 8703 } 8704 } 8705 CondOpcode = Cond.getOpcode(); 8706 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8707 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8708 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8709 Cond.getOperand(0).getValueType() != MVT::i8)) { 8710 SDValue LHS = Cond.getOperand(0); 8711 SDValue RHS = Cond.getOperand(1); 8712 unsigned X86Opcode; 8713 unsigned X86Cond; 8714 SDVTList VTs; 8715 switch (CondOpcode) { 8716 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8717 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8718 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8719 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8720 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8721 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8722 default: llvm_unreachable("unexpected overflowing operator"); 8723 } 8724 if (Inverted) 8725 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8726 if (CondOpcode == ISD::UMULO) 8727 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8728 MVT::i32); 8729 else 8730 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8731 8732 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8733 8734 if (CondOpcode == ISD::UMULO) 8735 Cond = X86Op.getValue(2); 8736 else 8737 Cond = X86Op.getValue(1); 8738 8739 CC = DAG.getConstant(X86Cond, MVT::i8); 8740 addTest = false; 8741 } else { 8742 unsigned CondOpc; 8743 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8744 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8745 if (CondOpc == ISD::OR) { 8746 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8747 // two branches instead of an explicit OR instruction with a 8748 // separate test. 8749 if (Cmp == Cond.getOperand(1).getOperand(1) && 8750 isX86LogicalCmp(Cmp)) { 8751 CC = Cond.getOperand(0).getOperand(0); 8752 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8753 Chain, Dest, CC, Cmp); 8754 CC = Cond.getOperand(1).getOperand(0); 8755 Cond = Cmp; 8756 addTest = false; 8757 } 8758 } else { // ISD::AND 8759 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8760 // two branches instead of an explicit AND instruction with a 8761 // separate test. However, we only do this if this block doesn't 8762 // have a fall-through edge, because this requires an explicit 8763 // jmp when the condition is false. 8764 if (Cmp == Cond.getOperand(1).getOperand(1) && 8765 isX86LogicalCmp(Cmp) && 8766 Op.getNode()->hasOneUse()) { 8767 X86::CondCode CCode = 8768 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8769 CCode = X86::GetOppositeBranchCondition(CCode); 8770 CC = DAG.getConstant(CCode, MVT::i8); 8771 SDNode *User = *Op.getNode()->use_begin(); 8772 // Look for an unconditional branch following this conditional branch. 8773 // We need this because we need to reverse the successors in order 8774 // to implement FCMP_OEQ. 8775 if (User->getOpcode() == ISD::BR) { 8776 SDValue FalseBB = User->getOperand(1); 8777 SDNode *NewBR = 8778 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8779 assert(NewBR == User); 8780 (void)NewBR; 8781 Dest = FalseBB; 8782 8783 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8784 Chain, Dest, CC, Cmp); 8785 X86::CondCode CCode = 8786 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8787 CCode = X86::GetOppositeBranchCondition(CCode); 8788 CC = DAG.getConstant(CCode, MVT::i8); 8789 Cond = Cmp; 8790 addTest = false; 8791 } 8792 } 8793 } 8794 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8795 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8796 // It should be transformed during dag combiner except when the condition 8797 // is set by a arithmetics with overflow node. 8798 X86::CondCode CCode = 8799 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8800 CCode = X86::GetOppositeBranchCondition(CCode); 8801 CC = DAG.getConstant(CCode, MVT::i8); 8802 Cond = Cond.getOperand(0).getOperand(1); 8803 addTest = false; 8804 } else if (Cond.getOpcode() == ISD::SETCC && 8805 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8806 // For FCMP_OEQ, we can emit 8807 // two branches instead of an explicit AND instruction with a 8808 // separate test. However, we only do this if this block doesn't 8809 // have a fall-through edge, because this requires an explicit 8810 // jmp when the condition is false. 8811 if (Op.getNode()->hasOneUse()) { 8812 SDNode *User = *Op.getNode()->use_begin(); 8813 // Look for an unconditional branch following this conditional branch. 8814 // We need this because we need to reverse the successors in order 8815 // to implement FCMP_OEQ. 8816 if (User->getOpcode() == ISD::BR) { 8817 SDValue FalseBB = User->getOperand(1); 8818 SDNode *NewBR = 8819 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8820 assert(NewBR == User); 8821 (void)NewBR; 8822 Dest = FalseBB; 8823 8824 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8825 Cond.getOperand(0), Cond.getOperand(1)); 8826 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8827 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8828 Chain, Dest, CC, Cmp); 8829 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8830 Cond = Cmp; 8831 addTest = false; 8832 } 8833 } 8834 } else if (Cond.getOpcode() == ISD::SETCC && 8835 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8836 // For FCMP_UNE, we can emit 8837 // two branches instead of an explicit AND instruction with a 8838 // separate test. However, we only do this if this block doesn't 8839 // have a fall-through edge, because this requires an explicit 8840 // jmp when the condition is false. 8841 if (Op.getNode()->hasOneUse()) { 8842 SDNode *User = *Op.getNode()->use_begin(); 8843 // Look for an unconditional branch following this conditional branch. 8844 // We need this because we need to reverse the successors in order 8845 // to implement FCMP_UNE. 8846 if (User->getOpcode() == ISD::BR) { 8847 SDValue FalseBB = User->getOperand(1); 8848 SDNode *NewBR = 8849 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8850 assert(NewBR == User); 8851 (void)NewBR; 8852 8853 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8854 Cond.getOperand(0), Cond.getOperand(1)); 8855 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8856 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8857 Chain, Dest, CC, Cmp); 8858 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8859 Cond = Cmp; 8860 addTest = false; 8861 Dest = FalseBB; 8862 } 8863 } 8864 } 8865 } 8866 8867 if (addTest) { 8868 // Look pass the truncate. 8869 if (Cond.getOpcode() == ISD::TRUNCATE) 8870 Cond = Cond.getOperand(0); 8871 8872 // We know the result of AND is compared against zero. Try to match 8873 // it to BT. 8874 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8875 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8876 if (NewSetCC.getNode()) { 8877 CC = NewSetCC.getOperand(0); 8878 Cond = NewSetCC.getOperand(1); 8879 addTest = false; 8880 } 8881 } 8882 } 8883 8884 if (addTest) { 8885 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8886 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8887 } 8888 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8889 Chain, Dest, CC, Cond); 8890} 8891 8892 8893// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8894// Calls to _alloca is needed to probe the stack when allocating more than 4k 8895// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8896// that the guard pages used by the OS virtual memory manager are allocated in 8897// correct sequence. 8898SDValue 8899X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8900 SelectionDAG &DAG) const { 8901 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8902 getTargetMachine().Options.EnableSegmentedStacks) && 8903 "This should be used only on Windows targets or when segmented stacks " 8904 "are being used"); 8905 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8906 DebugLoc dl = Op.getDebugLoc(); 8907 8908 // Get the inputs. 8909 SDValue Chain = Op.getOperand(0); 8910 SDValue Size = Op.getOperand(1); 8911 // FIXME: Ensure alignment here 8912 8913 bool Is64Bit = Subtarget->is64Bit(); 8914 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8915 8916 if (getTargetMachine().Options.EnableSegmentedStacks) { 8917 MachineFunction &MF = DAG.getMachineFunction(); 8918 MachineRegisterInfo &MRI = MF.getRegInfo(); 8919 8920 if (Is64Bit) { 8921 // The 64 bit implementation of segmented stacks needs to clobber both r10 8922 // r11. This makes it impossible to use it along with nested parameters. 8923 const Function *F = MF.getFunction(); 8924 8925 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8926 I != E; I++) 8927 if (I->hasNestAttr()) 8928 report_fatal_error("Cannot use segmented stacks with functions that " 8929 "have nested arguments."); 8930 } 8931 8932 const TargetRegisterClass *AddrRegClass = 8933 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8934 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8935 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8936 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8937 DAG.getRegister(Vreg, SPTy)); 8938 SDValue Ops1[2] = { Value, Chain }; 8939 return DAG.getMergeValues(Ops1, 2, dl); 8940 } else { 8941 SDValue Flag; 8942 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8943 8944 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8945 Flag = Chain.getValue(1); 8946 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8947 8948 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8949 Flag = Chain.getValue(1); 8950 8951 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8952 8953 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8954 return DAG.getMergeValues(Ops1, 2, dl); 8955 } 8956} 8957 8958SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8959 MachineFunction &MF = DAG.getMachineFunction(); 8960 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8961 8962 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8963 DebugLoc DL = Op.getDebugLoc(); 8964 8965 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8966 // vastart just stores the address of the VarArgsFrameIndex slot into the 8967 // memory location argument. 8968 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8969 getPointerTy()); 8970 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8971 MachinePointerInfo(SV), false, false, 0); 8972 } 8973 8974 // __va_list_tag: 8975 // gp_offset (0 - 6 * 8) 8976 // fp_offset (48 - 48 + 8 * 16) 8977 // overflow_arg_area (point to parameters coming in memory). 8978 // reg_save_area 8979 SmallVector<SDValue, 8> MemOps; 8980 SDValue FIN = Op.getOperand(1); 8981 // Store gp_offset 8982 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8983 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 8984 MVT::i32), 8985 FIN, MachinePointerInfo(SV), false, false, 0); 8986 MemOps.push_back(Store); 8987 8988 // Store fp_offset 8989 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8990 FIN, DAG.getIntPtrConstant(4)); 8991 Store = DAG.getStore(Op.getOperand(0), DL, 8992 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 8993 MVT::i32), 8994 FIN, MachinePointerInfo(SV, 4), false, false, 0); 8995 MemOps.push_back(Store); 8996 8997 // Store ptr to overflow_arg_area 8998 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8999 FIN, DAG.getIntPtrConstant(4)); 9000 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9001 getPointerTy()); 9002 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9003 MachinePointerInfo(SV, 8), 9004 false, false, 0); 9005 MemOps.push_back(Store); 9006 9007 // Store ptr to reg_save_area. 9008 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9009 FIN, DAG.getIntPtrConstant(8)); 9010 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9011 getPointerTy()); 9012 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9013 MachinePointerInfo(SV, 16), false, false, 0); 9014 MemOps.push_back(Store); 9015 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9016 &MemOps[0], MemOps.size()); 9017} 9018 9019SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9020 assert(Subtarget->is64Bit() && 9021 "LowerVAARG only handles 64-bit va_arg!"); 9022 assert((Subtarget->isTargetLinux() || 9023 Subtarget->isTargetDarwin()) && 9024 "Unhandled target in LowerVAARG"); 9025 assert(Op.getNode()->getNumOperands() == 4); 9026 SDValue Chain = Op.getOperand(0); 9027 SDValue SrcPtr = Op.getOperand(1); 9028 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9029 unsigned Align = Op.getConstantOperandVal(3); 9030 DebugLoc dl = Op.getDebugLoc(); 9031 9032 EVT ArgVT = Op.getNode()->getValueType(0); 9033 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9034 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9035 uint8_t ArgMode; 9036 9037 // Decide which area this value should be read from. 9038 // TODO: Implement the AMD64 ABI in its entirety. This simple 9039 // selection mechanism works only for the basic types. 9040 if (ArgVT == MVT::f80) { 9041 llvm_unreachable("va_arg for f80 not yet implemented"); 9042 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9043 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9044 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9045 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9046 } else { 9047 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9048 } 9049 9050 if (ArgMode == 2) { 9051 // Sanity Check: Make sure using fp_offset makes sense. 9052 assert(!getTargetMachine().Options.UseSoftFloat && 9053 !(DAG.getMachineFunction() 9054 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9055 Subtarget->hasSSE1()); 9056 } 9057 9058 // Insert VAARG_64 node into the DAG 9059 // VAARG_64 returns two values: Variable Argument Address, Chain 9060 SmallVector<SDValue, 11> InstOps; 9061 InstOps.push_back(Chain); 9062 InstOps.push_back(SrcPtr); 9063 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9064 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9065 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9066 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9067 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9068 VTs, &InstOps[0], InstOps.size(), 9069 MVT::i64, 9070 MachinePointerInfo(SV), 9071 /*Align=*/0, 9072 /*Volatile=*/false, 9073 /*ReadMem=*/true, 9074 /*WriteMem=*/true); 9075 Chain = VAARG.getValue(1); 9076 9077 // Load the next argument and return it 9078 return DAG.getLoad(ArgVT, dl, 9079 Chain, 9080 VAARG, 9081 MachinePointerInfo(), 9082 false, false, false, 0); 9083} 9084 9085SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9086 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9087 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9088 SDValue Chain = Op.getOperand(0); 9089 SDValue DstPtr = Op.getOperand(1); 9090 SDValue SrcPtr = Op.getOperand(2); 9091 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9092 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9093 DebugLoc DL = Op.getDebugLoc(); 9094 9095 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9096 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9097 false, 9098 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9099} 9100 9101// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9102// may or may not be a constant. Takes immediate version of shift as input. 9103static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9104 SDValue SrcOp, SDValue ShAmt, 9105 SelectionDAG &DAG) { 9106 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9107 9108 if (isa<ConstantSDNode>(ShAmt)) { 9109 switch (Opc) { 9110 default: llvm_unreachable("Unknown target vector shift node"); 9111 case X86ISD::VSHLI: 9112 case X86ISD::VSRLI: 9113 case X86ISD::VSRAI: 9114 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9115 } 9116 } 9117 9118 // Change opcode to non-immediate version 9119 switch (Opc) { 9120 default: llvm_unreachable("Unknown target vector shift node"); 9121 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9122 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9123 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9124 } 9125 9126 // Need to build a vector containing shift amount 9127 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9128 SDValue ShOps[4]; 9129 ShOps[0] = ShAmt; 9130 ShOps[1] = DAG.getConstant(0, MVT::i32); 9131 ShOps[2] = DAG.getUNDEF(MVT::i32); 9132 ShOps[3] = DAG.getUNDEF(MVT::i32); 9133 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9134 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9135 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9136} 9137 9138SDValue 9139X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9140 DebugLoc dl = Op.getDebugLoc(); 9141 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9142 switch (IntNo) { 9143 default: return SDValue(); // Don't custom lower most intrinsics. 9144 // Comparison intrinsics. 9145 case Intrinsic::x86_sse_comieq_ss: 9146 case Intrinsic::x86_sse_comilt_ss: 9147 case Intrinsic::x86_sse_comile_ss: 9148 case Intrinsic::x86_sse_comigt_ss: 9149 case Intrinsic::x86_sse_comige_ss: 9150 case Intrinsic::x86_sse_comineq_ss: 9151 case Intrinsic::x86_sse_ucomieq_ss: 9152 case Intrinsic::x86_sse_ucomilt_ss: 9153 case Intrinsic::x86_sse_ucomile_ss: 9154 case Intrinsic::x86_sse_ucomigt_ss: 9155 case Intrinsic::x86_sse_ucomige_ss: 9156 case Intrinsic::x86_sse_ucomineq_ss: 9157 case Intrinsic::x86_sse2_comieq_sd: 9158 case Intrinsic::x86_sse2_comilt_sd: 9159 case Intrinsic::x86_sse2_comile_sd: 9160 case Intrinsic::x86_sse2_comigt_sd: 9161 case Intrinsic::x86_sse2_comige_sd: 9162 case Intrinsic::x86_sse2_comineq_sd: 9163 case Intrinsic::x86_sse2_ucomieq_sd: 9164 case Intrinsic::x86_sse2_ucomilt_sd: 9165 case Intrinsic::x86_sse2_ucomile_sd: 9166 case Intrinsic::x86_sse2_ucomigt_sd: 9167 case Intrinsic::x86_sse2_ucomige_sd: 9168 case Intrinsic::x86_sse2_ucomineq_sd: { 9169 unsigned Opc = 0; 9170 ISD::CondCode CC = ISD::SETCC_INVALID; 9171 switch (IntNo) { 9172 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9173 case Intrinsic::x86_sse_comieq_ss: 9174 case Intrinsic::x86_sse2_comieq_sd: 9175 Opc = X86ISD::COMI; 9176 CC = ISD::SETEQ; 9177 break; 9178 case Intrinsic::x86_sse_comilt_ss: 9179 case Intrinsic::x86_sse2_comilt_sd: 9180 Opc = X86ISD::COMI; 9181 CC = ISD::SETLT; 9182 break; 9183 case Intrinsic::x86_sse_comile_ss: 9184 case Intrinsic::x86_sse2_comile_sd: 9185 Opc = X86ISD::COMI; 9186 CC = ISD::SETLE; 9187 break; 9188 case Intrinsic::x86_sse_comigt_ss: 9189 case Intrinsic::x86_sse2_comigt_sd: 9190 Opc = X86ISD::COMI; 9191 CC = ISD::SETGT; 9192 break; 9193 case Intrinsic::x86_sse_comige_ss: 9194 case Intrinsic::x86_sse2_comige_sd: 9195 Opc = X86ISD::COMI; 9196 CC = ISD::SETGE; 9197 break; 9198 case Intrinsic::x86_sse_comineq_ss: 9199 case Intrinsic::x86_sse2_comineq_sd: 9200 Opc = X86ISD::COMI; 9201 CC = ISD::SETNE; 9202 break; 9203 case Intrinsic::x86_sse_ucomieq_ss: 9204 case Intrinsic::x86_sse2_ucomieq_sd: 9205 Opc = X86ISD::UCOMI; 9206 CC = ISD::SETEQ; 9207 break; 9208 case Intrinsic::x86_sse_ucomilt_ss: 9209 case Intrinsic::x86_sse2_ucomilt_sd: 9210 Opc = X86ISD::UCOMI; 9211 CC = ISD::SETLT; 9212 break; 9213 case Intrinsic::x86_sse_ucomile_ss: 9214 case Intrinsic::x86_sse2_ucomile_sd: 9215 Opc = X86ISD::UCOMI; 9216 CC = ISD::SETLE; 9217 break; 9218 case Intrinsic::x86_sse_ucomigt_ss: 9219 case Intrinsic::x86_sse2_ucomigt_sd: 9220 Opc = X86ISD::UCOMI; 9221 CC = ISD::SETGT; 9222 break; 9223 case Intrinsic::x86_sse_ucomige_ss: 9224 case Intrinsic::x86_sse2_ucomige_sd: 9225 Opc = X86ISD::UCOMI; 9226 CC = ISD::SETGE; 9227 break; 9228 case Intrinsic::x86_sse_ucomineq_ss: 9229 case Intrinsic::x86_sse2_ucomineq_sd: 9230 Opc = X86ISD::UCOMI; 9231 CC = ISD::SETNE; 9232 break; 9233 } 9234 9235 SDValue LHS = Op.getOperand(1); 9236 SDValue RHS = Op.getOperand(2); 9237 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9238 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9239 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9240 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9241 DAG.getConstant(X86CC, MVT::i8), Cond); 9242 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9243 } 9244 // XOP comparison intrinsics 9245 case Intrinsic::x86_xop_vpcomltb: 9246 case Intrinsic::x86_xop_vpcomltw: 9247 case Intrinsic::x86_xop_vpcomltd: 9248 case Intrinsic::x86_xop_vpcomltq: 9249 case Intrinsic::x86_xop_vpcomltub: 9250 case Intrinsic::x86_xop_vpcomltuw: 9251 case Intrinsic::x86_xop_vpcomltud: 9252 case Intrinsic::x86_xop_vpcomltuq: 9253 case Intrinsic::x86_xop_vpcomleb: 9254 case Intrinsic::x86_xop_vpcomlew: 9255 case Intrinsic::x86_xop_vpcomled: 9256 case Intrinsic::x86_xop_vpcomleq: 9257 case Intrinsic::x86_xop_vpcomleub: 9258 case Intrinsic::x86_xop_vpcomleuw: 9259 case Intrinsic::x86_xop_vpcomleud: 9260 case Intrinsic::x86_xop_vpcomleuq: 9261 case Intrinsic::x86_xop_vpcomgtb: 9262 case Intrinsic::x86_xop_vpcomgtw: 9263 case Intrinsic::x86_xop_vpcomgtd: 9264 case Intrinsic::x86_xop_vpcomgtq: 9265 case Intrinsic::x86_xop_vpcomgtub: 9266 case Intrinsic::x86_xop_vpcomgtuw: 9267 case Intrinsic::x86_xop_vpcomgtud: 9268 case Intrinsic::x86_xop_vpcomgtuq: 9269 case Intrinsic::x86_xop_vpcomgeb: 9270 case Intrinsic::x86_xop_vpcomgew: 9271 case Intrinsic::x86_xop_vpcomged: 9272 case Intrinsic::x86_xop_vpcomgeq: 9273 case Intrinsic::x86_xop_vpcomgeub: 9274 case Intrinsic::x86_xop_vpcomgeuw: 9275 case Intrinsic::x86_xop_vpcomgeud: 9276 case Intrinsic::x86_xop_vpcomgeuq: 9277 case Intrinsic::x86_xop_vpcomeqb: 9278 case Intrinsic::x86_xop_vpcomeqw: 9279 case Intrinsic::x86_xop_vpcomeqd: 9280 case Intrinsic::x86_xop_vpcomeqq: 9281 case Intrinsic::x86_xop_vpcomequb: 9282 case Intrinsic::x86_xop_vpcomequw: 9283 case Intrinsic::x86_xop_vpcomequd: 9284 case Intrinsic::x86_xop_vpcomequq: 9285 case Intrinsic::x86_xop_vpcomneb: 9286 case Intrinsic::x86_xop_vpcomnew: 9287 case Intrinsic::x86_xop_vpcomned: 9288 case Intrinsic::x86_xop_vpcomneq: 9289 case Intrinsic::x86_xop_vpcomneub: 9290 case Intrinsic::x86_xop_vpcomneuw: 9291 case Intrinsic::x86_xop_vpcomneud: 9292 case Intrinsic::x86_xop_vpcomneuq: 9293 case Intrinsic::x86_xop_vpcomfalseb: 9294 case Intrinsic::x86_xop_vpcomfalsew: 9295 case Intrinsic::x86_xop_vpcomfalsed: 9296 case Intrinsic::x86_xop_vpcomfalseq: 9297 case Intrinsic::x86_xop_vpcomfalseub: 9298 case Intrinsic::x86_xop_vpcomfalseuw: 9299 case Intrinsic::x86_xop_vpcomfalseud: 9300 case Intrinsic::x86_xop_vpcomfalseuq: 9301 case Intrinsic::x86_xop_vpcomtrueb: 9302 case Intrinsic::x86_xop_vpcomtruew: 9303 case Intrinsic::x86_xop_vpcomtrued: 9304 case Intrinsic::x86_xop_vpcomtrueq: 9305 case Intrinsic::x86_xop_vpcomtrueub: 9306 case Intrinsic::x86_xop_vpcomtrueuw: 9307 case Intrinsic::x86_xop_vpcomtrueud: 9308 case Intrinsic::x86_xop_vpcomtrueuq: { 9309 unsigned CC = 0; 9310 unsigned Opc = 0; 9311 9312 switch (IntNo) { 9313 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9314 case Intrinsic::x86_xop_vpcomltb: 9315 case Intrinsic::x86_xop_vpcomltw: 9316 case Intrinsic::x86_xop_vpcomltd: 9317 case Intrinsic::x86_xop_vpcomltq: 9318 CC = 0; 9319 Opc = X86ISD::VPCOM; 9320 break; 9321 case Intrinsic::x86_xop_vpcomltub: 9322 case Intrinsic::x86_xop_vpcomltuw: 9323 case Intrinsic::x86_xop_vpcomltud: 9324 case Intrinsic::x86_xop_vpcomltuq: 9325 CC = 0; 9326 Opc = X86ISD::VPCOMU; 9327 break; 9328 case Intrinsic::x86_xop_vpcomleb: 9329 case Intrinsic::x86_xop_vpcomlew: 9330 case Intrinsic::x86_xop_vpcomled: 9331 case Intrinsic::x86_xop_vpcomleq: 9332 CC = 1; 9333 Opc = X86ISD::VPCOM; 9334 break; 9335 case Intrinsic::x86_xop_vpcomleub: 9336 case Intrinsic::x86_xop_vpcomleuw: 9337 case Intrinsic::x86_xop_vpcomleud: 9338 case Intrinsic::x86_xop_vpcomleuq: 9339 CC = 1; 9340 Opc = X86ISD::VPCOMU; 9341 break; 9342 case Intrinsic::x86_xop_vpcomgtb: 9343 case Intrinsic::x86_xop_vpcomgtw: 9344 case Intrinsic::x86_xop_vpcomgtd: 9345 case Intrinsic::x86_xop_vpcomgtq: 9346 CC = 2; 9347 Opc = X86ISD::VPCOM; 9348 break; 9349 case Intrinsic::x86_xop_vpcomgtub: 9350 case Intrinsic::x86_xop_vpcomgtuw: 9351 case Intrinsic::x86_xop_vpcomgtud: 9352 case Intrinsic::x86_xop_vpcomgtuq: 9353 CC = 2; 9354 Opc = X86ISD::VPCOMU; 9355 break; 9356 case Intrinsic::x86_xop_vpcomgeb: 9357 case Intrinsic::x86_xop_vpcomgew: 9358 case Intrinsic::x86_xop_vpcomged: 9359 case Intrinsic::x86_xop_vpcomgeq: 9360 CC = 3; 9361 Opc = X86ISD::VPCOM; 9362 break; 9363 case Intrinsic::x86_xop_vpcomgeub: 9364 case Intrinsic::x86_xop_vpcomgeuw: 9365 case Intrinsic::x86_xop_vpcomgeud: 9366 case Intrinsic::x86_xop_vpcomgeuq: 9367 CC = 3; 9368 Opc = X86ISD::VPCOMU; 9369 break; 9370 case Intrinsic::x86_xop_vpcomeqb: 9371 case Intrinsic::x86_xop_vpcomeqw: 9372 case Intrinsic::x86_xop_vpcomeqd: 9373 case Intrinsic::x86_xop_vpcomeqq: 9374 CC = 4; 9375 Opc = X86ISD::VPCOM; 9376 break; 9377 case Intrinsic::x86_xop_vpcomequb: 9378 case Intrinsic::x86_xop_vpcomequw: 9379 case Intrinsic::x86_xop_vpcomequd: 9380 case Intrinsic::x86_xop_vpcomequq: 9381 CC = 4; 9382 Opc = X86ISD::VPCOMU; 9383 break; 9384 case Intrinsic::x86_xop_vpcomneb: 9385 case Intrinsic::x86_xop_vpcomnew: 9386 case Intrinsic::x86_xop_vpcomned: 9387 case Intrinsic::x86_xop_vpcomneq: 9388 CC = 5; 9389 Opc = X86ISD::VPCOM; 9390 break; 9391 case Intrinsic::x86_xop_vpcomneub: 9392 case Intrinsic::x86_xop_vpcomneuw: 9393 case Intrinsic::x86_xop_vpcomneud: 9394 case Intrinsic::x86_xop_vpcomneuq: 9395 CC = 5; 9396 Opc = X86ISD::VPCOMU; 9397 break; 9398 case Intrinsic::x86_xop_vpcomfalseb: 9399 case Intrinsic::x86_xop_vpcomfalsew: 9400 case Intrinsic::x86_xop_vpcomfalsed: 9401 case Intrinsic::x86_xop_vpcomfalseq: 9402 CC = 6; 9403 Opc = X86ISD::VPCOM; 9404 break; 9405 case Intrinsic::x86_xop_vpcomfalseub: 9406 case Intrinsic::x86_xop_vpcomfalseuw: 9407 case Intrinsic::x86_xop_vpcomfalseud: 9408 case Intrinsic::x86_xop_vpcomfalseuq: 9409 CC = 6; 9410 Opc = X86ISD::VPCOMU; 9411 break; 9412 case Intrinsic::x86_xop_vpcomtrueb: 9413 case Intrinsic::x86_xop_vpcomtruew: 9414 case Intrinsic::x86_xop_vpcomtrued: 9415 case Intrinsic::x86_xop_vpcomtrueq: 9416 CC = 7; 9417 Opc = X86ISD::VPCOM; 9418 break; 9419 case Intrinsic::x86_xop_vpcomtrueub: 9420 case Intrinsic::x86_xop_vpcomtrueuw: 9421 case Intrinsic::x86_xop_vpcomtrueud: 9422 case Intrinsic::x86_xop_vpcomtrueuq: 9423 CC = 7; 9424 Opc = X86ISD::VPCOMU; 9425 break; 9426 } 9427 9428 SDValue LHS = Op.getOperand(1); 9429 SDValue RHS = Op.getOperand(2); 9430 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9431 DAG.getConstant(CC, MVT::i8)); 9432 } 9433 9434 // Arithmetic intrinsics. 9435 case Intrinsic::x86_sse2_pmulu_dq: 9436 case Intrinsic::x86_avx2_pmulu_dq: 9437 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9438 Op.getOperand(1), Op.getOperand(2)); 9439 case Intrinsic::x86_sse3_hadd_ps: 9440 case Intrinsic::x86_sse3_hadd_pd: 9441 case Intrinsic::x86_avx_hadd_ps_256: 9442 case Intrinsic::x86_avx_hadd_pd_256: 9443 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9444 Op.getOperand(1), Op.getOperand(2)); 9445 case Intrinsic::x86_sse3_hsub_ps: 9446 case Intrinsic::x86_sse3_hsub_pd: 9447 case Intrinsic::x86_avx_hsub_ps_256: 9448 case Intrinsic::x86_avx_hsub_pd_256: 9449 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9450 Op.getOperand(1), Op.getOperand(2)); 9451 case Intrinsic::x86_ssse3_phadd_w_128: 9452 case Intrinsic::x86_ssse3_phadd_d_128: 9453 case Intrinsic::x86_avx2_phadd_w: 9454 case Intrinsic::x86_avx2_phadd_d: 9455 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9456 Op.getOperand(1), Op.getOperand(2)); 9457 case Intrinsic::x86_ssse3_phsub_w_128: 9458 case Intrinsic::x86_ssse3_phsub_d_128: 9459 case Intrinsic::x86_avx2_phsub_w: 9460 case Intrinsic::x86_avx2_phsub_d: 9461 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9462 Op.getOperand(1), Op.getOperand(2)); 9463 case Intrinsic::x86_avx2_psllv_d: 9464 case Intrinsic::x86_avx2_psllv_q: 9465 case Intrinsic::x86_avx2_psllv_d_256: 9466 case Intrinsic::x86_avx2_psllv_q_256: 9467 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9468 Op.getOperand(1), Op.getOperand(2)); 9469 case Intrinsic::x86_avx2_psrlv_d: 9470 case Intrinsic::x86_avx2_psrlv_q: 9471 case Intrinsic::x86_avx2_psrlv_d_256: 9472 case Intrinsic::x86_avx2_psrlv_q_256: 9473 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9474 Op.getOperand(1), Op.getOperand(2)); 9475 case Intrinsic::x86_avx2_psrav_d: 9476 case Intrinsic::x86_avx2_psrav_d_256: 9477 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9478 Op.getOperand(1), Op.getOperand(2)); 9479 case Intrinsic::x86_ssse3_pshuf_b_128: 9480 case Intrinsic::x86_avx2_pshuf_b: 9481 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9482 Op.getOperand(1), Op.getOperand(2)); 9483 case Intrinsic::x86_ssse3_psign_b_128: 9484 case Intrinsic::x86_ssse3_psign_w_128: 9485 case Intrinsic::x86_ssse3_psign_d_128: 9486 case Intrinsic::x86_avx2_psign_b: 9487 case Intrinsic::x86_avx2_psign_w: 9488 case Intrinsic::x86_avx2_psign_d: 9489 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9490 Op.getOperand(1), Op.getOperand(2)); 9491 case Intrinsic::x86_sse41_insertps: 9492 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9493 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9494 case Intrinsic::x86_avx_vperm2f128_ps_256: 9495 case Intrinsic::x86_avx_vperm2f128_pd_256: 9496 case Intrinsic::x86_avx_vperm2f128_si_256: 9497 case Intrinsic::x86_avx2_vperm2i128: 9498 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9499 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9500 case Intrinsic::x86_avx_vpermil_ps: 9501 case Intrinsic::x86_avx_vpermil_pd: 9502 case Intrinsic::x86_avx_vpermil_ps_256: 9503 case Intrinsic::x86_avx_vpermil_pd_256: 9504 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(), 9505 Op.getOperand(1), Op.getOperand(2)); 9506 9507 // ptest and testp intrinsics. The intrinsic these come from are designed to 9508 // return an integer value, not just an instruction so lower it to the ptest 9509 // or testp pattern and a setcc for the result. 9510 case Intrinsic::x86_sse41_ptestz: 9511 case Intrinsic::x86_sse41_ptestc: 9512 case Intrinsic::x86_sse41_ptestnzc: 9513 case Intrinsic::x86_avx_ptestz_256: 9514 case Intrinsic::x86_avx_ptestc_256: 9515 case Intrinsic::x86_avx_ptestnzc_256: 9516 case Intrinsic::x86_avx_vtestz_ps: 9517 case Intrinsic::x86_avx_vtestc_ps: 9518 case Intrinsic::x86_avx_vtestnzc_ps: 9519 case Intrinsic::x86_avx_vtestz_pd: 9520 case Intrinsic::x86_avx_vtestc_pd: 9521 case Intrinsic::x86_avx_vtestnzc_pd: 9522 case Intrinsic::x86_avx_vtestz_ps_256: 9523 case Intrinsic::x86_avx_vtestc_ps_256: 9524 case Intrinsic::x86_avx_vtestnzc_ps_256: 9525 case Intrinsic::x86_avx_vtestz_pd_256: 9526 case Intrinsic::x86_avx_vtestc_pd_256: 9527 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9528 bool IsTestPacked = false; 9529 unsigned X86CC = 0; 9530 switch (IntNo) { 9531 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9532 case Intrinsic::x86_avx_vtestz_ps: 9533 case Intrinsic::x86_avx_vtestz_pd: 9534 case Intrinsic::x86_avx_vtestz_ps_256: 9535 case Intrinsic::x86_avx_vtestz_pd_256: 9536 IsTestPacked = true; // Fallthrough 9537 case Intrinsic::x86_sse41_ptestz: 9538 case Intrinsic::x86_avx_ptestz_256: 9539 // ZF = 1 9540 X86CC = X86::COND_E; 9541 break; 9542 case Intrinsic::x86_avx_vtestc_ps: 9543 case Intrinsic::x86_avx_vtestc_pd: 9544 case Intrinsic::x86_avx_vtestc_ps_256: 9545 case Intrinsic::x86_avx_vtestc_pd_256: 9546 IsTestPacked = true; // Fallthrough 9547 case Intrinsic::x86_sse41_ptestc: 9548 case Intrinsic::x86_avx_ptestc_256: 9549 // CF = 1 9550 X86CC = X86::COND_B; 9551 break; 9552 case Intrinsic::x86_avx_vtestnzc_ps: 9553 case Intrinsic::x86_avx_vtestnzc_pd: 9554 case Intrinsic::x86_avx_vtestnzc_ps_256: 9555 case Intrinsic::x86_avx_vtestnzc_pd_256: 9556 IsTestPacked = true; // Fallthrough 9557 case Intrinsic::x86_sse41_ptestnzc: 9558 case Intrinsic::x86_avx_ptestnzc_256: 9559 // ZF and CF = 0 9560 X86CC = X86::COND_A; 9561 break; 9562 } 9563 9564 SDValue LHS = Op.getOperand(1); 9565 SDValue RHS = Op.getOperand(2); 9566 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9567 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9568 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9569 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9570 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9571 } 9572 9573 // SSE/AVX shift intrinsics 9574 case Intrinsic::x86_sse2_psll_w: 9575 case Intrinsic::x86_sse2_psll_d: 9576 case Intrinsic::x86_sse2_psll_q: 9577 case Intrinsic::x86_avx2_psll_w: 9578 case Intrinsic::x86_avx2_psll_d: 9579 case Intrinsic::x86_avx2_psll_q: 9580 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9581 Op.getOperand(1), Op.getOperand(2)); 9582 case Intrinsic::x86_sse2_psrl_w: 9583 case Intrinsic::x86_sse2_psrl_d: 9584 case Intrinsic::x86_sse2_psrl_q: 9585 case Intrinsic::x86_avx2_psrl_w: 9586 case Intrinsic::x86_avx2_psrl_d: 9587 case Intrinsic::x86_avx2_psrl_q: 9588 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9589 Op.getOperand(1), Op.getOperand(2)); 9590 case Intrinsic::x86_sse2_psra_w: 9591 case Intrinsic::x86_sse2_psra_d: 9592 case Intrinsic::x86_avx2_psra_w: 9593 case Intrinsic::x86_avx2_psra_d: 9594 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9595 Op.getOperand(1), Op.getOperand(2)); 9596 case Intrinsic::x86_sse2_pslli_w: 9597 case Intrinsic::x86_sse2_pslli_d: 9598 case Intrinsic::x86_sse2_pslli_q: 9599 case Intrinsic::x86_avx2_pslli_w: 9600 case Intrinsic::x86_avx2_pslli_d: 9601 case Intrinsic::x86_avx2_pslli_q: 9602 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9603 Op.getOperand(1), Op.getOperand(2), DAG); 9604 case Intrinsic::x86_sse2_psrli_w: 9605 case Intrinsic::x86_sse2_psrli_d: 9606 case Intrinsic::x86_sse2_psrli_q: 9607 case Intrinsic::x86_avx2_psrli_w: 9608 case Intrinsic::x86_avx2_psrli_d: 9609 case Intrinsic::x86_avx2_psrli_q: 9610 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9611 Op.getOperand(1), Op.getOperand(2), DAG); 9612 case Intrinsic::x86_sse2_psrai_w: 9613 case Intrinsic::x86_sse2_psrai_d: 9614 case Intrinsic::x86_avx2_psrai_w: 9615 case Intrinsic::x86_avx2_psrai_d: 9616 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9617 Op.getOperand(1), Op.getOperand(2), DAG); 9618 // Fix vector shift instructions where the last operand is a non-immediate 9619 // i32 value. 9620 case Intrinsic::x86_mmx_pslli_w: 9621 case Intrinsic::x86_mmx_pslli_d: 9622 case Intrinsic::x86_mmx_pslli_q: 9623 case Intrinsic::x86_mmx_psrli_w: 9624 case Intrinsic::x86_mmx_psrli_d: 9625 case Intrinsic::x86_mmx_psrli_q: 9626 case Intrinsic::x86_mmx_psrai_w: 9627 case Intrinsic::x86_mmx_psrai_d: { 9628 SDValue ShAmt = Op.getOperand(2); 9629 if (isa<ConstantSDNode>(ShAmt)) 9630 return SDValue(); 9631 9632 unsigned NewIntNo = 0; 9633 switch (IntNo) { 9634 case Intrinsic::x86_mmx_pslli_w: 9635 NewIntNo = Intrinsic::x86_mmx_psll_w; 9636 break; 9637 case Intrinsic::x86_mmx_pslli_d: 9638 NewIntNo = Intrinsic::x86_mmx_psll_d; 9639 break; 9640 case Intrinsic::x86_mmx_pslli_q: 9641 NewIntNo = Intrinsic::x86_mmx_psll_q; 9642 break; 9643 case Intrinsic::x86_mmx_psrli_w: 9644 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9645 break; 9646 case Intrinsic::x86_mmx_psrli_d: 9647 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9648 break; 9649 case Intrinsic::x86_mmx_psrli_q: 9650 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9651 break; 9652 case Intrinsic::x86_mmx_psrai_w: 9653 NewIntNo = Intrinsic::x86_mmx_psra_w; 9654 break; 9655 case Intrinsic::x86_mmx_psrai_d: 9656 NewIntNo = Intrinsic::x86_mmx_psra_d; 9657 break; 9658 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9659 } 9660 9661 // The vector shift intrinsics with scalars uses 32b shift amounts but 9662 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9663 // to be zero. 9664 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9665 DAG.getConstant(0, MVT::i32)); 9666// FIXME this must be lowered to get rid of the invalid type. 9667 9668 EVT VT = Op.getValueType(); 9669 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9670 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9671 DAG.getConstant(NewIntNo, MVT::i32), 9672 Op.getOperand(1), ShAmt); 9673 } 9674 } 9675} 9676 9677SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9678 SelectionDAG &DAG) const { 9679 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9680 MFI->setReturnAddressIsTaken(true); 9681 9682 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9683 DebugLoc dl = Op.getDebugLoc(); 9684 9685 if (Depth > 0) { 9686 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9687 SDValue Offset = 9688 DAG.getConstant(TD->getPointerSize(), 9689 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9690 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9691 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9692 FrameAddr, Offset), 9693 MachinePointerInfo(), false, false, false, 0); 9694 } 9695 9696 // Just load the return address. 9697 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9698 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9699 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9700} 9701 9702SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9703 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9704 MFI->setFrameAddressIsTaken(true); 9705 9706 EVT VT = Op.getValueType(); 9707 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9708 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9709 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9710 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9711 while (Depth--) 9712 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9713 MachinePointerInfo(), 9714 false, false, false, 0); 9715 return FrameAddr; 9716} 9717 9718SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9719 SelectionDAG &DAG) const { 9720 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9721} 9722 9723SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9724 MachineFunction &MF = DAG.getMachineFunction(); 9725 SDValue Chain = Op.getOperand(0); 9726 SDValue Offset = Op.getOperand(1); 9727 SDValue Handler = Op.getOperand(2); 9728 DebugLoc dl = Op.getDebugLoc(); 9729 9730 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9731 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9732 getPointerTy()); 9733 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9734 9735 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9736 DAG.getIntPtrConstant(TD->getPointerSize())); 9737 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9738 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9739 false, false, 0); 9740 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9741 MF.getRegInfo().addLiveOut(StoreAddrReg); 9742 9743 return DAG.getNode(X86ISD::EH_RETURN, dl, 9744 MVT::Other, 9745 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9746} 9747 9748SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9749 SelectionDAG &DAG) const { 9750 return Op.getOperand(0); 9751} 9752 9753SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9754 SelectionDAG &DAG) const { 9755 SDValue Root = Op.getOperand(0); 9756 SDValue Trmp = Op.getOperand(1); // trampoline 9757 SDValue FPtr = Op.getOperand(2); // nested function 9758 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9759 DebugLoc dl = Op.getDebugLoc(); 9760 9761 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9762 9763 if (Subtarget->is64Bit()) { 9764 SDValue OutChains[6]; 9765 9766 // Large code-model. 9767 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9768 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9769 9770 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9771 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9772 9773 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9774 9775 // Load the pointer to the nested function into R11. 9776 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9777 SDValue Addr = Trmp; 9778 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9779 Addr, MachinePointerInfo(TrmpAddr), 9780 false, false, 0); 9781 9782 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9783 DAG.getConstant(2, MVT::i64)); 9784 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9785 MachinePointerInfo(TrmpAddr, 2), 9786 false, false, 2); 9787 9788 // Load the 'nest' parameter value into R10. 9789 // R10 is specified in X86CallingConv.td 9790 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9792 DAG.getConstant(10, MVT::i64)); 9793 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9794 Addr, MachinePointerInfo(TrmpAddr, 10), 9795 false, false, 0); 9796 9797 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9798 DAG.getConstant(12, MVT::i64)); 9799 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9800 MachinePointerInfo(TrmpAddr, 12), 9801 false, false, 2); 9802 9803 // Jump to the nested function. 9804 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9805 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9806 DAG.getConstant(20, MVT::i64)); 9807 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9808 Addr, MachinePointerInfo(TrmpAddr, 20), 9809 false, false, 0); 9810 9811 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9812 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9813 DAG.getConstant(22, MVT::i64)); 9814 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9815 MachinePointerInfo(TrmpAddr, 22), 9816 false, false, 0); 9817 9818 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9819 } else { 9820 const Function *Func = 9821 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9822 CallingConv::ID CC = Func->getCallingConv(); 9823 unsigned NestReg; 9824 9825 switch (CC) { 9826 default: 9827 llvm_unreachable("Unsupported calling convention"); 9828 case CallingConv::C: 9829 case CallingConv::X86_StdCall: { 9830 // Pass 'nest' parameter in ECX. 9831 // Must be kept in sync with X86CallingConv.td 9832 NestReg = X86::ECX; 9833 9834 // Check that ECX wasn't needed by an 'inreg' parameter. 9835 FunctionType *FTy = Func->getFunctionType(); 9836 const AttrListPtr &Attrs = Func->getAttributes(); 9837 9838 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9839 unsigned InRegCount = 0; 9840 unsigned Idx = 1; 9841 9842 for (FunctionType::param_iterator I = FTy->param_begin(), 9843 E = FTy->param_end(); I != E; ++I, ++Idx) 9844 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9845 // FIXME: should only count parameters that are lowered to integers. 9846 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9847 9848 if (InRegCount > 2) { 9849 report_fatal_error("Nest register in use - reduce number of inreg" 9850 " parameters!"); 9851 } 9852 } 9853 break; 9854 } 9855 case CallingConv::X86_FastCall: 9856 case CallingConv::X86_ThisCall: 9857 case CallingConv::Fast: 9858 // Pass 'nest' parameter in EAX. 9859 // Must be kept in sync with X86CallingConv.td 9860 NestReg = X86::EAX; 9861 break; 9862 } 9863 9864 SDValue OutChains[4]; 9865 SDValue Addr, Disp; 9866 9867 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9868 DAG.getConstant(10, MVT::i32)); 9869 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9870 9871 // This is storing the opcode for MOV32ri. 9872 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9873 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9874 OutChains[0] = DAG.getStore(Root, dl, 9875 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9876 Trmp, MachinePointerInfo(TrmpAddr), 9877 false, false, 0); 9878 9879 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9880 DAG.getConstant(1, MVT::i32)); 9881 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9882 MachinePointerInfo(TrmpAddr, 1), 9883 false, false, 1); 9884 9885 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9886 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9887 DAG.getConstant(5, MVT::i32)); 9888 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9889 MachinePointerInfo(TrmpAddr, 5), 9890 false, false, 1); 9891 9892 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9893 DAG.getConstant(6, MVT::i32)); 9894 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9895 MachinePointerInfo(TrmpAddr, 6), 9896 false, false, 1); 9897 9898 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9899 } 9900} 9901 9902SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9903 SelectionDAG &DAG) const { 9904 /* 9905 The rounding mode is in bits 11:10 of FPSR, and has the following 9906 settings: 9907 00 Round to nearest 9908 01 Round to -inf 9909 10 Round to +inf 9910 11 Round to 0 9911 9912 FLT_ROUNDS, on the other hand, expects the following: 9913 -1 Undefined 9914 0 Round to 0 9915 1 Round to nearest 9916 2 Round to +inf 9917 3 Round to -inf 9918 9919 To perform the conversion, we do: 9920 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9921 */ 9922 9923 MachineFunction &MF = DAG.getMachineFunction(); 9924 const TargetMachine &TM = MF.getTarget(); 9925 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9926 unsigned StackAlignment = TFI.getStackAlignment(); 9927 EVT VT = Op.getValueType(); 9928 DebugLoc DL = Op.getDebugLoc(); 9929 9930 // Save FP Control Word to stack slot 9931 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9932 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9933 9934 9935 MachineMemOperand *MMO = 9936 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9937 MachineMemOperand::MOStore, 2, 2); 9938 9939 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9940 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9941 DAG.getVTList(MVT::Other), 9942 Ops, 2, MVT::i16, MMO); 9943 9944 // Load FP Control Word from stack slot 9945 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9946 MachinePointerInfo(), false, false, false, 0); 9947 9948 // Transform as necessary 9949 SDValue CWD1 = 9950 DAG.getNode(ISD::SRL, DL, MVT::i16, 9951 DAG.getNode(ISD::AND, DL, MVT::i16, 9952 CWD, DAG.getConstant(0x800, MVT::i16)), 9953 DAG.getConstant(11, MVT::i8)); 9954 SDValue CWD2 = 9955 DAG.getNode(ISD::SRL, DL, MVT::i16, 9956 DAG.getNode(ISD::AND, DL, MVT::i16, 9957 CWD, DAG.getConstant(0x400, MVT::i16)), 9958 DAG.getConstant(9, MVT::i8)); 9959 9960 SDValue RetVal = 9961 DAG.getNode(ISD::AND, DL, MVT::i16, 9962 DAG.getNode(ISD::ADD, DL, MVT::i16, 9963 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9964 DAG.getConstant(1, MVT::i16)), 9965 DAG.getConstant(3, MVT::i16)); 9966 9967 9968 return DAG.getNode((VT.getSizeInBits() < 16 ? 9969 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9970} 9971 9972SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9973 EVT VT = Op.getValueType(); 9974 EVT OpVT = VT; 9975 unsigned NumBits = VT.getSizeInBits(); 9976 DebugLoc dl = Op.getDebugLoc(); 9977 9978 Op = Op.getOperand(0); 9979 if (VT == MVT::i8) { 9980 // Zero extend to i32 since there is not an i8 bsr. 9981 OpVT = MVT::i32; 9982 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9983 } 9984 9985 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9986 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9987 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9988 9989 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9990 SDValue Ops[] = { 9991 Op, 9992 DAG.getConstant(NumBits+NumBits-1, OpVT), 9993 DAG.getConstant(X86::COND_E, MVT::i8), 9994 Op.getValue(1) 9995 }; 9996 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9997 9998 // Finally xor with NumBits-1. 9999 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10000 10001 if (VT == MVT::i8) 10002 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10003 return Op; 10004} 10005 10006SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10007 SelectionDAG &DAG) const { 10008 EVT VT = Op.getValueType(); 10009 EVT OpVT = VT; 10010 unsigned NumBits = VT.getSizeInBits(); 10011 DebugLoc dl = Op.getDebugLoc(); 10012 10013 Op = Op.getOperand(0); 10014 if (VT == MVT::i8) { 10015 // Zero extend to i32 since there is not an i8 bsr. 10016 OpVT = MVT::i32; 10017 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10018 } 10019 10020 // Issue a bsr (scan bits in reverse). 10021 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10022 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10023 10024 // And xor with NumBits-1. 10025 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10026 10027 if (VT == MVT::i8) 10028 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10029 return Op; 10030} 10031 10032SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10033 EVT VT = Op.getValueType(); 10034 unsigned NumBits = VT.getSizeInBits(); 10035 DebugLoc dl = Op.getDebugLoc(); 10036 Op = Op.getOperand(0); 10037 10038 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10039 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10040 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10041 10042 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10043 SDValue Ops[] = { 10044 Op, 10045 DAG.getConstant(NumBits, VT), 10046 DAG.getConstant(X86::COND_E, MVT::i8), 10047 Op.getValue(1) 10048 }; 10049 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10050} 10051 10052// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10053// ones, and then concatenate the result back. 10054static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10055 EVT VT = Op.getValueType(); 10056 10057 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10058 "Unsupported value type for operation"); 10059 10060 int NumElems = VT.getVectorNumElements(); 10061 DebugLoc dl = Op.getDebugLoc(); 10062 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10063 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10064 10065 // Extract the LHS vectors 10066 SDValue LHS = Op.getOperand(0); 10067 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10068 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10069 10070 // Extract the RHS vectors 10071 SDValue RHS = Op.getOperand(1); 10072 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10073 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10074 10075 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10076 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10077 10078 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10079 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10080 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10081} 10082 10083SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10084 assert(Op.getValueType().getSizeInBits() == 256 && 10085 Op.getValueType().isInteger() && 10086 "Only handle AVX 256-bit vector integer operation"); 10087 return Lower256IntArith(Op, DAG); 10088} 10089 10090SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10091 assert(Op.getValueType().getSizeInBits() == 256 && 10092 Op.getValueType().isInteger() && 10093 "Only handle AVX 256-bit vector integer operation"); 10094 return Lower256IntArith(Op, DAG); 10095} 10096 10097SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10098 EVT VT = Op.getValueType(); 10099 10100 // Decompose 256-bit ops into smaller 128-bit ops. 10101 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10102 return Lower256IntArith(Op, DAG); 10103 10104 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10105 "Only know how to lower V2I64/V4I64 multiply"); 10106 10107 DebugLoc dl = Op.getDebugLoc(); 10108 10109 // Ahi = psrlqi(a, 32); 10110 // Bhi = psrlqi(b, 32); 10111 // 10112 // AloBlo = pmuludq(a, b); 10113 // AloBhi = pmuludq(a, Bhi); 10114 // AhiBlo = pmuludq(Ahi, b); 10115 10116 // AloBhi = psllqi(AloBhi, 32); 10117 // AhiBlo = psllqi(AhiBlo, 32); 10118 // return AloBlo + AloBhi + AhiBlo; 10119 10120 SDValue A = Op.getOperand(0); 10121 SDValue B = Op.getOperand(1); 10122 10123 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10124 10125 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10126 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10127 10128 // Bit cast to 32-bit vectors for MULUDQ 10129 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10130 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10131 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10132 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10133 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10134 10135 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10136 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10137 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10138 10139 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10140 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10141 10142 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10143 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10144} 10145 10146SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10147 10148 EVT VT = Op.getValueType(); 10149 DebugLoc dl = Op.getDebugLoc(); 10150 SDValue R = Op.getOperand(0); 10151 SDValue Amt = Op.getOperand(1); 10152 LLVMContext *Context = DAG.getContext(); 10153 10154 if (!Subtarget->hasSSE2()) 10155 return SDValue(); 10156 10157 // Optimize shl/srl/sra with constant shift amount. 10158 if (isSplatVector(Amt.getNode())) { 10159 SDValue SclrAmt = Amt->getOperand(0); 10160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10161 uint64_t ShiftAmt = C->getZExtValue(); 10162 10163 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10164 (Subtarget->hasAVX2() && 10165 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10166 if (Op.getOpcode() == ISD::SHL) 10167 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10168 DAG.getConstant(ShiftAmt, MVT::i32)); 10169 if (Op.getOpcode() == ISD::SRL) 10170 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10171 DAG.getConstant(ShiftAmt, MVT::i32)); 10172 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10173 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10174 DAG.getConstant(ShiftAmt, MVT::i32)); 10175 } 10176 10177 if (VT == MVT::v16i8) { 10178 if (Op.getOpcode() == ISD::SHL) { 10179 // Make a large shift. 10180 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10181 DAG.getConstant(ShiftAmt, MVT::i32)); 10182 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10183 // Zero out the rightmost bits. 10184 SmallVector<SDValue, 16> V(16, 10185 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10186 MVT::i8)); 10187 return DAG.getNode(ISD::AND, dl, VT, SHL, 10188 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10189 } 10190 if (Op.getOpcode() == ISD::SRL) { 10191 // Make a large shift. 10192 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10193 DAG.getConstant(ShiftAmt, MVT::i32)); 10194 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10195 // Zero out the leftmost bits. 10196 SmallVector<SDValue, 16> V(16, 10197 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10198 MVT::i8)); 10199 return DAG.getNode(ISD::AND, dl, VT, SRL, 10200 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10201 } 10202 if (Op.getOpcode() == ISD::SRA) { 10203 if (ShiftAmt == 7) { 10204 // R s>> 7 === R s< 0 10205 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10206 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10207 } 10208 10209 // R s>> a === ((R u>> a) ^ m) - m 10210 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10211 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10212 MVT::i8)); 10213 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10214 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10215 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10216 return Res; 10217 } 10218 } 10219 10220 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10221 if (Op.getOpcode() == ISD::SHL) { 10222 // Make a large shift. 10223 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10224 DAG.getConstant(ShiftAmt, MVT::i32)); 10225 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10226 // Zero out the rightmost bits. 10227 SmallVector<SDValue, 32> V(32, 10228 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10229 MVT::i8)); 10230 return DAG.getNode(ISD::AND, dl, VT, SHL, 10231 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10232 } 10233 if (Op.getOpcode() == ISD::SRL) { 10234 // Make a large shift. 10235 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10236 DAG.getConstant(ShiftAmt, MVT::i32)); 10237 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10238 // Zero out the leftmost bits. 10239 SmallVector<SDValue, 32> V(32, 10240 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10241 MVT::i8)); 10242 return DAG.getNode(ISD::AND, dl, VT, SRL, 10243 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10244 } 10245 if (Op.getOpcode() == ISD::SRA) { 10246 if (ShiftAmt == 7) { 10247 // R s>> 7 === R s< 0 10248 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10249 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10250 } 10251 10252 // R s>> a === ((R u>> a) ^ m) - m 10253 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10254 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10255 MVT::i8)); 10256 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10257 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10258 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10259 return Res; 10260 } 10261 } 10262 } 10263 } 10264 10265 // Lower SHL with variable shift amount. 10266 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10267 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10268 DAG.getConstant(23, MVT::i32)); 10269 10270 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10271 Constant *C = ConstantDataVector::get(*Context, CV); 10272 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10273 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10274 MachinePointerInfo::getConstantPool(), 10275 false, false, false, 16); 10276 10277 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10278 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10279 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10280 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10281 } 10282 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10283 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10284 10285 // a = a << 5; 10286 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10287 DAG.getConstant(5, MVT::i32)); 10288 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10289 10290 // Turn 'a' into a mask suitable for VSELECT 10291 SDValue VSelM = DAG.getConstant(0x80, VT); 10292 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10293 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10294 10295 SDValue CM1 = DAG.getConstant(0x0f, VT); 10296 SDValue CM2 = DAG.getConstant(0x3f, VT); 10297 10298 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10299 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10300 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10301 DAG.getConstant(4, MVT::i32), DAG); 10302 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10303 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10304 10305 // a += a 10306 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10307 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10308 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10309 10310 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10311 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10312 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10313 DAG.getConstant(2, MVT::i32), DAG); 10314 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10315 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10316 10317 // a += a 10318 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10319 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10320 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10321 10322 // return VSELECT(r, r+r, a); 10323 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10324 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10325 return R; 10326 } 10327 10328 // Decompose 256-bit shifts into smaller 128-bit shifts. 10329 if (VT.getSizeInBits() == 256) { 10330 unsigned NumElems = VT.getVectorNumElements(); 10331 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10332 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10333 10334 // Extract the two vectors 10335 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10336 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10337 DAG, dl); 10338 10339 // Recreate the shift amount vectors 10340 SDValue Amt1, Amt2; 10341 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10342 // Constant shift amount 10343 SmallVector<SDValue, 4> Amt1Csts; 10344 SmallVector<SDValue, 4> Amt2Csts; 10345 for (unsigned i = 0; i != NumElems/2; ++i) 10346 Amt1Csts.push_back(Amt->getOperand(i)); 10347 for (unsigned i = NumElems/2; i != NumElems; ++i) 10348 Amt2Csts.push_back(Amt->getOperand(i)); 10349 10350 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10351 &Amt1Csts[0], NumElems/2); 10352 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10353 &Amt2Csts[0], NumElems/2); 10354 } else { 10355 // Variable shift amount 10356 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10357 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10358 DAG, dl); 10359 } 10360 10361 // Issue new vector shifts for the smaller types 10362 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10363 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10364 10365 // Concatenate the result back 10366 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10367 } 10368 10369 return SDValue(); 10370} 10371 10372SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10373 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10374 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10375 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10376 // has only one use. 10377 SDNode *N = Op.getNode(); 10378 SDValue LHS = N->getOperand(0); 10379 SDValue RHS = N->getOperand(1); 10380 unsigned BaseOp = 0; 10381 unsigned Cond = 0; 10382 DebugLoc DL = Op.getDebugLoc(); 10383 switch (Op.getOpcode()) { 10384 default: llvm_unreachable("Unknown ovf instruction!"); 10385 case ISD::SADDO: 10386 // A subtract of one will be selected as a INC. Note that INC doesn't 10387 // set CF, so we can't do this for UADDO. 10388 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10389 if (C->isOne()) { 10390 BaseOp = X86ISD::INC; 10391 Cond = X86::COND_O; 10392 break; 10393 } 10394 BaseOp = X86ISD::ADD; 10395 Cond = X86::COND_O; 10396 break; 10397 case ISD::UADDO: 10398 BaseOp = X86ISD::ADD; 10399 Cond = X86::COND_B; 10400 break; 10401 case ISD::SSUBO: 10402 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10403 // set CF, so we can't do this for USUBO. 10404 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10405 if (C->isOne()) { 10406 BaseOp = X86ISD::DEC; 10407 Cond = X86::COND_O; 10408 break; 10409 } 10410 BaseOp = X86ISD::SUB; 10411 Cond = X86::COND_O; 10412 break; 10413 case ISD::USUBO: 10414 BaseOp = X86ISD::SUB; 10415 Cond = X86::COND_B; 10416 break; 10417 case ISD::SMULO: 10418 BaseOp = X86ISD::SMUL; 10419 Cond = X86::COND_O; 10420 break; 10421 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10422 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10423 MVT::i32); 10424 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10425 10426 SDValue SetCC = 10427 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10428 DAG.getConstant(X86::COND_O, MVT::i32), 10429 SDValue(Sum.getNode(), 2)); 10430 10431 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10432 } 10433 } 10434 10435 // Also sets EFLAGS. 10436 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10437 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10438 10439 SDValue SetCC = 10440 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10441 DAG.getConstant(Cond, MVT::i32), 10442 SDValue(Sum.getNode(), 1)); 10443 10444 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10445} 10446 10447SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10448 SelectionDAG &DAG) const { 10449 DebugLoc dl = Op.getDebugLoc(); 10450 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10451 EVT VT = Op.getValueType(); 10452 10453 if (!Subtarget->hasSSE2() || !VT.isVector()) 10454 return SDValue(); 10455 10456 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10457 ExtraVT.getScalarType().getSizeInBits(); 10458 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10459 10460 switch (VT.getSimpleVT().SimpleTy) { 10461 default: return SDValue(); 10462 case MVT::v8i32: 10463 case MVT::v16i16: 10464 if (!Subtarget->hasAVX()) 10465 return SDValue(); 10466 if (!Subtarget->hasAVX2()) { 10467 // needs to be split 10468 int NumElems = VT.getVectorNumElements(); 10469 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10470 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10471 10472 // Extract the LHS vectors 10473 SDValue LHS = Op.getOperand(0); 10474 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10475 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10476 10477 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10478 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10479 10480 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10481 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10482 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10483 ExtraNumElems/2); 10484 SDValue Extra = DAG.getValueType(ExtraVT); 10485 10486 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10487 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10488 10489 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10490 } 10491 // fall through 10492 case MVT::v4i32: 10493 case MVT::v8i16: { 10494 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10495 Op.getOperand(0), ShAmt, DAG); 10496 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10497 } 10498 } 10499} 10500 10501 10502SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10503 DebugLoc dl = Op.getDebugLoc(); 10504 10505 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10506 // There isn't any reason to disable it if the target processor supports it. 10507 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10508 SDValue Chain = Op.getOperand(0); 10509 SDValue Zero = DAG.getConstant(0, MVT::i32); 10510 SDValue Ops[] = { 10511 DAG.getRegister(X86::ESP, MVT::i32), // Base 10512 DAG.getTargetConstant(1, MVT::i8), // Scale 10513 DAG.getRegister(0, MVT::i32), // Index 10514 DAG.getTargetConstant(0, MVT::i32), // Disp 10515 DAG.getRegister(0, MVT::i32), // Segment. 10516 Zero, 10517 Chain 10518 }; 10519 SDNode *Res = 10520 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10521 array_lengthof(Ops)); 10522 return SDValue(Res, 0); 10523 } 10524 10525 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10526 if (!isDev) 10527 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10528 10529 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10530 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10531 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10532 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10533 10534 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10535 if (!Op1 && !Op2 && !Op3 && Op4) 10536 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10537 10538 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10539 if (Op1 && !Op2 && !Op3 && !Op4) 10540 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10541 10542 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10543 // (MFENCE)>; 10544 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10545} 10546 10547SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10548 SelectionDAG &DAG) const { 10549 DebugLoc dl = Op.getDebugLoc(); 10550 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10551 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10552 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10553 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10554 10555 // The only fence that needs an instruction is a sequentially-consistent 10556 // cross-thread fence. 10557 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10558 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10559 // no-sse2). There isn't any reason to disable it if the target processor 10560 // supports it. 10561 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10562 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10563 10564 SDValue Chain = Op.getOperand(0); 10565 SDValue Zero = DAG.getConstant(0, MVT::i32); 10566 SDValue Ops[] = { 10567 DAG.getRegister(X86::ESP, MVT::i32), // Base 10568 DAG.getTargetConstant(1, MVT::i8), // Scale 10569 DAG.getRegister(0, MVT::i32), // Index 10570 DAG.getTargetConstant(0, MVT::i32), // Disp 10571 DAG.getRegister(0, MVT::i32), // Segment. 10572 Zero, 10573 Chain 10574 }; 10575 SDNode *Res = 10576 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10577 array_lengthof(Ops)); 10578 return SDValue(Res, 0); 10579 } 10580 10581 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10582 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10583} 10584 10585 10586SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10587 EVT T = Op.getValueType(); 10588 DebugLoc DL = Op.getDebugLoc(); 10589 unsigned Reg = 0; 10590 unsigned size = 0; 10591 switch(T.getSimpleVT().SimpleTy) { 10592 default: llvm_unreachable("Invalid value type!"); 10593 case MVT::i8: Reg = X86::AL; size = 1; break; 10594 case MVT::i16: Reg = X86::AX; size = 2; break; 10595 case MVT::i32: Reg = X86::EAX; size = 4; break; 10596 case MVT::i64: 10597 assert(Subtarget->is64Bit() && "Node not type legal!"); 10598 Reg = X86::RAX; size = 8; 10599 break; 10600 } 10601 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10602 Op.getOperand(2), SDValue()); 10603 SDValue Ops[] = { cpIn.getValue(0), 10604 Op.getOperand(1), 10605 Op.getOperand(3), 10606 DAG.getTargetConstant(size, MVT::i8), 10607 cpIn.getValue(1) }; 10608 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10609 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10610 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10611 Ops, 5, T, MMO); 10612 SDValue cpOut = 10613 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10614 return cpOut; 10615} 10616 10617SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10618 SelectionDAG &DAG) const { 10619 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10620 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10621 SDValue TheChain = Op.getOperand(0); 10622 DebugLoc dl = Op.getDebugLoc(); 10623 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10624 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10625 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10626 rax.getValue(2)); 10627 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10628 DAG.getConstant(32, MVT::i8)); 10629 SDValue Ops[] = { 10630 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10631 rdx.getValue(1) 10632 }; 10633 return DAG.getMergeValues(Ops, 2, dl); 10634} 10635 10636SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10637 SelectionDAG &DAG) const { 10638 EVT SrcVT = Op.getOperand(0).getValueType(); 10639 EVT DstVT = Op.getValueType(); 10640 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10641 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10642 assert((DstVT == MVT::i64 || 10643 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10644 "Unexpected custom BITCAST"); 10645 // i64 <=> MMX conversions are Legal. 10646 if (SrcVT==MVT::i64 && DstVT.isVector()) 10647 return Op; 10648 if (DstVT==MVT::i64 && SrcVT.isVector()) 10649 return Op; 10650 // MMX <=> MMX conversions are Legal. 10651 if (SrcVT.isVector() && DstVT.isVector()) 10652 return Op; 10653 // All other conversions need to be expanded. 10654 return SDValue(); 10655} 10656 10657SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10658 SDNode *Node = Op.getNode(); 10659 DebugLoc dl = Node->getDebugLoc(); 10660 EVT T = Node->getValueType(0); 10661 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10662 DAG.getConstant(0, T), Node->getOperand(2)); 10663 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10664 cast<AtomicSDNode>(Node)->getMemoryVT(), 10665 Node->getOperand(0), 10666 Node->getOperand(1), negOp, 10667 cast<AtomicSDNode>(Node)->getSrcValue(), 10668 cast<AtomicSDNode>(Node)->getAlignment(), 10669 cast<AtomicSDNode>(Node)->getOrdering(), 10670 cast<AtomicSDNode>(Node)->getSynchScope()); 10671} 10672 10673static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10674 SDNode *Node = Op.getNode(); 10675 DebugLoc dl = Node->getDebugLoc(); 10676 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10677 10678 // Convert seq_cst store -> xchg 10679 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10680 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10681 // (The only way to get a 16-byte store is cmpxchg16b) 10682 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10683 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10684 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10685 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10686 cast<AtomicSDNode>(Node)->getMemoryVT(), 10687 Node->getOperand(0), 10688 Node->getOperand(1), Node->getOperand(2), 10689 cast<AtomicSDNode>(Node)->getMemOperand(), 10690 cast<AtomicSDNode>(Node)->getOrdering(), 10691 cast<AtomicSDNode>(Node)->getSynchScope()); 10692 return Swap.getValue(1); 10693 } 10694 // Other atomic stores have a simple pattern. 10695 return Op; 10696} 10697 10698static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10699 EVT VT = Op.getNode()->getValueType(0); 10700 10701 // Let legalize expand this if it isn't a legal type yet. 10702 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10703 return SDValue(); 10704 10705 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10706 10707 unsigned Opc; 10708 bool ExtraOp = false; 10709 switch (Op.getOpcode()) { 10710 default: llvm_unreachable("Invalid code"); 10711 case ISD::ADDC: Opc = X86ISD::ADD; break; 10712 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10713 case ISD::SUBC: Opc = X86ISD::SUB; break; 10714 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10715 } 10716 10717 if (!ExtraOp) 10718 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10719 Op.getOperand(1)); 10720 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10721 Op.getOperand(1), Op.getOperand(2)); 10722} 10723 10724/// LowerOperation - Provide custom lowering hooks for some operations. 10725/// 10726SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10727 switch (Op.getOpcode()) { 10728 default: llvm_unreachable("Should not custom lower this!"); 10729 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10730 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10731 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10732 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10733 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10734 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10735 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10736 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10737 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10738 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10739 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10740 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10741 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10742 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10743 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10744 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10745 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10746 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10747 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10748 case ISD::SHL_PARTS: 10749 case ISD::SRA_PARTS: 10750 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10751 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10752 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10753 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10754 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10755 case ISD::FABS: return LowerFABS(Op, DAG); 10756 case ISD::FNEG: return LowerFNEG(Op, DAG); 10757 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10758 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10759 case ISD::SETCC: return LowerSETCC(Op, DAG); 10760 case ISD::SELECT: return LowerSELECT(Op, DAG); 10761 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10762 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10763 case ISD::VASTART: return LowerVASTART(Op, DAG); 10764 case ISD::VAARG: return LowerVAARG(Op, DAG); 10765 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10766 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10767 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10768 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10769 case ISD::FRAME_TO_ARGS_OFFSET: 10770 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10771 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10772 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10773 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10774 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10775 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10776 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10777 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10778 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10779 case ISD::MUL: return LowerMUL(Op, DAG); 10780 case ISD::SRA: 10781 case ISD::SRL: 10782 case ISD::SHL: return LowerShift(Op, DAG); 10783 case ISD::SADDO: 10784 case ISD::UADDO: 10785 case ISD::SSUBO: 10786 case ISD::USUBO: 10787 case ISD::SMULO: 10788 case ISD::UMULO: return LowerXALUO(Op, DAG); 10789 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10790 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10791 case ISD::ADDC: 10792 case ISD::ADDE: 10793 case ISD::SUBC: 10794 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10795 case ISD::ADD: return LowerADD(Op, DAG); 10796 case ISD::SUB: return LowerSUB(Op, DAG); 10797 } 10798} 10799 10800static void ReplaceATOMIC_LOAD(SDNode *Node, 10801 SmallVectorImpl<SDValue> &Results, 10802 SelectionDAG &DAG) { 10803 DebugLoc dl = Node->getDebugLoc(); 10804 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10805 10806 // Convert wide load -> cmpxchg8b/cmpxchg16b 10807 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10808 // (The only way to get a 16-byte load is cmpxchg16b) 10809 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10810 SDValue Zero = DAG.getConstant(0, VT); 10811 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10812 Node->getOperand(0), 10813 Node->getOperand(1), Zero, Zero, 10814 cast<AtomicSDNode>(Node)->getMemOperand(), 10815 cast<AtomicSDNode>(Node)->getOrdering(), 10816 cast<AtomicSDNode>(Node)->getSynchScope()); 10817 Results.push_back(Swap.getValue(0)); 10818 Results.push_back(Swap.getValue(1)); 10819} 10820 10821void X86TargetLowering:: 10822ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10823 SelectionDAG &DAG, unsigned NewOp) const { 10824 DebugLoc dl = Node->getDebugLoc(); 10825 assert (Node->getValueType(0) == MVT::i64 && 10826 "Only know how to expand i64 atomics"); 10827 10828 SDValue Chain = Node->getOperand(0); 10829 SDValue In1 = Node->getOperand(1); 10830 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10831 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10832 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10833 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10834 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10835 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10836 SDValue Result = 10837 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10838 cast<MemSDNode>(Node)->getMemOperand()); 10839 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10840 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10841 Results.push_back(Result.getValue(2)); 10842} 10843 10844/// ReplaceNodeResults - Replace a node with an illegal result type 10845/// with a new node built out of custom code. 10846void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10847 SmallVectorImpl<SDValue>&Results, 10848 SelectionDAG &DAG) const { 10849 DebugLoc dl = N->getDebugLoc(); 10850 switch (N->getOpcode()) { 10851 default: 10852 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10853 case ISD::SIGN_EXTEND_INREG: 10854 case ISD::ADDC: 10855 case ISD::ADDE: 10856 case ISD::SUBC: 10857 case ISD::SUBE: 10858 // We don't want to expand or promote these. 10859 return; 10860 case ISD::FP_TO_SINT: { 10861 std::pair<SDValue,SDValue> Vals = 10862 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10863 SDValue FIST = Vals.first, StackSlot = Vals.second; 10864 if (FIST.getNode() != 0) { 10865 EVT VT = N->getValueType(0); 10866 // Return a load from the stack slot. 10867 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10868 MachinePointerInfo(), 10869 false, false, false, 0)); 10870 } 10871 return; 10872 } 10873 case ISD::READCYCLECOUNTER: { 10874 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10875 SDValue TheChain = N->getOperand(0); 10876 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10877 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10878 rd.getValue(1)); 10879 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10880 eax.getValue(2)); 10881 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10882 SDValue Ops[] = { eax, edx }; 10883 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10884 Results.push_back(edx.getValue(1)); 10885 return; 10886 } 10887 case ISD::ATOMIC_CMP_SWAP: { 10888 EVT T = N->getValueType(0); 10889 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10890 bool Regs64bit = T == MVT::i128; 10891 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10892 SDValue cpInL, cpInH; 10893 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10894 DAG.getConstant(0, HalfT)); 10895 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10896 DAG.getConstant(1, HalfT)); 10897 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10898 Regs64bit ? X86::RAX : X86::EAX, 10899 cpInL, SDValue()); 10900 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10901 Regs64bit ? X86::RDX : X86::EDX, 10902 cpInH, cpInL.getValue(1)); 10903 SDValue swapInL, swapInH; 10904 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10905 DAG.getConstant(0, HalfT)); 10906 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10907 DAG.getConstant(1, HalfT)); 10908 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10909 Regs64bit ? X86::RBX : X86::EBX, 10910 swapInL, cpInH.getValue(1)); 10911 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10912 Regs64bit ? X86::RCX : X86::ECX, 10913 swapInH, swapInL.getValue(1)); 10914 SDValue Ops[] = { swapInH.getValue(0), 10915 N->getOperand(1), 10916 swapInH.getValue(1) }; 10917 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10918 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10919 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10920 X86ISD::LCMPXCHG8_DAG; 10921 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10922 Ops, 3, T, MMO); 10923 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10924 Regs64bit ? X86::RAX : X86::EAX, 10925 HalfT, Result.getValue(1)); 10926 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10927 Regs64bit ? X86::RDX : X86::EDX, 10928 HalfT, cpOutL.getValue(2)); 10929 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10930 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10931 Results.push_back(cpOutH.getValue(1)); 10932 return; 10933 } 10934 case ISD::ATOMIC_LOAD_ADD: 10935 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10936 return; 10937 case ISD::ATOMIC_LOAD_AND: 10938 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10939 return; 10940 case ISD::ATOMIC_LOAD_NAND: 10941 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10942 return; 10943 case ISD::ATOMIC_LOAD_OR: 10944 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10945 return; 10946 case ISD::ATOMIC_LOAD_SUB: 10947 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10948 return; 10949 case ISD::ATOMIC_LOAD_XOR: 10950 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10951 return; 10952 case ISD::ATOMIC_SWAP: 10953 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10954 return; 10955 case ISD::ATOMIC_LOAD: 10956 ReplaceATOMIC_LOAD(N, Results, DAG); 10957 } 10958} 10959 10960const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10961 switch (Opcode) { 10962 default: return NULL; 10963 case X86ISD::BSF: return "X86ISD::BSF"; 10964 case X86ISD::BSR: return "X86ISD::BSR"; 10965 case X86ISD::SHLD: return "X86ISD::SHLD"; 10966 case X86ISD::SHRD: return "X86ISD::SHRD"; 10967 case X86ISD::FAND: return "X86ISD::FAND"; 10968 case X86ISD::FOR: return "X86ISD::FOR"; 10969 case X86ISD::FXOR: return "X86ISD::FXOR"; 10970 case X86ISD::FSRL: return "X86ISD::FSRL"; 10971 case X86ISD::FILD: return "X86ISD::FILD"; 10972 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10973 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10974 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10975 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10976 case X86ISD::FLD: return "X86ISD::FLD"; 10977 case X86ISD::FST: return "X86ISD::FST"; 10978 case X86ISD::CALL: return "X86ISD::CALL"; 10979 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10980 case X86ISD::BT: return "X86ISD::BT"; 10981 case X86ISD::CMP: return "X86ISD::CMP"; 10982 case X86ISD::COMI: return "X86ISD::COMI"; 10983 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10984 case X86ISD::SETCC: return "X86ISD::SETCC"; 10985 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10986 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10987 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10988 case X86ISD::CMOV: return "X86ISD::CMOV"; 10989 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10990 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10991 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10992 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10993 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10994 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10995 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10996 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10997 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10998 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10999 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11000 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11001 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11002 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11003 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11004 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11005 case X86ISD::HADD: return "X86ISD::HADD"; 11006 case X86ISD::HSUB: return "X86ISD::HSUB"; 11007 case X86ISD::FHADD: return "X86ISD::FHADD"; 11008 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11009 case X86ISD::FMAX: return "X86ISD::FMAX"; 11010 case X86ISD::FMIN: return "X86ISD::FMIN"; 11011 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11012 case X86ISD::FRCP: return "X86ISD::FRCP"; 11013 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11014 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11015 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11016 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11017 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11018 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11019 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11020 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11021 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11022 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11023 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11024 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11025 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11026 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11027 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11028 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11029 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11030 case X86ISD::VSHL: return "X86ISD::VSHL"; 11031 case X86ISD::VSRL: return "X86ISD::VSRL"; 11032 case X86ISD::VSRA: return "X86ISD::VSRA"; 11033 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11034 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11035 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11036 case X86ISD::CMPP: return "X86ISD::CMPP"; 11037 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11038 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11039 case X86ISD::ADD: return "X86ISD::ADD"; 11040 case X86ISD::SUB: return "X86ISD::SUB"; 11041 case X86ISD::ADC: return "X86ISD::ADC"; 11042 case X86ISD::SBB: return "X86ISD::SBB"; 11043 case X86ISD::SMUL: return "X86ISD::SMUL"; 11044 case X86ISD::UMUL: return "X86ISD::UMUL"; 11045 case X86ISD::INC: return "X86ISD::INC"; 11046 case X86ISD::DEC: return "X86ISD::DEC"; 11047 case X86ISD::OR: return "X86ISD::OR"; 11048 case X86ISD::XOR: return "X86ISD::XOR"; 11049 case X86ISD::AND: return "X86ISD::AND"; 11050 case X86ISD::ANDN: return "X86ISD::ANDN"; 11051 case X86ISD::BLSI: return "X86ISD::BLSI"; 11052 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11053 case X86ISD::BLSR: return "X86ISD::BLSR"; 11054 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11055 case X86ISD::PTEST: return "X86ISD::PTEST"; 11056 case X86ISD::TESTP: return "X86ISD::TESTP"; 11057 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11058 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11059 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11060 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11061 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11062 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11063 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11064 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11065 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11066 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11067 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11068 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11069 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11070 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11071 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11072 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11073 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11074 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11075 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11076 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11077 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11078 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11079 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11080 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11081 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11082 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11083 } 11084} 11085 11086// isLegalAddressingMode - Return true if the addressing mode represented 11087// by AM is legal for this target, for a load/store of the specified type. 11088bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11089 Type *Ty) const { 11090 // X86 supports extremely general addressing modes. 11091 CodeModel::Model M = getTargetMachine().getCodeModel(); 11092 Reloc::Model R = getTargetMachine().getRelocationModel(); 11093 11094 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11095 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11096 return false; 11097 11098 if (AM.BaseGV) { 11099 unsigned GVFlags = 11100 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11101 11102 // If a reference to this global requires an extra load, we can't fold it. 11103 if (isGlobalStubReference(GVFlags)) 11104 return false; 11105 11106 // If BaseGV requires a register for the PIC base, we cannot also have a 11107 // BaseReg specified. 11108 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11109 return false; 11110 11111 // If lower 4G is not available, then we must use rip-relative addressing. 11112 if ((M != CodeModel::Small || R != Reloc::Static) && 11113 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11114 return false; 11115 } 11116 11117 switch (AM.Scale) { 11118 case 0: 11119 case 1: 11120 case 2: 11121 case 4: 11122 case 8: 11123 // These scales always work. 11124 break; 11125 case 3: 11126 case 5: 11127 case 9: 11128 // These scales are formed with basereg+scalereg. Only accept if there is 11129 // no basereg yet. 11130 if (AM.HasBaseReg) 11131 return false; 11132 break; 11133 default: // Other stuff never works. 11134 return false; 11135 } 11136 11137 return true; 11138} 11139 11140 11141bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11142 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11143 return false; 11144 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11145 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11146 if (NumBits1 <= NumBits2) 11147 return false; 11148 return true; 11149} 11150 11151bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11152 if (!VT1.isInteger() || !VT2.isInteger()) 11153 return false; 11154 unsigned NumBits1 = VT1.getSizeInBits(); 11155 unsigned NumBits2 = VT2.getSizeInBits(); 11156 if (NumBits1 <= NumBits2) 11157 return false; 11158 return true; 11159} 11160 11161bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11162 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11163 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11164} 11165 11166bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11167 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11168 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11169} 11170 11171bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11172 // i16 instructions are longer (0x66 prefix) and potentially slower. 11173 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11174} 11175 11176/// isShuffleMaskLegal - Targets can use this to indicate that they only 11177/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11178/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11179/// are assumed to be legal. 11180bool 11181X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11182 EVT VT) const { 11183 // Very little shuffling can be done for 64-bit vectors right now. 11184 if (VT.getSizeInBits() == 64) 11185 return false; 11186 11187 // FIXME: pshufb, blends, shifts. 11188 return (VT.getVectorNumElements() == 2 || 11189 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11190 isMOVLMask(M, VT) || 11191 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11192 isPSHUFDMask(M, VT) || 11193 isPSHUFHWMask(M, VT) || 11194 isPSHUFLWMask(M, VT) || 11195 isPALIGNRMask(M, VT, Subtarget) || 11196 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11197 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11198 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11199 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11200} 11201 11202bool 11203X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11204 EVT VT) const { 11205 unsigned NumElts = VT.getVectorNumElements(); 11206 // FIXME: This collection of masks seems suspect. 11207 if (NumElts == 2) 11208 return true; 11209 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11210 return (isMOVLMask(Mask, VT) || 11211 isCommutedMOVLMask(Mask, VT, true) || 11212 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11213 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11214 } 11215 return false; 11216} 11217 11218//===----------------------------------------------------------------------===// 11219// X86 Scheduler Hooks 11220//===----------------------------------------------------------------------===// 11221 11222// private utility function 11223MachineBasicBlock * 11224X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11225 MachineBasicBlock *MBB, 11226 unsigned regOpc, 11227 unsigned immOpc, 11228 unsigned LoadOpc, 11229 unsigned CXchgOpc, 11230 unsigned notOpc, 11231 unsigned EAXreg, 11232 TargetRegisterClass *RC, 11233 bool invSrc) const { 11234 // For the atomic bitwise operator, we generate 11235 // thisMBB: 11236 // newMBB: 11237 // ld t1 = [bitinstr.addr] 11238 // op t2 = t1, [bitinstr.val] 11239 // mov EAX = t1 11240 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11241 // bz newMBB 11242 // fallthrough -->nextMBB 11243 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11244 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11245 MachineFunction::iterator MBBIter = MBB; 11246 ++MBBIter; 11247 11248 /// First build the CFG 11249 MachineFunction *F = MBB->getParent(); 11250 MachineBasicBlock *thisMBB = MBB; 11251 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11252 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11253 F->insert(MBBIter, newMBB); 11254 F->insert(MBBIter, nextMBB); 11255 11256 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11257 nextMBB->splice(nextMBB->begin(), thisMBB, 11258 llvm::next(MachineBasicBlock::iterator(bInstr)), 11259 thisMBB->end()); 11260 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11261 11262 // Update thisMBB to fall through to newMBB 11263 thisMBB->addSuccessor(newMBB); 11264 11265 // newMBB jumps to itself and fall through to nextMBB 11266 newMBB->addSuccessor(nextMBB); 11267 newMBB->addSuccessor(newMBB); 11268 11269 // Insert instructions into newMBB based on incoming instruction 11270 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11271 "unexpected number of operands"); 11272 DebugLoc dl = bInstr->getDebugLoc(); 11273 MachineOperand& destOper = bInstr->getOperand(0); 11274 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11275 int numArgs = bInstr->getNumOperands() - 1; 11276 for (int i=0; i < numArgs; ++i) 11277 argOpers[i] = &bInstr->getOperand(i+1); 11278 11279 // x86 address has 4 operands: base, index, scale, and displacement 11280 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11281 int valArgIndx = lastAddrIndx + 1; 11282 11283 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11284 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11285 for (int i=0; i <= lastAddrIndx; ++i) 11286 (*MIB).addOperand(*argOpers[i]); 11287 11288 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11289 if (invSrc) { 11290 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11291 } 11292 else 11293 tt = t1; 11294 11295 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11296 assert((argOpers[valArgIndx]->isReg() || 11297 argOpers[valArgIndx]->isImm()) && 11298 "invalid operand"); 11299 if (argOpers[valArgIndx]->isReg()) 11300 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11301 else 11302 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11303 MIB.addReg(tt); 11304 (*MIB).addOperand(*argOpers[valArgIndx]); 11305 11306 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11307 MIB.addReg(t1); 11308 11309 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11310 for (int i=0; i <= lastAddrIndx; ++i) 11311 (*MIB).addOperand(*argOpers[i]); 11312 MIB.addReg(t2); 11313 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11314 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11315 bInstr->memoperands_end()); 11316 11317 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11318 MIB.addReg(EAXreg); 11319 11320 // insert branch 11321 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11322 11323 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11324 return nextMBB; 11325} 11326 11327// private utility function: 64 bit atomics on 32 bit host. 11328MachineBasicBlock * 11329X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11330 MachineBasicBlock *MBB, 11331 unsigned regOpcL, 11332 unsigned regOpcH, 11333 unsigned immOpcL, 11334 unsigned immOpcH, 11335 bool invSrc) const { 11336 // For the atomic bitwise operator, we generate 11337 // thisMBB (instructions are in pairs, except cmpxchg8b) 11338 // ld t1,t2 = [bitinstr.addr] 11339 // newMBB: 11340 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11341 // op t5, t6 <- out1, out2, [bitinstr.val] 11342 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11343 // mov ECX, EBX <- t5, t6 11344 // mov EAX, EDX <- t1, t2 11345 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11346 // mov t3, t4 <- EAX, EDX 11347 // bz newMBB 11348 // result in out1, out2 11349 // fallthrough -->nextMBB 11350 11351 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11352 const unsigned LoadOpc = X86::MOV32rm; 11353 const unsigned NotOpc = X86::NOT32r; 11354 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11355 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11356 MachineFunction::iterator MBBIter = MBB; 11357 ++MBBIter; 11358 11359 /// First build the CFG 11360 MachineFunction *F = MBB->getParent(); 11361 MachineBasicBlock *thisMBB = MBB; 11362 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11363 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11364 F->insert(MBBIter, newMBB); 11365 F->insert(MBBIter, nextMBB); 11366 11367 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11368 nextMBB->splice(nextMBB->begin(), thisMBB, 11369 llvm::next(MachineBasicBlock::iterator(bInstr)), 11370 thisMBB->end()); 11371 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11372 11373 // Update thisMBB to fall through to newMBB 11374 thisMBB->addSuccessor(newMBB); 11375 11376 // newMBB jumps to itself and fall through to nextMBB 11377 newMBB->addSuccessor(nextMBB); 11378 newMBB->addSuccessor(newMBB); 11379 11380 DebugLoc dl = bInstr->getDebugLoc(); 11381 // Insert instructions into newMBB based on incoming instruction 11382 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11383 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11384 "unexpected number of operands"); 11385 MachineOperand& dest1Oper = bInstr->getOperand(0); 11386 MachineOperand& dest2Oper = bInstr->getOperand(1); 11387 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11388 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11389 argOpers[i] = &bInstr->getOperand(i+2); 11390 11391 // We use some of the operands multiple times, so conservatively just 11392 // clear any kill flags that might be present. 11393 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11394 argOpers[i]->setIsKill(false); 11395 } 11396 11397 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11398 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11399 11400 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11401 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11402 for (int i=0; i <= lastAddrIndx; ++i) 11403 (*MIB).addOperand(*argOpers[i]); 11404 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11405 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11406 // add 4 to displacement. 11407 for (int i=0; i <= lastAddrIndx-2; ++i) 11408 (*MIB).addOperand(*argOpers[i]); 11409 MachineOperand newOp3 = *(argOpers[3]); 11410 if (newOp3.isImm()) 11411 newOp3.setImm(newOp3.getImm()+4); 11412 else 11413 newOp3.setOffset(newOp3.getOffset()+4); 11414 (*MIB).addOperand(newOp3); 11415 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11416 11417 // t3/4 are defined later, at the bottom of the loop 11418 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11419 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11420 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11421 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11422 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11423 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11424 11425 // The subsequent operations should be using the destination registers of 11426 //the PHI instructions. 11427 if (invSrc) { 11428 t1 = F->getRegInfo().createVirtualRegister(RC); 11429 t2 = F->getRegInfo().createVirtualRegister(RC); 11430 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11431 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11432 } else { 11433 t1 = dest1Oper.getReg(); 11434 t2 = dest2Oper.getReg(); 11435 } 11436 11437 int valArgIndx = lastAddrIndx + 1; 11438 assert((argOpers[valArgIndx]->isReg() || 11439 argOpers[valArgIndx]->isImm()) && 11440 "invalid operand"); 11441 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11442 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11443 if (argOpers[valArgIndx]->isReg()) 11444 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11445 else 11446 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11447 if (regOpcL != X86::MOV32rr) 11448 MIB.addReg(t1); 11449 (*MIB).addOperand(*argOpers[valArgIndx]); 11450 assert(argOpers[valArgIndx + 1]->isReg() == 11451 argOpers[valArgIndx]->isReg()); 11452 assert(argOpers[valArgIndx + 1]->isImm() == 11453 argOpers[valArgIndx]->isImm()); 11454 if (argOpers[valArgIndx + 1]->isReg()) 11455 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11456 else 11457 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11458 if (regOpcH != X86::MOV32rr) 11459 MIB.addReg(t2); 11460 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11461 11462 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11463 MIB.addReg(t1); 11464 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11465 MIB.addReg(t2); 11466 11467 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11468 MIB.addReg(t5); 11469 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11470 MIB.addReg(t6); 11471 11472 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11473 for (int i=0; i <= lastAddrIndx; ++i) 11474 (*MIB).addOperand(*argOpers[i]); 11475 11476 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11477 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11478 bInstr->memoperands_end()); 11479 11480 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11481 MIB.addReg(X86::EAX); 11482 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11483 MIB.addReg(X86::EDX); 11484 11485 // insert branch 11486 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11487 11488 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11489 return nextMBB; 11490} 11491 11492// private utility function 11493MachineBasicBlock * 11494X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11495 MachineBasicBlock *MBB, 11496 unsigned cmovOpc) const { 11497 // For the atomic min/max operator, we generate 11498 // thisMBB: 11499 // newMBB: 11500 // ld t1 = [min/max.addr] 11501 // mov t2 = [min/max.val] 11502 // cmp t1, t2 11503 // cmov[cond] t2 = t1 11504 // mov EAX = t1 11505 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11506 // bz newMBB 11507 // fallthrough -->nextMBB 11508 // 11509 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11510 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11511 MachineFunction::iterator MBBIter = MBB; 11512 ++MBBIter; 11513 11514 /// First build the CFG 11515 MachineFunction *F = MBB->getParent(); 11516 MachineBasicBlock *thisMBB = MBB; 11517 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11518 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11519 F->insert(MBBIter, newMBB); 11520 F->insert(MBBIter, nextMBB); 11521 11522 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11523 nextMBB->splice(nextMBB->begin(), thisMBB, 11524 llvm::next(MachineBasicBlock::iterator(mInstr)), 11525 thisMBB->end()); 11526 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11527 11528 // Update thisMBB to fall through to newMBB 11529 thisMBB->addSuccessor(newMBB); 11530 11531 // newMBB jumps to newMBB and fall through to nextMBB 11532 newMBB->addSuccessor(nextMBB); 11533 newMBB->addSuccessor(newMBB); 11534 11535 DebugLoc dl = mInstr->getDebugLoc(); 11536 // Insert instructions into newMBB based on incoming instruction 11537 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11538 "unexpected number of operands"); 11539 MachineOperand& destOper = mInstr->getOperand(0); 11540 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11541 int numArgs = mInstr->getNumOperands() - 1; 11542 for (int i=0; i < numArgs; ++i) 11543 argOpers[i] = &mInstr->getOperand(i+1); 11544 11545 // x86 address has 4 operands: base, index, scale, and displacement 11546 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11547 int valArgIndx = lastAddrIndx + 1; 11548 11549 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11550 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11551 for (int i=0; i <= lastAddrIndx; ++i) 11552 (*MIB).addOperand(*argOpers[i]); 11553 11554 // We only support register and immediate values 11555 assert((argOpers[valArgIndx]->isReg() || 11556 argOpers[valArgIndx]->isImm()) && 11557 "invalid operand"); 11558 11559 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11560 if (argOpers[valArgIndx]->isReg()) 11561 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11562 else 11563 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11564 (*MIB).addOperand(*argOpers[valArgIndx]); 11565 11566 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11567 MIB.addReg(t1); 11568 11569 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11570 MIB.addReg(t1); 11571 MIB.addReg(t2); 11572 11573 // Generate movc 11574 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11575 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11576 MIB.addReg(t2); 11577 MIB.addReg(t1); 11578 11579 // Cmp and exchange if none has modified the memory location 11580 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11581 for (int i=0; i <= lastAddrIndx; ++i) 11582 (*MIB).addOperand(*argOpers[i]); 11583 MIB.addReg(t3); 11584 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11585 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11586 mInstr->memoperands_end()); 11587 11588 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11589 MIB.addReg(X86::EAX); 11590 11591 // insert branch 11592 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11593 11594 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11595 return nextMBB; 11596} 11597 11598// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11599// or XMM0_V32I8 in AVX all of this code can be replaced with that 11600// in the .td file. 11601MachineBasicBlock * 11602X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11603 unsigned numArgs, bool memArg) const { 11604 assert(Subtarget->hasSSE42() && 11605 "Target must have SSE4.2 or AVX features enabled"); 11606 11607 DebugLoc dl = MI->getDebugLoc(); 11608 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11609 unsigned Opc; 11610 if (!Subtarget->hasAVX()) { 11611 if (memArg) 11612 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11613 else 11614 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11615 } else { 11616 if (memArg) 11617 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11618 else 11619 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11620 } 11621 11622 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11623 for (unsigned i = 0; i < numArgs; ++i) { 11624 MachineOperand &Op = MI->getOperand(i+1); 11625 if (!(Op.isReg() && Op.isImplicit())) 11626 MIB.addOperand(Op); 11627 } 11628 BuildMI(*BB, MI, dl, 11629 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11630 MI->getOperand(0).getReg()) 11631 .addReg(X86::XMM0); 11632 11633 MI->eraseFromParent(); 11634 return BB; 11635} 11636 11637MachineBasicBlock * 11638X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11639 DebugLoc dl = MI->getDebugLoc(); 11640 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11641 11642 // Address into RAX/EAX, other two args into ECX, EDX. 11643 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11644 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11645 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11646 for (int i = 0; i < X86::AddrNumOperands; ++i) 11647 MIB.addOperand(MI->getOperand(i)); 11648 11649 unsigned ValOps = X86::AddrNumOperands; 11650 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11651 .addReg(MI->getOperand(ValOps).getReg()); 11652 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11653 .addReg(MI->getOperand(ValOps+1).getReg()); 11654 11655 // The instruction doesn't actually take any operands though. 11656 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11657 11658 MI->eraseFromParent(); // The pseudo is gone now. 11659 return BB; 11660} 11661 11662MachineBasicBlock * 11663X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11664 DebugLoc dl = MI->getDebugLoc(); 11665 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11666 11667 // First arg in ECX, the second in EAX. 11668 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11669 .addReg(MI->getOperand(0).getReg()); 11670 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11671 .addReg(MI->getOperand(1).getReg()); 11672 11673 // The instruction doesn't actually take any operands though. 11674 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11675 11676 MI->eraseFromParent(); // The pseudo is gone now. 11677 return BB; 11678} 11679 11680MachineBasicBlock * 11681X86TargetLowering::EmitVAARG64WithCustomInserter( 11682 MachineInstr *MI, 11683 MachineBasicBlock *MBB) const { 11684 // Emit va_arg instruction on X86-64. 11685 11686 // Operands to this pseudo-instruction: 11687 // 0 ) Output : destination address (reg) 11688 // 1-5) Input : va_list address (addr, i64mem) 11689 // 6 ) ArgSize : Size (in bytes) of vararg type 11690 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11691 // 8 ) Align : Alignment of type 11692 // 9 ) EFLAGS (implicit-def) 11693 11694 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11695 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11696 11697 unsigned DestReg = MI->getOperand(0).getReg(); 11698 MachineOperand &Base = MI->getOperand(1); 11699 MachineOperand &Scale = MI->getOperand(2); 11700 MachineOperand &Index = MI->getOperand(3); 11701 MachineOperand &Disp = MI->getOperand(4); 11702 MachineOperand &Segment = MI->getOperand(5); 11703 unsigned ArgSize = MI->getOperand(6).getImm(); 11704 unsigned ArgMode = MI->getOperand(7).getImm(); 11705 unsigned Align = MI->getOperand(8).getImm(); 11706 11707 // Memory Reference 11708 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11709 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11710 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11711 11712 // Machine Information 11713 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11714 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11715 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11716 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11717 DebugLoc DL = MI->getDebugLoc(); 11718 11719 // struct va_list { 11720 // i32 gp_offset 11721 // i32 fp_offset 11722 // i64 overflow_area (address) 11723 // i64 reg_save_area (address) 11724 // } 11725 // sizeof(va_list) = 24 11726 // alignment(va_list) = 8 11727 11728 unsigned TotalNumIntRegs = 6; 11729 unsigned TotalNumXMMRegs = 8; 11730 bool UseGPOffset = (ArgMode == 1); 11731 bool UseFPOffset = (ArgMode == 2); 11732 unsigned MaxOffset = TotalNumIntRegs * 8 + 11733 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11734 11735 /* Align ArgSize to a multiple of 8 */ 11736 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11737 bool NeedsAlign = (Align > 8); 11738 11739 MachineBasicBlock *thisMBB = MBB; 11740 MachineBasicBlock *overflowMBB; 11741 MachineBasicBlock *offsetMBB; 11742 MachineBasicBlock *endMBB; 11743 11744 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11745 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11746 unsigned OffsetReg = 0; 11747 11748 if (!UseGPOffset && !UseFPOffset) { 11749 // If we only pull from the overflow region, we don't create a branch. 11750 // We don't need to alter control flow. 11751 OffsetDestReg = 0; // unused 11752 OverflowDestReg = DestReg; 11753 11754 offsetMBB = NULL; 11755 overflowMBB = thisMBB; 11756 endMBB = thisMBB; 11757 } else { 11758 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11759 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11760 // If not, pull from overflow_area. (branch to overflowMBB) 11761 // 11762 // thisMBB 11763 // | . 11764 // | . 11765 // offsetMBB overflowMBB 11766 // | . 11767 // | . 11768 // endMBB 11769 11770 // Registers for the PHI in endMBB 11771 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11772 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11773 11774 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11775 MachineFunction *MF = MBB->getParent(); 11776 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11777 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11778 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11779 11780 MachineFunction::iterator MBBIter = MBB; 11781 ++MBBIter; 11782 11783 // Insert the new basic blocks 11784 MF->insert(MBBIter, offsetMBB); 11785 MF->insert(MBBIter, overflowMBB); 11786 MF->insert(MBBIter, endMBB); 11787 11788 // Transfer the remainder of MBB and its successor edges to endMBB. 11789 endMBB->splice(endMBB->begin(), thisMBB, 11790 llvm::next(MachineBasicBlock::iterator(MI)), 11791 thisMBB->end()); 11792 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11793 11794 // Make offsetMBB and overflowMBB successors of thisMBB 11795 thisMBB->addSuccessor(offsetMBB); 11796 thisMBB->addSuccessor(overflowMBB); 11797 11798 // endMBB is a successor of both offsetMBB and overflowMBB 11799 offsetMBB->addSuccessor(endMBB); 11800 overflowMBB->addSuccessor(endMBB); 11801 11802 // Load the offset value into a register 11803 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11804 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11805 .addOperand(Base) 11806 .addOperand(Scale) 11807 .addOperand(Index) 11808 .addDisp(Disp, UseFPOffset ? 4 : 0) 11809 .addOperand(Segment) 11810 .setMemRefs(MMOBegin, MMOEnd); 11811 11812 // Check if there is enough room left to pull this argument. 11813 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11814 .addReg(OffsetReg) 11815 .addImm(MaxOffset + 8 - ArgSizeA8); 11816 11817 // Branch to "overflowMBB" if offset >= max 11818 // Fall through to "offsetMBB" otherwise 11819 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11820 .addMBB(overflowMBB); 11821 } 11822 11823 // In offsetMBB, emit code to use the reg_save_area. 11824 if (offsetMBB) { 11825 assert(OffsetReg != 0); 11826 11827 // Read the reg_save_area address. 11828 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11829 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11830 .addOperand(Base) 11831 .addOperand(Scale) 11832 .addOperand(Index) 11833 .addDisp(Disp, 16) 11834 .addOperand(Segment) 11835 .setMemRefs(MMOBegin, MMOEnd); 11836 11837 // Zero-extend the offset 11838 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11839 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11840 .addImm(0) 11841 .addReg(OffsetReg) 11842 .addImm(X86::sub_32bit); 11843 11844 // Add the offset to the reg_save_area to get the final address. 11845 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11846 .addReg(OffsetReg64) 11847 .addReg(RegSaveReg); 11848 11849 // Compute the offset for the next argument 11850 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11851 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11852 .addReg(OffsetReg) 11853 .addImm(UseFPOffset ? 16 : 8); 11854 11855 // Store it back into the va_list. 11856 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11857 .addOperand(Base) 11858 .addOperand(Scale) 11859 .addOperand(Index) 11860 .addDisp(Disp, UseFPOffset ? 4 : 0) 11861 .addOperand(Segment) 11862 .addReg(NextOffsetReg) 11863 .setMemRefs(MMOBegin, MMOEnd); 11864 11865 // Jump to endMBB 11866 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11867 .addMBB(endMBB); 11868 } 11869 11870 // 11871 // Emit code to use overflow area 11872 // 11873 11874 // Load the overflow_area address into a register. 11875 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11876 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11877 .addOperand(Base) 11878 .addOperand(Scale) 11879 .addOperand(Index) 11880 .addDisp(Disp, 8) 11881 .addOperand(Segment) 11882 .setMemRefs(MMOBegin, MMOEnd); 11883 11884 // If we need to align it, do so. Otherwise, just copy the address 11885 // to OverflowDestReg. 11886 if (NeedsAlign) { 11887 // Align the overflow address 11888 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11889 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11890 11891 // aligned_addr = (addr + (align-1)) & ~(align-1) 11892 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11893 .addReg(OverflowAddrReg) 11894 .addImm(Align-1); 11895 11896 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11897 .addReg(TmpReg) 11898 .addImm(~(uint64_t)(Align-1)); 11899 } else { 11900 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11901 .addReg(OverflowAddrReg); 11902 } 11903 11904 // Compute the next overflow address after this argument. 11905 // (the overflow address should be kept 8-byte aligned) 11906 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11907 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11908 .addReg(OverflowDestReg) 11909 .addImm(ArgSizeA8); 11910 11911 // Store the new overflow address. 11912 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11913 .addOperand(Base) 11914 .addOperand(Scale) 11915 .addOperand(Index) 11916 .addDisp(Disp, 8) 11917 .addOperand(Segment) 11918 .addReg(NextAddrReg) 11919 .setMemRefs(MMOBegin, MMOEnd); 11920 11921 // If we branched, emit the PHI to the front of endMBB. 11922 if (offsetMBB) { 11923 BuildMI(*endMBB, endMBB->begin(), DL, 11924 TII->get(X86::PHI), DestReg) 11925 .addReg(OffsetDestReg).addMBB(offsetMBB) 11926 .addReg(OverflowDestReg).addMBB(overflowMBB); 11927 } 11928 11929 // Erase the pseudo instruction 11930 MI->eraseFromParent(); 11931 11932 return endMBB; 11933} 11934 11935MachineBasicBlock * 11936X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11937 MachineInstr *MI, 11938 MachineBasicBlock *MBB) const { 11939 // Emit code to save XMM registers to the stack. The ABI says that the 11940 // number of registers to save is given in %al, so it's theoretically 11941 // possible to do an indirect jump trick to avoid saving all of them, 11942 // however this code takes a simpler approach and just executes all 11943 // of the stores if %al is non-zero. It's less code, and it's probably 11944 // easier on the hardware branch predictor, and stores aren't all that 11945 // expensive anyway. 11946 11947 // Create the new basic blocks. One block contains all the XMM stores, 11948 // and one block is the final destination regardless of whether any 11949 // stores were performed. 11950 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11951 MachineFunction *F = MBB->getParent(); 11952 MachineFunction::iterator MBBIter = MBB; 11953 ++MBBIter; 11954 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11955 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11956 F->insert(MBBIter, XMMSaveMBB); 11957 F->insert(MBBIter, EndMBB); 11958 11959 // Transfer the remainder of MBB and its successor edges to EndMBB. 11960 EndMBB->splice(EndMBB->begin(), MBB, 11961 llvm::next(MachineBasicBlock::iterator(MI)), 11962 MBB->end()); 11963 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11964 11965 // The original block will now fall through to the XMM save block. 11966 MBB->addSuccessor(XMMSaveMBB); 11967 // The XMMSaveMBB will fall through to the end block. 11968 XMMSaveMBB->addSuccessor(EndMBB); 11969 11970 // Now add the instructions. 11971 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11972 DebugLoc DL = MI->getDebugLoc(); 11973 11974 unsigned CountReg = MI->getOperand(0).getReg(); 11975 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11976 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11977 11978 if (!Subtarget->isTargetWin64()) { 11979 // If %al is 0, branch around the XMM save block. 11980 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11981 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11982 MBB->addSuccessor(EndMBB); 11983 } 11984 11985 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11986 // In the XMM save block, save all the XMM argument registers. 11987 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11988 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11989 MachineMemOperand *MMO = 11990 F->getMachineMemOperand( 11991 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11992 MachineMemOperand::MOStore, 11993 /*Size=*/16, /*Align=*/16); 11994 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11995 .addFrameIndex(RegSaveFrameIndex) 11996 .addImm(/*Scale=*/1) 11997 .addReg(/*IndexReg=*/0) 11998 .addImm(/*Disp=*/Offset) 11999 .addReg(/*Segment=*/0) 12000 .addReg(MI->getOperand(i).getReg()) 12001 .addMemOperand(MMO); 12002 } 12003 12004 MI->eraseFromParent(); // The pseudo instruction is gone now. 12005 12006 return EndMBB; 12007} 12008 12009// The EFLAGS operand of SelectItr might be missing a kill marker 12010// because there were multiple uses of EFLAGS, and ISel didn't know 12011// which to mark. Figure out whether SelectItr should have had a 12012// kill marker, and set it if it should. Returns the correct kill 12013// marker value. 12014static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12015 MachineBasicBlock* BB, 12016 const TargetRegisterInfo* TRI) { 12017 // Scan forward through BB for a use/def of EFLAGS. 12018 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12019 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12020 const MachineInstr& mi = *miI; 12021 if (mi.readsRegister(X86::EFLAGS)) 12022 return false; 12023 if (mi.definesRegister(X86::EFLAGS)) 12024 break; // Should have kill-flag - update below. 12025 } 12026 12027 // If we hit the end of the block, check whether EFLAGS is live into a 12028 // successor. 12029 if (miI == BB->end()) { 12030 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12031 sEnd = BB->succ_end(); 12032 sItr != sEnd; ++sItr) { 12033 MachineBasicBlock* succ = *sItr; 12034 if (succ->isLiveIn(X86::EFLAGS)) 12035 return false; 12036 } 12037 } 12038 12039 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12040 // out. SelectMI should have a kill flag on EFLAGS. 12041 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12042 return true; 12043} 12044 12045MachineBasicBlock * 12046X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12047 MachineBasicBlock *BB) const { 12048 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12049 DebugLoc DL = MI->getDebugLoc(); 12050 12051 // To "insert" a SELECT_CC instruction, we actually have to insert the 12052 // diamond control-flow pattern. The incoming instruction knows the 12053 // destination vreg to set, the condition code register to branch on, the 12054 // true/false values to select between, and a branch opcode to use. 12055 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12056 MachineFunction::iterator It = BB; 12057 ++It; 12058 12059 // thisMBB: 12060 // ... 12061 // TrueVal = ... 12062 // cmpTY ccX, r1, r2 12063 // bCC copy1MBB 12064 // fallthrough --> copy0MBB 12065 MachineBasicBlock *thisMBB = BB; 12066 MachineFunction *F = BB->getParent(); 12067 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12068 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12069 F->insert(It, copy0MBB); 12070 F->insert(It, sinkMBB); 12071 12072 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12073 // live into the sink and copy blocks. 12074 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12075 if (!MI->killsRegister(X86::EFLAGS) && 12076 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12077 copy0MBB->addLiveIn(X86::EFLAGS); 12078 sinkMBB->addLiveIn(X86::EFLAGS); 12079 } 12080 12081 // Transfer the remainder of BB and its successor edges to sinkMBB. 12082 sinkMBB->splice(sinkMBB->begin(), BB, 12083 llvm::next(MachineBasicBlock::iterator(MI)), 12084 BB->end()); 12085 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12086 12087 // Add the true and fallthrough blocks as its successors. 12088 BB->addSuccessor(copy0MBB); 12089 BB->addSuccessor(sinkMBB); 12090 12091 // Create the conditional branch instruction. 12092 unsigned Opc = 12093 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12094 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12095 12096 // copy0MBB: 12097 // %FalseValue = ... 12098 // # fallthrough to sinkMBB 12099 copy0MBB->addSuccessor(sinkMBB); 12100 12101 // sinkMBB: 12102 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12103 // ... 12104 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12105 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12106 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12107 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12108 12109 MI->eraseFromParent(); // The pseudo instruction is gone now. 12110 return sinkMBB; 12111} 12112 12113MachineBasicBlock * 12114X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12115 bool Is64Bit) const { 12116 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12117 DebugLoc DL = MI->getDebugLoc(); 12118 MachineFunction *MF = BB->getParent(); 12119 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12120 12121 assert(getTargetMachine().Options.EnableSegmentedStacks); 12122 12123 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12124 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12125 12126 // BB: 12127 // ... [Till the alloca] 12128 // If stacklet is not large enough, jump to mallocMBB 12129 // 12130 // bumpMBB: 12131 // Allocate by subtracting from RSP 12132 // Jump to continueMBB 12133 // 12134 // mallocMBB: 12135 // Allocate by call to runtime 12136 // 12137 // continueMBB: 12138 // ... 12139 // [rest of original BB] 12140 // 12141 12142 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12143 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12144 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12145 12146 MachineRegisterInfo &MRI = MF->getRegInfo(); 12147 const TargetRegisterClass *AddrRegClass = 12148 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12149 12150 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12151 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12152 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12153 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12154 sizeVReg = MI->getOperand(1).getReg(), 12155 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12156 12157 MachineFunction::iterator MBBIter = BB; 12158 ++MBBIter; 12159 12160 MF->insert(MBBIter, bumpMBB); 12161 MF->insert(MBBIter, mallocMBB); 12162 MF->insert(MBBIter, continueMBB); 12163 12164 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12165 (MachineBasicBlock::iterator(MI)), BB->end()); 12166 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12167 12168 // Add code to the main basic block to check if the stack limit has been hit, 12169 // and if so, jump to mallocMBB otherwise to bumpMBB. 12170 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12171 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12172 .addReg(tmpSPVReg).addReg(sizeVReg); 12173 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12174 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12175 .addReg(SPLimitVReg); 12176 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12177 12178 // bumpMBB simply decreases the stack pointer, since we know the current 12179 // stacklet has enough space. 12180 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12181 .addReg(SPLimitVReg); 12182 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12183 .addReg(SPLimitVReg); 12184 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12185 12186 // Calls into a routine in libgcc to allocate more space from the heap. 12187 const uint32_t *RegMask = 12188 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12189 if (Is64Bit) { 12190 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12191 .addReg(sizeVReg); 12192 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12193 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12194 .addRegMask(RegMask) 12195 .addReg(X86::RAX, RegState::ImplicitDefine); 12196 } else { 12197 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12198 .addImm(12); 12199 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12200 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12201 .addExternalSymbol("__morestack_allocate_stack_space") 12202 .addRegMask(RegMask) 12203 .addReg(X86::EAX, RegState::ImplicitDefine); 12204 } 12205 12206 if (!Is64Bit) 12207 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12208 .addImm(16); 12209 12210 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12211 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12212 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12213 12214 // Set up the CFG correctly. 12215 BB->addSuccessor(bumpMBB); 12216 BB->addSuccessor(mallocMBB); 12217 mallocMBB->addSuccessor(continueMBB); 12218 bumpMBB->addSuccessor(continueMBB); 12219 12220 // Take care of the PHI nodes. 12221 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12222 MI->getOperand(0).getReg()) 12223 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12224 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12225 12226 // Delete the original pseudo instruction. 12227 MI->eraseFromParent(); 12228 12229 // And we're done. 12230 return continueMBB; 12231} 12232 12233MachineBasicBlock * 12234X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12235 MachineBasicBlock *BB) const { 12236 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12237 DebugLoc DL = MI->getDebugLoc(); 12238 12239 assert(!Subtarget->isTargetEnvMacho()); 12240 12241 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12242 // non-trivial part is impdef of ESP. 12243 12244 if (Subtarget->isTargetWin64()) { 12245 if (Subtarget->isTargetCygMing()) { 12246 // ___chkstk(Mingw64): 12247 // Clobbers R10, R11, RAX and EFLAGS. 12248 // Updates RSP. 12249 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12250 .addExternalSymbol("___chkstk") 12251 .addReg(X86::RAX, RegState::Implicit) 12252 .addReg(X86::RSP, RegState::Implicit) 12253 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12254 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12255 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12256 } else { 12257 // __chkstk(MSVCRT): does not update stack pointer. 12258 // Clobbers R10, R11 and EFLAGS. 12259 // FIXME: RAX(allocated size) might be reused and not killed. 12260 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12261 .addExternalSymbol("__chkstk") 12262 .addReg(X86::RAX, RegState::Implicit) 12263 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12264 // RAX has the offset to subtracted from RSP. 12265 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12266 .addReg(X86::RSP) 12267 .addReg(X86::RAX); 12268 } 12269 } else { 12270 const char *StackProbeSymbol = 12271 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12272 12273 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12274 .addExternalSymbol(StackProbeSymbol) 12275 .addReg(X86::EAX, RegState::Implicit) 12276 .addReg(X86::ESP, RegState::Implicit) 12277 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12278 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12279 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12280 } 12281 12282 MI->eraseFromParent(); // The pseudo instruction is gone now. 12283 return BB; 12284} 12285 12286MachineBasicBlock * 12287X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12288 MachineBasicBlock *BB) const { 12289 // This is pretty easy. We're taking the value that we received from 12290 // our load from the relocation, sticking it in either RDI (x86-64) 12291 // or EAX and doing an indirect call. The return value will then 12292 // be in the normal return register. 12293 const X86InstrInfo *TII 12294 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12295 DebugLoc DL = MI->getDebugLoc(); 12296 MachineFunction *F = BB->getParent(); 12297 12298 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12299 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12300 12301 // Get a register mask for the lowered call. 12302 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12303 // proper register mask. 12304 const uint32_t *RegMask = 12305 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12306 if (Subtarget->is64Bit()) { 12307 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12308 TII->get(X86::MOV64rm), X86::RDI) 12309 .addReg(X86::RIP) 12310 .addImm(0).addReg(0) 12311 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12312 MI->getOperand(3).getTargetFlags()) 12313 .addReg(0); 12314 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12315 addDirectMem(MIB, X86::RDI); 12316 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12317 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12318 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12319 TII->get(X86::MOV32rm), X86::EAX) 12320 .addReg(0) 12321 .addImm(0).addReg(0) 12322 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12323 MI->getOperand(3).getTargetFlags()) 12324 .addReg(0); 12325 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12326 addDirectMem(MIB, X86::EAX); 12327 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12328 } else { 12329 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12330 TII->get(X86::MOV32rm), X86::EAX) 12331 .addReg(TII->getGlobalBaseReg(F)) 12332 .addImm(0).addReg(0) 12333 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12334 MI->getOperand(3).getTargetFlags()) 12335 .addReg(0); 12336 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12337 addDirectMem(MIB, X86::EAX); 12338 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12339 } 12340 12341 MI->eraseFromParent(); // The pseudo instruction is gone now. 12342 return BB; 12343} 12344 12345MachineBasicBlock * 12346X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12347 MachineBasicBlock *BB) const { 12348 switch (MI->getOpcode()) { 12349 default: llvm_unreachable("Unexpected instr type to insert"); 12350 case X86::TAILJMPd64: 12351 case X86::TAILJMPr64: 12352 case X86::TAILJMPm64: 12353 llvm_unreachable("TAILJMP64 would not be touched here."); 12354 case X86::TCRETURNdi64: 12355 case X86::TCRETURNri64: 12356 case X86::TCRETURNmi64: 12357 return BB; 12358 case X86::WIN_ALLOCA: 12359 return EmitLoweredWinAlloca(MI, BB); 12360 case X86::SEG_ALLOCA_32: 12361 return EmitLoweredSegAlloca(MI, BB, false); 12362 case X86::SEG_ALLOCA_64: 12363 return EmitLoweredSegAlloca(MI, BB, true); 12364 case X86::TLSCall_32: 12365 case X86::TLSCall_64: 12366 return EmitLoweredTLSCall(MI, BB); 12367 case X86::CMOV_GR8: 12368 case X86::CMOV_FR32: 12369 case X86::CMOV_FR64: 12370 case X86::CMOV_V4F32: 12371 case X86::CMOV_V2F64: 12372 case X86::CMOV_V2I64: 12373 case X86::CMOV_V8F32: 12374 case X86::CMOV_V4F64: 12375 case X86::CMOV_V4I64: 12376 case X86::CMOV_GR16: 12377 case X86::CMOV_GR32: 12378 case X86::CMOV_RFP32: 12379 case X86::CMOV_RFP64: 12380 case X86::CMOV_RFP80: 12381 return EmitLoweredSelect(MI, BB); 12382 12383 case X86::FP32_TO_INT16_IN_MEM: 12384 case X86::FP32_TO_INT32_IN_MEM: 12385 case X86::FP32_TO_INT64_IN_MEM: 12386 case X86::FP64_TO_INT16_IN_MEM: 12387 case X86::FP64_TO_INT32_IN_MEM: 12388 case X86::FP64_TO_INT64_IN_MEM: 12389 case X86::FP80_TO_INT16_IN_MEM: 12390 case X86::FP80_TO_INT32_IN_MEM: 12391 case X86::FP80_TO_INT64_IN_MEM: { 12392 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12393 DebugLoc DL = MI->getDebugLoc(); 12394 12395 // Change the floating point control register to use "round towards zero" 12396 // mode when truncating to an integer value. 12397 MachineFunction *F = BB->getParent(); 12398 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12399 addFrameReference(BuildMI(*BB, MI, DL, 12400 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12401 12402 // Load the old value of the high byte of the control word... 12403 unsigned OldCW = 12404 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12405 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12406 CWFrameIdx); 12407 12408 // Set the high part to be round to zero... 12409 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12410 .addImm(0xC7F); 12411 12412 // Reload the modified control word now... 12413 addFrameReference(BuildMI(*BB, MI, DL, 12414 TII->get(X86::FLDCW16m)), CWFrameIdx); 12415 12416 // Restore the memory image of control word to original value 12417 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12418 .addReg(OldCW); 12419 12420 // Get the X86 opcode to use. 12421 unsigned Opc; 12422 switch (MI->getOpcode()) { 12423 default: llvm_unreachable("illegal opcode!"); 12424 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12425 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12426 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12427 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12428 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12429 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12430 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12431 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12432 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12433 } 12434 12435 X86AddressMode AM; 12436 MachineOperand &Op = MI->getOperand(0); 12437 if (Op.isReg()) { 12438 AM.BaseType = X86AddressMode::RegBase; 12439 AM.Base.Reg = Op.getReg(); 12440 } else { 12441 AM.BaseType = X86AddressMode::FrameIndexBase; 12442 AM.Base.FrameIndex = Op.getIndex(); 12443 } 12444 Op = MI->getOperand(1); 12445 if (Op.isImm()) 12446 AM.Scale = Op.getImm(); 12447 Op = MI->getOperand(2); 12448 if (Op.isImm()) 12449 AM.IndexReg = Op.getImm(); 12450 Op = MI->getOperand(3); 12451 if (Op.isGlobal()) { 12452 AM.GV = Op.getGlobal(); 12453 } else { 12454 AM.Disp = Op.getImm(); 12455 } 12456 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12457 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12458 12459 // Reload the original control word now. 12460 addFrameReference(BuildMI(*BB, MI, DL, 12461 TII->get(X86::FLDCW16m)), CWFrameIdx); 12462 12463 MI->eraseFromParent(); // The pseudo instruction is gone now. 12464 return BB; 12465 } 12466 // String/text processing lowering. 12467 case X86::PCMPISTRM128REG: 12468 case X86::VPCMPISTRM128REG: 12469 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12470 case X86::PCMPISTRM128MEM: 12471 case X86::VPCMPISTRM128MEM: 12472 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12473 case X86::PCMPESTRM128REG: 12474 case X86::VPCMPESTRM128REG: 12475 return EmitPCMP(MI, BB, 5, false /* in mem */); 12476 case X86::PCMPESTRM128MEM: 12477 case X86::VPCMPESTRM128MEM: 12478 return EmitPCMP(MI, BB, 5, true /* in mem */); 12479 12480 // Thread synchronization. 12481 case X86::MONITOR: 12482 return EmitMonitor(MI, BB); 12483 case X86::MWAIT: 12484 return EmitMwait(MI, BB); 12485 12486 // Atomic Lowering. 12487 case X86::ATOMAND32: 12488 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12489 X86::AND32ri, X86::MOV32rm, 12490 X86::LCMPXCHG32, 12491 X86::NOT32r, X86::EAX, 12492 X86::GR32RegisterClass); 12493 case X86::ATOMOR32: 12494 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12495 X86::OR32ri, X86::MOV32rm, 12496 X86::LCMPXCHG32, 12497 X86::NOT32r, X86::EAX, 12498 X86::GR32RegisterClass); 12499 case X86::ATOMXOR32: 12500 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12501 X86::XOR32ri, X86::MOV32rm, 12502 X86::LCMPXCHG32, 12503 X86::NOT32r, X86::EAX, 12504 X86::GR32RegisterClass); 12505 case X86::ATOMNAND32: 12506 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12507 X86::AND32ri, X86::MOV32rm, 12508 X86::LCMPXCHG32, 12509 X86::NOT32r, X86::EAX, 12510 X86::GR32RegisterClass, true); 12511 case X86::ATOMMIN32: 12512 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12513 case X86::ATOMMAX32: 12514 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12515 case X86::ATOMUMIN32: 12516 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12517 case X86::ATOMUMAX32: 12518 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12519 12520 case X86::ATOMAND16: 12521 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12522 X86::AND16ri, X86::MOV16rm, 12523 X86::LCMPXCHG16, 12524 X86::NOT16r, X86::AX, 12525 X86::GR16RegisterClass); 12526 case X86::ATOMOR16: 12527 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12528 X86::OR16ri, X86::MOV16rm, 12529 X86::LCMPXCHG16, 12530 X86::NOT16r, X86::AX, 12531 X86::GR16RegisterClass); 12532 case X86::ATOMXOR16: 12533 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12534 X86::XOR16ri, X86::MOV16rm, 12535 X86::LCMPXCHG16, 12536 X86::NOT16r, X86::AX, 12537 X86::GR16RegisterClass); 12538 case X86::ATOMNAND16: 12539 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12540 X86::AND16ri, X86::MOV16rm, 12541 X86::LCMPXCHG16, 12542 X86::NOT16r, X86::AX, 12543 X86::GR16RegisterClass, true); 12544 case X86::ATOMMIN16: 12545 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12546 case X86::ATOMMAX16: 12547 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12548 case X86::ATOMUMIN16: 12549 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12550 case X86::ATOMUMAX16: 12551 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12552 12553 case X86::ATOMAND8: 12554 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12555 X86::AND8ri, X86::MOV8rm, 12556 X86::LCMPXCHG8, 12557 X86::NOT8r, X86::AL, 12558 X86::GR8RegisterClass); 12559 case X86::ATOMOR8: 12560 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12561 X86::OR8ri, X86::MOV8rm, 12562 X86::LCMPXCHG8, 12563 X86::NOT8r, X86::AL, 12564 X86::GR8RegisterClass); 12565 case X86::ATOMXOR8: 12566 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12567 X86::XOR8ri, X86::MOV8rm, 12568 X86::LCMPXCHG8, 12569 X86::NOT8r, X86::AL, 12570 X86::GR8RegisterClass); 12571 case X86::ATOMNAND8: 12572 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12573 X86::AND8ri, X86::MOV8rm, 12574 X86::LCMPXCHG8, 12575 X86::NOT8r, X86::AL, 12576 X86::GR8RegisterClass, true); 12577 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12578 // This group is for 64-bit host. 12579 case X86::ATOMAND64: 12580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12581 X86::AND64ri32, X86::MOV64rm, 12582 X86::LCMPXCHG64, 12583 X86::NOT64r, X86::RAX, 12584 X86::GR64RegisterClass); 12585 case X86::ATOMOR64: 12586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12587 X86::OR64ri32, X86::MOV64rm, 12588 X86::LCMPXCHG64, 12589 X86::NOT64r, X86::RAX, 12590 X86::GR64RegisterClass); 12591 case X86::ATOMXOR64: 12592 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12593 X86::XOR64ri32, X86::MOV64rm, 12594 X86::LCMPXCHG64, 12595 X86::NOT64r, X86::RAX, 12596 X86::GR64RegisterClass); 12597 case X86::ATOMNAND64: 12598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12599 X86::AND64ri32, X86::MOV64rm, 12600 X86::LCMPXCHG64, 12601 X86::NOT64r, X86::RAX, 12602 X86::GR64RegisterClass, true); 12603 case X86::ATOMMIN64: 12604 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12605 case X86::ATOMMAX64: 12606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12607 case X86::ATOMUMIN64: 12608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12609 case X86::ATOMUMAX64: 12610 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12611 12612 // This group does 64-bit operations on a 32-bit host. 12613 case X86::ATOMAND6432: 12614 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12615 X86::AND32rr, X86::AND32rr, 12616 X86::AND32ri, X86::AND32ri, 12617 false); 12618 case X86::ATOMOR6432: 12619 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12620 X86::OR32rr, X86::OR32rr, 12621 X86::OR32ri, X86::OR32ri, 12622 false); 12623 case X86::ATOMXOR6432: 12624 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12625 X86::XOR32rr, X86::XOR32rr, 12626 X86::XOR32ri, X86::XOR32ri, 12627 false); 12628 case X86::ATOMNAND6432: 12629 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12630 X86::AND32rr, X86::AND32rr, 12631 X86::AND32ri, X86::AND32ri, 12632 true); 12633 case X86::ATOMADD6432: 12634 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12635 X86::ADD32rr, X86::ADC32rr, 12636 X86::ADD32ri, X86::ADC32ri, 12637 false); 12638 case X86::ATOMSUB6432: 12639 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12640 X86::SUB32rr, X86::SBB32rr, 12641 X86::SUB32ri, X86::SBB32ri, 12642 false); 12643 case X86::ATOMSWAP6432: 12644 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12645 X86::MOV32rr, X86::MOV32rr, 12646 X86::MOV32ri, X86::MOV32ri, 12647 false); 12648 case X86::VASTART_SAVE_XMM_REGS: 12649 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12650 12651 case X86::VAARG_64: 12652 return EmitVAARG64WithCustomInserter(MI, BB); 12653 } 12654} 12655 12656//===----------------------------------------------------------------------===// 12657// X86 Optimization Hooks 12658//===----------------------------------------------------------------------===// 12659 12660void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12661 const APInt &Mask, 12662 APInt &KnownZero, 12663 APInt &KnownOne, 12664 const SelectionDAG &DAG, 12665 unsigned Depth) const { 12666 unsigned Opc = Op.getOpcode(); 12667 assert((Opc >= ISD::BUILTIN_OP_END || 12668 Opc == ISD::INTRINSIC_WO_CHAIN || 12669 Opc == ISD::INTRINSIC_W_CHAIN || 12670 Opc == ISD::INTRINSIC_VOID) && 12671 "Should use MaskedValueIsZero if you don't know whether Op" 12672 " is a target node!"); 12673 12674 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12675 switch (Opc) { 12676 default: break; 12677 case X86ISD::ADD: 12678 case X86ISD::SUB: 12679 case X86ISD::ADC: 12680 case X86ISD::SBB: 12681 case X86ISD::SMUL: 12682 case X86ISD::UMUL: 12683 case X86ISD::INC: 12684 case X86ISD::DEC: 12685 case X86ISD::OR: 12686 case X86ISD::XOR: 12687 case X86ISD::AND: 12688 // These nodes' second result is a boolean. 12689 if (Op.getResNo() == 0) 12690 break; 12691 // Fallthrough 12692 case X86ISD::SETCC: 12693 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12694 Mask.getBitWidth() - 1); 12695 break; 12696 case ISD::INTRINSIC_WO_CHAIN: { 12697 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12698 unsigned NumLoBits = 0; 12699 switch (IntId) { 12700 default: break; 12701 case Intrinsic::x86_sse_movmsk_ps: 12702 case Intrinsic::x86_avx_movmsk_ps_256: 12703 case Intrinsic::x86_sse2_movmsk_pd: 12704 case Intrinsic::x86_avx_movmsk_pd_256: 12705 case Intrinsic::x86_mmx_pmovmskb: 12706 case Intrinsic::x86_sse2_pmovmskb_128: 12707 case Intrinsic::x86_avx2_pmovmskb: { 12708 // High bits of movmskp{s|d}, pmovmskb are known zero. 12709 switch (IntId) { 12710 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12711 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12712 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12713 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12714 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12715 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12716 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12717 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12718 } 12719 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12720 Mask.getBitWidth() - NumLoBits); 12721 break; 12722 } 12723 } 12724 break; 12725 } 12726 } 12727} 12728 12729unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12730 unsigned Depth) const { 12731 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12732 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12733 return Op.getValueType().getScalarType().getSizeInBits(); 12734 12735 // Fallback case. 12736 return 1; 12737} 12738 12739/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12740/// node is a GlobalAddress + offset. 12741bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12742 const GlobalValue* &GA, 12743 int64_t &Offset) const { 12744 if (N->getOpcode() == X86ISD::Wrapper) { 12745 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12746 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12747 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12748 return true; 12749 } 12750 } 12751 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12752} 12753 12754/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12755/// same as extracting the high 128-bit part of 256-bit vector and then 12756/// inserting the result into the low part of a new 256-bit vector 12757static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12758 EVT VT = SVOp->getValueType(0); 12759 int NumElems = VT.getVectorNumElements(); 12760 12761 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12762 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12763 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12764 SVOp->getMaskElt(j) >= 0) 12765 return false; 12766 12767 return true; 12768} 12769 12770/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12771/// same as extracting the low 128-bit part of 256-bit vector and then 12772/// inserting the result into the high part of a new 256-bit vector 12773static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12774 EVT VT = SVOp->getValueType(0); 12775 int NumElems = VT.getVectorNumElements(); 12776 12777 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12778 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12779 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12780 SVOp->getMaskElt(j) >= 0) 12781 return false; 12782 12783 return true; 12784} 12785 12786/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12787static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12788 TargetLowering::DAGCombinerInfo &DCI, 12789 const X86Subtarget* Subtarget) { 12790 DebugLoc dl = N->getDebugLoc(); 12791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12792 SDValue V1 = SVOp->getOperand(0); 12793 SDValue V2 = SVOp->getOperand(1); 12794 EVT VT = SVOp->getValueType(0); 12795 int NumElems = VT.getVectorNumElements(); 12796 12797 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12798 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12799 // 12800 // 0,0,0,... 12801 // | 12802 // V UNDEF BUILD_VECTOR UNDEF 12803 // \ / \ / 12804 // CONCAT_VECTOR CONCAT_VECTOR 12805 // \ / 12806 // \ / 12807 // RESULT: V + zero extended 12808 // 12809 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12810 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12811 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12812 return SDValue(); 12813 12814 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12815 return SDValue(); 12816 12817 // To match the shuffle mask, the first half of the mask should 12818 // be exactly the first vector, and all the rest a splat with the 12819 // first element of the second one. 12820 for (int i = 0; i < NumElems/2; ++i) 12821 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12822 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12823 return SDValue(); 12824 12825 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12826 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12827 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12828 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12829 SDValue ResNode = 12830 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12831 Ld->getMemoryVT(), 12832 Ld->getPointerInfo(), 12833 Ld->getAlignment(), 12834 false/*isVolatile*/, true/*ReadMem*/, 12835 false/*WriteMem*/); 12836 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12837 } 12838 12839 // Emit a zeroed vector and insert the desired subvector on its 12840 // first half. 12841 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12842 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12843 DAG.getConstant(0, MVT::i32), DAG, dl); 12844 return DCI.CombineTo(N, InsV); 12845 } 12846 12847 //===--------------------------------------------------------------------===// 12848 // Combine some shuffles into subvector extracts and inserts: 12849 // 12850 12851 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12852 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12853 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12854 DAG, dl); 12855 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12856 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12857 return DCI.CombineTo(N, InsV); 12858 } 12859 12860 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12861 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12862 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12863 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12864 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12865 return DCI.CombineTo(N, InsV); 12866 } 12867 12868 return SDValue(); 12869} 12870 12871/// PerformShuffleCombine - Performs several different shuffle combines. 12872static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12873 TargetLowering::DAGCombinerInfo &DCI, 12874 const X86Subtarget *Subtarget) { 12875 DebugLoc dl = N->getDebugLoc(); 12876 EVT VT = N->getValueType(0); 12877 12878 // Don't create instructions with illegal types after legalize types has run. 12879 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12880 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12881 return SDValue(); 12882 12883 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12884 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12885 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12886 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 12887 12888 // Only handle 128 wide vector from here on. 12889 if (VT.getSizeInBits() != 128) 12890 return SDValue(); 12891 12892 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12893 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12894 // consecutive, non-overlapping, and in the right order. 12895 SmallVector<SDValue, 16> Elts; 12896 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12897 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12898 12899 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12900} 12901 12902 12903/// PerformTruncateCombine - Converts truncate operation to 12904/// a sequence of vector shuffle operations. 12905/// It is possible when we truncate 256-bit vector to 128-bit vector 12906 12907SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 12908 DAGCombinerInfo &DCI) const { 12909 if (!DCI.isBeforeLegalizeOps()) 12910 return SDValue(); 12911 12912 if (!Subtarget->hasAVX()) return SDValue(); 12913 12914 EVT VT = N->getValueType(0); 12915 SDValue Op = N->getOperand(0); 12916 EVT OpVT = Op.getValueType(); 12917 DebugLoc dl = N->getDebugLoc(); 12918 12919 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 12920 12921 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12922 DAG.getIntPtrConstant(0)); 12923 12924 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12925 DAG.getIntPtrConstant(2)); 12926 12927 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12928 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12929 12930 // PSHUFD 12931 int ShufMask1[] = {0, 2, 0, 0}; 12932 12933 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), 12934 ShufMask1); 12935 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), 12936 ShufMask1); 12937 12938 // MOVLHPS 12939 int ShufMask2[] = {0, 1, 4, 5}; 12940 12941 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 12942 } 12943 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 12944 12945 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12946 DAG.getIntPtrConstant(0)); 12947 12948 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12949 DAG.getIntPtrConstant(4)); 12950 12951 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 12952 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 12953 12954 // PSHUFB 12955 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 12956 -1, -1, -1, -1, -1, -1, -1, -1}; 12957 12958 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, 12959 DAG.getUNDEF(MVT::v16i8), 12960 ShufMask1); 12961 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, 12962 DAG.getUNDEF(MVT::v16i8), 12963 ShufMask1); 12964 12965 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12966 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12967 12968 // MOVLHPS 12969 int ShufMask2[] = {0, 1, 4, 5}; 12970 12971 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 12972 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 12973 } 12974 12975 return SDValue(); 12976} 12977 12978/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12979/// generation and convert it from being a bunch of shuffles and extracts 12980/// to a simple store and scalar loads to extract the elements. 12981static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12982 const TargetLowering &TLI) { 12983 SDValue InputVector = N->getOperand(0); 12984 12985 // Only operate on vectors of 4 elements, where the alternative shuffling 12986 // gets to be more expensive. 12987 if (InputVector.getValueType() != MVT::v4i32) 12988 return SDValue(); 12989 12990 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12991 // single use which is a sign-extend or zero-extend, and all elements are 12992 // used. 12993 SmallVector<SDNode *, 4> Uses; 12994 unsigned ExtractedElements = 0; 12995 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12996 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12997 if (UI.getUse().getResNo() != InputVector.getResNo()) 12998 return SDValue(); 12999 13000 SDNode *Extract = *UI; 13001 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13002 return SDValue(); 13003 13004 if (Extract->getValueType(0) != MVT::i32) 13005 return SDValue(); 13006 if (!Extract->hasOneUse()) 13007 return SDValue(); 13008 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13009 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13010 return SDValue(); 13011 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13012 return SDValue(); 13013 13014 // Record which element was extracted. 13015 ExtractedElements |= 13016 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13017 13018 Uses.push_back(Extract); 13019 } 13020 13021 // If not all the elements were used, this may not be worthwhile. 13022 if (ExtractedElements != 15) 13023 return SDValue(); 13024 13025 // Ok, we've now decided to do the transformation. 13026 DebugLoc dl = InputVector.getDebugLoc(); 13027 13028 // Store the value to a temporary stack slot. 13029 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13030 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13031 MachinePointerInfo(), false, false, 0); 13032 13033 // Replace each use (extract) with a load of the appropriate element. 13034 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13035 UE = Uses.end(); UI != UE; ++UI) { 13036 SDNode *Extract = *UI; 13037 13038 // cOMpute the element's address. 13039 SDValue Idx = Extract->getOperand(1); 13040 unsigned EltSize = 13041 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13042 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13043 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13044 13045 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13046 StackPtr, OffsetVal); 13047 13048 // Load the scalar. 13049 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13050 ScalarAddr, MachinePointerInfo(), 13051 false, false, false, 0); 13052 13053 // Replace the exact with the load. 13054 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13055 } 13056 13057 // The replacement was made in place; don't return anything. 13058 return SDValue(); 13059} 13060 13061/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13062/// nodes. 13063static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13064 TargetLowering::DAGCombinerInfo &DCI, 13065 const X86Subtarget *Subtarget) { 13066 DebugLoc DL = N->getDebugLoc(); 13067 SDValue Cond = N->getOperand(0); 13068 // Get the LHS/RHS of the select. 13069 SDValue LHS = N->getOperand(1); 13070 SDValue RHS = N->getOperand(2); 13071 EVT VT = LHS.getValueType(); 13072 13073 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13074 // instructions match the semantics of the common C idiom x<y?x:y but not 13075 // x<=y?x:y, because of how they handle negative zero (which can be 13076 // ignored in unsafe-math mode). 13077 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13078 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13079 (Subtarget->hasSSE2() || 13080 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13081 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13082 13083 unsigned Opcode = 0; 13084 // Check for x CC y ? x : y. 13085 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13086 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13087 switch (CC) { 13088 default: break; 13089 case ISD::SETULT: 13090 // Converting this to a min would handle NaNs incorrectly, and swapping 13091 // the operands would cause it to handle comparisons between positive 13092 // and negative zero incorrectly. 13093 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13094 if (!DAG.getTarget().Options.UnsafeFPMath && 13095 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13096 break; 13097 std::swap(LHS, RHS); 13098 } 13099 Opcode = X86ISD::FMIN; 13100 break; 13101 case ISD::SETOLE: 13102 // Converting this to a min would handle comparisons between positive 13103 // and negative zero incorrectly. 13104 if (!DAG.getTarget().Options.UnsafeFPMath && 13105 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13106 break; 13107 Opcode = X86ISD::FMIN; 13108 break; 13109 case ISD::SETULE: 13110 // Converting this to a min would handle both negative zeros and NaNs 13111 // incorrectly, but we can swap the operands to fix both. 13112 std::swap(LHS, RHS); 13113 case ISD::SETOLT: 13114 case ISD::SETLT: 13115 case ISD::SETLE: 13116 Opcode = X86ISD::FMIN; 13117 break; 13118 13119 case ISD::SETOGE: 13120 // Converting this to a max would handle comparisons between positive 13121 // and negative zero incorrectly. 13122 if (!DAG.getTarget().Options.UnsafeFPMath && 13123 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13124 break; 13125 Opcode = X86ISD::FMAX; 13126 break; 13127 case ISD::SETUGT: 13128 // Converting this to a max would handle NaNs incorrectly, and swapping 13129 // the operands would cause it to handle comparisons between positive 13130 // and negative zero incorrectly. 13131 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13132 if (!DAG.getTarget().Options.UnsafeFPMath && 13133 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13134 break; 13135 std::swap(LHS, RHS); 13136 } 13137 Opcode = X86ISD::FMAX; 13138 break; 13139 case ISD::SETUGE: 13140 // Converting this to a max would handle both negative zeros and NaNs 13141 // incorrectly, but we can swap the operands to fix both. 13142 std::swap(LHS, RHS); 13143 case ISD::SETOGT: 13144 case ISD::SETGT: 13145 case ISD::SETGE: 13146 Opcode = X86ISD::FMAX; 13147 break; 13148 } 13149 // Check for x CC y ? y : x -- a min/max with reversed arms. 13150 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13151 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13152 switch (CC) { 13153 default: break; 13154 case ISD::SETOGE: 13155 // Converting this to a min would handle comparisons between positive 13156 // and negative zero incorrectly, and swapping the operands would 13157 // cause it to handle NaNs incorrectly. 13158 if (!DAG.getTarget().Options.UnsafeFPMath && 13159 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13160 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13161 break; 13162 std::swap(LHS, RHS); 13163 } 13164 Opcode = X86ISD::FMIN; 13165 break; 13166 case ISD::SETUGT: 13167 // Converting this to a min would handle NaNs incorrectly. 13168 if (!DAG.getTarget().Options.UnsafeFPMath && 13169 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13170 break; 13171 Opcode = X86ISD::FMIN; 13172 break; 13173 case ISD::SETUGE: 13174 // Converting this to a min would handle both negative zeros and NaNs 13175 // incorrectly, but we can swap the operands to fix both. 13176 std::swap(LHS, RHS); 13177 case ISD::SETOGT: 13178 case ISD::SETGT: 13179 case ISD::SETGE: 13180 Opcode = X86ISD::FMIN; 13181 break; 13182 13183 case ISD::SETULT: 13184 // Converting this to a max would handle NaNs incorrectly. 13185 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13186 break; 13187 Opcode = X86ISD::FMAX; 13188 break; 13189 case ISD::SETOLE: 13190 // Converting this to a max would handle comparisons between positive 13191 // and negative zero incorrectly, and swapping the operands would 13192 // cause it to handle NaNs incorrectly. 13193 if (!DAG.getTarget().Options.UnsafeFPMath && 13194 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13195 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13196 break; 13197 std::swap(LHS, RHS); 13198 } 13199 Opcode = X86ISD::FMAX; 13200 break; 13201 case ISD::SETULE: 13202 // Converting this to a max would handle both negative zeros and NaNs 13203 // incorrectly, but we can swap the operands to fix both. 13204 std::swap(LHS, RHS); 13205 case ISD::SETOLT: 13206 case ISD::SETLT: 13207 case ISD::SETLE: 13208 Opcode = X86ISD::FMAX; 13209 break; 13210 } 13211 } 13212 13213 if (Opcode) 13214 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13215 } 13216 13217 // If this is a select between two integer constants, try to do some 13218 // optimizations. 13219 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13220 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13221 // Don't do this for crazy integer types. 13222 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13223 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13224 // so that TrueC (the true value) is larger than FalseC. 13225 bool NeedsCondInvert = false; 13226 13227 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13228 // Efficiently invertible. 13229 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13230 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13231 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13232 NeedsCondInvert = true; 13233 std::swap(TrueC, FalseC); 13234 } 13235 13236 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13237 if (FalseC->getAPIntValue() == 0 && 13238 TrueC->getAPIntValue().isPowerOf2()) { 13239 if (NeedsCondInvert) // Invert the condition if needed. 13240 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13241 DAG.getConstant(1, Cond.getValueType())); 13242 13243 // Zero extend the condition if needed. 13244 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13245 13246 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13247 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13248 DAG.getConstant(ShAmt, MVT::i8)); 13249 } 13250 13251 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13252 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13253 if (NeedsCondInvert) // Invert the condition if needed. 13254 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13255 DAG.getConstant(1, Cond.getValueType())); 13256 13257 // Zero extend the condition if needed. 13258 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13259 FalseC->getValueType(0), Cond); 13260 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13261 SDValue(FalseC, 0)); 13262 } 13263 13264 // Optimize cases that will turn into an LEA instruction. This requires 13265 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13266 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13267 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13268 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13269 13270 bool isFastMultiplier = false; 13271 if (Diff < 10) { 13272 switch ((unsigned char)Diff) { 13273 default: break; 13274 case 1: // result = add base, cond 13275 case 2: // result = lea base( , cond*2) 13276 case 3: // result = lea base(cond, cond*2) 13277 case 4: // result = lea base( , cond*4) 13278 case 5: // result = lea base(cond, cond*4) 13279 case 8: // result = lea base( , cond*8) 13280 case 9: // result = lea base(cond, cond*8) 13281 isFastMultiplier = true; 13282 break; 13283 } 13284 } 13285 13286 if (isFastMultiplier) { 13287 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13288 if (NeedsCondInvert) // Invert the condition if needed. 13289 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13290 DAG.getConstant(1, Cond.getValueType())); 13291 13292 // Zero extend the condition if needed. 13293 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13294 Cond); 13295 // Scale the condition by the difference. 13296 if (Diff != 1) 13297 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13298 DAG.getConstant(Diff, Cond.getValueType())); 13299 13300 // Add the base if non-zero. 13301 if (FalseC->getAPIntValue() != 0) 13302 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13303 SDValue(FalseC, 0)); 13304 return Cond; 13305 } 13306 } 13307 } 13308 } 13309 13310 // Canonicalize max and min: 13311 // (x > y) ? x : y -> (x >= y) ? x : y 13312 // (x < y) ? x : y -> (x <= y) ? x : y 13313 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13314 // the need for an extra compare 13315 // against zero. e.g. 13316 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13317 // subl %esi, %edi 13318 // testl %edi, %edi 13319 // movl $0, %eax 13320 // cmovgl %edi, %eax 13321 // => 13322 // xorl %eax, %eax 13323 // subl %esi, $edi 13324 // cmovsl %eax, %edi 13325 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13326 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13327 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13328 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13329 switch (CC) { 13330 default: break; 13331 case ISD::SETLT: 13332 case ISD::SETGT: { 13333 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13334 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13335 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13336 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13337 } 13338 } 13339 } 13340 13341 // If we know that this node is legal then we know that it is going to be 13342 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13343 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13344 // to simplify previous instructions. 13345 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13346 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13347 !DCI.isBeforeLegalize() && 13348 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13349 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13350 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13351 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13352 13353 APInt KnownZero, KnownOne; 13354 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13355 DCI.isBeforeLegalizeOps()); 13356 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13357 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13358 DCI.CommitTargetLoweringOpt(TLO); 13359 } 13360 13361 return SDValue(); 13362} 13363 13364/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13365static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13366 TargetLowering::DAGCombinerInfo &DCI) { 13367 DebugLoc DL = N->getDebugLoc(); 13368 13369 // If the flag operand isn't dead, don't touch this CMOV. 13370 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13371 return SDValue(); 13372 13373 SDValue FalseOp = N->getOperand(0); 13374 SDValue TrueOp = N->getOperand(1); 13375 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13376 SDValue Cond = N->getOperand(3); 13377 if (CC == X86::COND_E || CC == X86::COND_NE) { 13378 switch (Cond.getOpcode()) { 13379 default: break; 13380 case X86ISD::BSR: 13381 case X86ISD::BSF: 13382 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13383 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13384 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13385 } 13386 } 13387 13388 // If this is a select between two integer constants, try to do some 13389 // optimizations. Note that the operands are ordered the opposite of SELECT 13390 // operands. 13391 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13392 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13393 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13394 // larger than FalseC (the false value). 13395 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13396 CC = X86::GetOppositeBranchCondition(CC); 13397 std::swap(TrueC, FalseC); 13398 } 13399 13400 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13401 // This is efficient for any integer data type (including i8/i16) and 13402 // shift amount. 13403 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13404 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13405 DAG.getConstant(CC, MVT::i8), Cond); 13406 13407 // Zero extend the condition if needed. 13408 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13409 13410 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13411 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13412 DAG.getConstant(ShAmt, MVT::i8)); 13413 if (N->getNumValues() == 2) // Dead flag value? 13414 return DCI.CombineTo(N, Cond, SDValue()); 13415 return Cond; 13416 } 13417 13418 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13419 // for any integer data type, including i8/i16. 13420 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13421 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13422 DAG.getConstant(CC, MVT::i8), Cond); 13423 13424 // Zero extend the condition if needed. 13425 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13426 FalseC->getValueType(0), Cond); 13427 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13428 SDValue(FalseC, 0)); 13429 13430 if (N->getNumValues() == 2) // Dead flag value? 13431 return DCI.CombineTo(N, Cond, SDValue()); 13432 return Cond; 13433 } 13434 13435 // Optimize cases that will turn into an LEA instruction. This requires 13436 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13437 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13438 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13439 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13440 13441 bool isFastMultiplier = false; 13442 if (Diff < 10) { 13443 switch ((unsigned char)Diff) { 13444 default: break; 13445 case 1: // result = add base, cond 13446 case 2: // result = lea base( , cond*2) 13447 case 3: // result = lea base(cond, cond*2) 13448 case 4: // result = lea base( , cond*4) 13449 case 5: // result = lea base(cond, cond*4) 13450 case 8: // result = lea base( , cond*8) 13451 case 9: // result = lea base(cond, cond*8) 13452 isFastMultiplier = true; 13453 break; 13454 } 13455 } 13456 13457 if (isFastMultiplier) { 13458 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13459 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13460 DAG.getConstant(CC, MVT::i8), Cond); 13461 // Zero extend the condition if needed. 13462 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13463 Cond); 13464 // Scale the condition by the difference. 13465 if (Diff != 1) 13466 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13467 DAG.getConstant(Diff, Cond.getValueType())); 13468 13469 // Add the base if non-zero. 13470 if (FalseC->getAPIntValue() != 0) 13471 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13472 SDValue(FalseC, 0)); 13473 if (N->getNumValues() == 2) // Dead flag value? 13474 return DCI.CombineTo(N, Cond, SDValue()); 13475 return Cond; 13476 } 13477 } 13478 } 13479 } 13480 return SDValue(); 13481} 13482 13483 13484/// PerformMulCombine - Optimize a single multiply with constant into two 13485/// in order to implement it with two cheaper instructions, e.g. 13486/// LEA + SHL, LEA + LEA. 13487static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13488 TargetLowering::DAGCombinerInfo &DCI) { 13489 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13490 return SDValue(); 13491 13492 EVT VT = N->getValueType(0); 13493 if (VT != MVT::i64) 13494 return SDValue(); 13495 13496 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13497 if (!C) 13498 return SDValue(); 13499 uint64_t MulAmt = C->getZExtValue(); 13500 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13501 return SDValue(); 13502 13503 uint64_t MulAmt1 = 0; 13504 uint64_t MulAmt2 = 0; 13505 if ((MulAmt % 9) == 0) { 13506 MulAmt1 = 9; 13507 MulAmt2 = MulAmt / 9; 13508 } else if ((MulAmt % 5) == 0) { 13509 MulAmt1 = 5; 13510 MulAmt2 = MulAmt / 5; 13511 } else if ((MulAmt % 3) == 0) { 13512 MulAmt1 = 3; 13513 MulAmt2 = MulAmt / 3; 13514 } 13515 if (MulAmt2 && 13516 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13517 DebugLoc DL = N->getDebugLoc(); 13518 13519 if (isPowerOf2_64(MulAmt2) && 13520 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13521 // If second multiplifer is pow2, issue it first. We want the multiply by 13522 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13523 // is an add. 13524 std::swap(MulAmt1, MulAmt2); 13525 13526 SDValue NewMul; 13527 if (isPowerOf2_64(MulAmt1)) 13528 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13529 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13530 else 13531 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13532 DAG.getConstant(MulAmt1, VT)); 13533 13534 if (isPowerOf2_64(MulAmt2)) 13535 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13536 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13537 else 13538 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13539 DAG.getConstant(MulAmt2, VT)); 13540 13541 // Do not add new nodes to DAG combiner worklist. 13542 DCI.CombineTo(N, NewMul, false); 13543 } 13544 return SDValue(); 13545} 13546 13547static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13548 SDValue N0 = N->getOperand(0); 13549 SDValue N1 = N->getOperand(1); 13550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13551 EVT VT = N0.getValueType(); 13552 13553 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13554 // since the result of setcc_c is all zero's or all ones. 13555 if (VT.isInteger() && !VT.isVector() && 13556 N1C && N0.getOpcode() == ISD::AND && 13557 N0.getOperand(1).getOpcode() == ISD::Constant) { 13558 SDValue N00 = N0.getOperand(0); 13559 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13560 ((N00.getOpcode() == ISD::ANY_EXTEND || 13561 N00.getOpcode() == ISD::ZERO_EXTEND) && 13562 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13563 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13564 APInt ShAmt = N1C->getAPIntValue(); 13565 Mask = Mask.shl(ShAmt); 13566 if (Mask != 0) 13567 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13568 N00, DAG.getConstant(Mask, VT)); 13569 } 13570 } 13571 13572 13573 // Hardware support for vector shifts is sparse which makes us scalarize the 13574 // vector operations in many cases. Also, on sandybridge ADD is faster than 13575 // shl. 13576 // (shl V, 1) -> add V,V 13577 if (isSplatVector(N1.getNode())) { 13578 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13579 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13580 // We shift all of the values by one. In many cases we do not have 13581 // hardware support for this operation. This is better expressed as an ADD 13582 // of two values. 13583 if (N1C && (1 == N1C->getZExtValue())) { 13584 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13585 } 13586 } 13587 13588 return SDValue(); 13589} 13590 13591/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13592/// when possible. 13593static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13594 TargetLowering::DAGCombinerInfo &DCI, 13595 const X86Subtarget *Subtarget) { 13596 EVT VT = N->getValueType(0); 13597 if (N->getOpcode() == ISD::SHL) { 13598 SDValue V = PerformSHLCombine(N, DAG); 13599 if (V.getNode()) return V; 13600 } 13601 13602 // On X86 with SSE2 support, we can transform this to a vector shift if 13603 // all elements are shifted by the same amount. We can't do this in legalize 13604 // because the a constant vector is typically transformed to a constant pool 13605 // so we have no knowledge of the shift amount. 13606 if (!Subtarget->hasSSE2()) 13607 return SDValue(); 13608 13609 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13610 (!Subtarget->hasAVX2() || 13611 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13612 return SDValue(); 13613 13614 SDValue ShAmtOp = N->getOperand(1); 13615 EVT EltVT = VT.getVectorElementType(); 13616 DebugLoc DL = N->getDebugLoc(); 13617 SDValue BaseShAmt = SDValue(); 13618 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13619 unsigned NumElts = VT.getVectorNumElements(); 13620 unsigned i = 0; 13621 for (; i != NumElts; ++i) { 13622 SDValue Arg = ShAmtOp.getOperand(i); 13623 if (Arg.getOpcode() == ISD::UNDEF) continue; 13624 BaseShAmt = Arg; 13625 break; 13626 } 13627 // Handle the case where the build_vector is all undef 13628 // FIXME: Should DAG allow this? 13629 if (i == NumElts) 13630 return SDValue(); 13631 13632 for (; i != NumElts; ++i) { 13633 SDValue Arg = ShAmtOp.getOperand(i); 13634 if (Arg.getOpcode() == ISD::UNDEF) continue; 13635 if (Arg != BaseShAmt) { 13636 return SDValue(); 13637 } 13638 } 13639 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13640 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13641 SDValue InVec = ShAmtOp.getOperand(0); 13642 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13643 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13644 unsigned i = 0; 13645 for (; i != NumElts; ++i) { 13646 SDValue Arg = InVec.getOperand(i); 13647 if (Arg.getOpcode() == ISD::UNDEF) continue; 13648 BaseShAmt = Arg; 13649 break; 13650 } 13651 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13653 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13654 if (C->getZExtValue() == SplatIdx) 13655 BaseShAmt = InVec.getOperand(1); 13656 } 13657 } 13658 if (BaseShAmt.getNode() == 0) { 13659 // Don't create instructions with illegal types after legalize 13660 // types has run. 13661 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13662 !DCI.isBeforeLegalize()) 13663 return SDValue(); 13664 13665 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13666 DAG.getIntPtrConstant(0)); 13667 } 13668 } else 13669 return SDValue(); 13670 13671 // The shift amount is an i32. 13672 if (EltVT.bitsGT(MVT::i32)) 13673 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13674 else if (EltVT.bitsLT(MVT::i32)) 13675 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13676 13677 // The shift amount is identical so we can do a vector shift. 13678 SDValue ValOp = N->getOperand(0); 13679 switch (N->getOpcode()) { 13680 default: 13681 llvm_unreachable("Unknown shift opcode!"); 13682 case ISD::SHL: 13683 switch (VT.getSimpleVT().SimpleTy) { 13684 default: return SDValue(); 13685 case MVT::v2i64: 13686 case MVT::v4i32: 13687 case MVT::v8i16: 13688 case MVT::v4i64: 13689 case MVT::v8i32: 13690 case MVT::v16i16: 13691 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13692 } 13693 case ISD::SRA: 13694 switch (VT.getSimpleVT().SimpleTy) { 13695 default: return SDValue(); 13696 case MVT::v4i32: 13697 case MVT::v8i16: 13698 case MVT::v8i32: 13699 case MVT::v16i16: 13700 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13701 } 13702 case ISD::SRL: 13703 switch (VT.getSimpleVT().SimpleTy) { 13704 default: return SDValue(); 13705 case MVT::v2i64: 13706 case MVT::v4i32: 13707 case MVT::v8i16: 13708 case MVT::v4i64: 13709 case MVT::v8i32: 13710 case MVT::v16i16: 13711 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13712 } 13713 } 13714} 13715 13716 13717// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13718// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13719// and friends. Likewise for OR -> CMPNEQSS. 13720static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13721 TargetLowering::DAGCombinerInfo &DCI, 13722 const X86Subtarget *Subtarget) { 13723 unsigned opcode; 13724 13725 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13726 // we're requiring SSE2 for both. 13727 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13728 SDValue N0 = N->getOperand(0); 13729 SDValue N1 = N->getOperand(1); 13730 SDValue CMP0 = N0->getOperand(1); 13731 SDValue CMP1 = N1->getOperand(1); 13732 DebugLoc DL = N->getDebugLoc(); 13733 13734 // The SETCCs should both refer to the same CMP. 13735 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13736 return SDValue(); 13737 13738 SDValue CMP00 = CMP0->getOperand(0); 13739 SDValue CMP01 = CMP0->getOperand(1); 13740 EVT VT = CMP00.getValueType(); 13741 13742 if (VT == MVT::f32 || VT == MVT::f64) { 13743 bool ExpectingFlags = false; 13744 // Check for any users that want flags: 13745 for (SDNode::use_iterator UI = N->use_begin(), 13746 UE = N->use_end(); 13747 !ExpectingFlags && UI != UE; ++UI) 13748 switch (UI->getOpcode()) { 13749 default: 13750 case ISD::BR_CC: 13751 case ISD::BRCOND: 13752 case ISD::SELECT: 13753 ExpectingFlags = true; 13754 break; 13755 case ISD::CopyToReg: 13756 case ISD::SIGN_EXTEND: 13757 case ISD::ZERO_EXTEND: 13758 case ISD::ANY_EXTEND: 13759 break; 13760 } 13761 13762 if (!ExpectingFlags) { 13763 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13764 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13765 13766 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13767 X86::CondCode tmp = cc0; 13768 cc0 = cc1; 13769 cc1 = tmp; 13770 } 13771 13772 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13773 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13774 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13775 X86ISD::NodeType NTOperator = is64BitFP ? 13776 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13777 // FIXME: need symbolic constants for these magic numbers. 13778 // See X86ATTInstPrinter.cpp:printSSECC(). 13779 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13780 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13781 DAG.getConstant(x86cc, MVT::i8)); 13782 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13783 OnesOrZeroesF); 13784 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13785 DAG.getConstant(1, MVT::i32)); 13786 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13787 return OneBitOfTruth; 13788 } 13789 } 13790 } 13791 } 13792 return SDValue(); 13793} 13794 13795/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13796/// so it can be folded inside ANDNP. 13797static bool CanFoldXORWithAllOnes(const SDNode *N) { 13798 EVT VT = N->getValueType(0); 13799 13800 // Match direct AllOnes for 128 and 256-bit vectors 13801 if (ISD::isBuildVectorAllOnes(N)) 13802 return true; 13803 13804 // Look through a bit convert. 13805 if (N->getOpcode() == ISD::BITCAST) 13806 N = N->getOperand(0).getNode(); 13807 13808 // Sometimes the operand may come from a insert_subvector building a 256-bit 13809 // allones vector 13810 if (VT.getSizeInBits() == 256 && 13811 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13812 SDValue V1 = N->getOperand(0); 13813 SDValue V2 = N->getOperand(1); 13814 13815 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13816 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13817 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13818 ISD::isBuildVectorAllOnes(V2.getNode())) 13819 return true; 13820 } 13821 13822 return false; 13823} 13824 13825static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13826 TargetLowering::DAGCombinerInfo &DCI, 13827 const X86Subtarget *Subtarget) { 13828 if (DCI.isBeforeLegalizeOps()) 13829 return SDValue(); 13830 13831 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13832 if (R.getNode()) 13833 return R; 13834 13835 EVT VT = N->getValueType(0); 13836 13837 // Create ANDN, BLSI, and BLSR instructions 13838 // BLSI is X & (-X) 13839 // BLSR is X & (X-1) 13840 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13841 SDValue N0 = N->getOperand(0); 13842 SDValue N1 = N->getOperand(1); 13843 DebugLoc DL = N->getDebugLoc(); 13844 13845 // Check LHS for not 13846 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13847 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13848 // Check RHS for not 13849 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13850 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13851 13852 // Check LHS for neg 13853 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13854 isZero(N0.getOperand(0))) 13855 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13856 13857 // Check RHS for neg 13858 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13859 isZero(N1.getOperand(0))) 13860 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13861 13862 // Check LHS for X-1 13863 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13864 isAllOnes(N0.getOperand(1))) 13865 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13866 13867 // Check RHS for X-1 13868 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13869 isAllOnes(N1.getOperand(1))) 13870 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13871 13872 return SDValue(); 13873 } 13874 13875 // Want to form ANDNP nodes: 13876 // 1) In the hopes of then easily combining them with OR and AND nodes 13877 // to form PBLEND/PSIGN. 13878 // 2) To match ANDN packed intrinsics 13879 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13880 return SDValue(); 13881 13882 SDValue N0 = N->getOperand(0); 13883 SDValue N1 = N->getOperand(1); 13884 DebugLoc DL = N->getDebugLoc(); 13885 13886 // Check LHS for vnot 13887 if (N0.getOpcode() == ISD::XOR && 13888 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13889 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13890 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13891 13892 // Check RHS for vnot 13893 if (N1.getOpcode() == ISD::XOR && 13894 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13895 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13896 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13897 13898 return SDValue(); 13899} 13900 13901static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13902 TargetLowering::DAGCombinerInfo &DCI, 13903 const X86Subtarget *Subtarget) { 13904 if (DCI.isBeforeLegalizeOps()) 13905 return SDValue(); 13906 13907 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13908 if (R.getNode()) 13909 return R; 13910 13911 EVT VT = N->getValueType(0); 13912 13913 SDValue N0 = N->getOperand(0); 13914 SDValue N1 = N->getOperand(1); 13915 13916 // look for psign/blend 13917 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13918 if (!Subtarget->hasSSSE3() || 13919 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13920 return SDValue(); 13921 13922 // Canonicalize pandn to RHS 13923 if (N0.getOpcode() == X86ISD::ANDNP) 13924 std::swap(N0, N1); 13925 // or (and (m, y), (pandn m, x)) 13926 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13927 SDValue Mask = N1.getOperand(0); 13928 SDValue X = N1.getOperand(1); 13929 SDValue Y; 13930 if (N0.getOperand(0) == Mask) 13931 Y = N0.getOperand(1); 13932 if (N0.getOperand(1) == Mask) 13933 Y = N0.getOperand(0); 13934 13935 // Check to see if the mask appeared in both the AND and ANDNP and 13936 if (!Y.getNode()) 13937 return SDValue(); 13938 13939 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13940 if (Mask.getOpcode() != ISD::BITCAST || 13941 X.getOpcode() != ISD::BITCAST || 13942 Y.getOpcode() != ISD::BITCAST) 13943 return SDValue(); 13944 13945 // Look through mask bitcast. 13946 Mask = Mask.getOperand(0); 13947 EVT MaskVT = Mask.getValueType(); 13948 13949 // Validate that the Mask operand is a vector sra node. 13950 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13951 // there is no psrai.b 13952 if (Mask.getOpcode() != X86ISD::VSRAI) 13953 return SDValue(); 13954 13955 // Check that the SRA is all signbits. 13956 SDValue SraC = Mask.getOperand(1); 13957 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13958 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13959 if ((SraAmt + 1) != EltBits) 13960 return SDValue(); 13961 13962 DebugLoc DL = N->getDebugLoc(); 13963 13964 // Now we know we at least have a plendvb with the mask val. See if 13965 // we can form a psignb/w/d. 13966 // psign = x.type == y.type == mask.type && y = sub(0, x); 13967 X = X.getOperand(0); 13968 Y = Y.getOperand(0); 13969 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13970 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13971 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 13972 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 13973 "Unsupported VT for PSIGN"); 13974 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 13975 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13976 } 13977 // PBLENDVB only available on SSE 4.1 13978 if (!Subtarget->hasSSE41()) 13979 return SDValue(); 13980 13981 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 13982 13983 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 13984 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 13985 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 13986 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 13987 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13988 } 13989 } 13990 13991 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 13992 return SDValue(); 13993 13994 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13995 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13996 std::swap(N0, N1); 13997 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13998 return SDValue(); 13999 if (!N0.hasOneUse() || !N1.hasOneUse()) 14000 return SDValue(); 14001 14002 SDValue ShAmt0 = N0.getOperand(1); 14003 if (ShAmt0.getValueType() != MVT::i8) 14004 return SDValue(); 14005 SDValue ShAmt1 = N1.getOperand(1); 14006 if (ShAmt1.getValueType() != MVT::i8) 14007 return SDValue(); 14008 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14009 ShAmt0 = ShAmt0.getOperand(0); 14010 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14011 ShAmt1 = ShAmt1.getOperand(0); 14012 14013 DebugLoc DL = N->getDebugLoc(); 14014 unsigned Opc = X86ISD::SHLD; 14015 SDValue Op0 = N0.getOperand(0); 14016 SDValue Op1 = N1.getOperand(0); 14017 if (ShAmt0.getOpcode() == ISD::SUB) { 14018 Opc = X86ISD::SHRD; 14019 std::swap(Op0, Op1); 14020 std::swap(ShAmt0, ShAmt1); 14021 } 14022 14023 unsigned Bits = VT.getSizeInBits(); 14024 if (ShAmt1.getOpcode() == ISD::SUB) { 14025 SDValue Sum = ShAmt1.getOperand(0); 14026 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14027 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14028 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14029 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14030 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14031 return DAG.getNode(Opc, DL, VT, 14032 Op0, Op1, 14033 DAG.getNode(ISD::TRUNCATE, DL, 14034 MVT::i8, ShAmt0)); 14035 } 14036 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14037 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14038 if (ShAmt0C && 14039 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14040 return DAG.getNode(Opc, DL, VT, 14041 N0.getOperand(0), N1.getOperand(0), 14042 DAG.getNode(ISD::TRUNCATE, DL, 14043 MVT::i8, ShAmt0)); 14044 } 14045 14046 return SDValue(); 14047} 14048 14049// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14050static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14051 TargetLowering::DAGCombinerInfo &DCI, 14052 const X86Subtarget *Subtarget) { 14053 if (DCI.isBeforeLegalizeOps()) 14054 return SDValue(); 14055 14056 EVT VT = N->getValueType(0); 14057 14058 if (VT != MVT::i32 && VT != MVT::i64) 14059 return SDValue(); 14060 14061 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14062 14063 // Create BLSMSK instructions by finding X ^ (X-1) 14064 SDValue N0 = N->getOperand(0); 14065 SDValue N1 = N->getOperand(1); 14066 DebugLoc DL = N->getDebugLoc(); 14067 14068 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14069 isAllOnes(N0.getOperand(1))) 14070 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14071 14072 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14073 isAllOnes(N1.getOperand(1))) 14074 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14075 14076 return SDValue(); 14077} 14078 14079/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14080static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14081 const X86Subtarget *Subtarget) { 14082 LoadSDNode *Ld = cast<LoadSDNode>(N); 14083 EVT RegVT = Ld->getValueType(0); 14084 EVT MemVT = Ld->getMemoryVT(); 14085 DebugLoc dl = Ld->getDebugLoc(); 14086 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14087 14088 ISD::LoadExtType Ext = Ld->getExtensionType(); 14089 14090 // If this is a vector EXT Load then attempt to optimize it using a 14091 // shuffle. We need SSE4 for the shuffles. 14092 // TODO: It is possible to support ZExt by zeroing the undef values 14093 // during the shuffle phase or after the shuffle. 14094 if (RegVT.isVector() && RegVT.isInteger() && 14095 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14096 assert(MemVT != RegVT && "Cannot extend to the same type"); 14097 assert(MemVT.isVector() && "Must load a vector from memory"); 14098 14099 unsigned NumElems = RegVT.getVectorNumElements(); 14100 unsigned RegSz = RegVT.getSizeInBits(); 14101 unsigned MemSz = MemVT.getSizeInBits(); 14102 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14103 // All sizes must be a power of two 14104 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14105 14106 // Attempt to load the original value using a single load op. 14107 // Find a scalar type which is equal to the loaded word size. 14108 MVT SclrLoadTy = MVT::i8; 14109 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14110 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14111 MVT Tp = (MVT::SimpleValueType)tp; 14112 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14113 SclrLoadTy = Tp; 14114 break; 14115 } 14116 } 14117 14118 // Proceed if a load word is found. 14119 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14120 14121 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14122 RegSz/SclrLoadTy.getSizeInBits()); 14123 14124 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14125 RegSz/MemVT.getScalarType().getSizeInBits()); 14126 // Can't shuffle using an illegal type. 14127 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14128 14129 // Perform a single load. 14130 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14131 Ld->getBasePtr(), 14132 Ld->getPointerInfo(), Ld->isVolatile(), 14133 Ld->isNonTemporal(), Ld->isInvariant(), 14134 Ld->getAlignment()); 14135 14136 // Insert the word loaded into a vector. 14137 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14138 LoadUnitVecVT, ScalarLoad); 14139 14140 // Bitcast the loaded value to a vector of the original element type, in 14141 // the size of the target vector type. 14142 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14143 ScalarInVector); 14144 unsigned SizeRatio = RegSz/MemSz; 14145 14146 // Redistribute the loaded elements into the different locations. 14147 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14148 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14149 14150 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14151 DAG.getUNDEF(SlicedVec.getValueType()), 14152 ShuffleVec.data()); 14153 14154 // Bitcast to the requested type. 14155 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14156 // Replace the original load with the new sequence 14157 // and return the new chain. 14158 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14159 return SDValue(ScalarLoad.getNode(), 1); 14160 } 14161 14162 return SDValue(); 14163} 14164 14165/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14166static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14167 const X86Subtarget *Subtarget) { 14168 StoreSDNode *St = cast<StoreSDNode>(N); 14169 EVT VT = St->getValue().getValueType(); 14170 EVT StVT = St->getMemoryVT(); 14171 DebugLoc dl = St->getDebugLoc(); 14172 SDValue StoredVal = St->getOperand(1); 14173 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14174 14175 // If we are saving a concatenation of two XMM registers, perform two stores. 14176 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14177 // 128-bit ones. If in the future the cost becomes only one memory access the 14178 // first version would be better. 14179 if (VT.getSizeInBits() == 256 && 14180 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14181 StoredVal.getNumOperands() == 2) { 14182 14183 SDValue Value0 = StoredVal.getOperand(0); 14184 SDValue Value1 = StoredVal.getOperand(1); 14185 14186 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14187 SDValue Ptr0 = St->getBasePtr(); 14188 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14189 14190 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14191 St->getPointerInfo(), St->isVolatile(), 14192 St->isNonTemporal(), St->getAlignment()); 14193 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14194 St->getPointerInfo(), St->isVolatile(), 14195 St->isNonTemporal(), St->getAlignment()); 14196 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14197 } 14198 14199 // Optimize trunc store (of multiple scalars) to shuffle and store. 14200 // First, pack all of the elements in one place. Next, store to memory 14201 // in fewer chunks. 14202 if (St->isTruncatingStore() && VT.isVector()) { 14203 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14204 unsigned NumElems = VT.getVectorNumElements(); 14205 assert(StVT != VT && "Cannot truncate to the same type"); 14206 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14207 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14208 14209 // From, To sizes and ElemCount must be pow of two 14210 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14211 // We are going to use the original vector elt for storing. 14212 // Accumulated smaller vector elements must be a multiple of the store size. 14213 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14214 14215 unsigned SizeRatio = FromSz / ToSz; 14216 14217 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14218 14219 // Create a type on which we perform the shuffle 14220 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14221 StVT.getScalarType(), NumElems*SizeRatio); 14222 14223 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14224 14225 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14226 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14227 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14228 14229 // Can't shuffle using an illegal type 14230 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14231 14232 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14233 DAG.getUNDEF(WideVec.getValueType()), 14234 ShuffleVec.data()); 14235 // At this point all of the data is stored at the bottom of the 14236 // register. We now need to save it to mem. 14237 14238 // Find the largest store unit 14239 MVT StoreType = MVT::i8; 14240 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14241 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14242 MVT Tp = (MVT::SimpleValueType)tp; 14243 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14244 StoreType = Tp; 14245 } 14246 14247 // Bitcast the original vector into a vector of store-size units 14248 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14249 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14250 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14251 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14252 SmallVector<SDValue, 8> Chains; 14253 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14254 TLI.getPointerTy()); 14255 SDValue Ptr = St->getBasePtr(); 14256 14257 // Perform one or more big stores into memory. 14258 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14259 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14260 StoreType, ShuffWide, 14261 DAG.getIntPtrConstant(i)); 14262 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14263 St->getPointerInfo(), St->isVolatile(), 14264 St->isNonTemporal(), St->getAlignment()); 14265 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14266 Chains.push_back(Ch); 14267 } 14268 14269 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14270 Chains.size()); 14271 } 14272 14273 14274 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14275 // the FP state in cases where an emms may be missing. 14276 // A preferable solution to the general problem is to figure out the right 14277 // places to insert EMMS. This qualifies as a quick hack. 14278 14279 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14280 if (VT.getSizeInBits() != 64) 14281 return SDValue(); 14282 14283 const Function *F = DAG.getMachineFunction().getFunction(); 14284 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14285 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14286 && Subtarget->hasSSE2(); 14287 if ((VT.isVector() || 14288 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14289 isa<LoadSDNode>(St->getValue()) && 14290 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14291 St->getChain().hasOneUse() && !St->isVolatile()) { 14292 SDNode* LdVal = St->getValue().getNode(); 14293 LoadSDNode *Ld = 0; 14294 int TokenFactorIndex = -1; 14295 SmallVector<SDValue, 8> Ops; 14296 SDNode* ChainVal = St->getChain().getNode(); 14297 // Must be a store of a load. We currently handle two cases: the load 14298 // is a direct child, and it's under an intervening TokenFactor. It is 14299 // possible to dig deeper under nested TokenFactors. 14300 if (ChainVal == LdVal) 14301 Ld = cast<LoadSDNode>(St->getChain()); 14302 else if (St->getValue().hasOneUse() && 14303 ChainVal->getOpcode() == ISD::TokenFactor) { 14304 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14305 if (ChainVal->getOperand(i).getNode() == LdVal) { 14306 TokenFactorIndex = i; 14307 Ld = cast<LoadSDNode>(St->getValue()); 14308 } else 14309 Ops.push_back(ChainVal->getOperand(i)); 14310 } 14311 } 14312 14313 if (!Ld || !ISD::isNormalLoad(Ld)) 14314 return SDValue(); 14315 14316 // If this is not the MMX case, i.e. we are just turning i64 load/store 14317 // into f64 load/store, avoid the transformation if there are multiple 14318 // uses of the loaded value. 14319 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14320 return SDValue(); 14321 14322 DebugLoc LdDL = Ld->getDebugLoc(); 14323 DebugLoc StDL = N->getDebugLoc(); 14324 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14325 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14326 // pair instead. 14327 if (Subtarget->is64Bit() || F64IsLegal) { 14328 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14329 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14330 Ld->getPointerInfo(), Ld->isVolatile(), 14331 Ld->isNonTemporal(), Ld->isInvariant(), 14332 Ld->getAlignment()); 14333 SDValue NewChain = NewLd.getValue(1); 14334 if (TokenFactorIndex != -1) { 14335 Ops.push_back(NewChain); 14336 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14337 Ops.size()); 14338 } 14339 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14340 St->getPointerInfo(), 14341 St->isVolatile(), St->isNonTemporal(), 14342 St->getAlignment()); 14343 } 14344 14345 // Otherwise, lower to two pairs of 32-bit loads / stores. 14346 SDValue LoAddr = Ld->getBasePtr(); 14347 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14348 DAG.getConstant(4, MVT::i32)); 14349 14350 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14351 Ld->getPointerInfo(), 14352 Ld->isVolatile(), Ld->isNonTemporal(), 14353 Ld->isInvariant(), Ld->getAlignment()); 14354 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14355 Ld->getPointerInfo().getWithOffset(4), 14356 Ld->isVolatile(), Ld->isNonTemporal(), 14357 Ld->isInvariant(), 14358 MinAlign(Ld->getAlignment(), 4)); 14359 14360 SDValue NewChain = LoLd.getValue(1); 14361 if (TokenFactorIndex != -1) { 14362 Ops.push_back(LoLd); 14363 Ops.push_back(HiLd); 14364 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14365 Ops.size()); 14366 } 14367 14368 LoAddr = St->getBasePtr(); 14369 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14370 DAG.getConstant(4, MVT::i32)); 14371 14372 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14373 St->getPointerInfo(), 14374 St->isVolatile(), St->isNonTemporal(), 14375 St->getAlignment()); 14376 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14377 St->getPointerInfo().getWithOffset(4), 14378 St->isVolatile(), 14379 St->isNonTemporal(), 14380 MinAlign(St->getAlignment(), 4)); 14381 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14382 } 14383 return SDValue(); 14384} 14385 14386/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14387/// and return the operands for the horizontal operation in LHS and RHS. A 14388/// horizontal operation performs the binary operation on successive elements 14389/// of its first operand, then on successive elements of its second operand, 14390/// returning the resulting values in a vector. For example, if 14391/// A = < float a0, float a1, float a2, float a3 > 14392/// and 14393/// B = < float b0, float b1, float b2, float b3 > 14394/// then the result of doing a horizontal operation on A and B is 14395/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14396/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14397/// A horizontal-op B, for some already available A and B, and if so then LHS is 14398/// set to A, RHS to B, and the routine returns 'true'. 14399/// Note that the binary operation should have the property that if one of the 14400/// operands is UNDEF then the result is UNDEF. 14401static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14402 // Look for the following pattern: if 14403 // A = < float a0, float a1, float a2, float a3 > 14404 // B = < float b0, float b1, float b2, float b3 > 14405 // and 14406 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14407 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14408 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14409 // which is A horizontal-op B. 14410 14411 // At least one of the operands should be a vector shuffle. 14412 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14413 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14414 return false; 14415 14416 EVT VT = LHS.getValueType(); 14417 14418 assert((VT.is128BitVector() || VT.is256BitVector()) && 14419 "Unsupported vector type for horizontal add/sub"); 14420 14421 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14422 // operate independently on 128-bit lanes. 14423 unsigned NumElts = VT.getVectorNumElements(); 14424 unsigned NumLanes = VT.getSizeInBits()/128; 14425 unsigned NumLaneElts = NumElts / NumLanes; 14426 assert((NumLaneElts % 2 == 0) && 14427 "Vector type should have an even number of elements in each lane"); 14428 unsigned HalfLaneElts = NumLaneElts/2; 14429 14430 // View LHS in the form 14431 // LHS = VECTOR_SHUFFLE A, B, LMask 14432 // If LHS is not a shuffle then pretend it is the shuffle 14433 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14434 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14435 // type VT. 14436 SDValue A, B; 14437 SmallVector<int, 16> LMask(NumElts); 14438 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14439 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14440 A = LHS.getOperand(0); 14441 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14442 B = LHS.getOperand(1); 14443 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14444 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14445 } else { 14446 if (LHS.getOpcode() != ISD::UNDEF) 14447 A = LHS; 14448 for (unsigned i = 0; i != NumElts; ++i) 14449 LMask[i] = i; 14450 } 14451 14452 // Likewise, view RHS in the form 14453 // RHS = VECTOR_SHUFFLE C, D, RMask 14454 SDValue C, D; 14455 SmallVector<int, 16> RMask(NumElts); 14456 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14457 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14458 C = RHS.getOperand(0); 14459 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14460 D = RHS.getOperand(1); 14461 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14462 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14463 } else { 14464 if (RHS.getOpcode() != ISD::UNDEF) 14465 C = RHS; 14466 for (unsigned i = 0; i != NumElts; ++i) 14467 RMask[i] = i; 14468 } 14469 14470 // Check that the shuffles are both shuffling the same vectors. 14471 if (!(A == C && B == D) && !(A == D && B == C)) 14472 return false; 14473 14474 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14475 if (!A.getNode() && !B.getNode()) 14476 return false; 14477 14478 // If A and B occur in reverse order in RHS, then "swap" them (which means 14479 // rewriting the mask). 14480 if (A != C) 14481 CommuteVectorShuffleMask(RMask, NumElts); 14482 14483 // At this point LHS and RHS are equivalent to 14484 // LHS = VECTOR_SHUFFLE A, B, LMask 14485 // RHS = VECTOR_SHUFFLE A, B, RMask 14486 // Check that the masks correspond to performing a horizontal operation. 14487 for (unsigned i = 0; i != NumElts; ++i) { 14488 int LIdx = LMask[i], RIdx = RMask[i]; 14489 14490 // Ignore any UNDEF components. 14491 if (LIdx < 0 || RIdx < 0 || 14492 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14493 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14494 continue; 14495 14496 // Check that successive elements are being operated on. If not, this is 14497 // not a horizontal operation. 14498 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14499 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14500 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14501 if (!(LIdx == Index && RIdx == Index + 1) && 14502 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14503 return false; 14504 } 14505 14506 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14507 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14508 return true; 14509} 14510 14511/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14512static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14513 const X86Subtarget *Subtarget) { 14514 EVT VT = N->getValueType(0); 14515 SDValue LHS = N->getOperand(0); 14516 SDValue RHS = N->getOperand(1); 14517 14518 // Try to synthesize horizontal adds from adds of shuffles. 14519 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14520 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14521 isHorizontalBinOp(LHS, RHS, true)) 14522 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14523 return SDValue(); 14524} 14525 14526/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14527static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14528 const X86Subtarget *Subtarget) { 14529 EVT VT = N->getValueType(0); 14530 SDValue LHS = N->getOperand(0); 14531 SDValue RHS = N->getOperand(1); 14532 14533 // Try to synthesize horizontal subs from subs of shuffles. 14534 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14535 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14536 isHorizontalBinOp(LHS, RHS, false)) 14537 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14538 return SDValue(); 14539} 14540 14541/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14542/// X86ISD::FXOR nodes. 14543static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14544 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14545 // F[X]OR(0.0, x) -> x 14546 // F[X]OR(x, 0.0) -> x 14547 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14548 if (C->getValueAPF().isPosZero()) 14549 return N->getOperand(1); 14550 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14551 if (C->getValueAPF().isPosZero()) 14552 return N->getOperand(0); 14553 return SDValue(); 14554} 14555 14556/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14557static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14558 // FAND(0.0, x) -> 0.0 14559 // FAND(x, 0.0) -> 0.0 14560 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14561 if (C->getValueAPF().isPosZero()) 14562 return N->getOperand(0); 14563 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14564 if (C->getValueAPF().isPosZero()) 14565 return N->getOperand(1); 14566 return SDValue(); 14567} 14568 14569static SDValue PerformBTCombine(SDNode *N, 14570 SelectionDAG &DAG, 14571 TargetLowering::DAGCombinerInfo &DCI) { 14572 // BT ignores high bits in the bit index operand. 14573 SDValue Op1 = N->getOperand(1); 14574 if (Op1.hasOneUse()) { 14575 unsigned BitWidth = Op1.getValueSizeInBits(); 14576 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14577 APInt KnownZero, KnownOne; 14578 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14579 !DCI.isBeforeLegalizeOps()); 14580 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14581 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14582 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14583 DCI.CommitTargetLoweringOpt(TLO); 14584 } 14585 return SDValue(); 14586} 14587 14588static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14589 SDValue Op = N->getOperand(0); 14590 if (Op.getOpcode() == ISD::BITCAST) 14591 Op = Op.getOperand(0); 14592 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14593 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14594 VT.getVectorElementType().getSizeInBits() == 14595 OpVT.getVectorElementType().getSizeInBits()) { 14596 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14597 } 14598 return SDValue(); 14599} 14600 14601static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14602 TargetLowering::DAGCombinerInfo &DCI, 14603 const X86Subtarget *Subtarget) { 14604 if (!DCI.isBeforeLegalizeOps()) 14605 return SDValue(); 14606 14607 if (!Subtarget->hasAVX()) 14608 return SDValue(); 14609 14610 // Optimize vectors in AVX mode 14611 // Sign extend v8i16 to v8i32 and 14612 // v4i32 to v4i64 14613 // 14614 // Divide input vector into two parts 14615 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14616 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14617 // concat the vectors to original VT 14618 14619 EVT VT = N->getValueType(0); 14620 SDValue Op = N->getOperand(0); 14621 EVT OpVT = Op.getValueType(); 14622 DebugLoc dl = N->getDebugLoc(); 14623 14624 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14625 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14626 14627 unsigned NumElems = OpVT.getVectorNumElements(); 14628 SmallVector<int,8> ShufMask1(NumElems, -1); 14629 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i; 14630 14631 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14632 ShufMask1.data()); 14633 14634 SmallVector<int,8> ShufMask2(NumElems, -1); 14635 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2; 14636 14637 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14638 ShufMask2.data()); 14639 14640 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14641 VT.getVectorNumElements()/2); 14642 14643 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14644 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14645 14646 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14647 } 14648 return SDValue(); 14649} 14650 14651static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14652 const X86Subtarget *Subtarget) { 14653 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14654 // (and (i32 x86isd::setcc_carry), 1) 14655 // This eliminates the zext. This transformation is necessary because 14656 // ISD::SETCC is always legalized to i8. 14657 DebugLoc dl = N->getDebugLoc(); 14658 SDValue N0 = N->getOperand(0); 14659 EVT VT = N->getValueType(0); 14660 EVT OpVT = N0.getValueType(); 14661 14662 if (N0.getOpcode() == ISD::AND && 14663 N0.hasOneUse() && 14664 N0.getOperand(0).hasOneUse()) { 14665 SDValue N00 = N0.getOperand(0); 14666 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14667 return SDValue(); 14668 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14669 if (!C || C->getZExtValue() != 1) 14670 return SDValue(); 14671 return DAG.getNode(ISD::AND, dl, VT, 14672 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14673 N00.getOperand(0), N00.getOperand(1)), 14674 DAG.getConstant(1, VT)); 14675 } 14676 // Optimize vectors in AVX mode: 14677 // 14678 // v8i16 -> v8i32 14679 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14680 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14681 // Concat upper and lower parts. 14682 // 14683 // v4i32 -> v4i64 14684 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14685 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14686 // Concat upper and lower parts. 14687 // 14688 if (Subtarget->hasAVX()) { 14689 14690 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14691 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14692 14693 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14694 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG); 14695 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG); 14696 14697 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14698 VT.getVectorNumElements()/2); 14699 14700 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14701 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14702 14703 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14704 } 14705 } 14706 14707 14708 return SDValue(); 14709} 14710 14711// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14712static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14713 unsigned X86CC = N->getConstantOperandVal(0); 14714 SDValue EFLAG = N->getOperand(1); 14715 DebugLoc DL = N->getDebugLoc(); 14716 14717 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14718 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14719 // cases. 14720 if (X86CC == X86::COND_B) 14721 return DAG.getNode(ISD::AND, DL, MVT::i8, 14722 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14723 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14724 DAG.getConstant(1, MVT::i8)); 14725 14726 return SDValue(); 14727} 14728 14729static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14730 const X86TargetLowering *XTLI) { 14731 SDValue Op0 = N->getOperand(0); 14732 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14733 // a 32-bit target where SSE doesn't support i64->FP operations. 14734 if (Op0.getOpcode() == ISD::LOAD) { 14735 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14736 EVT VT = Ld->getValueType(0); 14737 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14738 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14739 !XTLI->getSubtarget()->is64Bit() && 14740 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14741 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14742 Ld->getChain(), Op0, DAG); 14743 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14744 return FILDChain; 14745 } 14746 } 14747 return SDValue(); 14748} 14749 14750// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14751static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14752 X86TargetLowering::DAGCombinerInfo &DCI) { 14753 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14754 // the result is either zero or one (depending on the input carry bit). 14755 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14756 if (X86::isZeroNode(N->getOperand(0)) && 14757 X86::isZeroNode(N->getOperand(1)) && 14758 // We don't have a good way to replace an EFLAGS use, so only do this when 14759 // dead right now. 14760 SDValue(N, 1).use_empty()) { 14761 DebugLoc DL = N->getDebugLoc(); 14762 EVT VT = N->getValueType(0); 14763 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14764 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14765 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14766 DAG.getConstant(X86::COND_B,MVT::i8), 14767 N->getOperand(2)), 14768 DAG.getConstant(1, VT)); 14769 return DCI.CombineTo(N, Res1, CarryOut); 14770 } 14771 14772 return SDValue(); 14773} 14774 14775// fold (add Y, (sete X, 0)) -> adc 0, Y 14776// (add Y, (setne X, 0)) -> sbb -1, Y 14777// (sub (sete X, 0), Y) -> sbb 0, Y 14778// (sub (setne X, 0), Y) -> adc -1, Y 14779static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14780 DebugLoc DL = N->getDebugLoc(); 14781 14782 // Look through ZExts. 14783 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14784 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14785 return SDValue(); 14786 14787 SDValue SetCC = Ext.getOperand(0); 14788 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14789 return SDValue(); 14790 14791 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14792 if (CC != X86::COND_E && CC != X86::COND_NE) 14793 return SDValue(); 14794 14795 SDValue Cmp = SetCC.getOperand(1); 14796 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14797 !X86::isZeroNode(Cmp.getOperand(1)) || 14798 !Cmp.getOperand(0).getValueType().isInteger()) 14799 return SDValue(); 14800 14801 SDValue CmpOp0 = Cmp.getOperand(0); 14802 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14803 DAG.getConstant(1, CmpOp0.getValueType())); 14804 14805 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14806 if (CC == X86::COND_NE) 14807 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14808 DL, OtherVal.getValueType(), OtherVal, 14809 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14810 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14811 DL, OtherVal.getValueType(), OtherVal, 14812 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14813} 14814 14815/// PerformADDCombine - Do target-specific dag combines on integer adds. 14816static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14817 const X86Subtarget *Subtarget) { 14818 EVT VT = N->getValueType(0); 14819 SDValue Op0 = N->getOperand(0); 14820 SDValue Op1 = N->getOperand(1); 14821 14822 // Try to synthesize horizontal adds from adds of shuffles. 14823 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14824 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14825 isHorizontalBinOp(Op0, Op1, true)) 14826 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14827 14828 return OptimizeConditionalInDecrement(N, DAG); 14829} 14830 14831static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14832 const X86Subtarget *Subtarget) { 14833 SDValue Op0 = N->getOperand(0); 14834 SDValue Op1 = N->getOperand(1); 14835 14836 // X86 can't encode an immediate LHS of a sub. See if we can push the 14837 // negation into a preceding instruction. 14838 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14839 // If the RHS of the sub is a XOR with one use and a constant, invert the 14840 // immediate. Then add one to the LHS of the sub so we can turn 14841 // X-Y -> X+~Y+1, saving one register. 14842 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14843 isa<ConstantSDNode>(Op1.getOperand(1))) { 14844 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14845 EVT VT = Op0.getValueType(); 14846 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14847 Op1.getOperand(0), 14848 DAG.getConstant(~XorC, VT)); 14849 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14850 DAG.getConstant(C->getAPIntValue()+1, VT)); 14851 } 14852 } 14853 14854 // Try to synthesize horizontal adds from adds of shuffles. 14855 EVT VT = N->getValueType(0); 14856 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14857 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14858 isHorizontalBinOp(Op0, Op1, true)) 14859 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14860 14861 return OptimizeConditionalInDecrement(N, DAG); 14862} 14863 14864SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14865 DAGCombinerInfo &DCI) const { 14866 SelectionDAG &DAG = DCI.DAG; 14867 switch (N->getOpcode()) { 14868 default: break; 14869 case ISD::EXTRACT_VECTOR_ELT: 14870 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14871 case ISD::VSELECT: 14872 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 14873 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14874 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14875 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14876 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14877 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14878 case ISD::SHL: 14879 case ISD::SRA: 14880 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 14881 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14882 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14883 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14884 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14885 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14886 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14887 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14888 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14889 case X86ISD::FXOR: 14890 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14891 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14892 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14893 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14894 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); 14895 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 14896 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 14897 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14898 case X86ISD::SHUFP: // Handle all target specific shuffles 14899 case X86ISD::PALIGN: 14900 case X86ISD::UNPCKH: 14901 case X86ISD::UNPCKL: 14902 case X86ISD::MOVHLPS: 14903 case X86ISD::MOVLHPS: 14904 case X86ISD::PSHUFD: 14905 case X86ISD::PSHUFHW: 14906 case X86ISD::PSHUFLW: 14907 case X86ISD::MOVSS: 14908 case X86ISD::MOVSD: 14909 case X86ISD::VPERMILP: 14910 case X86ISD::VPERM2X128: 14911 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14912 } 14913 14914 return SDValue(); 14915} 14916 14917/// isTypeDesirableForOp - Return true if the target has native support for 14918/// the specified value type and it is 'desirable' to use the type for the 14919/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14920/// instruction encodings are longer and some i16 instructions are slow. 14921bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14922 if (!isTypeLegal(VT)) 14923 return false; 14924 if (VT != MVT::i16) 14925 return true; 14926 14927 switch (Opc) { 14928 default: 14929 return true; 14930 case ISD::LOAD: 14931 case ISD::SIGN_EXTEND: 14932 case ISD::ZERO_EXTEND: 14933 case ISD::ANY_EXTEND: 14934 case ISD::SHL: 14935 case ISD::SRL: 14936 case ISD::SUB: 14937 case ISD::ADD: 14938 case ISD::MUL: 14939 case ISD::AND: 14940 case ISD::OR: 14941 case ISD::XOR: 14942 return false; 14943 } 14944} 14945 14946/// IsDesirableToPromoteOp - This method query the target whether it is 14947/// beneficial for dag combiner to promote the specified node. If true, it 14948/// should return the desired promotion type by reference. 14949bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14950 EVT VT = Op.getValueType(); 14951 if (VT != MVT::i16) 14952 return false; 14953 14954 bool Promote = false; 14955 bool Commute = false; 14956 switch (Op.getOpcode()) { 14957 default: break; 14958 case ISD::LOAD: { 14959 LoadSDNode *LD = cast<LoadSDNode>(Op); 14960 // If the non-extending load has a single use and it's not live out, then it 14961 // might be folded. 14962 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14963 Op.hasOneUse()*/) { 14964 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14965 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14966 // The only case where we'd want to promote LOAD (rather then it being 14967 // promoted as an operand is when it's only use is liveout. 14968 if (UI->getOpcode() != ISD::CopyToReg) 14969 return false; 14970 } 14971 } 14972 Promote = true; 14973 break; 14974 } 14975 case ISD::SIGN_EXTEND: 14976 case ISD::ZERO_EXTEND: 14977 case ISD::ANY_EXTEND: 14978 Promote = true; 14979 break; 14980 case ISD::SHL: 14981 case ISD::SRL: { 14982 SDValue N0 = Op.getOperand(0); 14983 // Look out for (store (shl (load), x)). 14984 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14985 return false; 14986 Promote = true; 14987 break; 14988 } 14989 case ISD::ADD: 14990 case ISD::MUL: 14991 case ISD::AND: 14992 case ISD::OR: 14993 case ISD::XOR: 14994 Commute = true; 14995 // fallthrough 14996 case ISD::SUB: { 14997 SDValue N0 = Op.getOperand(0); 14998 SDValue N1 = Op.getOperand(1); 14999 if (!Commute && MayFoldLoad(N1)) 15000 return false; 15001 // Avoid disabling potential load folding opportunities. 15002 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15003 return false; 15004 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15005 return false; 15006 Promote = true; 15007 } 15008 } 15009 15010 PVT = MVT::i32; 15011 return Promote; 15012} 15013 15014//===----------------------------------------------------------------------===// 15015// X86 Inline Assembly Support 15016//===----------------------------------------------------------------------===// 15017 15018namespace { 15019 // Helper to match a string separated by whitespace. 15020 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15021 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15022 15023 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15024 StringRef piece(*args[i]); 15025 if (!s.startswith(piece)) // Check if the piece matches. 15026 return false; 15027 15028 s = s.substr(piece.size()); 15029 StringRef::size_type pos = s.find_first_not_of(" \t"); 15030 if (pos == 0) // We matched a prefix. 15031 return false; 15032 15033 s = s.substr(pos); 15034 } 15035 15036 return s.empty(); 15037 } 15038 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15039} 15040 15041bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15042 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15043 15044 std::string AsmStr = IA->getAsmString(); 15045 15046 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15047 if (!Ty || Ty->getBitWidth() % 16 != 0) 15048 return false; 15049 15050 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15051 SmallVector<StringRef, 4> AsmPieces; 15052 SplitString(AsmStr, AsmPieces, ";\n"); 15053 15054 switch (AsmPieces.size()) { 15055 default: return false; 15056 case 1: 15057 // FIXME: this should verify that we are targeting a 486 or better. If not, 15058 // we will turn this bswap into something that will be lowered to logical 15059 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15060 // lower so don't worry about this. 15061 // bswap $0 15062 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15063 matchAsm(AsmPieces[0], "bswapl", "$0") || 15064 matchAsm(AsmPieces[0], "bswapq", "$0") || 15065 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15066 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15067 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15068 // No need to check constraints, nothing other than the equivalent of 15069 // "=r,0" would be valid here. 15070 return IntrinsicLowering::LowerToByteSwap(CI); 15071 } 15072 15073 // rorw $$8, ${0:w} --> llvm.bswap.i16 15074 if (CI->getType()->isIntegerTy(16) && 15075 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15076 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15077 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15078 AsmPieces.clear(); 15079 const std::string &ConstraintsStr = IA->getConstraintString(); 15080 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15081 std::sort(AsmPieces.begin(), AsmPieces.end()); 15082 if (AsmPieces.size() == 4 && 15083 AsmPieces[0] == "~{cc}" && 15084 AsmPieces[1] == "~{dirflag}" && 15085 AsmPieces[2] == "~{flags}" && 15086 AsmPieces[3] == "~{fpsr}") 15087 return IntrinsicLowering::LowerToByteSwap(CI); 15088 } 15089 break; 15090 case 3: 15091 if (CI->getType()->isIntegerTy(32) && 15092 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15093 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15094 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15095 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15096 AsmPieces.clear(); 15097 const std::string &ConstraintsStr = IA->getConstraintString(); 15098 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15099 std::sort(AsmPieces.begin(), AsmPieces.end()); 15100 if (AsmPieces.size() == 4 && 15101 AsmPieces[0] == "~{cc}" && 15102 AsmPieces[1] == "~{dirflag}" && 15103 AsmPieces[2] == "~{flags}" && 15104 AsmPieces[3] == "~{fpsr}") 15105 return IntrinsicLowering::LowerToByteSwap(CI); 15106 } 15107 15108 if (CI->getType()->isIntegerTy(64)) { 15109 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15110 if (Constraints.size() >= 2 && 15111 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15112 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15113 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15114 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15115 matchAsm(AsmPieces[1], "bswap", "%edx") && 15116 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15117 return IntrinsicLowering::LowerToByteSwap(CI); 15118 } 15119 } 15120 break; 15121 } 15122 return false; 15123} 15124 15125 15126 15127/// getConstraintType - Given a constraint letter, return the type of 15128/// constraint it is for this target. 15129X86TargetLowering::ConstraintType 15130X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15131 if (Constraint.size() == 1) { 15132 switch (Constraint[0]) { 15133 case 'R': 15134 case 'q': 15135 case 'Q': 15136 case 'f': 15137 case 't': 15138 case 'u': 15139 case 'y': 15140 case 'x': 15141 case 'Y': 15142 case 'l': 15143 return C_RegisterClass; 15144 case 'a': 15145 case 'b': 15146 case 'c': 15147 case 'd': 15148 case 'S': 15149 case 'D': 15150 case 'A': 15151 return C_Register; 15152 case 'I': 15153 case 'J': 15154 case 'K': 15155 case 'L': 15156 case 'M': 15157 case 'N': 15158 case 'G': 15159 case 'C': 15160 case 'e': 15161 case 'Z': 15162 return C_Other; 15163 default: 15164 break; 15165 } 15166 } 15167 return TargetLowering::getConstraintType(Constraint); 15168} 15169 15170/// Examine constraint type and operand type and determine a weight value. 15171/// This object must already have been set up with the operand type 15172/// and the current alternative constraint selected. 15173TargetLowering::ConstraintWeight 15174 X86TargetLowering::getSingleConstraintMatchWeight( 15175 AsmOperandInfo &info, const char *constraint) const { 15176 ConstraintWeight weight = CW_Invalid; 15177 Value *CallOperandVal = info.CallOperandVal; 15178 // If we don't have a value, we can't do a match, 15179 // but allow it at the lowest weight. 15180 if (CallOperandVal == NULL) 15181 return CW_Default; 15182 Type *type = CallOperandVal->getType(); 15183 // Look at the constraint type. 15184 switch (*constraint) { 15185 default: 15186 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15187 case 'R': 15188 case 'q': 15189 case 'Q': 15190 case 'a': 15191 case 'b': 15192 case 'c': 15193 case 'd': 15194 case 'S': 15195 case 'D': 15196 case 'A': 15197 if (CallOperandVal->getType()->isIntegerTy()) 15198 weight = CW_SpecificReg; 15199 break; 15200 case 'f': 15201 case 't': 15202 case 'u': 15203 if (type->isFloatingPointTy()) 15204 weight = CW_SpecificReg; 15205 break; 15206 case 'y': 15207 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15208 weight = CW_SpecificReg; 15209 break; 15210 case 'x': 15211 case 'Y': 15212 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15213 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15214 weight = CW_Register; 15215 break; 15216 case 'I': 15217 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15218 if (C->getZExtValue() <= 31) 15219 weight = CW_Constant; 15220 } 15221 break; 15222 case 'J': 15223 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15224 if (C->getZExtValue() <= 63) 15225 weight = CW_Constant; 15226 } 15227 break; 15228 case 'K': 15229 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15230 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15231 weight = CW_Constant; 15232 } 15233 break; 15234 case 'L': 15235 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15236 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15237 weight = CW_Constant; 15238 } 15239 break; 15240 case 'M': 15241 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15242 if (C->getZExtValue() <= 3) 15243 weight = CW_Constant; 15244 } 15245 break; 15246 case 'N': 15247 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15248 if (C->getZExtValue() <= 0xff) 15249 weight = CW_Constant; 15250 } 15251 break; 15252 case 'G': 15253 case 'C': 15254 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15255 weight = CW_Constant; 15256 } 15257 break; 15258 case 'e': 15259 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15260 if ((C->getSExtValue() >= -0x80000000LL) && 15261 (C->getSExtValue() <= 0x7fffffffLL)) 15262 weight = CW_Constant; 15263 } 15264 break; 15265 case 'Z': 15266 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15267 if (C->getZExtValue() <= 0xffffffff) 15268 weight = CW_Constant; 15269 } 15270 break; 15271 } 15272 return weight; 15273} 15274 15275/// LowerXConstraint - try to replace an X constraint, which matches anything, 15276/// with another that has more specific requirements based on the type of the 15277/// corresponding operand. 15278const char *X86TargetLowering:: 15279LowerXConstraint(EVT ConstraintVT) const { 15280 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15281 // 'f' like normal targets. 15282 if (ConstraintVT.isFloatingPoint()) { 15283 if (Subtarget->hasSSE2()) 15284 return "Y"; 15285 if (Subtarget->hasSSE1()) 15286 return "x"; 15287 } 15288 15289 return TargetLowering::LowerXConstraint(ConstraintVT); 15290} 15291 15292/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15293/// vector. If it is invalid, don't add anything to Ops. 15294void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15295 std::string &Constraint, 15296 std::vector<SDValue>&Ops, 15297 SelectionDAG &DAG) const { 15298 SDValue Result(0, 0); 15299 15300 // Only support length 1 constraints for now. 15301 if (Constraint.length() > 1) return; 15302 15303 char ConstraintLetter = Constraint[0]; 15304 switch (ConstraintLetter) { 15305 default: break; 15306 case 'I': 15307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15308 if (C->getZExtValue() <= 31) { 15309 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15310 break; 15311 } 15312 } 15313 return; 15314 case 'J': 15315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15316 if (C->getZExtValue() <= 63) { 15317 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15318 break; 15319 } 15320 } 15321 return; 15322 case 'K': 15323 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15324 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15325 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15326 break; 15327 } 15328 } 15329 return; 15330 case 'N': 15331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15332 if (C->getZExtValue() <= 255) { 15333 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15334 break; 15335 } 15336 } 15337 return; 15338 case 'e': { 15339 // 32-bit signed value 15340 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15341 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15342 C->getSExtValue())) { 15343 // Widen to 64 bits here to get it sign extended. 15344 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15345 break; 15346 } 15347 // FIXME gcc accepts some relocatable values here too, but only in certain 15348 // memory models; it's complicated. 15349 } 15350 return; 15351 } 15352 case 'Z': { 15353 // 32-bit unsigned value 15354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15355 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15356 C->getZExtValue())) { 15357 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15358 break; 15359 } 15360 } 15361 // FIXME gcc accepts some relocatable values here too, but only in certain 15362 // memory models; it's complicated. 15363 return; 15364 } 15365 case 'i': { 15366 // Literal immediates are always ok. 15367 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15368 // Widen to 64 bits here to get it sign extended. 15369 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15370 break; 15371 } 15372 15373 // In any sort of PIC mode addresses need to be computed at runtime by 15374 // adding in a register or some sort of table lookup. These can't 15375 // be used as immediates. 15376 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15377 return; 15378 15379 // If we are in non-pic codegen mode, we allow the address of a global (with 15380 // an optional displacement) to be used with 'i'. 15381 GlobalAddressSDNode *GA = 0; 15382 int64_t Offset = 0; 15383 15384 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15385 while (1) { 15386 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15387 Offset += GA->getOffset(); 15388 break; 15389 } else if (Op.getOpcode() == ISD::ADD) { 15390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15391 Offset += C->getZExtValue(); 15392 Op = Op.getOperand(0); 15393 continue; 15394 } 15395 } else if (Op.getOpcode() == ISD::SUB) { 15396 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15397 Offset += -C->getZExtValue(); 15398 Op = Op.getOperand(0); 15399 continue; 15400 } 15401 } 15402 15403 // Otherwise, this isn't something we can handle, reject it. 15404 return; 15405 } 15406 15407 const GlobalValue *GV = GA->getGlobal(); 15408 // If we require an extra load to get this address, as in PIC mode, we 15409 // can't accept it. 15410 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15411 getTargetMachine()))) 15412 return; 15413 15414 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15415 GA->getValueType(0), Offset); 15416 break; 15417 } 15418 } 15419 15420 if (Result.getNode()) { 15421 Ops.push_back(Result); 15422 return; 15423 } 15424 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15425} 15426 15427std::pair<unsigned, const TargetRegisterClass*> 15428X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15429 EVT VT) const { 15430 // First, see if this is a constraint that directly corresponds to an LLVM 15431 // register class. 15432 if (Constraint.size() == 1) { 15433 // GCC Constraint Letters 15434 switch (Constraint[0]) { 15435 default: break; 15436 // TODO: Slight differences here in allocation order and leaving 15437 // RIP in the class. Do they matter any more here than they do 15438 // in the normal allocation? 15439 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15440 if (Subtarget->is64Bit()) { 15441 if (VT == MVT::i32 || VT == MVT::f32) 15442 return std::make_pair(0U, X86::GR32RegisterClass); 15443 else if (VT == MVT::i16) 15444 return std::make_pair(0U, X86::GR16RegisterClass); 15445 else if (VT == MVT::i8 || VT == MVT::i1) 15446 return std::make_pair(0U, X86::GR8RegisterClass); 15447 else if (VT == MVT::i64 || VT == MVT::f64) 15448 return std::make_pair(0U, X86::GR64RegisterClass); 15449 break; 15450 } 15451 // 32-bit fallthrough 15452 case 'Q': // Q_REGS 15453 if (VT == MVT::i32 || VT == MVT::f32) 15454 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15455 else if (VT == MVT::i16) 15456 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15457 else if (VT == MVT::i8 || VT == MVT::i1) 15458 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15459 else if (VT == MVT::i64) 15460 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15461 break; 15462 case 'r': // GENERAL_REGS 15463 case 'l': // INDEX_REGS 15464 if (VT == MVT::i8 || VT == MVT::i1) 15465 return std::make_pair(0U, X86::GR8RegisterClass); 15466 if (VT == MVT::i16) 15467 return std::make_pair(0U, X86::GR16RegisterClass); 15468 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15469 return std::make_pair(0U, X86::GR32RegisterClass); 15470 return std::make_pair(0U, X86::GR64RegisterClass); 15471 case 'R': // LEGACY_REGS 15472 if (VT == MVT::i8 || VT == MVT::i1) 15473 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15474 if (VT == MVT::i16) 15475 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15476 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15477 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15478 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15479 case 'f': // FP Stack registers. 15480 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15481 // value to the correct fpstack register class. 15482 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15483 return std::make_pair(0U, X86::RFP32RegisterClass); 15484 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15485 return std::make_pair(0U, X86::RFP64RegisterClass); 15486 return std::make_pair(0U, X86::RFP80RegisterClass); 15487 case 'y': // MMX_REGS if MMX allowed. 15488 if (!Subtarget->hasMMX()) break; 15489 return std::make_pair(0U, X86::VR64RegisterClass); 15490 case 'Y': // SSE_REGS if SSE2 allowed 15491 if (!Subtarget->hasSSE2()) break; 15492 // FALL THROUGH. 15493 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15494 if (!Subtarget->hasSSE1()) break; 15495 15496 switch (VT.getSimpleVT().SimpleTy) { 15497 default: break; 15498 // Scalar SSE types. 15499 case MVT::f32: 15500 case MVT::i32: 15501 return std::make_pair(0U, X86::FR32RegisterClass); 15502 case MVT::f64: 15503 case MVT::i64: 15504 return std::make_pair(0U, X86::FR64RegisterClass); 15505 // Vector types. 15506 case MVT::v16i8: 15507 case MVT::v8i16: 15508 case MVT::v4i32: 15509 case MVT::v2i64: 15510 case MVT::v4f32: 15511 case MVT::v2f64: 15512 return std::make_pair(0U, X86::VR128RegisterClass); 15513 // AVX types. 15514 case MVT::v32i8: 15515 case MVT::v16i16: 15516 case MVT::v8i32: 15517 case MVT::v4i64: 15518 case MVT::v8f32: 15519 case MVT::v4f64: 15520 return std::make_pair(0U, X86::VR256RegisterClass); 15521 15522 } 15523 break; 15524 } 15525 } 15526 15527 // Use the default implementation in TargetLowering to convert the register 15528 // constraint into a member of a register class. 15529 std::pair<unsigned, const TargetRegisterClass*> Res; 15530 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15531 15532 // Not found as a standard register? 15533 if (Res.second == 0) { 15534 // Map st(0) -> st(7) -> ST0 15535 if (Constraint.size() == 7 && Constraint[0] == '{' && 15536 tolower(Constraint[1]) == 's' && 15537 tolower(Constraint[2]) == 't' && 15538 Constraint[3] == '(' && 15539 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15540 Constraint[5] == ')' && 15541 Constraint[6] == '}') { 15542 15543 Res.first = X86::ST0+Constraint[4]-'0'; 15544 Res.second = X86::RFP80RegisterClass; 15545 return Res; 15546 } 15547 15548 // GCC allows "st(0)" to be called just plain "st". 15549 if (StringRef("{st}").equals_lower(Constraint)) { 15550 Res.first = X86::ST0; 15551 Res.second = X86::RFP80RegisterClass; 15552 return Res; 15553 } 15554 15555 // flags -> EFLAGS 15556 if (StringRef("{flags}").equals_lower(Constraint)) { 15557 Res.first = X86::EFLAGS; 15558 Res.second = X86::CCRRegisterClass; 15559 return Res; 15560 } 15561 15562 // 'A' means EAX + EDX. 15563 if (Constraint == "A") { 15564 Res.first = X86::EAX; 15565 Res.second = X86::GR32_ADRegisterClass; 15566 return Res; 15567 } 15568 return Res; 15569 } 15570 15571 // Otherwise, check to see if this is a register class of the wrong value 15572 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15573 // turn into {ax},{dx}. 15574 if (Res.second->hasType(VT)) 15575 return Res; // Correct type already, nothing to do. 15576 15577 // All of the single-register GCC register classes map their values onto 15578 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15579 // really want an 8-bit or 32-bit register, map to the appropriate register 15580 // class and return the appropriate register. 15581 if (Res.second == X86::GR16RegisterClass) { 15582 if (VT == MVT::i8) { 15583 unsigned DestReg = 0; 15584 switch (Res.first) { 15585 default: break; 15586 case X86::AX: DestReg = X86::AL; break; 15587 case X86::DX: DestReg = X86::DL; break; 15588 case X86::CX: DestReg = X86::CL; break; 15589 case X86::BX: DestReg = X86::BL; break; 15590 } 15591 if (DestReg) { 15592 Res.first = DestReg; 15593 Res.second = X86::GR8RegisterClass; 15594 } 15595 } else if (VT == MVT::i32) { 15596 unsigned DestReg = 0; 15597 switch (Res.first) { 15598 default: break; 15599 case X86::AX: DestReg = X86::EAX; break; 15600 case X86::DX: DestReg = X86::EDX; break; 15601 case X86::CX: DestReg = X86::ECX; break; 15602 case X86::BX: DestReg = X86::EBX; break; 15603 case X86::SI: DestReg = X86::ESI; break; 15604 case X86::DI: DestReg = X86::EDI; break; 15605 case X86::BP: DestReg = X86::EBP; break; 15606 case X86::SP: DestReg = X86::ESP; break; 15607 } 15608 if (DestReg) { 15609 Res.first = DestReg; 15610 Res.second = X86::GR32RegisterClass; 15611 } 15612 } else if (VT == MVT::i64) { 15613 unsigned DestReg = 0; 15614 switch (Res.first) { 15615 default: break; 15616 case X86::AX: DestReg = X86::RAX; break; 15617 case X86::DX: DestReg = X86::RDX; break; 15618 case X86::CX: DestReg = X86::RCX; break; 15619 case X86::BX: DestReg = X86::RBX; break; 15620 case X86::SI: DestReg = X86::RSI; break; 15621 case X86::DI: DestReg = X86::RDI; break; 15622 case X86::BP: DestReg = X86::RBP; break; 15623 case X86::SP: DestReg = X86::RSP; break; 15624 } 15625 if (DestReg) { 15626 Res.first = DestReg; 15627 Res.second = X86::GR64RegisterClass; 15628 } 15629 } 15630 } else if (Res.second == X86::FR32RegisterClass || 15631 Res.second == X86::FR64RegisterClass || 15632 Res.second == X86::VR128RegisterClass) { 15633 // Handle references to XMM physical registers that got mapped into the 15634 // wrong class. This can happen with constraints like {xmm0} where the 15635 // target independent register mapper will just pick the first match it can 15636 // find, ignoring the required type. 15637 if (VT == MVT::f32) 15638 Res.second = X86::FR32RegisterClass; 15639 else if (VT == MVT::f64) 15640 Res.second = X86::FR64RegisterClass; 15641 else if (X86::VR128RegisterClass->hasType(VT)) 15642 Res.second = X86::VR128RegisterClass; 15643 } 15644 15645 return Res; 15646} 15647