X86ISelLowering.cpp revision 5b8a1db7ea6510a2589f710d50754599da742de9
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VariadicFunction.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetOptions.h" 55#include <bitset> 56using namespace llvm; 57using namespace dwarf; 58 59STATISTIC(NumTailCalls, "Number of tail calls"); 60 61static cl::opt<bool> UseRegMask("x86-use-regmask", 62 cl::desc("Use register masks for x86 calls")); 63 64// Forward declarations. 65static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 66 SDValue V2); 67 68/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 69/// sets things up to match to an AVX VEXTRACTF128 instruction or a 70/// simple subregister reference. Idx is an index in the 128 bits we 71/// want. It need not be aligned to a 128-bit bounday. That makes 72/// lowering EXTRACT_VECTOR_ELT operations easier. 73static SDValue Extract128BitVector(SDValue Vec, 74 SDValue Idx, 75 SelectionDAG &DAG, 76 DebugLoc dl) { 77 EVT VT = Vec.getValueType(); 78 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 79 EVT ElVT = VT.getVectorElementType(); 80 int Factor = VT.getSizeInBits()/128; 81 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 82 VT.getVectorNumElements()/Factor); 83 84 // Extract from UNDEF is UNDEF. 85 if (Vec.getOpcode() == ISD::UNDEF) 86 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 87 88 if (isa<ConstantSDNode>(Idx)) { 89 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 90 91 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 92 // we can match to VEXTRACTF128. 93 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 94 95 // This is the index of the first element of the 128-bit chunk 96 // we want. 97 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 98 * ElemsPerChunk); 99 100 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 101 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 102 VecIdx); 103 104 return Result; 105 } 106 107 return SDValue(); 108} 109 110/// Generate a DAG to put 128-bits into a vector > 128 bits. This 111/// sets things up to match to an AVX VINSERTF128 instruction or a 112/// simple superregister reference. Idx is an index in the 128 bits 113/// we want. It need not be aligned to a 128-bit bounday. That makes 114/// lowering INSERT_VECTOR_ELT operations easier. 115static SDValue Insert128BitVector(SDValue Result, 116 SDValue Vec, 117 SDValue Idx, 118 SelectionDAG &DAG, 119 DebugLoc dl) { 120 if (isa<ConstantSDNode>(Idx)) { 121 EVT VT = Vec.getValueType(); 122 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 123 124 EVT ElVT = VT.getVectorElementType(); 125 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 126 EVT ResultVT = Result.getValueType(); 127 128 // Insert the relevant 128 bits. 129 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 130 131 // This is the index of the first element of the 128-bit chunk 132 // we want. 133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 134 * ElemsPerChunk); 135 136 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 137 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 138 VecIdx); 139 return Result; 140 } 141 142 return SDValue(); 143} 144 145static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 146 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 147 bool is64Bit = Subtarget->is64Bit(); 148 149 if (Subtarget->isTargetEnvMacho()) { 150 if (is64Bit) 151 return new X8664_MachoTargetObjectFile(); 152 return new TargetLoweringObjectFileMachO(); 153 } 154 155 if (Subtarget->isTargetELF()) 156 return new TargetLoweringObjectFileELF(); 157 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 158 return new TargetLoweringObjectFileCOFF(); 159 llvm_unreachable("unknown subtarget type"); 160} 161 162X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 163 : TargetLowering(TM, createTLOF(TM)) { 164 Subtarget = &TM.getSubtarget<X86Subtarget>(); 165 X86ScalarSSEf64 = Subtarget->hasSSE2(); 166 X86ScalarSSEf32 = Subtarget->hasSSE1(); 167 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 168 169 RegInfo = TM.getRegisterInfo(); 170 TD = getTargetData(); 171 172 // Set up the TargetLowering object. 173 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 174 175 // X86 is weird, it always uses i8 for shift amounts and setcc results. 176 setBooleanContents(ZeroOrOneBooleanContent); 177 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 178 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 179 180 // For 64-bit since we have so many registers use the ILP scheduler, for 181 // 32-bit code use the register pressure specific scheduling. 182 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 183 if (Subtarget->is64Bit()) 184 setSchedulingPreference(Sched::ILP); 185 else if (Subtarget->isAtom()) 186 setSchedulingPreference(Sched::Hybrid); 187 else 188 setSchedulingPreference(Sched::RegPressure); 189 setStackPointerRegisterToSaveRestore(X86StackPtr); 190 191 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 192 // Setup Windows compiler runtime calls. 193 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 194 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 195 setLibcallName(RTLIB::SREM_I64, "_allrem"); 196 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 197 setLibcallName(RTLIB::MUL_I64, "_allmul"); 198 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 199 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 200 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 201 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 202 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 203 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 206 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 207 } 208 209 if (Subtarget->isTargetDarwin()) { 210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 211 setUseUnderscoreSetJmp(false); 212 setUseUnderscoreLongJmp(false); 213 } else if (Subtarget->isTargetMingw()) { 214 // MS runtime is weird: it exports _setjmp, but longjmp! 215 setUseUnderscoreSetJmp(true); 216 setUseUnderscoreLongJmp(false); 217 } else { 218 setUseUnderscoreSetJmp(true); 219 setUseUnderscoreLongJmp(true); 220 } 221 222 // Set up the register classes. 223 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 224 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 225 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 226 if (Subtarget->is64Bit()) 227 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 228 229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 230 231 // We don't accept any truncstore of integer registers. 232 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 233 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 235 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 237 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 238 239 // SETOEQ and SETUNE require checking two conditions. 240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 246 247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 248 // operation. 249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 252 253 if (Subtarget->is64Bit()) { 254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 256 } else if (!TM.Options.UseSoftFloat) { 257 // We have an algorithm for SSE2->double, and we turn this into a 258 // 64-bit FILD followed by conditional FADD for other targets. 259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 260 // We have an algorithm for SSE2, and we turn this into a 64-bit 261 // FILD for other targets. 262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 263 } 264 265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 266 // this operation. 267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 269 270 if (!TM.Options.UseSoftFloat) { 271 // SSE has no i16 to fp conversion, only i32 272 if (X86ScalarSSEf32) { 273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 274 // f32 and f64 cases are Legal, f80 case is not 275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 276 } else { 277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 279 } 280 } else { 281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 283 } 284 285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 286 // are Legal, f80 is custom lowered. 287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 289 290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 291 // this operation. 292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 294 295 if (X86ScalarSSEf32) { 296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 297 // f32 and f64 cases are Legal, f80 case is not 298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 299 } else { 300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 302 } 303 304 // Handle FP_TO_UINT by promoting the destination to a larger signed 305 // conversion. 306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 309 310 if (Subtarget->is64Bit()) { 311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 313 } else if (!TM.Options.UseSoftFloat) { 314 // Since AVX is a superset of SSE3, only check for SSE here. 315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 316 // Expand FP_TO_UINT into a select. 317 // FIXME: We would like to use a Custom expander here eventually to do 318 // the optimal thing for SSE vs. the default expansion in the legalizer. 319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 320 else 321 // With SSE3 we can use fisttpll to convert to a signed i64; without 322 // SSE, we're stuck with a fistpll. 323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 324 } 325 326 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 327 if (!X86ScalarSSEf64) { 328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 330 if (Subtarget->is64Bit()) { 331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 332 // Without SSE, i64->f64 goes through memory. 333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 334 } 335 } 336 337 // Scalar integer divide and remainder are lowered to use operations that 338 // produce two results, to match the available instructions. This exposes 339 // the two-result form to trivial CSE, which is able to combine x/y and x%y 340 // into a single instruction. 341 // 342 // Scalar integer multiply-high is also lowered to use two-result 343 // operations, to match the available instructions. However, plain multiply 344 // (low) operations are left as Legal, as there are single-result 345 // instructions for this in x86. Using the two-result multiply instructions 346 // when both high and low results are needed must be arranged by dagcombine. 347 for (unsigned i = 0, e = 4; i != e; ++i) { 348 MVT VT = IntVTs[i]; 349 setOperationAction(ISD::MULHS, VT, Expand); 350 setOperationAction(ISD::MULHU, VT, Expand); 351 setOperationAction(ISD::SDIV, VT, Expand); 352 setOperationAction(ISD::UDIV, VT, Expand); 353 setOperationAction(ISD::SREM, VT, Expand); 354 setOperationAction(ISD::UREM, VT, Expand); 355 356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 357 setOperationAction(ISD::ADDC, VT, Custom); 358 setOperationAction(ISD::ADDE, VT, Custom); 359 setOperationAction(ISD::SUBC, VT, Custom); 360 setOperationAction(ISD::SUBE, VT, Custom); 361 } 362 363 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 364 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 365 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 367 if (Subtarget->is64Bit()) 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 373 setOperationAction(ISD::FREM , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f64 , Expand); 375 setOperationAction(ISD::FREM , MVT::f80 , Expand); 376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 377 378 // Promote the i8 variants and force them on up to i32 which has a shorter 379 // encoding. 380 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 381 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 382 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 383 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 384 if (Subtarget->hasBMI()) { 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 387 if (Subtarget->is64Bit()) 388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 389 } else { 390 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 391 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 392 if (Subtarget->is64Bit()) 393 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 394 } 395 396 if (Subtarget->hasLZCNT()) { 397 // When promoting the i8 variants, force them to i32 for a shorter 398 // encoding. 399 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 400 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 402 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 405 if (Subtarget->is64Bit()) 406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 407 } else { 408 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 409 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 410 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 414 if (Subtarget->is64Bit()) { 415 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 416 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 417 } 418 } 419 420 if (Subtarget->hasPOPCNT()) { 421 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 422 } else { 423 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 424 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 425 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 426 if (Subtarget->is64Bit()) 427 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 428 } 429 430 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 431 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 432 433 // These should be promoted to a larger select which is supported. 434 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 435 // X86 wants to expand cmov itself. 436 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 437 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 438 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 439 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 440 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 441 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 442 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 443 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 444 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 445 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 446 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 447 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 448 if (Subtarget->is64Bit()) { 449 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 450 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 451 } 452 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 453 454 // Darwin ABI issue. 455 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 456 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 457 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 458 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 459 if (Subtarget->is64Bit()) 460 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 461 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 462 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 463 if (Subtarget->is64Bit()) { 464 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 465 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 466 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 467 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 468 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 469 } 470 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 471 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 472 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 473 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 474 if (Subtarget->is64Bit()) { 475 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 476 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 477 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 478 } 479 480 if (Subtarget->hasSSE1()) 481 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 482 483 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 484 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 485 486 // On X86 and X86-64, atomic operations are lowered to locked instructions. 487 // Locked instructions, in turn, have implicit fence semantics (all memory 488 // operations are flushed before issuing the locked instruction, and they 489 // are not buffered), so we can fold away the common pattern of 490 // fence-atomic-fence. 491 setShouldFoldAtomicFences(true); 492 493 // Expand certain atomics 494 for (unsigned i = 0, e = 4; i != e; ++i) { 495 MVT VT = IntVTs[i]; 496 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 497 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 498 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 499 } 500 501 if (!Subtarget->is64Bit()) { 502 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 503 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 507 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 508 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 509 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 510 } 511 512 if (Subtarget->hasCmpxchg16b()) { 513 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 514 } 515 516 // FIXME - use subtarget debug flags 517 if (!Subtarget->isTargetDarwin() && 518 !Subtarget->isTargetELF() && 519 !Subtarget->isTargetCygMing()) { 520 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 521 } 522 523 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 524 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 526 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 527 if (Subtarget->is64Bit()) { 528 setExceptionPointerRegister(X86::RAX); 529 setExceptionSelectorRegister(X86::RDX); 530 } else { 531 setExceptionPointerRegister(X86::EAX); 532 setExceptionSelectorRegister(X86::EDX); 533 } 534 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 536 537 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 538 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 539 540 setOperationAction(ISD::TRAP, MVT::Other, Legal); 541 542 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 543 setOperationAction(ISD::VASTART , MVT::Other, Custom); 544 setOperationAction(ISD::VAEND , MVT::Other, Expand); 545 if (Subtarget->is64Bit()) { 546 setOperationAction(ISD::VAARG , MVT::Other, Custom); 547 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 548 } else { 549 setOperationAction(ISD::VAARG , MVT::Other, Expand); 550 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 551 } 552 553 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 554 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 555 556 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 558 MVT::i64 : MVT::i32, Custom); 559 else if (TM.Options.EnableSegmentedStacks) 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Custom); 562 else 563 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 564 MVT::i64 : MVT::i32, Expand); 565 566 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 567 // f32 and f64 use SSE. 568 // Set up the FP register classes. 569 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 570 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 571 572 // Use ANDPD to simulate FABS. 573 setOperationAction(ISD::FABS , MVT::f64, Custom); 574 setOperationAction(ISD::FABS , MVT::f32, Custom); 575 576 // Use XORP to simulate FNEG. 577 setOperationAction(ISD::FNEG , MVT::f64, Custom); 578 setOperationAction(ISD::FNEG , MVT::f32, Custom); 579 580 // Use ANDPD and ORPD to simulate FCOPYSIGN. 581 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 582 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 583 584 // Lower this to FGETSIGNx86 plus an AND. 585 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 586 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 587 588 // We don't support sin/cos/fmod 589 setOperationAction(ISD::FSIN , MVT::f64, Expand); 590 setOperationAction(ISD::FCOS , MVT::f64, Expand); 591 setOperationAction(ISD::FSIN , MVT::f32, Expand); 592 setOperationAction(ISD::FCOS , MVT::f32, Expand); 593 594 // Expand FP immediates into loads from the stack, except for the special 595 // cases we handle. 596 addLegalFPImmediate(APFloat(+0.0)); // xorpd 597 addLegalFPImmediate(APFloat(+0.0f)); // xorps 598 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 599 // Use SSE for f32, x87 for f64. 600 // Set up the FP register classes. 601 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 602 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 603 604 // Use ANDPS to simulate FABS. 605 setOperationAction(ISD::FABS , MVT::f32, Custom); 606 607 // Use XORP to simulate FNEG. 608 setOperationAction(ISD::FNEG , MVT::f32, Custom); 609 610 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 611 612 // Use ANDPS and ORPS to simulate FCOPYSIGN. 613 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 614 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 615 616 // We don't support sin/cos/fmod 617 setOperationAction(ISD::FSIN , MVT::f32, Expand); 618 setOperationAction(ISD::FCOS , MVT::f32, Expand); 619 620 // Special cases we handle for FP constants. 621 addLegalFPImmediate(APFloat(+0.0f)); // xorps 622 addLegalFPImmediate(APFloat(+0.0)); // FLD0 623 addLegalFPImmediate(APFloat(+1.0)); // FLD1 624 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 625 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 626 627 if (!TM.Options.UnsafeFPMath) { 628 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 629 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 630 } 631 } else if (!TM.Options.UseSoftFloat) { 632 // f32 and f64 in x87. 633 // Set up the FP register classes. 634 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 635 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 636 637 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 638 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 639 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 640 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 641 642 if (!TM.Options.UnsafeFPMath) { 643 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 644 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 645 } 646 addLegalFPImmediate(APFloat(+0.0)); // FLD0 647 addLegalFPImmediate(APFloat(+1.0)); // FLD1 648 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 649 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 650 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 651 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 652 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 653 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 654 } 655 656 // We don't support FMA. 657 setOperationAction(ISD::FMA, MVT::f64, Expand); 658 setOperationAction(ISD::FMA, MVT::f32, Expand); 659 660 // Long double always uses X87. 661 if (!TM.Options.UseSoftFloat) { 662 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 663 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 664 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 665 { 666 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 667 addLegalFPImmediate(TmpFlt); // FLD0 668 TmpFlt.changeSign(); 669 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 670 671 bool ignored; 672 APFloat TmpFlt2(+1.0); 673 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 674 &ignored); 675 addLegalFPImmediate(TmpFlt2); // FLD1 676 TmpFlt2.changeSign(); 677 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 678 } 679 680 if (!TM.Options.UnsafeFPMath) { 681 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 682 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 683 } 684 685 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 686 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 687 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 688 setOperationAction(ISD::FRINT, MVT::f80, Expand); 689 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 690 setOperationAction(ISD::FMA, MVT::f80, Expand); 691 } 692 693 // Always use a library call for pow. 694 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 695 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 696 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 697 698 setOperationAction(ISD::FLOG, MVT::f80, Expand); 699 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 700 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 701 setOperationAction(ISD::FEXP, MVT::f80, Expand); 702 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 703 704 // First set operation action for all vector types to either promote 705 // (for widening) or expand (for scalarization). Then we will selectively 706 // turn on ones that can be effectively codegen'd. 707 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 708 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 709 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 724 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 726 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 727 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 761 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 766 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 767 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 768 setTruncStoreAction((MVT::SimpleValueType)VT, 769 (MVT::SimpleValueType)InnerVT, Expand); 770 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 771 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 772 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 773 } 774 775 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 776 // with -msoft-float, disable use of MMX as well. 777 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 778 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 779 // No operations on x86mmx supported, everything uses intrinsics. 780 } 781 782 // MMX-sized vectors (other than x86mmx) are expected to be expanded 783 // into smaller operations. 784 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 785 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 786 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 787 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 788 setOperationAction(ISD::AND, MVT::v8i8, Expand); 789 setOperationAction(ISD::AND, MVT::v4i16, Expand); 790 setOperationAction(ISD::AND, MVT::v2i32, Expand); 791 setOperationAction(ISD::AND, MVT::v1i64, Expand); 792 setOperationAction(ISD::OR, MVT::v8i8, Expand); 793 setOperationAction(ISD::OR, MVT::v4i16, Expand); 794 setOperationAction(ISD::OR, MVT::v2i32, Expand); 795 setOperationAction(ISD::OR, MVT::v1i64, Expand); 796 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 797 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 798 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 799 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 805 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 806 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 807 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 808 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 809 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 810 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 811 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 812 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 813 814 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 815 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 816 817 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 818 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 819 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 820 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 821 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 822 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 823 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 824 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 825 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 827 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 828 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 829 } 830 831 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 832 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 833 834 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 835 // registers cannot be used even for integer operations. 836 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 837 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 838 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 839 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 840 841 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 842 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 843 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 844 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 845 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 846 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 847 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 848 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 849 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 850 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 851 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 852 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 853 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 854 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 855 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 856 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 857 858 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 859 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 860 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 861 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 862 863 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 865 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 868 869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 874 875 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 876 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 877 EVT VT = (MVT::SimpleValueType)i; 878 // Do not attempt to custom lower non-power-of-2 vectors 879 if (!isPowerOf2_32(VT.getVectorNumElements())) 880 continue; 881 // Do not attempt to custom lower non-128-bit vectors 882 if (!VT.is128BitVector()) 883 continue; 884 setOperationAction(ISD::BUILD_VECTOR, 885 VT.getSimpleVT().SimpleTy, Custom); 886 setOperationAction(ISD::VECTOR_SHUFFLE, 887 VT.getSimpleVT().SimpleTy, Custom); 888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 889 VT.getSimpleVT().SimpleTy, Custom); 890 } 891 892 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 894 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 897 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 898 899 if (Subtarget->is64Bit()) { 900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 902 } 903 904 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 905 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 906 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 907 EVT VT = SVT; 908 909 // Do not attempt to promote non-128-bit vectors 910 if (!VT.is128BitVector()) 911 continue; 912 913 setOperationAction(ISD::AND, SVT, Promote); 914 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 915 setOperationAction(ISD::OR, SVT, Promote); 916 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 917 setOperationAction(ISD::XOR, SVT, Promote); 918 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 919 setOperationAction(ISD::LOAD, SVT, Promote); 920 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 921 setOperationAction(ISD::SELECT, SVT, Promote); 922 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 923 } 924 925 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 926 927 // Custom lower v2i64 and v2f64 selects. 928 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 929 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 930 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 931 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 932 933 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 934 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 935 } 936 937 if (Subtarget->hasSSE41()) { 938 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 939 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 940 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 941 setOperationAction(ISD::FRINT, MVT::f32, Legal); 942 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 943 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 944 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 945 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 946 setOperationAction(ISD::FRINT, MVT::f64, Legal); 947 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 948 949 // FIXME: Do we need to handle scalar-to-vector here? 950 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 951 952 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 953 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 954 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 955 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 956 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 957 958 // i8 and i16 vectors are custom , because the source register and source 959 // source memory operand types are not the same width. f32 vectors are 960 // custom since the immediate controlling the insert encodes additional 961 // information. 962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 966 967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 971 972 // FIXME: these should be Legal but thats only for the case where 973 // the index is constant. For now custom expand to deal with that. 974 if (Subtarget->is64Bit()) { 975 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 977 } 978 } 979 980 if (Subtarget->hasSSE2()) { 981 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 982 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 983 984 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 985 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 986 987 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 988 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 989 990 if (Subtarget->hasAVX2()) { 991 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 992 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 993 994 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 995 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 996 997 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 998 } else { 999 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1000 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1001 1002 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1003 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1004 1005 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1006 } 1007 } 1008 1009 if (Subtarget->hasSSE42()) 1010 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1011 1012 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1013 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1014 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1015 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1016 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1017 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1018 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1019 1020 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1021 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1022 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1023 1024 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1025 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1027 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1028 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1029 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1030 1031 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1032 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1034 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1035 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1036 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1037 1038 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1039 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1040 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1041 1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1048 1049 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1050 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1051 1052 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1056 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1057 1058 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1059 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1060 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1061 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1062 1063 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1064 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1065 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1066 1067 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1068 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1069 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1070 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1071 1072 if (Subtarget->hasAVX2()) { 1073 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1074 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1075 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1076 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1077 1078 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1079 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1080 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1081 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1082 1083 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1084 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1085 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1086 // Don't lower v32i8 because there is no 128-bit byte mul 1087 1088 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1089 1090 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1091 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1092 1093 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1094 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1095 1096 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1097 } else { 1098 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1099 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1100 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1101 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1102 1103 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1104 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1105 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1106 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1107 1108 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1109 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1110 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1111 // Don't lower v32i8 because there is no 128-bit byte mul 1112 1113 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1114 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1115 1116 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1117 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1118 1119 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1120 } 1121 1122 // Custom lower several nodes for 256-bit types. 1123 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1124 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1125 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1126 EVT VT = SVT; 1127 1128 // Extract subvector is special because the value type 1129 // (result) is 128-bit but the source is 256-bit wide. 1130 if (VT.is128BitVector()) 1131 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1132 1133 // Do not attempt to custom lower other non-256-bit vectors 1134 if (!VT.is256BitVector()) 1135 continue; 1136 1137 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1138 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1139 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1141 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1142 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1143 } 1144 1145 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1146 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1147 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1148 EVT VT = SVT; 1149 1150 // Do not attempt to promote non-256-bit vectors 1151 if (!VT.is256BitVector()) 1152 continue; 1153 1154 setOperationAction(ISD::AND, SVT, Promote); 1155 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1156 setOperationAction(ISD::OR, SVT, Promote); 1157 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1158 setOperationAction(ISD::XOR, SVT, Promote); 1159 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1160 setOperationAction(ISD::LOAD, SVT, Promote); 1161 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1162 setOperationAction(ISD::SELECT, SVT, Promote); 1163 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1164 } 1165 } 1166 1167 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1168 // of this type with custom code. 1169 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1170 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1171 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1172 Custom); 1173 } 1174 1175 // We want to custom lower some of our intrinsics. 1176 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1177 1178 1179 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1180 // handle type legalization for these operations here. 1181 // 1182 // FIXME: We really should do custom legalization for addition and 1183 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1184 // than generic legalization for 64-bit multiplication-with-overflow, though. 1185 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1186 // Add/Sub/Mul with overflow operations are custom lowered. 1187 MVT VT = IntVTs[i]; 1188 setOperationAction(ISD::SADDO, VT, Custom); 1189 setOperationAction(ISD::UADDO, VT, Custom); 1190 setOperationAction(ISD::SSUBO, VT, Custom); 1191 setOperationAction(ISD::USUBO, VT, Custom); 1192 setOperationAction(ISD::SMULO, VT, Custom); 1193 setOperationAction(ISD::UMULO, VT, Custom); 1194 } 1195 1196 // There are no 8-bit 3-address imul/mul instructions 1197 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1198 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1199 1200 if (!Subtarget->is64Bit()) { 1201 // These libcalls are not available in 32-bit. 1202 setLibcallName(RTLIB::SHL_I128, 0); 1203 setLibcallName(RTLIB::SRL_I128, 0); 1204 setLibcallName(RTLIB::SRA_I128, 0); 1205 } 1206 1207 // We have target-specific dag combine patterns for the following nodes: 1208 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1209 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1210 setTargetDAGCombine(ISD::VSELECT); 1211 setTargetDAGCombine(ISD::SELECT); 1212 setTargetDAGCombine(ISD::SHL); 1213 setTargetDAGCombine(ISD::SRA); 1214 setTargetDAGCombine(ISD::SRL); 1215 setTargetDAGCombine(ISD::OR); 1216 setTargetDAGCombine(ISD::AND); 1217 setTargetDAGCombine(ISD::ADD); 1218 setTargetDAGCombine(ISD::FADD); 1219 setTargetDAGCombine(ISD::FSUB); 1220 setTargetDAGCombine(ISD::SUB); 1221 setTargetDAGCombine(ISD::LOAD); 1222 setTargetDAGCombine(ISD::STORE); 1223 setTargetDAGCombine(ISD::ZERO_EXTEND); 1224 setTargetDAGCombine(ISD::SIGN_EXTEND); 1225 setTargetDAGCombine(ISD::TRUNCATE); 1226 setTargetDAGCombine(ISD::SINT_TO_FP); 1227 if (Subtarget->is64Bit()) 1228 setTargetDAGCombine(ISD::MUL); 1229 if (Subtarget->hasBMI()) 1230 setTargetDAGCombine(ISD::XOR); 1231 1232 computeRegisterProperties(); 1233 1234 // On Darwin, -Os means optimize for size without hurting performance, 1235 // do not reduce the limit. 1236 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1237 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1238 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1239 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1240 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1241 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1242 setPrefLoopAlignment(4); // 2^4 bytes. 1243 benefitFromCodePlacementOpt = true; 1244 1245 setPrefFunctionAlignment(4); // 2^4 bytes. 1246} 1247 1248 1249EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1250 if (!VT.isVector()) return MVT::i8; 1251 return VT.changeVectorElementTypeToInteger(); 1252} 1253 1254 1255/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1256/// the desired ByVal argument alignment. 1257static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1258 if (MaxAlign == 16) 1259 return; 1260 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1261 if (VTy->getBitWidth() == 128) 1262 MaxAlign = 16; 1263 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1264 unsigned EltAlign = 0; 1265 getMaxByValAlign(ATy->getElementType(), EltAlign); 1266 if (EltAlign > MaxAlign) 1267 MaxAlign = EltAlign; 1268 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1269 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1270 unsigned EltAlign = 0; 1271 getMaxByValAlign(STy->getElementType(i), EltAlign); 1272 if (EltAlign > MaxAlign) 1273 MaxAlign = EltAlign; 1274 if (MaxAlign == 16) 1275 break; 1276 } 1277 } 1278 return; 1279} 1280 1281/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1282/// function arguments in the caller parameter area. For X86, aggregates 1283/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1284/// are at 4-byte boundaries. 1285unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1286 if (Subtarget->is64Bit()) { 1287 // Max of 8 and alignment of type. 1288 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1289 if (TyAlign > 8) 1290 return TyAlign; 1291 return 8; 1292 } 1293 1294 unsigned Align = 4; 1295 if (Subtarget->hasSSE1()) 1296 getMaxByValAlign(Ty, Align); 1297 return Align; 1298} 1299 1300/// getOptimalMemOpType - Returns the target specific optimal type for load 1301/// and store operations as a result of memset, memcpy, and memmove 1302/// lowering. If DstAlign is zero that means it's safe to destination 1303/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1304/// means there isn't a need to check it against alignment requirement, 1305/// probably because the source does not need to be loaded. If 1306/// 'IsZeroVal' is true, that means it's safe to return a 1307/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1308/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1309/// constant so it does not need to be loaded. 1310/// It returns EVT::Other if the type should be determined using generic 1311/// target-independent logic. 1312EVT 1313X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1314 unsigned DstAlign, unsigned SrcAlign, 1315 bool IsZeroVal, 1316 bool MemcpyStrSrc, 1317 MachineFunction &MF) const { 1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1319 // linux. This is because the stack realignment code can't handle certain 1320 // cases like PR2962. This should be removed when PR2962 is fixed. 1321 const Function *F = MF.getFunction(); 1322 if (IsZeroVal && 1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1324 if (Size >= 16 && 1325 (Subtarget->isUnalignedMemAccessFast() || 1326 ((DstAlign == 0 || DstAlign >= 16) && 1327 (SrcAlign == 0 || SrcAlign >= 16))) && 1328 Subtarget->getStackAlignment() >= 16) { 1329 if (Subtarget->getStackAlignment() >= 32) { 1330 if (Subtarget->hasAVX2()) 1331 return MVT::v8i32; 1332 if (Subtarget->hasAVX()) 1333 return MVT::v8f32; 1334 } 1335 if (Subtarget->hasSSE2()) 1336 return MVT::v4i32; 1337 if (Subtarget->hasSSE1()) 1338 return MVT::v4f32; 1339 } else if (!MemcpyStrSrc && Size >= 8 && 1340 !Subtarget->is64Bit() && 1341 Subtarget->getStackAlignment() >= 8 && 1342 Subtarget->hasSSE2()) { 1343 // Do not use f64 to lower memcpy if source is string constant. It's 1344 // better to use i32 to avoid the loads. 1345 return MVT::f64; 1346 } 1347 } 1348 if (Subtarget->is64Bit() && Size >= 8) 1349 return MVT::i64; 1350 return MVT::i32; 1351} 1352 1353/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1354/// current function. The returned value is a member of the 1355/// MachineJumpTableInfo::JTEntryKind enum. 1356unsigned X86TargetLowering::getJumpTableEncoding() const { 1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1358 // symbol. 1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1360 Subtarget->isPICStyleGOT()) 1361 return MachineJumpTableInfo::EK_Custom32; 1362 1363 // Otherwise, use the normal jump table encoding heuristics. 1364 return TargetLowering::getJumpTableEncoding(); 1365} 1366 1367const MCExpr * 1368X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1369 const MachineBasicBlock *MBB, 1370 unsigned uid,MCContext &Ctx) const{ 1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1372 Subtarget->isPICStyleGOT()); 1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1374 // entries. 1375 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1376 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1377} 1378 1379/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1380/// jumptable. 1381SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1382 SelectionDAG &DAG) const { 1383 if (!Subtarget->is64Bit()) 1384 // This doesn't have DebugLoc associated with it, but is not really the 1385 // same as a Register. 1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1387 return Table; 1388} 1389 1390/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1391/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1392/// MCExpr. 1393const MCExpr *X86TargetLowering:: 1394getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1395 MCContext &Ctx) const { 1396 // X86-64 uses RIP relative addressing based on the jump table label. 1397 if (Subtarget->isPICStyleRIPRel()) 1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1399 1400 // Otherwise, the reference is relative to the PIC base. 1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1402} 1403 1404// FIXME: Why this routine is here? Move to RegInfo! 1405std::pair<const TargetRegisterClass*, uint8_t> 1406X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1407 const TargetRegisterClass *RRC = 0; 1408 uint8_t Cost = 1; 1409 switch (VT.getSimpleVT().SimpleTy) { 1410 default: 1411 return TargetLowering::findRepresentativeClass(VT); 1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1413 RRC = (Subtarget->is64Bit() 1414 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1415 break; 1416 case MVT::x86mmx: 1417 RRC = X86::VR64RegisterClass; 1418 break; 1419 case MVT::f32: case MVT::f64: 1420 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1421 case MVT::v4f32: case MVT::v2f64: 1422 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1423 case MVT::v4f64: 1424 RRC = X86::VR128RegisterClass; 1425 break; 1426 } 1427 return std::make_pair(RRC, Cost); 1428} 1429 1430bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1431 unsigned &Offset) const { 1432 if (!Subtarget->isTargetLinux()) 1433 return false; 1434 1435 if (Subtarget->is64Bit()) { 1436 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1437 Offset = 0x28; 1438 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1439 AddressSpace = 256; 1440 else 1441 AddressSpace = 257; 1442 } else { 1443 // %gs:0x14 on i386 1444 Offset = 0x14; 1445 AddressSpace = 256; 1446 } 1447 return true; 1448} 1449 1450 1451//===----------------------------------------------------------------------===// 1452// Return Value Calling Convention Implementation 1453//===----------------------------------------------------------------------===// 1454 1455#include "X86GenCallingConv.inc" 1456 1457bool 1458X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1459 MachineFunction &MF, bool isVarArg, 1460 const SmallVectorImpl<ISD::OutputArg> &Outs, 1461 LLVMContext &Context) const { 1462 SmallVector<CCValAssign, 16> RVLocs; 1463 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1464 RVLocs, Context); 1465 return CCInfo.CheckReturn(Outs, RetCC_X86); 1466} 1467 1468SDValue 1469X86TargetLowering::LowerReturn(SDValue Chain, 1470 CallingConv::ID CallConv, bool isVarArg, 1471 const SmallVectorImpl<ISD::OutputArg> &Outs, 1472 const SmallVectorImpl<SDValue> &OutVals, 1473 DebugLoc dl, SelectionDAG &DAG) const { 1474 MachineFunction &MF = DAG.getMachineFunction(); 1475 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1476 1477 SmallVector<CCValAssign, 16> RVLocs; 1478 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1479 RVLocs, *DAG.getContext()); 1480 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1481 1482 // Add the regs to the liveout set for the function. 1483 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1484 for (unsigned i = 0; i != RVLocs.size(); ++i) 1485 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1486 MRI.addLiveOut(RVLocs[i].getLocReg()); 1487 1488 SDValue Flag; 1489 1490 SmallVector<SDValue, 6> RetOps; 1491 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1492 // Operand #1 = Bytes To Pop 1493 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1494 MVT::i16)); 1495 1496 // Copy the result values into the output registers. 1497 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1498 CCValAssign &VA = RVLocs[i]; 1499 assert(VA.isRegLoc() && "Can only return in registers!"); 1500 SDValue ValToCopy = OutVals[i]; 1501 EVT ValVT = ValToCopy.getValueType(); 1502 1503 // If this is x86-64, and we disabled SSE, we can't return FP values, 1504 // or SSE or MMX vectors. 1505 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1506 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1507 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1508 report_fatal_error("SSE register return with SSE disabled"); 1509 } 1510 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1511 // llvm-gcc has never done it right and no one has noticed, so this 1512 // should be OK for now. 1513 if (ValVT == MVT::f64 && 1514 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1515 report_fatal_error("SSE2 register return with SSE2 disabled"); 1516 1517 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1518 // the RET instruction and handled by the FP Stackifier. 1519 if (VA.getLocReg() == X86::ST0 || 1520 VA.getLocReg() == X86::ST1) { 1521 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1522 // change the value to the FP stack register class. 1523 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1524 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1525 RetOps.push_back(ValToCopy); 1526 // Don't emit a copytoreg. 1527 continue; 1528 } 1529 1530 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1531 // which is returned in RAX / RDX. 1532 if (Subtarget->is64Bit()) { 1533 if (ValVT == MVT::x86mmx) { 1534 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1536 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1537 ValToCopy); 1538 // If we don't have SSE2 available, convert to v4f32 so the generated 1539 // register is legal. 1540 if (!Subtarget->hasSSE2()) 1541 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1542 } 1543 } 1544 } 1545 1546 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1547 Flag = Chain.getValue(1); 1548 } 1549 1550 // The x86-64 ABI for returning structs by value requires that we copy 1551 // the sret argument into %rax for the return. We saved the argument into 1552 // a virtual register in the entry block, so now we copy the value out 1553 // and into %rax. 1554 if (Subtarget->is64Bit() && 1555 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1556 MachineFunction &MF = DAG.getMachineFunction(); 1557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1558 unsigned Reg = FuncInfo->getSRetReturnReg(); 1559 assert(Reg && 1560 "SRetReturnReg should have been set in LowerFormalArguments()."); 1561 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1562 1563 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1564 Flag = Chain.getValue(1); 1565 1566 // RAX now acts like a return value. 1567 MRI.addLiveOut(X86::RAX); 1568 } 1569 1570 RetOps[0] = Chain; // Update chain. 1571 1572 // Add the flag if we have it. 1573 if (Flag.getNode()) 1574 RetOps.push_back(Flag); 1575 1576 return DAG.getNode(X86ISD::RET_FLAG, dl, 1577 MVT::Other, &RetOps[0], RetOps.size()); 1578} 1579 1580bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1581 if (N->getNumValues() != 1) 1582 return false; 1583 if (!N->hasNUsesOfValue(1, 0)) 1584 return false; 1585 1586 SDNode *Copy = *N->use_begin(); 1587 if (Copy->getOpcode() != ISD::CopyToReg && 1588 Copy->getOpcode() != ISD::FP_EXTEND) 1589 return false; 1590 1591 bool HasRet = false; 1592 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1593 UI != UE; ++UI) { 1594 if (UI->getOpcode() != X86ISD::RET_FLAG) 1595 return false; 1596 HasRet = true; 1597 } 1598 1599 return HasRet; 1600} 1601 1602EVT 1603X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1604 ISD::NodeType ExtendKind) const { 1605 MVT ReturnMVT; 1606 // TODO: Is this also valid on 32-bit? 1607 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1608 ReturnMVT = MVT::i8; 1609 else 1610 ReturnMVT = MVT::i32; 1611 1612 EVT MinVT = getRegisterType(Context, ReturnMVT); 1613 return VT.bitsLT(MinVT) ? MinVT : VT; 1614} 1615 1616/// LowerCallResult - Lower the result values of a call into the 1617/// appropriate copies out of appropriate physical registers. 1618/// 1619SDValue 1620X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1621 CallingConv::ID CallConv, bool isVarArg, 1622 const SmallVectorImpl<ISD::InputArg> &Ins, 1623 DebugLoc dl, SelectionDAG &DAG, 1624 SmallVectorImpl<SDValue> &InVals) const { 1625 1626 // Assign locations to each value returned by this call. 1627 SmallVector<CCValAssign, 16> RVLocs; 1628 bool Is64Bit = Subtarget->is64Bit(); 1629 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1630 getTargetMachine(), RVLocs, *DAG.getContext()); 1631 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1632 1633 // Copy all of the result registers out of their specified physreg. 1634 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1635 CCValAssign &VA = RVLocs[i]; 1636 EVT CopyVT = VA.getValVT(); 1637 1638 // If this is x86-64, and we disabled SSE, we can't return FP values 1639 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1640 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1641 report_fatal_error("SSE register return with SSE disabled"); 1642 } 1643 1644 SDValue Val; 1645 1646 // If this is a call to a function that returns an fp value on the floating 1647 // point stack, we must guarantee the the value is popped from the stack, so 1648 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1649 // if the return value is not used. We use the FpPOP_RETVAL instruction 1650 // instead. 1651 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1652 // If we prefer to use the value in xmm registers, copy it out as f80 and 1653 // use a truncate to move it from fp stack reg to xmm reg. 1654 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1655 SDValue Ops[] = { Chain, InFlag }; 1656 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1657 MVT::Other, MVT::Glue, Ops, 2), 1); 1658 Val = Chain.getValue(0); 1659 1660 // Round the f80 to the right size, which also moves it to the appropriate 1661 // xmm register. 1662 if (CopyVT != VA.getValVT()) 1663 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1664 // This truncation won't change the value. 1665 DAG.getIntPtrConstant(1)); 1666 } else { 1667 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1668 CopyVT, InFlag).getValue(1); 1669 Val = Chain.getValue(0); 1670 } 1671 InFlag = Chain.getValue(2); 1672 InVals.push_back(Val); 1673 } 1674 1675 return Chain; 1676} 1677 1678 1679//===----------------------------------------------------------------------===// 1680// C & StdCall & Fast Calling Convention implementation 1681//===----------------------------------------------------------------------===// 1682// StdCall calling convention seems to be standard for many Windows' API 1683// routines and around. It differs from C calling convention just a little: 1684// callee should clean up the stack, not caller. Symbols should be also 1685// decorated in some fancy way :) It doesn't support any vector arguments. 1686// For info on fast calling convention see Fast Calling Convention (tail call) 1687// implementation LowerX86_32FastCCCallTo. 1688 1689/// CallIsStructReturn - Determines whether a call uses struct return 1690/// semantics. 1691static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1692 if (Outs.empty()) 1693 return false; 1694 1695 return Outs[0].Flags.isSRet(); 1696} 1697 1698/// ArgsAreStructReturn - Determines whether a function uses struct 1699/// return semantics. 1700static bool 1701ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1702 if (Ins.empty()) 1703 return false; 1704 1705 return Ins[0].Flags.isSRet(); 1706} 1707 1708/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1709/// by "Src" to address "Dst" with size and alignment information specified by 1710/// the specific parameter attribute. The copy will be passed as a byval 1711/// function parameter. 1712static SDValue 1713CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1714 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1715 DebugLoc dl) { 1716 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1717 1718 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1719 /*isVolatile*/false, /*AlwaysInline=*/true, 1720 MachinePointerInfo(), MachinePointerInfo()); 1721} 1722 1723/// IsTailCallConvention - Return true if the calling convention is one that 1724/// supports tail call optimization. 1725static bool IsTailCallConvention(CallingConv::ID CC) { 1726 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1727} 1728 1729bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1730 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1731 return false; 1732 1733 CallSite CS(CI); 1734 CallingConv::ID CalleeCC = CS.getCallingConv(); 1735 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1736 return false; 1737 1738 return true; 1739} 1740 1741/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1742/// a tailcall target by changing its ABI. 1743static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1744 bool GuaranteedTailCallOpt) { 1745 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1746} 1747 1748SDValue 1749X86TargetLowering::LowerMemArgument(SDValue Chain, 1750 CallingConv::ID CallConv, 1751 const SmallVectorImpl<ISD::InputArg> &Ins, 1752 DebugLoc dl, SelectionDAG &DAG, 1753 const CCValAssign &VA, 1754 MachineFrameInfo *MFI, 1755 unsigned i) const { 1756 // Create the nodes corresponding to a load from this parameter slot. 1757 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1758 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1759 getTargetMachine().Options.GuaranteedTailCallOpt); 1760 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1761 EVT ValVT; 1762 1763 // If value is passed by pointer we have address passed instead of the value 1764 // itself. 1765 if (VA.getLocInfo() == CCValAssign::Indirect) 1766 ValVT = VA.getLocVT(); 1767 else 1768 ValVT = VA.getValVT(); 1769 1770 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1771 // changed with more analysis. 1772 // In case of tail call optimization mark all arguments mutable. Since they 1773 // could be overwritten by lowering of arguments in case of a tail call. 1774 if (Flags.isByVal()) { 1775 unsigned Bytes = Flags.getByValSize(); 1776 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1777 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1778 return DAG.getFrameIndex(FI, getPointerTy()); 1779 } else { 1780 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1781 VA.getLocMemOffset(), isImmutable); 1782 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1783 return DAG.getLoad(ValVT, dl, Chain, FIN, 1784 MachinePointerInfo::getFixedStack(FI), 1785 false, false, false, 0); 1786 } 1787} 1788 1789SDValue 1790X86TargetLowering::LowerFormalArguments(SDValue Chain, 1791 CallingConv::ID CallConv, 1792 bool isVarArg, 1793 const SmallVectorImpl<ISD::InputArg> &Ins, 1794 DebugLoc dl, 1795 SelectionDAG &DAG, 1796 SmallVectorImpl<SDValue> &InVals) 1797 const { 1798 MachineFunction &MF = DAG.getMachineFunction(); 1799 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1800 1801 const Function* Fn = MF.getFunction(); 1802 if (Fn->hasExternalLinkage() && 1803 Subtarget->isTargetCygMing() && 1804 Fn->getName() == "main") 1805 FuncInfo->setForceFramePointer(true); 1806 1807 MachineFrameInfo *MFI = MF.getFrameInfo(); 1808 bool Is64Bit = Subtarget->is64Bit(); 1809 bool IsWindows = Subtarget->isTargetWindows(); 1810 bool IsWin64 = Subtarget->isTargetWin64(); 1811 1812 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1813 "Var args not supported with calling convention fastcc or ghc"); 1814 1815 // Assign locations to all of the incoming arguments. 1816 SmallVector<CCValAssign, 16> ArgLocs; 1817 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1818 ArgLocs, *DAG.getContext()); 1819 1820 // Allocate shadow area for Win64 1821 if (IsWin64) { 1822 CCInfo.AllocateStack(32, 8); 1823 } 1824 1825 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1826 1827 unsigned LastVal = ~0U; 1828 SDValue ArgValue; 1829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1830 CCValAssign &VA = ArgLocs[i]; 1831 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1832 // places. 1833 assert(VA.getValNo() != LastVal && 1834 "Don't support value assigned to multiple locs yet"); 1835 (void)LastVal; 1836 LastVal = VA.getValNo(); 1837 1838 if (VA.isRegLoc()) { 1839 EVT RegVT = VA.getLocVT(); 1840 TargetRegisterClass *RC = NULL; 1841 if (RegVT == MVT::i32) 1842 RC = X86::GR32RegisterClass; 1843 else if (Is64Bit && RegVT == MVT::i64) 1844 RC = X86::GR64RegisterClass; 1845 else if (RegVT == MVT::f32) 1846 RC = X86::FR32RegisterClass; 1847 else if (RegVT == MVT::f64) 1848 RC = X86::FR64RegisterClass; 1849 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1850 RC = X86::VR256RegisterClass; 1851 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1852 RC = X86::VR128RegisterClass; 1853 else if (RegVT == MVT::x86mmx) 1854 RC = X86::VR64RegisterClass; 1855 else 1856 llvm_unreachable("Unknown argument type!"); 1857 1858 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1859 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1860 1861 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1862 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1863 // right size. 1864 if (VA.getLocInfo() == CCValAssign::SExt) 1865 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1866 DAG.getValueType(VA.getValVT())); 1867 else if (VA.getLocInfo() == CCValAssign::ZExt) 1868 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1869 DAG.getValueType(VA.getValVT())); 1870 else if (VA.getLocInfo() == CCValAssign::BCvt) 1871 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1872 1873 if (VA.isExtInLoc()) { 1874 // Handle MMX values passed in XMM regs. 1875 if (RegVT.isVector()) { 1876 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1877 ArgValue); 1878 } else 1879 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1880 } 1881 } else { 1882 assert(VA.isMemLoc()); 1883 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1884 } 1885 1886 // If value is passed via pointer - do a load. 1887 if (VA.getLocInfo() == CCValAssign::Indirect) 1888 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1889 MachinePointerInfo(), false, false, false, 0); 1890 1891 InVals.push_back(ArgValue); 1892 } 1893 1894 // The x86-64 ABI for returning structs by value requires that we copy 1895 // the sret argument into %rax for the return. Save the argument into 1896 // a virtual register so that we can access it from the return points. 1897 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1898 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1899 unsigned Reg = FuncInfo->getSRetReturnReg(); 1900 if (!Reg) { 1901 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1902 FuncInfo->setSRetReturnReg(Reg); 1903 } 1904 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1906 } 1907 1908 unsigned StackSize = CCInfo.getNextStackOffset(); 1909 // Align stack specially for tail calls. 1910 if (FuncIsMadeTailCallSafe(CallConv, 1911 MF.getTarget().Options.GuaranteedTailCallOpt)) 1912 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1913 1914 // If the function takes variable number of arguments, make a frame index for 1915 // the start of the first vararg value... for expansion of llvm.va_start. 1916 if (isVarArg) { 1917 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1918 CallConv != CallingConv::X86_ThisCall)) { 1919 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1920 } 1921 if (Is64Bit) { 1922 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1923 1924 // FIXME: We should really autogenerate these arrays 1925 static const unsigned GPR64ArgRegsWin64[] = { 1926 X86::RCX, X86::RDX, X86::R8, X86::R9 1927 }; 1928 static const unsigned GPR64ArgRegs64Bit[] = { 1929 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1930 }; 1931 static const unsigned XMMArgRegs64Bit[] = { 1932 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1933 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1934 }; 1935 const unsigned *GPR64ArgRegs; 1936 unsigned NumXMMRegs = 0; 1937 1938 if (IsWin64) { 1939 // The XMM registers which might contain var arg parameters are shadowed 1940 // in their paired GPR. So we only need to save the GPR to their home 1941 // slots. 1942 TotalNumIntRegs = 4; 1943 GPR64ArgRegs = GPR64ArgRegsWin64; 1944 } else { 1945 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1946 GPR64ArgRegs = GPR64ArgRegs64Bit; 1947 1948 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1949 TotalNumXMMRegs); 1950 } 1951 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1952 TotalNumIntRegs); 1953 1954 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1955 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1956 "SSE register cannot be used when SSE is disabled!"); 1957 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1958 NoImplicitFloatOps) && 1959 "SSE register cannot be used when SSE is disabled!"); 1960 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1961 !Subtarget->hasSSE1()) 1962 // Kernel mode asks for SSE to be disabled, so don't push them 1963 // on the stack. 1964 TotalNumXMMRegs = 0; 1965 1966 if (IsWin64) { 1967 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1968 // Get to the caller-allocated home save location. Add 8 to account 1969 // for the return address. 1970 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1971 FuncInfo->setRegSaveFrameIndex( 1972 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1973 // Fixup to set vararg frame on shadow area (4 x i64). 1974 if (NumIntRegs < 4) 1975 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1976 } else { 1977 // For X86-64, if there are vararg parameters that are passed via 1978 // registers, then we must store them to their spots on the stack so 1979 // they may be loaded by deferencing the result of va_next. 1980 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1981 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1982 FuncInfo->setRegSaveFrameIndex( 1983 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1984 false)); 1985 } 1986 1987 // Store the integer parameter registers. 1988 SmallVector<SDValue, 8> MemOps; 1989 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1990 getPointerTy()); 1991 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1992 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1993 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1994 DAG.getIntPtrConstant(Offset)); 1995 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1996 X86::GR64RegisterClass); 1997 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1998 SDValue Store = 1999 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2000 MachinePointerInfo::getFixedStack( 2001 FuncInfo->getRegSaveFrameIndex(), Offset), 2002 false, false, 0); 2003 MemOps.push_back(Store); 2004 Offset += 8; 2005 } 2006 2007 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2008 // Now store the XMM (fp + vector) parameter registers. 2009 SmallVector<SDValue, 11> SaveXMMOps; 2010 SaveXMMOps.push_back(Chain); 2011 2012 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2013 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2014 SaveXMMOps.push_back(ALVal); 2015 2016 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2017 FuncInfo->getRegSaveFrameIndex())); 2018 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2019 FuncInfo->getVarArgsFPOffset())); 2020 2021 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2022 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2023 X86::VR128RegisterClass); 2024 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2025 SaveXMMOps.push_back(Val); 2026 } 2027 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2028 MVT::Other, 2029 &SaveXMMOps[0], SaveXMMOps.size())); 2030 } 2031 2032 if (!MemOps.empty()) 2033 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2034 &MemOps[0], MemOps.size()); 2035 } 2036 } 2037 2038 // Some CCs need callee pop. 2039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2040 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2041 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2042 } else { 2043 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2044 // If this is an sret function, the return should pop the hidden pointer. 2045 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2046 ArgsAreStructReturn(Ins)) 2047 FuncInfo->setBytesToPopOnReturn(4); 2048 } 2049 2050 if (!Is64Bit) { 2051 // RegSaveFrameIndex is X86-64 only. 2052 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2053 if (CallConv == CallingConv::X86_FastCall || 2054 CallConv == CallingConv::X86_ThisCall) 2055 // fastcc functions can't have varargs. 2056 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2057 } 2058 2059 FuncInfo->setArgumentStackSize(StackSize); 2060 2061 return Chain; 2062} 2063 2064SDValue 2065X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2066 SDValue StackPtr, SDValue Arg, 2067 DebugLoc dl, SelectionDAG &DAG, 2068 const CCValAssign &VA, 2069 ISD::ArgFlagsTy Flags) const { 2070 unsigned LocMemOffset = VA.getLocMemOffset(); 2071 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2072 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2073 if (Flags.isByVal()) 2074 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2075 2076 return DAG.getStore(Chain, dl, Arg, PtrOff, 2077 MachinePointerInfo::getStack(LocMemOffset), 2078 false, false, 0); 2079} 2080 2081/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2082/// optimization is performed and it is required. 2083SDValue 2084X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2085 SDValue &OutRetAddr, SDValue Chain, 2086 bool IsTailCall, bool Is64Bit, 2087 int FPDiff, DebugLoc dl) const { 2088 // Adjust the Return address stack slot. 2089 EVT VT = getPointerTy(); 2090 OutRetAddr = getReturnAddressFrameIndex(DAG); 2091 2092 // Load the "old" Return address. 2093 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2094 false, false, false, 0); 2095 return SDValue(OutRetAddr.getNode(), 1); 2096} 2097 2098/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2099/// optimization is performed and it is required (FPDiff!=0). 2100static SDValue 2101EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2102 SDValue Chain, SDValue RetAddrFrIdx, 2103 bool Is64Bit, int FPDiff, DebugLoc dl) { 2104 // Store the return address to the appropriate stack slot. 2105 if (!FPDiff) return Chain; 2106 // Calculate the new stack slot for the return address. 2107 int SlotSize = Is64Bit ? 8 : 4; 2108 int NewReturnAddrFI = 2109 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2110 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2111 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2112 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2113 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2114 false, false, 0); 2115 return Chain; 2116} 2117 2118SDValue 2119X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2120 CallingConv::ID CallConv, bool isVarArg, 2121 bool &isTailCall, 2122 const SmallVectorImpl<ISD::OutputArg> &Outs, 2123 const SmallVectorImpl<SDValue> &OutVals, 2124 const SmallVectorImpl<ISD::InputArg> &Ins, 2125 DebugLoc dl, SelectionDAG &DAG, 2126 SmallVectorImpl<SDValue> &InVals) const { 2127 MachineFunction &MF = DAG.getMachineFunction(); 2128 bool Is64Bit = Subtarget->is64Bit(); 2129 bool IsWin64 = Subtarget->isTargetWin64(); 2130 bool IsWindows = Subtarget->isTargetWindows(); 2131 bool IsStructRet = CallIsStructReturn(Outs); 2132 bool IsSibcall = false; 2133 2134 if (MF.getTarget().Options.DisableTailCalls) 2135 isTailCall = false; 2136 2137 if (isTailCall) { 2138 // Check if it's really possible to do a tail call. 2139 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2140 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2141 Outs, OutVals, Ins, DAG); 2142 2143 // Sibcalls are automatically detected tailcalls which do not require 2144 // ABI changes. 2145 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2146 IsSibcall = true; 2147 2148 if (isTailCall) 2149 ++NumTailCalls; 2150 } 2151 2152 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2153 "Var args not supported with calling convention fastcc or ghc"); 2154 2155 // Analyze operands of the call, assigning locations to each operand. 2156 SmallVector<CCValAssign, 16> ArgLocs; 2157 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2158 ArgLocs, *DAG.getContext()); 2159 2160 // Allocate shadow area for Win64 2161 if (IsWin64) { 2162 CCInfo.AllocateStack(32, 8); 2163 } 2164 2165 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2166 2167 // Get a count of how many bytes are to be pushed on the stack. 2168 unsigned NumBytes = CCInfo.getNextStackOffset(); 2169 if (IsSibcall) 2170 // This is a sibcall. The memory operands are available in caller's 2171 // own caller's stack. 2172 NumBytes = 0; 2173 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2174 IsTailCallConvention(CallConv)) 2175 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2176 2177 int FPDiff = 0; 2178 if (isTailCall && !IsSibcall) { 2179 // Lower arguments at fp - stackoffset + fpdiff. 2180 unsigned NumBytesCallerPushed = 2181 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2182 FPDiff = NumBytesCallerPushed - NumBytes; 2183 2184 // Set the delta of movement of the returnaddr stackslot. 2185 // But only set if delta is greater than previous delta. 2186 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2187 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2188 } 2189 2190 if (!IsSibcall) 2191 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2192 2193 SDValue RetAddrFrIdx; 2194 // Load return address for tail calls. 2195 if (isTailCall && FPDiff) 2196 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2197 Is64Bit, FPDiff, dl); 2198 2199 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2200 SmallVector<SDValue, 8> MemOpChains; 2201 SDValue StackPtr; 2202 2203 // Walk the register/memloc assignments, inserting copies/loads. In the case 2204 // of tail call optimization arguments are handle later. 2205 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2206 CCValAssign &VA = ArgLocs[i]; 2207 EVT RegVT = VA.getLocVT(); 2208 SDValue Arg = OutVals[i]; 2209 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2210 bool isByVal = Flags.isByVal(); 2211 2212 // Promote the value if needed. 2213 switch (VA.getLocInfo()) { 2214 default: llvm_unreachable("Unknown loc info!"); 2215 case CCValAssign::Full: break; 2216 case CCValAssign::SExt: 2217 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2218 break; 2219 case CCValAssign::ZExt: 2220 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2221 break; 2222 case CCValAssign::AExt: 2223 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2224 // Special case: passing MMX values in XMM registers. 2225 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2226 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2227 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2228 } else 2229 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2230 break; 2231 case CCValAssign::BCvt: 2232 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2233 break; 2234 case CCValAssign::Indirect: { 2235 // Store the argument. 2236 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2237 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2238 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2239 MachinePointerInfo::getFixedStack(FI), 2240 false, false, 0); 2241 Arg = SpillSlot; 2242 break; 2243 } 2244 } 2245 2246 if (VA.isRegLoc()) { 2247 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2248 if (isVarArg && IsWin64) { 2249 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2250 // shadow reg if callee is a varargs function. 2251 unsigned ShadowReg = 0; 2252 switch (VA.getLocReg()) { 2253 case X86::XMM0: ShadowReg = X86::RCX; break; 2254 case X86::XMM1: ShadowReg = X86::RDX; break; 2255 case X86::XMM2: ShadowReg = X86::R8; break; 2256 case X86::XMM3: ShadowReg = X86::R9; break; 2257 } 2258 if (ShadowReg) 2259 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2260 } 2261 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2262 assert(VA.isMemLoc()); 2263 if (StackPtr.getNode() == 0) 2264 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2265 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2266 dl, DAG, VA, Flags)); 2267 } 2268 } 2269 2270 if (!MemOpChains.empty()) 2271 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2272 &MemOpChains[0], MemOpChains.size()); 2273 2274 // Build a sequence of copy-to-reg nodes chained together with token chain 2275 // and flag operands which copy the outgoing args into registers. 2276 SDValue InFlag; 2277 // Tail call byval lowering might overwrite argument registers so in case of 2278 // tail call optimization the copies to registers are lowered later. 2279 if (!isTailCall) 2280 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2281 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2282 RegsToPass[i].second, InFlag); 2283 InFlag = Chain.getValue(1); 2284 } 2285 2286 if (Subtarget->isPICStyleGOT()) { 2287 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2288 // GOT pointer. 2289 if (!isTailCall) { 2290 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2291 DAG.getNode(X86ISD::GlobalBaseReg, 2292 DebugLoc(), getPointerTy()), 2293 InFlag); 2294 InFlag = Chain.getValue(1); 2295 } else { 2296 // If we are tail calling and generating PIC/GOT style code load the 2297 // address of the callee into ECX. The value in ecx is used as target of 2298 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2299 // for tail calls on PIC/GOT architectures. Normally we would just put the 2300 // address of GOT into ebx and then call target@PLT. But for tail calls 2301 // ebx would be restored (since ebx is callee saved) before jumping to the 2302 // target@PLT. 2303 2304 // Note: The actual moving to ECX is done further down. 2305 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2306 if (G && !G->getGlobal()->hasHiddenVisibility() && 2307 !G->getGlobal()->hasProtectedVisibility()) 2308 Callee = LowerGlobalAddress(Callee, DAG); 2309 else if (isa<ExternalSymbolSDNode>(Callee)) 2310 Callee = LowerExternalSymbol(Callee, DAG); 2311 } 2312 } 2313 2314 if (Is64Bit && isVarArg && !IsWin64) { 2315 // From AMD64 ABI document: 2316 // For calls that may call functions that use varargs or stdargs 2317 // (prototype-less calls or calls to functions containing ellipsis (...) in 2318 // the declaration) %al is used as hidden argument to specify the number 2319 // of SSE registers used. The contents of %al do not need to match exactly 2320 // the number of registers, but must be an ubound on the number of SSE 2321 // registers used and is in the range 0 - 8 inclusive. 2322 2323 // Count the number of XMM registers allocated. 2324 static const unsigned XMMArgRegs[] = { 2325 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2326 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2327 }; 2328 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2329 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2330 && "SSE registers cannot be used when SSE is disabled"); 2331 2332 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2333 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2334 InFlag = Chain.getValue(1); 2335 } 2336 2337 2338 // For tail calls lower the arguments to the 'real' stack slot. 2339 if (isTailCall) { 2340 // Force all the incoming stack arguments to be loaded from the stack 2341 // before any new outgoing arguments are stored to the stack, because the 2342 // outgoing stack slots may alias the incoming argument stack slots, and 2343 // the alias isn't otherwise explicit. This is slightly more conservative 2344 // than necessary, because it means that each store effectively depends 2345 // on every argument instead of just those arguments it would clobber. 2346 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2347 2348 SmallVector<SDValue, 8> MemOpChains2; 2349 SDValue FIN; 2350 int FI = 0; 2351 // Do not flag preceding copytoreg stuff together with the following stuff. 2352 InFlag = SDValue(); 2353 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2354 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2355 CCValAssign &VA = ArgLocs[i]; 2356 if (VA.isRegLoc()) 2357 continue; 2358 assert(VA.isMemLoc()); 2359 SDValue Arg = OutVals[i]; 2360 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2361 // Create frame index. 2362 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2363 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2364 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2365 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2366 2367 if (Flags.isByVal()) { 2368 // Copy relative to framepointer. 2369 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2370 if (StackPtr.getNode() == 0) 2371 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2372 getPointerTy()); 2373 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2374 2375 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2376 ArgChain, 2377 Flags, DAG, dl)); 2378 } else { 2379 // Store relative to framepointer. 2380 MemOpChains2.push_back( 2381 DAG.getStore(ArgChain, dl, Arg, FIN, 2382 MachinePointerInfo::getFixedStack(FI), 2383 false, false, 0)); 2384 } 2385 } 2386 } 2387 2388 if (!MemOpChains2.empty()) 2389 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2390 &MemOpChains2[0], MemOpChains2.size()); 2391 2392 // Copy arguments to their registers. 2393 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2394 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2395 RegsToPass[i].second, InFlag); 2396 InFlag = Chain.getValue(1); 2397 } 2398 InFlag =SDValue(); 2399 2400 // Store the return address to the appropriate stack slot. 2401 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2402 FPDiff, dl); 2403 } 2404 2405 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2406 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2407 // In the 64-bit large code model, we have to make all calls 2408 // through a register, since the call instruction's 32-bit 2409 // pc-relative offset may not be large enough to hold the whole 2410 // address. 2411 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2412 // If the callee is a GlobalAddress node (quite common, every direct call 2413 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2414 // it. 2415 2416 // We should use extra load for direct calls to dllimported functions in 2417 // non-JIT mode. 2418 const GlobalValue *GV = G->getGlobal(); 2419 if (!GV->hasDLLImportLinkage()) { 2420 unsigned char OpFlags = 0; 2421 bool ExtraLoad = false; 2422 unsigned WrapperKind = ISD::DELETED_NODE; 2423 2424 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2425 // external symbols most go through the PLT in PIC mode. If the symbol 2426 // has hidden or protected visibility, or if it is static or local, then 2427 // we don't need to use the PLT - we can directly call it. 2428 if (Subtarget->isTargetELF() && 2429 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2430 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2431 OpFlags = X86II::MO_PLT; 2432 } else if (Subtarget->isPICStyleStubAny() && 2433 (GV->isDeclaration() || GV->isWeakForLinker()) && 2434 (!Subtarget->getTargetTriple().isMacOSX() || 2435 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2436 // PC-relative references to external symbols should go through $stub, 2437 // unless we're building with the leopard linker or later, which 2438 // automatically synthesizes these stubs. 2439 OpFlags = X86II::MO_DARWIN_STUB; 2440 } else if (Subtarget->isPICStyleRIPRel() && 2441 isa<Function>(GV) && 2442 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2443 // If the function is marked as non-lazy, generate an indirect call 2444 // which loads from the GOT directly. This avoids runtime overhead 2445 // at the cost of eager binding (and one extra byte of encoding). 2446 OpFlags = X86II::MO_GOTPCREL; 2447 WrapperKind = X86ISD::WrapperRIP; 2448 ExtraLoad = true; 2449 } 2450 2451 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2452 G->getOffset(), OpFlags); 2453 2454 // Add a wrapper if needed. 2455 if (WrapperKind != ISD::DELETED_NODE) 2456 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2457 // Add extra indirection if needed. 2458 if (ExtraLoad) 2459 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2460 MachinePointerInfo::getGOT(), 2461 false, false, false, 0); 2462 } 2463 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2464 unsigned char OpFlags = 0; 2465 2466 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2467 // external symbols should go through the PLT. 2468 if (Subtarget->isTargetELF() && 2469 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2470 OpFlags = X86II::MO_PLT; 2471 } else if (Subtarget->isPICStyleStubAny() && 2472 (!Subtarget->getTargetTriple().isMacOSX() || 2473 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2474 // PC-relative references to external symbols should go through $stub, 2475 // unless we're building with the leopard linker or later, which 2476 // automatically synthesizes these stubs. 2477 OpFlags = X86II::MO_DARWIN_STUB; 2478 } 2479 2480 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2481 OpFlags); 2482 } 2483 2484 // Returns a chain & a flag for retval copy to use. 2485 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2486 SmallVector<SDValue, 8> Ops; 2487 2488 if (!IsSibcall && isTailCall) { 2489 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2490 DAG.getIntPtrConstant(0, true), InFlag); 2491 InFlag = Chain.getValue(1); 2492 } 2493 2494 Ops.push_back(Chain); 2495 Ops.push_back(Callee); 2496 2497 if (isTailCall) 2498 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2499 2500 // Add argument registers to the end of the list so that they are known live 2501 // into the call. 2502 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2503 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2504 RegsToPass[i].second.getValueType())); 2505 2506 // Add an implicit use GOT pointer in EBX. 2507 if (!isTailCall && Subtarget->isPICStyleGOT()) 2508 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2509 2510 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2511 if (Is64Bit && isVarArg && !IsWin64) 2512 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2513 2514 // Experimental: Add a register mask operand representing the call-preserved 2515 // registers. 2516 if (UseRegMask) { 2517 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2518 if (const uint32_t *Mask = TRI->getCallPreservedMask(CallConv)) 2519 Ops.push_back(DAG.getRegisterMask(Mask)); 2520 } 2521 2522 if (InFlag.getNode()) 2523 Ops.push_back(InFlag); 2524 2525 if (isTailCall) { 2526 // We used to do: 2527 //// If this is the first return lowered for this function, add the regs 2528 //// to the liveout set for the function. 2529 // This isn't right, although it's probably harmless on x86; liveouts 2530 // should be computed from returns not tail calls. Consider a void 2531 // function making a tail call to a function returning int. 2532 return DAG.getNode(X86ISD::TC_RETURN, dl, 2533 NodeTys, &Ops[0], Ops.size()); 2534 } 2535 2536 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2537 InFlag = Chain.getValue(1); 2538 2539 // Create the CALLSEQ_END node. 2540 unsigned NumBytesForCalleeToPush; 2541 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2542 getTargetMachine().Options.GuaranteedTailCallOpt)) 2543 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2544 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2545 IsStructRet) 2546 // If this is a call to a struct-return function, the callee 2547 // pops the hidden struct pointer, so we have to push it back. 2548 // This is common for Darwin/X86, Linux & Mingw32 targets. 2549 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2550 NumBytesForCalleeToPush = 4; 2551 else 2552 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2553 2554 // Returns a flag for retval copy to use. 2555 if (!IsSibcall) { 2556 Chain = DAG.getCALLSEQ_END(Chain, 2557 DAG.getIntPtrConstant(NumBytes, true), 2558 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2559 true), 2560 InFlag); 2561 InFlag = Chain.getValue(1); 2562 } 2563 2564 // Handle result values, copying them out of physregs into vregs that we 2565 // return. 2566 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2567 Ins, dl, DAG, InVals); 2568} 2569 2570 2571//===----------------------------------------------------------------------===// 2572// Fast Calling Convention (tail call) implementation 2573//===----------------------------------------------------------------------===// 2574 2575// Like std call, callee cleans arguments, convention except that ECX is 2576// reserved for storing the tail called function address. Only 2 registers are 2577// free for argument passing (inreg). Tail call optimization is performed 2578// provided: 2579// * tailcallopt is enabled 2580// * caller/callee are fastcc 2581// On X86_64 architecture with GOT-style position independent code only local 2582// (within module) calls are supported at the moment. 2583// To keep the stack aligned according to platform abi the function 2584// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2585// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2586// If a tail called function callee has more arguments than the caller the 2587// caller needs to make sure that there is room to move the RETADDR to. This is 2588// achieved by reserving an area the size of the argument delta right after the 2589// original REtADDR, but before the saved framepointer or the spilled registers 2590// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2591// stack layout: 2592// arg1 2593// arg2 2594// RETADDR 2595// [ new RETADDR 2596// move area ] 2597// (possible EBP) 2598// ESI 2599// EDI 2600// local1 .. 2601 2602/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2603/// for a 16 byte align requirement. 2604unsigned 2605X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2606 SelectionDAG& DAG) const { 2607 MachineFunction &MF = DAG.getMachineFunction(); 2608 const TargetMachine &TM = MF.getTarget(); 2609 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2610 unsigned StackAlignment = TFI.getStackAlignment(); 2611 uint64_t AlignMask = StackAlignment - 1; 2612 int64_t Offset = StackSize; 2613 uint64_t SlotSize = TD->getPointerSize(); 2614 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2615 // Number smaller than 12 so just add the difference. 2616 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2617 } else { 2618 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2619 Offset = ((~AlignMask) & Offset) + StackAlignment + 2620 (StackAlignment-SlotSize); 2621 } 2622 return Offset; 2623} 2624 2625/// MatchingStackOffset - Return true if the given stack call argument is 2626/// already available in the same position (relatively) of the caller's 2627/// incoming argument stack. 2628static 2629bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2630 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2631 const X86InstrInfo *TII) { 2632 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2633 int FI = INT_MAX; 2634 if (Arg.getOpcode() == ISD::CopyFromReg) { 2635 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2636 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2637 return false; 2638 MachineInstr *Def = MRI->getVRegDef(VR); 2639 if (!Def) 2640 return false; 2641 if (!Flags.isByVal()) { 2642 if (!TII->isLoadFromStackSlot(Def, FI)) 2643 return false; 2644 } else { 2645 unsigned Opcode = Def->getOpcode(); 2646 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2647 Def->getOperand(1).isFI()) { 2648 FI = Def->getOperand(1).getIndex(); 2649 Bytes = Flags.getByValSize(); 2650 } else 2651 return false; 2652 } 2653 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2654 if (Flags.isByVal()) 2655 // ByVal argument is passed in as a pointer but it's now being 2656 // dereferenced. e.g. 2657 // define @foo(%struct.X* %A) { 2658 // tail call @bar(%struct.X* byval %A) 2659 // } 2660 return false; 2661 SDValue Ptr = Ld->getBasePtr(); 2662 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2663 if (!FINode) 2664 return false; 2665 FI = FINode->getIndex(); 2666 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2667 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2668 FI = FINode->getIndex(); 2669 Bytes = Flags.getByValSize(); 2670 } else 2671 return false; 2672 2673 assert(FI != INT_MAX); 2674 if (!MFI->isFixedObjectIndex(FI)) 2675 return false; 2676 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2677} 2678 2679/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2680/// for tail call optimization. Targets which want to do tail call 2681/// optimization should implement this function. 2682bool 2683X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2684 CallingConv::ID CalleeCC, 2685 bool isVarArg, 2686 bool isCalleeStructRet, 2687 bool isCallerStructRet, 2688 const SmallVectorImpl<ISD::OutputArg> &Outs, 2689 const SmallVectorImpl<SDValue> &OutVals, 2690 const SmallVectorImpl<ISD::InputArg> &Ins, 2691 SelectionDAG& DAG) const { 2692 if (!IsTailCallConvention(CalleeCC) && 2693 CalleeCC != CallingConv::C) 2694 return false; 2695 2696 // If -tailcallopt is specified, make fastcc functions tail-callable. 2697 const MachineFunction &MF = DAG.getMachineFunction(); 2698 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2699 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2700 bool CCMatch = CallerCC == CalleeCC; 2701 2702 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2703 if (IsTailCallConvention(CalleeCC) && CCMatch) 2704 return true; 2705 return false; 2706 } 2707 2708 // Look for obvious safe cases to perform tail call optimization that do not 2709 // require ABI changes. This is what gcc calls sibcall. 2710 2711 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2712 // emit a special epilogue. 2713 if (RegInfo->needsStackRealignment(MF)) 2714 return false; 2715 2716 // Also avoid sibcall optimization if either caller or callee uses struct 2717 // return semantics. 2718 if (isCalleeStructRet || isCallerStructRet) 2719 return false; 2720 2721 // An stdcall caller is expected to clean up its arguments; the callee 2722 // isn't going to do that. 2723 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2724 return false; 2725 2726 // Do not sibcall optimize vararg calls unless all arguments are passed via 2727 // registers. 2728 if (isVarArg && !Outs.empty()) { 2729 2730 // Optimizing for varargs on Win64 is unlikely to be safe without 2731 // additional testing. 2732 if (Subtarget->isTargetWin64()) 2733 return false; 2734 2735 SmallVector<CCValAssign, 16> ArgLocs; 2736 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2737 getTargetMachine(), ArgLocs, *DAG.getContext()); 2738 2739 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2740 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2741 if (!ArgLocs[i].isRegLoc()) 2742 return false; 2743 } 2744 2745 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2746 // stack. Therefore, if it's not used by the call it is not safe to optimize 2747 // this into a sibcall. 2748 bool Unused = false; 2749 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2750 if (!Ins[i].Used) { 2751 Unused = true; 2752 break; 2753 } 2754 } 2755 if (Unused) { 2756 SmallVector<CCValAssign, 16> RVLocs; 2757 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2758 getTargetMachine(), RVLocs, *DAG.getContext()); 2759 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2760 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2761 CCValAssign &VA = RVLocs[i]; 2762 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2763 return false; 2764 } 2765 } 2766 2767 // If the calling conventions do not match, then we'd better make sure the 2768 // results are returned in the same way as what the caller expects. 2769 if (!CCMatch) { 2770 SmallVector<CCValAssign, 16> RVLocs1; 2771 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2772 getTargetMachine(), RVLocs1, *DAG.getContext()); 2773 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2774 2775 SmallVector<CCValAssign, 16> RVLocs2; 2776 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2777 getTargetMachine(), RVLocs2, *DAG.getContext()); 2778 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2779 2780 if (RVLocs1.size() != RVLocs2.size()) 2781 return false; 2782 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2783 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2784 return false; 2785 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2786 return false; 2787 if (RVLocs1[i].isRegLoc()) { 2788 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2789 return false; 2790 } else { 2791 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2792 return false; 2793 } 2794 } 2795 } 2796 2797 // If the callee takes no arguments then go on to check the results of the 2798 // call. 2799 if (!Outs.empty()) { 2800 // Check if stack adjustment is needed. For now, do not do this if any 2801 // argument is passed on the stack. 2802 SmallVector<CCValAssign, 16> ArgLocs; 2803 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2804 getTargetMachine(), ArgLocs, *DAG.getContext()); 2805 2806 // Allocate shadow area for Win64 2807 if (Subtarget->isTargetWin64()) { 2808 CCInfo.AllocateStack(32, 8); 2809 } 2810 2811 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2812 if (CCInfo.getNextStackOffset()) { 2813 MachineFunction &MF = DAG.getMachineFunction(); 2814 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2815 return false; 2816 2817 // Check if the arguments are already laid out in the right way as 2818 // the caller's fixed stack objects. 2819 MachineFrameInfo *MFI = MF.getFrameInfo(); 2820 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2821 const X86InstrInfo *TII = 2822 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2823 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2824 CCValAssign &VA = ArgLocs[i]; 2825 SDValue Arg = OutVals[i]; 2826 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2827 if (VA.getLocInfo() == CCValAssign::Indirect) 2828 return false; 2829 if (!VA.isRegLoc()) { 2830 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2831 MFI, MRI, TII)) 2832 return false; 2833 } 2834 } 2835 } 2836 2837 // If the tailcall address may be in a register, then make sure it's 2838 // possible to register allocate for it. In 32-bit, the call address can 2839 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2840 // callee-saved registers are restored. These happen to be the same 2841 // registers used to pass 'inreg' arguments so watch out for those. 2842 if (!Subtarget->is64Bit() && 2843 !isa<GlobalAddressSDNode>(Callee) && 2844 !isa<ExternalSymbolSDNode>(Callee)) { 2845 unsigned NumInRegs = 0; 2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2847 CCValAssign &VA = ArgLocs[i]; 2848 if (!VA.isRegLoc()) 2849 continue; 2850 unsigned Reg = VA.getLocReg(); 2851 switch (Reg) { 2852 default: break; 2853 case X86::EAX: case X86::EDX: case X86::ECX: 2854 if (++NumInRegs == 3) 2855 return false; 2856 break; 2857 } 2858 } 2859 } 2860 } 2861 2862 return true; 2863} 2864 2865FastISel * 2866X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2867 return X86::createFastISel(funcInfo); 2868} 2869 2870 2871//===----------------------------------------------------------------------===// 2872// Other Lowering Hooks 2873//===----------------------------------------------------------------------===// 2874 2875static bool MayFoldLoad(SDValue Op) { 2876 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2877} 2878 2879static bool MayFoldIntoStore(SDValue Op) { 2880 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2881} 2882 2883static bool isTargetShuffle(unsigned Opcode) { 2884 switch(Opcode) { 2885 default: return false; 2886 case X86ISD::PSHUFD: 2887 case X86ISD::PSHUFHW: 2888 case X86ISD::PSHUFLW: 2889 case X86ISD::SHUFP: 2890 case X86ISD::PALIGN: 2891 case X86ISD::MOVLHPS: 2892 case X86ISD::MOVLHPD: 2893 case X86ISD::MOVHLPS: 2894 case X86ISD::MOVLPS: 2895 case X86ISD::MOVLPD: 2896 case X86ISD::MOVSHDUP: 2897 case X86ISD::MOVSLDUP: 2898 case X86ISD::MOVDDUP: 2899 case X86ISD::MOVSS: 2900 case X86ISD::MOVSD: 2901 case X86ISD::UNPCKL: 2902 case X86ISD::UNPCKH: 2903 case X86ISD::VPERMILP: 2904 case X86ISD::VPERM2X128: 2905 return true; 2906 } 2907} 2908 2909static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2910 SDValue V1, SelectionDAG &DAG) { 2911 switch(Opc) { 2912 default: llvm_unreachable("Unknown x86 shuffle node"); 2913 case X86ISD::MOVSHDUP: 2914 case X86ISD::MOVSLDUP: 2915 case X86ISD::MOVDDUP: 2916 return DAG.getNode(Opc, dl, VT, V1); 2917 } 2918} 2919 2920static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2921 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2922 switch(Opc) { 2923 default: llvm_unreachable("Unknown x86 shuffle node"); 2924 case X86ISD::PSHUFD: 2925 case X86ISD::PSHUFHW: 2926 case X86ISD::PSHUFLW: 2927 case X86ISD::VPERMILP: 2928 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2929 } 2930} 2931 2932static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2933 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2934 switch(Opc) { 2935 default: llvm_unreachable("Unknown x86 shuffle node"); 2936 case X86ISD::PALIGN: 2937 case X86ISD::SHUFP: 2938 case X86ISD::VPERM2X128: 2939 return DAG.getNode(Opc, dl, VT, V1, V2, 2940 DAG.getConstant(TargetMask, MVT::i8)); 2941 } 2942} 2943 2944static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2945 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2946 switch(Opc) { 2947 default: llvm_unreachable("Unknown x86 shuffle node"); 2948 case X86ISD::MOVLHPS: 2949 case X86ISD::MOVLHPD: 2950 case X86ISD::MOVHLPS: 2951 case X86ISD::MOVLPS: 2952 case X86ISD::MOVLPD: 2953 case X86ISD::MOVSS: 2954 case X86ISD::MOVSD: 2955 case X86ISD::UNPCKL: 2956 case X86ISD::UNPCKH: 2957 return DAG.getNode(Opc, dl, VT, V1, V2); 2958 } 2959} 2960 2961SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2962 MachineFunction &MF = DAG.getMachineFunction(); 2963 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2964 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2965 2966 if (ReturnAddrIndex == 0) { 2967 // Set up a frame object for the return address. 2968 uint64_t SlotSize = TD->getPointerSize(); 2969 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2970 false); 2971 FuncInfo->setRAIndex(ReturnAddrIndex); 2972 } 2973 2974 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2975} 2976 2977 2978bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2979 bool hasSymbolicDisplacement) { 2980 // Offset should fit into 32 bit immediate field. 2981 if (!isInt<32>(Offset)) 2982 return false; 2983 2984 // If we don't have a symbolic displacement - we don't have any extra 2985 // restrictions. 2986 if (!hasSymbolicDisplacement) 2987 return true; 2988 2989 // FIXME: Some tweaks might be needed for medium code model. 2990 if (M != CodeModel::Small && M != CodeModel::Kernel) 2991 return false; 2992 2993 // For small code model we assume that latest object is 16MB before end of 31 2994 // bits boundary. We may also accept pretty large negative constants knowing 2995 // that all objects are in the positive half of address space. 2996 if (M == CodeModel::Small && Offset < 16*1024*1024) 2997 return true; 2998 2999 // For kernel code model we know that all object resist in the negative half 3000 // of 32bits address space. We may not accept negative offsets, since they may 3001 // be just off and we may accept pretty large positive ones. 3002 if (M == CodeModel::Kernel && Offset > 0) 3003 return true; 3004 3005 return false; 3006} 3007 3008/// isCalleePop - Determines whether the callee is required to pop its 3009/// own arguments. Callee pop is necessary to support tail calls. 3010bool X86::isCalleePop(CallingConv::ID CallingConv, 3011 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3012 if (IsVarArg) 3013 return false; 3014 3015 switch (CallingConv) { 3016 default: 3017 return false; 3018 case CallingConv::X86_StdCall: 3019 return !is64Bit; 3020 case CallingConv::X86_FastCall: 3021 return !is64Bit; 3022 case CallingConv::X86_ThisCall: 3023 return !is64Bit; 3024 case CallingConv::Fast: 3025 return TailCallOpt; 3026 case CallingConv::GHC: 3027 return TailCallOpt; 3028 } 3029} 3030 3031/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3032/// specific condition code, returning the condition code and the LHS/RHS of the 3033/// comparison to make. 3034static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3035 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3036 if (!isFP) { 3037 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3038 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3039 // X > -1 -> X == 0, jump !sign. 3040 RHS = DAG.getConstant(0, RHS.getValueType()); 3041 return X86::COND_NS; 3042 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3043 // X < 0 -> X == 0, jump on sign. 3044 return X86::COND_S; 3045 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3046 // X < 1 -> X <= 0 3047 RHS = DAG.getConstant(0, RHS.getValueType()); 3048 return X86::COND_LE; 3049 } 3050 } 3051 3052 switch (SetCCOpcode) { 3053 default: llvm_unreachable("Invalid integer condition!"); 3054 case ISD::SETEQ: return X86::COND_E; 3055 case ISD::SETGT: return X86::COND_G; 3056 case ISD::SETGE: return X86::COND_GE; 3057 case ISD::SETLT: return X86::COND_L; 3058 case ISD::SETLE: return X86::COND_LE; 3059 case ISD::SETNE: return X86::COND_NE; 3060 case ISD::SETULT: return X86::COND_B; 3061 case ISD::SETUGT: return X86::COND_A; 3062 case ISD::SETULE: return X86::COND_BE; 3063 case ISD::SETUGE: return X86::COND_AE; 3064 } 3065 } 3066 3067 // First determine if it is required or is profitable to flip the operands. 3068 3069 // If LHS is a foldable load, but RHS is not, flip the condition. 3070 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3071 !ISD::isNON_EXTLoad(RHS.getNode())) { 3072 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3073 std::swap(LHS, RHS); 3074 } 3075 3076 switch (SetCCOpcode) { 3077 default: break; 3078 case ISD::SETOLT: 3079 case ISD::SETOLE: 3080 case ISD::SETUGT: 3081 case ISD::SETUGE: 3082 std::swap(LHS, RHS); 3083 break; 3084 } 3085 3086 // On a floating point condition, the flags are set as follows: 3087 // ZF PF CF op 3088 // 0 | 0 | 0 | X > Y 3089 // 0 | 0 | 1 | X < Y 3090 // 1 | 0 | 0 | X == Y 3091 // 1 | 1 | 1 | unordered 3092 switch (SetCCOpcode) { 3093 default: llvm_unreachable("Condcode should be pre-legalized away"); 3094 case ISD::SETUEQ: 3095 case ISD::SETEQ: return X86::COND_E; 3096 case ISD::SETOLT: // flipped 3097 case ISD::SETOGT: 3098 case ISD::SETGT: return X86::COND_A; 3099 case ISD::SETOLE: // flipped 3100 case ISD::SETOGE: 3101 case ISD::SETGE: return X86::COND_AE; 3102 case ISD::SETUGT: // flipped 3103 case ISD::SETULT: 3104 case ISD::SETLT: return X86::COND_B; 3105 case ISD::SETUGE: // flipped 3106 case ISD::SETULE: 3107 case ISD::SETLE: return X86::COND_BE; 3108 case ISD::SETONE: 3109 case ISD::SETNE: return X86::COND_NE; 3110 case ISD::SETUO: return X86::COND_P; 3111 case ISD::SETO: return X86::COND_NP; 3112 case ISD::SETOEQ: 3113 case ISD::SETUNE: return X86::COND_INVALID; 3114 } 3115} 3116 3117/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3118/// code. Current x86 isa includes the following FP cmov instructions: 3119/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3120static bool hasFPCMov(unsigned X86CC) { 3121 switch (X86CC) { 3122 default: 3123 return false; 3124 case X86::COND_B: 3125 case X86::COND_BE: 3126 case X86::COND_E: 3127 case X86::COND_P: 3128 case X86::COND_A: 3129 case X86::COND_AE: 3130 case X86::COND_NE: 3131 case X86::COND_NP: 3132 return true; 3133 } 3134} 3135 3136/// isFPImmLegal - Returns true if the target can instruction select the 3137/// specified FP immediate natively. If false, the legalizer will 3138/// materialize the FP immediate as a load from a constant pool. 3139bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3140 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3141 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3142 return true; 3143 } 3144 return false; 3145} 3146 3147/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3148/// the specified range (L, H]. 3149static bool isUndefOrInRange(int Val, int Low, int Hi) { 3150 return (Val < 0) || (Val >= Low && Val < Hi); 3151} 3152 3153/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3154/// specified value. 3155static bool isUndefOrEqual(int Val, int CmpVal) { 3156 if (Val < 0 || Val == CmpVal) 3157 return true; 3158 return false; 3159} 3160 3161/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3162/// from position Pos and ending in Pos+Size, falls within the specified 3163/// sequential range (L, L+Pos]. or is undef. 3164static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3165 int Pos, int Size, int Low) { 3166 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3167 if (!isUndefOrEqual(Mask[i], Low)) 3168 return false; 3169 return true; 3170} 3171 3172/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3173/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3174/// the second operand. 3175static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3176 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3177 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3178 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3179 return (Mask[0] < 2 && Mask[1] < 2); 3180 return false; 3181} 3182 3183bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3184 return ::isPSHUFDMask(N->getMask(), N->getValueType(0)); 3185} 3186 3187/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3188/// is suitable for input to PSHUFHW. 3189static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3190 if (VT != MVT::v8i16) 3191 return false; 3192 3193 // Lower quadword copied in order or undef. 3194 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3195 return false; 3196 3197 // Upper quadword shuffled. 3198 for (unsigned i = 4; i != 8; ++i) 3199 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3200 return false; 3201 3202 return true; 3203} 3204 3205bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3206 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0)); 3207} 3208 3209/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3210/// is suitable for input to PSHUFLW. 3211static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3212 if (VT != MVT::v8i16) 3213 return false; 3214 3215 // Upper quadword copied in order. 3216 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3217 return false; 3218 3219 // Lower quadword shuffled. 3220 for (unsigned i = 0; i != 4; ++i) 3221 if (Mask[i] >= 4) 3222 return false; 3223 3224 return true; 3225} 3226 3227bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3228 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0)); 3229} 3230 3231/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3232/// is suitable for input to PALIGNR. 3233static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3234 const X86Subtarget *Subtarget) { 3235 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3236 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3237 return false; 3238 3239 unsigned NumElts = VT.getVectorNumElements(); 3240 unsigned NumLanes = VT.getSizeInBits()/128; 3241 unsigned NumLaneElts = NumElts/NumLanes; 3242 3243 // Do not handle 64-bit element shuffles with palignr. 3244 if (NumLaneElts == 2) 3245 return false; 3246 3247 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3248 unsigned i; 3249 for (i = 0; i != NumLaneElts; ++i) { 3250 if (Mask[i+l] >= 0) 3251 break; 3252 } 3253 3254 // Lane is all undef, go to next lane 3255 if (i == NumLaneElts) 3256 continue; 3257 3258 int Start = Mask[i+l]; 3259 3260 // Make sure its in this lane in one of the sources 3261 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3262 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3263 return false; 3264 3265 // If not lane 0, then we must match lane 0 3266 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3267 return false; 3268 3269 // Correct second source to be contiguous with first source 3270 if (Start >= (int)NumElts) 3271 Start -= NumElts - NumLaneElts; 3272 3273 // Make sure we're shifting in the right direction. 3274 if (Start <= (int)(i+l)) 3275 return false; 3276 3277 Start -= i; 3278 3279 // Check the rest of the elements to see if they are consecutive. 3280 for (++i; i != NumLaneElts; ++i) { 3281 int Idx = Mask[i+l]; 3282 3283 // Make sure its in this lane 3284 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3285 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3286 return false; 3287 3288 // If not lane 0, then we must match lane 0 3289 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3290 return false; 3291 3292 if (Idx >= (int)NumElts) 3293 Idx -= NumElts - NumLaneElts; 3294 3295 if (!isUndefOrEqual(Idx, Start+i)) 3296 return false; 3297 3298 } 3299 } 3300 3301 return true; 3302} 3303 3304/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3305/// the two vector operands have swapped position. 3306static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3307 unsigned NumElems) { 3308 for (unsigned i = 0; i != NumElems; ++i) { 3309 int idx = Mask[i]; 3310 if (idx < 0) 3311 continue; 3312 else if (idx < (int)NumElems) 3313 Mask[i] = idx + NumElems; 3314 else 3315 Mask[i] = idx - NumElems; 3316 } 3317} 3318 3319/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3320/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3321/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3322/// reverse of what x86 shuffles want. 3323static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3324 bool Commuted = false) { 3325 if (!HasAVX && VT.getSizeInBits() == 256) 3326 return false; 3327 3328 unsigned NumElems = VT.getVectorNumElements(); 3329 unsigned NumLanes = VT.getSizeInBits()/128; 3330 unsigned NumLaneElems = NumElems/NumLanes; 3331 3332 if (NumLaneElems != 2 && NumLaneElems != 4) 3333 return false; 3334 3335 // VSHUFPSY divides the resulting vector into 4 chunks. 3336 // The sources are also splitted into 4 chunks, and each destination 3337 // chunk must come from a different source chunk. 3338 // 3339 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3340 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3341 // 3342 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3343 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3344 // 3345 // VSHUFPDY divides the resulting vector into 4 chunks. 3346 // The sources are also splitted into 4 chunks, and each destination 3347 // chunk must come from a different source chunk. 3348 // 3349 // SRC1 => X3 X2 X1 X0 3350 // SRC2 => Y3 Y2 Y1 Y0 3351 // 3352 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3353 // 3354 unsigned HalfLaneElems = NumLaneElems/2; 3355 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3356 for (unsigned i = 0; i != NumLaneElems; ++i) { 3357 int Idx = Mask[i+l]; 3358 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3359 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3360 return false; 3361 // For VSHUFPSY, the mask of the second half must be the same as the 3362 // first but with the appropriate offsets. This works in the same way as 3363 // VPERMILPS works with masks. 3364 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3365 continue; 3366 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3367 return false; 3368 } 3369 } 3370 3371 return true; 3372} 3373 3374bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) { 3375 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX); 3376} 3377 3378/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3379/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3380bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3381 EVT VT = N->getValueType(0); 3382 unsigned NumElems = VT.getVectorNumElements(); 3383 3384 if (VT.getSizeInBits() != 128) 3385 return false; 3386 3387 if (NumElems != 4) 3388 return false; 3389 3390 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3391 return isUndefOrEqual(N->getMaskElt(0), 6) && 3392 isUndefOrEqual(N->getMaskElt(1), 7) && 3393 isUndefOrEqual(N->getMaskElt(2), 2) && 3394 isUndefOrEqual(N->getMaskElt(3), 3); 3395} 3396 3397/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3398/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3399/// <2, 3, 2, 3> 3400bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3401 EVT VT = N->getValueType(0); 3402 unsigned NumElems = VT.getVectorNumElements(); 3403 3404 if (VT.getSizeInBits() != 128) 3405 return false; 3406 3407 if (NumElems != 4) 3408 return false; 3409 3410 return isUndefOrEqual(N->getMaskElt(0), 2) && 3411 isUndefOrEqual(N->getMaskElt(1), 3) && 3412 isUndefOrEqual(N->getMaskElt(2), 2) && 3413 isUndefOrEqual(N->getMaskElt(3), 3); 3414} 3415 3416/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3417/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3418bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3419 EVT VT = N->getValueType(0); 3420 3421 if (VT.getSizeInBits() != 128) 3422 return false; 3423 3424 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3425 3426 if (NumElems != 2 && NumElems != 4) 3427 return false; 3428 3429 for (unsigned i = 0; i < NumElems/2; ++i) 3430 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3431 return false; 3432 3433 for (unsigned i = NumElems/2; i < NumElems; ++i) 3434 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3435 return false; 3436 3437 return true; 3438} 3439 3440/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3441/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3442bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3443 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3444 3445 if ((NumElems != 2 && NumElems != 4) 3446 || N->getValueType(0).getSizeInBits() > 128) 3447 return false; 3448 3449 for (unsigned i = 0; i < NumElems/2; ++i) 3450 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3451 return false; 3452 3453 for (unsigned i = 0; i < NumElems/2; ++i) 3454 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3455 return false; 3456 3457 return true; 3458} 3459 3460/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3461/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3462static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3463 bool HasAVX2, bool V2IsSplat = false) { 3464 unsigned NumElts = VT.getVectorNumElements(); 3465 3466 assert((VT.is128BitVector() || VT.is256BitVector()) && 3467 "Unsupported vector type for unpckh"); 3468 3469 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3470 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3471 return false; 3472 3473 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3474 // independently on 128-bit lanes. 3475 unsigned NumLanes = VT.getSizeInBits()/128; 3476 unsigned NumLaneElts = NumElts/NumLanes; 3477 3478 for (unsigned l = 0; l != NumLanes; ++l) { 3479 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3480 i != (l+1)*NumLaneElts; 3481 i += 2, ++j) { 3482 int BitI = Mask[i]; 3483 int BitI1 = Mask[i+1]; 3484 if (!isUndefOrEqual(BitI, j)) 3485 return false; 3486 if (V2IsSplat) { 3487 if (!isUndefOrEqual(BitI1, NumElts)) 3488 return false; 3489 } else { 3490 if (!isUndefOrEqual(BitI1, j + NumElts)) 3491 return false; 3492 } 3493 } 3494 } 3495 3496 return true; 3497} 3498 3499bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3500 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat); 3501} 3502 3503/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3504/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3505static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3506 bool HasAVX2, bool V2IsSplat = false) { 3507 unsigned NumElts = VT.getVectorNumElements(); 3508 3509 assert((VT.is128BitVector() || VT.is256BitVector()) && 3510 "Unsupported vector type for unpckh"); 3511 3512 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3513 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3514 return false; 3515 3516 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3517 // independently on 128-bit lanes. 3518 unsigned NumLanes = VT.getSizeInBits()/128; 3519 unsigned NumLaneElts = NumElts/NumLanes; 3520 3521 for (unsigned l = 0; l != NumLanes; ++l) { 3522 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3523 i != (l+1)*NumLaneElts; i += 2, ++j) { 3524 int BitI = Mask[i]; 3525 int BitI1 = Mask[i+1]; 3526 if (!isUndefOrEqual(BitI, j)) 3527 return false; 3528 if (V2IsSplat) { 3529 if (isUndefOrEqual(BitI1, NumElts)) 3530 return false; 3531 } else { 3532 if (!isUndefOrEqual(BitI1, j+NumElts)) 3533 return false; 3534 } 3535 } 3536 } 3537 return true; 3538} 3539 3540bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3541 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat); 3542} 3543 3544/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3545/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3546/// <0, 0, 1, 1> 3547static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3548 bool HasAVX2) { 3549 unsigned NumElts = VT.getVectorNumElements(); 3550 3551 assert((VT.is128BitVector() || VT.is256BitVector()) && 3552 "Unsupported vector type for unpckh"); 3553 3554 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3555 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3556 return false; 3557 3558 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3559 // FIXME: Need a better way to get rid of this, there's no latency difference 3560 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3561 // the former later. We should also remove the "_undef" special mask. 3562 if (NumElts == 4 && VT.getSizeInBits() == 256) 3563 return false; 3564 3565 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3566 // independently on 128-bit lanes. 3567 unsigned NumLanes = VT.getSizeInBits()/128; 3568 unsigned NumLaneElts = NumElts/NumLanes; 3569 3570 for (unsigned l = 0; l != NumLanes; ++l) { 3571 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3572 i != (l+1)*NumLaneElts; 3573 i += 2, ++j) { 3574 int BitI = Mask[i]; 3575 int BitI1 = Mask[i+1]; 3576 3577 if (!isUndefOrEqual(BitI, j)) 3578 return false; 3579 if (!isUndefOrEqual(BitI1, j)) 3580 return false; 3581 } 3582 } 3583 3584 return true; 3585} 3586 3587bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3588 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2); 3589} 3590 3591/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3592/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3593/// <2, 2, 3, 3> 3594static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3595 unsigned NumElts = VT.getVectorNumElements(); 3596 3597 assert((VT.is128BitVector() || VT.is256BitVector()) && 3598 "Unsupported vector type for unpckh"); 3599 3600 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3601 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3602 return false; 3603 3604 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3605 // independently on 128-bit lanes. 3606 unsigned NumLanes = VT.getSizeInBits()/128; 3607 unsigned NumLaneElts = NumElts/NumLanes; 3608 3609 for (unsigned l = 0; l != NumLanes; ++l) { 3610 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3611 i != (l+1)*NumLaneElts; i += 2, ++j) { 3612 int BitI = Mask[i]; 3613 int BitI1 = Mask[i+1]; 3614 if (!isUndefOrEqual(BitI, j)) 3615 return false; 3616 if (!isUndefOrEqual(BitI1, j)) 3617 return false; 3618 } 3619 } 3620 return true; 3621} 3622 3623bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3624 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2); 3625} 3626 3627/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3628/// specifies a shuffle of elements that is suitable for input to MOVSS, 3629/// MOVSD, and MOVD, i.e. setting the lowest element. 3630static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3631 if (VT.getVectorElementType().getSizeInBits() < 32) 3632 return false; 3633 if (VT.getSizeInBits() == 256) 3634 return false; 3635 3636 unsigned NumElts = VT.getVectorNumElements(); 3637 3638 if (!isUndefOrEqual(Mask[0], NumElts)) 3639 return false; 3640 3641 for (unsigned i = 1; i != NumElts; ++i) 3642 if (!isUndefOrEqual(Mask[i], i)) 3643 return false; 3644 3645 return true; 3646} 3647 3648bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3649 return ::isMOVLMask(N->getMask(), N->getValueType(0)); 3650} 3651 3652/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3653/// as permutations between 128-bit chunks or halves. As an example: this 3654/// shuffle bellow: 3655/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3656/// The first half comes from the second half of V1 and the second half from the 3657/// the second half of V2. 3658static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3659 if (!HasAVX || VT.getSizeInBits() != 256) 3660 return false; 3661 3662 // The shuffle result is divided into half A and half B. In total the two 3663 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3664 // B must come from C, D, E or F. 3665 unsigned HalfSize = VT.getVectorNumElements()/2; 3666 bool MatchA = false, MatchB = false; 3667 3668 // Check if A comes from one of C, D, E, F. 3669 for (unsigned Half = 0; Half != 4; ++Half) { 3670 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3671 MatchA = true; 3672 break; 3673 } 3674 } 3675 3676 // Check if B comes from one of C, D, E, F. 3677 for (unsigned Half = 0; Half != 4; ++Half) { 3678 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3679 MatchB = true; 3680 break; 3681 } 3682 } 3683 3684 return MatchA && MatchB; 3685} 3686 3687/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3688/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3689static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3690 EVT VT = SVOp->getValueType(0); 3691 3692 unsigned HalfSize = VT.getVectorNumElements()/2; 3693 3694 unsigned FstHalf = 0, SndHalf = 0; 3695 for (unsigned i = 0; i < HalfSize; ++i) { 3696 if (SVOp->getMaskElt(i) > 0) { 3697 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3698 break; 3699 } 3700 } 3701 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3702 if (SVOp->getMaskElt(i) > 0) { 3703 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3704 break; 3705 } 3706 } 3707 3708 return (FstHalf | (SndHalf << 4)); 3709} 3710 3711/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3712/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3713/// Note that VPERMIL mask matching is different depending whether theunderlying 3714/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3715/// to the same elements of the low, but to the higher half of the source. 3716/// In VPERMILPD the two lanes could be shuffled independently of each other 3717/// with the same restriction that lanes can't be crossed. 3718static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3719 if (!HasAVX) 3720 return false; 3721 3722 unsigned NumElts = VT.getVectorNumElements(); 3723 // Only match 256-bit with 32/64-bit types 3724 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3725 return false; 3726 3727 unsigned NumLanes = VT.getSizeInBits()/128; 3728 unsigned LaneSize = NumElts/NumLanes; 3729 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3730 for (unsigned i = 0; i != LaneSize; ++i) { 3731 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3732 return false; 3733 if (NumElts != 8 || l == 0) 3734 continue; 3735 // VPERMILPS handling 3736 if (Mask[i] < 0) 3737 continue; 3738 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3739 return false; 3740 } 3741 } 3742 3743 return true; 3744} 3745 3746/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3747/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3748/// element of vector 2 and the other elements to come from vector 1 in order. 3749static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3750 bool V2IsSplat = false, bool V2IsUndef = false) { 3751 unsigned NumOps = VT.getVectorNumElements(); 3752 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3753 return false; 3754 3755 if (!isUndefOrEqual(Mask[0], 0)) 3756 return false; 3757 3758 for (unsigned i = 1; i != NumOps; ++i) 3759 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3760 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3761 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3762 return false; 3763 3764 return true; 3765} 3766 3767static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3768 bool V2IsUndef = false) { 3769 return isCommutedMOVLMask(N->getMask(), N->getValueType(0), 3770 V2IsSplat, V2IsUndef); 3771} 3772 3773/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3774/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3775/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3776bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3777 const X86Subtarget *Subtarget) { 3778 if (!Subtarget->hasSSE3()) 3779 return false; 3780 3781 // The second vector must be undef 3782 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3783 return false; 3784 3785 EVT VT = N->getValueType(0); 3786 unsigned NumElems = VT.getVectorNumElements(); 3787 3788 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3789 (VT.getSizeInBits() == 256 && NumElems != 8)) 3790 return false; 3791 3792 // "i+1" is the value the indexed mask element must have 3793 for (unsigned i = 0; i < NumElems; i += 2) 3794 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3795 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3796 return false; 3797 3798 return true; 3799} 3800 3801/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3802/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3803/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3804bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3805 const X86Subtarget *Subtarget) { 3806 if (!Subtarget->hasSSE3()) 3807 return false; 3808 3809 // The second vector must be undef 3810 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3811 return false; 3812 3813 EVT VT = N->getValueType(0); 3814 unsigned NumElems = VT.getVectorNumElements(); 3815 3816 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3817 (VT.getSizeInBits() == 256 && NumElems != 8)) 3818 return false; 3819 3820 // "i" is the value the indexed mask element must have 3821 for (unsigned i = 0; i != NumElems; i += 2) 3822 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3823 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3824 return false; 3825 3826 return true; 3827} 3828 3829/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3830/// specifies a shuffle of elements that is suitable for input to 256-bit 3831/// version of MOVDDUP. 3832static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3833 unsigned NumElts = VT.getVectorNumElements(); 3834 3835 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3836 return false; 3837 3838 for (unsigned i = 0; i != NumElts/2; ++i) 3839 if (!isUndefOrEqual(Mask[i], 0)) 3840 return false; 3841 for (unsigned i = NumElts/2; i != NumElts; ++i) 3842 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3843 return false; 3844 return true; 3845} 3846 3847/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3848/// specifies a shuffle of elements that is suitable for input to 128-bit 3849/// version of MOVDDUP. 3850bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3851 EVT VT = N->getValueType(0); 3852 3853 if (VT.getSizeInBits() != 128) 3854 return false; 3855 3856 unsigned e = VT.getVectorNumElements() / 2; 3857 for (unsigned i = 0; i != e; ++i) 3858 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3859 return false; 3860 for (unsigned i = 0; i != e; ++i) 3861 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3862 return false; 3863 return true; 3864} 3865 3866/// isVEXTRACTF128Index - Return true if the specified 3867/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3868/// suitable for input to VEXTRACTF128. 3869bool X86::isVEXTRACTF128Index(SDNode *N) { 3870 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3871 return false; 3872 3873 // The index should be aligned on a 128-bit boundary. 3874 uint64_t Index = 3875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3876 3877 unsigned VL = N->getValueType(0).getVectorNumElements(); 3878 unsigned VBits = N->getValueType(0).getSizeInBits(); 3879 unsigned ElSize = VBits / VL; 3880 bool Result = (Index * ElSize) % 128 == 0; 3881 3882 return Result; 3883} 3884 3885/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3886/// operand specifies a subvector insert that is suitable for input to 3887/// VINSERTF128. 3888bool X86::isVINSERTF128Index(SDNode *N) { 3889 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3890 return false; 3891 3892 // The index should be aligned on a 128-bit boundary. 3893 uint64_t Index = 3894 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3895 3896 unsigned VL = N->getValueType(0).getVectorNumElements(); 3897 unsigned VBits = N->getValueType(0).getSizeInBits(); 3898 unsigned ElSize = VBits / VL; 3899 bool Result = (Index * ElSize) % 128 == 0; 3900 3901 return Result; 3902} 3903 3904/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3905/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3906/// Handles 128-bit and 256-bit. 3907unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3908 EVT VT = N->getValueType(0); 3909 3910 assert((VT.is128BitVector() || VT.is256BitVector()) && 3911 "Unsupported vector type for PSHUF/SHUFP"); 3912 3913 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3914 // independently on 128-bit lanes. 3915 unsigned NumElts = VT.getVectorNumElements(); 3916 unsigned NumLanes = VT.getSizeInBits()/128; 3917 unsigned NumLaneElts = NumElts/NumLanes; 3918 3919 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3920 "Only supports 2 or 4 elements per lane"); 3921 3922 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3923 unsigned Mask = 0; 3924 for (unsigned i = 0; i != NumElts; ++i) { 3925 int Elt = N->getMaskElt(i); 3926 if (Elt < 0) continue; 3927 Elt %= NumLaneElts; 3928 unsigned ShAmt = i << Shift; 3929 if (ShAmt >= 8) ShAmt -= 8; 3930 Mask |= Elt << ShAmt; 3931 } 3932 3933 return Mask; 3934} 3935 3936/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3937/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3938unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3939 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3940 unsigned Mask = 0; 3941 // 8 nodes, but we only care about the last 4. 3942 for (unsigned i = 7; i >= 4; --i) { 3943 int Val = SVOp->getMaskElt(i); 3944 if (Val >= 0) 3945 Mask |= (Val - 4); 3946 if (i != 4) 3947 Mask <<= 2; 3948 } 3949 return Mask; 3950} 3951 3952/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3953/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3954unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3955 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3956 unsigned Mask = 0; 3957 // 8 nodes, but we only care about the first 4. 3958 for (int i = 3; i >= 0; --i) { 3959 int Val = SVOp->getMaskElt(i); 3960 if (Val >= 0) 3961 Mask |= Val; 3962 if (i != 0) 3963 Mask <<= 2; 3964 } 3965 return Mask; 3966} 3967 3968/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3969/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3970static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3971 EVT VT = SVOp->getValueType(0); 3972 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3973 3974 unsigned NumElts = VT.getVectorNumElements(); 3975 unsigned NumLanes = VT.getSizeInBits()/128; 3976 unsigned NumLaneElts = NumElts/NumLanes; 3977 3978 int Val = 0; 3979 unsigned i; 3980 for (i = 0; i != NumElts; ++i) { 3981 Val = SVOp->getMaskElt(i); 3982 if (Val >= 0) 3983 break; 3984 } 3985 if (Val >= (int)NumElts) 3986 Val -= NumElts - NumLaneElts; 3987 3988 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3989 return (Val - i) * EltSize; 3990} 3991 3992/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3993/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3994/// instructions. 3995unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3996 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3997 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3998 3999 uint64_t Index = 4000 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4001 4002 EVT VecVT = N->getOperand(0).getValueType(); 4003 EVT ElVT = VecVT.getVectorElementType(); 4004 4005 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4006 return Index / NumElemsPerChunk; 4007} 4008 4009/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4010/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4011/// instructions. 4012unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4013 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4014 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4015 4016 uint64_t Index = 4017 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4018 4019 EVT VecVT = N->getValueType(0); 4020 EVT ElVT = VecVT.getVectorElementType(); 4021 4022 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4023 return Index / NumElemsPerChunk; 4024} 4025 4026/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4027/// constant +0.0. 4028bool X86::isZeroNode(SDValue Elt) { 4029 return ((isa<ConstantSDNode>(Elt) && 4030 cast<ConstantSDNode>(Elt)->isNullValue()) || 4031 (isa<ConstantFPSDNode>(Elt) && 4032 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4033} 4034 4035/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4036/// their permute mask. 4037static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4038 SelectionDAG &DAG) { 4039 EVT VT = SVOp->getValueType(0); 4040 unsigned NumElems = VT.getVectorNumElements(); 4041 SmallVector<int, 8> MaskVec; 4042 4043 for (unsigned i = 0; i != NumElems; ++i) { 4044 int idx = SVOp->getMaskElt(i); 4045 if (idx < 0) 4046 MaskVec.push_back(idx); 4047 else if (idx < (int)NumElems) 4048 MaskVec.push_back(idx + NumElems); 4049 else 4050 MaskVec.push_back(idx - NumElems); 4051 } 4052 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4053 SVOp->getOperand(0), &MaskVec[0]); 4054} 4055 4056/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4057/// match movhlps. The lower half elements should come from upper half of 4058/// V1 (and in order), and the upper half elements should come from the upper 4059/// half of V2 (and in order). 4060static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4061 EVT VT = Op->getValueType(0); 4062 if (VT.getSizeInBits() != 128) 4063 return false; 4064 if (VT.getVectorNumElements() != 4) 4065 return false; 4066 for (unsigned i = 0, e = 2; i != e; ++i) 4067 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4068 return false; 4069 for (unsigned i = 2; i != 4; ++i) 4070 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4071 return false; 4072 return true; 4073} 4074 4075/// isScalarLoadToVector - Returns true if the node is a scalar load that 4076/// is promoted to a vector. It also returns the LoadSDNode by reference if 4077/// required. 4078static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4079 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4080 return false; 4081 N = N->getOperand(0).getNode(); 4082 if (!ISD::isNON_EXTLoad(N)) 4083 return false; 4084 if (LD) 4085 *LD = cast<LoadSDNode>(N); 4086 return true; 4087} 4088 4089// Test whether the given value is a vector value which will be legalized 4090// into a load. 4091static bool WillBeConstantPoolLoad(SDNode *N) { 4092 if (N->getOpcode() != ISD::BUILD_VECTOR) 4093 return false; 4094 4095 // Check for any non-constant elements. 4096 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4097 switch (N->getOperand(i).getNode()->getOpcode()) { 4098 case ISD::UNDEF: 4099 case ISD::ConstantFP: 4100 case ISD::Constant: 4101 break; 4102 default: 4103 return false; 4104 } 4105 4106 // Vectors of all-zeros and all-ones are materialized with special 4107 // instructions rather than being loaded. 4108 return !ISD::isBuildVectorAllZeros(N) && 4109 !ISD::isBuildVectorAllOnes(N); 4110} 4111 4112/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4113/// match movlp{s|d}. The lower half elements should come from lower half of 4114/// V1 (and in order), and the upper half elements should come from the upper 4115/// half of V2 (and in order). And since V1 will become the source of the 4116/// MOVLP, it must be either a vector load or a scalar load to vector. 4117static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4118 ShuffleVectorSDNode *Op) { 4119 EVT VT = Op->getValueType(0); 4120 if (VT.getSizeInBits() != 128) 4121 return false; 4122 4123 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4124 return false; 4125 // Is V2 is a vector load, don't do this transformation. We will try to use 4126 // load folding shufps op. 4127 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4128 return false; 4129 4130 unsigned NumElems = VT.getVectorNumElements(); 4131 4132 if (NumElems != 2 && NumElems != 4) 4133 return false; 4134 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4135 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4136 return false; 4137 for (unsigned i = NumElems/2; i != NumElems; ++i) 4138 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4139 return false; 4140 return true; 4141} 4142 4143/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4144/// all the same. 4145static bool isSplatVector(SDNode *N) { 4146 if (N->getOpcode() != ISD::BUILD_VECTOR) 4147 return false; 4148 4149 SDValue SplatValue = N->getOperand(0); 4150 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4151 if (N->getOperand(i) != SplatValue) 4152 return false; 4153 return true; 4154} 4155 4156/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4157/// to an zero vector. 4158/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4159static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4160 SDValue V1 = N->getOperand(0); 4161 SDValue V2 = N->getOperand(1); 4162 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4163 for (unsigned i = 0; i != NumElems; ++i) { 4164 int Idx = N->getMaskElt(i); 4165 if (Idx >= (int)NumElems) { 4166 unsigned Opc = V2.getOpcode(); 4167 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4168 continue; 4169 if (Opc != ISD::BUILD_VECTOR || 4170 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4171 return false; 4172 } else if (Idx >= 0) { 4173 unsigned Opc = V1.getOpcode(); 4174 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4175 continue; 4176 if (Opc != ISD::BUILD_VECTOR || 4177 !X86::isZeroNode(V1.getOperand(Idx))) 4178 return false; 4179 } 4180 } 4181 return true; 4182} 4183 4184/// getZeroVector - Returns a vector of specified type with all zero elements. 4185/// 4186static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4187 SelectionDAG &DAG, DebugLoc dl) { 4188 assert(VT.isVector() && "Expected a vector type"); 4189 4190 // Always build SSE zero vectors as <4 x i32> bitcasted 4191 // to their dest type. This ensures they get CSE'd. 4192 SDValue Vec; 4193 if (VT.getSizeInBits() == 128) { // SSE 4194 if (Subtarget->hasSSE2()) { // SSE2 4195 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4196 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4197 } else { // SSE1 4198 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4199 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4200 } 4201 } else if (VT.getSizeInBits() == 256) { // AVX 4202 if (Subtarget->hasAVX2()) { // AVX2 4203 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4204 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4206 } else { 4207 // 256-bit logic and arithmetic instructions in AVX are all 4208 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4209 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4210 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4212 } 4213 } 4214 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4215} 4216 4217/// getOnesVector - Returns a vector of specified type with all bits set. 4218/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4219/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4220/// Then bitcast to their original type, ensuring they get CSE'd. 4221static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4222 DebugLoc dl) { 4223 assert(VT.isVector() && "Expected a vector type"); 4224 assert((VT.is128BitVector() || VT.is256BitVector()) 4225 && "Expected a 128-bit or 256-bit vector type"); 4226 4227 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4228 SDValue Vec; 4229 if (VT.getSizeInBits() == 256) { 4230 if (HasAVX2) { // AVX2 4231 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4232 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4233 } else { // AVX 4234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4235 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4236 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4237 Vec = Insert128BitVector(InsV, Vec, 4238 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4239 } 4240 } else { 4241 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4242 } 4243 4244 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4245} 4246 4247/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4248/// that point to V2 points to its first element. 4249static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4250 EVT VT = SVOp->getValueType(0); 4251 unsigned NumElems = VT.getVectorNumElements(); 4252 4253 bool Changed = false; 4254 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end()); 4255 4256 for (unsigned i = 0; i != NumElems; ++i) { 4257 if (MaskVec[i] > (int)NumElems) { 4258 MaskVec[i] = NumElems; 4259 Changed = true; 4260 } 4261 } 4262 if (Changed) 4263 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4264 SVOp->getOperand(1), &MaskVec[0]); 4265 return SDValue(SVOp, 0); 4266} 4267 4268/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4269/// operation of specified width. 4270static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4271 SDValue V2) { 4272 unsigned NumElems = VT.getVectorNumElements(); 4273 SmallVector<int, 8> Mask; 4274 Mask.push_back(NumElems); 4275 for (unsigned i = 1; i != NumElems; ++i) 4276 Mask.push_back(i); 4277 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4278} 4279 4280/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4281static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4282 SDValue V2) { 4283 unsigned NumElems = VT.getVectorNumElements(); 4284 SmallVector<int, 8> Mask; 4285 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4286 Mask.push_back(i); 4287 Mask.push_back(i + NumElems); 4288 } 4289 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4290} 4291 4292/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4293static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4294 SDValue V2) { 4295 unsigned NumElems = VT.getVectorNumElements(); 4296 unsigned Half = NumElems/2; 4297 SmallVector<int, 8> Mask; 4298 for (unsigned i = 0; i != Half; ++i) { 4299 Mask.push_back(i + Half); 4300 Mask.push_back(i + NumElems + Half); 4301 } 4302 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4303} 4304 4305// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4306// a generic shuffle instruction because the target has no such instructions. 4307// Generate shuffles which repeat i16 and i8 several times until they can be 4308// represented by v4f32 and then be manipulated by target suported shuffles. 4309static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4310 EVT VT = V.getValueType(); 4311 int NumElems = VT.getVectorNumElements(); 4312 DebugLoc dl = V.getDebugLoc(); 4313 4314 while (NumElems > 4) { 4315 if (EltNo < NumElems/2) { 4316 V = getUnpackl(DAG, dl, VT, V, V); 4317 } else { 4318 V = getUnpackh(DAG, dl, VT, V, V); 4319 EltNo -= NumElems/2; 4320 } 4321 NumElems >>= 1; 4322 } 4323 return V; 4324} 4325 4326/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4327static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4328 EVT VT = V.getValueType(); 4329 DebugLoc dl = V.getDebugLoc(); 4330 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4331 && "Vector size not supported"); 4332 4333 if (VT.getSizeInBits() == 128) { 4334 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4335 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4336 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4337 &SplatMask[0]); 4338 } else { 4339 // To use VPERMILPS to splat scalars, the second half of indicies must 4340 // refer to the higher part, which is a duplication of the lower one, 4341 // because VPERMILPS can only handle in-lane permutations. 4342 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4343 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4344 4345 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4346 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4347 &SplatMask[0]); 4348 } 4349 4350 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4351} 4352 4353/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4354static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4355 EVT SrcVT = SV->getValueType(0); 4356 SDValue V1 = SV->getOperand(0); 4357 DebugLoc dl = SV->getDebugLoc(); 4358 4359 int EltNo = SV->getSplatIndex(); 4360 int NumElems = SrcVT.getVectorNumElements(); 4361 unsigned Size = SrcVT.getSizeInBits(); 4362 4363 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4364 "Unknown how to promote splat for type"); 4365 4366 // Extract the 128-bit part containing the splat element and update 4367 // the splat element index when it refers to the higher register. 4368 if (Size == 256) { 4369 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4370 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4371 if (Idx > 0) 4372 EltNo -= NumElems/2; 4373 } 4374 4375 // All i16 and i8 vector types can't be used directly by a generic shuffle 4376 // instruction because the target has no such instruction. Generate shuffles 4377 // which repeat i16 and i8 several times until they fit in i32, and then can 4378 // be manipulated by target suported shuffles. 4379 EVT EltVT = SrcVT.getVectorElementType(); 4380 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4381 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4382 4383 // Recreate the 256-bit vector and place the same 128-bit vector 4384 // into the low and high part. This is necessary because we want 4385 // to use VPERM* to shuffle the vectors 4386 if (Size == 256) { 4387 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4388 DAG.getConstant(0, MVT::i32), DAG, dl); 4389 V1 = Insert128BitVector(InsV, V1, 4390 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4391 } 4392 4393 return getLegalSplat(DAG, V1, EltNo); 4394} 4395 4396/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4397/// vector of zero or undef vector. This produces a shuffle where the low 4398/// element of V2 is swizzled into the zero/undef vector, landing at element 4399/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4400static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4401 bool IsZero, 4402 const X86Subtarget *Subtarget, 4403 SelectionDAG &DAG) { 4404 EVT VT = V2.getValueType(); 4405 SDValue V1 = IsZero 4406 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4407 unsigned NumElems = VT.getVectorNumElements(); 4408 SmallVector<int, 16> MaskVec; 4409 for (unsigned i = 0; i != NumElems; ++i) 4410 // If this is the insertion idx, put the low elt of V2 here. 4411 MaskVec.push_back(i == Idx ? NumElems : i); 4412 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4413} 4414 4415/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4416/// element of the result of the vector shuffle. 4417static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4418 unsigned Depth) { 4419 if (Depth == 6) 4420 return SDValue(); // Limit search depth. 4421 4422 SDValue V = SDValue(N, 0); 4423 EVT VT = V.getValueType(); 4424 unsigned Opcode = V.getOpcode(); 4425 4426 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4427 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4428 Index = SV->getMaskElt(Index); 4429 4430 if (Index < 0) 4431 return DAG.getUNDEF(VT.getVectorElementType()); 4432 4433 int NumElems = VT.getVectorNumElements(); 4434 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4435 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4436 } 4437 4438 // Recurse into target specific vector shuffles to find scalars. 4439 if (isTargetShuffle(Opcode)) { 4440 int NumElems = VT.getVectorNumElements(); 4441 SmallVector<unsigned, 16> ShuffleMask; 4442 SDValue ImmN; 4443 4444 switch(Opcode) { 4445 case X86ISD::SHUFP: 4446 ImmN = N->getOperand(N->getNumOperands()-1); 4447 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4448 ShuffleMask); 4449 break; 4450 case X86ISD::UNPCKH: 4451 DecodeUNPCKHMask(VT, ShuffleMask); 4452 break; 4453 case X86ISD::UNPCKL: 4454 DecodeUNPCKLMask(VT, ShuffleMask); 4455 break; 4456 case X86ISD::MOVHLPS: 4457 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4458 break; 4459 case X86ISD::MOVLHPS: 4460 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4461 break; 4462 case X86ISD::PSHUFD: 4463 ImmN = N->getOperand(N->getNumOperands()-1); 4464 DecodePSHUFMask(NumElems, 4465 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4466 ShuffleMask); 4467 break; 4468 case X86ISD::PSHUFHW: 4469 ImmN = N->getOperand(N->getNumOperands()-1); 4470 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4471 ShuffleMask); 4472 break; 4473 case X86ISD::PSHUFLW: 4474 ImmN = N->getOperand(N->getNumOperands()-1); 4475 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4476 ShuffleMask); 4477 break; 4478 case X86ISD::MOVSS: 4479 case X86ISD::MOVSD: { 4480 // The index 0 always comes from the first element of the second source, 4481 // this is why MOVSS and MOVSD are used in the first place. The other 4482 // elements come from the other positions of the first source vector. 4483 unsigned OpNum = (Index == 0) ? 1 : 0; 4484 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4485 Depth+1); 4486 } 4487 case X86ISD::VPERMILP: 4488 ImmN = N->getOperand(N->getNumOperands()-1); 4489 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4490 ShuffleMask); 4491 break; 4492 case X86ISD::VPERM2X128: 4493 ImmN = N->getOperand(N->getNumOperands()-1); 4494 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4495 ShuffleMask); 4496 break; 4497 case X86ISD::MOVDDUP: 4498 case X86ISD::MOVLHPD: 4499 case X86ISD::MOVLPD: 4500 case X86ISD::MOVLPS: 4501 case X86ISD::MOVSHDUP: 4502 case X86ISD::MOVSLDUP: 4503 case X86ISD::PALIGN: 4504 return SDValue(); // Not yet implemented. 4505 default: llvm_unreachable("unknown target shuffle node"); 4506 } 4507 4508 Index = ShuffleMask[Index]; 4509 if (Index < 0) 4510 return DAG.getUNDEF(VT.getVectorElementType()); 4511 4512 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4513 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4514 Depth+1); 4515 } 4516 4517 // Actual nodes that may contain scalar elements 4518 if (Opcode == ISD::BITCAST) { 4519 V = V.getOperand(0); 4520 EVT SrcVT = V.getValueType(); 4521 unsigned NumElems = VT.getVectorNumElements(); 4522 4523 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4524 return SDValue(); 4525 } 4526 4527 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4528 return (Index == 0) ? V.getOperand(0) 4529 : DAG.getUNDEF(VT.getVectorElementType()); 4530 4531 if (V.getOpcode() == ISD::BUILD_VECTOR) 4532 return V.getOperand(Index); 4533 4534 return SDValue(); 4535} 4536 4537/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4538/// shuffle operation which come from a consecutively from a zero. The 4539/// search can start in two different directions, from left or right. 4540static 4541unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4542 bool ZerosFromLeft, SelectionDAG &DAG) { 4543 int i = 0; 4544 4545 while (i < NumElems) { 4546 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4547 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4548 if (!(Elt.getNode() && 4549 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4550 break; 4551 ++i; 4552 } 4553 4554 return i; 4555} 4556 4557/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4558/// MaskE correspond consecutively to elements from one of the vector operands, 4559/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4560static 4561bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4562 int OpIdx, int NumElems, unsigned &OpNum) { 4563 bool SeenV1 = false; 4564 bool SeenV2 = false; 4565 4566 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4567 int Idx = SVOp->getMaskElt(i); 4568 // Ignore undef indicies 4569 if (Idx < 0) 4570 continue; 4571 4572 if (Idx < NumElems) 4573 SeenV1 = true; 4574 else 4575 SeenV2 = true; 4576 4577 // Only accept consecutive elements from the same vector 4578 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4579 return false; 4580 } 4581 4582 OpNum = SeenV1 ? 0 : 1; 4583 return true; 4584} 4585 4586/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4587/// logical left shift of a vector. 4588static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4589 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4590 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4591 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4592 false /* check zeros from right */, DAG); 4593 unsigned OpSrc; 4594 4595 if (!NumZeros) 4596 return false; 4597 4598 // Considering the elements in the mask that are not consecutive zeros, 4599 // check if they consecutively come from only one of the source vectors. 4600 // 4601 // V1 = {X, A, B, C} 0 4602 // \ \ \ / 4603 // vector_shuffle V1, V2 <1, 2, 3, X> 4604 // 4605 if (!isShuffleMaskConsecutive(SVOp, 4606 0, // Mask Start Index 4607 NumElems-NumZeros-1, // Mask End Index 4608 NumZeros, // Where to start looking in the src vector 4609 NumElems, // Number of elements in vector 4610 OpSrc)) // Which source operand ? 4611 return false; 4612 4613 isLeft = false; 4614 ShAmt = NumZeros; 4615 ShVal = SVOp->getOperand(OpSrc); 4616 return true; 4617} 4618 4619/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4620/// logical left shift of a vector. 4621static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4622 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4623 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4624 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4625 true /* check zeros from left */, DAG); 4626 unsigned OpSrc; 4627 4628 if (!NumZeros) 4629 return false; 4630 4631 // Considering the elements in the mask that are not consecutive zeros, 4632 // check if they consecutively come from only one of the source vectors. 4633 // 4634 // 0 { A, B, X, X } = V2 4635 // / \ / / 4636 // vector_shuffle V1, V2 <X, X, 4, 5> 4637 // 4638 if (!isShuffleMaskConsecutive(SVOp, 4639 NumZeros, // Mask Start Index 4640 NumElems-1, // Mask End Index 4641 0, // Where to start looking in the src vector 4642 NumElems, // Number of elements in vector 4643 OpSrc)) // Which source operand ? 4644 return false; 4645 4646 isLeft = true; 4647 ShAmt = NumZeros; 4648 ShVal = SVOp->getOperand(OpSrc); 4649 return true; 4650} 4651 4652/// isVectorShift - Returns true if the shuffle can be implemented as a 4653/// logical left or right shift of a vector. 4654static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4655 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4656 // Although the logic below support any bitwidth size, there are no 4657 // shift instructions which handle more than 128-bit vectors. 4658 if (SVOp->getValueType(0).getSizeInBits() > 128) 4659 return false; 4660 4661 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4662 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4663 return true; 4664 4665 return false; 4666} 4667 4668/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4669/// 4670static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4671 unsigned NumNonZero, unsigned NumZero, 4672 SelectionDAG &DAG, 4673 const X86Subtarget* Subtarget, 4674 const TargetLowering &TLI) { 4675 if (NumNonZero > 8) 4676 return SDValue(); 4677 4678 DebugLoc dl = Op.getDebugLoc(); 4679 SDValue V(0, 0); 4680 bool First = true; 4681 for (unsigned i = 0; i < 16; ++i) { 4682 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4683 if (ThisIsNonZero && First) { 4684 if (NumZero) 4685 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4686 else 4687 V = DAG.getUNDEF(MVT::v8i16); 4688 First = false; 4689 } 4690 4691 if ((i & 1) != 0) { 4692 SDValue ThisElt(0, 0), LastElt(0, 0); 4693 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4694 if (LastIsNonZero) { 4695 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4696 MVT::i16, Op.getOperand(i-1)); 4697 } 4698 if (ThisIsNonZero) { 4699 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4700 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4701 ThisElt, DAG.getConstant(8, MVT::i8)); 4702 if (LastIsNonZero) 4703 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4704 } else 4705 ThisElt = LastElt; 4706 4707 if (ThisElt.getNode()) 4708 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4709 DAG.getIntPtrConstant(i/2)); 4710 } 4711 } 4712 4713 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4714} 4715 4716/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4717/// 4718static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4719 unsigned NumNonZero, unsigned NumZero, 4720 SelectionDAG &DAG, 4721 const X86Subtarget* Subtarget, 4722 const TargetLowering &TLI) { 4723 if (NumNonZero > 4) 4724 return SDValue(); 4725 4726 DebugLoc dl = Op.getDebugLoc(); 4727 SDValue V(0, 0); 4728 bool First = true; 4729 for (unsigned i = 0; i < 8; ++i) { 4730 bool isNonZero = (NonZeros & (1 << i)) != 0; 4731 if (isNonZero) { 4732 if (First) { 4733 if (NumZero) 4734 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4735 else 4736 V = DAG.getUNDEF(MVT::v8i16); 4737 First = false; 4738 } 4739 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4740 MVT::v8i16, V, Op.getOperand(i), 4741 DAG.getIntPtrConstant(i)); 4742 } 4743 } 4744 4745 return V; 4746} 4747 4748/// getVShift - Return a vector logical shift node. 4749/// 4750static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4751 unsigned NumBits, SelectionDAG &DAG, 4752 const TargetLowering &TLI, DebugLoc dl) { 4753 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4754 EVT ShVT = MVT::v2i64; 4755 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4756 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4757 return DAG.getNode(ISD::BITCAST, dl, VT, 4758 DAG.getNode(Opc, dl, ShVT, SrcOp, 4759 DAG.getConstant(NumBits, 4760 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4761} 4762 4763SDValue 4764X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4765 SelectionDAG &DAG) const { 4766 4767 // Check if the scalar load can be widened into a vector load. And if 4768 // the address is "base + cst" see if the cst can be "absorbed" into 4769 // the shuffle mask. 4770 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4771 SDValue Ptr = LD->getBasePtr(); 4772 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4773 return SDValue(); 4774 EVT PVT = LD->getValueType(0); 4775 if (PVT != MVT::i32 && PVT != MVT::f32) 4776 return SDValue(); 4777 4778 int FI = -1; 4779 int64_t Offset = 0; 4780 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4781 FI = FINode->getIndex(); 4782 Offset = 0; 4783 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4784 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4785 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4786 Offset = Ptr.getConstantOperandVal(1); 4787 Ptr = Ptr.getOperand(0); 4788 } else { 4789 return SDValue(); 4790 } 4791 4792 // FIXME: 256-bit vector instructions don't require a strict alignment, 4793 // improve this code to support it better. 4794 unsigned RequiredAlign = VT.getSizeInBits()/8; 4795 SDValue Chain = LD->getChain(); 4796 // Make sure the stack object alignment is at least 16 or 32. 4797 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4798 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4799 if (MFI->isFixedObjectIndex(FI)) { 4800 // Can't change the alignment. FIXME: It's possible to compute 4801 // the exact stack offset and reference FI + adjust offset instead. 4802 // If someone *really* cares about this. That's the way to implement it. 4803 return SDValue(); 4804 } else { 4805 MFI->setObjectAlignment(FI, RequiredAlign); 4806 } 4807 } 4808 4809 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4810 // Ptr + (Offset & ~15). 4811 if (Offset < 0) 4812 return SDValue(); 4813 if ((Offset % RequiredAlign) & 3) 4814 return SDValue(); 4815 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4816 if (StartOffset) 4817 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4818 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4819 4820 int EltNo = (Offset - StartOffset) >> 2; 4821 int NumElems = VT.getVectorNumElements(); 4822 4823 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4824 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4825 LD->getPointerInfo().getWithOffset(StartOffset), 4826 false, false, false, 0); 4827 4828 SmallVector<int, 8> Mask; 4829 for (int i = 0; i < NumElems; ++i) 4830 Mask.push_back(EltNo); 4831 4832 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4833 } 4834 4835 return SDValue(); 4836} 4837 4838/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4839/// vector of type 'VT', see if the elements can be replaced by a single large 4840/// load which has the same value as a build_vector whose operands are 'elts'. 4841/// 4842/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4843/// 4844/// FIXME: we'd also like to handle the case where the last elements are zero 4845/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4846/// There's even a handy isZeroNode for that purpose. 4847static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4848 DebugLoc &DL, SelectionDAG &DAG) { 4849 EVT EltVT = VT.getVectorElementType(); 4850 unsigned NumElems = Elts.size(); 4851 4852 LoadSDNode *LDBase = NULL; 4853 unsigned LastLoadedElt = -1U; 4854 4855 // For each element in the initializer, see if we've found a load or an undef. 4856 // If we don't find an initial load element, or later load elements are 4857 // non-consecutive, bail out. 4858 for (unsigned i = 0; i < NumElems; ++i) { 4859 SDValue Elt = Elts[i]; 4860 4861 if (!Elt.getNode() || 4862 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4863 return SDValue(); 4864 if (!LDBase) { 4865 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4866 return SDValue(); 4867 LDBase = cast<LoadSDNode>(Elt.getNode()); 4868 LastLoadedElt = i; 4869 continue; 4870 } 4871 if (Elt.getOpcode() == ISD::UNDEF) 4872 continue; 4873 4874 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4875 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4876 return SDValue(); 4877 LastLoadedElt = i; 4878 } 4879 4880 // If we have found an entire vector of loads and undefs, then return a large 4881 // load of the entire vector width starting at the base pointer. If we found 4882 // consecutive loads for the low half, generate a vzext_load node. 4883 if (LastLoadedElt == NumElems - 1) { 4884 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4885 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4886 LDBase->getPointerInfo(), 4887 LDBase->isVolatile(), LDBase->isNonTemporal(), 4888 LDBase->isInvariant(), 0); 4889 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4890 LDBase->getPointerInfo(), 4891 LDBase->isVolatile(), LDBase->isNonTemporal(), 4892 LDBase->isInvariant(), LDBase->getAlignment()); 4893 } else if (NumElems == 4 && LastLoadedElt == 1 && 4894 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4895 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4896 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4897 SDValue ResNode = 4898 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4899 LDBase->getPointerInfo(), 4900 LDBase->getAlignment(), 4901 false/*isVolatile*/, true/*ReadMem*/, 4902 false/*WriteMem*/); 4903 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4904 } 4905 return SDValue(); 4906} 4907 4908/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4909/// a vbroadcast node. We support two patterns: 4910/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4911/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4912/// a scalar load. 4913/// The scalar load node is returned when a pattern is found, 4914/// or SDValue() otherwise. 4915static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) { 4916 if (!Subtarget->hasAVX()) 4917 return SDValue(); 4918 4919 EVT VT = Op.getValueType(); 4920 SDValue V = Op; 4921 4922 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4923 V = V.getOperand(0); 4924 4925 //A suspected load to be broadcasted. 4926 SDValue Ld; 4927 4928 switch (V.getOpcode()) { 4929 default: 4930 // Unknown pattern found. 4931 return SDValue(); 4932 4933 case ISD::BUILD_VECTOR: { 4934 // The BUILD_VECTOR node must be a splat. 4935 if (!isSplatVector(V.getNode())) 4936 return SDValue(); 4937 4938 Ld = V.getOperand(0); 4939 4940 // The suspected load node has several users. Make sure that all 4941 // of its users are from the BUILD_VECTOR node. 4942 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4943 return SDValue(); 4944 break; 4945 } 4946 4947 case ISD::VECTOR_SHUFFLE: { 4948 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4949 4950 // Shuffles must have a splat mask where the first element is 4951 // broadcasted. 4952 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4953 return SDValue(); 4954 4955 SDValue Sc = Op.getOperand(0); 4956 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4957 return SDValue(); 4958 4959 Ld = Sc.getOperand(0); 4960 4961 // The scalar_to_vector node and the suspected 4962 // load node must have exactly one user. 4963 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 4964 return SDValue(); 4965 break; 4966 } 4967 } 4968 4969 // The scalar source must be a normal load. 4970 if (!ISD::isNormalLoad(Ld.getNode())) 4971 return SDValue(); 4972 4973 // Reject loads that have uses of the chain result 4974 if (Ld->hasAnyUseOfValue(1)) 4975 return SDValue(); 4976 4977 bool Is256 = VT.getSizeInBits() == 256; 4978 bool Is128 = VT.getSizeInBits() == 128; 4979 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4980 4981 // VBroadcast to YMM 4982 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4983 return Ld; 4984 4985 // VBroadcast to XMM 4986 if (Is128 && (ScalarSize == 32)) 4987 return Ld; 4988 4989 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 4990 // double since there is vbroadcastsd xmm 4991 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 4992 // VBroadcast to YMM 4993 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 4994 return Ld; 4995 4996 // VBroadcast to XMM 4997 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 4998 return Ld; 4999 } 5000 5001 // Unsupported broadcast. 5002 return SDValue(); 5003} 5004 5005SDValue 5006X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5007 DebugLoc dl = Op.getDebugLoc(); 5008 5009 EVT VT = Op.getValueType(); 5010 EVT ExtVT = VT.getVectorElementType(); 5011 unsigned NumElems = Op.getNumOperands(); 5012 5013 // Vectors containing all zeros can be matched by pxor and xorps later 5014 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5015 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5016 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5017 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5018 return Op; 5019 5020 return getZeroVector(VT, Subtarget, DAG, dl); 5021 } 5022 5023 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5024 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5025 // vpcmpeqd on 256-bit vectors. 5026 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5027 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5028 return Op; 5029 5030 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5031 } 5032 5033 SDValue LD = isVectorBroadcast(Op, Subtarget); 5034 if (LD.getNode()) 5035 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 5036 5037 unsigned EVTBits = ExtVT.getSizeInBits(); 5038 5039 unsigned NumZero = 0; 5040 unsigned NumNonZero = 0; 5041 unsigned NonZeros = 0; 5042 bool IsAllConstants = true; 5043 SmallSet<SDValue, 8> Values; 5044 for (unsigned i = 0; i < NumElems; ++i) { 5045 SDValue Elt = Op.getOperand(i); 5046 if (Elt.getOpcode() == ISD::UNDEF) 5047 continue; 5048 Values.insert(Elt); 5049 if (Elt.getOpcode() != ISD::Constant && 5050 Elt.getOpcode() != ISD::ConstantFP) 5051 IsAllConstants = false; 5052 if (X86::isZeroNode(Elt)) 5053 NumZero++; 5054 else { 5055 NonZeros |= (1 << i); 5056 NumNonZero++; 5057 } 5058 } 5059 5060 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5061 if (NumNonZero == 0) 5062 return DAG.getUNDEF(VT); 5063 5064 // Special case for single non-zero, non-undef, element. 5065 if (NumNonZero == 1) { 5066 unsigned Idx = CountTrailingZeros_32(NonZeros); 5067 SDValue Item = Op.getOperand(Idx); 5068 5069 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5070 // the value are obviously zero, truncate the value to i32 and do the 5071 // insertion that way. Only do this if the value is non-constant or if the 5072 // value is a constant being inserted into element 0. It is cheaper to do 5073 // a constant pool load than it is to do a movd + shuffle. 5074 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5075 (!IsAllConstants || Idx == 0)) { 5076 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5077 // Handle SSE only. 5078 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5079 EVT VecVT = MVT::v4i32; 5080 unsigned VecElts = 4; 5081 5082 // Truncate the value (which may itself be a constant) to i32, and 5083 // convert it to a vector with movd (S2V+shuffle to zero extend). 5084 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5085 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5086 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5087 5088 // Now we have our 32-bit value zero extended in the low element of 5089 // a vector. If Idx != 0, swizzle it into place. 5090 if (Idx != 0) { 5091 SmallVector<int, 4> Mask; 5092 Mask.push_back(Idx); 5093 for (unsigned i = 1; i != VecElts; ++i) 5094 Mask.push_back(i); 5095 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5096 DAG.getUNDEF(Item.getValueType()), 5097 &Mask[0]); 5098 } 5099 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5100 } 5101 } 5102 5103 // If we have a constant or non-constant insertion into the low element of 5104 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5105 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5106 // depending on what the source datatype is. 5107 if (Idx == 0) { 5108 if (NumZero == 0) 5109 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5110 5111 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5112 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5113 if (VT.getSizeInBits() == 256) { 5114 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5115 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5116 Item, DAG.getIntPtrConstant(0)); 5117 } 5118 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5119 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5120 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5121 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5122 } 5123 5124 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5125 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5126 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5127 if (VT.getSizeInBits() == 256) { 5128 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5129 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5130 DAG, dl); 5131 } else { 5132 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5133 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5134 } 5135 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5136 } 5137 } 5138 5139 // Is it a vector logical left shift? 5140 if (NumElems == 2 && Idx == 1 && 5141 X86::isZeroNode(Op.getOperand(0)) && 5142 !X86::isZeroNode(Op.getOperand(1))) { 5143 unsigned NumBits = VT.getSizeInBits(); 5144 return getVShift(true, VT, 5145 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5146 VT, Op.getOperand(1)), 5147 NumBits/2, DAG, *this, dl); 5148 } 5149 5150 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5151 return SDValue(); 5152 5153 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5154 // is a non-constant being inserted into an element other than the low one, 5155 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5156 // movd/movss) to move this into the low element, then shuffle it into 5157 // place. 5158 if (EVTBits == 32) { 5159 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5160 5161 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5162 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5163 SmallVector<int, 8> MaskVec; 5164 for (unsigned i = 0; i < NumElems; i++) 5165 MaskVec.push_back(i == Idx ? 0 : 1); 5166 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5167 } 5168 } 5169 5170 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5171 if (Values.size() == 1) { 5172 if (EVTBits == 32) { 5173 // Instead of a shuffle like this: 5174 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5175 // Check if it's possible to issue this instead. 5176 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5177 unsigned Idx = CountTrailingZeros_32(NonZeros); 5178 SDValue Item = Op.getOperand(Idx); 5179 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5180 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5181 } 5182 return SDValue(); 5183 } 5184 5185 // A vector full of immediates; various special cases are already 5186 // handled, so this is best done with a single constant-pool load. 5187 if (IsAllConstants) 5188 return SDValue(); 5189 5190 // For AVX-length vectors, build the individual 128-bit pieces and use 5191 // shuffles to put them in place. 5192 if (VT.getSizeInBits() == 256) { 5193 SmallVector<SDValue, 32> V; 5194 for (unsigned i = 0; i != NumElems; ++i) 5195 V.push_back(Op.getOperand(i)); 5196 5197 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5198 5199 // Build both the lower and upper subvector. 5200 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5201 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5202 NumElems/2); 5203 5204 // Recreate the wider vector with the lower and upper part. 5205 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5206 DAG.getConstant(0, MVT::i32), DAG, dl); 5207 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5208 DAG, dl); 5209 } 5210 5211 // Let legalizer expand 2-wide build_vectors. 5212 if (EVTBits == 64) { 5213 if (NumNonZero == 1) { 5214 // One half is zero or undef. 5215 unsigned Idx = CountTrailingZeros_32(NonZeros); 5216 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5217 Op.getOperand(Idx)); 5218 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5219 } 5220 return SDValue(); 5221 } 5222 5223 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5224 if (EVTBits == 8 && NumElems == 16) { 5225 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5226 Subtarget, *this); 5227 if (V.getNode()) return V; 5228 } 5229 5230 if (EVTBits == 16 && NumElems == 8) { 5231 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5232 Subtarget, *this); 5233 if (V.getNode()) return V; 5234 } 5235 5236 // If element VT is == 32 bits, turn it into a number of shuffles. 5237 SmallVector<SDValue, 8> V(NumElems); 5238 if (NumElems == 4 && NumZero > 0) { 5239 for (unsigned i = 0; i < 4; ++i) { 5240 bool isZero = !(NonZeros & (1 << i)); 5241 if (isZero) 5242 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5243 else 5244 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5245 } 5246 5247 for (unsigned i = 0; i < 2; ++i) { 5248 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5249 default: break; 5250 case 0: 5251 V[i] = V[i*2]; // Must be a zero vector. 5252 break; 5253 case 1: 5254 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5255 break; 5256 case 2: 5257 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5258 break; 5259 case 3: 5260 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5261 break; 5262 } 5263 } 5264 5265 bool Reverse1 = (NonZeros & 0x3) == 2; 5266 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5267 int MaskVec[] = { 5268 Reverse1 ? 1 : 0, 5269 Reverse1 ? 0 : 1, 5270 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5271 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5272 }; 5273 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5274 } 5275 5276 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5277 // Check for a build vector of consecutive loads. 5278 for (unsigned i = 0; i < NumElems; ++i) 5279 V[i] = Op.getOperand(i); 5280 5281 // Check for elements which are consecutive loads. 5282 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5283 if (LD.getNode()) 5284 return LD; 5285 5286 // For SSE 4.1, use insertps to put the high elements into the low element. 5287 if (getSubtarget()->hasSSE41()) { 5288 SDValue Result; 5289 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5290 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5291 else 5292 Result = DAG.getUNDEF(VT); 5293 5294 for (unsigned i = 1; i < NumElems; ++i) { 5295 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5296 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5297 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5298 } 5299 return Result; 5300 } 5301 5302 // Otherwise, expand into a number of unpckl*, start by extending each of 5303 // our (non-undef) elements to the full vector width with the element in the 5304 // bottom slot of the vector (which generates no code for SSE). 5305 for (unsigned i = 0; i < NumElems; ++i) { 5306 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5307 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5308 else 5309 V[i] = DAG.getUNDEF(VT); 5310 } 5311 5312 // Next, we iteratively mix elements, e.g. for v4f32: 5313 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5314 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5315 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5316 unsigned EltStride = NumElems >> 1; 5317 while (EltStride != 0) { 5318 for (unsigned i = 0; i < EltStride; ++i) { 5319 // If V[i+EltStride] is undef and this is the first round of mixing, 5320 // then it is safe to just drop this shuffle: V[i] is already in the 5321 // right place, the one element (since it's the first round) being 5322 // inserted as undef can be dropped. This isn't safe for successive 5323 // rounds because they will permute elements within both vectors. 5324 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5325 EltStride == NumElems/2) 5326 continue; 5327 5328 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5329 } 5330 EltStride >>= 1; 5331 } 5332 return V[0]; 5333 } 5334 return SDValue(); 5335} 5336 5337// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5338// them in a MMX register. This is better than doing a stack convert. 5339static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5340 DebugLoc dl = Op.getDebugLoc(); 5341 EVT ResVT = Op.getValueType(); 5342 5343 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5344 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5345 int Mask[2]; 5346 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5347 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5348 InVec = Op.getOperand(1); 5349 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5350 unsigned NumElts = ResVT.getVectorNumElements(); 5351 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5352 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5353 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5354 } else { 5355 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5356 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5357 Mask[0] = 0; Mask[1] = 2; 5358 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5359 } 5360 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5361} 5362 5363// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5364// to create 256-bit vectors from two other 128-bit ones. 5365static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5366 DebugLoc dl = Op.getDebugLoc(); 5367 EVT ResVT = Op.getValueType(); 5368 5369 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5370 5371 SDValue V1 = Op.getOperand(0); 5372 SDValue V2 = Op.getOperand(1); 5373 unsigned NumElems = ResVT.getVectorNumElements(); 5374 5375 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5376 DAG.getConstant(0, MVT::i32), DAG, dl); 5377 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5378 DAG, dl); 5379} 5380 5381SDValue 5382X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5383 EVT ResVT = Op.getValueType(); 5384 5385 assert(Op.getNumOperands() == 2); 5386 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5387 "Unsupported CONCAT_VECTORS for value type"); 5388 5389 // We support concatenate two MMX registers and place them in a MMX register. 5390 // This is better than doing a stack convert. 5391 if (ResVT.is128BitVector()) 5392 return LowerMMXCONCAT_VECTORS(Op, DAG); 5393 5394 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5395 // from two other 128-bit ones. 5396 return LowerAVXCONCAT_VECTORS(Op, DAG); 5397} 5398 5399// v8i16 shuffles - Prefer shuffles in the following order: 5400// 1. [all] pshuflw, pshufhw, optional move 5401// 2. [ssse3] 1 x pshufb 5402// 3. [ssse3] 2 x pshufb + 1 x por 5403// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5404SDValue 5405X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5406 SelectionDAG &DAG) const { 5407 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5408 SDValue V1 = SVOp->getOperand(0); 5409 SDValue V2 = SVOp->getOperand(1); 5410 DebugLoc dl = SVOp->getDebugLoc(); 5411 SmallVector<int, 8> MaskVals; 5412 5413 // Determine if more than 1 of the words in each of the low and high quadwords 5414 // of the result come from the same quadword of one of the two inputs. Undef 5415 // mask values count as coming from any quadword, for better codegen. 5416 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5417 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5418 BitVector InputQuads(4); 5419 for (unsigned i = 0; i < 8; ++i) { 5420 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5421 int EltIdx = SVOp->getMaskElt(i); 5422 MaskVals.push_back(EltIdx); 5423 if (EltIdx < 0) { 5424 ++Quad[0]; 5425 ++Quad[1]; 5426 ++Quad[2]; 5427 ++Quad[3]; 5428 continue; 5429 } 5430 ++Quad[EltIdx / 4]; 5431 InputQuads.set(EltIdx / 4); 5432 } 5433 5434 int BestLoQuad = -1; 5435 unsigned MaxQuad = 1; 5436 for (unsigned i = 0; i < 4; ++i) { 5437 if (LoQuad[i] > MaxQuad) { 5438 BestLoQuad = i; 5439 MaxQuad = LoQuad[i]; 5440 } 5441 } 5442 5443 int BestHiQuad = -1; 5444 MaxQuad = 1; 5445 for (unsigned i = 0; i < 4; ++i) { 5446 if (HiQuad[i] > MaxQuad) { 5447 BestHiQuad = i; 5448 MaxQuad = HiQuad[i]; 5449 } 5450 } 5451 5452 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5453 // of the two input vectors, shuffle them into one input vector so only a 5454 // single pshufb instruction is necessary. If There are more than 2 input 5455 // quads, disable the next transformation since it does not help SSSE3. 5456 bool V1Used = InputQuads[0] || InputQuads[1]; 5457 bool V2Used = InputQuads[2] || InputQuads[3]; 5458 if (Subtarget->hasSSSE3()) { 5459 if (InputQuads.count() == 2 && V1Used && V2Used) { 5460 BestLoQuad = InputQuads.find_first(); 5461 BestHiQuad = InputQuads.find_next(BestLoQuad); 5462 } 5463 if (InputQuads.count() > 2) { 5464 BestLoQuad = -1; 5465 BestHiQuad = -1; 5466 } 5467 } 5468 5469 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5470 // the shuffle mask. If a quad is scored as -1, that means that it contains 5471 // words from all 4 input quadwords. 5472 SDValue NewV; 5473 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5474 int MaskV[] = { 5475 BestLoQuad < 0 ? 0 : BestLoQuad, 5476 BestHiQuad < 0 ? 1 : BestHiQuad 5477 }; 5478 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5479 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5480 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5481 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5482 5483 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5484 // source words for the shuffle, to aid later transformations. 5485 bool AllWordsInNewV = true; 5486 bool InOrder[2] = { true, true }; 5487 for (unsigned i = 0; i != 8; ++i) { 5488 int idx = MaskVals[i]; 5489 if (idx != (int)i) 5490 InOrder[i/4] = false; 5491 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5492 continue; 5493 AllWordsInNewV = false; 5494 break; 5495 } 5496 5497 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5498 if (AllWordsInNewV) { 5499 for (int i = 0; i != 8; ++i) { 5500 int idx = MaskVals[i]; 5501 if (idx < 0) 5502 continue; 5503 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5504 if ((idx != i) && idx < 4) 5505 pshufhw = false; 5506 if ((idx != i) && idx > 3) 5507 pshuflw = false; 5508 } 5509 V1 = NewV; 5510 V2Used = false; 5511 BestLoQuad = 0; 5512 BestHiQuad = 1; 5513 } 5514 5515 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5516 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5517 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5518 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5519 unsigned TargetMask = 0; 5520 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5521 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5522 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5523 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5524 V1 = NewV.getOperand(0); 5525 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5526 } 5527 } 5528 5529 // If we have SSSE3, and all words of the result are from 1 input vector, 5530 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5531 // is present, fall back to case 4. 5532 if (Subtarget->hasSSSE3()) { 5533 SmallVector<SDValue,16> pshufbMask; 5534 5535 // If we have elements from both input vectors, set the high bit of the 5536 // shuffle mask element to zero out elements that come from V2 in the V1 5537 // mask, and elements that come from V1 in the V2 mask, so that the two 5538 // results can be OR'd together. 5539 bool TwoInputs = V1Used && V2Used; 5540 for (unsigned i = 0; i != 8; ++i) { 5541 int EltIdx = MaskVals[i] * 2; 5542 if (TwoInputs && (EltIdx >= 16)) { 5543 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5544 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5545 continue; 5546 } 5547 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5548 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5549 } 5550 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5551 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5552 DAG.getNode(ISD::BUILD_VECTOR, dl, 5553 MVT::v16i8, &pshufbMask[0], 16)); 5554 if (!TwoInputs) 5555 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5556 5557 // Calculate the shuffle mask for the second input, shuffle it, and 5558 // OR it with the first shuffled input. 5559 pshufbMask.clear(); 5560 for (unsigned i = 0; i != 8; ++i) { 5561 int EltIdx = MaskVals[i] * 2; 5562 if (EltIdx < 16) { 5563 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5564 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5565 continue; 5566 } 5567 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5568 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5569 } 5570 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5571 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5572 DAG.getNode(ISD::BUILD_VECTOR, dl, 5573 MVT::v16i8, &pshufbMask[0], 16)); 5574 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5575 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5576 } 5577 5578 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5579 // and update MaskVals with new element order. 5580 std::bitset<8> InOrder; 5581 if (BestLoQuad >= 0) { 5582 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5583 for (int i = 0; i != 4; ++i) { 5584 int idx = MaskVals[i]; 5585 if (idx < 0) { 5586 InOrder.set(i); 5587 } else if ((idx / 4) == BestLoQuad) { 5588 MaskV[i] = idx & 3; 5589 InOrder.set(i); 5590 } 5591 } 5592 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5593 &MaskV[0]); 5594 5595 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5596 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5597 NewV.getOperand(0), 5598 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5599 DAG); 5600 } 5601 5602 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5603 // and update MaskVals with the new element order. 5604 if (BestHiQuad >= 0) { 5605 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5606 for (unsigned i = 4; i != 8; ++i) { 5607 int idx = MaskVals[i]; 5608 if (idx < 0) { 5609 InOrder.set(i); 5610 } else if ((idx / 4) == BestHiQuad) { 5611 MaskV[i] = (idx & 3) + 4; 5612 InOrder.set(i); 5613 } 5614 } 5615 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5616 &MaskV[0]); 5617 5618 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5619 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5620 NewV.getOperand(0), 5621 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5622 DAG); 5623 } 5624 5625 // In case BestHi & BestLo were both -1, which means each quadword has a word 5626 // from each of the four input quadwords, calculate the InOrder bitvector now 5627 // before falling through to the insert/extract cleanup. 5628 if (BestLoQuad == -1 && BestHiQuad == -1) { 5629 NewV = V1; 5630 for (int i = 0; i != 8; ++i) 5631 if (MaskVals[i] < 0 || MaskVals[i] == i) 5632 InOrder.set(i); 5633 } 5634 5635 // The other elements are put in the right place using pextrw and pinsrw. 5636 for (unsigned i = 0; i != 8; ++i) { 5637 if (InOrder[i]) 5638 continue; 5639 int EltIdx = MaskVals[i]; 5640 if (EltIdx < 0) 5641 continue; 5642 SDValue ExtOp = (EltIdx < 8) 5643 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5644 DAG.getIntPtrConstant(EltIdx)) 5645 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5646 DAG.getIntPtrConstant(EltIdx - 8)); 5647 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5648 DAG.getIntPtrConstant(i)); 5649 } 5650 return NewV; 5651} 5652 5653// v16i8 shuffles - Prefer shuffles in the following order: 5654// 1. [ssse3] 1 x pshufb 5655// 2. [ssse3] 2 x pshufb + 1 x por 5656// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5657static 5658SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5659 SelectionDAG &DAG, 5660 const X86TargetLowering &TLI) { 5661 SDValue V1 = SVOp->getOperand(0); 5662 SDValue V2 = SVOp->getOperand(1); 5663 DebugLoc dl = SVOp->getDebugLoc(); 5664 ArrayRef<int> MaskVals = SVOp->getMask(); 5665 5666 // If we have SSSE3, case 1 is generated when all result bytes come from 5667 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5668 // present, fall back to case 3. 5669 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5670 bool V1Only = true; 5671 bool V2Only = true; 5672 for (unsigned i = 0; i < 16; ++i) { 5673 int EltIdx = MaskVals[i]; 5674 if (EltIdx < 0) 5675 continue; 5676 if (EltIdx < 16) 5677 V2Only = false; 5678 else 5679 V1Only = false; 5680 } 5681 5682 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5683 if (TLI.getSubtarget()->hasSSSE3()) { 5684 SmallVector<SDValue,16> pshufbMask; 5685 5686 // If all result elements are from one input vector, then only translate 5687 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5688 // 5689 // Otherwise, we have elements from both input vectors, and must zero out 5690 // elements that come from V2 in the first mask, and V1 in the second mask 5691 // so that we can OR them together. 5692 bool TwoInputs = !(V1Only || V2Only); 5693 for (unsigned i = 0; i != 16; ++i) { 5694 int EltIdx = MaskVals[i]; 5695 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5696 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5697 continue; 5698 } 5699 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5700 } 5701 // If all the elements are from V2, assign it to V1 and return after 5702 // building the first pshufb. 5703 if (V2Only) 5704 V1 = V2; 5705 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5706 DAG.getNode(ISD::BUILD_VECTOR, dl, 5707 MVT::v16i8, &pshufbMask[0], 16)); 5708 if (!TwoInputs) 5709 return V1; 5710 5711 // Calculate the shuffle mask for the second input, shuffle it, and 5712 // OR it with the first shuffled input. 5713 pshufbMask.clear(); 5714 for (unsigned i = 0; i != 16; ++i) { 5715 int EltIdx = MaskVals[i]; 5716 if (EltIdx < 16) { 5717 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5718 continue; 5719 } 5720 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5721 } 5722 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5723 DAG.getNode(ISD::BUILD_VECTOR, dl, 5724 MVT::v16i8, &pshufbMask[0], 16)); 5725 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5726 } 5727 5728 // No SSSE3 - Calculate in place words and then fix all out of place words 5729 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5730 // the 16 different words that comprise the two doublequadword input vectors. 5731 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5732 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5733 SDValue NewV = V2Only ? V2 : V1; 5734 for (int i = 0; i != 8; ++i) { 5735 int Elt0 = MaskVals[i*2]; 5736 int Elt1 = MaskVals[i*2+1]; 5737 5738 // This word of the result is all undef, skip it. 5739 if (Elt0 < 0 && Elt1 < 0) 5740 continue; 5741 5742 // This word of the result is already in the correct place, skip it. 5743 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5744 continue; 5745 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5746 continue; 5747 5748 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5749 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5750 SDValue InsElt; 5751 5752 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5753 // using a single extract together, load it and store it. 5754 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5755 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5756 DAG.getIntPtrConstant(Elt1 / 2)); 5757 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5758 DAG.getIntPtrConstant(i)); 5759 continue; 5760 } 5761 5762 // If Elt1 is defined, extract it from the appropriate source. If the 5763 // source byte is not also odd, shift the extracted word left 8 bits 5764 // otherwise clear the bottom 8 bits if we need to do an or. 5765 if (Elt1 >= 0) { 5766 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5767 DAG.getIntPtrConstant(Elt1 / 2)); 5768 if ((Elt1 & 1) == 0) 5769 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5770 DAG.getConstant(8, 5771 TLI.getShiftAmountTy(InsElt.getValueType()))); 5772 else if (Elt0 >= 0) 5773 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5774 DAG.getConstant(0xFF00, MVT::i16)); 5775 } 5776 // If Elt0 is defined, extract it from the appropriate source. If the 5777 // source byte is not also even, shift the extracted word right 8 bits. If 5778 // Elt1 was also defined, OR the extracted values together before 5779 // inserting them in the result. 5780 if (Elt0 >= 0) { 5781 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5782 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5783 if ((Elt0 & 1) != 0) 5784 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5785 DAG.getConstant(8, 5786 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5787 else if (Elt1 >= 0) 5788 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5789 DAG.getConstant(0x00FF, MVT::i16)); 5790 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5791 : InsElt0; 5792 } 5793 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5794 DAG.getIntPtrConstant(i)); 5795 } 5796 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5797} 5798 5799/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5800/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5801/// done when every pair / quad of shuffle mask elements point to elements in 5802/// the right sequence. e.g. 5803/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5804static 5805SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5806 SelectionDAG &DAG, DebugLoc dl) { 5807 EVT VT = SVOp->getValueType(0); 5808 SDValue V1 = SVOp->getOperand(0); 5809 SDValue V2 = SVOp->getOperand(1); 5810 unsigned NumElems = VT.getVectorNumElements(); 5811 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5812 EVT NewVT; 5813 switch (VT.getSimpleVT().SimpleTy) { 5814 default: llvm_unreachable("Unexpected!"); 5815 case MVT::v4f32: NewVT = MVT::v2f64; break; 5816 case MVT::v4i32: NewVT = MVT::v2i64; break; 5817 case MVT::v8i16: NewVT = MVT::v4i32; break; 5818 case MVT::v16i8: NewVT = MVT::v4i32; break; 5819 } 5820 5821 int Scale = NumElems / NewWidth; 5822 SmallVector<int, 8> MaskVec; 5823 for (unsigned i = 0; i < NumElems; i += Scale) { 5824 int StartIdx = -1; 5825 for (int j = 0; j < Scale; ++j) { 5826 int EltIdx = SVOp->getMaskElt(i+j); 5827 if (EltIdx < 0) 5828 continue; 5829 if (StartIdx == -1) 5830 StartIdx = EltIdx - (EltIdx % Scale); 5831 if (EltIdx != StartIdx + j) 5832 return SDValue(); 5833 } 5834 if (StartIdx == -1) 5835 MaskVec.push_back(-1); 5836 else 5837 MaskVec.push_back(StartIdx / Scale); 5838 } 5839 5840 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5841 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5842 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5843} 5844 5845/// getVZextMovL - Return a zero-extending vector move low node. 5846/// 5847static SDValue getVZextMovL(EVT VT, EVT OpVT, 5848 SDValue SrcOp, SelectionDAG &DAG, 5849 const X86Subtarget *Subtarget, DebugLoc dl) { 5850 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5851 LoadSDNode *LD = NULL; 5852 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5853 LD = dyn_cast<LoadSDNode>(SrcOp); 5854 if (!LD) { 5855 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5856 // instead. 5857 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5858 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5859 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5860 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5861 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5862 // PR2108 5863 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5864 return DAG.getNode(ISD::BITCAST, dl, VT, 5865 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5866 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5867 OpVT, 5868 SrcOp.getOperand(0) 5869 .getOperand(0)))); 5870 } 5871 } 5872 } 5873 5874 return DAG.getNode(ISD::BITCAST, dl, VT, 5875 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5876 DAG.getNode(ISD::BITCAST, dl, 5877 OpVT, SrcOp))); 5878} 5879 5880/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5881/// which could not be matched by any known target speficic shuffle 5882static SDValue 5883LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5884 EVT VT = SVOp->getValueType(0); 5885 5886 unsigned NumElems = VT.getVectorNumElements(); 5887 unsigned NumLaneElems = NumElems / 2; 5888 5889 int MinRange[2][2] = { { static_cast<int>(NumElems), 5890 static_cast<int>(NumElems) }, 5891 { static_cast<int>(NumElems), 5892 static_cast<int>(NumElems) } }; 5893 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } }; 5894 5895 // Collect used ranges for each source in each lane 5896 for (unsigned l = 0; l < 2; ++l) { 5897 unsigned LaneStart = l*NumLaneElems; 5898 for (unsigned i = 0; i != NumLaneElems; ++i) { 5899 int Idx = SVOp->getMaskElt(i+LaneStart); 5900 if (Idx < 0) 5901 continue; 5902 5903 int Input = 0; 5904 if (Idx >= (int)NumElems) { 5905 Idx -= NumElems; 5906 Input = 1; 5907 } 5908 5909 if (Idx > MaxRange[l][Input]) 5910 MaxRange[l][Input] = Idx; 5911 if (Idx < MinRange[l][Input]) 5912 MinRange[l][Input] = Idx; 5913 } 5914 } 5915 5916 // Make sure each range is 128-bits 5917 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } }; 5918 for (unsigned l = 0; l < 2; ++l) { 5919 for (unsigned Input = 0; Input < 2; ++Input) { 5920 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0) 5921 continue; 5922 5923 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems) 5924 ExtractIdx[l][Input] = 0; 5925 else if (MinRange[l][Input] >= (int)NumLaneElems && 5926 MaxRange[l][Input] < (int)NumElems) 5927 ExtractIdx[l][Input] = NumLaneElems; 5928 else 5929 return SDValue(); 5930 } 5931 } 5932 5933 DebugLoc dl = SVOp->getDebugLoc(); 5934 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5935 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2); 5936 5937 SDValue Ops[2][2]; 5938 for (unsigned l = 0; l < 2; ++l) { 5939 for (unsigned Input = 0; Input < 2; ++Input) { 5940 if (ExtractIdx[l][Input] >= 0) 5941 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input), 5942 DAG.getConstant(ExtractIdx[l][Input], MVT::i32), 5943 DAG, dl); 5944 else 5945 Ops[l][Input] = DAG.getUNDEF(NVT); 5946 } 5947 } 5948 5949 // Generate 128-bit shuffles 5950 SmallVector<int, 16> Mask1, Mask2; 5951 for (unsigned i = 0; i != NumLaneElems; ++i) { 5952 int Elt = SVOp->getMaskElt(i); 5953 if (Elt >= (int)NumElems) { 5954 Elt %= NumLaneElems; 5955 Elt += NumLaneElems; 5956 } else if (Elt >= 0) { 5957 Elt %= NumLaneElems; 5958 } 5959 Mask1.push_back(Elt); 5960 } 5961 for (unsigned i = NumLaneElems; i != NumElems; ++i) { 5962 int Elt = SVOp->getMaskElt(i); 5963 if (Elt >= (int)NumElems) { 5964 Elt %= NumLaneElems; 5965 Elt += NumLaneElems; 5966 } else if (Elt >= 0) { 5967 Elt %= NumLaneElems; 5968 } 5969 Mask2.push_back(Elt); 5970 } 5971 5972 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]); 5973 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]); 5974 5975 // Concatenate the result back 5976 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1, 5977 DAG.getConstant(0, MVT::i32), DAG, dl); 5978 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32), 5979 DAG, dl); 5980} 5981 5982/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 5983/// 4 elements, and match them with several different shuffle types. 5984static SDValue 5985LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5986 SDValue V1 = SVOp->getOperand(0); 5987 SDValue V2 = SVOp->getOperand(1); 5988 DebugLoc dl = SVOp->getDebugLoc(); 5989 EVT VT = SVOp->getValueType(0); 5990 5991 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 5992 5993 std::pair<int, int> Locs[4]; 5994 int Mask1[] = { -1, -1, -1, -1 }; 5995 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 5996 5997 unsigned NumHi = 0; 5998 unsigned NumLo = 0; 5999 for (unsigned i = 0; i != 4; ++i) { 6000 int Idx = PermMask[i]; 6001 if (Idx < 0) { 6002 Locs[i] = std::make_pair(-1, -1); 6003 } else { 6004 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6005 if (Idx < 4) { 6006 Locs[i] = std::make_pair(0, NumLo); 6007 Mask1[NumLo] = Idx; 6008 NumLo++; 6009 } else { 6010 Locs[i] = std::make_pair(1, NumHi); 6011 if (2+NumHi < 4) 6012 Mask1[2+NumHi] = Idx; 6013 NumHi++; 6014 } 6015 } 6016 } 6017 6018 if (NumLo <= 2 && NumHi <= 2) { 6019 // If no more than two elements come from either vector. This can be 6020 // implemented with two shuffles. First shuffle gather the elements. 6021 // The second shuffle, which takes the first shuffle as both of its 6022 // vector operands, put the elements into the right order. 6023 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6024 6025 int Mask2[] = { -1, -1, -1, -1 }; 6026 6027 for (unsigned i = 0; i != 4; ++i) 6028 if (Locs[i].first != -1) { 6029 unsigned Idx = (i < 2) ? 0 : 4; 6030 Idx += Locs[i].first * 2 + Locs[i].second; 6031 Mask2[i] = Idx; 6032 } 6033 6034 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6035 } else if (NumLo == 3 || NumHi == 3) { 6036 // Otherwise, we must have three elements from one vector, call it X, and 6037 // one element from the other, call it Y. First, use a shufps to build an 6038 // intermediate vector with the one element from Y and the element from X 6039 // that will be in the same half in the final destination (the indexes don't 6040 // matter). Then, use a shufps to build the final vector, taking the half 6041 // containing the element from Y from the intermediate, and the other half 6042 // from X. 6043 if (NumHi == 3) { 6044 // Normalize it so the 3 elements come from V1. 6045 CommuteVectorShuffleMask(PermMask, 4); 6046 std::swap(V1, V2); 6047 } 6048 6049 // Find the element from V2. 6050 unsigned HiIndex; 6051 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6052 int Val = PermMask[HiIndex]; 6053 if (Val < 0) 6054 continue; 6055 if (Val >= 4) 6056 break; 6057 } 6058 6059 Mask1[0] = PermMask[HiIndex]; 6060 Mask1[1] = -1; 6061 Mask1[2] = PermMask[HiIndex^1]; 6062 Mask1[3] = -1; 6063 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6064 6065 if (HiIndex >= 2) { 6066 Mask1[0] = PermMask[0]; 6067 Mask1[1] = PermMask[1]; 6068 Mask1[2] = HiIndex & 1 ? 6 : 4; 6069 Mask1[3] = HiIndex & 1 ? 4 : 6; 6070 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6071 } else { 6072 Mask1[0] = HiIndex & 1 ? 2 : 0; 6073 Mask1[1] = HiIndex & 1 ? 0 : 2; 6074 Mask1[2] = PermMask[2]; 6075 Mask1[3] = PermMask[3]; 6076 if (Mask1[2] >= 0) 6077 Mask1[2] += 4; 6078 if (Mask1[3] >= 0) 6079 Mask1[3] += 4; 6080 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6081 } 6082 } 6083 6084 // Break it into (shuffle shuffle_hi, shuffle_lo). 6085 int LoMask[] = { -1, -1, -1, -1 }; 6086 int HiMask[] = { -1, -1, -1, -1 }; 6087 6088 int *MaskPtr = LoMask; 6089 unsigned MaskIdx = 0; 6090 unsigned LoIdx = 0; 6091 unsigned HiIdx = 2; 6092 for (unsigned i = 0; i != 4; ++i) { 6093 if (i == 2) { 6094 MaskPtr = HiMask; 6095 MaskIdx = 1; 6096 LoIdx = 0; 6097 HiIdx = 2; 6098 } 6099 int Idx = PermMask[i]; 6100 if (Idx < 0) { 6101 Locs[i] = std::make_pair(-1, -1); 6102 } else if (Idx < 4) { 6103 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6104 MaskPtr[LoIdx] = Idx; 6105 LoIdx++; 6106 } else { 6107 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6108 MaskPtr[HiIdx] = Idx; 6109 HiIdx++; 6110 } 6111 } 6112 6113 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6114 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6115 int MaskOps[] = { -1, -1, -1, -1 }; 6116 for (unsigned i = 0; i != 4; ++i) 6117 if (Locs[i].first != -1) 6118 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6119 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6120} 6121 6122static bool MayFoldVectorLoad(SDValue V) { 6123 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6124 V = V.getOperand(0); 6125 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6126 V = V.getOperand(0); 6127 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6128 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6129 // BUILD_VECTOR (load), undef 6130 V = V.getOperand(0); 6131 if (MayFoldLoad(V)) 6132 return true; 6133 return false; 6134} 6135 6136// FIXME: the version above should always be used. Since there's 6137// a bug where several vector shuffles can't be folded because the 6138// DAG is not updated during lowering and a node claims to have two 6139// uses while it only has one, use this version, and let isel match 6140// another instruction if the load really happens to have more than 6141// one use. Remove this version after this bug get fixed. 6142// rdar://8434668, PR8156 6143static bool RelaxedMayFoldVectorLoad(SDValue V) { 6144 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6145 V = V.getOperand(0); 6146 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6147 V = V.getOperand(0); 6148 if (ISD::isNormalLoad(V.getNode())) 6149 return true; 6150 return false; 6151} 6152 6153/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6154/// a vector extract, and if both can be later optimized into a single load. 6155/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6156/// here because otherwise a target specific shuffle node is going to be 6157/// emitted for this shuffle, and the optimization not done. 6158/// FIXME: This is probably not the best approach, but fix the problem 6159/// until the right path is decided. 6160static 6161bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6162 const TargetLowering &TLI) { 6163 EVT VT = V.getValueType(); 6164 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6165 6166 // Be sure that the vector shuffle is present in a pattern like this: 6167 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6168 if (!V.hasOneUse()) 6169 return false; 6170 6171 SDNode *N = *V.getNode()->use_begin(); 6172 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6173 return false; 6174 6175 SDValue EltNo = N->getOperand(1); 6176 if (!isa<ConstantSDNode>(EltNo)) 6177 return false; 6178 6179 // If the bit convert changed the number of elements, it is unsafe 6180 // to examine the mask. 6181 bool HasShuffleIntoBitcast = false; 6182 if (V.getOpcode() == ISD::BITCAST) { 6183 EVT SrcVT = V.getOperand(0).getValueType(); 6184 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6185 return false; 6186 V = V.getOperand(0); 6187 HasShuffleIntoBitcast = true; 6188 } 6189 6190 // Select the input vector, guarding against out of range extract vector. 6191 unsigned NumElems = VT.getVectorNumElements(); 6192 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6193 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6194 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6195 6196 // If we are accessing the upper part of a YMM register 6197 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of 6198 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point 6199 // because the legalization of N did not happen yet. 6200 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256) 6201 return false; 6202 6203 // Skip one more bit_convert if necessary 6204 if (V.getOpcode() == ISD::BITCAST) 6205 V = V.getOperand(0); 6206 6207 if (!ISD::isNormalLoad(V.getNode())) 6208 return false; 6209 6210 // Is the original load suitable? 6211 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6212 6213 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6214 return false; 6215 6216 if (!HasShuffleIntoBitcast) 6217 return true; 6218 6219 // If there's a bitcast before the shuffle, check if the load type and 6220 // alignment is valid. 6221 unsigned Align = LN0->getAlignment(); 6222 unsigned NewAlign = 6223 TLI.getTargetData()->getABITypeAlignment( 6224 VT.getTypeForEVT(*DAG.getContext())); 6225 6226 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6227 return false; 6228 6229 return true; 6230} 6231 6232static 6233SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6234 EVT VT = Op.getValueType(); 6235 6236 // Canonizalize to v2f64. 6237 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6238 return DAG.getNode(ISD::BITCAST, dl, VT, 6239 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6240 V1, DAG)); 6241} 6242 6243static 6244SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6245 bool HasSSE2) { 6246 SDValue V1 = Op.getOperand(0); 6247 SDValue V2 = Op.getOperand(1); 6248 EVT VT = Op.getValueType(); 6249 6250 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6251 6252 if (HasSSE2 && VT == MVT::v2f64) 6253 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6254 6255 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6256 return DAG.getNode(ISD::BITCAST, dl, VT, 6257 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6258 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6259 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6260} 6261 6262static 6263SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6264 SDValue V1 = Op.getOperand(0); 6265 SDValue V2 = Op.getOperand(1); 6266 EVT VT = Op.getValueType(); 6267 6268 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6269 "unsupported shuffle type"); 6270 6271 if (V2.getOpcode() == ISD::UNDEF) 6272 V2 = V1; 6273 6274 // v4i32 or v4f32 6275 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6276} 6277 6278static 6279SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6280 SDValue V1 = Op.getOperand(0); 6281 SDValue V2 = Op.getOperand(1); 6282 EVT VT = Op.getValueType(); 6283 unsigned NumElems = VT.getVectorNumElements(); 6284 6285 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6286 // operand of these instructions is only memory, so check if there's a 6287 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6288 // same masks. 6289 bool CanFoldLoad = false; 6290 6291 // Trivial case, when V2 comes from a load. 6292 if (MayFoldVectorLoad(V2)) 6293 CanFoldLoad = true; 6294 6295 // When V1 is a load, it can be folded later into a store in isel, example: 6296 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6297 // turns into: 6298 // (MOVLPSmr addr:$src1, VR128:$src2) 6299 // So, recognize this potential and also use MOVLPS or MOVLPD 6300 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6301 CanFoldLoad = true; 6302 6303 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6304 if (CanFoldLoad) { 6305 if (HasSSE2 && NumElems == 2) 6306 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6307 6308 if (NumElems == 4) 6309 // If we don't care about the second element, procede to use movss. 6310 if (SVOp->getMaskElt(1) != -1) 6311 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6312 } 6313 6314 // movl and movlp will both match v2i64, but v2i64 is never matched by 6315 // movl earlier because we make it strict to avoid messing with the movlp load 6316 // folding logic (see the code above getMOVLP call). Match it here then, 6317 // this is horrible, but will stay like this until we move all shuffle 6318 // matching to x86 specific nodes. Note that for the 1st condition all 6319 // types are matched with movsd. 6320 if (HasSSE2) { 6321 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6322 // as to remove this logic from here, as much as possible 6323 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6324 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6325 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6326 } 6327 6328 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6329 6330 // Invert the operand order and use SHUFPS to match it. 6331 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6332 X86::getShuffleSHUFImmediate(SVOp), DAG); 6333} 6334 6335static 6336SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6337 const TargetLowering &TLI, 6338 const X86Subtarget *Subtarget) { 6339 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6340 EVT VT = Op.getValueType(); 6341 DebugLoc dl = Op.getDebugLoc(); 6342 SDValue V1 = Op.getOperand(0); 6343 SDValue V2 = Op.getOperand(1); 6344 6345 if (isZeroShuffle(SVOp)) 6346 return getZeroVector(VT, Subtarget, DAG, dl); 6347 6348 // Handle splat operations 6349 if (SVOp->isSplat()) { 6350 unsigned NumElem = VT.getVectorNumElements(); 6351 int Size = VT.getSizeInBits(); 6352 // Special case, this is the only place now where it's allowed to return 6353 // a vector_shuffle operation without using a target specific node, because 6354 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6355 // this be moved to DAGCombine instead? 6356 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6357 return Op; 6358 6359 // Use vbroadcast whenever the splat comes from a foldable load 6360 SDValue LD = isVectorBroadcast(Op, Subtarget); 6361 if (LD.getNode()) 6362 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6363 6364 // Handle splats by matching through known shuffle masks 6365 if ((Size == 128 && NumElem <= 4) || 6366 (Size == 256 && NumElem < 8)) 6367 return SDValue(); 6368 6369 // All remaning splats are promoted to target supported vector shuffles. 6370 return PromoteSplat(SVOp, DAG); 6371 } 6372 6373 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6374 // do it! 6375 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6376 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6377 if (NewOp.getNode()) 6378 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6379 } else if ((VT == MVT::v4i32 || 6380 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6381 // FIXME: Figure out a cleaner way to do this. 6382 // Try to make use of movq to zero out the top part. 6383 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6384 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6385 if (NewOp.getNode()) { 6386 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6387 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6388 DAG, Subtarget, dl); 6389 } 6390 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6391 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6392 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6393 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6394 DAG, Subtarget, dl); 6395 } 6396 } 6397 return SDValue(); 6398} 6399 6400SDValue 6401X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6402 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6403 SDValue V1 = Op.getOperand(0); 6404 SDValue V2 = Op.getOperand(1); 6405 EVT VT = Op.getValueType(); 6406 DebugLoc dl = Op.getDebugLoc(); 6407 unsigned NumElems = VT.getVectorNumElements(); 6408 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6409 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6410 bool V1IsSplat = false; 6411 bool V2IsSplat = false; 6412 bool HasSSE2 = Subtarget->hasSSE2(); 6413 bool HasAVX = Subtarget->hasAVX(); 6414 bool HasAVX2 = Subtarget->hasAVX2(); 6415 MachineFunction &MF = DAG.getMachineFunction(); 6416 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6417 6418 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6419 6420 if (V1IsUndef && V2IsUndef) 6421 return DAG.getUNDEF(VT); 6422 6423 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6424 6425 // Vector shuffle lowering takes 3 steps: 6426 // 6427 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6428 // narrowing and commutation of operands should be handled. 6429 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6430 // shuffle nodes. 6431 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6432 // so the shuffle can be broken into other shuffles and the legalizer can 6433 // try the lowering again. 6434 // 6435 // The general idea is that no vector_shuffle operation should be left to 6436 // be matched during isel, all of them must be converted to a target specific 6437 // node here. 6438 6439 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6440 // narrowing and commutation of operands should be handled. The actual code 6441 // doesn't include all of those, work in progress... 6442 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6443 if (NewOp.getNode()) 6444 return NewOp; 6445 6446 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6447 // unpckh_undef). Only use pshufd if speed is more important than size. 6448 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2)) 6449 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6450 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2)) 6451 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6452 6453 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() && 6454 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6455 return getMOVDDup(Op, dl, V1, DAG); 6456 6457 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6458 return getMOVHighToLow(Op, dl, DAG); 6459 6460 // Use to match splats 6461 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && 6462 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6463 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6464 6465 if (X86::isPSHUFDMask(SVOp)) { 6466 // The actual implementation will match the mask in the if above and then 6467 // during isel it can match several different instructions, not only pshufd 6468 // as its name says, sad but true, emulate the behavior for now... 6469 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6470 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6471 6472 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6473 6474 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6475 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6476 6477 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6478 TargetMask, DAG); 6479 } 6480 6481 // Check if this can be converted into a logical shift. 6482 bool isLeft = false; 6483 unsigned ShAmt = 0; 6484 SDValue ShVal; 6485 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6486 if (isShift && ShVal.hasOneUse()) { 6487 // If the shifted value has multiple uses, it may be cheaper to use 6488 // v_set0 + movlhps or movhlps, etc. 6489 EVT EltVT = VT.getVectorElementType(); 6490 ShAmt *= EltVT.getSizeInBits(); 6491 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6492 } 6493 6494 if (X86::isMOVLMask(SVOp)) { 6495 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6496 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6497 if (!X86::isMOVLPMask(SVOp)) { 6498 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6499 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6500 6501 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6502 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6503 } 6504 } 6505 6506 // FIXME: fold these into legal mask. 6507 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2)) 6508 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6509 6510 if (X86::isMOVHLPSMask(SVOp)) 6511 return getMOVHighToLow(Op, dl, DAG); 6512 6513 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6514 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6515 6516 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6517 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6518 6519 if (X86::isMOVLPMask(SVOp)) 6520 return getMOVLP(Op, dl, DAG, HasSSE2); 6521 6522 if (ShouldXformToMOVHLPS(SVOp) || 6523 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6524 return CommuteVectorShuffle(SVOp, DAG); 6525 6526 if (isShift) { 6527 // No better options. Use a vshldq / vsrldq. 6528 EVT EltVT = VT.getVectorElementType(); 6529 ShAmt *= EltVT.getSizeInBits(); 6530 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6531 } 6532 6533 bool Commuted = false; 6534 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6535 // 1,1,1,1 -> v8i16 though. 6536 V1IsSplat = isSplatVector(V1.getNode()); 6537 V2IsSplat = isSplatVector(V2.getNode()); 6538 6539 // Canonicalize the splat or undef, if present, to be on the RHS. 6540 if (V1IsSplat && !V2IsSplat) { 6541 Op = CommuteVectorShuffle(SVOp, DAG); 6542 SVOp = cast<ShuffleVectorSDNode>(Op); 6543 V1 = SVOp->getOperand(0); 6544 V2 = SVOp->getOperand(1); 6545 std::swap(V1IsSplat, V2IsSplat); 6546 Commuted = true; 6547 } 6548 6549 ArrayRef<int> M = SVOp->getMask(); 6550 6551 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6552 // Shuffling low element of v1 into undef, just return v1. 6553 if (V2IsUndef) 6554 return V1; 6555 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6556 // the instruction selector will not match, so get a canonical MOVL with 6557 // swapped operands to undo the commute. 6558 return getMOVL(DAG, dl, VT, V2, V1); 6559 } 6560 6561 if (isUNPCKLMask(M, VT, HasAVX2)) 6562 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6563 6564 if (isUNPCKHMask(M, VT, HasAVX2)) 6565 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6566 6567 if (V2IsSplat) { 6568 // Normalize mask so all entries that point to V2 points to its first 6569 // element then try to match unpck{h|l} again. If match, return a 6570 // new vector_shuffle with the corrected mask. 6571 SDValue NewMask = NormalizeMask(SVOp, DAG); 6572 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6573 if (NSVOp != SVOp) { 6574 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) { 6575 return NewMask; 6576 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) { 6577 return NewMask; 6578 } 6579 } 6580 } 6581 6582 if (Commuted) { 6583 // Commute is back and try unpck* again. 6584 // FIXME: this seems wrong. 6585 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6586 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6587 6588 if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) 6589 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG); 6590 6591 if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) 6592 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG); 6593 } 6594 6595 // Normalize the node to match x86 shuffle ops if needed 6596 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6597 return CommuteVectorShuffle(SVOp, DAG); 6598 6599 // The checks below are all present in isShuffleMaskLegal, but they are 6600 // inlined here right now to enable us to directly emit target specific 6601 // nodes, and remove one by one until they don't return Op anymore. 6602 6603 if (isPALIGNRMask(M, VT, Subtarget)) 6604 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6605 getShufflePALIGNRImmediate(SVOp), 6606 DAG); 6607 6608 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6609 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6610 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6611 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6612 } 6613 6614 if (isPSHUFHWMask(M, VT)) 6615 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6616 X86::getShufflePSHUFHWImmediate(SVOp), 6617 DAG); 6618 6619 if (isPSHUFLWMask(M, VT)) 6620 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6621 X86::getShufflePSHUFLWImmediate(SVOp), 6622 DAG); 6623 6624 if (isSHUFPMask(M, VT, HasAVX)) 6625 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6626 X86::getShuffleSHUFImmediate(SVOp), DAG); 6627 6628 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6629 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6630 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6631 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6632 6633 //===--------------------------------------------------------------------===// 6634 // Generate target specific nodes for 128 or 256-bit shuffles only 6635 // supported in the AVX instruction set. 6636 // 6637 6638 // Handle VMOVDDUPY permutations 6639 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6640 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6641 6642 // Handle VPERMILPS/D* permutations 6643 if (isVPERMILPMask(M, VT, HasAVX)) 6644 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6645 X86::getShuffleSHUFImmediate(SVOp), DAG); 6646 6647 // Handle VPERM2F128/VPERM2I128 permutations 6648 if (isVPERM2X128Mask(M, VT, HasAVX)) 6649 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6650 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6651 6652 //===--------------------------------------------------------------------===// 6653 // Since no target specific shuffle was selected for this generic one, 6654 // lower it into other known shuffles. FIXME: this isn't true yet, but 6655 // this is the plan. 6656 // 6657 6658 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6659 if (VT == MVT::v8i16) { 6660 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6661 if (NewOp.getNode()) 6662 return NewOp; 6663 } 6664 6665 if (VT == MVT::v16i8) { 6666 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6667 if (NewOp.getNode()) 6668 return NewOp; 6669 } 6670 6671 // Handle all 128-bit wide vectors with 4 elements, and match them with 6672 // several different shuffle types. 6673 if (NumElems == 4 && VT.getSizeInBits() == 128) 6674 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6675 6676 // Handle general 256-bit shuffles 6677 if (VT.is256BitVector()) 6678 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6679 6680 return SDValue(); 6681} 6682 6683SDValue 6684X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6685 SelectionDAG &DAG) const { 6686 EVT VT = Op.getValueType(); 6687 DebugLoc dl = Op.getDebugLoc(); 6688 6689 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6690 return SDValue(); 6691 6692 if (VT.getSizeInBits() == 8) { 6693 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6694 Op.getOperand(0), Op.getOperand(1)); 6695 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6696 DAG.getValueType(VT)); 6697 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6698 } else if (VT.getSizeInBits() == 16) { 6699 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6700 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6701 if (Idx == 0) 6702 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6703 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6704 DAG.getNode(ISD::BITCAST, dl, 6705 MVT::v4i32, 6706 Op.getOperand(0)), 6707 Op.getOperand(1))); 6708 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6709 Op.getOperand(0), Op.getOperand(1)); 6710 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6711 DAG.getValueType(VT)); 6712 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6713 } else if (VT == MVT::f32) { 6714 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6715 // the result back to FR32 register. It's only worth matching if the 6716 // result has a single use which is a store or a bitcast to i32. And in 6717 // the case of a store, it's not worth it if the index is a constant 0, 6718 // because a MOVSSmr can be used instead, which is smaller and faster. 6719 if (!Op.hasOneUse()) 6720 return SDValue(); 6721 SDNode *User = *Op.getNode()->use_begin(); 6722 if ((User->getOpcode() != ISD::STORE || 6723 (isa<ConstantSDNode>(Op.getOperand(1)) && 6724 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6725 (User->getOpcode() != ISD::BITCAST || 6726 User->getValueType(0) != MVT::i32)) 6727 return SDValue(); 6728 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6729 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6730 Op.getOperand(0)), 6731 Op.getOperand(1)); 6732 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6733 } else if (VT == MVT::i32 || VT == MVT::i64) { 6734 // ExtractPS/pextrq works with constant index. 6735 if (isa<ConstantSDNode>(Op.getOperand(1))) 6736 return Op; 6737 } 6738 return SDValue(); 6739} 6740 6741 6742SDValue 6743X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6744 SelectionDAG &DAG) const { 6745 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6746 return SDValue(); 6747 6748 SDValue Vec = Op.getOperand(0); 6749 EVT VecVT = Vec.getValueType(); 6750 6751 // If this is a 256-bit vector result, first extract the 128-bit vector and 6752 // then extract the element from the 128-bit vector. 6753 if (VecVT.getSizeInBits() == 256) { 6754 DebugLoc dl = Op.getNode()->getDebugLoc(); 6755 unsigned NumElems = VecVT.getVectorNumElements(); 6756 SDValue Idx = Op.getOperand(1); 6757 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6758 6759 // Get the 128-bit vector. 6760 bool Upper = IdxVal >= NumElems/2; 6761 Vec = Extract128BitVector(Vec, 6762 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6763 6764 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6765 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6766 } 6767 6768 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6769 6770 if (Subtarget->hasSSE41()) { 6771 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6772 if (Res.getNode()) 6773 return Res; 6774 } 6775 6776 EVT VT = Op.getValueType(); 6777 DebugLoc dl = Op.getDebugLoc(); 6778 // TODO: handle v16i8. 6779 if (VT.getSizeInBits() == 16) { 6780 SDValue Vec = Op.getOperand(0); 6781 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6782 if (Idx == 0) 6783 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6784 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6785 DAG.getNode(ISD::BITCAST, dl, 6786 MVT::v4i32, Vec), 6787 Op.getOperand(1))); 6788 // Transform it so it match pextrw which produces a 32-bit result. 6789 EVT EltVT = MVT::i32; 6790 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6791 Op.getOperand(0), Op.getOperand(1)); 6792 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6793 DAG.getValueType(VT)); 6794 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6795 } else if (VT.getSizeInBits() == 32) { 6796 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6797 if (Idx == 0) 6798 return Op; 6799 6800 // SHUFPS the element to the lowest double word, then movss. 6801 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6802 EVT VVT = Op.getOperand(0).getValueType(); 6803 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6804 DAG.getUNDEF(VVT), Mask); 6805 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6806 DAG.getIntPtrConstant(0)); 6807 } else if (VT.getSizeInBits() == 64) { 6808 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6809 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6810 // to match extract_elt for f64. 6811 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6812 if (Idx == 0) 6813 return Op; 6814 6815 // UNPCKHPD the element to the lowest double word, then movsd. 6816 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6817 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6818 int Mask[2] = { 1, -1 }; 6819 EVT VVT = Op.getOperand(0).getValueType(); 6820 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6821 DAG.getUNDEF(VVT), Mask); 6822 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6823 DAG.getIntPtrConstant(0)); 6824 } 6825 6826 return SDValue(); 6827} 6828 6829SDValue 6830X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6831 SelectionDAG &DAG) const { 6832 EVT VT = Op.getValueType(); 6833 EVT EltVT = VT.getVectorElementType(); 6834 DebugLoc dl = Op.getDebugLoc(); 6835 6836 SDValue N0 = Op.getOperand(0); 6837 SDValue N1 = Op.getOperand(1); 6838 SDValue N2 = Op.getOperand(2); 6839 6840 if (VT.getSizeInBits() == 256) 6841 return SDValue(); 6842 6843 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6844 isa<ConstantSDNode>(N2)) { 6845 unsigned Opc; 6846 if (VT == MVT::v8i16) 6847 Opc = X86ISD::PINSRW; 6848 else if (VT == MVT::v16i8) 6849 Opc = X86ISD::PINSRB; 6850 else 6851 Opc = X86ISD::PINSRB; 6852 6853 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6854 // argument. 6855 if (N1.getValueType() != MVT::i32) 6856 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6857 if (N2.getValueType() != MVT::i32) 6858 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6859 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6860 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6861 // Bits [7:6] of the constant are the source select. This will always be 6862 // zero here. The DAG Combiner may combine an extract_elt index into these 6863 // bits. For example (insert (extract, 3), 2) could be matched by putting 6864 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6865 // Bits [5:4] of the constant are the destination select. This is the 6866 // value of the incoming immediate. 6867 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6868 // combine either bitwise AND or insert of float 0.0 to set these bits. 6869 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6870 // Create this as a scalar to vector.. 6871 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6872 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6873 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6874 isa<ConstantSDNode>(N2)) { 6875 // PINSR* works with constant index. 6876 return Op; 6877 } 6878 return SDValue(); 6879} 6880 6881SDValue 6882X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6883 EVT VT = Op.getValueType(); 6884 EVT EltVT = VT.getVectorElementType(); 6885 6886 DebugLoc dl = Op.getDebugLoc(); 6887 SDValue N0 = Op.getOperand(0); 6888 SDValue N1 = Op.getOperand(1); 6889 SDValue N2 = Op.getOperand(2); 6890 6891 // If this is a 256-bit vector result, first extract the 128-bit vector, 6892 // insert the element into the extracted half and then place it back. 6893 if (VT.getSizeInBits() == 256) { 6894 if (!isa<ConstantSDNode>(N2)) 6895 return SDValue(); 6896 6897 // Get the desired 128-bit vector half. 6898 unsigned NumElems = VT.getVectorNumElements(); 6899 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6900 bool Upper = IdxVal >= NumElems/2; 6901 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6902 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6903 6904 // Insert the element into the desired half. 6905 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6906 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6907 6908 // Insert the changed part back to the 256-bit vector 6909 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6910 } 6911 6912 if (Subtarget->hasSSE41()) 6913 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6914 6915 if (EltVT == MVT::i8) 6916 return SDValue(); 6917 6918 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6919 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6920 // as its second argument. 6921 if (N1.getValueType() != MVT::i32) 6922 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6923 if (N2.getValueType() != MVT::i32) 6924 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6925 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6926 } 6927 return SDValue(); 6928} 6929 6930SDValue 6931X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6932 LLVMContext *Context = DAG.getContext(); 6933 DebugLoc dl = Op.getDebugLoc(); 6934 EVT OpVT = Op.getValueType(); 6935 6936 // If this is a 256-bit vector result, first insert into a 128-bit 6937 // vector and then insert into the 256-bit vector. 6938 if (OpVT.getSizeInBits() > 128) { 6939 // Insert into a 128-bit vector. 6940 EVT VT128 = EVT::getVectorVT(*Context, 6941 OpVT.getVectorElementType(), 6942 OpVT.getVectorNumElements() / 2); 6943 6944 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6945 6946 // Insert the 128-bit vector. 6947 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6948 DAG.getConstant(0, MVT::i32), 6949 DAG, dl); 6950 } 6951 6952 if (Op.getValueType() == MVT::v1i64 && 6953 Op.getOperand(0).getValueType() == MVT::i64) 6954 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6955 6956 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6957 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6958 "Expected an SSE type!"); 6959 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6960 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6961} 6962 6963// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6964// a simple subregister reference or explicit instructions to grab 6965// upper bits of a vector. 6966SDValue 6967X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6968 if (Subtarget->hasAVX()) { 6969 DebugLoc dl = Op.getNode()->getDebugLoc(); 6970 SDValue Vec = Op.getNode()->getOperand(0); 6971 SDValue Idx = Op.getNode()->getOperand(1); 6972 6973 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6974 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6975 return Extract128BitVector(Vec, Idx, DAG, dl); 6976 } 6977 } 6978 return SDValue(); 6979} 6980 6981// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6982// simple superregister reference or explicit instructions to insert 6983// the upper bits of a vector. 6984SDValue 6985X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6986 if (Subtarget->hasAVX()) { 6987 DebugLoc dl = Op.getNode()->getDebugLoc(); 6988 SDValue Vec = Op.getNode()->getOperand(0); 6989 SDValue SubVec = Op.getNode()->getOperand(1); 6990 SDValue Idx = Op.getNode()->getOperand(2); 6991 6992 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6993 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6994 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6995 } 6996 } 6997 return SDValue(); 6998} 6999 7000// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7001// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7002// one of the above mentioned nodes. It has to be wrapped because otherwise 7003// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7004// be used to form addressing mode. These wrapped nodes will be selected 7005// into MOV32ri. 7006SDValue 7007X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7008 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7009 7010 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7011 // global base reg. 7012 unsigned char OpFlag = 0; 7013 unsigned WrapperKind = X86ISD::Wrapper; 7014 CodeModel::Model M = getTargetMachine().getCodeModel(); 7015 7016 if (Subtarget->isPICStyleRIPRel() && 7017 (M == CodeModel::Small || M == CodeModel::Kernel)) 7018 WrapperKind = X86ISD::WrapperRIP; 7019 else if (Subtarget->isPICStyleGOT()) 7020 OpFlag = X86II::MO_GOTOFF; 7021 else if (Subtarget->isPICStyleStubPIC()) 7022 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7023 7024 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7025 CP->getAlignment(), 7026 CP->getOffset(), OpFlag); 7027 DebugLoc DL = CP->getDebugLoc(); 7028 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7029 // With PIC, the address is actually $g + Offset. 7030 if (OpFlag) { 7031 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7032 DAG.getNode(X86ISD::GlobalBaseReg, 7033 DebugLoc(), getPointerTy()), 7034 Result); 7035 } 7036 7037 return Result; 7038} 7039 7040SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7041 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7042 7043 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7044 // global base reg. 7045 unsigned char OpFlag = 0; 7046 unsigned WrapperKind = X86ISD::Wrapper; 7047 CodeModel::Model M = getTargetMachine().getCodeModel(); 7048 7049 if (Subtarget->isPICStyleRIPRel() && 7050 (M == CodeModel::Small || M == CodeModel::Kernel)) 7051 WrapperKind = X86ISD::WrapperRIP; 7052 else if (Subtarget->isPICStyleGOT()) 7053 OpFlag = X86II::MO_GOTOFF; 7054 else if (Subtarget->isPICStyleStubPIC()) 7055 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7056 7057 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7058 OpFlag); 7059 DebugLoc DL = JT->getDebugLoc(); 7060 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7061 7062 // With PIC, the address is actually $g + Offset. 7063 if (OpFlag) 7064 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7065 DAG.getNode(X86ISD::GlobalBaseReg, 7066 DebugLoc(), getPointerTy()), 7067 Result); 7068 7069 return Result; 7070} 7071 7072SDValue 7073X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7074 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7075 7076 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7077 // global base reg. 7078 unsigned char OpFlag = 0; 7079 unsigned WrapperKind = X86ISD::Wrapper; 7080 CodeModel::Model M = getTargetMachine().getCodeModel(); 7081 7082 if (Subtarget->isPICStyleRIPRel() && 7083 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7084 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7085 OpFlag = X86II::MO_GOTPCREL; 7086 WrapperKind = X86ISD::WrapperRIP; 7087 } else if (Subtarget->isPICStyleGOT()) { 7088 OpFlag = X86II::MO_GOT; 7089 } else if (Subtarget->isPICStyleStubPIC()) { 7090 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7091 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7092 OpFlag = X86II::MO_DARWIN_NONLAZY; 7093 } 7094 7095 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7096 7097 DebugLoc DL = Op.getDebugLoc(); 7098 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7099 7100 7101 // With PIC, the address is actually $g + Offset. 7102 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7103 !Subtarget->is64Bit()) { 7104 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7105 DAG.getNode(X86ISD::GlobalBaseReg, 7106 DebugLoc(), getPointerTy()), 7107 Result); 7108 } 7109 7110 // For symbols that require a load from a stub to get the address, emit the 7111 // load. 7112 if (isGlobalStubReference(OpFlag)) 7113 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7114 MachinePointerInfo::getGOT(), false, false, false, 0); 7115 7116 return Result; 7117} 7118 7119SDValue 7120X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7121 // Create the TargetBlockAddressAddress node. 7122 unsigned char OpFlags = 7123 Subtarget->ClassifyBlockAddressReference(); 7124 CodeModel::Model M = getTargetMachine().getCodeModel(); 7125 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7126 DebugLoc dl = Op.getDebugLoc(); 7127 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7128 /*isTarget=*/true, OpFlags); 7129 7130 if (Subtarget->isPICStyleRIPRel() && 7131 (M == CodeModel::Small || M == CodeModel::Kernel)) 7132 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7133 else 7134 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7135 7136 // With PIC, the address is actually $g + Offset. 7137 if (isGlobalRelativeToPICBase(OpFlags)) { 7138 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7139 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7140 Result); 7141 } 7142 7143 return Result; 7144} 7145 7146SDValue 7147X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7148 int64_t Offset, 7149 SelectionDAG &DAG) const { 7150 // Create the TargetGlobalAddress node, folding in the constant 7151 // offset if it is legal. 7152 unsigned char OpFlags = 7153 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7154 CodeModel::Model M = getTargetMachine().getCodeModel(); 7155 SDValue Result; 7156 if (OpFlags == X86II::MO_NO_FLAG && 7157 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7158 // A direct static reference to a global. 7159 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7160 Offset = 0; 7161 } else { 7162 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7163 } 7164 7165 if (Subtarget->isPICStyleRIPRel() && 7166 (M == CodeModel::Small || M == CodeModel::Kernel)) 7167 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7168 else 7169 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7170 7171 // With PIC, the address is actually $g + Offset. 7172 if (isGlobalRelativeToPICBase(OpFlags)) { 7173 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7174 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7175 Result); 7176 } 7177 7178 // For globals that require a load from a stub to get the address, emit the 7179 // load. 7180 if (isGlobalStubReference(OpFlags)) 7181 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7182 MachinePointerInfo::getGOT(), false, false, false, 0); 7183 7184 // If there was a non-zero offset that we didn't fold, create an explicit 7185 // addition for it. 7186 if (Offset != 0) 7187 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7188 DAG.getConstant(Offset, getPointerTy())); 7189 7190 return Result; 7191} 7192 7193SDValue 7194X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7195 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7196 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7197 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7198} 7199 7200static SDValue 7201GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7202 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7203 unsigned char OperandFlags) { 7204 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7205 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7206 DebugLoc dl = GA->getDebugLoc(); 7207 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7208 GA->getValueType(0), 7209 GA->getOffset(), 7210 OperandFlags); 7211 if (InFlag) { 7212 SDValue Ops[] = { Chain, TGA, *InFlag }; 7213 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7214 } else { 7215 SDValue Ops[] = { Chain, TGA }; 7216 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7217 } 7218 7219 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7220 MFI->setAdjustsStack(true); 7221 7222 SDValue Flag = Chain.getValue(1); 7223 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7224} 7225 7226// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7227static SDValue 7228LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7229 const EVT PtrVT) { 7230 SDValue InFlag; 7231 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7232 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7233 DAG.getNode(X86ISD::GlobalBaseReg, 7234 DebugLoc(), PtrVT), InFlag); 7235 InFlag = Chain.getValue(1); 7236 7237 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7238} 7239 7240// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7241static SDValue 7242LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7243 const EVT PtrVT) { 7244 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7245 X86::RAX, X86II::MO_TLSGD); 7246} 7247 7248// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7249// "local exec" model. 7250static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7251 const EVT PtrVT, TLSModel::Model model, 7252 bool is64Bit) { 7253 DebugLoc dl = GA->getDebugLoc(); 7254 7255 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7256 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7257 is64Bit ? 257 : 256)); 7258 7259 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7260 DAG.getIntPtrConstant(0), 7261 MachinePointerInfo(Ptr), 7262 false, false, false, 0); 7263 7264 unsigned char OperandFlags = 0; 7265 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7266 // initialexec. 7267 unsigned WrapperKind = X86ISD::Wrapper; 7268 if (model == TLSModel::LocalExec) { 7269 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7270 } else if (is64Bit) { 7271 assert(model == TLSModel::InitialExec); 7272 OperandFlags = X86II::MO_GOTTPOFF; 7273 WrapperKind = X86ISD::WrapperRIP; 7274 } else { 7275 assert(model == TLSModel::InitialExec); 7276 OperandFlags = X86II::MO_INDNTPOFF; 7277 } 7278 7279 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7280 // exec) 7281 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7282 GA->getValueType(0), 7283 GA->getOffset(), OperandFlags); 7284 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7285 7286 if (model == TLSModel::InitialExec) 7287 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7288 MachinePointerInfo::getGOT(), false, false, false, 0); 7289 7290 // The address of the thread local variable is the add of the thread 7291 // pointer with the offset of the variable. 7292 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7293} 7294 7295SDValue 7296X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7297 7298 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7299 const GlobalValue *GV = GA->getGlobal(); 7300 7301 if (Subtarget->isTargetELF()) { 7302 // TODO: implement the "local dynamic" model 7303 // TODO: implement the "initial exec"model for pic executables 7304 7305 // If GV is an alias then use the aliasee for determining 7306 // thread-localness. 7307 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7308 GV = GA->resolveAliasedGlobal(false); 7309 7310 TLSModel::Model model 7311 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7312 7313 switch (model) { 7314 case TLSModel::GeneralDynamic: 7315 case TLSModel::LocalDynamic: // not implemented 7316 if (Subtarget->is64Bit()) 7317 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7318 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7319 7320 case TLSModel::InitialExec: 7321 case TLSModel::LocalExec: 7322 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7323 Subtarget->is64Bit()); 7324 } 7325 } else if (Subtarget->isTargetDarwin()) { 7326 // Darwin only has one model of TLS. Lower to that. 7327 unsigned char OpFlag = 0; 7328 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7329 X86ISD::WrapperRIP : X86ISD::Wrapper; 7330 7331 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7332 // global base reg. 7333 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7334 !Subtarget->is64Bit(); 7335 if (PIC32) 7336 OpFlag = X86II::MO_TLVP_PIC_BASE; 7337 else 7338 OpFlag = X86II::MO_TLVP; 7339 DebugLoc DL = Op.getDebugLoc(); 7340 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7341 GA->getValueType(0), 7342 GA->getOffset(), OpFlag); 7343 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7344 7345 // With PIC32, the address is actually $g + Offset. 7346 if (PIC32) 7347 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7348 DAG.getNode(X86ISD::GlobalBaseReg, 7349 DebugLoc(), getPointerTy()), 7350 Offset); 7351 7352 // Lowering the machine isd will make sure everything is in the right 7353 // location. 7354 SDValue Chain = DAG.getEntryNode(); 7355 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7356 SDValue Args[] = { Chain, Offset }; 7357 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7358 7359 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7360 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7361 MFI->setAdjustsStack(true); 7362 7363 // And our return value (tls address) is in the standard call return value 7364 // location. 7365 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7366 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7367 Chain.getValue(1)); 7368 } 7369 7370 llvm_unreachable("TLS not implemented for this target."); 7371} 7372 7373 7374/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7375/// and take a 2 x i32 value to shift plus a shift amount. 7376SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7377 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7378 EVT VT = Op.getValueType(); 7379 unsigned VTBits = VT.getSizeInBits(); 7380 DebugLoc dl = Op.getDebugLoc(); 7381 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7382 SDValue ShOpLo = Op.getOperand(0); 7383 SDValue ShOpHi = Op.getOperand(1); 7384 SDValue ShAmt = Op.getOperand(2); 7385 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7386 DAG.getConstant(VTBits - 1, MVT::i8)) 7387 : DAG.getConstant(0, VT); 7388 7389 SDValue Tmp2, Tmp3; 7390 if (Op.getOpcode() == ISD::SHL_PARTS) { 7391 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7392 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7393 } else { 7394 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7395 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7396 } 7397 7398 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7399 DAG.getConstant(VTBits, MVT::i8)); 7400 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7401 AndNode, DAG.getConstant(0, MVT::i8)); 7402 7403 SDValue Hi, Lo; 7404 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7405 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7406 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7407 7408 if (Op.getOpcode() == ISD::SHL_PARTS) { 7409 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7410 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7411 } else { 7412 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7413 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7414 } 7415 7416 SDValue Ops[2] = { Lo, Hi }; 7417 return DAG.getMergeValues(Ops, 2, dl); 7418} 7419 7420SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7421 SelectionDAG &DAG) const { 7422 EVT SrcVT = Op.getOperand(0).getValueType(); 7423 7424 if (SrcVT.isVector()) 7425 return SDValue(); 7426 7427 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7428 "Unknown SINT_TO_FP to lower!"); 7429 7430 // These are really Legal; return the operand so the caller accepts it as 7431 // Legal. 7432 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7433 return Op; 7434 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7435 Subtarget->is64Bit()) { 7436 return Op; 7437 } 7438 7439 DebugLoc dl = Op.getDebugLoc(); 7440 unsigned Size = SrcVT.getSizeInBits()/8; 7441 MachineFunction &MF = DAG.getMachineFunction(); 7442 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7443 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7444 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7445 StackSlot, 7446 MachinePointerInfo::getFixedStack(SSFI), 7447 false, false, 0); 7448 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7449} 7450 7451SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7452 SDValue StackSlot, 7453 SelectionDAG &DAG) const { 7454 // Build the FILD 7455 DebugLoc DL = Op.getDebugLoc(); 7456 SDVTList Tys; 7457 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7458 if (useSSE) 7459 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7460 else 7461 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7462 7463 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7464 7465 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7466 MachineMemOperand *MMO; 7467 if (FI) { 7468 int SSFI = FI->getIndex(); 7469 MMO = 7470 DAG.getMachineFunction() 7471 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7472 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7473 } else { 7474 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7475 StackSlot = StackSlot.getOperand(1); 7476 } 7477 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7478 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7479 X86ISD::FILD, DL, 7480 Tys, Ops, array_lengthof(Ops), 7481 SrcVT, MMO); 7482 7483 if (useSSE) { 7484 Chain = Result.getValue(1); 7485 SDValue InFlag = Result.getValue(2); 7486 7487 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7488 // shouldn't be necessary except that RFP cannot be live across 7489 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7490 MachineFunction &MF = DAG.getMachineFunction(); 7491 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7492 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7493 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7494 Tys = DAG.getVTList(MVT::Other); 7495 SDValue Ops[] = { 7496 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7497 }; 7498 MachineMemOperand *MMO = 7499 DAG.getMachineFunction() 7500 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7501 MachineMemOperand::MOStore, SSFISize, SSFISize); 7502 7503 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7504 Ops, array_lengthof(Ops), 7505 Op.getValueType(), MMO); 7506 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7507 MachinePointerInfo::getFixedStack(SSFI), 7508 false, false, false, 0); 7509 } 7510 7511 return Result; 7512} 7513 7514// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7515SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7516 SelectionDAG &DAG) const { 7517 // This algorithm is not obvious. Here it is what we're trying to output: 7518 /* 7519 movq %rax, %xmm0 7520 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7521 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7522 #ifdef __SSE3__ 7523 haddpd %xmm0, %xmm0 7524 #else 7525 pshufd $0x4e, %xmm0, %xmm1 7526 addpd %xmm1, %xmm0 7527 #endif 7528 */ 7529 7530 DebugLoc dl = Op.getDebugLoc(); 7531 LLVMContext *Context = DAG.getContext(); 7532 7533 // Build some magic constants. 7534 SmallVector<Constant*,4> CV0; 7535 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7536 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7537 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7538 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7539 Constant *C0 = ConstantVector::get(CV0); 7540 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7541 7542 SmallVector<Constant*,2> CV1; 7543 CV1.push_back( 7544 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7545 CV1.push_back( 7546 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7547 Constant *C1 = ConstantVector::get(CV1); 7548 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7549 7550 // Load the 64-bit value into an XMM register. 7551 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7552 Op.getOperand(0)); 7553 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7554 MachinePointerInfo::getConstantPool(), 7555 false, false, false, 16); 7556 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7557 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7558 CLod0); 7559 7560 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7561 MachinePointerInfo::getConstantPool(), 7562 false, false, false, 16); 7563 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7564 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7565 SDValue Result; 7566 7567 if (Subtarget->hasSSE3()) { 7568 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7569 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7570 } else { 7571 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7572 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7573 S2F, 0x4E, DAG); 7574 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7575 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7576 Sub); 7577 } 7578 7579 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7580 DAG.getIntPtrConstant(0)); 7581} 7582 7583// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7584SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7585 SelectionDAG &DAG) const { 7586 DebugLoc dl = Op.getDebugLoc(); 7587 // FP constant to bias correct the final result. 7588 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7589 MVT::f64); 7590 7591 // Load the 32-bit value into an XMM register. 7592 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7593 Op.getOperand(0)); 7594 7595 // Zero out the upper parts of the register. 7596 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7597 7598 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7599 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7600 DAG.getIntPtrConstant(0)); 7601 7602 // Or the load with the bias. 7603 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7604 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7605 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7606 MVT::v2f64, Load)), 7607 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7608 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7609 MVT::v2f64, Bias))); 7610 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7611 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7612 DAG.getIntPtrConstant(0)); 7613 7614 // Subtract the bias. 7615 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7616 7617 // Handle final rounding. 7618 EVT DestVT = Op.getValueType(); 7619 7620 if (DestVT.bitsLT(MVT::f64)) { 7621 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7622 DAG.getIntPtrConstant(0)); 7623 } else if (DestVT.bitsGT(MVT::f64)) { 7624 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7625 } 7626 7627 // Handle final rounding. 7628 return Sub; 7629} 7630 7631SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7632 SelectionDAG &DAG) const { 7633 SDValue N0 = Op.getOperand(0); 7634 DebugLoc dl = Op.getDebugLoc(); 7635 7636 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7637 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7638 // the optimization here. 7639 if (DAG.SignBitIsZero(N0)) 7640 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7641 7642 EVT SrcVT = N0.getValueType(); 7643 EVT DstVT = Op.getValueType(); 7644 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7645 return LowerUINT_TO_FP_i64(Op, DAG); 7646 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7647 return LowerUINT_TO_FP_i32(Op, DAG); 7648 else if (Subtarget->is64Bit() && 7649 SrcVT == MVT::i64 && DstVT == MVT::f32) 7650 return SDValue(); 7651 7652 // Make a 64-bit buffer, and use it to build an FILD. 7653 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7654 if (SrcVT == MVT::i32) { 7655 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7656 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7657 getPointerTy(), StackSlot, WordOff); 7658 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7659 StackSlot, MachinePointerInfo(), 7660 false, false, 0); 7661 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7662 OffsetSlot, MachinePointerInfo(), 7663 false, false, 0); 7664 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7665 return Fild; 7666 } 7667 7668 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7669 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7670 StackSlot, MachinePointerInfo(), 7671 false, false, 0); 7672 // For i64 source, we need to add the appropriate power of 2 if the input 7673 // was negative. This is the same as the optimization in 7674 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7675 // we must be careful to do the computation in x87 extended precision, not 7676 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7677 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7678 MachineMemOperand *MMO = 7679 DAG.getMachineFunction() 7680 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7681 MachineMemOperand::MOLoad, 8, 8); 7682 7683 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7684 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7685 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7686 MVT::i64, MMO); 7687 7688 APInt FF(32, 0x5F800000ULL); 7689 7690 // Check whether the sign bit is set. 7691 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7692 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7693 ISD::SETLT); 7694 7695 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7696 SDValue FudgePtr = DAG.getConstantPool( 7697 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7698 getPointerTy()); 7699 7700 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7701 SDValue Zero = DAG.getIntPtrConstant(0); 7702 SDValue Four = DAG.getIntPtrConstant(4); 7703 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7704 Zero, Four); 7705 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7706 7707 // Load the value out, extending it from f32 to f80. 7708 // FIXME: Avoid the extend by constructing the right constant pool? 7709 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7710 FudgePtr, MachinePointerInfo::getConstantPool(), 7711 MVT::f32, false, false, 4); 7712 // Extend everything to 80 bits to force it to be done on x87. 7713 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7714 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7715} 7716 7717std::pair<SDValue,SDValue> X86TargetLowering:: 7718FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7719 DebugLoc DL = Op.getDebugLoc(); 7720 7721 EVT DstTy = Op.getValueType(); 7722 7723 if (!IsSigned) { 7724 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7725 DstTy = MVT::i64; 7726 } 7727 7728 assert(DstTy.getSimpleVT() <= MVT::i64 && 7729 DstTy.getSimpleVT() >= MVT::i16 && 7730 "Unknown FP_TO_SINT to lower!"); 7731 7732 // These are really Legal. 7733 if (DstTy == MVT::i32 && 7734 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7735 return std::make_pair(SDValue(), SDValue()); 7736 if (Subtarget->is64Bit() && 7737 DstTy == MVT::i64 && 7738 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7739 return std::make_pair(SDValue(), SDValue()); 7740 7741 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7742 // stack slot. 7743 MachineFunction &MF = DAG.getMachineFunction(); 7744 unsigned MemSize = DstTy.getSizeInBits()/8; 7745 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7746 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7747 7748 7749 7750 unsigned Opc; 7751 switch (DstTy.getSimpleVT().SimpleTy) { 7752 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7753 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7754 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7755 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7756 } 7757 7758 SDValue Chain = DAG.getEntryNode(); 7759 SDValue Value = Op.getOperand(0); 7760 EVT TheVT = Op.getOperand(0).getValueType(); 7761 if (isScalarFPTypeInSSEReg(TheVT)) { 7762 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7763 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7764 MachinePointerInfo::getFixedStack(SSFI), 7765 false, false, 0); 7766 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7767 SDValue Ops[] = { 7768 Chain, StackSlot, DAG.getValueType(TheVT) 7769 }; 7770 7771 MachineMemOperand *MMO = 7772 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7773 MachineMemOperand::MOLoad, MemSize, MemSize); 7774 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7775 DstTy, MMO); 7776 Chain = Value.getValue(1); 7777 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7778 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7779 } 7780 7781 MachineMemOperand *MMO = 7782 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7783 MachineMemOperand::MOStore, MemSize, MemSize); 7784 7785 // Build the FP_TO_INT*_IN_MEM 7786 SDValue Ops[] = { Chain, Value, StackSlot }; 7787 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7788 Ops, 3, DstTy, MMO); 7789 7790 return std::make_pair(FIST, StackSlot); 7791} 7792 7793SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7794 SelectionDAG &DAG) const { 7795 if (Op.getValueType().isVector()) 7796 return SDValue(); 7797 7798 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7799 SDValue FIST = Vals.first, StackSlot = Vals.second; 7800 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7801 if (FIST.getNode() == 0) return Op; 7802 7803 // Load the result. 7804 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7805 FIST, StackSlot, MachinePointerInfo(), 7806 false, false, false, 0); 7807} 7808 7809SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7810 SelectionDAG &DAG) const { 7811 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7812 SDValue FIST = Vals.first, StackSlot = Vals.second; 7813 assert(FIST.getNode() && "Unexpected failure"); 7814 7815 // Load the result. 7816 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7817 FIST, StackSlot, MachinePointerInfo(), 7818 false, false, false, 0); 7819} 7820 7821SDValue X86TargetLowering::LowerFABS(SDValue Op, 7822 SelectionDAG &DAG) const { 7823 LLVMContext *Context = DAG.getContext(); 7824 DebugLoc dl = Op.getDebugLoc(); 7825 EVT VT = Op.getValueType(); 7826 EVT EltVT = VT; 7827 if (VT.isVector()) 7828 EltVT = VT.getVectorElementType(); 7829 Constant *C; 7830 if (EltVT == MVT::f64) { 7831 C = ConstantVector::getSplat(2, 7832 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7833 } else { 7834 C = ConstantVector::getSplat(4, 7835 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7836 } 7837 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7838 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7839 MachinePointerInfo::getConstantPool(), 7840 false, false, false, 16); 7841 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7842} 7843 7844SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7845 LLVMContext *Context = DAG.getContext(); 7846 DebugLoc dl = Op.getDebugLoc(); 7847 EVT VT = Op.getValueType(); 7848 EVT EltVT = VT; 7849 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7850 if (VT.isVector()) { 7851 EltVT = VT.getVectorElementType(); 7852 NumElts = VT.getVectorNumElements(); 7853 } 7854 Constant *C; 7855 if (EltVT == MVT::f64) 7856 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7857 else 7858 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7859 C = ConstantVector::getSplat(NumElts, C); 7860 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7861 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7862 MachinePointerInfo::getConstantPool(), 7863 false, false, false, 16); 7864 if (VT.isVector()) { 7865 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7866 return DAG.getNode(ISD::BITCAST, dl, VT, 7867 DAG.getNode(ISD::XOR, dl, XORVT, 7868 DAG.getNode(ISD::BITCAST, dl, XORVT, 7869 Op.getOperand(0)), 7870 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7871 } else { 7872 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7873 } 7874} 7875 7876SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7877 LLVMContext *Context = DAG.getContext(); 7878 SDValue Op0 = Op.getOperand(0); 7879 SDValue Op1 = Op.getOperand(1); 7880 DebugLoc dl = Op.getDebugLoc(); 7881 EVT VT = Op.getValueType(); 7882 EVT SrcVT = Op1.getValueType(); 7883 7884 // If second operand is smaller, extend it first. 7885 if (SrcVT.bitsLT(VT)) { 7886 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7887 SrcVT = VT; 7888 } 7889 // And if it is bigger, shrink it first. 7890 if (SrcVT.bitsGT(VT)) { 7891 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7892 SrcVT = VT; 7893 } 7894 7895 // At this point the operands and the result should have the same 7896 // type, and that won't be f80 since that is not custom lowered. 7897 7898 // First get the sign bit of second operand. 7899 SmallVector<Constant*,4> CV; 7900 if (SrcVT == MVT::f64) { 7901 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7902 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7903 } else { 7904 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7905 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7906 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7907 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7908 } 7909 Constant *C = ConstantVector::get(CV); 7910 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7911 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7912 MachinePointerInfo::getConstantPool(), 7913 false, false, false, 16); 7914 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7915 7916 // Shift sign bit right or left if the two operands have different types. 7917 if (SrcVT.bitsGT(VT)) { 7918 // Op0 is MVT::f32, Op1 is MVT::f64. 7919 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7920 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7921 DAG.getConstant(32, MVT::i32)); 7922 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7923 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7924 DAG.getIntPtrConstant(0)); 7925 } 7926 7927 // Clear first operand sign bit. 7928 CV.clear(); 7929 if (VT == MVT::f64) { 7930 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7931 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7932 } else { 7933 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7934 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7935 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7936 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7937 } 7938 C = ConstantVector::get(CV); 7939 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7940 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7941 MachinePointerInfo::getConstantPool(), 7942 false, false, false, 16); 7943 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7944 7945 // Or the value with the sign bit. 7946 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7947} 7948 7949SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7950 SDValue N0 = Op.getOperand(0); 7951 DebugLoc dl = Op.getDebugLoc(); 7952 EVT VT = Op.getValueType(); 7953 7954 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 7955 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 7956 DAG.getConstant(1, VT)); 7957 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 7958} 7959 7960/// Emit nodes that will be selected as "test Op0,Op0", or something 7961/// equivalent. 7962SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 7963 SelectionDAG &DAG) const { 7964 DebugLoc dl = Op.getDebugLoc(); 7965 7966 // CF and OF aren't always set the way we want. Determine which 7967 // of these we need. 7968 bool NeedCF = false; 7969 bool NeedOF = false; 7970 switch (X86CC) { 7971 default: break; 7972 case X86::COND_A: case X86::COND_AE: 7973 case X86::COND_B: case X86::COND_BE: 7974 NeedCF = true; 7975 break; 7976 case X86::COND_G: case X86::COND_GE: 7977 case X86::COND_L: case X86::COND_LE: 7978 case X86::COND_O: case X86::COND_NO: 7979 NeedOF = true; 7980 break; 7981 } 7982 7983 // See if we can use the EFLAGS value from the operand instead of 7984 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 7985 // we prove that the arithmetic won't overflow, we can't use OF or CF. 7986 if (Op.getResNo() != 0 || NeedOF || NeedCF) 7987 // Emit a CMP with 0, which is the TEST pattern. 7988 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7989 DAG.getConstant(0, Op.getValueType())); 7990 7991 unsigned Opcode = 0; 7992 unsigned NumOperands = 0; 7993 switch (Op.getNode()->getOpcode()) { 7994 case ISD::ADD: 7995 // Due to an isel shortcoming, be conservative if this add is likely to be 7996 // selected as part of a load-modify-store instruction. When the root node 7997 // in a match is a store, isel doesn't know how to remap non-chain non-flag 7998 // uses of other nodes in the match, such as the ADD in this case. This 7999 // leads to the ADD being left around and reselected, with the result being 8000 // two adds in the output. Alas, even if none our users are stores, that 8001 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8002 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8003 // climbing the DAG back to the root, and it doesn't seem to be worth the 8004 // effort. 8005 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8006 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8007 if (UI->getOpcode() != ISD::CopyToReg && 8008 UI->getOpcode() != ISD::SETCC && 8009 UI->getOpcode() != ISD::STORE) 8010 goto default_case; 8011 8012 if (ConstantSDNode *C = 8013 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8014 // An add of one will be selected as an INC. 8015 if (C->getAPIntValue() == 1) { 8016 Opcode = X86ISD::INC; 8017 NumOperands = 1; 8018 break; 8019 } 8020 8021 // An add of negative one (subtract of one) will be selected as a DEC. 8022 if (C->getAPIntValue().isAllOnesValue()) { 8023 Opcode = X86ISD::DEC; 8024 NumOperands = 1; 8025 break; 8026 } 8027 } 8028 8029 // Otherwise use a regular EFLAGS-setting add. 8030 Opcode = X86ISD::ADD; 8031 NumOperands = 2; 8032 break; 8033 case ISD::AND: { 8034 // If the primary and result isn't used, don't bother using X86ISD::AND, 8035 // because a TEST instruction will be better. 8036 bool NonFlagUse = false; 8037 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8038 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8039 SDNode *User = *UI; 8040 unsigned UOpNo = UI.getOperandNo(); 8041 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8042 // Look pass truncate. 8043 UOpNo = User->use_begin().getOperandNo(); 8044 User = *User->use_begin(); 8045 } 8046 8047 if (User->getOpcode() != ISD::BRCOND && 8048 User->getOpcode() != ISD::SETCC && 8049 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8050 NonFlagUse = true; 8051 break; 8052 } 8053 } 8054 8055 if (!NonFlagUse) 8056 break; 8057 } 8058 // FALL THROUGH 8059 case ISD::SUB: 8060 case ISD::OR: 8061 case ISD::XOR: 8062 // Due to the ISEL shortcoming noted above, be conservative if this op is 8063 // likely to be selected as part of a load-modify-store instruction. 8064 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8065 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8066 if (UI->getOpcode() == ISD::STORE) 8067 goto default_case; 8068 8069 // Otherwise use a regular EFLAGS-setting instruction. 8070 switch (Op.getNode()->getOpcode()) { 8071 default: llvm_unreachable("unexpected operator!"); 8072 case ISD::SUB: Opcode = X86ISD::SUB; break; 8073 case ISD::OR: Opcode = X86ISD::OR; break; 8074 case ISD::XOR: Opcode = X86ISD::XOR; break; 8075 case ISD::AND: Opcode = X86ISD::AND; break; 8076 } 8077 8078 NumOperands = 2; 8079 break; 8080 case X86ISD::ADD: 8081 case X86ISD::SUB: 8082 case X86ISD::INC: 8083 case X86ISD::DEC: 8084 case X86ISD::OR: 8085 case X86ISD::XOR: 8086 case X86ISD::AND: 8087 return SDValue(Op.getNode(), 1); 8088 default: 8089 default_case: 8090 break; 8091 } 8092 8093 if (Opcode == 0) 8094 // Emit a CMP with 0, which is the TEST pattern. 8095 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8096 DAG.getConstant(0, Op.getValueType())); 8097 8098 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8099 SmallVector<SDValue, 4> Ops; 8100 for (unsigned i = 0; i != NumOperands; ++i) 8101 Ops.push_back(Op.getOperand(i)); 8102 8103 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8104 DAG.ReplaceAllUsesWith(Op, New); 8105 return SDValue(New.getNode(), 1); 8106} 8107 8108/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8109/// equivalent. 8110SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8111 SelectionDAG &DAG) const { 8112 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8113 if (C->getAPIntValue() == 0) 8114 return EmitTest(Op0, X86CC, DAG); 8115 8116 DebugLoc dl = Op0.getDebugLoc(); 8117 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8118} 8119 8120/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8121/// if it's possible. 8122SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8123 DebugLoc dl, SelectionDAG &DAG) const { 8124 SDValue Op0 = And.getOperand(0); 8125 SDValue Op1 = And.getOperand(1); 8126 if (Op0.getOpcode() == ISD::TRUNCATE) 8127 Op0 = Op0.getOperand(0); 8128 if (Op1.getOpcode() == ISD::TRUNCATE) 8129 Op1 = Op1.getOperand(0); 8130 8131 SDValue LHS, RHS; 8132 if (Op1.getOpcode() == ISD::SHL) 8133 std::swap(Op0, Op1); 8134 if (Op0.getOpcode() == ISD::SHL) { 8135 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8136 if (And00C->getZExtValue() == 1) { 8137 // If we looked past a truncate, check that it's only truncating away 8138 // known zeros. 8139 unsigned BitWidth = Op0.getValueSizeInBits(); 8140 unsigned AndBitWidth = And.getValueSizeInBits(); 8141 if (BitWidth > AndBitWidth) { 8142 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8143 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8144 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8145 return SDValue(); 8146 } 8147 LHS = Op1; 8148 RHS = Op0.getOperand(1); 8149 } 8150 } else if (Op1.getOpcode() == ISD::Constant) { 8151 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8152 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8153 SDValue AndLHS = Op0; 8154 8155 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8156 LHS = AndLHS.getOperand(0); 8157 RHS = AndLHS.getOperand(1); 8158 } 8159 8160 // Use BT if the immediate can't be encoded in a TEST instruction. 8161 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8162 LHS = AndLHS; 8163 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8164 } 8165 } 8166 8167 if (LHS.getNode()) { 8168 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8169 // instruction. Since the shift amount is in-range-or-undefined, we know 8170 // that doing a bittest on the i32 value is ok. We extend to i32 because 8171 // the encoding for the i16 version is larger than the i32 version. 8172 // Also promote i16 to i32 for performance / code size reason. 8173 if (LHS.getValueType() == MVT::i8 || 8174 LHS.getValueType() == MVT::i16) 8175 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8176 8177 // If the operand types disagree, extend the shift amount to match. Since 8178 // BT ignores high bits (like shifts) we can use anyextend. 8179 if (LHS.getValueType() != RHS.getValueType()) 8180 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8181 8182 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8183 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8184 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8185 DAG.getConstant(Cond, MVT::i8), BT); 8186 } 8187 8188 return SDValue(); 8189} 8190 8191SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8192 8193 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8194 8195 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8196 SDValue Op0 = Op.getOperand(0); 8197 SDValue Op1 = Op.getOperand(1); 8198 DebugLoc dl = Op.getDebugLoc(); 8199 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8200 8201 // Optimize to BT if possible. 8202 // Lower (X & (1 << N)) == 0 to BT(X, N). 8203 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8204 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8205 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8206 Op1.getOpcode() == ISD::Constant && 8207 cast<ConstantSDNode>(Op1)->isNullValue() && 8208 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8209 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8210 if (NewSetCC.getNode()) 8211 return NewSetCC; 8212 } 8213 8214 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8215 // these. 8216 if (Op1.getOpcode() == ISD::Constant && 8217 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8218 cast<ConstantSDNode>(Op1)->isNullValue()) && 8219 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8220 8221 // If the input is a setcc, then reuse the input setcc or use a new one with 8222 // the inverted condition. 8223 if (Op0.getOpcode() == X86ISD::SETCC) { 8224 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8225 bool Invert = (CC == ISD::SETNE) ^ 8226 cast<ConstantSDNode>(Op1)->isNullValue(); 8227 if (!Invert) return Op0; 8228 8229 CCode = X86::GetOppositeBranchCondition(CCode); 8230 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8231 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8232 } 8233 } 8234 8235 bool isFP = Op1.getValueType().isFloatingPoint(); 8236 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8237 if (X86CC == X86::COND_INVALID) 8238 return SDValue(); 8239 8240 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8241 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8242 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8243} 8244 8245// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8246// ones, and then concatenate the result back. 8247static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8248 EVT VT = Op.getValueType(); 8249 8250 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8251 "Unsupported value type for operation"); 8252 8253 int NumElems = VT.getVectorNumElements(); 8254 DebugLoc dl = Op.getDebugLoc(); 8255 SDValue CC = Op.getOperand(2); 8256 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8257 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8258 8259 // Extract the LHS vectors 8260 SDValue LHS = Op.getOperand(0); 8261 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8262 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8263 8264 // Extract the RHS vectors 8265 SDValue RHS = Op.getOperand(1); 8266 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8267 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8268 8269 // Issue the operation on the smaller types and concatenate the result back 8270 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8271 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8272 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8273 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8274 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8275} 8276 8277 8278SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8279 SDValue Cond; 8280 SDValue Op0 = Op.getOperand(0); 8281 SDValue Op1 = Op.getOperand(1); 8282 SDValue CC = Op.getOperand(2); 8283 EVT VT = Op.getValueType(); 8284 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8285 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8286 DebugLoc dl = Op.getDebugLoc(); 8287 8288 if (isFP) { 8289 unsigned SSECC = 8; 8290 EVT EltVT = Op0.getValueType().getVectorElementType(); 8291 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8292 8293 bool Swap = false; 8294 8295 // SSE Condition code mapping: 8296 // 0 - EQ 8297 // 1 - LT 8298 // 2 - LE 8299 // 3 - UNORD 8300 // 4 - NEQ 8301 // 5 - NLT 8302 // 6 - NLE 8303 // 7 - ORD 8304 switch (SetCCOpcode) { 8305 default: break; 8306 case ISD::SETOEQ: 8307 case ISD::SETEQ: SSECC = 0; break; 8308 case ISD::SETOGT: 8309 case ISD::SETGT: Swap = true; // Fallthrough 8310 case ISD::SETLT: 8311 case ISD::SETOLT: SSECC = 1; break; 8312 case ISD::SETOGE: 8313 case ISD::SETGE: Swap = true; // Fallthrough 8314 case ISD::SETLE: 8315 case ISD::SETOLE: SSECC = 2; break; 8316 case ISD::SETUO: SSECC = 3; break; 8317 case ISD::SETUNE: 8318 case ISD::SETNE: SSECC = 4; break; 8319 case ISD::SETULE: Swap = true; 8320 case ISD::SETUGE: SSECC = 5; break; 8321 case ISD::SETULT: Swap = true; 8322 case ISD::SETUGT: SSECC = 6; break; 8323 case ISD::SETO: SSECC = 7; break; 8324 } 8325 if (Swap) 8326 std::swap(Op0, Op1); 8327 8328 // In the two special cases we can't handle, emit two comparisons. 8329 if (SSECC == 8) { 8330 if (SetCCOpcode == ISD::SETUEQ) { 8331 SDValue UNORD, EQ; 8332 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8333 DAG.getConstant(3, MVT::i8)); 8334 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8335 DAG.getConstant(0, MVT::i8)); 8336 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8337 } else if (SetCCOpcode == ISD::SETONE) { 8338 SDValue ORD, NEQ; 8339 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8340 DAG.getConstant(7, MVT::i8)); 8341 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8342 DAG.getConstant(4, MVT::i8)); 8343 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8344 } 8345 llvm_unreachable("Illegal FP comparison"); 8346 } 8347 // Handle all other FP comparisons here. 8348 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8349 DAG.getConstant(SSECC, MVT::i8)); 8350 } 8351 8352 // Break 256-bit integer vector compare into smaller ones. 8353 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8354 return Lower256IntVSETCC(Op, DAG); 8355 8356 // We are handling one of the integer comparisons here. Since SSE only has 8357 // GT and EQ comparisons for integer, swapping operands and multiple 8358 // operations may be required for some comparisons. 8359 unsigned Opc = 0; 8360 bool Swap = false, Invert = false, FlipSigns = false; 8361 8362 switch (SetCCOpcode) { 8363 default: break; 8364 case ISD::SETNE: Invert = true; 8365 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8366 case ISD::SETLT: Swap = true; 8367 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8368 case ISD::SETGE: Swap = true; 8369 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8370 case ISD::SETULT: Swap = true; 8371 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8372 case ISD::SETUGE: Swap = true; 8373 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8374 } 8375 if (Swap) 8376 std::swap(Op0, Op1); 8377 8378 // Check that the operation in question is available (most are plain SSE2, 8379 // but PCMPGTQ and PCMPEQQ have different requirements). 8380 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8381 return SDValue(); 8382 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8383 return SDValue(); 8384 8385 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8386 // bits of the inputs before performing those operations. 8387 if (FlipSigns) { 8388 EVT EltVT = VT.getVectorElementType(); 8389 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8390 EltVT); 8391 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8392 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8393 SignBits.size()); 8394 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8395 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8396 } 8397 8398 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8399 8400 // If the logical-not of the result is required, perform that now. 8401 if (Invert) 8402 Result = DAG.getNOT(dl, Result, VT); 8403 8404 return Result; 8405} 8406 8407// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8408static bool isX86LogicalCmp(SDValue Op) { 8409 unsigned Opc = Op.getNode()->getOpcode(); 8410 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8411 return true; 8412 if (Op.getResNo() == 1 && 8413 (Opc == X86ISD::ADD || 8414 Opc == X86ISD::SUB || 8415 Opc == X86ISD::ADC || 8416 Opc == X86ISD::SBB || 8417 Opc == X86ISD::SMUL || 8418 Opc == X86ISD::UMUL || 8419 Opc == X86ISD::INC || 8420 Opc == X86ISD::DEC || 8421 Opc == X86ISD::OR || 8422 Opc == X86ISD::XOR || 8423 Opc == X86ISD::AND)) 8424 return true; 8425 8426 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8427 return true; 8428 8429 return false; 8430} 8431 8432static bool isZero(SDValue V) { 8433 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8434 return C && C->isNullValue(); 8435} 8436 8437static bool isAllOnes(SDValue V) { 8438 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8439 return C && C->isAllOnesValue(); 8440} 8441 8442SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8443 bool addTest = true; 8444 SDValue Cond = Op.getOperand(0); 8445 SDValue Op1 = Op.getOperand(1); 8446 SDValue Op2 = Op.getOperand(2); 8447 DebugLoc DL = Op.getDebugLoc(); 8448 SDValue CC; 8449 8450 if (Cond.getOpcode() == ISD::SETCC) { 8451 SDValue NewCond = LowerSETCC(Cond, DAG); 8452 if (NewCond.getNode()) 8453 Cond = NewCond; 8454 } 8455 8456 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8457 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8458 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8459 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8460 if (Cond.getOpcode() == X86ISD::SETCC && 8461 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8462 isZero(Cond.getOperand(1).getOperand(1))) { 8463 SDValue Cmp = Cond.getOperand(1); 8464 8465 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8466 8467 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8468 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8469 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8470 8471 SDValue CmpOp0 = Cmp.getOperand(0); 8472 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8473 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8474 8475 SDValue Res = // Res = 0 or -1. 8476 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8477 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8478 8479 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8480 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8481 8482 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8483 if (N2C == 0 || !N2C->isNullValue()) 8484 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8485 return Res; 8486 } 8487 } 8488 8489 // Look past (and (setcc_carry (cmp ...)), 1). 8490 if (Cond.getOpcode() == ISD::AND && 8491 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8492 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8493 if (C && C->getAPIntValue() == 1) 8494 Cond = Cond.getOperand(0); 8495 } 8496 8497 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8498 // setting operand in place of the X86ISD::SETCC. 8499 unsigned CondOpcode = Cond.getOpcode(); 8500 if (CondOpcode == X86ISD::SETCC || 8501 CondOpcode == X86ISD::SETCC_CARRY) { 8502 CC = Cond.getOperand(0); 8503 8504 SDValue Cmp = Cond.getOperand(1); 8505 unsigned Opc = Cmp.getOpcode(); 8506 EVT VT = Op.getValueType(); 8507 8508 bool IllegalFPCMov = false; 8509 if (VT.isFloatingPoint() && !VT.isVector() && 8510 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8511 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8512 8513 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8514 Opc == X86ISD::BT) { // FIXME 8515 Cond = Cmp; 8516 addTest = false; 8517 } 8518 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8519 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8520 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8521 Cond.getOperand(0).getValueType() != MVT::i8)) { 8522 SDValue LHS = Cond.getOperand(0); 8523 SDValue RHS = Cond.getOperand(1); 8524 unsigned X86Opcode; 8525 unsigned X86Cond; 8526 SDVTList VTs; 8527 switch (CondOpcode) { 8528 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8529 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8530 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8531 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8532 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8533 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8534 default: llvm_unreachable("unexpected overflowing operator"); 8535 } 8536 if (CondOpcode == ISD::UMULO) 8537 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8538 MVT::i32); 8539 else 8540 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8541 8542 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8543 8544 if (CondOpcode == ISD::UMULO) 8545 Cond = X86Op.getValue(2); 8546 else 8547 Cond = X86Op.getValue(1); 8548 8549 CC = DAG.getConstant(X86Cond, MVT::i8); 8550 addTest = false; 8551 } 8552 8553 if (addTest) { 8554 // Look pass the truncate. 8555 if (Cond.getOpcode() == ISD::TRUNCATE) 8556 Cond = Cond.getOperand(0); 8557 8558 // We know the result of AND is compared against zero. Try to match 8559 // it to BT. 8560 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8561 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8562 if (NewSetCC.getNode()) { 8563 CC = NewSetCC.getOperand(0); 8564 Cond = NewSetCC.getOperand(1); 8565 addTest = false; 8566 } 8567 } 8568 } 8569 8570 if (addTest) { 8571 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8572 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8573 } 8574 8575 // a < b ? -1 : 0 -> RES = ~setcc_carry 8576 // a < b ? 0 : -1 -> RES = setcc_carry 8577 // a >= b ? -1 : 0 -> RES = setcc_carry 8578 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8579 if (Cond.getOpcode() == X86ISD::CMP) { 8580 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8581 8582 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8583 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8584 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8585 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8586 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8587 return DAG.getNOT(DL, Res, Res.getValueType()); 8588 return Res; 8589 } 8590 } 8591 8592 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8593 // condition is true. 8594 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8595 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8596 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8597} 8598 8599// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8600// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8601// from the AND / OR. 8602static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8603 Opc = Op.getOpcode(); 8604 if (Opc != ISD::OR && Opc != ISD::AND) 8605 return false; 8606 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8607 Op.getOperand(0).hasOneUse() && 8608 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8609 Op.getOperand(1).hasOneUse()); 8610} 8611 8612// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8613// 1 and that the SETCC node has a single use. 8614static bool isXor1OfSetCC(SDValue Op) { 8615 if (Op.getOpcode() != ISD::XOR) 8616 return false; 8617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8618 if (N1C && N1C->getAPIntValue() == 1) { 8619 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8620 Op.getOperand(0).hasOneUse(); 8621 } 8622 return false; 8623} 8624 8625SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8626 bool addTest = true; 8627 SDValue Chain = Op.getOperand(0); 8628 SDValue Cond = Op.getOperand(1); 8629 SDValue Dest = Op.getOperand(2); 8630 DebugLoc dl = Op.getDebugLoc(); 8631 SDValue CC; 8632 bool Inverted = false; 8633 8634 if (Cond.getOpcode() == ISD::SETCC) { 8635 // Check for setcc([su]{add,sub,mul}o == 0). 8636 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8637 isa<ConstantSDNode>(Cond.getOperand(1)) && 8638 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8639 Cond.getOperand(0).getResNo() == 1 && 8640 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8641 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8642 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8643 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8644 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8645 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8646 Inverted = true; 8647 Cond = Cond.getOperand(0); 8648 } else { 8649 SDValue NewCond = LowerSETCC(Cond, DAG); 8650 if (NewCond.getNode()) 8651 Cond = NewCond; 8652 } 8653 } 8654#if 0 8655 // FIXME: LowerXALUO doesn't handle these!! 8656 else if (Cond.getOpcode() == X86ISD::ADD || 8657 Cond.getOpcode() == X86ISD::SUB || 8658 Cond.getOpcode() == X86ISD::SMUL || 8659 Cond.getOpcode() == X86ISD::UMUL) 8660 Cond = LowerXALUO(Cond, DAG); 8661#endif 8662 8663 // Look pass (and (setcc_carry (cmp ...)), 1). 8664 if (Cond.getOpcode() == ISD::AND && 8665 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8667 if (C && C->getAPIntValue() == 1) 8668 Cond = Cond.getOperand(0); 8669 } 8670 8671 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8672 // setting operand in place of the X86ISD::SETCC. 8673 unsigned CondOpcode = Cond.getOpcode(); 8674 if (CondOpcode == X86ISD::SETCC || 8675 CondOpcode == X86ISD::SETCC_CARRY) { 8676 CC = Cond.getOperand(0); 8677 8678 SDValue Cmp = Cond.getOperand(1); 8679 unsigned Opc = Cmp.getOpcode(); 8680 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8681 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8682 Cond = Cmp; 8683 addTest = false; 8684 } else { 8685 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8686 default: break; 8687 case X86::COND_O: 8688 case X86::COND_B: 8689 // These can only come from an arithmetic instruction with overflow, 8690 // e.g. SADDO, UADDO. 8691 Cond = Cond.getNode()->getOperand(1); 8692 addTest = false; 8693 break; 8694 } 8695 } 8696 } 8697 CondOpcode = Cond.getOpcode(); 8698 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8699 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8700 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8701 Cond.getOperand(0).getValueType() != MVT::i8)) { 8702 SDValue LHS = Cond.getOperand(0); 8703 SDValue RHS = Cond.getOperand(1); 8704 unsigned X86Opcode; 8705 unsigned X86Cond; 8706 SDVTList VTs; 8707 switch (CondOpcode) { 8708 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8709 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8710 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8711 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8712 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8713 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8714 default: llvm_unreachable("unexpected overflowing operator"); 8715 } 8716 if (Inverted) 8717 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8718 if (CondOpcode == ISD::UMULO) 8719 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8720 MVT::i32); 8721 else 8722 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8723 8724 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8725 8726 if (CondOpcode == ISD::UMULO) 8727 Cond = X86Op.getValue(2); 8728 else 8729 Cond = X86Op.getValue(1); 8730 8731 CC = DAG.getConstant(X86Cond, MVT::i8); 8732 addTest = false; 8733 } else { 8734 unsigned CondOpc; 8735 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8736 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8737 if (CondOpc == ISD::OR) { 8738 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8739 // two branches instead of an explicit OR instruction with a 8740 // separate test. 8741 if (Cmp == Cond.getOperand(1).getOperand(1) && 8742 isX86LogicalCmp(Cmp)) { 8743 CC = Cond.getOperand(0).getOperand(0); 8744 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8745 Chain, Dest, CC, Cmp); 8746 CC = Cond.getOperand(1).getOperand(0); 8747 Cond = Cmp; 8748 addTest = false; 8749 } 8750 } else { // ISD::AND 8751 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8752 // two branches instead of an explicit AND instruction with a 8753 // separate test. However, we only do this if this block doesn't 8754 // have a fall-through edge, because this requires an explicit 8755 // jmp when the condition is false. 8756 if (Cmp == Cond.getOperand(1).getOperand(1) && 8757 isX86LogicalCmp(Cmp) && 8758 Op.getNode()->hasOneUse()) { 8759 X86::CondCode CCode = 8760 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8761 CCode = X86::GetOppositeBranchCondition(CCode); 8762 CC = DAG.getConstant(CCode, MVT::i8); 8763 SDNode *User = *Op.getNode()->use_begin(); 8764 // Look for an unconditional branch following this conditional branch. 8765 // We need this because we need to reverse the successors in order 8766 // to implement FCMP_OEQ. 8767 if (User->getOpcode() == ISD::BR) { 8768 SDValue FalseBB = User->getOperand(1); 8769 SDNode *NewBR = 8770 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8771 assert(NewBR == User); 8772 (void)NewBR; 8773 Dest = FalseBB; 8774 8775 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8776 Chain, Dest, CC, Cmp); 8777 X86::CondCode CCode = 8778 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8779 CCode = X86::GetOppositeBranchCondition(CCode); 8780 CC = DAG.getConstant(CCode, MVT::i8); 8781 Cond = Cmp; 8782 addTest = false; 8783 } 8784 } 8785 } 8786 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8787 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8788 // It should be transformed during dag combiner except when the condition 8789 // is set by a arithmetics with overflow node. 8790 X86::CondCode CCode = 8791 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8792 CCode = X86::GetOppositeBranchCondition(CCode); 8793 CC = DAG.getConstant(CCode, MVT::i8); 8794 Cond = Cond.getOperand(0).getOperand(1); 8795 addTest = false; 8796 } else if (Cond.getOpcode() == ISD::SETCC && 8797 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8798 // For FCMP_OEQ, we can emit 8799 // two branches instead of an explicit AND instruction with a 8800 // separate test. However, we only do this if this block doesn't 8801 // have a fall-through edge, because this requires an explicit 8802 // jmp when the condition is false. 8803 if (Op.getNode()->hasOneUse()) { 8804 SDNode *User = *Op.getNode()->use_begin(); 8805 // Look for an unconditional branch following this conditional branch. 8806 // We need this because we need to reverse the successors in order 8807 // to implement FCMP_OEQ. 8808 if (User->getOpcode() == ISD::BR) { 8809 SDValue FalseBB = User->getOperand(1); 8810 SDNode *NewBR = 8811 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8812 assert(NewBR == User); 8813 (void)NewBR; 8814 Dest = FalseBB; 8815 8816 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8817 Cond.getOperand(0), Cond.getOperand(1)); 8818 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8819 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8820 Chain, Dest, CC, Cmp); 8821 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8822 Cond = Cmp; 8823 addTest = false; 8824 } 8825 } 8826 } else if (Cond.getOpcode() == ISD::SETCC && 8827 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8828 // For FCMP_UNE, we can emit 8829 // two branches instead of an explicit AND instruction with a 8830 // separate test. However, we only do this if this block doesn't 8831 // have a fall-through edge, because this requires an explicit 8832 // jmp when the condition is false. 8833 if (Op.getNode()->hasOneUse()) { 8834 SDNode *User = *Op.getNode()->use_begin(); 8835 // Look for an unconditional branch following this conditional branch. 8836 // We need this because we need to reverse the successors in order 8837 // to implement FCMP_UNE. 8838 if (User->getOpcode() == ISD::BR) { 8839 SDValue FalseBB = User->getOperand(1); 8840 SDNode *NewBR = 8841 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8842 assert(NewBR == User); 8843 (void)NewBR; 8844 8845 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8846 Cond.getOperand(0), Cond.getOperand(1)); 8847 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8848 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8849 Chain, Dest, CC, Cmp); 8850 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8851 Cond = Cmp; 8852 addTest = false; 8853 Dest = FalseBB; 8854 } 8855 } 8856 } 8857 } 8858 8859 if (addTest) { 8860 // Look pass the truncate. 8861 if (Cond.getOpcode() == ISD::TRUNCATE) 8862 Cond = Cond.getOperand(0); 8863 8864 // We know the result of AND is compared against zero. Try to match 8865 // it to BT. 8866 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8867 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8868 if (NewSetCC.getNode()) { 8869 CC = NewSetCC.getOperand(0); 8870 Cond = NewSetCC.getOperand(1); 8871 addTest = false; 8872 } 8873 } 8874 } 8875 8876 if (addTest) { 8877 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8878 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8879 } 8880 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8881 Chain, Dest, CC, Cond); 8882} 8883 8884 8885// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8886// Calls to _alloca is needed to probe the stack when allocating more than 4k 8887// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8888// that the guard pages used by the OS virtual memory manager are allocated in 8889// correct sequence. 8890SDValue 8891X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8892 SelectionDAG &DAG) const { 8893 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8894 getTargetMachine().Options.EnableSegmentedStacks) && 8895 "This should be used only on Windows targets or when segmented stacks " 8896 "are being used"); 8897 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8898 DebugLoc dl = Op.getDebugLoc(); 8899 8900 // Get the inputs. 8901 SDValue Chain = Op.getOperand(0); 8902 SDValue Size = Op.getOperand(1); 8903 // FIXME: Ensure alignment here 8904 8905 bool Is64Bit = Subtarget->is64Bit(); 8906 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8907 8908 if (getTargetMachine().Options.EnableSegmentedStacks) { 8909 MachineFunction &MF = DAG.getMachineFunction(); 8910 MachineRegisterInfo &MRI = MF.getRegInfo(); 8911 8912 if (Is64Bit) { 8913 // The 64 bit implementation of segmented stacks needs to clobber both r10 8914 // r11. This makes it impossible to use it along with nested parameters. 8915 const Function *F = MF.getFunction(); 8916 8917 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8918 I != E; I++) 8919 if (I->hasNestAttr()) 8920 report_fatal_error("Cannot use segmented stacks with functions that " 8921 "have nested arguments."); 8922 } 8923 8924 const TargetRegisterClass *AddrRegClass = 8925 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8926 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8927 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8928 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8929 DAG.getRegister(Vreg, SPTy)); 8930 SDValue Ops1[2] = { Value, Chain }; 8931 return DAG.getMergeValues(Ops1, 2, dl); 8932 } else { 8933 SDValue Flag; 8934 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8935 8936 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8937 Flag = Chain.getValue(1); 8938 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8939 8940 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8941 Flag = Chain.getValue(1); 8942 8943 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8944 8945 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8946 return DAG.getMergeValues(Ops1, 2, dl); 8947 } 8948} 8949 8950SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8951 MachineFunction &MF = DAG.getMachineFunction(); 8952 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8953 8954 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8955 DebugLoc DL = Op.getDebugLoc(); 8956 8957 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8958 // vastart just stores the address of the VarArgsFrameIndex slot into the 8959 // memory location argument. 8960 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8961 getPointerTy()); 8962 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8963 MachinePointerInfo(SV), false, false, 0); 8964 } 8965 8966 // __va_list_tag: 8967 // gp_offset (0 - 6 * 8) 8968 // fp_offset (48 - 48 + 8 * 16) 8969 // overflow_arg_area (point to parameters coming in memory). 8970 // reg_save_area 8971 SmallVector<SDValue, 8> MemOps; 8972 SDValue FIN = Op.getOperand(1); 8973 // Store gp_offset 8974 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8975 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 8976 MVT::i32), 8977 FIN, MachinePointerInfo(SV), false, false, 0); 8978 MemOps.push_back(Store); 8979 8980 // Store fp_offset 8981 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8982 FIN, DAG.getIntPtrConstant(4)); 8983 Store = DAG.getStore(Op.getOperand(0), DL, 8984 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 8985 MVT::i32), 8986 FIN, MachinePointerInfo(SV, 4), false, false, 0); 8987 MemOps.push_back(Store); 8988 8989 // Store ptr to overflow_arg_area 8990 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8991 FIN, DAG.getIntPtrConstant(4)); 8992 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8993 getPointerTy()); 8994 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 8995 MachinePointerInfo(SV, 8), 8996 false, false, 0); 8997 MemOps.push_back(Store); 8998 8999 // Store ptr to reg_save_area. 9000 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9001 FIN, DAG.getIntPtrConstant(8)); 9002 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9003 getPointerTy()); 9004 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9005 MachinePointerInfo(SV, 16), false, false, 0); 9006 MemOps.push_back(Store); 9007 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9008 &MemOps[0], MemOps.size()); 9009} 9010 9011SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9012 assert(Subtarget->is64Bit() && 9013 "LowerVAARG only handles 64-bit va_arg!"); 9014 assert((Subtarget->isTargetLinux() || 9015 Subtarget->isTargetDarwin()) && 9016 "Unhandled target in LowerVAARG"); 9017 assert(Op.getNode()->getNumOperands() == 4); 9018 SDValue Chain = Op.getOperand(0); 9019 SDValue SrcPtr = Op.getOperand(1); 9020 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9021 unsigned Align = Op.getConstantOperandVal(3); 9022 DebugLoc dl = Op.getDebugLoc(); 9023 9024 EVT ArgVT = Op.getNode()->getValueType(0); 9025 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9026 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9027 uint8_t ArgMode; 9028 9029 // Decide which area this value should be read from. 9030 // TODO: Implement the AMD64 ABI in its entirety. This simple 9031 // selection mechanism works only for the basic types. 9032 if (ArgVT == MVT::f80) { 9033 llvm_unreachable("va_arg for f80 not yet implemented"); 9034 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9035 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9036 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9037 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9038 } else { 9039 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9040 } 9041 9042 if (ArgMode == 2) { 9043 // Sanity Check: Make sure using fp_offset makes sense. 9044 assert(!getTargetMachine().Options.UseSoftFloat && 9045 !(DAG.getMachineFunction() 9046 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9047 Subtarget->hasSSE1()); 9048 } 9049 9050 // Insert VAARG_64 node into the DAG 9051 // VAARG_64 returns two values: Variable Argument Address, Chain 9052 SmallVector<SDValue, 11> InstOps; 9053 InstOps.push_back(Chain); 9054 InstOps.push_back(SrcPtr); 9055 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9056 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9057 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9058 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9059 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9060 VTs, &InstOps[0], InstOps.size(), 9061 MVT::i64, 9062 MachinePointerInfo(SV), 9063 /*Align=*/0, 9064 /*Volatile=*/false, 9065 /*ReadMem=*/true, 9066 /*WriteMem=*/true); 9067 Chain = VAARG.getValue(1); 9068 9069 // Load the next argument and return it 9070 return DAG.getLoad(ArgVT, dl, 9071 Chain, 9072 VAARG, 9073 MachinePointerInfo(), 9074 false, false, false, 0); 9075} 9076 9077SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9078 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9079 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9080 SDValue Chain = Op.getOperand(0); 9081 SDValue DstPtr = Op.getOperand(1); 9082 SDValue SrcPtr = Op.getOperand(2); 9083 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9084 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9085 DebugLoc DL = Op.getDebugLoc(); 9086 9087 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9088 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9089 false, 9090 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9091} 9092 9093// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9094// may or may not be a constant. Takes immediate version of shift as input. 9095static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9096 SDValue SrcOp, SDValue ShAmt, 9097 SelectionDAG &DAG) { 9098 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9099 9100 if (isa<ConstantSDNode>(ShAmt)) { 9101 switch (Opc) { 9102 default: llvm_unreachable("Unknown target vector shift node"); 9103 case X86ISD::VSHLI: 9104 case X86ISD::VSRLI: 9105 case X86ISD::VSRAI: 9106 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9107 } 9108 } 9109 9110 // Change opcode to non-immediate version 9111 switch (Opc) { 9112 default: llvm_unreachable("Unknown target vector shift node"); 9113 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9114 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9115 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9116 } 9117 9118 // Need to build a vector containing shift amount 9119 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9120 SDValue ShOps[4]; 9121 ShOps[0] = ShAmt; 9122 ShOps[1] = DAG.getConstant(0, MVT::i32); 9123 ShOps[2] = DAG.getUNDEF(MVT::i32); 9124 ShOps[3] = DAG.getUNDEF(MVT::i32); 9125 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9126 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9127 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9128} 9129 9130SDValue 9131X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9132 DebugLoc dl = Op.getDebugLoc(); 9133 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9134 switch (IntNo) { 9135 default: return SDValue(); // Don't custom lower most intrinsics. 9136 // Comparison intrinsics. 9137 case Intrinsic::x86_sse_comieq_ss: 9138 case Intrinsic::x86_sse_comilt_ss: 9139 case Intrinsic::x86_sse_comile_ss: 9140 case Intrinsic::x86_sse_comigt_ss: 9141 case Intrinsic::x86_sse_comige_ss: 9142 case Intrinsic::x86_sse_comineq_ss: 9143 case Intrinsic::x86_sse_ucomieq_ss: 9144 case Intrinsic::x86_sse_ucomilt_ss: 9145 case Intrinsic::x86_sse_ucomile_ss: 9146 case Intrinsic::x86_sse_ucomigt_ss: 9147 case Intrinsic::x86_sse_ucomige_ss: 9148 case Intrinsic::x86_sse_ucomineq_ss: 9149 case Intrinsic::x86_sse2_comieq_sd: 9150 case Intrinsic::x86_sse2_comilt_sd: 9151 case Intrinsic::x86_sse2_comile_sd: 9152 case Intrinsic::x86_sse2_comigt_sd: 9153 case Intrinsic::x86_sse2_comige_sd: 9154 case Intrinsic::x86_sse2_comineq_sd: 9155 case Intrinsic::x86_sse2_ucomieq_sd: 9156 case Intrinsic::x86_sse2_ucomilt_sd: 9157 case Intrinsic::x86_sse2_ucomile_sd: 9158 case Intrinsic::x86_sse2_ucomigt_sd: 9159 case Intrinsic::x86_sse2_ucomige_sd: 9160 case Intrinsic::x86_sse2_ucomineq_sd: { 9161 unsigned Opc = 0; 9162 ISD::CondCode CC = ISD::SETCC_INVALID; 9163 switch (IntNo) { 9164 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9165 case Intrinsic::x86_sse_comieq_ss: 9166 case Intrinsic::x86_sse2_comieq_sd: 9167 Opc = X86ISD::COMI; 9168 CC = ISD::SETEQ; 9169 break; 9170 case Intrinsic::x86_sse_comilt_ss: 9171 case Intrinsic::x86_sse2_comilt_sd: 9172 Opc = X86ISD::COMI; 9173 CC = ISD::SETLT; 9174 break; 9175 case Intrinsic::x86_sse_comile_ss: 9176 case Intrinsic::x86_sse2_comile_sd: 9177 Opc = X86ISD::COMI; 9178 CC = ISD::SETLE; 9179 break; 9180 case Intrinsic::x86_sse_comigt_ss: 9181 case Intrinsic::x86_sse2_comigt_sd: 9182 Opc = X86ISD::COMI; 9183 CC = ISD::SETGT; 9184 break; 9185 case Intrinsic::x86_sse_comige_ss: 9186 case Intrinsic::x86_sse2_comige_sd: 9187 Opc = X86ISD::COMI; 9188 CC = ISD::SETGE; 9189 break; 9190 case Intrinsic::x86_sse_comineq_ss: 9191 case Intrinsic::x86_sse2_comineq_sd: 9192 Opc = X86ISD::COMI; 9193 CC = ISD::SETNE; 9194 break; 9195 case Intrinsic::x86_sse_ucomieq_ss: 9196 case Intrinsic::x86_sse2_ucomieq_sd: 9197 Opc = X86ISD::UCOMI; 9198 CC = ISD::SETEQ; 9199 break; 9200 case Intrinsic::x86_sse_ucomilt_ss: 9201 case Intrinsic::x86_sse2_ucomilt_sd: 9202 Opc = X86ISD::UCOMI; 9203 CC = ISD::SETLT; 9204 break; 9205 case Intrinsic::x86_sse_ucomile_ss: 9206 case Intrinsic::x86_sse2_ucomile_sd: 9207 Opc = X86ISD::UCOMI; 9208 CC = ISD::SETLE; 9209 break; 9210 case Intrinsic::x86_sse_ucomigt_ss: 9211 case Intrinsic::x86_sse2_ucomigt_sd: 9212 Opc = X86ISD::UCOMI; 9213 CC = ISD::SETGT; 9214 break; 9215 case Intrinsic::x86_sse_ucomige_ss: 9216 case Intrinsic::x86_sse2_ucomige_sd: 9217 Opc = X86ISD::UCOMI; 9218 CC = ISD::SETGE; 9219 break; 9220 case Intrinsic::x86_sse_ucomineq_ss: 9221 case Intrinsic::x86_sse2_ucomineq_sd: 9222 Opc = X86ISD::UCOMI; 9223 CC = ISD::SETNE; 9224 break; 9225 } 9226 9227 SDValue LHS = Op.getOperand(1); 9228 SDValue RHS = Op.getOperand(2); 9229 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9230 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9231 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9232 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9233 DAG.getConstant(X86CC, MVT::i8), Cond); 9234 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9235 } 9236 // XOP comparison intrinsics 9237 case Intrinsic::x86_xop_vpcomltb: 9238 case Intrinsic::x86_xop_vpcomltw: 9239 case Intrinsic::x86_xop_vpcomltd: 9240 case Intrinsic::x86_xop_vpcomltq: 9241 case Intrinsic::x86_xop_vpcomltub: 9242 case Intrinsic::x86_xop_vpcomltuw: 9243 case Intrinsic::x86_xop_vpcomltud: 9244 case Intrinsic::x86_xop_vpcomltuq: 9245 case Intrinsic::x86_xop_vpcomleb: 9246 case Intrinsic::x86_xop_vpcomlew: 9247 case Intrinsic::x86_xop_vpcomled: 9248 case Intrinsic::x86_xop_vpcomleq: 9249 case Intrinsic::x86_xop_vpcomleub: 9250 case Intrinsic::x86_xop_vpcomleuw: 9251 case Intrinsic::x86_xop_vpcomleud: 9252 case Intrinsic::x86_xop_vpcomleuq: 9253 case Intrinsic::x86_xop_vpcomgtb: 9254 case Intrinsic::x86_xop_vpcomgtw: 9255 case Intrinsic::x86_xop_vpcomgtd: 9256 case Intrinsic::x86_xop_vpcomgtq: 9257 case Intrinsic::x86_xop_vpcomgtub: 9258 case Intrinsic::x86_xop_vpcomgtuw: 9259 case Intrinsic::x86_xop_vpcomgtud: 9260 case Intrinsic::x86_xop_vpcomgtuq: 9261 case Intrinsic::x86_xop_vpcomgeb: 9262 case Intrinsic::x86_xop_vpcomgew: 9263 case Intrinsic::x86_xop_vpcomged: 9264 case Intrinsic::x86_xop_vpcomgeq: 9265 case Intrinsic::x86_xop_vpcomgeub: 9266 case Intrinsic::x86_xop_vpcomgeuw: 9267 case Intrinsic::x86_xop_vpcomgeud: 9268 case Intrinsic::x86_xop_vpcomgeuq: 9269 case Intrinsic::x86_xop_vpcomeqb: 9270 case Intrinsic::x86_xop_vpcomeqw: 9271 case Intrinsic::x86_xop_vpcomeqd: 9272 case Intrinsic::x86_xop_vpcomeqq: 9273 case Intrinsic::x86_xop_vpcomequb: 9274 case Intrinsic::x86_xop_vpcomequw: 9275 case Intrinsic::x86_xop_vpcomequd: 9276 case Intrinsic::x86_xop_vpcomequq: 9277 case Intrinsic::x86_xop_vpcomneb: 9278 case Intrinsic::x86_xop_vpcomnew: 9279 case Intrinsic::x86_xop_vpcomned: 9280 case Intrinsic::x86_xop_vpcomneq: 9281 case Intrinsic::x86_xop_vpcomneub: 9282 case Intrinsic::x86_xop_vpcomneuw: 9283 case Intrinsic::x86_xop_vpcomneud: 9284 case Intrinsic::x86_xop_vpcomneuq: 9285 case Intrinsic::x86_xop_vpcomfalseb: 9286 case Intrinsic::x86_xop_vpcomfalsew: 9287 case Intrinsic::x86_xop_vpcomfalsed: 9288 case Intrinsic::x86_xop_vpcomfalseq: 9289 case Intrinsic::x86_xop_vpcomfalseub: 9290 case Intrinsic::x86_xop_vpcomfalseuw: 9291 case Intrinsic::x86_xop_vpcomfalseud: 9292 case Intrinsic::x86_xop_vpcomfalseuq: 9293 case Intrinsic::x86_xop_vpcomtrueb: 9294 case Intrinsic::x86_xop_vpcomtruew: 9295 case Intrinsic::x86_xop_vpcomtrued: 9296 case Intrinsic::x86_xop_vpcomtrueq: 9297 case Intrinsic::x86_xop_vpcomtrueub: 9298 case Intrinsic::x86_xop_vpcomtrueuw: 9299 case Intrinsic::x86_xop_vpcomtrueud: 9300 case Intrinsic::x86_xop_vpcomtrueuq: { 9301 unsigned CC = 0; 9302 unsigned Opc = 0; 9303 9304 switch (IntNo) { 9305 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9306 case Intrinsic::x86_xop_vpcomltb: 9307 case Intrinsic::x86_xop_vpcomltw: 9308 case Intrinsic::x86_xop_vpcomltd: 9309 case Intrinsic::x86_xop_vpcomltq: 9310 CC = 0; 9311 Opc = X86ISD::VPCOM; 9312 break; 9313 case Intrinsic::x86_xop_vpcomltub: 9314 case Intrinsic::x86_xop_vpcomltuw: 9315 case Intrinsic::x86_xop_vpcomltud: 9316 case Intrinsic::x86_xop_vpcomltuq: 9317 CC = 0; 9318 Opc = X86ISD::VPCOMU; 9319 break; 9320 case Intrinsic::x86_xop_vpcomleb: 9321 case Intrinsic::x86_xop_vpcomlew: 9322 case Intrinsic::x86_xop_vpcomled: 9323 case Intrinsic::x86_xop_vpcomleq: 9324 CC = 1; 9325 Opc = X86ISD::VPCOM; 9326 break; 9327 case Intrinsic::x86_xop_vpcomleub: 9328 case Intrinsic::x86_xop_vpcomleuw: 9329 case Intrinsic::x86_xop_vpcomleud: 9330 case Intrinsic::x86_xop_vpcomleuq: 9331 CC = 1; 9332 Opc = X86ISD::VPCOMU; 9333 break; 9334 case Intrinsic::x86_xop_vpcomgtb: 9335 case Intrinsic::x86_xop_vpcomgtw: 9336 case Intrinsic::x86_xop_vpcomgtd: 9337 case Intrinsic::x86_xop_vpcomgtq: 9338 CC = 2; 9339 Opc = X86ISD::VPCOM; 9340 break; 9341 case Intrinsic::x86_xop_vpcomgtub: 9342 case Intrinsic::x86_xop_vpcomgtuw: 9343 case Intrinsic::x86_xop_vpcomgtud: 9344 case Intrinsic::x86_xop_vpcomgtuq: 9345 CC = 2; 9346 Opc = X86ISD::VPCOMU; 9347 break; 9348 case Intrinsic::x86_xop_vpcomgeb: 9349 case Intrinsic::x86_xop_vpcomgew: 9350 case Intrinsic::x86_xop_vpcomged: 9351 case Intrinsic::x86_xop_vpcomgeq: 9352 CC = 3; 9353 Opc = X86ISD::VPCOM; 9354 break; 9355 case Intrinsic::x86_xop_vpcomgeub: 9356 case Intrinsic::x86_xop_vpcomgeuw: 9357 case Intrinsic::x86_xop_vpcomgeud: 9358 case Intrinsic::x86_xop_vpcomgeuq: 9359 CC = 3; 9360 Opc = X86ISD::VPCOMU; 9361 break; 9362 case Intrinsic::x86_xop_vpcomeqb: 9363 case Intrinsic::x86_xop_vpcomeqw: 9364 case Intrinsic::x86_xop_vpcomeqd: 9365 case Intrinsic::x86_xop_vpcomeqq: 9366 CC = 4; 9367 Opc = X86ISD::VPCOM; 9368 break; 9369 case Intrinsic::x86_xop_vpcomequb: 9370 case Intrinsic::x86_xop_vpcomequw: 9371 case Intrinsic::x86_xop_vpcomequd: 9372 case Intrinsic::x86_xop_vpcomequq: 9373 CC = 4; 9374 Opc = X86ISD::VPCOMU; 9375 break; 9376 case Intrinsic::x86_xop_vpcomneb: 9377 case Intrinsic::x86_xop_vpcomnew: 9378 case Intrinsic::x86_xop_vpcomned: 9379 case Intrinsic::x86_xop_vpcomneq: 9380 CC = 5; 9381 Opc = X86ISD::VPCOM; 9382 break; 9383 case Intrinsic::x86_xop_vpcomneub: 9384 case Intrinsic::x86_xop_vpcomneuw: 9385 case Intrinsic::x86_xop_vpcomneud: 9386 case Intrinsic::x86_xop_vpcomneuq: 9387 CC = 5; 9388 Opc = X86ISD::VPCOMU; 9389 break; 9390 case Intrinsic::x86_xop_vpcomfalseb: 9391 case Intrinsic::x86_xop_vpcomfalsew: 9392 case Intrinsic::x86_xop_vpcomfalsed: 9393 case Intrinsic::x86_xop_vpcomfalseq: 9394 CC = 6; 9395 Opc = X86ISD::VPCOM; 9396 break; 9397 case Intrinsic::x86_xop_vpcomfalseub: 9398 case Intrinsic::x86_xop_vpcomfalseuw: 9399 case Intrinsic::x86_xop_vpcomfalseud: 9400 case Intrinsic::x86_xop_vpcomfalseuq: 9401 CC = 6; 9402 Opc = X86ISD::VPCOMU; 9403 break; 9404 case Intrinsic::x86_xop_vpcomtrueb: 9405 case Intrinsic::x86_xop_vpcomtruew: 9406 case Intrinsic::x86_xop_vpcomtrued: 9407 case Intrinsic::x86_xop_vpcomtrueq: 9408 CC = 7; 9409 Opc = X86ISD::VPCOM; 9410 break; 9411 case Intrinsic::x86_xop_vpcomtrueub: 9412 case Intrinsic::x86_xop_vpcomtrueuw: 9413 case Intrinsic::x86_xop_vpcomtrueud: 9414 case Intrinsic::x86_xop_vpcomtrueuq: 9415 CC = 7; 9416 Opc = X86ISD::VPCOMU; 9417 break; 9418 } 9419 9420 SDValue LHS = Op.getOperand(1); 9421 SDValue RHS = Op.getOperand(2); 9422 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9423 DAG.getConstant(CC, MVT::i8)); 9424 } 9425 9426 // Arithmetic intrinsics. 9427 case Intrinsic::x86_sse2_pmulu_dq: 9428 case Intrinsic::x86_avx2_pmulu_dq: 9429 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9430 Op.getOperand(1), Op.getOperand(2)); 9431 case Intrinsic::x86_sse3_hadd_ps: 9432 case Intrinsic::x86_sse3_hadd_pd: 9433 case Intrinsic::x86_avx_hadd_ps_256: 9434 case Intrinsic::x86_avx_hadd_pd_256: 9435 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9436 Op.getOperand(1), Op.getOperand(2)); 9437 case Intrinsic::x86_sse3_hsub_ps: 9438 case Intrinsic::x86_sse3_hsub_pd: 9439 case Intrinsic::x86_avx_hsub_ps_256: 9440 case Intrinsic::x86_avx_hsub_pd_256: 9441 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9442 Op.getOperand(1), Op.getOperand(2)); 9443 case Intrinsic::x86_ssse3_phadd_w_128: 9444 case Intrinsic::x86_ssse3_phadd_d_128: 9445 case Intrinsic::x86_avx2_phadd_w: 9446 case Intrinsic::x86_avx2_phadd_d: 9447 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9448 Op.getOperand(1), Op.getOperand(2)); 9449 case Intrinsic::x86_ssse3_phsub_w_128: 9450 case Intrinsic::x86_ssse3_phsub_d_128: 9451 case Intrinsic::x86_avx2_phsub_w: 9452 case Intrinsic::x86_avx2_phsub_d: 9453 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9454 Op.getOperand(1), Op.getOperand(2)); 9455 case Intrinsic::x86_avx2_psllv_d: 9456 case Intrinsic::x86_avx2_psllv_q: 9457 case Intrinsic::x86_avx2_psllv_d_256: 9458 case Intrinsic::x86_avx2_psllv_q_256: 9459 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9460 Op.getOperand(1), Op.getOperand(2)); 9461 case Intrinsic::x86_avx2_psrlv_d: 9462 case Intrinsic::x86_avx2_psrlv_q: 9463 case Intrinsic::x86_avx2_psrlv_d_256: 9464 case Intrinsic::x86_avx2_psrlv_q_256: 9465 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9466 Op.getOperand(1), Op.getOperand(2)); 9467 case Intrinsic::x86_avx2_psrav_d: 9468 case Intrinsic::x86_avx2_psrav_d_256: 9469 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9470 Op.getOperand(1), Op.getOperand(2)); 9471 case Intrinsic::x86_ssse3_pshuf_b_128: 9472 case Intrinsic::x86_avx2_pshuf_b: 9473 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9474 Op.getOperand(1), Op.getOperand(2)); 9475 case Intrinsic::x86_ssse3_psign_b_128: 9476 case Intrinsic::x86_ssse3_psign_w_128: 9477 case Intrinsic::x86_ssse3_psign_d_128: 9478 case Intrinsic::x86_avx2_psign_b: 9479 case Intrinsic::x86_avx2_psign_w: 9480 case Intrinsic::x86_avx2_psign_d: 9481 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9482 Op.getOperand(1), Op.getOperand(2)); 9483 case Intrinsic::x86_sse41_insertps: 9484 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9485 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9486 case Intrinsic::x86_avx_vperm2f128_ps_256: 9487 case Intrinsic::x86_avx_vperm2f128_pd_256: 9488 case Intrinsic::x86_avx_vperm2f128_si_256: 9489 case Intrinsic::x86_avx2_vperm2i128: 9490 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9491 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9492 9493 // ptest and testp intrinsics. The intrinsic these come from are designed to 9494 // return an integer value, not just an instruction so lower it to the ptest 9495 // or testp pattern and a setcc for the result. 9496 case Intrinsic::x86_sse41_ptestz: 9497 case Intrinsic::x86_sse41_ptestc: 9498 case Intrinsic::x86_sse41_ptestnzc: 9499 case Intrinsic::x86_avx_ptestz_256: 9500 case Intrinsic::x86_avx_ptestc_256: 9501 case Intrinsic::x86_avx_ptestnzc_256: 9502 case Intrinsic::x86_avx_vtestz_ps: 9503 case Intrinsic::x86_avx_vtestc_ps: 9504 case Intrinsic::x86_avx_vtestnzc_ps: 9505 case Intrinsic::x86_avx_vtestz_pd: 9506 case Intrinsic::x86_avx_vtestc_pd: 9507 case Intrinsic::x86_avx_vtestnzc_pd: 9508 case Intrinsic::x86_avx_vtestz_ps_256: 9509 case Intrinsic::x86_avx_vtestc_ps_256: 9510 case Intrinsic::x86_avx_vtestnzc_ps_256: 9511 case Intrinsic::x86_avx_vtestz_pd_256: 9512 case Intrinsic::x86_avx_vtestc_pd_256: 9513 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9514 bool IsTestPacked = false; 9515 unsigned X86CC = 0; 9516 switch (IntNo) { 9517 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9518 case Intrinsic::x86_avx_vtestz_ps: 9519 case Intrinsic::x86_avx_vtestz_pd: 9520 case Intrinsic::x86_avx_vtestz_ps_256: 9521 case Intrinsic::x86_avx_vtestz_pd_256: 9522 IsTestPacked = true; // Fallthrough 9523 case Intrinsic::x86_sse41_ptestz: 9524 case Intrinsic::x86_avx_ptestz_256: 9525 // ZF = 1 9526 X86CC = X86::COND_E; 9527 break; 9528 case Intrinsic::x86_avx_vtestc_ps: 9529 case Intrinsic::x86_avx_vtestc_pd: 9530 case Intrinsic::x86_avx_vtestc_ps_256: 9531 case Intrinsic::x86_avx_vtestc_pd_256: 9532 IsTestPacked = true; // Fallthrough 9533 case Intrinsic::x86_sse41_ptestc: 9534 case Intrinsic::x86_avx_ptestc_256: 9535 // CF = 1 9536 X86CC = X86::COND_B; 9537 break; 9538 case Intrinsic::x86_avx_vtestnzc_ps: 9539 case Intrinsic::x86_avx_vtestnzc_pd: 9540 case Intrinsic::x86_avx_vtestnzc_ps_256: 9541 case Intrinsic::x86_avx_vtestnzc_pd_256: 9542 IsTestPacked = true; // Fallthrough 9543 case Intrinsic::x86_sse41_ptestnzc: 9544 case Intrinsic::x86_avx_ptestnzc_256: 9545 // ZF and CF = 0 9546 X86CC = X86::COND_A; 9547 break; 9548 } 9549 9550 SDValue LHS = Op.getOperand(1); 9551 SDValue RHS = Op.getOperand(2); 9552 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9553 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9554 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9555 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9556 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9557 } 9558 9559 // SSE/AVX shift intrinsics 9560 case Intrinsic::x86_sse2_psll_w: 9561 case Intrinsic::x86_sse2_psll_d: 9562 case Intrinsic::x86_sse2_psll_q: 9563 case Intrinsic::x86_avx2_psll_w: 9564 case Intrinsic::x86_avx2_psll_d: 9565 case Intrinsic::x86_avx2_psll_q: 9566 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9567 Op.getOperand(1), Op.getOperand(2)); 9568 case Intrinsic::x86_sse2_psrl_w: 9569 case Intrinsic::x86_sse2_psrl_d: 9570 case Intrinsic::x86_sse2_psrl_q: 9571 case Intrinsic::x86_avx2_psrl_w: 9572 case Intrinsic::x86_avx2_psrl_d: 9573 case Intrinsic::x86_avx2_psrl_q: 9574 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9575 Op.getOperand(1), Op.getOperand(2)); 9576 case Intrinsic::x86_sse2_psra_w: 9577 case Intrinsic::x86_sse2_psra_d: 9578 case Intrinsic::x86_avx2_psra_w: 9579 case Intrinsic::x86_avx2_psra_d: 9580 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9581 Op.getOperand(1), Op.getOperand(2)); 9582 case Intrinsic::x86_sse2_pslli_w: 9583 case Intrinsic::x86_sse2_pslli_d: 9584 case Intrinsic::x86_sse2_pslli_q: 9585 case Intrinsic::x86_avx2_pslli_w: 9586 case Intrinsic::x86_avx2_pslli_d: 9587 case Intrinsic::x86_avx2_pslli_q: 9588 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9589 Op.getOperand(1), Op.getOperand(2), DAG); 9590 case Intrinsic::x86_sse2_psrli_w: 9591 case Intrinsic::x86_sse2_psrli_d: 9592 case Intrinsic::x86_sse2_psrli_q: 9593 case Intrinsic::x86_avx2_psrli_w: 9594 case Intrinsic::x86_avx2_psrli_d: 9595 case Intrinsic::x86_avx2_psrli_q: 9596 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9597 Op.getOperand(1), Op.getOperand(2), DAG); 9598 case Intrinsic::x86_sse2_psrai_w: 9599 case Intrinsic::x86_sse2_psrai_d: 9600 case Intrinsic::x86_avx2_psrai_w: 9601 case Intrinsic::x86_avx2_psrai_d: 9602 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9603 Op.getOperand(1), Op.getOperand(2), DAG); 9604 // Fix vector shift instructions where the last operand is a non-immediate 9605 // i32 value. 9606 case Intrinsic::x86_mmx_pslli_w: 9607 case Intrinsic::x86_mmx_pslli_d: 9608 case Intrinsic::x86_mmx_pslli_q: 9609 case Intrinsic::x86_mmx_psrli_w: 9610 case Intrinsic::x86_mmx_psrli_d: 9611 case Intrinsic::x86_mmx_psrli_q: 9612 case Intrinsic::x86_mmx_psrai_w: 9613 case Intrinsic::x86_mmx_psrai_d: { 9614 SDValue ShAmt = Op.getOperand(2); 9615 if (isa<ConstantSDNode>(ShAmt)) 9616 return SDValue(); 9617 9618 unsigned NewIntNo = 0; 9619 switch (IntNo) { 9620 case Intrinsic::x86_mmx_pslli_w: 9621 NewIntNo = Intrinsic::x86_mmx_psll_w; 9622 break; 9623 case Intrinsic::x86_mmx_pslli_d: 9624 NewIntNo = Intrinsic::x86_mmx_psll_d; 9625 break; 9626 case Intrinsic::x86_mmx_pslli_q: 9627 NewIntNo = Intrinsic::x86_mmx_psll_q; 9628 break; 9629 case Intrinsic::x86_mmx_psrli_w: 9630 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9631 break; 9632 case Intrinsic::x86_mmx_psrli_d: 9633 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9634 break; 9635 case Intrinsic::x86_mmx_psrli_q: 9636 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9637 break; 9638 case Intrinsic::x86_mmx_psrai_w: 9639 NewIntNo = Intrinsic::x86_mmx_psra_w; 9640 break; 9641 case Intrinsic::x86_mmx_psrai_d: 9642 NewIntNo = Intrinsic::x86_mmx_psra_d; 9643 break; 9644 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9645 } 9646 9647 // The vector shift intrinsics with scalars uses 32b shift amounts but 9648 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9649 // to be zero. 9650 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9651 DAG.getConstant(0, MVT::i32)); 9652// FIXME this must be lowered to get rid of the invalid type. 9653 9654 EVT VT = Op.getValueType(); 9655 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9656 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9657 DAG.getConstant(NewIntNo, MVT::i32), 9658 Op.getOperand(1), ShAmt); 9659 } 9660 } 9661} 9662 9663SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9664 SelectionDAG &DAG) const { 9665 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9666 MFI->setReturnAddressIsTaken(true); 9667 9668 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9669 DebugLoc dl = Op.getDebugLoc(); 9670 9671 if (Depth > 0) { 9672 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9673 SDValue Offset = 9674 DAG.getConstant(TD->getPointerSize(), 9675 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9676 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9677 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9678 FrameAddr, Offset), 9679 MachinePointerInfo(), false, false, false, 0); 9680 } 9681 9682 // Just load the return address. 9683 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9684 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9685 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9686} 9687 9688SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9689 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9690 MFI->setFrameAddressIsTaken(true); 9691 9692 EVT VT = Op.getValueType(); 9693 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9694 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9695 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9696 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9697 while (Depth--) 9698 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9699 MachinePointerInfo(), 9700 false, false, false, 0); 9701 return FrameAddr; 9702} 9703 9704SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9705 SelectionDAG &DAG) const { 9706 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9707} 9708 9709SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9710 MachineFunction &MF = DAG.getMachineFunction(); 9711 SDValue Chain = Op.getOperand(0); 9712 SDValue Offset = Op.getOperand(1); 9713 SDValue Handler = Op.getOperand(2); 9714 DebugLoc dl = Op.getDebugLoc(); 9715 9716 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9717 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9718 getPointerTy()); 9719 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9720 9721 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9722 DAG.getIntPtrConstant(TD->getPointerSize())); 9723 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9724 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9725 false, false, 0); 9726 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9727 MF.getRegInfo().addLiveOut(StoreAddrReg); 9728 9729 return DAG.getNode(X86ISD::EH_RETURN, dl, 9730 MVT::Other, 9731 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9732} 9733 9734SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9735 SelectionDAG &DAG) const { 9736 return Op.getOperand(0); 9737} 9738 9739SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9740 SelectionDAG &DAG) const { 9741 SDValue Root = Op.getOperand(0); 9742 SDValue Trmp = Op.getOperand(1); // trampoline 9743 SDValue FPtr = Op.getOperand(2); // nested function 9744 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9745 DebugLoc dl = Op.getDebugLoc(); 9746 9747 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9748 9749 if (Subtarget->is64Bit()) { 9750 SDValue OutChains[6]; 9751 9752 // Large code-model. 9753 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9754 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9755 9756 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9757 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9758 9759 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9760 9761 // Load the pointer to the nested function into R11. 9762 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9763 SDValue Addr = Trmp; 9764 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9765 Addr, MachinePointerInfo(TrmpAddr), 9766 false, false, 0); 9767 9768 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9769 DAG.getConstant(2, MVT::i64)); 9770 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9771 MachinePointerInfo(TrmpAddr, 2), 9772 false, false, 2); 9773 9774 // Load the 'nest' parameter value into R10. 9775 // R10 is specified in X86CallingConv.td 9776 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9777 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9778 DAG.getConstant(10, MVT::i64)); 9779 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9780 Addr, MachinePointerInfo(TrmpAddr, 10), 9781 false, false, 0); 9782 9783 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9784 DAG.getConstant(12, MVT::i64)); 9785 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9786 MachinePointerInfo(TrmpAddr, 12), 9787 false, false, 2); 9788 9789 // Jump to the nested function. 9790 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9792 DAG.getConstant(20, MVT::i64)); 9793 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9794 Addr, MachinePointerInfo(TrmpAddr, 20), 9795 false, false, 0); 9796 9797 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9798 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9799 DAG.getConstant(22, MVT::i64)); 9800 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9801 MachinePointerInfo(TrmpAddr, 22), 9802 false, false, 0); 9803 9804 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9805 } else { 9806 const Function *Func = 9807 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9808 CallingConv::ID CC = Func->getCallingConv(); 9809 unsigned NestReg; 9810 9811 switch (CC) { 9812 default: 9813 llvm_unreachable("Unsupported calling convention"); 9814 case CallingConv::C: 9815 case CallingConv::X86_StdCall: { 9816 // Pass 'nest' parameter in ECX. 9817 // Must be kept in sync with X86CallingConv.td 9818 NestReg = X86::ECX; 9819 9820 // Check that ECX wasn't needed by an 'inreg' parameter. 9821 FunctionType *FTy = Func->getFunctionType(); 9822 const AttrListPtr &Attrs = Func->getAttributes(); 9823 9824 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9825 unsigned InRegCount = 0; 9826 unsigned Idx = 1; 9827 9828 for (FunctionType::param_iterator I = FTy->param_begin(), 9829 E = FTy->param_end(); I != E; ++I, ++Idx) 9830 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9831 // FIXME: should only count parameters that are lowered to integers. 9832 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9833 9834 if (InRegCount > 2) { 9835 report_fatal_error("Nest register in use - reduce number of inreg" 9836 " parameters!"); 9837 } 9838 } 9839 break; 9840 } 9841 case CallingConv::X86_FastCall: 9842 case CallingConv::X86_ThisCall: 9843 case CallingConv::Fast: 9844 // Pass 'nest' parameter in EAX. 9845 // Must be kept in sync with X86CallingConv.td 9846 NestReg = X86::EAX; 9847 break; 9848 } 9849 9850 SDValue OutChains[4]; 9851 SDValue Addr, Disp; 9852 9853 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9854 DAG.getConstant(10, MVT::i32)); 9855 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9856 9857 // This is storing the opcode for MOV32ri. 9858 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9859 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9860 OutChains[0] = DAG.getStore(Root, dl, 9861 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9862 Trmp, MachinePointerInfo(TrmpAddr), 9863 false, false, 0); 9864 9865 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9866 DAG.getConstant(1, MVT::i32)); 9867 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9868 MachinePointerInfo(TrmpAddr, 1), 9869 false, false, 1); 9870 9871 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9872 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9873 DAG.getConstant(5, MVT::i32)); 9874 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9875 MachinePointerInfo(TrmpAddr, 5), 9876 false, false, 1); 9877 9878 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9879 DAG.getConstant(6, MVT::i32)); 9880 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9881 MachinePointerInfo(TrmpAddr, 6), 9882 false, false, 1); 9883 9884 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9885 } 9886} 9887 9888SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9889 SelectionDAG &DAG) const { 9890 /* 9891 The rounding mode is in bits 11:10 of FPSR, and has the following 9892 settings: 9893 00 Round to nearest 9894 01 Round to -inf 9895 10 Round to +inf 9896 11 Round to 0 9897 9898 FLT_ROUNDS, on the other hand, expects the following: 9899 -1 Undefined 9900 0 Round to 0 9901 1 Round to nearest 9902 2 Round to +inf 9903 3 Round to -inf 9904 9905 To perform the conversion, we do: 9906 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9907 */ 9908 9909 MachineFunction &MF = DAG.getMachineFunction(); 9910 const TargetMachine &TM = MF.getTarget(); 9911 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9912 unsigned StackAlignment = TFI.getStackAlignment(); 9913 EVT VT = Op.getValueType(); 9914 DebugLoc DL = Op.getDebugLoc(); 9915 9916 // Save FP Control Word to stack slot 9917 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9918 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9919 9920 9921 MachineMemOperand *MMO = 9922 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9923 MachineMemOperand::MOStore, 2, 2); 9924 9925 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9926 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9927 DAG.getVTList(MVT::Other), 9928 Ops, 2, MVT::i16, MMO); 9929 9930 // Load FP Control Word from stack slot 9931 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9932 MachinePointerInfo(), false, false, false, 0); 9933 9934 // Transform as necessary 9935 SDValue CWD1 = 9936 DAG.getNode(ISD::SRL, DL, MVT::i16, 9937 DAG.getNode(ISD::AND, DL, MVT::i16, 9938 CWD, DAG.getConstant(0x800, MVT::i16)), 9939 DAG.getConstant(11, MVT::i8)); 9940 SDValue CWD2 = 9941 DAG.getNode(ISD::SRL, DL, MVT::i16, 9942 DAG.getNode(ISD::AND, DL, MVT::i16, 9943 CWD, DAG.getConstant(0x400, MVT::i16)), 9944 DAG.getConstant(9, MVT::i8)); 9945 9946 SDValue RetVal = 9947 DAG.getNode(ISD::AND, DL, MVT::i16, 9948 DAG.getNode(ISD::ADD, DL, MVT::i16, 9949 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9950 DAG.getConstant(1, MVT::i16)), 9951 DAG.getConstant(3, MVT::i16)); 9952 9953 9954 return DAG.getNode((VT.getSizeInBits() < 16 ? 9955 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9956} 9957 9958SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9959 EVT VT = Op.getValueType(); 9960 EVT OpVT = VT; 9961 unsigned NumBits = VT.getSizeInBits(); 9962 DebugLoc dl = Op.getDebugLoc(); 9963 9964 Op = Op.getOperand(0); 9965 if (VT == MVT::i8) { 9966 // Zero extend to i32 since there is not an i8 bsr. 9967 OpVT = MVT::i32; 9968 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9969 } 9970 9971 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9972 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9973 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9974 9975 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9976 SDValue Ops[] = { 9977 Op, 9978 DAG.getConstant(NumBits+NumBits-1, OpVT), 9979 DAG.getConstant(X86::COND_E, MVT::i8), 9980 Op.getValue(1) 9981 }; 9982 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9983 9984 // Finally xor with NumBits-1. 9985 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9986 9987 if (VT == MVT::i8) 9988 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9989 return Op; 9990} 9991 9992SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 9993 SelectionDAG &DAG) const { 9994 EVT VT = Op.getValueType(); 9995 EVT OpVT = VT; 9996 unsigned NumBits = VT.getSizeInBits(); 9997 DebugLoc dl = Op.getDebugLoc(); 9998 9999 Op = Op.getOperand(0); 10000 if (VT == MVT::i8) { 10001 // Zero extend to i32 since there is not an i8 bsr. 10002 OpVT = MVT::i32; 10003 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10004 } 10005 10006 // Issue a bsr (scan bits in reverse). 10007 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10008 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10009 10010 // And xor with NumBits-1. 10011 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10012 10013 if (VT == MVT::i8) 10014 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10015 return Op; 10016} 10017 10018SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10019 EVT VT = Op.getValueType(); 10020 unsigned NumBits = VT.getSizeInBits(); 10021 DebugLoc dl = Op.getDebugLoc(); 10022 Op = Op.getOperand(0); 10023 10024 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10025 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10026 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10027 10028 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10029 SDValue Ops[] = { 10030 Op, 10031 DAG.getConstant(NumBits, VT), 10032 DAG.getConstant(X86::COND_E, MVT::i8), 10033 Op.getValue(1) 10034 }; 10035 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10036} 10037 10038// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10039// ones, and then concatenate the result back. 10040static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10041 EVT VT = Op.getValueType(); 10042 10043 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10044 "Unsupported value type for operation"); 10045 10046 int NumElems = VT.getVectorNumElements(); 10047 DebugLoc dl = Op.getDebugLoc(); 10048 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10049 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10050 10051 // Extract the LHS vectors 10052 SDValue LHS = Op.getOperand(0); 10053 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10054 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10055 10056 // Extract the RHS vectors 10057 SDValue RHS = Op.getOperand(1); 10058 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 10059 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 10060 10061 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10062 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10063 10064 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10065 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10066 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10067} 10068 10069SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10070 assert(Op.getValueType().getSizeInBits() == 256 && 10071 Op.getValueType().isInteger() && 10072 "Only handle AVX 256-bit vector integer operation"); 10073 return Lower256IntArith(Op, DAG); 10074} 10075 10076SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10077 assert(Op.getValueType().getSizeInBits() == 256 && 10078 Op.getValueType().isInteger() && 10079 "Only handle AVX 256-bit vector integer operation"); 10080 return Lower256IntArith(Op, DAG); 10081} 10082 10083SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10084 EVT VT = Op.getValueType(); 10085 10086 // Decompose 256-bit ops into smaller 128-bit ops. 10087 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10088 return Lower256IntArith(Op, DAG); 10089 10090 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10091 "Only know how to lower V2I64/V4I64 multiply"); 10092 10093 DebugLoc dl = Op.getDebugLoc(); 10094 10095 // Ahi = psrlqi(a, 32); 10096 // Bhi = psrlqi(b, 32); 10097 // 10098 // AloBlo = pmuludq(a, b); 10099 // AloBhi = pmuludq(a, Bhi); 10100 // AhiBlo = pmuludq(Ahi, b); 10101 10102 // AloBhi = psllqi(AloBhi, 32); 10103 // AhiBlo = psllqi(AhiBlo, 32); 10104 // return AloBlo + AloBhi + AhiBlo; 10105 10106 SDValue A = Op.getOperand(0); 10107 SDValue B = Op.getOperand(1); 10108 10109 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10110 10111 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10112 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10113 10114 // Bit cast to 32-bit vectors for MULUDQ 10115 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10116 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10117 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10118 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10119 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10120 10121 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10122 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10123 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10124 10125 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10126 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10127 10128 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10129 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10130} 10131 10132SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10133 10134 EVT VT = Op.getValueType(); 10135 DebugLoc dl = Op.getDebugLoc(); 10136 SDValue R = Op.getOperand(0); 10137 SDValue Amt = Op.getOperand(1); 10138 LLVMContext *Context = DAG.getContext(); 10139 10140 if (!Subtarget->hasSSE2()) 10141 return SDValue(); 10142 10143 // Optimize shl/srl/sra with constant shift amount. 10144 if (isSplatVector(Amt.getNode())) { 10145 SDValue SclrAmt = Amt->getOperand(0); 10146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10147 uint64_t ShiftAmt = C->getZExtValue(); 10148 10149 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10150 (Subtarget->hasAVX2() && 10151 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10152 if (Op.getOpcode() == ISD::SHL) 10153 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10154 DAG.getConstant(ShiftAmt, MVT::i32)); 10155 if (Op.getOpcode() == ISD::SRL) 10156 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10157 DAG.getConstant(ShiftAmt, MVT::i32)); 10158 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10159 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10160 DAG.getConstant(ShiftAmt, MVT::i32)); 10161 } 10162 10163 if (VT == MVT::v16i8) { 10164 if (Op.getOpcode() == ISD::SHL) { 10165 // Make a large shift. 10166 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10167 DAG.getConstant(ShiftAmt, MVT::i32)); 10168 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10169 // Zero out the rightmost bits. 10170 SmallVector<SDValue, 16> V(16, 10171 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10172 MVT::i8)); 10173 return DAG.getNode(ISD::AND, dl, VT, SHL, 10174 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10175 } 10176 if (Op.getOpcode() == ISD::SRL) { 10177 // Make a large shift. 10178 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10179 DAG.getConstant(ShiftAmt, MVT::i32)); 10180 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10181 // Zero out the leftmost bits. 10182 SmallVector<SDValue, 16> V(16, 10183 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10184 MVT::i8)); 10185 return DAG.getNode(ISD::AND, dl, VT, SRL, 10186 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10187 } 10188 if (Op.getOpcode() == ISD::SRA) { 10189 if (ShiftAmt == 7) { 10190 // R s>> 7 === R s< 0 10191 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10192 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10193 } 10194 10195 // R s>> a === ((R u>> a) ^ m) - m 10196 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10197 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10198 MVT::i8)); 10199 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10200 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10201 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10202 return Res; 10203 } 10204 } 10205 10206 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10207 if (Op.getOpcode() == ISD::SHL) { 10208 // Make a large shift. 10209 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10210 DAG.getConstant(ShiftAmt, MVT::i32)); 10211 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10212 // Zero out the rightmost bits. 10213 SmallVector<SDValue, 32> V(32, 10214 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10215 MVT::i8)); 10216 return DAG.getNode(ISD::AND, dl, VT, SHL, 10217 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10218 } 10219 if (Op.getOpcode() == ISD::SRL) { 10220 // Make a large shift. 10221 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10222 DAG.getConstant(ShiftAmt, MVT::i32)); 10223 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10224 // Zero out the leftmost bits. 10225 SmallVector<SDValue, 32> V(32, 10226 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10227 MVT::i8)); 10228 return DAG.getNode(ISD::AND, dl, VT, SRL, 10229 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10230 } 10231 if (Op.getOpcode() == ISD::SRA) { 10232 if (ShiftAmt == 7) { 10233 // R s>> 7 === R s< 0 10234 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10235 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10236 } 10237 10238 // R s>> a === ((R u>> a) ^ m) - m 10239 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10240 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10241 MVT::i8)); 10242 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10243 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10244 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10245 return Res; 10246 } 10247 } 10248 } 10249 } 10250 10251 // Lower SHL with variable shift amount. 10252 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10253 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10254 DAG.getConstant(23, MVT::i32)); 10255 10256 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10257 Constant *C = ConstantVector::getSplat(4, CI); 10258 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10259 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10260 MachinePointerInfo::getConstantPool(), 10261 false, false, false, 16); 10262 10263 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10264 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10265 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10266 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10267 } 10268 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10269 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10270 10271 // a = a << 5; 10272 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10273 DAG.getConstant(5, MVT::i32)); 10274 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10275 10276 // Turn 'a' into a mask suitable for VSELECT 10277 SDValue VSelM = DAG.getConstant(0x80, VT); 10278 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10279 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10280 10281 SDValue CM1 = DAG.getConstant(0x0f, VT); 10282 SDValue CM2 = DAG.getConstant(0x3f, VT); 10283 10284 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10285 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10286 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10287 DAG.getConstant(4, MVT::i32), DAG); 10288 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10289 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10290 10291 // a += a 10292 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10293 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10294 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10295 10296 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10297 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10298 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10299 DAG.getConstant(2, MVT::i32), DAG); 10300 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10301 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10302 10303 // a += a 10304 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10305 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10306 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10307 10308 // return VSELECT(r, r+r, a); 10309 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10310 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10311 return R; 10312 } 10313 10314 // Decompose 256-bit shifts into smaller 128-bit shifts. 10315 if (VT.getSizeInBits() == 256) { 10316 unsigned NumElems = VT.getVectorNumElements(); 10317 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10318 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10319 10320 // Extract the two vectors 10321 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10322 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10323 DAG, dl); 10324 10325 // Recreate the shift amount vectors 10326 SDValue Amt1, Amt2; 10327 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10328 // Constant shift amount 10329 SmallVector<SDValue, 4> Amt1Csts; 10330 SmallVector<SDValue, 4> Amt2Csts; 10331 for (unsigned i = 0; i != NumElems/2; ++i) 10332 Amt1Csts.push_back(Amt->getOperand(i)); 10333 for (unsigned i = NumElems/2; i != NumElems; ++i) 10334 Amt2Csts.push_back(Amt->getOperand(i)); 10335 10336 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10337 &Amt1Csts[0], NumElems/2); 10338 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10339 &Amt2Csts[0], NumElems/2); 10340 } else { 10341 // Variable shift amount 10342 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10343 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10344 DAG, dl); 10345 } 10346 10347 // Issue new vector shifts for the smaller types 10348 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10349 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10350 10351 // Concatenate the result back 10352 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10353 } 10354 10355 return SDValue(); 10356} 10357 10358SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10359 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10360 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10361 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10362 // has only one use. 10363 SDNode *N = Op.getNode(); 10364 SDValue LHS = N->getOperand(0); 10365 SDValue RHS = N->getOperand(1); 10366 unsigned BaseOp = 0; 10367 unsigned Cond = 0; 10368 DebugLoc DL = Op.getDebugLoc(); 10369 switch (Op.getOpcode()) { 10370 default: llvm_unreachable("Unknown ovf instruction!"); 10371 case ISD::SADDO: 10372 // A subtract of one will be selected as a INC. Note that INC doesn't 10373 // set CF, so we can't do this for UADDO. 10374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10375 if (C->isOne()) { 10376 BaseOp = X86ISD::INC; 10377 Cond = X86::COND_O; 10378 break; 10379 } 10380 BaseOp = X86ISD::ADD; 10381 Cond = X86::COND_O; 10382 break; 10383 case ISD::UADDO: 10384 BaseOp = X86ISD::ADD; 10385 Cond = X86::COND_B; 10386 break; 10387 case ISD::SSUBO: 10388 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10389 // set CF, so we can't do this for USUBO. 10390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10391 if (C->isOne()) { 10392 BaseOp = X86ISD::DEC; 10393 Cond = X86::COND_O; 10394 break; 10395 } 10396 BaseOp = X86ISD::SUB; 10397 Cond = X86::COND_O; 10398 break; 10399 case ISD::USUBO: 10400 BaseOp = X86ISD::SUB; 10401 Cond = X86::COND_B; 10402 break; 10403 case ISD::SMULO: 10404 BaseOp = X86ISD::SMUL; 10405 Cond = X86::COND_O; 10406 break; 10407 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10408 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10409 MVT::i32); 10410 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10411 10412 SDValue SetCC = 10413 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10414 DAG.getConstant(X86::COND_O, MVT::i32), 10415 SDValue(Sum.getNode(), 2)); 10416 10417 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10418 } 10419 } 10420 10421 // Also sets EFLAGS. 10422 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10423 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10424 10425 SDValue SetCC = 10426 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10427 DAG.getConstant(Cond, MVT::i32), 10428 SDValue(Sum.getNode(), 1)); 10429 10430 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10431} 10432 10433SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10434 SelectionDAG &DAG) const { 10435 DebugLoc dl = Op.getDebugLoc(); 10436 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10437 EVT VT = Op.getValueType(); 10438 10439 if (!Subtarget->hasSSE2() || !VT.isVector()) 10440 return SDValue(); 10441 10442 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10443 ExtraVT.getScalarType().getSizeInBits(); 10444 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10445 10446 switch (VT.getSimpleVT().SimpleTy) { 10447 default: return SDValue(); 10448 case MVT::v8i32: 10449 case MVT::v16i16: 10450 if (!Subtarget->hasAVX()) 10451 return SDValue(); 10452 if (!Subtarget->hasAVX2()) { 10453 // needs to be split 10454 int NumElems = VT.getVectorNumElements(); 10455 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10456 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10457 10458 // Extract the LHS vectors 10459 SDValue LHS = Op.getOperand(0); 10460 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10461 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10462 10463 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10464 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10465 10466 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10467 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10468 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10469 ExtraNumElems/2); 10470 SDValue Extra = DAG.getValueType(ExtraVT); 10471 10472 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10473 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10474 10475 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10476 } 10477 // fall through 10478 case MVT::v4i32: 10479 case MVT::v8i16: { 10480 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10481 Op.getOperand(0), ShAmt, DAG); 10482 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10483 } 10484 } 10485} 10486 10487 10488SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10489 DebugLoc dl = Op.getDebugLoc(); 10490 10491 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10492 // There isn't any reason to disable it if the target processor supports it. 10493 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10494 SDValue Chain = Op.getOperand(0); 10495 SDValue Zero = DAG.getConstant(0, MVT::i32); 10496 SDValue Ops[] = { 10497 DAG.getRegister(X86::ESP, MVT::i32), // Base 10498 DAG.getTargetConstant(1, MVT::i8), // Scale 10499 DAG.getRegister(0, MVT::i32), // Index 10500 DAG.getTargetConstant(0, MVT::i32), // Disp 10501 DAG.getRegister(0, MVT::i32), // Segment. 10502 Zero, 10503 Chain 10504 }; 10505 SDNode *Res = 10506 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10507 array_lengthof(Ops)); 10508 return SDValue(Res, 0); 10509 } 10510 10511 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10512 if (!isDev) 10513 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10514 10515 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10516 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10517 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10518 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10519 10520 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10521 if (!Op1 && !Op2 && !Op3 && Op4) 10522 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10523 10524 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10525 if (Op1 && !Op2 && !Op3 && !Op4) 10526 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10527 10528 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10529 // (MFENCE)>; 10530 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10531} 10532 10533SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10534 SelectionDAG &DAG) const { 10535 DebugLoc dl = Op.getDebugLoc(); 10536 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10537 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10538 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10539 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10540 10541 // The only fence that needs an instruction is a sequentially-consistent 10542 // cross-thread fence. 10543 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10544 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10545 // no-sse2). There isn't any reason to disable it if the target processor 10546 // supports it. 10547 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10548 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10549 10550 SDValue Chain = Op.getOperand(0); 10551 SDValue Zero = DAG.getConstant(0, MVT::i32); 10552 SDValue Ops[] = { 10553 DAG.getRegister(X86::ESP, MVT::i32), // Base 10554 DAG.getTargetConstant(1, MVT::i8), // Scale 10555 DAG.getRegister(0, MVT::i32), // Index 10556 DAG.getTargetConstant(0, MVT::i32), // Disp 10557 DAG.getRegister(0, MVT::i32), // Segment. 10558 Zero, 10559 Chain 10560 }; 10561 SDNode *Res = 10562 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10563 array_lengthof(Ops)); 10564 return SDValue(Res, 0); 10565 } 10566 10567 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10568 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10569} 10570 10571 10572SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10573 EVT T = Op.getValueType(); 10574 DebugLoc DL = Op.getDebugLoc(); 10575 unsigned Reg = 0; 10576 unsigned size = 0; 10577 switch(T.getSimpleVT().SimpleTy) { 10578 default: llvm_unreachable("Invalid value type!"); 10579 case MVT::i8: Reg = X86::AL; size = 1; break; 10580 case MVT::i16: Reg = X86::AX; size = 2; break; 10581 case MVT::i32: Reg = X86::EAX; size = 4; break; 10582 case MVT::i64: 10583 assert(Subtarget->is64Bit() && "Node not type legal!"); 10584 Reg = X86::RAX; size = 8; 10585 break; 10586 } 10587 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10588 Op.getOperand(2), SDValue()); 10589 SDValue Ops[] = { cpIn.getValue(0), 10590 Op.getOperand(1), 10591 Op.getOperand(3), 10592 DAG.getTargetConstant(size, MVT::i8), 10593 cpIn.getValue(1) }; 10594 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10595 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10596 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10597 Ops, 5, T, MMO); 10598 SDValue cpOut = 10599 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10600 return cpOut; 10601} 10602 10603SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10604 SelectionDAG &DAG) const { 10605 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10606 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10607 SDValue TheChain = Op.getOperand(0); 10608 DebugLoc dl = Op.getDebugLoc(); 10609 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10610 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10611 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10612 rax.getValue(2)); 10613 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10614 DAG.getConstant(32, MVT::i8)); 10615 SDValue Ops[] = { 10616 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10617 rdx.getValue(1) 10618 }; 10619 return DAG.getMergeValues(Ops, 2, dl); 10620} 10621 10622SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10623 SelectionDAG &DAG) const { 10624 EVT SrcVT = Op.getOperand(0).getValueType(); 10625 EVT DstVT = Op.getValueType(); 10626 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10627 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10628 assert((DstVT == MVT::i64 || 10629 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10630 "Unexpected custom BITCAST"); 10631 // i64 <=> MMX conversions are Legal. 10632 if (SrcVT==MVT::i64 && DstVT.isVector()) 10633 return Op; 10634 if (DstVT==MVT::i64 && SrcVT.isVector()) 10635 return Op; 10636 // MMX <=> MMX conversions are Legal. 10637 if (SrcVT.isVector() && DstVT.isVector()) 10638 return Op; 10639 // All other conversions need to be expanded. 10640 return SDValue(); 10641} 10642 10643SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10644 SDNode *Node = Op.getNode(); 10645 DebugLoc dl = Node->getDebugLoc(); 10646 EVT T = Node->getValueType(0); 10647 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10648 DAG.getConstant(0, T), Node->getOperand(2)); 10649 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10650 cast<AtomicSDNode>(Node)->getMemoryVT(), 10651 Node->getOperand(0), 10652 Node->getOperand(1), negOp, 10653 cast<AtomicSDNode>(Node)->getSrcValue(), 10654 cast<AtomicSDNode>(Node)->getAlignment(), 10655 cast<AtomicSDNode>(Node)->getOrdering(), 10656 cast<AtomicSDNode>(Node)->getSynchScope()); 10657} 10658 10659static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10660 SDNode *Node = Op.getNode(); 10661 DebugLoc dl = Node->getDebugLoc(); 10662 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10663 10664 // Convert seq_cst store -> xchg 10665 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10666 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10667 // (The only way to get a 16-byte store is cmpxchg16b) 10668 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10669 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10670 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10671 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10672 cast<AtomicSDNode>(Node)->getMemoryVT(), 10673 Node->getOperand(0), 10674 Node->getOperand(1), Node->getOperand(2), 10675 cast<AtomicSDNode>(Node)->getMemOperand(), 10676 cast<AtomicSDNode>(Node)->getOrdering(), 10677 cast<AtomicSDNode>(Node)->getSynchScope()); 10678 return Swap.getValue(1); 10679 } 10680 // Other atomic stores have a simple pattern. 10681 return Op; 10682} 10683 10684static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10685 EVT VT = Op.getNode()->getValueType(0); 10686 10687 // Let legalize expand this if it isn't a legal type yet. 10688 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10689 return SDValue(); 10690 10691 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10692 10693 unsigned Opc; 10694 bool ExtraOp = false; 10695 switch (Op.getOpcode()) { 10696 default: llvm_unreachable("Invalid code"); 10697 case ISD::ADDC: Opc = X86ISD::ADD; break; 10698 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10699 case ISD::SUBC: Opc = X86ISD::SUB; break; 10700 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10701 } 10702 10703 if (!ExtraOp) 10704 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10705 Op.getOperand(1)); 10706 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10707 Op.getOperand(1), Op.getOperand(2)); 10708} 10709 10710/// LowerOperation - Provide custom lowering hooks for some operations. 10711/// 10712SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10713 switch (Op.getOpcode()) { 10714 default: llvm_unreachable("Should not custom lower this!"); 10715 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10716 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10717 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10718 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10719 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10720 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10721 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10722 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10723 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10724 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10725 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10726 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10727 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10728 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10729 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10730 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10731 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10732 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10733 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10734 case ISD::SHL_PARTS: 10735 case ISD::SRA_PARTS: 10736 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10737 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10738 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10739 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10740 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10741 case ISD::FABS: return LowerFABS(Op, DAG); 10742 case ISD::FNEG: return LowerFNEG(Op, DAG); 10743 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10744 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10745 case ISD::SETCC: return LowerSETCC(Op, DAG); 10746 case ISD::SELECT: return LowerSELECT(Op, DAG); 10747 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10748 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10749 case ISD::VASTART: return LowerVASTART(Op, DAG); 10750 case ISD::VAARG: return LowerVAARG(Op, DAG); 10751 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10752 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10753 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10754 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10755 case ISD::FRAME_TO_ARGS_OFFSET: 10756 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10757 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10758 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10759 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10760 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10761 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10762 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10763 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10764 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10765 case ISD::MUL: return LowerMUL(Op, DAG); 10766 case ISD::SRA: 10767 case ISD::SRL: 10768 case ISD::SHL: return LowerShift(Op, DAG); 10769 case ISD::SADDO: 10770 case ISD::UADDO: 10771 case ISD::SSUBO: 10772 case ISD::USUBO: 10773 case ISD::SMULO: 10774 case ISD::UMULO: return LowerXALUO(Op, DAG); 10775 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10776 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10777 case ISD::ADDC: 10778 case ISD::ADDE: 10779 case ISD::SUBC: 10780 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10781 case ISD::ADD: return LowerADD(Op, DAG); 10782 case ISD::SUB: return LowerSUB(Op, DAG); 10783 } 10784} 10785 10786static void ReplaceATOMIC_LOAD(SDNode *Node, 10787 SmallVectorImpl<SDValue> &Results, 10788 SelectionDAG &DAG) { 10789 DebugLoc dl = Node->getDebugLoc(); 10790 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10791 10792 // Convert wide load -> cmpxchg8b/cmpxchg16b 10793 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10794 // (The only way to get a 16-byte load is cmpxchg16b) 10795 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10796 SDValue Zero = DAG.getConstant(0, VT); 10797 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10798 Node->getOperand(0), 10799 Node->getOperand(1), Zero, Zero, 10800 cast<AtomicSDNode>(Node)->getMemOperand(), 10801 cast<AtomicSDNode>(Node)->getOrdering(), 10802 cast<AtomicSDNode>(Node)->getSynchScope()); 10803 Results.push_back(Swap.getValue(0)); 10804 Results.push_back(Swap.getValue(1)); 10805} 10806 10807void X86TargetLowering:: 10808ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10809 SelectionDAG &DAG, unsigned NewOp) const { 10810 DebugLoc dl = Node->getDebugLoc(); 10811 assert (Node->getValueType(0) == MVT::i64 && 10812 "Only know how to expand i64 atomics"); 10813 10814 SDValue Chain = Node->getOperand(0); 10815 SDValue In1 = Node->getOperand(1); 10816 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10817 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10818 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10819 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10820 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10821 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10822 SDValue Result = 10823 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10824 cast<MemSDNode>(Node)->getMemOperand()); 10825 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10826 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10827 Results.push_back(Result.getValue(2)); 10828} 10829 10830/// ReplaceNodeResults - Replace a node with an illegal result type 10831/// with a new node built out of custom code. 10832void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10833 SmallVectorImpl<SDValue>&Results, 10834 SelectionDAG &DAG) const { 10835 DebugLoc dl = N->getDebugLoc(); 10836 switch (N->getOpcode()) { 10837 default: 10838 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10839 case ISD::SIGN_EXTEND_INREG: 10840 case ISD::ADDC: 10841 case ISD::ADDE: 10842 case ISD::SUBC: 10843 case ISD::SUBE: 10844 // We don't want to expand or promote these. 10845 return; 10846 case ISD::FP_TO_SINT: { 10847 std::pair<SDValue,SDValue> Vals = 10848 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10849 SDValue FIST = Vals.first, StackSlot = Vals.second; 10850 if (FIST.getNode() != 0) { 10851 EVT VT = N->getValueType(0); 10852 // Return a load from the stack slot. 10853 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10854 MachinePointerInfo(), 10855 false, false, false, 0)); 10856 } 10857 return; 10858 } 10859 case ISD::READCYCLECOUNTER: { 10860 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10861 SDValue TheChain = N->getOperand(0); 10862 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10863 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10864 rd.getValue(1)); 10865 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10866 eax.getValue(2)); 10867 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10868 SDValue Ops[] = { eax, edx }; 10869 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10870 Results.push_back(edx.getValue(1)); 10871 return; 10872 } 10873 case ISD::ATOMIC_CMP_SWAP: { 10874 EVT T = N->getValueType(0); 10875 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10876 bool Regs64bit = T == MVT::i128; 10877 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10878 SDValue cpInL, cpInH; 10879 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10880 DAG.getConstant(0, HalfT)); 10881 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10882 DAG.getConstant(1, HalfT)); 10883 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10884 Regs64bit ? X86::RAX : X86::EAX, 10885 cpInL, SDValue()); 10886 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10887 Regs64bit ? X86::RDX : X86::EDX, 10888 cpInH, cpInL.getValue(1)); 10889 SDValue swapInL, swapInH; 10890 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10891 DAG.getConstant(0, HalfT)); 10892 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10893 DAG.getConstant(1, HalfT)); 10894 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10895 Regs64bit ? X86::RBX : X86::EBX, 10896 swapInL, cpInH.getValue(1)); 10897 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10898 Regs64bit ? X86::RCX : X86::ECX, 10899 swapInH, swapInL.getValue(1)); 10900 SDValue Ops[] = { swapInH.getValue(0), 10901 N->getOperand(1), 10902 swapInH.getValue(1) }; 10903 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10904 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10905 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10906 X86ISD::LCMPXCHG8_DAG; 10907 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10908 Ops, 3, T, MMO); 10909 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10910 Regs64bit ? X86::RAX : X86::EAX, 10911 HalfT, Result.getValue(1)); 10912 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10913 Regs64bit ? X86::RDX : X86::EDX, 10914 HalfT, cpOutL.getValue(2)); 10915 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10916 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10917 Results.push_back(cpOutH.getValue(1)); 10918 return; 10919 } 10920 case ISD::ATOMIC_LOAD_ADD: 10921 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10922 return; 10923 case ISD::ATOMIC_LOAD_AND: 10924 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10925 return; 10926 case ISD::ATOMIC_LOAD_NAND: 10927 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10928 return; 10929 case ISD::ATOMIC_LOAD_OR: 10930 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10931 return; 10932 case ISD::ATOMIC_LOAD_SUB: 10933 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10934 return; 10935 case ISD::ATOMIC_LOAD_XOR: 10936 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10937 return; 10938 case ISD::ATOMIC_SWAP: 10939 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10940 return; 10941 case ISD::ATOMIC_LOAD: 10942 ReplaceATOMIC_LOAD(N, Results, DAG); 10943 } 10944} 10945 10946const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10947 switch (Opcode) { 10948 default: return NULL; 10949 case X86ISD::BSF: return "X86ISD::BSF"; 10950 case X86ISD::BSR: return "X86ISD::BSR"; 10951 case X86ISD::SHLD: return "X86ISD::SHLD"; 10952 case X86ISD::SHRD: return "X86ISD::SHRD"; 10953 case X86ISD::FAND: return "X86ISD::FAND"; 10954 case X86ISD::FOR: return "X86ISD::FOR"; 10955 case X86ISD::FXOR: return "X86ISD::FXOR"; 10956 case X86ISD::FSRL: return "X86ISD::FSRL"; 10957 case X86ISD::FILD: return "X86ISD::FILD"; 10958 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10959 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10960 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10961 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10962 case X86ISD::FLD: return "X86ISD::FLD"; 10963 case X86ISD::FST: return "X86ISD::FST"; 10964 case X86ISD::CALL: return "X86ISD::CALL"; 10965 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10966 case X86ISD::BT: return "X86ISD::BT"; 10967 case X86ISD::CMP: return "X86ISD::CMP"; 10968 case X86ISD::COMI: return "X86ISD::COMI"; 10969 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10970 case X86ISD::SETCC: return "X86ISD::SETCC"; 10971 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10972 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10973 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10974 case X86ISD::CMOV: return "X86ISD::CMOV"; 10975 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10976 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10977 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10978 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10979 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10980 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10981 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10982 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10983 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10984 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10985 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10986 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10987 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10988 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10989 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 10990 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 10991 case X86ISD::HADD: return "X86ISD::HADD"; 10992 case X86ISD::HSUB: return "X86ISD::HSUB"; 10993 case X86ISD::FHADD: return "X86ISD::FHADD"; 10994 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10995 case X86ISD::FMAX: return "X86ISD::FMAX"; 10996 case X86ISD::FMIN: return "X86ISD::FMIN"; 10997 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10998 case X86ISD::FRCP: return "X86ISD::FRCP"; 10999 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11000 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11001 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11002 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11003 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11004 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11005 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11006 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11007 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11008 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11009 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11010 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11011 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11012 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11013 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11014 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11015 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11016 case X86ISD::VSHL: return "X86ISD::VSHL"; 11017 case X86ISD::VSRL: return "X86ISD::VSRL"; 11018 case X86ISD::VSRA: return "X86ISD::VSRA"; 11019 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11020 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11021 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11022 case X86ISD::CMPP: return "X86ISD::CMPP"; 11023 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11024 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11025 case X86ISD::ADD: return "X86ISD::ADD"; 11026 case X86ISD::SUB: return "X86ISD::SUB"; 11027 case X86ISD::ADC: return "X86ISD::ADC"; 11028 case X86ISD::SBB: return "X86ISD::SBB"; 11029 case X86ISD::SMUL: return "X86ISD::SMUL"; 11030 case X86ISD::UMUL: return "X86ISD::UMUL"; 11031 case X86ISD::INC: return "X86ISD::INC"; 11032 case X86ISD::DEC: return "X86ISD::DEC"; 11033 case X86ISD::OR: return "X86ISD::OR"; 11034 case X86ISD::XOR: return "X86ISD::XOR"; 11035 case X86ISD::AND: return "X86ISD::AND"; 11036 case X86ISD::ANDN: return "X86ISD::ANDN"; 11037 case X86ISD::BLSI: return "X86ISD::BLSI"; 11038 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11039 case X86ISD::BLSR: return "X86ISD::BLSR"; 11040 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11041 case X86ISD::PTEST: return "X86ISD::PTEST"; 11042 case X86ISD::TESTP: return "X86ISD::TESTP"; 11043 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11044 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11045 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11046 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11047 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11048 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11049 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11050 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11051 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11052 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11053 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11054 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11055 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11056 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11057 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11058 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11059 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11060 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11061 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11062 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11063 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11064 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11065 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11066 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11067 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11068 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11069 } 11070} 11071 11072// isLegalAddressingMode - Return true if the addressing mode represented 11073// by AM is legal for this target, for a load/store of the specified type. 11074bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11075 Type *Ty) const { 11076 // X86 supports extremely general addressing modes. 11077 CodeModel::Model M = getTargetMachine().getCodeModel(); 11078 Reloc::Model R = getTargetMachine().getRelocationModel(); 11079 11080 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11081 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11082 return false; 11083 11084 if (AM.BaseGV) { 11085 unsigned GVFlags = 11086 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11087 11088 // If a reference to this global requires an extra load, we can't fold it. 11089 if (isGlobalStubReference(GVFlags)) 11090 return false; 11091 11092 // If BaseGV requires a register for the PIC base, we cannot also have a 11093 // BaseReg specified. 11094 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11095 return false; 11096 11097 // If lower 4G is not available, then we must use rip-relative addressing. 11098 if ((M != CodeModel::Small || R != Reloc::Static) && 11099 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11100 return false; 11101 } 11102 11103 switch (AM.Scale) { 11104 case 0: 11105 case 1: 11106 case 2: 11107 case 4: 11108 case 8: 11109 // These scales always work. 11110 break; 11111 case 3: 11112 case 5: 11113 case 9: 11114 // These scales are formed with basereg+scalereg. Only accept if there is 11115 // no basereg yet. 11116 if (AM.HasBaseReg) 11117 return false; 11118 break; 11119 default: // Other stuff never works. 11120 return false; 11121 } 11122 11123 return true; 11124} 11125 11126 11127bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11128 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11129 return false; 11130 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11131 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11132 if (NumBits1 <= NumBits2) 11133 return false; 11134 return true; 11135} 11136 11137bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11138 if (!VT1.isInteger() || !VT2.isInteger()) 11139 return false; 11140 unsigned NumBits1 = VT1.getSizeInBits(); 11141 unsigned NumBits2 = VT2.getSizeInBits(); 11142 if (NumBits1 <= NumBits2) 11143 return false; 11144 return true; 11145} 11146 11147bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11148 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11149 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11150} 11151 11152bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11153 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11154 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11155} 11156 11157bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11158 // i16 instructions are longer (0x66 prefix) and potentially slower. 11159 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11160} 11161 11162/// isShuffleMaskLegal - Targets can use this to indicate that they only 11163/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11164/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11165/// are assumed to be legal. 11166bool 11167X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11168 EVT VT) const { 11169 // Very little shuffling can be done for 64-bit vectors right now. 11170 if (VT.getSizeInBits() == 64) 11171 return false; 11172 11173 // FIXME: pshufb, blends, shifts. 11174 return (VT.getVectorNumElements() == 2 || 11175 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11176 isMOVLMask(M, VT) || 11177 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11178 isPSHUFDMask(M, VT) || 11179 isPSHUFHWMask(M, VT) || 11180 isPSHUFLWMask(M, VT) || 11181 isPALIGNRMask(M, VT, Subtarget) || 11182 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11183 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11184 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11185 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11186} 11187 11188bool 11189X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11190 EVT VT) const { 11191 unsigned NumElts = VT.getVectorNumElements(); 11192 // FIXME: This collection of masks seems suspect. 11193 if (NumElts == 2) 11194 return true; 11195 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11196 return (isMOVLMask(Mask, VT) || 11197 isCommutedMOVLMask(Mask, VT, true) || 11198 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11199 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11200 } 11201 return false; 11202} 11203 11204//===----------------------------------------------------------------------===// 11205// X86 Scheduler Hooks 11206//===----------------------------------------------------------------------===// 11207 11208// private utility function 11209MachineBasicBlock * 11210X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11211 MachineBasicBlock *MBB, 11212 unsigned regOpc, 11213 unsigned immOpc, 11214 unsigned LoadOpc, 11215 unsigned CXchgOpc, 11216 unsigned notOpc, 11217 unsigned EAXreg, 11218 TargetRegisterClass *RC, 11219 bool invSrc) const { 11220 // For the atomic bitwise operator, we generate 11221 // thisMBB: 11222 // newMBB: 11223 // ld t1 = [bitinstr.addr] 11224 // op t2 = t1, [bitinstr.val] 11225 // mov EAX = t1 11226 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11227 // bz newMBB 11228 // fallthrough -->nextMBB 11229 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11230 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11231 MachineFunction::iterator MBBIter = MBB; 11232 ++MBBIter; 11233 11234 /// First build the CFG 11235 MachineFunction *F = MBB->getParent(); 11236 MachineBasicBlock *thisMBB = MBB; 11237 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11238 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11239 F->insert(MBBIter, newMBB); 11240 F->insert(MBBIter, nextMBB); 11241 11242 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11243 nextMBB->splice(nextMBB->begin(), thisMBB, 11244 llvm::next(MachineBasicBlock::iterator(bInstr)), 11245 thisMBB->end()); 11246 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11247 11248 // Update thisMBB to fall through to newMBB 11249 thisMBB->addSuccessor(newMBB); 11250 11251 // newMBB jumps to itself and fall through to nextMBB 11252 newMBB->addSuccessor(nextMBB); 11253 newMBB->addSuccessor(newMBB); 11254 11255 // Insert instructions into newMBB based on incoming instruction 11256 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11257 "unexpected number of operands"); 11258 DebugLoc dl = bInstr->getDebugLoc(); 11259 MachineOperand& destOper = bInstr->getOperand(0); 11260 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11261 int numArgs = bInstr->getNumOperands() - 1; 11262 for (int i=0; i < numArgs; ++i) 11263 argOpers[i] = &bInstr->getOperand(i+1); 11264 11265 // x86 address has 4 operands: base, index, scale, and displacement 11266 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11267 int valArgIndx = lastAddrIndx + 1; 11268 11269 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11270 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11271 for (int i=0; i <= lastAddrIndx; ++i) 11272 (*MIB).addOperand(*argOpers[i]); 11273 11274 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11275 if (invSrc) { 11276 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11277 } 11278 else 11279 tt = t1; 11280 11281 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11282 assert((argOpers[valArgIndx]->isReg() || 11283 argOpers[valArgIndx]->isImm()) && 11284 "invalid operand"); 11285 if (argOpers[valArgIndx]->isReg()) 11286 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11287 else 11288 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11289 MIB.addReg(tt); 11290 (*MIB).addOperand(*argOpers[valArgIndx]); 11291 11292 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11293 MIB.addReg(t1); 11294 11295 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11296 for (int i=0; i <= lastAddrIndx; ++i) 11297 (*MIB).addOperand(*argOpers[i]); 11298 MIB.addReg(t2); 11299 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11300 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11301 bInstr->memoperands_end()); 11302 11303 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11304 MIB.addReg(EAXreg); 11305 11306 // insert branch 11307 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11308 11309 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11310 return nextMBB; 11311} 11312 11313// private utility function: 64 bit atomics on 32 bit host. 11314MachineBasicBlock * 11315X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11316 MachineBasicBlock *MBB, 11317 unsigned regOpcL, 11318 unsigned regOpcH, 11319 unsigned immOpcL, 11320 unsigned immOpcH, 11321 bool invSrc) const { 11322 // For the atomic bitwise operator, we generate 11323 // thisMBB (instructions are in pairs, except cmpxchg8b) 11324 // ld t1,t2 = [bitinstr.addr] 11325 // newMBB: 11326 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11327 // op t5, t6 <- out1, out2, [bitinstr.val] 11328 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11329 // mov ECX, EBX <- t5, t6 11330 // mov EAX, EDX <- t1, t2 11331 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11332 // mov t3, t4 <- EAX, EDX 11333 // bz newMBB 11334 // result in out1, out2 11335 // fallthrough -->nextMBB 11336 11337 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11338 const unsigned LoadOpc = X86::MOV32rm; 11339 const unsigned NotOpc = X86::NOT32r; 11340 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11341 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11342 MachineFunction::iterator MBBIter = MBB; 11343 ++MBBIter; 11344 11345 /// First build the CFG 11346 MachineFunction *F = MBB->getParent(); 11347 MachineBasicBlock *thisMBB = MBB; 11348 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11349 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11350 F->insert(MBBIter, newMBB); 11351 F->insert(MBBIter, nextMBB); 11352 11353 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11354 nextMBB->splice(nextMBB->begin(), thisMBB, 11355 llvm::next(MachineBasicBlock::iterator(bInstr)), 11356 thisMBB->end()); 11357 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11358 11359 // Update thisMBB to fall through to newMBB 11360 thisMBB->addSuccessor(newMBB); 11361 11362 // newMBB jumps to itself and fall through to nextMBB 11363 newMBB->addSuccessor(nextMBB); 11364 newMBB->addSuccessor(newMBB); 11365 11366 DebugLoc dl = bInstr->getDebugLoc(); 11367 // Insert instructions into newMBB based on incoming instruction 11368 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11369 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11370 "unexpected number of operands"); 11371 MachineOperand& dest1Oper = bInstr->getOperand(0); 11372 MachineOperand& dest2Oper = bInstr->getOperand(1); 11373 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11374 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11375 argOpers[i] = &bInstr->getOperand(i+2); 11376 11377 // We use some of the operands multiple times, so conservatively just 11378 // clear any kill flags that might be present. 11379 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11380 argOpers[i]->setIsKill(false); 11381 } 11382 11383 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11384 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11385 11386 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11387 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11388 for (int i=0; i <= lastAddrIndx; ++i) 11389 (*MIB).addOperand(*argOpers[i]); 11390 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11391 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11392 // add 4 to displacement. 11393 for (int i=0; i <= lastAddrIndx-2; ++i) 11394 (*MIB).addOperand(*argOpers[i]); 11395 MachineOperand newOp3 = *(argOpers[3]); 11396 if (newOp3.isImm()) 11397 newOp3.setImm(newOp3.getImm()+4); 11398 else 11399 newOp3.setOffset(newOp3.getOffset()+4); 11400 (*MIB).addOperand(newOp3); 11401 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11402 11403 // t3/4 are defined later, at the bottom of the loop 11404 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11405 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11406 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11407 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11408 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11409 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11410 11411 // The subsequent operations should be using the destination registers of 11412 //the PHI instructions. 11413 if (invSrc) { 11414 t1 = F->getRegInfo().createVirtualRegister(RC); 11415 t2 = F->getRegInfo().createVirtualRegister(RC); 11416 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11417 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11418 } else { 11419 t1 = dest1Oper.getReg(); 11420 t2 = dest2Oper.getReg(); 11421 } 11422 11423 int valArgIndx = lastAddrIndx + 1; 11424 assert((argOpers[valArgIndx]->isReg() || 11425 argOpers[valArgIndx]->isImm()) && 11426 "invalid operand"); 11427 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11428 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11429 if (argOpers[valArgIndx]->isReg()) 11430 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11431 else 11432 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11433 if (regOpcL != X86::MOV32rr) 11434 MIB.addReg(t1); 11435 (*MIB).addOperand(*argOpers[valArgIndx]); 11436 assert(argOpers[valArgIndx + 1]->isReg() == 11437 argOpers[valArgIndx]->isReg()); 11438 assert(argOpers[valArgIndx + 1]->isImm() == 11439 argOpers[valArgIndx]->isImm()); 11440 if (argOpers[valArgIndx + 1]->isReg()) 11441 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11442 else 11443 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11444 if (regOpcH != X86::MOV32rr) 11445 MIB.addReg(t2); 11446 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11447 11448 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11449 MIB.addReg(t1); 11450 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11451 MIB.addReg(t2); 11452 11453 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11454 MIB.addReg(t5); 11455 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11456 MIB.addReg(t6); 11457 11458 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11459 for (int i=0; i <= lastAddrIndx; ++i) 11460 (*MIB).addOperand(*argOpers[i]); 11461 11462 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11463 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11464 bInstr->memoperands_end()); 11465 11466 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11467 MIB.addReg(X86::EAX); 11468 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11469 MIB.addReg(X86::EDX); 11470 11471 // insert branch 11472 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11473 11474 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11475 return nextMBB; 11476} 11477 11478// private utility function 11479MachineBasicBlock * 11480X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11481 MachineBasicBlock *MBB, 11482 unsigned cmovOpc) const { 11483 // For the atomic min/max operator, we generate 11484 // thisMBB: 11485 // newMBB: 11486 // ld t1 = [min/max.addr] 11487 // mov t2 = [min/max.val] 11488 // cmp t1, t2 11489 // cmov[cond] t2 = t1 11490 // mov EAX = t1 11491 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11492 // bz newMBB 11493 // fallthrough -->nextMBB 11494 // 11495 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11496 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11497 MachineFunction::iterator MBBIter = MBB; 11498 ++MBBIter; 11499 11500 /// First build the CFG 11501 MachineFunction *F = MBB->getParent(); 11502 MachineBasicBlock *thisMBB = MBB; 11503 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11504 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11505 F->insert(MBBIter, newMBB); 11506 F->insert(MBBIter, nextMBB); 11507 11508 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11509 nextMBB->splice(nextMBB->begin(), thisMBB, 11510 llvm::next(MachineBasicBlock::iterator(mInstr)), 11511 thisMBB->end()); 11512 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11513 11514 // Update thisMBB to fall through to newMBB 11515 thisMBB->addSuccessor(newMBB); 11516 11517 // newMBB jumps to newMBB and fall through to nextMBB 11518 newMBB->addSuccessor(nextMBB); 11519 newMBB->addSuccessor(newMBB); 11520 11521 DebugLoc dl = mInstr->getDebugLoc(); 11522 // Insert instructions into newMBB based on incoming instruction 11523 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11524 "unexpected number of operands"); 11525 MachineOperand& destOper = mInstr->getOperand(0); 11526 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11527 int numArgs = mInstr->getNumOperands() - 1; 11528 for (int i=0; i < numArgs; ++i) 11529 argOpers[i] = &mInstr->getOperand(i+1); 11530 11531 // x86 address has 4 operands: base, index, scale, and displacement 11532 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11533 int valArgIndx = lastAddrIndx + 1; 11534 11535 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11536 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11537 for (int i=0; i <= lastAddrIndx; ++i) 11538 (*MIB).addOperand(*argOpers[i]); 11539 11540 // We only support register and immediate values 11541 assert((argOpers[valArgIndx]->isReg() || 11542 argOpers[valArgIndx]->isImm()) && 11543 "invalid operand"); 11544 11545 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11546 if (argOpers[valArgIndx]->isReg()) 11547 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11548 else 11549 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11550 (*MIB).addOperand(*argOpers[valArgIndx]); 11551 11552 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11553 MIB.addReg(t1); 11554 11555 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11556 MIB.addReg(t1); 11557 MIB.addReg(t2); 11558 11559 // Generate movc 11560 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11561 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11562 MIB.addReg(t2); 11563 MIB.addReg(t1); 11564 11565 // Cmp and exchange if none has modified the memory location 11566 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11567 for (int i=0; i <= lastAddrIndx; ++i) 11568 (*MIB).addOperand(*argOpers[i]); 11569 MIB.addReg(t3); 11570 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11571 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11572 mInstr->memoperands_end()); 11573 11574 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11575 MIB.addReg(X86::EAX); 11576 11577 // insert branch 11578 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11579 11580 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11581 return nextMBB; 11582} 11583 11584// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11585// or XMM0_V32I8 in AVX all of this code can be replaced with that 11586// in the .td file. 11587MachineBasicBlock * 11588X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11589 unsigned numArgs, bool memArg) const { 11590 assert(Subtarget->hasSSE42() && 11591 "Target must have SSE4.2 or AVX features enabled"); 11592 11593 DebugLoc dl = MI->getDebugLoc(); 11594 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11595 unsigned Opc; 11596 if (!Subtarget->hasAVX()) { 11597 if (memArg) 11598 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11599 else 11600 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11601 } else { 11602 if (memArg) 11603 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11604 else 11605 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11606 } 11607 11608 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11609 for (unsigned i = 0; i < numArgs; ++i) { 11610 MachineOperand &Op = MI->getOperand(i+1); 11611 if (!(Op.isReg() && Op.isImplicit())) 11612 MIB.addOperand(Op); 11613 } 11614 BuildMI(*BB, MI, dl, 11615 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11616 MI->getOperand(0).getReg()) 11617 .addReg(X86::XMM0); 11618 11619 MI->eraseFromParent(); 11620 return BB; 11621} 11622 11623MachineBasicBlock * 11624X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11625 DebugLoc dl = MI->getDebugLoc(); 11626 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11627 11628 // Address into RAX/EAX, other two args into ECX, EDX. 11629 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11630 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11631 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11632 for (int i = 0; i < X86::AddrNumOperands; ++i) 11633 MIB.addOperand(MI->getOperand(i)); 11634 11635 unsigned ValOps = X86::AddrNumOperands; 11636 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11637 .addReg(MI->getOperand(ValOps).getReg()); 11638 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11639 .addReg(MI->getOperand(ValOps+1).getReg()); 11640 11641 // The instruction doesn't actually take any operands though. 11642 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11643 11644 MI->eraseFromParent(); // The pseudo is gone now. 11645 return BB; 11646} 11647 11648MachineBasicBlock * 11649X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11650 DebugLoc dl = MI->getDebugLoc(); 11651 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11652 11653 // First arg in ECX, the second in EAX. 11654 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11655 .addReg(MI->getOperand(0).getReg()); 11656 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11657 .addReg(MI->getOperand(1).getReg()); 11658 11659 // The instruction doesn't actually take any operands though. 11660 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11661 11662 MI->eraseFromParent(); // The pseudo is gone now. 11663 return BB; 11664} 11665 11666MachineBasicBlock * 11667X86TargetLowering::EmitVAARG64WithCustomInserter( 11668 MachineInstr *MI, 11669 MachineBasicBlock *MBB) const { 11670 // Emit va_arg instruction on X86-64. 11671 11672 // Operands to this pseudo-instruction: 11673 // 0 ) Output : destination address (reg) 11674 // 1-5) Input : va_list address (addr, i64mem) 11675 // 6 ) ArgSize : Size (in bytes) of vararg type 11676 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11677 // 8 ) Align : Alignment of type 11678 // 9 ) EFLAGS (implicit-def) 11679 11680 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11681 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11682 11683 unsigned DestReg = MI->getOperand(0).getReg(); 11684 MachineOperand &Base = MI->getOperand(1); 11685 MachineOperand &Scale = MI->getOperand(2); 11686 MachineOperand &Index = MI->getOperand(3); 11687 MachineOperand &Disp = MI->getOperand(4); 11688 MachineOperand &Segment = MI->getOperand(5); 11689 unsigned ArgSize = MI->getOperand(6).getImm(); 11690 unsigned ArgMode = MI->getOperand(7).getImm(); 11691 unsigned Align = MI->getOperand(8).getImm(); 11692 11693 // Memory Reference 11694 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11695 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11696 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11697 11698 // Machine Information 11699 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11700 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11701 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11702 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11703 DebugLoc DL = MI->getDebugLoc(); 11704 11705 // struct va_list { 11706 // i32 gp_offset 11707 // i32 fp_offset 11708 // i64 overflow_area (address) 11709 // i64 reg_save_area (address) 11710 // } 11711 // sizeof(va_list) = 24 11712 // alignment(va_list) = 8 11713 11714 unsigned TotalNumIntRegs = 6; 11715 unsigned TotalNumXMMRegs = 8; 11716 bool UseGPOffset = (ArgMode == 1); 11717 bool UseFPOffset = (ArgMode == 2); 11718 unsigned MaxOffset = TotalNumIntRegs * 8 + 11719 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11720 11721 /* Align ArgSize to a multiple of 8 */ 11722 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11723 bool NeedsAlign = (Align > 8); 11724 11725 MachineBasicBlock *thisMBB = MBB; 11726 MachineBasicBlock *overflowMBB; 11727 MachineBasicBlock *offsetMBB; 11728 MachineBasicBlock *endMBB; 11729 11730 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11731 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11732 unsigned OffsetReg = 0; 11733 11734 if (!UseGPOffset && !UseFPOffset) { 11735 // If we only pull from the overflow region, we don't create a branch. 11736 // We don't need to alter control flow. 11737 OffsetDestReg = 0; // unused 11738 OverflowDestReg = DestReg; 11739 11740 offsetMBB = NULL; 11741 overflowMBB = thisMBB; 11742 endMBB = thisMBB; 11743 } else { 11744 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11745 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11746 // If not, pull from overflow_area. (branch to overflowMBB) 11747 // 11748 // thisMBB 11749 // | . 11750 // | . 11751 // offsetMBB overflowMBB 11752 // | . 11753 // | . 11754 // endMBB 11755 11756 // Registers for the PHI in endMBB 11757 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11758 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11759 11760 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11761 MachineFunction *MF = MBB->getParent(); 11762 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11763 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11764 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11765 11766 MachineFunction::iterator MBBIter = MBB; 11767 ++MBBIter; 11768 11769 // Insert the new basic blocks 11770 MF->insert(MBBIter, offsetMBB); 11771 MF->insert(MBBIter, overflowMBB); 11772 MF->insert(MBBIter, endMBB); 11773 11774 // Transfer the remainder of MBB and its successor edges to endMBB. 11775 endMBB->splice(endMBB->begin(), thisMBB, 11776 llvm::next(MachineBasicBlock::iterator(MI)), 11777 thisMBB->end()); 11778 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11779 11780 // Make offsetMBB and overflowMBB successors of thisMBB 11781 thisMBB->addSuccessor(offsetMBB); 11782 thisMBB->addSuccessor(overflowMBB); 11783 11784 // endMBB is a successor of both offsetMBB and overflowMBB 11785 offsetMBB->addSuccessor(endMBB); 11786 overflowMBB->addSuccessor(endMBB); 11787 11788 // Load the offset value into a register 11789 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11790 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11791 .addOperand(Base) 11792 .addOperand(Scale) 11793 .addOperand(Index) 11794 .addDisp(Disp, UseFPOffset ? 4 : 0) 11795 .addOperand(Segment) 11796 .setMemRefs(MMOBegin, MMOEnd); 11797 11798 // Check if there is enough room left to pull this argument. 11799 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11800 .addReg(OffsetReg) 11801 .addImm(MaxOffset + 8 - ArgSizeA8); 11802 11803 // Branch to "overflowMBB" if offset >= max 11804 // Fall through to "offsetMBB" otherwise 11805 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11806 .addMBB(overflowMBB); 11807 } 11808 11809 // In offsetMBB, emit code to use the reg_save_area. 11810 if (offsetMBB) { 11811 assert(OffsetReg != 0); 11812 11813 // Read the reg_save_area address. 11814 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11815 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11816 .addOperand(Base) 11817 .addOperand(Scale) 11818 .addOperand(Index) 11819 .addDisp(Disp, 16) 11820 .addOperand(Segment) 11821 .setMemRefs(MMOBegin, MMOEnd); 11822 11823 // Zero-extend the offset 11824 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11825 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11826 .addImm(0) 11827 .addReg(OffsetReg) 11828 .addImm(X86::sub_32bit); 11829 11830 // Add the offset to the reg_save_area to get the final address. 11831 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11832 .addReg(OffsetReg64) 11833 .addReg(RegSaveReg); 11834 11835 // Compute the offset for the next argument 11836 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11837 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11838 .addReg(OffsetReg) 11839 .addImm(UseFPOffset ? 16 : 8); 11840 11841 // Store it back into the va_list. 11842 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11843 .addOperand(Base) 11844 .addOperand(Scale) 11845 .addOperand(Index) 11846 .addDisp(Disp, UseFPOffset ? 4 : 0) 11847 .addOperand(Segment) 11848 .addReg(NextOffsetReg) 11849 .setMemRefs(MMOBegin, MMOEnd); 11850 11851 // Jump to endMBB 11852 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11853 .addMBB(endMBB); 11854 } 11855 11856 // 11857 // Emit code to use overflow area 11858 // 11859 11860 // Load the overflow_area address into a register. 11861 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11862 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11863 .addOperand(Base) 11864 .addOperand(Scale) 11865 .addOperand(Index) 11866 .addDisp(Disp, 8) 11867 .addOperand(Segment) 11868 .setMemRefs(MMOBegin, MMOEnd); 11869 11870 // If we need to align it, do so. Otherwise, just copy the address 11871 // to OverflowDestReg. 11872 if (NeedsAlign) { 11873 // Align the overflow address 11874 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11875 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11876 11877 // aligned_addr = (addr + (align-1)) & ~(align-1) 11878 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11879 .addReg(OverflowAddrReg) 11880 .addImm(Align-1); 11881 11882 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11883 .addReg(TmpReg) 11884 .addImm(~(uint64_t)(Align-1)); 11885 } else { 11886 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11887 .addReg(OverflowAddrReg); 11888 } 11889 11890 // Compute the next overflow address after this argument. 11891 // (the overflow address should be kept 8-byte aligned) 11892 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11893 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11894 .addReg(OverflowDestReg) 11895 .addImm(ArgSizeA8); 11896 11897 // Store the new overflow address. 11898 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11899 .addOperand(Base) 11900 .addOperand(Scale) 11901 .addOperand(Index) 11902 .addDisp(Disp, 8) 11903 .addOperand(Segment) 11904 .addReg(NextAddrReg) 11905 .setMemRefs(MMOBegin, MMOEnd); 11906 11907 // If we branched, emit the PHI to the front of endMBB. 11908 if (offsetMBB) { 11909 BuildMI(*endMBB, endMBB->begin(), DL, 11910 TII->get(X86::PHI), DestReg) 11911 .addReg(OffsetDestReg).addMBB(offsetMBB) 11912 .addReg(OverflowDestReg).addMBB(overflowMBB); 11913 } 11914 11915 // Erase the pseudo instruction 11916 MI->eraseFromParent(); 11917 11918 return endMBB; 11919} 11920 11921MachineBasicBlock * 11922X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11923 MachineInstr *MI, 11924 MachineBasicBlock *MBB) const { 11925 // Emit code to save XMM registers to the stack. The ABI says that the 11926 // number of registers to save is given in %al, so it's theoretically 11927 // possible to do an indirect jump trick to avoid saving all of them, 11928 // however this code takes a simpler approach and just executes all 11929 // of the stores if %al is non-zero. It's less code, and it's probably 11930 // easier on the hardware branch predictor, and stores aren't all that 11931 // expensive anyway. 11932 11933 // Create the new basic blocks. One block contains all the XMM stores, 11934 // and one block is the final destination regardless of whether any 11935 // stores were performed. 11936 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11937 MachineFunction *F = MBB->getParent(); 11938 MachineFunction::iterator MBBIter = MBB; 11939 ++MBBIter; 11940 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11941 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11942 F->insert(MBBIter, XMMSaveMBB); 11943 F->insert(MBBIter, EndMBB); 11944 11945 // Transfer the remainder of MBB and its successor edges to EndMBB. 11946 EndMBB->splice(EndMBB->begin(), MBB, 11947 llvm::next(MachineBasicBlock::iterator(MI)), 11948 MBB->end()); 11949 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11950 11951 // The original block will now fall through to the XMM save block. 11952 MBB->addSuccessor(XMMSaveMBB); 11953 // The XMMSaveMBB will fall through to the end block. 11954 XMMSaveMBB->addSuccessor(EndMBB); 11955 11956 // Now add the instructions. 11957 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11958 DebugLoc DL = MI->getDebugLoc(); 11959 11960 unsigned CountReg = MI->getOperand(0).getReg(); 11961 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11962 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11963 11964 if (!Subtarget->isTargetWin64()) { 11965 // If %al is 0, branch around the XMM save block. 11966 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11967 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11968 MBB->addSuccessor(EndMBB); 11969 } 11970 11971 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11972 // In the XMM save block, save all the XMM argument registers. 11973 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11974 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11975 MachineMemOperand *MMO = 11976 F->getMachineMemOperand( 11977 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11978 MachineMemOperand::MOStore, 11979 /*Size=*/16, /*Align=*/16); 11980 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11981 .addFrameIndex(RegSaveFrameIndex) 11982 .addImm(/*Scale=*/1) 11983 .addReg(/*IndexReg=*/0) 11984 .addImm(/*Disp=*/Offset) 11985 .addReg(/*Segment=*/0) 11986 .addReg(MI->getOperand(i).getReg()) 11987 .addMemOperand(MMO); 11988 } 11989 11990 MI->eraseFromParent(); // The pseudo instruction is gone now. 11991 11992 return EndMBB; 11993} 11994 11995// The EFLAGS operand of SelectItr might be missing a kill marker 11996// because there were multiple uses of EFLAGS, and ISel didn't know 11997// which to mark. Figure out whether SelectItr should have had a 11998// kill marker, and set it if it should. Returns the correct kill 11999// marker value. 12000static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12001 MachineBasicBlock* BB, 12002 const TargetRegisterInfo* TRI) { 12003 // Scan forward through BB for a use/def of EFLAGS. 12004 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12005 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12006 const MachineInstr& mi = *miI; 12007 if (mi.readsRegister(X86::EFLAGS)) 12008 return false; 12009 if (mi.definesRegister(X86::EFLAGS)) 12010 break; // Should have kill-flag - update below. 12011 } 12012 12013 // If we hit the end of the block, check whether EFLAGS is live into a 12014 // successor. 12015 if (miI == BB->end()) { 12016 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12017 sEnd = BB->succ_end(); 12018 sItr != sEnd; ++sItr) { 12019 MachineBasicBlock* succ = *sItr; 12020 if (succ->isLiveIn(X86::EFLAGS)) 12021 return false; 12022 } 12023 } 12024 12025 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12026 // out. SelectMI should have a kill flag on EFLAGS. 12027 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12028 return true; 12029} 12030 12031MachineBasicBlock * 12032X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12033 MachineBasicBlock *BB) const { 12034 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12035 DebugLoc DL = MI->getDebugLoc(); 12036 12037 // To "insert" a SELECT_CC instruction, we actually have to insert the 12038 // diamond control-flow pattern. The incoming instruction knows the 12039 // destination vreg to set, the condition code register to branch on, the 12040 // true/false values to select between, and a branch opcode to use. 12041 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12042 MachineFunction::iterator It = BB; 12043 ++It; 12044 12045 // thisMBB: 12046 // ... 12047 // TrueVal = ... 12048 // cmpTY ccX, r1, r2 12049 // bCC copy1MBB 12050 // fallthrough --> copy0MBB 12051 MachineBasicBlock *thisMBB = BB; 12052 MachineFunction *F = BB->getParent(); 12053 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12054 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12055 F->insert(It, copy0MBB); 12056 F->insert(It, sinkMBB); 12057 12058 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12059 // live into the sink and copy blocks. 12060 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12061 if (!MI->killsRegister(X86::EFLAGS) && 12062 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12063 copy0MBB->addLiveIn(X86::EFLAGS); 12064 sinkMBB->addLiveIn(X86::EFLAGS); 12065 } 12066 12067 // Transfer the remainder of BB and its successor edges to sinkMBB. 12068 sinkMBB->splice(sinkMBB->begin(), BB, 12069 llvm::next(MachineBasicBlock::iterator(MI)), 12070 BB->end()); 12071 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12072 12073 // Add the true and fallthrough blocks as its successors. 12074 BB->addSuccessor(copy0MBB); 12075 BB->addSuccessor(sinkMBB); 12076 12077 // Create the conditional branch instruction. 12078 unsigned Opc = 12079 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12080 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12081 12082 // copy0MBB: 12083 // %FalseValue = ... 12084 // # fallthrough to sinkMBB 12085 copy0MBB->addSuccessor(sinkMBB); 12086 12087 // sinkMBB: 12088 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12089 // ... 12090 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12091 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12092 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12093 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12094 12095 MI->eraseFromParent(); // The pseudo instruction is gone now. 12096 return sinkMBB; 12097} 12098 12099MachineBasicBlock * 12100X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12101 bool Is64Bit) const { 12102 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12103 DebugLoc DL = MI->getDebugLoc(); 12104 MachineFunction *MF = BB->getParent(); 12105 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12106 12107 assert(getTargetMachine().Options.EnableSegmentedStacks); 12108 12109 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12110 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12111 12112 // BB: 12113 // ... [Till the alloca] 12114 // If stacklet is not large enough, jump to mallocMBB 12115 // 12116 // bumpMBB: 12117 // Allocate by subtracting from RSP 12118 // Jump to continueMBB 12119 // 12120 // mallocMBB: 12121 // Allocate by call to runtime 12122 // 12123 // continueMBB: 12124 // ... 12125 // [rest of original BB] 12126 // 12127 12128 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12129 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12130 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12131 12132 MachineRegisterInfo &MRI = MF->getRegInfo(); 12133 const TargetRegisterClass *AddrRegClass = 12134 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12135 12136 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12137 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12138 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12139 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12140 sizeVReg = MI->getOperand(1).getReg(), 12141 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12142 12143 MachineFunction::iterator MBBIter = BB; 12144 ++MBBIter; 12145 12146 MF->insert(MBBIter, bumpMBB); 12147 MF->insert(MBBIter, mallocMBB); 12148 MF->insert(MBBIter, continueMBB); 12149 12150 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12151 (MachineBasicBlock::iterator(MI)), BB->end()); 12152 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12153 12154 // Add code to the main basic block to check if the stack limit has been hit, 12155 // and if so, jump to mallocMBB otherwise to bumpMBB. 12156 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12157 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12158 .addReg(tmpSPVReg).addReg(sizeVReg); 12159 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12160 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12161 .addReg(SPLimitVReg); 12162 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12163 12164 // bumpMBB simply decreases the stack pointer, since we know the current 12165 // stacklet has enough space. 12166 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12167 .addReg(SPLimitVReg); 12168 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12169 .addReg(SPLimitVReg); 12170 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12171 12172 // Calls into a routine in libgcc to allocate more space from the heap. 12173 if (Is64Bit) { 12174 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12175 .addReg(sizeVReg); 12176 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12177 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12178 } else { 12179 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12180 .addImm(12); 12181 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12182 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12183 .addExternalSymbol("__morestack_allocate_stack_space"); 12184 } 12185 12186 if (!Is64Bit) 12187 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12188 .addImm(16); 12189 12190 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12191 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12192 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12193 12194 // Set up the CFG correctly. 12195 BB->addSuccessor(bumpMBB); 12196 BB->addSuccessor(mallocMBB); 12197 mallocMBB->addSuccessor(continueMBB); 12198 bumpMBB->addSuccessor(continueMBB); 12199 12200 // Take care of the PHI nodes. 12201 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12202 MI->getOperand(0).getReg()) 12203 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12204 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12205 12206 // Delete the original pseudo instruction. 12207 MI->eraseFromParent(); 12208 12209 // And we're done. 12210 return continueMBB; 12211} 12212 12213MachineBasicBlock * 12214X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12215 MachineBasicBlock *BB) const { 12216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12217 DebugLoc DL = MI->getDebugLoc(); 12218 12219 assert(!Subtarget->isTargetEnvMacho()); 12220 12221 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12222 // non-trivial part is impdef of ESP. 12223 12224 if (Subtarget->isTargetWin64()) { 12225 if (Subtarget->isTargetCygMing()) { 12226 // ___chkstk(Mingw64): 12227 // Clobbers R10, R11, RAX and EFLAGS. 12228 // Updates RSP. 12229 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12230 .addExternalSymbol("___chkstk") 12231 .addReg(X86::RAX, RegState::Implicit) 12232 .addReg(X86::RSP, RegState::Implicit) 12233 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12234 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12235 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12236 } else { 12237 // __chkstk(MSVCRT): does not update stack pointer. 12238 // Clobbers R10, R11 and EFLAGS. 12239 // FIXME: RAX(allocated size) might be reused and not killed. 12240 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12241 .addExternalSymbol("__chkstk") 12242 .addReg(X86::RAX, RegState::Implicit) 12243 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12244 // RAX has the offset to subtracted from RSP. 12245 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12246 .addReg(X86::RSP) 12247 .addReg(X86::RAX); 12248 } 12249 } else { 12250 const char *StackProbeSymbol = 12251 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12252 12253 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12254 .addExternalSymbol(StackProbeSymbol) 12255 .addReg(X86::EAX, RegState::Implicit) 12256 .addReg(X86::ESP, RegState::Implicit) 12257 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12258 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12259 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12260 } 12261 12262 MI->eraseFromParent(); // The pseudo instruction is gone now. 12263 return BB; 12264} 12265 12266MachineBasicBlock * 12267X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12268 MachineBasicBlock *BB) const { 12269 // This is pretty easy. We're taking the value that we received from 12270 // our load from the relocation, sticking it in either RDI (x86-64) 12271 // or EAX and doing an indirect call. The return value will then 12272 // be in the normal return register. 12273 const X86InstrInfo *TII 12274 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12275 DebugLoc DL = MI->getDebugLoc(); 12276 MachineFunction *F = BB->getParent(); 12277 12278 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12279 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12280 12281 if (Subtarget->is64Bit()) { 12282 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12283 TII->get(X86::MOV64rm), X86::RDI) 12284 .addReg(X86::RIP) 12285 .addImm(0).addReg(0) 12286 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12287 MI->getOperand(3).getTargetFlags()) 12288 .addReg(0); 12289 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12290 addDirectMem(MIB, X86::RDI); 12291 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12292 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12293 TII->get(X86::MOV32rm), X86::EAX) 12294 .addReg(0) 12295 .addImm(0).addReg(0) 12296 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12297 MI->getOperand(3).getTargetFlags()) 12298 .addReg(0); 12299 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12300 addDirectMem(MIB, X86::EAX); 12301 } else { 12302 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12303 TII->get(X86::MOV32rm), X86::EAX) 12304 .addReg(TII->getGlobalBaseReg(F)) 12305 .addImm(0).addReg(0) 12306 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12307 MI->getOperand(3).getTargetFlags()) 12308 .addReg(0); 12309 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12310 addDirectMem(MIB, X86::EAX); 12311 } 12312 12313 MI->eraseFromParent(); // The pseudo instruction is gone now. 12314 return BB; 12315} 12316 12317MachineBasicBlock * 12318X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12319 MachineBasicBlock *BB) const { 12320 switch (MI->getOpcode()) { 12321 default: llvm_unreachable("Unexpected instr type to insert"); 12322 case X86::TAILJMPd64: 12323 case X86::TAILJMPr64: 12324 case X86::TAILJMPm64: 12325 llvm_unreachable("TAILJMP64 would not be touched here."); 12326 case X86::TCRETURNdi64: 12327 case X86::TCRETURNri64: 12328 case X86::TCRETURNmi64: 12329 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12330 // On AMD64, additional defs should be added before register allocation. 12331 if (!Subtarget->isTargetWin64()) { 12332 MI->addRegisterDefined(X86::RSI); 12333 MI->addRegisterDefined(X86::RDI); 12334 MI->addRegisterDefined(X86::XMM6); 12335 MI->addRegisterDefined(X86::XMM7); 12336 MI->addRegisterDefined(X86::XMM8); 12337 MI->addRegisterDefined(X86::XMM9); 12338 MI->addRegisterDefined(X86::XMM10); 12339 MI->addRegisterDefined(X86::XMM11); 12340 MI->addRegisterDefined(X86::XMM12); 12341 MI->addRegisterDefined(X86::XMM13); 12342 MI->addRegisterDefined(X86::XMM14); 12343 MI->addRegisterDefined(X86::XMM15); 12344 } 12345 return BB; 12346 case X86::WIN_ALLOCA: 12347 return EmitLoweredWinAlloca(MI, BB); 12348 case X86::SEG_ALLOCA_32: 12349 return EmitLoweredSegAlloca(MI, BB, false); 12350 case X86::SEG_ALLOCA_64: 12351 return EmitLoweredSegAlloca(MI, BB, true); 12352 case X86::TLSCall_32: 12353 case X86::TLSCall_64: 12354 return EmitLoweredTLSCall(MI, BB); 12355 case X86::CMOV_GR8: 12356 case X86::CMOV_FR32: 12357 case X86::CMOV_FR64: 12358 case X86::CMOV_V4F32: 12359 case X86::CMOV_V2F64: 12360 case X86::CMOV_V2I64: 12361 case X86::CMOV_V8F32: 12362 case X86::CMOV_V4F64: 12363 case X86::CMOV_V4I64: 12364 case X86::CMOV_GR16: 12365 case X86::CMOV_GR32: 12366 case X86::CMOV_RFP32: 12367 case X86::CMOV_RFP64: 12368 case X86::CMOV_RFP80: 12369 return EmitLoweredSelect(MI, BB); 12370 12371 case X86::FP32_TO_INT16_IN_MEM: 12372 case X86::FP32_TO_INT32_IN_MEM: 12373 case X86::FP32_TO_INT64_IN_MEM: 12374 case X86::FP64_TO_INT16_IN_MEM: 12375 case X86::FP64_TO_INT32_IN_MEM: 12376 case X86::FP64_TO_INT64_IN_MEM: 12377 case X86::FP80_TO_INT16_IN_MEM: 12378 case X86::FP80_TO_INT32_IN_MEM: 12379 case X86::FP80_TO_INT64_IN_MEM: { 12380 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12381 DebugLoc DL = MI->getDebugLoc(); 12382 12383 // Change the floating point control register to use "round towards zero" 12384 // mode when truncating to an integer value. 12385 MachineFunction *F = BB->getParent(); 12386 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12387 addFrameReference(BuildMI(*BB, MI, DL, 12388 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12389 12390 // Load the old value of the high byte of the control word... 12391 unsigned OldCW = 12392 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12393 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12394 CWFrameIdx); 12395 12396 // Set the high part to be round to zero... 12397 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12398 .addImm(0xC7F); 12399 12400 // Reload the modified control word now... 12401 addFrameReference(BuildMI(*BB, MI, DL, 12402 TII->get(X86::FLDCW16m)), CWFrameIdx); 12403 12404 // Restore the memory image of control word to original value 12405 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12406 .addReg(OldCW); 12407 12408 // Get the X86 opcode to use. 12409 unsigned Opc; 12410 switch (MI->getOpcode()) { 12411 default: llvm_unreachable("illegal opcode!"); 12412 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12413 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12414 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12415 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12416 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12417 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12418 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12419 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12420 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12421 } 12422 12423 X86AddressMode AM; 12424 MachineOperand &Op = MI->getOperand(0); 12425 if (Op.isReg()) { 12426 AM.BaseType = X86AddressMode::RegBase; 12427 AM.Base.Reg = Op.getReg(); 12428 } else { 12429 AM.BaseType = X86AddressMode::FrameIndexBase; 12430 AM.Base.FrameIndex = Op.getIndex(); 12431 } 12432 Op = MI->getOperand(1); 12433 if (Op.isImm()) 12434 AM.Scale = Op.getImm(); 12435 Op = MI->getOperand(2); 12436 if (Op.isImm()) 12437 AM.IndexReg = Op.getImm(); 12438 Op = MI->getOperand(3); 12439 if (Op.isGlobal()) { 12440 AM.GV = Op.getGlobal(); 12441 } else { 12442 AM.Disp = Op.getImm(); 12443 } 12444 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12445 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12446 12447 // Reload the original control word now. 12448 addFrameReference(BuildMI(*BB, MI, DL, 12449 TII->get(X86::FLDCW16m)), CWFrameIdx); 12450 12451 MI->eraseFromParent(); // The pseudo instruction is gone now. 12452 return BB; 12453 } 12454 // String/text processing lowering. 12455 case X86::PCMPISTRM128REG: 12456 case X86::VPCMPISTRM128REG: 12457 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12458 case X86::PCMPISTRM128MEM: 12459 case X86::VPCMPISTRM128MEM: 12460 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12461 case X86::PCMPESTRM128REG: 12462 case X86::VPCMPESTRM128REG: 12463 return EmitPCMP(MI, BB, 5, false /* in mem */); 12464 case X86::PCMPESTRM128MEM: 12465 case X86::VPCMPESTRM128MEM: 12466 return EmitPCMP(MI, BB, 5, true /* in mem */); 12467 12468 // Thread synchronization. 12469 case X86::MONITOR: 12470 return EmitMonitor(MI, BB); 12471 case X86::MWAIT: 12472 return EmitMwait(MI, BB); 12473 12474 // Atomic Lowering. 12475 case X86::ATOMAND32: 12476 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12477 X86::AND32ri, X86::MOV32rm, 12478 X86::LCMPXCHG32, 12479 X86::NOT32r, X86::EAX, 12480 X86::GR32RegisterClass); 12481 case X86::ATOMOR32: 12482 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12483 X86::OR32ri, X86::MOV32rm, 12484 X86::LCMPXCHG32, 12485 X86::NOT32r, X86::EAX, 12486 X86::GR32RegisterClass); 12487 case X86::ATOMXOR32: 12488 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12489 X86::XOR32ri, X86::MOV32rm, 12490 X86::LCMPXCHG32, 12491 X86::NOT32r, X86::EAX, 12492 X86::GR32RegisterClass); 12493 case X86::ATOMNAND32: 12494 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12495 X86::AND32ri, X86::MOV32rm, 12496 X86::LCMPXCHG32, 12497 X86::NOT32r, X86::EAX, 12498 X86::GR32RegisterClass, true); 12499 case X86::ATOMMIN32: 12500 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12501 case X86::ATOMMAX32: 12502 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12503 case X86::ATOMUMIN32: 12504 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12505 case X86::ATOMUMAX32: 12506 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12507 12508 case X86::ATOMAND16: 12509 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12510 X86::AND16ri, X86::MOV16rm, 12511 X86::LCMPXCHG16, 12512 X86::NOT16r, X86::AX, 12513 X86::GR16RegisterClass); 12514 case X86::ATOMOR16: 12515 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12516 X86::OR16ri, X86::MOV16rm, 12517 X86::LCMPXCHG16, 12518 X86::NOT16r, X86::AX, 12519 X86::GR16RegisterClass); 12520 case X86::ATOMXOR16: 12521 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12522 X86::XOR16ri, X86::MOV16rm, 12523 X86::LCMPXCHG16, 12524 X86::NOT16r, X86::AX, 12525 X86::GR16RegisterClass); 12526 case X86::ATOMNAND16: 12527 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12528 X86::AND16ri, X86::MOV16rm, 12529 X86::LCMPXCHG16, 12530 X86::NOT16r, X86::AX, 12531 X86::GR16RegisterClass, true); 12532 case X86::ATOMMIN16: 12533 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12534 case X86::ATOMMAX16: 12535 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12536 case X86::ATOMUMIN16: 12537 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12538 case X86::ATOMUMAX16: 12539 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12540 12541 case X86::ATOMAND8: 12542 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12543 X86::AND8ri, X86::MOV8rm, 12544 X86::LCMPXCHG8, 12545 X86::NOT8r, X86::AL, 12546 X86::GR8RegisterClass); 12547 case X86::ATOMOR8: 12548 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12549 X86::OR8ri, X86::MOV8rm, 12550 X86::LCMPXCHG8, 12551 X86::NOT8r, X86::AL, 12552 X86::GR8RegisterClass); 12553 case X86::ATOMXOR8: 12554 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12555 X86::XOR8ri, X86::MOV8rm, 12556 X86::LCMPXCHG8, 12557 X86::NOT8r, X86::AL, 12558 X86::GR8RegisterClass); 12559 case X86::ATOMNAND8: 12560 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12561 X86::AND8ri, X86::MOV8rm, 12562 X86::LCMPXCHG8, 12563 X86::NOT8r, X86::AL, 12564 X86::GR8RegisterClass, true); 12565 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12566 // This group is for 64-bit host. 12567 case X86::ATOMAND64: 12568 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12569 X86::AND64ri32, X86::MOV64rm, 12570 X86::LCMPXCHG64, 12571 X86::NOT64r, X86::RAX, 12572 X86::GR64RegisterClass); 12573 case X86::ATOMOR64: 12574 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12575 X86::OR64ri32, X86::MOV64rm, 12576 X86::LCMPXCHG64, 12577 X86::NOT64r, X86::RAX, 12578 X86::GR64RegisterClass); 12579 case X86::ATOMXOR64: 12580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12581 X86::XOR64ri32, X86::MOV64rm, 12582 X86::LCMPXCHG64, 12583 X86::NOT64r, X86::RAX, 12584 X86::GR64RegisterClass); 12585 case X86::ATOMNAND64: 12586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12587 X86::AND64ri32, X86::MOV64rm, 12588 X86::LCMPXCHG64, 12589 X86::NOT64r, X86::RAX, 12590 X86::GR64RegisterClass, true); 12591 case X86::ATOMMIN64: 12592 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12593 case X86::ATOMMAX64: 12594 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12595 case X86::ATOMUMIN64: 12596 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12597 case X86::ATOMUMAX64: 12598 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12599 12600 // This group does 64-bit operations on a 32-bit host. 12601 case X86::ATOMAND6432: 12602 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12603 X86::AND32rr, X86::AND32rr, 12604 X86::AND32ri, X86::AND32ri, 12605 false); 12606 case X86::ATOMOR6432: 12607 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12608 X86::OR32rr, X86::OR32rr, 12609 X86::OR32ri, X86::OR32ri, 12610 false); 12611 case X86::ATOMXOR6432: 12612 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12613 X86::XOR32rr, X86::XOR32rr, 12614 X86::XOR32ri, X86::XOR32ri, 12615 false); 12616 case X86::ATOMNAND6432: 12617 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12618 X86::AND32rr, X86::AND32rr, 12619 X86::AND32ri, X86::AND32ri, 12620 true); 12621 case X86::ATOMADD6432: 12622 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12623 X86::ADD32rr, X86::ADC32rr, 12624 X86::ADD32ri, X86::ADC32ri, 12625 false); 12626 case X86::ATOMSUB6432: 12627 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12628 X86::SUB32rr, X86::SBB32rr, 12629 X86::SUB32ri, X86::SBB32ri, 12630 false); 12631 case X86::ATOMSWAP6432: 12632 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12633 X86::MOV32rr, X86::MOV32rr, 12634 X86::MOV32ri, X86::MOV32ri, 12635 false); 12636 case X86::VASTART_SAVE_XMM_REGS: 12637 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12638 12639 case X86::VAARG_64: 12640 return EmitVAARG64WithCustomInserter(MI, BB); 12641 } 12642} 12643 12644//===----------------------------------------------------------------------===// 12645// X86 Optimization Hooks 12646//===----------------------------------------------------------------------===// 12647 12648void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12649 const APInt &Mask, 12650 APInt &KnownZero, 12651 APInt &KnownOne, 12652 const SelectionDAG &DAG, 12653 unsigned Depth) const { 12654 unsigned Opc = Op.getOpcode(); 12655 assert((Opc >= ISD::BUILTIN_OP_END || 12656 Opc == ISD::INTRINSIC_WO_CHAIN || 12657 Opc == ISD::INTRINSIC_W_CHAIN || 12658 Opc == ISD::INTRINSIC_VOID) && 12659 "Should use MaskedValueIsZero if you don't know whether Op" 12660 " is a target node!"); 12661 12662 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12663 switch (Opc) { 12664 default: break; 12665 case X86ISD::ADD: 12666 case X86ISD::SUB: 12667 case X86ISD::ADC: 12668 case X86ISD::SBB: 12669 case X86ISD::SMUL: 12670 case X86ISD::UMUL: 12671 case X86ISD::INC: 12672 case X86ISD::DEC: 12673 case X86ISD::OR: 12674 case X86ISD::XOR: 12675 case X86ISD::AND: 12676 // These nodes' second result is a boolean. 12677 if (Op.getResNo() == 0) 12678 break; 12679 // Fallthrough 12680 case X86ISD::SETCC: 12681 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12682 Mask.getBitWidth() - 1); 12683 break; 12684 case ISD::INTRINSIC_WO_CHAIN: { 12685 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12686 unsigned NumLoBits = 0; 12687 switch (IntId) { 12688 default: break; 12689 case Intrinsic::x86_sse_movmsk_ps: 12690 case Intrinsic::x86_avx_movmsk_ps_256: 12691 case Intrinsic::x86_sse2_movmsk_pd: 12692 case Intrinsic::x86_avx_movmsk_pd_256: 12693 case Intrinsic::x86_mmx_pmovmskb: 12694 case Intrinsic::x86_sse2_pmovmskb_128: 12695 case Intrinsic::x86_avx2_pmovmskb: { 12696 // High bits of movmskp{s|d}, pmovmskb are known zero. 12697 switch (IntId) { 12698 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12699 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12700 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12701 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12702 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12703 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12704 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12705 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12706 } 12707 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12708 Mask.getBitWidth() - NumLoBits); 12709 break; 12710 } 12711 } 12712 break; 12713 } 12714 } 12715} 12716 12717unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12718 unsigned Depth) const { 12719 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12720 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12721 return Op.getValueType().getScalarType().getSizeInBits(); 12722 12723 // Fallback case. 12724 return 1; 12725} 12726 12727/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12728/// node is a GlobalAddress + offset. 12729bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12730 const GlobalValue* &GA, 12731 int64_t &Offset) const { 12732 if (N->getOpcode() == X86ISD::Wrapper) { 12733 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12734 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12735 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12736 return true; 12737 } 12738 } 12739 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12740} 12741 12742/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12743/// same as extracting the high 128-bit part of 256-bit vector and then 12744/// inserting the result into the low part of a new 256-bit vector 12745static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12746 EVT VT = SVOp->getValueType(0); 12747 int NumElems = VT.getVectorNumElements(); 12748 12749 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12750 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12751 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12752 SVOp->getMaskElt(j) >= 0) 12753 return false; 12754 12755 return true; 12756} 12757 12758/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12759/// same as extracting the low 128-bit part of 256-bit vector and then 12760/// inserting the result into the high part of a new 256-bit vector 12761static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12762 EVT VT = SVOp->getValueType(0); 12763 int NumElems = VT.getVectorNumElements(); 12764 12765 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12766 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12767 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12768 SVOp->getMaskElt(j) >= 0) 12769 return false; 12770 12771 return true; 12772} 12773 12774/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12775static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12776 TargetLowering::DAGCombinerInfo &DCI, 12777 const X86Subtarget* Subtarget) { 12778 DebugLoc dl = N->getDebugLoc(); 12779 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12780 SDValue V1 = SVOp->getOperand(0); 12781 SDValue V2 = SVOp->getOperand(1); 12782 EVT VT = SVOp->getValueType(0); 12783 int NumElems = VT.getVectorNumElements(); 12784 12785 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12786 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12787 // 12788 // 0,0,0,... 12789 // | 12790 // V UNDEF BUILD_VECTOR UNDEF 12791 // \ / \ / 12792 // CONCAT_VECTOR CONCAT_VECTOR 12793 // \ / 12794 // \ / 12795 // RESULT: V + zero extended 12796 // 12797 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12798 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12799 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12800 return SDValue(); 12801 12802 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12803 return SDValue(); 12804 12805 // To match the shuffle mask, the first half of the mask should 12806 // be exactly the first vector, and all the rest a splat with the 12807 // first element of the second one. 12808 for (int i = 0; i < NumElems/2; ++i) 12809 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12810 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12811 return SDValue(); 12812 12813 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12814 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12815 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12816 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12817 SDValue ResNode = 12818 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12819 Ld->getMemoryVT(), 12820 Ld->getPointerInfo(), 12821 Ld->getAlignment(), 12822 false/*isVolatile*/, true/*ReadMem*/, 12823 false/*WriteMem*/); 12824 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12825 } 12826 12827 // Emit a zeroed vector and insert the desired subvector on its 12828 // first half. 12829 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12830 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12831 DAG.getConstant(0, MVT::i32), DAG, dl); 12832 return DCI.CombineTo(N, InsV); 12833 } 12834 12835 //===--------------------------------------------------------------------===// 12836 // Combine some shuffles into subvector extracts and inserts: 12837 // 12838 12839 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12840 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12841 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12842 DAG, dl); 12843 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12844 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12845 return DCI.CombineTo(N, InsV); 12846 } 12847 12848 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12849 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12850 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12851 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12852 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12853 return DCI.CombineTo(N, InsV); 12854 } 12855 12856 return SDValue(); 12857} 12858 12859/// PerformShuffleCombine - Performs several different shuffle combines. 12860static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12861 TargetLowering::DAGCombinerInfo &DCI, 12862 const X86Subtarget *Subtarget) { 12863 DebugLoc dl = N->getDebugLoc(); 12864 EVT VT = N->getValueType(0); 12865 12866 // Don't create instructions with illegal types after legalize types has run. 12867 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12868 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12869 return SDValue(); 12870 12871 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12872 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12873 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12874 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 12875 12876 // Only handle 128 wide vector from here on. 12877 if (VT.getSizeInBits() != 128) 12878 return SDValue(); 12879 12880 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12881 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12882 // consecutive, non-overlapping, and in the right order. 12883 SmallVector<SDValue, 16> Elts; 12884 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12885 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12886 12887 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12888} 12889 12890 12891/// PerformTruncateCombine - Converts truncate operation to 12892/// a sequence of vector shuffle operations. 12893/// It is possible when we truncate 256-bit vector to 128-bit vector 12894 12895SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 12896 DAGCombinerInfo &DCI) const { 12897 if (!DCI.isBeforeLegalizeOps()) 12898 return SDValue(); 12899 12900 if (!Subtarget->hasAVX()) return SDValue(); 12901 12902 EVT VT = N->getValueType(0); 12903 SDValue Op = N->getOperand(0); 12904 EVT OpVT = Op.getValueType(); 12905 DebugLoc dl = N->getDebugLoc(); 12906 12907 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 12908 12909 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12910 DAG.getIntPtrConstant(0)); 12911 12912 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 12913 DAG.getIntPtrConstant(2)); 12914 12915 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12916 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12917 12918 // PSHUFD 12919 int ShufMask1[] = {0, 2, 0, 0}; 12920 12921 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), 12922 ShufMask1); 12923 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), 12924 ShufMask1); 12925 12926 // MOVLHPS 12927 int ShufMask2[] = {0, 1, 4, 5}; 12928 12929 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 12930 } 12931 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 12932 12933 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12934 DAG.getIntPtrConstant(0)); 12935 12936 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 12937 DAG.getIntPtrConstant(4)); 12938 12939 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 12940 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 12941 12942 // PSHUFB 12943 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 12944 -1, -1, -1, -1, -1, -1, -1, -1}; 12945 12946 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, 12947 DAG.getUNDEF(MVT::v16i8), 12948 ShufMask1); 12949 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, 12950 DAG.getUNDEF(MVT::v16i8), 12951 ShufMask1); 12952 12953 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 12954 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 12955 12956 // MOVLHPS 12957 int ShufMask2[] = {0, 1, 4, 5}; 12958 12959 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 12960 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 12961 } 12962 12963 return SDValue(); 12964} 12965 12966/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12967/// generation and convert it from being a bunch of shuffles and extracts 12968/// to a simple store and scalar loads to extract the elements. 12969static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12970 const TargetLowering &TLI) { 12971 SDValue InputVector = N->getOperand(0); 12972 12973 // Only operate on vectors of 4 elements, where the alternative shuffling 12974 // gets to be more expensive. 12975 if (InputVector.getValueType() != MVT::v4i32) 12976 return SDValue(); 12977 12978 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12979 // single use which is a sign-extend or zero-extend, and all elements are 12980 // used. 12981 SmallVector<SDNode *, 4> Uses; 12982 unsigned ExtractedElements = 0; 12983 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12984 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12985 if (UI.getUse().getResNo() != InputVector.getResNo()) 12986 return SDValue(); 12987 12988 SDNode *Extract = *UI; 12989 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12990 return SDValue(); 12991 12992 if (Extract->getValueType(0) != MVT::i32) 12993 return SDValue(); 12994 if (!Extract->hasOneUse()) 12995 return SDValue(); 12996 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12997 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12998 return SDValue(); 12999 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13000 return SDValue(); 13001 13002 // Record which element was extracted. 13003 ExtractedElements |= 13004 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13005 13006 Uses.push_back(Extract); 13007 } 13008 13009 // If not all the elements were used, this may not be worthwhile. 13010 if (ExtractedElements != 15) 13011 return SDValue(); 13012 13013 // Ok, we've now decided to do the transformation. 13014 DebugLoc dl = InputVector.getDebugLoc(); 13015 13016 // Store the value to a temporary stack slot. 13017 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13018 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13019 MachinePointerInfo(), false, false, 0); 13020 13021 // Replace each use (extract) with a load of the appropriate element. 13022 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13023 UE = Uses.end(); UI != UE; ++UI) { 13024 SDNode *Extract = *UI; 13025 13026 // cOMpute the element's address. 13027 SDValue Idx = Extract->getOperand(1); 13028 unsigned EltSize = 13029 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13030 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13031 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13032 13033 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13034 StackPtr, OffsetVal); 13035 13036 // Load the scalar. 13037 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13038 ScalarAddr, MachinePointerInfo(), 13039 false, false, false, 0); 13040 13041 // Replace the exact with the load. 13042 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13043 } 13044 13045 // The replacement was made in place; don't return anything. 13046 return SDValue(); 13047} 13048 13049/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13050/// nodes. 13051static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13052 TargetLowering::DAGCombinerInfo &DCI, 13053 const X86Subtarget *Subtarget) { 13054 DebugLoc DL = N->getDebugLoc(); 13055 SDValue Cond = N->getOperand(0); 13056 // Get the LHS/RHS of the select. 13057 SDValue LHS = N->getOperand(1); 13058 SDValue RHS = N->getOperand(2); 13059 EVT VT = LHS.getValueType(); 13060 13061 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13062 // instructions match the semantics of the common C idiom x<y?x:y but not 13063 // x<=y?x:y, because of how they handle negative zero (which can be 13064 // ignored in unsafe-math mode). 13065 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13066 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13067 (Subtarget->hasSSE2() || 13068 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13069 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13070 13071 unsigned Opcode = 0; 13072 // Check for x CC y ? x : y. 13073 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13074 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13075 switch (CC) { 13076 default: break; 13077 case ISD::SETULT: 13078 // Converting this to a min would handle NaNs incorrectly, and swapping 13079 // the operands would cause it to handle comparisons between positive 13080 // and negative zero incorrectly. 13081 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13082 if (!DAG.getTarget().Options.UnsafeFPMath && 13083 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13084 break; 13085 std::swap(LHS, RHS); 13086 } 13087 Opcode = X86ISD::FMIN; 13088 break; 13089 case ISD::SETOLE: 13090 // Converting this to a min would handle comparisons between positive 13091 // and negative zero incorrectly. 13092 if (!DAG.getTarget().Options.UnsafeFPMath && 13093 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13094 break; 13095 Opcode = X86ISD::FMIN; 13096 break; 13097 case ISD::SETULE: 13098 // Converting this to a min would handle both negative zeros and NaNs 13099 // incorrectly, but we can swap the operands to fix both. 13100 std::swap(LHS, RHS); 13101 case ISD::SETOLT: 13102 case ISD::SETLT: 13103 case ISD::SETLE: 13104 Opcode = X86ISD::FMIN; 13105 break; 13106 13107 case ISD::SETOGE: 13108 // Converting this to a max would handle comparisons between positive 13109 // and negative zero incorrectly. 13110 if (!DAG.getTarget().Options.UnsafeFPMath && 13111 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13112 break; 13113 Opcode = X86ISD::FMAX; 13114 break; 13115 case ISD::SETUGT: 13116 // Converting this to a max would handle NaNs incorrectly, and swapping 13117 // the operands would cause it to handle comparisons between positive 13118 // and negative zero incorrectly. 13119 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13120 if (!DAG.getTarget().Options.UnsafeFPMath && 13121 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13122 break; 13123 std::swap(LHS, RHS); 13124 } 13125 Opcode = X86ISD::FMAX; 13126 break; 13127 case ISD::SETUGE: 13128 // Converting this to a max would handle both negative zeros and NaNs 13129 // incorrectly, but we can swap the operands to fix both. 13130 std::swap(LHS, RHS); 13131 case ISD::SETOGT: 13132 case ISD::SETGT: 13133 case ISD::SETGE: 13134 Opcode = X86ISD::FMAX; 13135 break; 13136 } 13137 // Check for x CC y ? y : x -- a min/max with reversed arms. 13138 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13139 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13140 switch (CC) { 13141 default: break; 13142 case ISD::SETOGE: 13143 // Converting this to a min would handle comparisons between positive 13144 // and negative zero incorrectly, and swapping the operands would 13145 // cause it to handle NaNs incorrectly. 13146 if (!DAG.getTarget().Options.UnsafeFPMath && 13147 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13148 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13149 break; 13150 std::swap(LHS, RHS); 13151 } 13152 Opcode = X86ISD::FMIN; 13153 break; 13154 case ISD::SETUGT: 13155 // Converting this to a min would handle NaNs incorrectly. 13156 if (!DAG.getTarget().Options.UnsafeFPMath && 13157 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13158 break; 13159 Opcode = X86ISD::FMIN; 13160 break; 13161 case ISD::SETUGE: 13162 // Converting this to a min would handle both negative zeros and NaNs 13163 // incorrectly, but we can swap the operands to fix both. 13164 std::swap(LHS, RHS); 13165 case ISD::SETOGT: 13166 case ISD::SETGT: 13167 case ISD::SETGE: 13168 Opcode = X86ISD::FMIN; 13169 break; 13170 13171 case ISD::SETULT: 13172 // Converting this to a max would handle NaNs incorrectly. 13173 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13174 break; 13175 Opcode = X86ISD::FMAX; 13176 break; 13177 case ISD::SETOLE: 13178 // Converting this to a max would handle comparisons between positive 13179 // and negative zero incorrectly, and swapping the operands would 13180 // cause it to handle NaNs incorrectly. 13181 if (!DAG.getTarget().Options.UnsafeFPMath && 13182 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13183 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13184 break; 13185 std::swap(LHS, RHS); 13186 } 13187 Opcode = X86ISD::FMAX; 13188 break; 13189 case ISD::SETULE: 13190 // Converting this to a max would handle both negative zeros and NaNs 13191 // incorrectly, but we can swap the operands to fix both. 13192 std::swap(LHS, RHS); 13193 case ISD::SETOLT: 13194 case ISD::SETLT: 13195 case ISD::SETLE: 13196 Opcode = X86ISD::FMAX; 13197 break; 13198 } 13199 } 13200 13201 if (Opcode) 13202 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13203 } 13204 13205 // If this is a select between two integer constants, try to do some 13206 // optimizations. 13207 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13208 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13209 // Don't do this for crazy integer types. 13210 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13211 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13212 // so that TrueC (the true value) is larger than FalseC. 13213 bool NeedsCondInvert = false; 13214 13215 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13216 // Efficiently invertible. 13217 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13218 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13219 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13220 NeedsCondInvert = true; 13221 std::swap(TrueC, FalseC); 13222 } 13223 13224 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13225 if (FalseC->getAPIntValue() == 0 && 13226 TrueC->getAPIntValue().isPowerOf2()) { 13227 if (NeedsCondInvert) // Invert the condition if needed. 13228 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13229 DAG.getConstant(1, Cond.getValueType())); 13230 13231 // Zero extend the condition if needed. 13232 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13233 13234 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13235 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13236 DAG.getConstant(ShAmt, MVT::i8)); 13237 } 13238 13239 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13240 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13241 if (NeedsCondInvert) // Invert the condition if needed. 13242 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13243 DAG.getConstant(1, Cond.getValueType())); 13244 13245 // Zero extend the condition if needed. 13246 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13247 FalseC->getValueType(0), Cond); 13248 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13249 SDValue(FalseC, 0)); 13250 } 13251 13252 // Optimize cases that will turn into an LEA instruction. This requires 13253 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13254 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13255 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13256 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13257 13258 bool isFastMultiplier = false; 13259 if (Diff < 10) { 13260 switch ((unsigned char)Diff) { 13261 default: break; 13262 case 1: // result = add base, cond 13263 case 2: // result = lea base( , cond*2) 13264 case 3: // result = lea base(cond, cond*2) 13265 case 4: // result = lea base( , cond*4) 13266 case 5: // result = lea base(cond, cond*4) 13267 case 8: // result = lea base( , cond*8) 13268 case 9: // result = lea base(cond, cond*8) 13269 isFastMultiplier = true; 13270 break; 13271 } 13272 } 13273 13274 if (isFastMultiplier) { 13275 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13276 if (NeedsCondInvert) // Invert the condition if needed. 13277 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13278 DAG.getConstant(1, Cond.getValueType())); 13279 13280 // Zero extend the condition if needed. 13281 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13282 Cond); 13283 // Scale the condition by the difference. 13284 if (Diff != 1) 13285 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13286 DAG.getConstant(Diff, Cond.getValueType())); 13287 13288 // Add the base if non-zero. 13289 if (FalseC->getAPIntValue() != 0) 13290 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13291 SDValue(FalseC, 0)); 13292 return Cond; 13293 } 13294 } 13295 } 13296 } 13297 13298 // Canonicalize max and min: 13299 // (x > y) ? x : y -> (x >= y) ? x : y 13300 // (x < y) ? x : y -> (x <= y) ? x : y 13301 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13302 // the need for an extra compare 13303 // against zero. e.g. 13304 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13305 // subl %esi, %edi 13306 // testl %edi, %edi 13307 // movl $0, %eax 13308 // cmovgl %edi, %eax 13309 // => 13310 // xorl %eax, %eax 13311 // subl %esi, $edi 13312 // cmovsl %eax, %edi 13313 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13314 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13315 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13316 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13317 switch (CC) { 13318 default: break; 13319 case ISD::SETLT: 13320 case ISD::SETGT: { 13321 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13322 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13323 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13324 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13325 } 13326 } 13327 } 13328 13329 // If we know that this node is legal then we know that it is going to be 13330 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13331 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13332 // to simplify previous instructions. 13333 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13334 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13335 !DCI.isBeforeLegalize() && 13336 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13337 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13338 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13339 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13340 13341 APInt KnownZero, KnownOne; 13342 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13343 DCI.isBeforeLegalizeOps()); 13344 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13345 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13346 DCI.CommitTargetLoweringOpt(TLO); 13347 } 13348 13349 return SDValue(); 13350} 13351 13352/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13353static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13354 TargetLowering::DAGCombinerInfo &DCI) { 13355 DebugLoc DL = N->getDebugLoc(); 13356 13357 // If the flag operand isn't dead, don't touch this CMOV. 13358 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13359 return SDValue(); 13360 13361 SDValue FalseOp = N->getOperand(0); 13362 SDValue TrueOp = N->getOperand(1); 13363 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13364 SDValue Cond = N->getOperand(3); 13365 if (CC == X86::COND_E || CC == X86::COND_NE) { 13366 switch (Cond.getOpcode()) { 13367 default: break; 13368 case X86ISD::BSR: 13369 case X86ISD::BSF: 13370 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13371 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13372 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13373 } 13374 } 13375 13376 // If this is a select between two integer constants, try to do some 13377 // optimizations. Note that the operands are ordered the opposite of SELECT 13378 // operands. 13379 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13380 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13381 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13382 // larger than FalseC (the false value). 13383 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13384 CC = X86::GetOppositeBranchCondition(CC); 13385 std::swap(TrueC, FalseC); 13386 } 13387 13388 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13389 // This is efficient for any integer data type (including i8/i16) and 13390 // shift amount. 13391 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13392 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13393 DAG.getConstant(CC, MVT::i8), Cond); 13394 13395 // Zero extend the condition if needed. 13396 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13397 13398 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13399 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13400 DAG.getConstant(ShAmt, MVT::i8)); 13401 if (N->getNumValues() == 2) // Dead flag value? 13402 return DCI.CombineTo(N, Cond, SDValue()); 13403 return Cond; 13404 } 13405 13406 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13407 // for any integer data type, including i8/i16. 13408 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13409 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13410 DAG.getConstant(CC, MVT::i8), Cond); 13411 13412 // Zero extend the condition if needed. 13413 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13414 FalseC->getValueType(0), Cond); 13415 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13416 SDValue(FalseC, 0)); 13417 13418 if (N->getNumValues() == 2) // Dead flag value? 13419 return DCI.CombineTo(N, Cond, SDValue()); 13420 return Cond; 13421 } 13422 13423 // Optimize cases that will turn into an LEA instruction. This requires 13424 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13425 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13426 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13427 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13428 13429 bool isFastMultiplier = false; 13430 if (Diff < 10) { 13431 switch ((unsigned char)Diff) { 13432 default: break; 13433 case 1: // result = add base, cond 13434 case 2: // result = lea base( , cond*2) 13435 case 3: // result = lea base(cond, cond*2) 13436 case 4: // result = lea base( , cond*4) 13437 case 5: // result = lea base(cond, cond*4) 13438 case 8: // result = lea base( , cond*8) 13439 case 9: // result = lea base(cond, cond*8) 13440 isFastMultiplier = true; 13441 break; 13442 } 13443 } 13444 13445 if (isFastMultiplier) { 13446 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13447 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13448 DAG.getConstant(CC, MVT::i8), Cond); 13449 // Zero extend the condition if needed. 13450 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13451 Cond); 13452 // Scale the condition by the difference. 13453 if (Diff != 1) 13454 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13455 DAG.getConstant(Diff, Cond.getValueType())); 13456 13457 // Add the base if non-zero. 13458 if (FalseC->getAPIntValue() != 0) 13459 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13460 SDValue(FalseC, 0)); 13461 if (N->getNumValues() == 2) // Dead flag value? 13462 return DCI.CombineTo(N, Cond, SDValue()); 13463 return Cond; 13464 } 13465 } 13466 } 13467 } 13468 return SDValue(); 13469} 13470 13471 13472/// PerformMulCombine - Optimize a single multiply with constant into two 13473/// in order to implement it with two cheaper instructions, e.g. 13474/// LEA + SHL, LEA + LEA. 13475static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13476 TargetLowering::DAGCombinerInfo &DCI) { 13477 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13478 return SDValue(); 13479 13480 EVT VT = N->getValueType(0); 13481 if (VT != MVT::i64) 13482 return SDValue(); 13483 13484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13485 if (!C) 13486 return SDValue(); 13487 uint64_t MulAmt = C->getZExtValue(); 13488 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13489 return SDValue(); 13490 13491 uint64_t MulAmt1 = 0; 13492 uint64_t MulAmt2 = 0; 13493 if ((MulAmt % 9) == 0) { 13494 MulAmt1 = 9; 13495 MulAmt2 = MulAmt / 9; 13496 } else if ((MulAmt % 5) == 0) { 13497 MulAmt1 = 5; 13498 MulAmt2 = MulAmt / 5; 13499 } else if ((MulAmt % 3) == 0) { 13500 MulAmt1 = 3; 13501 MulAmt2 = MulAmt / 3; 13502 } 13503 if (MulAmt2 && 13504 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13505 DebugLoc DL = N->getDebugLoc(); 13506 13507 if (isPowerOf2_64(MulAmt2) && 13508 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13509 // If second multiplifer is pow2, issue it first. We want the multiply by 13510 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13511 // is an add. 13512 std::swap(MulAmt1, MulAmt2); 13513 13514 SDValue NewMul; 13515 if (isPowerOf2_64(MulAmt1)) 13516 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13517 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13518 else 13519 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13520 DAG.getConstant(MulAmt1, VT)); 13521 13522 if (isPowerOf2_64(MulAmt2)) 13523 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13524 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13525 else 13526 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13527 DAG.getConstant(MulAmt2, VT)); 13528 13529 // Do not add new nodes to DAG combiner worklist. 13530 DCI.CombineTo(N, NewMul, false); 13531 } 13532 return SDValue(); 13533} 13534 13535static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13536 SDValue N0 = N->getOperand(0); 13537 SDValue N1 = N->getOperand(1); 13538 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13539 EVT VT = N0.getValueType(); 13540 13541 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13542 // since the result of setcc_c is all zero's or all ones. 13543 if (VT.isInteger() && !VT.isVector() && 13544 N1C && N0.getOpcode() == ISD::AND && 13545 N0.getOperand(1).getOpcode() == ISD::Constant) { 13546 SDValue N00 = N0.getOperand(0); 13547 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13548 ((N00.getOpcode() == ISD::ANY_EXTEND || 13549 N00.getOpcode() == ISD::ZERO_EXTEND) && 13550 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13551 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13552 APInt ShAmt = N1C->getAPIntValue(); 13553 Mask = Mask.shl(ShAmt); 13554 if (Mask != 0) 13555 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13556 N00, DAG.getConstant(Mask, VT)); 13557 } 13558 } 13559 13560 13561 // Hardware support for vector shifts is sparse which makes us scalarize the 13562 // vector operations in many cases. Also, on sandybridge ADD is faster than 13563 // shl. 13564 // (shl V, 1) -> add V,V 13565 if (isSplatVector(N1.getNode())) { 13566 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13568 // We shift all of the values by one. In many cases we do not have 13569 // hardware support for this operation. This is better expressed as an ADD 13570 // of two values. 13571 if (N1C && (1 == N1C->getZExtValue())) { 13572 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13573 } 13574 } 13575 13576 return SDValue(); 13577} 13578 13579/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13580/// when possible. 13581static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13582 TargetLowering::DAGCombinerInfo &DCI, 13583 const X86Subtarget *Subtarget) { 13584 EVT VT = N->getValueType(0); 13585 if (N->getOpcode() == ISD::SHL) { 13586 SDValue V = PerformSHLCombine(N, DAG); 13587 if (V.getNode()) return V; 13588 } 13589 13590 // On X86 with SSE2 support, we can transform this to a vector shift if 13591 // all elements are shifted by the same amount. We can't do this in legalize 13592 // because the a constant vector is typically transformed to a constant pool 13593 // so we have no knowledge of the shift amount. 13594 if (!Subtarget->hasSSE2()) 13595 return SDValue(); 13596 13597 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13598 (!Subtarget->hasAVX2() || 13599 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13600 return SDValue(); 13601 13602 SDValue ShAmtOp = N->getOperand(1); 13603 EVT EltVT = VT.getVectorElementType(); 13604 DebugLoc DL = N->getDebugLoc(); 13605 SDValue BaseShAmt = SDValue(); 13606 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13607 unsigned NumElts = VT.getVectorNumElements(); 13608 unsigned i = 0; 13609 for (; i != NumElts; ++i) { 13610 SDValue Arg = ShAmtOp.getOperand(i); 13611 if (Arg.getOpcode() == ISD::UNDEF) continue; 13612 BaseShAmt = Arg; 13613 break; 13614 } 13615 // Handle the case where the build_vector is all undef 13616 // FIXME: Should DAG allow this? 13617 if (i == NumElts) 13618 return SDValue(); 13619 13620 for (; i != NumElts; ++i) { 13621 SDValue Arg = ShAmtOp.getOperand(i); 13622 if (Arg.getOpcode() == ISD::UNDEF) continue; 13623 if (Arg != BaseShAmt) { 13624 return SDValue(); 13625 } 13626 } 13627 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13628 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13629 SDValue InVec = ShAmtOp.getOperand(0); 13630 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13631 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13632 unsigned i = 0; 13633 for (; i != NumElts; ++i) { 13634 SDValue Arg = InVec.getOperand(i); 13635 if (Arg.getOpcode() == ISD::UNDEF) continue; 13636 BaseShAmt = Arg; 13637 break; 13638 } 13639 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13640 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13641 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13642 if (C->getZExtValue() == SplatIdx) 13643 BaseShAmt = InVec.getOperand(1); 13644 } 13645 } 13646 if (BaseShAmt.getNode() == 0) { 13647 // Don't create instructions with illegal types after legalize 13648 // types has run. 13649 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13650 !DCI.isBeforeLegalize()) 13651 return SDValue(); 13652 13653 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13654 DAG.getIntPtrConstant(0)); 13655 } 13656 } else 13657 return SDValue(); 13658 13659 // The shift amount is an i32. 13660 if (EltVT.bitsGT(MVT::i32)) 13661 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13662 else if (EltVT.bitsLT(MVT::i32)) 13663 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13664 13665 // The shift amount is identical so we can do a vector shift. 13666 SDValue ValOp = N->getOperand(0); 13667 switch (N->getOpcode()) { 13668 default: 13669 llvm_unreachable("Unknown shift opcode!"); 13670 case ISD::SHL: 13671 switch (VT.getSimpleVT().SimpleTy) { 13672 default: return SDValue(); 13673 case MVT::v2i64: 13674 case MVT::v4i32: 13675 case MVT::v8i16: 13676 case MVT::v4i64: 13677 case MVT::v8i32: 13678 case MVT::v16i16: 13679 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13680 } 13681 case ISD::SRA: 13682 switch (VT.getSimpleVT().SimpleTy) { 13683 default: return SDValue(); 13684 case MVT::v4i32: 13685 case MVT::v8i16: 13686 case MVT::v8i32: 13687 case MVT::v16i16: 13688 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13689 } 13690 case ISD::SRL: 13691 switch (VT.getSimpleVT().SimpleTy) { 13692 default: return SDValue(); 13693 case MVT::v2i64: 13694 case MVT::v4i32: 13695 case MVT::v8i16: 13696 case MVT::v4i64: 13697 case MVT::v8i32: 13698 case MVT::v16i16: 13699 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13700 } 13701 } 13702} 13703 13704 13705// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13706// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13707// and friends. Likewise for OR -> CMPNEQSS. 13708static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13709 TargetLowering::DAGCombinerInfo &DCI, 13710 const X86Subtarget *Subtarget) { 13711 unsigned opcode; 13712 13713 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13714 // we're requiring SSE2 for both. 13715 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13716 SDValue N0 = N->getOperand(0); 13717 SDValue N1 = N->getOperand(1); 13718 SDValue CMP0 = N0->getOperand(1); 13719 SDValue CMP1 = N1->getOperand(1); 13720 DebugLoc DL = N->getDebugLoc(); 13721 13722 // The SETCCs should both refer to the same CMP. 13723 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13724 return SDValue(); 13725 13726 SDValue CMP00 = CMP0->getOperand(0); 13727 SDValue CMP01 = CMP0->getOperand(1); 13728 EVT VT = CMP00.getValueType(); 13729 13730 if (VT == MVT::f32 || VT == MVT::f64) { 13731 bool ExpectingFlags = false; 13732 // Check for any users that want flags: 13733 for (SDNode::use_iterator UI = N->use_begin(), 13734 UE = N->use_end(); 13735 !ExpectingFlags && UI != UE; ++UI) 13736 switch (UI->getOpcode()) { 13737 default: 13738 case ISD::BR_CC: 13739 case ISD::BRCOND: 13740 case ISD::SELECT: 13741 ExpectingFlags = true; 13742 break; 13743 case ISD::CopyToReg: 13744 case ISD::SIGN_EXTEND: 13745 case ISD::ZERO_EXTEND: 13746 case ISD::ANY_EXTEND: 13747 break; 13748 } 13749 13750 if (!ExpectingFlags) { 13751 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13752 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13753 13754 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13755 X86::CondCode tmp = cc0; 13756 cc0 = cc1; 13757 cc1 = tmp; 13758 } 13759 13760 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13761 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13762 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13763 X86ISD::NodeType NTOperator = is64BitFP ? 13764 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13765 // FIXME: need symbolic constants for these magic numbers. 13766 // See X86ATTInstPrinter.cpp:printSSECC(). 13767 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13768 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13769 DAG.getConstant(x86cc, MVT::i8)); 13770 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13771 OnesOrZeroesF); 13772 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13773 DAG.getConstant(1, MVT::i32)); 13774 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13775 return OneBitOfTruth; 13776 } 13777 } 13778 } 13779 } 13780 return SDValue(); 13781} 13782 13783/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13784/// so it can be folded inside ANDNP. 13785static bool CanFoldXORWithAllOnes(const SDNode *N) { 13786 EVT VT = N->getValueType(0); 13787 13788 // Match direct AllOnes for 128 and 256-bit vectors 13789 if (ISD::isBuildVectorAllOnes(N)) 13790 return true; 13791 13792 // Look through a bit convert. 13793 if (N->getOpcode() == ISD::BITCAST) 13794 N = N->getOperand(0).getNode(); 13795 13796 // Sometimes the operand may come from a insert_subvector building a 256-bit 13797 // allones vector 13798 if (VT.getSizeInBits() == 256 && 13799 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13800 SDValue V1 = N->getOperand(0); 13801 SDValue V2 = N->getOperand(1); 13802 13803 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13804 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13805 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13806 ISD::isBuildVectorAllOnes(V2.getNode())) 13807 return true; 13808 } 13809 13810 return false; 13811} 13812 13813static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13814 TargetLowering::DAGCombinerInfo &DCI, 13815 const X86Subtarget *Subtarget) { 13816 if (DCI.isBeforeLegalizeOps()) 13817 return SDValue(); 13818 13819 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13820 if (R.getNode()) 13821 return R; 13822 13823 EVT VT = N->getValueType(0); 13824 13825 // Create ANDN, BLSI, and BLSR instructions 13826 // BLSI is X & (-X) 13827 // BLSR is X & (X-1) 13828 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13829 SDValue N0 = N->getOperand(0); 13830 SDValue N1 = N->getOperand(1); 13831 DebugLoc DL = N->getDebugLoc(); 13832 13833 // Check LHS for not 13834 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13835 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13836 // Check RHS for not 13837 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13838 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13839 13840 // Check LHS for neg 13841 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13842 isZero(N0.getOperand(0))) 13843 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13844 13845 // Check RHS for neg 13846 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13847 isZero(N1.getOperand(0))) 13848 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13849 13850 // Check LHS for X-1 13851 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13852 isAllOnes(N0.getOperand(1))) 13853 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13854 13855 // Check RHS for X-1 13856 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13857 isAllOnes(N1.getOperand(1))) 13858 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13859 13860 return SDValue(); 13861 } 13862 13863 // Want to form ANDNP nodes: 13864 // 1) In the hopes of then easily combining them with OR and AND nodes 13865 // to form PBLEND/PSIGN. 13866 // 2) To match ANDN packed intrinsics 13867 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13868 return SDValue(); 13869 13870 SDValue N0 = N->getOperand(0); 13871 SDValue N1 = N->getOperand(1); 13872 DebugLoc DL = N->getDebugLoc(); 13873 13874 // Check LHS for vnot 13875 if (N0.getOpcode() == ISD::XOR && 13876 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13877 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13878 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13879 13880 // Check RHS for vnot 13881 if (N1.getOpcode() == ISD::XOR && 13882 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13883 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13884 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13885 13886 return SDValue(); 13887} 13888 13889static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13890 TargetLowering::DAGCombinerInfo &DCI, 13891 const X86Subtarget *Subtarget) { 13892 if (DCI.isBeforeLegalizeOps()) 13893 return SDValue(); 13894 13895 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13896 if (R.getNode()) 13897 return R; 13898 13899 EVT VT = N->getValueType(0); 13900 13901 SDValue N0 = N->getOperand(0); 13902 SDValue N1 = N->getOperand(1); 13903 13904 // look for psign/blend 13905 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13906 if (!Subtarget->hasSSSE3() || 13907 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13908 return SDValue(); 13909 13910 // Canonicalize pandn to RHS 13911 if (N0.getOpcode() == X86ISD::ANDNP) 13912 std::swap(N0, N1); 13913 // or (and (m, y), (pandn m, x)) 13914 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13915 SDValue Mask = N1.getOperand(0); 13916 SDValue X = N1.getOperand(1); 13917 SDValue Y; 13918 if (N0.getOperand(0) == Mask) 13919 Y = N0.getOperand(1); 13920 if (N0.getOperand(1) == Mask) 13921 Y = N0.getOperand(0); 13922 13923 // Check to see if the mask appeared in both the AND and ANDNP and 13924 if (!Y.getNode()) 13925 return SDValue(); 13926 13927 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13928 if (Mask.getOpcode() != ISD::BITCAST || 13929 X.getOpcode() != ISD::BITCAST || 13930 Y.getOpcode() != ISD::BITCAST) 13931 return SDValue(); 13932 13933 // Look through mask bitcast. 13934 Mask = Mask.getOperand(0); 13935 EVT MaskVT = Mask.getValueType(); 13936 13937 // Validate that the Mask operand is a vector sra node. 13938 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13939 // there is no psrai.b 13940 if (Mask.getOpcode() != X86ISD::VSRAI) 13941 return SDValue(); 13942 13943 // Check that the SRA is all signbits. 13944 SDValue SraC = Mask.getOperand(1); 13945 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13946 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13947 if ((SraAmt + 1) != EltBits) 13948 return SDValue(); 13949 13950 DebugLoc DL = N->getDebugLoc(); 13951 13952 // Now we know we at least have a plendvb with the mask val. See if 13953 // we can form a psignb/w/d. 13954 // psign = x.type == y.type == mask.type && y = sub(0, x); 13955 X = X.getOperand(0); 13956 Y = Y.getOperand(0); 13957 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13958 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13959 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 13960 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 13961 "Unsupported VT for PSIGN"); 13962 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 13963 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13964 } 13965 // PBLENDVB only available on SSE 4.1 13966 if (!Subtarget->hasSSE41()) 13967 return SDValue(); 13968 13969 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 13970 13971 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 13972 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 13973 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 13974 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 13975 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13976 } 13977 } 13978 13979 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 13980 return SDValue(); 13981 13982 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13983 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13984 std::swap(N0, N1); 13985 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13986 return SDValue(); 13987 if (!N0.hasOneUse() || !N1.hasOneUse()) 13988 return SDValue(); 13989 13990 SDValue ShAmt0 = N0.getOperand(1); 13991 if (ShAmt0.getValueType() != MVT::i8) 13992 return SDValue(); 13993 SDValue ShAmt1 = N1.getOperand(1); 13994 if (ShAmt1.getValueType() != MVT::i8) 13995 return SDValue(); 13996 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13997 ShAmt0 = ShAmt0.getOperand(0); 13998 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13999 ShAmt1 = ShAmt1.getOperand(0); 14000 14001 DebugLoc DL = N->getDebugLoc(); 14002 unsigned Opc = X86ISD::SHLD; 14003 SDValue Op0 = N0.getOperand(0); 14004 SDValue Op1 = N1.getOperand(0); 14005 if (ShAmt0.getOpcode() == ISD::SUB) { 14006 Opc = X86ISD::SHRD; 14007 std::swap(Op0, Op1); 14008 std::swap(ShAmt0, ShAmt1); 14009 } 14010 14011 unsigned Bits = VT.getSizeInBits(); 14012 if (ShAmt1.getOpcode() == ISD::SUB) { 14013 SDValue Sum = ShAmt1.getOperand(0); 14014 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14015 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14016 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14017 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14018 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14019 return DAG.getNode(Opc, DL, VT, 14020 Op0, Op1, 14021 DAG.getNode(ISD::TRUNCATE, DL, 14022 MVT::i8, ShAmt0)); 14023 } 14024 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14025 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14026 if (ShAmt0C && 14027 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14028 return DAG.getNode(Opc, DL, VT, 14029 N0.getOperand(0), N1.getOperand(0), 14030 DAG.getNode(ISD::TRUNCATE, DL, 14031 MVT::i8, ShAmt0)); 14032 } 14033 14034 return SDValue(); 14035} 14036 14037// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14038static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14039 TargetLowering::DAGCombinerInfo &DCI, 14040 const X86Subtarget *Subtarget) { 14041 if (DCI.isBeforeLegalizeOps()) 14042 return SDValue(); 14043 14044 EVT VT = N->getValueType(0); 14045 14046 if (VT != MVT::i32 && VT != MVT::i64) 14047 return SDValue(); 14048 14049 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14050 14051 // Create BLSMSK instructions by finding X ^ (X-1) 14052 SDValue N0 = N->getOperand(0); 14053 SDValue N1 = N->getOperand(1); 14054 DebugLoc DL = N->getDebugLoc(); 14055 14056 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14057 isAllOnes(N0.getOperand(1))) 14058 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14059 14060 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14061 isAllOnes(N1.getOperand(1))) 14062 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14063 14064 return SDValue(); 14065} 14066 14067/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14068static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14069 const X86Subtarget *Subtarget) { 14070 LoadSDNode *Ld = cast<LoadSDNode>(N); 14071 EVT RegVT = Ld->getValueType(0); 14072 EVT MemVT = Ld->getMemoryVT(); 14073 DebugLoc dl = Ld->getDebugLoc(); 14074 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14075 14076 ISD::LoadExtType Ext = Ld->getExtensionType(); 14077 14078 // If this is a vector EXT Load then attempt to optimize it using a 14079 // shuffle. We need SSE4 for the shuffles. 14080 // TODO: It is possible to support ZExt by zeroing the undef values 14081 // during the shuffle phase or after the shuffle. 14082 if (RegVT.isVector() && RegVT.isInteger() && 14083 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14084 assert(MemVT != RegVT && "Cannot extend to the same type"); 14085 assert(MemVT.isVector() && "Must load a vector from memory"); 14086 14087 unsigned NumElems = RegVT.getVectorNumElements(); 14088 unsigned RegSz = RegVT.getSizeInBits(); 14089 unsigned MemSz = MemVT.getSizeInBits(); 14090 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14091 // All sizes must be a power of two 14092 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14093 14094 // Attempt to load the original value using a single load op. 14095 // Find a scalar type which is equal to the loaded word size. 14096 MVT SclrLoadTy = MVT::i8; 14097 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14098 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14099 MVT Tp = (MVT::SimpleValueType)tp; 14100 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14101 SclrLoadTy = Tp; 14102 break; 14103 } 14104 } 14105 14106 // Proceed if a load word is found. 14107 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14108 14109 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14110 RegSz/SclrLoadTy.getSizeInBits()); 14111 14112 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14113 RegSz/MemVT.getScalarType().getSizeInBits()); 14114 // Can't shuffle using an illegal type. 14115 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14116 14117 // Perform a single load. 14118 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14119 Ld->getBasePtr(), 14120 Ld->getPointerInfo(), Ld->isVolatile(), 14121 Ld->isNonTemporal(), Ld->isInvariant(), 14122 Ld->getAlignment()); 14123 14124 // Insert the word loaded into a vector. 14125 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14126 LoadUnitVecVT, ScalarLoad); 14127 14128 // Bitcast the loaded value to a vector of the original element type, in 14129 // the size of the target vector type. 14130 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14131 ScalarInVector); 14132 unsigned SizeRatio = RegSz/MemSz; 14133 14134 // Redistribute the loaded elements into the different locations. 14135 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14136 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14137 14138 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14139 DAG.getUNDEF(SlicedVec.getValueType()), 14140 ShuffleVec.data()); 14141 14142 // Bitcast to the requested type. 14143 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14144 // Replace the original load with the new sequence 14145 // and return the new chain. 14146 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14147 return SDValue(ScalarLoad.getNode(), 1); 14148 } 14149 14150 return SDValue(); 14151} 14152 14153/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14154static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14155 const X86Subtarget *Subtarget) { 14156 StoreSDNode *St = cast<StoreSDNode>(N); 14157 EVT VT = St->getValue().getValueType(); 14158 EVT StVT = St->getMemoryVT(); 14159 DebugLoc dl = St->getDebugLoc(); 14160 SDValue StoredVal = St->getOperand(1); 14161 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14162 14163 // If we are saving a concatenation of two XMM registers, perform two stores. 14164 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14165 // 128-bit ones. If in the future the cost becomes only one memory access the 14166 // first version would be better. 14167 if (VT.getSizeInBits() == 256 && 14168 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14169 StoredVal.getNumOperands() == 2) { 14170 14171 SDValue Value0 = StoredVal.getOperand(0); 14172 SDValue Value1 = StoredVal.getOperand(1); 14173 14174 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14175 SDValue Ptr0 = St->getBasePtr(); 14176 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14177 14178 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14179 St->getPointerInfo(), St->isVolatile(), 14180 St->isNonTemporal(), St->getAlignment()); 14181 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14182 St->getPointerInfo(), St->isVolatile(), 14183 St->isNonTemporal(), St->getAlignment()); 14184 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14185 } 14186 14187 // Optimize trunc store (of multiple scalars) to shuffle and store. 14188 // First, pack all of the elements in one place. Next, store to memory 14189 // in fewer chunks. 14190 if (St->isTruncatingStore() && VT.isVector()) { 14191 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14192 unsigned NumElems = VT.getVectorNumElements(); 14193 assert(StVT != VT && "Cannot truncate to the same type"); 14194 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14195 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14196 14197 // From, To sizes and ElemCount must be pow of two 14198 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14199 // We are going to use the original vector elt for storing. 14200 // Accumulated smaller vector elements must be a multiple of the store size. 14201 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14202 14203 unsigned SizeRatio = FromSz / ToSz; 14204 14205 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14206 14207 // Create a type on which we perform the shuffle 14208 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14209 StVT.getScalarType(), NumElems*SizeRatio); 14210 14211 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14212 14213 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14214 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14215 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14216 14217 // Can't shuffle using an illegal type 14218 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14219 14220 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14221 DAG.getUNDEF(WideVec.getValueType()), 14222 ShuffleVec.data()); 14223 // At this point all of the data is stored at the bottom of the 14224 // register. We now need to save it to mem. 14225 14226 // Find the largest store unit 14227 MVT StoreType = MVT::i8; 14228 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14229 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14230 MVT Tp = (MVT::SimpleValueType)tp; 14231 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14232 StoreType = Tp; 14233 } 14234 14235 // Bitcast the original vector into a vector of store-size units 14236 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14237 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14238 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14239 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14240 SmallVector<SDValue, 8> Chains; 14241 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14242 TLI.getPointerTy()); 14243 SDValue Ptr = St->getBasePtr(); 14244 14245 // Perform one or more big stores into memory. 14246 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14247 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14248 StoreType, ShuffWide, 14249 DAG.getIntPtrConstant(i)); 14250 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14251 St->getPointerInfo(), St->isVolatile(), 14252 St->isNonTemporal(), St->getAlignment()); 14253 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14254 Chains.push_back(Ch); 14255 } 14256 14257 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14258 Chains.size()); 14259 } 14260 14261 14262 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14263 // the FP state in cases where an emms may be missing. 14264 // A preferable solution to the general problem is to figure out the right 14265 // places to insert EMMS. This qualifies as a quick hack. 14266 14267 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14268 if (VT.getSizeInBits() != 64) 14269 return SDValue(); 14270 14271 const Function *F = DAG.getMachineFunction().getFunction(); 14272 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14273 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14274 && Subtarget->hasSSE2(); 14275 if ((VT.isVector() || 14276 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14277 isa<LoadSDNode>(St->getValue()) && 14278 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14279 St->getChain().hasOneUse() && !St->isVolatile()) { 14280 SDNode* LdVal = St->getValue().getNode(); 14281 LoadSDNode *Ld = 0; 14282 int TokenFactorIndex = -1; 14283 SmallVector<SDValue, 8> Ops; 14284 SDNode* ChainVal = St->getChain().getNode(); 14285 // Must be a store of a load. We currently handle two cases: the load 14286 // is a direct child, and it's under an intervening TokenFactor. It is 14287 // possible to dig deeper under nested TokenFactors. 14288 if (ChainVal == LdVal) 14289 Ld = cast<LoadSDNode>(St->getChain()); 14290 else if (St->getValue().hasOneUse() && 14291 ChainVal->getOpcode() == ISD::TokenFactor) { 14292 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14293 if (ChainVal->getOperand(i).getNode() == LdVal) { 14294 TokenFactorIndex = i; 14295 Ld = cast<LoadSDNode>(St->getValue()); 14296 } else 14297 Ops.push_back(ChainVal->getOperand(i)); 14298 } 14299 } 14300 14301 if (!Ld || !ISD::isNormalLoad(Ld)) 14302 return SDValue(); 14303 14304 // If this is not the MMX case, i.e. we are just turning i64 load/store 14305 // into f64 load/store, avoid the transformation if there are multiple 14306 // uses of the loaded value. 14307 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14308 return SDValue(); 14309 14310 DebugLoc LdDL = Ld->getDebugLoc(); 14311 DebugLoc StDL = N->getDebugLoc(); 14312 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14313 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14314 // pair instead. 14315 if (Subtarget->is64Bit() || F64IsLegal) { 14316 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14317 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14318 Ld->getPointerInfo(), Ld->isVolatile(), 14319 Ld->isNonTemporal(), Ld->isInvariant(), 14320 Ld->getAlignment()); 14321 SDValue NewChain = NewLd.getValue(1); 14322 if (TokenFactorIndex != -1) { 14323 Ops.push_back(NewChain); 14324 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14325 Ops.size()); 14326 } 14327 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14328 St->getPointerInfo(), 14329 St->isVolatile(), St->isNonTemporal(), 14330 St->getAlignment()); 14331 } 14332 14333 // Otherwise, lower to two pairs of 32-bit loads / stores. 14334 SDValue LoAddr = Ld->getBasePtr(); 14335 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14336 DAG.getConstant(4, MVT::i32)); 14337 14338 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14339 Ld->getPointerInfo(), 14340 Ld->isVolatile(), Ld->isNonTemporal(), 14341 Ld->isInvariant(), Ld->getAlignment()); 14342 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14343 Ld->getPointerInfo().getWithOffset(4), 14344 Ld->isVolatile(), Ld->isNonTemporal(), 14345 Ld->isInvariant(), 14346 MinAlign(Ld->getAlignment(), 4)); 14347 14348 SDValue NewChain = LoLd.getValue(1); 14349 if (TokenFactorIndex != -1) { 14350 Ops.push_back(LoLd); 14351 Ops.push_back(HiLd); 14352 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14353 Ops.size()); 14354 } 14355 14356 LoAddr = St->getBasePtr(); 14357 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14358 DAG.getConstant(4, MVT::i32)); 14359 14360 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14361 St->getPointerInfo(), 14362 St->isVolatile(), St->isNonTemporal(), 14363 St->getAlignment()); 14364 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14365 St->getPointerInfo().getWithOffset(4), 14366 St->isVolatile(), 14367 St->isNonTemporal(), 14368 MinAlign(St->getAlignment(), 4)); 14369 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14370 } 14371 return SDValue(); 14372} 14373 14374/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14375/// and return the operands for the horizontal operation in LHS and RHS. A 14376/// horizontal operation performs the binary operation on successive elements 14377/// of its first operand, then on successive elements of its second operand, 14378/// returning the resulting values in a vector. For example, if 14379/// A = < float a0, float a1, float a2, float a3 > 14380/// and 14381/// B = < float b0, float b1, float b2, float b3 > 14382/// then the result of doing a horizontal operation on A and B is 14383/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14384/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14385/// A horizontal-op B, for some already available A and B, and if so then LHS is 14386/// set to A, RHS to B, and the routine returns 'true'. 14387/// Note that the binary operation should have the property that if one of the 14388/// operands is UNDEF then the result is UNDEF. 14389static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14390 // Look for the following pattern: if 14391 // A = < float a0, float a1, float a2, float a3 > 14392 // B = < float b0, float b1, float b2, float b3 > 14393 // and 14394 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14395 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14396 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14397 // which is A horizontal-op B. 14398 14399 // At least one of the operands should be a vector shuffle. 14400 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14401 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14402 return false; 14403 14404 EVT VT = LHS.getValueType(); 14405 14406 assert((VT.is128BitVector() || VT.is256BitVector()) && 14407 "Unsupported vector type for horizontal add/sub"); 14408 14409 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14410 // operate independently on 128-bit lanes. 14411 unsigned NumElts = VT.getVectorNumElements(); 14412 unsigned NumLanes = VT.getSizeInBits()/128; 14413 unsigned NumLaneElts = NumElts / NumLanes; 14414 assert((NumLaneElts % 2 == 0) && 14415 "Vector type should have an even number of elements in each lane"); 14416 unsigned HalfLaneElts = NumLaneElts/2; 14417 14418 // View LHS in the form 14419 // LHS = VECTOR_SHUFFLE A, B, LMask 14420 // If LHS is not a shuffle then pretend it is the shuffle 14421 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14422 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14423 // type VT. 14424 SDValue A, B; 14425 SmallVector<int, 16> LMask(NumElts); 14426 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14427 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14428 A = LHS.getOperand(0); 14429 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14430 B = LHS.getOperand(1); 14431 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14432 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14433 } else { 14434 if (LHS.getOpcode() != ISD::UNDEF) 14435 A = LHS; 14436 for (unsigned i = 0; i != NumElts; ++i) 14437 LMask[i] = i; 14438 } 14439 14440 // Likewise, view RHS in the form 14441 // RHS = VECTOR_SHUFFLE C, D, RMask 14442 SDValue C, D; 14443 SmallVector<int, 16> RMask(NumElts); 14444 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14445 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14446 C = RHS.getOperand(0); 14447 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14448 D = RHS.getOperand(1); 14449 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14450 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14451 } else { 14452 if (RHS.getOpcode() != ISD::UNDEF) 14453 C = RHS; 14454 for (unsigned i = 0; i != NumElts; ++i) 14455 RMask[i] = i; 14456 } 14457 14458 // Check that the shuffles are both shuffling the same vectors. 14459 if (!(A == C && B == D) && !(A == D && B == C)) 14460 return false; 14461 14462 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14463 if (!A.getNode() && !B.getNode()) 14464 return false; 14465 14466 // If A and B occur in reverse order in RHS, then "swap" them (which means 14467 // rewriting the mask). 14468 if (A != C) 14469 CommuteVectorShuffleMask(RMask, NumElts); 14470 14471 // At this point LHS and RHS are equivalent to 14472 // LHS = VECTOR_SHUFFLE A, B, LMask 14473 // RHS = VECTOR_SHUFFLE A, B, RMask 14474 // Check that the masks correspond to performing a horizontal operation. 14475 for (unsigned i = 0; i != NumElts; ++i) { 14476 int LIdx = LMask[i], RIdx = RMask[i]; 14477 14478 // Ignore any UNDEF components. 14479 if (LIdx < 0 || RIdx < 0 || 14480 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14481 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14482 continue; 14483 14484 // Check that successive elements are being operated on. If not, this is 14485 // not a horizontal operation. 14486 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14487 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14488 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14489 if (!(LIdx == Index && RIdx == Index + 1) && 14490 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14491 return false; 14492 } 14493 14494 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14495 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14496 return true; 14497} 14498 14499/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14500static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14501 const X86Subtarget *Subtarget) { 14502 EVT VT = N->getValueType(0); 14503 SDValue LHS = N->getOperand(0); 14504 SDValue RHS = N->getOperand(1); 14505 14506 // Try to synthesize horizontal adds from adds of shuffles. 14507 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14508 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14509 isHorizontalBinOp(LHS, RHS, true)) 14510 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14511 return SDValue(); 14512} 14513 14514/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14515static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14516 const X86Subtarget *Subtarget) { 14517 EVT VT = N->getValueType(0); 14518 SDValue LHS = N->getOperand(0); 14519 SDValue RHS = N->getOperand(1); 14520 14521 // Try to synthesize horizontal subs from subs of shuffles. 14522 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14523 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14524 isHorizontalBinOp(LHS, RHS, false)) 14525 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14526 return SDValue(); 14527} 14528 14529/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14530/// X86ISD::FXOR nodes. 14531static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14532 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14533 // F[X]OR(0.0, x) -> x 14534 // F[X]OR(x, 0.0) -> x 14535 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14536 if (C->getValueAPF().isPosZero()) 14537 return N->getOperand(1); 14538 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14539 if (C->getValueAPF().isPosZero()) 14540 return N->getOperand(0); 14541 return SDValue(); 14542} 14543 14544/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14545static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14546 // FAND(0.0, x) -> 0.0 14547 // FAND(x, 0.0) -> 0.0 14548 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14549 if (C->getValueAPF().isPosZero()) 14550 return N->getOperand(0); 14551 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14552 if (C->getValueAPF().isPosZero()) 14553 return N->getOperand(1); 14554 return SDValue(); 14555} 14556 14557static SDValue PerformBTCombine(SDNode *N, 14558 SelectionDAG &DAG, 14559 TargetLowering::DAGCombinerInfo &DCI) { 14560 // BT ignores high bits in the bit index operand. 14561 SDValue Op1 = N->getOperand(1); 14562 if (Op1.hasOneUse()) { 14563 unsigned BitWidth = Op1.getValueSizeInBits(); 14564 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14565 APInt KnownZero, KnownOne; 14566 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14567 !DCI.isBeforeLegalizeOps()); 14568 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14569 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14570 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14571 DCI.CommitTargetLoweringOpt(TLO); 14572 } 14573 return SDValue(); 14574} 14575 14576static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14577 SDValue Op = N->getOperand(0); 14578 if (Op.getOpcode() == ISD::BITCAST) 14579 Op = Op.getOperand(0); 14580 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14581 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14582 VT.getVectorElementType().getSizeInBits() == 14583 OpVT.getVectorElementType().getSizeInBits()) { 14584 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14585 } 14586 return SDValue(); 14587} 14588 14589static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14590 TargetLowering::DAGCombinerInfo &DCI, 14591 const X86Subtarget *Subtarget) { 14592 if (!DCI.isBeforeLegalizeOps()) 14593 return SDValue(); 14594 14595 if (!Subtarget->hasAVX()) return SDValue(); 14596 14597 // Optimize vectors in AVX mode 14598 // Sign extend v8i16 to v8i32 and 14599 // v4i32 to v4i64 14600 // 14601 // Divide input vector into two parts 14602 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14603 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14604 // concat the vectors to original VT 14605 14606 EVT VT = N->getValueType(0); 14607 SDValue Op = N->getOperand(0); 14608 EVT OpVT = Op.getValueType(); 14609 DebugLoc dl = N->getDebugLoc(); 14610 14611 if (((VT == MVT::v4i64) && (OpVT == MVT::v4i32)) || 14612 ((VT == MVT::v8i32) && (OpVT == MVT::v8i16))) { 14613 14614 unsigned NumElems = OpVT.getVectorNumElements(); 14615 SmallVector<int,8> ShufMask1(NumElems, -1); 14616 for (unsigned i=0; i< NumElems/2; i++) ShufMask1[i] = i; 14617 14618 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14619 ShufMask1.data()); 14620 14621 SmallVector<int,8> ShufMask2(NumElems, -1); 14622 for (unsigned i=0; i< NumElems/2; i++) ShufMask2[i] = i+NumElems/2; 14623 14624 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14625 ShufMask2.data()); 14626 14627 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14628 VT.getVectorNumElements()/2); 14629 14630 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14631 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14632 14633 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14634 } 14635 return SDValue(); 14636} 14637 14638static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14639 const X86Subtarget *Subtarget) { 14640 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14641 // (and (i32 x86isd::setcc_carry), 1) 14642 // This eliminates the zext. This transformation is necessary because 14643 // ISD::SETCC is always legalized to i8. 14644 DebugLoc dl = N->getDebugLoc(); 14645 SDValue N0 = N->getOperand(0); 14646 EVT VT = N->getValueType(0); 14647 EVT OpVT = N0.getValueType(); 14648 14649 if (N0.getOpcode() == ISD::AND && 14650 N0.hasOneUse() && 14651 N0.getOperand(0).hasOneUse()) { 14652 SDValue N00 = N0.getOperand(0); 14653 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14654 return SDValue(); 14655 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14656 if (!C || C->getZExtValue() != 1) 14657 return SDValue(); 14658 return DAG.getNode(ISD::AND, dl, VT, 14659 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14660 N00.getOperand(0), N00.getOperand(1)), 14661 DAG.getConstant(1, VT)); 14662 } 14663 // Optimize vectors in AVX mode: 14664 // 14665 // v8i16 -> v8i32 14666 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14667 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14668 // Concat upper and lower parts. 14669 // 14670 // v4i32 -> v4i64 14671 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14672 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14673 // Concat upper and lower parts. 14674 // 14675 if (Subtarget->hasAVX()) { 14676 14677 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14678 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14679 14680 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14681 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG); 14682 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG); 14683 14684 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14685 VT.getVectorNumElements()/2); 14686 14687 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14688 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14689 14690 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14691 } 14692 } 14693 14694 14695 return SDValue(); 14696} 14697 14698// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14699static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14700 unsigned X86CC = N->getConstantOperandVal(0); 14701 SDValue EFLAG = N->getOperand(1); 14702 DebugLoc DL = N->getDebugLoc(); 14703 14704 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14705 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14706 // cases. 14707 if (X86CC == X86::COND_B) 14708 return DAG.getNode(ISD::AND, DL, MVT::i8, 14709 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14710 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14711 DAG.getConstant(1, MVT::i8)); 14712 14713 return SDValue(); 14714} 14715 14716static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14717 const X86TargetLowering *XTLI) { 14718 SDValue Op0 = N->getOperand(0); 14719 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14720 // a 32-bit target where SSE doesn't support i64->FP operations. 14721 if (Op0.getOpcode() == ISD::LOAD) { 14722 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14723 EVT VT = Ld->getValueType(0); 14724 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14725 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14726 !XTLI->getSubtarget()->is64Bit() && 14727 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14728 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14729 Ld->getChain(), Op0, DAG); 14730 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14731 return FILDChain; 14732 } 14733 } 14734 return SDValue(); 14735} 14736 14737// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14738static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14739 X86TargetLowering::DAGCombinerInfo &DCI) { 14740 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14741 // the result is either zero or one (depending on the input carry bit). 14742 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14743 if (X86::isZeroNode(N->getOperand(0)) && 14744 X86::isZeroNode(N->getOperand(1)) && 14745 // We don't have a good way to replace an EFLAGS use, so only do this when 14746 // dead right now. 14747 SDValue(N, 1).use_empty()) { 14748 DebugLoc DL = N->getDebugLoc(); 14749 EVT VT = N->getValueType(0); 14750 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14751 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14752 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14753 DAG.getConstant(X86::COND_B,MVT::i8), 14754 N->getOperand(2)), 14755 DAG.getConstant(1, VT)); 14756 return DCI.CombineTo(N, Res1, CarryOut); 14757 } 14758 14759 return SDValue(); 14760} 14761 14762// fold (add Y, (sete X, 0)) -> adc 0, Y 14763// (add Y, (setne X, 0)) -> sbb -1, Y 14764// (sub (sete X, 0), Y) -> sbb 0, Y 14765// (sub (setne X, 0), Y) -> adc -1, Y 14766static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14767 DebugLoc DL = N->getDebugLoc(); 14768 14769 // Look through ZExts. 14770 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14771 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14772 return SDValue(); 14773 14774 SDValue SetCC = Ext.getOperand(0); 14775 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14776 return SDValue(); 14777 14778 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14779 if (CC != X86::COND_E && CC != X86::COND_NE) 14780 return SDValue(); 14781 14782 SDValue Cmp = SetCC.getOperand(1); 14783 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14784 !X86::isZeroNode(Cmp.getOperand(1)) || 14785 !Cmp.getOperand(0).getValueType().isInteger()) 14786 return SDValue(); 14787 14788 SDValue CmpOp0 = Cmp.getOperand(0); 14789 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14790 DAG.getConstant(1, CmpOp0.getValueType())); 14791 14792 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14793 if (CC == X86::COND_NE) 14794 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14795 DL, OtherVal.getValueType(), OtherVal, 14796 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14797 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14798 DL, OtherVal.getValueType(), OtherVal, 14799 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14800} 14801 14802/// PerformADDCombine - Do target-specific dag combines on integer adds. 14803static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14804 const X86Subtarget *Subtarget) { 14805 EVT VT = N->getValueType(0); 14806 SDValue Op0 = N->getOperand(0); 14807 SDValue Op1 = N->getOperand(1); 14808 14809 // Try to synthesize horizontal adds from adds of shuffles. 14810 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14811 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14812 isHorizontalBinOp(Op0, Op1, true)) 14813 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14814 14815 return OptimizeConditionalInDecrement(N, DAG); 14816} 14817 14818static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14819 const X86Subtarget *Subtarget) { 14820 SDValue Op0 = N->getOperand(0); 14821 SDValue Op1 = N->getOperand(1); 14822 14823 // X86 can't encode an immediate LHS of a sub. See if we can push the 14824 // negation into a preceding instruction. 14825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14826 // If the RHS of the sub is a XOR with one use and a constant, invert the 14827 // immediate. Then add one to the LHS of the sub so we can turn 14828 // X-Y -> X+~Y+1, saving one register. 14829 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14830 isa<ConstantSDNode>(Op1.getOperand(1))) { 14831 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14832 EVT VT = Op0.getValueType(); 14833 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14834 Op1.getOperand(0), 14835 DAG.getConstant(~XorC, VT)); 14836 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14837 DAG.getConstant(C->getAPIntValue()+1, VT)); 14838 } 14839 } 14840 14841 // Try to synthesize horizontal adds from adds of shuffles. 14842 EVT VT = N->getValueType(0); 14843 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14844 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14845 isHorizontalBinOp(Op0, Op1, true)) 14846 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14847 14848 return OptimizeConditionalInDecrement(N, DAG); 14849} 14850 14851SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14852 DAGCombinerInfo &DCI) const { 14853 SelectionDAG &DAG = DCI.DAG; 14854 switch (N->getOpcode()) { 14855 default: break; 14856 case ISD::EXTRACT_VECTOR_ELT: 14857 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14858 case ISD::VSELECT: 14859 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 14860 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14861 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14862 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14863 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14864 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14865 case ISD::SHL: 14866 case ISD::SRA: 14867 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 14868 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14869 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14870 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14871 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14872 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14873 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14874 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14875 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14876 case X86ISD::FXOR: 14877 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14878 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14879 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14880 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14881 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget); 14882 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 14883 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 14884 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14885 case X86ISD::SHUFP: // Handle all target specific shuffles 14886 case X86ISD::PALIGN: 14887 case X86ISD::UNPCKH: 14888 case X86ISD::UNPCKL: 14889 case X86ISD::MOVHLPS: 14890 case X86ISD::MOVLHPS: 14891 case X86ISD::PSHUFD: 14892 case X86ISD::PSHUFHW: 14893 case X86ISD::PSHUFLW: 14894 case X86ISD::MOVSS: 14895 case X86ISD::MOVSD: 14896 case X86ISD::VPERMILP: 14897 case X86ISD::VPERM2X128: 14898 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14899 } 14900 14901 return SDValue(); 14902} 14903 14904/// isTypeDesirableForOp - Return true if the target has native support for 14905/// the specified value type and it is 'desirable' to use the type for the 14906/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14907/// instruction encodings are longer and some i16 instructions are slow. 14908bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14909 if (!isTypeLegal(VT)) 14910 return false; 14911 if (VT != MVT::i16) 14912 return true; 14913 14914 switch (Opc) { 14915 default: 14916 return true; 14917 case ISD::LOAD: 14918 case ISD::SIGN_EXTEND: 14919 case ISD::ZERO_EXTEND: 14920 case ISD::ANY_EXTEND: 14921 case ISD::SHL: 14922 case ISD::SRL: 14923 case ISD::SUB: 14924 case ISD::ADD: 14925 case ISD::MUL: 14926 case ISD::AND: 14927 case ISD::OR: 14928 case ISD::XOR: 14929 return false; 14930 } 14931} 14932 14933/// IsDesirableToPromoteOp - This method query the target whether it is 14934/// beneficial for dag combiner to promote the specified node. If true, it 14935/// should return the desired promotion type by reference. 14936bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14937 EVT VT = Op.getValueType(); 14938 if (VT != MVT::i16) 14939 return false; 14940 14941 bool Promote = false; 14942 bool Commute = false; 14943 switch (Op.getOpcode()) { 14944 default: break; 14945 case ISD::LOAD: { 14946 LoadSDNode *LD = cast<LoadSDNode>(Op); 14947 // If the non-extending load has a single use and it's not live out, then it 14948 // might be folded. 14949 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14950 Op.hasOneUse()*/) { 14951 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14952 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14953 // The only case where we'd want to promote LOAD (rather then it being 14954 // promoted as an operand is when it's only use is liveout. 14955 if (UI->getOpcode() != ISD::CopyToReg) 14956 return false; 14957 } 14958 } 14959 Promote = true; 14960 break; 14961 } 14962 case ISD::SIGN_EXTEND: 14963 case ISD::ZERO_EXTEND: 14964 case ISD::ANY_EXTEND: 14965 Promote = true; 14966 break; 14967 case ISD::SHL: 14968 case ISD::SRL: { 14969 SDValue N0 = Op.getOperand(0); 14970 // Look out for (store (shl (load), x)). 14971 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14972 return false; 14973 Promote = true; 14974 break; 14975 } 14976 case ISD::ADD: 14977 case ISD::MUL: 14978 case ISD::AND: 14979 case ISD::OR: 14980 case ISD::XOR: 14981 Commute = true; 14982 // fallthrough 14983 case ISD::SUB: { 14984 SDValue N0 = Op.getOperand(0); 14985 SDValue N1 = Op.getOperand(1); 14986 if (!Commute && MayFoldLoad(N1)) 14987 return false; 14988 // Avoid disabling potential load folding opportunities. 14989 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14990 return false; 14991 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14992 return false; 14993 Promote = true; 14994 } 14995 } 14996 14997 PVT = MVT::i32; 14998 return Promote; 14999} 15000 15001//===----------------------------------------------------------------------===// 15002// X86 Inline Assembly Support 15003//===----------------------------------------------------------------------===// 15004 15005namespace { 15006 // Helper to match a string separated by whitespace. 15007 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15008 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15009 15010 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15011 StringRef piece(*args[i]); 15012 if (!s.startswith(piece)) // Check if the piece matches. 15013 return false; 15014 15015 s = s.substr(piece.size()); 15016 StringRef::size_type pos = s.find_first_not_of(" \t"); 15017 if (pos == 0) // We matched a prefix. 15018 return false; 15019 15020 s = s.substr(pos); 15021 } 15022 15023 return s.empty(); 15024 } 15025 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15026} 15027 15028bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15029 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15030 15031 std::string AsmStr = IA->getAsmString(); 15032 15033 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15034 if (!Ty || Ty->getBitWidth() % 16 != 0) 15035 return false; 15036 15037 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15038 SmallVector<StringRef, 4> AsmPieces; 15039 SplitString(AsmStr, AsmPieces, ";\n"); 15040 15041 switch (AsmPieces.size()) { 15042 default: return false; 15043 case 1: 15044 // FIXME: this should verify that we are targeting a 486 or better. If not, 15045 // we will turn this bswap into something that will be lowered to logical 15046 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15047 // lower so don't worry about this. 15048 // bswap $0 15049 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15050 matchAsm(AsmPieces[0], "bswapl", "$0") || 15051 matchAsm(AsmPieces[0], "bswapq", "$0") || 15052 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15053 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15054 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15055 // No need to check constraints, nothing other than the equivalent of 15056 // "=r,0" would be valid here. 15057 return IntrinsicLowering::LowerToByteSwap(CI); 15058 } 15059 15060 // rorw $$8, ${0:w} --> llvm.bswap.i16 15061 if (CI->getType()->isIntegerTy(16) && 15062 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15063 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15064 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15065 AsmPieces.clear(); 15066 const std::string &ConstraintsStr = IA->getConstraintString(); 15067 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15068 std::sort(AsmPieces.begin(), AsmPieces.end()); 15069 if (AsmPieces.size() == 4 && 15070 AsmPieces[0] == "~{cc}" && 15071 AsmPieces[1] == "~{dirflag}" && 15072 AsmPieces[2] == "~{flags}" && 15073 AsmPieces[3] == "~{fpsr}") 15074 return IntrinsicLowering::LowerToByteSwap(CI); 15075 } 15076 break; 15077 case 3: 15078 if (CI->getType()->isIntegerTy(32) && 15079 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15080 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15081 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15082 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15083 AsmPieces.clear(); 15084 const std::string &ConstraintsStr = IA->getConstraintString(); 15085 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15086 std::sort(AsmPieces.begin(), AsmPieces.end()); 15087 if (AsmPieces.size() == 4 && 15088 AsmPieces[0] == "~{cc}" && 15089 AsmPieces[1] == "~{dirflag}" && 15090 AsmPieces[2] == "~{flags}" && 15091 AsmPieces[3] == "~{fpsr}") 15092 return IntrinsicLowering::LowerToByteSwap(CI); 15093 } 15094 15095 if (CI->getType()->isIntegerTy(64)) { 15096 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15097 if (Constraints.size() >= 2 && 15098 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15099 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15100 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15101 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15102 matchAsm(AsmPieces[1], "bswap", "%edx") && 15103 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15104 return IntrinsicLowering::LowerToByteSwap(CI); 15105 } 15106 } 15107 break; 15108 } 15109 return false; 15110} 15111 15112 15113 15114/// getConstraintType - Given a constraint letter, return the type of 15115/// constraint it is for this target. 15116X86TargetLowering::ConstraintType 15117X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15118 if (Constraint.size() == 1) { 15119 switch (Constraint[0]) { 15120 case 'R': 15121 case 'q': 15122 case 'Q': 15123 case 'f': 15124 case 't': 15125 case 'u': 15126 case 'y': 15127 case 'x': 15128 case 'Y': 15129 case 'l': 15130 return C_RegisterClass; 15131 case 'a': 15132 case 'b': 15133 case 'c': 15134 case 'd': 15135 case 'S': 15136 case 'D': 15137 case 'A': 15138 return C_Register; 15139 case 'I': 15140 case 'J': 15141 case 'K': 15142 case 'L': 15143 case 'M': 15144 case 'N': 15145 case 'G': 15146 case 'C': 15147 case 'e': 15148 case 'Z': 15149 return C_Other; 15150 default: 15151 break; 15152 } 15153 } 15154 return TargetLowering::getConstraintType(Constraint); 15155} 15156 15157/// Examine constraint type and operand type and determine a weight value. 15158/// This object must already have been set up with the operand type 15159/// and the current alternative constraint selected. 15160TargetLowering::ConstraintWeight 15161 X86TargetLowering::getSingleConstraintMatchWeight( 15162 AsmOperandInfo &info, const char *constraint) const { 15163 ConstraintWeight weight = CW_Invalid; 15164 Value *CallOperandVal = info.CallOperandVal; 15165 // If we don't have a value, we can't do a match, 15166 // but allow it at the lowest weight. 15167 if (CallOperandVal == NULL) 15168 return CW_Default; 15169 Type *type = CallOperandVal->getType(); 15170 // Look at the constraint type. 15171 switch (*constraint) { 15172 default: 15173 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15174 case 'R': 15175 case 'q': 15176 case 'Q': 15177 case 'a': 15178 case 'b': 15179 case 'c': 15180 case 'd': 15181 case 'S': 15182 case 'D': 15183 case 'A': 15184 if (CallOperandVal->getType()->isIntegerTy()) 15185 weight = CW_SpecificReg; 15186 break; 15187 case 'f': 15188 case 't': 15189 case 'u': 15190 if (type->isFloatingPointTy()) 15191 weight = CW_SpecificReg; 15192 break; 15193 case 'y': 15194 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15195 weight = CW_SpecificReg; 15196 break; 15197 case 'x': 15198 case 'Y': 15199 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15200 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15201 weight = CW_Register; 15202 break; 15203 case 'I': 15204 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15205 if (C->getZExtValue() <= 31) 15206 weight = CW_Constant; 15207 } 15208 break; 15209 case 'J': 15210 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15211 if (C->getZExtValue() <= 63) 15212 weight = CW_Constant; 15213 } 15214 break; 15215 case 'K': 15216 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15217 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15218 weight = CW_Constant; 15219 } 15220 break; 15221 case 'L': 15222 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15223 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15224 weight = CW_Constant; 15225 } 15226 break; 15227 case 'M': 15228 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15229 if (C->getZExtValue() <= 3) 15230 weight = CW_Constant; 15231 } 15232 break; 15233 case 'N': 15234 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15235 if (C->getZExtValue() <= 0xff) 15236 weight = CW_Constant; 15237 } 15238 break; 15239 case 'G': 15240 case 'C': 15241 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15242 weight = CW_Constant; 15243 } 15244 break; 15245 case 'e': 15246 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15247 if ((C->getSExtValue() >= -0x80000000LL) && 15248 (C->getSExtValue() <= 0x7fffffffLL)) 15249 weight = CW_Constant; 15250 } 15251 break; 15252 case 'Z': 15253 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15254 if (C->getZExtValue() <= 0xffffffff) 15255 weight = CW_Constant; 15256 } 15257 break; 15258 } 15259 return weight; 15260} 15261 15262/// LowerXConstraint - try to replace an X constraint, which matches anything, 15263/// with another that has more specific requirements based on the type of the 15264/// corresponding operand. 15265const char *X86TargetLowering:: 15266LowerXConstraint(EVT ConstraintVT) const { 15267 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15268 // 'f' like normal targets. 15269 if (ConstraintVT.isFloatingPoint()) { 15270 if (Subtarget->hasSSE2()) 15271 return "Y"; 15272 if (Subtarget->hasSSE1()) 15273 return "x"; 15274 } 15275 15276 return TargetLowering::LowerXConstraint(ConstraintVT); 15277} 15278 15279/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15280/// vector. If it is invalid, don't add anything to Ops. 15281void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15282 std::string &Constraint, 15283 std::vector<SDValue>&Ops, 15284 SelectionDAG &DAG) const { 15285 SDValue Result(0, 0); 15286 15287 // Only support length 1 constraints for now. 15288 if (Constraint.length() > 1) return; 15289 15290 char ConstraintLetter = Constraint[0]; 15291 switch (ConstraintLetter) { 15292 default: break; 15293 case 'I': 15294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15295 if (C->getZExtValue() <= 31) { 15296 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15297 break; 15298 } 15299 } 15300 return; 15301 case 'J': 15302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15303 if (C->getZExtValue() <= 63) { 15304 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15305 break; 15306 } 15307 } 15308 return; 15309 case 'K': 15310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15311 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15312 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15313 break; 15314 } 15315 } 15316 return; 15317 case 'N': 15318 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15319 if (C->getZExtValue() <= 255) { 15320 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15321 break; 15322 } 15323 } 15324 return; 15325 case 'e': { 15326 // 32-bit signed value 15327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15328 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15329 C->getSExtValue())) { 15330 // Widen to 64 bits here to get it sign extended. 15331 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15332 break; 15333 } 15334 // FIXME gcc accepts some relocatable values here too, but only in certain 15335 // memory models; it's complicated. 15336 } 15337 return; 15338 } 15339 case 'Z': { 15340 // 32-bit unsigned value 15341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15342 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15343 C->getZExtValue())) { 15344 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15345 break; 15346 } 15347 } 15348 // FIXME gcc accepts some relocatable values here too, but only in certain 15349 // memory models; it's complicated. 15350 return; 15351 } 15352 case 'i': { 15353 // Literal immediates are always ok. 15354 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15355 // Widen to 64 bits here to get it sign extended. 15356 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15357 break; 15358 } 15359 15360 // In any sort of PIC mode addresses need to be computed at runtime by 15361 // adding in a register or some sort of table lookup. These can't 15362 // be used as immediates. 15363 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15364 return; 15365 15366 // If we are in non-pic codegen mode, we allow the address of a global (with 15367 // an optional displacement) to be used with 'i'. 15368 GlobalAddressSDNode *GA = 0; 15369 int64_t Offset = 0; 15370 15371 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15372 while (1) { 15373 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15374 Offset += GA->getOffset(); 15375 break; 15376 } else if (Op.getOpcode() == ISD::ADD) { 15377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15378 Offset += C->getZExtValue(); 15379 Op = Op.getOperand(0); 15380 continue; 15381 } 15382 } else if (Op.getOpcode() == ISD::SUB) { 15383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15384 Offset += -C->getZExtValue(); 15385 Op = Op.getOperand(0); 15386 continue; 15387 } 15388 } 15389 15390 // Otherwise, this isn't something we can handle, reject it. 15391 return; 15392 } 15393 15394 const GlobalValue *GV = GA->getGlobal(); 15395 // If we require an extra load to get this address, as in PIC mode, we 15396 // can't accept it. 15397 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15398 getTargetMachine()))) 15399 return; 15400 15401 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15402 GA->getValueType(0), Offset); 15403 break; 15404 } 15405 } 15406 15407 if (Result.getNode()) { 15408 Ops.push_back(Result); 15409 return; 15410 } 15411 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15412} 15413 15414std::pair<unsigned, const TargetRegisterClass*> 15415X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15416 EVT VT) const { 15417 // First, see if this is a constraint that directly corresponds to an LLVM 15418 // register class. 15419 if (Constraint.size() == 1) { 15420 // GCC Constraint Letters 15421 switch (Constraint[0]) { 15422 default: break; 15423 // TODO: Slight differences here in allocation order and leaving 15424 // RIP in the class. Do they matter any more here than they do 15425 // in the normal allocation? 15426 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15427 if (Subtarget->is64Bit()) { 15428 if (VT == MVT::i32 || VT == MVT::f32) 15429 return std::make_pair(0U, X86::GR32RegisterClass); 15430 else if (VT == MVT::i16) 15431 return std::make_pair(0U, X86::GR16RegisterClass); 15432 else if (VT == MVT::i8 || VT == MVT::i1) 15433 return std::make_pair(0U, X86::GR8RegisterClass); 15434 else if (VT == MVT::i64 || VT == MVT::f64) 15435 return std::make_pair(0U, X86::GR64RegisterClass); 15436 break; 15437 } 15438 // 32-bit fallthrough 15439 case 'Q': // Q_REGS 15440 if (VT == MVT::i32 || VT == MVT::f32) 15441 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15442 else if (VT == MVT::i16) 15443 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15444 else if (VT == MVT::i8 || VT == MVT::i1) 15445 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15446 else if (VT == MVT::i64) 15447 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15448 break; 15449 case 'r': // GENERAL_REGS 15450 case 'l': // INDEX_REGS 15451 if (VT == MVT::i8 || VT == MVT::i1) 15452 return std::make_pair(0U, X86::GR8RegisterClass); 15453 if (VT == MVT::i16) 15454 return std::make_pair(0U, X86::GR16RegisterClass); 15455 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15456 return std::make_pair(0U, X86::GR32RegisterClass); 15457 return std::make_pair(0U, X86::GR64RegisterClass); 15458 case 'R': // LEGACY_REGS 15459 if (VT == MVT::i8 || VT == MVT::i1) 15460 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15461 if (VT == MVT::i16) 15462 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15463 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15464 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15465 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15466 case 'f': // FP Stack registers. 15467 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15468 // value to the correct fpstack register class. 15469 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15470 return std::make_pair(0U, X86::RFP32RegisterClass); 15471 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15472 return std::make_pair(0U, X86::RFP64RegisterClass); 15473 return std::make_pair(0U, X86::RFP80RegisterClass); 15474 case 'y': // MMX_REGS if MMX allowed. 15475 if (!Subtarget->hasMMX()) break; 15476 return std::make_pair(0U, X86::VR64RegisterClass); 15477 case 'Y': // SSE_REGS if SSE2 allowed 15478 if (!Subtarget->hasSSE2()) break; 15479 // FALL THROUGH. 15480 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15481 if (!Subtarget->hasSSE1()) break; 15482 15483 switch (VT.getSimpleVT().SimpleTy) { 15484 default: break; 15485 // Scalar SSE types. 15486 case MVT::f32: 15487 case MVT::i32: 15488 return std::make_pair(0U, X86::FR32RegisterClass); 15489 case MVT::f64: 15490 case MVT::i64: 15491 return std::make_pair(0U, X86::FR64RegisterClass); 15492 // Vector types. 15493 case MVT::v16i8: 15494 case MVT::v8i16: 15495 case MVT::v4i32: 15496 case MVT::v2i64: 15497 case MVT::v4f32: 15498 case MVT::v2f64: 15499 return std::make_pair(0U, X86::VR128RegisterClass); 15500 // AVX types. 15501 case MVT::v32i8: 15502 case MVT::v16i16: 15503 case MVT::v8i32: 15504 case MVT::v4i64: 15505 case MVT::v8f32: 15506 case MVT::v4f64: 15507 return std::make_pair(0U, X86::VR256RegisterClass); 15508 15509 } 15510 break; 15511 } 15512 } 15513 15514 // Use the default implementation in TargetLowering to convert the register 15515 // constraint into a member of a register class. 15516 std::pair<unsigned, const TargetRegisterClass*> Res; 15517 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15518 15519 // Not found as a standard register? 15520 if (Res.second == 0) { 15521 // Map st(0) -> st(7) -> ST0 15522 if (Constraint.size() == 7 && Constraint[0] == '{' && 15523 tolower(Constraint[1]) == 's' && 15524 tolower(Constraint[2]) == 't' && 15525 Constraint[3] == '(' && 15526 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15527 Constraint[5] == ')' && 15528 Constraint[6] == '}') { 15529 15530 Res.first = X86::ST0+Constraint[4]-'0'; 15531 Res.second = X86::RFP80RegisterClass; 15532 return Res; 15533 } 15534 15535 // GCC allows "st(0)" to be called just plain "st". 15536 if (StringRef("{st}").equals_lower(Constraint)) { 15537 Res.first = X86::ST0; 15538 Res.second = X86::RFP80RegisterClass; 15539 return Res; 15540 } 15541 15542 // flags -> EFLAGS 15543 if (StringRef("{flags}").equals_lower(Constraint)) { 15544 Res.first = X86::EFLAGS; 15545 Res.second = X86::CCRRegisterClass; 15546 return Res; 15547 } 15548 15549 // 'A' means EAX + EDX. 15550 if (Constraint == "A") { 15551 Res.first = X86::EAX; 15552 Res.second = X86::GR32_ADRegisterClass; 15553 return Res; 15554 } 15555 return Res; 15556 } 15557 15558 // Otherwise, check to see if this is a register class of the wrong value 15559 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15560 // turn into {ax},{dx}. 15561 if (Res.second->hasType(VT)) 15562 return Res; // Correct type already, nothing to do. 15563 15564 // All of the single-register GCC register classes map their values onto 15565 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15566 // really want an 8-bit or 32-bit register, map to the appropriate register 15567 // class and return the appropriate register. 15568 if (Res.second == X86::GR16RegisterClass) { 15569 if (VT == MVT::i8) { 15570 unsigned DestReg = 0; 15571 switch (Res.first) { 15572 default: break; 15573 case X86::AX: DestReg = X86::AL; break; 15574 case X86::DX: DestReg = X86::DL; break; 15575 case X86::CX: DestReg = X86::CL; break; 15576 case X86::BX: DestReg = X86::BL; break; 15577 } 15578 if (DestReg) { 15579 Res.first = DestReg; 15580 Res.second = X86::GR8RegisterClass; 15581 } 15582 } else if (VT == MVT::i32) { 15583 unsigned DestReg = 0; 15584 switch (Res.first) { 15585 default: break; 15586 case X86::AX: DestReg = X86::EAX; break; 15587 case X86::DX: DestReg = X86::EDX; break; 15588 case X86::CX: DestReg = X86::ECX; break; 15589 case X86::BX: DestReg = X86::EBX; break; 15590 case X86::SI: DestReg = X86::ESI; break; 15591 case X86::DI: DestReg = X86::EDI; break; 15592 case X86::BP: DestReg = X86::EBP; break; 15593 case X86::SP: DestReg = X86::ESP; break; 15594 } 15595 if (DestReg) { 15596 Res.first = DestReg; 15597 Res.second = X86::GR32RegisterClass; 15598 } 15599 } else if (VT == MVT::i64) { 15600 unsigned DestReg = 0; 15601 switch (Res.first) { 15602 default: break; 15603 case X86::AX: DestReg = X86::RAX; break; 15604 case X86::DX: DestReg = X86::RDX; break; 15605 case X86::CX: DestReg = X86::RCX; break; 15606 case X86::BX: DestReg = X86::RBX; break; 15607 case X86::SI: DestReg = X86::RSI; break; 15608 case X86::DI: DestReg = X86::RDI; break; 15609 case X86::BP: DestReg = X86::RBP; break; 15610 case X86::SP: DestReg = X86::RSP; break; 15611 } 15612 if (DestReg) { 15613 Res.first = DestReg; 15614 Res.second = X86::GR64RegisterClass; 15615 } 15616 } 15617 } else if (Res.second == X86::FR32RegisterClass || 15618 Res.second == X86::FR64RegisterClass || 15619 Res.second == X86::VR128RegisterClass) { 15620 // Handle references to XMM physical registers that got mapped into the 15621 // wrong class. This can happen with constraints like {xmm0} where the 15622 // target independent register mapper will just pick the first match it can 15623 // find, ignoring the required type. 15624 if (VT == MVT::f32) 15625 Res.second = X86::FR32RegisterClass; 15626 else if (VT == MVT::f64) 15627 Res.second = X86::FR64RegisterClass; 15628 else if (X86::VR128RegisterClass->hasType(VT)) 15629 Res.second = X86::VR128RegisterClass; 15630 } 15631 15632 return Res; 15633} 15634