X86ISelLowering.cpp revision 5f1d8abf759ab3553abe5e7ed40174bc57a985c8
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/PseudoSourceValue.h" 39#include "llvm/MC/MCAsmInfo.h" 40#include "llvm/MC/MCContext.h" 41#include "llvm/MC/MCExpr.h" 42#include "llvm/MC/MCSymbol.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/SmallSet.h" 45#include "llvm/ADT/Statistic.h" 46#include "llvm/ADT/StringExtras.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/Support/CallSite.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54using namespace llvm; 55using namespace dwarf; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58 59// Forward declarations. 60static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 61 SDValue V2); 62 63static SDValue Insert128BitVector(SDValue Result, 64 SDValue Vec, 65 SDValue Idx, 66 SelectionDAG &DAG, 67 DebugLoc dl); 68 69static SDValue Extract128BitVector(SDValue Vec, 70 SDValue Idx, 71 SelectionDAG &DAG, 72 DebugLoc dl); 73 74/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 75/// sets things up to match to an AVX VEXTRACTF128 instruction or a 76/// simple subregister reference. Idx is an index in the 128 bits we 77/// want. It need not be aligned to a 128-bit bounday. That makes 78/// lowering EXTRACT_VECTOR_ELT operations easier. 79static SDValue Extract128BitVector(SDValue Vec, 80 SDValue Idx, 81 SelectionDAG &DAG, 82 DebugLoc dl) { 83 EVT VT = Vec.getValueType(); 84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 85 EVT ElVT = VT.getVectorElementType(); 86 int Factor = VT.getSizeInBits()/128; 87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 88 VT.getVectorNumElements()/Factor); 89 90 // Extract from UNDEF is UNDEF. 91 if (Vec.getOpcode() == ISD::UNDEF) 92 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 93 94 if (isa<ConstantSDNode>(Idx)) { 95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 96 97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 98 // we can match to VEXTRACTF128. 99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 100 101 // This is the index of the first element of the 128-bit chunk 102 // we want. 103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 104 * ElemsPerChunk); 105 106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 108 VecIdx); 109 110 return Result; 111 } 112 113 return SDValue(); 114} 115 116/// Generate a DAG to put 128-bits into a vector > 128 bits. This 117/// sets things up to match to an AVX VINSERTF128 instruction or a 118/// simple superregister reference. Idx is an index in the 128 bits 119/// we want. It need not be aligned to a 128-bit bounday. That makes 120/// lowering INSERT_VECTOR_ELT operations easier. 121static SDValue Insert128BitVector(SDValue Result, 122 SDValue Vec, 123 SDValue Idx, 124 SelectionDAG &DAG, 125 DebugLoc dl) { 126 if (isa<ConstantSDNode>(Idx)) { 127 EVT VT = Vec.getValueType(); 128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 129 130 EVT ElVT = VT.getVectorElementType(); 131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 132 EVT ResultVT = Result.getValueType(); 133 134 // Insert the relevant 128 bits. 135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 136 137 // This is the index of the first element of the 128-bit chunk 138 // we want. 139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 140 * ElemsPerChunk); 141 142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 144 VecIdx); 145 return Result; 146 } 147 148 return SDValue(); 149} 150 151static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 bool is64Bit = Subtarget->is64Bit(); 154 155 if (Subtarget->isTargetEnvMacho()) { 156 if (is64Bit) 157 return new X8664_MachoTargetObjectFile(); 158 return new TargetLoweringObjectFileMachO(); 159 } 160 161 if (Subtarget->isTargetELF()) 162 return new TargetLoweringObjectFileELF(); 163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 164 return new TargetLoweringObjectFileCOFF(); 165 llvm_unreachable("unknown subtarget type"); 166} 167 168X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 169 : TargetLowering(TM, createTLOF(TM)) { 170 Subtarget = &TM.getSubtarget<X86Subtarget>(); 171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX(); 172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX(); 173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 174 175 RegInfo = TM.getRegisterInfo(); 176 TD = getTargetData(); 177 178 // Set up the TargetLowering object. 179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 180 181 // X86 is weird, it always uses i8 for shift amounts and setcc results. 182 setBooleanContents(ZeroOrOneBooleanContent); 183 184 // For 64-bit since we have so many registers use the ILP scheduler, for 185 // 32-bit code use the register pressure specific scheduling. 186 if (Subtarget->is64Bit()) 187 setSchedulingPreference(Sched::ILP); 188 else 189 setSchedulingPreference(Sched::RegPressure); 190 setStackPointerRegisterToSaveRestore(X86StackPtr); 191 192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 193 // Setup Windows compiler runtime calls. 194 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 196 setLibcallName(RTLIB::SREM_I64, "_allrem"); 197 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 198 setLibcallName(RTLIB::MUL_I64, "_allmul"); 199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 208 } 209 210 if (Subtarget->isTargetDarwin()) { 211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 212 setUseUnderscoreSetJmp(false); 213 setUseUnderscoreLongJmp(false); 214 } else if (Subtarget->isTargetMingw()) { 215 // MS runtime is weird: it exports _setjmp, but longjmp! 216 setUseUnderscoreSetJmp(true); 217 setUseUnderscoreLongJmp(false); 218 } else { 219 setUseUnderscoreSetJmp(true); 220 setUseUnderscoreLongJmp(true); 221 } 222 223 // Set up the register classes. 224 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 225 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 226 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 227 if (Subtarget->is64Bit()) 228 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 229 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 231 232 // We don't accept any truncstore of integer registers. 233 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 234 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 236 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 238 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 239 240 // SETOEQ and SETUNE require checking two conditions. 241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 247 248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 249 // operation. 250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 253 254 if (Subtarget->is64Bit()) { 255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 257 } else if (!UseSoftFloat) { 258 // We have an algorithm for SSE2->double, and we turn this into a 259 // 64-bit FILD followed by conditional FADD for other targets. 260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 261 // We have an algorithm for SSE2, and we turn this into a 64-bit 262 // FILD for other targets. 263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 264 } 265 266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 267 // this operation. 268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 270 271 if (!UseSoftFloat) { 272 // SSE has no i16 to fp conversion, only i32 273 if (X86ScalarSSEf32) { 274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 275 // f32 and f64 cases are Legal, f80 case is not 276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 277 } else { 278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 280 } 281 } else { 282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 284 } 285 286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 287 // are Legal, f80 is custom lowered. 288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 290 291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 292 // this operation. 293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 295 296 if (X86ScalarSSEf32) { 297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 298 // f32 and f64 cases are Legal, f80 case is not 299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 300 } else { 301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 303 } 304 305 // Handle FP_TO_UINT by promoting the destination to a larger signed 306 // conversion. 307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 310 311 if (Subtarget->is64Bit()) { 312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 314 } else if (!UseSoftFloat) { 315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 316 // Expand FP_TO_UINT into a select. 317 // FIXME: We would like to use a Custom expander here eventually to do 318 // the optimal thing for SSE vs. the default expansion in the legalizer. 319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 320 else 321 // With SSE3 we can use fisttpll to convert to a signed i64; without 322 // SSE, we're stuck with a fistpll. 323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 324 } 325 326 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 327 if (!X86ScalarSSEf64) { 328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 330 if (Subtarget->is64Bit()) { 331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 332 // Without SSE, i64->f64 goes through memory. 333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 334 } 335 } 336 337 // Scalar integer divide and remainder are lowered to use operations that 338 // produce two results, to match the available instructions. This exposes 339 // the two-result form to trivial CSE, which is able to combine x/y and x%y 340 // into a single instruction. 341 // 342 // Scalar integer multiply-high is also lowered to use two-result 343 // operations, to match the available instructions. However, plain multiply 344 // (low) operations are left as Legal, as there are single-result 345 // instructions for this in x86. Using the two-result multiply instructions 346 // when both high and low results are needed must be arranged by dagcombine. 347 for (unsigned i = 0, e = 4; i != e; ++i) { 348 MVT VT = IntVTs[i]; 349 setOperationAction(ISD::MULHS, VT, Expand); 350 setOperationAction(ISD::MULHU, VT, Expand); 351 setOperationAction(ISD::SDIV, VT, Expand); 352 setOperationAction(ISD::UDIV, VT, Expand); 353 setOperationAction(ISD::SREM, VT, Expand); 354 setOperationAction(ISD::UREM, VT, Expand); 355 356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 357 setOperationAction(ISD::ADDC, VT, Custom); 358 setOperationAction(ISD::ADDE, VT, Custom); 359 setOperationAction(ISD::SUBC, VT, Custom); 360 setOperationAction(ISD::SUBE, VT, Custom); 361 } 362 363 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 364 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 365 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 367 if (Subtarget->is64Bit()) 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 373 setOperationAction(ISD::FREM , MVT::f32 , Expand); 374 setOperationAction(ISD::FREM , MVT::f64 , Expand); 375 setOperationAction(ISD::FREM , MVT::f80 , Expand); 376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 377 378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 384 if (Subtarget->is64Bit()) { 385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 387 } 388 389 if (Subtarget->hasPOPCNT()) { 390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 391 } else { 392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 395 if (Subtarget->is64Bit()) 396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 397 } 398 399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 401 402 // These should be promoted to a larger select which is supported. 403 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 404 // X86 wants to expand cmov itself. 405 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 406 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 407 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 408 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 409 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 410 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 411 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 412 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 413 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 414 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 415 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 416 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 417 if (Subtarget->is64Bit()) { 418 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 419 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 420 } 421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 422 423 // Darwin ABI issue. 424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 428 if (Subtarget->is64Bit()) 429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 432 if (Subtarget->is64Bit()) { 433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 438 } 439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 443 if (Subtarget->is64Bit()) { 444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 447 } 448 449 if (Subtarget->hasXMM()) 450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 451 452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 454 455 // On X86 and X86-64, atomic operations are lowered to locked instructions. 456 // Locked instructions, in turn, have implicit fence semantics (all memory 457 // operations are flushed before issuing the locked instruction, and they 458 // are not buffered), so we can fold away the common pattern of 459 // fence-atomic-fence. 460 setShouldFoldAtomicFences(true); 461 462 // Expand certain atomics 463 for (unsigned i = 0, e = 4; i != e; ++i) { 464 MVT VT = IntVTs[i]; 465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 467 } 468 469 if (!Subtarget->is64Bit()) { 470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 476 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 477 } 478 479 // FIXME - use subtarget debug flags 480 if (!Subtarget->isTargetDarwin() && 481 !Subtarget->isTargetELF() && 482 !Subtarget->isTargetCygMing()) { 483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 484 } 485 486 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 487 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 489 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 490 if (Subtarget->is64Bit()) { 491 setExceptionPointerRegister(X86::RAX); 492 setExceptionSelectorRegister(X86::RDX); 493 } else { 494 setExceptionPointerRegister(X86::EAX); 495 setExceptionSelectorRegister(X86::EDX); 496 } 497 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 498 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 499 500 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 501 502 setOperationAction(ISD::TRAP, MVT::Other, Legal); 503 504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 505 setOperationAction(ISD::VASTART , MVT::Other, Custom); 506 setOperationAction(ISD::VAEND , MVT::Other, Expand); 507 if (Subtarget->is64Bit()) { 508 setOperationAction(ISD::VAARG , MVT::Other, Custom); 509 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 510 } else { 511 setOperationAction(ISD::VAARG , MVT::Other, Expand); 512 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 513 } 514 515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 517 setOperationAction(ISD::DYNAMIC_STACKALLOC, 518 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), 519 (Subtarget->isTargetCOFF() 520 && !Subtarget->isTargetEnvMacho() 521 ? Custom : Expand)); 522 523 if (!UseSoftFloat && X86ScalarSSEf64) { 524 // f32 and f64 use SSE. 525 // Set up the FP register classes. 526 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 527 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 528 529 // Use ANDPD to simulate FABS. 530 setOperationAction(ISD::FABS , MVT::f64, Custom); 531 setOperationAction(ISD::FABS , MVT::f32, Custom); 532 533 // Use XORP to simulate FNEG. 534 setOperationAction(ISD::FNEG , MVT::f64, Custom); 535 setOperationAction(ISD::FNEG , MVT::f32, Custom); 536 537 // Use ANDPD and ORPD to simulate FCOPYSIGN. 538 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 539 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 540 541 // Lower this to FGETSIGNx86 plus an AND. 542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 544 545 // We don't support sin/cos/fmod 546 setOperationAction(ISD::FSIN , MVT::f64, Expand); 547 setOperationAction(ISD::FCOS , MVT::f64, Expand); 548 setOperationAction(ISD::FSIN , MVT::f32, Expand); 549 setOperationAction(ISD::FCOS , MVT::f32, Expand); 550 551 // Expand FP immediates into loads from the stack, except for the special 552 // cases we handle. 553 addLegalFPImmediate(APFloat(+0.0)); // xorpd 554 addLegalFPImmediate(APFloat(+0.0f)); // xorps 555 } else if (!UseSoftFloat && X86ScalarSSEf32) { 556 // Use SSE for f32, x87 for f64. 557 // Set up the FP register classes. 558 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 559 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 560 561 // Use ANDPS to simulate FABS. 562 setOperationAction(ISD::FABS , MVT::f32, Custom); 563 564 // Use XORP to simulate FNEG. 565 setOperationAction(ISD::FNEG , MVT::f32, Custom); 566 567 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 568 569 // Use ANDPS and ORPS to simulate FCOPYSIGN. 570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 572 573 // We don't support sin/cos/fmod 574 setOperationAction(ISD::FSIN , MVT::f32, Expand); 575 setOperationAction(ISD::FCOS , MVT::f32, Expand); 576 577 // Special cases we handle for FP constants. 578 addLegalFPImmediate(APFloat(+0.0f)); // xorps 579 addLegalFPImmediate(APFloat(+0.0)); // FLD0 580 addLegalFPImmediate(APFloat(+1.0)); // FLD1 581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 583 584 if (!UnsafeFPMath) { 585 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 586 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 587 } 588 } else if (!UseSoftFloat) { 589 // f32 and f64 in x87. 590 // Set up the FP register classes. 591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 592 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 593 594 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 595 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 598 599 if (!UnsafeFPMath) { 600 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 601 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 602 } 603 addLegalFPImmediate(APFloat(+0.0)); // FLD0 604 addLegalFPImmediate(APFloat(+1.0)); // FLD1 605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 611 } 612 613 // We don't support FMA. 614 setOperationAction(ISD::FMA, MVT::f64, Expand); 615 setOperationAction(ISD::FMA, MVT::f32, Expand); 616 617 // Long double always uses X87. 618 if (!UseSoftFloat) { 619 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 620 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 622 { 623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 624 addLegalFPImmediate(TmpFlt); // FLD0 625 TmpFlt.changeSign(); 626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 627 628 bool ignored; 629 APFloat TmpFlt2(+1.0); 630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 631 &ignored); 632 addLegalFPImmediate(TmpFlt2); // FLD1 633 TmpFlt2.changeSign(); 634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 635 } 636 637 if (!UnsafeFPMath) { 638 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 639 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 640 } 641 642 setOperationAction(ISD::FMA, MVT::f80, Expand); 643 } 644 645 // Always use a library call for pow. 646 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 647 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 648 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 649 650 setOperationAction(ISD::FLOG, MVT::f80, Expand); 651 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 652 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 653 setOperationAction(ISD::FEXP, MVT::f80, Expand); 654 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 655 656 // First set operation action for all vector types to either promote 657 // (for widening) or expand (for scalarization). Then we will selectively 658 // turn on ones that can be effectively codegen'd. 659 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 660 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 661 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 662 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 663 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 664 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 665 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 666 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 667 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 668 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 669 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 670 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 671 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 672 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 673 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 674 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 675 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 676 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 677 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 678 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 679 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 680 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 681 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 682 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 683 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 684 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 685 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 686 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 692 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 700 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 701 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 702 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 703 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 704 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 711 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 715 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 716 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 717 setTruncStoreAction((MVT::SimpleValueType)VT, 718 (MVT::SimpleValueType)InnerVT, Expand); 719 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 720 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 721 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 722 } 723 724 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 725 // with -msoft-float, disable use of MMX as well. 726 if (!UseSoftFloat && Subtarget->hasMMX()) { 727 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 728 // No operations on x86mmx supported, everything uses intrinsics. 729 } 730 731 // MMX-sized vectors (other than x86mmx) are expected to be expanded 732 // into smaller operations. 733 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 734 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 735 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 736 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 737 setOperationAction(ISD::AND, MVT::v8i8, Expand); 738 setOperationAction(ISD::AND, MVT::v4i16, Expand); 739 setOperationAction(ISD::AND, MVT::v2i32, Expand); 740 setOperationAction(ISD::AND, MVT::v1i64, Expand); 741 setOperationAction(ISD::OR, MVT::v8i8, Expand); 742 setOperationAction(ISD::OR, MVT::v4i16, Expand); 743 setOperationAction(ISD::OR, MVT::v2i32, Expand); 744 setOperationAction(ISD::OR, MVT::v1i64, Expand); 745 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 746 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 747 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 748 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 754 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 755 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 756 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 757 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 758 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 759 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 760 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 761 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 762 763 if (!UseSoftFloat && Subtarget->hasXMM()) { 764 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 765 766 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 767 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 768 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 769 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 770 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 771 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 772 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 773 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 774 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 776 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 777 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 778 } 779 780 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 781 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 782 783 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 784 // registers cannot be used even for integer operations. 785 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 786 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 787 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 788 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 789 790 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 791 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 792 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 793 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 794 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 795 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 796 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 797 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 798 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 799 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 800 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 801 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 802 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 803 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 804 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 805 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 806 807 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 808 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 809 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 810 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 811 812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 817 818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 823 824 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 825 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 826 EVT VT = (MVT::SimpleValueType)i; 827 // Do not attempt to custom lower non-power-of-2 vectors 828 if (!isPowerOf2_32(VT.getVectorNumElements())) 829 continue; 830 // Do not attempt to custom lower non-128-bit vectors 831 if (!VT.is128BitVector()) 832 continue; 833 setOperationAction(ISD::BUILD_VECTOR, 834 VT.getSimpleVT().SimpleTy, Custom); 835 setOperationAction(ISD::VECTOR_SHUFFLE, 836 VT.getSimpleVT().SimpleTy, Custom); 837 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 838 VT.getSimpleVT().SimpleTy, Custom); 839 } 840 841 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 842 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 843 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 847 848 if (Subtarget->is64Bit()) { 849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 851 } 852 853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 854 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 855 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 856 EVT VT = SVT; 857 858 // Do not attempt to promote non-128-bit vectors 859 if (!VT.is128BitVector()) 860 continue; 861 862 setOperationAction(ISD::AND, SVT, Promote); 863 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 864 setOperationAction(ISD::OR, SVT, Promote); 865 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 866 setOperationAction(ISD::XOR, SVT, Promote); 867 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 868 setOperationAction(ISD::LOAD, SVT, Promote); 869 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 870 setOperationAction(ISD::SELECT, SVT, Promote); 871 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 872 } 873 874 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 875 876 // Custom lower v2i64 and v2f64 selects. 877 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 878 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 879 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 880 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 881 882 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 883 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 884 } 885 886 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 887 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 888 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 889 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 890 setOperationAction(ISD::FRINT, MVT::f32, Legal); 891 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 892 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 893 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 894 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 895 setOperationAction(ISD::FRINT, MVT::f64, Legal); 896 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 897 898 // FIXME: Do we need to handle scalar-to-vector here? 899 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 900 901 // Can turn SHL into an integer multiply. 902 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 903 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 904 905 // i8 and i16 vectors are custom , because the source register and source 906 // source memory operand types are not the same width. f32 vectors are 907 // custom since the immediate controlling the insert encodes additional 908 // information. 909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 913 914 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 918 919 if (Subtarget->is64Bit()) { 920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 922 } 923 } 924 925 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) { 926 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 927 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 928 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 929 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 930 931 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 932 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 933 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 934 935 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 936 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 937 } 938 939 if (Subtarget->hasSSE42() || Subtarget->hasAVX()) 940 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 941 942 if (!UseSoftFloat && Subtarget->hasAVX()) { 943 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 944 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 945 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 946 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 947 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 948 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 949 950 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 951 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 952 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 953 954 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 955 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 956 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 957 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 958 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 959 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 960 961 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 962 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 963 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 964 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 965 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 966 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 967 968 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 969 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 970 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 971 972 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 973 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 978 979 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 980 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 981 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 982 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 983 984 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 985 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 986 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 987 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 988 989 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 990 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 991 992 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 993 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom); 994 995 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 996 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 997 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 998 999 // Custom lower several nodes for 256-bit types. 1000 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1001 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1002 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1003 EVT VT = SVT; 1004 1005 // Extract subvector is special because the value type 1006 // (result) is 128-bit but the source is 256-bit wide. 1007 if (VT.is128BitVector()) 1008 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1009 1010 // Do not attempt to custom lower other non-256-bit vectors 1011 if (!VT.is256BitVector()) 1012 continue; 1013 1014 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1015 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1016 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1018 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1019 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1020 } 1021 1022 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1023 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1024 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1025 EVT VT = SVT; 1026 1027 // Do not attempt to promote non-256-bit vectors 1028 if (!VT.is256BitVector()) 1029 continue; 1030 1031 setOperationAction(ISD::AND, SVT, Promote); 1032 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1033 setOperationAction(ISD::OR, SVT, Promote); 1034 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1035 setOperationAction(ISD::XOR, SVT, Promote); 1036 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1037 setOperationAction(ISD::LOAD, SVT, Promote); 1038 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1039 setOperationAction(ISD::SELECT, SVT, Promote); 1040 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1041 } 1042 } 1043 1044 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1045 // of this type with custom code. 1046 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1047 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1048 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1049 } 1050 1051 // We want to custom lower some of our intrinsics. 1052 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1053 1054 1055 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1056 // handle type legalization for these operations here. 1057 // 1058 // FIXME: We really should do custom legalization for addition and 1059 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1060 // than generic legalization for 64-bit multiplication-with-overflow, though. 1061 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1062 // Add/Sub/Mul with overflow operations are custom lowered. 1063 MVT VT = IntVTs[i]; 1064 setOperationAction(ISD::SADDO, VT, Custom); 1065 setOperationAction(ISD::UADDO, VT, Custom); 1066 setOperationAction(ISD::SSUBO, VT, Custom); 1067 setOperationAction(ISD::USUBO, VT, Custom); 1068 setOperationAction(ISD::SMULO, VT, Custom); 1069 setOperationAction(ISD::UMULO, VT, Custom); 1070 } 1071 1072 // There are no 8-bit 3-address imul/mul instructions 1073 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1074 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1075 1076 if (!Subtarget->is64Bit()) { 1077 // These libcalls are not available in 32-bit. 1078 setLibcallName(RTLIB::SHL_I128, 0); 1079 setLibcallName(RTLIB::SRL_I128, 0); 1080 setLibcallName(RTLIB::SRA_I128, 0); 1081 } 1082 1083 // We have target-specific dag combine patterns for the following nodes: 1084 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1085 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1086 setTargetDAGCombine(ISD::BUILD_VECTOR); 1087 setTargetDAGCombine(ISD::SELECT); 1088 setTargetDAGCombine(ISD::SHL); 1089 setTargetDAGCombine(ISD::SRA); 1090 setTargetDAGCombine(ISD::SRL); 1091 setTargetDAGCombine(ISD::OR); 1092 setTargetDAGCombine(ISD::AND); 1093 setTargetDAGCombine(ISD::ADD); 1094 setTargetDAGCombine(ISD::SUB); 1095 setTargetDAGCombine(ISD::STORE); 1096 setTargetDAGCombine(ISD::ZERO_EXTEND); 1097 setTargetDAGCombine(ISD::SINT_TO_FP); 1098 if (Subtarget->is64Bit()) 1099 setTargetDAGCombine(ISD::MUL); 1100 1101 computeRegisterProperties(); 1102 1103 // On Darwin, -Os means optimize for size without hurting performance, 1104 // do not reduce the limit. 1105 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1106 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1107 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1108 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1109 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1110 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1111 setPrefLoopAlignment(16); 1112 benefitFromCodePlacementOpt = true; 1113 1114 setPrefFunctionAlignment(4); 1115} 1116 1117 1118MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1119 return MVT::i8; 1120} 1121 1122 1123/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1124/// the desired ByVal argument alignment. 1125static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1126 if (MaxAlign == 16) 1127 return; 1128 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1129 if (VTy->getBitWidth() == 128) 1130 MaxAlign = 16; 1131 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1132 unsigned EltAlign = 0; 1133 getMaxByValAlign(ATy->getElementType(), EltAlign); 1134 if (EltAlign > MaxAlign) 1135 MaxAlign = EltAlign; 1136 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1137 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1138 unsigned EltAlign = 0; 1139 getMaxByValAlign(STy->getElementType(i), EltAlign); 1140 if (EltAlign > MaxAlign) 1141 MaxAlign = EltAlign; 1142 if (MaxAlign == 16) 1143 break; 1144 } 1145 } 1146 return; 1147} 1148 1149/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1150/// function arguments in the caller parameter area. For X86, aggregates 1151/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1152/// are at 4-byte boundaries. 1153unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1154 if (Subtarget->is64Bit()) { 1155 // Max of 8 and alignment of type. 1156 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1157 if (TyAlign > 8) 1158 return TyAlign; 1159 return 8; 1160 } 1161 1162 unsigned Align = 4; 1163 if (Subtarget->hasXMM()) 1164 getMaxByValAlign(Ty, Align); 1165 return Align; 1166} 1167 1168/// getOptimalMemOpType - Returns the target specific optimal type for load 1169/// and store operations as a result of memset, memcpy, and memmove 1170/// lowering. If DstAlign is zero that means it's safe to destination 1171/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1172/// means there isn't a need to check it against alignment requirement, 1173/// probably because the source does not need to be loaded. If 1174/// 'NonScalarIntSafe' is true, that means it's safe to return a 1175/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1176/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1177/// constant so it does not need to be loaded. 1178/// It returns EVT::Other if the type should be determined using generic 1179/// target-independent logic. 1180EVT 1181X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1182 unsigned DstAlign, unsigned SrcAlign, 1183 bool NonScalarIntSafe, 1184 bool MemcpyStrSrc, 1185 MachineFunction &MF) const { 1186 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1187 // linux. This is because the stack realignment code can't handle certain 1188 // cases like PR2962. This should be removed when PR2962 is fixed. 1189 const Function *F = MF.getFunction(); 1190 if (NonScalarIntSafe && 1191 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1192 if (Size >= 16 && 1193 (Subtarget->isUnalignedMemAccessFast() || 1194 ((DstAlign == 0 || DstAlign >= 16) && 1195 (SrcAlign == 0 || SrcAlign >= 16))) && 1196 Subtarget->getStackAlignment() >= 16) { 1197 if (Subtarget->hasSSE2()) 1198 return MVT::v4i32; 1199 if (Subtarget->hasSSE1()) 1200 return MVT::v4f32; 1201 } else if (!MemcpyStrSrc && Size >= 8 && 1202 !Subtarget->is64Bit() && 1203 Subtarget->getStackAlignment() >= 8 && 1204 Subtarget->hasXMMInt()) { 1205 // Do not use f64 to lower memcpy if source is string constant. It's 1206 // better to use i32 to avoid the loads. 1207 return MVT::f64; 1208 } 1209 } 1210 if (Subtarget->is64Bit() && Size >= 8) 1211 return MVT::i64; 1212 return MVT::i32; 1213} 1214 1215/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1216/// current function. The returned value is a member of the 1217/// MachineJumpTableInfo::JTEntryKind enum. 1218unsigned X86TargetLowering::getJumpTableEncoding() const { 1219 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1220 // symbol. 1221 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1222 Subtarget->isPICStyleGOT()) 1223 return MachineJumpTableInfo::EK_Custom32; 1224 1225 // Otherwise, use the normal jump table encoding heuristics. 1226 return TargetLowering::getJumpTableEncoding(); 1227} 1228 1229const MCExpr * 1230X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1231 const MachineBasicBlock *MBB, 1232 unsigned uid,MCContext &Ctx) const{ 1233 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1234 Subtarget->isPICStyleGOT()); 1235 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1236 // entries. 1237 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1238 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1239} 1240 1241/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1242/// jumptable. 1243SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1244 SelectionDAG &DAG) const { 1245 if (!Subtarget->is64Bit()) 1246 // This doesn't have DebugLoc associated with it, but is not really the 1247 // same as a Register. 1248 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1249 return Table; 1250} 1251 1252/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1253/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1254/// MCExpr. 1255const MCExpr *X86TargetLowering:: 1256getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1257 MCContext &Ctx) const { 1258 // X86-64 uses RIP relative addressing based on the jump table label. 1259 if (Subtarget->isPICStyleRIPRel()) 1260 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1261 1262 // Otherwise, the reference is relative to the PIC base. 1263 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1264} 1265 1266// FIXME: Why this routine is here? Move to RegInfo! 1267std::pair<const TargetRegisterClass*, uint8_t> 1268X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1269 const TargetRegisterClass *RRC = 0; 1270 uint8_t Cost = 1; 1271 switch (VT.getSimpleVT().SimpleTy) { 1272 default: 1273 return TargetLowering::findRepresentativeClass(VT); 1274 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1275 RRC = (Subtarget->is64Bit() 1276 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1277 break; 1278 case MVT::x86mmx: 1279 RRC = X86::VR64RegisterClass; 1280 break; 1281 case MVT::f32: case MVT::f64: 1282 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1283 case MVT::v4f32: case MVT::v2f64: 1284 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1285 case MVT::v4f64: 1286 RRC = X86::VR128RegisterClass; 1287 break; 1288 } 1289 return std::make_pair(RRC, Cost); 1290} 1291 1292bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1293 unsigned &Offset) const { 1294 if (!Subtarget->isTargetLinux()) 1295 return false; 1296 1297 if (Subtarget->is64Bit()) { 1298 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1299 Offset = 0x28; 1300 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1301 AddressSpace = 256; 1302 else 1303 AddressSpace = 257; 1304 } else { 1305 // %gs:0x14 on i386 1306 Offset = 0x14; 1307 AddressSpace = 256; 1308 } 1309 return true; 1310} 1311 1312 1313//===----------------------------------------------------------------------===// 1314// Return Value Calling Convention Implementation 1315//===----------------------------------------------------------------------===// 1316 1317#include "X86GenCallingConv.inc" 1318 1319bool 1320X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1321 MachineFunction &MF, bool isVarArg, 1322 const SmallVectorImpl<ISD::OutputArg> &Outs, 1323 LLVMContext &Context) const { 1324 SmallVector<CCValAssign, 16> RVLocs; 1325 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1326 RVLocs, Context); 1327 return CCInfo.CheckReturn(Outs, RetCC_X86); 1328} 1329 1330SDValue 1331X86TargetLowering::LowerReturn(SDValue Chain, 1332 CallingConv::ID CallConv, bool isVarArg, 1333 const SmallVectorImpl<ISD::OutputArg> &Outs, 1334 const SmallVectorImpl<SDValue> &OutVals, 1335 DebugLoc dl, SelectionDAG &DAG) const { 1336 MachineFunction &MF = DAG.getMachineFunction(); 1337 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1338 1339 SmallVector<CCValAssign, 16> RVLocs; 1340 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1341 RVLocs, *DAG.getContext()); 1342 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1343 1344 // Add the regs to the liveout set for the function. 1345 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1346 for (unsigned i = 0; i != RVLocs.size(); ++i) 1347 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1348 MRI.addLiveOut(RVLocs[i].getLocReg()); 1349 1350 SDValue Flag; 1351 1352 SmallVector<SDValue, 6> RetOps; 1353 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1354 // Operand #1 = Bytes To Pop 1355 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1356 MVT::i16)); 1357 1358 // Copy the result values into the output registers. 1359 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1360 CCValAssign &VA = RVLocs[i]; 1361 assert(VA.isRegLoc() && "Can only return in registers!"); 1362 SDValue ValToCopy = OutVals[i]; 1363 EVT ValVT = ValToCopy.getValueType(); 1364 1365 // If this is x86-64, and we disabled SSE, we can't return FP values, 1366 // or SSE or MMX vectors. 1367 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1368 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1369 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1370 report_fatal_error("SSE register return with SSE disabled"); 1371 } 1372 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1373 // llvm-gcc has never done it right and no one has noticed, so this 1374 // should be OK for now. 1375 if (ValVT == MVT::f64 && 1376 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1377 report_fatal_error("SSE2 register return with SSE2 disabled"); 1378 1379 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1380 // the RET instruction and handled by the FP Stackifier. 1381 if (VA.getLocReg() == X86::ST0 || 1382 VA.getLocReg() == X86::ST1) { 1383 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1384 // change the value to the FP stack register class. 1385 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1386 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1387 RetOps.push_back(ValToCopy); 1388 // Don't emit a copytoreg. 1389 continue; 1390 } 1391 1392 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1393 // which is returned in RAX / RDX. 1394 if (Subtarget->is64Bit()) { 1395 if (ValVT == MVT::x86mmx) { 1396 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1397 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1398 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1399 ValToCopy); 1400 // If we don't have SSE2 available, convert to v4f32 so the generated 1401 // register is legal. 1402 if (!Subtarget->hasSSE2()) 1403 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1404 } 1405 } 1406 } 1407 1408 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1409 Flag = Chain.getValue(1); 1410 } 1411 1412 // The x86-64 ABI for returning structs by value requires that we copy 1413 // the sret argument into %rax for the return. We saved the argument into 1414 // a virtual register in the entry block, so now we copy the value out 1415 // and into %rax. 1416 if (Subtarget->is64Bit() && 1417 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1418 MachineFunction &MF = DAG.getMachineFunction(); 1419 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1420 unsigned Reg = FuncInfo->getSRetReturnReg(); 1421 assert(Reg && 1422 "SRetReturnReg should have been set in LowerFormalArguments()."); 1423 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1424 1425 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1426 Flag = Chain.getValue(1); 1427 1428 // RAX now acts like a return value. 1429 MRI.addLiveOut(X86::RAX); 1430 } 1431 1432 RetOps[0] = Chain; // Update chain. 1433 1434 // Add the flag if we have it. 1435 if (Flag.getNode()) 1436 RetOps.push_back(Flag); 1437 1438 return DAG.getNode(X86ISD::RET_FLAG, dl, 1439 MVT::Other, &RetOps[0], RetOps.size()); 1440} 1441 1442bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1443 if (N->getNumValues() != 1) 1444 return false; 1445 if (!N->hasNUsesOfValue(1, 0)) 1446 return false; 1447 1448 SDNode *Copy = *N->use_begin(); 1449 if (Copy->getOpcode() != ISD::CopyToReg && 1450 Copy->getOpcode() != ISD::FP_EXTEND) 1451 return false; 1452 1453 bool HasRet = false; 1454 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1455 UI != UE; ++UI) { 1456 if (UI->getOpcode() != X86ISD::RET_FLAG) 1457 return false; 1458 HasRet = true; 1459 } 1460 1461 return HasRet; 1462} 1463 1464EVT 1465X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1466 ISD::NodeType ExtendKind) const { 1467 MVT ReturnMVT; 1468 // TODO: Is this also valid on 32-bit? 1469 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1470 ReturnMVT = MVT::i8; 1471 else 1472 ReturnMVT = MVT::i32; 1473 1474 EVT MinVT = getRegisterType(Context, ReturnMVT); 1475 return VT.bitsLT(MinVT) ? MinVT : VT; 1476} 1477 1478/// LowerCallResult - Lower the result values of a call into the 1479/// appropriate copies out of appropriate physical registers. 1480/// 1481SDValue 1482X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1483 CallingConv::ID CallConv, bool isVarArg, 1484 const SmallVectorImpl<ISD::InputArg> &Ins, 1485 DebugLoc dl, SelectionDAG &DAG, 1486 SmallVectorImpl<SDValue> &InVals) const { 1487 1488 // Assign locations to each value returned by this call. 1489 SmallVector<CCValAssign, 16> RVLocs; 1490 bool Is64Bit = Subtarget->is64Bit(); 1491 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1492 getTargetMachine(), RVLocs, *DAG.getContext()); 1493 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1494 1495 // Copy all of the result registers out of their specified physreg. 1496 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1497 CCValAssign &VA = RVLocs[i]; 1498 EVT CopyVT = VA.getValVT(); 1499 1500 // If this is x86-64, and we disabled SSE, we can't return FP values 1501 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1502 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1503 report_fatal_error("SSE register return with SSE disabled"); 1504 } 1505 1506 SDValue Val; 1507 1508 // If this is a call to a function that returns an fp value on the floating 1509 // point stack, we must guarantee the the value is popped from the stack, so 1510 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1511 // if the return value is not used. We use the FpPOP_RETVAL instruction 1512 // instead. 1513 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1514 // If we prefer to use the value in xmm registers, copy it out as f80 and 1515 // use a truncate to move it from fp stack reg to xmm reg. 1516 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1517 SDValue Ops[] = { Chain, InFlag }; 1518 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1519 MVT::Other, MVT::Glue, Ops, 2), 1); 1520 Val = Chain.getValue(0); 1521 1522 // Round the f80 to the right size, which also moves it to the appropriate 1523 // xmm register. 1524 if (CopyVT != VA.getValVT()) 1525 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1526 // This truncation won't change the value. 1527 DAG.getIntPtrConstant(1)); 1528 } else { 1529 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1530 CopyVT, InFlag).getValue(1); 1531 Val = Chain.getValue(0); 1532 } 1533 InFlag = Chain.getValue(2); 1534 InVals.push_back(Val); 1535 } 1536 1537 return Chain; 1538} 1539 1540 1541//===----------------------------------------------------------------------===// 1542// C & StdCall & Fast Calling Convention implementation 1543//===----------------------------------------------------------------------===// 1544// StdCall calling convention seems to be standard for many Windows' API 1545// routines and around. It differs from C calling convention just a little: 1546// callee should clean up the stack, not caller. Symbols should be also 1547// decorated in some fancy way :) It doesn't support any vector arguments. 1548// For info on fast calling convention see Fast Calling Convention (tail call) 1549// implementation LowerX86_32FastCCCallTo. 1550 1551/// CallIsStructReturn - Determines whether a call uses struct return 1552/// semantics. 1553static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1554 if (Outs.empty()) 1555 return false; 1556 1557 return Outs[0].Flags.isSRet(); 1558} 1559 1560/// ArgsAreStructReturn - Determines whether a function uses struct 1561/// return semantics. 1562static bool 1563ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1564 if (Ins.empty()) 1565 return false; 1566 1567 return Ins[0].Flags.isSRet(); 1568} 1569 1570/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1571/// by "Src" to address "Dst" with size and alignment information specified by 1572/// the specific parameter attribute. The copy will be passed as a byval 1573/// function parameter. 1574static SDValue 1575CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1576 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1577 DebugLoc dl) { 1578 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1579 1580 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1581 /*isVolatile*/false, /*AlwaysInline=*/true, 1582 MachinePointerInfo(), MachinePointerInfo()); 1583} 1584 1585/// IsTailCallConvention - Return true if the calling convention is one that 1586/// supports tail call optimization. 1587static bool IsTailCallConvention(CallingConv::ID CC) { 1588 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1589} 1590 1591bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1592 if (!CI->isTailCall()) 1593 return false; 1594 1595 CallSite CS(CI); 1596 CallingConv::ID CalleeCC = CS.getCallingConv(); 1597 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1598 return false; 1599 1600 return true; 1601} 1602 1603/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1604/// a tailcall target by changing its ABI. 1605static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1606 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1607} 1608 1609SDValue 1610X86TargetLowering::LowerMemArgument(SDValue Chain, 1611 CallingConv::ID CallConv, 1612 const SmallVectorImpl<ISD::InputArg> &Ins, 1613 DebugLoc dl, SelectionDAG &DAG, 1614 const CCValAssign &VA, 1615 MachineFrameInfo *MFI, 1616 unsigned i) const { 1617 // Create the nodes corresponding to a load from this parameter slot. 1618 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1619 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1620 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1621 EVT ValVT; 1622 1623 // If value is passed by pointer we have address passed instead of the value 1624 // itself. 1625 if (VA.getLocInfo() == CCValAssign::Indirect) 1626 ValVT = VA.getLocVT(); 1627 else 1628 ValVT = VA.getValVT(); 1629 1630 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1631 // changed with more analysis. 1632 // In case of tail call optimization mark all arguments mutable. Since they 1633 // could be overwritten by lowering of arguments in case of a tail call. 1634 if (Flags.isByVal()) { 1635 unsigned Bytes = Flags.getByValSize(); 1636 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1637 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1638 return DAG.getFrameIndex(FI, getPointerTy()); 1639 } else { 1640 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1641 VA.getLocMemOffset(), isImmutable); 1642 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1643 return DAG.getLoad(ValVT, dl, Chain, FIN, 1644 MachinePointerInfo::getFixedStack(FI), 1645 false, false, 0); 1646 } 1647} 1648 1649SDValue 1650X86TargetLowering::LowerFormalArguments(SDValue Chain, 1651 CallingConv::ID CallConv, 1652 bool isVarArg, 1653 const SmallVectorImpl<ISD::InputArg> &Ins, 1654 DebugLoc dl, 1655 SelectionDAG &DAG, 1656 SmallVectorImpl<SDValue> &InVals) 1657 const { 1658 MachineFunction &MF = DAG.getMachineFunction(); 1659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1660 1661 const Function* Fn = MF.getFunction(); 1662 if (Fn->hasExternalLinkage() && 1663 Subtarget->isTargetCygMing() && 1664 Fn->getName() == "main") 1665 FuncInfo->setForceFramePointer(true); 1666 1667 MachineFrameInfo *MFI = MF.getFrameInfo(); 1668 bool Is64Bit = Subtarget->is64Bit(); 1669 bool IsWin64 = Subtarget->isTargetWin64(); 1670 1671 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1672 "Var args not supported with calling convention fastcc or ghc"); 1673 1674 // Assign locations to all of the incoming arguments. 1675 SmallVector<CCValAssign, 16> ArgLocs; 1676 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1677 ArgLocs, *DAG.getContext()); 1678 1679 // Allocate shadow area for Win64 1680 if (IsWin64) { 1681 CCInfo.AllocateStack(32, 8); 1682 } 1683 1684 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1685 1686 unsigned LastVal = ~0U; 1687 SDValue ArgValue; 1688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1689 CCValAssign &VA = ArgLocs[i]; 1690 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1691 // places. 1692 assert(VA.getValNo() != LastVal && 1693 "Don't support value assigned to multiple locs yet"); 1694 LastVal = VA.getValNo(); 1695 1696 if (VA.isRegLoc()) { 1697 EVT RegVT = VA.getLocVT(); 1698 TargetRegisterClass *RC = NULL; 1699 if (RegVT == MVT::i32) 1700 RC = X86::GR32RegisterClass; 1701 else if (Is64Bit && RegVT == MVT::i64) 1702 RC = X86::GR64RegisterClass; 1703 else if (RegVT == MVT::f32) 1704 RC = X86::FR32RegisterClass; 1705 else if (RegVT == MVT::f64) 1706 RC = X86::FR64RegisterClass; 1707 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1708 RC = X86::VR256RegisterClass; 1709 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1710 RC = X86::VR128RegisterClass; 1711 else if (RegVT == MVT::x86mmx) 1712 RC = X86::VR64RegisterClass; 1713 else 1714 llvm_unreachable("Unknown argument type!"); 1715 1716 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1717 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1718 1719 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1720 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1721 // right size. 1722 if (VA.getLocInfo() == CCValAssign::SExt) 1723 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1724 DAG.getValueType(VA.getValVT())); 1725 else if (VA.getLocInfo() == CCValAssign::ZExt) 1726 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1727 DAG.getValueType(VA.getValVT())); 1728 else if (VA.getLocInfo() == CCValAssign::BCvt) 1729 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1730 1731 if (VA.isExtInLoc()) { 1732 // Handle MMX values passed in XMM regs. 1733 if (RegVT.isVector()) { 1734 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1735 ArgValue); 1736 } else 1737 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1738 } 1739 } else { 1740 assert(VA.isMemLoc()); 1741 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1742 } 1743 1744 // If value is passed via pointer - do a load. 1745 if (VA.getLocInfo() == CCValAssign::Indirect) 1746 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1747 MachinePointerInfo(), false, false, 0); 1748 1749 InVals.push_back(ArgValue); 1750 } 1751 1752 // The x86-64 ABI for returning structs by value requires that we copy 1753 // the sret argument into %rax for the return. Save the argument into 1754 // a virtual register so that we can access it from the return points. 1755 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1756 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1757 unsigned Reg = FuncInfo->getSRetReturnReg(); 1758 if (!Reg) { 1759 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1760 FuncInfo->setSRetReturnReg(Reg); 1761 } 1762 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1763 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1764 } 1765 1766 unsigned StackSize = CCInfo.getNextStackOffset(); 1767 // Align stack specially for tail calls. 1768 if (FuncIsMadeTailCallSafe(CallConv)) 1769 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1770 1771 // If the function takes variable number of arguments, make a frame index for 1772 // the start of the first vararg value... for expansion of llvm.va_start. 1773 if (isVarArg) { 1774 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1775 CallConv != CallingConv::X86_ThisCall)) { 1776 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1777 } 1778 if (Is64Bit) { 1779 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1780 1781 // FIXME: We should really autogenerate these arrays 1782 static const unsigned GPR64ArgRegsWin64[] = { 1783 X86::RCX, X86::RDX, X86::R8, X86::R9 1784 }; 1785 static const unsigned GPR64ArgRegs64Bit[] = { 1786 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1787 }; 1788 static const unsigned XMMArgRegs64Bit[] = { 1789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1791 }; 1792 const unsigned *GPR64ArgRegs; 1793 unsigned NumXMMRegs = 0; 1794 1795 if (IsWin64) { 1796 // The XMM registers which might contain var arg parameters are shadowed 1797 // in their paired GPR. So we only need to save the GPR to their home 1798 // slots. 1799 TotalNumIntRegs = 4; 1800 GPR64ArgRegs = GPR64ArgRegsWin64; 1801 } else { 1802 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1803 GPR64ArgRegs = GPR64ArgRegs64Bit; 1804 1805 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1806 } 1807 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1808 TotalNumIntRegs); 1809 1810 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1811 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1812 "SSE register cannot be used when SSE is disabled!"); 1813 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1814 "SSE register cannot be used when SSE is disabled!"); 1815 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1816 // Kernel mode asks for SSE to be disabled, so don't push them 1817 // on the stack. 1818 TotalNumXMMRegs = 0; 1819 1820 if (IsWin64) { 1821 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1822 // Get to the caller-allocated home save location. Add 8 to account 1823 // for the return address. 1824 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1825 FuncInfo->setRegSaveFrameIndex( 1826 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1827 // Fixup to set vararg frame on shadow area (4 x i64). 1828 if (NumIntRegs < 4) 1829 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1830 } else { 1831 // For X86-64, if there are vararg parameters that are passed via 1832 // registers, then we must store them to their spots on the stack so they 1833 // may be loaded by deferencing the result of va_next. 1834 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1835 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1836 FuncInfo->setRegSaveFrameIndex( 1837 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1838 false)); 1839 } 1840 1841 // Store the integer parameter registers. 1842 SmallVector<SDValue, 8> MemOps; 1843 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1844 getPointerTy()); 1845 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1846 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1847 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1848 DAG.getIntPtrConstant(Offset)); 1849 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1850 X86::GR64RegisterClass); 1851 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1852 SDValue Store = 1853 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1854 MachinePointerInfo::getFixedStack( 1855 FuncInfo->getRegSaveFrameIndex(), Offset), 1856 false, false, 0); 1857 MemOps.push_back(Store); 1858 Offset += 8; 1859 } 1860 1861 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1862 // Now store the XMM (fp + vector) parameter registers. 1863 SmallVector<SDValue, 11> SaveXMMOps; 1864 SaveXMMOps.push_back(Chain); 1865 1866 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1867 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1868 SaveXMMOps.push_back(ALVal); 1869 1870 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1871 FuncInfo->getRegSaveFrameIndex())); 1872 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1873 FuncInfo->getVarArgsFPOffset())); 1874 1875 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1876 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1877 X86::VR128RegisterClass); 1878 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1879 SaveXMMOps.push_back(Val); 1880 } 1881 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1882 MVT::Other, 1883 &SaveXMMOps[0], SaveXMMOps.size())); 1884 } 1885 1886 if (!MemOps.empty()) 1887 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1888 &MemOps[0], MemOps.size()); 1889 } 1890 } 1891 1892 // Some CCs need callee pop. 1893 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 1894 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1895 } else { 1896 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1897 // If this is an sret function, the return should pop the hidden pointer. 1898 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1899 FuncInfo->setBytesToPopOnReturn(4); 1900 } 1901 1902 if (!Is64Bit) { 1903 // RegSaveFrameIndex is X86-64 only. 1904 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1905 if (CallConv == CallingConv::X86_FastCall || 1906 CallConv == CallingConv::X86_ThisCall) 1907 // fastcc functions can't have varargs. 1908 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1909 } 1910 1911 return Chain; 1912} 1913 1914SDValue 1915X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1916 SDValue StackPtr, SDValue Arg, 1917 DebugLoc dl, SelectionDAG &DAG, 1918 const CCValAssign &VA, 1919 ISD::ArgFlagsTy Flags) const { 1920 unsigned LocMemOffset = VA.getLocMemOffset(); 1921 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1922 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1923 if (Flags.isByVal()) 1924 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1925 1926 return DAG.getStore(Chain, dl, Arg, PtrOff, 1927 MachinePointerInfo::getStack(LocMemOffset), 1928 false, false, 0); 1929} 1930 1931/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1932/// optimization is performed and it is required. 1933SDValue 1934X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1935 SDValue &OutRetAddr, SDValue Chain, 1936 bool IsTailCall, bool Is64Bit, 1937 int FPDiff, DebugLoc dl) const { 1938 // Adjust the Return address stack slot. 1939 EVT VT = getPointerTy(); 1940 OutRetAddr = getReturnAddressFrameIndex(DAG); 1941 1942 // Load the "old" Return address. 1943 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 1944 false, false, 0); 1945 return SDValue(OutRetAddr.getNode(), 1); 1946} 1947 1948/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 1949/// optimization is performed and it is required (FPDiff!=0). 1950static SDValue 1951EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1952 SDValue Chain, SDValue RetAddrFrIdx, 1953 bool Is64Bit, int FPDiff, DebugLoc dl) { 1954 // Store the return address to the appropriate stack slot. 1955 if (!FPDiff) return Chain; 1956 // Calculate the new stack slot for the return address. 1957 int SlotSize = Is64Bit ? 8 : 4; 1958 int NewReturnAddrFI = 1959 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 1960 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1961 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1962 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1963 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 1964 false, false, 0); 1965 return Chain; 1966} 1967 1968SDValue 1969X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1970 CallingConv::ID CallConv, bool isVarArg, 1971 bool &isTailCall, 1972 const SmallVectorImpl<ISD::OutputArg> &Outs, 1973 const SmallVectorImpl<SDValue> &OutVals, 1974 const SmallVectorImpl<ISD::InputArg> &Ins, 1975 DebugLoc dl, SelectionDAG &DAG, 1976 SmallVectorImpl<SDValue> &InVals) const { 1977 MachineFunction &MF = DAG.getMachineFunction(); 1978 bool Is64Bit = Subtarget->is64Bit(); 1979 bool IsWin64 = Subtarget->isTargetWin64(); 1980 bool IsStructRet = CallIsStructReturn(Outs); 1981 bool IsSibcall = false; 1982 1983 if (isTailCall) { 1984 // Check if it's really possible to do a tail call. 1985 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1986 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1987 Outs, OutVals, Ins, DAG); 1988 1989 // Sibcalls are automatically detected tailcalls which do not require 1990 // ABI changes. 1991 if (!GuaranteedTailCallOpt && isTailCall) 1992 IsSibcall = true; 1993 1994 if (isTailCall) 1995 ++NumTailCalls; 1996 } 1997 1998 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1999 "Var args not supported with calling convention fastcc or ghc"); 2000 2001 // Analyze operands of the call, assigning locations to each operand. 2002 SmallVector<CCValAssign, 16> ArgLocs; 2003 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2004 ArgLocs, *DAG.getContext()); 2005 2006 // Allocate shadow area for Win64 2007 if (IsWin64) { 2008 CCInfo.AllocateStack(32, 8); 2009 } 2010 2011 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2012 2013 // Get a count of how many bytes are to be pushed on the stack. 2014 unsigned NumBytes = CCInfo.getNextStackOffset(); 2015 if (IsSibcall) 2016 // This is a sibcall. The memory operands are available in caller's 2017 // own caller's stack. 2018 NumBytes = 0; 2019 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2020 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2021 2022 int FPDiff = 0; 2023 if (isTailCall && !IsSibcall) { 2024 // Lower arguments at fp - stackoffset + fpdiff. 2025 unsigned NumBytesCallerPushed = 2026 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2027 FPDiff = NumBytesCallerPushed - NumBytes; 2028 2029 // Set the delta of movement of the returnaddr stackslot. 2030 // But only set if delta is greater than previous delta. 2031 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2032 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2033 } 2034 2035 if (!IsSibcall) 2036 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2037 2038 SDValue RetAddrFrIdx; 2039 // Load return address for tail calls. 2040 if (isTailCall && FPDiff) 2041 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2042 Is64Bit, FPDiff, dl); 2043 2044 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2045 SmallVector<SDValue, 8> MemOpChains; 2046 SDValue StackPtr; 2047 2048 // Walk the register/memloc assignments, inserting copies/loads. In the case 2049 // of tail call optimization arguments are handle later. 2050 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2051 CCValAssign &VA = ArgLocs[i]; 2052 EVT RegVT = VA.getLocVT(); 2053 SDValue Arg = OutVals[i]; 2054 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2055 bool isByVal = Flags.isByVal(); 2056 2057 // Promote the value if needed. 2058 switch (VA.getLocInfo()) { 2059 default: llvm_unreachable("Unknown loc info!"); 2060 case CCValAssign::Full: break; 2061 case CCValAssign::SExt: 2062 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2063 break; 2064 case CCValAssign::ZExt: 2065 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2066 break; 2067 case CCValAssign::AExt: 2068 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2069 // Special case: passing MMX values in XMM registers. 2070 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2071 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2072 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2073 } else 2074 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2075 break; 2076 case CCValAssign::BCvt: 2077 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2078 break; 2079 case CCValAssign::Indirect: { 2080 // Store the argument. 2081 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2082 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2083 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2084 MachinePointerInfo::getFixedStack(FI), 2085 false, false, 0); 2086 Arg = SpillSlot; 2087 break; 2088 } 2089 } 2090 2091 if (VA.isRegLoc()) { 2092 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2093 if (isVarArg && IsWin64) { 2094 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2095 // shadow reg if callee is a varargs function. 2096 unsigned ShadowReg = 0; 2097 switch (VA.getLocReg()) { 2098 case X86::XMM0: ShadowReg = X86::RCX; break; 2099 case X86::XMM1: ShadowReg = X86::RDX; break; 2100 case X86::XMM2: ShadowReg = X86::R8; break; 2101 case X86::XMM3: ShadowReg = X86::R9; break; 2102 } 2103 if (ShadowReg) 2104 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2105 } 2106 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2107 assert(VA.isMemLoc()); 2108 if (StackPtr.getNode() == 0) 2109 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2110 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2111 dl, DAG, VA, Flags)); 2112 } 2113 } 2114 2115 if (!MemOpChains.empty()) 2116 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2117 &MemOpChains[0], MemOpChains.size()); 2118 2119 // Build a sequence of copy-to-reg nodes chained together with token chain 2120 // and flag operands which copy the outgoing args into registers. 2121 SDValue InFlag; 2122 // Tail call byval lowering might overwrite argument registers so in case of 2123 // tail call optimization the copies to registers are lowered later. 2124 if (!isTailCall) 2125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2126 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2127 RegsToPass[i].second, InFlag); 2128 InFlag = Chain.getValue(1); 2129 } 2130 2131 if (Subtarget->isPICStyleGOT()) { 2132 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2133 // GOT pointer. 2134 if (!isTailCall) { 2135 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2136 DAG.getNode(X86ISD::GlobalBaseReg, 2137 DebugLoc(), getPointerTy()), 2138 InFlag); 2139 InFlag = Chain.getValue(1); 2140 } else { 2141 // If we are tail calling and generating PIC/GOT style code load the 2142 // address of the callee into ECX. The value in ecx is used as target of 2143 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2144 // for tail calls on PIC/GOT architectures. Normally we would just put the 2145 // address of GOT into ebx and then call target@PLT. But for tail calls 2146 // ebx would be restored (since ebx is callee saved) before jumping to the 2147 // target@PLT. 2148 2149 // Note: The actual moving to ECX is done further down. 2150 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2151 if (G && !G->getGlobal()->hasHiddenVisibility() && 2152 !G->getGlobal()->hasProtectedVisibility()) 2153 Callee = LowerGlobalAddress(Callee, DAG); 2154 else if (isa<ExternalSymbolSDNode>(Callee)) 2155 Callee = LowerExternalSymbol(Callee, DAG); 2156 } 2157 } 2158 2159 if (Is64Bit && isVarArg && !IsWin64) { 2160 // From AMD64 ABI document: 2161 // For calls that may call functions that use varargs or stdargs 2162 // (prototype-less calls or calls to functions containing ellipsis (...) in 2163 // the declaration) %al is used as hidden argument to specify the number 2164 // of SSE registers used. The contents of %al do not need to match exactly 2165 // the number of registers, but must be an ubound on the number of SSE 2166 // registers used and is in the range 0 - 8 inclusive. 2167 2168 // Count the number of XMM registers allocated. 2169 static const unsigned XMMArgRegs[] = { 2170 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2171 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2172 }; 2173 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2174 assert((Subtarget->hasXMM() || !NumXMMRegs) 2175 && "SSE registers cannot be used when SSE is disabled"); 2176 2177 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2178 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2179 InFlag = Chain.getValue(1); 2180 } 2181 2182 2183 // For tail calls lower the arguments to the 'real' stack slot. 2184 if (isTailCall) { 2185 // Force all the incoming stack arguments to be loaded from the stack 2186 // before any new outgoing arguments are stored to the stack, because the 2187 // outgoing stack slots may alias the incoming argument stack slots, and 2188 // the alias isn't otherwise explicit. This is slightly more conservative 2189 // than necessary, because it means that each store effectively depends 2190 // on every argument instead of just those arguments it would clobber. 2191 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2192 2193 SmallVector<SDValue, 8> MemOpChains2; 2194 SDValue FIN; 2195 int FI = 0; 2196 // Do not flag preceding copytoreg stuff together with the following stuff. 2197 InFlag = SDValue(); 2198 if (GuaranteedTailCallOpt) { 2199 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2200 CCValAssign &VA = ArgLocs[i]; 2201 if (VA.isRegLoc()) 2202 continue; 2203 assert(VA.isMemLoc()); 2204 SDValue Arg = OutVals[i]; 2205 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2206 // Create frame index. 2207 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2208 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2209 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2210 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2211 2212 if (Flags.isByVal()) { 2213 // Copy relative to framepointer. 2214 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2215 if (StackPtr.getNode() == 0) 2216 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2217 getPointerTy()); 2218 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2219 2220 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2221 ArgChain, 2222 Flags, DAG, dl)); 2223 } else { 2224 // Store relative to framepointer. 2225 MemOpChains2.push_back( 2226 DAG.getStore(ArgChain, dl, Arg, FIN, 2227 MachinePointerInfo::getFixedStack(FI), 2228 false, false, 0)); 2229 } 2230 } 2231 } 2232 2233 if (!MemOpChains2.empty()) 2234 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2235 &MemOpChains2[0], MemOpChains2.size()); 2236 2237 // Copy arguments to their registers. 2238 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2239 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2240 RegsToPass[i].second, InFlag); 2241 InFlag = Chain.getValue(1); 2242 } 2243 InFlag =SDValue(); 2244 2245 // Store the return address to the appropriate stack slot. 2246 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2247 FPDiff, dl); 2248 } 2249 2250 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2251 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2252 // In the 64-bit large code model, we have to make all calls 2253 // through a register, since the call instruction's 32-bit 2254 // pc-relative offset may not be large enough to hold the whole 2255 // address. 2256 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2257 // If the callee is a GlobalAddress node (quite common, every direct call 2258 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2259 // it. 2260 2261 // We should use extra load for direct calls to dllimported functions in 2262 // non-JIT mode. 2263 const GlobalValue *GV = G->getGlobal(); 2264 if (!GV->hasDLLImportLinkage()) { 2265 unsigned char OpFlags = 0; 2266 bool ExtraLoad = false; 2267 unsigned WrapperKind = ISD::DELETED_NODE; 2268 2269 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2270 // external symbols most go through the PLT in PIC mode. If the symbol 2271 // has hidden or protected visibility, or if it is static or local, then 2272 // we don't need to use the PLT - we can directly call it. 2273 if (Subtarget->isTargetELF() && 2274 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2275 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2276 OpFlags = X86II::MO_PLT; 2277 } else if (Subtarget->isPICStyleStubAny() && 2278 (GV->isDeclaration() || GV->isWeakForLinker()) && 2279 (!Subtarget->getTargetTriple().isMacOSX() || 2280 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2281 // PC-relative references to external symbols should go through $stub, 2282 // unless we're building with the leopard linker or later, which 2283 // automatically synthesizes these stubs. 2284 OpFlags = X86II::MO_DARWIN_STUB; 2285 } else if (Subtarget->isPICStyleRIPRel() && 2286 isa<Function>(GV) && 2287 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2288 // If the function is marked as non-lazy, generate an indirect call 2289 // which loads from the GOT directly. This avoids runtime overhead 2290 // at the cost of eager binding (and one extra byte of encoding). 2291 OpFlags = X86II::MO_GOTPCREL; 2292 WrapperKind = X86ISD::WrapperRIP; 2293 ExtraLoad = true; 2294 } 2295 2296 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2297 G->getOffset(), OpFlags); 2298 2299 // Add a wrapper if needed. 2300 if (WrapperKind != ISD::DELETED_NODE) 2301 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2302 // Add extra indirection if needed. 2303 if (ExtraLoad) 2304 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2305 MachinePointerInfo::getGOT(), 2306 false, false, 0); 2307 } 2308 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2309 unsigned char OpFlags = 0; 2310 2311 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2312 // external symbols should go through the PLT. 2313 if (Subtarget->isTargetELF() && 2314 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2315 OpFlags = X86II::MO_PLT; 2316 } else if (Subtarget->isPICStyleStubAny() && 2317 (!Subtarget->getTargetTriple().isMacOSX() || 2318 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2319 // PC-relative references to external symbols should go through $stub, 2320 // unless we're building with the leopard linker or later, which 2321 // automatically synthesizes these stubs. 2322 OpFlags = X86II::MO_DARWIN_STUB; 2323 } 2324 2325 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2326 OpFlags); 2327 } 2328 2329 // Returns a chain & a flag for retval copy to use. 2330 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2331 SmallVector<SDValue, 8> Ops; 2332 2333 if (!IsSibcall && isTailCall) { 2334 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2335 DAG.getIntPtrConstant(0, true), InFlag); 2336 InFlag = Chain.getValue(1); 2337 } 2338 2339 Ops.push_back(Chain); 2340 Ops.push_back(Callee); 2341 2342 if (isTailCall) 2343 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2344 2345 // Add argument registers to the end of the list so that they are known live 2346 // into the call. 2347 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2348 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2349 RegsToPass[i].second.getValueType())); 2350 2351 // Add an implicit use GOT pointer in EBX. 2352 if (!isTailCall && Subtarget->isPICStyleGOT()) 2353 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2354 2355 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2356 if (Is64Bit && isVarArg && !IsWin64) 2357 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2358 2359 if (InFlag.getNode()) 2360 Ops.push_back(InFlag); 2361 2362 if (isTailCall) { 2363 // We used to do: 2364 //// If this is the first return lowered for this function, add the regs 2365 //// to the liveout set for the function. 2366 // This isn't right, although it's probably harmless on x86; liveouts 2367 // should be computed from returns not tail calls. Consider a void 2368 // function making a tail call to a function returning int. 2369 return DAG.getNode(X86ISD::TC_RETURN, dl, 2370 NodeTys, &Ops[0], Ops.size()); 2371 } 2372 2373 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2374 InFlag = Chain.getValue(1); 2375 2376 // Create the CALLSEQ_END node. 2377 unsigned NumBytesForCalleeToPush; 2378 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2379 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2380 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2381 // If this is a call to a struct-return function, the callee 2382 // pops the hidden struct pointer, so we have to push it back. 2383 // This is common for Darwin/X86, Linux & Mingw32 targets. 2384 NumBytesForCalleeToPush = 4; 2385 else 2386 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2387 2388 // Returns a flag for retval copy to use. 2389 if (!IsSibcall) { 2390 Chain = DAG.getCALLSEQ_END(Chain, 2391 DAG.getIntPtrConstant(NumBytes, true), 2392 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2393 true), 2394 InFlag); 2395 InFlag = Chain.getValue(1); 2396 } 2397 2398 // Handle result values, copying them out of physregs into vregs that we 2399 // return. 2400 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2401 Ins, dl, DAG, InVals); 2402} 2403 2404 2405//===----------------------------------------------------------------------===// 2406// Fast Calling Convention (tail call) implementation 2407//===----------------------------------------------------------------------===// 2408 2409// Like std call, callee cleans arguments, convention except that ECX is 2410// reserved for storing the tail called function address. Only 2 registers are 2411// free for argument passing (inreg). Tail call optimization is performed 2412// provided: 2413// * tailcallopt is enabled 2414// * caller/callee are fastcc 2415// On X86_64 architecture with GOT-style position independent code only local 2416// (within module) calls are supported at the moment. 2417// To keep the stack aligned according to platform abi the function 2418// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2419// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2420// If a tail called function callee has more arguments than the caller the 2421// caller needs to make sure that there is room to move the RETADDR to. This is 2422// achieved by reserving an area the size of the argument delta right after the 2423// original REtADDR, but before the saved framepointer or the spilled registers 2424// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2425// stack layout: 2426// arg1 2427// arg2 2428// RETADDR 2429// [ new RETADDR 2430// move area ] 2431// (possible EBP) 2432// ESI 2433// EDI 2434// local1 .. 2435 2436/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2437/// for a 16 byte align requirement. 2438unsigned 2439X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2440 SelectionDAG& DAG) const { 2441 MachineFunction &MF = DAG.getMachineFunction(); 2442 const TargetMachine &TM = MF.getTarget(); 2443 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2444 unsigned StackAlignment = TFI.getStackAlignment(); 2445 uint64_t AlignMask = StackAlignment - 1; 2446 int64_t Offset = StackSize; 2447 uint64_t SlotSize = TD->getPointerSize(); 2448 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2449 // Number smaller than 12 so just add the difference. 2450 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2451 } else { 2452 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2453 Offset = ((~AlignMask) & Offset) + StackAlignment + 2454 (StackAlignment-SlotSize); 2455 } 2456 return Offset; 2457} 2458 2459/// MatchingStackOffset - Return true if the given stack call argument is 2460/// already available in the same position (relatively) of the caller's 2461/// incoming argument stack. 2462static 2463bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2464 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2465 const X86InstrInfo *TII) { 2466 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2467 int FI = INT_MAX; 2468 if (Arg.getOpcode() == ISD::CopyFromReg) { 2469 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2470 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2471 return false; 2472 MachineInstr *Def = MRI->getVRegDef(VR); 2473 if (!Def) 2474 return false; 2475 if (!Flags.isByVal()) { 2476 if (!TII->isLoadFromStackSlot(Def, FI)) 2477 return false; 2478 } else { 2479 unsigned Opcode = Def->getOpcode(); 2480 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2481 Def->getOperand(1).isFI()) { 2482 FI = Def->getOperand(1).getIndex(); 2483 Bytes = Flags.getByValSize(); 2484 } else 2485 return false; 2486 } 2487 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2488 if (Flags.isByVal()) 2489 // ByVal argument is passed in as a pointer but it's now being 2490 // dereferenced. e.g. 2491 // define @foo(%struct.X* %A) { 2492 // tail call @bar(%struct.X* byval %A) 2493 // } 2494 return false; 2495 SDValue Ptr = Ld->getBasePtr(); 2496 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2497 if (!FINode) 2498 return false; 2499 FI = FINode->getIndex(); 2500 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2501 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2502 FI = FINode->getIndex(); 2503 Bytes = Flags.getByValSize(); 2504 } else 2505 return false; 2506 2507 assert(FI != INT_MAX); 2508 if (!MFI->isFixedObjectIndex(FI)) 2509 return false; 2510 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2511} 2512 2513/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2514/// for tail call optimization. Targets which want to do tail call 2515/// optimization should implement this function. 2516bool 2517X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2518 CallingConv::ID CalleeCC, 2519 bool isVarArg, 2520 bool isCalleeStructRet, 2521 bool isCallerStructRet, 2522 const SmallVectorImpl<ISD::OutputArg> &Outs, 2523 const SmallVectorImpl<SDValue> &OutVals, 2524 const SmallVectorImpl<ISD::InputArg> &Ins, 2525 SelectionDAG& DAG) const { 2526 if (!IsTailCallConvention(CalleeCC) && 2527 CalleeCC != CallingConv::C) 2528 return false; 2529 2530 // If -tailcallopt is specified, make fastcc functions tail-callable. 2531 const MachineFunction &MF = DAG.getMachineFunction(); 2532 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2533 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2534 bool CCMatch = CallerCC == CalleeCC; 2535 2536 if (GuaranteedTailCallOpt) { 2537 if (IsTailCallConvention(CalleeCC) && CCMatch) 2538 return true; 2539 return false; 2540 } 2541 2542 // Look for obvious safe cases to perform tail call optimization that do not 2543 // require ABI changes. This is what gcc calls sibcall. 2544 2545 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2546 // emit a special epilogue. 2547 if (RegInfo->needsStackRealignment(MF)) 2548 return false; 2549 2550 // Also avoid sibcall optimization if either caller or callee uses struct 2551 // return semantics. 2552 if (isCalleeStructRet || isCallerStructRet) 2553 return false; 2554 2555 // An stdcall caller is expected to clean up its arguments; the callee 2556 // isn't going to do that. 2557 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2558 return false; 2559 2560 // Do not sibcall optimize vararg calls unless all arguments are passed via 2561 // registers. 2562 if (isVarArg && !Outs.empty()) { 2563 2564 // Optimizing for varargs on Win64 is unlikely to be safe without 2565 // additional testing. 2566 if (Subtarget->isTargetWin64()) 2567 return false; 2568 2569 SmallVector<CCValAssign, 16> ArgLocs; 2570 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2571 getTargetMachine(), ArgLocs, *DAG.getContext()); 2572 2573 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2574 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2575 if (!ArgLocs[i].isRegLoc()) 2576 return false; 2577 } 2578 2579 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2580 // Therefore if it's not used by the call it is not safe to optimize this into 2581 // a sibcall. 2582 bool Unused = false; 2583 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2584 if (!Ins[i].Used) { 2585 Unused = true; 2586 break; 2587 } 2588 } 2589 if (Unused) { 2590 SmallVector<CCValAssign, 16> RVLocs; 2591 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2592 getTargetMachine(), RVLocs, *DAG.getContext()); 2593 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2594 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2595 CCValAssign &VA = RVLocs[i]; 2596 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2597 return false; 2598 } 2599 } 2600 2601 // If the calling conventions do not match, then we'd better make sure the 2602 // results are returned in the same way as what the caller expects. 2603 if (!CCMatch) { 2604 SmallVector<CCValAssign, 16> RVLocs1; 2605 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2606 getTargetMachine(), RVLocs1, *DAG.getContext()); 2607 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2608 2609 SmallVector<CCValAssign, 16> RVLocs2; 2610 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2611 getTargetMachine(), RVLocs2, *DAG.getContext()); 2612 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2613 2614 if (RVLocs1.size() != RVLocs2.size()) 2615 return false; 2616 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2617 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2618 return false; 2619 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2620 return false; 2621 if (RVLocs1[i].isRegLoc()) { 2622 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2623 return false; 2624 } else { 2625 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2626 return false; 2627 } 2628 } 2629 } 2630 2631 // If the callee takes no arguments then go on to check the results of the 2632 // call. 2633 if (!Outs.empty()) { 2634 // Check if stack adjustment is needed. For now, do not do this if any 2635 // argument is passed on the stack. 2636 SmallVector<CCValAssign, 16> ArgLocs; 2637 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2638 getTargetMachine(), ArgLocs, *DAG.getContext()); 2639 2640 // Allocate shadow area for Win64 2641 if (Subtarget->isTargetWin64()) { 2642 CCInfo.AllocateStack(32, 8); 2643 } 2644 2645 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2646 if (CCInfo.getNextStackOffset()) { 2647 MachineFunction &MF = DAG.getMachineFunction(); 2648 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2649 return false; 2650 2651 // Check if the arguments are already laid out in the right way as 2652 // the caller's fixed stack objects. 2653 MachineFrameInfo *MFI = MF.getFrameInfo(); 2654 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2655 const X86InstrInfo *TII = 2656 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2657 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2658 CCValAssign &VA = ArgLocs[i]; 2659 SDValue Arg = OutVals[i]; 2660 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2661 if (VA.getLocInfo() == CCValAssign::Indirect) 2662 return false; 2663 if (!VA.isRegLoc()) { 2664 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2665 MFI, MRI, TII)) 2666 return false; 2667 } 2668 } 2669 } 2670 2671 // If the tailcall address may be in a register, then make sure it's 2672 // possible to register allocate for it. In 32-bit, the call address can 2673 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2674 // callee-saved registers are restored. These happen to be the same 2675 // registers used to pass 'inreg' arguments so watch out for those. 2676 if (!Subtarget->is64Bit() && 2677 !isa<GlobalAddressSDNode>(Callee) && 2678 !isa<ExternalSymbolSDNode>(Callee)) { 2679 unsigned NumInRegs = 0; 2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2681 CCValAssign &VA = ArgLocs[i]; 2682 if (!VA.isRegLoc()) 2683 continue; 2684 unsigned Reg = VA.getLocReg(); 2685 switch (Reg) { 2686 default: break; 2687 case X86::EAX: case X86::EDX: case X86::ECX: 2688 if (++NumInRegs == 3) 2689 return false; 2690 break; 2691 } 2692 } 2693 } 2694 } 2695 2696 return true; 2697} 2698 2699FastISel * 2700X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2701 return X86::createFastISel(funcInfo); 2702} 2703 2704 2705//===----------------------------------------------------------------------===// 2706// Other Lowering Hooks 2707//===----------------------------------------------------------------------===// 2708 2709static bool MayFoldLoad(SDValue Op) { 2710 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2711} 2712 2713static bool MayFoldIntoStore(SDValue Op) { 2714 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2715} 2716 2717static bool isTargetShuffle(unsigned Opcode) { 2718 switch(Opcode) { 2719 default: return false; 2720 case X86ISD::PSHUFD: 2721 case X86ISD::PSHUFHW: 2722 case X86ISD::PSHUFLW: 2723 case X86ISD::SHUFPD: 2724 case X86ISD::PALIGN: 2725 case X86ISD::SHUFPS: 2726 case X86ISD::MOVLHPS: 2727 case X86ISD::MOVLHPD: 2728 case X86ISD::MOVHLPS: 2729 case X86ISD::MOVLPS: 2730 case X86ISD::MOVLPD: 2731 case X86ISD::MOVSHDUP: 2732 case X86ISD::MOVSLDUP: 2733 case X86ISD::MOVDDUP: 2734 case X86ISD::MOVSS: 2735 case X86ISD::MOVSD: 2736 case X86ISD::UNPCKLPS: 2737 case X86ISD::UNPCKLPD: 2738 case X86ISD::VUNPCKLPSY: 2739 case X86ISD::VUNPCKLPDY: 2740 case X86ISD::PUNPCKLWD: 2741 case X86ISD::PUNPCKLBW: 2742 case X86ISD::PUNPCKLDQ: 2743 case X86ISD::PUNPCKLQDQ: 2744 case X86ISD::UNPCKHPS: 2745 case X86ISD::UNPCKHPD: 2746 case X86ISD::VUNPCKHPSY: 2747 case X86ISD::VUNPCKHPDY: 2748 case X86ISD::PUNPCKHWD: 2749 case X86ISD::PUNPCKHBW: 2750 case X86ISD::PUNPCKHDQ: 2751 case X86ISD::PUNPCKHQDQ: 2752 case X86ISD::VPERMILPS: 2753 case X86ISD::VPERMILPSY: 2754 case X86ISD::VPERMILPD: 2755 case X86ISD::VPERMILPDY: 2756 return true; 2757 } 2758 return false; 2759} 2760 2761static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2762 SDValue V1, SelectionDAG &DAG) { 2763 switch(Opc) { 2764 default: llvm_unreachable("Unknown x86 shuffle node"); 2765 case X86ISD::MOVSHDUP: 2766 case X86ISD::MOVSLDUP: 2767 case X86ISD::MOVDDUP: 2768 return DAG.getNode(Opc, dl, VT, V1); 2769 } 2770 2771 return SDValue(); 2772} 2773 2774static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2775 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2776 switch(Opc) { 2777 default: llvm_unreachable("Unknown x86 shuffle node"); 2778 case X86ISD::PSHUFD: 2779 case X86ISD::PSHUFHW: 2780 case X86ISD::PSHUFLW: 2781 case X86ISD::VPERMILPS: 2782 case X86ISD::VPERMILPSY: 2783 case X86ISD::VPERMILPD: 2784 case X86ISD::VPERMILPDY: 2785 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2786 } 2787 2788 return SDValue(); 2789} 2790 2791static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2792 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2793 switch(Opc) { 2794 default: llvm_unreachable("Unknown x86 shuffle node"); 2795 case X86ISD::PALIGN: 2796 case X86ISD::SHUFPD: 2797 case X86ISD::SHUFPS: 2798 return DAG.getNode(Opc, dl, VT, V1, V2, 2799 DAG.getConstant(TargetMask, MVT::i8)); 2800 } 2801 return SDValue(); 2802} 2803 2804static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2805 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2806 switch(Opc) { 2807 default: llvm_unreachable("Unknown x86 shuffle node"); 2808 case X86ISD::MOVLHPS: 2809 case X86ISD::MOVLHPD: 2810 case X86ISD::MOVHLPS: 2811 case X86ISD::MOVLPS: 2812 case X86ISD::MOVLPD: 2813 case X86ISD::MOVSS: 2814 case X86ISD::MOVSD: 2815 case X86ISD::UNPCKLPS: 2816 case X86ISD::UNPCKLPD: 2817 case X86ISD::VUNPCKLPSY: 2818 case X86ISD::VUNPCKLPDY: 2819 case X86ISD::PUNPCKLWD: 2820 case X86ISD::PUNPCKLBW: 2821 case X86ISD::PUNPCKLDQ: 2822 case X86ISD::PUNPCKLQDQ: 2823 case X86ISD::UNPCKHPS: 2824 case X86ISD::UNPCKHPD: 2825 case X86ISD::VUNPCKHPSY: 2826 case X86ISD::VUNPCKHPDY: 2827 case X86ISD::PUNPCKHWD: 2828 case X86ISD::PUNPCKHBW: 2829 case X86ISD::PUNPCKHDQ: 2830 case X86ISD::PUNPCKHQDQ: 2831 return DAG.getNode(Opc, dl, VT, V1, V2); 2832 } 2833 return SDValue(); 2834} 2835 2836SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2837 MachineFunction &MF = DAG.getMachineFunction(); 2838 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2839 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2840 2841 if (ReturnAddrIndex == 0) { 2842 // Set up a frame object for the return address. 2843 uint64_t SlotSize = TD->getPointerSize(); 2844 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2845 false); 2846 FuncInfo->setRAIndex(ReturnAddrIndex); 2847 } 2848 2849 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2850} 2851 2852 2853bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2854 bool hasSymbolicDisplacement) { 2855 // Offset should fit into 32 bit immediate field. 2856 if (!isInt<32>(Offset)) 2857 return false; 2858 2859 // If we don't have a symbolic displacement - we don't have any extra 2860 // restrictions. 2861 if (!hasSymbolicDisplacement) 2862 return true; 2863 2864 // FIXME: Some tweaks might be needed for medium code model. 2865 if (M != CodeModel::Small && M != CodeModel::Kernel) 2866 return false; 2867 2868 // For small code model we assume that latest object is 16MB before end of 31 2869 // bits boundary. We may also accept pretty large negative constants knowing 2870 // that all objects are in the positive half of address space. 2871 if (M == CodeModel::Small && Offset < 16*1024*1024) 2872 return true; 2873 2874 // For kernel code model we know that all object resist in the negative half 2875 // of 32bits address space. We may not accept negative offsets, since they may 2876 // be just off and we may accept pretty large positive ones. 2877 if (M == CodeModel::Kernel && Offset > 0) 2878 return true; 2879 2880 return false; 2881} 2882 2883/// isCalleePop - Determines whether the callee is required to pop its 2884/// own arguments. Callee pop is necessary to support tail calls. 2885bool X86::isCalleePop(CallingConv::ID CallingConv, 2886 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 2887 if (IsVarArg) 2888 return false; 2889 2890 switch (CallingConv) { 2891 default: 2892 return false; 2893 case CallingConv::X86_StdCall: 2894 return !is64Bit; 2895 case CallingConv::X86_FastCall: 2896 return !is64Bit; 2897 case CallingConv::X86_ThisCall: 2898 return !is64Bit; 2899 case CallingConv::Fast: 2900 return TailCallOpt; 2901 case CallingConv::GHC: 2902 return TailCallOpt; 2903 } 2904} 2905 2906/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2907/// specific condition code, returning the condition code and the LHS/RHS of the 2908/// comparison to make. 2909static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2910 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2911 if (!isFP) { 2912 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2913 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2914 // X > -1 -> X == 0, jump !sign. 2915 RHS = DAG.getConstant(0, RHS.getValueType()); 2916 return X86::COND_NS; 2917 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2918 // X < 0 -> X == 0, jump on sign. 2919 return X86::COND_S; 2920 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2921 // X < 1 -> X <= 0 2922 RHS = DAG.getConstant(0, RHS.getValueType()); 2923 return X86::COND_LE; 2924 } 2925 } 2926 2927 switch (SetCCOpcode) { 2928 default: llvm_unreachable("Invalid integer condition!"); 2929 case ISD::SETEQ: return X86::COND_E; 2930 case ISD::SETGT: return X86::COND_G; 2931 case ISD::SETGE: return X86::COND_GE; 2932 case ISD::SETLT: return X86::COND_L; 2933 case ISD::SETLE: return X86::COND_LE; 2934 case ISD::SETNE: return X86::COND_NE; 2935 case ISD::SETULT: return X86::COND_B; 2936 case ISD::SETUGT: return X86::COND_A; 2937 case ISD::SETULE: return X86::COND_BE; 2938 case ISD::SETUGE: return X86::COND_AE; 2939 } 2940 } 2941 2942 // First determine if it is required or is profitable to flip the operands. 2943 2944 // If LHS is a foldable load, but RHS is not, flip the condition. 2945 if (ISD::isNON_EXTLoad(LHS.getNode()) && 2946 !ISD::isNON_EXTLoad(RHS.getNode())) { 2947 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2948 std::swap(LHS, RHS); 2949 } 2950 2951 switch (SetCCOpcode) { 2952 default: break; 2953 case ISD::SETOLT: 2954 case ISD::SETOLE: 2955 case ISD::SETUGT: 2956 case ISD::SETUGE: 2957 std::swap(LHS, RHS); 2958 break; 2959 } 2960 2961 // On a floating point condition, the flags are set as follows: 2962 // ZF PF CF op 2963 // 0 | 0 | 0 | X > Y 2964 // 0 | 0 | 1 | X < Y 2965 // 1 | 0 | 0 | X == Y 2966 // 1 | 1 | 1 | unordered 2967 switch (SetCCOpcode) { 2968 default: llvm_unreachable("Condcode should be pre-legalized away"); 2969 case ISD::SETUEQ: 2970 case ISD::SETEQ: return X86::COND_E; 2971 case ISD::SETOLT: // flipped 2972 case ISD::SETOGT: 2973 case ISD::SETGT: return X86::COND_A; 2974 case ISD::SETOLE: // flipped 2975 case ISD::SETOGE: 2976 case ISD::SETGE: return X86::COND_AE; 2977 case ISD::SETUGT: // flipped 2978 case ISD::SETULT: 2979 case ISD::SETLT: return X86::COND_B; 2980 case ISD::SETUGE: // flipped 2981 case ISD::SETULE: 2982 case ISD::SETLE: return X86::COND_BE; 2983 case ISD::SETONE: 2984 case ISD::SETNE: return X86::COND_NE; 2985 case ISD::SETUO: return X86::COND_P; 2986 case ISD::SETO: return X86::COND_NP; 2987 case ISD::SETOEQ: 2988 case ISD::SETUNE: return X86::COND_INVALID; 2989 } 2990} 2991 2992/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2993/// code. Current x86 isa includes the following FP cmov instructions: 2994/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2995static bool hasFPCMov(unsigned X86CC) { 2996 switch (X86CC) { 2997 default: 2998 return false; 2999 case X86::COND_B: 3000 case X86::COND_BE: 3001 case X86::COND_E: 3002 case X86::COND_P: 3003 case X86::COND_A: 3004 case X86::COND_AE: 3005 case X86::COND_NE: 3006 case X86::COND_NP: 3007 return true; 3008 } 3009} 3010 3011/// isFPImmLegal - Returns true if the target can instruction select the 3012/// specified FP immediate natively. If false, the legalizer will 3013/// materialize the FP immediate as a load from a constant pool. 3014bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3015 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3016 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3017 return true; 3018 } 3019 return false; 3020} 3021 3022/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3023/// the specified range (L, H]. 3024static bool isUndefOrInRange(int Val, int Low, int Hi) { 3025 return (Val < 0) || (Val >= Low && Val < Hi); 3026} 3027 3028/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3029/// specified value. 3030static bool isUndefOrEqual(int Val, int CmpVal) { 3031 if (Val < 0 || Val == CmpVal) 3032 return true; 3033 return false; 3034} 3035 3036/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3037/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3038/// the second operand. 3039static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3040 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3041 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3042 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3043 return (Mask[0] < 2 && Mask[1] < 2); 3044 return false; 3045} 3046 3047bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3048 SmallVector<int, 8> M; 3049 N->getMask(M); 3050 return ::isPSHUFDMask(M, N->getValueType(0)); 3051} 3052 3053/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3054/// is suitable for input to PSHUFHW. 3055static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3056 if (VT != MVT::v8i16) 3057 return false; 3058 3059 // Lower quadword copied in order or undef. 3060 for (int i = 0; i != 4; ++i) 3061 if (Mask[i] >= 0 && Mask[i] != i) 3062 return false; 3063 3064 // Upper quadword shuffled. 3065 for (int i = 4; i != 8; ++i) 3066 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3067 return false; 3068 3069 return true; 3070} 3071 3072bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3073 SmallVector<int, 8> M; 3074 N->getMask(M); 3075 return ::isPSHUFHWMask(M, N->getValueType(0)); 3076} 3077 3078/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3079/// is suitable for input to PSHUFLW. 3080static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3081 if (VT != MVT::v8i16) 3082 return false; 3083 3084 // Upper quadword copied in order. 3085 for (int i = 4; i != 8; ++i) 3086 if (Mask[i] >= 0 && Mask[i] != i) 3087 return false; 3088 3089 // Lower quadword shuffled. 3090 for (int i = 0; i != 4; ++i) 3091 if (Mask[i] >= 4) 3092 return false; 3093 3094 return true; 3095} 3096 3097bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3098 SmallVector<int, 8> M; 3099 N->getMask(M); 3100 return ::isPSHUFLWMask(M, N->getValueType(0)); 3101} 3102 3103/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3104/// is suitable for input to PALIGNR. 3105static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3106 bool hasSSSE3) { 3107 int i, e = VT.getVectorNumElements(); 3108 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3109 return false; 3110 3111 // Do not handle v2i64 / v2f64 shuffles with palignr. 3112 if (e < 4 || !hasSSSE3) 3113 return false; 3114 3115 for (i = 0; i != e; ++i) 3116 if (Mask[i] >= 0) 3117 break; 3118 3119 // All undef, not a palignr. 3120 if (i == e) 3121 return false; 3122 3123 // Make sure we're shifting in the right direction. 3124 if (Mask[i] <= i) 3125 return false; 3126 3127 int s = Mask[i] - i; 3128 3129 // Check the rest of the elements to see if they are consecutive. 3130 for (++i; i != e; ++i) { 3131 int m = Mask[i]; 3132 if (m >= 0 && m != s+i) 3133 return false; 3134 } 3135 return true; 3136} 3137 3138/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3139/// specifies a shuffle of elements that is suitable for input to SHUFP*. 3140static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3141 int NumElems = VT.getVectorNumElements(); 3142 if (NumElems != 2 && NumElems != 4) 3143 return false; 3144 3145 int Half = NumElems / 2; 3146 for (int i = 0; i < Half; ++i) 3147 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3148 return false; 3149 for (int i = Half; i < NumElems; ++i) 3150 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3151 return false; 3152 3153 return true; 3154} 3155 3156bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3157 SmallVector<int, 8> M; 3158 N->getMask(M); 3159 return ::isSHUFPMask(M, N->getValueType(0)); 3160} 3161 3162/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3163/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3164/// half elements to come from vector 1 (which would equal the dest.) and 3165/// the upper half to come from vector 2. 3166static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3167 int NumElems = VT.getVectorNumElements(); 3168 3169 if (NumElems != 2 && NumElems != 4) 3170 return false; 3171 3172 int Half = NumElems / 2; 3173 for (int i = 0; i < Half; ++i) 3174 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3175 return false; 3176 for (int i = Half; i < NumElems; ++i) 3177 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3178 return false; 3179 return true; 3180} 3181 3182static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3183 SmallVector<int, 8> M; 3184 N->getMask(M); 3185 return isCommutedSHUFPMask(M, N->getValueType(0)); 3186} 3187 3188/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3189/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3190bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3191 EVT VT = N->getValueType(0); 3192 unsigned NumElems = VT.getVectorNumElements(); 3193 3194 if (VT.getSizeInBits() != 128) 3195 return false; 3196 3197 if (NumElems != 4) 3198 return false; 3199 3200 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3201 return isUndefOrEqual(N->getMaskElt(0), 6) && 3202 isUndefOrEqual(N->getMaskElt(1), 7) && 3203 isUndefOrEqual(N->getMaskElt(2), 2) && 3204 isUndefOrEqual(N->getMaskElt(3), 3); 3205} 3206 3207/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3208/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3209/// <2, 3, 2, 3> 3210bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3211 EVT VT = N->getValueType(0); 3212 unsigned NumElems = VT.getVectorNumElements(); 3213 3214 if (VT.getSizeInBits() != 128) 3215 return false; 3216 3217 if (NumElems != 4) 3218 return false; 3219 3220 return isUndefOrEqual(N->getMaskElt(0), 2) && 3221 isUndefOrEqual(N->getMaskElt(1), 3) && 3222 isUndefOrEqual(N->getMaskElt(2), 2) && 3223 isUndefOrEqual(N->getMaskElt(3), 3); 3224} 3225 3226/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3227/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3228bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3229 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3230 3231 if (NumElems != 2 && NumElems != 4) 3232 return false; 3233 3234 for (unsigned i = 0; i < NumElems/2; ++i) 3235 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3236 return false; 3237 3238 for (unsigned i = NumElems/2; i < NumElems; ++i) 3239 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3240 return false; 3241 3242 return true; 3243} 3244 3245/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3246/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3247bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3248 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3249 3250 if ((NumElems != 2 && NumElems != 4) 3251 || N->getValueType(0).getSizeInBits() > 128) 3252 return false; 3253 3254 for (unsigned i = 0; i < NumElems/2; ++i) 3255 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3256 return false; 3257 3258 for (unsigned i = 0; i < NumElems/2; ++i) 3259 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3260 return false; 3261 3262 return true; 3263} 3264 3265/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3266/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3267static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3268 bool V2IsSplat = false) { 3269 int NumElts = VT.getVectorNumElements(); 3270 3271 assert((VT.is128BitVector() || VT.is256BitVector()) && 3272 "Unsupported vector type for unpckh"); 3273 3274 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3275 return false; 3276 3277 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3278 // independently on 128-bit lanes. 3279 unsigned NumLanes = VT.getSizeInBits()/128; 3280 unsigned NumLaneElts = NumElts/NumLanes; 3281 3282 unsigned Start = 0; 3283 unsigned End = NumLaneElts; 3284 for (unsigned s = 0; s < NumLanes; ++s) { 3285 for (unsigned i = Start, j = s * NumLaneElts; 3286 i != End; 3287 i += 2, ++j) { 3288 int BitI = Mask[i]; 3289 int BitI1 = Mask[i+1]; 3290 if (!isUndefOrEqual(BitI, j)) 3291 return false; 3292 if (V2IsSplat) { 3293 if (!isUndefOrEqual(BitI1, NumElts)) 3294 return false; 3295 } else { 3296 if (!isUndefOrEqual(BitI1, j + NumElts)) 3297 return false; 3298 } 3299 } 3300 // Process the next 128 bits. 3301 Start += NumLaneElts; 3302 End += NumLaneElts; 3303 } 3304 3305 return true; 3306} 3307 3308bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3309 SmallVector<int, 8> M; 3310 N->getMask(M); 3311 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3312} 3313 3314/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3315/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3316static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3317 bool V2IsSplat = false) { 3318 int NumElts = VT.getVectorNumElements(); 3319 3320 assert((VT.is128BitVector() || VT.is256BitVector()) && 3321 "Unsupported vector type for unpckh"); 3322 3323 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3324 return false; 3325 3326 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3327 // independently on 128-bit lanes. 3328 unsigned NumLanes = VT.getSizeInBits()/128; 3329 unsigned NumLaneElts = NumElts/NumLanes; 3330 3331 unsigned Start = 0; 3332 unsigned End = NumLaneElts; 3333 for (unsigned l = 0; l != NumLanes; ++l) { 3334 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3335 i != End; i += 2, ++j) { 3336 int BitI = Mask[i]; 3337 int BitI1 = Mask[i+1]; 3338 if (!isUndefOrEqual(BitI, j)) 3339 return false; 3340 if (V2IsSplat) { 3341 if (isUndefOrEqual(BitI1, NumElts)) 3342 return false; 3343 } else { 3344 if (!isUndefOrEqual(BitI1, j+NumElts)) 3345 return false; 3346 } 3347 } 3348 // Process the next 128 bits. 3349 Start += NumLaneElts; 3350 End += NumLaneElts; 3351 } 3352 return true; 3353} 3354 3355bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3356 SmallVector<int, 8> M; 3357 N->getMask(M); 3358 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3359} 3360 3361/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3362/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3363/// <0, 0, 1, 1> 3364static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3365 int NumElems = VT.getVectorNumElements(); 3366 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3367 return false; 3368 3369 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3370 // independently on 128-bit lanes. 3371 unsigned NumLanes = VT.getSizeInBits() / 128; 3372 unsigned NumLaneElts = NumElems / NumLanes; 3373 3374 for (unsigned s = 0; s < NumLanes; ++s) { 3375 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3376 i != NumLaneElts * (s + 1); 3377 i += 2, ++j) { 3378 int BitI = Mask[i]; 3379 int BitI1 = Mask[i+1]; 3380 3381 if (!isUndefOrEqual(BitI, j)) 3382 return false; 3383 if (!isUndefOrEqual(BitI1, j)) 3384 return false; 3385 } 3386 } 3387 3388 return true; 3389} 3390 3391bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3392 SmallVector<int, 8> M; 3393 N->getMask(M); 3394 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3395} 3396 3397/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3398/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3399/// <2, 2, 3, 3> 3400static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3401 int NumElems = VT.getVectorNumElements(); 3402 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3403 return false; 3404 3405 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3406 int BitI = Mask[i]; 3407 int BitI1 = Mask[i+1]; 3408 if (!isUndefOrEqual(BitI, j)) 3409 return false; 3410 if (!isUndefOrEqual(BitI1, j)) 3411 return false; 3412 } 3413 return true; 3414} 3415 3416bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3417 SmallVector<int, 8> M; 3418 N->getMask(M); 3419 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3420} 3421 3422/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3423/// specifies a shuffle of elements that is suitable for input to MOVSS, 3424/// MOVSD, and MOVD, i.e. setting the lowest element. 3425static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3426 if (VT.getVectorElementType().getSizeInBits() < 32) 3427 return false; 3428 3429 int NumElts = VT.getVectorNumElements(); 3430 3431 if (!isUndefOrEqual(Mask[0], NumElts)) 3432 return false; 3433 3434 for (int i = 1; i < NumElts; ++i) 3435 if (!isUndefOrEqual(Mask[i], i)) 3436 return false; 3437 3438 return true; 3439} 3440 3441bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3442 SmallVector<int, 8> M; 3443 N->getMask(M); 3444 return ::isMOVLMask(M, N->getValueType(0)); 3445} 3446 3447/// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3448/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3449/// Note that VPERMIL mask matching is different depending whether theunderlying 3450/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3451/// to the same elements of the low, but to the higher half of the source. 3452/// In VPERMILPD the two lanes could be shuffled independently of each other 3453/// with the same restriction that lanes can't be crossed. 3454static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3455 const X86Subtarget *Subtarget) { 3456 int NumElts = VT.getVectorNumElements(); 3457 int NumLanes = VT.getSizeInBits()/128; 3458 3459 if (!Subtarget->hasAVX()) 3460 return false; 3461 3462 // Match any permutation of 128-bit vector with 64-bit types 3463 if (NumLanes == 1 && NumElts != 2) 3464 return false; 3465 3466 // Only match 256-bit with 32 types 3467 if (VT.getSizeInBits() == 256 && NumElts != 4) 3468 return false; 3469 3470 // The mask on the high lane is independent of the low. Both can match 3471 // any element in inside its own lane, but can't cross. 3472 int LaneSize = NumElts/NumLanes; 3473 for (int l = 0; l < NumLanes; ++l) 3474 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3475 int LaneStart = l*LaneSize; 3476 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3477 return false; 3478 } 3479 3480 return true; 3481} 3482 3483/// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3484/// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3485/// Note that VPERMIL mask matching is different depending whether theunderlying 3486/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3487/// to the same elements of the low, but to the higher half of the source. 3488/// In VPERMILPD the two lanes could be shuffled independently of each other 3489/// with the same restriction that lanes can't be crossed. 3490static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3491 const X86Subtarget *Subtarget) { 3492 unsigned NumElts = VT.getVectorNumElements(); 3493 unsigned NumLanes = VT.getSizeInBits()/128; 3494 3495 if (!Subtarget->hasAVX()) 3496 return false; 3497 3498 // Match any permutation of 128-bit vector with 32-bit types 3499 if (NumLanes == 1 && NumElts != 4) 3500 return false; 3501 3502 // Only match 256-bit with 32 types 3503 if (VT.getSizeInBits() == 256 && NumElts != 8) 3504 return false; 3505 3506 // The mask on the high lane should be the same as the low. Actually, 3507 // they can differ if any of the corresponding index in a lane is undef 3508 // and the other stays in range. 3509 int LaneSize = NumElts/NumLanes; 3510 for (int i = 0; i < LaneSize; ++i) { 3511 int HighElt = i+LaneSize; 3512 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts); 3513 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize); 3514 3515 if (!HighValid || !LowValid) 3516 return false; 3517 if (Mask[i] < 0 || Mask[HighElt] < 0) 3518 continue; 3519 if (Mask[HighElt]-Mask[i] != LaneSize) 3520 return false; 3521 } 3522 3523 return true; 3524} 3525 3526/// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3527/// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3528static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3529 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3530 EVT VT = SVOp->getValueType(0); 3531 3532 int NumElts = VT.getVectorNumElements(); 3533 int NumLanes = VT.getSizeInBits()/128; 3534 int LaneSize = NumElts/NumLanes; 3535 3536 // Although the mask is equal for both lanes do it twice to get the cases 3537 // where a mask will match because the same mask element is undef on the 3538 // first half but valid on the second. This would get pathological cases 3539 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3540 unsigned Mask = 0; 3541 for (int l = 0; l < NumLanes; ++l) { 3542 for (int i = 0; i < LaneSize; ++i) { 3543 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3544 if (MaskElt < 0) 3545 continue; 3546 if (MaskElt >= LaneSize) 3547 MaskElt -= LaneSize; 3548 Mask |= MaskElt << (i*2); 3549 } 3550 } 3551 3552 return Mask; 3553} 3554 3555/// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3556/// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3557static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3558 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3559 EVT VT = SVOp->getValueType(0); 3560 3561 int NumElts = VT.getVectorNumElements(); 3562 int NumLanes = VT.getSizeInBits()/128; 3563 3564 unsigned Mask = 0; 3565 int LaneSize = NumElts/NumLanes; 3566 for (int l = 0; l < NumLanes; ++l) 3567 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3568 int MaskElt = SVOp->getMaskElt(i); 3569 if (MaskElt < 0) 3570 continue; 3571 Mask |= (MaskElt-l*LaneSize) << i; 3572 } 3573 3574 return Mask; 3575} 3576 3577/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3578/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3579/// element of vector 2 and the other elements to come from vector 1 in order. 3580static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3581 bool V2IsSplat = false, bool V2IsUndef = false) { 3582 int NumOps = VT.getVectorNumElements(); 3583 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3584 return false; 3585 3586 if (!isUndefOrEqual(Mask[0], 0)) 3587 return false; 3588 3589 for (int i = 1; i < NumOps; ++i) 3590 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3591 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3592 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3593 return false; 3594 3595 return true; 3596} 3597 3598static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3599 bool V2IsUndef = false) { 3600 SmallVector<int, 8> M; 3601 N->getMask(M); 3602 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3603} 3604 3605/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3606/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3607/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3608bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3609 const X86Subtarget *Subtarget) { 3610 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3611 return false; 3612 3613 // The second vector must be undef 3614 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3615 return false; 3616 3617 EVT VT = N->getValueType(0); 3618 unsigned NumElems = VT.getVectorNumElements(); 3619 3620 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3621 (VT.getSizeInBits() == 256 && NumElems != 8)) 3622 return false; 3623 3624 // "i+1" is the value the indexed mask element must have 3625 for (unsigned i = 0; i < NumElems; i += 2) 3626 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3627 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3628 return false; 3629 3630 return true; 3631} 3632 3633/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3634/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3635/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3636bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3637 const X86Subtarget *Subtarget) { 3638 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3639 return false; 3640 3641 // The second vector must be undef 3642 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3643 return false; 3644 3645 EVT VT = N->getValueType(0); 3646 unsigned NumElems = VT.getVectorNumElements(); 3647 3648 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3649 (VT.getSizeInBits() == 256 && NumElems != 8)) 3650 return false; 3651 3652 // "i" is the value the indexed mask element must have 3653 for (unsigned i = 0; i < NumElems; i += 2) 3654 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3655 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3656 return false; 3657 3658 return true; 3659} 3660 3661/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3662/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 3663bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3664 int e = N->getValueType(0).getVectorNumElements() / 2; 3665 3666 for (int i = 0; i < e; ++i) 3667 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3668 return false; 3669 for (int i = 0; i < e; ++i) 3670 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3671 return false; 3672 return true; 3673} 3674 3675/// isVEXTRACTF128Index - Return true if the specified 3676/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3677/// suitable for input to VEXTRACTF128. 3678bool X86::isVEXTRACTF128Index(SDNode *N) { 3679 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3680 return false; 3681 3682 // The index should be aligned on a 128-bit boundary. 3683 uint64_t Index = 3684 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3685 3686 unsigned VL = N->getValueType(0).getVectorNumElements(); 3687 unsigned VBits = N->getValueType(0).getSizeInBits(); 3688 unsigned ElSize = VBits / VL; 3689 bool Result = (Index * ElSize) % 128 == 0; 3690 3691 return Result; 3692} 3693 3694/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3695/// operand specifies a subvector insert that is suitable for input to 3696/// VINSERTF128. 3697bool X86::isVINSERTF128Index(SDNode *N) { 3698 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3699 return false; 3700 3701 // The index should be aligned on a 128-bit boundary. 3702 uint64_t Index = 3703 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3704 3705 unsigned VL = N->getValueType(0).getVectorNumElements(); 3706 unsigned VBits = N->getValueType(0).getSizeInBits(); 3707 unsigned ElSize = VBits / VL; 3708 bool Result = (Index * ElSize) % 128 == 0; 3709 3710 return Result; 3711} 3712 3713/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3714/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3715unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3716 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3717 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3718 3719 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3720 unsigned Mask = 0; 3721 for (int i = 0; i < NumOperands; ++i) { 3722 int Val = SVOp->getMaskElt(NumOperands-i-1); 3723 if (Val < 0) Val = 0; 3724 if (Val >= NumOperands) Val -= NumOperands; 3725 Mask |= Val; 3726 if (i != NumOperands - 1) 3727 Mask <<= Shift; 3728 } 3729 return Mask; 3730} 3731 3732/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3733/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3734unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3736 unsigned Mask = 0; 3737 // 8 nodes, but we only care about the last 4. 3738 for (unsigned i = 7; i >= 4; --i) { 3739 int Val = SVOp->getMaskElt(i); 3740 if (Val >= 0) 3741 Mask |= (Val - 4); 3742 if (i != 4) 3743 Mask <<= 2; 3744 } 3745 return Mask; 3746} 3747 3748/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3749/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3750unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3751 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3752 unsigned Mask = 0; 3753 // 8 nodes, but we only care about the first 4. 3754 for (int i = 3; i >= 0; --i) { 3755 int Val = SVOp->getMaskElt(i); 3756 if (Val >= 0) 3757 Mask |= Val; 3758 if (i != 0) 3759 Mask <<= 2; 3760 } 3761 return Mask; 3762} 3763 3764/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3765/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3766unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3767 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3768 EVT VVT = N->getValueType(0); 3769 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3770 int Val = 0; 3771 3772 unsigned i, e; 3773 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3774 Val = SVOp->getMaskElt(i); 3775 if (Val >= 0) 3776 break; 3777 } 3778 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3779 return (Val - i) * EltSize; 3780} 3781 3782/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3783/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3784/// instructions. 3785unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3786 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3787 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3788 3789 uint64_t Index = 3790 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3791 3792 EVT VecVT = N->getOperand(0).getValueType(); 3793 EVT ElVT = VecVT.getVectorElementType(); 3794 3795 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3796 return Index / NumElemsPerChunk; 3797} 3798 3799/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3800/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3801/// instructions. 3802unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3803 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3804 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3805 3806 uint64_t Index = 3807 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3808 3809 EVT VecVT = N->getValueType(0); 3810 EVT ElVT = VecVT.getVectorElementType(); 3811 3812 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3813 return Index / NumElemsPerChunk; 3814} 3815 3816/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3817/// constant +0.0. 3818bool X86::isZeroNode(SDValue Elt) { 3819 return ((isa<ConstantSDNode>(Elt) && 3820 cast<ConstantSDNode>(Elt)->isNullValue()) || 3821 (isa<ConstantFPSDNode>(Elt) && 3822 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3823} 3824 3825/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3826/// their permute mask. 3827static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3828 SelectionDAG &DAG) { 3829 EVT VT = SVOp->getValueType(0); 3830 unsigned NumElems = VT.getVectorNumElements(); 3831 SmallVector<int, 8> MaskVec; 3832 3833 for (unsigned i = 0; i != NumElems; ++i) { 3834 int idx = SVOp->getMaskElt(i); 3835 if (idx < 0) 3836 MaskVec.push_back(idx); 3837 else if (idx < (int)NumElems) 3838 MaskVec.push_back(idx + NumElems); 3839 else 3840 MaskVec.push_back(idx - NumElems); 3841 } 3842 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3843 SVOp->getOperand(0), &MaskVec[0]); 3844} 3845 3846/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3847/// the two vector operands have swapped position. 3848static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3849 unsigned NumElems = VT.getVectorNumElements(); 3850 for (unsigned i = 0; i != NumElems; ++i) { 3851 int idx = Mask[i]; 3852 if (idx < 0) 3853 continue; 3854 else if (idx < (int)NumElems) 3855 Mask[i] = idx + NumElems; 3856 else 3857 Mask[i] = idx - NumElems; 3858 } 3859} 3860 3861/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3862/// match movhlps. The lower half elements should come from upper half of 3863/// V1 (and in order), and the upper half elements should come from the upper 3864/// half of V2 (and in order). 3865static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3866 if (Op->getValueType(0).getVectorNumElements() != 4) 3867 return false; 3868 for (unsigned i = 0, e = 2; i != e; ++i) 3869 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3870 return false; 3871 for (unsigned i = 2; i != 4; ++i) 3872 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3873 return false; 3874 return true; 3875} 3876 3877/// isScalarLoadToVector - Returns true if the node is a scalar load that 3878/// is promoted to a vector. It also returns the LoadSDNode by reference if 3879/// required. 3880static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3881 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3882 return false; 3883 N = N->getOperand(0).getNode(); 3884 if (!ISD::isNON_EXTLoad(N)) 3885 return false; 3886 if (LD) 3887 *LD = cast<LoadSDNode>(N); 3888 return true; 3889} 3890 3891/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3892/// match movlp{s|d}. The lower half elements should come from lower half of 3893/// V1 (and in order), and the upper half elements should come from the upper 3894/// half of V2 (and in order). And since V1 will become the source of the 3895/// MOVLP, it must be either a vector load or a scalar load to vector. 3896static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3897 ShuffleVectorSDNode *Op) { 3898 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3899 return false; 3900 // Is V2 is a vector load, don't do this transformation. We will try to use 3901 // load folding shufps op. 3902 if (ISD::isNON_EXTLoad(V2)) 3903 return false; 3904 3905 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3906 3907 if (NumElems != 2 && NumElems != 4) 3908 return false; 3909 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3910 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3911 return false; 3912 for (unsigned i = NumElems/2; i != NumElems; ++i) 3913 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3914 return false; 3915 return true; 3916} 3917 3918/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3919/// all the same. 3920static bool isSplatVector(SDNode *N) { 3921 if (N->getOpcode() != ISD::BUILD_VECTOR) 3922 return false; 3923 3924 SDValue SplatValue = N->getOperand(0); 3925 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3926 if (N->getOperand(i) != SplatValue) 3927 return false; 3928 return true; 3929} 3930 3931/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3932/// to an zero vector. 3933/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3934static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3935 SDValue V1 = N->getOperand(0); 3936 SDValue V2 = N->getOperand(1); 3937 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3938 for (unsigned i = 0; i != NumElems; ++i) { 3939 int Idx = N->getMaskElt(i); 3940 if (Idx >= (int)NumElems) { 3941 unsigned Opc = V2.getOpcode(); 3942 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3943 continue; 3944 if (Opc != ISD::BUILD_VECTOR || 3945 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3946 return false; 3947 } else if (Idx >= 0) { 3948 unsigned Opc = V1.getOpcode(); 3949 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3950 continue; 3951 if (Opc != ISD::BUILD_VECTOR || 3952 !X86::isZeroNode(V1.getOperand(Idx))) 3953 return false; 3954 } 3955 } 3956 return true; 3957} 3958 3959/// getZeroVector - Returns a vector of specified type with all zero elements. 3960/// 3961static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3962 DebugLoc dl) { 3963 assert(VT.isVector() && "Expected a vector type"); 3964 3965 // Always build SSE zero vectors as <4 x i32> bitcasted 3966 // to their dest type. This ensures they get CSE'd. 3967 SDValue Vec; 3968 if (VT.getSizeInBits() == 128) { // SSE 3969 if (HasSSE2) { // SSE2 3970 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3971 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3972 } else { // SSE1 3973 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3974 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3975 } 3976 } else if (VT.getSizeInBits() == 256) { // AVX 3977 // 256-bit logic and arithmetic instructions in AVX are 3978 // all floating-point, no support for integer ops. Default 3979 // to emitting fp zeroed vectors then. 3980 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3981 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 3982 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 3983 } 3984 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 3985} 3986 3987/// getOnesVector - Returns a vector of specified type with all bits set. 3988/// Always build ones vectors as <4 x i32>. For 256-bit types, use two 3989/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their 3990/// original type, ensuring they get CSE'd. 3991static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3992 assert(VT.isVector() && "Expected a vector type"); 3993 assert((VT.is128BitVector() || VT.is256BitVector()) 3994 && "Expected a 128-bit or 256-bit vector type"); 3995 3996 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3997 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 3998 Cst, Cst, Cst, Cst); 3999 4000 if (VT.is256BitVector()) { 4001 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4002 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4003 Vec = Insert128BitVector(InsV, Vec, 4004 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4005 } 4006 4007 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4008} 4009 4010/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4011/// that point to V2 points to its first element. 4012static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4013 EVT VT = SVOp->getValueType(0); 4014 unsigned NumElems = VT.getVectorNumElements(); 4015 4016 bool Changed = false; 4017 SmallVector<int, 8> MaskVec; 4018 SVOp->getMask(MaskVec); 4019 4020 for (unsigned i = 0; i != NumElems; ++i) { 4021 if (MaskVec[i] > (int)NumElems) { 4022 MaskVec[i] = NumElems; 4023 Changed = true; 4024 } 4025 } 4026 if (Changed) 4027 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4028 SVOp->getOperand(1), &MaskVec[0]); 4029 return SDValue(SVOp, 0); 4030} 4031 4032/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4033/// operation of specified width. 4034static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4035 SDValue V2) { 4036 unsigned NumElems = VT.getVectorNumElements(); 4037 SmallVector<int, 8> Mask; 4038 Mask.push_back(NumElems); 4039 for (unsigned i = 1; i != NumElems; ++i) 4040 Mask.push_back(i); 4041 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4042} 4043 4044/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4045static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4046 SDValue V2) { 4047 unsigned NumElems = VT.getVectorNumElements(); 4048 SmallVector<int, 8> Mask; 4049 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4050 Mask.push_back(i); 4051 Mask.push_back(i + NumElems); 4052 } 4053 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4054} 4055 4056/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4057static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4058 SDValue V2) { 4059 unsigned NumElems = VT.getVectorNumElements(); 4060 unsigned Half = NumElems/2; 4061 SmallVector<int, 8> Mask; 4062 for (unsigned i = 0; i != Half; ++i) { 4063 Mask.push_back(i + Half); 4064 Mask.push_back(i + NumElems + Half); 4065 } 4066 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4067} 4068 4069// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4070// a generic shuffle instruction because the target has no such instructions. 4071// Generate shuffles which repeat i16 and i8 several times until they can be 4072// represented by v4f32 and then be manipulated by target suported shuffles. 4073static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4074 EVT VT = V.getValueType(); 4075 int NumElems = VT.getVectorNumElements(); 4076 DebugLoc dl = V.getDebugLoc(); 4077 4078 while (NumElems > 4) { 4079 if (EltNo < NumElems/2) { 4080 V = getUnpackl(DAG, dl, VT, V, V); 4081 } else { 4082 V = getUnpackh(DAG, dl, VT, V, V); 4083 EltNo -= NumElems/2; 4084 } 4085 NumElems >>= 1; 4086 } 4087 return V; 4088} 4089 4090/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4091static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4092 EVT VT = V.getValueType(); 4093 DebugLoc dl = V.getDebugLoc(); 4094 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4095 && "Vector size not supported"); 4096 4097 bool Is128 = VT.getSizeInBits() == 128; 4098 EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32; 4099 V = DAG.getNode(ISD::BITCAST, dl, NVT, V); 4100 4101 if (Is128) { 4102 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4103 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]); 4104 } else { 4105 // The second half of indicies refer to the higher part, which is a 4106 // duplication of the lower one. This makes this shuffle a perfect match 4107 // for the VPERM instruction. 4108 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4109 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4110 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]); 4111 } 4112 4113 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4114} 4115 4116/// PromoteVectorToScalarSplat - Since there's no native support for 4117/// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector + 4118/// INSERT_SUBVECTOR is generated. Recognize this idiom and do the 4119/// shuffle before the insertion, this yields less instructions in the end. 4120static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV, 4121 SelectionDAG &DAG) { 4122 EVT SrcVT = SV->getValueType(0); 4123 SDValue V1 = SV->getOperand(0); 4124 DebugLoc dl = SV->getDebugLoc(); 4125 int NumElems = SrcVT.getVectorNumElements(); 4126 4127 assert(SrcVT.is256BitVector() && "unknown howto handle vector type"); 4128 assert(SV->isSplat() && "shuffle must be a splat"); 4129 4130 int SplatIdx = SV->getSplatIndex(); 4131 const int Mask[4] = { SplatIdx, SplatIdx, SplatIdx, SplatIdx }; 4132 4133 EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(), 4134 NumElems/2); 4135 SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1), 4136 DAG.getUNDEF(SVT), Mask); 4137 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1, 4138 DAG.getConstant(0, MVT::i32), DAG, dl); 4139 4140 return Insert128BitVector(InsV, SV1, 4141 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4142} 4143 4144/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and 4145/// v8i32, v16i16 or v32i8 to v8f32. 4146static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4147 EVT SrcVT = SV->getValueType(0); 4148 SDValue V1 = SV->getOperand(0); 4149 DebugLoc dl = SV->getDebugLoc(); 4150 4151 int EltNo = SV->getSplatIndex(); 4152 int NumElems = SrcVT.getVectorNumElements(); 4153 unsigned Size = SrcVT.getSizeInBits(); 4154 4155 // Extract the 128-bit part containing the splat element and update 4156 // the splat element index when it refers to the higher register. 4157 if (Size == 256) { 4158 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4159 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4160 if (Idx > 0) 4161 EltNo -= NumElems/2; 4162 } 4163 4164 // Make this 128-bit vector duplicate i8 and i16 elements 4165 EVT EltVT = SrcVT.getVectorElementType(); 4166 if (NumElems > 4 && (EltVT == MVT::i8 || EltVT == MVT::i16)) 4167 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4168 4169 // Recreate the 256-bit vector and place the same 128-bit vector 4170 // into the low and high part. This is necessary because we want 4171 // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles 4172 // inside each separate v4f32 lane. 4173 if (Size == 256) { 4174 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4175 DAG.getConstant(0, MVT::i32), DAG, dl); 4176 V1 = Insert128BitVector(InsV, V1, 4177 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4178 } 4179 4180 return getLegalSplat(DAG, V1, EltNo); 4181} 4182 4183/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4184/// vector of zero or undef vector. This produces a shuffle where the low 4185/// element of V2 is swizzled into the zero/undef vector, landing at element 4186/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4187static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4188 bool isZero, bool HasSSE2, 4189 SelectionDAG &DAG) { 4190 EVT VT = V2.getValueType(); 4191 SDValue V1 = isZero 4192 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4193 unsigned NumElems = VT.getVectorNumElements(); 4194 SmallVector<int, 16> MaskVec; 4195 for (unsigned i = 0; i != NumElems; ++i) 4196 // If this is the insertion idx, put the low elt of V2 here. 4197 MaskVec.push_back(i == Idx ? NumElems : i); 4198 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4199} 4200 4201/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4202/// element of the result of the vector shuffle. 4203static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4204 unsigned Depth) { 4205 if (Depth == 6) 4206 return SDValue(); // Limit search depth. 4207 4208 SDValue V = SDValue(N, 0); 4209 EVT VT = V.getValueType(); 4210 unsigned Opcode = V.getOpcode(); 4211 4212 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4213 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4214 Index = SV->getMaskElt(Index); 4215 4216 if (Index < 0) 4217 return DAG.getUNDEF(VT.getVectorElementType()); 4218 4219 int NumElems = VT.getVectorNumElements(); 4220 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4221 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4222 } 4223 4224 // Recurse into target specific vector shuffles to find scalars. 4225 if (isTargetShuffle(Opcode)) { 4226 int NumElems = VT.getVectorNumElements(); 4227 SmallVector<unsigned, 16> ShuffleMask; 4228 SDValue ImmN; 4229 4230 switch(Opcode) { 4231 case X86ISD::SHUFPS: 4232 case X86ISD::SHUFPD: 4233 ImmN = N->getOperand(N->getNumOperands()-1); 4234 DecodeSHUFPSMask(NumElems, 4235 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4236 ShuffleMask); 4237 break; 4238 case X86ISD::PUNPCKHBW: 4239 case X86ISD::PUNPCKHWD: 4240 case X86ISD::PUNPCKHDQ: 4241 case X86ISD::PUNPCKHQDQ: 4242 DecodePUNPCKHMask(NumElems, ShuffleMask); 4243 break; 4244 case X86ISD::UNPCKHPS: 4245 case X86ISD::UNPCKHPD: 4246 case X86ISD::VUNPCKHPSY: 4247 case X86ISD::VUNPCKHPDY: 4248 DecodeUNPCKHPMask(NumElems, ShuffleMask); 4249 break; 4250 case X86ISD::PUNPCKLBW: 4251 case X86ISD::PUNPCKLWD: 4252 case X86ISD::PUNPCKLDQ: 4253 case X86ISD::PUNPCKLQDQ: 4254 DecodePUNPCKLMask(VT, ShuffleMask); 4255 break; 4256 case X86ISD::UNPCKLPS: 4257 case X86ISD::UNPCKLPD: 4258 case X86ISD::VUNPCKLPSY: 4259 case X86ISD::VUNPCKLPDY: 4260 DecodeUNPCKLPMask(VT, ShuffleMask); 4261 break; 4262 case X86ISD::MOVHLPS: 4263 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4264 break; 4265 case X86ISD::MOVLHPS: 4266 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4267 break; 4268 case X86ISD::PSHUFD: 4269 ImmN = N->getOperand(N->getNumOperands()-1); 4270 DecodePSHUFMask(NumElems, 4271 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4272 ShuffleMask); 4273 break; 4274 case X86ISD::PSHUFHW: 4275 ImmN = N->getOperand(N->getNumOperands()-1); 4276 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4277 ShuffleMask); 4278 break; 4279 case X86ISD::PSHUFLW: 4280 ImmN = N->getOperand(N->getNumOperands()-1); 4281 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4282 ShuffleMask); 4283 break; 4284 case X86ISD::MOVSS: 4285 case X86ISD::MOVSD: { 4286 // The index 0 always comes from the first element of the second source, 4287 // this is why MOVSS and MOVSD are used in the first place. The other 4288 // elements come from the other positions of the first source vector. 4289 unsigned OpNum = (Index == 0) ? 1 : 0; 4290 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4291 Depth+1); 4292 } 4293 case X86ISD::VPERMILPS: 4294 ImmN = N->getOperand(N->getNumOperands()-1); 4295 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4296 ShuffleMask); 4297 break; 4298 case X86ISD::VPERMILPSY: 4299 ImmN = N->getOperand(N->getNumOperands()-1); 4300 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4301 ShuffleMask); 4302 break; 4303 case X86ISD::VPERMILPD: 4304 ImmN = N->getOperand(N->getNumOperands()-1); 4305 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4306 ShuffleMask); 4307 break; 4308 case X86ISD::VPERMILPDY: 4309 ImmN = N->getOperand(N->getNumOperands()-1); 4310 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4311 ShuffleMask); 4312 break; 4313 default: 4314 assert("not implemented for target shuffle node"); 4315 return SDValue(); 4316 } 4317 4318 Index = ShuffleMask[Index]; 4319 if (Index < 0) 4320 return DAG.getUNDEF(VT.getVectorElementType()); 4321 4322 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4323 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4324 Depth+1); 4325 } 4326 4327 // Actual nodes that may contain scalar elements 4328 if (Opcode == ISD::BITCAST) { 4329 V = V.getOperand(0); 4330 EVT SrcVT = V.getValueType(); 4331 unsigned NumElems = VT.getVectorNumElements(); 4332 4333 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4334 return SDValue(); 4335 } 4336 4337 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4338 return (Index == 0) ? V.getOperand(0) 4339 : DAG.getUNDEF(VT.getVectorElementType()); 4340 4341 if (V.getOpcode() == ISD::BUILD_VECTOR) 4342 return V.getOperand(Index); 4343 4344 return SDValue(); 4345} 4346 4347/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4348/// shuffle operation which come from a consecutively from a zero. The 4349/// search can start in two different directions, from left or right. 4350static 4351unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4352 bool ZerosFromLeft, SelectionDAG &DAG) { 4353 int i = 0; 4354 4355 while (i < NumElems) { 4356 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4357 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4358 if (!(Elt.getNode() && 4359 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4360 break; 4361 ++i; 4362 } 4363 4364 return i; 4365} 4366 4367/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4368/// MaskE correspond consecutively to elements from one of the vector operands, 4369/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4370static 4371bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4372 int OpIdx, int NumElems, unsigned &OpNum) { 4373 bool SeenV1 = false; 4374 bool SeenV2 = false; 4375 4376 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4377 int Idx = SVOp->getMaskElt(i); 4378 // Ignore undef indicies 4379 if (Idx < 0) 4380 continue; 4381 4382 if (Idx < NumElems) 4383 SeenV1 = true; 4384 else 4385 SeenV2 = true; 4386 4387 // Only accept consecutive elements from the same vector 4388 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4389 return false; 4390 } 4391 4392 OpNum = SeenV1 ? 0 : 1; 4393 return true; 4394} 4395 4396/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4397/// logical left shift of a vector. 4398static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4399 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4400 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4401 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4402 false /* check zeros from right */, DAG); 4403 unsigned OpSrc; 4404 4405 if (!NumZeros) 4406 return false; 4407 4408 // Considering the elements in the mask that are not consecutive zeros, 4409 // check if they consecutively come from only one of the source vectors. 4410 // 4411 // V1 = {X, A, B, C} 0 4412 // \ \ \ / 4413 // vector_shuffle V1, V2 <1, 2, 3, X> 4414 // 4415 if (!isShuffleMaskConsecutive(SVOp, 4416 0, // Mask Start Index 4417 NumElems-NumZeros-1, // Mask End Index 4418 NumZeros, // Where to start looking in the src vector 4419 NumElems, // Number of elements in vector 4420 OpSrc)) // Which source operand ? 4421 return false; 4422 4423 isLeft = false; 4424 ShAmt = NumZeros; 4425 ShVal = SVOp->getOperand(OpSrc); 4426 return true; 4427} 4428 4429/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4430/// logical left shift of a vector. 4431static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4432 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4433 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4434 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4435 true /* check zeros from left */, DAG); 4436 unsigned OpSrc; 4437 4438 if (!NumZeros) 4439 return false; 4440 4441 // Considering the elements in the mask that are not consecutive zeros, 4442 // check if they consecutively come from only one of the source vectors. 4443 // 4444 // 0 { A, B, X, X } = V2 4445 // / \ / / 4446 // vector_shuffle V1, V2 <X, X, 4, 5> 4447 // 4448 if (!isShuffleMaskConsecutive(SVOp, 4449 NumZeros, // Mask Start Index 4450 NumElems-1, // Mask End Index 4451 0, // Where to start looking in the src vector 4452 NumElems, // Number of elements in vector 4453 OpSrc)) // Which source operand ? 4454 return false; 4455 4456 isLeft = true; 4457 ShAmt = NumZeros; 4458 ShVal = SVOp->getOperand(OpSrc); 4459 return true; 4460} 4461 4462/// isVectorShift - Returns true if the shuffle can be implemented as a 4463/// logical left or right shift of a vector. 4464static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4465 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4466 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4467 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4468 return true; 4469 4470 return false; 4471} 4472 4473/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4474/// 4475static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4476 unsigned NumNonZero, unsigned NumZero, 4477 SelectionDAG &DAG, 4478 const TargetLowering &TLI) { 4479 if (NumNonZero > 8) 4480 return SDValue(); 4481 4482 DebugLoc dl = Op.getDebugLoc(); 4483 SDValue V(0, 0); 4484 bool First = true; 4485 for (unsigned i = 0; i < 16; ++i) { 4486 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4487 if (ThisIsNonZero && First) { 4488 if (NumZero) 4489 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4490 else 4491 V = DAG.getUNDEF(MVT::v8i16); 4492 First = false; 4493 } 4494 4495 if ((i & 1) != 0) { 4496 SDValue ThisElt(0, 0), LastElt(0, 0); 4497 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4498 if (LastIsNonZero) { 4499 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4500 MVT::i16, Op.getOperand(i-1)); 4501 } 4502 if (ThisIsNonZero) { 4503 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4504 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4505 ThisElt, DAG.getConstant(8, MVT::i8)); 4506 if (LastIsNonZero) 4507 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4508 } else 4509 ThisElt = LastElt; 4510 4511 if (ThisElt.getNode()) 4512 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4513 DAG.getIntPtrConstant(i/2)); 4514 } 4515 } 4516 4517 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4518} 4519 4520/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4521/// 4522static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4523 unsigned NumNonZero, unsigned NumZero, 4524 SelectionDAG &DAG, 4525 const TargetLowering &TLI) { 4526 if (NumNonZero > 4) 4527 return SDValue(); 4528 4529 DebugLoc dl = Op.getDebugLoc(); 4530 SDValue V(0, 0); 4531 bool First = true; 4532 for (unsigned i = 0; i < 8; ++i) { 4533 bool isNonZero = (NonZeros & (1 << i)) != 0; 4534 if (isNonZero) { 4535 if (First) { 4536 if (NumZero) 4537 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4538 else 4539 V = DAG.getUNDEF(MVT::v8i16); 4540 First = false; 4541 } 4542 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4543 MVT::v8i16, V, Op.getOperand(i), 4544 DAG.getIntPtrConstant(i)); 4545 } 4546 } 4547 4548 return V; 4549} 4550 4551/// getVShift - Return a vector logical shift node. 4552/// 4553static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4554 unsigned NumBits, SelectionDAG &DAG, 4555 const TargetLowering &TLI, DebugLoc dl) { 4556 EVT ShVT = MVT::v2i64; 4557 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4558 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4559 return DAG.getNode(ISD::BITCAST, dl, VT, 4560 DAG.getNode(Opc, dl, ShVT, SrcOp, 4561 DAG.getConstant(NumBits, 4562 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4563} 4564 4565SDValue 4566X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4567 SelectionDAG &DAG) const { 4568 4569 // Check if the scalar load can be widened into a vector load. And if 4570 // the address is "base + cst" see if the cst can be "absorbed" into 4571 // the shuffle mask. 4572 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4573 SDValue Ptr = LD->getBasePtr(); 4574 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4575 return SDValue(); 4576 EVT PVT = LD->getValueType(0); 4577 if (PVT != MVT::i32 && PVT != MVT::f32) 4578 return SDValue(); 4579 4580 int FI = -1; 4581 int64_t Offset = 0; 4582 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4583 FI = FINode->getIndex(); 4584 Offset = 0; 4585 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4586 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4587 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4588 Offset = Ptr.getConstantOperandVal(1); 4589 Ptr = Ptr.getOperand(0); 4590 } else { 4591 return SDValue(); 4592 } 4593 4594 // FIXME: 256-bit vector instructions don't require a strict alignment, 4595 // improve this code to support it better. 4596 unsigned RequiredAlign = VT.getSizeInBits()/8; 4597 SDValue Chain = LD->getChain(); 4598 // Make sure the stack object alignment is at least 16 or 32. 4599 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4600 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4601 if (MFI->isFixedObjectIndex(FI)) { 4602 // Can't change the alignment. FIXME: It's possible to compute 4603 // the exact stack offset and reference FI + adjust offset instead. 4604 // If someone *really* cares about this. That's the way to implement it. 4605 return SDValue(); 4606 } else { 4607 MFI->setObjectAlignment(FI, RequiredAlign); 4608 } 4609 } 4610 4611 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4612 // Ptr + (Offset & ~15). 4613 if (Offset < 0) 4614 return SDValue(); 4615 if ((Offset % RequiredAlign) & 3) 4616 return SDValue(); 4617 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4618 if (StartOffset) 4619 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4620 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4621 4622 int EltNo = (Offset - StartOffset) >> 2; 4623 int NumElems = VT.getVectorNumElements(); 4624 4625 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4626 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4627 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4628 LD->getPointerInfo().getWithOffset(StartOffset), 4629 false, false, 0); 4630 4631 // Canonicalize it to a v4i32 or v8i32 shuffle. 4632 SmallVector<int, 8> Mask; 4633 for (int i = 0; i < NumElems; ++i) 4634 Mask.push_back(EltNo); 4635 4636 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4637 return DAG.getNode(ISD::BITCAST, dl, NVT, 4638 DAG.getVectorShuffle(CanonVT, dl, V1, 4639 DAG.getUNDEF(CanonVT),&Mask[0])); 4640 } 4641 4642 return SDValue(); 4643} 4644 4645/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4646/// vector of type 'VT', see if the elements can be replaced by a single large 4647/// load which has the same value as a build_vector whose operands are 'elts'. 4648/// 4649/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4650/// 4651/// FIXME: we'd also like to handle the case where the last elements are zero 4652/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4653/// There's even a handy isZeroNode for that purpose. 4654static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4655 DebugLoc &DL, SelectionDAG &DAG) { 4656 EVT EltVT = VT.getVectorElementType(); 4657 unsigned NumElems = Elts.size(); 4658 4659 LoadSDNode *LDBase = NULL; 4660 unsigned LastLoadedElt = -1U; 4661 4662 // For each element in the initializer, see if we've found a load or an undef. 4663 // If we don't find an initial load element, or later load elements are 4664 // non-consecutive, bail out. 4665 for (unsigned i = 0; i < NumElems; ++i) { 4666 SDValue Elt = Elts[i]; 4667 4668 if (!Elt.getNode() || 4669 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4670 return SDValue(); 4671 if (!LDBase) { 4672 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4673 return SDValue(); 4674 LDBase = cast<LoadSDNode>(Elt.getNode()); 4675 LastLoadedElt = i; 4676 continue; 4677 } 4678 if (Elt.getOpcode() == ISD::UNDEF) 4679 continue; 4680 4681 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4682 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4683 return SDValue(); 4684 LastLoadedElt = i; 4685 } 4686 4687 // If we have found an entire vector of loads and undefs, then return a large 4688 // load of the entire vector width starting at the base pointer. If we found 4689 // consecutive loads for the low half, generate a vzext_load node. 4690 if (LastLoadedElt == NumElems - 1) { 4691 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4692 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4693 LDBase->getPointerInfo(), 4694 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 4695 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4696 LDBase->getPointerInfo(), 4697 LDBase->isVolatile(), LDBase->isNonTemporal(), 4698 LDBase->getAlignment()); 4699 } else if (NumElems == 4 && LastLoadedElt == 1 && 4700 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4701 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4702 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4703 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, 4704 Ops, 2, MVT::i32, 4705 LDBase->getMemOperand()); 4706 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4707 } 4708 return SDValue(); 4709} 4710 4711SDValue 4712X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 4713 DebugLoc dl = Op.getDebugLoc(); 4714 4715 EVT VT = Op.getValueType(); 4716 EVT ExtVT = VT.getVectorElementType(); 4717 unsigned NumElems = Op.getNumOperands(); 4718 4719 // Vectors containing all zeros can be matched by pxor and xorps later 4720 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 4721 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 4722 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 4723 if (Op.getValueType() == MVT::v4i32 || 4724 Op.getValueType() == MVT::v8i32) 4725 return Op; 4726 4727 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 4728 } 4729 4730 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 4731 // vectors or broken into v4i32 operations on 256-bit vectors. 4732 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 4733 if (Op.getValueType() == MVT::v4i32) 4734 return Op; 4735 4736 return getOnesVector(Op.getValueType(), DAG, dl); 4737 } 4738 4739 unsigned EVTBits = ExtVT.getSizeInBits(); 4740 4741 unsigned NumZero = 0; 4742 unsigned NumNonZero = 0; 4743 unsigned NonZeros = 0; 4744 bool IsAllConstants = true; 4745 SmallSet<SDValue, 8> Values; 4746 for (unsigned i = 0; i < NumElems; ++i) { 4747 SDValue Elt = Op.getOperand(i); 4748 if (Elt.getOpcode() == ISD::UNDEF) 4749 continue; 4750 Values.insert(Elt); 4751 if (Elt.getOpcode() != ISD::Constant && 4752 Elt.getOpcode() != ISD::ConstantFP) 4753 IsAllConstants = false; 4754 if (X86::isZeroNode(Elt)) 4755 NumZero++; 4756 else { 4757 NonZeros |= (1 << i); 4758 NumNonZero++; 4759 } 4760 } 4761 4762 // All undef vector. Return an UNDEF. All zero vectors were handled above. 4763 if (NumNonZero == 0) 4764 return DAG.getUNDEF(VT); 4765 4766 // Special case for single non-zero, non-undef, element. 4767 if (NumNonZero == 1) { 4768 unsigned Idx = CountTrailingZeros_32(NonZeros); 4769 SDValue Item = Op.getOperand(Idx); 4770 4771 // If this is an insertion of an i64 value on x86-32, and if the top bits of 4772 // the value are obviously zero, truncate the value to i32 and do the 4773 // insertion that way. Only do this if the value is non-constant or if the 4774 // value is a constant being inserted into element 0. It is cheaper to do 4775 // a constant pool load than it is to do a movd + shuffle. 4776 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 4777 (!IsAllConstants || Idx == 0)) { 4778 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 4779 // Handle SSE only. 4780 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 4781 EVT VecVT = MVT::v4i32; 4782 unsigned VecElts = 4; 4783 4784 // Truncate the value (which may itself be a constant) to i32, and 4785 // convert it to a vector with movd (S2V+shuffle to zero extend). 4786 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 4787 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 4788 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4789 Subtarget->hasSSE2(), DAG); 4790 4791 // Now we have our 32-bit value zero extended in the low element of 4792 // a vector. If Idx != 0, swizzle it into place. 4793 if (Idx != 0) { 4794 SmallVector<int, 4> Mask; 4795 Mask.push_back(Idx); 4796 for (unsigned i = 1; i != VecElts; ++i) 4797 Mask.push_back(i); 4798 Item = DAG.getVectorShuffle(VecVT, dl, Item, 4799 DAG.getUNDEF(Item.getValueType()), 4800 &Mask[0]); 4801 } 4802 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 4803 } 4804 } 4805 4806 // If we have a constant or non-constant insertion into the low element of 4807 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 4808 // the rest of the elements. This will be matched as movd/movq/movss/movsd 4809 // depending on what the source datatype is. 4810 if (Idx == 0) { 4811 if (NumZero == 0) { 4812 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4813 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 4814 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 4815 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4816 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 4817 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 4818 DAG); 4819 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 4820 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 4821 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 4822 EVT MiddleVT = MVT::v4i32; 4823 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 4824 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 4825 Subtarget->hasSSE2(), DAG); 4826 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 4827 } 4828 } 4829 4830 // Is it a vector logical left shift? 4831 if (NumElems == 2 && Idx == 1 && 4832 X86::isZeroNode(Op.getOperand(0)) && 4833 !X86::isZeroNode(Op.getOperand(1))) { 4834 unsigned NumBits = VT.getSizeInBits(); 4835 return getVShift(true, VT, 4836 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4837 VT, Op.getOperand(1)), 4838 NumBits/2, DAG, *this, dl); 4839 } 4840 4841 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 4842 return SDValue(); 4843 4844 // Otherwise, if this is a vector with i32 or f32 elements, and the element 4845 // is a non-constant being inserted into an element other than the low one, 4846 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 4847 // movd/movss) to move this into the low element, then shuffle it into 4848 // place. 4849 if (EVTBits == 32) { 4850 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 4851 4852 // Turn it into a shuffle of zero and zero-extended scalar to vector. 4853 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 4854 Subtarget->hasSSE2(), DAG); 4855 SmallVector<int, 8> MaskVec; 4856 for (unsigned i = 0; i < NumElems; i++) 4857 MaskVec.push_back(i == Idx ? 0 : 1); 4858 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 4859 } 4860 } 4861 4862 // Splat is obviously ok. Let legalizer expand it to a shuffle. 4863 if (Values.size() == 1) { 4864 if (EVTBits == 32) { 4865 // Instead of a shuffle like this: 4866 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 4867 // Check if it's possible to issue this instead. 4868 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 4869 unsigned Idx = CountTrailingZeros_32(NonZeros); 4870 SDValue Item = Op.getOperand(Idx); 4871 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 4872 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 4873 } 4874 return SDValue(); 4875 } 4876 4877 // A vector full of immediates; various special cases are already 4878 // handled, so this is best done with a single constant-pool load. 4879 if (IsAllConstants) 4880 return SDValue(); 4881 4882 // For AVX-length vectors, build the individual 128-bit pieces and use 4883 // shuffles to put them in place. 4884 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 4885 SmallVector<SDValue, 32> V; 4886 for (unsigned i = 0; i < NumElems; ++i) 4887 V.push_back(Op.getOperand(i)); 4888 4889 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 4890 4891 // Build both the lower and upper subvector. 4892 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 4893 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 4894 NumElems/2); 4895 4896 // Recreate the wider vector with the lower and upper part. 4897 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 4898 DAG.getConstant(0, MVT::i32), DAG, dl); 4899 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 4900 DAG, dl); 4901 } 4902 4903 // Let legalizer expand 2-wide build_vectors. 4904 if (EVTBits == 64) { 4905 if (NumNonZero == 1) { 4906 // One half is zero or undef. 4907 unsigned Idx = CountTrailingZeros_32(NonZeros); 4908 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 4909 Op.getOperand(Idx)); 4910 return getShuffleVectorZeroOrUndef(V2, Idx, true, 4911 Subtarget->hasSSE2(), DAG); 4912 } 4913 return SDValue(); 4914 } 4915 4916 // If element VT is < 32 bits, convert it to inserts into a zero vector. 4917 if (EVTBits == 8 && NumElems == 16) { 4918 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 4919 *this); 4920 if (V.getNode()) return V; 4921 } 4922 4923 if (EVTBits == 16 && NumElems == 8) { 4924 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 4925 *this); 4926 if (V.getNode()) return V; 4927 } 4928 4929 // If element VT is == 32 bits, turn it into a number of shuffles. 4930 SmallVector<SDValue, 8> V; 4931 V.resize(NumElems); 4932 if (NumElems == 4 && NumZero > 0) { 4933 for (unsigned i = 0; i < 4; ++i) { 4934 bool isZero = !(NonZeros & (1 << i)); 4935 if (isZero) 4936 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4937 else 4938 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 4939 } 4940 4941 for (unsigned i = 0; i < 2; ++i) { 4942 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 4943 default: break; 4944 case 0: 4945 V[i] = V[i*2]; // Must be a zero vector. 4946 break; 4947 case 1: 4948 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 4949 break; 4950 case 2: 4951 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 4952 break; 4953 case 3: 4954 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 4955 break; 4956 } 4957 } 4958 4959 SmallVector<int, 8> MaskVec; 4960 bool Reverse = (NonZeros & 0x3) == 2; 4961 for (unsigned i = 0; i < 2; ++i) 4962 MaskVec.push_back(Reverse ? 1-i : i); 4963 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 4964 for (unsigned i = 0; i < 2; ++i) 4965 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 4966 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 4967 } 4968 4969 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 4970 // Check for a build vector of consecutive loads. 4971 for (unsigned i = 0; i < NumElems; ++i) 4972 V[i] = Op.getOperand(i); 4973 4974 // Check for elements which are consecutive loads. 4975 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 4976 if (LD.getNode()) 4977 return LD; 4978 4979 // For SSE 4.1, use insertps to put the high elements into the low element. 4980 if (getSubtarget()->hasSSE41()) { 4981 SDValue Result; 4982 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 4983 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 4984 else 4985 Result = DAG.getUNDEF(VT); 4986 4987 for (unsigned i = 1; i < NumElems; ++i) { 4988 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 4989 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 4990 Op.getOperand(i), DAG.getIntPtrConstant(i)); 4991 } 4992 return Result; 4993 } 4994 4995 // Otherwise, expand into a number of unpckl*, start by extending each of 4996 // our (non-undef) elements to the full vector width with the element in the 4997 // bottom slot of the vector (which generates no code for SSE). 4998 for (unsigned i = 0; i < NumElems; ++i) { 4999 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5000 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5001 else 5002 V[i] = DAG.getUNDEF(VT); 5003 } 5004 5005 // Next, we iteratively mix elements, e.g. for v4f32: 5006 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5007 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5008 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5009 unsigned EltStride = NumElems >> 1; 5010 while (EltStride != 0) { 5011 for (unsigned i = 0; i < EltStride; ++i) { 5012 // If V[i+EltStride] is undef and this is the first round of mixing, 5013 // then it is safe to just drop this shuffle: V[i] is already in the 5014 // right place, the one element (since it's the first round) being 5015 // inserted as undef can be dropped. This isn't safe for successive 5016 // rounds because they will permute elements within both vectors. 5017 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5018 EltStride == NumElems/2) 5019 continue; 5020 5021 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5022 } 5023 EltStride >>= 1; 5024 } 5025 return V[0]; 5026 } 5027 return SDValue(); 5028} 5029 5030// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5031// them in a MMX register. This is better than doing a stack convert. 5032static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5033 DebugLoc dl = Op.getDebugLoc(); 5034 EVT ResVT = Op.getValueType(); 5035 5036 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5037 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5038 int Mask[2]; 5039 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5040 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5041 InVec = Op.getOperand(1); 5042 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5043 unsigned NumElts = ResVT.getVectorNumElements(); 5044 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5045 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5046 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5047 } else { 5048 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5049 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5050 Mask[0] = 0; Mask[1] = 2; 5051 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5052 } 5053 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5054} 5055 5056// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5057// to create 256-bit vectors from two other 128-bit ones. 5058static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5059 DebugLoc dl = Op.getDebugLoc(); 5060 EVT ResVT = Op.getValueType(); 5061 5062 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5063 5064 SDValue V1 = Op.getOperand(0); 5065 SDValue V2 = Op.getOperand(1); 5066 unsigned NumElems = ResVT.getVectorNumElements(); 5067 5068 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5069 DAG.getConstant(0, MVT::i32), DAG, dl); 5070 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5071 DAG, dl); 5072} 5073 5074SDValue 5075X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5076 EVT ResVT = Op.getValueType(); 5077 5078 assert(Op.getNumOperands() == 2); 5079 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5080 "Unsupported CONCAT_VECTORS for value type"); 5081 5082 // We support concatenate two MMX registers and place them in a MMX register. 5083 // This is better than doing a stack convert. 5084 if (ResVT.is128BitVector()) 5085 return LowerMMXCONCAT_VECTORS(Op, DAG); 5086 5087 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5088 // from two other 128-bit ones. 5089 return LowerAVXCONCAT_VECTORS(Op, DAG); 5090} 5091 5092// v8i16 shuffles - Prefer shuffles in the following order: 5093// 1. [all] pshuflw, pshufhw, optional move 5094// 2. [ssse3] 1 x pshufb 5095// 3. [ssse3] 2 x pshufb + 1 x por 5096// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5097SDValue 5098X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5099 SelectionDAG &DAG) const { 5100 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5101 SDValue V1 = SVOp->getOperand(0); 5102 SDValue V2 = SVOp->getOperand(1); 5103 DebugLoc dl = SVOp->getDebugLoc(); 5104 SmallVector<int, 8> MaskVals; 5105 5106 // Determine if more than 1 of the words in each of the low and high quadwords 5107 // of the result come from the same quadword of one of the two inputs. Undef 5108 // mask values count as coming from any quadword, for better codegen. 5109 SmallVector<unsigned, 4> LoQuad(4); 5110 SmallVector<unsigned, 4> HiQuad(4); 5111 BitVector InputQuads(4); 5112 for (unsigned i = 0; i < 8; ++i) { 5113 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 5114 int EltIdx = SVOp->getMaskElt(i); 5115 MaskVals.push_back(EltIdx); 5116 if (EltIdx < 0) { 5117 ++Quad[0]; 5118 ++Quad[1]; 5119 ++Quad[2]; 5120 ++Quad[3]; 5121 continue; 5122 } 5123 ++Quad[EltIdx / 4]; 5124 InputQuads.set(EltIdx / 4); 5125 } 5126 5127 int BestLoQuad = -1; 5128 unsigned MaxQuad = 1; 5129 for (unsigned i = 0; i < 4; ++i) { 5130 if (LoQuad[i] > MaxQuad) { 5131 BestLoQuad = i; 5132 MaxQuad = LoQuad[i]; 5133 } 5134 } 5135 5136 int BestHiQuad = -1; 5137 MaxQuad = 1; 5138 for (unsigned i = 0; i < 4; ++i) { 5139 if (HiQuad[i] > MaxQuad) { 5140 BestHiQuad = i; 5141 MaxQuad = HiQuad[i]; 5142 } 5143 } 5144 5145 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5146 // of the two input vectors, shuffle them into one input vector so only a 5147 // single pshufb instruction is necessary. If There are more than 2 input 5148 // quads, disable the next transformation since it does not help SSSE3. 5149 bool V1Used = InputQuads[0] || InputQuads[1]; 5150 bool V2Used = InputQuads[2] || InputQuads[3]; 5151 if (Subtarget->hasSSSE3()) { 5152 if (InputQuads.count() == 2 && V1Used && V2Used) { 5153 BestLoQuad = InputQuads.find_first(); 5154 BestHiQuad = InputQuads.find_next(BestLoQuad); 5155 } 5156 if (InputQuads.count() > 2) { 5157 BestLoQuad = -1; 5158 BestHiQuad = -1; 5159 } 5160 } 5161 5162 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5163 // the shuffle mask. If a quad is scored as -1, that means that it contains 5164 // words from all 4 input quadwords. 5165 SDValue NewV; 5166 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5167 SmallVector<int, 8> MaskV; 5168 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5169 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5170 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5171 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5172 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5173 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5174 5175 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5176 // source words for the shuffle, to aid later transformations. 5177 bool AllWordsInNewV = true; 5178 bool InOrder[2] = { true, true }; 5179 for (unsigned i = 0; i != 8; ++i) { 5180 int idx = MaskVals[i]; 5181 if (idx != (int)i) 5182 InOrder[i/4] = false; 5183 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5184 continue; 5185 AllWordsInNewV = false; 5186 break; 5187 } 5188 5189 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5190 if (AllWordsInNewV) { 5191 for (int i = 0; i != 8; ++i) { 5192 int idx = MaskVals[i]; 5193 if (idx < 0) 5194 continue; 5195 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5196 if ((idx != i) && idx < 4) 5197 pshufhw = false; 5198 if ((idx != i) && idx > 3) 5199 pshuflw = false; 5200 } 5201 V1 = NewV; 5202 V2Used = false; 5203 BestLoQuad = 0; 5204 BestHiQuad = 1; 5205 } 5206 5207 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5208 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5209 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5210 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5211 unsigned TargetMask = 0; 5212 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5213 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5214 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5215 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5216 V1 = NewV.getOperand(0); 5217 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5218 } 5219 } 5220 5221 // If we have SSSE3, and all words of the result are from 1 input vector, 5222 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5223 // is present, fall back to case 4. 5224 if (Subtarget->hasSSSE3()) { 5225 SmallVector<SDValue,16> pshufbMask; 5226 5227 // If we have elements from both input vectors, set the high bit of the 5228 // shuffle mask element to zero out elements that come from V2 in the V1 5229 // mask, and elements that come from V1 in the V2 mask, so that the two 5230 // results can be OR'd together. 5231 bool TwoInputs = V1Used && V2Used; 5232 for (unsigned i = 0; i != 8; ++i) { 5233 int EltIdx = MaskVals[i] * 2; 5234 if (TwoInputs && (EltIdx >= 16)) { 5235 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5236 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5237 continue; 5238 } 5239 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5240 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5241 } 5242 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5243 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5244 DAG.getNode(ISD::BUILD_VECTOR, dl, 5245 MVT::v16i8, &pshufbMask[0], 16)); 5246 if (!TwoInputs) 5247 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5248 5249 // Calculate the shuffle mask for the second input, shuffle it, and 5250 // OR it with the first shuffled input. 5251 pshufbMask.clear(); 5252 for (unsigned i = 0; i != 8; ++i) { 5253 int EltIdx = MaskVals[i] * 2; 5254 if (EltIdx < 16) { 5255 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5256 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5257 continue; 5258 } 5259 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5260 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5261 } 5262 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5263 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5264 DAG.getNode(ISD::BUILD_VECTOR, dl, 5265 MVT::v16i8, &pshufbMask[0], 16)); 5266 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5267 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5268 } 5269 5270 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5271 // and update MaskVals with new element order. 5272 BitVector InOrder(8); 5273 if (BestLoQuad >= 0) { 5274 SmallVector<int, 8> MaskV; 5275 for (int i = 0; i != 4; ++i) { 5276 int idx = MaskVals[i]; 5277 if (idx < 0) { 5278 MaskV.push_back(-1); 5279 InOrder.set(i); 5280 } else if ((idx / 4) == BestLoQuad) { 5281 MaskV.push_back(idx & 3); 5282 InOrder.set(i); 5283 } else { 5284 MaskV.push_back(-1); 5285 } 5286 } 5287 for (unsigned i = 4; i != 8; ++i) 5288 MaskV.push_back(i); 5289 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5290 &MaskV[0]); 5291 5292 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5293 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5294 NewV.getOperand(0), 5295 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5296 DAG); 5297 } 5298 5299 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5300 // and update MaskVals with the new element order. 5301 if (BestHiQuad >= 0) { 5302 SmallVector<int, 8> MaskV; 5303 for (unsigned i = 0; i != 4; ++i) 5304 MaskV.push_back(i); 5305 for (unsigned i = 4; i != 8; ++i) { 5306 int idx = MaskVals[i]; 5307 if (idx < 0) { 5308 MaskV.push_back(-1); 5309 InOrder.set(i); 5310 } else if ((idx / 4) == BestHiQuad) { 5311 MaskV.push_back((idx & 3) + 4); 5312 InOrder.set(i); 5313 } else { 5314 MaskV.push_back(-1); 5315 } 5316 } 5317 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5318 &MaskV[0]); 5319 5320 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5321 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5322 NewV.getOperand(0), 5323 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5324 DAG); 5325 } 5326 5327 // In case BestHi & BestLo were both -1, which means each quadword has a word 5328 // from each of the four input quadwords, calculate the InOrder bitvector now 5329 // before falling through to the insert/extract cleanup. 5330 if (BestLoQuad == -1 && BestHiQuad == -1) { 5331 NewV = V1; 5332 for (int i = 0; i != 8; ++i) 5333 if (MaskVals[i] < 0 || MaskVals[i] == i) 5334 InOrder.set(i); 5335 } 5336 5337 // The other elements are put in the right place using pextrw and pinsrw. 5338 for (unsigned i = 0; i != 8; ++i) { 5339 if (InOrder[i]) 5340 continue; 5341 int EltIdx = MaskVals[i]; 5342 if (EltIdx < 0) 5343 continue; 5344 SDValue ExtOp = (EltIdx < 8) 5345 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5346 DAG.getIntPtrConstant(EltIdx)) 5347 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5348 DAG.getIntPtrConstant(EltIdx - 8)); 5349 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5350 DAG.getIntPtrConstant(i)); 5351 } 5352 return NewV; 5353} 5354 5355// v16i8 shuffles - Prefer shuffles in the following order: 5356// 1. [ssse3] 1 x pshufb 5357// 2. [ssse3] 2 x pshufb + 1 x por 5358// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5359static 5360SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5361 SelectionDAG &DAG, 5362 const X86TargetLowering &TLI) { 5363 SDValue V1 = SVOp->getOperand(0); 5364 SDValue V2 = SVOp->getOperand(1); 5365 DebugLoc dl = SVOp->getDebugLoc(); 5366 SmallVector<int, 16> MaskVals; 5367 SVOp->getMask(MaskVals); 5368 5369 // If we have SSSE3, case 1 is generated when all result bytes come from 5370 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5371 // present, fall back to case 3. 5372 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5373 bool V1Only = true; 5374 bool V2Only = true; 5375 for (unsigned i = 0; i < 16; ++i) { 5376 int EltIdx = MaskVals[i]; 5377 if (EltIdx < 0) 5378 continue; 5379 if (EltIdx < 16) 5380 V2Only = false; 5381 else 5382 V1Only = false; 5383 } 5384 5385 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5386 if (TLI.getSubtarget()->hasSSSE3()) { 5387 SmallVector<SDValue,16> pshufbMask; 5388 5389 // If all result elements are from one input vector, then only translate 5390 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5391 // 5392 // Otherwise, we have elements from both input vectors, and must zero out 5393 // elements that come from V2 in the first mask, and V1 in the second mask 5394 // so that we can OR them together. 5395 bool TwoInputs = !(V1Only || V2Only); 5396 for (unsigned i = 0; i != 16; ++i) { 5397 int EltIdx = MaskVals[i]; 5398 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5399 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5400 continue; 5401 } 5402 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5403 } 5404 // If all the elements are from V2, assign it to V1 and return after 5405 // building the first pshufb. 5406 if (V2Only) 5407 V1 = V2; 5408 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5409 DAG.getNode(ISD::BUILD_VECTOR, dl, 5410 MVT::v16i8, &pshufbMask[0], 16)); 5411 if (!TwoInputs) 5412 return V1; 5413 5414 // Calculate the shuffle mask for the second input, shuffle it, and 5415 // OR it with the first shuffled input. 5416 pshufbMask.clear(); 5417 for (unsigned i = 0; i != 16; ++i) { 5418 int EltIdx = MaskVals[i]; 5419 if (EltIdx < 16) { 5420 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5421 continue; 5422 } 5423 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5424 } 5425 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5426 DAG.getNode(ISD::BUILD_VECTOR, dl, 5427 MVT::v16i8, &pshufbMask[0], 16)); 5428 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5429 } 5430 5431 // No SSSE3 - Calculate in place words and then fix all out of place words 5432 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5433 // the 16 different words that comprise the two doublequadword input vectors. 5434 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5435 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5436 SDValue NewV = V2Only ? V2 : V1; 5437 for (int i = 0; i != 8; ++i) { 5438 int Elt0 = MaskVals[i*2]; 5439 int Elt1 = MaskVals[i*2+1]; 5440 5441 // This word of the result is all undef, skip it. 5442 if (Elt0 < 0 && Elt1 < 0) 5443 continue; 5444 5445 // This word of the result is already in the correct place, skip it. 5446 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5447 continue; 5448 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5449 continue; 5450 5451 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5452 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5453 SDValue InsElt; 5454 5455 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5456 // using a single extract together, load it and store it. 5457 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5458 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5459 DAG.getIntPtrConstant(Elt1 / 2)); 5460 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5461 DAG.getIntPtrConstant(i)); 5462 continue; 5463 } 5464 5465 // If Elt1 is defined, extract it from the appropriate source. If the 5466 // source byte is not also odd, shift the extracted word left 8 bits 5467 // otherwise clear the bottom 8 bits if we need to do an or. 5468 if (Elt1 >= 0) { 5469 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5470 DAG.getIntPtrConstant(Elt1 / 2)); 5471 if ((Elt1 & 1) == 0) 5472 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5473 DAG.getConstant(8, 5474 TLI.getShiftAmountTy(InsElt.getValueType()))); 5475 else if (Elt0 >= 0) 5476 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5477 DAG.getConstant(0xFF00, MVT::i16)); 5478 } 5479 // If Elt0 is defined, extract it from the appropriate source. If the 5480 // source byte is not also even, shift the extracted word right 8 bits. If 5481 // Elt1 was also defined, OR the extracted values together before 5482 // inserting them in the result. 5483 if (Elt0 >= 0) { 5484 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5485 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5486 if ((Elt0 & 1) != 0) 5487 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5488 DAG.getConstant(8, 5489 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5490 else if (Elt1 >= 0) 5491 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5492 DAG.getConstant(0x00FF, MVT::i16)); 5493 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5494 : InsElt0; 5495 } 5496 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5497 DAG.getIntPtrConstant(i)); 5498 } 5499 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5500} 5501 5502/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5503/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5504/// done when every pair / quad of shuffle mask elements point to elements in 5505/// the right sequence. e.g. 5506/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5507static 5508SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5509 SelectionDAG &DAG, DebugLoc dl) { 5510 EVT VT = SVOp->getValueType(0); 5511 SDValue V1 = SVOp->getOperand(0); 5512 SDValue V2 = SVOp->getOperand(1); 5513 unsigned NumElems = VT.getVectorNumElements(); 5514 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5515 EVT NewVT; 5516 switch (VT.getSimpleVT().SimpleTy) { 5517 default: assert(false && "Unexpected!"); 5518 case MVT::v4f32: NewVT = MVT::v2f64; break; 5519 case MVT::v4i32: NewVT = MVT::v2i64; break; 5520 case MVT::v8i16: NewVT = MVT::v4i32; break; 5521 case MVT::v16i8: NewVT = MVT::v4i32; break; 5522 } 5523 5524 int Scale = NumElems / NewWidth; 5525 SmallVector<int, 8> MaskVec; 5526 for (unsigned i = 0; i < NumElems; i += Scale) { 5527 int StartIdx = -1; 5528 for (int j = 0; j < Scale; ++j) { 5529 int EltIdx = SVOp->getMaskElt(i+j); 5530 if (EltIdx < 0) 5531 continue; 5532 if (StartIdx == -1) 5533 StartIdx = EltIdx - (EltIdx % Scale); 5534 if (EltIdx != StartIdx + j) 5535 return SDValue(); 5536 } 5537 if (StartIdx == -1) 5538 MaskVec.push_back(-1); 5539 else 5540 MaskVec.push_back(StartIdx / Scale); 5541 } 5542 5543 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5544 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5545 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5546} 5547 5548/// getVZextMovL - Return a zero-extending vector move low node. 5549/// 5550static SDValue getVZextMovL(EVT VT, EVT OpVT, 5551 SDValue SrcOp, SelectionDAG &DAG, 5552 const X86Subtarget *Subtarget, DebugLoc dl) { 5553 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5554 LoadSDNode *LD = NULL; 5555 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5556 LD = dyn_cast<LoadSDNode>(SrcOp); 5557 if (!LD) { 5558 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5559 // instead. 5560 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5561 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5562 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5563 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5564 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5565 // PR2108 5566 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5567 return DAG.getNode(ISD::BITCAST, dl, VT, 5568 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5569 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5570 OpVT, 5571 SrcOp.getOperand(0) 5572 .getOperand(0)))); 5573 } 5574 } 5575 } 5576 5577 return DAG.getNode(ISD::BITCAST, dl, VT, 5578 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5579 DAG.getNode(ISD::BITCAST, dl, 5580 OpVT, SrcOp))); 5581} 5582 5583/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5584/// which could not be matched by any known target speficic shuffle 5585static SDValue 5586LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5587 return SDValue(); 5588} 5589 5590/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 5591/// 4 elements, and match them with several different shuffle types. 5592static SDValue 5593LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5594 SDValue V1 = SVOp->getOperand(0); 5595 SDValue V2 = SVOp->getOperand(1); 5596 DebugLoc dl = SVOp->getDebugLoc(); 5597 EVT VT = SVOp->getValueType(0); 5598 5599 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 5600 5601 SmallVector<std::pair<int, int>, 8> Locs; 5602 Locs.resize(4); 5603 SmallVector<int, 8> Mask1(4U, -1); 5604 SmallVector<int, 8> PermMask; 5605 SVOp->getMask(PermMask); 5606 5607 unsigned NumHi = 0; 5608 unsigned NumLo = 0; 5609 for (unsigned i = 0; i != 4; ++i) { 5610 int Idx = PermMask[i]; 5611 if (Idx < 0) { 5612 Locs[i] = std::make_pair(-1, -1); 5613 } else { 5614 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 5615 if (Idx < 4) { 5616 Locs[i] = std::make_pair(0, NumLo); 5617 Mask1[NumLo] = Idx; 5618 NumLo++; 5619 } else { 5620 Locs[i] = std::make_pair(1, NumHi); 5621 if (2+NumHi < 4) 5622 Mask1[2+NumHi] = Idx; 5623 NumHi++; 5624 } 5625 } 5626 } 5627 5628 if (NumLo <= 2 && NumHi <= 2) { 5629 // If no more than two elements come from either vector. This can be 5630 // implemented with two shuffles. First shuffle gather the elements. 5631 // The second shuffle, which takes the first shuffle as both of its 5632 // vector operands, put the elements into the right order. 5633 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5634 5635 SmallVector<int, 8> Mask2(4U, -1); 5636 5637 for (unsigned i = 0; i != 4; ++i) { 5638 if (Locs[i].first == -1) 5639 continue; 5640 else { 5641 unsigned Idx = (i < 2) ? 0 : 4; 5642 Idx += Locs[i].first * 2 + Locs[i].second; 5643 Mask2[i] = Idx; 5644 } 5645 } 5646 5647 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 5648 } else if (NumLo == 3 || NumHi == 3) { 5649 // Otherwise, we must have three elements from one vector, call it X, and 5650 // one element from the other, call it Y. First, use a shufps to build an 5651 // intermediate vector with the one element from Y and the element from X 5652 // that will be in the same half in the final destination (the indexes don't 5653 // matter). Then, use a shufps to build the final vector, taking the half 5654 // containing the element from Y from the intermediate, and the other half 5655 // from X. 5656 if (NumHi == 3) { 5657 // Normalize it so the 3 elements come from V1. 5658 CommuteVectorShuffleMask(PermMask, VT); 5659 std::swap(V1, V2); 5660 } 5661 5662 // Find the element from V2. 5663 unsigned HiIndex; 5664 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 5665 int Val = PermMask[HiIndex]; 5666 if (Val < 0) 5667 continue; 5668 if (Val >= 4) 5669 break; 5670 } 5671 5672 Mask1[0] = PermMask[HiIndex]; 5673 Mask1[1] = -1; 5674 Mask1[2] = PermMask[HiIndex^1]; 5675 Mask1[3] = -1; 5676 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5677 5678 if (HiIndex >= 2) { 5679 Mask1[0] = PermMask[0]; 5680 Mask1[1] = PermMask[1]; 5681 Mask1[2] = HiIndex & 1 ? 6 : 4; 5682 Mask1[3] = HiIndex & 1 ? 4 : 6; 5683 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 5684 } else { 5685 Mask1[0] = HiIndex & 1 ? 2 : 0; 5686 Mask1[1] = HiIndex & 1 ? 0 : 2; 5687 Mask1[2] = PermMask[2]; 5688 Mask1[3] = PermMask[3]; 5689 if (Mask1[2] >= 0) 5690 Mask1[2] += 4; 5691 if (Mask1[3] >= 0) 5692 Mask1[3] += 4; 5693 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 5694 } 5695 } 5696 5697 // Break it into (shuffle shuffle_hi, shuffle_lo). 5698 Locs.clear(); 5699 Locs.resize(4); 5700 SmallVector<int,8> LoMask(4U, -1); 5701 SmallVector<int,8> HiMask(4U, -1); 5702 5703 SmallVector<int,8> *MaskPtr = &LoMask; 5704 unsigned MaskIdx = 0; 5705 unsigned LoIdx = 0; 5706 unsigned HiIdx = 2; 5707 for (unsigned i = 0; i != 4; ++i) { 5708 if (i == 2) { 5709 MaskPtr = &HiMask; 5710 MaskIdx = 1; 5711 LoIdx = 0; 5712 HiIdx = 2; 5713 } 5714 int Idx = PermMask[i]; 5715 if (Idx < 0) { 5716 Locs[i] = std::make_pair(-1, -1); 5717 } else if (Idx < 4) { 5718 Locs[i] = std::make_pair(MaskIdx, LoIdx); 5719 (*MaskPtr)[LoIdx] = Idx; 5720 LoIdx++; 5721 } else { 5722 Locs[i] = std::make_pair(MaskIdx, HiIdx); 5723 (*MaskPtr)[HiIdx] = Idx; 5724 HiIdx++; 5725 } 5726 } 5727 5728 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 5729 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 5730 SmallVector<int, 8> MaskOps; 5731 for (unsigned i = 0; i != 4; ++i) { 5732 if (Locs[i].first == -1) { 5733 MaskOps.push_back(-1); 5734 } else { 5735 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 5736 MaskOps.push_back(Idx); 5737 } 5738 } 5739 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 5740} 5741 5742static bool MayFoldVectorLoad(SDValue V) { 5743 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5744 V = V.getOperand(0); 5745 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5746 V = V.getOperand(0); 5747 if (MayFoldLoad(V)) 5748 return true; 5749 return false; 5750} 5751 5752// FIXME: the version above should always be used. Since there's 5753// a bug where several vector shuffles can't be folded because the 5754// DAG is not updated during lowering and a node claims to have two 5755// uses while it only has one, use this version, and let isel match 5756// another instruction if the load really happens to have more than 5757// one use. Remove this version after this bug get fixed. 5758// rdar://8434668, PR8156 5759static bool RelaxedMayFoldVectorLoad(SDValue V) { 5760 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 5761 V = V.getOperand(0); 5762 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 5763 V = V.getOperand(0); 5764 if (ISD::isNormalLoad(V.getNode())) 5765 return true; 5766 return false; 5767} 5768 5769/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 5770/// a vector extract, and if both can be later optimized into a single load. 5771/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 5772/// here because otherwise a target specific shuffle node is going to be 5773/// emitted for this shuffle, and the optimization not done. 5774/// FIXME: This is probably not the best approach, but fix the problem 5775/// until the right path is decided. 5776static 5777bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 5778 const TargetLowering &TLI) { 5779 EVT VT = V.getValueType(); 5780 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 5781 5782 // Be sure that the vector shuffle is present in a pattern like this: 5783 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 5784 if (!V.hasOneUse()) 5785 return false; 5786 5787 SDNode *N = *V.getNode()->use_begin(); 5788 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 5789 return false; 5790 5791 SDValue EltNo = N->getOperand(1); 5792 if (!isa<ConstantSDNode>(EltNo)) 5793 return false; 5794 5795 // If the bit convert changed the number of elements, it is unsafe 5796 // to examine the mask. 5797 bool HasShuffleIntoBitcast = false; 5798 if (V.getOpcode() == ISD::BITCAST) { 5799 EVT SrcVT = V.getOperand(0).getValueType(); 5800 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 5801 return false; 5802 V = V.getOperand(0); 5803 HasShuffleIntoBitcast = true; 5804 } 5805 5806 // Select the input vector, guarding against out of range extract vector. 5807 unsigned NumElems = VT.getVectorNumElements(); 5808 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5809 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 5810 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 5811 5812 // Skip one more bit_convert if necessary 5813 if (V.getOpcode() == ISD::BITCAST) 5814 V = V.getOperand(0); 5815 5816 if (ISD::isNormalLoad(V.getNode())) { 5817 // Is the original load suitable? 5818 LoadSDNode *LN0 = cast<LoadSDNode>(V); 5819 5820 // FIXME: avoid the multi-use bug that is preventing lots of 5821 // of foldings to be detected, this is still wrong of course, but 5822 // give the temporary desired behavior, and if it happens that 5823 // the load has real more uses, during isel it will not fold, and 5824 // will generate poor code. 5825 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 5826 return false; 5827 5828 if (!HasShuffleIntoBitcast) 5829 return true; 5830 5831 // If there's a bitcast before the shuffle, check if the load type and 5832 // alignment is valid. 5833 unsigned Align = LN0->getAlignment(); 5834 unsigned NewAlign = 5835 TLI.getTargetData()->getABITypeAlignment( 5836 VT.getTypeForEVT(*DAG.getContext())); 5837 5838 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 5839 return false; 5840 } 5841 5842 return true; 5843} 5844 5845static 5846SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 5847 EVT VT = Op.getValueType(); 5848 5849 // Canonizalize to v2f64. 5850 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 5851 return DAG.getNode(ISD::BITCAST, dl, VT, 5852 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 5853 V1, DAG)); 5854} 5855 5856static 5857SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 5858 bool HasSSE2) { 5859 SDValue V1 = Op.getOperand(0); 5860 SDValue V2 = Op.getOperand(1); 5861 EVT VT = Op.getValueType(); 5862 5863 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 5864 5865 if (HasSSE2 && VT == MVT::v2f64) 5866 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 5867 5868 // v4f32 or v4i32 5869 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); 5870} 5871 5872static 5873SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 5874 SDValue V1 = Op.getOperand(0); 5875 SDValue V2 = Op.getOperand(1); 5876 EVT VT = Op.getValueType(); 5877 5878 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 5879 "unsupported shuffle type"); 5880 5881 if (V2.getOpcode() == ISD::UNDEF) 5882 V2 = V1; 5883 5884 // v4i32 or v4f32 5885 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 5886} 5887 5888static 5889SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 5890 SDValue V1 = Op.getOperand(0); 5891 SDValue V2 = Op.getOperand(1); 5892 EVT VT = Op.getValueType(); 5893 unsigned NumElems = VT.getVectorNumElements(); 5894 5895 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 5896 // operand of these instructions is only memory, so check if there's a 5897 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 5898 // same masks. 5899 bool CanFoldLoad = false; 5900 5901 // Trivial case, when V2 comes from a load. 5902 if (MayFoldVectorLoad(V2)) 5903 CanFoldLoad = true; 5904 5905 // When V1 is a load, it can be folded later into a store in isel, example: 5906 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 5907 // turns into: 5908 // (MOVLPSmr addr:$src1, VR128:$src2) 5909 // So, recognize this potential and also use MOVLPS or MOVLPD 5910 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 5911 CanFoldLoad = true; 5912 5913 // Both of them can't be memory operations though. 5914 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) 5915 CanFoldLoad = false; 5916 5917 if (CanFoldLoad) { 5918 if (HasSSE2 && NumElems == 2) 5919 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 5920 5921 if (NumElems == 4) 5922 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 5923 } 5924 5925 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5926 // movl and movlp will both match v2i64, but v2i64 is never matched by 5927 // movl earlier because we make it strict to avoid messing with the movlp load 5928 // folding logic (see the code above getMOVLP call). Match it here then, 5929 // this is horrible, but will stay like this until we move all shuffle 5930 // matching to x86 specific nodes. Note that for the 1st condition all 5931 // types are matched with movsd. 5932 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) 5933 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 5934 else if (HasSSE2) 5935 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 5936 5937 5938 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 5939 5940 // Invert the operand order and use SHUFPS to match it. 5941 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, 5942 X86::getShuffleSHUFImmediate(SVOp), DAG); 5943} 5944 5945static inline unsigned getUNPCKLOpcode(EVT VT) { 5946 switch(VT.getSimpleVT().SimpleTy) { 5947 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 5948 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 5949 case MVT::v4f32: return X86ISD::UNPCKLPS; 5950 case MVT::v2f64: return X86ISD::UNPCKLPD; 5951 case MVT::v8i32: // Use fp unit for int unpack. 5952 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 5953 case MVT::v4i64: // Use fp unit for int unpack. 5954 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 5955 case MVT::v16i8: return X86ISD::PUNPCKLBW; 5956 case MVT::v8i16: return X86ISD::PUNPCKLWD; 5957 default: 5958 llvm_unreachable("Unknown type for unpckl"); 5959 } 5960 return 0; 5961} 5962 5963static inline unsigned getUNPCKHOpcode(EVT VT) { 5964 switch(VT.getSimpleVT().SimpleTy) { 5965 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 5966 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 5967 case MVT::v4f32: return X86ISD::UNPCKHPS; 5968 case MVT::v2f64: return X86ISD::UNPCKHPD; 5969 case MVT::v8i32: // Use fp unit for int unpack. 5970 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 5971 case MVT::v4i64: // Use fp unit for int unpack. 5972 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 5973 case MVT::v16i8: return X86ISD::PUNPCKHBW; 5974 case MVT::v8i16: return X86ISD::PUNPCKHWD; 5975 default: 5976 llvm_unreachable("Unknown type for unpckh"); 5977 } 5978 return 0; 5979} 5980 5981static inline unsigned getVPERMILOpcode(EVT VT) { 5982 switch(VT.getSimpleVT().SimpleTy) { 5983 case MVT::v4i32: 5984 case MVT::v4f32: return X86ISD::VPERMILPS; 5985 case MVT::v2i64: 5986 case MVT::v2f64: return X86ISD::VPERMILPD; 5987 case MVT::v8i32: 5988 case MVT::v8f32: return X86ISD::VPERMILPSY; 5989 case MVT::v4i64: 5990 case MVT::v4f64: return X86ISD::VPERMILPDY; 5991 default: 5992 llvm_unreachable("Unknown type for vpermil"); 5993 } 5994 return 0; 5995} 5996 5997static 5998SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 5999 const TargetLowering &TLI, 6000 const X86Subtarget *Subtarget) { 6001 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6002 EVT VT = Op.getValueType(); 6003 DebugLoc dl = Op.getDebugLoc(); 6004 SDValue V1 = Op.getOperand(0); 6005 SDValue V2 = Op.getOperand(1); 6006 6007 if (isZeroShuffle(SVOp)) 6008 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 6009 6010 // Handle splat operations 6011 if (SVOp->isSplat()) { 6012 unsigned NumElem = VT.getVectorNumElements(); 6013 // Special case, this is the only place now where it's allowed to return 6014 // a vector_shuffle operation without using a target specific node, because 6015 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6016 // this be moved to DAGCombine instead? 6017 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6018 return Op; 6019 6020 // Since there's no native support for scalar_to_vector for 256-bit AVX, a 6021 // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this 6022 // idiom and do the shuffle before the insertion, this yields less 6023 // instructions in the end. 6024 if (VT.is256BitVector() && 6025 V1.getOpcode() == ISD::INSERT_SUBVECTOR && 6026 V1.getOperand(0).getOpcode() == ISD::UNDEF && 6027 V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR) 6028 return PromoteVectorToScalarSplat(SVOp, DAG); 6029 6030 // Handle splats by matching through known shuffle masks 6031 if (VT.is128BitVector() && NumElem <= 4) 6032 return SDValue(); 6033 6034 // All i16 and i8 vector types can't be used directly by a generic shuffle 6035 // instruction because the target has no such instruction. Generate shuffles 6036 // which repeat i16 and i8 several times until they fit in i32, and then can 6037 // be manipulated by target suported shuffles. After the insertion of the 6038 // necessary shuffles, the result is bitcasted back to v4f32 or v8f32. 6039 return PromoteSplat(SVOp, DAG); 6040 } 6041 6042 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6043 // do it! 6044 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6045 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6046 if (NewOp.getNode()) 6047 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6048 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6049 // FIXME: Figure out a cleaner way to do this. 6050 // Try to make use of movq to zero out the top part. 6051 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6052 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6053 if (NewOp.getNode()) { 6054 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6055 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6056 DAG, Subtarget, dl); 6057 } 6058 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6059 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6060 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6061 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6062 DAG, Subtarget, dl); 6063 } 6064 } 6065 return SDValue(); 6066} 6067 6068SDValue 6069X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6071 SDValue V1 = Op.getOperand(0); 6072 SDValue V2 = Op.getOperand(1); 6073 EVT VT = Op.getValueType(); 6074 DebugLoc dl = Op.getDebugLoc(); 6075 unsigned NumElems = VT.getVectorNumElements(); 6076 bool isMMX = VT.getSizeInBits() == 64; 6077 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6078 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6079 bool V1IsSplat = false; 6080 bool V2IsSplat = false; 6081 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); 6082 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); 6083 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); 6084 MachineFunction &MF = DAG.getMachineFunction(); 6085 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6086 6087 // Shuffle operations on MMX not supported. 6088 if (isMMX) 6089 return Op; 6090 6091 // Vector shuffle lowering takes 3 steps: 6092 // 6093 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6094 // narrowing and commutation of operands should be handled. 6095 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6096 // shuffle nodes. 6097 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6098 // so the shuffle can be broken into other shuffles and the legalizer can 6099 // try the lowering again. 6100 // 6101 // The general ideia is that no vector_shuffle operation should be left to 6102 // be matched during isel, all of them must be converted to a target specific 6103 // node here. 6104 6105 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6106 // narrowing and commutation of operands should be handled. The actual code 6107 // doesn't include all of those, work in progress... 6108 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6109 if (NewOp.getNode()) 6110 return NewOp; 6111 6112 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6113 // unpckh_undef). Only use pshufd if speed is more important than size. 6114 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6115 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6116 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6117 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6118 6119 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef && 6120 RelaxedMayFoldVectorLoad(V1)) 6121 return getMOVDDup(Op, dl, V1, DAG); 6122 6123 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6124 return getMOVHighToLow(Op, dl, DAG); 6125 6126 // Use to match splats 6127 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef && 6128 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6129 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6130 6131 if (X86::isPSHUFDMask(SVOp)) { 6132 // The actual implementation will match the mask in the if above and then 6133 // during isel it can match several different instructions, not only pshufd 6134 // as its name says, sad but true, emulate the behavior for now... 6135 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6136 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6137 6138 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6139 6140 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6141 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6142 6143 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6144 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, 6145 TargetMask, DAG); 6146 6147 if (VT == MVT::v4f32) 6148 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1, 6149 TargetMask, DAG); 6150 } 6151 6152 // Check if this can be converted into a logical shift. 6153 bool isLeft = false; 6154 unsigned ShAmt = 0; 6155 SDValue ShVal; 6156 bool isShift = getSubtarget()->hasSSE2() && 6157 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6158 if (isShift && ShVal.hasOneUse()) { 6159 // If the shifted value has multiple uses, it may be cheaper to use 6160 // v_set0 + movlhps or movhlps, etc. 6161 EVT EltVT = VT.getVectorElementType(); 6162 ShAmt *= EltVT.getSizeInBits(); 6163 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6164 } 6165 6166 if (X86::isMOVLMask(SVOp)) { 6167 if (V1IsUndef) 6168 return V2; 6169 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6170 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6171 if (!X86::isMOVLPMask(SVOp)) { 6172 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6173 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6174 6175 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6176 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6177 } 6178 } 6179 6180 // FIXME: fold these into legal mask. 6181 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 6182 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6183 6184 if (X86::isMOVHLPSMask(SVOp)) 6185 return getMOVHighToLow(Op, dl, DAG); 6186 6187 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6188 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6189 6190 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6191 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6192 6193 if (X86::isMOVLPMask(SVOp)) 6194 return getMOVLP(Op, dl, DAG, HasSSE2); 6195 6196 if (ShouldXformToMOVHLPS(SVOp) || 6197 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6198 return CommuteVectorShuffle(SVOp, DAG); 6199 6200 if (isShift) { 6201 // No better options. Use a vshl / vsrl. 6202 EVT EltVT = VT.getVectorElementType(); 6203 ShAmt *= EltVT.getSizeInBits(); 6204 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6205 } 6206 6207 bool Commuted = false; 6208 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6209 // 1,1,1,1 -> v8i16 though. 6210 V1IsSplat = isSplatVector(V1.getNode()); 6211 V2IsSplat = isSplatVector(V2.getNode()); 6212 6213 // Canonicalize the splat or undef, if present, to be on the RHS. 6214 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6215 Op = CommuteVectorShuffle(SVOp, DAG); 6216 SVOp = cast<ShuffleVectorSDNode>(Op); 6217 V1 = SVOp->getOperand(0); 6218 V2 = SVOp->getOperand(1); 6219 std::swap(V1IsSplat, V2IsSplat); 6220 std::swap(V1IsUndef, V2IsUndef); 6221 Commuted = true; 6222 } 6223 6224 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6225 // Shuffling low element of v1 into undef, just return v1. 6226 if (V2IsUndef) 6227 return V1; 6228 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6229 // the instruction selector will not match, so get a canonical MOVL with 6230 // swapped operands to undo the commute. 6231 return getMOVL(DAG, dl, VT, V2, V1); 6232 } 6233 6234 if (X86::isUNPCKLMask(SVOp)) 6235 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 6236 6237 if (X86::isUNPCKHMask(SVOp)) 6238 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 6239 6240 if (V2IsSplat) { 6241 // Normalize mask so all entries that point to V2 points to its first 6242 // element then try to match unpck{h|l} again. If match, return a 6243 // new vector_shuffle with the corrected mask. 6244 SDValue NewMask = NormalizeMask(SVOp, DAG); 6245 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6246 if (NSVOp != SVOp) { 6247 if (X86::isUNPCKLMask(NSVOp, true)) { 6248 return NewMask; 6249 } else if (X86::isUNPCKHMask(NSVOp, true)) { 6250 return NewMask; 6251 } 6252 } 6253 } 6254 6255 if (Commuted) { 6256 // Commute is back and try unpck* again. 6257 // FIXME: this seems wrong. 6258 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6259 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6260 6261 if (X86::isUNPCKLMask(NewSVOp)) 6262 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 6263 6264 if (X86::isUNPCKHMask(NewSVOp)) 6265 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 6266 } 6267 6268 // Normalize the node to match x86 shuffle ops if needed 6269 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6270 return CommuteVectorShuffle(SVOp, DAG); 6271 6272 // The checks below are all present in isShuffleMaskLegal, but they are 6273 // inlined here right now to enable us to directly emit target specific 6274 // nodes, and remove one by one until they don't return Op anymore. 6275 SmallVector<int, 16> M; 6276 SVOp->getMask(M); 6277 6278 if (isPALIGNRMask(M, VT, HasSSSE3)) 6279 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6280 X86::getShufflePALIGNRImmediate(SVOp), 6281 DAG); 6282 6283 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6284 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6285 if (VT == MVT::v2f64) 6286 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6287 if (VT == MVT::v2i64) 6288 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6289 } 6290 6291 if (isPSHUFHWMask(M, VT)) 6292 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6293 X86::getShufflePSHUFHWImmediate(SVOp), 6294 DAG); 6295 6296 if (isPSHUFLWMask(M, VT)) 6297 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6298 X86::getShufflePSHUFLWImmediate(SVOp), 6299 DAG); 6300 6301 if (isSHUFPMask(M, VT)) { 6302 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6303 if (VT == MVT::v4f32 || VT == MVT::v4i32) 6304 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2, 6305 TargetMask, DAG); 6306 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6307 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2, 6308 TargetMask, DAG); 6309 } 6310 6311 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6312 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6313 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6314 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6315 6316 //===--------------------------------------------------------------------===// 6317 // Generate target specific nodes for 128 or 256-bit shuffles only 6318 // supported in the AVX instruction set. 6319 // 6320 6321 // Handle VPERMILPS* permutations 6322 if (isVPERMILPSMask(M, VT, Subtarget)) 6323 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6324 getShuffleVPERMILPSImmediate(SVOp), DAG); 6325 6326 // Handle VPERMILPD* permutations 6327 if (isVPERMILPDMask(M, VT, Subtarget)) 6328 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6329 getShuffleVPERMILPDImmediate(SVOp), DAG); 6330 6331 //===--------------------------------------------------------------------===// 6332 // Since no target specific shuffle was selected for this generic one, 6333 // lower it into other known shuffles. FIXME: this isn't true yet, but 6334 // this is the plan. 6335 // 6336 6337 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6338 if (VT == MVT::v8i16) { 6339 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6340 if (NewOp.getNode()) 6341 return NewOp; 6342 } 6343 6344 if (VT == MVT::v16i8) { 6345 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6346 if (NewOp.getNode()) 6347 return NewOp; 6348 } 6349 6350 // Handle all 128-bit wide vectors with 4 elements, and match them with 6351 // several different shuffle types. 6352 if (NumElems == 4 && VT.getSizeInBits() == 128) 6353 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6354 6355 // Handle general 256-bit shuffles 6356 if (VT.is256BitVector()) 6357 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6358 6359 return SDValue(); 6360} 6361 6362SDValue 6363X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6364 SelectionDAG &DAG) const { 6365 EVT VT = Op.getValueType(); 6366 DebugLoc dl = Op.getDebugLoc(); 6367 6368 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6369 return SDValue(); 6370 6371 if (VT.getSizeInBits() == 8) { 6372 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6373 Op.getOperand(0), Op.getOperand(1)); 6374 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6375 DAG.getValueType(VT)); 6376 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6377 } else if (VT.getSizeInBits() == 16) { 6378 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6379 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6380 if (Idx == 0) 6381 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6382 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6383 DAG.getNode(ISD::BITCAST, dl, 6384 MVT::v4i32, 6385 Op.getOperand(0)), 6386 Op.getOperand(1))); 6387 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6388 Op.getOperand(0), Op.getOperand(1)); 6389 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6390 DAG.getValueType(VT)); 6391 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6392 } else if (VT == MVT::f32) { 6393 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6394 // the result back to FR32 register. It's only worth matching if the 6395 // result has a single use which is a store or a bitcast to i32. And in 6396 // the case of a store, it's not worth it if the index is a constant 0, 6397 // because a MOVSSmr can be used instead, which is smaller and faster. 6398 if (!Op.hasOneUse()) 6399 return SDValue(); 6400 SDNode *User = *Op.getNode()->use_begin(); 6401 if ((User->getOpcode() != ISD::STORE || 6402 (isa<ConstantSDNode>(Op.getOperand(1)) && 6403 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6404 (User->getOpcode() != ISD::BITCAST || 6405 User->getValueType(0) != MVT::i32)) 6406 return SDValue(); 6407 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6408 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6409 Op.getOperand(0)), 6410 Op.getOperand(1)); 6411 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6412 } else if (VT == MVT::i32) { 6413 // ExtractPS works with constant index. 6414 if (isa<ConstantSDNode>(Op.getOperand(1))) 6415 return Op; 6416 } 6417 return SDValue(); 6418} 6419 6420 6421SDValue 6422X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6423 SelectionDAG &DAG) const { 6424 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6425 return SDValue(); 6426 6427 SDValue Vec = Op.getOperand(0); 6428 EVT VecVT = Vec.getValueType(); 6429 6430 // If this is a 256-bit vector result, first extract the 128-bit vector and 6431 // then extract the element from the 128-bit vector. 6432 if (VecVT.getSizeInBits() == 256) { 6433 DebugLoc dl = Op.getNode()->getDebugLoc(); 6434 unsigned NumElems = VecVT.getVectorNumElements(); 6435 SDValue Idx = Op.getOperand(1); 6436 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6437 6438 // Get the 128-bit vector. 6439 bool Upper = IdxVal >= NumElems/2; 6440 Vec = Extract128BitVector(Vec, 6441 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6442 6443 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6444 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6445 } 6446 6447 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6448 6449 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 6450 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6451 if (Res.getNode()) 6452 return Res; 6453 } 6454 6455 EVT VT = Op.getValueType(); 6456 DebugLoc dl = Op.getDebugLoc(); 6457 // TODO: handle v16i8. 6458 if (VT.getSizeInBits() == 16) { 6459 SDValue Vec = Op.getOperand(0); 6460 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6461 if (Idx == 0) 6462 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6463 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6464 DAG.getNode(ISD::BITCAST, dl, 6465 MVT::v4i32, Vec), 6466 Op.getOperand(1))); 6467 // Transform it so it match pextrw which produces a 32-bit result. 6468 EVT EltVT = MVT::i32; 6469 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6470 Op.getOperand(0), Op.getOperand(1)); 6471 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6472 DAG.getValueType(VT)); 6473 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6474 } else if (VT.getSizeInBits() == 32) { 6475 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6476 if (Idx == 0) 6477 return Op; 6478 6479 // SHUFPS the element to the lowest double word, then movss. 6480 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6481 EVT VVT = Op.getOperand(0).getValueType(); 6482 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6483 DAG.getUNDEF(VVT), Mask); 6484 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6485 DAG.getIntPtrConstant(0)); 6486 } else if (VT.getSizeInBits() == 64) { 6487 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6488 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6489 // to match extract_elt for f64. 6490 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6491 if (Idx == 0) 6492 return Op; 6493 6494 // UNPCKHPD the element to the lowest double word, then movsd. 6495 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6496 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6497 int Mask[2] = { 1, -1 }; 6498 EVT VVT = Op.getOperand(0).getValueType(); 6499 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6500 DAG.getUNDEF(VVT), Mask); 6501 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6502 DAG.getIntPtrConstant(0)); 6503 } 6504 6505 return SDValue(); 6506} 6507 6508SDValue 6509X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6510 SelectionDAG &DAG) const { 6511 EVT VT = Op.getValueType(); 6512 EVT EltVT = VT.getVectorElementType(); 6513 DebugLoc dl = Op.getDebugLoc(); 6514 6515 SDValue N0 = Op.getOperand(0); 6516 SDValue N1 = Op.getOperand(1); 6517 SDValue N2 = Op.getOperand(2); 6518 6519 if (VT.getSizeInBits() == 256) 6520 return SDValue(); 6521 6522 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6523 isa<ConstantSDNode>(N2)) { 6524 unsigned Opc; 6525 if (VT == MVT::v8i16) 6526 Opc = X86ISD::PINSRW; 6527 else if (VT == MVT::v16i8) 6528 Opc = X86ISD::PINSRB; 6529 else 6530 Opc = X86ISD::PINSRB; 6531 6532 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6533 // argument. 6534 if (N1.getValueType() != MVT::i32) 6535 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6536 if (N2.getValueType() != MVT::i32) 6537 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6538 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6539 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6540 // Bits [7:6] of the constant are the source select. This will always be 6541 // zero here. The DAG Combiner may combine an extract_elt index into these 6542 // bits. For example (insert (extract, 3), 2) could be matched by putting 6543 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6544 // Bits [5:4] of the constant are the destination select. This is the 6545 // value of the incoming immediate. 6546 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6547 // combine either bitwise AND or insert of float 0.0 to set these bits. 6548 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6549 // Create this as a scalar to vector.. 6550 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6551 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6552 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 6553 // PINSR* works with constant index. 6554 return Op; 6555 } 6556 return SDValue(); 6557} 6558 6559SDValue 6560X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6561 EVT VT = Op.getValueType(); 6562 EVT EltVT = VT.getVectorElementType(); 6563 6564 DebugLoc dl = Op.getDebugLoc(); 6565 SDValue N0 = Op.getOperand(0); 6566 SDValue N1 = Op.getOperand(1); 6567 SDValue N2 = Op.getOperand(2); 6568 6569 // If this is a 256-bit vector result, first extract the 128-bit vector, 6570 // insert the element into the extracted half and then place it back. 6571 if (VT.getSizeInBits() == 256) { 6572 if (!isa<ConstantSDNode>(N2)) 6573 return SDValue(); 6574 6575 // Get the desired 128-bit vector half. 6576 unsigned NumElems = VT.getVectorNumElements(); 6577 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6578 bool Upper = IdxVal >= NumElems/2; 6579 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6580 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6581 6582 // Insert the element into the desired half. 6583 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6584 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6585 6586 // Insert the changed part back to the 256-bit vector 6587 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6588 } 6589 6590 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) 6591 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6592 6593 if (EltVT == MVT::i8) 6594 return SDValue(); 6595 6596 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6597 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6598 // as its second argument. 6599 if (N1.getValueType() != MVT::i32) 6600 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6601 if (N2.getValueType() != MVT::i32) 6602 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6603 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6604 } 6605 return SDValue(); 6606} 6607 6608SDValue 6609X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6610 LLVMContext *Context = DAG.getContext(); 6611 DebugLoc dl = Op.getDebugLoc(); 6612 EVT OpVT = Op.getValueType(); 6613 6614 // If this is a 256-bit vector result, first insert into a 128-bit 6615 // vector and then insert into the 256-bit vector. 6616 if (OpVT.getSizeInBits() > 128) { 6617 // Insert into a 128-bit vector. 6618 EVT VT128 = EVT::getVectorVT(*Context, 6619 OpVT.getVectorElementType(), 6620 OpVT.getVectorNumElements() / 2); 6621 6622 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6623 6624 // Insert the 128-bit vector. 6625 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 6626 DAG.getConstant(0, MVT::i32), 6627 DAG, dl); 6628 } 6629 6630 if (Op.getValueType() == MVT::v1i64 && 6631 Op.getOperand(0).getValueType() == MVT::i64) 6632 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6633 6634 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6635 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6636 "Expected an SSE type!"); 6637 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6638 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6639} 6640 6641// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6642// a simple subregister reference or explicit instructions to grab 6643// upper bits of a vector. 6644SDValue 6645X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6646 if (Subtarget->hasAVX()) { 6647 DebugLoc dl = Op.getNode()->getDebugLoc(); 6648 SDValue Vec = Op.getNode()->getOperand(0); 6649 SDValue Idx = Op.getNode()->getOperand(1); 6650 6651 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 6652 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 6653 return Extract128BitVector(Vec, Idx, DAG, dl); 6654 } 6655 } 6656 return SDValue(); 6657} 6658 6659// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6660// simple superregister reference or explicit instructions to insert 6661// the upper bits of a vector. 6662SDValue 6663X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6664 if (Subtarget->hasAVX()) { 6665 DebugLoc dl = Op.getNode()->getDebugLoc(); 6666 SDValue Vec = Op.getNode()->getOperand(0); 6667 SDValue SubVec = Op.getNode()->getOperand(1); 6668 SDValue Idx = Op.getNode()->getOperand(2); 6669 6670 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 6671 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 6672 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 6673 } 6674 } 6675 return SDValue(); 6676} 6677 6678// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 6679// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 6680// one of the above mentioned nodes. It has to be wrapped because otherwise 6681// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 6682// be used to form addressing mode. These wrapped nodes will be selected 6683// into MOV32ri. 6684SDValue 6685X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 6686 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 6687 6688 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6689 // global base reg. 6690 unsigned char OpFlag = 0; 6691 unsigned WrapperKind = X86ISD::Wrapper; 6692 CodeModel::Model M = getTargetMachine().getCodeModel(); 6693 6694 if (Subtarget->isPICStyleRIPRel() && 6695 (M == CodeModel::Small || M == CodeModel::Kernel)) 6696 WrapperKind = X86ISD::WrapperRIP; 6697 else if (Subtarget->isPICStyleGOT()) 6698 OpFlag = X86II::MO_GOTOFF; 6699 else if (Subtarget->isPICStyleStubPIC()) 6700 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6701 6702 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 6703 CP->getAlignment(), 6704 CP->getOffset(), OpFlag); 6705 DebugLoc DL = CP->getDebugLoc(); 6706 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6707 // With PIC, the address is actually $g + Offset. 6708 if (OpFlag) { 6709 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6710 DAG.getNode(X86ISD::GlobalBaseReg, 6711 DebugLoc(), getPointerTy()), 6712 Result); 6713 } 6714 6715 return Result; 6716} 6717 6718SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 6719 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 6720 6721 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6722 // global base reg. 6723 unsigned char OpFlag = 0; 6724 unsigned WrapperKind = X86ISD::Wrapper; 6725 CodeModel::Model M = getTargetMachine().getCodeModel(); 6726 6727 if (Subtarget->isPICStyleRIPRel() && 6728 (M == CodeModel::Small || M == CodeModel::Kernel)) 6729 WrapperKind = X86ISD::WrapperRIP; 6730 else if (Subtarget->isPICStyleGOT()) 6731 OpFlag = X86II::MO_GOTOFF; 6732 else if (Subtarget->isPICStyleStubPIC()) 6733 OpFlag = X86II::MO_PIC_BASE_OFFSET; 6734 6735 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 6736 OpFlag); 6737 DebugLoc DL = JT->getDebugLoc(); 6738 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6739 6740 // With PIC, the address is actually $g + Offset. 6741 if (OpFlag) 6742 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6743 DAG.getNode(X86ISD::GlobalBaseReg, 6744 DebugLoc(), getPointerTy()), 6745 Result); 6746 6747 return Result; 6748} 6749 6750SDValue 6751X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 6752 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 6753 6754 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 6755 // global base reg. 6756 unsigned char OpFlag = 0; 6757 unsigned WrapperKind = X86ISD::Wrapper; 6758 CodeModel::Model M = getTargetMachine().getCodeModel(); 6759 6760 if (Subtarget->isPICStyleRIPRel() && 6761 (M == CodeModel::Small || M == CodeModel::Kernel)) { 6762 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 6763 OpFlag = X86II::MO_GOTPCREL; 6764 WrapperKind = X86ISD::WrapperRIP; 6765 } else if (Subtarget->isPICStyleGOT()) { 6766 OpFlag = X86II::MO_GOT; 6767 } else if (Subtarget->isPICStyleStubPIC()) { 6768 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 6769 } else if (Subtarget->isPICStyleStubNoDynamic()) { 6770 OpFlag = X86II::MO_DARWIN_NONLAZY; 6771 } 6772 6773 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 6774 6775 DebugLoc DL = Op.getDebugLoc(); 6776 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 6777 6778 6779 // With PIC, the address is actually $g + Offset. 6780 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 6781 !Subtarget->is64Bit()) { 6782 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 6783 DAG.getNode(X86ISD::GlobalBaseReg, 6784 DebugLoc(), getPointerTy()), 6785 Result); 6786 } 6787 6788 // For symbols that require a load from a stub to get the address, emit the 6789 // load. 6790 if (isGlobalStubReference(OpFlag)) 6791 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 6792 MachinePointerInfo::getGOT(), false, false, 0); 6793 6794 return Result; 6795} 6796 6797SDValue 6798X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 6799 // Create the TargetBlockAddressAddress node. 6800 unsigned char OpFlags = 6801 Subtarget->ClassifyBlockAddressReference(); 6802 CodeModel::Model M = getTargetMachine().getCodeModel(); 6803 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 6804 DebugLoc dl = Op.getDebugLoc(); 6805 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 6806 /*isTarget=*/true, OpFlags); 6807 6808 if (Subtarget->isPICStyleRIPRel() && 6809 (M == CodeModel::Small || M == CodeModel::Kernel)) 6810 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6811 else 6812 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6813 6814 // With PIC, the address is actually $g + Offset. 6815 if (isGlobalRelativeToPICBase(OpFlags)) { 6816 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6817 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6818 Result); 6819 } 6820 6821 return Result; 6822} 6823 6824SDValue 6825X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 6826 int64_t Offset, 6827 SelectionDAG &DAG) const { 6828 // Create the TargetGlobalAddress node, folding in the constant 6829 // offset if it is legal. 6830 unsigned char OpFlags = 6831 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 6832 CodeModel::Model M = getTargetMachine().getCodeModel(); 6833 SDValue Result; 6834 if (OpFlags == X86II::MO_NO_FLAG && 6835 X86::isOffsetSuitableForCodeModel(Offset, M)) { 6836 // A direct static reference to a global. 6837 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 6838 Offset = 0; 6839 } else { 6840 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 6841 } 6842 6843 if (Subtarget->isPICStyleRIPRel() && 6844 (M == CodeModel::Small || M == CodeModel::Kernel)) 6845 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 6846 else 6847 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 6848 6849 // With PIC, the address is actually $g + Offset. 6850 if (isGlobalRelativeToPICBase(OpFlags)) { 6851 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6852 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 6853 Result); 6854 } 6855 6856 // For globals that require a load from a stub to get the address, emit the 6857 // load. 6858 if (isGlobalStubReference(OpFlags)) 6859 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 6860 MachinePointerInfo::getGOT(), false, false, 0); 6861 6862 // If there was a non-zero offset that we didn't fold, create an explicit 6863 // addition for it. 6864 if (Offset != 0) 6865 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 6866 DAG.getConstant(Offset, getPointerTy())); 6867 6868 return Result; 6869} 6870 6871SDValue 6872X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 6873 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 6874 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 6875 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 6876} 6877 6878static SDValue 6879GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 6880 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 6881 unsigned char OperandFlags) { 6882 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6883 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 6884 DebugLoc dl = GA->getDebugLoc(); 6885 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6886 GA->getValueType(0), 6887 GA->getOffset(), 6888 OperandFlags); 6889 if (InFlag) { 6890 SDValue Ops[] = { Chain, TGA, *InFlag }; 6891 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 6892 } else { 6893 SDValue Ops[] = { Chain, TGA }; 6894 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 6895 } 6896 6897 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 6898 MFI->setAdjustsStack(true); 6899 6900 SDValue Flag = Chain.getValue(1); 6901 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 6902} 6903 6904// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 6905static SDValue 6906LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6907 const EVT PtrVT) { 6908 SDValue InFlag; 6909 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 6910 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 6911 DAG.getNode(X86ISD::GlobalBaseReg, 6912 DebugLoc(), PtrVT), InFlag); 6913 InFlag = Chain.getValue(1); 6914 6915 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 6916} 6917 6918// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 6919static SDValue 6920LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6921 const EVT PtrVT) { 6922 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 6923 X86::RAX, X86II::MO_TLSGD); 6924} 6925 6926// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 6927// "local exec" model. 6928static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 6929 const EVT PtrVT, TLSModel::Model model, 6930 bool is64Bit) { 6931 DebugLoc dl = GA->getDebugLoc(); 6932 6933 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 6934 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 6935 is64Bit ? 257 : 256)); 6936 6937 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 6938 DAG.getIntPtrConstant(0), 6939 MachinePointerInfo(Ptr), false, false, 0); 6940 6941 unsigned char OperandFlags = 0; 6942 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 6943 // initialexec. 6944 unsigned WrapperKind = X86ISD::Wrapper; 6945 if (model == TLSModel::LocalExec) { 6946 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 6947 } else if (is64Bit) { 6948 assert(model == TLSModel::InitialExec); 6949 OperandFlags = X86II::MO_GOTTPOFF; 6950 WrapperKind = X86ISD::WrapperRIP; 6951 } else { 6952 assert(model == TLSModel::InitialExec); 6953 OperandFlags = X86II::MO_INDNTPOFF; 6954 } 6955 6956 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 6957 // exec) 6958 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 6959 GA->getValueType(0), 6960 GA->getOffset(), OperandFlags); 6961 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 6962 6963 if (model == TLSModel::InitialExec) 6964 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 6965 MachinePointerInfo::getGOT(), false, false, 0); 6966 6967 // The address of the thread local variable is the add of the thread 6968 // pointer with the offset of the variable. 6969 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 6970} 6971 6972SDValue 6973X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 6974 6975 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 6976 const GlobalValue *GV = GA->getGlobal(); 6977 6978 if (Subtarget->isTargetELF()) { 6979 // TODO: implement the "local dynamic" model 6980 // TODO: implement the "initial exec"model for pic executables 6981 6982 // If GV is an alias then use the aliasee for determining 6983 // thread-localness. 6984 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 6985 GV = GA->resolveAliasedGlobal(false); 6986 6987 TLSModel::Model model 6988 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 6989 6990 switch (model) { 6991 case TLSModel::GeneralDynamic: 6992 case TLSModel::LocalDynamic: // not implemented 6993 if (Subtarget->is64Bit()) 6994 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 6995 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 6996 6997 case TLSModel::InitialExec: 6998 case TLSModel::LocalExec: 6999 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7000 Subtarget->is64Bit()); 7001 } 7002 } else if (Subtarget->isTargetDarwin()) { 7003 // Darwin only has one model of TLS. Lower to that. 7004 unsigned char OpFlag = 0; 7005 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7006 X86ISD::WrapperRIP : X86ISD::Wrapper; 7007 7008 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7009 // global base reg. 7010 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7011 !Subtarget->is64Bit(); 7012 if (PIC32) 7013 OpFlag = X86II::MO_TLVP_PIC_BASE; 7014 else 7015 OpFlag = X86II::MO_TLVP; 7016 DebugLoc DL = Op.getDebugLoc(); 7017 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7018 GA->getValueType(0), 7019 GA->getOffset(), OpFlag); 7020 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7021 7022 // With PIC32, the address is actually $g + Offset. 7023 if (PIC32) 7024 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7025 DAG.getNode(X86ISD::GlobalBaseReg, 7026 DebugLoc(), getPointerTy()), 7027 Offset); 7028 7029 // Lowering the machine isd will make sure everything is in the right 7030 // location. 7031 SDValue Chain = DAG.getEntryNode(); 7032 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7033 SDValue Args[] = { Chain, Offset }; 7034 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7035 7036 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7037 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7038 MFI->setAdjustsStack(true); 7039 7040 // And our return value (tls address) is in the standard call return value 7041 // location. 7042 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7043 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 7044 } 7045 7046 assert(false && 7047 "TLS not implemented for this target."); 7048 7049 llvm_unreachable("Unreachable"); 7050 return SDValue(); 7051} 7052 7053 7054/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7055/// take a 2 x i32 value to shift plus a shift amount. 7056SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7057 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7058 EVT VT = Op.getValueType(); 7059 unsigned VTBits = VT.getSizeInBits(); 7060 DebugLoc dl = Op.getDebugLoc(); 7061 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7062 SDValue ShOpLo = Op.getOperand(0); 7063 SDValue ShOpHi = Op.getOperand(1); 7064 SDValue ShAmt = Op.getOperand(2); 7065 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7066 DAG.getConstant(VTBits - 1, MVT::i8)) 7067 : DAG.getConstant(0, VT); 7068 7069 SDValue Tmp2, Tmp3; 7070 if (Op.getOpcode() == ISD::SHL_PARTS) { 7071 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7072 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7073 } else { 7074 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7075 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7076 } 7077 7078 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7079 DAG.getConstant(VTBits, MVT::i8)); 7080 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7081 AndNode, DAG.getConstant(0, MVT::i8)); 7082 7083 SDValue Hi, Lo; 7084 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7085 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7086 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7087 7088 if (Op.getOpcode() == ISD::SHL_PARTS) { 7089 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7090 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7091 } else { 7092 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7093 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7094 } 7095 7096 SDValue Ops[2] = { Lo, Hi }; 7097 return DAG.getMergeValues(Ops, 2, dl); 7098} 7099 7100SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7101 SelectionDAG &DAG) const { 7102 EVT SrcVT = Op.getOperand(0).getValueType(); 7103 7104 if (SrcVT.isVector()) 7105 return SDValue(); 7106 7107 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7108 "Unknown SINT_TO_FP to lower!"); 7109 7110 // These are really Legal; return the operand so the caller accepts it as 7111 // Legal. 7112 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7113 return Op; 7114 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7115 Subtarget->is64Bit()) { 7116 return Op; 7117 } 7118 7119 DebugLoc dl = Op.getDebugLoc(); 7120 unsigned Size = SrcVT.getSizeInBits()/8; 7121 MachineFunction &MF = DAG.getMachineFunction(); 7122 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7123 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7124 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7125 StackSlot, 7126 MachinePointerInfo::getFixedStack(SSFI), 7127 false, false, 0); 7128 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7129} 7130 7131SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7132 SDValue StackSlot, 7133 SelectionDAG &DAG) const { 7134 // Build the FILD 7135 DebugLoc DL = Op.getDebugLoc(); 7136 SDVTList Tys; 7137 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7138 if (useSSE) 7139 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7140 else 7141 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7142 7143 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7144 7145 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7146 MachineMemOperand *MMO; 7147 if (FI) { 7148 int SSFI = FI->getIndex(); 7149 MMO = 7150 DAG.getMachineFunction() 7151 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7152 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7153 } else { 7154 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7155 StackSlot = StackSlot.getOperand(1); 7156 } 7157 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7158 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7159 X86ISD::FILD, DL, 7160 Tys, Ops, array_lengthof(Ops), 7161 SrcVT, MMO); 7162 7163 if (useSSE) { 7164 Chain = Result.getValue(1); 7165 SDValue InFlag = Result.getValue(2); 7166 7167 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7168 // shouldn't be necessary except that RFP cannot be live across 7169 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7170 MachineFunction &MF = DAG.getMachineFunction(); 7171 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7172 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7173 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7174 Tys = DAG.getVTList(MVT::Other); 7175 SDValue Ops[] = { 7176 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7177 }; 7178 MachineMemOperand *MMO = 7179 DAG.getMachineFunction() 7180 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7181 MachineMemOperand::MOStore, SSFISize, SSFISize); 7182 7183 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7184 Ops, array_lengthof(Ops), 7185 Op.getValueType(), MMO); 7186 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7187 MachinePointerInfo::getFixedStack(SSFI), 7188 false, false, 0); 7189 } 7190 7191 return Result; 7192} 7193 7194// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7195SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7196 SelectionDAG &DAG) const { 7197 // This algorithm is not obvious. Here it is in C code, more or less: 7198 /* 7199 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7200 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7201 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7202 7203 // Copy ints to xmm registers. 7204 __m128i xh = _mm_cvtsi32_si128( hi ); 7205 __m128i xl = _mm_cvtsi32_si128( lo ); 7206 7207 // Combine into low half of a single xmm register. 7208 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7209 __m128d d; 7210 double sd; 7211 7212 // Merge in appropriate exponents to give the integer bits the right 7213 // magnitude. 7214 x = _mm_unpacklo_epi32( x, exp ); 7215 7216 // Subtract away the biases to deal with the IEEE-754 double precision 7217 // implicit 1. 7218 d = _mm_sub_pd( (__m128d) x, bias ); 7219 7220 // All conversions up to here are exact. The correctly rounded result is 7221 // calculated using the current rounding mode using the following 7222 // horizontal add. 7223 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7224 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7225 // store doesn't really need to be here (except 7226 // maybe to zero the other double) 7227 return sd; 7228 } 7229 */ 7230 7231 DebugLoc dl = Op.getDebugLoc(); 7232 LLVMContext *Context = DAG.getContext(); 7233 7234 // Build some magic constants. 7235 std::vector<Constant*> CV0; 7236 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7237 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7238 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7239 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7240 Constant *C0 = ConstantVector::get(CV0); 7241 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7242 7243 std::vector<Constant*> CV1; 7244 CV1.push_back( 7245 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7246 CV1.push_back( 7247 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7248 Constant *C1 = ConstantVector::get(CV1); 7249 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7250 7251 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7252 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7253 Op.getOperand(0), 7254 DAG.getIntPtrConstant(1))); 7255 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7256 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7257 Op.getOperand(0), 7258 DAG.getIntPtrConstant(0))); 7259 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7260 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7261 MachinePointerInfo::getConstantPool(), 7262 false, false, 16); 7263 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7264 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7265 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7266 MachinePointerInfo::getConstantPool(), 7267 false, false, 16); 7268 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7269 7270 // Add the halves; easiest way is to swap them into another reg first. 7271 int ShufMask[2] = { 1, -1 }; 7272 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7273 DAG.getUNDEF(MVT::v2f64), ShufMask); 7274 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7275 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7276 DAG.getIntPtrConstant(0)); 7277} 7278 7279// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7280SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7281 SelectionDAG &DAG) const { 7282 DebugLoc dl = Op.getDebugLoc(); 7283 // FP constant to bias correct the final result. 7284 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7285 MVT::f64); 7286 7287 // Load the 32-bit value into an XMM register. 7288 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7289 Op.getOperand(0)); 7290 7291 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7292 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7293 DAG.getIntPtrConstant(0)); 7294 7295 // Or the load with the bias. 7296 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7297 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7298 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7299 MVT::v2f64, Load)), 7300 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7301 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7302 MVT::v2f64, Bias))); 7303 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7304 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7305 DAG.getIntPtrConstant(0)); 7306 7307 // Subtract the bias. 7308 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7309 7310 // Handle final rounding. 7311 EVT DestVT = Op.getValueType(); 7312 7313 if (DestVT.bitsLT(MVT::f64)) { 7314 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7315 DAG.getIntPtrConstant(0)); 7316 } else if (DestVT.bitsGT(MVT::f64)) { 7317 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7318 } 7319 7320 // Handle final rounding. 7321 return Sub; 7322} 7323 7324SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7325 SelectionDAG &DAG) const { 7326 SDValue N0 = Op.getOperand(0); 7327 DebugLoc dl = Op.getDebugLoc(); 7328 7329 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7330 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7331 // the optimization here. 7332 if (DAG.SignBitIsZero(N0)) 7333 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7334 7335 EVT SrcVT = N0.getValueType(); 7336 EVT DstVT = Op.getValueType(); 7337 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7338 return LowerUINT_TO_FP_i64(Op, DAG); 7339 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7340 return LowerUINT_TO_FP_i32(Op, DAG); 7341 7342 // Make a 64-bit buffer, and use it to build an FILD. 7343 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7344 if (SrcVT == MVT::i32) { 7345 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7346 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7347 getPointerTy(), StackSlot, WordOff); 7348 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7349 StackSlot, MachinePointerInfo(), 7350 false, false, 0); 7351 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7352 OffsetSlot, MachinePointerInfo(), 7353 false, false, 0); 7354 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7355 return Fild; 7356 } 7357 7358 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7359 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7360 StackSlot, MachinePointerInfo(), 7361 false, false, 0); 7362 // For i64 source, we need to add the appropriate power of 2 if the input 7363 // was negative. This is the same as the optimization in 7364 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7365 // we must be careful to do the computation in x87 extended precision, not 7366 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7367 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7368 MachineMemOperand *MMO = 7369 DAG.getMachineFunction() 7370 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7371 MachineMemOperand::MOLoad, 8, 8); 7372 7373 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7374 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7375 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7376 MVT::i64, MMO); 7377 7378 APInt FF(32, 0x5F800000ULL); 7379 7380 // Check whether the sign bit is set. 7381 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7382 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7383 ISD::SETLT); 7384 7385 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7386 SDValue FudgePtr = DAG.getConstantPool( 7387 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7388 getPointerTy()); 7389 7390 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7391 SDValue Zero = DAG.getIntPtrConstant(0); 7392 SDValue Four = DAG.getIntPtrConstant(4); 7393 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7394 Zero, Four); 7395 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7396 7397 // Load the value out, extending it from f32 to f80. 7398 // FIXME: Avoid the extend by constructing the right constant pool? 7399 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7400 FudgePtr, MachinePointerInfo::getConstantPool(), 7401 MVT::f32, false, false, 4); 7402 // Extend everything to 80 bits to force it to be done on x87. 7403 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7404 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7405} 7406 7407std::pair<SDValue,SDValue> X86TargetLowering:: 7408FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7409 DebugLoc DL = Op.getDebugLoc(); 7410 7411 EVT DstTy = Op.getValueType(); 7412 7413 if (!IsSigned) { 7414 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7415 DstTy = MVT::i64; 7416 } 7417 7418 assert(DstTy.getSimpleVT() <= MVT::i64 && 7419 DstTy.getSimpleVT() >= MVT::i16 && 7420 "Unknown FP_TO_SINT to lower!"); 7421 7422 // These are really Legal. 7423 if (DstTy == MVT::i32 && 7424 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7425 return std::make_pair(SDValue(), SDValue()); 7426 if (Subtarget->is64Bit() && 7427 DstTy == MVT::i64 && 7428 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7429 return std::make_pair(SDValue(), SDValue()); 7430 7431 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7432 // stack slot. 7433 MachineFunction &MF = DAG.getMachineFunction(); 7434 unsigned MemSize = DstTy.getSizeInBits()/8; 7435 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7436 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7437 7438 7439 7440 unsigned Opc; 7441 switch (DstTy.getSimpleVT().SimpleTy) { 7442 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7443 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7444 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7445 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7446 } 7447 7448 SDValue Chain = DAG.getEntryNode(); 7449 SDValue Value = Op.getOperand(0); 7450 EVT TheVT = Op.getOperand(0).getValueType(); 7451 if (isScalarFPTypeInSSEReg(TheVT)) { 7452 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7453 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7454 MachinePointerInfo::getFixedStack(SSFI), 7455 false, false, 0); 7456 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7457 SDValue Ops[] = { 7458 Chain, StackSlot, DAG.getValueType(TheVT) 7459 }; 7460 7461 MachineMemOperand *MMO = 7462 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7463 MachineMemOperand::MOLoad, MemSize, MemSize); 7464 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7465 DstTy, MMO); 7466 Chain = Value.getValue(1); 7467 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7468 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7469 } 7470 7471 MachineMemOperand *MMO = 7472 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7473 MachineMemOperand::MOStore, MemSize, MemSize); 7474 7475 // Build the FP_TO_INT*_IN_MEM 7476 SDValue Ops[] = { Chain, Value, StackSlot }; 7477 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7478 Ops, 3, DstTy, MMO); 7479 7480 return std::make_pair(FIST, StackSlot); 7481} 7482 7483SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7484 SelectionDAG &DAG) const { 7485 if (Op.getValueType().isVector()) 7486 return SDValue(); 7487 7488 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7489 SDValue FIST = Vals.first, StackSlot = Vals.second; 7490 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7491 if (FIST.getNode() == 0) return Op; 7492 7493 // Load the result. 7494 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7495 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7496} 7497 7498SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7499 SelectionDAG &DAG) const { 7500 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7501 SDValue FIST = Vals.first, StackSlot = Vals.second; 7502 assert(FIST.getNode() && "Unexpected failure"); 7503 7504 // Load the result. 7505 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7506 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7507} 7508 7509SDValue X86TargetLowering::LowerFABS(SDValue Op, 7510 SelectionDAG &DAG) const { 7511 LLVMContext *Context = DAG.getContext(); 7512 DebugLoc dl = Op.getDebugLoc(); 7513 EVT VT = Op.getValueType(); 7514 EVT EltVT = VT; 7515 if (VT.isVector()) 7516 EltVT = VT.getVectorElementType(); 7517 std::vector<Constant*> CV; 7518 if (EltVT == MVT::f64) { 7519 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7520 CV.push_back(C); 7521 CV.push_back(C); 7522 } else { 7523 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7524 CV.push_back(C); 7525 CV.push_back(C); 7526 CV.push_back(C); 7527 CV.push_back(C); 7528 } 7529 Constant *C = ConstantVector::get(CV); 7530 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7531 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7532 MachinePointerInfo::getConstantPool(), 7533 false, false, 16); 7534 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7535} 7536 7537SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7538 LLVMContext *Context = DAG.getContext(); 7539 DebugLoc dl = Op.getDebugLoc(); 7540 EVT VT = Op.getValueType(); 7541 EVT EltVT = VT; 7542 if (VT.isVector()) 7543 EltVT = VT.getVectorElementType(); 7544 std::vector<Constant*> CV; 7545 if (EltVT == MVT::f64) { 7546 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7547 CV.push_back(C); 7548 CV.push_back(C); 7549 } else { 7550 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7551 CV.push_back(C); 7552 CV.push_back(C); 7553 CV.push_back(C); 7554 CV.push_back(C); 7555 } 7556 Constant *C = ConstantVector::get(CV); 7557 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7558 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7559 MachinePointerInfo::getConstantPool(), 7560 false, false, 16); 7561 if (VT.isVector()) { 7562 return DAG.getNode(ISD::BITCAST, dl, VT, 7563 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 7564 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7565 Op.getOperand(0)), 7566 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 7567 } else { 7568 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7569 } 7570} 7571 7572SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7573 LLVMContext *Context = DAG.getContext(); 7574 SDValue Op0 = Op.getOperand(0); 7575 SDValue Op1 = Op.getOperand(1); 7576 DebugLoc dl = Op.getDebugLoc(); 7577 EVT VT = Op.getValueType(); 7578 EVT SrcVT = Op1.getValueType(); 7579 7580 // If second operand is smaller, extend it first. 7581 if (SrcVT.bitsLT(VT)) { 7582 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7583 SrcVT = VT; 7584 } 7585 // And if it is bigger, shrink it first. 7586 if (SrcVT.bitsGT(VT)) { 7587 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7588 SrcVT = VT; 7589 } 7590 7591 // At this point the operands and the result should have the same 7592 // type, and that won't be f80 since that is not custom lowered. 7593 7594 // First get the sign bit of second operand. 7595 std::vector<Constant*> CV; 7596 if (SrcVT == MVT::f64) { 7597 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7598 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7599 } else { 7600 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7601 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7602 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7603 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7604 } 7605 Constant *C = ConstantVector::get(CV); 7606 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7607 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7608 MachinePointerInfo::getConstantPool(), 7609 false, false, 16); 7610 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7611 7612 // Shift sign bit right or left if the two operands have different types. 7613 if (SrcVT.bitsGT(VT)) { 7614 // Op0 is MVT::f32, Op1 is MVT::f64. 7615 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7616 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7617 DAG.getConstant(32, MVT::i32)); 7618 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7619 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7620 DAG.getIntPtrConstant(0)); 7621 } 7622 7623 // Clear first operand sign bit. 7624 CV.clear(); 7625 if (VT == MVT::f64) { 7626 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7627 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7628 } else { 7629 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7630 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7631 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7632 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7633 } 7634 C = ConstantVector::get(CV); 7635 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7636 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7637 MachinePointerInfo::getConstantPool(), 7638 false, false, 16); 7639 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 7640 7641 // Or the value with the sign bit. 7642 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 7643} 7644 7645SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 7646 SDValue N0 = Op.getOperand(0); 7647 DebugLoc dl = Op.getDebugLoc(); 7648 EVT VT = Op.getValueType(); 7649 7650 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 7651 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 7652 DAG.getConstant(1, VT)); 7653 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 7654} 7655 7656/// Emit nodes that will be selected as "test Op0,Op0", or something 7657/// equivalent. 7658SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 7659 SelectionDAG &DAG) const { 7660 DebugLoc dl = Op.getDebugLoc(); 7661 7662 // CF and OF aren't always set the way we want. Determine which 7663 // of these we need. 7664 bool NeedCF = false; 7665 bool NeedOF = false; 7666 switch (X86CC) { 7667 default: break; 7668 case X86::COND_A: case X86::COND_AE: 7669 case X86::COND_B: case X86::COND_BE: 7670 NeedCF = true; 7671 break; 7672 case X86::COND_G: case X86::COND_GE: 7673 case X86::COND_L: case X86::COND_LE: 7674 case X86::COND_O: case X86::COND_NO: 7675 NeedOF = true; 7676 break; 7677 } 7678 7679 // See if we can use the EFLAGS value from the operand instead of 7680 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 7681 // we prove that the arithmetic won't overflow, we can't use OF or CF. 7682 if (Op.getResNo() != 0 || NeedOF || NeedCF) 7683 // Emit a CMP with 0, which is the TEST pattern. 7684 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7685 DAG.getConstant(0, Op.getValueType())); 7686 7687 unsigned Opcode = 0; 7688 unsigned NumOperands = 0; 7689 switch (Op.getNode()->getOpcode()) { 7690 case ISD::ADD: 7691 // Due to an isel shortcoming, be conservative if this add is likely to be 7692 // selected as part of a load-modify-store instruction. When the root node 7693 // in a match is a store, isel doesn't know how to remap non-chain non-flag 7694 // uses of other nodes in the match, such as the ADD in this case. This 7695 // leads to the ADD being left around and reselected, with the result being 7696 // two adds in the output. Alas, even if none our users are stores, that 7697 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 7698 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 7699 // climbing the DAG back to the root, and it doesn't seem to be worth the 7700 // effort. 7701 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7702 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7703 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 7704 goto default_case; 7705 7706 if (ConstantSDNode *C = 7707 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 7708 // An add of one will be selected as an INC. 7709 if (C->getAPIntValue() == 1) { 7710 Opcode = X86ISD::INC; 7711 NumOperands = 1; 7712 break; 7713 } 7714 7715 // An add of negative one (subtract of one) will be selected as a DEC. 7716 if (C->getAPIntValue().isAllOnesValue()) { 7717 Opcode = X86ISD::DEC; 7718 NumOperands = 1; 7719 break; 7720 } 7721 } 7722 7723 // Otherwise use a regular EFLAGS-setting add. 7724 Opcode = X86ISD::ADD; 7725 NumOperands = 2; 7726 break; 7727 case ISD::AND: { 7728 // If the primary and result isn't used, don't bother using X86ISD::AND, 7729 // because a TEST instruction will be better. 7730 bool NonFlagUse = false; 7731 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7732 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 7733 SDNode *User = *UI; 7734 unsigned UOpNo = UI.getOperandNo(); 7735 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 7736 // Look pass truncate. 7737 UOpNo = User->use_begin().getOperandNo(); 7738 User = *User->use_begin(); 7739 } 7740 7741 if (User->getOpcode() != ISD::BRCOND && 7742 User->getOpcode() != ISD::SETCC && 7743 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 7744 NonFlagUse = true; 7745 break; 7746 } 7747 } 7748 7749 if (!NonFlagUse) 7750 break; 7751 } 7752 // FALL THROUGH 7753 case ISD::SUB: 7754 case ISD::OR: 7755 case ISD::XOR: 7756 // Due to the ISEL shortcoming noted above, be conservative if this op is 7757 // likely to be selected as part of a load-modify-store instruction. 7758 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 7759 UE = Op.getNode()->use_end(); UI != UE; ++UI) 7760 if (UI->getOpcode() == ISD::STORE) 7761 goto default_case; 7762 7763 // Otherwise use a regular EFLAGS-setting instruction. 7764 switch (Op.getNode()->getOpcode()) { 7765 default: llvm_unreachable("unexpected operator!"); 7766 case ISD::SUB: Opcode = X86ISD::SUB; break; 7767 case ISD::OR: Opcode = X86ISD::OR; break; 7768 case ISD::XOR: Opcode = X86ISD::XOR; break; 7769 case ISD::AND: Opcode = X86ISD::AND; break; 7770 } 7771 7772 NumOperands = 2; 7773 break; 7774 case X86ISD::ADD: 7775 case X86ISD::SUB: 7776 case X86ISD::INC: 7777 case X86ISD::DEC: 7778 case X86ISD::OR: 7779 case X86ISD::XOR: 7780 case X86ISD::AND: 7781 return SDValue(Op.getNode(), 1); 7782 default: 7783 default_case: 7784 break; 7785 } 7786 7787 if (Opcode == 0) 7788 // Emit a CMP with 0, which is the TEST pattern. 7789 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 7790 DAG.getConstant(0, Op.getValueType())); 7791 7792 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 7793 SmallVector<SDValue, 4> Ops; 7794 for (unsigned i = 0; i != NumOperands; ++i) 7795 Ops.push_back(Op.getOperand(i)); 7796 7797 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 7798 DAG.ReplaceAllUsesWith(Op, New); 7799 return SDValue(New.getNode(), 1); 7800} 7801 7802/// Emit nodes that will be selected as "cmp Op0,Op1", or something 7803/// equivalent. 7804SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 7805 SelectionDAG &DAG) const { 7806 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 7807 if (C->getAPIntValue() == 0) 7808 return EmitTest(Op0, X86CC, DAG); 7809 7810 DebugLoc dl = Op0.getDebugLoc(); 7811 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 7812} 7813 7814/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 7815/// if it's possible. 7816SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 7817 DebugLoc dl, SelectionDAG &DAG) const { 7818 SDValue Op0 = And.getOperand(0); 7819 SDValue Op1 = And.getOperand(1); 7820 if (Op0.getOpcode() == ISD::TRUNCATE) 7821 Op0 = Op0.getOperand(0); 7822 if (Op1.getOpcode() == ISD::TRUNCATE) 7823 Op1 = Op1.getOperand(0); 7824 7825 SDValue LHS, RHS; 7826 if (Op1.getOpcode() == ISD::SHL) 7827 std::swap(Op0, Op1); 7828 if (Op0.getOpcode() == ISD::SHL) { 7829 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 7830 if (And00C->getZExtValue() == 1) { 7831 // If we looked past a truncate, check that it's only truncating away 7832 // known zeros. 7833 unsigned BitWidth = Op0.getValueSizeInBits(); 7834 unsigned AndBitWidth = And.getValueSizeInBits(); 7835 if (BitWidth > AndBitWidth) { 7836 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 7837 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 7838 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 7839 return SDValue(); 7840 } 7841 LHS = Op1; 7842 RHS = Op0.getOperand(1); 7843 } 7844 } else if (Op1.getOpcode() == ISD::Constant) { 7845 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 7846 SDValue AndLHS = Op0; 7847 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 7848 LHS = AndLHS.getOperand(0); 7849 RHS = AndLHS.getOperand(1); 7850 } 7851 } 7852 7853 if (LHS.getNode()) { 7854 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 7855 // instruction. Since the shift amount is in-range-or-undefined, we know 7856 // that doing a bittest on the i32 value is ok. We extend to i32 because 7857 // the encoding for the i16 version is larger than the i32 version. 7858 // Also promote i16 to i32 for performance / code size reason. 7859 if (LHS.getValueType() == MVT::i8 || 7860 LHS.getValueType() == MVT::i16) 7861 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 7862 7863 // If the operand types disagree, extend the shift amount to match. Since 7864 // BT ignores high bits (like shifts) we can use anyextend. 7865 if (LHS.getValueType() != RHS.getValueType()) 7866 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 7867 7868 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 7869 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 7870 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7871 DAG.getConstant(Cond, MVT::i8), BT); 7872 } 7873 7874 return SDValue(); 7875} 7876 7877SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 7878 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 7879 SDValue Op0 = Op.getOperand(0); 7880 SDValue Op1 = Op.getOperand(1); 7881 DebugLoc dl = Op.getDebugLoc(); 7882 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 7883 7884 // Optimize to BT if possible. 7885 // Lower (X & (1 << N)) == 0 to BT(X, N). 7886 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 7887 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 7888 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 7889 Op1.getOpcode() == ISD::Constant && 7890 cast<ConstantSDNode>(Op1)->isNullValue() && 7891 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7892 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 7893 if (NewSetCC.getNode()) 7894 return NewSetCC; 7895 } 7896 7897 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 7898 // these. 7899 if (Op1.getOpcode() == ISD::Constant && 7900 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 7901 cast<ConstantSDNode>(Op1)->isNullValue()) && 7902 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 7903 7904 // If the input is a setcc, then reuse the input setcc or use a new one with 7905 // the inverted condition. 7906 if (Op0.getOpcode() == X86ISD::SETCC) { 7907 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 7908 bool Invert = (CC == ISD::SETNE) ^ 7909 cast<ConstantSDNode>(Op1)->isNullValue(); 7910 if (!Invert) return Op0; 7911 7912 CCode = X86::GetOppositeBranchCondition(CCode); 7913 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7914 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 7915 } 7916 } 7917 7918 bool isFP = Op1.getValueType().isFloatingPoint(); 7919 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 7920 if (X86CC == X86::COND_INVALID) 7921 return SDValue(); 7922 7923 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 7924 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 7925 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 7926} 7927 7928SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 7929 SDValue Cond; 7930 SDValue Op0 = Op.getOperand(0); 7931 SDValue Op1 = Op.getOperand(1); 7932 SDValue CC = Op.getOperand(2); 7933 EVT VT = Op.getValueType(); 7934 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 7935 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 7936 DebugLoc dl = Op.getDebugLoc(); 7937 7938 if (isFP) { 7939 unsigned SSECC = 8; 7940 EVT EltVT = Op0.getValueType().getVectorElementType(); 7941 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 7942 7943 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 7944 bool Swap = false; 7945 7946 switch (SetCCOpcode) { 7947 default: break; 7948 case ISD::SETOEQ: 7949 case ISD::SETEQ: SSECC = 0; break; 7950 case ISD::SETOGT: 7951 case ISD::SETGT: Swap = true; // Fallthrough 7952 case ISD::SETLT: 7953 case ISD::SETOLT: SSECC = 1; break; 7954 case ISD::SETOGE: 7955 case ISD::SETGE: Swap = true; // Fallthrough 7956 case ISD::SETLE: 7957 case ISD::SETOLE: SSECC = 2; break; 7958 case ISD::SETUO: SSECC = 3; break; 7959 case ISD::SETUNE: 7960 case ISD::SETNE: SSECC = 4; break; 7961 case ISD::SETULE: Swap = true; 7962 case ISD::SETUGE: SSECC = 5; break; 7963 case ISD::SETULT: Swap = true; 7964 case ISD::SETUGT: SSECC = 6; break; 7965 case ISD::SETO: SSECC = 7; break; 7966 } 7967 if (Swap) 7968 std::swap(Op0, Op1); 7969 7970 // In the two special cases we can't handle, emit two comparisons. 7971 if (SSECC == 8) { 7972 if (SetCCOpcode == ISD::SETUEQ) { 7973 SDValue UNORD, EQ; 7974 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 7975 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 7976 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 7977 } 7978 else if (SetCCOpcode == ISD::SETONE) { 7979 SDValue ORD, NEQ; 7980 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 7981 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 7982 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 7983 } 7984 llvm_unreachable("Illegal FP comparison"); 7985 } 7986 // Handle all other FP comparisons here. 7987 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 7988 } 7989 7990 if (!isFP && VT.getSizeInBits() == 256) 7991 return SDValue(); 7992 7993 // We are handling one of the integer comparisons here. Since SSE only has 7994 // GT and EQ comparisons for integer, swapping operands and multiple 7995 // operations may be required for some comparisons. 7996 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 7997 bool Swap = false, Invert = false, FlipSigns = false; 7998 7999 switch (VT.getSimpleVT().SimpleTy) { 8000 default: break; 8001 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8002 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8003 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8004 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8005 } 8006 8007 switch (SetCCOpcode) { 8008 default: break; 8009 case ISD::SETNE: Invert = true; 8010 case ISD::SETEQ: Opc = EQOpc; break; 8011 case ISD::SETLT: Swap = true; 8012 case ISD::SETGT: Opc = GTOpc; break; 8013 case ISD::SETGE: Swap = true; 8014 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8015 case ISD::SETULT: Swap = true; 8016 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8017 case ISD::SETUGE: Swap = true; 8018 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8019 } 8020 if (Swap) 8021 std::swap(Op0, Op1); 8022 8023 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8024 // bits of the inputs before performing those operations. 8025 if (FlipSigns) { 8026 EVT EltVT = VT.getVectorElementType(); 8027 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8028 EltVT); 8029 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8030 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8031 SignBits.size()); 8032 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8033 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8034 } 8035 8036 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8037 8038 // If the logical-not of the result is required, perform that now. 8039 if (Invert) 8040 Result = DAG.getNOT(dl, Result, VT); 8041 8042 return Result; 8043} 8044 8045// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8046static bool isX86LogicalCmp(SDValue Op) { 8047 unsigned Opc = Op.getNode()->getOpcode(); 8048 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8049 return true; 8050 if (Op.getResNo() == 1 && 8051 (Opc == X86ISD::ADD || 8052 Opc == X86ISD::SUB || 8053 Opc == X86ISD::ADC || 8054 Opc == X86ISD::SBB || 8055 Opc == X86ISD::SMUL || 8056 Opc == X86ISD::UMUL || 8057 Opc == X86ISD::INC || 8058 Opc == X86ISD::DEC || 8059 Opc == X86ISD::OR || 8060 Opc == X86ISD::XOR || 8061 Opc == X86ISD::AND)) 8062 return true; 8063 8064 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8065 return true; 8066 8067 return false; 8068} 8069 8070static bool isZero(SDValue V) { 8071 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8072 return C && C->isNullValue(); 8073} 8074 8075static bool isAllOnes(SDValue V) { 8076 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8077 return C && C->isAllOnesValue(); 8078} 8079 8080SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8081 bool addTest = true; 8082 SDValue Cond = Op.getOperand(0); 8083 SDValue Op1 = Op.getOperand(1); 8084 SDValue Op2 = Op.getOperand(2); 8085 DebugLoc DL = Op.getDebugLoc(); 8086 SDValue CC; 8087 8088 if (Cond.getOpcode() == ISD::SETCC) { 8089 SDValue NewCond = LowerSETCC(Cond, DAG); 8090 if (NewCond.getNode()) 8091 Cond = NewCond; 8092 } 8093 8094 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8095 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8096 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8097 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8098 if (Cond.getOpcode() == X86ISD::SETCC && 8099 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8100 isZero(Cond.getOperand(1).getOperand(1))) { 8101 SDValue Cmp = Cond.getOperand(1); 8102 8103 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8104 8105 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8106 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8107 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8108 8109 SDValue CmpOp0 = Cmp.getOperand(0); 8110 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8111 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8112 8113 SDValue Res = // Res = 0 or -1. 8114 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8115 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8116 8117 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8118 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8119 8120 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8121 if (N2C == 0 || !N2C->isNullValue()) 8122 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8123 return Res; 8124 } 8125 } 8126 8127 // Look past (and (setcc_carry (cmp ...)), 1). 8128 if (Cond.getOpcode() == ISD::AND && 8129 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8130 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8131 if (C && C->getAPIntValue() == 1) 8132 Cond = Cond.getOperand(0); 8133 } 8134 8135 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8136 // setting operand in place of the X86ISD::SETCC. 8137 if (Cond.getOpcode() == X86ISD::SETCC || 8138 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8139 CC = Cond.getOperand(0); 8140 8141 SDValue Cmp = Cond.getOperand(1); 8142 unsigned Opc = Cmp.getOpcode(); 8143 EVT VT = Op.getValueType(); 8144 8145 bool IllegalFPCMov = false; 8146 if (VT.isFloatingPoint() && !VT.isVector() && 8147 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8148 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8149 8150 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8151 Opc == X86ISD::BT) { // FIXME 8152 Cond = Cmp; 8153 addTest = false; 8154 } 8155 } 8156 8157 if (addTest) { 8158 // Look pass the truncate. 8159 if (Cond.getOpcode() == ISD::TRUNCATE) 8160 Cond = Cond.getOperand(0); 8161 8162 // We know the result of AND is compared against zero. Try to match 8163 // it to BT. 8164 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8165 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8166 if (NewSetCC.getNode()) { 8167 CC = NewSetCC.getOperand(0); 8168 Cond = NewSetCC.getOperand(1); 8169 addTest = false; 8170 } 8171 } 8172 } 8173 8174 if (addTest) { 8175 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8176 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8177 } 8178 8179 // a < b ? -1 : 0 -> RES = ~setcc_carry 8180 // a < b ? 0 : -1 -> RES = setcc_carry 8181 // a >= b ? -1 : 0 -> RES = setcc_carry 8182 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8183 if (Cond.getOpcode() == X86ISD::CMP) { 8184 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8185 8186 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8187 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8188 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8189 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8190 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8191 return DAG.getNOT(DL, Res, Res.getValueType()); 8192 return Res; 8193 } 8194 } 8195 8196 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8197 // condition is true. 8198 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8199 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8200 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8201} 8202 8203// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8204// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8205// from the AND / OR. 8206static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8207 Opc = Op.getOpcode(); 8208 if (Opc != ISD::OR && Opc != ISD::AND) 8209 return false; 8210 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8211 Op.getOperand(0).hasOneUse() && 8212 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8213 Op.getOperand(1).hasOneUse()); 8214} 8215 8216// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8217// 1 and that the SETCC node has a single use. 8218static bool isXor1OfSetCC(SDValue Op) { 8219 if (Op.getOpcode() != ISD::XOR) 8220 return false; 8221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8222 if (N1C && N1C->getAPIntValue() == 1) { 8223 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8224 Op.getOperand(0).hasOneUse(); 8225 } 8226 return false; 8227} 8228 8229SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8230 bool addTest = true; 8231 SDValue Chain = Op.getOperand(0); 8232 SDValue Cond = Op.getOperand(1); 8233 SDValue Dest = Op.getOperand(2); 8234 DebugLoc dl = Op.getDebugLoc(); 8235 SDValue CC; 8236 8237 if (Cond.getOpcode() == ISD::SETCC) { 8238 SDValue NewCond = LowerSETCC(Cond, DAG); 8239 if (NewCond.getNode()) 8240 Cond = NewCond; 8241 } 8242#if 0 8243 // FIXME: LowerXALUO doesn't handle these!! 8244 else if (Cond.getOpcode() == X86ISD::ADD || 8245 Cond.getOpcode() == X86ISD::SUB || 8246 Cond.getOpcode() == X86ISD::SMUL || 8247 Cond.getOpcode() == X86ISD::UMUL) 8248 Cond = LowerXALUO(Cond, DAG); 8249#endif 8250 8251 // Look pass (and (setcc_carry (cmp ...)), 1). 8252 if (Cond.getOpcode() == ISD::AND && 8253 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8254 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8255 if (C && C->getAPIntValue() == 1) 8256 Cond = Cond.getOperand(0); 8257 } 8258 8259 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8260 // setting operand in place of the X86ISD::SETCC. 8261 if (Cond.getOpcode() == X86ISD::SETCC || 8262 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8263 CC = Cond.getOperand(0); 8264 8265 SDValue Cmp = Cond.getOperand(1); 8266 unsigned Opc = Cmp.getOpcode(); 8267 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8268 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8269 Cond = Cmp; 8270 addTest = false; 8271 } else { 8272 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8273 default: break; 8274 case X86::COND_O: 8275 case X86::COND_B: 8276 // These can only come from an arithmetic instruction with overflow, 8277 // e.g. SADDO, UADDO. 8278 Cond = Cond.getNode()->getOperand(1); 8279 addTest = false; 8280 break; 8281 } 8282 } 8283 } else { 8284 unsigned CondOpc; 8285 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8286 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8287 if (CondOpc == ISD::OR) { 8288 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8289 // two branches instead of an explicit OR instruction with a 8290 // separate test. 8291 if (Cmp == Cond.getOperand(1).getOperand(1) && 8292 isX86LogicalCmp(Cmp)) { 8293 CC = Cond.getOperand(0).getOperand(0); 8294 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8295 Chain, Dest, CC, Cmp); 8296 CC = Cond.getOperand(1).getOperand(0); 8297 Cond = Cmp; 8298 addTest = false; 8299 } 8300 } else { // ISD::AND 8301 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8302 // two branches instead of an explicit AND instruction with a 8303 // separate test. However, we only do this if this block doesn't 8304 // have a fall-through edge, because this requires an explicit 8305 // jmp when the condition is false. 8306 if (Cmp == Cond.getOperand(1).getOperand(1) && 8307 isX86LogicalCmp(Cmp) && 8308 Op.getNode()->hasOneUse()) { 8309 X86::CondCode CCode = 8310 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8311 CCode = X86::GetOppositeBranchCondition(CCode); 8312 CC = DAG.getConstant(CCode, MVT::i8); 8313 SDNode *User = *Op.getNode()->use_begin(); 8314 // Look for an unconditional branch following this conditional branch. 8315 // We need this because we need to reverse the successors in order 8316 // to implement FCMP_OEQ. 8317 if (User->getOpcode() == ISD::BR) { 8318 SDValue FalseBB = User->getOperand(1); 8319 SDNode *NewBR = 8320 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8321 assert(NewBR == User); 8322 (void)NewBR; 8323 Dest = FalseBB; 8324 8325 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8326 Chain, Dest, CC, Cmp); 8327 X86::CondCode CCode = 8328 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8329 CCode = X86::GetOppositeBranchCondition(CCode); 8330 CC = DAG.getConstant(CCode, MVT::i8); 8331 Cond = Cmp; 8332 addTest = false; 8333 } 8334 } 8335 } 8336 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8337 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8338 // It should be transformed during dag combiner except when the condition 8339 // is set by a arithmetics with overflow node. 8340 X86::CondCode CCode = 8341 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8342 CCode = X86::GetOppositeBranchCondition(CCode); 8343 CC = DAG.getConstant(CCode, MVT::i8); 8344 Cond = Cond.getOperand(0).getOperand(1); 8345 addTest = false; 8346 } 8347 } 8348 8349 if (addTest) { 8350 // Look pass the truncate. 8351 if (Cond.getOpcode() == ISD::TRUNCATE) 8352 Cond = Cond.getOperand(0); 8353 8354 // We know the result of AND is compared against zero. Try to match 8355 // it to BT. 8356 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8357 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8358 if (NewSetCC.getNode()) { 8359 CC = NewSetCC.getOperand(0); 8360 Cond = NewSetCC.getOperand(1); 8361 addTest = false; 8362 } 8363 } 8364 } 8365 8366 if (addTest) { 8367 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8368 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8369 } 8370 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8371 Chain, Dest, CC, Cond); 8372} 8373 8374 8375// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8376// Calls to _alloca is needed to probe the stack when allocating more than 4k 8377// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8378// that the guard pages used by the OS virtual memory manager are allocated in 8379// correct sequence. 8380SDValue 8381X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8382 SelectionDAG &DAG) const { 8383 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) && 8384 "This should be used only on Windows targets"); 8385 assert(!Subtarget->isTargetEnvMacho()); 8386 DebugLoc dl = Op.getDebugLoc(); 8387 8388 // Get the inputs. 8389 SDValue Chain = Op.getOperand(0); 8390 SDValue Size = Op.getOperand(1); 8391 // FIXME: Ensure alignment here 8392 8393 SDValue Flag; 8394 8395 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 8396 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8397 8398 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8399 Flag = Chain.getValue(1); 8400 8401 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8402 8403 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8404 Flag = Chain.getValue(1); 8405 8406 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8407 8408 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8409 return DAG.getMergeValues(Ops1, 2, dl); 8410} 8411 8412SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8413 MachineFunction &MF = DAG.getMachineFunction(); 8414 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8415 8416 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8417 DebugLoc DL = Op.getDebugLoc(); 8418 8419 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8420 // vastart just stores the address of the VarArgsFrameIndex slot into the 8421 // memory location argument. 8422 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8423 getPointerTy()); 8424 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8425 MachinePointerInfo(SV), false, false, 0); 8426 } 8427 8428 // __va_list_tag: 8429 // gp_offset (0 - 6 * 8) 8430 // fp_offset (48 - 48 + 8 * 16) 8431 // overflow_arg_area (point to parameters coming in memory). 8432 // reg_save_area 8433 SmallVector<SDValue, 8> MemOps; 8434 SDValue FIN = Op.getOperand(1); 8435 // Store gp_offset 8436 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 8437 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 8438 MVT::i32), 8439 FIN, MachinePointerInfo(SV), false, false, 0); 8440 MemOps.push_back(Store); 8441 8442 // Store fp_offset 8443 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8444 FIN, DAG.getIntPtrConstant(4)); 8445 Store = DAG.getStore(Op.getOperand(0), DL, 8446 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 8447 MVT::i32), 8448 FIN, MachinePointerInfo(SV, 4), false, false, 0); 8449 MemOps.push_back(Store); 8450 8451 // Store ptr to overflow_arg_area 8452 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8453 FIN, DAG.getIntPtrConstant(4)); 8454 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8455 getPointerTy()); 8456 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 8457 MachinePointerInfo(SV, 8), 8458 false, false, 0); 8459 MemOps.push_back(Store); 8460 8461 // Store ptr to reg_save_area. 8462 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 8463 FIN, DAG.getIntPtrConstant(8)); 8464 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 8465 getPointerTy()); 8466 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 8467 MachinePointerInfo(SV, 16), false, false, 0); 8468 MemOps.push_back(Store); 8469 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 8470 &MemOps[0], MemOps.size()); 8471} 8472 8473SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 8474 assert(Subtarget->is64Bit() && 8475 "LowerVAARG only handles 64-bit va_arg!"); 8476 assert((Subtarget->isTargetLinux() || 8477 Subtarget->isTargetDarwin()) && 8478 "Unhandled target in LowerVAARG"); 8479 assert(Op.getNode()->getNumOperands() == 4); 8480 SDValue Chain = Op.getOperand(0); 8481 SDValue SrcPtr = Op.getOperand(1); 8482 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8483 unsigned Align = Op.getConstantOperandVal(3); 8484 DebugLoc dl = Op.getDebugLoc(); 8485 8486 EVT ArgVT = Op.getNode()->getValueType(0); 8487 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 8488 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 8489 uint8_t ArgMode; 8490 8491 // Decide which area this value should be read from. 8492 // TODO: Implement the AMD64 ABI in its entirety. This simple 8493 // selection mechanism works only for the basic types. 8494 if (ArgVT == MVT::f80) { 8495 llvm_unreachable("va_arg for f80 not yet implemented"); 8496 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 8497 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 8498 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 8499 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 8500 } else { 8501 llvm_unreachable("Unhandled argument type in LowerVAARG"); 8502 } 8503 8504 if (ArgMode == 2) { 8505 // Sanity Check: Make sure using fp_offset makes sense. 8506 assert(!UseSoftFloat && 8507 !(DAG.getMachineFunction() 8508 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 8509 Subtarget->hasXMM()); 8510 } 8511 8512 // Insert VAARG_64 node into the DAG 8513 // VAARG_64 returns two values: Variable Argument Address, Chain 8514 SmallVector<SDValue, 11> InstOps; 8515 InstOps.push_back(Chain); 8516 InstOps.push_back(SrcPtr); 8517 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 8518 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 8519 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 8520 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 8521 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 8522 VTs, &InstOps[0], InstOps.size(), 8523 MVT::i64, 8524 MachinePointerInfo(SV), 8525 /*Align=*/0, 8526 /*Volatile=*/false, 8527 /*ReadMem=*/true, 8528 /*WriteMem=*/true); 8529 Chain = VAARG.getValue(1); 8530 8531 // Load the next argument and return it 8532 return DAG.getLoad(ArgVT, dl, 8533 Chain, 8534 VAARG, 8535 MachinePointerInfo(), 8536 false, false, 0); 8537} 8538 8539SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 8540 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 8541 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 8542 SDValue Chain = Op.getOperand(0); 8543 SDValue DstPtr = Op.getOperand(1); 8544 SDValue SrcPtr = Op.getOperand(2); 8545 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 8546 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8547 DebugLoc DL = Op.getDebugLoc(); 8548 8549 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 8550 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 8551 false, 8552 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 8553} 8554 8555SDValue 8556X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 8557 DebugLoc dl = Op.getDebugLoc(); 8558 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8559 switch (IntNo) { 8560 default: return SDValue(); // Don't custom lower most intrinsics. 8561 // Comparison intrinsics. 8562 case Intrinsic::x86_sse_comieq_ss: 8563 case Intrinsic::x86_sse_comilt_ss: 8564 case Intrinsic::x86_sse_comile_ss: 8565 case Intrinsic::x86_sse_comigt_ss: 8566 case Intrinsic::x86_sse_comige_ss: 8567 case Intrinsic::x86_sse_comineq_ss: 8568 case Intrinsic::x86_sse_ucomieq_ss: 8569 case Intrinsic::x86_sse_ucomilt_ss: 8570 case Intrinsic::x86_sse_ucomile_ss: 8571 case Intrinsic::x86_sse_ucomigt_ss: 8572 case Intrinsic::x86_sse_ucomige_ss: 8573 case Intrinsic::x86_sse_ucomineq_ss: 8574 case Intrinsic::x86_sse2_comieq_sd: 8575 case Intrinsic::x86_sse2_comilt_sd: 8576 case Intrinsic::x86_sse2_comile_sd: 8577 case Intrinsic::x86_sse2_comigt_sd: 8578 case Intrinsic::x86_sse2_comige_sd: 8579 case Intrinsic::x86_sse2_comineq_sd: 8580 case Intrinsic::x86_sse2_ucomieq_sd: 8581 case Intrinsic::x86_sse2_ucomilt_sd: 8582 case Intrinsic::x86_sse2_ucomile_sd: 8583 case Intrinsic::x86_sse2_ucomigt_sd: 8584 case Intrinsic::x86_sse2_ucomige_sd: 8585 case Intrinsic::x86_sse2_ucomineq_sd: { 8586 unsigned Opc = 0; 8587 ISD::CondCode CC = ISD::SETCC_INVALID; 8588 switch (IntNo) { 8589 default: break; 8590 case Intrinsic::x86_sse_comieq_ss: 8591 case Intrinsic::x86_sse2_comieq_sd: 8592 Opc = X86ISD::COMI; 8593 CC = ISD::SETEQ; 8594 break; 8595 case Intrinsic::x86_sse_comilt_ss: 8596 case Intrinsic::x86_sse2_comilt_sd: 8597 Opc = X86ISD::COMI; 8598 CC = ISD::SETLT; 8599 break; 8600 case Intrinsic::x86_sse_comile_ss: 8601 case Intrinsic::x86_sse2_comile_sd: 8602 Opc = X86ISD::COMI; 8603 CC = ISD::SETLE; 8604 break; 8605 case Intrinsic::x86_sse_comigt_ss: 8606 case Intrinsic::x86_sse2_comigt_sd: 8607 Opc = X86ISD::COMI; 8608 CC = ISD::SETGT; 8609 break; 8610 case Intrinsic::x86_sse_comige_ss: 8611 case Intrinsic::x86_sse2_comige_sd: 8612 Opc = X86ISD::COMI; 8613 CC = ISD::SETGE; 8614 break; 8615 case Intrinsic::x86_sse_comineq_ss: 8616 case Intrinsic::x86_sse2_comineq_sd: 8617 Opc = X86ISD::COMI; 8618 CC = ISD::SETNE; 8619 break; 8620 case Intrinsic::x86_sse_ucomieq_ss: 8621 case Intrinsic::x86_sse2_ucomieq_sd: 8622 Opc = X86ISD::UCOMI; 8623 CC = ISD::SETEQ; 8624 break; 8625 case Intrinsic::x86_sse_ucomilt_ss: 8626 case Intrinsic::x86_sse2_ucomilt_sd: 8627 Opc = X86ISD::UCOMI; 8628 CC = ISD::SETLT; 8629 break; 8630 case Intrinsic::x86_sse_ucomile_ss: 8631 case Intrinsic::x86_sse2_ucomile_sd: 8632 Opc = X86ISD::UCOMI; 8633 CC = ISD::SETLE; 8634 break; 8635 case Intrinsic::x86_sse_ucomigt_ss: 8636 case Intrinsic::x86_sse2_ucomigt_sd: 8637 Opc = X86ISD::UCOMI; 8638 CC = ISD::SETGT; 8639 break; 8640 case Intrinsic::x86_sse_ucomige_ss: 8641 case Intrinsic::x86_sse2_ucomige_sd: 8642 Opc = X86ISD::UCOMI; 8643 CC = ISD::SETGE; 8644 break; 8645 case Intrinsic::x86_sse_ucomineq_ss: 8646 case Intrinsic::x86_sse2_ucomineq_sd: 8647 Opc = X86ISD::UCOMI; 8648 CC = ISD::SETNE; 8649 break; 8650 } 8651 8652 SDValue LHS = Op.getOperand(1); 8653 SDValue RHS = Op.getOperand(2); 8654 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 8655 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 8656 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 8657 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8658 DAG.getConstant(X86CC, MVT::i8), Cond); 8659 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 8660 } 8661 // ptest and testp intrinsics. The intrinsic these come from are designed to 8662 // return an integer value, not just an instruction so lower it to the ptest 8663 // or testp pattern and a setcc for the result. 8664 case Intrinsic::x86_sse41_ptestz: 8665 case Intrinsic::x86_sse41_ptestc: 8666 case Intrinsic::x86_sse41_ptestnzc: 8667 case Intrinsic::x86_avx_ptestz_256: 8668 case Intrinsic::x86_avx_ptestc_256: 8669 case Intrinsic::x86_avx_ptestnzc_256: 8670 case Intrinsic::x86_avx_vtestz_ps: 8671 case Intrinsic::x86_avx_vtestc_ps: 8672 case Intrinsic::x86_avx_vtestnzc_ps: 8673 case Intrinsic::x86_avx_vtestz_pd: 8674 case Intrinsic::x86_avx_vtestc_pd: 8675 case Intrinsic::x86_avx_vtestnzc_pd: 8676 case Intrinsic::x86_avx_vtestz_ps_256: 8677 case Intrinsic::x86_avx_vtestc_ps_256: 8678 case Intrinsic::x86_avx_vtestnzc_ps_256: 8679 case Intrinsic::x86_avx_vtestz_pd_256: 8680 case Intrinsic::x86_avx_vtestc_pd_256: 8681 case Intrinsic::x86_avx_vtestnzc_pd_256: { 8682 bool IsTestPacked = false; 8683 unsigned X86CC = 0; 8684 switch (IntNo) { 8685 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 8686 case Intrinsic::x86_avx_vtestz_ps: 8687 case Intrinsic::x86_avx_vtestz_pd: 8688 case Intrinsic::x86_avx_vtestz_ps_256: 8689 case Intrinsic::x86_avx_vtestz_pd_256: 8690 IsTestPacked = true; // Fallthrough 8691 case Intrinsic::x86_sse41_ptestz: 8692 case Intrinsic::x86_avx_ptestz_256: 8693 // ZF = 1 8694 X86CC = X86::COND_E; 8695 break; 8696 case Intrinsic::x86_avx_vtestc_ps: 8697 case Intrinsic::x86_avx_vtestc_pd: 8698 case Intrinsic::x86_avx_vtestc_ps_256: 8699 case Intrinsic::x86_avx_vtestc_pd_256: 8700 IsTestPacked = true; // Fallthrough 8701 case Intrinsic::x86_sse41_ptestc: 8702 case Intrinsic::x86_avx_ptestc_256: 8703 // CF = 1 8704 X86CC = X86::COND_B; 8705 break; 8706 case Intrinsic::x86_avx_vtestnzc_ps: 8707 case Intrinsic::x86_avx_vtestnzc_pd: 8708 case Intrinsic::x86_avx_vtestnzc_ps_256: 8709 case Intrinsic::x86_avx_vtestnzc_pd_256: 8710 IsTestPacked = true; // Fallthrough 8711 case Intrinsic::x86_sse41_ptestnzc: 8712 case Intrinsic::x86_avx_ptestnzc_256: 8713 // ZF and CF = 0 8714 X86CC = X86::COND_A; 8715 break; 8716 } 8717 8718 SDValue LHS = Op.getOperand(1); 8719 SDValue RHS = Op.getOperand(2); 8720 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 8721 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 8722 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 8723 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 8724 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 8725 } 8726 8727 // Fix vector shift instructions where the last operand is a non-immediate 8728 // i32 value. 8729 case Intrinsic::x86_sse2_pslli_w: 8730 case Intrinsic::x86_sse2_pslli_d: 8731 case Intrinsic::x86_sse2_pslli_q: 8732 case Intrinsic::x86_sse2_psrli_w: 8733 case Intrinsic::x86_sse2_psrli_d: 8734 case Intrinsic::x86_sse2_psrli_q: 8735 case Intrinsic::x86_sse2_psrai_w: 8736 case Intrinsic::x86_sse2_psrai_d: 8737 case Intrinsic::x86_mmx_pslli_w: 8738 case Intrinsic::x86_mmx_pslli_d: 8739 case Intrinsic::x86_mmx_pslli_q: 8740 case Intrinsic::x86_mmx_psrli_w: 8741 case Intrinsic::x86_mmx_psrli_d: 8742 case Intrinsic::x86_mmx_psrli_q: 8743 case Intrinsic::x86_mmx_psrai_w: 8744 case Intrinsic::x86_mmx_psrai_d: { 8745 SDValue ShAmt = Op.getOperand(2); 8746 if (isa<ConstantSDNode>(ShAmt)) 8747 return SDValue(); 8748 8749 unsigned NewIntNo = 0; 8750 EVT ShAmtVT = MVT::v4i32; 8751 switch (IntNo) { 8752 case Intrinsic::x86_sse2_pslli_w: 8753 NewIntNo = Intrinsic::x86_sse2_psll_w; 8754 break; 8755 case Intrinsic::x86_sse2_pslli_d: 8756 NewIntNo = Intrinsic::x86_sse2_psll_d; 8757 break; 8758 case Intrinsic::x86_sse2_pslli_q: 8759 NewIntNo = Intrinsic::x86_sse2_psll_q; 8760 break; 8761 case Intrinsic::x86_sse2_psrli_w: 8762 NewIntNo = Intrinsic::x86_sse2_psrl_w; 8763 break; 8764 case Intrinsic::x86_sse2_psrli_d: 8765 NewIntNo = Intrinsic::x86_sse2_psrl_d; 8766 break; 8767 case Intrinsic::x86_sse2_psrli_q: 8768 NewIntNo = Intrinsic::x86_sse2_psrl_q; 8769 break; 8770 case Intrinsic::x86_sse2_psrai_w: 8771 NewIntNo = Intrinsic::x86_sse2_psra_w; 8772 break; 8773 case Intrinsic::x86_sse2_psrai_d: 8774 NewIntNo = Intrinsic::x86_sse2_psra_d; 8775 break; 8776 default: { 8777 ShAmtVT = MVT::v2i32; 8778 switch (IntNo) { 8779 case Intrinsic::x86_mmx_pslli_w: 8780 NewIntNo = Intrinsic::x86_mmx_psll_w; 8781 break; 8782 case Intrinsic::x86_mmx_pslli_d: 8783 NewIntNo = Intrinsic::x86_mmx_psll_d; 8784 break; 8785 case Intrinsic::x86_mmx_pslli_q: 8786 NewIntNo = Intrinsic::x86_mmx_psll_q; 8787 break; 8788 case Intrinsic::x86_mmx_psrli_w: 8789 NewIntNo = Intrinsic::x86_mmx_psrl_w; 8790 break; 8791 case Intrinsic::x86_mmx_psrli_d: 8792 NewIntNo = Intrinsic::x86_mmx_psrl_d; 8793 break; 8794 case Intrinsic::x86_mmx_psrli_q: 8795 NewIntNo = Intrinsic::x86_mmx_psrl_q; 8796 break; 8797 case Intrinsic::x86_mmx_psrai_w: 8798 NewIntNo = Intrinsic::x86_mmx_psra_w; 8799 break; 8800 case Intrinsic::x86_mmx_psrai_d: 8801 NewIntNo = Intrinsic::x86_mmx_psra_d; 8802 break; 8803 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 8804 } 8805 break; 8806 } 8807 } 8808 8809 // The vector shift intrinsics with scalars uses 32b shift amounts but 8810 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 8811 // to be zero. 8812 SDValue ShOps[4]; 8813 ShOps[0] = ShAmt; 8814 ShOps[1] = DAG.getConstant(0, MVT::i32); 8815 if (ShAmtVT == MVT::v4i32) { 8816 ShOps[2] = DAG.getUNDEF(MVT::i32); 8817 ShOps[3] = DAG.getUNDEF(MVT::i32); 8818 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 8819 } else { 8820 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 8821// FIXME this must be lowered to get rid of the invalid type. 8822 } 8823 8824 EVT VT = Op.getValueType(); 8825 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 8826 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 8827 DAG.getConstant(NewIntNo, MVT::i32), 8828 Op.getOperand(1), ShAmt); 8829 } 8830 } 8831} 8832 8833SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 8834 SelectionDAG &DAG) const { 8835 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8836 MFI->setReturnAddressIsTaken(true); 8837 8838 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8839 DebugLoc dl = Op.getDebugLoc(); 8840 8841 if (Depth > 0) { 8842 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 8843 SDValue Offset = 8844 DAG.getConstant(TD->getPointerSize(), 8845 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 8846 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 8847 DAG.getNode(ISD::ADD, dl, getPointerTy(), 8848 FrameAddr, Offset), 8849 MachinePointerInfo(), false, false, 0); 8850 } 8851 8852 // Just load the return address. 8853 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 8854 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 8855 RetAddrFI, MachinePointerInfo(), false, false, 0); 8856} 8857 8858SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 8859 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8860 MFI->setFrameAddressIsTaken(true); 8861 8862 EVT VT = Op.getValueType(); 8863 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 8864 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 8865 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 8866 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 8867 while (Depth--) 8868 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 8869 MachinePointerInfo(), 8870 false, false, 0); 8871 return FrameAddr; 8872} 8873 8874SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 8875 SelectionDAG &DAG) const { 8876 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 8877} 8878 8879SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 8880 MachineFunction &MF = DAG.getMachineFunction(); 8881 SDValue Chain = Op.getOperand(0); 8882 SDValue Offset = Op.getOperand(1); 8883 SDValue Handler = Op.getOperand(2); 8884 DebugLoc dl = Op.getDebugLoc(); 8885 8886 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 8887 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 8888 getPointerTy()); 8889 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 8890 8891 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 8892 DAG.getIntPtrConstant(TD->getPointerSize())); 8893 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 8894 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 8895 false, false, 0); 8896 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 8897 MF.getRegInfo().addLiveOut(StoreAddrReg); 8898 8899 return DAG.getNode(X86ISD::EH_RETURN, dl, 8900 MVT::Other, 8901 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 8902} 8903 8904SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 8905 SelectionDAG &DAG) const { 8906 SDValue Root = Op.getOperand(0); 8907 SDValue Trmp = Op.getOperand(1); // trampoline 8908 SDValue FPtr = Op.getOperand(2); // nested function 8909 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 8910 DebugLoc dl = Op.getDebugLoc(); 8911 8912 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 8913 8914 if (Subtarget->is64Bit()) { 8915 SDValue OutChains[6]; 8916 8917 // Large code-model. 8918 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 8919 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 8920 8921 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 8922 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 8923 8924 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 8925 8926 // Load the pointer to the nested function into R11. 8927 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 8928 SDValue Addr = Trmp; 8929 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8930 Addr, MachinePointerInfo(TrmpAddr), 8931 false, false, 0); 8932 8933 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8934 DAG.getConstant(2, MVT::i64)); 8935 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 8936 MachinePointerInfo(TrmpAddr, 2), 8937 false, false, 2); 8938 8939 // Load the 'nest' parameter value into R10. 8940 // R10 is specified in X86CallingConv.td 8941 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 8942 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8943 DAG.getConstant(10, MVT::i64)); 8944 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8945 Addr, MachinePointerInfo(TrmpAddr, 10), 8946 false, false, 0); 8947 8948 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8949 DAG.getConstant(12, MVT::i64)); 8950 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 8951 MachinePointerInfo(TrmpAddr, 12), 8952 false, false, 2); 8953 8954 // Jump to the nested function. 8955 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 8956 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8957 DAG.getConstant(20, MVT::i64)); 8958 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 8959 Addr, MachinePointerInfo(TrmpAddr, 20), 8960 false, false, 0); 8961 8962 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 8963 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 8964 DAG.getConstant(22, MVT::i64)); 8965 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 8966 MachinePointerInfo(TrmpAddr, 22), 8967 false, false, 0); 8968 8969 SDValue Ops[] = 8970 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 8971 return DAG.getMergeValues(Ops, 2, dl); 8972 } else { 8973 const Function *Func = 8974 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 8975 CallingConv::ID CC = Func->getCallingConv(); 8976 unsigned NestReg; 8977 8978 switch (CC) { 8979 default: 8980 llvm_unreachable("Unsupported calling convention"); 8981 case CallingConv::C: 8982 case CallingConv::X86_StdCall: { 8983 // Pass 'nest' parameter in ECX. 8984 // Must be kept in sync with X86CallingConv.td 8985 NestReg = X86::ECX; 8986 8987 // Check that ECX wasn't needed by an 'inreg' parameter. 8988 FunctionType *FTy = Func->getFunctionType(); 8989 const AttrListPtr &Attrs = Func->getAttributes(); 8990 8991 if (!Attrs.isEmpty() && !Func->isVarArg()) { 8992 unsigned InRegCount = 0; 8993 unsigned Idx = 1; 8994 8995 for (FunctionType::param_iterator I = FTy->param_begin(), 8996 E = FTy->param_end(); I != E; ++I, ++Idx) 8997 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 8998 // FIXME: should only count parameters that are lowered to integers. 8999 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9000 9001 if (InRegCount > 2) { 9002 report_fatal_error("Nest register in use - reduce number of inreg" 9003 " parameters!"); 9004 } 9005 } 9006 break; 9007 } 9008 case CallingConv::X86_FastCall: 9009 case CallingConv::X86_ThisCall: 9010 case CallingConv::Fast: 9011 // Pass 'nest' parameter in EAX. 9012 // Must be kept in sync with X86CallingConv.td 9013 NestReg = X86::EAX; 9014 break; 9015 } 9016 9017 SDValue OutChains[4]; 9018 SDValue Addr, Disp; 9019 9020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9021 DAG.getConstant(10, MVT::i32)); 9022 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9023 9024 // This is storing the opcode for MOV32ri. 9025 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9026 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9027 OutChains[0] = DAG.getStore(Root, dl, 9028 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9029 Trmp, MachinePointerInfo(TrmpAddr), 9030 false, false, 0); 9031 9032 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9033 DAG.getConstant(1, MVT::i32)); 9034 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9035 MachinePointerInfo(TrmpAddr, 1), 9036 false, false, 1); 9037 9038 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9039 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9040 DAG.getConstant(5, MVT::i32)); 9041 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9042 MachinePointerInfo(TrmpAddr, 5), 9043 false, false, 1); 9044 9045 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9046 DAG.getConstant(6, MVT::i32)); 9047 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9048 MachinePointerInfo(TrmpAddr, 6), 9049 false, false, 1); 9050 9051 SDValue Ops[] = 9052 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 9053 return DAG.getMergeValues(Ops, 2, dl); 9054 } 9055} 9056 9057SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9058 SelectionDAG &DAG) const { 9059 /* 9060 The rounding mode is in bits 11:10 of FPSR, and has the following 9061 settings: 9062 00 Round to nearest 9063 01 Round to -inf 9064 10 Round to +inf 9065 11 Round to 0 9066 9067 FLT_ROUNDS, on the other hand, expects the following: 9068 -1 Undefined 9069 0 Round to 0 9070 1 Round to nearest 9071 2 Round to +inf 9072 3 Round to -inf 9073 9074 To perform the conversion, we do: 9075 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9076 */ 9077 9078 MachineFunction &MF = DAG.getMachineFunction(); 9079 const TargetMachine &TM = MF.getTarget(); 9080 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9081 unsigned StackAlignment = TFI.getStackAlignment(); 9082 EVT VT = Op.getValueType(); 9083 DebugLoc DL = Op.getDebugLoc(); 9084 9085 // Save FP Control Word to stack slot 9086 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9087 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9088 9089 9090 MachineMemOperand *MMO = 9091 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9092 MachineMemOperand::MOStore, 2, 2); 9093 9094 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9095 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9096 DAG.getVTList(MVT::Other), 9097 Ops, 2, MVT::i16, MMO); 9098 9099 // Load FP Control Word from stack slot 9100 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9101 MachinePointerInfo(), false, false, 0); 9102 9103 // Transform as necessary 9104 SDValue CWD1 = 9105 DAG.getNode(ISD::SRL, DL, MVT::i16, 9106 DAG.getNode(ISD::AND, DL, MVT::i16, 9107 CWD, DAG.getConstant(0x800, MVT::i16)), 9108 DAG.getConstant(11, MVT::i8)); 9109 SDValue CWD2 = 9110 DAG.getNode(ISD::SRL, DL, MVT::i16, 9111 DAG.getNode(ISD::AND, DL, MVT::i16, 9112 CWD, DAG.getConstant(0x400, MVT::i16)), 9113 DAG.getConstant(9, MVT::i8)); 9114 9115 SDValue RetVal = 9116 DAG.getNode(ISD::AND, DL, MVT::i16, 9117 DAG.getNode(ISD::ADD, DL, MVT::i16, 9118 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9119 DAG.getConstant(1, MVT::i16)), 9120 DAG.getConstant(3, MVT::i16)); 9121 9122 9123 return DAG.getNode((VT.getSizeInBits() < 16 ? 9124 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9125} 9126 9127SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9128 EVT VT = Op.getValueType(); 9129 EVT OpVT = VT; 9130 unsigned NumBits = VT.getSizeInBits(); 9131 DebugLoc dl = Op.getDebugLoc(); 9132 9133 Op = Op.getOperand(0); 9134 if (VT == MVT::i8) { 9135 // Zero extend to i32 since there is not an i8 bsr. 9136 OpVT = MVT::i32; 9137 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9138 } 9139 9140 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9141 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9142 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9143 9144 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9145 SDValue Ops[] = { 9146 Op, 9147 DAG.getConstant(NumBits+NumBits-1, OpVT), 9148 DAG.getConstant(X86::COND_E, MVT::i8), 9149 Op.getValue(1) 9150 }; 9151 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9152 9153 // Finally xor with NumBits-1. 9154 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9155 9156 if (VT == MVT::i8) 9157 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9158 return Op; 9159} 9160 9161SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9162 EVT VT = Op.getValueType(); 9163 EVT OpVT = VT; 9164 unsigned NumBits = VT.getSizeInBits(); 9165 DebugLoc dl = Op.getDebugLoc(); 9166 9167 Op = Op.getOperand(0); 9168 if (VT == MVT::i8) { 9169 OpVT = MVT::i32; 9170 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9171 } 9172 9173 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9174 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9175 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9176 9177 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9178 SDValue Ops[] = { 9179 Op, 9180 DAG.getConstant(NumBits, OpVT), 9181 DAG.getConstant(X86::COND_E, MVT::i8), 9182 Op.getValue(1) 9183 }; 9184 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9185 9186 if (VT == MVT::i8) 9187 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9188 return Op; 9189} 9190 9191SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const { 9192 EVT VT = Op.getValueType(); 9193 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9194 DebugLoc dl = Op.getDebugLoc(); 9195 9196 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9197 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9198 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9199 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9200 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9201 // 9202 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9203 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9204 // return AloBlo + AloBhi + AhiBlo; 9205 9206 SDValue A = Op.getOperand(0); 9207 SDValue B = Op.getOperand(1); 9208 9209 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9210 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9211 A, DAG.getConstant(32, MVT::i32)); 9212 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9213 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9214 B, DAG.getConstant(32, MVT::i32)); 9215 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9216 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9217 A, B); 9218 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9219 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9220 A, Bhi); 9221 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9222 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9223 Ahi, B); 9224 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9225 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9226 AloBhi, DAG.getConstant(32, MVT::i32)); 9227 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9228 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9229 AhiBlo, DAG.getConstant(32, MVT::i32)); 9230 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9231 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9232 return Res; 9233} 9234 9235SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 9236 9237 EVT VT = Op.getValueType(); 9238 DebugLoc dl = Op.getDebugLoc(); 9239 SDValue R = Op.getOperand(0); 9240 SDValue Amt = Op.getOperand(1); 9241 LLVMContext *Context = DAG.getContext(); 9242 9243 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX())) 9244 return SDValue(); 9245 9246 // Decompose 256-bit shifts into smaller 128-bit shifts. 9247 if (VT.getSizeInBits() == 256) { 9248 int NumElems = VT.getVectorNumElements(); 9249 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9250 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9251 9252 // Extract the two vectors 9253 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 9254 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 9255 DAG, dl); 9256 9257 // Recreate the shift amount vectors 9258 SmallVector<SDValue, 4> Amt1Csts; 9259 SmallVector<SDValue, 4> Amt2Csts; 9260 for (int i = 0; i < NumElems/2; ++i) 9261 Amt1Csts.push_back(Amt->getOperand(i)); 9262 for (int i = NumElems/2; i < NumElems; ++i) 9263 Amt2Csts.push_back(Amt->getOperand(i)); 9264 9265 SDValue Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9266 &Amt1Csts[0], NumElems/2); 9267 SDValue Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9268 &Amt2Csts[0], NumElems/2); 9269 9270 // Issue new vector shifts for the smaller types 9271 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 9272 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 9273 9274 // Concatenate the result back 9275 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 9276 } 9277 9278 // Optimize shl/srl/sra with constant shift amount. 9279 if (isSplatVector(Amt.getNode())) { 9280 SDValue SclrAmt = Amt->getOperand(0); 9281 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 9282 uint64_t ShiftAmt = C->getZExtValue(); 9283 9284 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 9285 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9286 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9287 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9288 9289 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 9290 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9291 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9292 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9293 9294 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 9295 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9296 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9297 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9298 9299 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 9300 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9301 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9302 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9303 9304 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 9305 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9306 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9307 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9308 9309 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 9310 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9311 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9312 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9313 9314 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 9315 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9316 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9317 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9318 9319 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 9320 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9321 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9322 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9323 } 9324 } 9325 9326 // Lower SHL with variable shift amount. 9327 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 9328 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9329 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9330 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 9331 9332 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 9333 9334 std::vector<Constant*> CV(4, CI); 9335 Constant *C = ConstantVector::get(CV); 9336 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9337 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9338 MachinePointerInfo::getConstantPool(), 9339 false, false, 16); 9340 9341 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 9342 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 9343 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 9344 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 9345 } 9346 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 9347 // a = a << 5; 9348 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9349 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9350 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 9351 9352 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 9353 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 9354 9355 std::vector<Constant*> CVM1(16, CM1); 9356 std::vector<Constant*> CVM2(16, CM2); 9357 Constant *C = ConstantVector::get(CVM1); 9358 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9359 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9360 MachinePointerInfo::getConstantPool(), 9361 false, false, 16); 9362 9363 // r = pblendv(r, psllw(r & (char16)15, 4), a); 9364 M = DAG.getNode(ISD::AND, dl, VT, R, M); 9365 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9366 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 9367 DAG.getConstant(4, MVT::i32)); 9368 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 9369 // a += a 9370 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 9371 9372 C = ConstantVector::get(CVM2); 9373 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9374 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9375 MachinePointerInfo::getConstantPool(), 9376 false, false, 16); 9377 9378 // r = pblendv(r, psllw(r & (char16)63, 2), a); 9379 M = DAG.getNode(ISD::AND, dl, VT, R, M); 9380 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9381 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 9382 DAG.getConstant(2, MVT::i32)); 9383 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op); 9384 // a += a 9385 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 9386 9387 // return pblendv(r, r+r, a); 9388 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, 9389 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); 9390 return R; 9391 } 9392 return SDValue(); 9393} 9394 9395SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 9396 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 9397 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 9398 // looks for this combo and may remove the "setcc" instruction if the "setcc" 9399 // has only one use. 9400 SDNode *N = Op.getNode(); 9401 SDValue LHS = N->getOperand(0); 9402 SDValue RHS = N->getOperand(1); 9403 unsigned BaseOp = 0; 9404 unsigned Cond = 0; 9405 DebugLoc DL = Op.getDebugLoc(); 9406 switch (Op.getOpcode()) { 9407 default: llvm_unreachable("Unknown ovf instruction!"); 9408 case ISD::SADDO: 9409 // A subtract of one will be selected as a INC. Note that INC doesn't 9410 // set CF, so we can't do this for UADDO. 9411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 9412 if (C->isOne()) { 9413 BaseOp = X86ISD::INC; 9414 Cond = X86::COND_O; 9415 break; 9416 } 9417 BaseOp = X86ISD::ADD; 9418 Cond = X86::COND_O; 9419 break; 9420 case ISD::UADDO: 9421 BaseOp = X86ISD::ADD; 9422 Cond = X86::COND_B; 9423 break; 9424 case ISD::SSUBO: 9425 // A subtract of one will be selected as a DEC. Note that DEC doesn't 9426 // set CF, so we can't do this for USUBO. 9427 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 9428 if (C->isOne()) { 9429 BaseOp = X86ISD::DEC; 9430 Cond = X86::COND_O; 9431 break; 9432 } 9433 BaseOp = X86ISD::SUB; 9434 Cond = X86::COND_O; 9435 break; 9436 case ISD::USUBO: 9437 BaseOp = X86ISD::SUB; 9438 Cond = X86::COND_B; 9439 break; 9440 case ISD::SMULO: 9441 BaseOp = X86ISD::SMUL; 9442 Cond = X86::COND_O; 9443 break; 9444 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 9445 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 9446 MVT::i32); 9447 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 9448 9449 SDValue SetCC = 9450 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9451 DAG.getConstant(X86::COND_O, MVT::i32), 9452 SDValue(Sum.getNode(), 2)); 9453 9454 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 9455 } 9456 } 9457 9458 // Also sets EFLAGS. 9459 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 9460 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 9461 9462 SDValue SetCC = 9463 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 9464 DAG.getConstant(Cond, MVT::i32), 9465 SDValue(Sum.getNode(), 1)); 9466 9467 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 9468} 9469 9470SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 9471 DebugLoc dl = Op.getDebugLoc(); 9472 SDNode* Node = Op.getNode(); 9473 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 9474 EVT VT = Node->getValueType(0); 9475 9476 if (Subtarget->hasSSE2() && VT.isVector()) { 9477 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 9478 ExtraVT.getScalarType().getSizeInBits(); 9479 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 9480 9481 unsigned SHLIntrinsicsID = 0; 9482 unsigned SRAIntrinsicsID = 0; 9483 switch (VT.getSimpleVT().SimpleTy) { 9484 default: 9485 return SDValue(); 9486 case MVT::v2i64: { 9487 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q; 9488 SRAIntrinsicsID = 0; 9489 break; 9490 } 9491 case MVT::v4i32: { 9492 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 9493 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 9494 break; 9495 } 9496 case MVT::v8i16: { 9497 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 9498 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 9499 break; 9500 } 9501 } 9502 9503 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9504 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 9505 Node->getOperand(0), ShAmt); 9506 9507 // In case of 1 bit sext, no need to shr 9508 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; 9509 9510 if (SRAIntrinsicsID) { 9511 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9512 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 9513 Tmp1, ShAmt); 9514 } 9515 return Tmp1; 9516 } 9517 9518 return SDValue(); 9519} 9520 9521 9522SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 9523 DebugLoc dl = Op.getDebugLoc(); 9524 9525 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 9526 // There isn't any reason to disable it if the target processor supports it. 9527 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 9528 SDValue Chain = Op.getOperand(0); 9529 SDValue Zero = DAG.getConstant(0, MVT::i32); 9530 SDValue Ops[] = { 9531 DAG.getRegister(X86::ESP, MVT::i32), // Base 9532 DAG.getTargetConstant(1, MVT::i8), // Scale 9533 DAG.getRegister(0, MVT::i32), // Index 9534 DAG.getTargetConstant(0, MVT::i32), // Disp 9535 DAG.getRegister(0, MVT::i32), // Segment. 9536 Zero, 9537 Chain 9538 }; 9539 SDNode *Res = 9540 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 9541 array_lengthof(Ops)); 9542 return SDValue(Res, 0); 9543 } 9544 9545 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 9546 if (!isDev) 9547 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 9548 9549 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 9550 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 9551 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 9552 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 9553 9554 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 9555 if (!Op1 && !Op2 && !Op3 && Op4) 9556 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 9557 9558 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 9559 if (Op1 && !Op2 && !Op3 && !Op4) 9560 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 9561 9562 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 9563 // (MFENCE)>; 9564 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 9565} 9566 9567SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 9568 SelectionDAG &DAG) const { 9569 DebugLoc dl = Op.getDebugLoc(); 9570 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 9571 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 9572 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 9573 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 9574 9575 // The only fence that needs an instruction is a sequentially-consistent 9576 // cross-thread fence. 9577 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 9578 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 9579 // no-sse2). There isn't any reason to disable it if the target processor 9580 // supports it. 9581 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 9582 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 9583 9584 SDValue Chain = Op.getOperand(0); 9585 SDValue Zero = DAG.getConstant(0, MVT::i32); 9586 SDValue Ops[] = { 9587 DAG.getRegister(X86::ESP, MVT::i32), // Base 9588 DAG.getTargetConstant(1, MVT::i8), // Scale 9589 DAG.getRegister(0, MVT::i32), // Index 9590 DAG.getTargetConstant(0, MVT::i32), // Disp 9591 DAG.getRegister(0, MVT::i32), // Segment. 9592 Zero, 9593 Chain 9594 }; 9595 SDNode *Res = 9596 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 9597 array_lengthof(Ops)); 9598 return SDValue(Res, 0); 9599 } 9600 9601 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 9602 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 9603} 9604 9605 9606SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 9607 EVT T = Op.getValueType(); 9608 DebugLoc DL = Op.getDebugLoc(); 9609 unsigned Reg = 0; 9610 unsigned size = 0; 9611 switch(T.getSimpleVT().SimpleTy) { 9612 default: 9613 assert(false && "Invalid value type!"); 9614 case MVT::i8: Reg = X86::AL; size = 1; break; 9615 case MVT::i16: Reg = X86::AX; size = 2; break; 9616 case MVT::i32: Reg = X86::EAX; size = 4; break; 9617 case MVT::i64: 9618 assert(Subtarget->is64Bit() && "Node not type legal!"); 9619 Reg = X86::RAX; size = 8; 9620 break; 9621 } 9622 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 9623 Op.getOperand(2), SDValue()); 9624 SDValue Ops[] = { cpIn.getValue(0), 9625 Op.getOperand(1), 9626 Op.getOperand(3), 9627 DAG.getTargetConstant(size, MVT::i8), 9628 cpIn.getValue(1) }; 9629 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9630 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 9631 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 9632 Ops, 5, T, MMO); 9633 SDValue cpOut = 9634 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 9635 return cpOut; 9636} 9637 9638SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 9639 SelectionDAG &DAG) const { 9640 assert(Subtarget->is64Bit() && "Result not type legalized?"); 9641 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9642 SDValue TheChain = Op.getOperand(0); 9643 DebugLoc dl = Op.getDebugLoc(); 9644 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 9645 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 9646 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 9647 rax.getValue(2)); 9648 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 9649 DAG.getConstant(32, MVT::i8)); 9650 SDValue Ops[] = { 9651 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 9652 rdx.getValue(1) 9653 }; 9654 return DAG.getMergeValues(Ops, 2, dl); 9655} 9656 9657SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 9658 SelectionDAG &DAG) const { 9659 EVT SrcVT = Op.getOperand(0).getValueType(); 9660 EVT DstVT = Op.getValueType(); 9661 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 9662 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 9663 assert((DstVT == MVT::i64 || 9664 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 9665 "Unexpected custom BITCAST"); 9666 // i64 <=> MMX conversions are Legal. 9667 if (SrcVT==MVT::i64 && DstVT.isVector()) 9668 return Op; 9669 if (DstVT==MVT::i64 && SrcVT.isVector()) 9670 return Op; 9671 // MMX <=> MMX conversions are Legal. 9672 if (SrcVT.isVector() && DstVT.isVector()) 9673 return Op; 9674 // All other conversions need to be expanded. 9675 return SDValue(); 9676} 9677 9678SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 9679 SDNode *Node = Op.getNode(); 9680 DebugLoc dl = Node->getDebugLoc(); 9681 EVT T = Node->getValueType(0); 9682 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 9683 DAG.getConstant(0, T), Node->getOperand(2)); 9684 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 9685 cast<AtomicSDNode>(Node)->getMemoryVT(), 9686 Node->getOperand(0), 9687 Node->getOperand(1), negOp, 9688 cast<AtomicSDNode>(Node)->getSrcValue(), 9689 cast<AtomicSDNode>(Node)->getAlignment(), 9690 cast<AtomicSDNode>(Node)->getOrdering(), 9691 cast<AtomicSDNode>(Node)->getSynchScope()); 9692} 9693 9694static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 9695 EVT VT = Op.getNode()->getValueType(0); 9696 9697 // Let legalize expand this if it isn't a legal type yet. 9698 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 9699 return SDValue(); 9700 9701 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9702 9703 unsigned Opc; 9704 bool ExtraOp = false; 9705 switch (Op.getOpcode()) { 9706 default: assert(0 && "Invalid code"); 9707 case ISD::ADDC: Opc = X86ISD::ADD; break; 9708 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 9709 case ISD::SUBC: Opc = X86ISD::SUB; break; 9710 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 9711 } 9712 9713 if (!ExtraOp) 9714 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 9715 Op.getOperand(1)); 9716 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 9717 Op.getOperand(1), Op.getOperand(2)); 9718} 9719 9720/// LowerOperation - Provide custom lowering hooks for some operations. 9721/// 9722SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 9723 switch (Op.getOpcode()) { 9724 default: llvm_unreachable("Should not custom lower this!"); 9725 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 9726 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 9727 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 9728 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 9729 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 9730 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 9731 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 9732 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 9733 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 9734 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 9735 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 9736 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 9737 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 9738 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 9739 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 9740 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 9741 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 9742 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 9743 case ISD::SHL_PARTS: 9744 case ISD::SRA_PARTS: 9745 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 9746 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 9747 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 9748 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 9749 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 9750 case ISD::FABS: return LowerFABS(Op, DAG); 9751 case ISD::FNEG: return LowerFNEG(Op, DAG); 9752 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 9753 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 9754 case ISD::SETCC: return LowerSETCC(Op, DAG); 9755 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 9756 case ISD::SELECT: return LowerSELECT(Op, DAG); 9757 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 9758 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 9759 case ISD::VASTART: return LowerVASTART(Op, DAG); 9760 case ISD::VAARG: return LowerVAARG(Op, DAG); 9761 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 9762 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 9763 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 9764 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 9765 case ISD::FRAME_TO_ARGS_OFFSET: 9766 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 9767 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 9768 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 9769 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 9770 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 9771 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 9772 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 9773 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 9774 case ISD::SRA: 9775 case ISD::SRL: 9776 case ISD::SHL: return LowerShift(Op, DAG); 9777 case ISD::SADDO: 9778 case ISD::UADDO: 9779 case ISD::SSUBO: 9780 case ISD::USUBO: 9781 case ISD::SMULO: 9782 case ISD::UMULO: return LowerXALUO(Op, DAG); 9783 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 9784 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 9785 case ISD::ADDC: 9786 case ISD::ADDE: 9787 case ISD::SUBC: 9788 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 9789 } 9790} 9791 9792void X86TargetLowering:: 9793ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 9794 SelectionDAG &DAG, unsigned NewOp) const { 9795 EVT T = Node->getValueType(0); 9796 DebugLoc dl = Node->getDebugLoc(); 9797 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 9798 9799 SDValue Chain = Node->getOperand(0); 9800 SDValue In1 = Node->getOperand(1); 9801 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 9802 Node->getOperand(2), DAG.getIntPtrConstant(0)); 9803 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 9804 Node->getOperand(2), DAG.getIntPtrConstant(1)); 9805 SDValue Ops[] = { Chain, In1, In2L, In2H }; 9806 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 9807 SDValue Result = 9808 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 9809 cast<MemSDNode>(Node)->getMemOperand()); 9810 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 9811 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 9812 Results.push_back(Result.getValue(2)); 9813} 9814 9815/// ReplaceNodeResults - Replace a node with an illegal result type 9816/// with a new node built out of custom code. 9817void X86TargetLowering::ReplaceNodeResults(SDNode *N, 9818 SmallVectorImpl<SDValue>&Results, 9819 SelectionDAG &DAG) const { 9820 DebugLoc dl = N->getDebugLoc(); 9821 switch (N->getOpcode()) { 9822 default: 9823 assert(false && "Do not know how to custom type legalize this operation!"); 9824 return; 9825 case ISD::SIGN_EXTEND_INREG: 9826 case ISD::ADDC: 9827 case ISD::ADDE: 9828 case ISD::SUBC: 9829 case ISD::SUBE: 9830 // We don't want to expand or promote these. 9831 return; 9832 case ISD::FP_TO_SINT: { 9833 std::pair<SDValue,SDValue> Vals = 9834 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 9835 SDValue FIST = Vals.first, StackSlot = Vals.second; 9836 if (FIST.getNode() != 0) { 9837 EVT VT = N->getValueType(0); 9838 // Return a load from the stack slot. 9839 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 9840 MachinePointerInfo(), false, false, 0)); 9841 } 9842 return; 9843 } 9844 case ISD::READCYCLECOUNTER: { 9845 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9846 SDValue TheChain = N->getOperand(0); 9847 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 9848 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 9849 rd.getValue(1)); 9850 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 9851 eax.getValue(2)); 9852 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 9853 SDValue Ops[] = { eax, edx }; 9854 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 9855 Results.push_back(edx.getValue(1)); 9856 return; 9857 } 9858 case ISD::ATOMIC_CMP_SWAP: { 9859 EVT T = N->getValueType(0); 9860 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 9861 SDValue cpInL, cpInH; 9862 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 9863 DAG.getConstant(0, MVT::i32)); 9864 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 9865 DAG.getConstant(1, MVT::i32)); 9866 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 9867 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 9868 cpInL.getValue(1)); 9869 SDValue swapInL, swapInH; 9870 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 9871 DAG.getConstant(0, MVT::i32)); 9872 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 9873 DAG.getConstant(1, MVT::i32)); 9874 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 9875 cpInH.getValue(1)); 9876 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 9877 swapInL.getValue(1)); 9878 SDValue Ops[] = { swapInH.getValue(0), 9879 N->getOperand(1), 9880 swapInH.getValue(1) }; 9881 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 9882 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 9883 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, 9884 Ops, 3, T, MMO); 9885 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 9886 MVT::i32, Result.getValue(1)); 9887 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 9888 MVT::i32, cpOutL.getValue(2)); 9889 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 9890 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 9891 Results.push_back(cpOutH.getValue(1)); 9892 return; 9893 } 9894 case ISD::ATOMIC_LOAD_ADD: 9895 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 9896 return; 9897 case ISD::ATOMIC_LOAD_AND: 9898 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 9899 return; 9900 case ISD::ATOMIC_LOAD_NAND: 9901 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 9902 return; 9903 case ISD::ATOMIC_LOAD_OR: 9904 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 9905 return; 9906 case ISD::ATOMIC_LOAD_SUB: 9907 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 9908 return; 9909 case ISD::ATOMIC_LOAD_XOR: 9910 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 9911 return; 9912 case ISD::ATOMIC_SWAP: 9913 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 9914 return; 9915 } 9916} 9917 9918const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 9919 switch (Opcode) { 9920 default: return NULL; 9921 case X86ISD::BSF: return "X86ISD::BSF"; 9922 case X86ISD::BSR: return "X86ISD::BSR"; 9923 case X86ISD::SHLD: return "X86ISD::SHLD"; 9924 case X86ISD::SHRD: return "X86ISD::SHRD"; 9925 case X86ISD::FAND: return "X86ISD::FAND"; 9926 case X86ISD::FOR: return "X86ISD::FOR"; 9927 case X86ISD::FXOR: return "X86ISD::FXOR"; 9928 case X86ISD::FSRL: return "X86ISD::FSRL"; 9929 case X86ISD::FILD: return "X86ISD::FILD"; 9930 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 9931 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 9932 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 9933 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 9934 case X86ISD::FLD: return "X86ISD::FLD"; 9935 case X86ISD::FST: return "X86ISD::FST"; 9936 case X86ISD::CALL: return "X86ISD::CALL"; 9937 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 9938 case X86ISD::BT: return "X86ISD::BT"; 9939 case X86ISD::CMP: return "X86ISD::CMP"; 9940 case X86ISD::COMI: return "X86ISD::COMI"; 9941 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 9942 case X86ISD::SETCC: return "X86ISD::SETCC"; 9943 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 9944 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 9945 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 9946 case X86ISD::CMOV: return "X86ISD::CMOV"; 9947 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 9948 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 9949 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 9950 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 9951 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 9952 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 9953 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 9954 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 9955 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 9956 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 9957 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 9958 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 9959 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 9960 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 9961 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 9962 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 9963 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 9964 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB"; 9965 case X86ISD::FMAX: return "X86ISD::FMAX"; 9966 case X86ISD::FMIN: return "X86ISD::FMIN"; 9967 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 9968 case X86ISD::FRCP: return "X86ISD::FRCP"; 9969 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 9970 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 9971 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 9972 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 9973 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 9974 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 9975 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 9976 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 9977 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 9978 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 9979 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 9980 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 9981 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 9982 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 9983 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 9984 case X86ISD::VSHL: return "X86ISD::VSHL"; 9985 case X86ISD::VSRL: return "X86ISD::VSRL"; 9986 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 9987 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 9988 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 9989 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 9990 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 9991 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 9992 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 9993 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 9994 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 9995 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 9996 case X86ISD::ADD: return "X86ISD::ADD"; 9997 case X86ISD::SUB: return "X86ISD::SUB"; 9998 case X86ISD::ADC: return "X86ISD::ADC"; 9999 case X86ISD::SBB: return "X86ISD::SBB"; 10000 case X86ISD::SMUL: return "X86ISD::SMUL"; 10001 case X86ISD::UMUL: return "X86ISD::UMUL"; 10002 case X86ISD::INC: return "X86ISD::INC"; 10003 case X86ISD::DEC: return "X86ISD::DEC"; 10004 case X86ISD::OR: return "X86ISD::OR"; 10005 case X86ISD::XOR: return "X86ISD::XOR"; 10006 case X86ISD::AND: return "X86ISD::AND"; 10007 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10008 case X86ISD::PTEST: return "X86ISD::PTEST"; 10009 case X86ISD::TESTP: return "X86ISD::TESTP"; 10010 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10011 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10012 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10013 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10014 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10015 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10016 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 10017 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 10018 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10019 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10020 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10021 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 10022 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10023 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10024 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10025 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10026 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10027 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 10028 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 10029 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10030 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10031 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 10032 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 10033 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 10034 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 10035 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 10036 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 10037 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 10038 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 10039 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 10040 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 10041 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 10042 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 10043 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 10044 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 10045 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 10046 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 10047 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 10048 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 10049 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 10050 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 10051 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 10052 } 10053} 10054 10055// isLegalAddressingMode - Return true if the addressing mode represented 10056// by AM is legal for this target, for a load/store of the specified type. 10057bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 10058 Type *Ty) const { 10059 // X86 supports extremely general addressing modes. 10060 CodeModel::Model M = getTargetMachine().getCodeModel(); 10061 Reloc::Model R = getTargetMachine().getRelocationModel(); 10062 10063 // X86 allows a sign-extended 32-bit immediate field as a displacement. 10064 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 10065 return false; 10066 10067 if (AM.BaseGV) { 10068 unsigned GVFlags = 10069 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 10070 10071 // If a reference to this global requires an extra load, we can't fold it. 10072 if (isGlobalStubReference(GVFlags)) 10073 return false; 10074 10075 // If BaseGV requires a register for the PIC base, we cannot also have a 10076 // BaseReg specified. 10077 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 10078 return false; 10079 10080 // If lower 4G is not available, then we must use rip-relative addressing. 10081 if ((M != CodeModel::Small || R != Reloc::Static) && 10082 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 10083 return false; 10084 } 10085 10086 switch (AM.Scale) { 10087 case 0: 10088 case 1: 10089 case 2: 10090 case 4: 10091 case 8: 10092 // These scales always work. 10093 break; 10094 case 3: 10095 case 5: 10096 case 9: 10097 // These scales are formed with basereg+scalereg. Only accept if there is 10098 // no basereg yet. 10099 if (AM.HasBaseReg) 10100 return false; 10101 break; 10102 default: // Other stuff never works. 10103 return false; 10104 } 10105 10106 return true; 10107} 10108 10109 10110bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 10111 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 10112 return false; 10113 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 10114 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 10115 if (NumBits1 <= NumBits2) 10116 return false; 10117 return true; 10118} 10119 10120bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 10121 if (!VT1.isInteger() || !VT2.isInteger()) 10122 return false; 10123 unsigned NumBits1 = VT1.getSizeInBits(); 10124 unsigned NumBits2 = VT2.getSizeInBits(); 10125 if (NumBits1 <= NumBits2) 10126 return false; 10127 return true; 10128} 10129 10130bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 10131 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10132 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 10133} 10134 10135bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 10136 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10137 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 10138} 10139 10140bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 10141 // i16 instructions are longer (0x66 prefix) and potentially slower. 10142 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 10143} 10144 10145/// isShuffleMaskLegal - Targets can use this to indicate that they only 10146/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 10147/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 10148/// are assumed to be legal. 10149bool 10150X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 10151 EVT VT) const { 10152 // Very little shuffling can be done for 64-bit vectors right now. 10153 if (VT.getSizeInBits() == 64) 10154 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()); 10155 10156 // FIXME: pshufb, blends, shifts. 10157 return (VT.getVectorNumElements() == 2 || 10158 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 10159 isMOVLMask(M, VT) || 10160 isSHUFPMask(M, VT) || 10161 isPSHUFDMask(M, VT) || 10162 isPSHUFHWMask(M, VT) || 10163 isPSHUFLWMask(M, VT) || 10164 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 10165 isUNPCKLMask(M, VT) || 10166 isUNPCKHMask(M, VT) || 10167 isUNPCKL_v_undef_Mask(M, VT) || 10168 isUNPCKH_v_undef_Mask(M, VT)); 10169} 10170 10171bool 10172X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 10173 EVT VT) const { 10174 unsigned NumElts = VT.getVectorNumElements(); 10175 // FIXME: This collection of masks seems suspect. 10176 if (NumElts == 2) 10177 return true; 10178 if (NumElts == 4 && VT.getSizeInBits() == 128) { 10179 return (isMOVLMask(Mask, VT) || 10180 isCommutedMOVLMask(Mask, VT, true) || 10181 isSHUFPMask(Mask, VT) || 10182 isCommutedSHUFPMask(Mask, VT)); 10183 } 10184 return false; 10185} 10186 10187//===----------------------------------------------------------------------===// 10188// X86 Scheduler Hooks 10189//===----------------------------------------------------------------------===// 10190 10191// private utility function 10192MachineBasicBlock * 10193X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 10194 MachineBasicBlock *MBB, 10195 unsigned regOpc, 10196 unsigned immOpc, 10197 unsigned LoadOpc, 10198 unsigned CXchgOpc, 10199 unsigned notOpc, 10200 unsigned EAXreg, 10201 TargetRegisterClass *RC, 10202 bool invSrc) const { 10203 // For the atomic bitwise operator, we generate 10204 // thisMBB: 10205 // newMBB: 10206 // ld t1 = [bitinstr.addr] 10207 // op t2 = t1, [bitinstr.val] 10208 // mov EAX = t1 10209 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10210 // bz newMBB 10211 // fallthrough -->nextMBB 10212 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10213 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10214 MachineFunction::iterator MBBIter = MBB; 10215 ++MBBIter; 10216 10217 /// First build the CFG 10218 MachineFunction *F = MBB->getParent(); 10219 MachineBasicBlock *thisMBB = MBB; 10220 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10221 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10222 F->insert(MBBIter, newMBB); 10223 F->insert(MBBIter, nextMBB); 10224 10225 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10226 nextMBB->splice(nextMBB->begin(), thisMBB, 10227 llvm::next(MachineBasicBlock::iterator(bInstr)), 10228 thisMBB->end()); 10229 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10230 10231 // Update thisMBB to fall through to newMBB 10232 thisMBB->addSuccessor(newMBB); 10233 10234 // newMBB jumps to itself and fall through to nextMBB 10235 newMBB->addSuccessor(nextMBB); 10236 newMBB->addSuccessor(newMBB); 10237 10238 // Insert instructions into newMBB based on incoming instruction 10239 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10240 "unexpected number of operands"); 10241 DebugLoc dl = bInstr->getDebugLoc(); 10242 MachineOperand& destOper = bInstr->getOperand(0); 10243 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10244 int numArgs = bInstr->getNumOperands() - 1; 10245 for (int i=0; i < numArgs; ++i) 10246 argOpers[i] = &bInstr->getOperand(i+1); 10247 10248 // x86 address has 4 operands: base, index, scale, and displacement 10249 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10250 int valArgIndx = lastAddrIndx + 1; 10251 10252 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10253 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 10254 for (int i=0; i <= lastAddrIndx; ++i) 10255 (*MIB).addOperand(*argOpers[i]); 10256 10257 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 10258 if (invSrc) { 10259 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 10260 } 10261 else 10262 tt = t1; 10263 10264 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10265 assert((argOpers[valArgIndx]->isReg() || 10266 argOpers[valArgIndx]->isImm()) && 10267 "invalid operand"); 10268 if (argOpers[valArgIndx]->isReg()) 10269 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 10270 else 10271 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 10272 MIB.addReg(tt); 10273 (*MIB).addOperand(*argOpers[valArgIndx]); 10274 10275 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 10276 MIB.addReg(t1); 10277 10278 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 10279 for (int i=0; i <= lastAddrIndx; ++i) 10280 (*MIB).addOperand(*argOpers[i]); 10281 MIB.addReg(t2); 10282 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10283 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10284 bInstr->memoperands_end()); 10285 10286 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10287 MIB.addReg(EAXreg); 10288 10289 // insert branch 10290 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10291 10292 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10293 return nextMBB; 10294} 10295 10296// private utility function: 64 bit atomics on 32 bit host. 10297MachineBasicBlock * 10298X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 10299 MachineBasicBlock *MBB, 10300 unsigned regOpcL, 10301 unsigned regOpcH, 10302 unsigned immOpcL, 10303 unsigned immOpcH, 10304 bool invSrc) const { 10305 // For the atomic bitwise operator, we generate 10306 // thisMBB (instructions are in pairs, except cmpxchg8b) 10307 // ld t1,t2 = [bitinstr.addr] 10308 // newMBB: 10309 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 10310 // op t5, t6 <- out1, out2, [bitinstr.val] 10311 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 10312 // mov ECX, EBX <- t5, t6 10313 // mov EAX, EDX <- t1, t2 10314 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 10315 // mov t3, t4 <- EAX, EDX 10316 // bz newMBB 10317 // result in out1, out2 10318 // fallthrough -->nextMBB 10319 10320 const TargetRegisterClass *RC = X86::GR32RegisterClass; 10321 const unsigned LoadOpc = X86::MOV32rm; 10322 const unsigned NotOpc = X86::NOT32r; 10323 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10324 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10325 MachineFunction::iterator MBBIter = MBB; 10326 ++MBBIter; 10327 10328 /// First build the CFG 10329 MachineFunction *F = MBB->getParent(); 10330 MachineBasicBlock *thisMBB = MBB; 10331 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10332 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10333 F->insert(MBBIter, newMBB); 10334 F->insert(MBBIter, nextMBB); 10335 10336 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10337 nextMBB->splice(nextMBB->begin(), thisMBB, 10338 llvm::next(MachineBasicBlock::iterator(bInstr)), 10339 thisMBB->end()); 10340 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10341 10342 // Update thisMBB to fall through to newMBB 10343 thisMBB->addSuccessor(newMBB); 10344 10345 // newMBB jumps to itself and fall through to nextMBB 10346 newMBB->addSuccessor(nextMBB); 10347 newMBB->addSuccessor(newMBB); 10348 10349 DebugLoc dl = bInstr->getDebugLoc(); 10350 // Insert instructions into newMBB based on incoming instruction 10351 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 10352 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 10353 "unexpected number of operands"); 10354 MachineOperand& dest1Oper = bInstr->getOperand(0); 10355 MachineOperand& dest2Oper = bInstr->getOperand(1); 10356 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10357 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 10358 argOpers[i] = &bInstr->getOperand(i+2); 10359 10360 // We use some of the operands multiple times, so conservatively just 10361 // clear any kill flags that might be present. 10362 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 10363 argOpers[i]->setIsKill(false); 10364 } 10365 10366 // x86 address has 5 operands: base, index, scale, displacement, and segment. 10367 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10368 10369 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10370 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 10371 for (int i=0; i <= lastAddrIndx; ++i) 10372 (*MIB).addOperand(*argOpers[i]); 10373 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10374 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 10375 // add 4 to displacement. 10376 for (int i=0; i <= lastAddrIndx-2; ++i) 10377 (*MIB).addOperand(*argOpers[i]); 10378 MachineOperand newOp3 = *(argOpers[3]); 10379 if (newOp3.isImm()) 10380 newOp3.setImm(newOp3.getImm()+4); 10381 else 10382 newOp3.setOffset(newOp3.getOffset()+4); 10383 (*MIB).addOperand(newOp3); 10384 (*MIB).addOperand(*argOpers[lastAddrIndx]); 10385 10386 // t3/4 are defined later, at the bottom of the loop 10387 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 10388 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 10389 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 10390 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 10391 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 10392 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 10393 10394 // The subsequent operations should be using the destination registers of 10395 //the PHI instructions. 10396 if (invSrc) { 10397 t1 = F->getRegInfo().createVirtualRegister(RC); 10398 t2 = F->getRegInfo().createVirtualRegister(RC); 10399 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 10400 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 10401 } else { 10402 t1 = dest1Oper.getReg(); 10403 t2 = dest2Oper.getReg(); 10404 } 10405 10406 int valArgIndx = lastAddrIndx + 1; 10407 assert((argOpers[valArgIndx]->isReg() || 10408 argOpers[valArgIndx]->isImm()) && 10409 "invalid operand"); 10410 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 10411 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 10412 if (argOpers[valArgIndx]->isReg()) 10413 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 10414 else 10415 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 10416 if (regOpcL != X86::MOV32rr) 10417 MIB.addReg(t1); 10418 (*MIB).addOperand(*argOpers[valArgIndx]); 10419 assert(argOpers[valArgIndx + 1]->isReg() == 10420 argOpers[valArgIndx]->isReg()); 10421 assert(argOpers[valArgIndx + 1]->isImm() == 10422 argOpers[valArgIndx]->isImm()); 10423 if (argOpers[valArgIndx + 1]->isReg()) 10424 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 10425 else 10426 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 10427 if (regOpcH != X86::MOV32rr) 10428 MIB.addReg(t2); 10429 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 10430 10431 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 10432 MIB.addReg(t1); 10433 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 10434 MIB.addReg(t2); 10435 10436 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 10437 MIB.addReg(t5); 10438 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 10439 MIB.addReg(t6); 10440 10441 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 10442 for (int i=0; i <= lastAddrIndx; ++i) 10443 (*MIB).addOperand(*argOpers[i]); 10444 10445 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10446 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10447 bInstr->memoperands_end()); 10448 10449 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 10450 MIB.addReg(X86::EAX); 10451 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 10452 MIB.addReg(X86::EDX); 10453 10454 // insert branch 10455 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10456 10457 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10458 return nextMBB; 10459} 10460 10461// private utility function 10462MachineBasicBlock * 10463X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 10464 MachineBasicBlock *MBB, 10465 unsigned cmovOpc) const { 10466 // For the atomic min/max operator, we generate 10467 // thisMBB: 10468 // newMBB: 10469 // ld t1 = [min/max.addr] 10470 // mov t2 = [min/max.val] 10471 // cmp t1, t2 10472 // cmov[cond] t2 = t1 10473 // mov EAX = t1 10474 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10475 // bz newMBB 10476 // fallthrough -->nextMBB 10477 // 10478 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10479 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10480 MachineFunction::iterator MBBIter = MBB; 10481 ++MBBIter; 10482 10483 /// First build the CFG 10484 MachineFunction *F = MBB->getParent(); 10485 MachineBasicBlock *thisMBB = MBB; 10486 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10487 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10488 F->insert(MBBIter, newMBB); 10489 F->insert(MBBIter, nextMBB); 10490 10491 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10492 nextMBB->splice(nextMBB->begin(), thisMBB, 10493 llvm::next(MachineBasicBlock::iterator(mInstr)), 10494 thisMBB->end()); 10495 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10496 10497 // Update thisMBB to fall through to newMBB 10498 thisMBB->addSuccessor(newMBB); 10499 10500 // newMBB jumps to newMBB and fall through to nextMBB 10501 newMBB->addSuccessor(nextMBB); 10502 newMBB->addSuccessor(newMBB); 10503 10504 DebugLoc dl = mInstr->getDebugLoc(); 10505 // Insert instructions into newMBB based on incoming instruction 10506 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10507 "unexpected number of operands"); 10508 MachineOperand& destOper = mInstr->getOperand(0); 10509 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10510 int numArgs = mInstr->getNumOperands() - 1; 10511 for (int i=0; i < numArgs; ++i) 10512 argOpers[i] = &mInstr->getOperand(i+1); 10513 10514 // x86 address has 4 operands: base, index, scale, and displacement 10515 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10516 int valArgIndx = lastAddrIndx + 1; 10517 10518 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 10519 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 10520 for (int i=0; i <= lastAddrIndx; ++i) 10521 (*MIB).addOperand(*argOpers[i]); 10522 10523 // We only support register and immediate values 10524 assert((argOpers[valArgIndx]->isReg() || 10525 argOpers[valArgIndx]->isImm()) && 10526 "invalid operand"); 10527 10528 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 10529 if (argOpers[valArgIndx]->isReg()) 10530 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 10531 else 10532 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 10533 (*MIB).addOperand(*argOpers[valArgIndx]); 10534 10535 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 10536 MIB.addReg(t1); 10537 10538 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 10539 MIB.addReg(t1); 10540 MIB.addReg(t2); 10541 10542 // Generate movc 10543 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 10544 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 10545 MIB.addReg(t2); 10546 MIB.addReg(t1); 10547 10548 // Cmp and exchange if none has modified the memory location 10549 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 10550 for (int i=0; i <= lastAddrIndx; ++i) 10551 (*MIB).addOperand(*argOpers[i]); 10552 MIB.addReg(t3); 10553 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10554 (*MIB).setMemRefs(mInstr->memoperands_begin(), 10555 mInstr->memoperands_end()); 10556 10557 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10558 MIB.addReg(X86::EAX); 10559 10560 // insert branch 10561 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10562 10563 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 10564 return nextMBB; 10565} 10566 10567// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 10568// or XMM0_V32I8 in AVX all of this code can be replaced with that 10569// in the .td file. 10570MachineBasicBlock * 10571X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 10572 unsigned numArgs, bool memArg) const { 10573 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 10574 "Target must have SSE4.2 or AVX features enabled"); 10575 10576 DebugLoc dl = MI->getDebugLoc(); 10577 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10578 unsigned Opc; 10579 if (!Subtarget->hasAVX()) { 10580 if (memArg) 10581 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 10582 else 10583 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 10584 } else { 10585 if (memArg) 10586 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 10587 else 10588 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 10589 } 10590 10591 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 10592 for (unsigned i = 0; i < numArgs; ++i) { 10593 MachineOperand &Op = MI->getOperand(i+1); 10594 if (!(Op.isReg() && Op.isImplicit())) 10595 MIB.addOperand(Op); 10596 } 10597 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 10598 .addReg(X86::XMM0); 10599 10600 MI->eraseFromParent(); 10601 return BB; 10602} 10603 10604MachineBasicBlock * 10605X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 10606 DebugLoc dl = MI->getDebugLoc(); 10607 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10608 10609 // Address into RAX/EAX, other two args into ECX, EDX. 10610 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 10611 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 10612 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 10613 for (int i = 0; i < X86::AddrNumOperands; ++i) 10614 MIB.addOperand(MI->getOperand(i)); 10615 10616 unsigned ValOps = X86::AddrNumOperands; 10617 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 10618 .addReg(MI->getOperand(ValOps).getReg()); 10619 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 10620 .addReg(MI->getOperand(ValOps+1).getReg()); 10621 10622 // The instruction doesn't actually take any operands though. 10623 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 10624 10625 MI->eraseFromParent(); // The pseudo is gone now. 10626 return BB; 10627} 10628 10629MachineBasicBlock * 10630X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 10631 DebugLoc dl = MI->getDebugLoc(); 10632 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10633 10634 // First arg in ECX, the second in EAX. 10635 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 10636 .addReg(MI->getOperand(0).getReg()); 10637 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 10638 .addReg(MI->getOperand(1).getReg()); 10639 10640 // The instruction doesn't actually take any operands though. 10641 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 10642 10643 MI->eraseFromParent(); // The pseudo is gone now. 10644 return BB; 10645} 10646 10647MachineBasicBlock * 10648X86TargetLowering::EmitVAARG64WithCustomInserter( 10649 MachineInstr *MI, 10650 MachineBasicBlock *MBB) const { 10651 // Emit va_arg instruction on X86-64. 10652 10653 // Operands to this pseudo-instruction: 10654 // 0 ) Output : destination address (reg) 10655 // 1-5) Input : va_list address (addr, i64mem) 10656 // 6 ) ArgSize : Size (in bytes) of vararg type 10657 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 10658 // 8 ) Align : Alignment of type 10659 // 9 ) EFLAGS (implicit-def) 10660 10661 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 10662 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 10663 10664 unsigned DestReg = MI->getOperand(0).getReg(); 10665 MachineOperand &Base = MI->getOperand(1); 10666 MachineOperand &Scale = MI->getOperand(2); 10667 MachineOperand &Index = MI->getOperand(3); 10668 MachineOperand &Disp = MI->getOperand(4); 10669 MachineOperand &Segment = MI->getOperand(5); 10670 unsigned ArgSize = MI->getOperand(6).getImm(); 10671 unsigned ArgMode = MI->getOperand(7).getImm(); 10672 unsigned Align = MI->getOperand(8).getImm(); 10673 10674 // Memory Reference 10675 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 10676 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 10677 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 10678 10679 // Machine Information 10680 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10681 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 10682 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 10683 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 10684 DebugLoc DL = MI->getDebugLoc(); 10685 10686 // struct va_list { 10687 // i32 gp_offset 10688 // i32 fp_offset 10689 // i64 overflow_area (address) 10690 // i64 reg_save_area (address) 10691 // } 10692 // sizeof(va_list) = 24 10693 // alignment(va_list) = 8 10694 10695 unsigned TotalNumIntRegs = 6; 10696 unsigned TotalNumXMMRegs = 8; 10697 bool UseGPOffset = (ArgMode == 1); 10698 bool UseFPOffset = (ArgMode == 2); 10699 unsigned MaxOffset = TotalNumIntRegs * 8 + 10700 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 10701 10702 /* Align ArgSize to a multiple of 8 */ 10703 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 10704 bool NeedsAlign = (Align > 8); 10705 10706 MachineBasicBlock *thisMBB = MBB; 10707 MachineBasicBlock *overflowMBB; 10708 MachineBasicBlock *offsetMBB; 10709 MachineBasicBlock *endMBB; 10710 10711 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 10712 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 10713 unsigned OffsetReg = 0; 10714 10715 if (!UseGPOffset && !UseFPOffset) { 10716 // If we only pull from the overflow region, we don't create a branch. 10717 // We don't need to alter control flow. 10718 OffsetDestReg = 0; // unused 10719 OverflowDestReg = DestReg; 10720 10721 offsetMBB = NULL; 10722 overflowMBB = thisMBB; 10723 endMBB = thisMBB; 10724 } else { 10725 // First emit code to check if gp_offset (or fp_offset) is below the bound. 10726 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 10727 // If not, pull from overflow_area. (branch to overflowMBB) 10728 // 10729 // thisMBB 10730 // | . 10731 // | . 10732 // offsetMBB overflowMBB 10733 // | . 10734 // | . 10735 // endMBB 10736 10737 // Registers for the PHI in endMBB 10738 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 10739 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 10740 10741 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10742 MachineFunction *MF = MBB->getParent(); 10743 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10744 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10745 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 10746 10747 MachineFunction::iterator MBBIter = MBB; 10748 ++MBBIter; 10749 10750 // Insert the new basic blocks 10751 MF->insert(MBBIter, offsetMBB); 10752 MF->insert(MBBIter, overflowMBB); 10753 MF->insert(MBBIter, endMBB); 10754 10755 // Transfer the remainder of MBB and its successor edges to endMBB. 10756 endMBB->splice(endMBB->begin(), thisMBB, 10757 llvm::next(MachineBasicBlock::iterator(MI)), 10758 thisMBB->end()); 10759 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10760 10761 // Make offsetMBB and overflowMBB successors of thisMBB 10762 thisMBB->addSuccessor(offsetMBB); 10763 thisMBB->addSuccessor(overflowMBB); 10764 10765 // endMBB is a successor of both offsetMBB and overflowMBB 10766 offsetMBB->addSuccessor(endMBB); 10767 overflowMBB->addSuccessor(endMBB); 10768 10769 // Load the offset value into a register 10770 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 10771 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 10772 .addOperand(Base) 10773 .addOperand(Scale) 10774 .addOperand(Index) 10775 .addDisp(Disp, UseFPOffset ? 4 : 0) 10776 .addOperand(Segment) 10777 .setMemRefs(MMOBegin, MMOEnd); 10778 10779 // Check if there is enough room left to pull this argument. 10780 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 10781 .addReg(OffsetReg) 10782 .addImm(MaxOffset + 8 - ArgSizeA8); 10783 10784 // Branch to "overflowMBB" if offset >= max 10785 // Fall through to "offsetMBB" otherwise 10786 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 10787 .addMBB(overflowMBB); 10788 } 10789 10790 // In offsetMBB, emit code to use the reg_save_area. 10791 if (offsetMBB) { 10792 assert(OffsetReg != 0); 10793 10794 // Read the reg_save_area address. 10795 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 10796 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 10797 .addOperand(Base) 10798 .addOperand(Scale) 10799 .addOperand(Index) 10800 .addDisp(Disp, 16) 10801 .addOperand(Segment) 10802 .setMemRefs(MMOBegin, MMOEnd); 10803 10804 // Zero-extend the offset 10805 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 10806 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 10807 .addImm(0) 10808 .addReg(OffsetReg) 10809 .addImm(X86::sub_32bit); 10810 10811 // Add the offset to the reg_save_area to get the final address. 10812 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 10813 .addReg(OffsetReg64) 10814 .addReg(RegSaveReg); 10815 10816 // Compute the offset for the next argument 10817 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 10818 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 10819 .addReg(OffsetReg) 10820 .addImm(UseFPOffset ? 16 : 8); 10821 10822 // Store it back into the va_list. 10823 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 10824 .addOperand(Base) 10825 .addOperand(Scale) 10826 .addOperand(Index) 10827 .addDisp(Disp, UseFPOffset ? 4 : 0) 10828 .addOperand(Segment) 10829 .addReg(NextOffsetReg) 10830 .setMemRefs(MMOBegin, MMOEnd); 10831 10832 // Jump to endMBB 10833 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 10834 .addMBB(endMBB); 10835 } 10836 10837 // 10838 // Emit code to use overflow area 10839 // 10840 10841 // Load the overflow_area address into a register. 10842 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 10843 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 10844 .addOperand(Base) 10845 .addOperand(Scale) 10846 .addOperand(Index) 10847 .addDisp(Disp, 8) 10848 .addOperand(Segment) 10849 .setMemRefs(MMOBegin, MMOEnd); 10850 10851 // If we need to align it, do so. Otherwise, just copy the address 10852 // to OverflowDestReg. 10853 if (NeedsAlign) { 10854 // Align the overflow address 10855 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 10856 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 10857 10858 // aligned_addr = (addr + (align-1)) & ~(align-1) 10859 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 10860 .addReg(OverflowAddrReg) 10861 .addImm(Align-1); 10862 10863 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 10864 .addReg(TmpReg) 10865 .addImm(~(uint64_t)(Align-1)); 10866 } else { 10867 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 10868 .addReg(OverflowAddrReg); 10869 } 10870 10871 // Compute the next overflow address after this argument. 10872 // (the overflow address should be kept 8-byte aligned) 10873 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 10874 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 10875 .addReg(OverflowDestReg) 10876 .addImm(ArgSizeA8); 10877 10878 // Store the new overflow address. 10879 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 10880 .addOperand(Base) 10881 .addOperand(Scale) 10882 .addOperand(Index) 10883 .addDisp(Disp, 8) 10884 .addOperand(Segment) 10885 .addReg(NextAddrReg) 10886 .setMemRefs(MMOBegin, MMOEnd); 10887 10888 // If we branched, emit the PHI to the front of endMBB. 10889 if (offsetMBB) { 10890 BuildMI(*endMBB, endMBB->begin(), DL, 10891 TII->get(X86::PHI), DestReg) 10892 .addReg(OffsetDestReg).addMBB(offsetMBB) 10893 .addReg(OverflowDestReg).addMBB(overflowMBB); 10894 } 10895 10896 // Erase the pseudo instruction 10897 MI->eraseFromParent(); 10898 10899 return endMBB; 10900} 10901 10902MachineBasicBlock * 10903X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 10904 MachineInstr *MI, 10905 MachineBasicBlock *MBB) const { 10906 // Emit code to save XMM registers to the stack. The ABI says that the 10907 // number of registers to save is given in %al, so it's theoretically 10908 // possible to do an indirect jump trick to avoid saving all of them, 10909 // however this code takes a simpler approach and just executes all 10910 // of the stores if %al is non-zero. It's less code, and it's probably 10911 // easier on the hardware branch predictor, and stores aren't all that 10912 // expensive anyway. 10913 10914 // Create the new basic blocks. One block contains all the XMM stores, 10915 // and one block is the final destination regardless of whether any 10916 // stores were performed. 10917 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10918 MachineFunction *F = MBB->getParent(); 10919 MachineFunction::iterator MBBIter = MBB; 10920 ++MBBIter; 10921 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 10922 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 10923 F->insert(MBBIter, XMMSaveMBB); 10924 F->insert(MBBIter, EndMBB); 10925 10926 // Transfer the remainder of MBB and its successor edges to EndMBB. 10927 EndMBB->splice(EndMBB->begin(), MBB, 10928 llvm::next(MachineBasicBlock::iterator(MI)), 10929 MBB->end()); 10930 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 10931 10932 // The original block will now fall through to the XMM save block. 10933 MBB->addSuccessor(XMMSaveMBB); 10934 // The XMMSaveMBB will fall through to the end block. 10935 XMMSaveMBB->addSuccessor(EndMBB); 10936 10937 // Now add the instructions. 10938 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10939 DebugLoc DL = MI->getDebugLoc(); 10940 10941 unsigned CountReg = MI->getOperand(0).getReg(); 10942 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 10943 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 10944 10945 if (!Subtarget->isTargetWin64()) { 10946 // If %al is 0, branch around the XMM save block. 10947 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 10948 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 10949 MBB->addSuccessor(EndMBB); 10950 } 10951 10952 // In the XMM save block, save all the XMM argument registers. 10953 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 10954 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 10955 MachineMemOperand *MMO = 10956 F->getMachineMemOperand( 10957 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 10958 MachineMemOperand::MOStore, 10959 /*Size=*/16, /*Align=*/16); 10960 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 10961 .addFrameIndex(RegSaveFrameIndex) 10962 .addImm(/*Scale=*/1) 10963 .addReg(/*IndexReg=*/0) 10964 .addImm(/*Disp=*/Offset) 10965 .addReg(/*Segment=*/0) 10966 .addReg(MI->getOperand(i).getReg()) 10967 .addMemOperand(MMO); 10968 } 10969 10970 MI->eraseFromParent(); // The pseudo instruction is gone now. 10971 10972 return EndMBB; 10973} 10974 10975MachineBasicBlock * 10976X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 10977 MachineBasicBlock *BB) const { 10978 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10979 DebugLoc DL = MI->getDebugLoc(); 10980 10981 // To "insert" a SELECT_CC instruction, we actually have to insert the 10982 // diamond control-flow pattern. The incoming instruction knows the 10983 // destination vreg to set, the condition code register to branch on, the 10984 // true/false values to select between, and a branch opcode to use. 10985 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 10986 MachineFunction::iterator It = BB; 10987 ++It; 10988 10989 // thisMBB: 10990 // ... 10991 // TrueVal = ... 10992 // cmpTY ccX, r1, r2 10993 // bCC copy1MBB 10994 // fallthrough --> copy0MBB 10995 MachineBasicBlock *thisMBB = BB; 10996 MachineFunction *F = BB->getParent(); 10997 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 10998 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 10999 F->insert(It, copy0MBB); 11000 F->insert(It, sinkMBB); 11001 11002 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11003 // live into the sink and copy blocks. 11004 const MachineFunction *MF = BB->getParent(); 11005 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 11006 BitVector ReservedRegs = TRI->getReservedRegs(*MF); 11007 11008 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 11009 const MachineOperand &MO = MI->getOperand(I); 11010 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue; 11011 unsigned Reg = MO.getReg(); 11012 if (Reg != X86::EFLAGS) continue; 11013 copy0MBB->addLiveIn(Reg); 11014 sinkMBB->addLiveIn(Reg); 11015 } 11016 11017 // Transfer the remainder of BB and its successor edges to sinkMBB. 11018 sinkMBB->splice(sinkMBB->begin(), BB, 11019 llvm::next(MachineBasicBlock::iterator(MI)), 11020 BB->end()); 11021 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11022 11023 // Add the true and fallthrough blocks as its successors. 11024 BB->addSuccessor(copy0MBB); 11025 BB->addSuccessor(sinkMBB); 11026 11027 // Create the conditional branch instruction. 11028 unsigned Opc = 11029 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11030 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11031 11032 // copy0MBB: 11033 // %FalseValue = ... 11034 // # fallthrough to sinkMBB 11035 copy0MBB->addSuccessor(sinkMBB); 11036 11037 // sinkMBB: 11038 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11039 // ... 11040 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11041 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11042 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11043 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11044 11045 MI->eraseFromParent(); // The pseudo instruction is gone now. 11046 return sinkMBB; 11047} 11048 11049MachineBasicBlock * 11050X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 11051 MachineBasicBlock *BB) const { 11052 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11053 DebugLoc DL = MI->getDebugLoc(); 11054 11055 assert(!Subtarget->isTargetEnvMacho()); 11056 11057 // The lowering is pretty easy: we're just emitting the call to _alloca. The 11058 // non-trivial part is impdef of ESP. 11059 11060 if (Subtarget->isTargetWin64()) { 11061 if (Subtarget->isTargetCygMing()) { 11062 // ___chkstk(Mingw64): 11063 // Clobbers R10, R11, RAX and EFLAGS. 11064 // Updates RSP. 11065 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11066 .addExternalSymbol("___chkstk") 11067 .addReg(X86::RAX, RegState::Implicit) 11068 .addReg(X86::RSP, RegState::Implicit) 11069 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 11070 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 11071 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11072 } else { 11073 // __chkstk(MSVCRT): does not update stack pointer. 11074 // Clobbers R10, R11 and EFLAGS. 11075 // FIXME: RAX(allocated size) might be reused and not killed. 11076 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11077 .addExternalSymbol("__chkstk") 11078 .addReg(X86::RAX, RegState::Implicit) 11079 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11080 // RAX has the offset to subtracted from RSP. 11081 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 11082 .addReg(X86::RSP) 11083 .addReg(X86::RAX); 11084 } 11085 } else { 11086 const char *StackProbeSymbol = 11087 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 11088 11089 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 11090 .addExternalSymbol(StackProbeSymbol) 11091 .addReg(X86::EAX, RegState::Implicit) 11092 .addReg(X86::ESP, RegState::Implicit) 11093 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 11094 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 11095 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11096 } 11097 11098 MI->eraseFromParent(); // The pseudo instruction is gone now. 11099 return BB; 11100} 11101 11102MachineBasicBlock * 11103X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 11104 MachineBasicBlock *BB) const { 11105 // This is pretty easy. We're taking the value that we received from 11106 // our load from the relocation, sticking it in either RDI (x86-64) 11107 // or EAX and doing an indirect call. The return value will then 11108 // be in the normal return register. 11109 const X86InstrInfo *TII 11110 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 11111 DebugLoc DL = MI->getDebugLoc(); 11112 MachineFunction *F = BB->getParent(); 11113 11114 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 11115 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 11116 11117 if (Subtarget->is64Bit()) { 11118 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11119 TII->get(X86::MOV64rm), X86::RDI) 11120 .addReg(X86::RIP) 11121 .addImm(0).addReg(0) 11122 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11123 MI->getOperand(3).getTargetFlags()) 11124 .addReg(0); 11125 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 11126 addDirectMem(MIB, X86::RDI); 11127 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 11128 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11129 TII->get(X86::MOV32rm), X86::EAX) 11130 .addReg(0) 11131 .addImm(0).addReg(0) 11132 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11133 MI->getOperand(3).getTargetFlags()) 11134 .addReg(0); 11135 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11136 addDirectMem(MIB, X86::EAX); 11137 } else { 11138 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11139 TII->get(X86::MOV32rm), X86::EAX) 11140 .addReg(TII->getGlobalBaseReg(F)) 11141 .addImm(0).addReg(0) 11142 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11143 MI->getOperand(3).getTargetFlags()) 11144 .addReg(0); 11145 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11146 addDirectMem(MIB, X86::EAX); 11147 } 11148 11149 MI->eraseFromParent(); // The pseudo instruction is gone now. 11150 return BB; 11151} 11152 11153MachineBasicBlock * 11154X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 11155 MachineBasicBlock *BB) const { 11156 switch (MI->getOpcode()) { 11157 default: assert(false && "Unexpected instr type to insert"); 11158 case X86::TAILJMPd64: 11159 case X86::TAILJMPr64: 11160 case X86::TAILJMPm64: 11161 assert(!"TAILJMP64 would not be touched here."); 11162 case X86::TCRETURNdi64: 11163 case X86::TCRETURNri64: 11164 case X86::TCRETURNmi64: 11165 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 11166 // On AMD64, additional defs should be added before register allocation. 11167 if (!Subtarget->isTargetWin64()) { 11168 MI->addRegisterDefined(X86::RSI); 11169 MI->addRegisterDefined(X86::RDI); 11170 MI->addRegisterDefined(X86::XMM6); 11171 MI->addRegisterDefined(X86::XMM7); 11172 MI->addRegisterDefined(X86::XMM8); 11173 MI->addRegisterDefined(X86::XMM9); 11174 MI->addRegisterDefined(X86::XMM10); 11175 MI->addRegisterDefined(X86::XMM11); 11176 MI->addRegisterDefined(X86::XMM12); 11177 MI->addRegisterDefined(X86::XMM13); 11178 MI->addRegisterDefined(X86::XMM14); 11179 MI->addRegisterDefined(X86::XMM15); 11180 } 11181 return BB; 11182 case X86::WIN_ALLOCA: 11183 return EmitLoweredWinAlloca(MI, BB); 11184 case X86::TLSCall_32: 11185 case X86::TLSCall_64: 11186 return EmitLoweredTLSCall(MI, BB); 11187 case X86::CMOV_GR8: 11188 case X86::CMOV_FR32: 11189 case X86::CMOV_FR64: 11190 case X86::CMOV_V4F32: 11191 case X86::CMOV_V2F64: 11192 case X86::CMOV_V2I64: 11193 case X86::CMOV_V8F32: 11194 case X86::CMOV_V4F64: 11195 case X86::CMOV_V4I64: 11196 case X86::CMOV_GR16: 11197 case X86::CMOV_GR32: 11198 case X86::CMOV_RFP32: 11199 case X86::CMOV_RFP64: 11200 case X86::CMOV_RFP80: 11201 return EmitLoweredSelect(MI, BB); 11202 11203 case X86::FP32_TO_INT16_IN_MEM: 11204 case X86::FP32_TO_INT32_IN_MEM: 11205 case X86::FP32_TO_INT64_IN_MEM: 11206 case X86::FP64_TO_INT16_IN_MEM: 11207 case X86::FP64_TO_INT32_IN_MEM: 11208 case X86::FP64_TO_INT64_IN_MEM: 11209 case X86::FP80_TO_INT16_IN_MEM: 11210 case X86::FP80_TO_INT32_IN_MEM: 11211 case X86::FP80_TO_INT64_IN_MEM: { 11212 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11213 DebugLoc DL = MI->getDebugLoc(); 11214 11215 // Change the floating point control register to use "round towards zero" 11216 // mode when truncating to an integer value. 11217 MachineFunction *F = BB->getParent(); 11218 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 11219 addFrameReference(BuildMI(*BB, MI, DL, 11220 TII->get(X86::FNSTCW16m)), CWFrameIdx); 11221 11222 // Load the old value of the high byte of the control word... 11223 unsigned OldCW = 11224 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 11225 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 11226 CWFrameIdx); 11227 11228 // Set the high part to be round to zero... 11229 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 11230 .addImm(0xC7F); 11231 11232 // Reload the modified control word now... 11233 addFrameReference(BuildMI(*BB, MI, DL, 11234 TII->get(X86::FLDCW16m)), CWFrameIdx); 11235 11236 // Restore the memory image of control word to original value 11237 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 11238 .addReg(OldCW); 11239 11240 // Get the X86 opcode to use. 11241 unsigned Opc; 11242 switch (MI->getOpcode()) { 11243 default: llvm_unreachable("illegal opcode!"); 11244 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 11245 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 11246 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 11247 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 11248 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 11249 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 11250 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 11251 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 11252 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 11253 } 11254 11255 X86AddressMode AM; 11256 MachineOperand &Op = MI->getOperand(0); 11257 if (Op.isReg()) { 11258 AM.BaseType = X86AddressMode::RegBase; 11259 AM.Base.Reg = Op.getReg(); 11260 } else { 11261 AM.BaseType = X86AddressMode::FrameIndexBase; 11262 AM.Base.FrameIndex = Op.getIndex(); 11263 } 11264 Op = MI->getOperand(1); 11265 if (Op.isImm()) 11266 AM.Scale = Op.getImm(); 11267 Op = MI->getOperand(2); 11268 if (Op.isImm()) 11269 AM.IndexReg = Op.getImm(); 11270 Op = MI->getOperand(3); 11271 if (Op.isGlobal()) { 11272 AM.GV = Op.getGlobal(); 11273 } else { 11274 AM.Disp = Op.getImm(); 11275 } 11276 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 11277 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 11278 11279 // Reload the original control word now. 11280 addFrameReference(BuildMI(*BB, MI, DL, 11281 TII->get(X86::FLDCW16m)), CWFrameIdx); 11282 11283 MI->eraseFromParent(); // The pseudo instruction is gone now. 11284 return BB; 11285 } 11286 // String/text processing lowering. 11287 case X86::PCMPISTRM128REG: 11288 case X86::VPCMPISTRM128REG: 11289 return EmitPCMP(MI, BB, 3, false /* in-mem */); 11290 case X86::PCMPISTRM128MEM: 11291 case X86::VPCMPISTRM128MEM: 11292 return EmitPCMP(MI, BB, 3, true /* in-mem */); 11293 case X86::PCMPESTRM128REG: 11294 case X86::VPCMPESTRM128REG: 11295 return EmitPCMP(MI, BB, 5, false /* in mem */); 11296 case X86::PCMPESTRM128MEM: 11297 case X86::VPCMPESTRM128MEM: 11298 return EmitPCMP(MI, BB, 5, true /* in mem */); 11299 11300 // Thread synchronization. 11301 case X86::MONITOR: 11302 return EmitMonitor(MI, BB); 11303 case X86::MWAIT: 11304 return EmitMwait(MI, BB); 11305 11306 // Atomic Lowering. 11307 case X86::ATOMAND32: 11308 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 11309 X86::AND32ri, X86::MOV32rm, 11310 X86::LCMPXCHG32, 11311 X86::NOT32r, X86::EAX, 11312 X86::GR32RegisterClass); 11313 case X86::ATOMOR32: 11314 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 11315 X86::OR32ri, X86::MOV32rm, 11316 X86::LCMPXCHG32, 11317 X86::NOT32r, X86::EAX, 11318 X86::GR32RegisterClass); 11319 case X86::ATOMXOR32: 11320 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 11321 X86::XOR32ri, X86::MOV32rm, 11322 X86::LCMPXCHG32, 11323 X86::NOT32r, X86::EAX, 11324 X86::GR32RegisterClass); 11325 case X86::ATOMNAND32: 11326 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 11327 X86::AND32ri, X86::MOV32rm, 11328 X86::LCMPXCHG32, 11329 X86::NOT32r, X86::EAX, 11330 X86::GR32RegisterClass, true); 11331 case X86::ATOMMIN32: 11332 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 11333 case X86::ATOMMAX32: 11334 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 11335 case X86::ATOMUMIN32: 11336 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 11337 case X86::ATOMUMAX32: 11338 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 11339 11340 case X86::ATOMAND16: 11341 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 11342 X86::AND16ri, X86::MOV16rm, 11343 X86::LCMPXCHG16, 11344 X86::NOT16r, X86::AX, 11345 X86::GR16RegisterClass); 11346 case X86::ATOMOR16: 11347 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 11348 X86::OR16ri, X86::MOV16rm, 11349 X86::LCMPXCHG16, 11350 X86::NOT16r, X86::AX, 11351 X86::GR16RegisterClass); 11352 case X86::ATOMXOR16: 11353 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 11354 X86::XOR16ri, X86::MOV16rm, 11355 X86::LCMPXCHG16, 11356 X86::NOT16r, X86::AX, 11357 X86::GR16RegisterClass); 11358 case X86::ATOMNAND16: 11359 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 11360 X86::AND16ri, X86::MOV16rm, 11361 X86::LCMPXCHG16, 11362 X86::NOT16r, X86::AX, 11363 X86::GR16RegisterClass, true); 11364 case X86::ATOMMIN16: 11365 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 11366 case X86::ATOMMAX16: 11367 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 11368 case X86::ATOMUMIN16: 11369 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 11370 case X86::ATOMUMAX16: 11371 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 11372 11373 case X86::ATOMAND8: 11374 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 11375 X86::AND8ri, X86::MOV8rm, 11376 X86::LCMPXCHG8, 11377 X86::NOT8r, X86::AL, 11378 X86::GR8RegisterClass); 11379 case X86::ATOMOR8: 11380 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 11381 X86::OR8ri, X86::MOV8rm, 11382 X86::LCMPXCHG8, 11383 X86::NOT8r, X86::AL, 11384 X86::GR8RegisterClass); 11385 case X86::ATOMXOR8: 11386 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 11387 X86::XOR8ri, X86::MOV8rm, 11388 X86::LCMPXCHG8, 11389 X86::NOT8r, X86::AL, 11390 X86::GR8RegisterClass); 11391 case X86::ATOMNAND8: 11392 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 11393 X86::AND8ri, X86::MOV8rm, 11394 X86::LCMPXCHG8, 11395 X86::NOT8r, X86::AL, 11396 X86::GR8RegisterClass, true); 11397 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 11398 // This group is for 64-bit host. 11399 case X86::ATOMAND64: 11400 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 11401 X86::AND64ri32, X86::MOV64rm, 11402 X86::LCMPXCHG64, 11403 X86::NOT64r, X86::RAX, 11404 X86::GR64RegisterClass); 11405 case X86::ATOMOR64: 11406 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 11407 X86::OR64ri32, X86::MOV64rm, 11408 X86::LCMPXCHG64, 11409 X86::NOT64r, X86::RAX, 11410 X86::GR64RegisterClass); 11411 case X86::ATOMXOR64: 11412 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 11413 X86::XOR64ri32, X86::MOV64rm, 11414 X86::LCMPXCHG64, 11415 X86::NOT64r, X86::RAX, 11416 X86::GR64RegisterClass); 11417 case X86::ATOMNAND64: 11418 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 11419 X86::AND64ri32, X86::MOV64rm, 11420 X86::LCMPXCHG64, 11421 X86::NOT64r, X86::RAX, 11422 X86::GR64RegisterClass, true); 11423 case X86::ATOMMIN64: 11424 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 11425 case X86::ATOMMAX64: 11426 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 11427 case X86::ATOMUMIN64: 11428 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 11429 case X86::ATOMUMAX64: 11430 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 11431 11432 // This group does 64-bit operations on a 32-bit host. 11433 case X86::ATOMAND6432: 11434 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11435 X86::AND32rr, X86::AND32rr, 11436 X86::AND32ri, X86::AND32ri, 11437 false); 11438 case X86::ATOMOR6432: 11439 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11440 X86::OR32rr, X86::OR32rr, 11441 X86::OR32ri, X86::OR32ri, 11442 false); 11443 case X86::ATOMXOR6432: 11444 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11445 X86::XOR32rr, X86::XOR32rr, 11446 X86::XOR32ri, X86::XOR32ri, 11447 false); 11448 case X86::ATOMNAND6432: 11449 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11450 X86::AND32rr, X86::AND32rr, 11451 X86::AND32ri, X86::AND32ri, 11452 true); 11453 case X86::ATOMADD6432: 11454 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11455 X86::ADD32rr, X86::ADC32rr, 11456 X86::ADD32ri, X86::ADC32ri, 11457 false); 11458 case X86::ATOMSUB6432: 11459 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11460 X86::SUB32rr, X86::SBB32rr, 11461 X86::SUB32ri, X86::SBB32ri, 11462 false); 11463 case X86::ATOMSWAP6432: 11464 return EmitAtomicBit6432WithCustomInserter(MI, BB, 11465 X86::MOV32rr, X86::MOV32rr, 11466 X86::MOV32ri, X86::MOV32ri, 11467 false); 11468 case X86::VASTART_SAVE_XMM_REGS: 11469 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 11470 11471 case X86::VAARG_64: 11472 return EmitVAARG64WithCustomInserter(MI, BB); 11473 } 11474} 11475 11476//===----------------------------------------------------------------------===// 11477// X86 Optimization Hooks 11478//===----------------------------------------------------------------------===// 11479 11480void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 11481 const APInt &Mask, 11482 APInt &KnownZero, 11483 APInt &KnownOne, 11484 const SelectionDAG &DAG, 11485 unsigned Depth) const { 11486 unsigned Opc = Op.getOpcode(); 11487 assert((Opc >= ISD::BUILTIN_OP_END || 11488 Opc == ISD::INTRINSIC_WO_CHAIN || 11489 Opc == ISD::INTRINSIC_W_CHAIN || 11490 Opc == ISD::INTRINSIC_VOID) && 11491 "Should use MaskedValueIsZero if you don't know whether Op" 11492 " is a target node!"); 11493 11494 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 11495 switch (Opc) { 11496 default: break; 11497 case X86ISD::ADD: 11498 case X86ISD::SUB: 11499 case X86ISD::ADC: 11500 case X86ISD::SBB: 11501 case X86ISD::SMUL: 11502 case X86ISD::UMUL: 11503 case X86ISD::INC: 11504 case X86ISD::DEC: 11505 case X86ISD::OR: 11506 case X86ISD::XOR: 11507 case X86ISD::AND: 11508 // These nodes' second result is a boolean. 11509 if (Op.getResNo() == 0) 11510 break; 11511 // Fallthrough 11512 case X86ISD::SETCC: 11513 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 11514 Mask.getBitWidth() - 1); 11515 break; 11516 } 11517} 11518 11519unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 11520 unsigned Depth) const { 11521 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 11522 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 11523 return Op.getValueType().getScalarType().getSizeInBits(); 11524 11525 // Fallback case. 11526 return 1; 11527} 11528 11529/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 11530/// node is a GlobalAddress + offset. 11531bool X86TargetLowering::isGAPlusOffset(SDNode *N, 11532 const GlobalValue* &GA, 11533 int64_t &Offset) const { 11534 if (N->getOpcode() == X86ISD::Wrapper) { 11535 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 11536 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 11537 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 11538 return true; 11539 } 11540 } 11541 return TargetLowering::isGAPlusOffset(N, GA, Offset); 11542} 11543 11544/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 11545static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 11546 TargetLowering::DAGCombinerInfo &DCI) { 11547 DebugLoc dl = N->getDebugLoc(); 11548 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 11549 SDValue V1 = SVOp->getOperand(0); 11550 SDValue V2 = SVOp->getOperand(1); 11551 EVT VT = SVOp->getValueType(0); 11552 11553 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 11554 V2.getOpcode() == ISD::CONCAT_VECTORS) { 11555 // 11556 // 0,0,0,... 11557 // | 11558 // V UNDEF BUILD_VECTOR UNDEF 11559 // \ / \ / 11560 // CONCAT_VECTOR CONCAT_VECTOR 11561 // \ / 11562 // \ / 11563 // RESULT: V + zero extended 11564 // 11565 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 11566 V2.getOperand(1).getOpcode() != ISD::UNDEF || 11567 V1.getOperand(1).getOpcode() != ISD::UNDEF) 11568 return SDValue(); 11569 11570 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 11571 return SDValue(); 11572 11573 // To match the shuffle mask, the first half of the mask should 11574 // be exactly the first vector, and all the rest a splat with the 11575 // first element of the second one. 11576 int NumElems = VT.getVectorNumElements(); 11577 for (int i = 0; i < NumElems/2; ++i) 11578 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 11579 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 11580 return SDValue(); 11581 11582 // Emit a zeroed vector and insert the desired subvector on its 11583 // first half. 11584 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl); 11585 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 11586 DAG.getConstant(0, MVT::i32), DAG, dl); 11587 return DCI.CombineTo(N, InsV); 11588 } 11589 11590 return SDValue(); 11591} 11592 11593/// PerformShuffleCombine - Performs several different shuffle combines. 11594static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 11595 TargetLowering::DAGCombinerInfo &DCI) { 11596 DebugLoc dl = N->getDebugLoc(); 11597 EVT VT = N->getValueType(0); 11598 11599 // Don't create instructions with illegal types after legalize types has run. 11600 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 11601 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 11602 return SDValue(); 11603 11604 // Only handle pure VECTOR_SHUFFLE nodes. 11605 if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE) 11606 return PerformShuffleCombine256(N, DAG, DCI); 11607 11608 // Only handle 128 wide vector from here on. 11609 if (VT.getSizeInBits() != 128) 11610 return SDValue(); 11611 11612 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 11613 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 11614 // consecutive, non-overlapping, and in the right order. 11615 SmallVector<SDValue, 16> Elts; 11616 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 11617 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 11618 11619 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 11620} 11621 11622/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 11623/// generation and convert it from being a bunch of shuffles and extracts 11624/// to a simple store and scalar loads to extract the elements. 11625static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 11626 const TargetLowering &TLI) { 11627 SDValue InputVector = N->getOperand(0); 11628 11629 // Only operate on vectors of 4 elements, where the alternative shuffling 11630 // gets to be more expensive. 11631 if (InputVector.getValueType() != MVT::v4i32) 11632 return SDValue(); 11633 11634 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 11635 // single use which is a sign-extend or zero-extend, and all elements are 11636 // used. 11637 SmallVector<SDNode *, 4> Uses; 11638 unsigned ExtractedElements = 0; 11639 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 11640 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 11641 if (UI.getUse().getResNo() != InputVector.getResNo()) 11642 return SDValue(); 11643 11644 SDNode *Extract = *UI; 11645 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 11646 return SDValue(); 11647 11648 if (Extract->getValueType(0) != MVT::i32) 11649 return SDValue(); 11650 if (!Extract->hasOneUse()) 11651 return SDValue(); 11652 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 11653 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 11654 return SDValue(); 11655 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 11656 return SDValue(); 11657 11658 // Record which element was extracted. 11659 ExtractedElements |= 11660 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 11661 11662 Uses.push_back(Extract); 11663 } 11664 11665 // If not all the elements were used, this may not be worthwhile. 11666 if (ExtractedElements != 15) 11667 return SDValue(); 11668 11669 // Ok, we've now decided to do the transformation. 11670 DebugLoc dl = InputVector.getDebugLoc(); 11671 11672 // Store the value to a temporary stack slot. 11673 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 11674 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 11675 MachinePointerInfo(), false, false, 0); 11676 11677 // Replace each use (extract) with a load of the appropriate element. 11678 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 11679 UE = Uses.end(); UI != UE; ++UI) { 11680 SDNode *Extract = *UI; 11681 11682 // cOMpute the element's address. 11683 SDValue Idx = Extract->getOperand(1); 11684 unsigned EltSize = 11685 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 11686 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 11687 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 11688 11689 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 11690 StackPtr, OffsetVal); 11691 11692 // Load the scalar. 11693 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 11694 ScalarAddr, MachinePointerInfo(), 11695 false, false, 0); 11696 11697 // Replace the exact with the load. 11698 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 11699 } 11700 11701 // The replacement was made in place; don't return anything. 11702 return SDValue(); 11703} 11704 11705/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 11706static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 11707 const X86Subtarget *Subtarget) { 11708 DebugLoc DL = N->getDebugLoc(); 11709 SDValue Cond = N->getOperand(0); 11710 // Get the LHS/RHS of the select. 11711 SDValue LHS = N->getOperand(1); 11712 SDValue RHS = N->getOperand(2); 11713 11714 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 11715 // instructions match the semantics of the common C idiom x<y?x:y but not 11716 // x<=y?x:y, because of how they handle negative zero (which can be 11717 // ignored in unsafe-math mode). 11718 if (Subtarget->hasSSE2() && 11719 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 11720 Cond.getOpcode() == ISD::SETCC) { 11721 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 11722 11723 unsigned Opcode = 0; 11724 // Check for x CC y ? x : y. 11725 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 11726 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 11727 switch (CC) { 11728 default: break; 11729 case ISD::SETULT: 11730 // Converting this to a min would handle NaNs incorrectly, and swapping 11731 // the operands would cause it to handle comparisons between positive 11732 // and negative zero incorrectly. 11733 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 11734 if (!UnsafeFPMath && 11735 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 11736 break; 11737 std::swap(LHS, RHS); 11738 } 11739 Opcode = X86ISD::FMIN; 11740 break; 11741 case ISD::SETOLE: 11742 // Converting this to a min would handle comparisons between positive 11743 // and negative zero incorrectly. 11744 if (!UnsafeFPMath && 11745 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 11746 break; 11747 Opcode = X86ISD::FMIN; 11748 break; 11749 case ISD::SETULE: 11750 // Converting this to a min would handle both negative zeros and NaNs 11751 // incorrectly, but we can swap the operands to fix both. 11752 std::swap(LHS, RHS); 11753 case ISD::SETOLT: 11754 case ISD::SETLT: 11755 case ISD::SETLE: 11756 Opcode = X86ISD::FMIN; 11757 break; 11758 11759 case ISD::SETOGE: 11760 // Converting this to a max would handle comparisons between positive 11761 // and negative zero incorrectly. 11762 if (!UnsafeFPMath && 11763 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 11764 break; 11765 Opcode = X86ISD::FMAX; 11766 break; 11767 case ISD::SETUGT: 11768 // Converting this to a max would handle NaNs incorrectly, and swapping 11769 // the operands would cause it to handle comparisons between positive 11770 // and negative zero incorrectly. 11771 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 11772 if (!UnsafeFPMath && 11773 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 11774 break; 11775 std::swap(LHS, RHS); 11776 } 11777 Opcode = X86ISD::FMAX; 11778 break; 11779 case ISD::SETUGE: 11780 // Converting this to a max would handle both negative zeros and NaNs 11781 // incorrectly, but we can swap the operands to fix both. 11782 std::swap(LHS, RHS); 11783 case ISD::SETOGT: 11784 case ISD::SETGT: 11785 case ISD::SETGE: 11786 Opcode = X86ISD::FMAX; 11787 break; 11788 } 11789 // Check for x CC y ? y : x -- a min/max with reversed arms. 11790 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 11791 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 11792 switch (CC) { 11793 default: break; 11794 case ISD::SETOGE: 11795 // Converting this to a min would handle comparisons between positive 11796 // and negative zero incorrectly, and swapping the operands would 11797 // cause it to handle NaNs incorrectly. 11798 if (!UnsafeFPMath && 11799 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 11800 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11801 break; 11802 std::swap(LHS, RHS); 11803 } 11804 Opcode = X86ISD::FMIN; 11805 break; 11806 case ISD::SETUGT: 11807 // Converting this to a min would handle NaNs incorrectly. 11808 if (!UnsafeFPMath && 11809 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 11810 break; 11811 Opcode = X86ISD::FMIN; 11812 break; 11813 case ISD::SETUGE: 11814 // Converting this to a min would handle both negative zeros and NaNs 11815 // incorrectly, but we can swap the operands to fix both. 11816 std::swap(LHS, RHS); 11817 case ISD::SETOGT: 11818 case ISD::SETGT: 11819 case ISD::SETGE: 11820 Opcode = X86ISD::FMIN; 11821 break; 11822 11823 case ISD::SETULT: 11824 // Converting this to a max would handle NaNs incorrectly. 11825 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11826 break; 11827 Opcode = X86ISD::FMAX; 11828 break; 11829 case ISD::SETOLE: 11830 // Converting this to a max would handle comparisons between positive 11831 // and negative zero incorrectly, and swapping the operands would 11832 // cause it to handle NaNs incorrectly. 11833 if (!UnsafeFPMath && 11834 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 11835 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 11836 break; 11837 std::swap(LHS, RHS); 11838 } 11839 Opcode = X86ISD::FMAX; 11840 break; 11841 case ISD::SETULE: 11842 // Converting this to a max would handle both negative zeros and NaNs 11843 // incorrectly, but we can swap the operands to fix both. 11844 std::swap(LHS, RHS); 11845 case ISD::SETOLT: 11846 case ISD::SETLT: 11847 case ISD::SETLE: 11848 Opcode = X86ISD::FMAX; 11849 break; 11850 } 11851 } 11852 11853 if (Opcode) 11854 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 11855 } 11856 11857 // If this is a select between two integer constants, try to do some 11858 // optimizations. 11859 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 11860 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 11861 // Don't do this for crazy integer types. 11862 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 11863 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 11864 // so that TrueC (the true value) is larger than FalseC. 11865 bool NeedsCondInvert = false; 11866 11867 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 11868 // Efficiently invertible. 11869 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 11870 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 11871 isa<ConstantSDNode>(Cond.getOperand(1))))) { 11872 NeedsCondInvert = true; 11873 std::swap(TrueC, FalseC); 11874 } 11875 11876 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 11877 if (FalseC->getAPIntValue() == 0 && 11878 TrueC->getAPIntValue().isPowerOf2()) { 11879 if (NeedsCondInvert) // Invert the condition if needed. 11880 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11881 DAG.getConstant(1, Cond.getValueType())); 11882 11883 // Zero extend the condition if needed. 11884 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 11885 11886 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 11887 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 11888 DAG.getConstant(ShAmt, MVT::i8)); 11889 } 11890 11891 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 11892 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 11893 if (NeedsCondInvert) // Invert the condition if needed. 11894 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11895 DAG.getConstant(1, Cond.getValueType())); 11896 11897 // Zero extend the condition if needed. 11898 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 11899 FalseC->getValueType(0), Cond); 11900 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11901 SDValue(FalseC, 0)); 11902 } 11903 11904 // Optimize cases that will turn into an LEA instruction. This requires 11905 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 11906 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 11907 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 11908 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 11909 11910 bool isFastMultiplier = false; 11911 if (Diff < 10) { 11912 switch ((unsigned char)Diff) { 11913 default: break; 11914 case 1: // result = add base, cond 11915 case 2: // result = lea base( , cond*2) 11916 case 3: // result = lea base(cond, cond*2) 11917 case 4: // result = lea base( , cond*4) 11918 case 5: // result = lea base(cond, cond*4) 11919 case 8: // result = lea base( , cond*8) 11920 case 9: // result = lea base(cond, cond*8) 11921 isFastMultiplier = true; 11922 break; 11923 } 11924 } 11925 11926 if (isFastMultiplier) { 11927 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 11928 if (NeedsCondInvert) // Invert the condition if needed. 11929 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 11930 DAG.getConstant(1, Cond.getValueType())); 11931 11932 // Zero extend the condition if needed. 11933 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 11934 Cond); 11935 // Scale the condition by the difference. 11936 if (Diff != 1) 11937 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 11938 DAG.getConstant(Diff, Cond.getValueType())); 11939 11940 // Add the base if non-zero. 11941 if (FalseC->getAPIntValue() != 0) 11942 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 11943 SDValue(FalseC, 0)); 11944 return Cond; 11945 } 11946 } 11947 } 11948 } 11949 11950 return SDValue(); 11951} 11952 11953/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 11954static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 11955 TargetLowering::DAGCombinerInfo &DCI) { 11956 DebugLoc DL = N->getDebugLoc(); 11957 11958 // If the flag operand isn't dead, don't touch this CMOV. 11959 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 11960 return SDValue(); 11961 11962 SDValue FalseOp = N->getOperand(0); 11963 SDValue TrueOp = N->getOperand(1); 11964 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 11965 SDValue Cond = N->getOperand(3); 11966 if (CC == X86::COND_E || CC == X86::COND_NE) { 11967 switch (Cond.getOpcode()) { 11968 default: break; 11969 case X86ISD::BSR: 11970 case X86ISD::BSF: 11971 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 11972 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 11973 return (CC == X86::COND_E) ? FalseOp : TrueOp; 11974 } 11975 } 11976 11977 // If this is a select between two integer constants, try to do some 11978 // optimizations. Note that the operands are ordered the opposite of SELECT 11979 // operands. 11980 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 11981 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 11982 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 11983 // larger than FalseC (the false value). 11984 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 11985 CC = X86::GetOppositeBranchCondition(CC); 11986 std::swap(TrueC, FalseC); 11987 } 11988 11989 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 11990 // This is efficient for any integer data type (including i8/i16) and 11991 // shift amount. 11992 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 11993 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 11994 DAG.getConstant(CC, MVT::i8), Cond); 11995 11996 // Zero extend the condition if needed. 11997 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 11998 11999 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12000 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 12001 DAG.getConstant(ShAmt, MVT::i8)); 12002 if (N->getNumValues() == 2) // Dead flag value? 12003 return DCI.CombineTo(N, Cond, SDValue()); 12004 return Cond; 12005 } 12006 12007 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 12008 // for any integer data type, including i8/i16. 12009 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12010 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12011 DAG.getConstant(CC, MVT::i8), Cond); 12012 12013 // Zero extend the condition if needed. 12014 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12015 FalseC->getValueType(0), Cond); 12016 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12017 SDValue(FalseC, 0)); 12018 12019 if (N->getNumValues() == 2) // Dead flag value? 12020 return DCI.CombineTo(N, Cond, SDValue()); 12021 return Cond; 12022 } 12023 12024 // Optimize cases that will turn into an LEA instruction. This requires 12025 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12026 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12027 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12028 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12029 12030 bool isFastMultiplier = false; 12031 if (Diff < 10) { 12032 switch ((unsigned char)Diff) { 12033 default: break; 12034 case 1: // result = add base, cond 12035 case 2: // result = lea base( , cond*2) 12036 case 3: // result = lea base(cond, cond*2) 12037 case 4: // result = lea base( , cond*4) 12038 case 5: // result = lea base(cond, cond*4) 12039 case 8: // result = lea base( , cond*8) 12040 case 9: // result = lea base(cond, cond*8) 12041 isFastMultiplier = true; 12042 break; 12043 } 12044 } 12045 12046 if (isFastMultiplier) { 12047 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12048 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12049 DAG.getConstant(CC, MVT::i8), Cond); 12050 // Zero extend the condition if needed. 12051 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12052 Cond); 12053 // Scale the condition by the difference. 12054 if (Diff != 1) 12055 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12056 DAG.getConstant(Diff, Cond.getValueType())); 12057 12058 // Add the base if non-zero. 12059 if (FalseC->getAPIntValue() != 0) 12060 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12061 SDValue(FalseC, 0)); 12062 if (N->getNumValues() == 2) // Dead flag value? 12063 return DCI.CombineTo(N, Cond, SDValue()); 12064 return Cond; 12065 } 12066 } 12067 } 12068 } 12069 return SDValue(); 12070} 12071 12072 12073/// PerformMulCombine - Optimize a single multiply with constant into two 12074/// in order to implement it with two cheaper instructions, e.g. 12075/// LEA + SHL, LEA + LEA. 12076static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 12077 TargetLowering::DAGCombinerInfo &DCI) { 12078 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 12079 return SDValue(); 12080 12081 EVT VT = N->getValueType(0); 12082 if (VT != MVT::i64) 12083 return SDValue(); 12084 12085 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 12086 if (!C) 12087 return SDValue(); 12088 uint64_t MulAmt = C->getZExtValue(); 12089 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 12090 return SDValue(); 12091 12092 uint64_t MulAmt1 = 0; 12093 uint64_t MulAmt2 = 0; 12094 if ((MulAmt % 9) == 0) { 12095 MulAmt1 = 9; 12096 MulAmt2 = MulAmt / 9; 12097 } else if ((MulAmt % 5) == 0) { 12098 MulAmt1 = 5; 12099 MulAmt2 = MulAmt / 5; 12100 } else if ((MulAmt % 3) == 0) { 12101 MulAmt1 = 3; 12102 MulAmt2 = MulAmt / 3; 12103 } 12104 if (MulAmt2 && 12105 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 12106 DebugLoc DL = N->getDebugLoc(); 12107 12108 if (isPowerOf2_64(MulAmt2) && 12109 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 12110 // If second multiplifer is pow2, issue it first. We want the multiply by 12111 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 12112 // is an add. 12113 std::swap(MulAmt1, MulAmt2); 12114 12115 SDValue NewMul; 12116 if (isPowerOf2_64(MulAmt1)) 12117 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 12118 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 12119 else 12120 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 12121 DAG.getConstant(MulAmt1, VT)); 12122 12123 if (isPowerOf2_64(MulAmt2)) 12124 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 12125 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 12126 else 12127 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 12128 DAG.getConstant(MulAmt2, VT)); 12129 12130 // Do not add new nodes to DAG combiner worklist. 12131 DCI.CombineTo(N, NewMul, false); 12132 } 12133 return SDValue(); 12134} 12135 12136static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 12137 SDValue N0 = N->getOperand(0); 12138 SDValue N1 = N->getOperand(1); 12139 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 12140 EVT VT = N0.getValueType(); 12141 12142 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 12143 // since the result of setcc_c is all zero's or all ones. 12144 if (N1C && N0.getOpcode() == ISD::AND && 12145 N0.getOperand(1).getOpcode() == ISD::Constant) { 12146 SDValue N00 = N0.getOperand(0); 12147 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 12148 ((N00.getOpcode() == ISD::ANY_EXTEND || 12149 N00.getOpcode() == ISD::ZERO_EXTEND) && 12150 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 12151 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 12152 APInt ShAmt = N1C->getAPIntValue(); 12153 Mask = Mask.shl(ShAmt); 12154 if (Mask != 0) 12155 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 12156 N00, DAG.getConstant(Mask, VT)); 12157 } 12158 } 12159 12160 return SDValue(); 12161} 12162 12163/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 12164/// when possible. 12165static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 12166 const X86Subtarget *Subtarget) { 12167 EVT VT = N->getValueType(0); 12168 if (!VT.isVector() && VT.isInteger() && 12169 N->getOpcode() == ISD::SHL) 12170 return PerformSHLCombine(N, DAG); 12171 12172 // On X86 with SSE2 support, we can transform this to a vector shift if 12173 // all elements are shifted by the same amount. We can't do this in legalize 12174 // because the a constant vector is typically transformed to a constant pool 12175 // so we have no knowledge of the shift amount. 12176 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX())) 12177 return SDValue(); 12178 12179 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 12180 return SDValue(); 12181 12182 SDValue ShAmtOp = N->getOperand(1); 12183 EVT EltVT = VT.getVectorElementType(); 12184 DebugLoc DL = N->getDebugLoc(); 12185 SDValue BaseShAmt = SDValue(); 12186 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 12187 unsigned NumElts = VT.getVectorNumElements(); 12188 unsigned i = 0; 12189 for (; i != NumElts; ++i) { 12190 SDValue Arg = ShAmtOp.getOperand(i); 12191 if (Arg.getOpcode() == ISD::UNDEF) continue; 12192 BaseShAmt = Arg; 12193 break; 12194 } 12195 for (; i != NumElts; ++i) { 12196 SDValue Arg = ShAmtOp.getOperand(i); 12197 if (Arg.getOpcode() == ISD::UNDEF) continue; 12198 if (Arg != BaseShAmt) { 12199 return SDValue(); 12200 } 12201 } 12202 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 12203 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 12204 SDValue InVec = ShAmtOp.getOperand(0); 12205 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 12206 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 12207 unsigned i = 0; 12208 for (; i != NumElts; ++i) { 12209 SDValue Arg = InVec.getOperand(i); 12210 if (Arg.getOpcode() == ISD::UNDEF) continue; 12211 BaseShAmt = Arg; 12212 break; 12213 } 12214 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 12215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 12216 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 12217 if (C->getZExtValue() == SplatIdx) 12218 BaseShAmt = InVec.getOperand(1); 12219 } 12220 } 12221 if (BaseShAmt.getNode() == 0) 12222 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 12223 DAG.getIntPtrConstant(0)); 12224 } else 12225 return SDValue(); 12226 12227 // The shift amount is an i32. 12228 if (EltVT.bitsGT(MVT::i32)) 12229 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 12230 else if (EltVT.bitsLT(MVT::i32)) 12231 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 12232 12233 // The shift amount is identical so we can do a vector shift. 12234 SDValue ValOp = N->getOperand(0); 12235 switch (N->getOpcode()) { 12236 default: 12237 llvm_unreachable("Unknown shift opcode!"); 12238 break; 12239 case ISD::SHL: 12240 if (VT == MVT::v2i64) 12241 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12242 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 12243 ValOp, BaseShAmt); 12244 if (VT == MVT::v4i32) 12245 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12246 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 12247 ValOp, BaseShAmt); 12248 if (VT == MVT::v8i16) 12249 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12250 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 12251 ValOp, BaseShAmt); 12252 break; 12253 case ISD::SRA: 12254 if (VT == MVT::v4i32) 12255 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12256 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 12257 ValOp, BaseShAmt); 12258 if (VT == MVT::v8i16) 12259 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12260 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 12261 ValOp, BaseShAmt); 12262 break; 12263 case ISD::SRL: 12264 if (VT == MVT::v2i64) 12265 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12266 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 12267 ValOp, BaseShAmt); 12268 if (VT == MVT::v4i32) 12269 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12270 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 12271 ValOp, BaseShAmt); 12272 if (VT == MVT::v8i16) 12273 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 12274 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 12275 ValOp, BaseShAmt); 12276 break; 12277 } 12278 return SDValue(); 12279} 12280 12281 12282// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 12283// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 12284// and friends. Likewise for OR -> CMPNEQSS. 12285static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 12286 TargetLowering::DAGCombinerInfo &DCI, 12287 const X86Subtarget *Subtarget) { 12288 unsigned opcode; 12289 12290 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 12291 // we're requiring SSE2 for both. 12292 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 12293 SDValue N0 = N->getOperand(0); 12294 SDValue N1 = N->getOperand(1); 12295 SDValue CMP0 = N0->getOperand(1); 12296 SDValue CMP1 = N1->getOperand(1); 12297 DebugLoc DL = N->getDebugLoc(); 12298 12299 // The SETCCs should both refer to the same CMP. 12300 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 12301 return SDValue(); 12302 12303 SDValue CMP00 = CMP0->getOperand(0); 12304 SDValue CMP01 = CMP0->getOperand(1); 12305 EVT VT = CMP00.getValueType(); 12306 12307 if (VT == MVT::f32 || VT == MVT::f64) { 12308 bool ExpectingFlags = false; 12309 // Check for any users that want flags: 12310 for (SDNode::use_iterator UI = N->use_begin(), 12311 UE = N->use_end(); 12312 !ExpectingFlags && UI != UE; ++UI) 12313 switch (UI->getOpcode()) { 12314 default: 12315 case ISD::BR_CC: 12316 case ISD::BRCOND: 12317 case ISD::SELECT: 12318 ExpectingFlags = true; 12319 break; 12320 case ISD::CopyToReg: 12321 case ISD::SIGN_EXTEND: 12322 case ISD::ZERO_EXTEND: 12323 case ISD::ANY_EXTEND: 12324 break; 12325 } 12326 12327 if (!ExpectingFlags) { 12328 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 12329 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 12330 12331 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 12332 X86::CondCode tmp = cc0; 12333 cc0 = cc1; 12334 cc1 = tmp; 12335 } 12336 12337 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 12338 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 12339 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 12340 X86ISD::NodeType NTOperator = is64BitFP ? 12341 X86ISD::FSETCCsd : X86ISD::FSETCCss; 12342 // FIXME: need symbolic constants for these magic numbers. 12343 // See X86ATTInstPrinter.cpp:printSSECC(). 12344 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 12345 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 12346 DAG.getConstant(x86cc, MVT::i8)); 12347 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 12348 OnesOrZeroesF); 12349 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 12350 DAG.getConstant(1, MVT::i32)); 12351 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 12352 return OneBitOfTruth; 12353 } 12354 } 12355 } 12356 } 12357 return SDValue(); 12358} 12359 12360/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 12361/// so it can be folded inside ANDNP. 12362static bool CanFoldXORWithAllOnes(const SDNode *N) { 12363 EVT VT = N->getValueType(0); 12364 12365 // Match direct AllOnes for 128 and 256-bit vectors 12366 if (ISD::isBuildVectorAllOnes(N)) 12367 return true; 12368 12369 // Look through a bit convert. 12370 if (N->getOpcode() == ISD::BITCAST) 12371 N = N->getOperand(0).getNode(); 12372 12373 // Sometimes the operand may come from a insert_subvector building a 256-bit 12374 // allones vector 12375 if (VT.getSizeInBits() == 256 && 12376 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 12377 SDValue V1 = N->getOperand(0); 12378 SDValue V2 = N->getOperand(1); 12379 12380 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 12381 V1.getOperand(0).getOpcode() == ISD::UNDEF && 12382 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 12383 ISD::isBuildVectorAllOnes(V2.getNode())) 12384 return true; 12385 } 12386 12387 return false; 12388} 12389 12390static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 12391 TargetLowering::DAGCombinerInfo &DCI, 12392 const X86Subtarget *Subtarget) { 12393 if (DCI.isBeforeLegalizeOps()) 12394 return SDValue(); 12395 12396 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 12397 if (R.getNode()) 12398 return R; 12399 12400 // Want to form ANDNP nodes: 12401 // 1) In the hopes of then easily combining them with OR and AND nodes 12402 // to form PBLEND/PSIGN. 12403 // 2) To match ANDN packed intrinsics 12404 EVT VT = N->getValueType(0); 12405 if (VT != MVT::v2i64 && VT != MVT::v4i64) 12406 return SDValue(); 12407 12408 SDValue N0 = N->getOperand(0); 12409 SDValue N1 = N->getOperand(1); 12410 DebugLoc DL = N->getDebugLoc(); 12411 12412 // Check LHS for vnot 12413 if (N0.getOpcode() == ISD::XOR && 12414 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 12415 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 12416 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 12417 12418 // Check RHS for vnot 12419 if (N1.getOpcode() == ISD::XOR && 12420 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 12421 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 12422 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 12423 12424 return SDValue(); 12425} 12426 12427static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 12428 TargetLowering::DAGCombinerInfo &DCI, 12429 const X86Subtarget *Subtarget) { 12430 if (DCI.isBeforeLegalizeOps()) 12431 return SDValue(); 12432 12433 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 12434 if (R.getNode()) 12435 return R; 12436 12437 EVT VT = N->getValueType(0); 12438 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 12439 return SDValue(); 12440 12441 SDValue N0 = N->getOperand(0); 12442 SDValue N1 = N->getOperand(1); 12443 12444 // look for psign/blend 12445 if (Subtarget->hasSSSE3()) { 12446 if (VT == MVT::v2i64) { 12447 // Canonicalize pandn to RHS 12448 if (N0.getOpcode() == X86ISD::ANDNP) 12449 std::swap(N0, N1); 12450 // or (and (m, x), (pandn m, y)) 12451 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 12452 SDValue Mask = N1.getOperand(0); 12453 SDValue X = N1.getOperand(1); 12454 SDValue Y; 12455 if (N0.getOperand(0) == Mask) 12456 Y = N0.getOperand(1); 12457 if (N0.getOperand(1) == Mask) 12458 Y = N0.getOperand(0); 12459 12460 // Check to see if the mask appeared in both the AND and ANDNP and 12461 if (!Y.getNode()) 12462 return SDValue(); 12463 12464 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 12465 if (Mask.getOpcode() != ISD::BITCAST || 12466 X.getOpcode() != ISD::BITCAST || 12467 Y.getOpcode() != ISD::BITCAST) 12468 return SDValue(); 12469 12470 // Look through mask bitcast. 12471 Mask = Mask.getOperand(0); 12472 EVT MaskVT = Mask.getValueType(); 12473 12474 // Validate that the Mask operand is a vector sra node. The sra node 12475 // will be an intrinsic. 12476 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 12477 return SDValue(); 12478 12479 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 12480 // there is no psrai.b 12481 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 12482 case Intrinsic::x86_sse2_psrai_w: 12483 case Intrinsic::x86_sse2_psrai_d: 12484 break; 12485 default: return SDValue(); 12486 } 12487 12488 // Check that the SRA is all signbits. 12489 SDValue SraC = Mask.getOperand(2); 12490 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 12491 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 12492 if ((SraAmt + 1) != EltBits) 12493 return SDValue(); 12494 12495 DebugLoc DL = N->getDebugLoc(); 12496 12497 // Now we know we at least have a plendvb with the mask val. See if 12498 // we can form a psignb/w/d. 12499 // psign = x.type == y.type == mask.type && y = sub(0, x); 12500 X = X.getOperand(0); 12501 Y = Y.getOperand(0); 12502 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 12503 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 12504 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 12505 unsigned Opc = 0; 12506 switch (EltBits) { 12507 case 8: Opc = X86ISD::PSIGNB; break; 12508 case 16: Opc = X86ISD::PSIGNW; break; 12509 case 32: Opc = X86ISD::PSIGND; break; 12510 default: break; 12511 } 12512 if (Opc) { 12513 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 12514 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 12515 } 12516 } 12517 // PBLENDVB only available on SSE 4.1 12518 if (!Subtarget->hasSSE41()) 12519 return SDValue(); 12520 12521 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 12522 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 12523 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 12524 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask); 12525 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 12526 } 12527 } 12528 } 12529 12530 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 12531 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 12532 std::swap(N0, N1); 12533 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 12534 return SDValue(); 12535 if (!N0.hasOneUse() || !N1.hasOneUse()) 12536 return SDValue(); 12537 12538 SDValue ShAmt0 = N0.getOperand(1); 12539 if (ShAmt0.getValueType() != MVT::i8) 12540 return SDValue(); 12541 SDValue ShAmt1 = N1.getOperand(1); 12542 if (ShAmt1.getValueType() != MVT::i8) 12543 return SDValue(); 12544 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 12545 ShAmt0 = ShAmt0.getOperand(0); 12546 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 12547 ShAmt1 = ShAmt1.getOperand(0); 12548 12549 DebugLoc DL = N->getDebugLoc(); 12550 unsigned Opc = X86ISD::SHLD; 12551 SDValue Op0 = N0.getOperand(0); 12552 SDValue Op1 = N1.getOperand(0); 12553 if (ShAmt0.getOpcode() == ISD::SUB) { 12554 Opc = X86ISD::SHRD; 12555 std::swap(Op0, Op1); 12556 std::swap(ShAmt0, ShAmt1); 12557 } 12558 12559 unsigned Bits = VT.getSizeInBits(); 12560 if (ShAmt1.getOpcode() == ISD::SUB) { 12561 SDValue Sum = ShAmt1.getOperand(0); 12562 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 12563 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 12564 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 12565 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 12566 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 12567 return DAG.getNode(Opc, DL, VT, 12568 Op0, Op1, 12569 DAG.getNode(ISD::TRUNCATE, DL, 12570 MVT::i8, ShAmt0)); 12571 } 12572 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 12573 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 12574 if (ShAmt0C && 12575 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 12576 return DAG.getNode(Opc, DL, VT, 12577 N0.getOperand(0), N1.getOperand(0), 12578 DAG.getNode(ISD::TRUNCATE, DL, 12579 MVT::i8, ShAmt0)); 12580 } 12581 12582 return SDValue(); 12583} 12584 12585/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 12586static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 12587 const X86Subtarget *Subtarget) { 12588 StoreSDNode *St = cast<StoreSDNode>(N); 12589 EVT VT = St->getValue().getValueType(); 12590 EVT StVT = St->getMemoryVT(); 12591 DebugLoc dl = St->getDebugLoc(); 12592 12593 // Optimize trunc store (of multiple scalars) to shuffle and store. 12594 // First, pack all of the elements in one place. Next, store to memory 12595 // in fewer chunks. 12596 if (St->isTruncatingStore() && VT.isVector()) { 12597 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12598 unsigned NumElems = VT.getVectorNumElements(); 12599 assert(StVT != VT && "Cannot truncate to the same type"); 12600 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 12601 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 12602 12603 // From, To sizes and ElemCount must be pow of two 12604 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 12605 // We are going to use the original vector elt for storing. 12606 // accumulated smaller vector elements must be a multiple of bigger size. 12607 if (0 != (NumElems * ToSz) % FromSz) return SDValue(); 12608 unsigned SizeRatio = FromSz / ToSz; 12609 12610 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 12611 12612 // Create a type on which we perform the shuffle 12613 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 12614 StVT.getScalarType(), NumElems*SizeRatio); 12615 12616 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 12617 12618 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 12619 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 12620 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 12621 12622 // Can't shuffle using an illegal type 12623 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 12624 12625 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 12626 DAG.getUNDEF(WideVec.getValueType()), 12627 ShuffleVec.data()); 12628 // At this point all of the data is stored at the bottom of the 12629 // register. We now need to save it to mem. 12630 12631 // Find the largest store unit 12632 MVT StoreType = MVT::i8; 12633 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 12634 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 12635 MVT Tp = (MVT::SimpleValueType)tp; 12636 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 12637 StoreType = Tp; 12638 } 12639 12640 // Bitcast the original vector into a vector of store-size units 12641 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 12642 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 12643 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 12644 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 12645 SmallVector<SDValue, 8> Chains; 12646 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 12647 TLI.getPointerTy()); 12648 SDValue Ptr = St->getBasePtr(); 12649 12650 // Perform one or more big stores into memory. 12651 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 12652 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 12653 StoreType, ShuffWide, 12654 DAG.getIntPtrConstant(i)); 12655 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 12656 St->getPointerInfo(), St->isVolatile(), 12657 St->isNonTemporal(), St->getAlignment()); 12658 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 12659 Chains.push_back(Ch); 12660 } 12661 12662 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 12663 Chains.size()); 12664 } 12665 12666 12667 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 12668 // the FP state in cases where an emms may be missing. 12669 // A preferable solution to the general problem is to figure out the right 12670 // places to insert EMMS. This qualifies as a quick hack. 12671 12672 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 12673 if (VT.getSizeInBits() != 64) 12674 return SDValue(); 12675 12676 const Function *F = DAG.getMachineFunction().getFunction(); 12677 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 12678 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 12679 && Subtarget->hasSSE2(); 12680 if ((VT.isVector() || 12681 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 12682 isa<LoadSDNode>(St->getValue()) && 12683 !cast<LoadSDNode>(St->getValue())->isVolatile() && 12684 St->getChain().hasOneUse() && !St->isVolatile()) { 12685 SDNode* LdVal = St->getValue().getNode(); 12686 LoadSDNode *Ld = 0; 12687 int TokenFactorIndex = -1; 12688 SmallVector<SDValue, 8> Ops; 12689 SDNode* ChainVal = St->getChain().getNode(); 12690 // Must be a store of a load. We currently handle two cases: the load 12691 // is a direct child, and it's under an intervening TokenFactor. It is 12692 // possible to dig deeper under nested TokenFactors. 12693 if (ChainVal == LdVal) 12694 Ld = cast<LoadSDNode>(St->getChain()); 12695 else if (St->getValue().hasOneUse() && 12696 ChainVal->getOpcode() == ISD::TokenFactor) { 12697 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 12698 if (ChainVal->getOperand(i).getNode() == LdVal) { 12699 TokenFactorIndex = i; 12700 Ld = cast<LoadSDNode>(St->getValue()); 12701 } else 12702 Ops.push_back(ChainVal->getOperand(i)); 12703 } 12704 } 12705 12706 if (!Ld || !ISD::isNormalLoad(Ld)) 12707 return SDValue(); 12708 12709 // If this is not the MMX case, i.e. we are just turning i64 load/store 12710 // into f64 load/store, avoid the transformation if there are multiple 12711 // uses of the loaded value. 12712 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 12713 return SDValue(); 12714 12715 DebugLoc LdDL = Ld->getDebugLoc(); 12716 DebugLoc StDL = N->getDebugLoc(); 12717 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 12718 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 12719 // pair instead. 12720 if (Subtarget->is64Bit() || F64IsLegal) { 12721 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 12722 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 12723 Ld->getPointerInfo(), Ld->isVolatile(), 12724 Ld->isNonTemporal(), Ld->getAlignment()); 12725 SDValue NewChain = NewLd.getValue(1); 12726 if (TokenFactorIndex != -1) { 12727 Ops.push_back(NewChain); 12728 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 12729 Ops.size()); 12730 } 12731 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 12732 St->getPointerInfo(), 12733 St->isVolatile(), St->isNonTemporal(), 12734 St->getAlignment()); 12735 } 12736 12737 // Otherwise, lower to two pairs of 32-bit loads / stores. 12738 SDValue LoAddr = Ld->getBasePtr(); 12739 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 12740 DAG.getConstant(4, MVT::i32)); 12741 12742 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 12743 Ld->getPointerInfo(), 12744 Ld->isVolatile(), Ld->isNonTemporal(), 12745 Ld->getAlignment()); 12746 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 12747 Ld->getPointerInfo().getWithOffset(4), 12748 Ld->isVolatile(), Ld->isNonTemporal(), 12749 MinAlign(Ld->getAlignment(), 4)); 12750 12751 SDValue NewChain = LoLd.getValue(1); 12752 if (TokenFactorIndex != -1) { 12753 Ops.push_back(LoLd); 12754 Ops.push_back(HiLd); 12755 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 12756 Ops.size()); 12757 } 12758 12759 LoAddr = St->getBasePtr(); 12760 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 12761 DAG.getConstant(4, MVT::i32)); 12762 12763 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 12764 St->getPointerInfo(), 12765 St->isVolatile(), St->isNonTemporal(), 12766 St->getAlignment()); 12767 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 12768 St->getPointerInfo().getWithOffset(4), 12769 St->isVolatile(), 12770 St->isNonTemporal(), 12771 MinAlign(St->getAlignment(), 4)); 12772 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 12773 } 12774 return SDValue(); 12775} 12776 12777/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 12778/// X86ISD::FXOR nodes. 12779static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 12780 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 12781 // F[X]OR(0.0, x) -> x 12782 // F[X]OR(x, 0.0) -> x 12783 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 12784 if (C->getValueAPF().isPosZero()) 12785 return N->getOperand(1); 12786 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 12787 if (C->getValueAPF().isPosZero()) 12788 return N->getOperand(0); 12789 return SDValue(); 12790} 12791 12792/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 12793static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 12794 // FAND(0.0, x) -> 0.0 12795 // FAND(x, 0.0) -> 0.0 12796 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 12797 if (C->getValueAPF().isPosZero()) 12798 return N->getOperand(0); 12799 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 12800 if (C->getValueAPF().isPosZero()) 12801 return N->getOperand(1); 12802 return SDValue(); 12803} 12804 12805static SDValue PerformBTCombine(SDNode *N, 12806 SelectionDAG &DAG, 12807 TargetLowering::DAGCombinerInfo &DCI) { 12808 // BT ignores high bits in the bit index operand. 12809 SDValue Op1 = N->getOperand(1); 12810 if (Op1.hasOneUse()) { 12811 unsigned BitWidth = Op1.getValueSizeInBits(); 12812 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 12813 APInt KnownZero, KnownOne; 12814 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 12815 !DCI.isBeforeLegalizeOps()); 12816 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12817 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 12818 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 12819 DCI.CommitTargetLoweringOpt(TLO); 12820 } 12821 return SDValue(); 12822} 12823 12824static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 12825 SDValue Op = N->getOperand(0); 12826 if (Op.getOpcode() == ISD::BITCAST) 12827 Op = Op.getOperand(0); 12828 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 12829 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 12830 VT.getVectorElementType().getSizeInBits() == 12831 OpVT.getVectorElementType().getSizeInBits()) { 12832 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 12833 } 12834 return SDValue(); 12835} 12836 12837static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 12838 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 12839 // (and (i32 x86isd::setcc_carry), 1) 12840 // This eliminates the zext. This transformation is necessary because 12841 // ISD::SETCC is always legalized to i8. 12842 DebugLoc dl = N->getDebugLoc(); 12843 SDValue N0 = N->getOperand(0); 12844 EVT VT = N->getValueType(0); 12845 if (N0.getOpcode() == ISD::AND && 12846 N0.hasOneUse() && 12847 N0.getOperand(0).hasOneUse()) { 12848 SDValue N00 = N0.getOperand(0); 12849 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 12850 return SDValue(); 12851 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 12852 if (!C || C->getZExtValue() != 1) 12853 return SDValue(); 12854 return DAG.getNode(ISD::AND, dl, VT, 12855 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 12856 N00.getOperand(0), N00.getOperand(1)), 12857 DAG.getConstant(1, VT)); 12858 } 12859 12860 return SDValue(); 12861} 12862 12863// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 12864static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 12865 unsigned X86CC = N->getConstantOperandVal(0); 12866 SDValue EFLAG = N->getOperand(1); 12867 DebugLoc DL = N->getDebugLoc(); 12868 12869 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 12870 // a zext and produces an all-ones bit which is more useful than 0/1 in some 12871 // cases. 12872 if (X86CC == X86::COND_B) 12873 return DAG.getNode(ISD::AND, DL, MVT::i8, 12874 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 12875 DAG.getConstant(X86CC, MVT::i8), EFLAG), 12876 DAG.getConstant(1, MVT::i8)); 12877 12878 return SDValue(); 12879} 12880 12881static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 12882 const X86TargetLowering *XTLI) { 12883 SDValue Op0 = N->getOperand(0); 12884 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 12885 // a 32-bit target where SSE doesn't support i64->FP operations. 12886 if (Op0.getOpcode() == ISD::LOAD) { 12887 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 12888 EVT VT = Ld->getValueType(0); 12889 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 12890 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 12891 !XTLI->getSubtarget()->is64Bit() && 12892 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 12893 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 12894 Ld->getChain(), Op0, DAG); 12895 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 12896 return FILDChain; 12897 } 12898 } 12899 return SDValue(); 12900} 12901 12902// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 12903static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 12904 X86TargetLowering::DAGCombinerInfo &DCI) { 12905 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 12906 // the result is either zero or one (depending on the input carry bit). 12907 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 12908 if (X86::isZeroNode(N->getOperand(0)) && 12909 X86::isZeroNode(N->getOperand(1)) && 12910 // We don't have a good way to replace an EFLAGS use, so only do this when 12911 // dead right now. 12912 SDValue(N, 1).use_empty()) { 12913 DebugLoc DL = N->getDebugLoc(); 12914 EVT VT = N->getValueType(0); 12915 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 12916 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 12917 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 12918 DAG.getConstant(X86::COND_B,MVT::i8), 12919 N->getOperand(2)), 12920 DAG.getConstant(1, VT)); 12921 return DCI.CombineTo(N, Res1, CarryOut); 12922 } 12923 12924 return SDValue(); 12925} 12926 12927// fold (add Y, (sete X, 0)) -> adc 0, Y 12928// (add Y, (setne X, 0)) -> sbb -1, Y 12929// (sub (sete X, 0), Y) -> sbb 0, Y 12930// (sub (setne X, 0), Y) -> adc -1, Y 12931static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 12932 DebugLoc DL = N->getDebugLoc(); 12933 12934 // Look through ZExts. 12935 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 12936 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 12937 return SDValue(); 12938 12939 SDValue SetCC = Ext.getOperand(0); 12940 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 12941 return SDValue(); 12942 12943 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 12944 if (CC != X86::COND_E && CC != X86::COND_NE) 12945 return SDValue(); 12946 12947 SDValue Cmp = SetCC.getOperand(1); 12948 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 12949 !X86::isZeroNode(Cmp.getOperand(1)) || 12950 !Cmp.getOperand(0).getValueType().isInteger()) 12951 return SDValue(); 12952 12953 SDValue CmpOp0 = Cmp.getOperand(0); 12954 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 12955 DAG.getConstant(1, CmpOp0.getValueType())); 12956 12957 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 12958 if (CC == X86::COND_NE) 12959 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 12960 DL, OtherVal.getValueType(), OtherVal, 12961 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 12962 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 12963 DL, OtherVal.getValueType(), OtherVal, 12964 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 12965} 12966 12967static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { 12968 SDValue Op0 = N->getOperand(0); 12969 SDValue Op1 = N->getOperand(1); 12970 12971 // X86 can't encode an immediate LHS of a sub. See if we can push the 12972 // negation into a preceding instruction. 12973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 12974 uint64_t Op0C = C->getSExtValue(); 12975 12976 // If the RHS of the sub is a XOR with one use and a constant, invert the 12977 // immediate. Then add one to the LHS of the sub so we can turn 12978 // X-Y -> X+~Y+1, saving one register. 12979 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 12980 isa<ConstantSDNode>(Op1.getOperand(1))) { 12981 uint64_t XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getSExtValue(); 12982 EVT VT = Op0.getValueType(); 12983 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 12984 Op1.getOperand(0), 12985 DAG.getConstant(~XorC, VT)); 12986 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 12987 DAG.getConstant(Op0C+1, VT)); 12988 } 12989 } 12990 12991 return OptimizeConditionalInDecrement(N, DAG); 12992} 12993 12994SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 12995 DAGCombinerInfo &DCI) const { 12996 SelectionDAG &DAG = DCI.DAG; 12997 switch (N->getOpcode()) { 12998 default: break; 12999 case ISD::EXTRACT_VECTOR_ELT: 13000 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 13001 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 13002 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 13003 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); 13004 case ISD::SUB: return PerformSubCombine(N, DAG); 13005 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 13006 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 13007 case ISD::SHL: 13008 case ISD::SRA: 13009 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 13010 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 13011 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 13012 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 13013 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 13014 case X86ISD::FXOR: 13015 case X86ISD::FOR: return PerformFORCombine(N, DAG); 13016 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 13017 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 13018 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 13019 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 13020 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 13021 case X86ISD::SHUFPS: // Handle all target specific shuffles 13022 case X86ISD::SHUFPD: 13023 case X86ISD::PALIGN: 13024 case X86ISD::PUNPCKHBW: 13025 case X86ISD::PUNPCKHWD: 13026 case X86ISD::PUNPCKHDQ: 13027 case X86ISD::PUNPCKHQDQ: 13028 case X86ISD::UNPCKHPS: 13029 case X86ISD::UNPCKHPD: 13030 case X86ISD::VUNPCKHPSY: 13031 case X86ISD::VUNPCKHPDY: 13032 case X86ISD::PUNPCKLBW: 13033 case X86ISD::PUNPCKLWD: 13034 case X86ISD::PUNPCKLDQ: 13035 case X86ISD::PUNPCKLQDQ: 13036 case X86ISD::UNPCKLPS: 13037 case X86ISD::UNPCKLPD: 13038 case X86ISD::VUNPCKLPSY: 13039 case X86ISD::VUNPCKLPDY: 13040 case X86ISD::MOVHLPS: 13041 case X86ISD::MOVLHPS: 13042 case X86ISD::PSHUFD: 13043 case X86ISD::PSHUFHW: 13044 case X86ISD::PSHUFLW: 13045 case X86ISD::MOVSS: 13046 case X86ISD::MOVSD: 13047 case X86ISD::VPERMILPS: 13048 case X86ISD::VPERMILPSY: 13049 case X86ISD::VPERMILPD: 13050 case X86ISD::VPERMILPDY: 13051 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI); 13052 } 13053 13054 return SDValue(); 13055} 13056 13057/// isTypeDesirableForOp - Return true if the target has native support for 13058/// the specified value type and it is 'desirable' to use the type for the 13059/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 13060/// instruction encodings are longer and some i16 instructions are slow. 13061bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 13062 if (!isTypeLegal(VT)) 13063 return false; 13064 if (VT != MVT::i16) 13065 return true; 13066 13067 switch (Opc) { 13068 default: 13069 return true; 13070 case ISD::LOAD: 13071 case ISD::SIGN_EXTEND: 13072 case ISD::ZERO_EXTEND: 13073 case ISD::ANY_EXTEND: 13074 case ISD::SHL: 13075 case ISD::SRL: 13076 case ISD::SUB: 13077 case ISD::ADD: 13078 case ISD::MUL: 13079 case ISD::AND: 13080 case ISD::OR: 13081 case ISD::XOR: 13082 return false; 13083 } 13084} 13085 13086/// IsDesirableToPromoteOp - This method query the target whether it is 13087/// beneficial for dag combiner to promote the specified node. If true, it 13088/// should return the desired promotion type by reference. 13089bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 13090 EVT VT = Op.getValueType(); 13091 if (VT != MVT::i16) 13092 return false; 13093 13094 bool Promote = false; 13095 bool Commute = false; 13096 switch (Op.getOpcode()) { 13097 default: break; 13098 case ISD::LOAD: { 13099 LoadSDNode *LD = cast<LoadSDNode>(Op); 13100 // If the non-extending load has a single use and it's not live out, then it 13101 // might be folded. 13102 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 13103 Op.hasOneUse()*/) { 13104 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 13105 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 13106 // The only case where we'd want to promote LOAD (rather then it being 13107 // promoted as an operand is when it's only use is liveout. 13108 if (UI->getOpcode() != ISD::CopyToReg) 13109 return false; 13110 } 13111 } 13112 Promote = true; 13113 break; 13114 } 13115 case ISD::SIGN_EXTEND: 13116 case ISD::ZERO_EXTEND: 13117 case ISD::ANY_EXTEND: 13118 Promote = true; 13119 break; 13120 case ISD::SHL: 13121 case ISD::SRL: { 13122 SDValue N0 = Op.getOperand(0); 13123 // Look out for (store (shl (load), x)). 13124 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 13125 return false; 13126 Promote = true; 13127 break; 13128 } 13129 case ISD::ADD: 13130 case ISD::MUL: 13131 case ISD::AND: 13132 case ISD::OR: 13133 case ISD::XOR: 13134 Commute = true; 13135 // fallthrough 13136 case ISD::SUB: { 13137 SDValue N0 = Op.getOperand(0); 13138 SDValue N1 = Op.getOperand(1); 13139 if (!Commute && MayFoldLoad(N1)) 13140 return false; 13141 // Avoid disabling potential load folding opportunities. 13142 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 13143 return false; 13144 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 13145 return false; 13146 Promote = true; 13147 } 13148 } 13149 13150 PVT = MVT::i32; 13151 return Promote; 13152} 13153 13154//===----------------------------------------------------------------------===// 13155// X86 Inline Assembly Support 13156//===----------------------------------------------------------------------===// 13157 13158bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 13159 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 13160 13161 std::string AsmStr = IA->getAsmString(); 13162 13163 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 13164 SmallVector<StringRef, 4> AsmPieces; 13165 SplitString(AsmStr, AsmPieces, ";\n"); 13166 13167 switch (AsmPieces.size()) { 13168 default: return false; 13169 case 1: 13170 AsmStr = AsmPieces[0]; 13171 AsmPieces.clear(); 13172 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 13173 13174 // FIXME: this should verify that we are targeting a 486 or better. If not, 13175 // we will turn this bswap into something that will be lowered to logical ops 13176 // instead of emitting the bswap asm. For now, we don't support 486 or lower 13177 // so don't worry about this. 13178 // bswap $0 13179 if (AsmPieces.size() == 2 && 13180 (AsmPieces[0] == "bswap" || 13181 AsmPieces[0] == "bswapq" || 13182 AsmPieces[0] == "bswapl") && 13183 (AsmPieces[1] == "$0" || 13184 AsmPieces[1] == "${0:q}")) { 13185 // No need to check constraints, nothing other than the equivalent of 13186 // "=r,0" would be valid here. 13187 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13188 if (!Ty || Ty->getBitWidth() % 16 != 0) 13189 return false; 13190 return IntrinsicLowering::LowerToByteSwap(CI); 13191 } 13192 // rorw $$8, ${0:w} --> llvm.bswap.i16 13193 if (CI->getType()->isIntegerTy(16) && 13194 AsmPieces.size() == 3 && 13195 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 13196 AsmPieces[1] == "$$8," && 13197 AsmPieces[2] == "${0:w}" && 13198 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 13199 AsmPieces.clear(); 13200 const std::string &ConstraintsStr = IA->getConstraintString(); 13201 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 13202 std::sort(AsmPieces.begin(), AsmPieces.end()); 13203 if (AsmPieces.size() == 4 && 13204 AsmPieces[0] == "~{cc}" && 13205 AsmPieces[1] == "~{dirflag}" && 13206 AsmPieces[2] == "~{flags}" && 13207 AsmPieces[3] == "~{fpsr}") { 13208 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13209 if (!Ty || Ty->getBitWidth() % 16 != 0) 13210 return false; 13211 return IntrinsicLowering::LowerToByteSwap(CI); 13212 } 13213 } 13214 break; 13215 case 3: 13216 if (CI->getType()->isIntegerTy(32) && 13217 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 13218 SmallVector<StringRef, 4> Words; 13219 SplitString(AsmPieces[0], Words, " \t,"); 13220 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 13221 Words[2] == "${0:w}") { 13222 Words.clear(); 13223 SplitString(AsmPieces[1], Words, " \t,"); 13224 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 13225 Words[2] == "$0") { 13226 Words.clear(); 13227 SplitString(AsmPieces[2], Words, " \t,"); 13228 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 13229 Words[2] == "${0:w}") { 13230 AsmPieces.clear(); 13231 const std::string &ConstraintsStr = IA->getConstraintString(); 13232 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 13233 std::sort(AsmPieces.begin(), AsmPieces.end()); 13234 if (AsmPieces.size() == 4 && 13235 AsmPieces[0] == "~{cc}" && 13236 AsmPieces[1] == "~{dirflag}" && 13237 AsmPieces[2] == "~{flags}" && 13238 AsmPieces[3] == "~{fpsr}") { 13239 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13240 if (!Ty || Ty->getBitWidth() % 16 != 0) 13241 return false; 13242 return IntrinsicLowering::LowerToByteSwap(CI); 13243 } 13244 } 13245 } 13246 } 13247 } 13248 13249 if (CI->getType()->isIntegerTy(64)) { 13250 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 13251 if (Constraints.size() >= 2 && 13252 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 13253 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 13254 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 13255 SmallVector<StringRef, 4> Words; 13256 SplitString(AsmPieces[0], Words, " \t"); 13257 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 13258 Words.clear(); 13259 SplitString(AsmPieces[1], Words, " \t"); 13260 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 13261 Words.clear(); 13262 SplitString(AsmPieces[2], Words, " \t,"); 13263 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 13264 Words[2] == "%edx") { 13265 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 13266 if (!Ty || Ty->getBitWidth() % 16 != 0) 13267 return false; 13268 return IntrinsicLowering::LowerToByteSwap(CI); 13269 } 13270 } 13271 } 13272 } 13273 } 13274 break; 13275 } 13276 return false; 13277} 13278 13279 13280 13281/// getConstraintType - Given a constraint letter, return the type of 13282/// constraint it is for this target. 13283X86TargetLowering::ConstraintType 13284X86TargetLowering::getConstraintType(const std::string &Constraint) const { 13285 if (Constraint.size() == 1) { 13286 switch (Constraint[0]) { 13287 case 'R': 13288 case 'q': 13289 case 'Q': 13290 case 'f': 13291 case 't': 13292 case 'u': 13293 case 'y': 13294 case 'x': 13295 case 'Y': 13296 case 'l': 13297 return C_RegisterClass; 13298 case 'a': 13299 case 'b': 13300 case 'c': 13301 case 'd': 13302 case 'S': 13303 case 'D': 13304 case 'A': 13305 return C_Register; 13306 case 'I': 13307 case 'J': 13308 case 'K': 13309 case 'L': 13310 case 'M': 13311 case 'N': 13312 case 'G': 13313 case 'C': 13314 case 'e': 13315 case 'Z': 13316 return C_Other; 13317 default: 13318 break; 13319 } 13320 } 13321 return TargetLowering::getConstraintType(Constraint); 13322} 13323 13324/// Examine constraint type and operand type and determine a weight value. 13325/// This object must already have been set up with the operand type 13326/// and the current alternative constraint selected. 13327TargetLowering::ConstraintWeight 13328 X86TargetLowering::getSingleConstraintMatchWeight( 13329 AsmOperandInfo &info, const char *constraint) const { 13330 ConstraintWeight weight = CW_Invalid; 13331 Value *CallOperandVal = info.CallOperandVal; 13332 // If we don't have a value, we can't do a match, 13333 // but allow it at the lowest weight. 13334 if (CallOperandVal == NULL) 13335 return CW_Default; 13336 Type *type = CallOperandVal->getType(); 13337 // Look at the constraint type. 13338 switch (*constraint) { 13339 default: 13340 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 13341 case 'R': 13342 case 'q': 13343 case 'Q': 13344 case 'a': 13345 case 'b': 13346 case 'c': 13347 case 'd': 13348 case 'S': 13349 case 'D': 13350 case 'A': 13351 if (CallOperandVal->getType()->isIntegerTy()) 13352 weight = CW_SpecificReg; 13353 break; 13354 case 'f': 13355 case 't': 13356 case 'u': 13357 if (type->isFloatingPointTy()) 13358 weight = CW_SpecificReg; 13359 break; 13360 case 'y': 13361 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 13362 weight = CW_SpecificReg; 13363 break; 13364 case 'x': 13365 case 'Y': 13366 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 13367 weight = CW_Register; 13368 break; 13369 case 'I': 13370 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 13371 if (C->getZExtValue() <= 31) 13372 weight = CW_Constant; 13373 } 13374 break; 13375 case 'J': 13376 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13377 if (C->getZExtValue() <= 63) 13378 weight = CW_Constant; 13379 } 13380 break; 13381 case 'K': 13382 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13383 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 13384 weight = CW_Constant; 13385 } 13386 break; 13387 case 'L': 13388 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13389 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 13390 weight = CW_Constant; 13391 } 13392 break; 13393 case 'M': 13394 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13395 if (C->getZExtValue() <= 3) 13396 weight = CW_Constant; 13397 } 13398 break; 13399 case 'N': 13400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13401 if (C->getZExtValue() <= 0xff) 13402 weight = CW_Constant; 13403 } 13404 break; 13405 case 'G': 13406 case 'C': 13407 if (dyn_cast<ConstantFP>(CallOperandVal)) { 13408 weight = CW_Constant; 13409 } 13410 break; 13411 case 'e': 13412 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13413 if ((C->getSExtValue() >= -0x80000000LL) && 13414 (C->getSExtValue() <= 0x7fffffffLL)) 13415 weight = CW_Constant; 13416 } 13417 break; 13418 case 'Z': 13419 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 13420 if (C->getZExtValue() <= 0xffffffff) 13421 weight = CW_Constant; 13422 } 13423 break; 13424 } 13425 return weight; 13426} 13427 13428/// LowerXConstraint - try to replace an X constraint, which matches anything, 13429/// with another that has more specific requirements based on the type of the 13430/// corresponding operand. 13431const char *X86TargetLowering:: 13432LowerXConstraint(EVT ConstraintVT) const { 13433 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 13434 // 'f' like normal targets. 13435 if (ConstraintVT.isFloatingPoint()) { 13436 if (Subtarget->hasXMMInt()) 13437 return "Y"; 13438 if (Subtarget->hasXMM()) 13439 return "x"; 13440 } 13441 13442 return TargetLowering::LowerXConstraint(ConstraintVT); 13443} 13444 13445/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 13446/// vector. If it is invalid, don't add anything to Ops. 13447void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 13448 std::string &Constraint, 13449 std::vector<SDValue>&Ops, 13450 SelectionDAG &DAG) const { 13451 SDValue Result(0, 0); 13452 13453 // Only support length 1 constraints for now. 13454 if (Constraint.length() > 1) return; 13455 13456 char ConstraintLetter = Constraint[0]; 13457 switch (ConstraintLetter) { 13458 default: break; 13459 case 'I': 13460 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13461 if (C->getZExtValue() <= 31) { 13462 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13463 break; 13464 } 13465 } 13466 return; 13467 case 'J': 13468 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13469 if (C->getZExtValue() <= 63) { 13470 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13471 break; 13472 } 13473 } 13474 return; 13475 case 'K': 13476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13477 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 13478 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13479 break; 13480 } 13481 } 13482 return; 13483 case 'N': 13484 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13485 if (C->getZExtValue() <= 255) { 13486 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13487 break; 13488 } 13489 } 13490 return; 13491 case 'e': { 13492 // 32-bit signed value 13493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13494 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 13495 C->getSExtValue())) { 13496 // Widen to 64 bits here to get it sign extended. 13497 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 13498 break; 13499 } 13500 // FIXME gcc accepts some relocatable values here too, but only in certain 13501 // memory models; it's complicated. 13502 } 13503 return; 13504 } 13505 case 'Z': { 13506 // 32-bit unsigned value 13507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 13508 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 13509 C->getZExtValue())) { 13510 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 13511 break; 13512 } 13513 } 13514 // FIXME gcc accepts some relocatable values here too, but only in certain 13515 // memory models; it's complicated. 13516 return; 13517 } 13518 case 'i': { 13519 // Literal immediates are always ok. 13520 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 13521 // Widen to 64 bits here to get it sign extended. 13522 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 13523 break; 13524 } 13525 13526 // In any sort of PIC mode addresses need to be computed at runtime by 13527 // adding in a register or some sort of table lookup. These can't 13528 // be used as immediates. 13529 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 13530 return; 13531 13532 // If we are in non-pic codegen mode, we allow the address of a global (with 13533 // an optional displacement) to be used with 'i'. 13534 GlobalAddressSDNode *GA = 0; 13535 int64_t Offset = 0; 13536 13537 // Match either (GA), (GA+C), (GA+C1+C2), etc. 13538 while (1) { 13539 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 13540 Offset += GA->getOffset(); 13541 break; 13542 } else if (Op.getOpcode() == ISD::ADD) { 13543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 13544 Offset += C->getZExtValue(); 13545 Op = Op.getOperand(0); 13546 continue; 13547 } 13548 } else if (Op.getOpcode() == ISD::SUB) { 13549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 13550 Offset += -C->getZExtValue(); 13551 Op = Op.getOperand(0); 13552 continue; 13553 } 13554 } 13555 13556 // Otherwise, this isn't something we can handle, reject it. 13557 return; 13558 } 13559 13560 const GlobalValue *GV = GA->getGlobal(); 13561 // If we require an extra load to get this address, as in PIC mode, we 13562 // can't accept it. 13563 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 13564 getTargetMachine()))) 13565 return; 13566 13567 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 13568 GA->getValueType(0), Offset); 13569 break; 13570 } 13571 } 13572 13573 if (Result.getNode()) { 13574 Ops.push_back(Result); 13575 return; 13576 } 13577 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 13578} 13579 13580std::pair<unsigned, const TargetRegisterClass*> 13581X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 13582 EVT VT) const { 13583 // First, see if this is a constraint that directly corresponds to an LLVM 13584 // register class. 13585 if (Constraint.size() == 1) { 13586 // GCC Constraint Letters 13587 switch (Constraint[0]) { 13588 default: break; 13589 // TODO: Slight differences here in allocation order and leaving 13590 // RIP in the class. Do they matter any more here than they do 13591 // in the normal allocation? 13592 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 13593 if (Subtarget->is64Bit()) { 13594 if (VT == MVT::i32 || VT == MVT::f32) 13595 return std::make_pair(0U, X86::GR32RegisterClass); 13596 else if (VT == MVT::i16) 13597 return std::make_pair(0U, X86::GR16RegisterClass); 13598 else if (VT == MVT::i8 || VT == MVT::i1) 13599 return std::make_pair(0U, X86::GR8RegisterClass); 13600 else if (VT == MVT::i64 || VT == MVT::f64) 13601 return std::make_pair(0U, X86::GR64RegisterClass); 13602 break; 13603 } 13604 // 32-bit fallthrough 13605 case 'Q': // Q_REGS 13606 if (VT == MVT::i32 || VT == MVT::f32) 13607 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 13608 else if (VT == MVT::i16) 13609 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 13610 else if (VT == MVT::i8 || VT == MVT::i1) 13611 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 13612 else if (VT == MVT::i64) 13613 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 13614 break; 13615 case 'r': // GENERAL_REGS 13616 case 'l': // INDEX_REGS 13617 if (VT == MVT::i8 || VT == MVT::i1) 13618 return std::make_pair(0U, X86::GR8RegisterClass); 13619 if (VT == MVT::i16) 13620 return std::make_pair(0U, X86::GR16RegisterClass); 13621 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 13622 return std::make_pair(0U, X86::GR32RegisterClass); 13623 return std::make_pair(0U, X86::GR64RegisterClass); 13624 case 'R': // LEGACY_REGS 13625 if (VT == MVT::i8 || VT == MVT::i1) 13626 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 13627 if (VT == MVT::i16) 13628 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 13629 if (VT == MVT::i32 || !Subtarget->is64Bit()) 13630 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 13631 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 13632 case 'f': // FP Stack registers. 13633 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 13634 // value to the correct fpstack register class. 13635 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 13636 return std::make_pair(0U, X86::RFP32RegisterClass); 13637 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 13638 return std::make_pair(0U, X86::RFP64RegisterClass); 13639 return std::make_pair(0U, X86::RFP80RegisterClass); 13640 case 'y': // MMX_REGS if MMX allowed. 13641 if (!Subtarget->hasMMX()) break; 13642 return std::make_pair(0U, X86::VR64RegisterClass); 13643 case 'Y': // SSE_REGS if SSE2 allowed 13644 if (!Subtarget->hasXMMInt()) break; 13645 // FALL THROUGH. 13646 case 'x': // SSE_REGS if SSE1 allowed 13647 if (!Subtarget->hasXMM()) break; 13648 13649 switch (VT.getSimpleVT().SimpleTy) { 13650 default: break; 13651 // Scalar SSE types. 13652 case MVT::f32: 13653 case MVT::i32: 13654 return std::make_pair(0U, X86::FR32RegisterClass); 13655 case MVT::f64: 13656 case MVT::i64: 13657 return std::make_pair(0U, X86::FR64RegisterClass); 13658 // Vector types. 13659 case MVT::v16i8: 13660 case MVT::v8i16: 13661 case MVT::v4i32: 13662 case MVT::v2i64: 13663 case MVT::v4f32: 13664 case MVT::v2f64: 13665 return std::make_pair(0U, X86::VR128RegisterClass); 13666 } 13667 break; 13668 } 13669 } 13670 13671 // Use the default implementation in TargetLowering to convert the register 13672 // constraint into a member of a register class. 13673 std::pair<unsigned, const TargetRegisterClass*> Res; 13674 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 13675 13676 // Not found as a standard register? 13677 if (Res.second == 0) { 13678 // Map st(0) -> st(7) -> ST0 13679 if (Constraint.size() == 7 && Constraint[0] == '{' && 13680 tolower(Constraint[1]) == 's' && 13681 tolower(Constraint[2]) == 't' && 13682 Constraint[3] == '(' && 13683 (Constraint[4] >= '0' && Constraint[4] <= '7') && 13684 Constraint[5] == ')' && 13685 Constraint[6] == '}') { 13686 13687 Res.first = X86::ST0+Constraint[4]-'0'; 13688 Res.second = X86::RFP80RegisterClass; 13689 return Res; 13690 } 13691 13692 // GCC allows "st(0)" to be called just plain "st". 13693 if (StringRef("{st}").equals_lower(Constraint)) { 13694 Res.first = X86::ST0; 13695 Res.second = X86::RFP80RegisterClass; 13696 return Res; 13697 } 13698 13699 // flags -> EFLAGS 13700 if (StringRef("{flags}").equals_lower(Constraint)) { 13701 Res.first = X86::EFLAGS; 13702 Res.second = X86::CCRRegisterClass; 13703 return Res; 13704 } 13705 13706 // 'A' means EAX + EDX. 13707 if (Constraint == "A") { 13708 Res.first = X86::EAX; 13709 Res.second = X86::GR32_ADRegisterClass; 13710 return Res; 13711 } 13712 return Res; 13713 } 13714 13715 // Otherwise, check to see if this is a register class of the wrong value 13716 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 13717 // turn into {ax},{dx}. 13718 if (Res.second->hasType(VT)) 13719 return Res; // Correct type already, nothing to do. 13720 13721 // All of the single-register GCC register classes map their values onto 13722 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 13723 // really want an 8-bit or 32-bit register, map to the appropriate register 13724 // class and return the appropriate register. 13725 if (Res.second == X86::GR16RegisterClass) { 13726 if (VT == MVT::i8) { 13727 unsigned DestReg = 0; 13728 switch (Res.first) { 13729 default: break; 13730 case X86::AX: DestReg = X86::AL; break; 13731 case X86::DX: DestReg = X86::DL; break; 13732 case X86::CX: DestReg = X86::CL; break; 13733 case X86::BX: DestReg = X86::BL; break; 13734 } 13735 if (DestReg) { 13736 Res.first = DestReg; 13737 Res.second = X86::GR8RegisterClass; 13738 } 13739 } else if (VT == MVT::i32) { 13740 unsigned DestReg = 0; 13741 switch (Res.first) { 13742 default: break; 13743 case X86::AX: DestReg = X86::EAX; break; 13744 case X86::DX: DestReg = X86::EDX; break; 13745 case X86::CX: DestReg = X86::ECX; break; 13746 case X86::BX: DestReg = X86::EBX; break; 13747 case X86::SI: DestReg = X86::ESI; break; 13748 case X86::DI: DestReg = X86::EDI; break; 13749 case X86::BP: DestReg = X86::EBP; break; 13750 case X86::SP: DestReg = X86::ESP; break; 13751 } 13752 if (DestReg) { 13753 Res.first = DestReg; 13754 Res.second = X86::GR32RegisterClass; 13755 } 13756 } else if (VT == MVT::i64) { 13757 unsigned DestReg = 0; 13758 switch (Res.first) { 13759 default: break; 13760 case X86::AX: DestReg = X86::RAX; break; 13761 case X86::DX: DestReg = X86::RDX; break; 13762 case X86::CX: DestReg = X86::RCX; break; 13763 case X86::BX: DestReg = X86::RBX; break; 13764 case X86::SI: DestReg = X86::RSI; break; 13765 case X86::DI: DestReg = X86::RDI; break; 13766 case X86::BP: DestReg = X86::RBP; break; 13767 case X86::SP: DestReg = X86::RSP; break; 13768 } 13769 if (DestReg) { 13770 Res.first = DestReg; 13771 Res.second = X86::GR64RegisterClass; 13772 } 13773 } 13774 } else if (Res.second == X86::FR32RegisterClass || 13775 Res.second == X86::FR64RegisterClass || 13776 Res.second == X86::VR128RegisterClass) { 13777 // Handle references to XMM physical registers that got mapped into the 13778 // wrong class. This can happen with constraints like {xmm0} where the 13779 // target independent register mapper will just pick the first match it can 13780 // find, ignoring the required type. 13781 if (VT == MVT::f32) 13782 Res.second = X86::FR32RegisterClass; 13783 else if (VT == MVT::f64) 13784 Res.second = X86::FR64RegisterClass; 13785 else if (X86::VR128RegisterClass->hasType(VT)) 13786 Res.second = X86::VR128RegisterClass; 13787 } 13788 13789 return Res; 13790} 13791