X86ISelLowering.cpp revision 62a3f1538cf50f0373c2a5eeb440d6288604f969
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Function.h" 25#include "llvm/Intrinsics.h" 26#include "llvm/ADT/BitVector.h" 27#include "llvm/ADT/VectorExtras.h" 28#include "llvm/Analysis/ScalarEvolutionExpressions.h" 29#include "llvm/CodeGen/CallingConvLower.h" 30#include "llvm/CodeGen/MachineFrameInfo.h" 31#include "llvm/CodeGen/MachineFunction.h" 32#include "llvm/CodeGen/MachineInstrBuilder.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/PseudoSourceValue.h" 36#include "llvm/CodeGen/SelectionDAG.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Target/TargetOptions.h" 40#include "llvm/ADT/SmallSet.h" 41#include "llvm/ADT/StringExtras.h" 42using namespace llvm; 43 44X86TargetLowering::X86TargetLowering(TargetMachine &TM) 45 : TargetLowering(TM) { 46 Subtarget = &TM.getSubtarget<X86Subtarget>(); 47 X86ScalarSSEf64 = Subtarget->hasSSE2(); 48 X86ScalarSSEf32 = Subtarget->hasSSE1(); 49 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 50 51 bool Fast = false; 52 53 RegInfo = TM.getRegisterInfo(); 54 55 // Set up the TargetLowering object. 56 57 // X86 is weird, it always uses i8 for shift amounts and setcc results. 58 setShiftAmountType(MVT::i8); 59 setSetCCResultContents(ZeroOrOneSetCCResult); 60 setSchedulingPreference(SchedulingForRegPressure); 61 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0 62 setStackPointerRegisterToSaveRestore(X86StackPtr); 63 64 if (Subtarget->isTargetDarwin()) { 65 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 66 setUseUnderscoreSetJmp(false); 67 setUseUnderscoreLongJmp(false); 68 } else if (Subtarget->isTargetMingw()) { 69 // MS runtime is weird: it exports _setjmp, but longjmp! 70 setUseUnderscoreSetJmp(true); 71 setUseUnderscoreLongJmp(false); 72 } else { 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 } 76 77 // Set up the register classes. 78 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 79 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 80 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 81 if (Subtarget->is64Bit()) 82 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 83 84 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 85 86 // We don't accept any truncstore of integer registers. 87 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 88 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 89 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 90 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 91 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 92 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 93 94 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 95 // operation. 96 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 97 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 98 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 99 100 if (Subtarget->is64Bit()) { 101 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 102 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 103 } else { 104 if (X86ScalarSSEf64) 105 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP. 106 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand); 107 else 108 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 109 } 110 111 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 112 // this operation. 113 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 114 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 115 // SSE has no i16 to fp conversion, only i32 116 if (X86ScalarSSEf32) { 117 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 118 // f32 and f64 cases are Legal, f80 case is not 119 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 120 } else { 121 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 123 } 124 125 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 126 // are Legal, f80 is custom lowered. 127 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 128 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 129 130 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 131 // this operation. 132 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 133 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 134 135 if (X86ScalarSSEf32) { 136 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 137 // f32 and f64 cases are Legal, f80 case is not 138 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 139 } else { 140 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 142 } 143 144 // Handle FP_TO_UINT by promoting the destination to a larger signed 145 // conversion. 146 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 147 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 148 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 149 150 if (Subtarget->is64Bit()) { 151 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 152 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 153 } else { 154 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 155 // Expand FP_TO_UINT into a select. 156 // FIXME: We would like to use a Custom expander here eventually to do 157 // the optimal thing for SSE vs. the default expansion in the legalizer. 158 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 159 else 160 // With SSE3 we can use fisttpll to convert to a signed i64. 161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 162 } 163 164 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 165 if (!X86ScalarSSEf64) { 166 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 167 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 168 } 169 170 // Scalar integer divide and remainder are lowered to use operations that 171 // produce two results, to match the available instructions. This exposes 172 // the two-result form to trivial CSE, which is able to combine x/y and x%y 173 // into a single instruction. 174 // 175 // Scalar integer multiply-high is also lowered to use two-result 176 // operations, to match the available instructions. However, plain multiply 177 // (low) operations are left as Legal, as there are single-result 178 // instructions for this in x86. Using the two-result multiply instructions 179 // when both high and low results are needed must be arranged by dagcombine. 180 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 181 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 182 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 183 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 184 setOperationAction(ISD::SREM , MVT::i8 , Expand); 185 setOperationAction(ISD::UREM , MVT::i8 , Expand); 186 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 187 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 188 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 189 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 190 setOperationAction(ISD::SREM , MVT::i16 , Expand); 191 setOperationAction(ISD::UREM , MVT::i16 , Expand); 192 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 193 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 194 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 195 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 196 setOperationAction(ISD::SREM , MVT::i32 , Expand); 197 setOperationAction(ISD::UREM , MVT::i32 , Expand); 198 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 199 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 200 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 201 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 202 setOperationAction(ISD::SREM , MVT::i64 , Expand); 203 setOperationAction(ISD::UREM , MVT::i64 , Expand); 204 205 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 206 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 207 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 208 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 209 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 210 if (Subtarget->is64Bit()) 211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 215 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 216 setOperationAction(ISD::FREM , MVT::f32 , Expand); 217 setOperationAction(ISD::FREM , MVT::f64 , Expand); 218 setOperationAction(ISD::FREM , MVT::f80 , Expand); 219 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 220 221 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 222 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 223 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 224 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 225 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 226 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 227 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 228 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 229 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 230 if (Subtarget->is64Bit()) { 231 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 232 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 233 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 234 } 235 236 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 237 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 238 239 // These should be promoted to a larger select which is supported. 240 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 241 setOperationAction(ISD::SELECT , MVT::i8 , Promote); 242 // X86 wants to expand cmov itself. 243 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 244 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 245 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 246 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 247 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 248 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 249 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 250 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 251 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 252 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 253 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 254 if (Subtarget->is64Bit()) { 255 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 256 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 257 } 258 // X86 ret instruction may pop stack. 259 setOperationAction(ISD::RET , MVT::Other, Custom); 260 if (!Subtarget->is64Bit()) 261 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 262 263 // Darwin ABI issue. 264 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 265 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 266 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 267 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 268 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 269 if (Subtarget->is64Bit()) { 270 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 271 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 272 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 273 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 274 } 275 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 276 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 277 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 278 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 279 if (Subtarget->is64Bit()) { 280 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 281 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 282 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 283 } 284 // X86 wants to expand memset / memcpy itself. 285 setOperationAction(ISD::MEMSET , MVT::Other, Custom); 286 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 287 288 if (Subtarget->hasSSE1()) 289 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 290 291 if (!Subtarget->hasSSE2()) 292 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 293 294 setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom); 295 setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom); 296 setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom); 297 setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom); 298 299 // Use the default ISD::LOCATION, ISD::DECLARE expansion. 300 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 301 // FIXME - use subtarget debug flags 302 if (!Subtarget->isTargetDarwin() && 303 !Subtarget->isTargetELF() && 304 !Subtarget->isTargetCygMing()) 305 setOperationAction(ISD::LABEL, MVT::Other, Expand); 306 307 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 308 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 309 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 310 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 311 if (Subtarget->is64Bit()) { 312 // FIXME: Verify 313 setExceptionPointerRegister(X86::RAX); 314 setExceptionSelectorRegister(X86::RDX); 315 } else { 316 setExceptionPointerRegister(X86::EAX); 317 setExceptionSelectorRegister(X86::EDX); 318 } 319 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 320 321 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 322 323 setOperationAction(ISD::TRAP, MVT::Other, Legal); 324 325 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 326 setOperationAction(ISD::VASTART , MVT::Other, Custom); 327 setOperationAction(ISD::VAARG , MVT::Other, Expand); 328 setOperationAction(ISD::VAEND , MVT::Other, Expand); 329 if (Subtarget->is64Bit()) 330 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 331 else 332 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 333 334 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 335 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 336 if (Subtarget->is64Bit()) 337 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 338 if (Subtarget->isTargetCygMing()) 339 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 340 else 341 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 342 343 if (X86ScalarSSEf64) { 344 // f32 and f64 use SSE. 345 // Set up the FP register classes. 346 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 347 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 348 349 // Use ANDPD to simulate FABS. 350 setOperationAction(ISD::FABS , MVT::f64, Custom); 351 setOperationAction(ISD::FABS , MVT::f32, Custom); 352 353 // Use XORP to simulate FNEG. 354 setOperationAction(ISD::FNEG , MVT::f64, Custom); 355 setOperationAction(ISD::FNEG , MVT::f32, Custom); 356 357 // Use ANDPD and ORPD to simulate FCOPYSIGN. 358 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 359 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 360 361 // We don't support sin/cos/fmod 362 setOperationAction(ISD::FSIN , MVT::f64, Expand); 363 setOperationAction(ISD::FCOS , MVT::f64, Expand); 364 setOperationAction(ISD::FSIN , MVT::f32, Expand); 365 setOperationAction(ISD::FCOS , MVT::f32, Expand); 366 367 // Expand FP immediates into loads from the stack, except for the special 368 // cases we handle. 369 addLegalFPImmediate(APFloat(+0.0)); // xorpd 370 addLegalFPImmediate(APFloat(+0.0f)); // xorps 371 372 // Floating truncations from f80 and extensions to f80 go through memory. 373 // If optimizing, we lie about this though and handle it in 374 // InstructionSelectPreprocess so that dagcombine2 can hack on these. 375 if (Fast) { 376 setConvertAction(MVT::f32, MVT::f80, Expand); 377 setConvertAction(MVT::f64, MVT::f80, Expand); 378 setConvertAction(MVT::f80, MVT::f32, Expand); 379 setConvertAction(MVT::f80, MVT::f64, Expand); 380 } 381 } else if (X86ScalarSSEf32) { 382 // Use SSE for f32, x87 for f64. 383 // Set up the FP register classes. 384 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 385 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 386 387 // Use ANDPS to simulate FABS. 388 setOperationAction(ISD::FABS , MVT::f32, Custom); 389 390 // Use XORP to simulate FNEG. 391 setOperationAction(ISD::FNEG , MVT::f32, Custom); 392 393 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 394 395 // Use ANDPS and ORPS to simulate FCOPYSIGN. 396 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 397 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 398 399 // We don't support sin/cos/fmod 400 setOperationAction(ISD::FSIN , MVT::f32, Expand); 401 setOperationAction(ISD::FCOS , MVT::f32, Expand); 402 403 // Special cases we handle for FP constants. 404 addLegalFPImmediate(APFloat(+0.0f)); // xorps 405 addLegalFPImmediate(APFloat(+0.0)); // FLD0 406 addLegalFPImmediate(APFloat(+1.0)); // FLD1 407 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 408 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 409 410 // SSE <-> X87 conversions go through memory. If optimizing, we lie about 411 // this though and handle it in InstructionSelectPreprocess so that 412 // dagcombine2 can hack on these. 413 if (Fast) { 414 setConvertAction(MVT::f32, MVT::f64, Expand); 415 setConvertAction(MVT::f32, MVT::f80, Expand); 416 setConvertAction(MVT::f80, MVT::f32, Expand); 417 setConvertAction(MVT::f64, MVT::f32, Expand); 418 // And x87->x87 truncations also. 419 setConvertAction(MVT::f80, MVT::f64, Expand); 420 } 421 422 if (!UnsafeFPMath) { 423 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 424 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 425 } 426 } else { 427 // f32 and f64 in x87. 428 // Set up the FP register classes. 429 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 430 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 431 432 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 433 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 434 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 435 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 436 437 // Floating truncations go through memory. If optimizing, we lie about 438 // this though and handle it in InstructionSelectPreprocess so that 439 // dagcombine2 can hack on these. 440 if (Fast) { 441 setConvertAction(MVT::f80, MVT::f32, Expand); 442 setConvertAction(MVT::f64, MVT::f32, Expand); 443 setConvertAction(MVT::f80, MVT::f64, Expand); 444 } 445 446 if (!UnsafeFPMath) { 447 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 448 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 449 } 450 addLegalFPImmediate(APFloat(+0.0)); // FLD0 451 addLegalFPImmediate(APFloat(+1.0)); // FLD1 452 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 453 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 454 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 455 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 456 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 457 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 458 } 459 460 // Long double always uses X87. 461 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 462 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 463 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 464 { 465 APFloat TmpFlt(+0.0); 466 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven); 467 addLegalFPImmediate(TmpFlt); // FLD0 468 TmpFlt.changeSign(); 469 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 470 APFloat TmpFlt2(+1.0); 471 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven); 472 addLegalFPImmediate(TmpFlt2); // FLD1 473 TmpFlt2.changeSign(); 474 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 475 } 476 477 if (!UnsafeFPMath) { 478 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 479 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 480 } 481 482 // Always use a library call for pow. 483 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 484 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 485 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 486 487 // First set operation action for all vector types to expand. Then we 488 // will selectively turn on ones that can be effectively codegen'd. 489 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 490 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 491 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); 492 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); 493 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand); 494 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 495 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand); 496 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 497 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand); 498 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 499 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 500 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 501 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 502 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 503 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand); 504 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); 505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 506 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 507 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand); 508 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand); 509 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand); 510 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand); 511 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand); 512 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand); 513 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand); 514 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 515 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 516 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 517 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 518 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); 519 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); 520 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); 521 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); 522 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand); 523 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand); 524 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand); 525 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand); 526 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand); 527 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand); 528 } 529 530 if (Subtarget->hasMMX()) { 531 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 532 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 533 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 534 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 535 536 // FIXME: add MMX packed arithmetics 537 538 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 539 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 540 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 541 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 542 543 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 544 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 545 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 546 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 547 548 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 549 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 550 551 setOperationAction(ISD::AND, MVT::v8i8, Promote); 552 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 553 setOperationAction(ISD::AND, MVT::v4i16, Promote); 554 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 555 setOperationAction(ISD::AND, MVT::v2i32, Promote); 556 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 557 setOperationAction(ISD::AND, MVT::v1i64, Legal); 558 559 setOperationAction(ISD::OR, MVT::v8i8, Promote); 560 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 561 setOperationAction(ISD::OR, MVT::v4i16, Promote); 562 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 563 setOperationAction(ISD::OR, MVT::v2i32, Promote); 564 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 565 setOperationAction(ISD::OR, MVT::v1i64, Legal); 566 567 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 568 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 569 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 570 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 571 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 572 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 573 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 574 575 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 576 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 577 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 578 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 579 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 580 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 581 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 582 583 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 584 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 585 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 586 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 587 588 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 589 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 590 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 591 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 592 593 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 594 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 595 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 596 } 597 598 if (Subtarget->hasSSE1()) { 599 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 600 601 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 602 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 603 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 604 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 605 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 606 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 607 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 608 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 609 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 610 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 611 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 612 } 613 614 if (Subtarget->hasSSE2()) { 615 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 616 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 617 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 618 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 619 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 620 621 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 622 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 623 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 624 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 625 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 626 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 627 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 628 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 629 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 630 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 631 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 632 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 633 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 634 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 635 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 636 637 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 638 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 639 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 640 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 641 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 642 643 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 644 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 645 // Do not attempt to custom lower non-power-of-2 vectors 646 if (!isPowerOf2_32(MVT::getVectorNumElements(VT))) 647 continue; 648 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom); 649 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom); 650 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom); 651 } 652 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 653 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 656 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 657 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 658 if (Subtarget->is64Bit()) { 659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 660 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 661 } 662 663 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 664 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) { 665 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote); 666 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64); 667 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote); 668 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64); 669 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote); 670 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64); 671 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote); 672 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64); 673 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 674 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64); 675 } 676 677 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 678 679 // Custom lower v2i64 and v2f64 selects. 680 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 681 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 682 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 683 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 684 } 685 686 if (Subtarget->hasSSE41()) { 687 // FIXME: Do we need to handle scalar-to-vector here? 688 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 689 690 // i8 and i16 vectors are custom , because the source register and source 691 // source memory operand types are not the same width. f32 vectors are 692 // custom since the immediate controlling the insert encodes additional 693 // information. 694 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 696 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); 697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 698 699 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 700 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 701 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); 702 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 703 704 if (Subtarget->is64Bit()) { 705 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 706 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 707 } 708 } 709 710 // We want to custom lower some of our intrinsics. 711 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 712 713 // We have target-specific dag combine patterns for the following nodes: 714 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 715 setTargetDAGCombine(ISD::SELECT); 716 setTargetDAGCombine(ISD::STORE); 717 718 computeRegisterProperties(); 719 720 // FIXME: These should be based on subtarget info. Plus, the values should 721 // be smaller when we are in optimizing for size mode. 722 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores 723 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores 724 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores 725 allowUnalignedMemoryAccesses = true; // x86 supports it! 726 setPrefLoopAlignment(16); 727} 728 729 730MVT::ValueType 731X86TargetLowering::getSetCCResultType(const SDOperand &) const { 732 return MVT::i8; 733} 734 735 736/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 737/// the desired ByVal argument alignment. 738static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 739 if (MaxAlign == 16) 740 return; 741 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 742 if (VTy->getBitWidth() == 128) 743 MaxAlign = 16; 744 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 745 unsigned EltAlign = 0; 746 getMaxByValAlign(ATy->getElementType(), EltAlign); 747 if (EltAlign > MaxAlign) 748 MaxAlign = EltAlign; 749 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 751 unsigned EltAlign = 0; 752 getMaxByValAlign(STy->getElementType(i), EltAlign); 753 if (EltAlign > MaxAlign) 754 MaxAlign = EltAlign; 755 if (MaxAlign == 16) 756 break; 757 } 758 } 759 return; 760} 761 762/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 763/// function arguments in the caller parameter area. For X86, aggregates 764/// that contain SSE vectors are placed at 16-byte boundaries while the rest 765/// are at 4-byte boundaries. 766unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 767 if (Subtarget->is64Bit()) 768 return getTargetData()->getABITypeAlignment(Ty); 769 unsigned Align = 4; 770 if (Subtarget->hasSSE1()) 771 getMaxByValAlign(Ty, Align); 772 return Align; 773} 774 775/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 776/// jumptable. 777SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 778 SelectionDAG &DAG) const { 779 if (usesGlobalOffsetTable()) 780 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 781 if (!Subtarget->isPICStyleRIPRel()) 782 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()); 783 return Table; 784} 785 786//===----------------------------------------------------------------------===// 787// Return Value Calling Convention Implementation 788//===----------------------------------------------------------------------===// 789 790#include "X86GenCallingConv.inc" 791 792/// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it 793/// exists skip possible ISD:TokenFactor. 794static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) { 795 if (Chain.getOpcode() == X86ISD::TAILCALL) { 796 return Chain; 797 } else if (Chain.getOpcode() == ISD::TokenFactor) { 798 if (Chain.getNumOperands() && 799 Chain.getOperand(0).getOpcode() == X86ISD::TAILCALL) 800 return Chain.getOperand(0); 801 } 802 return Chain; 803} 804 805/// LowerRET - Lower an ISD::RET node. 806SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) { 807 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args"); 808 809 SmallVector<CCValAssign, 16> RVLocs; 810 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 811 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 812 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 813 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86); 814 815 // If this is the first return lowered for this function, add the regs to the 816 // liveout set for the function. 817 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 818 for (unsigned i = 0; i != RVLocs.size(); ++i) 819 if (RVLocs[i].isRegLoc()) 820 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 821 } 822 SDOperand Chain = Op.getOperand(0); 823 824 // Handle tail call return. 825 Chain = GetPossiblePreceedingTailCall(Chain); 826 if (Chain.getOpcode() == X86ISD::TAILCALL) { 827 SDOperand TailCall = Chain; 828 SDOperand TargetAddress = TailCall.getOperand(1); 829 SDOperand StackAdjustment = TailCall.getOperand(2); 830 assert(((TargetAddress.getOpcode() == ISD::Register && 831 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX || 832 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) || 833 TargetAddress.getOpcode() == ISD::TargetExternalSymbol || 834 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) && 835 "Expecting an global address, external symbol, or register"); 836 assert(StackAdjustment.getOpcode() == ISD::Constant && 837 "Expecting a const value"); 838 839 SmallVector<SDOperand,8> Operands; 840 Operands.push_back(Chain.getOperand(0)); 841 Operands.push_back(TargetAddress); 842 Operands.push_back(StackAdjustment); 843 // Copy registers used by the call. Last operand is a flag so it is not 844 // copied. 845 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) { 846 Operands.push_back(Chain.getOperand(i)); 847 } 848 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0], 849 Operands.size()); 850 } 851 852 // Regular return. 853 SDOperand Flag; 854 855 SmallVector<SDOperand, 6> RetOps; 856 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 857 // Operand #1 = Bytes To Pop 858 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); 859 860 // Copy the result values into the output registers. 861 for (unsigned i = 0; i != RVLocs.size(); ++i) { 862 CCValAssign &VA = RVLocs[i]; 863 assert(VA.isRegLoc() && "Can only return in registers!"); 864 SDOperand ValToCopy = Op.getOperand(i*2+1); 865 866 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 867 // the RET instruction and handled by the FP Stackifier. 868 if (RVLocs[i].getLocReg() == X86::ST0 || 869 RVLocs[i].getLocReg() == X86::ST1) { 870 // If this is a copy from an xmm register to ST(0), use an FPExtend to 871 // change the value to the FP stack register class. 872 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) 873 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy); 874 RetOps.push_back(ValToCopy); 875 // Don't emit a copytoreg. 876 continue; 877 } 878 879 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag); 880 Flag = Chain.getValue(1); 881 } 882 883 RetOps[0] = Chain; // Update chain. 884 885 // Add the flag if we have it. 886 if (Flag.Val) 887 RetOps.push_back(Flag); 888 889 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size()); 890} 891 892 893/// LowerCallResult - Lower the result values of an ISD::CALL into the 894/// appropriate copies out of appropriate physical registers. This assumes that 895/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 896/// being lowered. The returns a SDNode with the same number of values as the 897/// ISD::CALL. 898SDNode *X86TargetLowering:: 899LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, 900 unsigned CallingConv, SelectionDAG &DAG) { 901 902 // Assign locations to each value returned by this call. 903 SmallVector<CCValAssign, 16> RVLocs; 904 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0; 905 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 906 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86); 907 908 SmallVector<SDOperand, 8> ResultVals; 909 910 // Copy all of the result registers out of their specified physreg. 911 for (unsigned i = 0; i != RVLocs.size(); ++i) { 912 MVT::ValueType CopyVT = RVLocs[i].getValVT(); 913 914 // If this is a call to a function that returns an fp value on the floating 915 // point stack, but where we prefer to use the value in xmm registers, copy 916 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 917 if (RVLocs[i].getLocReg() == X86::ST0 && 918 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 919 CopyVT = MVT::f80; 920 } 921 922 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(), 923 CopyVT, InFlag).getValue(1); 924 SDOperand Val = Chain.getValue(0); 925 InFlag = Chain.getValue(2); 926 927 if (CopyVT != RVLocs[i].getValVT()) { 928 // Round the F80 the right size, which also moves to the appropriate xmm 929 // register. 930 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val, 931 // This truncation won't change the value. 932 DAG.getIntPtrConstant(1)); 933 } 934 935 ResultVals.push_back(Val); 936 } 937 938 // Merge everything together with a MERGE_VALUES node. 939 ResultVals.push_back(Chain); 940 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), 941 &ResultVals[0], ResultVals.size()).Val; 942} 943 944 945//===----------------------------------------------------------------------===// 946// C & StdCall & Fast Calling Convention implementation 947//===----------------------------------------------------------------------===// 948// StdCall calling convention seems to be standard for many Windows' API 949// routines and around. It differs from C calling convention just a little: 950// callee should clean up the stack, not caller. Symbols should be also 951// decorated in some fancy way :) It doesn't support any vector arguments. 952// For info on fast calling convention see Fast Calling Convention (tail call) 953// implementation LowerX86_32FastCCCallTo. 954 955/// AddLiveIn - This helper function adds the specified physical register to the 956/// MachineFunction as a live in value. It also creates a corresponding virtual 957/// register for it. 958static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, 959 const TargetRegisterClass *RC) { 960 assert(RC->contains(PReg) && "Not the correct regclass!"); 961 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 962 MF.getRegInfo().addLiveIn(PReg, VReg); 963 return VReg; 964} 965 966/// CallIsStructReturn - Determines whether a CALL node uses struct return 967/// semantics. 968static bool CallIsStructReturn(SDOperand Op) { 969 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 970 if (!NumOps) 971 return false; 972 973 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet(); 974} 975 976/// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct 977/// return semantics. 978static bool ArgsAreStructReturn(SDOperand Op) { 979 unsigned NumArgs = Op.Val->getNumValues() - 1; 980 if (!NumArgs) 981 return false; 982 983 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet(); 984} 985 986/// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires the 987/// callee to pop its own arguments. Callee pop is necessary to support tail 988/// calls. 989bool X86TargetLowering::IsCalleePop(SDOperand Op) { 990 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 991 if (IsVarArg) 992 return false; 993 994 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 995 default: 996 return false; 997 case CallingConv::X86_StdCall: 998 return !Subtarget->is64Bit(); 999 case CallingConv::X86_FastCall: 1000 return !Subtarget->is64Bit(); 1001 case CallingConv::Fast: 1002 return PerformTailCallOpt; 1003 } 1004} 1005 1006/// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or 1007/// FORMAL_ARGUMENTS node. 1008CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const { 1009 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1010 1011 if (Subtarget->is64Bit()) { 1012 if (Subtarget->isTargetWin64()) 1013 return CC_X86_Win64_C; 1014 else { 1015 if (CC == CallingConv::Fast && PerformTailCallOpt) 1016 return CC_X86_64_TailCall; 1017 else 1018 return CC_X86_64_C; 1019 } 1020 } 1021 1022 if (CC == CallingConv::X86_FastCall) 1023 return CC_X86_32_FastCall; 1024 else if (CC == CallingConv::Fast && PerformTailCallOpt) 1025 return CC_X86_32_TailCall; 1026 else 1027 return CC_X86_32_C; 1028} 1029 1030/// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to 1031/// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node. 1032NameDecorationStyle 1033X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) { 1034 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1035 if (CC == CallingConv::X86_FastCall) 1036 return FastCall; 1037 else if (CC == CallingConv::X86_StdCall) 1038 return StdCall; 1039 return None; 1040} 1041 1042/// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could 1043/// possibly be overwritten when lowering the outgoing arguments in a tail 1044/// call. Currently the implementation of this call is very conservative and 1045/// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with 1046/// virtual registers would be overwritten by direct lowering. 1047static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op, 1048 MachineFrameInfo * MFI) { 1049 RegisterSDNode * OpReg = NULL; 1050 FrameIndexSDNode * FrameIdxNode = NULL; 1051 int FrameIdx = 0; 1052 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || 1053 (Op.getOpcode()== ISD::CopyFromReg && 1054 (OpReg = dyn_cast<RegisterSDNode>(Op.getOperand(1))) && 1055 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) || 1056 (Op.getOpcode() == ISD::LOAD && 1057 (FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op.getOperand(1))) && 1058 (MFI->isFixedObjectIndex((FrameIdx = FrameIdxNode->getIndex()))) && 1059 (MFI->getObjectOffset(FrameIdx) >= 0))) 1060 return true; 1061 return false; 1062} 1063 1064/// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer 1065/// in a register before calling. 1066bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) { 1067 return !IsTailCall && !Is64Bit && 1068 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1069 Subtarget->isPICStyleGOT(); 1070} 1071 1072 1073/// CallRequiresFnAddressInReg - Check whether the call requires the function 1074/// address to be loaded in a register. 1075bool 1076X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) { 1077 return !Is64Bit && IsTailCall && 1078 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1079 Subtarget->isPICStyleGOT(); 1080} 1081 1082/// CopyTailCallClobberedArgumentsToVRegs - Create virtual registers for all 1083/// arguments to force loading and guarantee that arguments sourcing from 1084/// incomming parameters are not overwriting each other. 1085static SDOperand 1086CopyTailCallClobberedArgumentsToVRegs(SDOperand Chain, 1087 SmallVector<std::pair<unsigned, SDOperand>, 8> &TailCallClobberedVRegs, 1088 SelectionDAG &DAG, 1089 MachineFunction &MF, 1090 const TargetLowering * TL) { 1091 1092 SDOperand InFlag; 1093 for (unsigned i = 0, e = TailCallClobberedVRegs.size(); i != e; i++) { 1094 SDOperand Arg = TailCallClobberedVRegs[i].second; 1095 unsigned Idx = TailCallClobberedVRegs[i].first; 1096 unsigned VReg = 1097 MF.getRegInfo(). 1098 createVirtualRegister(TL->getRegClassFor(Arg.getValueType())); 1099 Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag); 1100 InFlag = Chain.getValue(1); 1101 Arg = DAG.getCopyFromReg(Chain, VReg, Arg.getValueType(), InFlag); 1102 TailCallClobberedVRegs[i] = std::make_pair(Idx, Arg); 1103 Chain = Arg.getValue(1); 1104 InFlag = Arg.getValue(2); 1105 } 1106 return Chain; 1107} 1108 1109/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1110/// by "Src" to address "Dst" with size and alignment information specified by 1111/// the specific parameter attribute. The copy will be passed as a byval function 1112/// parameter. 1113static SDOperand 1114CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain, 1115 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) { 1116 SDOperand AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32); 1117 SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1118 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32); 1119 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline); 1120} 1121 1122SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG, 1123 const CCValAssign &VA, 1124 MachineFrameInfo *MFI, 1125 unsigned CC, 1126 SDOperand Root, unsigned i) { 1127 // Create the nodes corresponding to a load from this parameter slot. 1128 ISD::ArgFlagsTy Flags = 1129 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags(); 1130 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt; 1131 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1132 1133 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1134 // changed with more analysis. 1135 // In case of tail call optimization mark all arguments mutable. Since they 1136 // could be overwritten by lowering of arguments in case of a tail call. 1137 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8, 1138 VA.getLocMemOffset(), isImmutable); 1139 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy()); 1140 if (Flags.isByVal()) 1141 return FIN; 1142 return DAG.getLoad(VA.getValVT(), Root, FIN, 1143 PseudoSourceValue::getFixedStack(), FI); 1144} 1145 1146SDOperand 1147X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 1148 MachineFunction &MF = DAG.getMachineFunction(); 1149 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1150 1151 const Function* Fn = MF.getFunction(); 1152 if (Fn->hasExternalLinkage() && 1153 Subtarget->isTargetCygMing() && 1154 Fn->getName() == "main") 1155 FuncInfo->setForceFramePointer(true); 1156 1157 // Decorate the function name. 1158 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op)); 1159 1160 MachineFrameInfo *MFI = MF.getFrameInfo(); 1161 SDOperand Root = Op.getOperand(0); 1162 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1163 unsigned CC = MF.getFunction()->getCallingConv(); 1164 bool Is64Bit = Subtarget->is64Bit(); 1165 1166 assert(!(isVarArg && CC == CallingConv::Fast) && 1167 "Var args not supported with calling convention fastcc"); 1168 1169 // Assign locations to all of the incoming arguments. 1170 SmallVector<CCValAssign, 16> ArgLocs; 1171 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1172 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op)); 1173 1174 SmallVector<SDOperand, 8> ArgValues; 1175 unsigned LastVal = ~0U; 1176 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1177 CCValAssign &VA = ArgLocs[i]; 1178 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1179 // places. 1180 assert(VA.getValNo() != LastVal && 1181 "Don't support value assigned to multiple locs yet"); 1182 LastVal = VA.getValNo(); 1183 1184 if (VA.isRegLoc()) { 1185 MVT::ValueType RegVT = VA.getLocVT(); 1186 TargetRegisterClass *RC; 1187 if (RegVT == MVT::i32) 1188 RC = X86::GR32RegisterClass; 1189 else if (Is64Bit && RegVT == MVT::i64) 1190 RC = X86::GR64RegisterClass; 1191 else if (RegVT == MVT::f32) 1192 RC = X86::FR32RegisterClass; 1193 else if (RegVT == MVT::f64) 1194 RC = X86::FR64RegisterClass; 1195 else { 1196 assert(MVT::isVector(RegVT)); 1197 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) { 1198 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs. 1199 RegVT = MVT::i64; 1200 } else 1201 RC = X86::VR128RegisterClass; 1202 } 1203 1204 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); 1205 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); 1206 1207 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1208 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1209 // right size. 1210 if (VA.getLocInfo() == CCValAssign::SExt) 1211 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue, 1212 DAG.getValueType(VA.getValVT())); 1213 else if (VA.getLocInfo() == CCValAssign::ZExt) 1214 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue, 1215 DAG.getValueType(VA.getValVT())); 1216 1217 if (VA.getLocInfo() != CCValAssign::Full) 1218 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); 1219 1220 // Handle MMX values passed in GPRs. 1221 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass && 1222 MVT::getSizeInBits(RegVT) == 64) 1223 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); 1224 1225 ArgValues.push_back(ArgValue); 1226 } else { 1227 assert(VA.isMemLoc()); 1228 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i)); 1229 } 1230 } 1231 1232 unsigned StackSize = CCInfo.getNextStackOffset(); 1233 // align stack specially for tail calls 1234 if (CC == CallingConv::Fast) 1235 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1236 1237 // If the function takes variable number of arguments, make a frame index for 1238 // the start of the first vararg value... for expansion of llvm.va_start. 1239 if (isVarArg) { 1240 if (Is64Bit || CC != CallingConv::X86_FastCall) { 1241 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1242 } 1243 if (Is64Bit) { 1244 static const unsigned GPR64ArgRegs[] = { 1245 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1246 }; 1247 static const unsigned XMMArgRegs[] = { 1248 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1249 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1250 }; 1251 1252 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6); 1253 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1254 1255 // For X86-64, if there are vararg parameters that are passed via 1256 // registers, then we must store them to their spots on the stack so they 1257 // may be loaded by deferencing the result of va_next. 1258 VarArgsGPOffset = NumIntRegs * 8; 1259 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16; 1260 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16); 1261 1262 // Store the integer parameter registers. 1263 SmallVector<SDOperand, 8> MemOps; 1264 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1265 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1266 DAG.getIntPtrConstant(VarArgsGPOffset)); 1267 for (; NumIntRegs != 6; ++NumIntRegs) { 1268 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs], 1269 X86::GR64RegisterClass); 1270 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1271 SDOperand Store = 1272 DAG.getStore(Val.getValue(1), Val, FIN, 1273 PseudoSourceValue::getFixedStack(), 1274 RegSaveFrameIndex); 1275 MemOps.push_back(Store); 1276 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1277 DAG.getIntPtrConstant(8)); 1278 } 1279 1280 // Now store the XMM (fp + vector) parameter registers. 1281 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN, 1282 DAG.getIntPtrConstant(VarArgsFPOffset)); 1283 for (; NumXMMRegs != 8; ++NumXMMRegs) { 1284 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], 1285 X86::VR128RegisterClass); 1286 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32); 1287 SDOperand Store = 1288 DAG.getStore(Val.getValue(1), Val, FIN, 1289 PseudoSourceValue::getFixedStack(), 1290 RegSaveFrameIndex); 1291 MemOps.push_back(Store); 1292 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1293 DAG.getIntPtrConstant(16)); 1294 } 1295 if (!MemOps.empty()) 1296 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1297 &MemOps[0], MemOps.size()); 1298 } 1299 } 1300 1301 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1302 // arguments and the arguments after the retaddr has been pushed are 1303 // aligned. 1304 if (!Is64Bit && CC == CallingConv::X86_FastCall && 1305 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() && 1306 (StackSize & 7) == 0) 1307 StackSize += 4; 1308 1309 ArgValues.push_back(Root); 1310 1311 // Some CCs need callee pop. 1312 if (IsCalleePop(Op)) { 1313 BytesToPopOnReturn = StackSize; // Callee pops everything. 1314 BytesCallerReserves = 0; 1315 } else { 1316 BytesToPopOnReturn = 0; // Callee pops nothing. 1317 // If this is an sret function, the return should pop the hidden pointer. 1318 if (!Is64Bit && ArgsAreStructReturn(Op)) 1319 BytesToPopOnReturn = 4; 1320 BytesCallerReserves = StackSize; 1321 } 1322 1323 if (!Is64Bit) { 1324 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1325 if (CC == CallingConv::X86_FastCall) 1326 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1327 } 1328 1329 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1330 1331 // Return the new list of results. 1332 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), 1333 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); 1334} 1335 1336SDOperand 1337X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG, 1338 const SDOperand &StackPtr, 1339 const CCValAssign &VA, 1340 SDOperand Chain, 1341 SDOperand Arg) { 1342 unsigned LocMemOffset = VA.getLocMemOffset(); 1343 SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1344 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff); 1345 ISD::ArgFlagsTy Flags = 1346 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags(); 1347 if (Flags.isByVal()) { 1348 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG); 1349 } 1350 return DAG.getStore(Chain, Arg, PtrOff, 1351 PseudoSourceValue::getStack(), LocMemOffset); 1352} 1353 1354 1355SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 1356 MachineFunction &MF = DAG.getMachineFunction(); 1357 MachineFrameInfo * MFI = MF.getFrameInfo(); 1358 SDOperand Chain = Op.getOperand(0); 1359 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 1360 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1361 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0 1362 && CC == CallingConv::Fast && PerformTailCallOpt; 1363 SDOperand Callee = Op.getOperand(4); 1364 bool Is64Bit = Subtarget->is64Bit(); 1365 bool IsStructRet = CallIsStructReturn(Op); 1366 1367 assert(!(isVarArg && CC == CallingConv::Fast) && 1368 "Var args not supported with calling convention fastcc"); 1369 1370 // Analyze operands of the call, assigning locations to each operand. 1371 SmallVector<CCValAssign, 16> ArgLocs; 1372 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1373 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op)); 1374 1375 // Get a count of how many bytes are to be pushed on the stack. 1376 unsigned NumBytes = CCInfo.getNextStackOffset(); 1377 if (CC == CallingConv::Fast) 1378 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1379 1380 // Make sure the instruction takes 8n+4 bytes to make sure the start of the 1381 // arguments and the arguments after the retaddr has been pushed are aligned. 1382 if (!Is64Bit && CC == CallingConv::X86_FastCall && 1383 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() && 1384 (NumBytes & 7) == 0) 1385 NumBytes += 4; 1386 1387 int FPDiff = 0; 1388 if (IsTailCall) { 1389 // Lower arguments at fp - stackoffset + fpdiff. 1390 unsigned NumBytesCallerPushed = 1391 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1392 FPDiff = NumBytesCallerPushed - NumBytes; 1393 1394 // Set the delta of movement of the returnaddr stackslot. 1395 // But only set if delta is greater than previous delta. 1396 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1397 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1398 } 1399 1400 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes)); 1401 1402 SDOperand RetAddrFrIdx; 1403 if (IsTailCall) { 1404 // Adjust the Return address stack slot. 1405 if (FPDiff) { 1406 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32; 1407 RetAddrFrIdx = getReturnAddressFrameIndex(DAG); 1408 // Load the "old" Return address. 1409 RetAddrFrIdx = 1410 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0); 1411 Chain = SDOperand(RetAddrFrIdx.Val, 1); 1412 } 1413 } 1414 1415 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass; 1416 SmallVector<std::pair<unsigned, SDOperand>, 8> TailCallClobberedVRegs; 1417 SmallVector<SDOperand, 8> MemOpChains; 1418 1419 SDOperand StackPtr; 1420 1421 // Walk the register/memloc assignments, inserting copies/loads. For tail 1422 // calls, remember all arguments for later special lowering. 1423 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1424 CCValAssign &VA = ArgLocs[i]; 1425 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 1426 1427 // Promote the value if needed. 1428 switch (VA.getLocInfo()) { 1429 default: assert(0 && "Unknown loc info!"); 1430 case CCValAssign::Full: break; 1431 case CCValAssign::SExt: 1432 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg); 1433 break; 1434 case CCValAssign::ZExt: 1435 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg); 1436 break; 1437 case CCValAssign::AExt: 1438 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg); 1439 break; 1440 } 1441 1442 if (VA.isRegLoc()) { 1443 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1444 } else { 1445 if (!IsTailCall) { 1446 assert(VA.isMemLoc()); 1447 if (StackPtr.Val == 0) 1448 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy()); 1449 1450 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain, 1451 Arg)); 1452 } else if (IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) { 1453 TailCallClobberedVRegs.push_back(std::make_pair(i,Arg)); 1454 } 1455 } 1456 } 1457 1458 if (!MemOpChains.empty()) 1459 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1460 &MemOpChains[0], MemOpChains.size()); 1461 1462 // Build a sequence of copy-to-reg nodes chained together with token chain 1463 // and flag operands which copy the outgoing args into registers. 1464 SDOperand InFlag; 1465 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1466 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1467 InFlag); 1468 InFlag = Chain.getValue(1); 1469 } 1470 1471 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1472 // GOT pointer. 1473 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) { 1474 Chain = DAG.getCopyToReg(Chain, X86::EBX, 1475 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 1476 InFlag); 1477 InFlag = Chain.getValue(1); 1478 } 1479 // If we are tail calling and generating PIC/GOT style code load the address 1480 // of the callee into ecx. The value in ecx is used as target of the tail 1481 // jump. This is done to circumvent the ebx/callee-saved problem for tail 1482 // calls on PIC/GOT architectures. Normally we would just put the address of 1483 // GOT into ebx and then call target@PLT. But for tail callss ebx would be 1484 // restored (since ebx is callee saved) before jumping to the target@PLT. 1485 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) { 1486 // Note: The actual moving to ecx is done further down. 1487 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1488 if (G && !G->getGlobal()->hasHiddenVisibility() && 1489 !G->getGlobal()->hasProtectedVisibility()) 1490 Callee = LowerGlobalAddress(Callee, DAG); 1491 else if (isa<ExternalSymbolSDNode>(Callee)) 1492 Callee = LowerExternalSymbol(Callee,DAG); 1493 } 1494 1495 if (Is64Bit && isVarArg) { 1496 // From AMD64 ABI document: 1497 // For calls that may call functions that use varargs or stdargs 1498 // (prototype-less calls or calls to functions containing ellipsis (...) in 1499 // the declaration) %al is used as hidden argument to specify the number 1500 // of SSE registers used. The contents of %al do not need to match exactly 1501 // the number of registers, but must be an ubound on the number of SSE 1502 // registers used and is in the range 0 - 8 inclusive. 1503 1504 // Count the number of XMM registers allocated. 1505 static const unsigned XMMArgRegs[] = { 1506 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1507 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1508 }; 1509 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1510 1511 Chain = DAG.getCopyToReg(Chain, X86::AL, 1512 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1513 InFlag = Chain.getValue(1); 1514 } 1515 1516 1517 // For tail calls lower the arguments to the 'real' stack slot. 1518 if (IsTailCall) { 1519 SmallVector<SDOperand, 8> MemOpChains2; 1520 SDOperand FIN; 1521 int FI = 0; 1522 // Do not flag preceeding copytoreg stuff together with the following stuff. 1523 InFlag = SDOperand(); 1524 1525 Chain = CopyTailCallClobberedArgumentsToVRegs(Chain, TailCallClobberedVRegs, 1526 DAG, MF, this); 1527 1528 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1529 CCValAssign &VA = ArgLocs[i]; 1530 if (!VA.isRegLoc()) { 1531 assert(VA.isMemLoc()); 1532 SDOperand Arg = Op.getOperand(5+2*VA.getValNo()); 1533 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo()); 1534 ISD::ArgFlagsTy Flags = 1535 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags(); 1536 // Create frame index. 1537 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1538 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8; 1539 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1540 FIN = DAG.getFrameIndex(FI, MVT::i32); 1541 1542 // Find virtual register for this argument. 1543 bool Found=false; 1544 for (unsigned idx=0, e= TailCallClobberedVRegs.size(); idx < e; idx++) 1545 if (TailCallClobberedVRegs[idx].first==i) { 1546 Arg = TailCallClobberedVRegs[idx].second; 1547 Found=true; 1548 break; 1549 } 1550 assert(IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)==false || 1551 (Found==true && "No corresponding Argument was found")); 1552 1553 if (Flags.isByVal()) { 1554 // Copy relative to framepointer. 1555 MemOpChains2.push_back(CreateCopyOfByValArgument(Arg, FIN, Chain, 1556 Flags, DAG)); 1557 } else { 1558 // Store relative to framepointer. 1559 MemOpChains2.push_back( 1560 DAG.getStore(Chain, Arg, FIN, 1561 PseudoSourceValue::getFixedStack(), FI)); 1562 } 1563 } 1564 } 1565 1566 if (!MemOpChains2.empty()) 1567 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1568 &MemOpChains2[0], MemOpChains2.size()); 1569 1570 // Store the return address to the appropriate stack slot. 1571 if (FPDiff) { 1572 // Calculate the new stack slot for the return address. 1573 int SlotSize = Is64Bit ? 8 : 4; 1574 int NewReturnAddrFI = 1575 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1576 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32; 1577 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1578 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx, 1579 PseudoSourceValue::getFixedStack(), NewReturnAddrFI); 1580 } 1581 } 1582 1583 // If the callee is a GlobalAddress node (quite common, every direct call is) 1584 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1585 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1586 // We should use extra load for direct calls to dllimported functions in 1587 // non-JIT mode. 1588 if ((IsTailCall || !Is64Bit || 1589 getTargetMachine().getCodeModel() != CodeModel::Large) 1590 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(), 1591 getTargetMachine(), true)) 1592 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 1593 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1594 if (IsTailCall || !Is64Bit || 1595 getTargetMachine().getCodeModel() != CodeModel::Large) 1596 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 1597 } else if (IsTailCall) { 1598 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX; 1599 1600 Chain = DAG.getCopyToReg(Chain, 1601 DAG.getRegister(Opc, getPointerTy()), 1602 Callee,InFlag); 1603 Callee = DAG.getRegister(Opc, getPointerTy()); 1604 // Add register as live out. 1605 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc); 1606 } 1607 1608 // Returns a chain & a flag for retval copy to use. 1609 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1610 SmallVector<SDOperand, 8> Ops; 1611 1612 if (IsTailCall) { 1613 Ops.push_back(Chain); 1614 Ops.push_back(DAG.getIntPtrConstant(NumBytes)); 1615 Ops.push_back(DAG.getIntPtrConstant(0)); 1616 if (InFlag.Val) 1617 Ops.push_back(InFlag); 1618 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size()); 1619 InFlag = Chain.getValue(1); 1620 1621 // Returns a chain & a flag for retval copy to use. 1622 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1623 Ops.clear(); 1624 } 1625 1626 Ops.push_back(Chain); 1627 Ops.push_back(Callee); 1628 1629 if (IsTailCall) 1630 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1631 1632 // Add argument registers to the end of the list so that they are known live 1633 // into the call. 1634 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1635 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1636 RegsToPass[i].second.getValueType())); 1637 1638 // Add an implicit use GOT pointer in EBX. 1639 if (!IsTailCall && !Is64Bit && 1640 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1641 Subtarget->isPICStyleGOT()) 1642 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 1643 1644 // Add an implicit use of AL for x86 vararg functions. 1645 if (Is64Bit && isVarArg) 1646 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 1647 1648 if (InFlag.Val) 1649 Ops.push_back(InFlag); 1650 1651 if (IsTailCall) { 1652 assert(InFlag.Val && 1653 "Flag must be set. Depend on flag being set in LowerRET"); 1654 Chain = DAG.getNode(X86ISD::TAILCALL, 1655 Op.Val->getVTList(), &Ops[0], Ops.size()); 1656 1657 return SDOperand(Chain.Val, Op.ResNo); 1658 } 1659 1660 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size()); 1661 InFlag = Chain.getValue(1); 1662 1663 // Create the CALLSEQ_END node. 1664 unsigned NumBytesForCalleeToPush; 1665 if (IsCalleePop(Op)) 1666 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 1667 else if (!Is64Bit && IsStructRet) 1668 // If this is is a call to a struct-return function, the callee 1669 // pops the hidden struct pointer, so we have to push it back. 1670 // This is common for Darwin/X86, Linux & Mingw32 targets. 1671 NumBytesForCalleeToPush = 4; 1672 else 1673 NumBytesForCalleeToPush = 0; // Callee pops nothing. 1674 1675 // Returns a flag for retval copy to use. 1676 Chain = DAG.getCALLSEQ_END(Chain, 1677 DAG.getIntPtrConstant(NumBytes), 1678 DAG.getIntPtrConstant(NumBytesForCalleeToPush), 1679 InFlag); 1680 InFlag = Chain.getValue(1); 1681 1682 // Handle result values, copying them out of physregs into vregs that we 1683 // return. 1684 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo); 1685} 1686 1687 1688//===----------------------------------------------------------------------===// 1689// Fast Calling Convention (tail call) implementation 1690//===----------------------------------------------------------------------===// 1691 1692// Like std call, callee cleans arguments, convention except that ECX is 1693// reserved for storing the tail called function address. Only 2 registers are 1694// free for argument passing (inreg). Tail call optimization is performed 1695// provided: 1696// * tailcallopt is enabled 1697// * caller/callee are fastcc 1698// On X86_64 architecture with GOT-style position independent code only local 1699// (within module) calls are supported at the moment. 1700// To keep the stack aligned according to platform abi the function 1701// GetAlignedArgumentStackSize ensures that argument delta is always multiples 1702// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 1703// If a tail called function callee has more arguments than the caller the 1704// caller needs to make sure that there is room to move the RETADDR to. This is 1705// achieved by reserving an area the size of the argument delta right after the 1706// original REtADDR, but before the saved framepointer or the spilled registers 1707// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 1708// stack layout: 1709// arg1 1710// arg2 1711// RETADDR 1712// [ new RETADDR 1713// move area ] 1714// (possible EBP) 1715// ESI 1716// EDI 1717// local1 .. 1718 1719/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 1720/// for a 16 byte align requirement. 1721unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 1722 SelectionDAG& DAG) { 1723 if (PerformTailCallOpt) { 1724 MachineFunction &MF = DAG.getMachineFunction(); 1725 const TargetMachine &TM = MF.getTarget(); 1726 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 1727 unsigned StackAlignment = TFI.getStackAlignment(); 1728 uint64_t AlignMask = StackAlignment - 1; 1729 int64_t Offset = StackSize; 1730 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4; 1731 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 1732 // Number smaller than 12 so just add the difference. 1733 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 1734 } else { 1735 // Mask out lower bits, add stackalignment once plus the 12 bytes. 1736 Offset = ((~AlignMask) & Offset) + StackAlignment + 1737 (StackAlignment-SlotSize); 1738 } 1739 StackSize = Offset; 1740 } 1741 return StackSize; 1742} 1743 1744/// IsEligibleForTailCallElimination - Check to see whether the next instruction 1745/// following the call is a return. A function is eligible if caller/callee 1746/// calling conventions match, currently only fastcc supports tail calls, and 1747/// the function CALL is immediatly followed by a RET. 1748bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call, 1749 SDOperand Ret, 1750 SelectionDAG& DAG) const { 1751 if (!PerformTailCallOpt) 1752 return false; 1753 1754 // Check whether CALL node immediatly preceeds the RET node and whether the 1755 // return uses the result of the node or is a void return. 1756 unsigned NumOps = Ret.getNumOperands(); 1757 if ((NumOps == 1 && 1758 (Ret.getOperand(0) == SDOperand(Call.Val,1) || 1759 Ret.getOperand(0) == SDOperand(Call.Val,0))) || 1760 (NumOps > 1 && 1761 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) && 1762 Ret.getOperand(1) == SDOperand(Call.Val,0))) { 1763 MachineFunction &MF = DAG.getMachineFunction(); 1764 unsigned CallerCC = MF.getFunction()->getCallingConv(); 1765 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue(); 1766 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 1767 SDOperand Callee = Call.getOperand(4); 1768 // On x86/32Bit PIC/GOT tail calls are supported. 1769 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ || 1770 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit()) 1771 return true; 1772 1773 // Can only do local tail calls (in same module, hidden or protected) on 1774 // x86_64 PIC/GOT at the moment. 1775 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1776 return G->getGlobal()->hasHiddenVisibility() 1777 || G->getGlobal()->hasProtectedVisibility(); 1778 } 1779 } 1780 1781 return false; 1782} 1783 1784//===----------------------------------------------------------------------===// 1785// Other Lowering Hooks 1786//===----------------------------------------------------------------------===// 1787 1788 1789SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 1790 MachineFunction &MF = DAG.getMachineFunction(); 1791 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1792 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1793 1794 if (ReturnAddrIndex == 0) { 1795 // Set up a frame object for the return address. 1796 if (Subtarget->is64Bit()) 1797 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8); 1798 else 1799 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4); 1800 1801 FuncInfo->setRAIndex(ReturnAddrIndex); 1802 } 1803 1804 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1805} 1806 1807 1808 1809/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86 1810/// specific condition code. It returns a false if it cannot do a direct 1811/// translation. X86CC is the translated CondCode. LHS/RHS are modified as 1812/// needed. 1813static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 1814 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS, 1815 SelectionDAG &DAG) { 1816 X86CC = X86::COND_INVALID; 1817 if (!isFP) { 1818 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 1819 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 1820 // X > -1 -> X == 0, jump !sign. 1821 RHS = DAG.getConstant(0, RHS.getValueType()); 1822 X86CC = X86::COND_NS; 1823 return true; 1824 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 1825 // X < 0 -> X == 0, jump on sign. 1826 X86CC = X86::COND_S; 1827 return true; 1828 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) { 1829 // X < 1 -> X <= 0 1830 RHS = DAG.getConstant(0, RHS.getValueType()); 1831 X86CC = X86::COND_LE; 1832 return true; 1833 } 1834 } 1835 1836 switch (SetCCOpcode) { 1837 default: break; 1838 case ISD::SETEQ: X86CC = X86::COND_E; break; 1839 case ISD::SETGT: X86CC = X86::COND_G; break; 1840 case ISD::SETGE: X86CC = X86::COND_GE; break; 1841 case ISD::SETLT: X86CC = X86::COND_L; break; 1842 case ISD::SETLE: X86CC = X86::COND_LE; break; 1843 case ISD::SETNE: X86CC = X86::COND_NE; break; 1844 case ISD::SETULT: X86CC = X86::COND_B; break; 1845 case ISD::SETUGT: X86CC = X86::COND_A; break; 1846 case ISD::SETULE: X86CC = X86::COND_BE; break; 1847 case ISD::SETUGE: X86CC = X86::COND_AE; break; 1848 } 1849 } else { 1850 // On a floating point condition, the flags are set as follows: 1851 // ZF PF CF op 1852 // 0 | 0 | 0 | X > Y 1853 // 0 | 0 | 1 | X < Y 1854 // 1 | 0 | 0 | X == Y 1855 // 1 | 1 | 1 | unordered 1856 bool Flip = false; 1857 switch (SetCCOpcode) { 1858 default: break; 1859 case ISD::SETUEQ: 1860 case ISD::SETEQ: X86CC = X86::COND_E; break; 1861 case ISD::SETOLT: Flip = true; // Fallthrough 1862 case ISD::SETOGT: 1863 case ISD::SETGT: X86CC = X86::COND_A; break; 1864 case ISD::SETOLE: Flip = true; // Fallthrough 1865 case ISD::SETOGE: 1866 case ISD::SETGE: X86CC = X86::COND_AE; break; 1867 case ISD::SETUGT: Flip = true; // Fallthrough 1868 case ISD::SETULT: 1869 case ISD::SETLT: X86CC = X86::COND_B; break; 1870 case ISD::SETUGE: Flip = true; // Fallthrough 1871 case ISD::SETULE: 1872 case ISD::SETLE: X86CC = X86::COND_BE; break; 1873 case ISD::SETONE: 1874 case ISD::SETNE: X86CC = X86::COND_NE; break; 1875 case ISD::SETUO: X86CC = X86::COND_P; break; 1876 case ISD::SETO: X86CC = X86::COND_NP; break; 1877 } 1878 if (Flip) 1879 std::swap(LHS, RHS); 1880 } 1881 1882 return X86CC != X86::COND_INVALID; 1883} 1884 1885/// hasFPCMov - is there a floating point cmov for the specific X86 condition 1886/// code. Current x86 isa includes the following FP cmov instructions: 1887/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 1888static bool hasFPCMov(unsigned X86CC) { 1889 switch (X86CC) { 1890 default: 1891 return false; 1892 case X86::COND_B: 1893 case X86::COND_BE: 1894 case X86::COND_E: 1895 case X86::COND_P: 1896 case X86::COND_A: 1897 case X86::COND_AE: 1898 case X86::COND_NE: 1899 case X86::COND_NP: 1900 return true; 1901 } 1902} 1903 1904/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return 1905/// true if Op is undef or if its value falls within the specified range (L, H]. 1906static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) { 1907 if (Op.getOpcode() == ISD::UNDEF) 1908 return true; 1909 1910 unsigned Val = cast<ConstantSDNode>(Op)->getValue(); 1911 return (Val >= Low && Val < Hi); 1912} 1913 1914/// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return 1915/// true if Op is undef or if its value equal to the specified value. 1916static bool isUndefOrEqual(SDOperand Op, unsigned Val) { 1917 if (Op.getOpcode() == ISD::UNDEF) 1918 return true; 1919 return cast<ConstantSDNode>(Op)->getValue() == Val; 1920} 1921 1922/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 1923/// specifies a shuffle of elements that is suitable for input to PSHUFD. 1924bool X86::isPSHUFDMask(SDNode *N) { 1925 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1926 1927 if (N->getNumOperands() != 2 && N->getNumOperands() != 4) 1928 return false; 1929 1930 // Check if the value doesn't reference the second vector. 1931 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 1932 SDOperand Arg = N->getOperand(i); 1933 if (Arg.getOpcode() == ISD::UNDEF) continue; 1934 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1935 if (cast<ConstantSDNode>(Arg)->getValue() >= e) 1936 return false; 1937 } 1938 1939 return true; 1940} 1941 1942/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 1943/// specifies a shuffle of elements that is suitable for input to PSHUFHW. 1944bool X86::isPSHUFHWMask(SDNode *N) { 1945 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1946 1947 if (N->getNumOperands() != 8) 1948 return false; 1949 1950 // Lower quadword copied in order. 1951 for (unsigned i = 0; i != 4; ++i) { 1952 SDOperand Arg = N->getOperand(i); 1953 if (Arg.getOpcode() == ISD::UNDEF) continue; 1954 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1955 if (cast<ConstantSDNode>(Arg)->getValue() != i) 1956 return false; 1957 } 1958 1959 // Upper quadword shuffled. 1960 for (unsigned i = 4; i != 8; ++i) { 1961 SDOperand Arg = N->getOperand(i); 1962 if (Arg.getOpcode() == ISD::UNDEF) continue; 1963 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1964 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 1965 if (Val < 4 || Val > 7) 1966 return false; 1967 } 1968 1969 return true; 1970} 1971 1972/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 1973/// specifies a shuffle of elements that is suitable for input to PSHUFLW. 1974bool X86::isPSHUFLWMask(SDNode *N) { 1975 assert(N->getOpcode() == ISD::BUILD_VECTOR); 1976 1977 if (N->getNumOperands() != 8) 1978 return false; 1979 1980 // Upper quadword copied in order. 1981 for (unsigned i = 4; i != 8; ++i) 1982 if (!isUndefOrEqual(N->getOperand(i), i)) 1983 return false; 1984 1985 // Lower quadword shuffled. 1986 for (unsigned i = 0; i != 4; ++i) 1987 if (!isUndefOrInRange(N->getOperand(i), 0, 4)) 1988 return false; 1989 1990 return true; 1991} 1992 1993/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 1994/// specifies a shuffle of elements that is suitable for input to SHUFP*. 1995static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) { 1996 if (NumElems != 2 && NumElems != 4) return false; 1997 1998 unsigned Half = NumElems / 2; 1999 for (unsigned i = 0; i < Half; ++i) 2000 if (!isUndefOrInRange(Elems[i], 0, NumElems)) 2001 return false; 2002 for (unsigned i = Half; i < NumElems; ++i) 2003 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2)) 2004 return false; 2005 2006 return true; 2007} 2008 2009bool X86::isSHUFPMask(SDNode *N) { 2010 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2011 return ::isSHUFPMask(N->op_begin(), N->getNumOperands()); 2012} 2013 2014/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2015/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2016/// half elements to come from vector 1 (which would equal the dest.) and 2017/// the upper half to come from vector 2. 2018static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) { 2019 if (NumOps != 2 && NumOps != 4) return false; 2020 2021 unsigned Half = NumOps / 2; 2022 for (unsigned i = 0; i < Half; ++i) 2023 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2)) 2024 return false; 2025 for (unsigned i = Half; i < NumOps; ++i) 2026 if (!isUndefOrInRange(Ops[i], 0, NumOps)) 2027 return false; 2028 return true; 2029} 2030 2031static bool isCommutedSHUFP(SDNode *N) { 2032 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2033 return isCommutedSHUFP(N->op_begin(), N->getNumOperands()); 2034} 2035 2036/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2037/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2038bool X86::isMOVHLPSMask(SDNode *N) { 2039 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2040 2041 if (N->getNumOperands() != 4) 2042 return false; 2043 2044 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2045 return isUndefOrEqual(N->getOperand(0), 6) && 2046 isUndefOrEqual(N->getOperand(1), 7) && 2047 isUndefOrEqual(N->getOperand(2), 2) && 2048 isUndefOrEqual(N->getOperand(3), 3); 2049} 2050 2051/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2052/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2053/// <2, 3, 2, 3> 2054bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) { 2055 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2056 2057 if (N->getNumOperands() != 4) 2058 return false; 2059 2060 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3 2061 return isUndefOrEqual(N->getOperand(0), 2) && 2062 isUndefOrEqual(N->getOperand(1), 3) && 2063 isUndefOrEqual(N->getOperand(2), 2) && 2064 isUndefOrEqual(N->getOperand(3), 3); 2065} 2066 2067/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2068/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2069bool X86::isMOVLPMask(SDNode *N) { 2070 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2071 2072 unsigned NumElems = N->getNumOperands(); 2073 if (NumElems != 2 && NumElems != 4) 2074 return false; 2075 2076 for (unsigned i = 0; i < NumElems/2; ++i) 2077 if (!isUndefOrEqual(N->getOperand(i), i + NumElems)) 2078 return false; 2079 2080 for (unsigned i = NumElems/2; i < NumElems; ++i) 2081 if (!isUndefOrEqual(N->getOperand(i), i)) 2082 return false; 2083 2084 return true; 2085} 2086 2087/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2088/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2089/// and MOVLHPS. 2090bool X86::isMOVHPMask(SDNode *N) { 2091 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2092 2093 unsigned NumElems = N->getNumOperands(); 2094 if (NumElems != 2 && NumElems != 4) 2095 return false; 2096 2097 for (unsigned i = 0; i < NumElems/2; ++i) 2098 if (!isUndefOrEqual(N->getOperand(i), i)) 2099 return false; 2100 2101 for (unsigned i = 0; i < NumElems/2; ++i) { 2102 SDOperand Arg = N->getOperand(i + NumElems/2); 2103 if (!isUndefOrEqual(Arg, i + NumElems)) 2104 return false; 2105 } 2106 2107 return true; 2108} 2109 2110/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2111/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2112bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts, 2113 bool V2IsSplat = false) { 2114 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2115 return false; 2116 2117 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2118 SDOperand BitI = Elts[i]; 2119 SDOperand BitI1 = Elts[i+1]; 2120 if (!isUndefOrEqual(BitI, j)) 2121 return false; 2122 if (V2IsSplat) { 2123 if (isUndefOrEqual(BitI1, NumElts)) 2124 return false; 2125 } else { 2126 if (!isUndefOrEqual(BitI1, j + NumElts)) 2127 return false; 2128 } 2129 } 2130 2131 return true; 2132} 2133 2134bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) { 2135 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2136 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2137} 2138 2139/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2140/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2141bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts, 2142 bool V2IsSplat = false) { 2143 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2144 return false; 2145 2146 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) { 2147 SDOperand BitI = Elts[i]; 2148 SDOperand BitI1 = Elts[i+1]; 2149 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2150 return false; 2151 if (V2IsSplat) { 2152 if (isUndefOrEqual(BitI1, NumElts)) 2153 return false; 2154 } else { 2155 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2156 return false; 2157 } 2158 } 2159 2160 return true; 2161} 2162 2163bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) { 2164 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2165 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat); 2166} 2167 2168/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2169/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2170/// <0, 0, 1, 1> 2171bool X86::isUNPCKL_v_undef_Mask(SDNode *N) { 2172 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2173 2174 unsigned NumElems = N->getNumOperands(); 2175 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2176 return false; 2177 2178 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) { 2179 SDOperand BitI = N->getOperand(i); 2180 SDOperand BitI1 = N->getOperand(i+1); 2181 2182 if (!isUndefOrEqual(BitI, j)) 2183 return false; 2184 if (!isUndefOrEqual(BitI1, j)) 2185 return false; 2186 } 2187 2188 return true; 2189} 2190 2191/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2192/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2193/// <2, 2, 3, 3> 2194bool X86::isUNPCKH_v_undef_Mask(SDNode *N) { 2195 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2196 2197 unsigned NumElems = N->getNumOperands(); 2198 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2199 return false; 2200 2201 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2202 SDOperand BitI = N->getOperand(i); 2203 SDOperand BitI1 = N->getOperand(i + 1); 2204 2205 if (!isUndefOrEqual(BitI, j)) 2206 return false; 2207 if (!isUndefOrEqual(BitI1, j)) 2208 return false; 2209 } 2210 2211 return true; 2212} 2213 2214/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2215/// specifies a shuffle of elements that is suitable for input to MOVSS, 2216/// MOVSD, and MOVD, i.e. setting the lowest element. 2217static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) { 2218 if (NumElts != 2 && NumElts != 4) 2219 return false; 2220 2221 if (!isUndefOrEqual(Elts[0], NumElts)) 2222 return false; 2223 2224 for (unsigned i = 1; i < NumElts; ++i) { 2225 if (!isUndefOrEqual(Elts[i], i)) 2226 return false; 2227 } 2228 2229 return true; 2230} 2231 2232bool X86::isMOVLMask(SDNode *N) { 2233 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2234 return ::isMOVLMask(N->op_begin(), N->getNumOperands()); 2235} 2236 2237/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2238/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2239/// element of vector 2 and the other elements to come from vector 1 in order. 2240static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps, 2241 bool V2IsSplat = false, 2242 bool V2IsUndef = false) { 2243 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2244 return false; 2245 2246 if (!isUndefOrEqual(Ops[0], 0)) 2247 return false; 2248 2249 for (unsigned i = 1; i < NumOps; ++i) { 2250 SDOperand Arg = Ops[i]; 2251 if (!(isUndefOrEqual(Arg, i+NumOps) || 2252 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) || 2253 (V2IsSplat && isUndefOrEqual(Arg, NumOps)))) 2254 return false; 2255 } 2256 2257 return true; 2258} 2259 2260static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false, 2261 bool V2IsUndef = false) { 2262 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2263 return isCommutedMOVL(N->op_begin(), N->getNumOperands(), 2264 V2IsSplat, V2IsUndef); 2265} 2266 2267/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2268/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2269bool X86::isMOVSHDUPMask(SDNode *N) { 2270 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2271 2272 if (N->getNumOperands() != 4) 2273 return false; 2274 2275 // Expect 1, 1, 3, 3 2276 for (unsigned i = 0; i < 2; ++i) { 2277 SDOperand Arg = N->getOperand(i); 2278 if (Arg.getOpcode() == ISD::UNDEF) continue; 2279 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2280 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2281 if (Val != 1) return false; 2282 } 2283 2284 bool HasHi = false; 2285 for (unsigned i = 2; i < 4; ++i) { 2286 SDOperand Arg = N->getOperand(i); 2287 if (Arg.getOpcode() == ISD::UNDEF) continue; 2288 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2289 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2290 if (Val != 3) return false; 2291 HasHi = true; 2292 } 2293 2294 // Don't use movshdup if it can be done with a shufps. 2295 return HasHi; 2296} 2297 2298/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2299/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2300bool X86::isMOVSLDUPMask(SDNode *N) { 2301 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2302 2303 if (N->getNumOperands() != 4) 2304 return false; 2305 2306 // Expect 0, 0, 2, 2 2307 for (unsigned i = 0; i < 2; ++i) { 2308 SDOperand Arg = N->getOperand(i); 2309 if (Arg.getOpcode() == ISD::UNDEF) continue; 2310 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2311 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2312 if (Val != 0) return false; 2313 } 2314 2315 bool HasHi = false; 2316 for (unsigned i = 2; i < 4; ++i) { 2317 SDOperand Arg = N->getOperand(i); 2318 if (Arg.getOpcode() == ISD::UNDEF) continue; 2319 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2320 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2321 if (Val != 2) return false; 2322 HasHi = true; 2323 } 2324 2325 // Don't use movshdup if it can be done with a shufps. 2326 return HasHi; 2327} 2328 2329/// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand 2330/// specifies a identity operation on the LHS or RHS. 2331static bool isIdentityMask(SDNode *N, bool RHS = false) { 2332 unsigned NumElems = N->getNumOperands(); 2333 for (unsigned i = 0; i < NumElems; ++i) 2334 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0))) 2335 return false; 2336 return true; 2337} 2338 2339/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2340/// a splat of a single element. 2341static bool isSplatMask(SDNode *N) { 2342 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2343 2344 // This is a splat operation if each element of the permute is the same, and 2345 // if the value doesn't reference the second vector. 2346 unsigned NumElems = N->getNumOperands(); 2347 SDOperand ElementBase; 2348 unsigned i = 0; 2349 for (; i != NumElems; ++i) { 2350 SDOperand Elt = N->getOperand(i); 2351 if (isa<ConstantSDNode>(Elt)) { 2352 ElementBase = Elt; 2353 break; 2354 } 2355 } 2356 2357 if (!ElementBase.Val) 2358 return false; 2359 2360 for (; i != NumElems; ++i) { 2361 SDOperand Arg = N->getOperand(i); 2362 if (Arg.getOpcode() == ISD::UNDEF) continue; 2363 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2364 if (Arg != ElementBase) return false; 2365 } 2366 2367 // Make sure it is a splat of the first vector operand. 2368 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems; 2369} 2370 2371/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies 2372/// a splat of a single element and it's a 2 or 4 element mask. 2373bool X86::isSplatMask(SDNode *N) { 2374 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2375 2376 // We can only splat 64-bit, and 32-bit quantities with a single instruction. 2377 if (N->getNumOperands() != 4 && N->getNumOperands() != 2) 2378 return false; 2379 return ::isSplatMask(N); 2380} 2381 2382/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand 2383/// specifies a splat of zero element. 2384bool X86::isSplatLoMask(SDNode *N) { 2385 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2386 2387 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 2388 if (!isUndefOrEqual(N->getOperand(i), 0)) 2389 return false; 2390 return true; 2391} 2392 2393/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2394/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2395/// instructions. 2396unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2397 unsigned NumOperands = N->getNumOperands(); 2398 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2399 unsigned Mask = 0; 2400 for (unsigned i = 0; i < NumOperands; ++i) { 2401 unsigned Val = 0; 2402 SDOperand Arg = N->getOperand(NumOperands-i-1); 2403 if (Arg.getOpcode() != ISD::UNDEF) 2404 Val = cast<ConstantSDNode>(Arg)->getValue(); 2405 if (Val >= NumOperands) Val -= NumOperands; 2406 Mask |= Val; 2407 if (i != NumOperands - 1) 2408 Mask <<= Shift; 2409 } 2410 2411 return Mask; 2412} 2413 2414/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2415/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2416/// instructions. 2417unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2418 unsigned Mask = 0; 2419 // 8 nodes, but we only care about the last 4. 2420 for (unsigned i = 7; i >= 4; --i) { 2421 unsigned Val = 0; 2422 SDOperand Arg = N->getOperand(i); 2423 if (Arg.getOpcode() != ISD::UNDEF) 2424 Val = cast<ConstantSDNode>(Arg)->getValue(); 2425 Mask |= (Val - 4); 2426 if (i != 4) 2427 Mask <<= 2; 2428 } 2429 2430 return Mask; 2431} 2432 2433/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2434/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2435/// instructions. 2436unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2437 unsigned Mask = 0; 2438 // 8 nodes, but we only care about the first 4. 2439 for (int i = 3; i >= 0; --i) { 2440 unsigned Val = 0; 2441 SDOperand Arg = N->getOperand(i); 2442 if (Arg.getOpcode() != ISD::UNDEF) 2443 Val = cast<ConstantSDNode>(Arg)->getValue(); 2444 Mask |= Val; 2445 if (i != 0) 2446 Mask <<= 2; 2447 } 2448 2449 return Mask; 2450} 2451 2452/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand 2453/// specifies a 8 element shuffle that can be broken into a pair of 2454/// PSHUFHW and PSHUFLW. 2455static bool isPSHUFHW_PSHUFLWMask(SDNode *N) { 2456 assert(N->getOpcode() == ISD::BUILD_VECTOR); 2457 2458 if (N->getNumOperands() != 8) 2459 return false; 2460 2461 // Lower quadword shuffled. 2462 for (unsigned i = 0; i != 4; ++i) { 2463 SDOperand Arg = N->getOperand(i); 2464 if (Arg.getOpcode() == ISD::UNDEF) continue; 2465 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2466 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2467 if (Val >= 4) 2468 return false; 2469 } 2470 2471 // Upper quadword shuffled. 2472 for (unsigned i = 4; i != 8; ++i) { 2473 SDOperand Arg = N->getOperand(i); 2474 if (Arg.getOpcode() == ISD::UNDEF) continue; 2475 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2476 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2477 if (Val < 4 || Val > 7) 2478 return false; 2479 } 2480 2481 return true; 2482} 2483 2484/// CommuteVectorShuffle - Swap vector_shuffle operands as well as 2485/// values in ther permute mask. 2486static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1, 2487 SDOperand &V2, SDOperand &Mask, 2488 SelectionDAG &DAG) { 2489 MVT::ValueType VT = Op.getValueType(); 2490 MVT::ValueType MaskVT = Mask.getValueType(); 2491 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT); 2492 unsigned NumElems = Mask.getNumOperands(); 2493 SmallVector<SDOperand, 8> MaskVec; 2494 2495 for (unsigned i = 0; i != NumElems; ++i) { 2496 SDOperand Arg = Mask.getOperand(i); 2497 if (Arg.getOpcode() == ISD::UNDEF) { 2498 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2499 continue; 2500 } 2501 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2502 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2503 if (Val < NumElems) 2504 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2505 else 2506 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2507 } 2508 2509 std::swap(V1, V2); 2510 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2511 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2512} 2513 2514/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2515/// the two vector operands have swapped position. 2516static 2517SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) { 2518 MVT::ValueType MaskVT = Mask.getValueType(); 2519 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT); 2520 unsigned NumElems = Mask.getNumOperands(); 2521 SmallVector<SDOperand, 8> MaskVec; 2522 for (unsigned i = 0; i != NumElems; ++i) { 2523 SDOperand Arg = Mask.getOperand(i); 2524 if (Arg.getOpcode() == ISD::UNDEF) { 2525 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 2526 continue; 2527 } 2528 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 2529 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2530 if (Val < NumElems) 2531 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT)); 2532 else 2533 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT)); 2534 } 2535 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems); 2536} 2537 2538 2539/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2540/// match movhlps. The lower half elements should come from upper half of 2541/// V1 (and in order), and the upper half elements should come from the upper 2542/// half of V2 (and in order). 2543static bool ShouldXformToMOVHLPS(SDNode *Mask) { 2544 unsigned NumElems = Mask->getNumOperands(); 2545 if (NumElems != 4) 2546 return false; 2547 for (unsigned i = 0, e = 2; i != e; ++i) 2548 if (!isUndefOrEqual(Mask->getOperand(i), i+2)) 2549 return false; 2550 for (unsigned i = 2; i != 4; ++i) 2551 if (!isUndefOrEqual(Mask->getOperand(i), i+4)) 2552 return false; 2553 return true; 2554} 2555 2556/// isScalarLoadToVector - Returns true if the node is a scalar load that 2557/// is promoted to a vector. 2558static inline bool isScalarLoadToVector(SDNode *N) { 2559 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) { 2560 N = N->getOperand(0).Val; 2561 return ISD::isNON_EXTLoad(N); 2562 } 2563 return false; 2564} 2565 2566/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2567/// match movlp{s|d}. The lower half elements should come from lower half of 2568/// V1 (and in order), and the upper half elements should come from the upper 2569/// half of V2 (and in order). And since V1 will become the source of the 2570/// MOVLP, it must be either a vector load or a scalar load to vector. 2571static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) { 2572 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2573 return false; 2574 // Is V2 is a vector load, don't do this transformation. We will try to use 2575 // load folding shufps op. 2576 if (ISD::isNON_EXTLoad(V2)) 2577 return false; 2578 2579 unsigned NumElems = Mask->getNumOperands(); 2580 if (NumElems != 2 && NumElems != 4) 2581 return false; 2582 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2583 if (!isUndefOrEqual(Mask->getOperand(i), i)) 2584 return false; 2585 for (unsigned i = NumElems/2; i != NumElems; ++i) 2586 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems)) 2587 return false; 2588 return true; 2589} 2590 2591/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2592/// all the same. 2593static bool isSplatVector(SDNode *N) { 2594 if (N->getOpcode() != ISD::BUILD_VECTOR) 2595 return false; 2596 2597 SDOperand SplatValue = N->getOperand(0); 2598 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2599 if (N->getOperand(i) != SplatValue) 2600 return false; 2601 return true; 2602} 2603 2604/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2605/// to an undef. 2606static bool isUndefShuffle(SDNode *N) { 2607 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2608 return false; 2609 2610 SDOperand V1 = N->getOperand(0); 2611 SDOperand V2 = N->getOperand(1); 2612 SDOperand Mask = N->getOperand(2); 2613 unsigned NumElems = Mask.getNumOperands(); 2614 for (unsigned i = 0; i != NumElems; ++i) { 2615 SDOperand Arg = Mask.getOperand(i); 2616 if (Arg.getOpcode() != ISD::UNDEF) { 2617 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2618 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF) 2619 return false; 2620 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF) 2621 return false; 2622 } 2623 } 2624 return true; 2625} 2626 2627/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2628/// constant +0.0. 2629static inline bool isZeroNode(SDOperand Elt) { 2630 return ((isa<ConstantSDNode>(Elt) && 2631 cast<ConstantSDNode>(Elt)->getValue() == 0) || 2632 (isa<ConstantFPSDNode>(Elt) && 2633 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2634} 2635 2636/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2637/// to an zero vector. 2638static bool isZeroShuffle(SDNode *N) { 2639 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) 2640 return false; 2641 2642 SDOperand V1 = N->getOperand(0); 2643 SDOperand V2 = N->getOperand(1); 2644 SDOperand Mask = N->getOperand(2); 2645 unsigned NumElems = Mask.getNumOperands(); 2646 for (unsigned i = 0; i != NumElems; ++i) { 2647 SDOperand Arg = Mask.getOperand(i); 2648 if (Arg.getOpcode() == ISD::UNDEF) 2649 continue; 2650 2651 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 2652 if (Idx < NumElems) { 2653 unsigned Opc = V1.Val->getOpcode(); 2654 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val)) 2655 continue; 2656 if (Opc != ISD::BUILD_VECTOR || 2657 !isZeroNode(V1.Val->getOperand(Idx))) 2658 return false; 2659 } else if (Idx >= NumElems) { 2660 unsigned Opc = V2.Val->getOpcode(); 2661 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val)) 2662 continue; 2663 if (Opc != ISD::BUILD_VECTOR || 2664 !isZeroNode(V2.Val->getOperand(Idx - NumElems))) 2665 return false; 2666 } 2667 } 2668 return true; 2669} 2670 2671/// getZeroVector - Returns a vector of specified type with all zero elements. 2672/// 2673static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) { 2674 assert(MVT::isVector(VT) && "Expected a vector type"); 2675 2676 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2677 // type. This ensures they get CSE'd. 2678 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32); 2679 SDOperand Vec; 2680 if (MVT::getSizeInBits(VT) == 64) // MMX 2681 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2682 else // SSE 2683 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2684 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2685} 2686 2687/// getOnesVector - Returns a vector of specified type with all bits set. 2688/// 2689static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) { 2690 assert(MVT::isVector(VT) && "Expected a vector type"); 2691 2692 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2693 // type. This ensures they get CSE'd. 2694 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32); 2695 SDOperand Vec; 2696 if (MVT::getSizeInBits(VT) == 64) // MMX 2697 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst); 2698 else // SSE 2699 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst); 2700 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec); 2701} 2702 2703 2704/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2705/// that point to V2 points to its first element. 2706static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) { 2707 assert(Mask.getOpcode() == ISD::BUILD_VECTOR); 2708 2709 bool Changed = false; 2710 SmallVector<SDOperand, 8> MaskVec; 2711 unsigned NumElems = Mask.getNumOperands(); 2712 for (unsigned i = 0; i != NumElems; ++i) { 2713 SDOperand Arg = Mask.getOperand(i); 2714 if (Arg.getOpcode() != ISD::UNDEF) { 2715 unsigned Val = cast<ConstantSDNode>(Arg)->getValue(); 2716 if (Val > NumElems) { 2717 Arg = DAG.getConstant(NumElems, Arg.getValueType()); 2718 Changed = true; 2719 } 2720 } 2721 MaskVec.push_back(Arg); 2722 } 2723 2724 if (Changed) 2725 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), 2726 &MaskVec[0], MaskVec.size()); 2727 return Mask; 2728} 2729 2730/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2731/// operation of specified width. 2732static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) { 2733 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2734 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); 2735 2736 SmallVector<SDOperand, 8> MaskVec; 2737 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT)); 2738 for (unsigned i = 1; i != NumElems; ++i) 2739 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2740 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2741} 2742 2743/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation 2744/// of specified width. 2745static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) { 2746 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2747 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); 2748 SmallVector<SDOperand, 8> MaskVec; 2749 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 2750 MaskVec.push_back(DAG.getConstant(i, BaseVT)); 2751 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT)); 2752 } 2753 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2754} 2755 2756/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation 2757/// of specified width. 2758static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) { 2759 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2760 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); 2761 unsigned Half = NumElems/2; 2762 SmallVector<SDOperand, 8> MaskVec; 2763 for (unsigned i = 0; i != Half; ++i) { 2764 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT)); 2765 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT)); 2766 } 2767 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2768} 2769 2770/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps 2771/// element #0 of a vector with the specified index, leaving the rest of the 2772/// elements in place. 2773static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt, 2774 SelectionDAG &DAG) { 2775 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2776 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT); 2777 SmallVector<SDOperand, 8> MaskVec; 2778 // Element #0 of the result gets the elt we are replacing. 2779 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT)); 2780 for (unsigned i = 1; i != NumElems; ++i) 2781 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT)); 2782 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size()); 2783} 2784 2785/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32. 2786/// 2787static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) { 2788 SDOperand V1 = Op.getOperand(0); 2789 SDOperand Mask = Op.getOperand(2); 2790 MVT::ValueType VT = Op.getValueType(); 2791 unsigned NumElems = Mask.getNumOperands(); 2792 Mask = getUnpacklMask(NumElems, DAG); 2793 while (NumElems != 4) { 2794 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask); 2795 NumElems >>= 1; 2796 } 2797 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1); 2798 2799 Mask = getZeroVector(MVT::v4i32, DAG); 2800 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1, 2801 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask); 2802 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle); 2803} 2804 2805/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 2806/// vector of zero or undef vector. This produces a shuffle where the low 2807/// element of V2 is swizzled into the zero/undef vector, landing at element 2808/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 2809static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx, 2810 bool isZero, SelectionDAG &DAG) { 2811 MVT::ValueType VT = V2.getValueType(); 2812 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT); 2813 unsigned NumElems = MVT::getVectorNumElements(V2.getValueType()); 2814 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 2815 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT); 2816 SmallVector<SDOperand, 16> MaskVec; 2817 for (unsigned i = 0; i != NumElems; ++i) 2818 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here. 2819 MaskVec.push_back(DAG.getConstant(NumElems, EVT)); 2820 else 2821 MaskVec.push_back(DAG.getConstant(i, EVT)); 2822 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 2823 &MaskVec[0], MaskVec.size()); 2824 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask); 2825} 2826 2827/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 2828/// 2829static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros, 2830 unsigned NumNonZero, unsigned NumZero, 2831 SelectionDAG &DAG, TargetLowering &TLI) { 2832 if (NumNonZero > 8) 2833 return SDOperand(); 2834 2835 SDOperand V(0, 0); 2836 bool First = true; 2837 for (unsigned i = 0; i < 16; ++i) { 2838 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 2839 if (ThisIsNonZero && First) { 2840 if (NumZero) 2841 V = getZeroVector(MVT::v8i16, DAG); 2842 else 2843 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 2844 First = false; 2845 } 2846 2847 if ((i & 1) != 0) { 2848 SDOperand ThisElt(0, 0), LastElt(0, 0); 2849 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 2850 if (LastIsNonZero) { 2851 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1)); 2852 } 2853 if (ThisIsNonZero) { 2854 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i)); 2855 ThisElt = DAG.getNode(ISD::SHL, MVT::i16, 2856 ThisElt, DAG.getConstant(8, MVT::i8)); 2857 if (LastIsNonZero) 2858 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt); 2859 } else 2860 ThisElt = LastElt; 2861 2862 if (ThisElt.Val) 2863 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt, 2864 DAG.getIntPtrConstant(i/2)); 2865 } 2866 } 2867 2868 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V); 2869} 2870 2871/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 2872/// 2873static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros, 2874 unsigned NumNonZero, unsigned NumZero, 2875 SelectionDAG &DAG, TargetLowering &TLI) { 2876 if (NumNonZero > 4) 2877 return SDOperand(); 2878 2879 SDOperand V(0, 0); 2880 bool First = true; 2881 for (unsigned i = 0; i < 8; ++i) { 2882 bool isNonZero = (NonZeros & (1 << i)) != 0; 2883 if (isNonZero) { 2884 if (First) { 2885 if (NumZero) 2886 V = getZeroVector(MVT::v8i16, DAG); 2887 else 2888 V = DAG.getNode(ISD::UNDEF, MVT::v8i16); 2889 First = false; 2890 } 2891 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i), 2892 DAG.getIntPtrConstant(i)); 2893 } 2894 } 2895 2896 return V; 2897} 2898 2899SDOperand 2900X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2901 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 2902 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) { 2903 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 2904 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 2905 // eliminated on x86-32 hosts. 2906 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 2907 return Op; 2908 2909 if (ISD::isBuildVectorAllOnes(Op.Val)) 2910 return getOnesVector(Op.getValueType(), DAG); 2911 return getZeroVector(Op.getValueType(), DAG); 2912 } 2913 2914 MVT::ValueType VT = Op.getValueType(); 2915 MVT::ValueType EVT = MVT::getVectorElementType(VT); 2916 unsigned EVTBits = MVT::getSizeInBits(EVT); 2917 2918 unsigned NumElems = Op.getNumOperands(); 2919 unsigned NumZero = 0; 2920 unsigned NumNonZero = 0; 2921 unsigned NonZeros = 0; 2922 bool IsAllConstants = true; 2923 SmallSet<SDOperand, 8> Values; 2924 for (unsigned i = 0; i < NumElems; ++i) { 2925 SDOperand Elt = Op.getOperand(i); 2926 if (Elt.getOpcode() == ISD::UNDEF) 2927 continue; 2928 Values.insert(Elt); 2929 if (Elt.getOpcode() != ISD::Constant && 2930 Elt.getOpcode() != ISD::ConstantFP) 2931 IsAllConstants = false; 2932 if (isZeroNode(Elt)) 2933 NumZero++; 2934 else { 2935 NonZeros |= (1 << i); 2936 NumNonZero++; 2937 } 2938 } 2939 2940 if (NumNonZero == 0) { 2941 // All undef vector. Return an UNDEF. All zero vectors were handled above. 2942 return DAG.getNode(ISD::UNDEF, VT); 2943 } 2944 2945 // Special case for single non-zero, non-undef, element. 2946 if (NumNonZero == 1 && NumElems <= 4) { 2947 unsigned Idx = CountTrailingZeros_32(NonZeros); 2948 SDOperand Item = Op.getOperand(Idx); 2949 2950 // If this is an insertion of an i64 value on x86-32, and if the top bits of 2951 // the value are obviously zero, truncate the value to i32 and do the 2952 // insertion that way. Only do this if the value is non-constant or if the 2953 // value is a constant being inserted into element 0. It is cheaper to do 2954 // a constant pool load than it is to do a movd + shuffle. 2955 if (EVT == MVT::i64 && !Subtarget->is64Bit() && 2956 (!IsAllConstants || Idx == 0)) { 2957 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 2958 // Handle MMX and SSE both. 2959 MVT::ValueType VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 2960 MVT::ValueType VecElts = VT == MVT::v2i64 ? 4 : 2; 2961 2962 // Truncate the value (which may itself be a constant) to i32, and 2963 // convert it to a vector with movd (S2V+shuffle to zero extend). 2964 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item); 2965 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item); 2966 Item = getShuffleVectorZeroOrUndef(Item, 0, true, DAG); 2967 2968 // Now we have our 32-bit value zero extended in the low element of 2969 // a vector. If Idx != 0, swizzle it into place. 2970 if (Idx != 0) { 2971 SDOperand Ops[] = { 2972 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()), 2973 getSwapEltZeroMask(VecElts, Idx, DAG) 2974 }; 2975 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3); 2976 } 2977 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item); 2978 } 2979 } 2980 2981 // If we have a constant or non-constant insertion into the low element of 2982 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 2983 // the rest of the elements. This will be matched as movd/movq/movss/movsd 2984 // depending on what the source datatype is. Because we can only get here 2985 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64. 2986 if (Idx == 0 && 2987 // Don't do this for i64 values on x86-32. 2988 (EVT != MVT::i64 || Subtarget->is64Bit())) { 2989 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 2990 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 2991 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG); 2992 } 2993 2994 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 2995 return SDOperand(); 2996 2997 // Otherwise, if this is a vector with i32 or f32 elements, and the element 2998 // is a non-constant being inserted into an element other than the low one, 2999 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3000 // movd/movss) to move this into the low element, then shuffle it into 3001 // place. 3002 if (EVTBits == 32) { 3003 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item); 3004 3005 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3006 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, DAG); 3007 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3008 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); 3009 SmallVector<SDOperand, 8> MaskVec; 3010 for (unsigned i = 0; i < NumElems; i++) 3011 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT)); 3012 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3013 &MaskVec[0], MaskVec.size()); 3014 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item, 3015 DAG.getNode(ISD::UNDEF, VT), Mask); 3016 } 3017 } 3018 3019 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3020 if (Values.size() == 1) 3021 return SDOperand(); 3022 3023 // A vector full of immediates; various special cases are already 3024 // handled, so this is best done with a single constant-pool load. 3025 if (IsAllConstants) 3026 return SDOperand(); 3027 3028 // Let legalizer expand 2-wide build_vectors. 3029 if (EVTBits == 64) 3030 return SDOperand(); 3031 3032 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3033 if (EVTBits == 8 && NumElems == 16) { 3034 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3035 *this); 3036 if (V.Val) return V; 3037 } 3038 3039 if (EVTBits == 16 && NumElems == 8) { 3040 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3041 *this); 3042 if (V.Val) return V; 3043 } 3044 3045 // If element VT is == 32 bits, turn it into a number of shuffles. 3046 SmallVector<SDOperand, 8> V; 3047 V.resize(NumElems); 3048 if (NumElems == 4 && NumZero > 0) { 3049 for (unsigned i = 0; i < 4; ++i) { 3050 bool isZero = !(NonZeros & (1 << i)); 3051 if (isZero) 3052 V[i] = getZeroVector(VT, DAG); 3053 else 3054 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3055 } 3056 3057 for (unsigned i = 0; i < 2; ++i) { 3058 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3059 default: break; 3060 case 0: 3061 V[i] = V[i*2]; // Must be a zero vector. 3062 break; 3063 case 1: 3064 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2], 3065 getMOVLMask(NumElems, DAG)); 3066 break; 3067 case 2: 3068 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3069 getMOVLMask(NumElems, DAG)); 3070 break; 3071 case 3: 3072 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1], 3073 getUnpacklMask(NumElems, DAG)); 3074 break; 3075 } 3076 } 3077 3078 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd) 3079 // clears the upper bits. 3080 // FIXME: we can do the same for v4f32 case when we know both parts of 3081 // the lower half come from scalar_to_vector (loadf32). We should do 3082 // that in post legalizer dag combiner with target specific hooks. 3083 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0) 3084 return V[0]; 3085 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 3086 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT); 3087 SmallVector<SDOperand, 8> MaskVec; 3088 bool Reverse = (NonZeros & 0x3) == 2; 3089 for (unsigned i = 0; i < 2; ++i) 3090 if (Reverse) 3091 MaskVec.push_back(DAG.getConstant(1-i, EVT)); 3092 else 3093 MaskVec.push_back(DAG.getConstant(i, EVT)); 3094 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3095 for (unsigned i = 0; i < 2; ++i) 3096 if (Reverse) 3097 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT)); 3098 else 3099 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT)); 3100 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3101 &MaskVec[0], MaskVec.size()); 3102 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask); 3103 } 3104 3105 if (Values.size() > 2) { 3106 // Expand into a number of unpckl*. 3107 // e.g. for v4f32 3108 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3109 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3110 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3111 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG); 3112 for (unsigned i = 0; i < NumElems; ++i) 3113 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i)); 3114 NumElems >>= 1; 3115 while (NumElems != 0) { 3116 for (unsigned i = 0; i < NumElems; ++i) 3117 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems], 3118 UnpckMask); 3119 NumElems >>= 1; 3120 } 3121 return V[0]; 3122 } 3123 3124 return SDOperand(); 3125} 3126 3127static 3128SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2, 3129 SDOperand PermMask, SelectionDAG &DAG, 3130 TargetLowering &TLI) { 3131 SDOperand NewV; 3132 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8); 3133 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); 3134 MVT::ValueType PtrVT = TLI.getPointerTy(); 3135 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(), 3136 PermMask.Val->op_end()); 3137 3138 // First record which half of which vector the low elements come from. 3139 SmallVector<unsigned, 4> LowQuad(4); 3140 for (unsigned i = 0; i < 4; ++i) { 3141 SDOperand Elt = MaskElts[i]; 3142 if (Elt.getOpcode() == ISD::UNDEF) 3143 continue; 3144 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3145 int QuadIdx = EltIdx / 4; 3146 ++LowQuad[QuadIdx]; 3147 } 3148 int BestLowQuad = -1; 3149 unsigned MaxQuad = 1; 3150 for (unsigned i = 0; i < 4; ++i) { 3151 if (LowQuad[i] > MaxQuad) { 3152 BestLowQuad = i; 3153 MaxQuad = LowQuad[i]; 3154 } 3155 } 3156 3157 // Record which half of which vector the high elements come from. 3158 SmallVector<unsigned, 4> HighQuad(4); 3159 for (unsigned i = 4; i < 8; ++i) { 3160 SDOperand Elt = MaskElts[i]; 3161 if (Elt.getOpcode() == ISD::UNDEF) 3162 continue; 3163 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3164 int QuadIdx = EltIdx / 4; 3165 ++HighQuad[QuadIdx]; 3166 } 3167 int BestHighQuad = -1; 3168 MaxQuad = 1; 3169 for (unsigned i = 0; i < 4; ++i) { 3170 if (HighQuad[i] > MaxQuad) { 3171 BestHighQuad = i; 3172 MaxQuad = HighQuad[i]; 3173 } 3174 } 3175 3176 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it. 3177 if (BestLowQuad != -1 || BestHighQuad != -1) { 3178 // First sort the 4 chunks in order using shufpd. 3179 SmallVector<SDOperand, 8> MaskVec; 3180 if (BestLowQuad != -1) 3181 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32)); 3182 else 3183 MaskVec.push_back(DAG.getConstant(0, MVT::i32)); 3184 if (BestHighQuad != -1) 3185 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32)); 3186 else 3187 MaskVec.push_back(DAG.getConstant(1, MVT::i32)); 3188 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2); 3189 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64, 3190 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1), 3191 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask); 3192 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV); 3193 3194 // Now sort high and low parts separately. 3195 BitVector InOrder(8); 3196 if (BestLowQuad != -1) { 3197 // Sort lower half in order using PSHUFLW. 3198 MaskVec.clear(); 3199 bool AnyOutOrder = false; 3200 for (unsigned i = 0; i != 4; ++i) { 3201 SDOperand Elt = MaskElts[i]; 3202 if (Elt.getOpcode() == ISD::UNDEF) { 3203 MaskVec.push_back(Elt); 3204 InOrder.set(i); 3205 } else { 3206 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3207 if (EltIdx != i) 3208 AnyOutOrder = true; 3209 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT)); 3210 // If this element is in the right place after this shuffle, then 3211 // remember it. 3212 if ((int)(EltIdx / 4) == BestLowQuad) 3213 InOrder.set(i); 3214 } 3215 } 3216 if (AnyOutOrder) { 3217 for (unsigned i = 4; i != 8; ++i) 3218 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3219 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3220 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3221 } 3222 } 3223 3224 if (BestHighQuad != -1) { 3225 // Sort high half in order using PSHUFHW if possible. 3226 MaskVec.clear(); 3227 for (unsigned i = 0; i != 4; ++i) 3228 MaskVec.push_back(DAG.getConstant(i, MaskEVT)); 3229 bool AnyOutOrder = false; 3230 for (unsigned i = 4; i != 8; ++i) { 3231 SDOperand Elt = MaskElts[i]; 3232 if (Elt.getOpcode() == ISD::UNDEF) { 3233 MaskVec.push_back(Elt); 3234 InOrder.set(i); 3235 } else { 3236 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3237 if (EltIdx != i) 3238 AnyOutOrder = true; 3239 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT)); 3240 // If this element is in the right place after this shuffle, then 3241 // remember it. 3242 if ((int)(EltIdx / 4) == BestHighQuad) 3243 InOrder.set(i); 3244 } 3245 } 3246 if (AnyOutOrder) { 3247 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3248 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask); 3249 } 3250 } 3251 3252 // The other elements are put in the right place using pextrw and pinsrw. 3253 for (unsigned i = 0; i != 8; ++i) { 3254 if (InOrder[i]) 3255 continue; 3256 SDOperand Elt = MaskElts[i]; 3257 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3258 if (EltIdx == i) 3259 continue; 3260 SDOperand ExtOp = (EltIdx < 8) 3261 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3262 DAG.getConstant(EltIdx, PtrVT)) 3263 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3264 DAG.getConstant(EltIdx - 8, PtrVT)); 3265 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3266 DAG.getConstant(i, PtrVT)); 3267 } 3268 return NewV; 3269 } 3270 3271 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use 3272 ///as few as possible. 3273 // First, let's find out how many elements are already in the right order. 3274 unsigned V1InOrder = 0; 3275 unsigned V1FromV1 = 0; 3276 unsigned V2InOrder = 0; 3277 unsigned V2FromV2 = 0; 3278 SmallVector<SDOperand, 8> V1Elts; 3279 SmallVector<SDOperand, 8> V2Elts; 3280 for (unsigned i = 0; i < 8; ++i) { 3281 SDOperand Elt = MaskElts[i]; 3282 if (Elt.getOpcode() == ISD::UNDEF) { 3283 V1Elts.push_back(Elt); 3284 V2Elts.push_back(Elt); 3285 ++V1InOrder; 3286 ++V2InOrder; 3287 continue; 3288 } 3289 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3290 if (EltIdx == i) { 3291 V1Elts.push_back(Elt); 3292 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT)); 3293 ++V1InOrder; 3294 } else if (EltIdx == i+8) { 3295 V1Elts.push_back(Elt); 3296 V2Elts.push_back(DAG.getConstant(i, MaskEVT)); 3297 ++V2InOrder; 3298 } else if (EltIdx < 8) { 3299 V1Elts.push_back(Elt); 3300 ++V1FromV1; 3301 } else { 3302 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT)); 3303 ++V2FromV2; 3304 } 3305 } 3306 3307 if (V2InOrder > V1InOrder) { 3308 PermMask = CommuteVectorShuffleMask(PermMask, DAG); 3309 std::swap(V1, V2); 3310 std::swap(V1Elts, V2Elts); 3311 std::swap(V1FromV1, V2FromV2); 3312 } 3313 3314 if ((V1FromV1 + V1InOrder) != 8) { 3315 // Some elements are from V2. 3316 if (V1FromV1) { 3317 // If there are elements that are from V1 but out of place, 3318 // then first sort them in place 3319 SmallVector<SDOperand, 8> MaskVec; 3320 for (unsigned i = 0; i < 8; ++i) { 3321 SDOperand Elt = V1Elts[i]; 3322 if (Elt.getOpcode() == ISD::UNDEF) { 3323 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3324 continue; 3325 } 3326 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3327 if (EltIdx >= 8) 3328 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3329 else 3330 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT)); 3331 } 3332 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8); 3333 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask); 3334 } 3335 3336 NewV = V1; 3337 for (unsigned i = 0; i < 8; ++i) { 3338 SDOperand Elt = V1Elts[i]; 3339 if (Elt.getOpcode() == ISD::UNDEF) 3340 continue; 3341 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3342 if (EltIdx < 8) 3343 continue; 3344 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2, 3345 DAG.getConstant(EltIdx - 8, PtrVT)); 3346 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3347 DAG.getConstant(i, PtrVT)); 3348 } 3349 return NewV; 3350 } else { 3351 // All elements are from V1. 3352 NewV = V1; 3353 for (unsigned i = 0; i < 8; ++i) { 3354 SDOperand Elt = V1Elts[i]; 3355 if (Elt.getOpcode() == ISD::UNDEF) 3356 continue; 3357 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3358 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1, 3359 DAG.getConstant(EltIdx, PtrVT)); 3360 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp, 3361 DAG.getConstant(i, PtrVT)); 3362 } 3363 return NewV; 3364 } 3365} 3366 3367/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3368/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3369/// done when every pair / quad of shuffle mask elements point to elements in 3370/// the right sequence. e.g. 3371/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3372static 3373SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2, 3374 MVT::ValueType VT, 3375 SDOperand PermMask, SelectionDAG &DAG, 3376 TargetLowering &TLI) { 3377 unsigned NumElems = PermMask.getNumOperands(); 3378 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3379 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3380 MVT::ValueType NewVT = MaskVT; 3381 switch (VT) { 3382 case MVT::v4f32: NewVT = MVT::v2f64; break; 3383 case MVT::v4i32: NewVT = MVT::v2i64; break; 3384 case MVT::v8i16: NewVT = MVT::v4i32; break; 3385 case MVT::v16i8: NewVT = MVT::v4i32; break; 3386 default: assert(false && "Unexpected!"); 3387 } 3388 3389 if (NewWidth == 2) { 3390 if (MVT::isInteger(VT)) 3391 NewVT = MVT::v2i64; 3392 else 3393 NewVT = MVT::v2f64; 3394 } 3395 unsigned Scale = NumElems / NewWidth; 3396 SmallVector<SDOperand, 8> MaskVec; 3397 for (unsigned i = 0; i < NumElems; i += Scale) { 3398 unsigned StartIdx = ~0U; 3399 for (unsigned j = 0; j < Scale; ++j) { 3400 SDOperand Elt = PermMask.getOperand(i+j); 3401 if (Elt.getOpcode() == ISD::UNDEF) 3402 continue; 3403 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue(); 3404 if (StartIdx == ~0U) 3405 StartIdx = EltIdx - (EltIdx % Scale); 3406 if (EltIdx != StartIdx + j) 3407 return SDOperand(); 3408 } 3409 if (StartIdx == ~0U) 3410 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 3411 else 3412 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32)); 3413 } 3414 3415 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1); 3416 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2); 3417 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2, 3418 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3419 &MaskVec[0], MaskVec.size())); 3420} 3421 3422SDOperand 3423X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 3424 SDOperand V1 = Op.getOperand(0); 3425 SDOperand V2 = Op.getOperand(1); 3426 SDOperand PermMask = Op.getOperand(2); 3427 MVT::ValueType VT = Op.getValueType(); 3428 unsigned NumElems = PermMask.getNumOperands(); 3429 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 3430 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 3431 bool V1IsSplat = false; 3432 bool V2IsSplat = false; 3433 3434 if (isUndefShuffle(Op.Val)) 3435 return DAG.getNode(ISD::UNDEF, VT); 3436 3437 if (isZeroShuffle(Op.Val)) 3438 return getZeroVector(VT, DAG); 3439 3440 if (isIdentityMask(PermMask.Val)) 3441 return V1; 3442 else if (isIdentityMask(PermMask.Val, true)) 3443 return V2; 3444 3445 if (isSplatMask(PermMask.Val)) { 3446 if (NumElems <= 4) return Op; 3447 // Promote it to a v4i32 splat. 3448 return PromoteSplat(Op, DAG); 3449 } 3450 3451 // If the shuffle can be profitably rewritten as a narrower shuffle, then 3452 // do it! 3453 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 3454 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); 3455 if (NewOp.Val) 3456 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); 3457 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 3458 // FIXME: Figure out a cleaner way to do this. 3459 // Try to make use of movq to zero out the top part. 3460 if (ISD::isBuildVectorAllZeros(V2.Val)) { 3461 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); 3462 if (NewOp.Val) { 3463 SDOperand NewV1 = NewOp.getOperand(0); 3464 SDOperand NewV2 = NewOp.getOperand(1); 3465 SDOperand NewMask = NewOp.getOperand(2); 3466 if (isCommutedMOVL(NewMask.Val, true, false)) { 3467 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG); 3468 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(), 3469 NewV1, NewV2, getMOVLMask(2, DAG)); 3470 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); 3471 } 3472 } 3473 } else if (ISD::isBuildVectorAllZeros(V1.Val)) { 3474 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this); 3475 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val)) 3476 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); 3477 } 3478 } 3479 3480 if (X86::isMOVLMask(PermMask.Val)) 3481 return (V1IsUndef) ? V2 : Op; 3482 3483 if (X86::isMOVSHDUPMask(PermMask.Val) || 3484 X86::isMOVSLDUPMask(PermMask.Val) || 3485 X86::isMOVHLPSMask(PermMask.Val) || 3486 X86::isMOVHPMask(PermMask.Val) || 3487 X86::isMOVLPMask(PermMask.Val)) 3488 return Op; 3489 3490 if (ShouldXformToMOVHLPS(PermMask.Val) || 3491 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val)) 3492 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3493 3494 bool Commuted = false; 3495 // FIXME: This should also accept a bitcast of a splat? Be careful, not 3496 // 1,1,1,1 -> v8i16 though. 3497 V1IsSplat = isSplatVector(V1.Val); 3498 V2IsSplat = isSplatVector(V2.Val); 3499 3500 // Canonicalize the splat or undef, if present, to be on the RHS. 3501 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 3502 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3503 std::swap(V1IsSplat, V2IsSplat); 3504 std::swap(V1IsUndef, V2IsUndef); 3505 Commuted = true; 3506 } 3507 3508 // FIXME: Figure out a cleaner way to do this. 3509 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) { 3510 if (V2IsUndef) return V1; 3511 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3512 if (V2IsSplat) { 3513 // V2 is a splat, so the mask may be malformed. That is, it may point 3514 // to any V2 element. The instruction selectior won't like this. Get 3515 // a corrected mask and commute to form a proper MOVS{S|D}. 3516 SDOperand NewMask = getMOVLMask(NumElems, DAG); 3517 if (NewMask.Val != PermMask.Val) 3518 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3519 } 3520 return Op; 3521 } 3522 3523 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 3524 X86::isUNPCKH_v_undef_Mask(PermMask.Val) || 3525 X86::isUNPCKLMask(PermMask.Val) || 3526 X86::isUNPCKHMask(PermMask.Val)) 3527 return Op; 3528 3529 if (V2IsSplat) { 3530 // Normalize mask so all entries that point to V2 points to its first 3531 // element then try to match unpck{h|l} again. If match, return a 3532 // new vector_shuffle with the corrected mask. 3533 SDOperand NewMask = NormalizeMask(PermMask, DAG); 3534 if (NewMask.Val != PermMask.Val) { 3535 if (X86::isUNPCKLMask(PermMask.Val, true)) { 3536 SDOperand NewMask = getUnpacklMask(NumElems, DAG); 3537 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3538 } else if (X86::isUNPCKHMask(PermMask.Val, true)) { 3539 SDOperand NewMask = getUnpackhMask(NumElems, DAG); 3540 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask); 3541 } 3542 } 3543 } 3544 3545 // Normalize the node to match x86 shuffle ops if needed 3546 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val)) 3547 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3548 3549 if (Commuted) { 3550 // Commute is back and try unpck* again. 3551 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG); 3552 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || 3553 X86::isUNPCKH_v_undef_Mask(PermMask.Val) || 3554 X86::isUNPCKLMask(PermMask.Val) || 3555 X86::isUNPCKHMask(PermMask.Val)) 3556 return Op; 3557 } 3558 3559 // If VT is integer, try PSHUF* first, then SHUFP*. 3560 if (MVT::isInteger(VT)) { 3561 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically 3562 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented. 3563 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) && 3564 X86::isPSHUFDMask(PermMask.Val)) || 3565 X86::isPSHUFHWMask(PermMask.Val) || 3566 X86::isPSHUFLWMask(PermMask.Val)) { 3567 if (V2.getOpcode() != ISD::UNDEF) 3568 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 3569 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 3570 return Op; 3571 } 3572 3573 if (X86::isSHUFPMask(PermMask.Val) && 3574 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX. 3575 return Op; 3576 } else { 3577 // Floating point cases in the other order. 3578 if (X86::isSHUFPMask(PermMask.Val)) 3579 return Op; 3580 if (X86::isPSHUFDMask(PermMask.Val) || 3581 X86::isPSHUFHWMask(PermMask.Val) || 3582 X86::isPSHUFLWMask(PermMask.Val)) { 3583 if (V2.getOpcode() != ISD::UNDEF) 3584 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, 3585 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask); 3586 return Op; 3587 } 3588 } 3589 3590 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 3591 if (VT == MVT::v8i16) { 3592 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this); 3593 if (NewOp.Val) 3594 return NewOp; 3595 } 3596 3597 // Handle all 4 wide cases with a number of shuffles. 3598 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) { 3599 // Don't do this for MMX. 3600 MVT::ValueType MaskVT = PermMask.getValueType(); 3601 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT); 3602 SmallVector<std::pair<int, int>, 8> Locs; 3603 Locs.reserve(NumElems); 3604 SmallVector<SDOperand, 8> Mask1(NumElems, 3605 DAG.getNode(ISD::UNDEF, MaskEVT)); 3606 SmallVector<SDOperand, 8> Mask2(NumElems, 3607 DAG.getNode(ISD::UNDEF, MaskEVT)); 3608 unsigned NumHi = 0; 3609 unsigned NumLo = 0; 3610 // If no more than two elements come from either vector. This can be 3611 // implemented with two shuffles. First shuffle gather the elements. 3612 // The second shuffle, which takes the first shuffle as both of its 3613 // vector operands, put the elements into the right order. 3614 for (unsigned i = 0; i != NumElems; ++i) { 3615 SDOperand Elt = PermMask.getOperand(i); 3616 if (Elt.getOpcode() == ISD::UNDEF) { 3617 Locs[i] = std::make_pair(-1, -1); 3618 } else { 3619 unsigned Val = cast<ConstantSDNode>(Elt)->getValue(); 3620 if (Val < NumElems) { 3621 Locs[i] = std::make_pair(0, NumLo); 3622 Mask1[NumLo] = Elt; 3623 NumLo++; 3624 } else { 3625 Locs[i] = std::make_pair(1, NumHi); 3626 if (2+NumHi < NumElems) 3627 Mask1[2+NumHi] = Elt; 3628 NumHi++; 3629 } 3630 } 3631 } 3632 if (NumLo <= 2 && NumHi <= 2) { 3633 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3634 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3635 &Mask1[0], Mask1.size())); 3636 for (unsigned i = 0; i != NumElems; ++i) { 3637 if (Locs[i].first == -1) 3638 continue; 3639 else { 3640 unsigned Idx = (i < NumElems/2) ? 0 : NumElems; 3641 Idx += Locs[i].first * (NumElems/2) + Locs[i].second; 3642 Mask2[i] = DAG.getConstant(Idx, MaskEVT); 3643 } 3644 } 3645 3646 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, 3647 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3648 &Mask2[0], Mask2.size())); 3649 } 3650 3651 // Break it into (shuffle shuffle_hi, shuffle_lo). 3652 Locs.clear(); 3653 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3654 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT)); 3655 SmallVector<SDOperand,8> *MaskPtr = &LoMask; 3656 unsigned MaskIdx = 0; 3657 unsigned LoIdx = 0; 3658 unsigned HiIdx = NumElems/2; 3659 for (unsigned i = 0; i != NumElems; ++i) { 3660 if (i == NumElems/2) { 3661 MaskPtr = &HiMask; 3662 MaskIdx = 1; 3663 LoIdx = 0; 3664 HiIdx = NumElems/2; 3665 } 3666 SDOperand Elt = PermMask.getOperand(i); 3667 if (Elt.getOpcode() == ISD::UNDEF) { 3668 Locs[i] = std::make_pair(-1, -1); 3669 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) { 3670 Locs[i] = std::make_pair(MaskIdx, LoIdx); 3671 (*MaskPtr)[LoIdx] = Elt; 3672 LoIdx++; 3673 } else { 3674 Locs[i] = std::make_pair(MaskIdx, HiIdx); 3675 (*MaskPtr)[HiIdx] = Elt; 3676 HiIdx++; 3677 } 3678 } 3679 3680 SDOperand LoShuffle = 3681 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3682 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3683 &LoMask[0], LoMask.size())); 3684 SDOperand HiShuffle = 3685 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, 3686 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3687 &HiMask[0], HiMask.size())); 3688 SmallVector<SDOperand, 8> MaskOps; 3689 for (unsigned i = 0; i != NumElems; ++i) { 3690 if (Locs[i].first == -1) { 3691 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT)); 3692 } else { 3693 unsigned Idx = Locs[i].first * NumElems + Locs[i].second; 3694 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT)); 3695 } 3696 } 3697 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle, 3698 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3699 &MaskOps[0], MaskOps.size())); 3700 } 3701 3702 return SDOperand(); 3703} 3704 3705SDOperand 3706X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op, 3707 SelectionDAG &DAG) { 3708 MVT::ValueType VT = Op.getValueType(); 3709 if (MVT::getSizeInBits(VT) == 8) { 3710 SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32, 3711 Op.getOperand(0), Op.getOperand(1)); 3712 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 3713 DAG.getValueType(VT)); 3714 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 3715 } else if (MVT::getSizeInBits(VT) == 16) { 3716 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32, 3717 Op.getOperand(0), Op.getOperand(1)); 3718 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract, 3719 DAG.getValueType(VT)); 3720 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 3721 } else if (VT == MVT::f32) { 3722 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 3723 // the result back to FR32 register. It's only worth matching if the 3724 // result has a single use which is a store. 3725 if (!Op.hasOneUse()) 3726 return SDOperand(); 3727 SDNode *User = *Op.Val->use_begin(); 3728 if (User->getOpcode() != ISD::STORE) 3729 return SDOperand(); 3730 SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 3731 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)), 3732 Op.getOperand(1)); 3733 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract); 3734 } 3735 return SDOperand(); 3736} 3737 3738 3739SDOperand 3740X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 3741 if (!isa<ConstantSDNode>(Op.getOperand(1))) 3742 return SDOperand(); 3743 3744 if (Subtarget->hasSSE41()) { 3745 SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 3746 if (Res.Val) 3747 return Res; 3748 } 3749 3750 MVT::ValueType VT = Op.getValueType(); 3751 // TODO: handle v16i8. 3752 if (MVT::getSizeInBits(VT) == 16) { 3753 SDOperand Vec = Op.getOperand(0); 3754 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3755 if (Idx == 0) 3756 return DAG.getNode(ISD::TRUNCATE, MVT::i16, 3757 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, 3758 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec), 3759 Op.getOperand(1))); 3760 // Transform it so it match pextrw which produces a 32-bit result. 3761 MVT::ValueType EVT = (MVT::ValueType)(VT+1); 3762 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT, 3763 Op.getOperand(0), Op.getOperand(1)); 3764 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract, 3765 DAG.getValueType(VT)); 3766 return DAG.getNode(ISD::TRUNCATE, VT, Assert); 3767 } else if (MVT::getSizeInBits(VT) == 32) { 3768 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3769 if (Idx == 0) 3770 return Op; 3771 // SHUFPS the element to the lowest double word, then movss. 3772 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3773 SmallVector<SDOperand, 8> IdxVec; 3774 IdxVec. 3775 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT))); 3776 IdxVec. 3777 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); 3778 IdxVec. 3779 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); 3780 IdxVec. 3781 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); 3782 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3783 &IdxVec[0], IdxVec.size()); 3784 SDOperand Vec = Op.getOperand(0); 3785 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 3786 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 3787 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 3788 DAG.getIntPtrConstant(0)); 3789 } else if (MVT::getSizeInBits(VT) == 64) { 3790 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 3791 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 3792 // to match extract_elt for f64. 3793 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 3794 if (Idx == 0) 3795 return Op; 3796 3797 // UNPCKHPD the element to the lowest double word, then movsd. 3798 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 3799 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 3800 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4); 3801 SmallVector<SDOperand, 8> IdxVec; 3802 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT))); 3803 IdxVec. 3804 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT))); 3805 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3806 &IdxVec[0], IdxVec.size()); 3807 SDOperand Vec = Op.getOperand(0); 3808 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(), 3809 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask); 3810 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec, 3811 DAG.getIntPtrConstant(0)); 3812 } 3813 3814 return SDOperand(); 3815} 3816 3817SDOperand 3818X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){ 3819 MVT::ValueType VT = Op.getValueType(); 3820 MVT::ValueType EVT = MVT::getVectorElementType(VT); 3821 3822 SDOperand N0 = Op.getOperand(0); 3823 SDOperand N1 = Op.getOperand(1); 3824 SDOperand N2 = Op.getOperand(2); 3825 3826 if ((MVT::getSizeInBits(EVT) == 8) || (MVT::getSizeInBits(EVT) == 16)) { 3827 unsigned Opc = (MVT::getSizeInBits(EVT) == 8) ? X86ISD::PINSRB 3828 : X86ISD::PINSRW; 3829 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 3830 // argument. 3831 if (N1.getValueType() != MVT::i32) 3832 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 3833 if (N2.getValueType() != MVT::i32) 3834 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); 3835 return DAG.getNode(Opc, VT, N0, N1, N2); 3836 } else if (EVT == MVT::f32) { 3837 // Bits [7:6] of the constant are the source select. This will always be 3838 // zero here. The DAG Combiner may combine an extract_elt index into these 3839 // bits. For example (insert (extract, 3), 2) could be matched by putting 3840 // the '3' into bits [7:6] of X86ISD::INSERTPS. 3841 // Bits [5:4] of the constant are the destination select. This is the 3842 // value of the incoming immediate. 3843 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 3844 // combine either bitwise AND or insert of float 0.0 to set these bits. 3845 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4); 3846 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2); 3847 } 3848 return SDOperand(); 3849} 3850 3851SDOperand 3852X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { 3853 MVT::ValueType VT = Op.getValueType(); 3854 MVT::ValueType EVT = MVT::getVectorElementType(VT); 3855 3856 if (Subtarget->hasSSE41()) 3857 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 3858 3859 if (EVT == MVT::i8) 3860 return SDOperand(); 3861 3862 SDOperand N0 = Op.getOperand(0); 3863 SDOperand N1 = Op.getOperand(1); 3864 SDOperand N2 = Op.getOperand(2); 3865 3866 if (MVT::getSizeInBits(EVT) == 16) { 3867 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 3868 // as its second argument. 3869 if (N1.getValueType() != MVT::i32) 3870 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1); 3871 if (N2.getValueType() != MVT::i32) 3872 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue()); 3873 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2); 3874 } 3875 return SDOperand(); 3876} 3877 3878SDOperand 3879X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 3880 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0)); 3881 MVT::ValueType VT = MVT::v2i32; 3882 switch (Op.getValueType()) { 3883 default: break; 3884 case MVT::v16i8: 3885 case MVT::v8i16: 3886 VT = MVT::v4i32; 3887 break; 3888 } 3889 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), 3890 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt)); 3891} 3892 3893// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 3894// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 3895// one of the above mentioned nodes. It has to be wrapped because otherwise 3896// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 3897// be used to form addressing mode. These wrapped nodes will be selected 3898// into MOV32ri. 3899SDOperand 3900X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 3901 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 3902 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(), 3903 getPointerTy(), 3904 CP->getAlignment()); 3905 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 3906 // With PIC, the address is actually $g + Offset. 3907 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 3908 !Subtarget->isPICStyleRIPRel()) { 3909 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3910 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3911 Result); 3912 } 3913 3914 return Result; 3915} 3916 3917SDOperand 3918X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 3919 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 3920 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy()); 3921 // If it's a debug information descriptor, don't mess with it. 3922 if (DAG.isVerifiedDebugInfoDesc(Op)) 3923 return Result; 3924 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 3925 // With PIC, the address is actually $g + Offset. 3926 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 3927 !Subtarget->isPICStyleRIPRel()) { 3928 Result = DAG.getNode(ISD::ADD, getPointerTy(), 3929 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 3930 Result); 3931 } 3932 3933 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to 3934 // load the value at address GV, not the value of GV itself. This means that 3935 // the GlobalAddress must be in the base or index register of the address, not 3936 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call 3937 // The same applies for external symbols during PIC codegen 3938 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false)) 3939 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, 3940 PseudoSourceValue::getGOT(), 0); 3941 3942 return Result; 3943} 3944 3945// Lower ISD::GlobalTLSAddress using the "general dynamic" model 3946static SDOperand 3947LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 3948 const MVT::ValueType PtrVT) { 3949 SDOperand InFlag; 3950 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX, 3951 DAG.getNode(X86ISD::GlobalBaseReg, 3952 PtrVT), InFlag); 3953 InFlag = Chain.getValue(1); 3954 3955 // emit leal symbol@TLSGD(,%ebx,1), %eax 3956 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag); 3957 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 3958 GA->getValueType(0), 3959 GA->getOffset()); 3960 SDOperand Ops[] = { Chain, TGA, InFlag }; 3961 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3); 3962 InFlag = Result.getValue(2); 3963 Chain = Result.getValue(1); 3964 3965 // call ___tls_get_addr. This function receives its argument in 3966 // the register EAX. 3967 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag); 3968 InFlag = Chain.getValue(1); 3969 3970 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 3971 SDOperand Ops1[] = { Chain, 3972 DAG.getTargetExternalSymbol("___tls_get_addr", 3973 PtrVT), 3974 DAG.getRegister(X86::EAX, PtrVT), 3975 DAG.getRegister(X86::EBX, PtrVT), 3976 InFlag }; 3977 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5); 3978 InFlag = Chain.getValue(1); 3979 3980 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag); 3981} 3982 3983// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 3984// "local exec" model. 3985static SDOperand 3986LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 3987 const MVT::ValueType PtrVT) { 3988 // Get the Thread Pointer 3989 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT); 3990 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 3991 // exec) 3992 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 3993 GA->getValueType(0), 3994 GA->getOffset()); 3995 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA); 3996 3997 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model 3998 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, 3999 PseudoSourceValue::getGOT(), 0); 4000 4001 // The address of the thread local variable is the add of the thread 4002 // pointer with the offset of the variable. 4003 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 4004} 4005 4006SDOperand 4007X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 4008 // TODO: implement the "local dynamic" model 4009 // TODO: implement the "initial exec"model for pic executables 4010 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() && 4011 "TLS not implemented for non-ELF and 64-bit targets"); 4012 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4013 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 4014 // otherwise use the "Local Exec"TLS Model 4015 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 4016 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy()); 4017 else 4018 return LowerToTLSExecModel(GA, DAG, getPointerTy()); 4019} 4020 4021SDOperand 4022X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) { 4023 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4024 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 4025 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4026 // With PIC, the address is actually $g + Offset. 4027 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4028 !Subtarget->isPICStyleRIPRel()) { 4029 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4030 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4031 Result); 4032 } 4033 4034 return Result; 4035} 4036 4037SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 4038 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4039 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 4040 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result); 4041 // With PIC, the address is actually $g + Offset. 4042 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4043 !Subtarget->isPICStyleRIPRel()) { 4044 Result = DAG.getNode(ISD::ADD, getPointerTy(), 4045 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), 4046 Result); 4047 } 4048 4049 return Result; 4050} 4051 4052/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4053/// take a 2 x i32 value to shift plus a shift amount. 4054SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { 4055 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4056 MVT::ValueType VT = Op.getValueType(); 4057 unsigned VTBits = MVT::getSizeInBits(VT); 4058 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4059 SDOperand ShOpLo = Op.getOperand(0); 4060 SDOperand ShOpHi = Op.getOperand(1); 4061 SDOperand ShAmt = Op.getOperand(2); 4062 SDOperand Tmp1 = isSRA ? 4063 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) : 4064 DAG.getConstant(0, VT); 4065 4066 SDOperand Tmp2, Tmp3; 4067 if (Op.getOpcode() == ISD::SHL_PARTS) { 4068 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt); 4069 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt); 4070 } else { 4071 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt); 4072 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); 4073 } 4074 4075 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); 4076 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, 4077 DAG.getConstant(VTBits, MVT::i8)); 4078 SDOperand Cond = DAG.getNode(X86ISD::CMP, VT, 4079 AndNode, DAG.getConstant(0, MVT::i8)); 4080 4081 SDOperand Hi, Lo; 4082 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4083 VTs = DAG.getNodeValueTypes(VT, MVT::Flag); 4084 SmallVector<SDOperand, 4> Ops; 4085 if (Op.getOpcode() == ISD::SHL_PARTS) { 4086 Ops.push_back(Tmp2); 4087 Ops.push_back(Tmp3); 4088 Ops.push_back(CC); 4089 Ops.push_back(Cond); 4090 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); 4091 4092 Ops.clear(); 4093 Ops.push_back(Tmp3); 4094 Ops.push_back(Tmp1); 4095 Ops.push_back(CC); 4096 Ops.push_back(Cond); 4097 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); 4098 } else { 4099 Ops.push_back(Tmp2); 4100 Ops.push_back(Tmp3); 4101 Ops.push_back(CC); 4102 Ops.push_back(Cond); 4103 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); 4104 4105 Ops.clear(); 4106 Ops.push_back(Tmp3); 4107 Ops.push_back(Tmp1); 4108 Ops.push_back(CC); 4109 Ops.push_back(Cond); 4110 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); 4111 } 4112 4113 VTs = DAG.getNodeValueTypes(VT, VT); 4114 Ops.clear(); 4115 Ops.push_back(Lo); 4116 Ops.push_back(Hi); 4117 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size()); 4118} 4119 4120SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 4121 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 4122 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 && 4123 "Unknown SINT_TO_FP to lower!"); 4124 4125 // These are really Legal; caller falls through into that case. 4126 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4127 return SDOperand(); 4128 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 && 4129 Subtarget->is64Bit()) 4130 return SDOperand(); 4131 4132 unsigned Size = MVT::getSizeInBits(SrcVT)/8; 4133 MachineFunction &MF = DAG.getMachineFunction(); 4134 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4135 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4136 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0), 4137 StackSlot, 4138 PseudoSourceValue::getFixedStack(), 4139 SSFI); 4140 4141 // Build the FILD 4142 SDVTList Tys; 4143 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4144 if (useSSE) 4145 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4146 else 4147 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4148 SmallVector<SDOperand, 8> Ops; 4149 Ops.push_back(Chain); 4150 Ops.push_back(StackSlot); 4151 Ops.push_back(DAG.getValueType(SrcVT)); 4152 SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, 4153 Tys, &Ops[0], Ops.size()); 4154 4155 if (useSSE) { 4156 Chain = Result.getValue(1); 4157 SDOperand InFlag = Result.getValue(2); 4158 4159 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4160 // shouldn't be necessary except that RFP cannot be live across 4161 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4162 MachineFunction &MF = DAG.getMachineFunction(); 4163 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4164 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4165 Tys = DAG.getVTList(MVT::Other); 4166 SmallVector<SDOperand, 8> Ops; 4167 Ops.push_back(Chain); 4168 Ops.push_back(Result); 4169 Ops.push_back(StackSlot); 4170 Ops.push_back(DAG.getValueType(Op.getValueType())); 4171 Ops.push_back(InFlag); 4172 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size()); 4173 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, 4174 PseudoSourceValue::getFixedStack(), SSFI); 4175 } 4176 4177 return Result; 4178} 4179 4180std::pair<SDOperand,SDOperand> X86TargetLowering:: 4181FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) { 4182 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 && 4183 "Unknown FP_TO_SINT to lower!"); 4184 4185 // These are really Legal. 4186 if (Op.getValueType() == MVT::i32 && 4187 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 4188 return std::make_pair(SDOperand(), SDOperand()); 4189 if (Subtarget->is64Bit() && 4190 Op.getValueType() == MVT::i64 && 4191 Op.getOperand(0).getValueType() != MVT::f80) 4192 return std::make_pair(SDOperand(), SDOperand()); 4193 4194 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 4195 // stack slot. 4196 MachineFunction &MF = DAG.getMachineFunction(); 4197 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8; 4198 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4199 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4200 unsigned Opc; 4201 switch (Op.getValueType()) { 4202 default: assert(0 && "Invalid FP_TO_SINT to lower!"); 4203 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 4204 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 4205 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 4206 } 4207 4208 SDOperand Chain = DAG.getEntryNode(); 4209 SDOperand Value = Op.getOperand(0); 4210 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 4211 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 4212 Chain = DAG.getStore(Chain, Value, StackSlot, 4213 PseudoSourceValue::getFixedStack(), SSFI); 4214 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 4215 SDOperand Ops[] = { 4216 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 4217 }; 4218 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3); 4219 Chain = Value.getValue(1); 4220 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 4221 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4222 } 4223 4224 // Build the FP_TO_INT*_IN_MEM 4225 SDOperand Ops[] = { Chain, Value, StackSlot }; 4226 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3); 4227 4228 return std::make_pair(FIST, StackSlot); 4229} 4230 4231SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 4232 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG); 4233 SDOperand FIST = Vals.first, StackSlot = Vals.second; 4234 if (FIST.Val == 0) return SDOperand(); 4235 4236 // Load the result. 4237 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0); 4238} 4239 4240SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { 4241 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG); 4242 SDOperand FIST = Vals.first, StackSlot = Vals.second; 4243 if (FIST.Val == 0) return 0; 4244 4245 // Return an i64 load from the stack slot. 4246 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0); 4247 4248 // Use a MERGE_VALUES node to drop the chain result value. 4249 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val; 4250} 4251 4252SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { 4253 MVT::ValueType VT = Op.getValueType(); 4254 MVT::ValueType EltVT = VT; 4255 if (MVT::isVector(VT)) 4256 EltVT = MVT::getVectorElementType(VT); 4257 const Type *OpNTy = MVT::getTypeForValueType(EltVT); 4258 std::vector<Constant*> CV; 4259 if (EltVT == MVT::f64) { 4260 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63)))); 4261 CV.push_back(C); 4262 CV.push_back(C); 4263 } else { 4264 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31)))); 4265 CV.push_back(C); 4266 CV.push_back(C); 4267 CV.push_back(C); 4268 CV.push_back(C); 4269 } 4270 Constant *C = ConstantVector::get(CV); 4271 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4272 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4273 PseudoSourceValue::getConstantPool(), 0, 4274 false, 16); 4275 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask); 4276} 4277 4278SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) { 4279 MVT::ValueType VT = Op.getValueType(); 4280 MVT::ValueType EltVT = VT; 4281 unsigned EltNum = 1; 4282 if (MVT::isVector(VT)) { 4283 EltVT = MVT::getVectorElementType(VT); 4284 EltNum = MVT::getVectorNumElements(VT); 4285 } 4286 const Type *OpNTy = MVT::getTypeForValueType(EltVT); 4287 std::vector<Constant*> CV; 4288 if (EltVT == MVT::f64) { 4289 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63))); 4290 CV.push_back(C); 4291 CV.push_back(C); 4292 } else { 4293 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31))); 4294 CV.push_back(C); 4295 CV.push_back(C); 4296 CV.push_back(C); 4297 CV.push_back(C); 4298 } 4299 Constant *C = ConstantVector::get(CV); 4300 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4301 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4302 PseudoSourceValue::getConstantPool(), 0, 4303 false, 16); 4304 if (MVT::isVector(VT)) { 4305 return DAG.getNode(ISD::BIT_CONVERT, VT, 4306 DAG.getNode(ISD::XOR, MVT::v2i64, 4307 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)), 4308 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask))); 4309 } else { 4310 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask); 4311 } 4312} 4313 4314SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 4315 SDOperand Op0 = Op.getOperand(0); 4316 SDOperand Op1 = Op.getOperand(1); 4317 MVT::ValueType VT = Op.getValueType(); 4318 MVT::ValueType SrcVT = Op1.getValueType(); 4319 const Type *SrcTy = MVT::getTypeForValueType(SrcVT); 4320 4321 // If second operand is smaller, extend it first. 4322 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) { 4323 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1); 4324 SrcVT = VT; 4325 SrcTy = MVT::getTypeForValueType(SrcVT); 4326 } 4327 // And if it is bigger, shrink it first. 4328 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { 4329 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1)); 4330 SrcVT = VT; 4331 SrcTy = MVT::getTypeForValueType(SrcVT); 4332 } 4333 4334 // At this point the operands and the result should have the same 4335 // type, and that won't be f80 since that is not custom lowered. 4336 4337 // First get the sign bit of second operand. 4338 std::vector<Constant*> CV; 4339 if (SrcVT == MVT::f64) { 4340 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63)))); 4341 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0)))); 4342 } else { 4343 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31)))); 4344 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0)))); 4345 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0)))); 4346 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0)))); 4347 } 4348 Constant *C = ConstantVector::get(CV); 4349 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4350 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, 4351 PseudoSourceValue::getConstantPool(), 0, 4352 false, 16); 4353 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1); 4354 4355 // Shift sign bit right or left if the two operands have different types. 4356 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) { 4357 // Op0 is MVT::f32, Op1 is MVT::f64. 4358 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit); 4359 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit, 4360 DAG.getConstant(32, MVT::i32)); 4361 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit); 4362 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit, 4363 DAG.getIntPtrConstant(0)); 4364 } 4365 4366 // Clear first operand sign bit. 4367 CV.clear(); 4368 if (VT == MVT::f64) { 4369 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63))))); 4370 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0)))); 4371 } else { 4372 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31))))); 4373 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0)))); 4374 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0)))); 4375 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0)))); 4376 } 4377 C = ConstantVector::get(CV); 4378 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4); 4379 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4380 PseudoSourceValue::getConstantPool(), 0, 4381 false, 16); 4382 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2); 4383 4384 // Or the value with the sign bit. 4385 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit); 4386} 4387 4388SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 4389 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 4390 SDOperand Cond; 4391 SDOperand Op0 = Op.getOperand(0); 4392 SDOperand Op1 = Op.getOperand(1); 4393 SDOperand CC = Op.getOperand(2); 4394 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 4395 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType()); 4396 unsigned X86CC; 4397 4398 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC, 4399 Op0, Op1, DAG)) { 4400 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); 4401 return DAG.getNode(X86ISD::SETCC, MVT::i8, 4402 DAG.getConstant(X86CC, MVT::i8), Cond); 4403 } 4404 4405 assert(isFP && "Illegal integer SetCC!"); 4406 4407 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1); 4408 switch (SetCCOpcode) { 4409 default: assert(false && "Illegal floating point SetCC!"); 4410 case ISD::SETOEQ: { // !PF & ZF 4411 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4412 DAG.getConstant(X86::COND_NP, MVT::i8), Cond); 4413 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4414 DAG.getConstant(X86::COND_E, MVT::i8), Cond); 4415 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2); 4416 } 4417 case ISD::SETUNE: { // PF | !ZF 4418 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4419 DAG.getConstant(X86::COND_P, MVT::i8), Cond); 4420 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8, 4421 DAG.getConstant(X86::COND_NE, MVT::i8), Cond); 4422 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2); 4423 } 4424 } 4425} 4426 4427 4428SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { 4429 bool addTest = true; 4430 SDOperand Cond = Op.getOperand(0); 4431 SDOperand CC; 4432 4433 if (Cond.getOpcode() == ISD::SETCC) 4434 Cond = LowerSETCC(Cond, DAG); 4435 4436 // If condition flag is set by a X86ISD::CMP, then use it as the condition 4437 // setting operand in place of the X86ISD::SETCC. 4438 if (Cond.getOpcode() == X86ISD::SETCC) { 4439 CC = Cond.getOperand(0); 4440 4441 SDOperand Cmp = Cond.getOperand(1); 4442 unsigned Opc = Cmp.getOpcode(); 4443 MVT::ValueType VT = Op.getValueType(); 4444 4445 bool IllegalFPCMov = false; 4446 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) && 4447 !isScalarFPTypeInSSEReg(VT)) // FPStack? 4448 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended()); 4449 4450 if ((Opc == X86ISD::CMP || 4451 Opc == X86ISD::COMI || 4452 Opc == X86ISD::UCOMI) && !IllegalFPCMov) { 4453 Cond = Cmp; 4454 addTest = false; 4455 } 4456 } 4457 4458 if (addTest) { 4459 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4460 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 4461 } 4462 4463 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(), 4464 MVT::Flag); 4465 SmallVector<SDOperand, 4> Ops; 4466 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 4467 // condition is true. 4468 Ops.push_back(Op.getOperand(2)); 4469 Ops.push_back(Op.getOperand(1)); 4470 Ops.push_back(CC); 4471 Ops.push_back(Cond); 4472 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size()); 4473} 4474 4475SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { 4476 bool addTest = true; 4477 SDOperand Chain = Op.getOperand(0); 4478 SDOperand Cond = Op.getOperand(1); 4479 SDOperand Dest = Op.getOperand(2); 4480 SDOperand CC; 4481 4482 if (Cond.getOpcode() == ISD::SETCC) 4483 Cond = LowerSETCC(Cond, DAG); 4484 4485 // If condition flag is set by a X86ISD::CMP, then use it as the condition 4486 // setting operand in place of the X86ISD::SETCC. 4487 if (Cond.getOpcode() == X86ISD::SETCC) { 4488 CC = Cond.getOperand(0); 4489 4490 SDOperand Cmp = Cond.getOperand(1); 4491 unsigned Opc = Cmp.getOpcode(); 4492 if (Opc == X86ISD::CMP || 4493 Opc == X86ISD::COMI || 4494 Opc == X86ISD::UCOMI) { 4495 Cond = Cmp; 4496 addTest = false; 4497 } 4498 } 4499 4500 if (addTest) { 4501 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4502 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8)); 4503 } 4504 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), 4505 Chain, Op.getOperand(2), CC, Cond); 4506} 4507 4508 4509// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 4510// Calls to _alloca is needed to probe the stack when allocating more than 4k 4511// bytes in one go. Touching the stack at 4K increments is necessary to ensure 4512// that the guard pages used by the OS virtual memory manager are allocated in 4513// correct sequence. 4514SDOperand 4515X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, 4516 SelectionDAG &DAG) { 4517 assert(Subtarget->isTargetCygMing() && 4518 "This should be used only on Cygwin/Mingw targets"); 4519 4520 // Get the inputs. 4521 SDOperand Chain = Op.getOperand(0); 4522 SDOperand Size = Op.getOperand(1); 4523 // FIXME: Ensure alignment here 4524 4525 SDOperand Flag; 4526 4527 MVT::ValueType IntPtr = getPointerTy(); 4528 MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 4529 4530 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag); 4531 Flag = Chain.getValue(1); 4532 4533 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4534 SDOperand Ops[] = { Chain, 4535 DAG.getTargetExternalSymbol("_alloca", IntPtr), 4536 DAG.getRegister(X86::EAX, IntPtr), 4537 Flag }; 4538 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4); 4539 Flag = Chain.getValue(1); 4540 4541 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); 4542 4543 std::vector<MVT::ValueType> Tys; 4544 Tys.push_back(SPTy); 4545 Tys.push_back(MVT::Other); 4546 SDOperand Ops1[2] = { Chain.getValue(0), Chain }; 4547 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2); 4548} 4549 4550SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) { 4551 SDOperand InFlag(0, 0); 4552 SDOperand Chain = Op.getOperand(0); 4553 unsigned Align = 4554 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 4555 if (Align == 0) Align = 1; 4556 4557 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)); 4558 // If not DWORD aligned or size is more than the threshold, call memset. 4559 // The libc version is likely to be faster for these cases. It can use the 4560 // address value and run time information about the CPU. 4561 if ((Align & 3) != 0 || 4562 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) { 4563 MVT::ValueType IntPtr = getPointerTy(); 4564 const Type *IntPtrTy = getTargetData()->getIntPtrType(); 4565 TargetLowering::ArgListTy Args; 4566 TargetLowering::ArgListEntry Entry; 4567 Entry.Node = Op.getOperand(1); 4568 Entry.Ty = IntPtrTy; 4569 Args.push_back(Entry); 4570 // Extend the unsigned i8 argument to be an int value for the call. 4571 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2)); 4572 Entry.Ty = IntPtrTy; 4573 Args.push_back(Entry); 4574 Entry.Node = Op.getOperand(3); 4575 Args.push_back(Entry); 4576 std::pair<SDOperand,SDOperand> CallResult = 4577 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C, 4578 false, DAG.getExternalSymbol("memset", IntPtr), Args, DAG); 4579 return CallResult.second; 4580 } 4581 4582 MVT::ValueType AVT; 4583 SDOperand Count; 4584 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2)); 4585 unsigned BytesLeft = 0; 4586 bool TwoRepStos = false; 4587 if (ValC) { 4588 unsigned ValReg; 4589 uint64_t Val = ValC->getValue() & 255; 4590 4591 // If the value is a constant, then we can potentially use larger sets. 4592 switch (Align & 3) { 4593 case 2: // WORD aligned 4594 AVT = MVT::i16; 4595 ValReg = X86::AX; 4596 Val = (Val << 8) | Val; 4597 break; 4598 case 0: // DWORD aligned 4599 AVT = MVT::i32; 4600 ValReg = X86::EAX; 4601 Val = (Val << 8) | Val; 4602 Val = (Val << 16) | Val; 4603 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned 4604 AVT = MVT::i64; 4605 ValReg = X86::RAX; 4606 Val = (Val << 32) | Val; 4607 } 4608 break; 4609 default: // Byte aligned 4610 AVT = MVT::i8; 4611 ValReg = X86::AL; 4612 Count = Op.getOperand(3); 4613 break; 4614 } 4615 4616 if (AVT > MVT::i8) { 4617 if (I) { 4618 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 4619 Count = DAG.getIntPtrConstant(I->getValue() / UBytes); 4620 BytesLeft = I->getValue() % UBytes; 4621 } else { 4622 assert(AVT >= MVT::i32 && 4623 "Do not use rep;stos if not at least DWORD aligned"); 4624 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(), 4625 Op.getOperand(3), DAG.getConstant(2, MVT::i8)); 4626 TwoRepStos = true; 4627 } 4628 } 4629 4630 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT), 4631 InFlag); 4632 InFlag = Chain.getValue(1); 4633 } else { 4634 AVT = MVT::i8; 4635 Count = Op.getOperand(3); 4636 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag); 4637 InFlag = Chain.getValue(1); 4638 } 4639 4640 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 4641 Count, InFlag); 4642 InFlag = Chain.getValue(1); 4643 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 4644 Op.getOperand(1), InFlag); 4645 InFlag = Chain.getValue(1); 4646 4647 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4648 SmallVector<SDOperand, 8> Ops; 4649 Ops.push_back(Chain); 4650 Ops.push_back(DAG.getValueType(AVT)); 4651 Ops.push_back(InFlag); 4652 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 4653 4654 if (TwoRepStos) { 4655 InFlag = Chain.getValue(1); 4656 Count = Op.getOperand(3); 4657 MVT::ValueType CVT = Count.getValueType(); 4658 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count, 4659 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 4660 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX, 4661 Left, InFlag); 4662 InFlag = Chain.getValue(1); 4663 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4664 Ops.clear(); 4665 Ops.push_back(Chain); 4666 Ops.push_back(DAG.getValueType(MVT::i8)); 4667 Ops.push_back(InFlag); 4668 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size()); 4669 } else if (BytesLeft) { 4670 // Issue stores for the last 1 - 7 bytes. 4671 SDOperand Value; 4672 unsigned Val = ValC->getValue() & 255; 4673 unsigned Offset = I->getValue() - BytesLeft; 4674 SDOperand DstAddr = Op.getOperand(1); 4675 MVT::ValueType AddrVT = DstAddr.getValueType(); 4676 if (BytesLeft >= 4) { 4677 Val = (Val << 8) | Val; 4678 Val = (Val << 16) | Val; 4679 Value = DAG.getConstant(Val, MVT::i32); 4680 Chain = DAG.getStore(Chain, Value, 4681 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4682 DAG.getConstant(Offset, AddrVT)), 4683 NULL, 0); 4684 BytesLeft -= 4; 4685 Offset += 4; 4686 } 4687 if (BytesLeft >= 2) { 4688 Value = DAG.getConstant((Val << 8) | Val, MVT::i16); 4689 Chain = DAG.getStore(Chain, Value, 4690 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4691 DAG.getConstant(Offset, AddrVT)), 4692 NULL, 0); 4693 BytesLeft -= 2; 4694 Offset += 2; 4695 } 4696 if (BytesLeft == 1) { 4697 Value = DAG.getConstant(Val, MVT::i8); 4698 Chain = DAG.getStore(Chain, Value, 4699 DAG.getNode(ISD::ADD, AddrVT, DstAddr, 4700 DAG.getConstant(Offset, AddrVT)), 4701 NULL, 0); 4702 } 4703 } 4704 4705 return Chain; 4706} 4707 4708SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain, 4709 SDOperand Dest, 4710 SDOperand Source, 4711 unsigned Size, 4712 unsigned Align, 4713 SelectionDAG &DAG) { 4714 MVT::ValueType AVT; 4715 unsigned BytesLeft = 0; 4716 switch (Align & 3) { 4717 case 2: // WORD aligned 4718 AVT = MVT::i16; 4719 break; 4720 case 0: // DWORD aligned 4721 AVT = MVT::i32; 4722 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned 4723 AVT = MVT::i64; 4724 break; 4725 default: // Byte aligned 4726 AVT = MVT::i8; 4727 break; 4728 } 4729 4730 unsigned UBytes = MVT::getSizeInBits(AVT) / 8; 4731 SDOperand Count = DAG.getIntPtrConstant(Size / UBytes); 4732 BytesLeft = Size % UBytes; 4733 4734 SDOperand InFlag(0, 0); 4735 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX, 4736 Count, InFlag); 4737 InFlag = Chain.getValue(1); 4738 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI, 4739 Dest, InFlag); 4740 InFlag = Chain.getValue(1); 4741 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI, 4742 Source, InFlag); 4743 InFlag = Chain.getValue(1); 4744 4745 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4746 SmallVector<SDOperand, 8> Ops; 4747 Ops.push_back(Chain); 4748 Ops.push_back(DAG.getValueType(AVT)); 4749 Ops.push_back(InFlag); 4750 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size()); 4751 4752 if (BytesLeft) { 4753 // Issue loads and stores for the last 1 - 7 bytes. 4754 unsigned Offset = Size - BytesLeft; 4755 SDOperand DstAddr = Dest; 4756 MVT::ValueType DstVT = DstAddr.getValueType(); 4757 SDOperand SrcAddr = Source; 4758 MVT::ValueType SrcVT = SrcAddr.getValueType(); 4759 SDOperand Value; 4760 if (BytesLeft >= 4) { 4761 Value = DAG.getLoad(MVT::i32, Chain, 4762 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4763 DAG.getConstant(Offset, SrcVT)), 4764 NULL, 0); 4765 Chain = Value.getValue(1); 4766 Chain = DAG.getStore(Chain, Value, 4767 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4768 DAG.getConstant(Offset, DstVT)), 4769 NULL, 0); 4770 BytesLeft -= 4; 4771 Offset += 4; 4772 } 4773 if (BytesLeft >= 2) { 4774 Value = DAG.getLoad(MVT::i16, Chain, 4775 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4776 DAG.getConstant(Offset, SrcVT)), 4777 NULL, 0); 4778 Chain = Value.getValue(1); 4779 Chain = DAG.getStore(Chain, Value, 4780 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4781 DAG.getConstant(Offset, DstVT)), 4782 NULL, 0); 4783 BytesLeft -= 2; 4784 Offset += 2; 4785 } 4786 4787 if (BytesLeft == 1) { 4788 Value = DAG.getLoad(MVT::i8, Chain, 4789 DAG.getNode(ISD::ADD, SrcVT, SrcAddr, 4790 DAG.getConstant(Offset, SrcVT)), 4791 NULL, 0); 4792 Chain = Value.getValue(1); 4793 Chain = DAG.getStore(Chain, Value, 4794 DAG.getNode(ISD::ADD, DstVT, DstAddr, 4795 DAG.getConstant(Offset, DstVT)), 4796 NULL, 0); 4797 } 4798 } 4799 4800 return Chain; 4801} 4802 4803/// Expand the result of: i64,outchain = READCYCLECOUNTER inchain 4804SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ 4805 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 4806 SDOperand TheChain = N->getOperand(0); 4807 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1); 4808 if (Subtarget->is64Bit()) { 4809 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1)); 4810 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, 4811 MVT::i64, rax.getValue(2)); 4812 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx, 4813 DAG.getConstant(32, MVT::i8)); 4814 SDOperand Ops[] = { 4815 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1) 4816 }; 4817 4818 Tys = DAG.getVTList(MVT::i64, MVT::Other); 4819 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val; 4820 } 4821 4822 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); 4823 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, 4824 MVT::i32, eax.getValue(2)); 4825 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 4826 SDOperand Ops[] = { eax, edx }; 4827 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2); 4828 4829 // Use a MERGE_VALUES to return the value and chain. 4830 Ops[1] = edx.getValue(1); 4831 Tys = DAG.getVTList(MVT::i64, MVT::Other); 4832 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val; 4833} 4834 4835SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { 4836 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 4837 4838 if (!Subtarget->is64Bit()) { 4839 // vastart just stores the address of the VarArgsFrameIndex slot into the 4840 // memory location argument. 4841 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 4842 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0); 4843 } 4844 4845 // __va_list_tag: 4846 // gp_offset (0 - 6 * 8) 4847 // fp_offset (48 - 48 + 8 * 16) 4848 // overflow_arg_area (point to parameters coming in memory). 4849 // reg_save_area 4850 SmallVector<SDOperand, 8> MemOps; 4851 SDOperand FIN = Op.getOperand(1); 4852 // Store gp_offset 4853 SDOperand Store = DAG.getStore(Op.getOperand(0), 4854 DAG.getConstant(VarArgsGPOffset, MVT::i32), 4855 FIN, SV, 0); 4856 MemOps.push_back(Store); 4857 4858 // Store fp_offset 4859 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 4860 Store = DAG.getStore(Op.getOperand(0), 4861 DAG.getConstant(VarArgsFPOffset, MVT::i32), 4862 FIN, SV, 0); 4863 MemOps.push_back(Store); 4864 4865 // Store ptr to overflow_arg_area 4866 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); 4867 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 4868 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0); 4869 MemOps.push_back(Store); 4870 4871 // Store ptr to reg_save_area. 4872 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8)); 4873 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 4874 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0); 4875 MemOps.push_back(Store); 4876 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size()); 4877} 4878 4879SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) { 4880 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 4881 SDOperand Chain = Op.getOperand(0); 4882 SDOperand DstPtr = Op.getOperand(1); 4883 SDOperand SrcPtr = Op.getOperand(2); 4884 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 4885 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 4886 4887 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr, SrcSV, 0); 4888 Chain = SrcPtr.getValue(1); 4889 for (unsigned i = 0; i < 3; ++i) { 4890 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr, SrcSV, 0); 4891 Chain = Val.getValue(1); 4892 Chain = DAG.getStore(Chain, Val, DstPtr, DstSV, 0); 4893 if (i == 2) 4894 break; 4895 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr, 4896 DAG.getIntPtrConstant(8)); 4897 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr, 4898 DAG.getIntPtrConstant(8)); 4899 } 4900 return Chain; 4901} 4902 4903SDOperand 4904X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 4905 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 4906 switch (IntNo) { 4907 default: return SDOperand(); // Don't custom lower most intrinsics. 4908 // Comparison intrinsics. 4909 case Intrinsic::x86_sse_comieq_ss: 4910 case Intrinsic::x86_sse_comilt_ss: 4911 case Intrinsic::x86_sse_comile_ss: 4912 case Intrinsic::x86_sse_comigt_ss: 4913 case Intrinsic::x86_sse_comige_ss: 4914 case Intrinsic::x86_sse_comineq_ss: 4915 case Intrinsic::x86_sse_ucomieq_ss: 4916 case Intrinsic::x86_sse_ucomilt_ss: 4917 case Intrinsic::x86_sse_ucomile_ss: 4918 case Intrinsic::x86_sse_ucomigt_ss: 4919 case Intrinsic::x86_sse_ucomige_ss: 4920 case Intrinsic::x86_sse_ucomineq_ss: 4921 case Intrinsic::x86_sse2_comieq_sd: 4922 case Intrinsic::x86_sse2_comilt_sd: 4923 case Intrinsic::x86_sse2_comile_sd: 4924 case Intrinsic::x86_sse2_comigt_sd: 4925 case Intrinsic::x86_sse2_comige_sd: 4926 case Intrinsic::x86_sse2_comineq_sd: 4927 case Intrinsic::x86_sse2_ucomieq_sd: 4928 case Intrinsic::x86_sse2_ucomilt_sd: 4929 case Intrinsic::x86_sse2_ucomile_sd: 4930 case Intrinsic::x86_sse2_ucomigt_sd: 4931 case Intrinsic::x86_sse2_ucomige_sd: 4932 case Intrinsic::x86_sse2_ucomineq_sd: { 4933 unsigned Opc = 0; 4934 ISD::CondCode CC = ISD::SETCC_INVALID; 4935 switch (IntNo) { 4936 default: break; 4937 case Intrinsic::x86_sse_comieq_ss: 4938 case Intrinsic::x86_sse2_comieq_sd: 4939 Opc = X86ISD::COMI; 4940 CC = ISD::SETEQ; 4941 break; 4942 case Intrinsic::x86_sse_comilt_ss: 4943 case Intrinsic::x86_sse2_comilt_sd: 4944 Opc = X86ISD::COMI; 4945 CC = ISD::SETLT; 4946 break; 4947 case Intrinsic::x86_sse_comile_ss: 4948 case Intrinsic::x86_sse2_comile_sd: 4949 Opc = X86ISD::COMI; 4950 CC = ISD::SETLE; 4951 break; 4952 case Intrinsic::x86_sse_comigt_ss: 4953 case Intrinsic::x86_sse2_comigt_sd: 4954 Opc = X86ISD::COMI; 4955 CC = ISD::SETGT; 4956 break; 4957 case Intrinsic::x86_sse_comige_ss: 4958 case Intrinsic::x86_sse2_comige_sd: 4959 Opc = X86ISD::COMI; 4960 CC = ISD::SETGE; 4961 break; 4962 case Intrinsic::x86_sse_comineq_ss: 4963 case Intrinsic::x86_sse2_comineq_sd: 4964 Opc = X86ISD::COMI; 4965 CC = ISD::SETNE; 4966 break; 4967 case Intrinsic::x86_sse_ucomieq_ss: 4968 case Intrinsic::x86_sse2_ucomieq_sd: 4969 Opc = X86ISD::UCOMI; 4970 CC = ISD::SETEQ; 4971 break; 4972 case Intrinsic::x86_sse_ucomilt_ss: 4973 case Intrinsic::x86_sse2_ucomilt_sd: 4974 Opc = X86ISD::UCOMI; 4975 CC = ISD::SETLT; 4976 break; 4977 case Intrinsic::x86_sse_ucomile_ss: 4978 case Intrinsic::x86_sse2_ucomile_sd: 4979 Opc = X86ISD::UCOMI; 4980 CC = ISD::SETLE; 4981 break; 4982 case Intrinsic::x86_sse_ucomigt_ss: 4983 case Intrinsic::x86_sse2_ucomigt_sd: 4984 Opc = X86ISD::UCOMI; 4985 CC = ISD::SETGT; 4986 break; 4987 case Intrinsic::x86_sse_ucomige_ss: 4988 case Intrinsic::x86_sse2_ucomige_sd: 4989 Opc = X86ISD::UCOMI; 4990 CC = ISD::SETGE; 4991 break; 4992 case Intrinsic::x86_sse_ucomineq_ss: 4993 case Intrinsic::x86_sse2_ucomineq_sd: 4994 Opc = X86ISD::UCOMI; 4995 CC = ISD::SETNE; 4996 break; 4997 } 4998 4999 unsigned X86CC; 5000 SDOperand LHS = Op.getOperand(1); 5001 SDOperand RHS = Op.getOperand(2); 5002 translateX86CC(CC, true, X86CC, LHS, RHS, DAG); 5003 5004 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS); 5005 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8, 5006 DAG.getConstant(X86CC, MVT::i8), Cond); 5007 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC); 5008 } 5009 } 5010} 5011 5012SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 5013 // Depths > 0 not supported yet! 5014 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 5015 return SDOperand(); 5016 5017 // Just load the return address 5018 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 5019 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 5020} 5021 5022SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 5023 // Depths > 0 not supported yet! 5024 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 5025 return SDOperand(); 5026 5027 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG); 5028 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI, 5029 DAG.getIntPtrConstant(4)); 5030} 5031 5032SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, 5033 SelectionDAG &DAG) { 5034 // Is not yet supported on x86-64 5035 if (Subtarget->is64Bit()) 5036 return SDOperand(); 5037 5038 return DAG.getIntPtrConstant(8); 5039} 5040 5041SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG) 5042{ 5043 assert(!Subtarget->is64Bit() && 5044 "Lowering of eh_return builtin is not supported yet on x86-64"); 5045 5046 MachineFunction &MF = DAG.getMachineFunction(); 5047 SDOperand Chain = Op.getOperand(0); 5048 SDOperand Offset = Op.getOperand(1); 5049 SDOperand Handler = Op.getOperand(2); 5050 5051 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF), 5052 getPointerTy()); 5053 5054 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame, 5055 DAG.getIntPtrConstant(-4UL)); 5056 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset); 5057 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0); 5058 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr); 5059 MF.getRegInfo().addLiveOut(X86::ECX); 5060 5061 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other, 5062 Chain, DAG.getRegister(X86::ECX, getPointerTy())); 5063} 5064 5065SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, 5066 SelectionDAG &DAG) { 5067 SDOperand Root = Op.getOperand(0); 5068 SDOperand Trmp = Op.getOperand(1); // trampoline 5069 SDOperand FPtr = Op.getOperand(2); // nested function 5070 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value 5071 5072 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 5073 5074 const X86InstrInfo *TII = 5075 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 5076 5077 if (Subtarget->is64Bit()) { 5078 SDOperand OutChains[6]; 5079 5080 // Large code-model. 5081 5082 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 5083 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 5084 5085 const unsigned char N86R10 = 5086 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10); 5087 const unsigned char N86R11 = 5088 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11); 5089 5090 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 5091 5092 // Load the pointer to the nested function into R11. 5093 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 5094 SDOperand Addr = Trmp; 5095 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5096 TrmpAddr, 0); 5097 5098 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64)); 5099 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2); 5100 5101 // Load the 'nest' parameter value into R10. 5102 // R10 is specified in X86CallingConv.td 5103 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 5104 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64)); 5105 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5106 TrmpAddr, 10); 5107 5108 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64)); 5109 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2); 5110 5111 // Jump to the nested function. 5112 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 5113 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64)); 5114 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr, 5115 TrmpAddr, 20); 5116 5117 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 5118 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64)); 5119 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr, 5120 TrmpAddr, 22); 5121 5122 SDOperand Ops[] = 5123 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; 5124 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2); 5125 } else { 5126 const Function *Func = 5127 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 5128 unsigned CC = Func->getCallingConv(); 5129 unsigned NestReg; 5130 5131 switch (CC) { 5132 default: 5133 assert(0 && "Unsupported calling convention"); 5134 case CallingConv::C: 5135 case CallingConv::X86_StdCall: { 5136 // Pass 'nest' parameter in ECX. 5137 // Must be kept in sync with X86CallingConv.td 5138 NestReg = X86::ECX; 5139 5140 // Check that ECX wasn't needed by an 'inreg' parameter. 5141 const FunctionType *FTy = Func->getFunctionType(); 5142 const PAListPtr &Attrs = Func->getParamAttrs(); 5143 5144 if (!Attrs.isEmpty() && !Func->isVarArg()) { 5145 unsigned InRegCount = 0; 5146 unsigned Idx = 1; 5147 5148 for (FunctionType::param_iterator I = FTy->param_begin(), 5149 E = FTy->param_end(); I != E; ++I, ++Idx) 5150 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg)) 5151 // FIXME: should only count parameters that are lowered to integers. 5152 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32; 5153 5154 if (InRegCount > 2) { 5155 cerr << "Nest register in use - reduce number of inreg parameters!\n"; 5156 abort(); 5157 } 5158 } 5159 break; 5160 } 5161 case CallingConv::X86_FastCall: 5162 // Pass 'nest' parameter in EAX. 5163 // Must be kept in sync with X86CallingConv.td 5164 NestReg = X86::EAX; 5165 break; 5166 } 5167 5168 SDOperand OutChains[4]; 5169 SDOperand Addr, Disp; 5170 5171 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32)); 5172 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr); 5173 5174 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 5175 const unsigned char N86Reg = 5176 ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg); 5177 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 5178 Trmp, TrmpAddr, 0); 5179 5180 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32)); 5181 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1); 5182 5183 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 5184 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32)); 5185 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr, 5186 TrmpAddr, 5, false, 1); 5187 5188 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32)); 5189 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1); 5190 5191 SDOperand Ops[] = 5192 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; 5193 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2); 5194 } 5195} 5196 5197SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { 5198 /* 5199 The rounding mode is in bits 11:10 of FPSR, and has the following 5200 settings: 5201 00 Round to nearest 5202 01 Round to -inf 5203 10 Round to +inf 5204 11 Round to 0 5205 5206 FLT_ROUNDS, on the other hand, expects the following: 5207 -1 Undefined 5208 0 Round to 0 5209 1 Round to nearest 5210 2 Round to +inf 5211 3 Round to -inf 5212 5213 To perform the conversion, we do: 5214 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 5215 */ 5216 5217 MachineFunction &MF = DAG.getMachineFunction(); 5218 const TargetMachine &TM = MF.getTarget(); 5219 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 5220 unsigned StackAlignment = TFI.getStackAlignment(); 5221 MVT::ValueType VT = Op.getValueType(); 5222 5223 // Save FP Control Word to stack slot 5224 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 5225 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5226 5227 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other, 5228 DAG.getEntryNode(), StackSlot); 5229 5230 // Load FP Control Word from stack slot 5231 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0); 5232 5233 // Transform as necessary 5234 SDOperand CWD1 = 5235 DAG.getNode(ISD::SRL, MVT::i16, 5236 DAG.getNode(ISD::AND, MVT::i16, 5237 CWD, DAG.getConstant(0x800, MVT::i16)), 5238 DAG.getConstant(11, MVT::i8)); 5239 SDOperand CWD2 = 5240 DAG.getNode(ISD::SRL, MVT::i16, 5241 DAG.getNode(ISD::AND, MVT::i16, 5242 CWD, DAG.getConstant(0x400, MVT::i16)), 5243 DAG.getConstant(9, MVT::i8)); 5244 5245 SDOperand RetVal = 5246 DAG.getNode(ISD::AND, MVT::i16, 5247 DAG.getNode(ISD::ADD, MVT::i16, 5248 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2), 5249 DAG.getConstant(1, MVT::i16)), 5250 DAG.getConstant(3, MVT::i16)); 5251 5252 5253 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? 5254 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 5255} 5256 5257SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { 5258 MVT::ValueType VT = Op.getValueType(); 5259 MVT::ValueType OpVT = VT; 5260 unsigned NumBits = MVT::getSizeInBits(VT); 5261 5262 Op = Op.getOperand(0); 5263 if (VT == MVT::i8) { 5264 // Zero extend to i32 since there is not an i8 bsr. 5265 OpVT = MVT::i32; 5266 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 5267 } 5268 5269 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 5270 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 5271 Op = DAG.getNode(X86ISD::BSR, VTs, Op); 5272 5273 // If src is zero (i.e. bsr sets ZF), returns NumBits. 5274 SmallVector<SDOperand, 4> Ops; 5275 Ops.push_back(Op); 5276 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 5277 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 5278 Ops.push_back(Op.getValue(1)); 5279 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 5280 5281 // Finally xor with NumBits-1. 5282 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 5283 5284 if (VT == MVT::i8) 5285 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 5286 return Op; 5287} 5288 5289SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) { 5290 MVT::ValueType VT = Op.getValueType(); 5291 MVT::ValueType OpVT = VT; 5292 unsigned NumBits = MVT::getSizeInBits(VT); 5293 5294 Op = Op.getOperand(0); 5295 if (VT == MVT::i8) { 5296 OpVT = MVT::i32; 5297 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op); 5298 } 5299 5300 // Issue a bsf (scan bits forward) which also sets EFLAGS. 5301 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 5302 Op = DAG.getNode(X86ISD::BSF, VTs, Op); 5303 5304 // If src is zero (i.e. bsf sets ZF), returns NumBits. 5305 SmallVector<SDOperand, 4> Ops; 5306 Ops.push_back(Op); 5307 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 5308 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 5309 Ops.push_back(Op.getValue(1)); 5310 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4); 5311 5312 if (VT == MVT::i8) 5313 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op); 5314 return Op; 5315} 5316 5317SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) { 5318 MVT::ValueType T = cast<AtomicSDNode>(Op.Val)->getVT(); 5319 unsigned Reg = 0; 5320 unsigned size = 0; 5321 switch(T) { 5322 case MVT::i8: Reg = X86::AL; size = 1; break; 5323 case MVT::i16: Reg = X86::AX; size = 2; break; 5324 case MVT::i32: Reg = X86::EAX; size = 4; break; 5325 case MVT::i64: 5326 if (Subtarget->is64Bit()) { 5327 Reg = X86::RAX; size = 8; 5328 } else //Should go away when LowerType stuff lands 5329 return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0); 5330 break; 5331 }; 5332 SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg, 5333 Op.getOperand(3), SDOperand()); 5334 SDOperand Ops[] = { cpIn.getValue(0), 5335 Op.getOperand(1), 5336 Op.getOperand(2), 5337 DAG.getTargetConstant(size, MVT::i8), 5338 cpIn.getValue(1) }; 5339 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5340 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5); 5341 SDOperand cpOut = 5342 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1)); 5343 return cpOut; 5344} 5345 5346SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) { 5347 MVT::ValueType T = cast<AtomicSDNode>(Op)->getVT(); 5348 assert (T == MVT::i64 && "Only know how to expand i64 CAS"); 5349 SDOperand cpInL, cpInH; 5350 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), 5351 DAG.getConstant(0, MVT::i32)); 5352 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3), 5353 DAG.getConstant(1, MVT::i32)); 5354 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX, 5355 cpInL, SDOperand()); 5356 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, 5357 cpInH, cpInL.getValue(1)); 5358 SDOperand swapInL, swapInH; 5359 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), 5360 DAG.getConstant(0, MVT::i32)); 5361 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2), 5362 DAG.getConstant(1, MVT::i32)); 5363 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, 5364 swapInL, cpInH.getValue(1)); 5365 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, 5366 swapInH, swapInL.getValue(1)); 5367 SDOperand Ops[] = { swapInH.getValue(0), 5368 Op->getOperand(1), 5369 swapInH.getValue(1)}; 5370 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5371 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3); 5372 SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32, 5373 Result.getValue(1)); 5374 SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32, 5375 cpOutL.getValue(2)); 5376 SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 5377 SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); 5378 Tys = DAG.getVTList(MVT::i64, MVT::Other); 5379 return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val; 5380} 5381 5382/// LowerOperation - Provide custom lowering hooks for some operations. 5383/// 5384SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 5385 switch (Op.getOpcode()) { 5386 default: assert(0 && "Should not custom lower this!"); 5387 case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG); 5388 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5389 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5390 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 5391 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 5392 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5393 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5394 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5395 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5396 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 5397 case ISD::SHL_PARTS: 5398 case ISD::SRA_PARTS: 5399 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 5400 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 5401 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 5402 case ISD::FABS: return LowerFABS(Op, DAG); 5403 case ISD::FNEG: return LowerFNEG(Op, DAG); 5404 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 5405 case ISD::SETCC: return LowerSETCC(Op, DAG); 5406 case ISD::SELECT: return LowerSELECT(Op, DAG); 5407 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 5408 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5409 case ISD::CALL: return LowerCALL(Op, DAG); 5410 case ISD::RET: return LowerRET(Op, DAG); 5411 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 5412 case ISD::MEMSET: return LowerMEMSET(Op, DAG); 5413 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 5414 case ISD::VASTART: return LowerVASTART(Op, DAG); 5415 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 5416 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5417 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5418 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5419 case ISD::FRAME_TO_ARGS_OFFSET: 5420 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 5421 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 5422 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 5423 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 5424 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5425 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 5426 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 5427 5428 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands. 5429 case ISD::READCYCLECOUNTER: 5430 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0); 5431 } 5432} 5433 5434/// ExpandOperation - Provide custom lowering hooks for expanding operations. 5435SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 5436 switch (N->getOpcode()) { 5437 default: assert(0 && "Should not custom lower this!"); 5438 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG); 5439 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG); 5440 case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG); 5441 } 5442} 5443 5444const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 5445 switch (Opcode) { 5446 default: return NULL; 5447 case X86ISD::BSF: return "X86ISD::BSF"; 5448 case X86ISD::BSR: return "X86ISD::BSR"; 5449 case X86ISD::SHLD: return "X86ISD::SHLD"; 5450 case X86ISD::SHRD: return "X86ISD::SHRD"; 5451 case X86ISD::FAND: return "X86ISD::FAND"; 5452 case X86ISD::FOR: return "X86ISD::FOR"; 5453 case X86ISD::FXOR: return "X86ISD::FXOR"; 5454 case X86ISD::FSRL: return "X86ISD::FSRL"; 5455 case X86ISD::FILD: return "X86ISD::FILD"; 5456 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 5457 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 5458 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 5459 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 5460 case X86ISD::FLD: return "X86ISD::FLD"; 5461 case X86ISD::FST: return "X86ISD::FST"; 5462 case X86ISD::CALL: return "X86ISD::CALL"; 5463 case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; 5464 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 5465 case X86ISD::CMP: return "X86ISD::CMP"; 5466 case X86ISD::COMI: return "X86ISD::COMI"; 5467 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 5468 case X86ISD::SETCC: return "X86ISD::SETCC"; 5469 case X86ISD::CMOV: return "X86ISD::CMOV"; 5470 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 5471 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 5472 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 5473 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 5474 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 5475 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 5476 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 5477 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 5478 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 5479 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 5480 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 5481 case X86ISD::FMAX: return "X86ISD::FMAX"; 5482 case X86ISD::FMIN: return "X86ISD::FMIN"; 5483 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 5484 case X86ISD::FRCP: return "X86ISD::FRCP"; 5485 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 5486 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER"; 5487 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 5488 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 5489 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 5490 case X86ISD::LCMPXCHG_DAG: return "x86ISD::LCMPXCHG_DAG"; 5491 case X86ISD::LCMPXCHG8_DAG: return "x86ISD::LCMPXCHG8_DAG"; 5492 } 5493} 5494 5495// isLegalAddressingMode - Return true if the addressing mode represented 5496// by AM is legal for this target, for a load/store of the specified type. 5497bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 5498 const Type *Ty) const { 5499 // X86 supports extremely general addressing modes. 5500 5501 // X86 allows a sign-extended 32-bit immediate field as a displacement. 5502 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1) 5503 return false; 5504 5505 if (AM.BaseGV) { 5506 // We can only fold this if we don't need an extra load. 5507 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false)) 5508 return false; 5509 5510 // X86-64 only supports addr of globals in small code model. 5511 if (Subtarget->is64Bit()) { 5512 if (getTargetMachine().getCodeModel() != CodeModel::Small) 5513 return false; 5514 // If lower 4G is not available, then we must use rip-relative addressing. 5515 if (AM.BaseOffs || AM.Scale > 1) 5516 return false; 5517 } 5518 } 5519 5520 switch (AM.Scale) { 5521 case 0: 5522 case 1: 5523 case 2: 5524 case 4: 5525 case 8: 5526 // These scales always work. 5527 break; 5528 case 3: 5529 case 5: 5530 case 9: 5531 // These scales are formed with basereg+scalereg. Only accept if there is 5532 // no basereg yet. 5533 if (AM.HasBaseReg) 5534 return false; 5535 break; 5536 default: // Other stuff never works. 5537 return false; 5538 } 5539 5540 return true; 5541} 5542 5543 5544bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 5545 if (!Ty1->isInteger() || !Ty2->isInteger()) 5546 return false; 5547 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 5548 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 5549 if (NumBits1 <= NumBits2) 5550 return false; 5551 return Subtarget->is64Bit() || NumBits1 < 64; 5552} 5553 5554bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1, 5555 MVT::ValueType VT2) const { 5556 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2)) 5557 return false; 5558 unsigned NumBits1 = MVT::getSizeInBits(VT1); 5559 unsigned NumBits2 = MVT::getSizeInBits(VT2); 5560 if (NumBits1 <= NumBits2) 5561 return false; 5562 return Subtarget->is64Bit() || NumBits1 < 64; 5563} 5564 5565/// isShuffleMaskLegal - Targets can use this to indicate that they only 5566/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 5567/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 5568/// are assumed to be legal. 5569bool 5570X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const { 5571 // Only do shuffles on 128-bit vector types for now. 5572 if (MVT::getSizeInBits(VT) == 64) return false; 5573 return (Mask.Val->getNumOperands() <= 4 || 5574 isIdentityMask(Mask.Val) || 5575 isIdentityMask(Mask.Val, true) || 5576 isSplatMask(Mask.Val) || 5577 isPSHUFHW_PSHUFLWMask(Mask.Val) || 5578 X86::isUNPCKLMask(Mask.Val) || 5579 X86::isUNPCKHMask(Mask.Val) || 5580 X86::isUNPCKL_v_undef_Mask(Mask.Val) || 5581 X86::isUNPCKH_v_undef_Mask(Mask.Val)); 5582} 5583 5584bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps, 5585 MVT::ValueType EVT, 5586 SelectionDAG &DAG) const { 5587 unsigned NumElts = BVOps.size(); 5588 // Only do shuffles on 128-bit vector types for now. 5589 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false; 5590 if (NumElts == 2) return true; 5591 if (NumElts == 4) { 5592 return (isMOVLMask(&BVOps[0], 4) || 5593 isCommutedMOVL(&BVOps[0], 4, true) || 5594 isSHUFPMask(&BVOps[0], 4) || 5595 isCommutedSHUFP(&BVOps[0], 4)); 5596 } 5597 return false; 5598} 5599 5600//===----------------------------------------------------------------------===// 5601// X86 Scheduler Hooks 5602//===----------------------------------------------------------------------===// 5603 5604MachineBasicBlock * 5605X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5606 MachineBasicBlock *BB) { 5607 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5608 switch (MI->getOpcode()) { 5609 default: assert(false && "Unexpected instr type to insert"); 5610 case X86::CMOV_FR32: 5611 case X86::CMOV_FR64: 5612 case X86::CMOV_V4F32: 5613 case X86::CMOV_V2F64: 5614 case X86::CMOV_V2I64: { 5615 // To "insert" a SELECT_CC instruction, we actually have to insert the 5616 // diamond control-flow pattern. The incoming instruction knows the 5617 // destination vreg to set, the condition code register to branch on, the 5618 // true/false values to select between, and a branch opcode to use. 5619 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5620 ilist<MachineBasicBlock>::iterator It = BB; 5621 ++It; 5622 5623 // thisMBB: 5624 // ... 5625 // TrueVal = ... 5626 // cmpTY ccX, r1, r2 5627 // bCC copy1MBB 5628 // fallthrough --> copy0MBB 5629 MachineBasicBlock *thisMBB = BB; 5630 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 5631 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 5632 unsigned Opc = 5633 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 5634 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); 5635 MachineFunction *F = BB->getParent(); 5636 F->getBasicBlockList().insert(It, copy0MBB); 5637 F->getBasicBlockList().insert(It, sinkMBB); 5638 // Update machine-CFG edges by first adding all successors of the current 5639 // block to the new block which will contain the Phi node for the select. 5640 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 5641 e = BB->succ_end(); i != e; ++i) 5642 sinkMBB->addSuccessor(*i); 5643 // Next, remove all successors of the current block, and add the true 5644 // and fallthrough blocks as its successors. 5645 while(!BB->succ_empty()) 5646 BB->removeSuccessor(BB->succ_begin()); 5647 BB->addSuccessor(copy0MBB); 5648 BB->addSuccessor(sinkMBB); 5649 5650 // copy0MBB: 5651 // %FalseValue = ... 5652 // # fallthrough to sinkMBB 5653 BB = copy0MBB; 5654 5655 // Update machine-CFG edges 5656 BB->addSuccessor(sinkMBB); 5657 5658 // sinkMBB: 5659 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 5660 // ... 5661 BB = sinkMBB; 5662 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) 5663 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 5664 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 5665 5666 delete MI; // The pseudo instruction is gone now. 5667 return BB; 5668 } 5669 5670 case X86::FP32_TO_INT16_IN_MEM: 5671 case X86::FP32_TO_INT32_IN_MEM: 5672 case X86::FP32_TO_INT64_IN_MEM: 5673 case X86::FP64_TO_INT16_IN_MEM: 5674 case X86::FP64_TO_INT32_IN_MEM: 5675 case X86::FP64_TO_INT64_IN_MEM: 5676 case X86::FP80_TO_INT16_IN_MEM: 5677 case X86::FP80_TO_INT32_IN_MEM: 5678 case X86::FP80_TO_INT64_IN_MEM: { 5679 // Change the floating point control register to use "round towards zero" 5680 // mode when truncating to an integer value. 5681 MachineFunction *F = BB->getParent(); 5682 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 5683 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); 5684 5685 // Load the old value of the high byte of the control word... 5686 unsigned OldCW = 5687 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 5688 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); 5689 5690 // Set the high part to be round to zero... 5691 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) 5692 .addImm(0xC7F); 5693 5694 // Reload the modified control word now... 5695 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 5696 5697 // Restore the memory image of control word to original value 5698 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) 5699 .addReg(OldCW); 5700 5701 // Get the X86 opcode to use. 5702 unsigned Opc; 5703 switch (MI->getOpcode()) { 5704 default: assert(0 && "illegal opcode!"); 5705 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 5706 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 5707 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 5708 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 5709 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 5710 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 5711 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 5712 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 5713 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 5714 } 5715 5716 X86AddressMode AM; 5717 MachineOperand &Op = MI->getOperand(0); 5718 if (Op.isRegister()) { 5719 AM.BaseType = X86AddressMode::RegBase; 5720 AM.Base.Reg = Op.getReg(); 5721 } else { 5722 AM.BaseType = X86AddressMode::FrameIndexBase; 5723 AM.Base.FrameIndex = Op.getIndex(); 5724 } 5725 Op = MI->getOperand(1); 5726 if (Op.isImmediate()) 5727 AM.Scale = Op.getImm(); 5728 Op = MI->getOperand(2); 5729 if (Op.isImmediate()) 5730 AM.IndexReg = Op.getImm(); 5731 Op = MI->getOperand(3); 5732 if (Op.isGlobalAddress()) { 5733 AM.GV = Op.getGlobal(); 5734 } else { 5735 AM.Disp = Op.getImm(); 5736 } 5737 addFullAddress(BuildMI(BB, TII->get(Opc)), AM) 5738 .addReg(MI->getOperand(4).getReg()); 5739 5740 // Reload the original control word now. 5741 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); 5742 5743 delete MI; // The pseudo instruction is gone now. 5744 return BB; 5745 } 5746 } 5747} 5748 5749//===----------------------------------------------------------------------===// 5750// X86 Optimization Hooks 5751//===----------------------------------------------------------------------===// 5752 5753void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 5754 const APInt &Mask, 5755 APInt &KnownZero, 5756 APInt &KnownOne, 5757 const SelectionDAG &DAG, 5758 unsigned Depth) const { 5759 unsigned Opc = Op.getOpcode(); 5760 assert((Opc >= ISD::BUILTIN_OP_END || 5761 Opc == ISD::INTRINSIC_WO_CHAIN || 5762 Opc == ISD::INTRINSIC_W_CHAIN || 5763 Opc == ISD::INTRINSIC_VOID) && 5764 "Should use MaskedValueIsZero if you don't know whether Op" 5765 " is a target node!"); 5766 5767 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 5768 switch (Opc) { 5769 default: break; 5770 case X86ISD::SETCC: 5771 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 5772 Mask.getBitWidth() - 1); 5773 break; 5774 } 5775} 5776 5777/// getShuffleScalarElt - Returns the scalar element that will make up the ith 5778/// element of the result of the vector shuffle. 5779static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) { 5780 MVT::ValueType VT = N->getValueType(0); 5781 SDOperand PermMask = N->getOperand(2); 5782 unsigned NumElems = PermMask.getNumOperands(); 5783 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1); 5784 i %= NumElems; 5785 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5786 return (i == 0) 5787 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); 5788 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) { 5789 SDOperand Idx = PermMask.getOperand(i); 5790 if (Idx.getOpcode() == ISD::UNDEF) 5791 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT)); 5792 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG); 5793 } 5794 return SDOperand(); 5795} 5796 5797/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 5798/// node is a GlobalAddress + an offset. 5799static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) { 5800 unsigned Opc = N->getOpcode(); 5801 if (Opc == X86ISD::Wrapper) { 5802 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) { 5803 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 5804 return true; 5805 } 5806 } else if (Opc == ISD::ADD) { 5807 SDOperand N1 = N->getOperand(0); 5808 SDOperand N2 = N->getOperand(1); 5809 if (isGAPlusOffset(N1.Val, GA, Offset)) { 5810 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 5811 if (V) { 5812 Offset += V->getSignExtended(); 5813 return true; 5814 } 5815 } else if (isGAPlusOffset(N2.Val, GA, Offset)) { 5816 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 5817 if (V) { 5818 Offset += V->getSignExtended(); 5819 return true; 5820 } 5821 } 5822 } 5823 return false; 5824} 5825 5826/// isConsecutiveLoad - Returns true if N is loading from an address of Base 5827/// + Dist * Size. 5828static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size, 5829 MachineFrameInfo *MFI) { 5830 if (N->getOperand(0).Val != Base->getOperand(0).Val) 5831 return false; 5832 5833 SDOperand Loc = N->getOperand(1); 5834 SDOperand BaseLoc = Base->getOperand(1); 5835 if (Loc.getOpcode() == ISD::FrameIndex) { 5836 if (BaseLoc.getOpcode() != ISD::FrameIndex) 5837 return false; 5838 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 5839 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 5840 int FS = MFI->getObjectSize(FI); 5841 int BFS = MFI->getObjectSize(BFI); 5842 if (FS != BFS || FS != Size) return false; 5843 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size); 5844 } else { 5845 GlobalValue *GV1 = NULL; 5846 GlobalValue *GV2 = NULL; 5847 int64_t Offset1 = 0; 5848 int64_t Offset2 = 0; 5849 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); 5850 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); 5851 if (isGA1 && isGA2 && GV1 == GV2) 5852 return Offset1 == (Offset2 + Dist*Size); 5853 } 5854 5855 return false; 5856} 5857 5858static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI, 5859 const X86Subtarget *Subtarget) { 5860 GlobalValue *GV; 5861 int64_t Offset = 0; 5862 if (isGAPlusOffset(Base, GV, Offset)) 5863 return (GV->getAlignment() >= 16 && (Offset % 16) == 0); 5864 // DAG combine handles the stack object case. 5865 return false; 5866} 5867 5868 5869/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 5870/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 5871/// if the load addresses are consecutive, non-overlapping, and in the right 5872/// order. 5873static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 5874 const X86Subtarget *Subtarget) { 5875 MachineFunction &MF = DAG.getMachineFunction(); 5876 MachineFrameInfo *MFI = MF.getFrameInfo(); 5877 MVT::ValueType VT = N->getValueType(0); 5878 MVT::ValueType EVT = MVT::getVectorElementType(VT); 5879 SDOperand PermMask = N->getOperand(2); 5880 int NumElems = (int)PermMask.getNumOperands(); 5881 SDNode *Base = NULL; 5882 for (int i = 0; i < NumElems; ++i) { 5883 SDOperand Idx = PermMask.getOperand(i); 5884 if (Idx.getOpcode() == ISD::UNDEF) { 5885 if (!Base) return SDOperand(); 5886 } else { 5887 SDOperand Arg = 5888 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG); 5889 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val)) 5890 return SDOperand(); 5891 if (!Base) 5892 Base = Arg.Val; 5893 else if (!isConsecutiveLoad(Arg.Val, Base, 5894 i, MVT::getSizeInBits(EVT)/8,MFI)) 5895 return SDOperand(); 5896 } 5897 } 5898 5899 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget); 5900 LoadSDNode *LD = cast<LoadSDNode>(Base); 5901 if (isAlign16) { 5902 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 5903 LD->getSrcValueOffset(), LD->isVolatile()); 5904 } else { 5905 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), 5906 LD->getSrcValueOffset(), LD->isVolatile(), 5907 LD->getAlignment()); 5908 } 5909} 5910 5911/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 5912static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 5913 const X86Subtarget *Subtarget) { 5914 SDOperand Cond = N->getOperand(0); 5915 5916 // If we have SSE[12] support, try to form min/max nodes. 5917 if (Subtarget->hasSSE2() && 5918 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) { 5919 if (Cond.getOpcode() == ISD::SETCC) { 5920 // Get the LHS/RHS of the select. 5921 SDOperand LHS = N->getOperand(1); 5922 SDOperand RHS = N->getOperand(2); 5923 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 5924 5925 unsigned Opcode = 0; 5926 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 5927 switch (CC) { 5928 default: break; 5929 case ISD::SETOLE: // (X <= Y) ? X : Y -> min 5930 case ISD::SETULE: 5931 case ISD::SETLE: 5932 if (!UnsafeFPMath) break; 5933 // FALL THROUGH. 5934 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min 5935 case ISD::SETLT: 5936 Opcode = X86ISD::FMIN; 5937 break; 5938 5939 case ISD::SETOGT: // (X > Y) ? X : Y -> max 5940 case ISD::SETUGT: 5941 case ISD::SETGT: 5942 if (!UnsafeFPMath) break; 5943 // FALL THROUGH. 5944 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max 5945 case ISD::SETGE: 5946 Opcode = X86ISD::FMAX; 5947 break; 5948 } 5949 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 5950 switch (CC) { 5951 default: break; 5952 case ISD::SETOGT: // (X > Y) ? Y : X -> min 5953 case ISD::SETUGT: 5954 case ISD::SETGT: 5955 if (!UnsafeFPMath) break; 5956 // FALL THROUGH. 5957 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min 5958 case ISD::SETGE: 5959 Opcode = X86ISD::FMIN; 5960 break; 5961 5962 case ISD::SETOLE: // (X <= Y) ? Y : X -> max 5963 case ISD::SETULE: 5964 case ISD::SETLE: 5965 if (!UnsafeFPMath) break; 5966 // FALL THROUGH. 5967 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max 5968 case ISD::SETLT: 5969 Opcode = X86ISD::FMAX; 5970 break; 5971 } 5972 } 5973 5974 if (Opcode) 5975 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS); 5976 } 5977 5978 } 5979 5980 return SDOperand(); 5981} 5982 5983/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 5984static SDOperand PerformSTORECombine(StoreSDNode *St, SelectionDAG &DAG, 5985 const X86Subtarget *Subtarget) { 5986 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 5987 // the FP state in cases where an emms may be missing. 5988 // A preferable solution to the general problem is to figure out the right 5989 // places to insert EMMS. This qualifies as a quick hack. 5990 if (MVT::isVector(St->getValue().getValueType()) && 5991 MVT::getSizeInBits(St->getValue().getValueType()) == 64 && 5992 isa<LoadSDNode>(St->getValue()) && 5993 !cast<LoadSDNode>(St->getValue())->isVolatile() && 5994 St->getChain().hasOneUse() && !St->isVolatile()) { 5995 SDNode* LdVal = St->getValue().Val; 5996 LoadSDNode *Ld = 0; 5997 int TokenFactorIndex = -1; 5998 SmallVector<SDOperand, 8> Ops; 5999 SDNode* ChainVal = St->getChain().Val; 6000 // Must be a store of a load. We currently handle two cases: the load 6001 // is a direct child, and it's under an intervening TokenFactor. It is 6002 // possible to dig deeper under nested TokenFactors. 6003 if (ChainVal == LdVal) 6004 Ld = cast<LoadSDNode>(St->getChain()); 6005 else if (St->getValue().hasOneUse() && 6006 ChainVal->getOpcode() == ISD::TokenFactor) { 6007 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 6008 if (ChainVal->getOperand(i).Val == LdVal) { 6009 TokenFactorIndex = i; 6010 Ld = cast<LoadSDNode>(St->getValue()); 6011 } else 6012 Ops.push_back(ChainVal->getOperand(i)); 6013 } 6014 } 6015 if (Ld) { 6016 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 6017 if (Subtarget->is64Bit()) { 6018 SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(), 6019 Ld->getBasePtr(), Ld->getSrcValue(), 6020 Ld->getSrcValueOffset(), Ld->isVolatile(), 6021 Ld->getAlignment()); 6022 SDOperand NewChain = NewLd.getValue(1); 6023 if (TokenFactorIndex != -1) { 6024 Ops.push_back(NewLd); 6025 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 6026 Ops.size()); 6027 } 6028 return DAG.getStore(NewChain, NewLd, St->getBasePtr(), 6029 St->getSrcValue(), St->getSrcValueOffset(), 6030 St->isVolatile(), St->getAlignment()); 6031 } 6032 6033 // Otherwise, lower to two 32-bit copies. 6034 SDOperand LoAddr = Ld->getBasePtr(); 6035 SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 6036 DAG.getConstant(MVT::i32, 4)); 6037 6038 SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr, 6039 Ld->getSrcValue(), Ld->getSrcValueOffset(), 6040 Ld->isVolatile(), Ld->getAlignment()); 6041 SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr, 6042 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 6043 Ld->isVolatile(), 6044 MinAlign(Ld->getAlignment(), 4)); 6045 6046 SDOperand NewChain = LoLd.getValue(1); 6047 if (TokenFactorIndex != -1) { 6048 Ops.push_back(LoLd); 6049 Ops.push_back(HiLd); 6050 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], 6051 Ops.size()); 6052 } 6053 6054 LoAddr = St->getBasePtr(); 6055 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr, 6056 DAG.getConstant(MVT::i32, 4)); 6057 6058 SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr, 6059 St->getSrcValue(), St->getSrcValueOffset(), 6060 St->isVolatile(), St->getAlignment()); 6061 SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr, 6062 St->getSrcValue(), St->getSrcValueOffset()+4, 6063 St->isVolatile(), 6064 MinAlign(St->getAlignment(), 4)); 6065 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt); 6066 } 6067 } 6068 return SDOperand(); 6069} 6070 6071/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 6072/// X86ISD::FXOR nodes. 6073static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 6074 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 6075 // F[X]OR(0.0, x) -> x 6076 // F[X]OR(x, 0.0) -> x 6077 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 6078 if (C->getValueAPF().isPosZero()) 6079 return N->getOperand(1); 6080 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 6081 if (C->getValueAPF().isPosZero()) 6082 return N->getOperand(0); 6083 return SDOperand(); 6084} 6085 6086/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 6087static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 6088 // FAND(0.0, x) -> 0.0 6089 // FAND(x, 0.0) -> 0.0 6090 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 6091 if (C->getValueAPF().isPosZero()) 6092 return N->getOperand(0); 6093 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 6094 if (C->getValueAPF().isPosZero()) 6095 return N->getOperand(1); 6096 return SDOperand(); 6097} 6098 6099 6100SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N, 6101 DAGCombinerInfo &DCI) const { 6102 SelectionDAG &DAG = DCI.DAG; 6103 switch (N->getOpcode()) { 6104 default: break; 6105 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget); 6106 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 6107 case ISD::STORE: 6108 return PerformSTORECombine(cast<StoreSDNode>(N), DAG, Subtarget); 6109 case X86ISD::FXOR: 6110 case X86ISD::FOR: return PerformFORCombine(N, DAG); 6111 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 6112 } 6113 6114 return SDOperand(); 6115} 6116 6117//===----------------------------------------------------------------------===// 6118// X86 Inline Assembly Support 6119//===----------------------------------------------------------------------===// 6120 6121/// getConstraintType - Given a constraint letter, return the type of 6122/// constraint it is for this target. 6123X86TargetLowering::ConstraintType 6124X86TargetLowering::getConstraintType(const std::string &Constraint) const { 6125 if (Constraint.size() == 1) { 6126 switch (Constraint[0]) { 6127 case 'A': 6128 case 'f': 6129 case 'r': 6130 case 'R': 6131 case 'l': 6132 case 'q': 6133 case 'Q': 6134 case 'x': 6135 case 'Y': 6136 return C_RegisterClass; 6137 default: 6138 break; 6139 } 6140 } 6141 return TargetLowering::getConstraintType(Constraint); 6142} 6143 6144/// LowerXConstraint - try to replace an X constraint, which matches anything, 6145/// with another that has more specific requirements based on the type of the 6146/// corresponding operand. 6147void X86TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT, 6148 std::string& s) const { 6149 if (MVT::isFloatingPoint(ConstraintVT)) { 6150 if (Subtarget->hasSSE2()) 6151 s = "Y"; 6152 else if (Subtarget->hasSSE1()) 6153 s = "x"; 6154 else 6155 s = "f"; 6156 } else 6157 return TargetLowering::lowerXConstraint(ConstraintVT, s); 6158} 6159 6160/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 6161/// vector. If it is invalid, don't add anything to Ops. 6162void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 6163 char Constraint, 6164 std::vector<SDOperand>&Ops, 6165 SelectionDAG &DAG) { 6166 SDOperand Result(0, 0); 6167 6168 switch (Constraint) { 6169 default: break; 6170 case 'I': 6171 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 6172 if (C->getValue() <= 31) { 6173 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType()); 6174 break; 6175 } 6176 } 6177 return; 6178 case 'N': 6179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 6180 if (C->getValue() <= 255) { 6181 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType()); 6182 break; 6183 } 6184 } 6185 return; 6186 case 'i': { 6187 // Literal immediates are always ok. 6188 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 6189 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType()); 6190 break; 6191 } 6192 6193 // If we are in non-pic codegen mode, we allow the address of a global (with 6194 // an optional displacement) to be used with 'i'. 6195 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 6196 int64_t Offset = 0; 6197 6198 // Match either (GA) or (GA+C) 6199 if (GA) { 6200 Offset = GA->getOffset(); 6201 } else if (Op.getOpcode() == ISD::ADD) { 6202 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6203 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 6204 if (C && GA) { 6205 Offset = GA->getOffset()+C->getValue(); 6206 } else { 6207 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6208 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 6209 if (C && GA) 6210 Offset = GA->getOffset()+C->getValue(); 6211 else 6212 C = 0, GA = 0; 6213 } 6214 } 6215 6216 if (GA) { 6217 // If addressing this global requires a load (e.g. in PIC mode), we can't 6218 // match. 6219 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(), 6220 false)) 6221 return; 6222 6223 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 6224 Offset); 6225 Result = Op; 6226 break; 6227 } 6228 6229 // Otherwise, not valid for this mode. 6230 return; 6231 } 6232 } 6233 6234 if (Result.Val) { 6235 Ops.push_back(Result); 6236 return; 6237 } 6238 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 6239} 6240 6241std::vector<unsigned> X86TargetLowering:: 6242getRegClassForInlineAsmConstraint(const std::string &Constraint, 6243 MVT::ValueType VT) const { 6244 if (Constraint.size() == 1) { 6245 // FIXME: not handling fp-stack yet! 6246 switch (Constraint[0]) { // GCC X86 Constraint Letters 6247 default: break; // Unknown constraint letter 6248 case 'A': // EAX/EDX 6249 if (VT == MVT::i32 || VT == MVT::i64) 6250 return make_vector<unsigned>(X86::EAX, X86::EDX, 0); 6251 break; 6252 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) 6253 case 'Q': // Q_REGS 6254 if (VT == MVT::i32) 6255 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 6256 else if (VT == MVT::i16) 6257 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 6258 else if (VT == MVT::i8) 6259 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 6260 else if (VT == MVT::i64) 6261 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 6262 break; 6263 } 6264 } 6265 6266 return std::vector<unsigned>(); 6267} 6268 6269std::pair<unsigned, const TargetRegisterClass*> 6270X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 6271 MVT::ValueType VT) const { 6272 // First, see if this is a constraint that directly corresponds to an LLVM 6273 // register class. 6274 if (Constraint.size() == 1) { 6275 // GCC Constraint Letters 6276 switch (Constraint[0]) { 6277 default: break; 6278 case 'r': // GENERAL_REGS 6279 case 'R': // LEGACY_REGS 6280 case 'l': // INDEX_REGS 6281 if (VT == MVT::i64 && Subtarget->is64Bit()) 6282 return std::make_pair(0U, X86::GR64RegisterClass); 6283 if (VT == MVT::i32) 6284 return std::make_pair(0U, X86::GR32RegisterClass); 6285 else if (VT == MVT::i16) 6286 return std::make_pair(0U, X86::GR16RegisterClass); 6287 else if (VT == MVT::i8) 6288 return std::make_pair(0U, X86::GR8RegisterClass); 6289 break; 6290 case 'f': // FP Stack registers. 6291 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 6292 // value to the correct fpstack register class. 6293 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 6294 return std::make_pair(0U, X86::RFP32RegisterClass); 6295 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 6296 return std::make_pair(0U, X86::RFP64RegisterClass); 6297 return std::make_pair(0U, X86::RFP80RegisterClass); 6298 case 'y': // MMX_REGS if MMX allowed. 6299 if (!Subtarget->hasMMX()) break; 6300 return std::make_pair(0U, X86::VR64RegisterClass); 6301 break; 6302 case 'Y': // SSE_REGS if SSE2 allowed 6303 if (!Subtarget->hasSSE2()) break; 6304 // FALL THROUGH. 6305 case 'x': // SSE_REGS if SSE1 allowed 6306 if (!Subtarget->hasSSE1()) break; 6307 6308 switch (VT) { 6309 default: break; 6310 // Scalar SSE types. 6311 case MVT::f32: 6312 case MVT::i32: 6313 return std::make_pair(0U, X86::FR32RegisterClass); 6314 case MVT::f64: 6315 case MVT::i64: 6316 return std::make_pair(0U, X86::FR64RegisterClass); 6317 // Vector types. 6318 case MVT::v16i8: 6319 case MVT::v8i16: 6320 case MVT::v4i32: 6321 case MVT::v2i64: 6322 case MVT::v4f32: 6323 case MVT::v2f64: 6324 return std::make_pair(0U, X86::VR128RegisterClass); 6325 } 6326 break; 6327 } 6328 } 6329 6330 // Use the default implementation in TargetLowering to convert the register 6331 // constraint into a member of a register class. 6332 std::pair<unsigned, const TargetRegisterClass*> Res; 6333 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 6334 6335 // Not found as a standard register? 6336 if (Res.second == 0) { 6337 // GCC calls "st(0)" just plain "st". 6338 if (StringsEqualNoCase("{st}", Constraint)) { 6339 Res.first = X86::ST0; 6340 Res.second = X86::RFP80RegisterClass; 6341 } 6342 6343 return Res; 6344 } 6345 6346 // Otherwise, check to see if this is a register class of the wrong value 6347 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 6348 // turn into {ax},{dx}. 6349 if (Res.second->hasType(VT)) 6350 return Res; // Correct type already, nothing to do. 6351 6352 // All of the single-register GCC register classes map their values onto 6353 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 6354 // really want an 8-bit or 32-bit register, map to the appropriate register 6355 // class and return the appropriate register. 6356 if (Res.second != X86::GR16RegisterClass) 6357 return Res; 6358 6359 if (VT == MVT::i8) { 6360 unsigned DestReg = 0; 6361 switch (Res.first) { 6362 default: break; 6363 case X86::AX: DestReg = X86::AL; break; 6364 case X86::DX: DestReg = X86::DL; break; 6365 case X86::CX: DestReg = X86::CL; break; 6366 case X86::BX: DestReg = X86::BL; break; 6367 } 6368 if (DestReg) { 6369 Res.first = DestReg; 6370 Res.second = Res.second = X86::GR8RegisterClass; 6371 } 6372 } else if (VT == MVT::i32) { 6373 unsigned DestReg = 0; 6374 switch (Res.first) { 6375 default: break; 6376 case X86::AX: DestReg = X86::EAX; break; 6377 case X86::DX: DestReg = X86::EDX; break; 6378 case X86::CX: DestReg = X86::ECX; break; 6379 case X86::BX: DestReg = X86::EBX; break; 6380 case X86::SI: DestReg = X86::ESI; break; 6381 case X86::DI: DestReg = X86::EDI; break; 6382 case X86::BP: DestReg = X86::EBP; break; 6383 case X86::SP: DestReg = X86::ESP; break; 6384 } 6385 if (DestReg) { 6386 Res.first = DestReg; 6387 Res.second = Res.second = X86::GR32RegisterClass; 6388 } 6389 } else if (VT == MVT::i64) { 6390 unsigned DestReg = 0; 6391 switch (Res.first) { 6392 default: break; 6393 case X86::AX: DestReg = X86::RAX; break; 6394 case X86::DX: DestReg = X86::RDX; break; 6395 case X86::CX: DestReg = X86::RCX; break; 6396 case X86::BX: DestReg = X86::RBX; break; 6397 case X86::SI: DestReg = X86::RSI; break; 6398 case X86::DI: DestReg = X86::RDI; break; 6399 case X86::BP: DestReg = X86::RBP; break; 6400 case X86::SP: DestReg = X86::RSP; break; 6401 } 6402 if (DestReg) { 6403 Res.first = DestReg; 6404 Res.second = Res.second = X86::GR64RegisterClass; 6405 } 6406 } 6407 6408 return Res; 6409} 6410