X86ISelLowering.cpp revision 66ddd153f6c3481cc4e1a771526157f41a9832b5
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86ISelLowering.h" 17#include "X86.h" 18#include "X86InstrBuilder.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VariadicFunction.h" 46#include "llvm/Support/CallSite.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Target/TargetOptions.h" 51#include <bitset> 52using namespace llvm; 53 54STATISTIC(NumTailCalls, "Number of tail calls"); 55 56// Forward declarations. 57static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 58 SDValue V2); 59 60/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 61/// sets things up to match to an AVX VEXTRACTF128 instruction or a 62/// simple subregister reference. Idx is an index in the 128 bits we 63/// want. It need not be aligned to a 128-bit bounday. That makes 64/// lowering EXTRACT_VECTOR_ELT operations easier. 65static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, 66 SelectionDAG &DAG, DebugLoc dl) { 67 EVT VT = Vec.getValueType(); 68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 69 EVT ElVT = VT.getVectorElementType(); 70 unsigned Factor = VT.getSizeInBits()/128; 71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 72 VT.getVectorNumElements()/Factor); 73 74 // Extract from UNDEF is UNDEF. 75 if (Vec.getOpcode() == ISD::UNDEF) 76 return DAG.getUNDEF(ResultVT); 77 78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 79 // we can match to VEXTRACTF128. 80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 81 82 // This is the index of the first element of the 128-bit chunk 83 // we want. 84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 85 * ElemsPerChunk); 86 87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 89 VecIdx); 90 91 return Result; 92} 93 94/// Generate a DAG to put 128-bits into a vector > 128 bits. This 95/// sets things up to match to an AVX VINSERTF128 instruction or a 96/// simple superregister reference. Idx is an index in the 128 bits 97/// we want. It need not be aligned to a 128-bit bounday. That makes 98/// lowering INSERT_VECTOR_ELT operations easier. 99static SDValue Insert128BitVector(SDValue Result, SDValue Vec, 100 unsigned IdxVal, SelectionDAG &DAG, 101 DebugLoc dl) { 102 EVT VT = Vec.getValueType(); 103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 104 105 EVT ElVT = VT.getVectorElementType(); 106 EVT ResultVT = Result.getValueType(); 107 108 // Insert the relevant 128 bits. 109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 110 111 // This is the index of the first element of the 128-bit chunk 112 // we want. 113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 114 * ElemsPerChunk); 115 116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 118 VecIdx); 119 return Result; 120} 121 122/// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 123/// instructions. This is used because creating CONCAT_VECTOR nodes of 124/// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower 125/// large BUILD_VECTORS. 126static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, 127 unsigned NumElems, SelectionDAG &DAG, 128 DebugLoc dl) { 129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl); 130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl); 131} 132 133static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 135 bool is64Bit = Subtarget->is64Bit(); 136 137 if (Subtarget->isTargetEnvMacho()) { 138 if (is64Bit) 139 return new X8664_MachoTargetObjectFile(); 140 return new TargetLoweringObjectFileMachO(); 141 } 142 143 if (Subtarget->isTargetELF()) 144 return new TargetLoweringObjectFileELF(); 145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 146 return new TargetLoweringObjectFileCOFF(); 147 llvm_unreachable("unknown subtarget type"); 148} 149 150X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 151 : TargetLowering(TM, createTLOF(TM)) { 152 Subtarget = &TM.getSubtarget<X86Subtarget>(); 153 X86ScalarSSEf64 = Subtarget->hasSSE2(); 154 X86ScalarSSEf32 = Subtarget->hasSSE1(); 155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 156 157 RegInfo = TM.getRegisterInfo(); 158 TD = getTargetData(); 159 160 // Set up the TargetLowering object. 161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 162 163 // X86 is weird, it always uses i8 for shift amounts and setcc results. 164 setBooleanContents(ZeroOrOneBooleanContent); 165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 167 168 // For 64-bit since we have so many registers use the ILP scheduler, for 169 // 32-bit code use the register pressure specific scheduling. 170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling. 171 if (Subtarget->is64Bit()) 172 setSchedulingPreference(Sched::ILP); 173 else if (Subtarget->isAtom()) 174 setSchedulingPreference(Sched::Hybrid); 175 else 176 setSchedulingPreference(Sched::RegPressure); 177 setStackPointerRegisterToSaveRestore(X86StackPtr); 178 179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 180 // Setup Windows compiler runtime calls. 181 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 183 setLibcallName(RTLIB::SREM_I64, "_allrem"); 184 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 185 setLibcallName(RTLIB::MUL_I64, "_allmul"); 186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 191 192 // The _ftol2 runtime function has an unusual calling conv, which 193 // is modeled by a special pseudo-instruction. 194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0); 195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0); 196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0); 197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0); 198 } 199 200 if (Subtarget->isTargetDarwin()) { 201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 202 setUseUnderscoreSetJmp(false); 203 setUseUnderscoreLongJmp(false); 204 } else if (Subtarget->isTargetMingw()) { 205 // MS runtime is weird: it exports _setjmp, but longjmp! 206 setUseUnderscoreSetJmp(true); 207 setUseUnderscoreLongJmp(false); 208 } else { 209 setUseUnderscoreSetJmp(true); 210 setUseUnderscoreLongJmp(true); 211 } 212 213 // Set up the register classes. 214 addRegisterClass(MVT::i8, &X86::GR8RegClass); 215 addRegisterClass(MVT::i16, &X86::GR16RegClass); 216 addRegisterClass(MVT::i32, &X86::GR32RegClass); 217 if (Subtarget->is64Bit()) 218 addRegisterClass(MVT::i64, &X86::GR64RegClass); 219 220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 221 222 // We don't accept any truncstore of integer registers. 223 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 224 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 226 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 228 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 229 230 // SETOEQ and SETUNE require checking two conditions. 231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 237 238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 239 // operation. 240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 243 244 if (Subtarget->is64Bit()) { 245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 247 } else if (!TM.Options.UseSoftFloat) { 248 // We have an algorithm for SSE2->double, and we turn this into a 249 // 64-bit FILD followed by conditional FADD for other targets. 250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 251 // We have an algorithm for SSE2, and we turn this into a 64-bit 252 // FILD for other targets. 253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 254 } 255 256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 257 // this operation. 258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 260 261 if (!TM.Options.UseSoftFloat) { 262 // SSE has no i16 to fp conversion, only i32 263 if (X86ScalarSSEf32) { 264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 265 // f32 and f64 cases are Legal, f80 case is not 266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 267 } else { 268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 270 } 271 } else { 272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 274 } 275 276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 277 // are Legal, f80 is custom lowered. 278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 280 281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 282 // this operation. 283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 285 286 if (X86ScalarSSEf32) { 287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 288 // f32 and f64 cases are Legal, f80 case is not 289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 290 } else { 291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 293 } 294 295 // Handle FP_TO_UINT by promoting the destination to a larger signed 296 // conversion. 297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 300 301 if (Subtarget->is64Bit()) { 302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 304 } else if (!TM.Options.UseSoftFloat) { 305 // Since AVX is a superset of SSE3, only check for SSE here. 306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 307 // Expand FP_TO_UINT into a select. 308 // FIXME: We would like to use a Custom expander here eventually to do 309 // the optimal thing for SSE vs. the default expansion in the legalizer. 310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 311 else 312 // With SSE3 we can use fisttpll to convert to a signed i64; without 313 // SSE, we're stuck with a fistpll. 314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 315 } 316 317 if (isTargetFTOL()) { 318 // Use the _ftol2 runtime function, which has a pseudo-instruction 319 // to handle its weird calling convention. 320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom); 321 } 322 323 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 324 if (!X86ScalarSSEf64) { 325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 327 if (Subtarget->is64Bit()) { 328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 329 // Without SSE, i64->f64 goes through memory. 330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 331 } 332 } 333 334 // Scalar integer divide and remainder are lowered to use operations that 335 // produce two results, to match the available instructions. This exposes 336 // the two-result form to trivial CSE, which is able to combine x/y and x%y 337 // into a single instruction. 338 // 339 // Scalar integer multiply-high is also lowered to use two-result 340 // operations, to match the available instructions. However, plain multiply 341 // (low) operations are left as Legal, as there are single-result 342 // instructions for this in x86. Using the two-result multiply instructions 343 // when both high and low results are needed must be arranged by dagcombine. 344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 345 MVT VT = IntVTs[i]; 346 setOperationAction(ISD::MULHS, VT, Expand); 347 setOperationAction(ISD::MULHU, VT, Expand); 348 setOperationAction(ISD::SDIV, VT, Expand); 349 setOperationAction(ISD::UDIV, VT, Expand); 350 setOperationAction(ISD::SREM, VT, Expand); 351 setOperationAction(ISD::UREM, VT, Expand); 352 353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 354 setOperationAction(ISD::ADDC, VT, Custom); 355 setOperationAction(ISD::ADDE, VT, Custom); 356 setOperationAction(ISD::SUBC, VT, Custom); 357 setOperationAction(ISD::SUBE, VT, Custom); 358 } 359 360 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 361 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 362 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 364 if (Subtarget->is64Bit()) 365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 370 setOperationAction(ISD::FREM , MVT::f32 , Expand); 371 setOperationAction(ISD::FREM , MVT::f64 , Expand); 372 setOperationAction(ISD::FREM , MVT::f80 , Expand); 373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 374 375 // Promote the i8 variants and force them on up to i32 which has a shorter 376 // encoding. 377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 381 if (Subtarget->hasBMI()) { 382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 384 if (Subtarget->is64Bit()) 385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 386 } else { 387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 389 if (Subtarget->is64Bit()) 390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 391 } 392 393 if (Subtarget->hasLZCNT()) { 394 // When promoting the i8 variants, force them to i32 for a shorter 395 // encoding. 396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 402 if (Subtarget->is64Bit()) 403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 404 } else { 405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 411 if (Subtarget->is64Bit()) { 412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 414 } 415 } 416 417 if (Subtarget->hasPOPCNT()) { 418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 419 } else { 420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 423 if (Subtarget->is64Bit()) 424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 425 } 426 427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 429 430 // These should be promoted to a larger select which is supported. 431 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 432 // X86 wants to expand cmov itself. 433 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 434 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 435 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 436 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 437 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 438 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 439 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 440 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 441 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 442 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 443 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 444 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 445 if (Subtarget->is64Bit()) { 446 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 447 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 448 } 449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 450 451 // Darwin ABI issue. 452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 456 if (Subtarget->is64Bit()) 457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 460 if (Subtarget->is64Bit()) { 461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 466 } 467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 471 if (Subtarget->is64Bit()) { 472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 475 } 476 477 if (Subtarget->hasSSE1()) 478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 479 480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 482 483 // On X86 and X86-64, atomic operations are lowered to locked instructions. 484 // Locked instructions, in turn, have implicit fence semantics (all memory 485 // operations are flushed before issuing the locked instruction, and they 486 // are not buffered), so we can fold away the common pattern of 487 // fence-atomic-fence. 488 setShouldFoldAtomicFences(true); 489 490 // Expand certain atomics 491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) { 492 MVT VT = IntVTs[i]; 493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 496 } 497 498 if (!Subtarget->is64Bit()) { 499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 507 } 508 509 if (Subtarget->hasCmpxchg16b()) { 510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 511 } 512 513 // FIXME - use subtarget debug flags 514 if (!Subtarget->isTargetDarwin() && 515 !Subtarget->isTargetELF() && 516 !Subtarget->isTargetCygMing()) { 517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 518 } 519 520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 524 if (Subtarget->is64Bit()) { 525 setExceptionPointerRegister(X86::RAX); 526 setExceptionSelectorRegister(X86::RDX); 527 } else { 528 setExceptionPointerRegister(X86::EAX); 529 setExceptionSelectorRegister(X86::EDX); 530 } 531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 533 534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 536 537 setOperationAction(ISD::TRAP, MVT::Other, Legal); 538 539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 540 setOperationAction(ISD::VASTART , MVT::Other, Custom); 541 setOperationAction(ISD::VAEND , MVT::Other, Expand); 542 if (Subtarget->is64Bit()) { 543 setOperationAction(ISD::VAARG , MVT::Other, Custom); 544 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 545 } else { 546 setOperationAction(ISD::VAARG , MVT::Other, Expand); 547 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 548 } 549 550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 552 553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 555 MVT::i64 : MVT::i32, Custom); 556 else if (TM.Options.EnableSegmentedStacks) 557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 558 MVT::i64 : MVT::i32, Custom); 559 else 560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 561 MVT::i64 : MVT::i32, Expand); 562 563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 564 // f32 and f64 use SSE. 565 // Set up the FP register classes. 566 addRegisterClass(MVT::f32, &X86::FR32RegClass); 567 addRegisterClass(MVT::f64, &X86::FR64RegClass); 568 569 // Use ANDPD to simulate FABS. 570 setOperationAction(ISD::FABS , MVT::f64, Custom); 571 setOperationAction(ISD::FABS , MVT::f32, Custom); 572 573 // Use XORP to simulate FNEG. 574 setOperationAction(ISD::FNEG , MVT::f64, Custom); 575 setOperationAction(ISD::FNEG , MVT::f32, Custom); 576 577 // Use ANDPD and ORPD to simulate FCOPYSIGN. 578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 580 581 // Lower this to FGETSIGNx86 plus an AND. 582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 584 585 // We don't support sin/cos/fmod 586 setOperationAction(ISD::FSIN , MVT::f64, Expand); 587 setOperationAction(ISD::FCOS , MVT::f64, Expand); 588 setOperationAction(ISD::FSIN , MVT::f32, Expand); 589 setOperationAction(ISD::FCOS , MVT::f32, Expand); 590 591 // Expand FP immediates into loads from the stack, except for the special 592 // cases we handle. 593 addLegalFPImmediate(APFloat(+0.0)); // xorpd 594 addLegalFPImmediate(APFloat(+0.0f)); // xorps 595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 596 // Use SSE for f32, x87 for f64. 597 // Set up the FP register classes. 598 addRegisterClass(MVT::f32, &X86::FR32RegClass); 599 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 600 601 // Use ANDPS to simulate FABS. 602 setOperationAction(ISD::FABS , MVT::f32, Custom); 603 604 // Use XORP to simulate FNEG. 605 setOperationAction(ISD::FNEG , MVT::f32, Custom); 606 607 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 608 609 // Use ANDPS and ORPS to simulate FCOPYSIGN. 610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 612 613 // We don't support sin/cos/fmod 614 setOperationAction(ISD::FSIN , MVT::f32, Expand); 615 setOperationAction(ISD::FCOS , MVT::f32, Expand); 616 617 // Special cases we handle for FP constants. 618 addLegalFPImmediate(APFloat(+0.0f)); // xorps 619 addLegalFPImmediate(APFloat(+0.0)); // FLD0 620 addLegalFPImmediate(APFloat(+1.0)); // FLD1 621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 623 624 if (!TM.Options.UnsafeFPMath) { 625 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 626 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 627 } 628 } else if (!TM.Options.UseSoftFloat) { 629 // f32 and f64 in x87. 630 // Set up the FP register classes. 631 addRegisterClass(MVT::f64, &X86::RFP64RegClass); 632 addRegisterClass(MVT::f32, &X86::RFP32RegClass); 633 634 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 635 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 638 639 if (!TM.Options.UnsafeFPMath) { 640 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 641 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 642 } 643 addLegalFPImmediate(APFloat(+0.0)); // FLD0 644 addLegalFPImmediate(APFloat(+1.0)); // FLD1 645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 651 } 652 653 // We don't support FMA. 654 setOperationAction(ISD::FMA, MVT::f64, Expand); 655 setOperationAction(ISD::FMA, MVT::f32, Expand); 656 657 // Long double always uses X87. 658 if (!TM.Options.UseSoftFloat) { 659 addRegisterClass(MVT::f80, &X86::RFP80RegClass); 660 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 662 { 663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 664 addLegalFPImmediate(TmpFlt); // FLD0 665 TmpFlt.changeSign(); 666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 667 668 bool ignored; 669 APFloat TmpFlt2(+1.0); 670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 671 &ignored); 672 addLegalFPImmediate(TmpFlt2); // FLD1 673 TmpFlt2.changeSign(); 674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 675 } 676 677 if (!TM.Options.UnsafeFPMath) { 678 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 679 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 680 } 681 682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 683 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 685 setOperationAction(ISD::FRINT, MVT::f80, Expand); 686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 687 setOperationAction(ISD::FMA, MVT::f80, Expand); 688 } 689 690 // Always use a library call for pow. 691 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 692 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 693 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 694 695 setOperationAction(ISD::FLOG, MVT::f80, Expand); 696 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 697 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 698 setOperationAction(ISD::FEXP, MVT::f80, Expand); 699 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 700 701 // First set operation action for all vector types to either promote 702 // (for widening) or expand (for scalarization). Then we will selectively 703 // turn on ones that can be effectively codegen'd. 704 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 705 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 763 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 764 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 765 setTruncStoreAction((MVT::SimpleValueType)VT, 766 (MVT::SimpleValueType)InnerVT, Expand); 767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 770 } 771 772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 773 // with -msoft-float, disable use of MMX as well. 774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass); 776 // No operations on x86mmx supported, everything uses intrinsics. 777 } 778 779 // MMX-sized vectors (other than x86mmx) are expected to be expanded 780 // into smaller operations. 781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 785 setOperationAction(ISD::AND, MVT::v8i8, Expand); 786 setOperationAction(ISD::AND, MVT::v4i16, Expand); 787 setOperationAction(ISD::AND, MVT::v2i32, Expand); 788 setOperationAction(ISD::AND, MVT::v1i64, Expand); 789 setOperationAction(ISD::OR, MVT::v8i8, Expand); 790 setOperationAction(ISD::OR, MVT::v4i16, Expand); 791 setOperationAction(ISD::OR, MVT::v2i32, Expand); 792 setOperationAction(ISD::OR, MVT::v1i64, Expand); 793 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 794 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 795 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 796 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 810 811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass); 813 814 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 826 } 827 828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass); 830 831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 832 // registers cannot be used even for integer operations. 833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass); 834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass); 835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass); 836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass); 837 838 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 839 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 840 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 841 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 842 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 843 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 844 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 845 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 846 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 847 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 848 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 854 855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 859 860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 865 866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 871 872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 874 EVT VT = (MVT::SimpleValueType)i; 875 // Do not attempt to custom lower non-power-of-2 vectors 876 if (!isPowerOf2_32(VT.getVectorNumElements())) 877 continue; 878 // Do not attempt to custom lower non-128-bit vectors 879 if (!VT.is128BitVector()) 880 continue; 881 setOperationAction(ISD::BUILD_VECTOR, 882 VT.getSimpleVT().SimpleTy, Custom); 883 setOperationAction(ISD::VECTOR_SHUFFLE, 884 VT.getSimpleVT().SimpleTy, Custom); 885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 886 VT.getSimpleVT().SimpleTy, Custom); 887 } 888 889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 895 896 if (Subtarget->is64Bit()) { 897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 899 } 900 901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 902 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 904 EVT VT = SVT; 905 906 // Do not attempt to promote non-128-bit vectors 907 if (!VT.is128BitVector()) 908 continue; 909 910 setOperationAction(ISD::AND, SVT, Promote); 911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 912 setOperationAction(ISD::OR, SVT, Promote); 913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 914 setOperationAction(ISD::XOR, SVT, Promote); 915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 916 setOperationAction(ISD::LOAD, SVT, Promote); 917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 918 setOperationAction(ISD::SELECT, SVT, Promote); 919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 920 } 921 922 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 923 924 // Custom lower v2i64 and v2f64 selects. 925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 929 930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 932 } 933 934 if (Subtarget->hasSSE41()) { 935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 936 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 938 setOperationAction(ISD::FRINT, MVT::f32, Legal); 939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 941 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 943 setOperationAction(ISD::FRINT, MVT::f64, Legal); 944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 945 946 // FIXME: Do we need to handle scalar-to-vector here? 947 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 948 949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 954 955 // i8 and i16 vectors are custom , because the source register and source 956 // source memory operand types are not the same width. f32 vectors are 957 // custom since the immediate controlling the insert encodes additional 958 // information. 959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 963 964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 968 969 // FIXME: these should be Legal but thats only for the case where 970 // the index is constant. For now custom expand to deal with that. 971 if (Subtarget->is64Bit()) { 972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 974 } 975 } 976 977 if (Subtarget->hasSSE2()) { 978 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 979 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 980 981 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 982 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 983 984 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 985 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 986 987 if (Subtarget->hasAVX2()) { 988 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 989 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 990 991 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 992 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 993 994 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 995 } else { 996 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 997 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 998 999 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1001 1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1003 } 1004 } 1005 1006 if (Subtarget->hasSSE42()) 1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1008 1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass); 1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); 1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass); 1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); 1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass); 1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass); 1016 1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1020 1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1027 1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1034 1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1038 1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1045 1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1048 1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1051 1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1054 1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1059 1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1063 1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1068 1069 if (Subtarget->hasAVX2()) { 1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1074 1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1079 1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1083 // Don't lower v32i8 because there is no 128-bit byte mul 1084 1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1086 1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1089 1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1092 1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1094 } else { 1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1099 1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1104 1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1108 // Don't lower v32i8 because there is no 128-bit byte mul 1109 1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1112 1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1115 1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1117 } 1118 1119 // Custom lower several nodes for 256-bit types. 1120 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1123 EVT VT = SVT; 1124 1125 // Extract subvector is special because the value type 1126 // (result) is 128-bit but the source is 256-bit wide. 1127 if (VT.is128BitVector()) 1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1129 1130 // Do not attempt to custom lower other non-256-bit vectors 1131 if (!VT.is256BitVector()) 1132 continue; 1133 1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1140 } 1141 1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1143 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1145 EVT VT = SVT; 1146 1147 // Do not attempt to promote non-256-bit vectors 1148 if (!VT.is256BitVector()) 1149 continue; 1150 1151 setOperationAction(ISD::AND, SVT, Promote); 1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1153 setOperationAction(ISD::OR, SVT, Promote); 1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1155 setOperationAction(ISD::XOR, SVT, Promote); 1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1157 setOperationAction(ISD::LOAD, SVT, Promote); 1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1159 setOperationAction(ISD::SELECT, SVT, Promote); 1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1161 } 1162 } 1163 1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1165 // of this type with custom code. 1166 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1167 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1169 Custom); 1170 } 1171 1172 // We want to custom lower some of our intrinsics. 1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1174 1175 1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1177 // handle type legalization for these operations here. 1178 // 1179 // FIXME: We really should do custom legalization for addition and 1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1181 // than generic legalization for 64-bit multiplication-with-overflow, though. 1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1183 // Add/Sub/Mul with overflow operations are custom lowered. 1184 MVT VT = IntVTs[i]; 1185 setOperationAction(ISD::SADDO, VT, Custom); 1186 setOperationAction(ISD::UADDO, VT, Custom); 1187 setOperationAction(ISD::SSUBO, VT, Custom); 1188 setOperationAction(ISD::USUBO, VT, Custom); 1189 setOperationAction(ISD::SMULO, VT, Custom); 1190 setOperationAction(ISD::UMULO, VT, Custom); 1191 } 1192 1193 // There are no 8-bit 3-address imul/mul instructions 1194 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1195 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1196 1197 if (!Subtarget->is64Bit()) { 1198 // These libcalls are not available in 32-bit. 1199 setLibcallName(RTLIB::SHL_I128, 0); 1200 setLibcallName(RTLIB::SRL_I128, 0); 1201 setLibcallName(RTLIB::SRA_I128, 0); 1202 } 1203 1204 // We have target-specific dag combine patterns for the following nodes: 1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1207 setTargetDAGCombine(ISD::VSELECT); 1208 setTargetDAGCombine(ISD::SELECT); 1209 setTargetDAGCombine(ISD::SHL); 1210 setTargetDAGCombine(ISD::SRA); 1211 setTargetDAGCombine(ISD::SRL); 1212 setTargetDAGCombine(ISD::OR); 1213 setTargetDAGCombine(ISD::AND); 1214 setTargetDAGCombine(ISD::ADD); 1215 setTargetDAGCombine(ISD::FADD); 1216 setTargetDAGCombine(ISD::FSUB); 1217 setTargetDAGCombine(ISD::SUB); 1218 setTargetDAGCombine(ISD::LOAD); 1219 setTargetDAGCombine(ISD::STORE); 1220 setTargetDAGCombine(ISD::ZERO_EXTEND); 1221 setTargetDAGCombine(ISD::ANY_EXTEND); 1222 setTargetDAGCombine(ISD::SIGN_EXTEND); 1223 setTargetDAGCombine(ISD::TRUNCATE); 1224 setTargetDAGCombine(ISD::UINT_TO_FP); 1225 setTargetDAGCombine(ISD::SINT_TO_FP); 1226 setTargetDAGCombine(ISD::SETCC); 1227 setTargetDAGCombine(ISD::FP_TO_SINT); 1228 if (Subtarget->is64Bit()) 1229 setTargetDAGCombine(ISD::MUL); 1230 if (Subtarget->hasBMI()) 1231 setTargetDAGCombine(ISD::XOR); 1232 1233 computeRegisterProperties(); 1234 1235 // On Darwin, -Os means optimize for size without hurting performance, 1236 // do not reduce the limit. 1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1243 setPrefLoopAlignment(4); // 2^4 bytes. 1244 benefitFromCodePlacementOpt = true; 1245 1246 setPrefFunctionAlignment(4); // 2^4 bytes. 1247} 1248 1249 1250EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1251 if (!VT.isVector()) return MVT::i8; 1252 return VT.changeVectorElementTypeToInteger(); 1253} 1254 1255 1256/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1257/// the desired ByVal argument alignment. 1258static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1259 if (MaxAlign == 16) 1260 return; 1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1262 if (VTy->getBitWidth() == 128) 1263 MaxAlign = 16; 1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1265 unsigned EltAlign = 0; 1266 getMaxByValAlign(ATy->getElementType(), EltAlign); 1267 if (EltAlign > MaxAlign) 1268 MaxAlign = EltAlign; 1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1271 unsigned EltAlign = 0; 1272 getMaxByValAlign(STy->getElementType(i), EltAlign); 1273 if (EltAlign > MaxAlign) 1274 MaxAlign = EltAlign; 1275 if (MaxAlign == 16) 1276 break; 1277 } 1278 } 1279} 1280 1281/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1282/// function arguments in the caller parameter area. For X86, aggregates 1283/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1284/// are at 4-byte boundaries. 1285unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1286 if (Subtarget->is64Bit()) { 1287 // Max of 8 and alignment of type. 1288 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1289 if (TyAlign > 8) 1290 return TyAlign; 1291 return 8; 1292 } 1293 1294 unsigned Align = 4; 1295 if (Subtarget->hasSSE1()) 1296 getMaxByValAlign(Ty, Align); 1297 return Align; 1298} 1299 1300/// getOptimalMemOpType - Returns the target specific optimal type for load 1301/// and store operations as a result of memset, memcpy, and memmove 1302/// lowering. If DstAlign is zero that means it's safe to destination 1303/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1304/// means there isn't a need to check it against alignment requirement, 1305/// probably because the source does not need to be loaded. If 1306/// 'IsZeroVal' is true, that means it's safe to return a 1307/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1308/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1309/// constant so it does not need to be loaded. 1310/// It returns EVT::Other if the type should be determined using generic 1311/// target-independent logic. 1312EVT 1313X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1314 unsigned DstAlign, unsigned SrcAlign, 1315 bool IsZeroVal, 1316 bool MemcpyStrSrc, 1317 MachineFunction &MF) const { 1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1319 // linux. This is because the stack realignment code can't handle certain 1320 // cases like PR2962. This should be removed when PR2962 is fixed. 1321 const Function *F = MF.getFunction(); 1322 if (IsZeroVal && 1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1324 if (Size >= 16 && 1325 (Subtarget->isUnalignedMemAccessFast() || 1326 ((DstAlign == 0 || DstAlign >= 16) && 1327 (SrcAlign == 0 || SrcAlign >= 16))) && 1328 Subtarget->getStackAlignment() >= 16) { 1329 if (Subtarget->getStackAlignment() >= 32) { 1330 if (Subtarget->hasAVX2()) 1331 return MVT::v8i32; 1332 if (Subtarget->hasAVX()) 1333 return MVT::v8f32; 1334 } 1335 if (Subtarget->hasSSE2()) 1336 return MVT::v4i32; 1337 if (Subtarget->hasSSE1()) 1338 return MVT::v4f32; 1339 } else if (!MemcpyStrSrc && Size >= 8 && 1340 !Subtarget->is64Bit() && 1341 Subtarget->getStackAlignment() >= 8 && 1342 Subtarget->hasSSE2()) { 1343 // Do not use f64 to lower memcpy if source is string constant. It's 1344 // better to use i32 to avoid the loads. 1345 return MVT::f64; 1346 } 1347 } 1348 if (Subtarget->is64Bit() && Size >= 8) 1349 return MVT::i64; 1350 return MVT::i32; 1351} 1352 1353/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1354/// current function. The returned value is a member of the 1355/// MachineJumpTableInfo::JTEntryKind enum. 1356unsigned X86TargetLowering::getJumpTableEncoding() const { 1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1358 // symbol. 1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1360 Subtarget->isPICStyleGOT()) 1361 return MachineJumpTableInfo::EK_Custom32; 1362 1363 // Otherwise, use the normal jump table encoding heuristics. 1364 return TargetLowering::getJumpTableEncoding(); 1365} 1366 1367const MCExpr * 1368X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1369 const MachineBasicBlock *MBB, 1370 unsigned uid,MCContext &Ctx) const{ 1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1372 Subtarget->isPICStyleGOT()); 1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1374 // entries. 1375 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1376 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1377} 1378 1379/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1380/// jumptable. 1381SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1382 SelectionDAG &DAG) const { 1383 if (!Subtarget->is64Bit()) 1384 // This doesn't have DebugLoc associated with it, but is not really the 1385 // same as a Register. 1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1387 return Table; 1388} 1389 1390/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1391/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1392/// MCExpr. 1393const MCExpr *X86TargetLowering:: 1394getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1395 MCContext &Ctx) const { 1396 // X86-64 uses RIP relative addressing based on the jump table label. 1397 if (Subtarget->isPICStyleRIPRel()) 1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1399 1400 // Otherwise, the reference is relative to the PIC base. 1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1402} 1403 1404// FIXME: Why this routine is here? Move to RegInfo! 1405std::pair<const TargetRegisterClass*, uint8_t> 1406X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1407 const TargetRegisterClass *RRC = 0; 1408 uint8_t Cost = 1; 1409 switch (VT.getSimpleVT().SimpleTy) { 1410 default: 1411 return TargetLowering::findRepresentativeClass(VT); 1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1413 RRC = Subtarget->is64Bit() ? 1414 (const TargetRegisterClass*)&X86::GR64RegClass : 1415 (const TargetRegisterClass*)&X86::GR32RegClass; 1416 break; 1417 case MVT::x86mmx: 1418 RRC = &X86::VR64RegClass; 1419 break; 1420 case MVT::f32: case MVT::f64: 1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1422 case MVT::v4f32: case MVT::v2f64: 1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1424 case MVT::v4f64: 1425 RRC = &X86::VR128RegClass; 1426 break; 1427 } 1428 return std::make_pair(RRC, Cost); 1429} 1430 1431bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1432 unsigned &Offset) const { 1433 if (!Subtarget->isTargetLinux()) 1434 return false; 1435 1436 if (Subtarget->is64Bit()) { 1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1438 Offset = 0x28; 1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1440 AddressSpace = 256; 1441 else 1442 AddressSpace = 257; 1443 } else { 1444 // %gs:0x14 on i386 1445 Offset = 0x14; 1446 AddressSpace = 256; 1447 } 1448 return true; 1449} 1450 1451 1452//===----------------------------------------------------------------------===// 1453// Return Value Calling Convention Implementation 1454//===----------------------------------------------------------------------===// 1455 1456#include "X86GenCallingConv.inc" 1457 1458bool 1459X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1460 MachineFunction &MF, bool isVarArg, 1461 const SmallVectorImpl<ISD::OutputArg> &Outs, 1462 LLVMContext &Context) const { 1463 SmallVector<CCValAssign, 16> RVLocs; 1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1465 RVLocs, Context); 1466 return CCInfo.CheckReturn(Outs, RetCC_X86); 1467} 1468 1469SDValue 1470X86TargetLowering::LowerReturn(SDValue Chain, 1471 CallingConv::ID CallConv, bool isVarArg, 1472 const SmallVectorImpl<ISD::OutputArg> &Outs, 1473 const SmallVectorImpl<SDValue> &OutVals, 1474 DebugLoc dl, SelectionDAG &DAG) const { 1475 MachineFunction &MF = DAG.getMachineFunction(); 1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1477 1478 SmallVector<CCValAssign, 16> RVLocs; 1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1480 RVLocs, *DAG.getContext()); 1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1482 1483 // Add the regs to the liveout set for the function. 1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1485 for (unsigned i = 0; i != RVLocs.size(); ++i) 1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1487 MRI.addLiveOut(RVLocs[i].getLocReg()); 1488 1489 SDValue Flag; 1490 1491 SmallVector<SDValue, 6> RetOps; 1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1493 // Operand #1 = Bytes To Pop 1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1495 MVT::i16)); 1496 1497 // Copy the result values into the output registers. 1498 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1499 CCValAssign &VA = RVLocs[i]; 1500 assert(VA.isRegLoc() && "Can only return in registers!"); 1501 SDValue ValToCopy = OutVals[i]; 1502 EVT ValVT = ValToCopy.getValueType(); 1503 1504 // If this is x86-64, and we disabled SSE, we can't return FP values, 1505 // or SSE or MMX vectors. 1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1509 report_fatal_error("SSE register return with SSE disabled"); 1510 } 1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1512 // llvm-gcc has never done it right and no one has noticed, so this 1513 // should be OK for now. 1514 if (ValVT == MVT::f64 && 1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1516 report_fatal_error("SSE2 register return with SSE2 disabled"); 1517 1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1519 // the RET instruction and handled by the FP Stackifier. 1520 if (VA.getLocReg() == X86::ST0 || 1521 VA.getLocReg() == X86::ST1) { 1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1523 // change the value to the FP stack register class. 1524 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1526 RetOps.push_back(ValToCopy); 1527 // Don't emit a copytoreg. 1528 continue; 1529 } 1530 1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1532 // which is returned in RAX / RDX. 1533 if (Subtarget->is64Bit()) { 1534 if (ValVT == MVT::x86mmx) { 1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1538 ValToCopy); 1539 // If we don't have SSE2 available, convert to v4f32 so the generated 1540 // register is legal. 1541 if (!Subtarget->hasSSE2()) 1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1543 } 1544 } 1545 } 1546 1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1548 Flag = Chain.getValue(1); 1549 } 1550 1551 // The x86-64 ABI for returning structs by value requires that we copy 1552 // the sret argument into %rax for the return. We saved the argument into 1553 // a virtual register in the entry block, so now we copy the value out 1554 // and into %rax. 1555 if (Subtarget->is64Bit() && 1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1557 MachineFunction &MF = DAG.getMachineFunction(); 1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1559 unsigned Reg = FuncInfo->getSRetReturnReg(); 1560 assert(Reg && 1561 "SRetReturnReg should have been set in LowerFormalArguments()."); 1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1563 1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1565 Flag = Chain.getValue(1); 1566 1567 // RAX now acts like a return value. 1568 MRI.addLiveOut(X86::RAX); 1569 } 1570 1571 RetOps[0] = Chain; // Update chain. 1572 1573 // Add the flag if we have it. 1574 if (Flag.getNode()) 1575 RetOps.push_back(Flag); 1576 1577 return DAG.getNode(X86ISD::RET_FLAG, dl, 1578 MVT::Other, &RetOps[0], RetOps.size()); 1579} 1580 1581bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const { 1582 if (N->getNumValues() != 1) 1583 return false; 1584 if (!N->hasNUsesOfValue(1, 0)) 1585 return false; 1586 1587 SDValue TCChain = Chain; 1588 SDNode *Copy = *N->use_begin(); 1589 if (Copy->getOpcode() == ISD::CopyToReg) { 1590 // If the copy has a glue operand, we conservatively assume it isn't safe to 1591 // perform a tail call. 1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue) 1593 return false; 1594 TCChain = Copy->getOperand(0); 1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 1596 return false; 1597 1598 bool HasRet = false; 1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1600 UI != UE; ++UI) { 1601 if (UI->getOpcode() != X86ISD::RET_FLAG) 1602 return false; 1603 HasRet = true; 1604 } 1605 1606 if (!HasRet) 1607 return false; 1608 1609 Chain = TCChain; 1610 return true; 1611} 1612 1613EVT 1614X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1615 ISD::NodeType ExtendKind) const { 1616 MVT ReturnMVT; 1617 // TODO: Is this also valid on 32-bit? 1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1619 ReturnMVT = MVT::i8; 1620 else 1621 ReturnMVT = MVT::i32; 1622 1623 EVT MinVT = getRegisterType(Context, ReturnMVT); 1624 return VT.bitsLT(MinVT) ? MinVT : VT; 1625} 1626 1627/// LowerCallResult - Lower the result values of a call into the 1628/// appropriate copies out of appropriate physical registers. 1629/// 1630SDValue 1631X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1632 CallingConv::ID CallConv, bool isVarArg, 1633 const SmallVectorImpl<ISD::InputArg> &Ins, 1634 DebugLoc dl, SelectionDAG &DAG, 1635 SmallVectorImpl<SDValue> &InVals) const { 1636 1637 // Assign locations to each value returned by this call. 1638 SmallVector<CCValAssign, 16> RVLocs; 1639 bool Is64Bit = Subtarget->is64Bit(); 1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1641 getTargetMachine(), RVLocs, *DAG.getContext()); 1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1643 1644 // Copy all of the result registers out of their specified physreg. 1645 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1646 CCValAssign &VA = RVLocs[i]; 1647 EVT CopyVT = VA.getValVT(); 1648 1649 // If this is x86-64, and we disabled SSE, we can't return FP values 1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1652 report_fatal_error("SSE register return with SSE disabled"); 1653 } 1654 1655 SDValue Val; 1656 1657 // If this is a call to a function that returns an fp value on the floating 1658 // point stack, we must guarantee the the value is popped from the stack, so 1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1660 // if the return value is not used. We use the FpPOP_RETVAL instruction 1661 // instead. 1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1663 // If we prefer to use the value in xmm registers, copy it out as f80 and 1664 // use a truncate to move it from fp stack reg to xmm reg. 1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1666 SDValue Ops[] = { Chain, InFlag }; 1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1668 MVT::Other, MVT::Glue, Ops, 2), 1); 1669 Val = Chain.getValue(0); 1670 1671 // Round the f80 to the right size, which also moves it to the appropriate 1672 // xmm register. 1673 if (CopyVT != VA.getValVT()) 1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1675 // This truncation won't change the value. 1676 DAG.getIntPtrConstant(1)); 1677 } else { 1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1679 CopyVT, InFlag).getValue(1); 1680 Val = Chain.getValue(0); 1681 } 1682 InFlag = Chain.getValue(2); 1683 InVals.push_back(Val); 1684 } 1685 1686 return Chain; 1687} 1688 1689 1690//===----------------------------------------------------------------------===// 1691// C & StdCall & Fast Calling Convention implementation 1692//===----------------------------------------------------------------------===// 1693// StdCall calling convention seems to be standard for many Windows' API 1694// routines and around. It differs from C calling convention just a little: 1695// callee should clean up the stack, not caller. Symbols should be also 1696// decorated in some fancy way :) It doesn't support any vector arguments. 1697// For info on fast calling convention see Fast Calling Convention (tail call) 1698// implementation LowerX86_32FastCCCallTo. 1699 1700/// CallIsStructReturn - Determines whether a call uses struct return 1701/// semantics. 1702static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1703 if (Outs.empty()) 1704 return false; 1705 1706 return Outs[0].Flags.isSRet(); 1707} 1708 1709/// ArgsAreStructReturn - Determines whether a function uses struct 1710/// return semantics. 1711static bool 1712ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1713 if (Ins.empty()) 1714 return false; 1715 1716 return Ins[0].Flags.isSRet(); 1717} 1718 1719/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1720/// by "Src" to address "Dst" with size and alignment information specified by 1721/// the specific parameter attribute. The copy will be passed as a byval 1722/// function parameter. 1723static SDValue 1724CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1726 DebugLoc dl) { 1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1728 1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1730 /*isVolatile*/false, /*AlwaysInline=*/true, 1731 MachinePointerInfo(), MachinePointerInfo()); 1732} 1733 1734/// IsTailCallConvention - Return true if the calling convention is one that 1735/// supports tail call optimization. 1736static bool IsTailCallConvention(CallingConv::ID CC) { 1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1738} 1739 1740bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1742 return false; 1743 1744 CallSite CS(CI); 1745 CallingConv::ID CalleeCC = CS.getCallingConv(); 1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1747 return false; 1748 1749 return true; 1750} 1751 1752/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1753/// a tailcall target by changing its ABI. 1754static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1755 bool GuaranteedTailCallOpt) { 1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1757} 1758 1759SDValue 1760X86TargetLowering::LowerMemArgument(SDValue Chain, 1761 CallingConv::ID CallConv, 1762 const SmallVectorImpl<ISD::InputArg> &Ins, 1763 DebugLoc dl, SelectionDAG &DAG, 1764 const CCValAssign &VA, 1765 MachineFrameInfo *MFI, 1766 unsigned i) const { 1767 // Create the nodes corresponding to a load from this parameter slot. 1768 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1770 getTargetMachine().Options.GuaranteedTailCallOpt); 1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1772 EVT ValVT; 1773 1774 // If value is passed by pointer we have address passed instead of the value 1775 // itself. 1776 if (VA.getLocInfo() == CCValAssign::Indirect) 1777 ValVT = VA.getLocVT(); 1778 else 1779 ValVT = VA.getValVT(); 1780 1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1782 // changed with more analysis. 1783 // In case of tail call optimization mark all arguments mutable. Since they 1784 // could be overwritten by lowering of arguments in case of a tail call. 1785 if (Flags.isByVal()) { 1786 unsigned Bytes = Flags.getByValSize(); 1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1789 return DAG.getFrameIndex(FI, getPointerTy()); 1790 } else { 1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1792 VA.getLocMemOffset(), isImmutable); 1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1794 return DAG.getLoad(ValVT, dl, Chain, FIN, 1795 MachinePointerInfo::getFixedStack(FI), 1796 false, false, false, 0); 1797 } 1798} 1799 1800SDValue 1801X86TargetLowering::LowerFormalArguments(SDValue Chain, 1802 CallingConv::ID CallConv, 1803 bool isVarArg, 1804 const SmallVectorImpl<ISD::InputArg> &Ins, 1805 DebugLoc dl, 1806 SelectionDAG &DAG, 1807 SmallVectorImpl<SDValue> &InVals) 1808 const { 1809 MachineFunction &MF = DAG.getMachineFunction(); 1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1811 1812 const Function* Fn = MF.getFunction(); 1813 if (Fn->hasExternalLinkage() && 1814 Subtarget->isTargetCygMing() && 1815 Fn->getName() == "main") 1816 FuncInfo->setForceFramePointer(true); 1817 1818 MachineFrameInfo *MFI = MF.getFrameInfo(); 1819 bool Is64Bit = Subtarget->is64Bit(); 1820 bool IsWindows = Subtarget->isTargetWindows(); 1821 bool IsWin64 = Subtarget->isTargetWin64(); 1822 1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1824 "Var args not supported with calling convention fastcc or ghc"); 1825 1826 // Assign locations to all of the incoming arguments. 1827 SmallVector<CCValAssign, 16> ArgLocs; 1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1829 ArgLocs, *DAG.getContext()); 1830 1831 // Allocate shadow area for Win64 1832 if (IsWin64) { 1833 CCInfo.AllocateStack(32, 8); 1834 } 1835 1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1837 1838 unsigned LastVal = ~0U; 1839 SDValue ArgValue; 1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1841 CCValAssign &VA = ArgLocs[i]; 1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1843 // places. 1844 assert(VA.getValNo() != LastVal && 1845 "Don't support value assigned to multiple locs yet"); 1846 (void)LastVal; 1847 LastVal = VA.getValNo(); 1848 1849 if (VA.isRegLoc()) { 1850 EVT RegVT = VA.getLocVT(); 1851 const TargetRegisterClass *RC; 1852 if (RegVT == MVT::i32) 1853 RC = &X86::GR32RegClass; 1854 else if (Is64Bit && RegVT == MVT::i64) 1855 RC = &X86::GR64RegClass; 1856 else if (RegVT == MVT::f32) 1857 RC = &X86::FR32RegClass; 1858 else if (RegVT == MVT::f64) 1859 RC = &X86::FR64RegClass; 1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1861 RC = &X86::VR256RegClass; 1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1863 RC = &X86::VR128RegClass; 1864 else if (RegVT == MVT::x86mmx) 1865 RC = &X86::VR64RegClass; 1866 else 1867 llvm_unreachable("Unknown argument type!"); 1868 1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1871 1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1874 // right size. 1875 if (VA.getLocInfo() == CCValAssign::SExt) 1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1877 DAG.getValueType(VA.getValVT())); 1878 else if (VA.getLocInfo() == CCValAssign::ZExt) 1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1880 DAG.getValueType(VA.getValVT())); 1881 else if (VA.getLocInfo() == CCValAssign::BCvt) 1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1883 1884 if (VA.isExtInLoc()) { 1885 // Handle MMX values passed in XMM regs. 1886 if (RegVT.isVector()) { 1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1888 ArgValue); 1889 } else 1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1891 } 1892 } else { 1893 assert(VA.isMemLoc()); 1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1895 } 1896 1897 // If value is passed via pointer - do a load. 1898 if (VA.getLocInfo() == CCValAssign::Indirect) 1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1900 MachinePointerInfo(), false, false, false, 0); 1901 1902 InVals.push_back(ArgValue); 1903 } 1904 1905 // The x86-64 ABI for returning structs by value requires that we copy 1906 // the sret argument into %rax for the return. Save the argument into 1907 // a virtual register so that we can access it from the return points. 1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1910 unsigned Reg = FuncInfo->getSRetReturnReg(); 1911 if (!Reg) { 1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1913 FuncInfo->setSRetReturnReg(Reg); 1914 } 1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1917 } 1918 1919 unsigned StackSize = CCInfo.getNextStackOffset(); 1920 // Align stack specially for tail calls. 1921 if (FuncIsMadeTailCallSafe(CallConv, 1922 MF.getTarget().Options.GuaranteedTailCallOpt)) 1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1924 1925 // If the function takes variable number of arguments, make a frame index for 1926 // the start of the first vararg value... for expansion of llvm.va_start. 1927 if (isVarArg) { 1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1929 CallConv != CallingConv::X86_ThisCall)) { 1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1931 } 1932 if (Is64Bit) { 1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1934 1935 // FIXME: We should really autogenerate these arrays 1936 static const uint16_t GPR64ArgRegsWin64[] = { 1937 X86::RCX, X86::RDX, X86::R8, X86::R9 1938 }; 1939 static const uint16_t GPR64ArgRegs64Bit[] = { 1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1941 }; 1942 static const uint16_t XMMArgRegs64Bit[] = { 1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1945 }; 1946 const uint16_t *GPR64ArgRegs; 1947 unsigned NumXMMRegs = 0; 1948 1949 if (IsWin64) { 1950 // The XMM registers which might contain var arg parameters are shadowed 1951 // in their paired GPR. So we only need to save the GPR to their home 1952 // slots. 1953 TotalNumIntRegs = 4; 1954 GPR64ArgRegs = GPR64ArgRegsWin64; 1955 } else { 1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1957 GPR64ArgRegs = GPR64ArgRegs64Bit; 1958 1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1960 TotalNumXMMRegs); 1961 } 1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1963 TotalNumIntRegs); 1964 1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1967 "SSE register cannot be used when SSE is disabled!"); 1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1969 NoImplicitFloatOps) && 1970 "SSE register cannot be used when SSE is disabled!"); 1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1972 !Subtarget->hasSSE1()) 1973 // Kernel mode asks for SSE to be disabled, so don't push them 1974 // on the stack. 1975 TotalNumXMMRegs = 0; 1976 1977 if (IsWin64) { 1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1979 // Get to the caller-allocated home save location. Add 8 to account 1980 // for the return address. 1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1982 FuncInfo->setRegSaveFrameIndex( 1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1984 // Fixup to set vararg frame on shadow area (4 x i64). 1985 if (NumIntRegs < 4) 1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1987 } else { 1988 // For X86-64, if there are vararg parameters that are passed via 1989 // registers, then we must store them to their spots on the stack so 1990 // they may be loaded by deferencing the result of va_next. 1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1993 FuncInfo->setRegSaveFrameIndex( 1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1995 false)); 1996 } 1997 1998 // Store the integer parameter registers. 1999 SmallVector<SDValue, 8> MemOps; 2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 2001 getPointerTy()); 2002 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 2005 DAG.getIntPtrConstant(Offset)); 2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2007 &X86::GR64RegClass); 2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2009 SDValue Store = 2010 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2011 MachinePointerInfo::getFixedStack( 2012 FuncInfo->getRegSaveFrameIndex(), Offset), 2013 false, false, 0); 2014 MemOps.push_back(Store); 2015 Offset += 8; 2016 } 2017 2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2019 // Now store the XMM (fp + vector) parameter registers. 2020 SmallVector<SDValue, 11> SaveXMMOps; 2021 SaveXMMOps.push_back(Chain); 2022 2023 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass); 2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2025 SaveXMMOps.push_back(ALVal); 2026 2027 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2028 FuncInfo->getRegSaveFrameIndex())); 2029 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2030 FuncInfo->getVarArgsFPOffset())); 2031 2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2034 &X86::VR128RegClass); 2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2036 SaveXMMOps.push_back(Val); 2037 } 2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2039 MVT::Other, 2040 &SaveXMMOps[0], SaveXMMOps.size())); 2041 } 2042 2043 if (!MemOps.empty()) 2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2045 &MemOps[0], MemOps.size()); 2046 } 2047 } 2048 2049 // Some CCs need callee pop. 2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2051 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2053 } else { 2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2055 // If this is an sret function, the return should pop the hidden pointer. 2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2057 ArgsAreStructReturn(Ins)) 2058 FuncInfo->setBytesToPopOnReturn(4); 2059 } 2060 2061 if (!Is64Bit) { 2062 // RegSaveFrameIndex is X86-64 only. 2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2064 if (CallConv == CallingConv::X86_FastCall || 2065 CallConv == CallingConv::X86_ThisCall) 2066 // fastcc functions can't have varargs. 2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2068 } 2069 2070 FuncInfo->setArgumentStackSize(StackSize); 2071 2072 return Chain; 2073} 2074 2075SDValue 2076X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2077 SDValue StackPtr, SDValue Arg, 2078 DebugLoc dl, SelectionDAG &DAG, 2079 const CCValAssign &VA, 2080 ISD::ArgFlagsTy Flags) const { 2081 unsigned LocMemOffset = VA.getLocMemOffset(); 2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2084 if (Flags.isByVal()) 2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2086 2087 return DAG.getStore(Chain, dl, Arg, PtrOff, 2088 MachinePointerInfo::getStack(LocMemOffset), 2089 false, false, 0); 2090} 2091 2092/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2093/// optimization is performed and it is required. 2094SDValue 2095X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2096 SDValue &OutRetAddr, SDValue Chain, 2097 bool IsTailCall, bool Is64Bit, 2098 int FPDiff, DebugLoc dl) const { 2099 // Adjust the Return address stack slot. 2100 EVT VT = getPointerTy(); 2101 OutRetAddr = getReturnAddressFrameIndex(DAG); 2102 2103 // Load the "old" Return address. 2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2105 false, false, false, 0); 2106 return SDValue(OutRetAddr.getNode(), 1); 2107} 2108 2109/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2110/// optimization is performed and it is required (FPDiff!=0). 2111static SDValue 2112EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2113 SDValue Chain, SDValue RetAddrFrIdx, 2114 bool Is64Bit, int FPDiff, DebugLoc dl) { 2115 // Store the return address to the appropriate stack slot. 2116 if (!FPDiff) return Chain; 2117 // Calculate the new stack slot for the return address. 2118 int SlotSize = Is64Bit ? 8 : 4; 2119 int NewReturnAddrFI = 2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2125 false, false, 0); 2126 return Chain; 2127} 2128 2129SDValue 2130X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2131 CallingConv::ID CallConv, bool isVarArg, 2132 bool doesNotRet, bool &isTailCall, 2133 const SmallVectorImpl<ISD::OutputArg> &Outs, 2134 const SmallVectorImpl<SDValue> &OutVals, 2135 const SmallVectorImpl<ISD::InputArg> &Ins, 2136 DebugLoc dl, SelectionDAG &DAG, 2137 SmallVectorImpl<SDValue> &InVals) const { 2138 MachineFunction &MF = DAG.getMachineFunction(); 2139 bool Is64Bit = Subtarget->is64Bit(); 2140 bool IsWin64 = Subtarget->isTargetWin64(); 2141 bool IsWindows = Subtarget->isTargetWindows(); 2142 bool IsStructRet = CallIsStructReturn(Outs); 2143 bool IsSibcall = false; 2144 2145 if (MF.getTarget().Options.DisableTailCalls) 2146 isTailCall = false; 2147 2148 if (isTailCall) { 2149 // Check if it's really possible to do a tail call. 2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2152 Outs, OutVals, Ins, DAG); 2153 2154 // Sibcalls are automatically detected tailcalls which do not require 2155 // ABI changes. 2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2157 IsSibcall = true; 2158 2159 if (isTailCall) 2160 ++NumTailCalls; 2161 } 2162 2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2164 "Var args not supported with calling convention fastcc or ghc"); 2165 2166 // Analyze operands of the call, assigning locations to each operand. 2167 SmallVector<CCValAssign, 16> ArgLocs; 2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2169 ArgLocs, *DAG.getContext()); 2170 2171 // Allocate shadow area for Win64 2172 if (IsWin64) { 2173 CCInfo.AllocateStack(32, 8); 2174 } 2175 2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2177 2178 // Get a count of how many bytes are to be pushed on the stack. 2179 unsigned NumBytes = CCInfo.getNextStackOffset(); 2180 if (IsSibcall) 2181 // This is a sibcall. The memory operands are available in caller's 2182 // own caller's stack. 2183 NumBytes = 0; 2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2185 IsTailCallConvention(CallConv)) 2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2187 2188 int FPDiff = 0; 2189 if (isTailCall && !IsSibcall) { 2190 // Lower arguments at fp - stackoffset + fpdiff. 2191 unsigned NumBytesCallerPushed = 2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2193 FPDiff = NumBytesCallerPushed - NumBytes; 2194 2195 // Set the delta of movement of the returnaddr stackslot. 2196 // But only set if delta is greater than previous delta. 2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2199 } 2200 2201 if (!IsSibcall) 2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2203 2204 SDValue RetAddrFrIdx; 2205 // Load return address for tail calls. 2206 if (isTailCall && FPDiff) 2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2208 Is64Bit, FPDiff, dl); 2209 2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2211 SmallVector<SDValue, 8> MemOpChains; 2212 SDValue StackPtr; 2213 2214 // Walk the register/memloc assignments, inserting copies/loads. In the case 2215 // of tail call optimization arguments are handle later. 2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2217 CCValAssign &VA = ArgLocs[i]; 2218 EVT RegVT = VA.getLocVT(); 2219 SDValue Arg = OutVals[i]; 2220 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2221 bool isByVal = Flags.isByVal(); 2222 2223 // Promote the value if needed. 2224 switch (VA.getLocInfo()) { 2225 default: llvm_unreachable("Unknown loc info!"); 2226 case CCValAssign::Full: break; 2227 case CCValAssign::SExt: 2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2229 break; 2230 case CCValAssign::ZExt: 2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2232 break; 2233 case CCValAssign::AExt: 2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2235 // Special case: passing MMX values in XMM registers. 2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2239 } else 2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2241 break; 2242 case CCValAssign::BCvt: 2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2244 break; 2245 case CCValAssign::Indirect: { 2246 // Store the argument. 2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2250 MachinePointerInfo::getFixedStack(FI), 2251 false, false, 0); 2252 Arg = SpillSlot; 2253 break; 2254 } 2255 } 2256 2257 if (VA.isRegLoc()) { 2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2259 if (isVarArg && IsWin64) { 2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2261 // shadow reg if callee is a varargs function. 2262 unsigned ShadowReg = 0; 2263 switch (VA.getLocReg()) { 2264 case X86::XMM0: ShadowReg = X86::RCX; break; 2265 case X86::XMM1: ShadowReg = X86::RDX; break; 2266 case X86::XMM2: ShadowReg = X86::R8; break; 2267 case X86::XMM3: ShadowReg = X86::R9; break; 2268 } 2269 if (ShadowReg) 2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2271 } 2272 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2273 assert(VA.isMemLoc()); 2274 if (StackPtr.getNode() == 0) 2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2277 dl, DAG, VA, Flags)); 2278 } 2279 } 2280 2281 if (!MemOpChains.empty()) 2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2283 &MemOpChains[0], MemOpChains.size()); 2284 2285 // Build a sequence of copy-to-reg nodes chained together with token chain 2286 // and flag operands which copy the outgoing args into registers. 2287 SDValue InFlag; 2288 // Tail call byval lowering might overwrite argument registers so in case of 2289 // tail call optimization the copies to registers are lowered later. 2290 if (!isTailCall) 2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2293 RegsToPass[i].second, InFlag); 2294 InFlag = Chain.getValue(1); 2295 } 2296 2297 if (Subtarget->isPICStyleGOT()) { 2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2299 // GOT pointer. 2300 if (!isTailCall) { 2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2302 DAG.getNode(X86ISD::GlobalBaseReg, 2303 DebugLoc(), getPointerTy()), 2304 InFlag); 2305 InFlag = Chain.getValue(1); 2306 } else { 2307 // If we are tail calling and generating PIC/GOT style code load the 2308 // address of the callee into ECX. The value in ecx is used as target of 2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2310 // for tail calls on PIC/GOT architectures. Normally we would just put the 2311 // address of GOT into ebx and then call target@PLT. But for tail calls 2312 // ebx would be restored (since ebx is callee saved) before jumping to the 2313 // target@PLT. 2314 2315 // Note: The actual moving to ECX is done further down. 2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2317 if (G && !G->getGlobal()->hasHiddenVisibility() && 2318 !G->getGlobal()->hasProtectedVisibility()) 2319 Callee = LowerGlobalAddress(Callee, DAG); 2320 else if (isa<ExternalSymbolSDNode>(Callee)) 2321 Callee = LowerExternalSymbol(Callee, DAG); 2322 } 2323 } 2324 2325 if (Is64Bit && isVarArg && !IsWin64) { 2326 // From AMD64 ABI document: 2327 // For calls that may call functions that use varargs or stdargs 2328 // (prototype-less calls or calls to functions containing ellipsis (...) in 2329 // the declaration) %al is used as hidden argument to specify the number 2330 // of SSE registers used. The contents of %al do not need to match exactly 2331 // the number of registers, but must be an ubound on the number of SSE 2332 // registers used and is in the range 0 - 8 inclusive. 2333 2334 // Count the number of XMM registers allocated. 2335 static const uint16_t XMMArgRegs[] = { 2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2338 }; 2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2340 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2341 && "SSE registers cannot be used when SSE is disabled"); 2342 2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2345 InFlag = Chain.getValue(1); 2346 } 2347 2348 2349 // For tail calls lower the arguments to the 'real' stack slot. 2350 if (isTailCall) { 2351 // Force all the incoming stack arguments to be loaded from the stack 2352 // before any new outgoing arguments are stored to the stack, because the 2353 // outgoing stack slots may alias the incoming argument stack slots, and 2354 // the alias isn't otherwise explicit. This is slightly more conservative 2355 // than necessary, because it means that each store effectively depends 2356 // on every argument instead of just those arguments it would clobber. 2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2358 2359 SmallVector<SDValue, 8> MemOpChains2; 2360 SDValue FIN; 2361 int FI = 0; 2362 // Do not flag preceding copytoreg stuff together with the following stuff. 2363 InFlag = SDValue(); 2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2366 CCValAssign &VA = ArgLocs[i]; 2367 if (VA.isRegLoc()) 2368 continue; 2369 assert(VA.isMemLoc()); 2370 SDValue Arg = OutVals[i]; 2371 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2372 // Create frame index. 2373 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2376 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2377 2378 if (Flags.isByVal()) { 2379 // Copy relative to framepointer. 2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2381 if (StackPtr.getNode() == 0) 2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2383 getPointerTy()); 2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2385 2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2387 ArgChain, 2388 Flags, DAG, dl)); 2389 } else { 2390 // Store relative to framepointer. 2391 MemOpChains2.push_back( 2392 DAG.getStore(ArgChain, dl, Arg, FIN, 2393 MachinePointerInfo::getFixedStack(FI), 2394 false, false, 0)); 2395 } 2396 } 2397 } 2398 2399 if (!MemOpChains2.empty()) 2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2401 &MemOpChains2[0], MemOpChains2.size()); 2402 2403 // Copy arguments to their registers. 2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2406 RegsToPass[i].second, InFlag); 2407 InFlag = Chain.getValue(1); 2408 } 2409 InFlag =SDValue(); 2410 2411 // Store the return address to the appropriate stack slot. 2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2413 FPDiff, dl); 2414 } 2415 2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2418 // In the 64-bit large code model, we have to make all calls 2419 // through a register, since the call instruction's 32-bit 2420 // pc-relative offset may not be large enough to hold the whole 2421 // address. 2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2423 // If the callee is a GlobalAddress node (quite common, every direct call 2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2425 // it. 2426 2427 // We should use extra load for direct calls to dllimported functions in 2428 // non-JIT mode. 2429 const GlobalValue *GV = G->getGlobal(); 2430 if (!GV->hasDLLImportLinkage()) { 2431 unsigned char OpFlags = 0; 2432 bool ExtraLoad = false; 2433 unsigned WrapperKind = ISD::DELETED_NODE; 2434 2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2436 // external symbols most go through the PLT in PIC mode. If the symbol 2437 // has hidden or protected visibility, or if it is static or local, then 2438 // we don't need to use the PLT - we can directly call it. 2439 if (Subtarget->isTargetELF() && 2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2442 OpFlags = X86II::MO_PLT; 2443 } else if (Subtarget->isPICStyleStubAny() && 2444 (GV->isDeclaration() || GV->isWeakForLinker()) && 2445 (!Subtarget->getTargetTriple().isMacOSX() || 2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2447 // PC-relative references to external symbols should go through $stub, 2448 // unless we're building with the leopard linker or later, which 2449 // automatically synthesizes these stubs. 2450 OpFlags = X86II::MO_DARWIN_STUB; 2451 } else if (Subtarget->isPICStyleRIPRel() && 2452 isa<Function>(GV) && 2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2454 // If the function is marked as non-lazy, generate an indirect call 2455 // which loads from the GOT directly. This avoids runtime overhead 2456 // at the cost of eager binding (and one extra byte of encoding). 2457 OpFlags = X86II::MO_GOTPCREL; 2458 WrapperKind = X86ISD::WrapperRIP; 2459 ExtraLoad = true; 2460 } 2461 2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2463 G->getOffset(), OpFlags); 2464 2465 // Add a wrapper if needed. 2466 if (WrapperKind != ISD::DELETED_NODE) 2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2468 // Add extra indirection if needed. 2469 if (ExtraLoad) 2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2471 MachinePointerInfo::getGOT(), 2472 false, false, false, 0); 2473 } 2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2475 unsigned char OpFlags = 0; 2476 2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2478 // external symbols should go through the PLT. 2479 if (Subtarget->isTargetELF() && 2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2481 OpFlags = X86II::MO_PLT; 2482 } else if (Subtarget->isPICStyleStubAny() && 2483 (!Subtarget->getTargetTriple().isMacOSX() || 2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2485 // PC-relative references to external symbols should go through $stub, 2486 // unless we're building with the leopard linker or later, which 2487 // automatically synthesizes these stubs. 2488 OpFlags = X86II::MO_DARWIN_STUB; 2489 } 2490 2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2492 OpFlags); 2493 } 2494 2495 // Returns a chain & a flag for retval copy to use. 2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2497 SmallVector<SDValue, 8> Ops; 2498 2499 if (!IsSibcall && isTailCall) { 2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2501 DAG.getIntPtrConstant(0, true), InFlag); 2502 InFlag = Chain.getValue(1); 2503 } 2504 2505 Ops.push_back(Chain); 2506 Ops.push_back(Callee); 2507 2508 if (isTailCall) 2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2510 2511 // Add argument registers to the end of the list so that they are known live 2512 // into the call. 2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2515 RegsToPass[i].second.getValueType())); 2516 2517 // Add an implicit use GOT pointer in EBX. 2518 if (!isTailCall && Subtarget->isPICStyleGOT()) 2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2520 2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2522 if (Is64Bit && isVarArg && !IsWin64) 2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2524 2525 // Add a register mask operand representing the call-preserved registers. 2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2528 assert(Mask && "Missing call preserved mask for calling convention"); 2529 Ops.push_back(DAG.getRegisterMask(Mask)); 2530 2531 if (InFlag.getNode()) 2532 Ops.push_back(InFlag); 2533 2534 if (isTailCall) { 2535 // We used to do: 2536 //// If this is the first return lowered for this function, add the regs 2537 //// to the liveout set for the function. 2538 // This isn't right, although it's probably harmless on x86; liveouts 2539 // should be computed from returns not tail calls. Consider a void 2540 // function making a tail call to a function returning int. 2541 return DAG.getNode(X86ISD::TC_RETURN, dl, 2542 NodeTys, &Ops[0], Ops.size()); 2543 } 2544 2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2546 InFlag = Chain.getValue(1); 2547 2548 // Create the CALLSEQ_END node. 2549 unsigned NumBytesForCalleeToPush; 2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2551 getTargetMachine().Options.GuaranteedTailCallOpt)) 2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2554 IsStructRet) 2555 // If this is a call to a struct-return function, the callee 2556 // pops the hidden struct pointer, so we have to push it back. 2557 // This is common for Darwin/X86, Linux & Mingw32 targets. 2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2559 NumBytesForCalleeToPush = 4; 2560 else 2561 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2562 2563 // Returns a flag for retval copy to use. 2564 if (!IsSibcall) { 2565 Chain = DAG.getCALLSEQ_END(Chain, 2566 DAG.getIntPtrConstant(NumBytes, true), 2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2568 true), 2569 InFlag); 2570 InFlag = Chain.getValue(1); 2571 } 2572 2573 // Handle result values, copying them out of physregs into vregs that we 2574 // return. 2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2576 Ins, dl, DAG, InVals); 2577} 2578 2579 2580//===----------------------------------------------------------------------===// 2581// Fast Calling Convention (tail call) implementation 2582//===----------------------------------------------------------------------===// 2583 2584// Like std call, callee cleans arguments, convention except that ECX is 2585// reserved for storing the tail called function address. Only 2 registers are 2586// free for argument passing (inreg). Tail call optimization is performed 2587// provided: 2588// * tailcallopt is enabled 2589// * caller/callee are fastcc 2590// On X86_64 architecture with GOT-style position independent code only local 2591// (within module) calls are supported at the moment. 2592// To keep the stack aligned according to platform abi the function 2593// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2594// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2595// If a tail called function callee has more arguments than the caller the 2596// caller needs to make sure that there is room to move the RETADDR to. This is 2597// achieved by reserving an area the size of the argument delta right after the 2598// original REtADDR, but before the saved framepointer or the spilled registers 2599// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2600// stack layout: 2601// arg1 2602// arg2 2603// RETADDR 2604// [ new RETADDR 2605// move area ] 2606// (possible EBP) 2607// ESI 2608// EDI 2609// local1 .. 2610 2611/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2612/// for a 16 byte align requirement. 2613unsigned 2614X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2615 SelectionDAG& DAG) const { 2616 MachineFunction &MF = DAG.getMachineFunction(); 2617 const TargetMachine &TM = MF.getTarget(); 2618 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2619 unsigned StackAlignment = TFI.getStackAlignment(); 2620 uint64_t AlignMask = StackAlignment - 1; 2621 int64_t Offset = StackSize; 2622 uint64_t SlotSize = TD->getPointerSize(); 2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2624 // Number smaller than 12 so just add the difference. 2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2626 } else { 2627 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2628 Offset = ((~AlignMask) & Offset) + StackAlignment + 2629 (StackAlignment-SlotSize); 2630 } 2631 return Offset; 2632} 2633 2634/// MatchingStackOffset - Return true if the given stack call argument is 2635/// already available in the same position (relatively) of the caller's 2636/// incoming argument stack. 2637static 2638bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2640 const X86InstrInfo *TII) { 2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2642 int FI = INT_MAX; 2643 if (Arg.getOpcode() == ISD::CopyFromReg) { 2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2645 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2646 return false; 2647 MachineInstr *Def = MRI->getVRegDef(VR); 2648 if (!Def) 2649 return false; 2650 if (!Flags.isByVal()) { 2651 if (!TII->isLoadFromStackSlot(Def, FI)) 2652 return false; 2653 } else { 2654 unsigned Opcode = Def->getOpcode(); 2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2656 Def->getOperand(1).isFI()) { 2657 FI = Def->getOperand(1).getIndex(); 2658 Bytes = Flags.getByValSize(); 2659 } else 2660 return false; 2661 } 2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2663 if (Flags.isByVal()) 2664 // ByVal argument is passed in as a pointer but it's now being 2665 // dereferenced. e.g. 2666 // define @foo(%struct.X* %A) { 2667 // tail call @bar(%struct.X* byval %A) 2668 // } 2669 return false; 2670 SDValue Ptr = Ld->getBasePtr(); 2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2672 if (!FINode) 2673 return false; 2674 FI = FINode->getIndex(); 2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2677 FI = FINode->getIndex(); 2678 Bytes = Flags.getByValSize(); 2679 } else 2680 return false; 2681 2682 assert(FI != INT_MAX); 2683 if (!MFI->isFixedObjectIndex(FI)) 2684 return false; 2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2686} 2687 2688/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2689/// for tail call optimization. Targets which want to do tail call 2690/// optimization should implement this function. 2691bool 2692X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2693 CallingConv::ID CalleeCC, 2694 bool isVarArg, 2695 bool isCalleeStructRet, 2696 bool isCallerStructRet, 2697 const SmallVectorImpl<ISD::OutputArg> &Outs, 2698 const SmallVectorImpl<SDValue> &OutVals, 2699 const SmallVectorImpl<ISD::InputArg> &Ins, 2700 SelectionDAG& DAG) const { 2701 if (!IsTailCallConvention(CalleeCC) && 2702 CalleeCC != CallingConv::C) 2703 return false; 2704 2705 // If -tailcallopt is specified, make fastcc functions tail-callable. 2706 const MachineFunction &MF = DAG.getMachineFunction(); 2707 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2708 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2709 bool CCMatch = CallerCC == CalleeCC; 2710 2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2712 if (IsTailCallConvention(CalleeCC) && CCMatch) 2713 return true; 2714 return false; 2715 } 2716 2717 // Look for obvious safe cases to perform tail call optimization that do not 2718 // require ABI changes. This is what gcc calls sibcall. 2719 2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2721 // emit a special epilogue. 2722 if (RegInfo->needsStackRealignment(MF)) 2723 return false; 2724 2725 // Also avoid sibcall optimization if either caller or callee uses struct 2726 // return semantics. 2727 if (isCalleeStructRet || isCallerStructRet) 2728 return false; 2729 2730 // An stdcall caller is expected to clean up its arguments; the callee 2731 // isn't going to do that. 2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2733 return false; 2734 2735 // Do not sibcall optimize vararg calls unless all arguments are passed via 2736 // registers. 2737 if (isVarArg && !Outs.empty()) { 2738 2739 // Optimizing for varargs on Win64 is unlikely to be safe without 2740 // additional testing. 2741 if (Subtarget->isTargetWin64()) 2742 return false; 2743 2744 SmallVector<CCValAssign, 16> ArgLocs; 2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2746 getTargetMachine(), ArgLocs, *DAG.getContext()); 2747 2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2750 if (!ArgLocs[i].isRegLoc()) 2751 return false; 2752 } 2753 2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2755 // stack. Therefore, if it's not used by the call it is not safe to optimize 2756 // this into a sibcall. 2757 bool Unused = false; 2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2759 if (!Ins[i].Used) { 2760 Unused = true; 2761 break; 2762 } 2763 } 2764 if (Unused) { 2765 SmallVector<CCValAssign, 16> RVLocs; 2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2767 getTargetMachine(), RVLocs, *DAG.getContext()); 2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2770 CCValAssign &VA = RVLocs[i]; 2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2772 return false; 2773 } 2774 } 2775 2776 // If the calling conventions do not match, then we'd better make sure the 2777 // results are returned in the same way as what the caller expects. 2778 if (!CCMatch) { 2779 SmallVector<CCValAssign, 16> RVLocs1; 2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2781 getTargetMachine(), RVLocs1, *DAG.getContext()); 2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2783 2784 SmallVector<CCValAssign, 16> RVLocs2; 2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2786 getTargetMachine(), RVLocs2, *DAG.getContext()); 2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2788 2789 if (RVLocs1.size() != RVLocs2.size()) 2790 return false; 2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2793 return false; 2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2795 return false; 2796 if (RVLocs1[i].isRegLoc()) { 2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2798 return false; 2799 } else { 2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2801 return false; 2802 } 2803 } 2804 } 2805 2806 // If the callee takes no arguments then go on to check the results of the 2807 // call. 2808 if (!Outs.empty()) { 2809 // Check if stack adjustment is needed. For now, do not do this if any 2810 // argument is passed on the stack. 2811 SmallVector<CCValAssign, 16> ArgLocs; 2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2813 getTargetMachine(), ArgLocs, *DAG.getContext()); 2814 2815 // Allocate shadow area for Win64 2816 if (Subtarget->isTargetWin64()) { 2817 CCInfo.AllocateStack(32, 8); 2818 } 2819 2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2821 if (CCInfo.getNextStackOffset()) { 2822 MachineFunction &MF = DAG.getMachineFunction(); 2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2824 return false; 2825 2826 // Check if the arguments are already laid out in the right way as 2827 // the caller's fixed stack objects. 2828 MachineFrameInfo *MFI = MF.getFrameInfo(); 2829 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2830 const X86InstrInfo *TII = 2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2833 CCValAssign &VA = ArgLocs[i]; 2834 SDValue Arg = OutVals[i]; 2835 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2836 if (VA.getLocInfo() == CCValAssign::Indirect) 2837 return false; 2838 if (!VA.isRegLoc()) { 2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2840 MFI, MRI, TII)) 2841 return false; 2842 } 2843 } 2844 } 2845 2846 // If the tailcall address may be in a register, then make sure it's 2847 // possible to register allocate for it. In 32-bit, the call address can 2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2849 // callee-saved registers are restored. These happen to be the same 2850 // registers used to pass 'inreg' arguments so watch out for those. 2851 if (!Subtarget->is64Bit() && 2852 !isa<GlobalAddressSDNode>(Callee) && 2853 !isa<ExternalSymbolSDNode>(Callee)) { 2854 unsigned NumInRegs = 0; 2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2856 CCValAssign &VA = ArgLocs[i]; 2857 if (!VA.isRegLoc()) 2858 continue; 2859 unsigned Reg = VA.getLocReg(); 2860 switch (Reg) { 2861 default: break; 2862 case X86::EAX: case X86::EDX: case X86::ECX: 2863 if (++NumInRegs == 3) 2864 return false; 2865 break; 2866 } 2867 } 2868 } 2869 } 2870 2871 return true; 2872} 2873 2874FastISel * 2875X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2876 return X86::createFastISel(funcInfo); 2877} 2878 2879 2880//===----------------------------------------------------------------------===// 2881// Other Lowering Hooks 2882//===----------------------------------------------------------------------===// 2883 2884static bool MayFoldLoad(SDValue Op) { 2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2886} 2887 2888static bool MayFoldIntoStore(SDValue Op) { 2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2890} 2891 2892static bool isTargetShuffle(unsigned Opcode) { 2893 switch(Opcode) { 2894 default: return false; 2895 case X86ISD::PSHUFD: 2896 case X86ISD::PSHUFHW: 2897 case X86ISD::PSHUFLW: 2898 case X86ISD::SHUFP: 2899 case X86ISD::PALIGN: 2900 case X86ISD::MOVLHPS: 2901 case X86ISD::MOVLHPD: 2902 case X86ISD::MOVHLPS: 2903 case X86ISD::MOVLPS: 2904 case X86ISD::MOVLPD: 2905 case X86ISD::MOVSHDUP: 2906 case X86ISD::MOVSLDUP: 2907 case X86ISD::MOVDDUP: 2908 case X86ISD::MOVSS: 2909 case X86ISD::MOVSD: 2910 case X86ISD::UNPCKL: 2911 case X86ISD::UNPCKH: 2912 case X86ISD::VPERMILP: 2913 case X86ISD::VPERM2X128: 2914 return true; 2915 } 2916} 2917 2918static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2919 SDValue V1, SelectionDAG &DAG) { 2920 switch(Opc) { 2921 default: llvm_unreachable("Unknown x86 shuffle node"); 2922 case X86ISD::MOVSHDUP: 2923 case X86ISD::MOVSLDUP: 2924 case X86ISD::MOVDDUP: 2925 return DAG.getNode(Opc, dl, VT, V1); 2926 } 2927} 2928 2929static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2930 SDValue V1, unsigned TargetMask, 2931 SelectionDAG &DAG) { 2932 switch(Opc) { 2933 default: llvm_unreachable("Unknown x86 shuffle node"); 2934 case X86ISD::PSHUFD: 2935 case X86ISD::PSHUFHW: 2936 case X86ISD::PSHUFLW: 2937 case X86ISD::VPERMILP: 2938 case X86ISD::VPERMI: 2939 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2940 } 2941} 2942 2943static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2944 SDValue V1, SDValue V2, unsigned TargetMask, 2945 SelectionDAG &DAG) { 2946 switch(Opc) { 2947 default: llvm_unreachable("Unknown x86 shuffle node"); 2948 case X86ISD::PALIGN: 2949 case X86ISD::SHUFP: 2950 case X86ISD::VPERM2X128: 2951 return DAG.getNode(Opc, dl, VT, V1, V2, 2952 DAG.getConstant(TargetMask, MVT::i8)); 2953 } 2954} 2955 2956static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2957 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2958 switch(Opc) { 2959 default: llvm_unreachable("Unknown x86 shuffle node"); 2960 case X86ISD::MOVLHPS: 2961 case X86ISD::MOVLHPD: 2962 case X86ISD::MOVHLPS: 2963 case X86ISD::MOVLPS: 2964 case X86ISD::MOVLPD: 2965 case X86ISD::MOVSS: 2966 case X86ISD::MOVSD: 2967 case X86ISD::UNPCKL: 2968 case X86ISD::UNPCKH: 2969 return DAG.getNode(Opc, dl, VT, V1, V2); 2970 } 2971} 2972 2973SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2974 MachineFunction &MF = DAG.getMachineFunction(); 2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2976 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2977 2978 if (ReturnAddrIndex == 0) { 2979 // Set up a frame object for the return address. 2980 uint64_t SlotSize = TD->getPointerSize(); 2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2982 false); 2983 FuncInfo->setRAIndex(ReturnAddrIndex); 2984 } 2985 2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2987} 2988 2989 2990bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2991 bool hasSymbolicDisplacement) { 2992 // Offset should fit into 32 bit immediate field. 2993 if (!isInt<32>(Offset)) 2994 return false; 2995 2996 // If we don't have a symbolic displacement - we don't have any extra 2997 // restrictions. 2998 if (!hasSymbolicDisplacement) 2999 return true; 3000 3001 // FIXME: Some tweaks might be needed for medium code model. 3002 if (M != CodeModel::Small && M != CodeModel::Kernel) 3003 return false; 3004 3005 // For small code model we assume that latest object is 16MB before end of 31 3006 // bits boundary. We may also accept pretty large negative constants knowing 3007 // that all objects are in the positive half of address space. 3008 if (M == CodeModel::Small && Offset < 16*1024*1024) 3009 return true; 3010 3011 // For kernel code model we know that all object resist in the negative half 3012 // of 32bits address space. We may not accept negative offsets, since they may 3013 // be just off and we may accept pretty large positive ones. 3014 if (M == CodeModel::Kernel && Offset > 0) 3015 return true; 3016 3017 return false; 3018} 3019 3020/// isCalleePop - Determines whether the callee is required to pop its 3021/// own arguments. Callee pop is necessary to support tail calls. 3022bool X86::isCalleePop(CallingConv::ID CallingConv, 3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3024 if (IsVarArg) 3025 return false; 3026 3027 switch (CallingConv) { 3028 default: 3029 return false; 3030 case CallingConv::X86_StdCall: 3031 return !is64Bit; 3032 case CallingConv::X86_FastCall: 3033 return !is64Bit; 3034 case CallingConv::X86_ThisCall: 3035 return !is64Bit; 3036 case CallingConv::Fast: 3037 return TailCallOpt; 3038 case CallingConv::GHC: 3039 return TailCallOpt; 3040 } 3041} 3042 3043/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3044/// specific condition code, returning the condition code and the LHS/RHS of the 3045/// comparison to make. 3046static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3048 if (!isFP) { 3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3051 // X > -1 -> X == 0, jump !sign. 3052 RHS = DAG.getConstant(0, RHS.getValueType()); 3053 return X86::COND_NS; 3054 } 3055 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3056 // X < 0 -> X == 0, jump on sign. 3057 return X86::COND_S; 3058 } 3059 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3060 // X < 1 -> X <= 0 3061 RHS = DAG.getConstant(0, RHS.getValueType()); 3062 return X86::COND_LE; 3063 } 3064 } 3065 3066 switch (SetCCOpcode) { 3067 default: llvm_unreachable("Invalid integer condition!"); 3068 case ISD::SETEQ: return X86::COND_E; 3069 case ISD::SETGT: return X86::COND_G; 3070 case ISD::SETGE: return X86::COND_GE; 3071 case ISD::SETLT: return X86::COND_L; 3072 case ISD::SETLE: return X86::COND_LE; 3073 case ISD::SETNE: return X86::COND_NE; 3074 case ISD::SETULT: return X86::COND_B; 3075 case ISD::SETUGT: return X86::COND_A; 3076 case ISD::SETULE: return X86::COND_BE; 3077 case ISD::SETUGE: return X86::COND_AE; 3078 } 3079 } 3080 3081 // First determine if it is required or is profitable to flip the operands. 3082 3083 // If LHS is a foldable load, but RHS is not, flip the condition. 3084 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3085 !ISD::isNON_EXTLoad(RHS.getNode())) { 3086 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3087 std::swap(LHS, RHS); 3088 } 3089 3090 switch (SetCCOpcode) { 3091 default: break; 3092 case ISD::SETOLT: 3093 case ISD::SETOLE: 3094 case ISD::SETUGT: 3095 case ISD::SETUGE: 3096 std::swap(LHS, RHS); 3097 break; 3098 } 3099 3100 // On a floating point condition, the flags are set as follows: 3101 // ZF PF CF op 3102 // 0 | 0 | 0 | X > Y 3103 // 0 | 0 | 1 | X < Y 3104 // 1 | 0 | 0 | X == Y 3105 // 1 | 1 | 1 | unordered 3106 switch (SetCCOpcode) { 3107 default: llvm_unreachable("Condcode should be pre-legalized away"); 3108 case ISD::SETUEQ: 3109 case ISD::SETEQ: return X86::COND_E; 3110 case ISD::SETOLT: // flipped 3111 case ISD::SETOGT: 3112 case ISD::SETGT: return X86::COND_A; 3113 case ISD::SETOLE: // flipped 3114 case ISD::SETOGE: 3115 case ISD::SETGE: return X86::COND_AE; 3116 case ISD::SETUGT: // flipped 3117 case ISD::SETULT: 3118 case ISD::SETLT: return X86::COND_B; 3119 case ISD::SETUGE: // flipped 3120 case ISD::SETULE: 3121 case ISD::SETLE: return X86::COND_BE; 3122 case ISD::SETONE: 3123 case ISD::SETNE: return X86::COND_NE; 3124 case ISD::SETUO: return X86::COND_P; 3125 case ISD::SETO: return X86::COND_NP; 3126 case ISD::SETOEQ: 3127 case ISD::SETUNE: return X86::COND_INVALID; 3128 } 3129} 3130 3131/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3132/// code. Current x86 isa includes the following FP cmov instructions: 3133/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3134static bool hasFPCMov(unsigned X86CC) { 3135 switch (X86CC) { 3136 default: 3137 return false; 3138 case X86::COND_B: 3139 case X86::COND_BE: 3140 case X86::COND_E: 3141 case X86::COND_P: 3142 case X86::COND_A: 3143 case X86::COND_AE: 3144 case X86::COND_NE: 3145 case X86::COND_NP: 3146 return true; 3147 } 3148} 3149 3150/// isFPImmLegal - Returns true if the target can instruction select the 3151/// specified FP immediate natively. If false, the legalizer will 3152/// materialize the FP immediate as a load from a constant pool. 3153bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3154 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3155 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3156 return true; 3157 } 3158 return false; 3159} 3160 3161/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3162/// the specified range (L, H]. 3163static bool isUndefOrInRange(int Val, int Low, int Hi) { 3164 return (Val < 0) || (Val >= Low && Val < Hi); 3165} 3166 3167/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3168/// specified value. 3169static bool isUndefOrEqual(int Val, int CmpVal) { 3170 if (Val < 0 || Val == CmpVal) 3171 return true; 3172 return false; 3173} 3174 3175/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3176/// from position Pos and ending in Pos+Size, falls within the specified 3177/// sequential range (L, L+Pos]. or is undef. 3178static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3179 int Pos, int Size, int Low) { 3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3181 if (!isUndefOrEqual(Mask[i], Low)) 3182 return false; 3183 return true; 3184} 3185 3186/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3187/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3188/// the second operand. 3189static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3192 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3193 return (Mask[0] < 2 && Mask[1] < 2); 3194 return false; 3195} 3196 3197/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3198/// is suitable for input to PSHUFHW. 3199static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3200 if (VT != MVT::v8i16) 3201 return false; 3202 3203 // Lower quadword copied in order or undef. 3204 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3205 return false; 3206 3207 // Upper quadword shuffled. 3208 for (unsigned i = 4; i != 8; ++i) 3209 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3210 return false; 3211 3212 return true; 3213} 3214 3215/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3216/// is suitable for input to PSHUFLW. 3217static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3218 if (VT != MVT::v8i16) 3219 return false; 3220 3221 // Upper quadword copied in order. 3222 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3223 return false; 3224 3225 // Lower quadword shuffled. 3226 for (unsigned i = 0; i != 4; ++i) 3227 if (Mask[i] >= 4) 3228 return false; 3229 3230 return true; 3231} 3232 3233/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3234/// is suitable for input to PALIGNR. 3235static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3236 const X86Subtarget *Subtarget) { 3237 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3238 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3239 return false; 3240 3241 unsigned NumElts = VT.getVectorNumElements(); 3242 unsigned NumLanes = VT.getSizeInBits()/128; 3243 unsigned NumLaneElts = NumElts/NumLanes; 3244 3245 // Do not handle 64-bit element shuffles with palignr. 3246 if (NumLaneElts == 2) 3247 return false; 3248 3249 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3250 unsigned i; 3251 for (i = 0; i != NumLaneElts; ++i) { 3252 if (Mask[i+l] >= 0) 3253 break; 3254 } 3255 3256 // Lane is all undef, go to next lane 3257 if (i == NumLaneElts) 3258 continue; 3259 3260 int Start = Mask[i+l]; 3261 3262 // Make sure its in this lane in one of the sources 3263 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3264 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3265 return false; 3266 3267 // If not lane 0, then we must match lane 0 3268 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3269 return false; 3270 3271 // Correct second source to be contiguous with first source 3272 if (Start >= (int)NumElts) 3273 Start -= NumElts - NumLaneElts; 3274 3275 // Make sure we're shifting in the right direction. 3276 if (Start <= (int)(i+l)) 3277 return false; 3278 3279 Start -= i; 3280 3281 // Check the rest of the elements to see if they are consecutive. 3282 for (++i; i != NumLaneElts; ++i) { 3283 int Idx = Mask[i+l]; 3284 3285 // Make sure its in this lane 3286 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3287 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3288 return false; 3289 3290 // If not lane 0, then we must match lane 0 3291 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3292 return false; 3293 3294 if (Idx >= (int)NumElts) 3295 Idx -= NumElts - NumLaneElts; 3296 3297 if (!isUndefOrEqual(Idx, Start+i)) 3298 return false; 3299 3300 } 3301 } 3302 3303 return true; 3304} 3305 3306/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3307/// the two vector operands have swapped position. 3308static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3309 unsigned NumElems) { 3310 for (unsigned i = 0; i != NumElems; ++i) { 3311 int idx = Mask[i]; 3312 if (idx < 0) 3313 continue; 3314 else if (idx < (int)NumElems) 3315 Mask[i] = idx + NumElems; 3316 else 3317 Mask[i] = idx - NumElems; 3318 } 3319} 3320 3321/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3322/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3323/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3324/// reverse of what x86 shuffles want. 3325static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3326 bool Commuted = false) { 3327 if (!HasAVX && VT.getSizeInBits() == 256) 3328 return false; 3329 3330 unsigned NumElems = VT.getVectorNumElements(); 3331 unsigned NumLanes = VT.getSizeInBits()/128; 3332 unsigned NumLaneElems = NumElems/NumLanes; 3333 3334 if (NumLaneElems != 2 && NumLaneElems != 4) 3335 return false; 3336 3337 // VSHUFPSY divides the resulting vector into 4 chunks. 3338 // The sources are also splitted into 4 chunks, and each destination 3339 // chunk must come from a different source chunk. 3340 // 3341 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3342 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3343 // 3344 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3345 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3346 // 3347 // VSHUFPDY divides the resulting vector into 4 chunks. 3348 // The sources are also splitted into 4 chunks, and each destination 3349 // chunk must come from a different source chunk. 3350 // 3351 // SRC1 => X3 X2 X1 X0 3352 // SRC2 => Y3 Y2 Y1 Y0 3353 // 3354 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3355 // 3356 unsigned HalfLaneElems = NumLaneElems/2; 3357 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3358 for (unsigned i = 0; i != NumLaneElems; ++i) { 3359 int Idx = Mask[i+l]; 3360 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3361 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3362 return false; 3363 // For VSHUFPSY, the mask of the second half must be the same as the 3364 // first but with the appropriate offsets. This works in the same way as 3365 // VPERMILPS works with masks. 3366 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3367 continue; 3368 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3369 return false; 3370 } 3371 } 3372 3373 return true; 3374} 3375 3376/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3377/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3378static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) { 3379 unsigned NumElems = VT.getVectorNumElements(); 3380 3381 if (VT.getSizeInBits() != 128) 3382 return false; 3383 3384 if (NumElems != 4) 3385 return false; 3386 3387 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3388 return isUndefOrEqual(Mask[0], 6) && 3389 isUndefOrEqual(Mask[1], 7) && 3390 isUndefOrEqual(Mask[2], 2) && 3391 isUndefOrEqual(Mask[3], 3); 3392} 3393 3394/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3395/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3396/// <2, 3, 2, 3> 3397static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) { 3398 unsigned NumElems = VT.getVectorNumElements(); 3399 3400 if (VT.getSizeInBits() != 128) 3401 return false; 3402 3403 if (NumElems != 4) 3404 return false; 3405 3406 return isUndefOrEqual(Mask[0], 2) && 3407 isUndefOrEqual(Mask[1], 3) && 3408 isUndefOrEqual(Mask[2], 2) && 3409 isUndefOrEqual(Mask[3], 3); 3410} 3411 3412/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3413/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3414static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) { 3415 if (VT.getSizeInBits() != 128) 3416 return false; 3417 3418 unsigned NumElems = VT.getVectorNumElements(); 3419 3420 if (NumElems != 2 && NumElems != 4) 3421 return false; 3422 3423 for (unsigned i = 0; i != NumElems/2; ++i) 3424 if (!isUndefOrEqual(Mask[i], i + NumElems)) 3425 return false; 3426 3427 for (unsigned i = NumElems/2; i != NumElems; ++i) 3428 if (!isUndefOrEqual(Mask[i], i)) 3429 return false; 3430 3431 return true; 3432} 3433 3434/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3435/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3436static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) { 3437 unsigned NumElems = VT.getVectorNumElements(); 3438 3439 if ((NumElems != 2 && NumElems != 4) 3440 || VT.getSizeInBits() > 128) 3441 return false; 3442 3443 for (unsigned i = 0; i != NumElems/2; ++i) 3444 if (!isUndefOrEqual(Mask[i], i)) 3445 return false; 3446 3447 for (unsigned i = 0; i != NumElems/2; ++i) 3448 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems)) 3449 return false; 3450 3451 return true; 3452} 3453 3454/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3455/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3456static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3457 bool HasAVX2, bool V2IsSplat = false) { 3458 unsigned NumElts = VT.getVectorNumElements(); 3459 3460 assert((VT.is128BitVector() || VT.is256BitVector()) && 3461 "Unsupported vector type for unpckh"); 3462 3463 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3464 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3465 return false; 3466 3467 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3468 // independently on 128-bit lanes. 3469 unsigned NumLanes = VT.getSizeInBits()/128; 3470 unsigned NumLaneElts = NumElts/NumLanes; 3471 3472 for (unsigned l = 0; l != NumLanes; ++l) { 3473 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3474 i != (l+1)*NumLaneElts; 3475 i += 2, ++j) { 3476 int BitI = Mask[i]; 3477 int BitI1 = Mask[i+1]; 3478 if (!isUndefOrEqual(BitI, j)) 3479 return false; 3480 if (V2IsSplat) { 3481 if (!isUndefOrEqual(BitI1, NumElts)) 3482 return false; 3483 } else { 3484 if (!isUndefOrEqual(BitI1, j + NumElts)) 3485 return false; 3486 } 3487 } 3488 } 3489 3490 return true; 3491} 3492 3493/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3494/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3495static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3496 bool HasAVX2, bool V2IsSplat = false) { 3497 unsigned NumElts = VT.getVectorNumElements(); 3498 3499 assert((VT.is128BitVector() || VT.is256BitVector()) && 3500 "Unsupported vector type for unpckh"); 3501 3502 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3503 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3504 return false; 3505 3506 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3507 // independently on 128-bit lanes. 3508 unsigned NumLanes = VT.getSizeInBits()/128; 3509 unsigned NumLaneElts = NumElts/NumLanes; 3510 3511 for (unsigned l = 0; l != NumLanes; ++l) { 3512 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3513 i != (l+1)*NumLaneElts; i += 2, ++j) { 3514 int BitI = Mask[i]; 3515 int BitI1 = Mask[i+1]; 3516 if (!isUndefOrEqual(BitI, j)) 3517 return false; 3518 if (V2IsSplat) { 3519 if (isUndefOrEqual(BitI1, NumElts)) 3520 return false; 3521 } else { 3522 if (!isUndefOrEqual(BitI1, j+NumElts)) 3523 return false; 3524 } 3525 } 3526 } 3527 return true; 3528} 3529 3530/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3531/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3532/// <0, 0, 1, 1> 3533static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3534 bool HasAVX2) { 3535 unsigned NumElts = VT.getVectorNumElements(); 3536 3537 assert((VT.is128BitVector() || VT.is256BitVector()) && 3538 "Unsupported vector type for unpckh"); 3539 3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3541 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3542 return false; 3543 3544 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3545 // FIXME: Need a better way to get rid of this, there's no latency difference 3546 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3547 // the former later. We should also remove the "_undef" special mask. 3548 if (NumElts == 4 && VT.getSizeInBits() == 256) 3549 return false; 3550 3551 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3552 // independently on 128-bit lanes. 3553 unsigned NumLanes = VT.getSizeInBits()/128; 3554 unsigned NumLaneElts = NumElts/NumLanes; 3555 3556 for (unsigned l = 0; l != NumLanes; ++l) { 3557 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3558 i != (l+1)*NumLaneElts; 3559 i += 2, ++j) { 3560 int BitI = Mask[i]; 3561 int BitI1 = Mask[i+1]; 3562 3563 if (!isUndefOrEqual(BitI, j)) 3564 return false; 3565 if (!isUndefOrEqual(BitI1, j)) 3566 return false; 3567 } 3568 } 3569 3570 return true; 3571} 3572 3573/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3574/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3575/// <2, 2, 3, 3> 3576static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3577 unsigned NumElts = VT.getVectorNumElements(); 3578 3579 assert((VT.is128BitVector() || VT.is256BitVector()) && 3580 "Unsupported vector type for unpckh"); 3581 3582 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3583 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3584 return false; 3585 3586 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3587 // independently on 128-bit lanes. 3588 unsigned NumLanes = VT.getSizeInBits()/128; 3589 unsigned NumLaneElts = NumElts/NumLanes; 3590 3591 for (unsigned l = 0; l != NumLanes; ++l) { 3592 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3593 i != (l+1)*NumLaneElts; i += 2, ++j) { 3594 int BitI = Mask[i]; 3595 int BitI1 = Mask[i+1]; 3596 if (!isUndefOrEqual(BitI, j)) 3597 return false; 3598 if (!isUndefOrEqual(BitI1, j)) 3599 return false; 3600 } 3601 } 3602 return true; 3603} 3604 3605/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3606/// specifies a shuffle of elements that is suitable for input to MOVSS, 3607/// MOVSD, and MOVD, i.e. setting the lowest element. 3608static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3609 if (VT.getVectorElementType().getSizeInBits() < 32) 3610 return false; 3611 if (VT.getSizeInBits() == 256) 3612 return false; 3613 3614 unsigned NumElts = VT.getVectorNumElements(); 3615 3616 if (!isUndefOrEqual(Mask[0], NumElts)) 3617 return false; 3618 3619 for (unsigned i = 1; i != NumElts; ++i) 3620 if (!isUndefOrEqual(Mask[i], i)) 3621 return false; 3622 3623 return true; 3624} 3625 3626/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3627/// as permutations between 128-bit chunks or halves. As an example: this 3628/// shuffle bellow: 3629/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3630/// The first half comes from the second half of V1 and the second half from the 3631/// the second half of V2. 3632static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3633 if (!HasAVX || VT.getSizeInBits() != 256) 3634 return false; 3635 3636 // The shuffle result is divided into half A and half B. In total the two 3637 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3638 // B must come from C, D, E or F. 3639 unsigned HalfSize = VT.getVectorNumElements()/2; 3640 bool MatchA = false, MatchB = false; 3641 3642 // Check if A comes from one of C, D, E, F. 3643 for (unsigned Half = 0; Half != 4; ++Half) { 3644 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3645 MatchA = true; 3646 break; 3647 } 3648 } 3649 3650 // Check if B comes from one of C, D, E, F. 3651 for (unsigned Half = 0; Half != 4; ++Half) { 3652 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3653 MatchB = true; 3654 break; 3655 } 3656 } 3657 3658 return MatchA && MatchB; 3659} 3660 3661/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3662/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3663static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3664 EVT VT = SVOp->getValueType(0); 3665 3666 unsigned HalfSize = VT.getVectorNumElements()/2; 3667 3668 unsigned FstHalf = 0, SndHalf = 0; 3669 for (unsigned i = 0; i < HalfSize; ++i) { 3670 if (SVOp->getMaskElt(i) > 0) { 3671 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3672 break; 3673 } 3674 } 3675 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3676 if (SVOp->getMaskElt(i) > 0) { 3677 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3678 break; 3679 } 3680 } 3681 3682 return (FstHalf | (SndHalf << 4)); 3683} 3684 3685/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3686/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3687/// Note that VPERMIL mask matching is different depending whether theunderlying 3688/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3689/// to the same elements of the low, but to the higher half of the source. 3690/// In VPERMILPD the two lanes could be shuffled independently of each other 3691/// with the same restriction that lanes can't be crossed. Also handles PSHUFDY. 3692static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3693 if (!HasAVX) 3694 return false; 3695 3696 unsigned NumElts = VT.getVectorNumElements(); 3697 // Only match 256-bit with 32/64-bit types 3698 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3699 return false; 3700 3701 unsigned NumLanes = VT.getSizeInBits()/128; 3702 unsigned LaneSize = NumElts/NumLanes; 3703 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3704 for (unsigned i = 0; i != LaneSize; ++i) { 3705 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3706 return false; 3707 if (NumElts != 8 || l == 0) 3708 continue; 3709 // VPERMILPS handling 3710 if (Mask[i] < 0) 3711 continue; 3712 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3713 return false; 3714 } 3715 } 3716 3717 return true; 3718} 3719 3720/// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse 3721/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3722/// element of vector 2 and the other elements to come from vector 1 in order. 3723static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3724 bool V2IsSplat = false, bool V2IsUndef = false) { 3725 unsigned NumOps = VT.getVectorNumElements(); 3726 if (VT.getSizeInBits() == 256) 3727 return false; 3728 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3729 return false; 3730 3731 if (!isUndefOrEqual(Mask[0], 0)) 3732 return false; 3733 3734 for (unsigned i = 1; i != NumOps; ++i) 3735 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3736 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3737 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3738 return false; 3739 3740 return true; 3741} 3742 3743/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3744/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3745/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3746static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT, 3747 const X86Subtarget *Subtarget) { 3748 if (!Subtarget->hasSSE3()) 3749 return false; 3750 3751 unsigned NumElems = VT.getVectorNumElements(); 3752 3753 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3754 (VT.getSizeInBits() == 256 && NumElems != 8)) 3755 return false; 3756 3757 // "i+1" is the value the indexed mask element must have 3758 for (unsigned i = 0; i != NumElems; i += 2) 3759 if (!isUndefOrEqual(Mask[i], i+1) || 3760 !isUndefOrEqual(Mask[i+1], i+1)) 3761 return false; 3762 3763 return true; 3764} 3765 3766/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3767/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3768/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3769static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT, 3770 const X86Subtarget *Subtarget) { 3771 if (!Subtarget->hasSSE3()) 3772 return false; 3773 3774 unsigned NumElems = VT.getVectorNumElements(); 3775 3776 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3777 (VT.getSizeInBits() == 256 && NumElems != 8)) 3778 return false; 3779 3780 // "i" is the value the indexed mask element must have 3781 for (unsigned i = 0; i != NumElems; i += 2) 3782 if (!isUndefOrEqual(Mask[i], i) || 3783 !isUndefOrEqual(Mask[i+1], i)) 3784 return false; 3785 3786 return true; 3787} 3788 3789/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3790/// specifies a shuffle of elements that is suitable for input to 256-bit 3791/// version of MOVDDUP. 3792static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3793 unsigned NumElts = VT.getVectorNumElements(); 3794 3795 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3796 return false; 3797 3798 for (unsigned i = 0; i != NumElts/2; ++i) 3799 if (!isUndefOrEqual(Mask[i], 0)) 3800 return false; 3801 for (unsigned i = NumElts/2; i != NumElts; ++i) 3802 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3803 return false; 3804 return true; 3805} 3806 3807/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3808/// specifies a shuffle of elements that is suitable for input to 128-bit 3809/// version of MOVDDUP. 3810static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) { 3811 if (VT.getSizeInBits() != 128) 3812 return false; 3813 3814 unsigned e = VT.getVectorNumElements() / 2; 3815 for (unsigned i = 0; i != e; ++i) 3816 if (!isUndefOrEqual(Mask[i], i)) 3817 return false; 3818 for (unsigned i = 0; i != e; ++i) 3819 if (!isUndefOrEqual(Mask[e+i], i)) 3820 return false; 3821 return true; 3822} 3823 3824/// isVEXTRACTF128Index - Return true if the specified 3825/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3826/// suitable for input to VEXTRACTF128. 3827bool X86::isVEXTRACTF128Index(SDNode *N) { 3828 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3829 return false; 3830 3831 // The index should be aligned on a 128-bit boundary. 3832 uint64_t Index = 3833 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3834 3835 unsigned VL = N->getValueType(0).getVectorNumElements(); 3836 unsigned VBits = N->getValueType(0).getSizeInBits(); 3837 unsigned ElSize = VBits / VL; 3838 bool Result = (Index * ElSize) % 128 == 0; 3839 3840 return Result; 3841} 3842 3843/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3844/// operand specifies a subvector insert that is suitable for input to 3845/// VINSERTF128. 3846bool X86::isVINSERTF128Index(SDNode *N) { 3847 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3848 return false; 3849 3850 // The index should be aligned on a 128-bit boundary. 3851 uint64_t Index = 3852 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3853 3854 unsigned VL = N->getValueType(0).getVectorNumElements(); 3855 unsigned VBits = N->getValueType(0).getSizeInBits(); 3856 unsigned ElSize = VBits / VL; 3857 bool Result = (Index * ElSize) % 128 == 0; 3858 3859 return Result; 3860} 3861 3862/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3863/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3864/// Handles 128-bit and 256-bit. 3865static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3866 EVT VT = N->getValueType(0); 3867 3868 assert((VT.is128BitVector() || VT.is256BitVector()) && 3869 "Unsupported vector type for PSHUF/SHUFP"); 3870 3871 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3872 // independently on 128-bit lanes. 3873 unsigned NumElts = VT.getVectorNumElements(); 3874 unsigned NumLanes = VT.getSizeInBits()/128; 3875 unsigned NumLaneElts = NumElts/NumLanes; 3876 3877 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3878 "Only supports 2 or 4 elements per lane"); 3879 3880 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3881 unsigned Mask = 0; 3882 for (unsigned i = 0; i != NumElts; ++i) { 3883 int Elt = N->getMaskElt(i); 3884 if (Elt < 0) continue; 3885 Elt %= NumLaneElts; 3886 unsigned ShAmt = i << Shift; 3887 if (ShAmt >= 8) ShAmt -= 8; 3888 Mask |= Elt << ShAmt; 3889 } 3890 3891 return Mask; 3892} 3893 3894/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3895/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3896static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) { 3897 unsigned Mask = 0; 3898 // 8 nodes, but we only care about the last 4. 3899 for (unsigned i = 7; i >= 4; --i) { 3900 int Val = N->getMaskElt(i); 3901 if (Val >= 0) 3902 Mask |= (Val - 4); 3903 if (i != 4) 3904 Mask <<= 2; 3905 } 3906 return Mask; 3907} 3908 3909/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3910/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3911static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) { 3912 unsigned Mask = 0; 3913 // 8 nodes, but we only care about the first 4. 3914 for (int i = 3; i >= 0; --i) { 3915 int Val = N->getMaskElt(i); 3916 if (Val >= 0) 3917 Mask |= Val; 3918 if (i != 0) 3919 Mask <<= 2; 3920 } 3921 return Mask; 3922} 3923 3924/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3925/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3926static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 3927 EVT VT = SVOp->getValueType(0); 3928 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 3929 3930 unsigned NumElts = VT.getVectorNumElements(); 3931 unsigned NumLanes = VT.getSizeInBits()/128; 3932 unsigned NumLaneElts = NumElts/NumLanes; 3933 3934 int Val = 0; 3935 unsigned i; 3936 for (i = 0; i != NumElts; ++i) { 3937 Val = SVOp->getMaskElt(i); 3938 if (Val >= 0) 3939 break; 3940 } 3941 if (Val >= (int)NumElts) 3942 Val -= NumElts - NumLaneElts; 3943 3944 assert(Val - i > 0 && "PALIGNR imm should be positive"); 3945 return (Val - i) * EltSize; 3946} 3947 3948/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 3949/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 3950/// instructions. 3951unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 3952 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3953 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 3954 3955 uint64_t Index = 3956 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3957 3958 EVT VecVT = N->getOperand(0).getValueType(); 3959 EVT ElVT = VecVT.getVectorElementType(); 3960 3961 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3962 return Index / NumElemsPerChunk; 3963} 3964 3965/// getInsertVINSERTF128Immediate - Return the appropriate immediate 3966/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 3967/// instructions. 3968unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 3969 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3970 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 3971 3972 uint64_t Index = 3973 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3974 3975 EVT VecVT = N->getValueType(0); 3976 EVT ElVT = VecVT.getVectorElementType(); 3977 3978 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 3979 return Index / NumElemsPerChunk; 3980} 3981 3982/// getShuffleCLImmediate - Return the appropriate immediate to shuffle 3983/// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions. 3984/// Handles 256-bit. 3985static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) { 3986 EVT VT = N->getValueType(0); 3987 3988 unsigned NumElts = VT.getVectorNumElements(); 3989 3990 assert((VT.is256BitVector() && NumElts == 4) && 3991 "Unsupported vector type for VPERMQ/VPERMPD"); 3992 3993 unsigned Mask = 0; 3994 for (unsigned i = 0; i != NumElts; ++i) { 3995 int Elt = N->getMaskElt(i); 3996 if (Elt < 0) 3997 continue; 3998 Mask |= Elt << (i*2); 3999 } 4000 4001 return Mask; 4002} 4003/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4004/// constant +0.0. 4005bool X86::isZeroNode(SDValue Elt) { 4006 return ((isa<ConstantSDNode>(Elt) && 4007 cast<ConstantSDNode>(Elt)->isNullValue()) || 4008 (isa<ConstantFPSDNode>(Elt) && 4009 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4010} 4011 4012/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4013/// their permute mask. 4014static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4015 SelectionDAG &DAG) { 4016 EVT VT = SVOp->getValueType(0); 4017 unsigned NumElems = VT.getVectorNumElements(); 4018 SmallVector<int, 8> MaskVec; 4019 4020 for (unsigned i = 0; i != NumElems; ++i) { 4021 int idx = SVOp->getMaskElt(i); 4022 if (idx < 0) 4023 MaskVec.push_back(idx); 4024 else if (idx < (int)NumElems) 4025 MaskVec.push_back(idx + NumElems); 4026 else 4027 MaskVec.push_back(idx - NumElems); 4028 } 4029 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4030 SVOp->getOperand(0), &MaskVec[0]); 4031} 4032 4033/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4034/// match movhlps. The lower half elements should come from upper half of 4035/// V1 (and in order), and the upper half elements should come from the upper 4036/// half of V2 (and in order). 4037static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) { 4038 if (VT.getSizeInBits() != 128) 4039 return false; 4040 if (VT.getVectorNumElements() != 4) 4041 return false; 4042 for (unsigned i = 0, e = 2; i != e; ++i) 4043 if (!isUndefOrEqual(Mask[i], i+2)) 4044 return false; 4045 for (unsigned i = 2; i != 4; ++i) 4046 if (!isUndefOrEqual(Mask[i], i+4)) 4047 return false; 4048 return true; 4049} 4050 4051/// isScalarLoadToVector - Returns true if the node is a scalar load that 4052/// is promoted to a vector. It also returns the LoadSDNode by reference if 4053/// required. 4054static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4055 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4056 return false; 4057 N = N->getOperand(0).getNode(); 4058 if (!ISD::isNON_EXTLoad(N)) 4059 return false; 4060 if (LD) 4061 *LD = cast<LoadSDNode>(N); 4062 return true; 4063} 4064 4065// Test whether the given value is a vector value which will be legalized 4066// into a load. 4067static bool WillBeConstantPoolLoad(SDNode *N) { 4068 if (N->getOpcode() != ISD::BUILD_VECTOR) 4069 return false; 4070 4071 // Check for any non-constant elements. 4072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4073 switch (N->getOperand(i).getNode()->getOpcode()) { 4074 case ISD::UNDEF: 4075 case ISD::ConstantFP: 4076 case ISD::Constant: 4077 break; 4078 default: 4079 return false; 4080 } 4081 4082 // Vectors of all-zeros and all-ones are materialized with special 4083 // instructions rather than being loaded. 4084 return !ISD::isBuildVectorAllZeros(N) && 4085 !ISD::isBuildVectorAllOnes(N); 4086} 4087 4088/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4089/// match movlp{s|d}. The lower half elements should come from lower half of 4090/// V1 (and in order), and the upper half elements should come from the upper 4091/// half of V2 (and in order). And since V1 will become the source of the 4092/// MOVLP, it must be either a vector load or a scalar load to vector. 4093static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4094 ArrayRef<int> Mask, EVT VT) { 4095 if (VT.getSizeInBits() != 128) 4096 return false; 4097 4098 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4099 return false; 4100 // Is V2 is a vector load, don't do this transformation. We will try to use 4101 // load folding shufps op. 4102 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4103 return false; 4104 4105 unsigned NumElems = VT.getVectorNumElements(); 4106 4107 if (NumElems != 2 && NumElems != 4) 4108 return false; 4109 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4110 if (!isUndefOrEqual(Mask[i], i)) 4111 return false; 4112 for (unsigned i = NumElems/2; i != NumElems; ++i) 4113 if (!isUndefOrEqual(Mask[i], i+NumElems)) 4114 return false; 4115 return true; 4116} 4117 4118/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4119/// all the same. 4120static bool isSplatVector(SDNode *N) { 4121 if (N->getOpcode() != ISD::BUILD_VECTOR) 4122 return false; 4123 4124 SDValue SplatValue = N->getOperand(0); 4125 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4126 if (N->getOperand(i) != SplatValue) 4127 return false; 4128 return true; 4129} 4130 4131/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4132/// to an zero vector. 4133/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4134static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4135 SDValue V1 = N->getOperand(0); 4136 SDValue V2 = N->getOperand(1); 4137 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4138 for (unsigned i = 0; i != NumElems; ++i) { 4139 int Idx = N->getMaskElt(i); 4140 if (Idx >= (int)NumElems) { 4141 unsigned Opc = V2.getOpcode(); 4142 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4143 continue; 4144 if (Opc != ISD::BUILD_VECTOR || 4145 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4146 return false; 4147 } else if (Idx >= 0) { 4148 unsigned Opc = V1.getOpcode(); 4149 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4150 continue; 4151 if (Opc != ISD::BUILD_VECTOR || 4152 !X86::isZeroNode(V1.getOperand(Idx))) 4153 return false; 4154 } 4155 } 4156 return true; 4157} 4158 4159/// getZeroVector - Returns a vector of specified type with all zero elements. 4160/// 4161static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, 4162 SelectionDAG &DAG, DebugLoc dl) { 4163 assert(VT.isVector() && "Expected a vector type"); 4164 unsigned Size = VT.getSizeInBits(); 4165 4166 // Always build SSE zero vectors as <4 x i32> bitcasted 4167 // to their dest type. This ensures they get CSE'd. 4168 SDValue Vec; 4169 if (Size == 128) { // SSE 4170 if (Subtarget->hasSSE2()) { // SSE2 4171 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4173 } else { // SSE1 4174 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4175 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4176 } 4177 } else if (Size == 256) { // AVX 4178 if (Subtarget->hasAVX2()) { // AVX2 4179 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4180 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4181 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4182 } else { 4183 // 256-bit logic and arithmetic instructions in AVX are all 4184 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4185 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4186 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4187 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4188 } 4189 } else 4190 llvm_unreachable("Unexpected vector type"); 4191 4192 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4193} 4194 4195/// getOnesVector - Returns a vector of specified type with all bits set. 4196/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4197/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4198/// Then bitcast to their original type, ensuring they get CSE'd. 4199static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4200 DebugLoc dl) { 4201 assert(VT.isVector() && "Expected a vector type"); 4202 unsigned Size = VT.getSizeInBits(); 4203 4204 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4205 SDValue Vec; 4206 if (Size == 256) { 4207 if (HasAVX2) { // AVX2 4208 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4209 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4210 } else { // AVX 4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4212 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl); 4213 } 4214 } else if (Size == 128) { 4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4216 } else 4217 llvm_unreachable("Unexpected vector type"); 4218 4219 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4220} 4221 4222/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4223/// that point to V2 points to its first element. 4224static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) { 4225 for (unsigned i = 0; i != NumElems; ++i) { 4226 if (Mask[i] > (int)NumElems) { 4227 Mask[i] = NumElems; 4228 } 4229 } 4230} 4231 4232/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4233/// operation of specified width. 4234static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4235 SDValue V2) { 4236 unsigned NumElems = VT.getVectorNumElements(); 4237 SmallVector<int, 8> Mask; 4238 Mask.push_back(NumElems); 4239 for (unsigned i = 1; i != NumElems; ++i) 4240 Mask.push_back(i); 4241 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4242} 4243 4244/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4245static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4246 SDValue V2) { 4247 unsigned NumElems = VT.getVectorNumElements(); 4248 SmallVector<int, 8> Mask; 4249 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4250 Mask.push_back(i); 4251 Mask.push_back(i + NumElems); 4252 } 4253 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4254} 4255 4256/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4257static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4258 SDValue V2) { 4259 unsigned NumElems = VT.getVectorNumElements(); 4260 unsigned Half = NumElems/2; 4261 SmallVector<int, 8> Mask; 4262 for (unsigned i = 0; i != Half; ++i) { 4263 Mask.push_back(i + Half); 4264 Mask.push_back(i + NumElems + Half); 4265 } 4266 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4267} 4268 4269// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4270// a generic shuffle instruction because the target has no such instructions. 4271// Generate shuffles which repeat i16 and i8 several times until they can be 4272// represented by v4f32 and then be manipulated by target suported shuffles. 4273static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4274 EVT VT = V.getValueType(); 4275 int NumElems = VT.getVectorNumElements(); 4276 DebugLoc dl = V.getDebugLoc(); 4277 4278 while (NumElems > 4) { 4279 if (EltNo < NumElems/2) { 4280 V = getUnpackl(DAG, dl, VT, V, V); 4281 } else { 4282 V = getUnpackh(DAG, dl, VT, V, V); 4283 EltNo -= NumElems/2; 4284 } 4285 NumElems >>= 1; 4286 } 4287 return V; 4288} 4289 4290/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4291static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4292 EVT VT = V.getValueType(); 4293 DebugLoc dl = V.getDebugLoc(); 4294 unsigned Size = VT.getSizeInBits(); 4295 4296 if (Size == 128) { 4297 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4298 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4299 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4300 &SplatMask[0]); 4301 } else if (Size == 256) { 4302 // To use VPERMILPS to splat scalars, the second half of indicies must 4303 // refer to the higher part, which is a duplication of the lower one, 4304 // because VPERMILPS can only handle in-lane permutations. 4305 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4306 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4307 4308 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4309 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4310 &SplatMask[0]); 4311 } else 4312 llvm_unreachable("Vector size not supported"); 4313 4314 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4315} 4316 4317/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4318static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4319 EVT SrcVT = SV->getValueType(0); 4320 SDValue V1 = SV->getOperand(0); 4321 DebugLoc dl = SV->getDebugLoc(); 4322 4323 int EltNo = SV->getSplatIndex(); 4324 int NumElems = SrcVT.getVectorNumElements(); 4325 unsigned Size = SrcVT.getSizeInBits(); 4326 4327 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4328 "Unknown how to promote splat for type"); 4329 4330 // Extract the 128-bit part containing the splat element and update 4331 // the splat element index when it refers to the higher register. 4332 if (Size == 256) { 4333 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4334 V1 = Extract128BitVector(V1, Idx, DAG, dl); 4335 if (Idx > 0) 4336 EltNo -= NumElems/2; 4337 } 4338 4339 // All i16 and i8 vector types can't be used directly by a generic shuffle 4340 // instruction because the target has no such instruction. Generate shuffles 4341 // which repeat i16 and i8 several times until they fit in i32, and then can 4342 // be manipulated by target suported shuffles. 4343 EVT EltVT = SrcVT.getVectorElementType(); 4344 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4345 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4346 4347 // Recreate the 256-bit vector and place the same 128-bit vector 4348 // into the low and high part. This is necessary because we want 4349 // to use VPERM* to shuffle the vectors 4350 if (Size == 256) { 4351 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1); 4352 } 4353 4354 return getLegalSplat(DAG, V1, EltNo); 4355} 4356 4357/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4358/// vector of zero or undef vector. This produces a shuffle where the low 4359/// element of V2 is swizzled into the zero/undef vector, landing at element 4360/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4361static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4362 bool IsZero, 4363 const X86Subtarget *Subtarget, 4364 SelectionDAG &DAG) { 4365 EVT VT = V2.getValueType(); 4366 SDValue V1 = IsZero 4367 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4368 unsigned NumElems = VT.getVectorNumElements(); 4369 SmallVector<int, 16> MaskVec; 4370 for (unsigned i = 0; i != NumElems; ++i) 4371 // If this is the insertion idx, put the low elt of V2 here. 4372 MaskVec.push_back(i == Idx ? NumElems : i); 4373 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4374} 4375 4376/// getTargetShuffleMask - Calculates the shuffle mask corresponding to the 4377/// target specific opcode. Returns true if the Mask could be calculated. 4378/// Sets IsUnary to true if only uses one source. 4379static bool getTargetShuffleMask(SDNode *N, EVT VT, 4380 SmallVectorImpl<int> &Mask, bool &IsUnary) { 4381 unsigned NumElems = VT.getVectorNumElements(); 4382 SDValue ImmN; 4383 4384 IsUnary = false; 4385 switch(N->getOpcode()) { 4386 case X86ISD::SHUFP: 4387 ImmN = N->getOperand(N->getNumOperands()-1); 4388 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4389 break; 4390 case X86ISD::UNPCKH: 4391 DecodeUNPCKHMask(VT, Mask); 4392 break; 4393 case X86ISD::UNPCKL: 4394 DecodeUNPCKLMask(VT, Mask); 4395 break; 4396 case X86ISD::MOVHLPS: 4397 DecodeMOVHLPSMask(NumElems, Mask); 4398 break; 4399 case X86ISD::MOVLHPS: 4400 DecodeMOVLHPSMask(NumElems, Mask); 4401 break; 4402 case X86ISD::PSHUFD: 4403 case X86ISD::VPERMILP: 4404 ImmN = N->getOperand(N->getNumOperands()-1); 4405 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4406 IsUnary = true; 4407 break; 4408 case X86ISD::PSHUFHW: 4409 ImmN = N->getOperand(N->getNumOperands()-1); 4410 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4411 IsUnary = true; 4412 break; 4413 case X86ISD::PSHUFLW: 4414 ImmN = N->getOperand(N->getNumOperands()-1); 4415 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4416 IsUnary = true; 4417 break; 4418 case X86ISD::MOVSS: 4419 case X86ISD::MOVSD: { 4420 // The index 0 always comes from the first element of the second source, 4421 // this is why MOVSS and MOVSD are used in the first place. The other 4422 // elements come from the other positions of the first source vector 4423 Mask.push_back(NumElems); 4424 for (unsigned i = 1; i != NumElems; ++i) { 4425 Mask.push_back(i); 4426 } 4427 break; 4428 } 4429 case X86ISD::VPERM2X128: 4430 ImmN = N->getOperand(N->getNumOperands()-1); 4431 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask); 4432 if (Mask.empty()) return false; 4433 break; 4434 case X86ISD::MOVDDUP: 4435 case X86ISD::MOVLHPD: 4436 case X86ISD::MOVLPD: 4437 case X86ISD::MOVLPS: 4438 case X86ISD::MOVSHDUP: 4439 case X86ISD::MOVSLDUP: 4440 case X86ISD::PALIGN: 4441 // Not yet implemented 4442 return false; 4443 default: llvm_unreachable("unknown target shuffle node"); 4444 } 4445 4446 return true; 4447} 4448 4449/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4450/// element of the result of the vector shuffle. 4451static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, 4452 unsigned Depth) { 4453 if (Depth == 6) 4454 return SDValue(); // Limit search depth. 4455 4456 SDValue V = SDValue(N, 0); 4457 EVT VT = V.getValueType(); 4458 unsigned Opcode = V.getOpcode(); 4459 4460 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4461 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4462 int Elt = SV->getMaskElt(Index); 4463 4464 if (Elt < 0) 4465 return DAG.getUNDEF(VT.getVectorElementType()); 4466 4467 unsigned NumElems = VT.getVectorNumElements(); 4468 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0) 4469 : SV->getOperand(1); 4470 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1); 4471 } 4472 4473 // Recurse into target specific vector shuffles to find scalars. 4474 if (isTargetShuffle(Opcode)) { 4475 unsigned NumElems = VT.getVectorNumElements(); 4476 SmallVector<int, 16> ShuffleMask; 4477 SDValue ImmN; 4478 bool IsUnary; 4479 4480 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary)) 4481 return SDValue(); 4482 4483 int Elt = ShuffleMask[Index]; 4484 if (Elt < 0) 4485 return DAG.getUNDEF(VT.getVectorElementType()); 4486 4487 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0) 4488 : N->getOperand(1); 4489 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, 4490 Depth+1); 4491 } 4492 4493 // Actual nodes that may contain scalar elements 4494 if (Opcode == ISD::BITCAST) { 4495 V = V.getOperand(0); 4496 EVT SrcVT = V.getValueType(); 4497 unsigned NumElems = VT.getVectorNumElements(); 4498 4499 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4500 return SDValue(); 4501 } 4502 4503 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4504 return (Index == 0) ? V.getOperand(0) 4505 : DAG.getUNDEF(VT.getVectorElementType()); 4506 4507 if (V.getOpcode() == ISD::BUILD_VECTOR) 4508 return V.getOperand(Index); 4509 4510 return SDValue(); 4511} 4512 4513/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4514/// shuffle operation which come from a consecutively from a zero. The 4515/// search can start in two different directions, from left or right. 4516static 4517unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, 4518 bool ZerosFromLeft, SelectionDAG &DAG) { 4519 unsigned i; 4520 for (i = 0; i != NumElems; ++i) { 4521 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4522 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0); 4523 if (!(Elt.getNode() && 4524 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4525 break; 4526 } 4527 4528 return i; 4529} 4530 4531/// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) 4532/// correspond consecutively to elements from one of the vector operands, 4533/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4534static 4535bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, 4536 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4537 unsigned NumElems, unsigned &OpNum) { 4538 bool SeenV1 = false; 4539 bool SeenV2 = false; 4540 4541 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4542 int Idx = SVOp->getMaskElt(i); 4543 // Ignore undef indicies 4544 if (Idx < 0) 4545 continue; 4546 4547 if (Idx < (int)NumElems) 4548 SeenV1 = true; 4549 else 4550 SeenV2 = true; 4551 4552 // Only accept consecutive elements from the same vector 4553 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4554 return false; 4555 } 4556 4557 OpNum = SeenV1 ? 0 : 1; 4558 return true; 4559} 4560 4561/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4562/// logical left shift of a vector. 4563static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4564 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4565 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4566 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4567 false /* check zeros from right */, DAG); 4568 unsigned OpSrc; 4569 4570 if (!NumZeros) 4571 return false; 4572 4573 // Considering the elements in the mask that are not consecutive zeros, 4574 // check if they consecutively come from only one of the source vectors. 4575 // 4576 // V1 = {X, A, B, C} 0 4577 // \ \ \ / 4578 // vector_shuffle V1, V2 <1, 2, 3, X> 4579 // 4580 if (!isShuffleMaskConsecutive(SVOp, 4581 0, // Mask Start Index 4582 NumElems-NumZeros, // Mask End Index(exclusive) 4583 NumZeros, // Where to start looking in the src vector 4584 NumElems, // Number of elements in vector 4585 OpSrc)) // Which source operand ? 4586 return false; 4587 4588 isLeft = false; 4589 ShAmt = NumZeros; 4590 ShVal = SVOp->getOperand(OpSrc); 4591 return true; 4592} 4593 4594/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4595/// logical left shift of a vector. 4596static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4597 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4598 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4599 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4600 true /* check zeros from left */, DAG); 4601 unsigned OpSrc; 4602 4603 if (!NumZeros) 4604 return false; 4605 4606 // Considering the elements in the mask that are not consecutive zeros, 4607 // check if they consecutively come from only one of the source vectors. 4608 // 4609 // 0 { A, B, X, X } = V2 4610 // / \ / / 4611 // vector_shuffle V1, V2 <X, X, 4, 5> 4612 // 4613 if (!isShuffleMaskConsecutive(SVOp, 4614 NumZeros, // Mask Start Index 4615 NumElems, // Mask End Index(exclusive) 4616 0, // Where to start looking in the src vector 4617 NumElems, // Number of elements in vector 4618 OpSrc)) // Which source operand ? 4619 return false; 4620 4621 isLeft = true; 4622 ShAmt = NumZeros; 4623 ShVal = SVOp->getOperand(OpSrc); 4624 return true; 4625} 4626 4627/// isVectorShift - Returns true if the shuffle can be implemented as a 4628/// logical left or right shift of a vector. 4629static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4630 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4631 // Although the logic below support any bitwidth size, there are no 4632 // shift instructions which handle more than 128-bit vectors. 4633 if (SVOp->getValueType(0).getSizeInBits() > 128) 4634 return false; 4635 4636 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4637 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4638 return true; 4639 4640 return false; 4641} 4642 4643/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4644/// 4645static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4646 unsigned NumNonZero, unsigned NumZero, 4647 SelectionDAG &DAG, 4648 const X86Subtarget* Subtarget, 4649 const TargetLowering &TLI) { 4650 if (NumNonZero > 8) 4651 return SDValue(); 4652 4653 DebugLoc dl = Op.getDebugLoc(); 4654 SDValue V(0, 0); 4655 bool First = true; 4656 for (unsigned i = 0; i < 16; ++i) { 4657 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4658 if (ThisIsNonZero && First) { 4659 if (NumZero) 4660 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4661 else 4662 V = DAG.getUNDEF(MVT::v8i16); 4663 First = false; 4664 } 4665 4666 if ((i & 1) != 0) { 4667 SDValue ThisElt(0, 0), LastElt(0, 0); 4668 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4669 if (LastIsNonZero) { 4670 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4671 MVT::i16, Op.getOperand(i-1)); 4672 } 4673 if (ThisIsNonZero) { 4674 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4675 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4676 ThisElt, DAG.getConstant(8, MVT::i8)); 4677 if (LastIsNonZero) 4678 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4679 } else 4680 ThisElt = LastElt; 4681 4682 if (ThisElt.getNode()) 4683 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4684 DAG.getIntPtrConstant(i/2)); 4685 } 4686 } 4687 4688 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4689} 4690 4691/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4692/// 4693static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4694 unsigned NumNonZero, unsigned NumZero, 4695 SelectionDAG &DAG, 4696 const X86Subtarget* Subtarget, 4697 const TargetLowering &TLI) { 4698 if (NumNonZero > 4) 4699 return SDValue(); 4700 4701 DebugLoc dl = Op.getDebugLoc(); 4702 SDValue V(0, 0); 4703 bool First = true; 4704 for (unsigned i = 0; i < 8; ++i) { 4705 bool isNonZero = (NonZeros & (1 << i)) != 0; 4706 if (isNonZero) { 4707 if (First) { 4708 if (NumZero) 4709 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl); 4710 else 4711 V = DAG.getUNDEF(MVT::v8i16); 4712 First = false; 4713 } 4714 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4715 MVT::v8i16, V, Op.getOperand(i), 4716 DAG.getIntPtrConstant(i)); 4717 } 4718 } 4719 4720 return V; 4721} 4722 4723/// getVShift - Return a vector logical shift node. 4724/// 4725static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4726 unsigned NumBits, SelectionDAG &DAG, 4727 const TargetLowering &TLI, DebugLoc dl) { 4728 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4729 EVT ShVT = MVT::v2i64; 4730 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4731 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4732 return DAG.getNode(ISD::BITCAST, dl, VT, 4733 DAG.getNode(Opc, dl, ShVT, SrcOp, 4734 DAG.getConstant(NumBits, 4735 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4736} 4737 4738SDValue 4739X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4740 SelectionDAG &DAG) const { 4741 4742 // Check if the scalar load can be widened into a vector load. And if 4743 // the address is "base + cst" see if the cst can be "absorbed" into 4744 // the shuffle mask. 4745 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4746 SDValue Ptr = LD->getBasePtr(); 4747 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4748 return SDValue(); 4749 EVT PVT = LD->getValueType(0); 4750 if (PVT != MVT::i32 && PVT != MVT::f32) 4751 return SDValue(); 4752 4753 int FI = -1; 4754 int64_t Offset = 0; 4755 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4756 FI = FINode->getIndex(); 4757 Offset = 0; 4758 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4759 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4760 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4761 Offset = Ptr.getConstantOperandVal(1); 4762 Ptr = Ptr.getOperand(0); 4763 } else { 4764 return SDValue(); 4765 } 4766 4767 // FIXME: 256-bit vector instructions don't require a strict alignment, 4768 // improve this code to support it better. 4769 unsigned RequiredAlign = VT.getSizeInBits()/8; 4770 SDValue Chain = LD->getChain(); 4771 // Make sure the stack object alignment is at least 16 or 32. 4772 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4773 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4774 if (MFI->isFixedObjectIndex(FI)) { 4775 // Can't change the alignment. FIXME: It's possible to compute 4776 // the exact stack offset and reference FI + adjust offset instead. 4777 // If someone *really* cares about this. That's the way to implement it. 4778 return SDValue(); 4779 } else { 4780 MFI->setObjectAlignment(FI, RequiredAlign); 4781 } 4782 } 4783 4784 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4785 // Ptr + (Offset & ~15). 4786 if (Offset < 0) 4787 return SDValue(); 4788 if ((Offset % RequiredAlign) & 3) 4789 return SDValue(); 4790 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4791 if (StartOffset) 4792 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4793 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4794 4795 int EltNo = (Offset - StartOffset) >> 2; 4796 unsigned NumElems = VT.getVectorNumElements(); 4797 4798 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4799 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4800 LD->getPointerInfo().getWithOffset(StartOffset), 4801 false, false, false, 0); 4802 4803 SmallVector<int, 8> Mask; 4804 for (unsigned i = 0; i != NumElems; ++i) 4805 Mask.push_back(EltNo); 4806 4807 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); 4808 } 4809 4810 return SDValue(); 4811} 4812 4813/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4814/// vector of type 'VT', see if the elements can be replaced by a single large 4815/// load which has the same value as a build_vector whose operands are 'elts'. 4816/// 4817/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4818/// 4819/// FIXME: we'd also like to handle the case where the last elements are zero 4820/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4821/// There's even a handy isZeroNode for that purpose. 4822static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4823 DebugLoc &DL, SelectionDAG &DAG) { 4824 EVT EltVT = VT.getVectorElementType(); 4825 unsigned NumElems = Elts.size(); 4826 4827 LoadSDNode *LDBase = NULL; 4828 unsigned LastLoadedElt = -1U; 4829 4830 // For each element in the initializer, see if we've found a load or an undef. 4831 // If we don't find an initial load element, or later load elements are 4832 // non-consecutive, bail out. 4833 for (unsigned i = 0; i < NumElems; ++i) { 4834 SDValue Elt = Elts[i]; 4835 4836 if (!Elt.getNode() || 4837 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4838 return SDValue(); 4839 if (!LDBase) { 4840 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4841 return SDValue(); 4842 LDBase = cast<LoadSDNode>(Elt.getNode()); 4843 LastLoadedElt = i; 4844 continue; 4845 } 4846 if (Elt.getOpcode() == ISD::UNDEF) 4847 continue; 4848 4849 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4850 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4851 return SDValue(); 4852 LastLoadedElt = i; 4853 } 4854 4855 // If we have found an entire vector of loads and undefs, then return a large 4856 // load of the entire vector width starting at the base pointer. If we found 4857 // consecutive loads for the low half, generate a vzext_load node. 4858 if (LastLoadedElt == NumElems - 1) { 4859 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4860 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4861 LDBase->getPointerInfo(), 4862 LDBase->isVolatile(), LDBase->isNonTemporal(), 4863 LDBase->isInvariant(), 0); 4864 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4865 LDBase->getPointerInfo(), 4866 LDBase->isVolatile(), LDBase->isNonTemporal(), 4867 LDBase->isInvariant(), LDBase->getAlignment()); 4868 } 4869 if (NumElems == 4 && LastLoadedElt == 1 && 4870 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4871 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4872 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4873 SDValue ResNode = 4874 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4875 LDBase->getPointerInfo(), 4876 LDBase->getAlignment(), 4877 false/*isVolatile*/, true/*ReadMem*/, 4878 false/*WriteMem*/); 4879 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4880 } 4881 return SDValue(); 4882} 4883 4884/// LowerVectorBroadcast - Attempt to use the vbroadcast instruction 4885/// to generate a splat value for the following cases: 4886/// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant. 4887/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4888/// a scalar load, or a constant. 4889/// The VBROADCAST node is returned when a pattern is found, 4890/// or SDValue() otherwise. 4891SDValue 4892X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { 4893 if (!Subtarget->hasAVX()) 4894 return SDValue(); 4895 4896 EVT VT = Op.getValueType(); 4897 DebugLoc dl = Op.getDebugLoc(); 4898 4899 SDValue Ld; 4900 bool ConstSplatVal; 4901 4902 switch (Op.getOpcode()) { 4903 default: 4904 // Unknown pattern found. 4905 return SDValue(); 4906 4907 case ISD::BUILD_VECTOR: { 4908 // The BUILD_VECTOR node must be a splat. 4909 if (!isSplatVector(Op.getNode())) 4910 return SDValue(); 4911 4912 Ld = Op.getOperand(0); 4913 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4914 Ld.getOpcode() == ISD::ConstantFP); 4915 4916 // The suspected load node has several users. Make sure that all 4917 // of its users are from the BUILD_VECTOR node. 4918 // Constants may have multiple users. 4919 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4920 return SDValue(); 4921 break; 4922 } 4923 4924 case ISD::VECTOR_SHUFFLE: { 4925 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4926 4927 // Shuffles must have a splat mask where the first element is 4928 // broadcasted. 4929 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4930 return SDValue(); 4931 4932 SDValue Sc = Op.getOperand(0); 4933 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4934 return SDValue(); 4935 4936 Ld = Sc.getOperand(0); 4937 ConstSplatVal = (Ld.getOpcode() == ISD::Constant || 4938 Ld.getOpcode() == ISD::ConstantFP); 4939 4940 // The scalar_to_vector node and the suspected 4941 // load node must have exactly one user. 4942 // Constants may have multiple users. 4943 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse())) 4944 return SDValue(); 4945 break; 4946 } 4947 } 4948 4949 bool Is256 = VT.getSizeInBits() == 256; 4950 bool Is128 = VT.getSizeInBits() == 128; 4951 4952 // Handle the broadcasting a single constant scalar from the constant pool 4953 // into a vector. On Sandybridge it is still better to load a constant vector 4954 // from the constant pool and not to broadcast it from a scalar. 4955 if (ConstSplatVal && Subtarget->hasAVX2()) { 4956 EVT CVT = Ld.getValueType(); 4957 assert(!CVT.isVector() && "Must not broadcast a vector type"); 4958 unsigned ScalarSize = CVT.getSizeInBits(); 4959 4960 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) || 4961 (Is128 && (ScalarSize == 32))) { 4962 4963 const Constant *C = 0; 4964 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld)) 4965 C = CI->getConstantIntValue(); 4966 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld)) 4967 C = CF->getConstantFPValue(); 4968 4969 assert(C && "Invalid constant type"); 4970 4971 SDValue CP = DAG.getConstantPool(C, getPointerTy()); 4972 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment(); 4973 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, 4974 MachinePointerInfo::getConstantPool(), 4975 false, false, false, Alignment); 4976 4977 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4978 } 4979 } 4980 4981 // The scalar source must be a normal load. 4982 if (!ISD::isNormalLoad(Ld.getNode())) 4983 return SDValue(); 4984 4985 // Reject loads that have uses of the chain result 4986 if (Ld->hasAnyUseOfValue(1)) 4987 return SDValue(); 4988 4989 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 4990 4991 // VBroadcast to YMM 4992 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 4993 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4994 4995 // VBroadcast to XMM 4996 if (Is128 && (ScalarSize == 32)) 4997 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 4998 4999 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5000 // double since there is vbroadcastsd xmm 5001 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5002 // VBroadcast to YMM 5003 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 5004 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5005 5006 // VBroadcast to XMM 5007 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 5008 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); 5009 } 5010 5011 // Unsupported broadcast. 5012 return SDValue(); 5013} 5014 5015SDValue 5016X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5017 DebugLoc dl = Op.getDebugLoc(); 5018 5019 EVT VT = Op.getValueType(); 5020 EVT ExtVT = VT.getVectorElementType(); 5021 unsigned NumElems = Op.getNumOperands(); 5022 5023 // Vectors containing all zeros can be matched by pxor and xorps later 5024 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5025 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5026 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5027 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5028 return Op; 5029 5030 return getZeroVector(VT, Subtarget, DAG, dl); 5031 } 5032 5033 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5034 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5035 // vpcmpeqd on 256-bit vectors. 5036 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5037 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5038 return Op; 5039 5040 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5041 } 5042 5043 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 5044 if (Broadcast.getNode()) 5045 return Broadcast; 5046 5047 unsigned EVTBits = ExtVT.getSizeInBits(); 5048 5049 unsigned NumZero = 0; 5050 unsigned NumNonZero = 0; 5051 unsigned NonZeros = 0; 5052 bool IsAllConstants = true; 5053 SmallSet<SDValue, 8> Values; 5054 for (unsigned i = 0; i < NumElems; ++i) { 5055 SDValue Elt = Op.getOperand(i); 5056 if (Elt.getOpcode() == ISD::UNDEF) 5057 continue; 5058 Values.insert(Elt); 5059 if (Elt.getOpcode() != ISD::Constant && 5060 Elt.getOpcode() != ISD::ConstantFP) 5061 IsAllConstants = false; 5062 if (X86::isZeroNode(Elt)) 5063 NumZero++; 5064 else { 5065 NonZeros |= (1 << i); 5066 NumNonZero++; 5067 } 5068 } 5069 5070 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5071 if (NumNonZero == 0) 5072 return DAG.getUNDEF(VT); 5073 5074 // Special case for single non-zero, non-undef, element. 5075 if (NumNonZero == 1) { 5076 unsigned Idx = CountTrailingZeros_32(NonZeros); 5077 SDValue Item = Op.getOperand(Idx); 5078 5079 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5080 // the value are obviously zero, truncate the value to i32 and do the 5081 // insertion that way. Only do this if the value is non-constant or if the 5082 // value is a constant being inserted into element 0. It is cheaper to do 5083 // a constant pool load than it is to do a movd + shuffle. 5084 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5085 (!IsAllConstants || Idx == 0)) { 5086 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5087 // Handle SSE only. 5088 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5089 EVT VecVT = MVT::v4i32; 5090 unsigned VecElts = 4; 5091 5092 // Truncate the value (which may itself be a constant) to i32, and 5093 // convert it to a vector with movd (S2V+shuffle to zero extend). 5094 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5095 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5096 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5097 5098 // Now we have our 32-bit value zero extended in the low element of 5099 // a vector. If Idx != 0, swizzle it into place. 5100 if (Idx != 0) { 5101 SmallVector<int, 4> Mask; 5102 Mask.push_back(Idx); 5103 for (unsigned i = 1; i != VecElts; ++i) 5104 Mask.push_back(i); 5105 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT), 5106 &Mask[0]); 5107 } 5108 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5109 } 5110 } 5111 5112 // If we have a constant or non-constant insertion into the low element of 5113 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5114 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5115 // depending on what the source datatype is. 5116 if (Idx == 0) { 5117 if (NumZero == 0) 5118 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5119 5120 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5121 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5122 if (VT.getSizeInBits() == 256) { 5123 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl); 5124 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5125 Item, DAG.getIntPtrConstant(0)); 5126 } 5127 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5128 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5129 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5130 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5131 } 5132 5133 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5134 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5135 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5136 if (VT.getSizeInBits() == 256) { 5137 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl); 5138 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl); 5139 } else { 5140 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5141 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5142 } 5143 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5144 } 5145 } 5146 5147 // Is it a vector logical left shift? 5148 if (NumElems == 2 && Idx == 1 && 5149 X86::isZeroNode(Op.getOperand(0)) && 5150 !X86::isZeroNode(Op.getOperand(1))) { 5151 unsigned NumBits = VT.getSizeInBits(); 5152 return getVShift(true, VT, 5153 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5154 VT, Op.getOperand(1)), 5155 NumBits/2, DAG, *this, dl); 5156 } 5157 5158 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5159 return SDValue(); 5160 5161 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5162 // is a non-constant being inserted into an element other than the low one, 5163 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5164 // movd/movss) to move this into the low element, then shuffle it into 5165 // place. 5166 if (EVTBits == 32) { 5167 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5168 5169 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5170 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5171 SmallVector<int, 8> MaskVec; 5172 for (unsigned i = 0; i < NumElems; i++) 5173 MaskVec.push_back(i == Idx ? 0 : 1); 5174 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5175 } 5176 } 5177 5178 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5179 if (Values.size() == 1) { 5180 if (EVTBits == 32) { 5181 // Instead of a shuffle like this: 5182 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5183 // Check if it's possible to issue this instead. 5184 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5185 unsigned Idx = CountTrailingZeros_32(NonZeros); 5186 SDValue Item = Op.getOperand(Idx); 5187 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5188 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5189 } 5190 return SDValue(); 5191 } 5192 5193 // A vector full of immediates; various special cases are already 5194 // handled, so this is best done with a single constant-pool load. 5195 if (IsAllConstants) 5196 return SDValue(); 5197 5198 // For AVX-length vectors, build the individual 128-bit pieces and use 5199 // shuffles to put them in place. 5200 if (VT.getSizeInBits() == 256) { 5201 SmallVector<SDValue, 32> V; 5202 for (unsigned i = 0; i != NumElems; ++i) 5203 V.push_back(Op.getOperand(i)); 5204 5205 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5206 5207 // Build both the lower and upper subvector. 5208 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5209 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5210 NumElems/2); 5211 5212 // Recreate the wider vector with the lower and upper part. 5213 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl); 5214 } 5215 5216 // Let legalizer expand 2-wide build_vectors. 5217 if (EVTBits == 64) { 5218 if (NumNonZero == 1) { 5219 // One half is zero or undef. 5220 unsigned Idx = CountTrailingZeros_32(NonZeros); 5221 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5222 Op.getOperand(Idx)); 5223 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5224 } 5225 return SDValue(); 5226 } 5227 5228 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5229 if (EVTBits == 8 && NumElems == 16) { 5230 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5231 Subtarget, *this); 5232 if (V.getNode()) return V; 5233 } 5234 5235 if (EVTBits == 16 && NumElems == 8) { 5236 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5237 Subtarget, *this); 5238 if (V.getNode()) return V; 5239 } 5240 5241 // If element VT is == 32 bits, turn it into a number of shuffles. 5242 SmallVector<SDValue, 8> V(NumElems); 5243 if (NumElems == 4 && NumZero > 0) { 5244 for (unsigned i = 0; i < 4; ++i) { 5245 bool isZero = !(NonZeros & (1 << i)); 5246 if (isZero) 5247 V[i] = getZeroVector(VT, Subtarget, DAG, dl); 5248 else 5249 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5250 } 5251 5252 for (unsigned i = 0; i < 2; ++i) { 5253 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5254 default: break; 5255 case 0: 5256 V[i] = V[i*2]; // Must be a zero vector. 5257 break; 5258 case 1: 5259 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5260 break; 5261 case 2: 5262 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5263 break; 5264 case 3: 5265 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5266 break; 5267 } 5268 } 5269 5270 bool Reverse1 = (NonZeros & 0x3) == 2; 5271 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5272 int MaskVec[] = { 5273 Reverse1 ? 1 : 0, 5274 Reverse1 ? 0 : 1, 5275 static_cast<int>(Reverse2 ? NumElems+1 : NumElems), 5276 static_cast<int>(Reverse2 ? NumElems : NumElems+1) 5277 }; 5278 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5279 } 5280 5281 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5282 // Check for a build vector of consecutive loads. 5283 for (unsigned i = 0; i < NumElems; ++i) 5284 V[i] = Op.getOperand(i); 5285 5286 // Check for elements which are consecutive loads. 5287 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5288 if (LD.getNode()) 5289 return LD; 5290 5291 // For SSE 4.1, use insertps to put the high elements into the low element. 5292 if (getSubtarget()->hasSSE41()) { 5293 SDValue Result; 5294 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5295 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5296 else 5297 Result = DAG.getUNDEF(VT); 5298 5299 for (unsigned i = 1; i < NumElems; ++i) { 5300 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5301 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5302 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5303 } 5304 return Result; 5305 } 5306 5307 // Otherwise, expand into a number of unpckl*, start by extending each of 5308 // our (non-undef) elements to the full vector width with the element in the 5309 // bottom slot of the vector (which generates no code for SSE). 5310 for (unsigned i = 0; i < NumElems; ++i) { 5311 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5312 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5313 else 5314 V[i] = DAG.getUNDEF(VT); 5315 } 5316 5317 // Next, we iteratively mix elements, e.g. for v4f32: 5318 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5319 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5320 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5321 unsigned EltStride = NumElems >> 1; 5322 while (EltStride != 0) { 5323 for (unsigned i = 0; i < EltStride; ++i) { 5324 // If V[i+EltStride] is undef and this is the first round of mixing, 5325 // then it is safe to just drop this shuffle: V[i] is already in the 5326 // right place, the one element (since it's the first round) being 5327 // inserted as undef can be dropped. This isn't safe for successive 5328 // rounds because they will permute elements within both vectors. 5329 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5330 EltStride == NumElems/2) 5331 continue; 5332 5333 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5334 } 5335 EltStride >>= 1; 5336 } 5337 return V[0]; 5338 } 5339 return SDValue(); 5340} 5341 5342// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5343// them in a MMX register. This is better than doing a stack convert. 5344static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5345 DebugLoc dl = Op.getDebugLoc(); 5346 EVT ResVT = Op.getValueType(); 5347 5348 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5349 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5350 int Mask[2]; 5351 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5352 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5353 InVec = Op.getOperand(1); 5354 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5355 unsigned NumElts = ResVT.getVectorNumElements(); 5356 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5357 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5358 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5359 } else { 5360 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5361 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5362 Mask[0] = 0; Mask[1] = 2; 5363 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5364 } 5365 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5366} 5367 5368// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5369// to create 256-bit vectors from two other 128-bit ones. 5370static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5371 DebugLoc dl = Op.getDebugLoc(); 5372 EVT ResVT = Op.getValueType(); 5373 5374 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5375 5376 SDValue V1 = Op.getOperand(0); 5377 SDValue V2 = Op.getOperand(1); 5378 unsigned NumElems = ResVT.getVectorNumElements(); 5379 5380 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); 5381} 5382 5383SDValue 5384X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5385 EVT ResVT = Op.getValueType(); 5386 5387 assert(Op.getNumOperands() == 2); 5388 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5389 "Unsupported CONCAT_VECTORS for value type"); 5390 5391 // We support concatenate two MMX registers and place them in a MMX register. 5392 // This is better than doing a stack convert. 5393 if (ResVT.is128BitVector()) 5394 return LowerMMXCONCAT_VECTORS(Op, DAG); 5395 5396 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5397 // from two other 128-bit ones. 5398 return LowerAVXCONCAT_VECTORS(Op, DAG); 5399} 5400 5401// Try to lower a shuffle node into a simple blend instruction. 5402static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, 5403 const X86Subtarget *Subtarget, 5404 SelectionDAG &DAG) { 5405 SDValue V1 = SVOp->getOperand(0); 5406 SDValue V2 = SVOp->getOperand(1); 5407 DebugLoc dl = SVOp->getDebugLoc(); 5408 MVT VT = SVOp->getValueType(0).getSimpleVT(); 5409 unsigned NumElems = VT.getVectorNumElements(); 5410 5411 if (!Subtarget->hasSSE41()) 5412 return SDValue(); 5413 5414 unsigned ISDNo = 0; 5415 MVT OpTy; 5416 5417 switch (VT.SimpleTy) { 5418 default: return SDValue(); 5419 case MVT::v8i16: 5420 ISDNo = X86ISD::BLENDPW; 5421 OpTy = MVT::v8i16; 5422 break; 5423 case MVT::v4i32: 5424 case MVT::v4f32: 5425 ISDNo = X86ISD::BLENDPS; 5426 OpTy = MVT::v4f32; 5427 break; 5428 case MVT::v2i64: 5429 case MVT::v2f64: 5430 ISDNo = X86ISD::BLENDPD; 5431 OpTy = MVT::v2f64; 5432 break; 5433 case MVT::v8i32: 5434 case MVT::v8f32: 5435 if (!Subtarget->hasAVX()) 5436 return SDValue(); 5437 ISDNo = X86ISD::BLENDPS; 5438 OpTy = MVT::v8f32; 5439 break; 5440 case MVT::v4i64: 5441 case MVT::v4f64: 5442 if (!Subtarget->hasAVX()) 5443 return SDValue(); 5444 ISDNo = X86ISD::BLENDPD; 5445 OpTy = MVT::v4f64; 5446 break; 5447 } 5448 assert(ISDNo && "Invalid Op Number"); 5449 5450 unsigned MaskVals = 0; 5451 5452 for (unsigned i = 0; i != NumElems; ++i) { 5453 int EltIdx = SVOp->getMaskElt(i); 5454 if (EltIdx == (int)i || EltIdx < 0) 5455 MaskVals |= (1<<i); 5456 else if (EltIdx == (int)(i + NumElems)) 5457 continue; // Bit is set to zero; 5458 else 5459 return SDValue(); 5460 } 5461 5462 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); 5463 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2); 5464 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2, 5465 DAG.getConstant(MaskVals, MVT::i32)); 5466 return DAG.getNode(ISD::BITCAST, dl, VT, Ret); 5467} 5468 5469// v8i16 shuffles - Prefer shuffles in the following order: 5470// 1. [all] pshuflw, pshufhw, optional move 5471// 2. [ssse3] 1 x pshufb 5472// 3. [ssse3] 2 x pshufb + 1 x por 5473// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5474SDValue 5475X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5476 SelectionDAG &DAG) const { 5477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5478 SDValue V1 = SVOp->getOperand(0); 5479 SDValue V2 = SVOp->getOperand(1); 5480 DebugLoc dl = SVOp->getDebugLoc(); 5481 SmallVector<int, 8> MaskVals; 5482 5483 // Determine if more than 1 of the words in each of the low and high quadwords 5484 // of the result come from the same quadword of one of the two inputs. Undef 5485 // mask values count as coming from any quadword, for better codegen. 5486 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5487 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5488 std::bitset<4> InputQuads; 5489 for (unsigned i = 0; i < 8; ++i) { 5490 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5491 int EltIdx = SVOp->getMaskElt(i); 5492 MaskVals.push_back(EltIdx); 5493 if (EltIdx < 0) { 5494 ++Quad[0]; 5495 ++Quad[1]; 5496 ++Quad[2]; 5497 ++Quad[3]; 5498 continue; 5499 } 5500 ++Quad[EltIdx / 4]; 5501 InputQuads.set(EltIdx / 4); 5502 } 5503 5504 int BestLoQuad = -1; 5505 unsigned MaxQuad = 1; 5506 for (unsigned i = 0; i < 4; ++i) { 5507 if (LoQuad[i] > MaxQuad) { 5508 BestLoQuad = i; 5509 MaxQuad = LoQuad[i]; 5510 } 5511 } 5512 5513 int BestHiQuad = -1; 5514 MaxQuad = 1; 5515 for (unsigned i = 0; i < 4; ++i) { 5516 if (HiQuad[i] > MaxQuad) { 5517 BestHiQuad = i; 5518 MaxQuad = HiQuad[i]; 5519 } 5520 } 5521 5522 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5523 // of the two input vectors, shuffle them into one input vector so only a 5524 // single pshufb instruction is necessary. If There are more than 2 input 5525 // quads, disable the next transformation since it does not help SSSE3. 5526 bool V1Used = InputQuads[0] || InputQuads[1]; 5527 bool V2Used = InputQuads[2] || InputQuads[3]; 5528 if (Subtarget->hasSSSE3()) { 5529 if (InputQuads.count() == 2 && V1Used && V2Used) { 5530 BestLoQuad = InputQuads[0] ? 0 : 1; 5531 BestHiQuad = InputQuads[2] ? 2 : 3; 5532 } 5533 if (InputQuads.count() > 2) { 5534 BestLoQuad = -1; 5535 BestHiQuad = -1; 5536 } 5537 } 5538 5539 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5540 // the shuffle mask. If a quad is scored as -1, that means that it contains 5541 // words from all 4 input quadwords. 5542 SDValue NewV; 5543 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5544 int MaskV[] = { 5545 BestLoQuad < 0 ? 0 : BestLoQuad, 5546 BestHiQuad < 0 ? 1 : BestHiQuad 5547 }; 5548 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5549 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5550 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5551 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5552 5553 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5554 // source words for the shuffle, to aid later transformations. 5555 bool AllWordsInNewV = true; 5556 bool InOrder[2] = { true, true }; 5557 for (unsigned i = 0; i != 8; ++i) { 5558 int idx = MaskVals[i]; 5559 if (idx != (int)i) 5560 InOrder[i/4] = false; 5561 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5562 continue; 5563 AllWordsInNewV = false; 5564 break; 5565 } 5566 5567 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5568 if (AllWordsInNewV) { 5569 for (int i = 0; i != 8; ++i) { 5570 int idx = MaskVals[i]; 5571 if (idx < 0) 5572 continue; 5573 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5574 if ((idx != i) && idx < 4) 5575 pshufhw = false; 5576 if ((idx != i) && idx > 3) 5577 pshuflw = false; 5578 } 5579 V1 = NewV; 5580 V2Used = false; 5581 BestLoQuad = 0; 5582 BestHiQuad = 1; 5583 } 5584 5585 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5586 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5587 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5588 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5589 unsigned TargetMask = 0; 5590 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5591 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5592 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5593 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp): 5594 getShufflePSHUFLWImmediate(SVOp); 5595 V1 = NewV.getOperand(0); 5596 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5597 } 5598 } 5599 5600 // If we have SSSE3, and all words of the result are from 1 input vector, 5601 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5602 // is present, fall back to case 4. 5603 if (Subtarget->hasSSSE3()) { 5604 SmallVector<SDValue,16> pshufbMask; 5605 5606 // If we have elements from both input vectors, set the high bit of the 5607 // shuffle mask element to zero out elements that come from V2 in the V1 5608 // mask, and elements that come from V1 in the V2 mask, so that the two 5609 // results can be OR'd together. 5610 bool TwoInputs = V1Used && V2Used; 5611 for (unsigned i = 0; i != 8; ++i) { 5612 int EltIdx = MaskVals[i] * 2; 5613 if (TwoInputs && (EltIdx >= 16)) { 5614 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5615 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5616 continue; 5617 } 5618 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5619 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5620 } 5621 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5622 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5623 DAG.getNode(ISD::BUILD_VECTOR, dl, 5624 MVT::v16i8, &pshufbMask[0], 16)); 5625 if (!TwoInputs) 5626 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5627 5628 // Calculate the shuffle mask for the second input, shuffle it, and 5629 // OR it with the first shuffled input. 5630 pshufbMask.clear(); 5631 for (unsigned i = 0; i != 8; ++i) { 5632 int EltIdx = MaskVals[i] * 2; 5633 if (EltIdx < 16) { 5634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5636 continue; 5637 } 5638 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5639 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5640 } 5641 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5642 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5643 DAG.getNode(ISD::BUILD_VECTOR, dl, 5644 MVT::v16i8, &pshufbMask[0], 16)); 5645 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5646 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5647 } 5648 5649 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5650 // and update MaskVals with new element order. 5651 std::bitset<8> InOrder; 5652 if (BestLoQuad >= 0) { 5653 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 }; 5654 for (int i = 0; i != 4; ++i) { 5655 int idx = MaskVals[i]; 5656 if (idx < 0) { 5657 InOrder.set(i); 5658 } else if ((idx / 4) == BestLoQuad) { 5659 MaskV[i] = idx & 3; 5660 InOrder.set(i); 5661 } 5662 } 5663 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5664 &MaskV[0]); 5665 5666 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5667 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5668 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5669 NewV.getOperand(0), 5670 getShufflePSHUFLWImmediate(SVOp), DAG); 5671 } 5672 } 5673 5674 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5675 // and update MaskVals with the new element order. 5676 if (BestHiQuad >= 0) { 5677 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 }; 5678 for (unsigned i = 4; i != 8; ++i) { 5679 int idx = MaskVals[i]; 5680 if (idx < 0) { 5681 InOrder.set(i); 5682 } else if ((idx / 4) == BestHiQuad) { 5683 MaskV[i] = (idx & 3) + 4; 5684 InOrder.set(i); 5685 } 5686 } 5687 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5688 &MaskV[0]); 5689 5690 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) { 5691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode()); 5692 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5693 NewV.getOperand(0), 5694 getShufflePSHUFHWImmediate(SVOp), DAG); 5695 } 5696 } 5697 5698 // In case BestHi & BestLo were both -1, which means each quadword has a word 5699 // from each of the four input quadwords, calculate the InOrder bitvector now 5700 // before falling through to the insert/extract cleanup. 5701 if (BestLoQuad == -1 && BestHiQuad == -1) { 5702 NewV = V1; 5703 for (int i = 0; i != 8; ++i) 5704 if (MaskVals[i] < 0 || MaskVals[i] == i) 5705 InOrder.set(i); 5706 } 5707 5708 // The other elements are put in the right place using pextrw and pinsrw. 5709 for (unsigned i = 0; i != 8; ++i) { 5710 if (InOrder[i]) 5711 continue; 5712 int EltIdx = MaskVals[i]; 5713 if (EltIdx < 0) 5714 continue; 5715 SDValue ExtOp = (EltIdx < 8) 5716 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5717 DAG.getIntPtrConstant(EltIdx)) 5718 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5719 DAG.getIntPtrConstant(EltIdx - 8)); 5720 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5721 DAG.getIntPtrConstant(i)); 5722 } 5723 return NewV; 5724} 5725 5726// v16i8 shuffles - Prefer shuffles in the following order: 5727// 1. [ssse3] 1 x pshufb 5728// 2. [ssse3] 2 x pshufb + 1 x por 5729// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5730static 5731SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5732 SelectionDAG &DAG, 5733 const X86TargetLowering &TLI) { 5734 SDValue V1 = SVOp->getOperand(0); 5735 SDValue V2 = SVOp->getOperand(1); 5736 DebugLoc dl = SVOp->getDebugLoc(); 5737 ArrayRef<int> MaskVals = SVOp->getMask(); 5738 5739 // If we have SSSE3, case 1 is generated when all result bytes come from 5740 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5741 // present, fall back to case 3. 5742 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5743 bool V1Only = true; 5744 bool V2Only = true; 5745 for (unsigned i = 0; i < 16; ++i) { 5746 int EltIdx = MaskVals[i]; 5747 if (EltIdx < 0) 5748 continue; 5749 if (EltIdx < 16) 5750 V2Only = false; 5751 else 5752 V1Only = false; 5753 } 5754 5755 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5756 if (TLI.getSubtarget()->hasSSSE3()) { 5757 SmallVector<SDValue,16> pshufbMask; 5758 5759 // If all result elements are from one input vector, then only translate 5760 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5761 // 5762 // Otherwise, we have elements from both input vectors, and must zero out 5763 // elements that come from V2 in the first mask, and V1 in the second mask 5764 // so that we can OR them together. 5765 bool TwoInputs = !(V1Only || V2Only); 5766 for (unsigned i = 0; i != 16; ++i) { 5767 int EltIdx = MaskVals[i]; 5768 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5769 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5770 continue; 5771 } 5772 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5773 } 5774 // If all the elements are from V2, assign it to V1 and return after 5775 // building the first pshufb. 5776 if (V2Only) 5777 V1 = V2; 5778 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5779 DAG.getNode(ISD::BUILD_VECTOR, dl, 5780 MVT::v16i8, &pshufbMask[0], 16)); 5781 if (!TwoInputs) 5782 return V1; 5783 5784 // Calculate the shuffle mask for the second input, shuffle it, and 5785 // OR it with the first shuffled input. 5786 pshufbMask.clear(); 5787 for (unsigned i = 0; i != 16; ++i) { 5788 int EltIdx = MaskVals[i]; 5789 if (EltIdx < 16) { 5790 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5791 continue; 5792 } 5793 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5794 } 5795 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5796 DAG.getNode(ISD::BUILD_VECTOR, dl, 5797 MVT::v16i8, &pshufbMask[0], 16)); 5798 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5799 } 5800 5801 // No SSSE3 - Calculate in place words and then fix all out of place words 5802 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5803 // the 16 different words that comprise the two doublequadword input vectors. 5804 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5805 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5806 SDValue NewV = V2Only ? V2 : V1; 5807 for (int i = 0; i != 8; ++i) { 5808 int Elt0 = MaskVals[i*2]; 5809 int Elt1 = MaskVals[i*2+1]; 5810 5811 // This word of the result is all undef, skip it. 5812 if (Elt0 < 0 && Elt1 < 0) 5813 continue; 5814 5815 // This word of the result is already in the correct place, skip it. 5816 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5817 continue; 5818 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5819 continue; 5820 5821 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5822 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5823 SDValue InsElt; 5824 5825 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5826 // using a single extract together, load it and store it. 5827 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5828 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5829 DAG.getIntPtrConstant(Elt1 / 2)); 5830 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5831 DAG.getIntPtrConstant(i)); 5832 continue; 5833 } 5834 5835 // If Elt1 is defined, extract it from the appropriate source. If the 5836 // source byte is not also odd, shift the extracted word left 8 bits 5837 // otherwise clear the bottom 8 bits if we need to do an or. 5838 if (Elt1 >= 0) { 5839 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5840 DAG.getIntPtrConstant(Elt1 / 2)); 5841 if ((Elt1 & 1) == 0) 5842 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5843 DAG.getConstant(8, 5844 TLI.getShiftAmountTy(InsElt.getValueType()))); 5845 else if (Elt0 >= 0) 5846 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5847 DAG.getConstant(0xFF00, MVT::i16)); 5848 } 5849 // If Elt0 is defined, extract it from the appropriate source. If the 5850 // source byte is not also even, shift the extracted word right 8 bits. If 5851 // Elt1 was also defined, OR the extracted values together before 5852 // inserting them in the result. 5853 if (Elt0 >= 0) { 5854 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5855 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5856 if ((Elt0 & 1) != 0) 5857 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5858 DAG.getConstant(8, 5859 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5860 else if (Elt1 >= 0) 5861 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5862 DAG.getConstant(0x00FF, MVT::i16)); 5863 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5864 : InsElt0; 5865 } 5866 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5867 DAG.getIntPtrConstant(i)); 5868 } 5869 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5870} 5871 5872/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5873/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5874/// done when every pair / quad of shuffle mask elements point to elements in 5875/// the right sequence. e.g. 5876/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5877static 5878SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5879 SelectionDAG &DAG, DebugLoc dl) { 5880 EVT VT = SVOp->getValueType(0); 5881 SDValue V1 = SVOp->getOperand(0); 5882 SDValue V2 = SVOp->getOperand(1); 5883 unsigned NumElems = VT.getVectorNumElements(); 5884 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5885 EVT NewVT; 5886 switch (VT.getSimpleVT().SimpleTy) { 5887 default: llvm_unreachable("Unexpected!"); 5888 case MVT::v4f32: NewVT = MVT::v2f64; break; 5889 case MVT::v4i32: NewVT = MVT::v2i64; break; 5890 case MVT::v8i16: NewVT = MVT::v4i32; break; 5891 case MVT::v16i8: NewVT = MVT::v4i32; break; 5892 } 5893 5894 int Scale = NumElems / NewWidth; 5895 SmallVector<int, 8> MaskVec; 5896 for (unsigned i = 0; i < NumElems; i += Scale) { 5897 int StartIdx = -1; 5898 for (int j = 0; j < Scale; ++j) { 5899 int EltIdx = SVOp->getMaskElt(i+j); 5900 if (EltIdx < 0) 5901 continue; 5902 if (StartIdx == -1) 5903 StartIdx = EltIdx - (EltIdx % Scale); 5904 if (EltIdx != StartIdx + j) 5905 return SDValue(); 5906 } 5907 if (StartIdx == -1) 5908 MaskVec.push_back(-1); 5909 else 5910 MaskVec.push_back(StartIdx / Scale); 5911 } 5912 5913 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5914 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5915 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5916} 5917 5918/// getVZextMovL - Return a zero-extending vector move low node. 5919/// 5920static SDValue getVZextMovL(EVT VT, EVT OpVT, 5921 SDValue SrcOp, SelectionDAG &DAG, 5922 const X86Subtarget *Subtarget, DebugLoc dl) { 5923 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5924 LoadSDNode *LD = NULL; 5925 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5926 LD = dyn_cast<LoadSDNode>(SrcOp); 5927 if (!LD) { 5928 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5929 // instead. 5930 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5931 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5932 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5933 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5934 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5935 // PR2108 5936 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5937 return DAG.getNode(ISD::BITCAST, dl, VT, 5938 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5939 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5940 OpVT, 5941 SrcOp.getOperand(0) 5942 .getOperand(0)))); 5943 } 5944 } 5945 } 5946 5947 return DAG.getNode(ISD::BITCAST, dl, VT, 5948 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5949 DAG.getNode(ISD::BITCAST, dl, 5950 OpVT, SrcOp))); 5951} 5952 5953/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5954/// which could not be matched by any known target speficic shuffle 5955static SDValue 5956LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5957 EVT VT = SVOp->getValueType(0); 5958 5959 unsigned NumElems = VT.getVectorNumElements(); 5960 unsigned NumLaneElems = NumElems / 2; 5961 5962 DebugLoc dl = SVOp->getDebugLoc(); 5963 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5964 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems); 5965 SDValue Shufs[2]; 5966 5967 SmallVector<int, 16> Mask; 5968 for (unsigned l = 0; l < 2; ++l) { 5969 // Build a shuffle mask for the output, discovering on the fly which 5970 // input vectors to use as shuffle operands (recorded in InputUsed). 5971 // If building a suitable shuffle vector proves too hard, then bail 5972 // out with useBuildVector set. 5973 int InputUsed[2] = { -1, -1 }; // Not yet discovered. 5974 unsigned LaneStart = l * NumLaneElems; 5975 for (unsigned i = 0; i != NumLaneElems; ++i) { 5976 // The mask element. This indexes into the input. 5977 int Idx = SVOp->getMaskElt(i+LaneStart); 5978 if (Idx < 0) { 5979 // the mask element does not index into any input vector. 5980 Mask.push_back(-1); 5981 continue; 5982 } 5983 5984 // The input vector this mask element indexes into. 5985 int Input = Idx / NumLaneElems; 5986 5987 // Turn the index into an offset from the start of the input vector. 5988 Idx -= Input * NumLaneElems; 5989 5990 // Find or create a shuffle vector operand to hold this input. 5991 unsigned OpNo; 5992 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 5993 if (InputUsed[OpNo] == Input) 5994 // This input vector is already an operand. 5995 break; 5996 if (InputUsed[OpNo] < 0) { 5997 // Create a new operand for this input vector. 5998 InputUsed[OpNo] = Input; 5999 break; 6000 } 6001 } 6002 6003 if (OpNo >= array_lengthof(InputUsed)) { 6004 // More than two input vectors used! Give up. 6005 return SDValue(); 6006 } 6007 6008 // Add the mask index for the new shuffle vector. 6009 Mask.push_back(Idx + OpNo * NumLaneElems); 6010 } 6011 6012 if (InputUsed[0] < 0) { 6013 // No input vectors were used! The result is undefined. 6014 Shufs[l] = DAG.getUNDEF(NVT); 6015 } else { 6016 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), 6017 (InputUsed[0] % 2) * NumLaneElems, 6018 DAG, dl); 6019 // If only one input was used, use an undefined vector for the other. 6020 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) : 6021 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2), 6022 (InputUsed[1] % 2) * NumLaneElems, DAG, dl); 6023 // At least one input vector was used. Create a new shuffle vector. 6024 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]); 6025 } 6026 6027 Mask.clear(); 6028 } 6029 6030 // Concatenate the result back 6031 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]); 6032} 6033 6034/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6035/// 4 elements, and match them with several different shuffle types. 6036static SDValue 6037LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6038 SDValue V1 = SVOp->getOperand(0); 6039 SDValue V2 = SVOp->getOperand(1); 6040 DebugLoc dl = SVOp->getDebugLoc(); 6041 EVT VT = SVOp->getValueType(0); 6042 6043 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6044 6045 std::pair<int, int> Locs[4]; 6046 int Mask1[] = { -1, -1, -1, -1 }; 6047 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6048 6049 unsigned NumHi = 0; 6050 unsigned NumLo = 0; 6051 for (unsigned i = 0; i != 4; ++i) { 6052 int Idx = PermMask[i]; 6053 if (Idx < 0) { 6054 Locs[i] = std::make_pair(-1, -1); 6055 } else { 6056 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6057 if (Idx < 4) { 6058 Locs[i] = std::make_pair(0, NumLo); 6059 Mask1[NumLo] = Idx; 6060 NumLo++; 6061 } else { 6062 Locs[i] = std::make_pair(1, NumHi); 6063 if (2+NumHi < 4) 6064 Mask1[2+NumHi] = Idx; 6065 NumHi++; 6066 } 6067 } 6068 } 6069 6070 if (NumLo <= 2 && NumHi <= 2) { 6071 // If no more than two elements come from either vector. This can be 6072 // implemented with two shuffles. First shuffle gather the elements. 6073 // The second shuffle, which takes the first shuffle as both of its 6074 // vector operands, put the elements into the right order. 6075 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6076 6077 int Mask2[] = { -1, -1, -1, -1 }; 6078 6079 for (unsigned i = 0; i != 4; ++i) 6080 if (Locs[i].first != -1) { 6081 unsigned Idx = (i < 2) ? 0 : 4; 6082 Idx += Locs[i].first * 2 + Locs[i].second; 6083 Mask2[i] = Idx; 6084 } 6085 6086 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6087 } 6088 6089 if (NumLo == 3 || NumHi == 3) { 6090 // Otherwise, we must have three elements from one vector, call it X, and 6091 // one element from the other, call it Y. First, use a shufps to build an 6092 // intermediate vector with the one element from Y and the element from X 6093 // that will be in the same half in the final destination (the indexes don't 6094 // matter). Then, use a shufps to build the final vector, taking the half 6095 // containing the element from Y from the intermediate, and the other half 6096 // from X. 6097 if (NumHi == 3) { 6098 // Normalize it so the 3 elements come from V1. 6099 CommuteVectorShuffleMask(PermMask, 4); 6100 std::swap(V1, V2); 6101 } 6102 6103 // Find the element from V2. 6104 unsigned HiIndex; 6105 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6106 int Val = PermMask[HiIndex]; 6107 if (Val < 0) 6108 continue; 6109 if (Val >= 4) 6110 break; 6111 } 6112 6113 Mask1[0] = PermMask[HiIndex]; 6114 Mask1[1] = -1; 6115 Mask1[2] = PermMask[HiIndex^1]; 6116 Mask1[3] = -1; 6117 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6118 6119 if (HiIndex >= 2) { 6120 Mask1[0] = PermMask[0]; 6121 Mask1[1] = PermMask[1]; 6122 Mask1[2] = HiIndex & 1 ? 6 : 4; 6123 Mask1[3] = HiIndex & 1 ? 4 : 6; 6124 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6125 } 6126 6127 Mask1[0] = HiIndex & 1 ? 2 : 0; 6128 Mask1[1] = HiIndex & 1 ? 0 : 2; 6129 Mask1[2] = PermMask[2]; 6130 Mask1[3] = PermMask[3]; 6131 if (Mask1[2] >= 0) 6132 Mask1[2] += 4; 6133 if (Mask1[3] >= 0) 6134 Mask1[3] += 4; 6135 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6136 } 6137 6138 // Break it into (shuffle shuffle_hi, shuffle_lo). 6139 int LoMask[] = { -1, -1, -1, -1 }; 6140 int HiMask[] = { -1, -1, -1, -1 }; 6141 6142 int *MaskPtr = LoMask; 6143 unsigned MaskIdx = 0; 6144 unsigned LoIdx = 0; 6145 unsigned HiIdx = 2; 6146 for (unsigned i = 0; i != 4; ++i) { 6147 if (i == 2) { 6148 MaskPtr = HiMask; 6149 MaskIdx = 1; 6150 LoIdx = 0; 6151 HiIdx = 2; 6152 } 6153 int Idx = PermMask[i]; 6154 if (Idx < 0) { 6155 Locs[i] = std::make_pair(-1, -1); 6156 } else if (Idx < 4) { 6157 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6158 MaskPtr[LoIdx] = Idx; 6159 LoIdx++; 6160 } else { 6161 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6162 MaskPtr[HiIdx] = Idx; 6163 HiIdx++; 6164 } 6165 } 6166 6167 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6168 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6169 int MaskOps[] = { -1, -1, -1, -1 }; 6170 for (unsigned i = 0; i != 4; ++i) 6171 if (Locs[i].first != -1) 6172 MaskOps[i] = Locs[i].first * 4 + Locs[i].second; 6173 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6174} 6175 6176static bool MayFoldVectorLoad(SDValue V) { 6177 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6178 V = V.getOperand(0); 6179 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6180 V = V.getOperand(0); 6181 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6182 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6183 // BUILD_VECTOR (load), undef 6184 V = V.getOperand(0); 6185 if (MayFoldLoad(V)) 6186 return true; 6187 return false; 6188} 6189 6190// FIXME: the version above should always be used. Since there's 6191// a bug where several vector shuffles can't be folded because the 6192// DAG is not updated during lowering and a node claims to have two 6193// uses while it only has one, use this version, and let isel match 6194// another instruction if the load really happens to have more than 6195// one use. Remove this version after this bug get fixed. 6196// rdar://8434668, PR8156 6197static bool RelaxedMayFoldVectorLoad(SDValue V) { 6198 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6199 V = V.getOperand(0); 6200 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6201 V = V.getOperand(0); 6202 if (ISD::isNormalLoad(V.getNode())) 6203 return true; 6204 return false; 6205} 6206 6207static 6208SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6209 EVT VT = Op.getValueType(); 6210 6211 // Canonizalize to v2f64. 6212 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6213 return DAG.getNode(ISD::BITCAST, dl, VT, 6214 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6215 V1, DAG)); 6216} 6217 6218static 6219SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6220 bool HasSSE2) { 6221 SDValue V1 = Op.getOperand(0); 6222 SDValue V2 = Op.getOperand(1); 6223 EVT VT = Op.getValueType(); 6224 6225 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6226 6227 if (HasSSE2 && VT == MVT::v2f64) 6228 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6229 6230 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6231 return DAG.getNode(ISD::BITCAST, dl, VT, 6232 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6233 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6234 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6235} 6236 6237static 6238SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6239 SDValue V1 = Op.getOperand(0); 6240 SDValue V2 = Op.getOperand(1); 6241 EVT VT = Op.getValueType(); 6242 6243 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6244 "unsupported shuffle type"); 6245 6246 if (V2.getOpcode() == ISD::UNDEF) 6247 V2 = V1; 6248 6249 // v4i32 or v4f32 6250 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6251} 6252 6253static 6254SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6255 SDValue V1 = Op.getOperand(0); 6256 SDValue V2 = Op.getOperand(1); 6257 EVT VT = Op.getValueType(); 6258 unsigned NumElems = VT.getVectorNumElements(); 6259 6260 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6261 // operand of these instructions is only memory, so check if there's a 6262 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6263 // same masks. 6264 bool CanFoldLoad = false; 6265 6266 // Trivial case, when V2 comes from a load. 6267 if (MayFoldVectorLoad(V2)) 6268 CanFoldLoad = true; 6269 6270 // When V1 is a load, it can be folded later into a store in isel, example: 6271 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6272 // turns into: 6273 // (MOVLPSmr addr:$src1, VR128:$src2) 6274 // So, recognize this potential and also use MOVLPS or MOVLPD 6275 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6276 CanFoldLoad = true; 6277 6278 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6279 if (CanFoldLoad) { 6280 if (HasSSE2 && NumElems == 2) 6281 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6282 6283 if (NumElems == 4) 6284 // If we don't care about the second element, procede to use movss. 6285 if (SVOp->getMaskElt(1) != -1) 6286 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6287 } 6288 6289 // movl and movlp will both match v2i64, but v2i64 is never matched by 6290 // movl earlier because we make it strict to avoid messing with the movlp load 6291 // folding logic (see the code above getMOVLP call). Match it here then, 6292 // this is horrible, but will stay like this until we move all shuffle 6293 // matching to x86 specific nodes. Note that for the 1st condition all 6294 // types are matched with movsd. 6295 if (HasSSE2) { 6296 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6297 // as to remove this logic from here, as much as possible 6298 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT)) 6299 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6300 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6301 } 6302 6303 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6304 6305 // Invert the operand order and use SHUFPS to match it. 6306 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6307 getShuffleSHUFImmediate(SVOp), DAG); 6308} 6309 6310SDValue 6311X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const { 6312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6313 EVT VT = Op.getValueType(); 6314 DebugLoc dl = Op.getDebugLoc(); 6315 SDValue V1 = Op.getOperand(0); 6316 SDValue V2 = Op.getOperand(1); 6317 6318 if (isZeroShuffle(SVOp)) 6319 return getZeroVector(VT, Subtarget, DAG, dl); 6320 6321 // Handle splat operations 6322 if (SVOp->isSplat()) { 6323 unsigned NumElem = VT.getVectorNumElements(); 6324 int Size = VT.getSizeInBits(); 6325 6326 // Use vbroadcast whenever the splat comes from a foldable load 6327 SDValue Broadcast = LowerVectorBroadcast(Op, DAG); 6328 if (Broadcast.getNode()) 6329 return Broadcast; 6330 6331 // Handle splats by matching through known shuffle masks 6332 if ((Size == 128 && NumElem <= 4) || 6333 (Size == 256 && NumElem < 8)) 6334 return SDValue(); 6335 6336 // All remaning splats are promoted to target supported vector shuffles. 6337 return PromoteSplat(SVOp, DAG); 6338 } 6339 6340 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6341 // do it! 6342 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6343 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6344 if (NewOp.getNode()) 6345 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6346 } else if ((VT == MVT::v4i32 || 6347 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6348 // FIXME: Figure out a cleaner way to do this. 6349 // Try to make use of movq to zero out the top part. 6350 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6351 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6352 if (NewOp.getNode()) { 6353 EVT NewVT = NewOp.getValueType(); 6354 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), 6355 NewVT, true, false)) 6356 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), 6357 DAG, Subtarget, dl); 6358 } 6359 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6360 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6361 if (NewOp.getNode()) { 6362 EVT NewVT = NewOp.getValueType(); 6363 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT)) 6364 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), 6365 DAG, Subtarget, dl); 6366 } 6367 } 6368 } 6369 return SDValue(); 6370} 6371 6372SDValue 6373X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6375 SDValue V1 = Op.getOperand(0); 6376 SDValue V2 = Op.getOperand(1); 6377 EVT VT = Op.getValueType(); 6378 DebugLoc dl = Op.getDebugLoc(); 6379 unsigned NumElems = VT.getVectorNumElements(); 6380 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6381 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6382 bool V1IsSplat = false; 6383 bool V2IsSplat = false; 6384 bool HasSSE2 = Subtarget->hasSSE2(); 6385 bool HasAVX = Subtarget->hasAVX(); 6386 bool HasAVX2 = Subtarget->hasAVX2(); 6387 MachineFunction &MF = DAG.getMachineFunction(); 6388 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6389 6390 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6391 6392 if (V1IsUndef && V2IsUndef) 6393 return DAG.getUNDEF(VT); 6394 6395 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6396 6397 // Vector shuffle lowering takes 3 steps: 6398 // 6399 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6400 // narrowing and commutation of operands should be handled. 6401 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6402 // shuffle nodes. 6403 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6404 // so the shuffle can be broken into other shuffles and the legalizer can 6405 // try the lowering again. 6406 // 6407 // The general idea is that no vector_shuffle operation should be left to 6408 // be matched during isel, all of them must be converted to a target specific 6409 // node here. 6410 6411 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6412 // narrowing and commutation of operands should be handled. The actual code 6413 // doesn't include all of those, work in progress... 6414 SDValue NewOp = NormalizeVectorShuffle(Op, DAG); 6415 if (NewOp.getNode()) 6416 return NewOp; 6417 6418 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end()); 6419 6420 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6421 // unpckh_undef). Only use pshufd if speed is more important than size. 6422 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6423 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6424 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6425 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6426 6427 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() && 6428 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6429 return getMOVDDup(Op, dl, V1, DAG); 6430 6431 if (isMOVHLPS_v_undef_Mask(M, VT)) 6432 return getMOVHighToLow(Op, dl, DAG); 6433 6434 // Use to match splats 6435 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef && 6436 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6437 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6438 6439 if (isPSHUFDMask(M, VT)) { 6440 // The actual implementation will match the mask in the if above and then 6441 // during isel it can match several different instructions, not only pshufd 6442 // as its name says, sad but true, emulate the behavior for now... 6443 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6444 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6445 6446 unsigned TargetMask = getShuffleSHUFImmediate(SVOp); 6447 6448 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64)) 6449 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG); 6450 6451 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6452 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6453 6454 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6455 TargetMask, DAG); 6456 } 6457 6458 // Check if this can be converted into a logical shift. 6459 bool isLeft = false; 6460 unsigned ShAmt = 0; 6461 SDValue ShVal; 6462 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6463 if (isShift && ShVal.hasOneUse()) { 6464 // If the shifted value has multiple uses, it may be cheaper to use 6465 // v_set0 + movlhps or movhlps, etc. 6466 EVT EltVT = VT.getVectorElementType(); 6467 ShAmt *= EltVT.getSizeInBits(); 6468 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6469 } 6470 6471 if (isMOVLMask(M, VT)) { 6472 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6473 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6474 if (!isMOVLPMask(M, VT)) { 6475 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6476 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6477 6478 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6479 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6480 } 6481 } 6482 6483 // FIXME: fold these into legal mask. 6484 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2)) 6485 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6486 6487 if (isMOVHLPSMask(M, VT)) 6488 return getMOVHighToLow(Op, dl, DAG); 6489 6490 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget)) 6491 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6492 6493 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget)) 6494 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6495 6496 if (isMOVLPMask(M, VT)) 6497 return getMOVLP(Op, dl, DAG, HasSSE2); 6498 6499 if (ShouldXformToMOVHLPS(M, VT) || 6500 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT)) 6501 return CommuteVectorShuffle(SVOp, DAG); 6502 6503 if (isShift) { 6504 // No better options. Use a vshldq / vsrldq. 6505 EVT EltVT = VT.getVectorElementType(); 6506 ShAmt *= EltVT.getSizeInBits(); 6507 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6508 } 6509 6510 bool Commuted = false; 6511 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6512 // 1,1,1,1 -> v8i16 though. 6513 V1IsSplat = isSplatVector(V1.getNode()); 6514 V2IsSplat = isSplatVector(V2.getNode()); 6515 6516 // Canonicalize the splat or undef, if present, to be on the RHS. 6517 if (!V2IsUndef && V1IsSplat && !V2IsSplat) { 6518 CommuteVectorShuffleMask(M, NumElems); 6519 std::swap(V1, V2); 6520 std::swap(V1IsSplat, V2IsSplat); 6521 Commuted = true; 6522 } 6523 6524 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6525 // Shuffling low element of v1 into undef, just return v1. 6526 if (V2IsUndef) 6527 return V1; 6528 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6529 // the instruction selector will not match, so get a canonical MOVL with 6530 // swapped operands to undo the commute. 6531 return getMOVL(DAG, dl, VT, V2, V1); 6532 } 6533 6534 if (isUNPCKLMask(M, VT, HasAVX2)) 6535 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6536 6537 if (isUNPCKHMask(M, VT, HasAVX2)) 6538 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6539 6540 if (V2IsSplat) { 6541 // Normalize mask so all entries that point to V2 points to its first 6542 // element then try to match unpck{h|l} again. If match, return a 6543 // new vector_shuffle with the corrected mask.p 6544 SmallVector<int, 8> NewMask(M.begin(), M.end()); 6545 NormalizeMask(NewMask, NumElems); 6546 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) 6547 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6548 if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) 6549 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6550 } 6551 6552 if (Commuted) { 6553 // Commute is back and try unpck* again. 6554 // FIXME: this seems wrong. 6555 CommuteVectorShuffleMask(M, NumElems); 6556 std::swap(V1, V2); 6557 std::swap(V1IsSplat, V2IsSplat); 6558 Commuted = false; 6559 6560 if (isUNPCKLMask(M, VT, HasAVX2)) 6561 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6562 6563 if (isUNPCKHMask(M, VT, HasAVX2)) 6564 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6565 } 6566 6567 // Normalize the node to match x86 shuffle ops if needed 6568 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6569 return CommuteVectorShuffle(SVOp, DAG); 6570 6571 // The checks below are all present in isShuffleMaskLegal, but they are 6572 // inlined here right now to enable us to directly emit target specific 6573 // nodes, and remove one by one until they don't return Op anymore. 6574 6575 if (isPALIGNRMask(M, VT, Subtarget)) 6576 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6577 getShufflePALIGNRImmediate(SVOp), 6578 DAG); 6579 6580 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6581 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6582 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6583 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6584 } 6585 6586 if (isPSHUFHWMask(M, VT)) 6587 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6588 getShufflePSHUFHWImmediate(SVOp), 6589 DAG); 6590 6591 if (isPSHUFLWMask(M, VT)) 6592 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6593 getShufflePSHUFLWImmediate(SVOp), 6594 DAG); 6595 6596 if (isSHUFPMask(M, VT, HasAVX)) 6597 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6598 getShuffleSHUFImmediate(SVOp), DAG); 6599 6600 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6601 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6602 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6603 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6604 6605 //===--------------------------------------------------------------------===// 6606 // Generate target specific nodes for 128 or 256-bit shuffles only 6607 // supported in the AVX instruction set. 6608 // 6609 6610 // Handle VMOVDDUPY permutations 6611 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6612 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6613 6614 // Handle VPERMILPS/D* permutations 6615 if (isVPERMILPMask(M, VT, HasAVX)) { 6616 if (HasAVX2 && VT == MVT::v8i32) 6617 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, 6618 getShuffleSHUFImmediate(SVOp), DAG); 6619 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6620 getShuffleSHUFImmediate(SVOp), DAG); 6621 } 6622 6623 // Handle VPERM2F128/VPERM2I128 permutations 6624 if (isVPERM2X128Mask(M, VT, HasAVX)) 6625 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6626 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6627 6628 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG); 6629 if (BlendOp.getNode()) 6630 return BlendOp; 6631 6632 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) { 6633 SmallVector<SDValue, 8> permclMask; 6634 for (unsigned i = 0; i != 8; ++i) { 6635 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32)); 6636 } 6637 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, 6638 &permclMask[0], 8); 6639 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32 6640 return DAG.getNode(X86ISD::VPERMV, dl, VT, 6641 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1); 6642 } 6643 6644 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64)) 6645 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, 6646 getShuffleCLImmediate(SVOp), DAG); 6647 6648 6649 //===--------------------------------------------------------------------===// 6650 // Since no target specific shuffle was selected for this generic one, 6651 // lower it into other known shuffles. FIXME: this isn't true yet, but 6652 // this is the plan. 6653 // 6654 6655 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6656 if (VT == MVT::v8i16) { 6657 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6658 if (NewOp.getNode()) 6659 return NewOp; 6660 } 6661 6662 if (VT == MVT::v16i8) { 6663 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6664 if (NewOp.getNode()) 6665 return NewOp; 6666 } 6667 6668 // Handle all 128-bit wide vectors with 4 elements, and match them with 6669 // several different shuffle types. 6670 if (NumElems == 4 && VT.getSizeInBits() == 128) 6671 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6672 6673 // Handle general 256-bit shuffles 6674 if (VT.is256BitVector()) 6675 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6676 6677 return SDValue(); 6678} 6679 6680SDValue 6681X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6682 SelectionDAG &DAG) const { 6683 EVT VT = Op.getValueType(); 6684 DebugLoc dl = Op.getDebugLoc(); 6685 6686 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6687 return SDValue(); 6688 6689 if (VT.getSizeInBits() == 8) { 6690 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6691 Op.getOperand(0), Op.getOperand(1)); 6692 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6693 DAG.getValueType(VT)); 6694 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6695 } 6696 6697 if (VT.getSizeInBits() == 16) { 6698 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6699 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6700 if (Idx == 0) 6701 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6702 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6703 DAG.getNode(ISD::BITCAST, dl, 6704 MVT::v4i32, 6705 Op.getOperand(0)), 6706 Op.getOperand(1))); 6707 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6708 Op.getOperand(0), Op.getOperand(1)); 6709 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6710 DAG.getValueType(VT)); 6711 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6712 } 6713 6714 if (VT == MVT::f32) { 6715 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6716 // the result back to FR32 register. It's only worth matching if the 6717 // result has a single use which is a store or a bitcast to i32. And in 6718 // the case of a store, it's not worth it if the index is a constant 0, 6719 // because a MOVSSmr can be used instead, which is smaller and faster. 6720 if (!Op.hasOneUse()) 6721 return SDValue(); 6722 SDNode *User = *Op.getNode()->use_begin(); 6723 if ((User->getOpcode() != ISD::STORE || 6724 (isa<ConstantSDNode>(Op.getOperand(1)) && 6725 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6726 (User->getOpcode() != ISD::BITCAST || 6727 User->getValueType(0) != MVT::i32)) 6728 return SDValue(); 6729 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6730 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6731 Op.getOperand(0)), 6732 Op.getOperand(1)); 6733 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6734 } 6735 6736 if (VT == MVT::i32 || VT == MVT::i64) { 6737 // ExtractPS/pextrq works with constant index. 6738 if (isa<ConstantSDNode>(Op.getOperand(1))) 6739 return Op; 6740 } 6741 return SDValue(); 6742} 6743 6744 6745SDValue 6746X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6747 SelectionDAG &DAG) const { 6748 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6749 return SDValue(); 6750 6751 SDValue Vec = Op.getOperand(0); 6752 EVT VecVT = Vec.getValueType(); 6753 6754 // If this is a 256-bit vector result, first extract the 128-bit vector and 6755 // then extract the element from the 128-bit vector. 6756 if (VecVT.getSizeInBits() == 256) { 6757 DebugLoc dl = Op.getNode()->getDebugLoc(); 6758 unsigned NumElems = VecVT.getVectorNumElements(); 6759 SDValue Idx = Op.getOperand(1); 6760 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6761 6762 // Get the 128-bit vector. 6763 bool Upper = IdxVal >= NumElems/2; 6764 Vec = Extract128BitVector(Vec, Upper ? NumElems/2 : 0, DAG, dl); 6765 6766 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6767 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6768 } 6769 6770 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6771 6772 if (Subtarget->hasSSE41()) { 6773 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6774 if (Res.getNode()) 6775 return Res; 6776 } 6777 6778 EVT VT = Op.getValueType(); 6779 DebugLoc dl = Op.getDebugLoc(); 6780 // TODO: handle v16i8. 6781 if (VT.getSizeInBits() == 16) { 6782 SDValue Vec = Op.getOperand(0); 6783 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6784 if (Idx == 0) 6785 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6786 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6787 DAG.getNode(ISD::BITCAST, dl, 6788 MVT::v4i32, Vec), 6789 Op.getOperand(1))); 6790 // Transform it so it match pextrw which produces a 32-bit result. 6791 EVT EltVT = MVT::i32; 6792 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6793 Op.getOperand(0), Op.getOperand(1)); 6794 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6795 DAG.getValueType(VT)); 6796 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6797 } 6798 6799 if (VT.getSizeInBits() == 32) { 6800 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6801 if (Idx == 0) 6802 return Op; 6803 6804 // SHUFPS the element to the lowest double word, then movss. 6805 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6806 EVT VVT = Op.getOperand(0).getValueType(); 6807 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6808 DAG.getUNDEF(VVT), Mask); 6809 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6810 DAG.getIntPtrConstant(0)); 6811 } 6812 6813 if (VT.getSizeInBits() == 64) { 6814 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6815 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6816 // to match extract_elt for f64. 6817 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6818 if (Idx == 0) 6819 return Op; 6820 6821 // UNPCKHPD the element to the lowest double word, then movsd. 6822 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6823 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6824 int Mask[2] = { 1, -1 }; 6825 EVT VVT = Op.getOperand(0).getValueType(); 6826 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6827 DAG.getUNDEF(VVT), Mask); 6828 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6829 DAG.getIntPtrConstant(0)); 6830 } 6831 6832 return SDValue(); 6833} 6834 6835SDValue 6836X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6837 SelectionDAG &DAG) const { 6838 EVT VT = Op.getValueType(); 6839 EVT EltVT = VT.getVectorElementType(); 6840 DebugLoc dl = Op.getDebugLoc(); 6841 6842 SDValue N0 = Op.getOperand(0); 6843 SDValue N1 = Op.getOperand(1); 6844 SDValue N2 = Op.getOperand(2); 6845 6846 if (VT.getSizeInBits() == 256) 6847 return SDValue(); 6848 6849 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6850 isa<ConstantSDNode>(N2)) { 6851 unsigned Opc; 6852 if (VT == MVT::v8i16) 6853 Opc = X86ISD::PINSRW; 6854 else if (VT == MVT::v16i8) 6855 Opc = X86ISD::PINSRB; 6856 else 6857 Opc = X86ISD::PINSRB; 6858 6859 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6860 // argument. 6861 if (N1.getValueType() != MVT::i32) 6862 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6863 if (N2.getValueType() != MVT::i32) 6864 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6865 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6866 } 6867 6868 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6869 // Bits [7:6] of the constant are the source select. This will always be 6870 // zero here. The DAG Combiner may combine an extract_elt index into these 6871 // bits. For example (insert (extract, 3), 2) could be matched by putting 6872 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6873 // Bits [5:4] of the constant are the destination select. This is the 6874 // value of the incoming immediate. 6875 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6876 // combine either bitwise AND or insert of float 0.0 to set these bits. 6877 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6878 // Create this as a scalar to vector.. 6879 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6880 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6881 } 6882 6883 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) { 6884 // PINSR* works with constant index. 6885 return Op; 6886 } 6887 return SDValue(); 6888} 6889 6890SDValue 6891X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6892 EVT VT = Op.getValueType(); 6893 EVT EltVT = VT.getVectorElementType(); 6894 6895 DebugLoc dl = Op.getDebugLoc(); 6896 SDValue N0 = Op.getOperand(0); 6897 SDValue N1 = Op.getOperand(1); 6898 SDValue N2 = Op.getOperand(2); 6899 6900 // If this is a 256-bit vector result, first extract the 128-bit vector, 6901 // insert the element into the extracted half and then place it back. 6902 if (VT.getSizeInBits() == 256) { 6903 if (!isa<ConstantSDNode>(N2)) 6904 return SDValue(); 6905 6906 // Get the desired 128-bit vector half. 6907 unsigned NumElems = VT.getVectorNumElements(); 6908 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6909 bool Upper = IdxVal >= NumElems/2; 6910 unsigned Ins128Idx = Upper ? NumElems/2 : 0; 6911 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6912 6913 // Insert the element into the desired half. 6914 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6915 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6916 6917 // Insert the changed part back to the 256-bit vector 6918 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6919 } 6920 6921 if (Subtarget->hasSSE41()) 6922 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6923 6924 if (EltVT == MVT::i8) 6925 return SDValue(); 6926 6927 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6928 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6929 // as its second argument. 6930 if (N1.getValueType() != MVT::i32) 6931 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6932 if (N2.getValueType() != MVT::i32) 6933 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6934 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6935 } 6936 return SDValue(); 6937} 6938 6939SDValue 6940X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6941 LLVMContext *Context = DAG.getContext(); 6942 DebugLoc dl = Op.getDebugLoc(); 6943 EVT OpVT = Op.getValueType(); 6944 6945 // If this is a 256-bit vector result, first insert into a 128-bit 6946 // vector and then insert into the 256-bit vector. 6947 if (OpVT.getSizeInBits() > 128) { 6948 // Insert into a 128-bit vector. 6949 EVT VT128 = EVT::getVectorVT(*Context, 6950 OpVT.getVectorElementType(), 6951 OpVT.getVectorNumElements() / 2); 6952 6953 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 6954 6955 // Insert the 128-bit vector. 6956 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl); 6957 } 6958 6959 if (Op.getValueType() == MVT::v1i64 && 6960 Op.getOperand(0).getValueType() == MVT::i64) 6961 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 6962 6963 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 6964 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 6965 "Expected an SSE type!"); 6966 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 6967 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 6968} 6969 6970// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 6971// a simple subregister reference or explicit instructions to grab 6972// upper bits of a vector. 6973SDValue 6974X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6975 if (Subtarget->hasAVX()) { 6976 DebugLoc dl = Op.getNode()->getDebugLoc(); 6977 SDValue Vec = Op.getNode()->getOperand(0); 6978 SDValue Idx = Op.getNode()->getOperand(1); 6979 6980 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 && 6981 Vec.getNode()->getValueType(0).getSizeInBits() == 256 && 6982 isa<ConstantSDNode>(Idx)) { 6983 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6984 return Extract128BitVector(Vec, IdxVal, DAG, dl); 6985 } 6986 } 6987 return SDValue(); 6988} 6989 6990// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 6991// simple superregister reference or explicit instructions to insert 6992// the upper bits of a vector. 6993SDValue 6994X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 6995 if (Subtarget->hasAVX()) { 6996 DebugLoc dl = Op.getNode()->getDebugLoc(); 6997 SDValue Vec = Op.getNode()->getOperand(0); 6998 SDValue SubVec = Op.getNode()->getOperand(1); 6999 SDValue Idx = Op.getNode()->getOperand(2); 7000 7001 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 && 7002 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 && 7003 isa<ConstantSDNode>(Idx)) { 7004 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 7005 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); 7006 } 7007 } 7008 return SDValue(); 7009} 7010 7011// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7012// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7013// one of the above mentioned nodes. It has to be wrapped because otherwise 7014// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7015// be used to form addressing mode. These wrapped nodes will be selected 7016// into MOV32ri. 7017SDValue 7018X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7019 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7020 7021 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7022 // global base reg. 7023 unsigned char OpFlag = 0; 7024 unsigned WrapperKind = X86ISD::Wrapper; 7025 CodeModel::Model M = getTargetMachine().getCodeModel(); 7026 7027 if (Subtarget->isPICStyleRIPRel() && 7028 (M == CodeModel::Small || M == CodeModel::Kernel)) 7029 WrapperKind = X86ISD::WrapperRIP; 7030 else if (Subtarget->isPICStyleGOT()) 7031 OpFlag = X86II::MO_GOTOFF; 7032 else if (Subtarget->isPICStyleStubPIC()) 7033 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7034 7035 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7036 CP->getAlignment(), 7037 CP->getOffset(), OpFlag); 7038 DebugLoc DL = CP->getDebugLoc(); 7039 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7040 // With PIC, the address is actually $g + Offset. 7041 if (OpFlag) { 7042 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7043 DAG.getNode(X86ISD::GlobalBaseReg, 7044 DebugLoc(), getPointerTy()), 7045 Result); 7046 } 7047 7048 return Result; 7049} 7050 7051SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7052 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7053 7054 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7055 // global base reg. 7056 unsigned char OpFlag = 0; 7057 unsigned WrapperKind = X86ISD::Wrapper; 7058 CodeModel::Model M = getTargetMachine().getCodeModel(); 7059 7060 if (Subtarget->isPICStyleRIPRel() && 7061 (M == CodeModel::Small || M == CodeModel::Kernel)) 7062 WrapperKind = X86ISD::WrapperRIP; 7063 else if (Subtarget->isPICStyleGOT()) 7064 OpFlag = X86II::MO_GOTOFF; 7065 else if (Subtarget->isPICStyleStubPIC()) 7066 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7067 7068 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7069 OpFlag); 7070 DebugLoc DL = JT->getDebugLoc(); 7071 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7072 7073 // With PIC, the address is actually $g + Offset. 7074 if (OpFlag) 7075 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7076 DAG.getNode(X86ISD::GlobalBaseReg, 7077 DebugLoc(), getPointerTy()), 7078 Result); 7079 7080 return Result; 7081} 7082 7083SDValue 7084X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7085 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7086 7087 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7088 // global base reg. 7089 unsigned char OpFlag = 0; 7090 unsigned WrapperKind = X86ISD::Wrapper; 7091 CodeModel::Model M = getTargetMachine().getCodeModel(); 7092 7093 if (Subtarget->isPICStyleRIPRel() && 7094 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7095 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7096 OpFlag = X86II::MO_GOTPCREL; 7097 WrapperKind = X86ISD::WrapperRIP; 7098 } else if (Subtarget->isPICStyleGOT()) { 7099 OpFlag = X86II::MO_GOT; 7100 } else if (Subtarget->isPICStyleStubPIC()) { 7101 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7102 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7103 OpFlag = X86II::MO_DARWIN_NONLAZY; 7104 } 7105 7106 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7107 7108 DebugLoc DL = Op.getDebugLoc(); 7109 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7110 7111 7112 // With PIC, the address is actually $g + Offset. 7113 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7114 !Subtarget->is64Bit()) { 7115 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7116 DAG.getNode(X86ISD::GlobalBaseReg, 7117 DebugLoc(), getPointerTy()), 7118 Result); 7119 } 7120 7121 // For symbols that require a load from a stub to get the address, emit the 7122 // load. 7123 if (isGlobalStubReference(OpFlag)) 7124 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7125 MachinePointerInfo::getGOT(), false, false, false, 0); 7126 7127 return Result; 7128} 7129 7130SDValue 7131X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7132 // Create the TargetBlockAddressAddress node. 7133 unsigned char OpFlags = 7134 Subtarget->ClassifyBlockAddressReference(); 7135 CodeModel::Model M = getTargetMachine().getCodeModel(); 7136 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7137 DebugLoc dl = Op.getDebugLoc(); 7138 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7139 /*isTarget=*/true, OpFlags); 7140 7141 if (Subtarget->isPICStyleRIPRel() && 7142 (M == CodeModel::Small || M == CodeModel::Kernel)) 7143 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7144 else 7145 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7146 7147 // With PIC, the address is actually $g + Offset. 7148 if (isGlobalRelativeToPICBase(OpFlags)) { 7149 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7150 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7151 Result); 7152 } 7153 7154 return Result; 7155} 7156 7157SDValue 7158X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7159 int64_t Offset, 7160 SelectionDAG &DAG) const { 7161 // Create the TargetGlobalAddress node, folding in the constant 7162 // offset if it is legal. 7163 unsigned char OpFlags = 7164 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7165 CodeModel::Model M = getTargetMachine().getCodeModel(); 7166 SDValue Result; 7167 if (OpFlags == X86II::MO_NO_FLAG && 7168 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7169 // A direct static reference to a global. 7170 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7171 Offset = 0; 7172 } else { 7173 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7174 } 7175 7176 if (Subtarget->isPICStyleRIPRel() && 7177 (M == CodeModel::Small || M == CodeModel::Kernel)) 7178 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7179 else 7180 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7181 7182 // With PIC, the address is actually $g + Offset. 7183 if (isGlobalRelativeToPICBase(OpFlags)) { 7184 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7185 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7186 Result); 7187 } 7188 7189 // For globals that require a load from a stub to get the address, emit the 7190 // load. 7191 if (isGlobalStubReference(OpFlags)) 7192 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7193 MachinePointerInfo::getGOT(), false, false, false, 0); 7194 7195 // If there was a non-zero offset that we didn't fold, create an explicit 7196 // addition for it. 7197 if (Offset != 0) 7198 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7199 DAG.getConstant(Offset, getPointerTy())); 7200 7201 return Result; 7202} 7203 7204SDValue 7205X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7206 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7207 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7208 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7209} 7210 7211static SDValue 7212GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7213 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7214 unsigned char OperandFlags) { 7215 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7216 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7217 DebugLoc dl = GA->getDebugLoc(); 7218 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7219 GA->getValueType(0), 7220 GA->getOffset(), 7221 OperandFlags); 7222 if (InFlag) { 7223 SDValue Ops[] = { Chain, TGA, *InFlag }; 7224 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7225 } else { 7226 SDValue Ops[] = { Chain, TGA }; 7227 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7228 } 7229 7230 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7231 MFI->setAdjustsStack(true); 7232 7233 SDValue Flag = Chain.getValue(1); 7234 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7235} 7236 7237// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7238static SDValue 7239LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7240 const EVT PtrVT) { 7241 SDValue InFlag; 7242 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7243 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7244 DAG.getNode(X86ISD::GlobalBaseReg, 7245 DebugLoc(), PtrVT), InFlag); 7246 InFlag = Chain.getValue(1); 7247 7248 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7249} 7250 7251// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7252static SDValue 7253LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7254 const EVT PtrVT) { 7255 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7256 X86::RAX, X86II::MO_TLSGD); 7257} 7258 7259// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7260// "local exec" model. 7261static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7262 const EVT PtrVT, TLSModel::Model model, 7263 bool is64Bit) { 7264 DebugLoc dl = GA->getDebugLoc(); 7265 7266 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7267 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7268 is64Bit ? 257 : 256)); 7269 7270 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7271 DAG.getIntPtrConstant(0), 7272 MachinePointerInfo(Ptr), 7273 false, false, false, 0); 7274 7275 unsigned char OperandFlags = 0; 7276 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7277 // initialexec. 7278 unsigned WrapperKind = X86ISD::Wrapper; 7279 if (model == TLSModel::LocalExec) { 7280 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7281 } else if (is64Bit) { 7282 assert(model == TLSModel::InitialExec); 7283 OperandFlags = X86II::MO_GOTTPOFF; 7284 WrapperKind = X86ISD::WrapperRIP; 7285 } else { 7286 assert(model == TLSModel::InitialExec); 7287 OperandFlags = X86II::MO_INDNTPOFF; 7288 } 7289 7290 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7291 // exec) 7292 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7293 GA->getValueType(0), 7294 GA->getOffset(), OperandFlags); 7295 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7296 7297 if (model == TLSModel::InitialExec) 7298 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7299 MachinePointerInfo::getGOT(), false, false, false, 0); 7300 7301 // The address of the thread local variable is the add of the thread 7302 // pointer with the offset of the variable. 7303 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7304} 7305 7306SDValue 7307X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7308 7309 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7310 const GlobalValue *GV = GA->getGlobal(); 7311 7312 if (Subtarget->isTargetELF()) { 7313 // TODO: implement the "local dynamic" model 7314 // TODO: implement the "initial exec"model for pic executables 7315 7316 // If GV is an alias then use the aliasee for determining 7317 // thread-localness. 7318 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7319 GV = GA->resolveAliasedGlobal(false); 7320 7321 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 7322 7323 switch (model) { 7324 case TLSModel::GeneralDynamic: 7325 case TLSModel::LocalDynamic: // not implemented 7326 if (Subtarget->is64Bit()) 7327 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7328 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7329 7330 case TLSModel::InitialExec: 7331 case TLSModel::LocalExec: 7332 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7333 Subtarget->is64Bit()); 7334 } 7335 llvm_unreachable("Unknown TLS model."); 7336 } 7337 7338 if (Subtarget->isTargetDarwin()) { 7339 // Darwin only has one model of TLS. Lower to that. 7340 unsigned char OpFlag = 0; 7341 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7342 X86ISD::WrapperRIP : X86ISD::Wrapper; 7343 7344 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7345 // global base reg. 7346 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7347 !Subtarget->is64Bit(); 7348 if (PIC32) 7349 OpFlag = X86II::MO_TLVP_PIC_BASE; 7350 else 7351 OpFlag = X86II::MO_TLVP; 7352 DebugLoc DL = Op.getDebugLoc(); 7353 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7354 GA->getValueType(0), 7355 GA->getOffset(), OpFlag); 7356 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7357 7358 // With PIC32, the address is actually $g + Offset. 7359 if (PIC32) 7360 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7361 DAG.getNode(X86ISD::GlobalBaseReg, 7362 DebugLoc(), getPointerTy()), 7363 Offset); 7364 7365 // Lowering the machine isd will make sure everything is in the right 7366 // location. 7367 SDValue Chain = DAG.getEntryNode(); 7368 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7369 SDValue Args[] = { Chain, Offset }; 7370 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7371 7372 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7373 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7374 MFI->setAdjustsStack(true); 7375 7376 // And our return value (tls address) is in the standard call return value 7377 // location. 7378 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7379 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7380 Chain.getValue(1)); 7381 } 7382 7383 if (Subtarget->isTargetWindows()) { 7384 // Just use the implicit TLS architecture 7385 // Need to generate someting similar to: 7386 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage 7387 // ; from TEB 7388 // mov ecx, dword [rel _tls_index]: Load index (from C runtime) 7389 // mov rcx, qword [rdx+rcx*8] 7390 // mov eax, .tls$:tlsvar 7391 // [rax+rcx] contains the address 7392 // Windows 64bit: gs:0x58 7393 // Windows 32bit: fs:__tls_array 7394 7395 // If GV is an alias then use the aliasee for determining 7396 // thread-localness. 7397 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7398 GV = GA->resolveAliasedGlobal(false); 7399 DebugLoc dl = GA->getDebugLoc(); 7400 SDValue Chain = DAG.getEntryNode(); 7401 7402 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or 7403 // %gs:0x58 (64-bit). 7404 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit() 7405 ? Type::getInt8PtrTy(*DAG.getContext(), 7406 256) 7407 : Type::getInt32PtrTy(*DAG.getContext(), 7408 257)); 7409 7410 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, 7411 Subtarget->is64Bit() 7412 ? DAG.getIntPtrConstant(0x58) 7413 : DAG.getExternalSymbol("_tls_array", 7414 getPointerTy()), 7415 MachinePointerInfo(Ptr), 7416 false, false, false, 0); 7417 7418 // Load the _tls_index variable 7419 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy()); 7420 if (Subtarget->is64Bit()) 7421 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, 7422 IDX, MachinePointerInfo(), MVT::i32, 7423 false, false, 0); 7424 else 7425 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(), 7426 false, false, false, 0); 7427 7428 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), 7429 getPointerTy()); 7430 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale); 7431 7432 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX); 7433 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(), 7434 false, false, false, 0); 7435 7436 // Get the offset of start of .tls section 7437 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7438 GA->getValueType(0), 7439 GA->getOffset(), X86II::MO_SECREL); 7440 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA); 7441 7442 // The address of the thread local variable is the add of the thread 7443 // pointer with the offset of the variable. 7444 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset); 7445 } 7446 7447 llvm_unreachable("TLS not implemented for this target."); 7448} 7449 7450 7451/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7452/// and take a 2 x i32 value to shift plus a shift amount. 7453SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7454 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7455 EVT VT = Op.getValueType(); 7456 unsigned VTBits = VT.getSizeInBits(); 7457 DebugLoc dl = Op.getDebugLoc(); 7458 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7459 SDValue ShOpLo = Op.getOperand(0); 7460 SDValue ShOpHi = Op.getOperand(1); 7461 SDValue ShAmt = Op.getOperand(2); 7462 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7463 DAG.getConstant(VTBits - 1, MVT::i8)) 7464 : DAG.getConstant(0, VT); 7465 7466 SDValue Tmp2, Tmp3; 7467 if (Op.getOpcode() == ISD::SHL_PARTS) { 7468 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7469 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7470 } else { 7471 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7472 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7473 } 7474 7475 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7476 DAG.getConstant(VTBits, MVT::i8)); 7477 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7478 AndNode, DAG.getConstant(0, MVT::i8)); 7479 7480 SDValue Hi, Lo; 7481 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7482 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7483 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7484 7485 if (Op.getOpcode() == ISD::SHL_PARTS) { 7486 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7487 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7488 } else { 7489 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7490 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7491 } 7492 7493 SDValue Ops[2] = { Lo, Hi }; 7494 return DAG.getMergeValues(Ops, 2, dl); 7495} 7496 7497SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7498 SelectionDAG &DAG) const { 7499 EVT SrcVT = Op.getOperand(0).getValueType(); 7500 7501 if (SrcVT.isVector()) 7502 return SDValue(); 7503 7504 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7505 "Unknown SINT_TO_FP to lower!"); 7506 7507 // These are really Legal; return the operand so the caller accepts it as 7508 // Legal. 7509 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7510 return Op; 7511 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7512 Subtarget->is64Bit()) { 7513 return Op; 7514 } 7515 7516 DebugLoc dl = Op.getDebugLoc(); 7517 unsigned Size = SrcVT.getSizeInBits()/8; 7518 MachineFunction &MF = DAG.getMachineFunction(); 7519 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7520 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7521 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7522 StackSlot, 7523 MachinePointerInfo::getFixedStack(SSFI), 7524 false, false, 0); 7525 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7526} 7527 7528SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7529 SDValue StackSlot, 7530 SelectionDAG &DAG) const { 7531 // Build the FILD 7532 DebugLoc DL = Op.getDebugLoc(); 7533 SDVTList Tys; 7534 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7535 if (useSSE) 7536 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7537 else 7538 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7539 7540 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7541 7542 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7543 MachineMemOperand *MMO; 7544 if (FI) { 7545 int SSFI = FI->getIndex(); 7546 MMO = 7547 DAG.getMachineFunction() 7548 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7549 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7550 } else { 7551 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7552 StackSlot = StackSlot.getOperand(1); 7553 } 7554 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7555 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7556 X86ISD::FILD, DL, 7557 Tys, Ops, array_lengthof(Ops), 7558 SrcVT, MMO); 7559 7560 if (useSSE) { 7561 Chain = Result.getValue(1); 7562 SDValue InFlag = Result.getValue(2); 7563 7564 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7565 // shouldn't be necessary except that RFP cannot be live across 7566 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7567 MachineFunction &MF = DAG.getMachineFunction(); 7568 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7569 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7570 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7571 Tys = DAG.getVTList(MVT::Other); 7572 SDValue Ops[] = { 7573 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7574 }; 7575 MachineMemOperand *MMO = 7576 DAG.getMachineFunction() 7577 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7578 MachineMemOperand::MOStore, SSFISize, SSFISize); 7579 7580 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7581 Ops, array_lengthof(Ops), 7582 Op.getValueType(), MMO); 7583 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7584 MachinePointerInfo::getFixedStack(SSFI), 7585 false, false, false, 0); 7586 } 7587 7588 return Result; 7589} 7590 7591// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7592SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7593 SelectionDAG &DAG) const { 7594 // This algorithm is not obvious. Here it is what we're trying to output: 7595 /* 7596 movq %rax, %xmm0 7597 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7598 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7599 #ifdef __SSE3__ 7600 haddpd %xmm0, %xmm0 7601 #else 7602 pshufd $0x4e, %xmm0, %xmm1 7603 addpd %xmm1, %xmm0 7604 #endif 7605 */ 7606 7607 DebugLoc dl = Op.getDebugLoc(); 7608 LLVMContext *Context = DAG.getContext(); 7609 7610 // Build some magic constants. 7611 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 }; 7612 Constant *C0 = ConstantDataVector::get(*Context, CV0); 7613 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7614 7615 SmallVector<Constant*,2> CV1; 7616 CV1.push_back( 7617 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7618 CV1.push_back( 7619 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7620 Constant *C1 = ConstantVector::get(CV1); 7621 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7622 7623 // Load the 64-bit value into an XMM register. 7624 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7625 Op.getOperand(0)); 7626 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7627 MachinePointerInfo::getConstantPool(), 7628 false, false, false, 16); 7629 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7630 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7631 CLod0); 7632 7633 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7634 MachinePointerInfo::getConstantPool(), 7635 false, false, false, 16); 7636 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7637 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7638 SDValue Result; 7639 7640 if (Subtarget->hasSSE3()) { 7641 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7642 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7643 } else { 7644 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7645 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7646 S2F, 0x4E, DAG); 7647 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7648 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7649 Sub); 7650 } 7651 7652 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7653 DAG.getIntPtrConstant(0)); 7654} 7655 7656// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7657SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7658 SelectionDAG &DAG) const { 7659 DebugLoc dl = Op.getDebugLoc(); 7660 // FP constant to bias correct the final result. 7661 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7662 MVT::f64); 7663 7664 // Load the 32-bit value into an XMM register. 7665 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7666 Op.getOperand(0)); 7667 7668 // Zero out the upper parts of the register. 7669 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7670 7671 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7672 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7673 DAG.getIntPtrConstant(0)); 7674 7675 // Or the load with the bias. 7676 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7677 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7678 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7679 MVT::v2f64, Load)), 7680 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7681 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7682 MVT::v2f64, Bias))); 7683 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7684 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7685 DAG.getIntPtrConstant(0)); 7686 7687 // Subtract the bias. 7688 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7689 7690 // Handle final rounding. 7691 EVT DestVT = Op.getValueType(); 7692 7693 if (DestVT.bitsLT(MVT::f64)) 7694 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7695 DAG.getIntPtrConstant(0)); 7696 if (DestVT.bitsGT(MVT::f64)) 7697 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7698 7699 // Handle final rounding. 7700 return Sub; 7701} 7702 7703SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7704 SelectionDAG &DAG) const { 7705 SDValue N0 = Op.getOperand(0); 7706 DebugLoc dl = Op.getDebugLoc(); 7707 7708 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7709 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7710 // the optimization here. 7711 if (DAG.SignBitIsZero(N0)) 7712 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7713 7714 EVT SrcVT = N0.getValueType(); 7715 EVT DstVT = Op.getValueType(); 7716 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7717 return LowerUINT_TO_FP_i64(Op, DAG); 7718 if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7719 return LowerUINT_TO_FP_i32(Op, DAG); 7720 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) 7721 return SDValue(); 7722 7723 // Make a 64-bit buffer, and use it to build an FILD. 7724 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7725 if (SrcVT == MVT::i32) { 7726 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7727 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7728 getPointerTy(), StackSlot, WordOff); 7729 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7730 StackSlot, MachinePointerInfo(), 7731 false, false, 0); 7732 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7733 OffsetSlot, MachinePointerInfo(), 7734 false, false, 0); 7735 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7736 return Fild; 7737 } 7738 7739 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7740 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7741 StackSlot, MachinePointerInfo(), 7742 false, false, 0); 7743 // For i64 source, we need to add the appropriate power of 2 if the input 7744 // was negative. This is the same as the optimization in 7745 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7746 // we must be careful to do the computation in x87 extended precision, not 7747 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7748 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7749 MachineMemOperand *MMO = 7750 DAG.getMachineFunction() 7751 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7752 MachineMemOperand::MOLoad, 8, 8); 7753 7754 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7755 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7756 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7757 MVT::i64, MMO); 7758 7759 APInt FF(32, 0x5F800000ULL); 7760 7761 // Check whether the sign bit is set. 7762 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7763 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7764 ISD::SETLT); 7765 7766 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7767 SDValue FudgePtr = DAG.getConstantPool( 7768 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7769 getPointerTy()); 7770 7771 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7772 SDValue Zero = DAG.getIntPtrConstant(0); 7773 SDValue Four = DAG.getIntPtrConstant(4); 7774 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7775 Zero, Four); 7776 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7777 7778 // Load the value out, extending it from f32 to f80. 7779 // FIXME: Avoid the extend by constructing the right constant pool? 7780 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7781 FudgePtr, MachinePointerInfo::getConstantPool(), 7782 MVT::f32, false, false, 4); 7783 // Extend everything to 80 bits to force it to be done on x87. 7784 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7785 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7786} 7787 7788std::pair<SDValue,SDValue> X86TargetLowering:: 7789FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { 7790 DebugLoc DL = Op.getDebugLoc(); 7791 7792 EVT DstTy = Op.getValueType(); 7793 7794 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) { 7795 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7796 DstTy = MVT::i64; 7797 } 7798 7799 assert(DstTy.getSimpleVT() <= MVT::i64 && 7800 DstTy.getSimpleVT() >= MVT::i16 && 7801 "Unknown FP_TO_INT to lower!"); 7802 7803 // These are really Legal. 7804 if (DstTy == MVT::i32 && 7805 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7806 return std::make_pair(SDValue(), SDValue()); 7807 if (Subtarget->is64Bit() && 7808 DstTy == MVT::i64 && 7809 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7810 return std::make_pair(SDValue(), SDValue()); 7811 7812 // We lower FP->int64 either into FISTP64 followed by a load from a temporary 7813 // stack slot, or into the FTOL runtime function. 7814 MachineFunction &MF = DAG.getMachineFunction(); 7815 unsigned MemSize = DstTy.getSizeInBits()/8; 7816 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7817 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7818 7819 unsigned Opc; 7820 if (!IsSigned && isIntegerTypeFTOL(DstTy)) 7821 Opc = X86ISD::WIN_FTOL; 7822 else 7823 switch (DstTy.getSimpleVT().SimpleTy) { 7824 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7825 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7826 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7827 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7828 } 7829 7830 SDValue Chain = DAG.getEntryNode(); 7831 SDValue Value = Op.getOperand(0); 7832 EVT TheVT = Op.getOperand(0).getValueType(); 7833 // FIXME This causes a redundant load/store if the SSE-class value is already 7834 // in memory, such as if it is on the callstack. 7835 if (isScalarFPTypeInSSEReg(TheVT)) { 7836 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7837 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7838 MachinePointerInfo::getFixedStack(SSFI), 7839 false, false, 0); 7840 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7841 SDValue Ops[] = { 7842 Chain, StackSlot, DAG.getValueType(TheVT) 7843 }; 7844 7845 MachineMemOperand *MMO = 7846 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7847 MachineMemOperand::MOLoad, MemSize, MemSize); 7848 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7849 DstTy, MMO); 7850 Chain = Value.getValue(1); 7851 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7852 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7853 } 7854 7855 MachineMemOperand *MMO = 7856 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7857 MachineMemOperand::MOStore, MemSize, MemSize); 7858 7859 if (Opc != X86ISD::WIN_FTOL) { 7860 // Build the FP_TO_INT*_IN_MEM 7861 SDValue Ops[] = { Chain, Value, StackSlot }; 7862 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7863 Ops, 3, DstTy, MMO); 7864 return std::make_pair(FIST, StackSlot); 7865 } else { 7866 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL, 7867 DAG.getVTList(MVT::Other, MVT::Glue), 7868 Chain, Value); 7869 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX, 7870 MVT::i32, ftol.getValue(1)); 7871 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX, 7872 MVT::i32, eax.getValue(2)); 7873 SDValue Ops[] = { eax, edx }; 7874 SDValue pair = IsReplace 7875 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2) 7876 : DAG.getMergeValues(Ops, 2, DL); 7877 return std::make_pair(pair, SDValue()); 7878 } 7879} 7880 7881SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7882 SelectionDAG &DAG) const { 7883 if (Op.getValueType().isVector()) 7884 return SDValue(); 7885 7886 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7887 /*IsSigned=*/ true, /*IsReplace=*/ false); 7888 SDValue FIST = Vals.first, StackSlot = Vals.second; 7889 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7890 if (FIST.getNode() == 0) return Op; 7891 7892 if (StackSlot.getNode()) 7893 // Load the result. 7894 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7895 FIST, StackSlot, MachinePointerInfo(), 7896 false, false, false, 0); 7897 7898 // The node is the result. 7899 return FIST; 7900} 7901 7902SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7903 SelectionDAG &DAG) const { 7904 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, 7905 /*IsSigned=*/ false, /*IsReplace=*/ false); 7906 SDValue FIST = Vals.first, StackSlot = Vals.second; 7907 assert(FIST.getNode() && "Unexpected failure"); 7908 7909 if (StackSlot.getNode()) 7910 // Load the result. 7911 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7912 FIST, StackSlot, MachinePointerInfo(), 7913 false, false, false, 0); 7914 7915 // The node is the result. 7916 return FIST; 7917} 7918 7919SDValue X86TargetLowering::LowerFABS(SDValue Op, 7920 SelectionDAG &DAG) const { 7921 LLVMContext *Context = DAG.getContext(); 7922 DebugLoc dl = Op.getDebugLoc(); 7923 EVT VT = Op.getValueType(); 7924 EVT EltVT = VT; 7925 if (VT.isVector()) 7926 EltVT = VT.getVectorElementType(); 7927 Constant *C; 7928 if (EltVT == MVT::f64) { 7929 C = ConstantVector::getSplat(2, 7930 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7931 } else { 7932 C = ConstantVector::getSplat(4, 7933 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 7934 } 7935 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7936 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7937 MachinePointerInfo::getConstantPool(), 7938 false, false, false, 16); 7939 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7940} 7941 7942SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7943 LLVMContext *Context = DAG.getContext(); 7944 DebugLoc dl = Op.getDebugLoc(); 7945 EVT VT = Op.getValueType(); 7946 EVT EltVT = VT; 7947 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7948 if (VT.isVector()) { 7949 EltVT = VT.getVectorElementType(); 7950 NumElts = VT.getVectorNumElements(); 7951 } 7952 Constant *C; 7953 if (EltVT == MVT::f64) 7954 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7955 else 7956 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7957 C = ConstantVector::getSplat(NumElts, C); 7958 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7959 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7960 MachinePointerInfo::getConstantPool(), 7961 false, false, false, 16); 7962 if (VT.isVector()) { 7963 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7964 return DAG.getNode(ISD::BITCAST, dl, VT, 7965 DAG.getNode(ISD::XOR, dl, XORVT, 7966 DAG.getNode(ISD::BITCAST, dl, XORVT, 7967 Op.getOperand(0)), 7968 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7969 } 7970 7971 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7972} 7973 7974SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7975 LLVMContext *Context = DAG.getContext(); 7976 SDValue Op0 = Op.getOperand(0); 7977 SDValue Op1 = Op.getOperand(1); 7978 DebugLoc dl = Op.getDebugLoc(); 7979 EVT VT = Op.getValueType(); 7980 EVT SrcVT = Op1.getValueType(); 7981 7982 // If second operand is smaller, extend it first. 7983 if (SrcVT.bitsLT(VT)) { 7984 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7985 SrcVT = VT; 7986 } 7987 // And if it is bigger, shrink it first. 7988 if (SrcVT.bitsGT(VT)) { 7989 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7990 SrcVT = VT; 7991 } 7992 7993 // At this point the operands and the result should have the same 7994 // type, and that won't be f80 since that is not custom lowered. 7995 7996 // First get the sign bit of second operand. 7997 SmallVector<Constant*,4> CV; 7998 if (SrcVT == MVT::f64) { 7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8000 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8001 } else { 8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8006 } 8007 Constant *C = ConstantVector::get(CV); 8008 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8009 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8010 MachinePointerInfo::getConstantPool(), 8011 false, false, false, 16); 8012 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8013 8014 // Shift sign bit right or left if the two operands have different types. 8015 if (SrcVT.bitsGT(VT)) { 8016 // Op0 is MVT::f32, Op1 is MVT::f64. 8017 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8018 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8019 DAG.getConstant(32, MVT::i32)); 8020 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8021 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8022 DAG.getIntPtrConstant(0)); 8023 } 8024 8025 // Clear first operand sign bit. 8026 CV.clear(); 8027 if (VT == MVT::f64) { 8028 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8029 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8030 } else { 8031 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8032 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8034 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8035 } 8036 C = ConstantVector::get(CV); 8037 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8038 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8039 MachinePointerInfo::getConstantPool(), 8040 false, false, false, 16); 8041 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8042 8043 // Or the value with the sign bit. 8044 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8045} 8046 8047SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8048 SDValue N0 = Op.getOperand(0); 8049 DebugLoc dl = Op.getDebugLoc(); 8050 EVT VT = Op.getValueType(); 8051 8052 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8053 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8054 DAG.getConstant(1, VT)); 8055 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8056} 8057 8058/// Emit nodes that will be selected as "test Op0,Op0", or something 8059/// equivalent. 8060SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8061 SelectionDAG &DAG) const { 8062 DebugLoc dl = Op.getDebugLoc(); 8063 8064 // CF and OF aren't always set the way we want. Determine which 8065 // of these we need. 8066 bool NeedCF = false; 8067 bool NeedOF = false; 8068 switch (X86CC) { 8069 default: break; 8070 case X86::COND_A: case X86::COND_AE: 8071 case X86::COND_B: case X86::COND_BE: 8072 NeedCF = true; 8073 break; 8074 case X86::COND_G: case X86::COND_GE: 8075 case X86::COND_L: case X86::COND_LE: 8076 case X86::COND_O: case X86::COND_NO: 8077 NeedOF = true; 8078 break; 8079 } 8080 8081 // See if we can use the EFLAGS value from the operand instead of 8082 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8083 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8084 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8085 // Emit a CMP with 0, which is the TEST pattern. 8086 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8087 DAG.getConstant(0, Op.getValueType())); 8088 8089 unsigned Opcode = 0; 8090 unsigned NumOperands = 0; 8091 switch (Op.getNode()->getOpcode()) { 8092 case ISD::ADD: 8093 // Due to an isel shortcoming, be conservative if this add is likely to be 8094 // selected as part of a load-modify-store instruction. When the root node 8095 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8096 // uses of other nodes in the match, such as the ADD in this case. This 8097 // leads to the ADD being left around and reselected, with the result being 8098 // two adds in the output. Alas, even if none our users are stores, that 8099 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8100 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8101 // climbing the DAG back to the root, and it doesn't seem to be worth the 8102 // effort. 8103 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8104 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8105 if (UI->getOpcode() != ISD::CopyToReg && 8106 UI->getOpcode() != ISD::SETCC && 8107 UI->getOpcode() != ISD::STORE) 8108 goto default_case; 8109 8110 if (ConstantSDNode *C = 8111 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8112 // An add of one will be selected as an INC. 8113 if (C->getAPIntValue() == 1) { 8114 Opcode = X86ISD::INC; 8115 NumOperands = 1; 8116 break; 8117 } 8118 8119 // An add of negative one (subtract of one) will be selected as a DEC. 8120 if (C->getAPIntValue().isAllOnesValue()) { 8121 Opcode = X86ISD::DEC; 8122 NumOperands = 1; 8123 break; 8124 } 8125 } 8126 8127 // Otherwise use a regular EFLAGS-setting add. 8128 Opcode = X86ISD::ADD; 8129 NumOperands = 2; 8130 break; 8131 case ISD::AND: { 8132 // If the primary and result isn't used, don't bother using X86ISD::AND, 8133 // because a TEST instruction will be better. 8134 bool NonFlagUse = false; 8135 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8136 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8137 SDNode *User = *UI; 8138 unsigned UOpNo = UI.getOperandNo(); 8139 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8140 // Look pass truncate. 8141 UOpNo = User->use_begin().getOperandNo(); 8142 User = *User->use_begin(); 8143 } 8144 8145 if (User->getOpcode() != ISD::BRCOND && 8146 User->getOpcode() != ISD::SETCC && 8147 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8148 NonFlagUse = true; 8149 break; 8150 } 8151 } 8152 8153 if (!NonFlagUse) 8154 break; 8155 } 8156 // FALL THROUGH 8157 case ISD::SUB: 8158 case ISD::OR: 8159 case ISD::XOR: 8160 // Due to the ISEL shortcoming noted above, be conservative if this op is 8161 // likely to be selected as part of a load-modify-store instruction. 8162 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8163 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8164 if (UI->getOpcode() == ISD::STORE) 8165 goto default_case; 8166 8167 // Otherwise use a regular EFLAGS-setting instruction. 8168 switch (Op.getNode()->getOpcode()) { 8169 default: llvm_unreachable("unexpected operator!"); 8170 case ISD::SUB: Opcode = X86ISD::SUB; break; 8171 case ISD::OR: Opcode = X86ISD::OR; break; 8172 case ISD::XOR: Opcode = X86ISD::XOR; break; 8173 case ISD::AND: Opcode = X86ISD::AND; break; 8174 } 8175 8176 NumOperands = 2; 8177 break; 8178 case X86ISD::ADD: 8179 case X86ISD::SUB: 8180 case X86ISD::INC: 8181 case X86ISD::DEC: 8182 case X86ISD::OR: 8183 case X86ISD::XOR: 8184 case X86ISD::AND: 8185 return SDValue(Op.getNode(), 1); 8186 default: 8187 default_case: 8188 break; 8189 } 8190 8191 if (Opcode == 0) 8192 // Emit a CMP with 0, which is the TEST pattern. 8193 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8194 DAG.getConstant(0, Op.getValueType())); 8195 8196 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8197 SmallVector<SDValue, 4> Ops; 8198 for (unsigned i = 0; i != NumOperands; ++i) 8199 Ops.push_back(Op.getOperand(i)); 8200 8201 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8202 DAG.ReplaceAllUsesWith(Op, New); 8203 return SDValue(New.getNode(), 1); 8204} 8205 8206/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8207/// equivalent. 8208SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8209 SelectionDAG &DAG) const { 8210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8211 if (C->getAPIntValue() == 0) 8212 return EmitTest(Op0, X86CC, DAG); 8213 8214 DebugLoc dl = Op0.getDebugLoc(); 8215 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8216} 8217 8218/// Convert a comparison if required by the subtarget. 8219SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp, 8220 SelectionDAG &DAG) const { 8221 // If the subtarget does not support the FUCOMI instruction, floating-point 8222 // comparisons have to be converted. 8223 if (Subtarget->hasCMov() || 8224 Cmp.getOpcode() != X86ISD::CMP || 8225 !Cmp.getOperand(0).getValueType().isFloatingPoint() || 8226 !Cmp.getOperand(1).getValueType().isFloatingPoint()) 8227 return Cmp; 8228 8229 // The instruction selector will select an FUCOM instruction instead of 8230 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence 8231 // build an SDNode sequence that transfers the result from FPSW into EFLAGS: 8232 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8)))) 8233 DebugLoc dl = Cmp.getDebugLoc(); 8234 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp); 8235 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW); 8236 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, 8237 DAG.getConstant(8, MVT::i8)); 8238 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); 8239 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl); 8240} 8241 8242/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8243/// if it's possible. 8244SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8245 DebugLoc dl, SelectionDAG &DAG) const { 8246 SDValue Op0 = And.getOperand(0); 8247 SDValue Op1 = And.getOperand(1); 8248 if (Op0.getOpcode() == ISD::TRUNCATE) 8249 Op0 = Op0.getOperand(0); 8250 if (Op1.getOpcode() == ISD::TRUNCATE) 8251 Op1 = Op1.getOperand(0); 8252 8253 SDValue LHS, RHS; 8254 if (Op1.getOpcode() == ISD::SHL) 8255 std::swap(Op0, Op1); 8256 if (Op0.getOpcode() == ISD::SHL) { 8257 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8258 if (And00C->getZExtValue() == 1) { 8259 // If we looked past a truncate, check that it's only truncating away 8260 // known zeros. 8261 unsigned BitWidth = Op0.getValueSizeInBits(); 8262 unsigned AndBitWidth = And.getValueSizeInBits(); 8263 if (BitWidth > AndBitWidth) { 8264 APInt Zeros, Ones; 8265 DAG.ComputeMaskedBits(Op0, Zeros, Ones); 8266 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8267 return SDValue(); 8268 } 8269 LHS = Op1; 8270 RHS = Op0.getOperand(1); 8271 } 8272 } else if (Op1.getOpcode() == ISD::Constant) { 8273 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8274 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8275 SDValue AndLHS = Op0; 8276 8277 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8278 LHS = AndLHS.getOperand(0); 8279 RHS = AndLHS.getOperand(1); 8280 } 8281 8282 // Use BT if the immediate can't be encoded in a TEST instruction. 8283 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8284 LHS = AndLHS; 8285 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8286 } 8287 } 8288 8289 if (LHS.getNode()) { 8290 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8291 // instruction. Since the shift amount is in-range-or-undefined, we know 8292 // that doing a bittest on the i32 value is ok. We extend to i32 because 8293 // the encoding for the i16 version is larger than the i32 version. 8294 // Also promote i16 to i32 for performance / code size reason. 8295 if (LHS.getValueType() == MVT::i8 || 8296 LHS.getValueType() == MVT::i16) 8297 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8298 8299 // If the operand types disagree, extend the shift amount to match. Since 8300 // BT ignores high bits (like shifts) we can use anyextend. 8301 if (LHS.getValueType() != RHS.getValueType()) 8302 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8303 8304 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8305 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8306 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8307 DAG.getConstant(Cond, MVT::i8), BT); 8308 } 8309 8310 return SDValue(); 8311} 8312 8313SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8314 8315 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8316 8317 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8318 SDValue Op0 = Op.getOperand(0); 8319 SDValue Op1 = Op.getOperand(1); 8320 DebugLoc dl = Op.getDebugLoc(); 8321 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8322 8323 // Optimize to BT if possible. 8324 // Lower (X & (1 << N)) == 0 to BT(X, N). 8325 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8326 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8327 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8328 Op1.getOpcode() == ISD::Constant && 8329 cast<ConstantSDNode>(Op1)->isNullValue() && 8330 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8331 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8332 if (NewSetCC.getNode()) 8333 return NewSetCC; 8334 } 8335 8336 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8337 // these. 8338 if (Op1.getOpcode() == ISD::Constant && 8339 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8340 cast<ConstantSDNode>(Op1)->isNullValue()) && 8341 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8342 8343 // If the input is a setcc, then reuse the input setcc or use a new one with 8344 // the inverted condition. 8345 if (Op0.getOpcode() == X86ISD::SETCC) { 8346 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8347 bool Invert = (CC == ISD::SETNE) ^ 8348 cast<ConstantSDNode>(Op1)->isNullValue(); 8349 if (!Invert) return Op0; 8350 8351 CCode = X86::GetOppositeBranchCondition(CCode); 8352 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8353 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8354 } 8355 } 8356 8357 bool isFP = Op1.getValueType().isFloatingPoint(); 8358 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8359 if (X86CC == X86::COND_INVALID) 8360 return SDValue(); 8361 8362 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8363 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG); 8364 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8365 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8366} 8367 8368// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8369// ones, and then concatenate the result back. 8370static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8371 EVT VT = Op.getValueType(); 8372 8373 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8374 "Unsupported value type for operation"); 8375 8376 unsigned NumElems = VT.getVectorNumElements(); 8377 DebugLoc dl = Op.getDebugLoc(); 8378 SDValue CC = Op.getOperand(2); 8379 8380 // Extract the LHS vectors 8381 SDValue LHS = Op.getOperand(0); 8382 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 8383 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 8384 8385 // Extract the RHS vectors 8386 SDValue RHS = Op.getOperand(1); 8387 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 8388 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 8389 8390 // Issue the operation on the smaller types and concatenate the result back 8391 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8392 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8393 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8394 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8395 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8396} 8397 8398 8399SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8400 SDValue Cond; 8401 SDValue Op0 = Op.getOperand(0); 8402 SDValue Op1 = Op.getOperand(1); 8403 SDValue CC = Op.getOperand(2); 8404 EVT VT = Op.getValueType(); 8405 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8406 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8407 DebugLoc dl = Op.getDebugLoc(); 8408 8409 if (isFP) { 8410 unsigned SSECC = 8; 8411 EVT EltVT = Op0.getValueType().getVectorElementType(); 8412 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT; 8413 8414 bool Swap = false; 8415 8416 // SSE Condition code mapping: 8417 // 0 - EQ 8418 // 1 - LT 8419 // 2 - LE 8420 // 3 - UNORD 8421 // 4 - NEQ 8422 // 5 - NLT 8423 // 6 - NLE 8424 // 7 - ORD 8425 switch (SetCCOpcode) { 8426 default: break; 8427 case ISD::SETOEQ: 8428 case ISD::SETEQ: SSECC = 0; break; 8429 case ISD::SETOGT: 8430 case ISD::SETGT: Swap = true; // Fallthrough 8431 case ISD::SETLT: 8432 case ISD::SETOLT: SSECC = 1; break; 8433 case ISD::SETOGE: 8434 case ISD::SETGE: Swap = true; // Fallthrough 8435 case ISD::SETLE: 8436 case ISD::SETOLE: SSECC = 2; break; 8437 case ISD::SETUO: SSECC = 3; break; 8438 case ISD::SETUNE: 8439 case ISD::SETNE: SSECC = 4; break; 8440 case ISD::SETULE: Swap = true; 8441 case ISD::SETUGE: SSECC = 5; break; 8442 case ISD::SETULT: Swap = true; 8443 case ISD::SETUGT: SSECC = 6; break; 8444 case ISD::SETO: SSECC = 7; break; 8445 } 8446 if (Swap) 8447 std::swap(Op0, Op1); 8448 8449 // In the two special cases we can't handle, emit two comparisons. 8450 if (SSECC == 8) { 8451 if (SetCCOpcode == ISD::SETUEQ) { 8452 SDValue UNORD, EQ; 8453 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8454 DAG.getConstant(3, MVT::i8)); 8455 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8456 DAG.getConstant(0, MVT::i8)); 8457 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8458 } 8459 if (SetCCOpcode == ISD::SETONE) { 8460 SDValue ORD, NEQ; 8461 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8462 DAG.getConstant(7, MVT::i8)); 8463 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8464 DAG.getConstant(4, MVT::i8)); 8465 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8466 } 8467 llvm_unreachable("Illegal FP comparison"); 8468 } 8469 // Handle all other FP comparisons here. 8470 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1, 8471 DAG.getConstant(SSECC, MVT::i8)); 8472 } 8473 8474 // Break 256-bit integer vector compare into smaller ones. 8475 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8476 return Lower256IntVSETCC(Op, DAG); 8477 8478 // We are handling one of the integer comparisons here. Since SSE only has 8479 // GT and EQ comparisons for integer, swapping operands and multiple 8480 // operations may be required for some comparisons. 8481 unsigned Opc = 0; 8482 bool Swap = false, Invert = false, FlipSigns = false; 8483 8484 switch (SetCCOpcode) { 8485 default: break; 8486 case ISD::SETNE: Invert = true; 8487 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8488 case ISD::SETLT: Swap = true; 8489 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8490 case ISD::SETGE: Swap = true; 8491 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8492 case ISD::SETULT: Swap = true; 8493 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8494 case ISD::SETUGE: Swap = true; 8495 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8496 } 8497 if (Swap) 8498 std::swap(Op0, Op1); 8499 8500 // Check that the operation in question is available (most are plain SSE2, 8501 // but PCMPGTQ and PCMPEQQ have different requirements). 8502 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8503 return SDValue(); 8504 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8505 return SDValue(); 8506 8507 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8508 // bits of the inputs before performing those operations. 8509 if (FlipSigns) { 8510 EVT EltVT = VT.getVectorElementType(); 8511 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8512 EltVT); 8513 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8514 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8515 SignBits.size()); 8516 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8517 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8518 } 8519 8520 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8521 8522 // If the logical-not of the result is required, perform that now. 8523 if (Invert) 8524 Result = DAG.getNOT(dl, Result, VT); 8525 8526 return Result; 8527} 8528 8529// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8530static bool isX86LogicalCmp(SDValue Op) { 8531 unsigned Opc = Op.getNode()->getOpcode(); 8532 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI || 8533 Opc == X86ISD::SAHF) 8534 return true; 8535 if (Op.getResNo() == 1 && 8536 (Opc == X86ISD::ADD || 8537 Opc == X86ISD::SUB || 8538 Opc == X86ISD::ADC || 8539 Opc == X86ISD::SBB || 8540 Opc == X86ISD::SMUL || 8541 Opc == X86ISD::UMUL || 8542 Opc == X86ISD::INC || 8543 Opc == X86ISD::DEC || 8544 Opc == X86ISD::OR || 8545 Opc == X86ISD::XOR || 8546 Opc == X86ISD::AND)) 8547 return true; 8548 8549 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8550 return true; 8551 8552 return false; 8553} 8554 8555static bool isZero(SDValue V) { 8556 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8557 return C && C->isNullValue(); 8558} 8559 8560static bool isAllOnes(SDValue V) { 8561 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8562 return C && C->isAllOnesValue(); 8563} 8564 8565SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8566 bool addTest = true; 8567 SDValue Cond = Op.getOperand(0); 8568 SDValue Op1 = Op.getOperand(1); 8569 SDValue Op2 = Op.getOperand(2); 8570 DebugLoc DL = Op.getDebugLoc(); 8571 SDValue CC; 8572 8573 if (Cond.getOpcode() == ISD::SETCC) { 8574 SDValue NewCond = LowerSETCC(Cond, DAG); 8575 if (NewCond.getNode()) 8576 Cond = NewCond; 8577 } 8578 8579 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8580 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8581 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8582 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8583 if (Cond.getOpcode() == X86ISD::SETCC && 8584 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8585 isZero(Cond.getOperand(1).getOperand(1))) { 8586 SDValue Cmp = Cond.getOperand(1); 8587 8588 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8589 8590 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8591 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8592 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8593 8594 SDValue CmpOp0 = Cmp.getOperand(0); 8595 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8596 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8597 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 8598 8599 SDValue Res = // Res = 0 or -1. 8600 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8601 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8602 8603 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8604 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8605 8606 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8607 if (N2C == 0 || !N2C->isNullValue()) 8608 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8609 return Res; 8610 } 8611 } 8612 8613 // Look past (and (setcc_carry (cmp ...)), 1). 8614 if (Cond.getOpcode() == ISD::AND && 8615 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8617 if (C && C->getAPIntValue() == 1) 8618 Cond = Cond.getOperand(0); 8619 } 8620 8621 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8622 // setting operand in place of the X86ISD::SETCC. 8623 unsigned CondOpcode = Cond.getOpcode(); 8624 if (CondOpcode == X86ISD::SETCC || 8625 CondOpcode == X86ISD::SETCC_CARRY) { 8626 CC = Cond.getOperand(0); 8627 8628 SDValue Cmp = Cond.getOperand(1); 8629 unsigned Opc = Cmp.getOpcode(); 8630 EVT VT = Op.getValueType(); 8631 8632 bool IllegalFPCMov = false; 8633 if (VT.isFloatingPoint() && !VT.isVector() && 8634 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8635 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8636 8637 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8638 Opc == X86ISD::BT) { // FIXME 8639 Cond = Cmp; 8640 addTest = false; 8641 } 8642 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8643 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8644 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8645 Cond.getOperand(0).getValueType() != MVT::i8)) { 8646 SDValue LHS = Cond.getOperand(0); 8647 SDValue RHS = Cond.getOperand(1); 8648 unsigned X86Opcode; 8649 unsigned X86Cond; 8650 SDVTList VTs; 8651 switch (CondOpcode) { 8652 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8653 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8654 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8655 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8656 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8657 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8658 default: llvm_unreachable("unexpected overflowing operator"); 8659 } 8660 if (CondOpcode == ISD::UMULO) 8661 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8662 MVT::i32); 8663 else 8664 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8665 8666 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8667 8668 if (CondOpcode == ISD::UMULO) 8669 Cond = X86Op.getValue(2); 8670 else 8671 Cond = X86Op.getValue(1); 8672 8673 CC = DAG.getConstant(X86Cond, MVT::i8); 8674 addTest = false; 8675 } 8676 8677 if (addTest) { 8678 // Look pass the truncate. 8679 if (Cond.getOpcode() == ISD::TRUNCATE) 8680 Cond = Cond.getOperand(0); 8681 8682 // We know the result of AND is compared against zero. Try to match 8683 // it to BT. 8684 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8685 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8686 if (NewSetCC.getNode()) { 8687 CC = NewSetCC.getOperand(0); 8688 Cond = NewSetCC.getOperand(1); 8689 addTest = false; 8690 } 8691 } 8692 } 8693 8694 if (addTest) { 8695 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8696 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8697 } 8698 8699 // a < b ? -1 : 0 -> RES = ~setcc_carry 8700 // a < b ? 0 : -1 -> RES = setcc_carry 8701 // a >= b ? -1 : 0 -> RES = setcc_carry 8702 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8703 if (Cond.getOpcode() == X86ISD::CMP) { 8704 Cond = ConvertCmpIfNecessary(Cond, DAG); 8705 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8706 8707 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8708 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8709 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8710 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8711 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8712 return DAG.getNOT(DL, Res, Res.getValueType()); 8713 return Res; 8714 } 8715 } 8716 8717 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8718 // condition is true. 8719 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8720 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8721 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8722} 8723 8724// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8725// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8726// from the AND / OR. 8727static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8728 Opc = Op.getOpcode(); 8729 if (Opc != ISD::OR && Opc != ISD::AND) 8730 return false; 8731 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8732 Op.getOperand(0).hasOneUse() && 8733 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8734 Op.getOperand(1).hasOneUse()); 8735} 8736 8737// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8738// 1 and that the SETCC node has a single use. 8739static bool isXor1OfSetCC(SDValue Op) { 8740 if (Op.getOpcode() != ISD::XOR) 8741 return false; 8742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8743 if (N1C && N1C->getAPIntValue() == 1) { 8744 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8745 Op.getOperand(0).hasOneUse(); 8746 } 8747 return false; 8748} 8749 8750SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8751 bool addTest = true; 8752 SDValue Chain = Op.getOperand(0); 8753 SDValue Cond = Op.getOperand(1); 8754 SDValue Dest = Op.getOperand(2); 8755 DebugLoc dl = Op.getDebugLoc(); 8756 SDValue CC; 8757 bool Inverted = false; 8758 8759 if (Cond.getOpcode() == ISD::SETCC) { 8760 // Check for setcc([su]{add,sub,mul}o == 0). 8761 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8762 isa<ConstantSDNode>(Cond.getOperand(1)) && 8763 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8764 Cond.getOperand(0).getResNo() == 1 && 8765 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8766 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8767 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8768 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8769 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8770 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8771 Inverted = true; 8772 Cond = Cond.getOperand(0); 8773 } else { 8774 SDValue NewCond = LowerSETCC(Cond, DAG); 8775 if (NewCond.getNode()) 8776 Cond = NewCond; 8777 } 8778 } 8779#if 0 8780 // FIXME: LowerXALUO doesn't handle these!! 8781 else if (Cond.getOpcode() == X86ISD::ADD || 8782 Cond.getOpcode() == X86ISD::SUB || 8783 Cond.getOpcode() == X86ISD::SMUL || 8784 Cond.getOpcode() == X86ISD::UMUL) 8785 Cond = LowerXALUO(Cond, DAG); 8786#endif 8787 8788 // Look pass (and (setcc_carry (cmp ...)), 1). 8789 if (Cond.getOpcode() == ISD::AND && 8790 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8791 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8792 if (C && C->getAPIntValue() == 1) 8793 Cond = Cond.getOperand(0); 8794 } 8795 8796 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8797 // setting operand in place of the X86ISD::SETCC. 8798 unsigned CondOpcode = Cond.getOpcode(); 8799 if (CondOpcode == X86ISD::SETCC || 8800 CondOpcode == X86ISD::SETCC_CARRY) { 8801 CC = Cond.getOperand(0); 8802 8803 SDValue Cmp = Cond.getOperand(1); 8804 unsigned Opc = Cmp.getOpcode(); 8805 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8806 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8807 Cond = Cmp; 8808 addTest = false; 8809 } else { 8810 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8811 default: break; 8812 case X86::COND_O: 8813 case X86::COND_B: 8814 // These can only come from an arithmetic instruction with overflow, 8815 // e.g. SADDO, UADDO. 8816 Cond = Cond.getNode()->getOperand(1); 8817 addTest = false; 8818 break; 8819 } 8820 } 8821 } 8822 CondOpcode = Cond.getOpcode(); 8823 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8824 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8825 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8826 Cond.getOperand(0).getValueType() != MVT::i8)) { 8827 SDValue LHS = Cond.getOperand(0); 8828 SDValue RHS = Cond.getOperand(1); 8829 unsigned X86Opcode; 8830 unsigned X86Cond; 8831 SDVTList VTs; 8832 switch (CondOpcode) { 8833 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8834 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8835 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8836 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8837 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8838 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8839 default: llvm_unreachable("unexpected overflowing operator"); 8840 } 8841 if (Inverted) 8842 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8843 if (CondOpcode == ISD::UMULO) 8844 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8845 MVT::i32); 8846 else 8847 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8848 8849 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8850 8851 if (CondOpcode == ISD::UMULO) 8852 Cond = X86Op.getValue(2); 8853 else 8854 Cond = X86Op.getValue(1); 8855 8856 CC = DAG.getConstant(X86Cond, MVT::i8); 8857 addTest = false; 8858 } else { 8859 unsigned CondOpc; 8860 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8861 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8862 if (CondOpc == ISD::OR) { 8863 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8864 // two branches instead of an explicit OR instruction with a 8865 // separate test. 8866 if (Cmp == Cond.getOperand(1).getOperand(1) && 8867 isX86LogicalCmp(Cmp)) { 8868 CC = Cond.getOperand(0).getOperand(0); 8869 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8870 Chain, Dest, CC, Cmp); 8871 CC = Cond.getOperand(1).getOperand(0); 8872 Cond = Cmp; 8873 addTest = false; 8874 } 8875 } else { // ISD::AND 8876 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8877 // two branches instead of an explicit AND instruction with a 8878 // separate test. However, we only do this if this block doesn't 8879 // have a fall-through edge, because this requires an explicit 8880 // jmp when the condition is false. 8881 if (Cmp == Cond.getOperand(1).getOperand(1) && 8882 isX86LogicalCmp(Cmp) && 8883 Op.getNode()->hasOneUse()) { 8884 X86::CondCode CCode = 8885 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8886 CCode = X86::GetOppositeBranchCondition(CCode); 8887 CC = DAG.getConstant(CCode, MVT::i8); 8888 SDNode *User = *Op.getNode()->use_begin(); 8889 // Look for an unconditional branch following this conditional branch. 8890 // We need this because we need to reverse the successors in order 8891 // to implement FCMP_OEQ. 8892 if (User->getOpcode() == ISD::BR) { 8893 SDValue FalseBB = User->getOperand(1); 8894 SDNode *NewBR = 8895 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8896 assert(NewBR == User); 8897 (void)NewBR; 8898 Dest = FalseBB; 8899 8900 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8901 Chain, Dest, CC, Cmp); 8902 X86::CondCode CCode = 8903 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8904 CCode = X86::GetOppositeBranchCondition(CCode); 8905 CC = DAG.getConstant(CCode, MVT::i8); 8906 Cond = Cmp; 8907 addTest = false; 8908 } 8909 } 8910 } 8911 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8912 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8913 // It should be transformed during dag combiner except when the condition 8914 // is set by a arithmetics with overflow node. 8915 X86::CondCode CCode = 8916 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8917 CCode = X86::GetOppositeBranchCondition(CCode); 8918 CC = DAG.getConstant(CCode, MVT::i8); 8919 Cond = Cond.getOperand(0).getOperand(1); 8920 addTest = false; 8921 } else if (Cond.getOpcode() == ISD::SETCC && 8922 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8923 // For FCMP_OEQ, we can emit 8924 // two branches instead of an explicit AND instruction with a 8925 // separate test. However, we only do this if this block doesn't 8926 // have a fall-through edge, because this requires an explicit 8927 // jmp when the condition is false. 8928 if (Op.getNode()->hasOneUse()) { 8929 SDNode *User = *Op.getNode()->use_begin(); 8930 // Look for an unconditional branch following this conditional branch. 8931 // We need this because we need to reverse the successors in order 8932 // to implement FCMP_OEQ. 8933 if (User->getOpcode() == ISD::BR) { 8934 SDValue FalseBB = User->getOperand(1); 8935 SDNode *NewBR = 8936 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8937 assert(NewBR == User); 8938 (void)NewBR; 8939 Dest = FalseBB; 8940 8941 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8942 Cond.getOperand(0), Cond.getOperand(1)); 8943 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 8944 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8945 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8946 Chain, Dest, CC, Cmp); 8947 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8948 Cond = Cmp; 8949 addTest = false; 8950 } 8951 } 8952 } else if (Cond.getOpcode() == ISD::SETCC && 8953 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8954 // For FCMP_UNE, we can emit 8955 // two branches instead of an explicit AND instruction with a 8956 // separate test. However, we only do this if this block doesn't 8957 // have a fall-through edge, because this requires an explicit 8958 // jmp when the condition is false. 8959 if (Op.getNode()->hasOneUse()) { 8960 SDNode *User = *Op.getNode()->use_begin(); 8961 // Look for an unconditional branch following this conditional branch. 8962 // We need this because we need to reverse the successors in order 8963 // to implement FCMP_UNE. 8964 if (User->getOpcode() == ISD::BR) { 8965 SDValue FalseBB = User->getOperand(1); 8966 SDNode *NewBR = 8967 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8968 assert(NewBR == User); 8969 (void)NewBR; 8970 8971 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8972 Cond.getOperand(0), Cond.getOperand(1)); 8973 Cmp = ConvertCmpIfNecessary(Cmp, DAG); 8974 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8975 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8976 Chain, Dest, CC, Cmp); 8977 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8978 Cond = Cmp; 8979 addTest = false; 8980 Dest = FalseBB; 8981 } 8982 } 8983 } 8984 } 8985 8986 if (addTest) { 8987 // Look pass the truncate. 8988 if (Cond.getOpcode() == ISD::TRUNCATE) 8989 Cond = Cond.getOperand(0); 8990 8991 // We know the result of AND is compared against zero. Try to match 8992 // it to BT. 8993 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8994 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8995 if (NewSetCC.getNode()) { 8996 CC = NewSetCC.getOperand(0); 8997 Cond = NewSetCC.getOperand(1); 8998 addTest = false; 8999 } 9000 } 9001 } 9002 9003 if (addTest) { 9004 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 9005 Cond = EmitTest(Cond, X86::COND_NE, DAG); 9006 } 9007 Cond = ConvertCmpIfNecessary(Cond, DAG); 9008 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 9009 Chain, Dest, CC, Cond); 9010} 9011 9012 9013// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 9014// Calls to _alloca is needed to probe the stack when allocating more than 4k 9015// bytes in one go. Touching the stack at 4K increments is necessary to ensure 9016// that the guard pages used by the OS virtual memory manager are allocated in 9017// correct sequence. 9018SDValue 9019X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 9020 SelectionDAG &DAG) const { 9021 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 9022 getTargetMachine().Options.EnableSegmentedStacks) && 9023 "This should be used only on Windows targets or when segmented stacks " 9024 "are being used"); 9025 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 9026 DebugLoc dl = Op.getDebugLoc(); 9027 9028 // Get the inputs. 9029 SDValue Chain = Op.getOperand(0); 9030 SDValue Size = Op.getOperand(1); 9031 // FIXME: Ensure alignment here 9032 9033 bool Is64Bit = Subtarget->is64Bit(); 9034 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 9035 9036 if (getTargetMachine().Options.EnableSegmentedStacks) { 9037 MachineFunction &MF = DAG.getMachineFunction(); 9038 MachineRegisterInfo &MRI = MF.getRegInfo(); 9039 9040 if (Is64Bit) { 9041 // The 64 bit implementation of segmented stacks needs to clobber both r10 9042 // r11. This makes it impossible to use it along with nested parameters. 9043 const Function *F = MF.getFunction(); 9044 9045 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 9046 I != E; I++) 9047 if (I->hasNestAttr()) 9048 report_fatal_error("Cannot use segmented stacks with functions that " 9049 "have nested arguments."); 9050 } 9051 9052 const TargetRegisterClass *AddrRegClass = 9053 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 9054 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 9055 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 9056 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 9057 DAG.getRegister(Vreg, SPTy)); 9058 SDValue Ops1[2] = { Value, Chain }; 9059 return DAG.getMergeValues(Ops1, 2, dl); 9060 } else { 9061 SDValue Flag; 9062 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 9063 9064 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9065 Flag = Chain.getValue(1); 9066 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9067 9068 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9069 Flag = Chain.getValue(1); 9070 9071 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9072 9073 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9074 return DAG.getMergeValues(Ops1, 2, dl); 9075 } 9076} 9077 9078SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9079 MachineFunction &MF = DAG.getMachineFunction(); 9080 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9081 9082 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9083 DebugLoc DL = Op.getDebugLoc(); 9084 9085 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9086 // vastart just stores the address of the VarArgsFrameIndex slot into the 9087 // memory location argument. 9088 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9089 getPointerTy()); 9090 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9091 MachinePointerInfo(SV), false, false, 0); 9092 } 9093 9094 // __va_list_tag: 9095 // gp_offset (0 - 6 * 8) 9096 // fp_offset (48 - 48 + 8 * 16) 9097 // overflow_arg_area (point to parameters coming in memory). 9098 // reg_save_area 9099 SmallVector<SDValue, 8> MemOps; 9100 SDValue FIN = Op.getOperand(1); 9101 // Store gp_offset 9102 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9103 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9104 MVT::i32), 9105 FIN, MachinePointerInfo(SV), false, false, 0); 9106 MemOps.push_back(Store); 9107 9108 // Store fp_offset 9109 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9110 FIN, DAG.getIntPtrConstant(4)); 9111 Store = DAG.getStore(Op.getOperand(0), DL, 9112 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9113 MVT::i32), 9114 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9115 MemOps.push_back(Store); 9116 9117 // Store ptr to overflow_arg_area 9118 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9119 FIN, DAG.getIntPtrConstant(4)); 9120 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9121 getPointerTy()); 9122 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9123 MachinePointerInfo(SV, 8), 9124 false, false, 0); 9125 MemOps.push_back(Store); 9126 9127 // Store ptr to reg_save_area. 9128 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9129 FIN, DAG.getIntPtrConstant(8)); 9130 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9131 getPointerTy()); 9132 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9133 MachinePointerInfo(SV, 16), false, false, 0); 9134 MemOps.push_back(Store); 9135 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9136 &MemOps[0], MemOps.size()); 9137} 9138 9139SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9140 assert(Subtarget->is64Bit() && 9141 "LowerVAARG only handles 64-bit va_arg!"); 9142 assert((Subtarget->isTargetLinux() || 9143 Subtarget->isTargetDarwin()) && 9144 "Unhandled target in LowerVAARG"); 9145 assert(Op.getNode()->getNumOperands() == 4); 9146 SDValue Chain = Op.getOperand(0); 9147 SDValue SrcPtr = Op.getOperand(1); 9148 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9149 unsigned Align = Op.getConstantOperandVal(3); 9150 DebugLoc dl = Op.getDebugLoc(); 9151 9152 EVT ArgVT = Op.getNode()->getValueType(0); 9153 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9154 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9155 uint8_t ArgMode; 9156 9157 // Decide which area this value should be read from. 9158 // TODO: Implement the AMD64 ABI in its entirety. This simple 9159 // selection mechanism works only for the basic types. 9160 if (ArgVT == MVT::f80) { 9161 llvm_unreachable("va_arg for f80 not yet implemented"); 9162 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9163 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9164 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9165 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9166 } else { 9167 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9168 } 9169 9170 if (ArgMode == 2) { 9171 // Sanity Check: Make sure using fp_offset makes sense. 9172 assert(!getTargetMachine().Options.UseSoftFloat && 9173 !(DAG.getMachineFunction() 9174 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9175 Subtarget->hasSSE1()); 9176 } 9177 9178 // Insert VAARG_64 node into the DAG 9179 // VAARG_64 returns two values: Variable Argument Address, Chain 9180 SmallVector<SDValue, 11> InstOps; 9181 InstOps.push_back(Chain); 9182 InstOps.push_back(SrcPtr); 9183 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9184 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9185 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9186 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9187 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9188 VTs, &InstOps[0], InstOps.size(), 9189 MVT::i64, 9190 MachinePointerInfo(SV), 9191 /*Align=*/0, 9192 /*Volatile=*/false, 9193 /*ReadMem=*/true, 9194 /*WriteMem=*/true); 9195 Chain = VAARG.getValue(1); 9196 9197 // Load the next argument and return it 9198 return DAG.getLoad(ArgVT, dl, 9199 Chain, 9200 VAARG, 9201 MachinePointerInfo(), 9202 false, false, false, 0); 9203} 9204 9205SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9206 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9207 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9208 SDValue Chain = Op.getOperand(0); 9209 SDValue DstPtr = Op.getOperand(1); 9210 SDValue SrcPtr = Op.getOperand(2); 9211 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9212 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9213 DebugLoc DL = Op.getDebugLoc(); 9214 9215 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9216 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9217 false, 9218 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9219} 9220 9221// getTargetVShiftNOde - Handle vector element shifts where the shift amount 9222// may or may not be a constant. Takes immediate version of shift as input. 9223static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 9224 SDValue SrcOp, SDValue ShAmt, 9225 SelectionDAG &DAG) { 9226 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 9227 9228 if (isa<ConstantSDNode>(ShAmt)) { 9229 switch (Opc) { 9230 default: llvm_unreachable("Unknown target vector shift node"); 9231 case X86ISD::VSHLI: 9232 case X86ISD::VSRLI: 9233 case X86ISD::VSRAI: 9234 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9235 } 9236 } 9237 9238 // Change opcode to non-immediate version 9239 switch (Opc) { 9240 default: llvm_unreachable("Unknown target vector shift node"); 9241 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 9242 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 9243 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 9244 } 9245 9246 // Need to build a vector containing shift amount 9247 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 9248 SDValue ShOps[4]; 9249 ShOps[0] = ShAmt; 9250 ShOps[1] = DAG.getConstant(0, MVT::i32); 9251 ShOps[2] = DAG.getUNDEF(MVT::i32); 9252 ShOps[3] = DAG.getUNDEF(MVT::i32); 9253 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 9254 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9255 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 9256} 9257 9258SDValue 9259X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9260 DebugLoc dl = Op.getDebugLoc(); 9261 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9262 switch (IntNo) { 9263 default: return SDValue(); // Don't custom lower most intrinsics. 9264 // Comparison intrinsics. 9265 case Intrinsic::x86_sse_comieq_ss: 9266 case Intrinsic::x86_sse_comilt_ss: 9267 case Intrinsic::x86_sse_comile_ss: 9268 case Intrinsic::x86_sse_comigt_ss: 9269 case Intrinsic::x86_sse_comige_ss: 9270 case Intrinsic::x86_sse_comineq_ss: 9271 case Intrinsic::x86_sse_ucomieq_ss: 9272 case Intrinsic::x86_sse_ucomilt_ss: 9273 case Intrinsic::x86_sse_ucomile_ss: 9274 case Intrinsic::x86_sse_ucomigt_ss: 9275 case Intrinsic::x86_sse_ucomige_ss: 9276 case Intrinsic::x86_sse_ucomineq_ss: 9277 case Intrinsic::x86_sse2_comieq_sd: 9278 case Intrinsic::x86_sse2_comilt_sd: 9279 case Intrinsic::x86_sse2_comile_sd: 9280 case Intrinsic::x86_sse2_comigt_sd: 9281 case Intrinsic::x86_sse2_comige_sd: 9282 case Intrinsic::x86_sse2_comineq_sd: 9283 case Intrinsic::x86_sse2_ucomieq_sd: 9284 case Intrinsic::x86_sse2_ucomilt_sd: 9285 case Intrinsic::x86_sse2_ucomile_sd: 9286 case Intrinsic::x86_sse2_ucomigt_sd: 9287 case Intrinsic::x86_sse2_ucomige_sd: 9288 case Intrinsic::x86_sse2_ucomineq_sd: { 9289 unsigned Opc = 0; 9290 ISD::CondCode CC = ISD::SETCC_INVALID; 9291 switch (IntNo) { 9292 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9293 case Intrinsic::x86_sse_comieq_ss: 9294 case Intrinsic::x86_sse2_comieq_sd: 9295 Opc = X86ISD::COMI; 9296 CC = ISD::SETEQ; 9297 break; 9298 case Intrinsic::x86_sse_comilt_ss: 9299 case Intrinsic::x86_sse2_comilt_sd: 9300 Opc = X86ISD::COMI; 9301 CC = ISD::SETLT; 9302 break; 9303 case Intrinsic::x86_sse_comile_ss: 9304 case Intrinsic::x86_sse2_comile_sd: 9305 Opc = X86ISD::COMI; 9306 CC = ISD::SETLE; 9307 break; 9308 case Intrinsic::x86_sse_comigt_ss: 9309 case Intrinsic::x86_sse2_comigt_sd: 9310 Opc = X86ISD::COMI; 9311 CC = ISD::SETGT; 9312 break; 9313 case Intrinsic::x86_sse_comige_ss: 9314 case Intrinsic::x86_sse2_comige_sd: 9315 Opc = X86ISD::COMI; 9316 CC = ISD::SETGE; 9317 break; 9318 case Intrinsic::x86_sse_comineq_ss: 9319 case Intrinsic::x86_sse2_comineq_sd: 9320 Opc = X86ISD::COMI; 9321 CC = ISD::SETNE; 9322 break; 9323 case Intrinsic::x86_sse_ucomieq_ss: 9324 case Intrinsic::x86_sse2_ucomieq_sd: 9325 Opc = X86ISD::UCOMI; 9326 CC = ISD::SETEQ; 9327 break; 9328 case Intrinsic::x86_sse_ucomilt_ss: 9329 case Intrinsic::x86_sse2_ucomilt_sd: 9330 Opc = X86ISD::UCOMI; 9331 CC = ISD::SETLT; 9332 break; 9333 case Intrinsic::x86_sse_ucomile_ss: 9334 case Intrinsic::x86_sse2_ucomile_sd: 9335 Opc = X86ISD::UCOMI; 9336 CC = ISD::SETLE; 9337 break; 9338 case Intrinsic::x86_sse_ucomigt_ss: 9339 case Intrinsic::x86_sse2_ucomigt_sd: 9340 Opc = X86ISD::UCOMI; 9341 CC = ISD::SETGT; 9342 break; 9343 case Intrinsic::x86_sse_ucomige_ss: 9344 case Intrinsic::x86_sse2_ucomige_sd: 9345 Opc = X86ISD::UCOMI; 9346 CC = ISD::SETGE; 9347 break; 9348 case Intrinsic::x86_sse_ucomineq_ss: 9349 case Intrinsic::x86_sse2_ucomineq_sd: 9350 Opc = X86ISD::UCOMI; 9351 CC = ISD::SETNE; 9352 break; 9353 } 9354 9355 SDValue LHS = Op.getOperand(1); 9356 SDValue RHS = Op.getOperand(2); 9357 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9358 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9359 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9360 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9361 DAG.getConstant(X86CC, MVT::i8), Cond); 9362 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9363 } 9364 // XOP comparison intrinsics 9365 case Intrinsic::x86_xop_vpcomltb: 9366 case Intrinsic::x86_xop_vpcomltw: 9367 case Intrinsic::x86_xop_vpcomltd: 9368 case Intrinsic::x86_xop_vpcomltq: 9369 case Intrinsic::x86_xop_vpcomltub: 9370 case Intrinsic::x86_xop_vpcomltuw: 9371 case Intrinsic::x86_xop_vpcomltud: 9372 case Intrinsic::x86_xop_vpcomltuq: 9373 case Intrinsic::x86_xop_vpcomleb: 9374 case Intrinsic::x86_xop_vpcomlew: 9375 case Intrinsic::x86_xop_vpcomled: 9376 case Intrinsic::x86_xop_vpcomleq: 9377 case Intrinsic::x86_xop_vpcomleub: 9378 case Intrinsic::x86_xop_vpcomleuw: 9379 case Intrinsic::x86_xop_vpcomleud: 9380 case Intrinsic::x86_xop_vpcomleuq: 9381 case Intrinsic::x86_xop_vpcomgtb: 9382 case Intrinsic::x86_xop_vpcomgtw: 9383 case Intrinsic::x86_xop_vpcomgtd: 9384 case Intrinsic::x86_xop_vpcomgtq: 9385 case Intrinsic::x86_xop_vpcomgtub: 9386 case Intrinsic::x86_xop_vpcomgtuw: 9387 case Intrinsic::x86_xop_vpcomgtud: 9388 case Intrinsic::x86_xop_vpcomgtuq: 9389 case Intrinsic::x86_xop_vpcomgeb: 9390 case Intrinsic::x86_xop_vpcomgew: 9391 case Intrinsic::x86_xop_vpcomged: 9392 case Intrinsic::x86_xop_vpcomgeq: 9393 case Intrinsic::x86_xop_vpcomgeub: 9394 case Intrinsic::x86_xop_vpcomgeuw: 9395 case Intrinsic::x86_xop_vpcomgeud: 9396 case Intrinsic::x86_xop_vpcomgeuq: 9397 case Intrinsic::x86_xop_vpcomeqb: 9398 case Intrinsic::x86_xop_vpcomeqw: 9399 case Intrinsic::x86_xop_vpcomeqd: 9400 case Intrinsic::x86_xop_vpcomeqq: 9401 case Intrinsic::x86_xop_vpcomequb: 9402 case Intrinsic::x86_xop_vpcomequw: 9403 case Intrinsic::x86_xop_vpcomequd: 9404 case Intrinsic::x86_xop_vpcomequq: 9405 case Intrinsic::x86_xop_vpcomneb: 9406 case Intrinsic::x86_xop_vpcomnew: 9407 case Intrinsic::x86_xop_vpcomned: 9408 case Intrinsic::x86_xop_vpcomneq: 9409 case Intrinsic::x86_xop_vpcomneub: 9410 case Intrinsic::x86_xop_vpcomneuw: 9411 case Intrinsic::x86_xop_vpcomneud: 9412 case Intrinsic::x86_xop_vpcomneuq: 9413 case Intrinsic::x86_xop_vpcomfalseb: 9414 case Intrinsic::x86_xop_vpcomfalsew: 9415 case Intrinsic::x86_xop_vpcomfalsed: 9416 case Intrinsic::x86_xop_vpcomfalseq: 9417 case Intrinsic::x86_xop_vpcomfalseub: 9418 case Intrinsic::x86_xop_vpcomfalseuw: 9419 case Intrinsic::x86_xop_vpcomfalseud: 9420 case Intrinsic::x86_xop_vpcomfalseuq: 9421 case Intrinsic::x86_xop_vpcomtrueb: 9422 case Intrinsic::x86_xop_vpcomtruew: 9423 case Intrinsic::x86_xop_vpcomtrued: 9424 case Intrinsic::x86_xop_vpcomtrueq: 9425 case Intrinsic::x86_xop_vpcomtrueub: 9426 case Intrinsic::x86_xop_vpcomtrueuw: 9427 case Intrinsic::x86_xop_vpcomtrueud: 9428 case Intrinsic::x86_xop_vpcomtrueuq: { 9429 unsigned CC = 0; 9430 unsigned Opc = 0; 9431 9432 switch (IntNo) { 9433 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9434 case Intrinsic::x86_xop_vpcomltb: 9435 case Intrinsic::x86_xop_vpcomltw: 9436 case Intrinsic::x86_xop_vpcomltd: 9437 case Intrinsic::x86_xop_vpcomltq: 9438 CC = 0; 9439 Opc = X86ISD::VPCOM; 9440 break; 9441 case Intrinsic::x86_xop_vpcomltub: 9442 case Intrinsic::x86_xop_vpcomltuw: 9443 case Intrinsic::x86_xop_vpcomltud: 9444 case Intrinsic::x86_xop_vpcomltuq: 9445 CC = 0; 9446 Opc = X86ISD::VPCOMU; 9447 break; 9448 case Intrinsic::x86_xop_vpcomleb: 9449 case Intrinsic::x86_xop_vpcomlew: 9450 case Intrinsic::x86_xop_vpcomled: 9451 case Intrinsic::x86_xop_vpcomleq: 9452 CC = 1; 9453 Opc = X86ISD::VPCOM; 9454 break; 9455 case Intrinsic::x86_xop_vpcomleub: 9456 case Intrinsic::x86_xop_vpcomleuw: 9457 case Intrinsic::x86_xop_vpcomleud: 9458 case Intrinsic::x86_xop_vpcomleuq: 9459 CC = 1; 9460 Opc = X86ISD::VPCOMU; 9461 break; 9462 case Intrinsic::x86_xop_vpcomgtb: 9463 case Intrinsic::x86_xop_vpcomgtw: 9464 case Intrinsic::x86_xop_vpcomgtd: 9465 case Intrinsic::x86_xop_vpcomgtq: 9466 CC = 2; 9467 Opc = X86ISD::VPCOM; 9468 break; 9469 case Intrinsic::x86_xop_vpcomgtub: 9470 case Intrinsic::x86_xop_vpcomgtuw: 9471 case Intrinsic::x86_xop_vpcomgtud: 9472 case Intrinsic::x86_xop_vpcomgtuq: 9473 CC = 2; 9474 Opc = X86ISD::VPCOMU; 9475 break; 9476 case Intrinsic::x86_xop_vpcomgeb: 9477 case Intrinsic::x86_xop_vpcomgew: 9478 case Intrinsic::x86_xop_vpcomged: 9479 case Intrinsic::x86_xop_vpcomgeq: 9480 CC = 3; 9481 Opc = X86ISD::VPCOM; 9482 break; 9483 case Intrinsic::x86_xop_vpcomgeub: 9484 case Intrinsic::x86_xop_vpcomgeuw: 9485 case Intrinsic::x86_xop_vpcomgeud: 9486 case Intrinsic::x86_xop_vpcomgeuq: 9487 CC = 3; 9488 Opc = X86ISD::VPCOMU; 9489 break; 9490 case Intrinsic::x86_xop_vpcomeqb: 9491 case Intrinsic::x86_xop_vpcomeqw: 9492 case Intrinsic::x86_xop_vpcomeqd: 9493 case Intrinsic::x86_xop_vpcomeqq: 9494 CC = 4; 9495 Opc = X86ISD::VPCOM; 9496 break; 9497 case Intrinsic::x86_xop_vpcomequb: 9498 case Intrinsic::x86_xop_vpcomequw: 9499 case Intrinsic::x86_xop_vpcomequd: 9500 case Intrinsic::x86_xop_vpcomequq: 9501 CC = 4; 9502 Opc = X86ISD::VPCOMU; 9503 break; 9504 case Intrinsic::x86_xop_vpcomneb: 9505 case Intrinsic::x86_xop_vpcomnew: 9506 case Intrinsic::x86_xop_vpcomned: 9507 case Intrinsic::x86_xop_vpcomneq: 9508 CC = 5; 9509 Opc = X86ISD::VPCOM; 9510 break; 9511 case Intrinsic::x86_xop_vpcomneub: 9512 case Intrinsic::x86_xop_vpcomneuw: 9513 case Intrinsic::x86_xop_vpcomneud: 9514 case Intrinsic::x86_xop_vpcomneuq: 9515 CC = 5; 9516 Opc = X86ISD::VPCOMU; 9517 break; 9518 case Intrinsic::x86_xop_vpcomfalseb: 9519 case Intrinsic::x86_xop_vpcomfalsew: 9520 case Intrinsic::x86_xop_vpcomfalsed: 9521 case Intrinsic::x86_xop_vpcomfalseq: 9522 CC = 6; 9523 Opc = X86ISD::VPCOM; 9524 break; 9525 case Intrinsic::x86_xop_vpcomfalseub: 9526 case Intrinsic::x86_xop_vpcomfalseuw: 9527 case Intrinsic::x86_xop_vpcomfalseud: 9528 case Intrinsic::x86_xop_vpcomfalseuq: 9529 CC = 6; 9530 Opc = X86ISD::VPCOMU; 9531 break; 9532 case Intrinsic::x86_xop_vpcomtrueb: 9533 case Intrinsic::x86_xop_vpcomtruew: 9534 case Intrinsic::x86_xop_vpcomtrued: 9535 case Intrinsic::x86_xop_vpcomtrueq: 9536 CC = 7; 9537 Opc = X86ISD::VPCOM; 9538 break; 9539 case Intrinsic::x86_xop_vpcomtrueub: 9540 case Intrinsic::x86_xop_vpcomtrueuw: 9541 case Intrinsic::x86_xop_vpcomtrueud: 9542 case Intrinsic::x86_xop_vpcomtrueuq: 9543 CC = 7; 9544 Opc = X86ISD::VPCOMU; 9545 break; 9546 } 9547 9548 SDValue LHS = Op.getOperand(1); 9549 SDValue RHS = Op.getOperand(2); 9550 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS, 9551 DAG.getConstant(CC, MVT::i8)); 9552 } 9553 9554 // Arithmetic intrinsics. 9555 case Intrinsic::x86_sse2_pmulu_dq: 9556 case Intrinsic::x86_avx2_pmulu_dq: 9557 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(), 9558 Op.getOperand(1), Op.getOperand(2)); 9559 case Intrinsic::x86_sse3_hadd_ps: 9560 case Intrinsic::x86_sse3_hadd_pd: 9561 case Intrinsic::x86_avx_hadd_ps_256: 9562 case Intrinsic::x86_avx_hadd_pd_256: 9563 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9564 Op.getOperand(1), Op.getOperand(2)); 9565 case Intrinsic::x86_sse3_hsub_ps: 9566 case Intrinsic::x86_sse3_hsub_pd: 9567 case Intrinsic::x86_avx_hsub_ps_256: 9568 case Intrinsic::x86_avx_hsub_pd_256: 9569 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9570 Op.getOperand(1), Op.getOperand(2)); 9571 case Intrinsic::x86_ssse3_phadd_w_128: 9572 case Intrinsic::x86_ssse3_phadd_d_128: 9573 case Intrinsic::x86_avx2_phadd_w: 9574 case Intrinsic::x86_avx2_phadd_d: 9575 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(), 9576 Op.getOperand(1), Op.getOperand(2)); 9577 case Intrinsic::x86_ssse3_phsub_w_128: 9578 case Intrinsic::x86_ssse3_phsub_d_128: 9579 case Intrinsic::x86_avx2_phsub_w: 9580 case Intrinsic::x86_avx2_phsub_d: 9581 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(), 9582 Op.getOperand(1), Op.getOperand(2)); 9583 case Intrinsic::x86_avx2_psllv_d: 9584 case Intrinsic::x86_avx2_psllv_q: 9585 case Intrinsic::x86_avx2_psllv_d_256: 9586 case Intrinsic::x86_avx2_psllv_q_256: 9587 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9588 Op.getOperand(1), Op.getOperand(2)); 9589 case Intrinsic::x86_avx2_psrlv_d: 9590 case Intrinsic::x86_avx2_psrlv_q: 9591 case Intrinsic::x86_avx2_psrlv_d_256: 9592 case Intrinsic::x86_avx2_psrlv_q_256: 9593 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9594 Op.getOperand(1), Op.getOperand(2)); 9595 case Intrinsic::x86_avx2_psrav_d: 9596 case Intrinsic::x86_avx2_psrav_d_256: 9597 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9598 Op.getOperand(1), Op.getOperand(2)); 9599 case Intrinsic::x86_ssse3_pshuf_b_128: 9600 case Intrinsic::x86_avx2_pshuf_b: 9601 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(), 9602 Op.getOperand(1), Op.getOperand(2)); 9603 case Intrinsic::x86_ssse3_psign_b_128: 9604 case Intrinsic::x86_ssse3_psign_w_128: 9605 case Intrinsic::x86_ssse3_psign_d_128: 9606 case Intrinsic::x86_avx2_psign_b: 9607 case Intrinsic::x86_avx2_psign_w: 9608 case Intrinsic::x86_avx2_psign_d: 9609 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(), 9610 Op.getOperand(1), Op.getOperand(2)); 9611 case Intrinsic::x86_sse41_insertps: 9612 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(), 9613 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9614 case Intrinsic::x86_avx_vperm2f128_ps_256: 9615 case Intrinsic::x86_avx_vperm2f128_pd_256: 9616 case Intrinsic::x86_avx_vperm2f128_si_256: 9617 case Intrinsic::x86_avx2_vperm2i128: 9618 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(), 9619 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); 9620 case Intrinsic::x86_avx2_permd: 9621 case Intrinsic::x86_avx2_permps: 9622 // Operands intentionally swapped. Mask is last operand to intrinsic, 9623 // but second operand for node/intruction. 9624 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(), 9625 Op.getOperand(2), Op.getOperand(1)); 9626 9627 // ptest and testp intrinsics. The intrinsic these come from are designed to 9628 // return an integer value, not just an instruction so lower it to the ptest 9629 // or testp pattern and a setcc for the result. 9630 case Intrinsic::x86_sse41_ptestz: 9631 case Intrinsic::x86_sse41_ptestc: 9632 case Intrinsic::x86_sse41_ptestnzc: 9633 case Intrinsic::x86_avx_ptestz_256: 9634 case Intrinsic::x86_avx_ptestc_256: 9635 case Intrinsic::x86_avx_ptestnzc_256: 9636 case Intrinsic::x86_avx_vtestz_ps: 9637 case Intrinsic::x86_avx_vtestc_ps: 9638 case Intrinsic::x86_avx_vtestnzc_ps: 9639 case Intrinsic::x86_avx_vtestz_pd: 9640 case Intrinsic::x86_avx_vtestc_pd: 9641 case Intrinsic::x86_avx_vtestnzc_pd: 9642 case Intrinsic::x86_avx_vtestz_ps_256: 9643 case Intrinsic::x86_avx_vtestc_ps_256: 9644 case Intrinsic::x86_avx_vtestnzc_ps_256: 9645 case Intrinsic::x86_avx_vtestz_pd_256: 9646 case Intrinsic::x86_avx_vtestc_pd_256: 9647 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9648 bool IsTestPacked = false; 9649 unsigned X86CC = 0; 9650 switch (IntNo) { 9651 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9652 case Intrinsic::x86_avx_vtestz_ps: 9653 case Intrinsic::x86_avx_vtestz_pd: 9654 case Intrinsic::x86_avx_vtestz_ps_256: 9655 case Intrinsic::x86_avx_vtestz_pd_256: 9656 IsTestPacked = true; // Fallthrough 9657 case Intrinsic::x86_sse41_ptestz: 9658 case Intrinsic::x86_avx_ptestz_256: 9659 // ZF = 1 9660 X86CC = X86::COND_E; 9661 break; 9662 case Intrinsic::x86_avx_vtestc_ps: 9663 case Intrinsic::x86_avx_vtestc_pd: 9664 case Intrinsic::x86_avx_vtestc_ps_256: 9665 case Intrinsic::x86_avx_vtestc_pd_256: 9666 IsTestPacked = true; // Fallthrough 9667 case Intrinsic::x86_sse41_ptestc: 9668 case Intrinsic::x86_avx_ptestc_256: 9669 // CF = 1 9670 X86CC = X86::COND_B; 9671 break; 9672 case Intrinsic::x86_avx_vtestnzc_ps: 9673 case Intrinsic::x86_avx_vtestnzc_pd: 9674 case Intrinsic::x86_avx_vtestnzc_ps_256: 9675 case Intrinsic::x86_avx_vtestnzc_pd_256: 9676 IsTestPacked = true; // Fallthrough 9677 case Intrinsic::x86_sse41_ptestnzc: 9678 case Intrinsic::x86_avx_ptestnzc_256: 9679 // ZF and CF = 0 9680 X86CC = X86::COND_A; 9681 break; 9682 } 9683 9684 SDValue LHS = Op.getOperand(1); 9685 SDValue RHS = Op.getOperand(2); 9686 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9687 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9688 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9689 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9690 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9691 } 9692 9693 // SSE/AVX shift intrinsics 9694 case Intrinsic::x86_sse2_psll_w: 9695 case Intrinsic::x86_sse2_psll_d: 9696 case Intrinsic::x86_sse2_psll_q: 9697 case Intrinsic::x86_avx2_psll_w: 9698 case Intrinsic::x86_avx2_psll_d: 9699 case Intrinsic::x86_avx2_psll_q: 9700 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(), 9701 Op.getOperand(1), Op.getOperand(2)); 9702 case Intrinsic::x86_sse2_psrl_w: 9703 case Intrinsic::x86_sse2_psrl_d: 9704 case Intrinsic::x86_sse2_psrl_q: 9705 case Intrinsic::x86_avx2_psrl_w: 9706 case Intrinsic::x86_avx2_psrl_d: 9707 case Intrinsic::x86_avx2_psrl_q: 9708 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(), 9709 Op.getOperand(1), Op.getOperand(2)); 9710 case Intrinsic::x86_sse2_psra_w: 9711 case Intrinsic::x86_sse2_psra_d: 9712 case Intrinsic::x86_avx2_psra_w: 9713 case Intrinsic::x86_avx2_psra_d: 9714 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(), 9715 Op.getOperand(1), Op.getOperand(2)); 9716 case Intrinsic::x86_sse2_pslli_w: 9717 case Intrinsic::x86_sse2_pslli_d: 9718 case Intrinsic::x86_sse2_pslli_q: 9719 case Intrinsic::x86_avx2_pslli_w: 9720 case Intrinsic::x86_avx2_pslli_d: 9721 case Intrinsic::x86_avx2_pslli_q: 9722 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(), 9723 Op.getOperand(1), Op.getOperand(2), DAG); 9724 case Intrinsic::x86_sse2_psrli_w: 9725 case Intrinsic::x86_sse2_psrli_d: 9726 case Intrinsic::x86_sse2_psrli_q: 9727 case Intrinsic::x86_avx2_psrli_w: 9728 case Intrinsic::x86_avx2_psrli_d: 9729 case Intrinsic::x86_avx2_psrli_q: 9730 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(), 9731 Op.getOperand(1), Op.getOperand(2), DAG); 9732 case Intrinsic::x86_sse2_psrai_w: 9733 case Intrinsic::x86_sse2_psrai_d: 9734 case Intrinsic::x86_avx2_psrai_w: 9735 case Intrinsic::x86_avx2_psrai_d: 9736 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(), 9737 Op.getOperand(1), Op.getOperand(2), DAG); 9738 // Fix vector shift instructions where the last operand is a non-immediate 9739 // i32 value. 9740 case Intrinsic::x86_mmx_pslli_w: 9741 case Intrinsic::x86_mmx_pslli_d: 9742 case Intrinsic::x86_mmx_pslli_q: 9743 case Intrinsic::x86_mmx_psrli_w: 9744 case Intrinsic::x86_mmx_psrli_d: 9745 case Intrinsic::x86_mmx_psrli_q: 9746 case Intrinsic::x86_mmx_psrai_w: 9747 case Intrinsic::x86_mmx_psrai_d: { 9748 SDValue ShAmt = Op.getOperand(2); 9749 if (isa<ConstantSDNode>(ShAmt)) 9750 return SDValue(); 9751 9752 unsigned NewIntNo = 0; 9753 switch (IntNo) { 9754 case Intrinsic::x86_mmx_pslli_w: 9755 NewIntNo = Intrinsic::x86_mmx_psll_w; 9756 break; 9757 case Intrinsic::x86_mmx_pslli_d: 9758 NewIntNo = Intrinsic::x86_mmx_psll_d; 9759 break; 9760 case Intrinsic::x86_mmx_pslli_q: 9761 NewIntNo = Intrinsic::x86_mmx_psll_q; 9762 break; 9763 case Intrinsic::x86_mmx_psrli_w: 9764 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9765 break; 9766 case Intrinsic::x86_mmx_psrli_d: 9767 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9768 break; 9769 case Intrinsic::x86_mmx_psrli_q: 9770 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9771 break; 9772 case Intrinsic::x86_mmx_psrai_w: 9773 NewIntNo = Intrinsic::x86_mmx_psra_w; 9774 break; 9775 case Intrinsic::x86_mmx_psrai_d: 9776 NewIntNo = Intrinsic::x86_mmx_psra_d; 9777 break; 9778 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9779 } 9780 9781 // The vector shift intrinsics with scalars uses 32b shift amounts but 9782 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9783 // to be zero. 9784 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt, 9785 DAG.getConstant(0, MVT::i32)); 9786// FIXME this must be lowered to get rid of the invalid type. 9787 9788 EVT VT = Op.getValueType(); 9789 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9790 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9791 DAG.getConstant(NewIntNo, MVT::i32), 9792 Op.getOperand(1), ShAmt); 9793 } 9794 } 9795} 9796 9797SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9798 SelectionDAG &DAG) const { 9799 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9800 MFI->setReturnAddressIsTaken(true); 9801 9802 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9803 DebugLoc dl = Op.getDebugLoc(); 9804 9805 if (Depth > 0) { 9806 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9807 SDValue Offset = 9808 DAG.getConstant(TD->getPointerSize(), 9809 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9810 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9811 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9812 FrameAddr, Offset), 9813 MachinePointerInfo(), false, false, false, 0); 9814 } 9815 9816 // Just load the return address. 9817 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9818 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9819 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9820} 9821 9822SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9823 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9824 MFI->setFrameAddressIsTaken(true); 9825 9826 EVT VT = Op.getValueType(); 9827 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9828 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9829 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9830 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9831 while (Depth--) 9832 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9833 MachinePointerInfo(), 9834 false, false, false, 0); 9835 return FrameAddr; 9836} 9837 9838SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9839 SelectionDAG &DAG) const { 9840 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9841} 9842 9843SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9844 MachineFunction &MF = DAG.getMachineFunction(); 9845 SDValue Chain = Op.getOperand(0); 9846 SDValue Offset = Op.getOperand(1); 9847 SDValue Handler = Op.getOperand(2); 9848 DebugLoc dl = Op.getDebugLoc(); 9849 9850 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9851 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9852 getPointerTy()); 9853 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9854 9855 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9856 DAG.getIntPtrConstant(TD->getPointerSize())); 9857 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9858 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9859 false, false, 0); 9860 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9861 MF.getRegInfo().addLiveOut(StoreAddrReg); 9862 9863 return DAG.getNode(X86ISD::EH_RETURN, dl, 9864 MVT::Other, 9865 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9866} 9867 9868SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9869 SelectionDAG &DAG) const { 9870 return Op.getOperand(0); 9871} 9872 9873SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9874 SelectionDAG &DAG) const { 9875 SDValue Root = Op.getOperand(0); 9876 SDValue Trmp = Op.getOperand(1); // trampoline 9877 SDValue FPtr = Op.getOperand(2); // nested function 9878 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9879 DebugLoc dl = Op.getDebugLoc(); 9880 9881 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9882 9883 if (Subtarget->is64Bit()) { 9884 SDValue OutChains[6]; 9885 9886 // Large code-model. 9887 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9888 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9889 9890 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9891 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9892 9893 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9894 9895 // Load the pointer to the nested function into R11. 9896 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9897 SDValue Addr = Trmp; 9898 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9899 Addr, MachinePointerInfo(TrmpAddr), 9900 false, false, 0); 9901 9902 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9903 DAG.getConstant(2, MVT::i64)); 9904 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9905 MachinePointerInfo(TrmpAddr, 2), 9906 false, false, 2); 9907 9908 // Load the 'nest' parameter value into R10. 9909 // R10 is specified in X86CallingConv.td 9910 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9911 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9912 DAG.getConstant(10, MVT::i64)); 9913 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9914 Addr, MachinePointerInfo(TrmpAddr, 10), 9915 false, false, 0); 9916 9917 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9918 DAG.getConstant(12, MVT::i64)); 9919 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9920 MachinePointerInfo(TrmpAddr, 12), 9921 false, false, 2); 9922 9923 // Jump to the nested function. 9924 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9925 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9926 DAG.getConstant(20, MVT::i64)); 9927 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9928 Addr, MachinePointerInfo(TrmpAddr, 20), 9929 false, false, 0); 9930 9931 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9932 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9933 DAG.getConstant(22, MVT::i64)); 9934 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9935 MachinePointerInfo(TrmpAddr, 22), 9936 false, false, 0); 9937 9938 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9939 } else { 9940 const Function *Func = 9941 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9942 CallingConv::ID CC = Func->getCallingConv(); 9943 unsigned NestReg; 9944 9945 switch (CC) { 9946 default: 9947 llvm_unreachable("Unsupported calling convention"); 9948 case CallingConv::C: 9949 case CallingConv::X86_StdCall: { 9950 // Pass 'nest' parameter in ECX. 9951 // Must be kept in sync with X86CallingConv.td 9952 NestReg = X86::ECX; 9953 9954 // Check that ECX wasn't needed by an 'inreg' parameter. 9955 FunctionType *FTy = Func->getFunctionType(); 9956 const AttrListPtr &Attrs = Func->getAttributes(); 9957 9958 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9959 unsigned InRegCount = 0; 9960 unsigned Idx = 1; 9961 9962 for (FunctionType::param_iterator I = FTy->param_begin(), 9963 E = FTy->param_end(); I != E; ++I, ++Idx) 9964 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9965 // FIXME: should only count parameters that are lowered to integers. 9966 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9967 9968 if (InRegCount > 2) { 9969 report_fatal_error("Nest register in use - reduce number of inreg" 9970 " parameters!"); 9971 } 9972 } 9973 break; 9974 } 9975 case CallingConv::X86_FastCall: 9976 case CallingConv::X86_ThisCall: 9977 case CallingConv::Fast: 9978 // Pass 'nest' parameter in EAX. 9979 // Must be kept in sync with X86CallingConv.td 9980 NestReg = X86::EAX; 9981 break; 9982 } 9983 9984 SDValue OutChains[4]; 9985 SDValue Addr, Disp; 9986 9987 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9988 DAG.getConstant(10, MVT::i32)); 9989 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9990 9991 // This is storing the opcode for MOV32ri. 9992 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9993 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9994 OutChains[0] = DAG.getStore(Root, dl, 9995 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9996 Trmp, MachinePointerInfo(TrmpAddr), 9997 false, false, 0); 9998 9999 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10000 DAG.getConstant(1, MVT::i32)); 10001 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 10002 MachinePointerInfo(TrmpAddr, 1), 10003 false, false, 1); 10004 10005 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 10006 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10007 DAG.getConstant(5, MVT::i32)); 10008 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 10009 MachinePointerInfo(TrmpAddr, 5), 10010 false, false, 1); 10011 10012 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 10013 DAG.getConstant(6, MVT::i32)); 10014 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 10015 MachinePointerInfo(TrmpAddr, 6), 10016 false, false, 1); 10017 10018 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 10019 } 10020} 10021 10022SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 10023 SelectionDAG &DAG) const { 10024 /* 10025 The rounding mode is in bits 11:10 of FPSR, and has the following 10026 settings: 10027 00 Round to nearest 10028 01 Round to -inf 10029 10 Round to +inf 10030 11 Round to 0 10031 10032 FLT_ROUNDS, on the other hand, expects the following: 10033 -1 Undefined 10034 0 Round to 0 10035 1 Round to nearest 10036 2 Round to +inf 10037 3 Round to -inf 10038 10039 To perform the conversion, we do: 10040 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 10041 */ 10042 10043 MachineFunction &MF = DAG.getMachineFunction(); 10044 const TargetMachine &TM = MF.getTarget(); 10045 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 10046 unsigned StackAlignment = TFI.getStackAlignment(); 10047 EVT VT = Op.getValueType(); 10048 DebugLoc DL = Op.getDebugLoc(); 10049 10050 // Save FP Control Word to stack slot 10051 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 10052 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 10053 10054 10055 MachineMemOperand *MMO = 10056 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 10057 MachineMemOperand::MOStore, 2, 2); 10058 10059 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 10060 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 10061 DAG.getVTList(MVT::Other), 10062 Ops, 2, MVT::i16, MMO); 10063 10064 // Load FP Control Word from stack slot 10065 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 10066 MachinePointerInfo(), false, false, false, 0); 10067 10068 // Transform as necessary 10069 SDValue CWD1 = 10070 DAG.getNode(ISD::SRL, DL, MVT::i16, 10071 DAG.getNode(ISD::AND, DL, MVT::i16, 10072 CWD, DAG.getConstant(0x800, MVT::i16)), 10073 DAG.getConstant(11, MVT::i8)); 10074 SDValue CWD2 = 10075 DAG.getNode(ISD::SRL, DL, MVT::i16, 10076 DAG.getNode(ISD::AND, DL, MVT::i16, 10077 CWD, DAG.getConstant(0x400, MVT::i16)), 10078 DAG.getConstant(9, MVT::i8)); 10079 10080 SDValue RetVal = 10081 DAG.getNode(ISD::AND, DL, MVT::i16, 10082 DAG.getNode(ISD::ADD, DL, MVT::i16, 10083 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 10084 DAG.getConstant(1, MVT::i16)), 10085 DAG.getConstant(3, MVT::i16)); 10086 10087 10088 return DAG.getNode((VT.getSizeInBits() < 16 ? 10089 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 10090} 10091 10092SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 10093 EVT VT = Op.getValueType(); 10094 EVT OpVT = VT; 10095 unsigned NumBits = VT.getSizeInBits(); 10096 DebugLoc dl = Op.getDebugLoc(); 10097 10098 Op = Op.getOperand(0); 10099 if (VT == MVT::i8) { 10100 // Zero extend to i32 since there is not an i8 bsr. 10101 OpVT = MVT::i32; 10102 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10103 } 10104 10105 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 10106 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10107 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10108 10109 // If src is zero (i.e. bsr sets ZF), returns NumBits. 10110 SDValue Ops[] = { 10111 Op, 10112 DAG.getConstant(NumBits+NumBits-1, OpVT), 10113 DAG.getConstant(X86::COND_E, MVT::i8), 10114 Op.getValue(1) 10115 }; 10116 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 10117 10118 // Finally xor with NumBits-1. 10119 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10120 10121 if (VT == MVT::i8) 10122 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10123 return Op; 10124} 10125 10126SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 10127 SelectionDAG &DAG) const { 10128 EVT VT = Op.getValueType(); 10129 EVT OpVT = VT; 10130 unsigned NumBits = VT.getSizeInBits(); 10131 DebugLoc dl = Op.getDebugLoc(); 10132 10133 Op = Op.getOperand(0); 10134 if (VT == MVT::i8) { 10135 // Zero extend to i32 since there is not an i8 bsr. 10136 OpVT = MVT::i32; 10137 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 10138 } 10139 10140 // Issue a bsr (scan bits in reverse). 10141 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 10142 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 10143 10144 // And xor with NumBits-1. 10145 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 10146 10147 if (VT == MVT::i8) 10148 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 10149 return Op; 10150} 10151 10152SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 10153 EVT VT = Op.getValueType(); 10154 unsigned NumBits = VT.getSizeInBits(); 10155 DebugLoc dl = Op.getDebugLoc(); 10156 Op = Op.getOperand(0); 10157 10158 // Issue a bsf (scan bits forward) which also sets EFLAGS. 10159 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10160 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 10161 10162 // If src is zero (i.e. bsf sets ZF), returns NumBits. 10163 SDValue Ops[] = { 10164 Op, 10165 DAG.getConstant(NumBits, VT), 10166 DAG.getConstant(X86::COND_E, MVT::i8), 10167 Op.getValue(1) 10168 }; 10169 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 10170} 10171 10172// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 10173// ones, and then concatenate the result back. 10174static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 10175 EVT VT = Op.getValueType(); 10176 10177 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 10178 "Unsupported value type for operation"); 10179 10180 unsigned NumElems = VT.getVectorNumElements(); 10181 DebugLoc dl = Op.getDebugLoc(); 10182 10183 // Extract the LHS vectors 10184 SDValue LHS = Op.getOperand(0); 10185 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10186 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10187 10188 // Extract the RHS vectors 10189 SDValue RHS = Op.getOperand(1); 10190 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl); 10191 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl); 10192 10193 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10194 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10195 10196 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 10197 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 10198 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 10199} 10200 10201SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 10202 assert(Op.getValueType().getSizeInBits() == 256 && 10203 Op.getValueType().isInteger() && 10204 "Only handle AVX 256-bit vector integer operation"); 10205 return Lower256IntArith(Op, DAG); 10206} 10207 10208SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 10209 assert(Op.getValueType().getSizeInBits() == 256 && 10210 Op.getValueType().isInteger() && 10211 "Only handle AVX 256-bit vector integer operation"); 10212 return Lower256IntArith(Op, DAG); 10213} 10214 10215SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 10216 EVT VT = Op.getValueType(); 10217 10218 // Decompose 256-bit ops into smaller 128-bit ops. 10219 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 10220 return Lower256IntArith(Op, DAG); 10221 10222 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && 10223 "Only know how to lower V2I64/V4I64 multiply"); 10224 10225 DebugLoc dl = Op.getDebugLoc(); 10226 10227 // Ahi = psrlqi(a, 32); 10228 // Bhi = psrlqi(b, 32); 10229 // 10230 // AloBlo = pmuludq(a, b); 10231 // AloBhi = pmuludq(a, Bhi); 10232 // AhiBlo = pmuludq(Ahi, b); 10233 10234 // AloBhi = psllqi(AloBhi, 32); 10235 // AhiBlo = psllqi(AhiBlo, 32); 10236 // return AloBlo + AloBhi + AhiBlo; 10237 10238 SDValue A = Op.getOperand(0); 10239 SDValue B = Op.getOperand(1); 10240 10241 SDValue ShAmt = DAG.getConstant(32, MVT::i32); 10242 10243 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt); 10244 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt); 10245 10246 // Bit cast to 32-bit vectors for MULUDQ 10247 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32; 10248 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A); 10249 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B); 10250 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi); 10251 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi); 10252 10253 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B); 10254 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi); 10255 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B); 10256 10257 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt); 10258 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt); 10259 10260 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10261 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10262} 10263 10264SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10265 10266 EVT VT = Op.getValueType(); 10267 DebugLoc dl = Op.getDebugLoc(); 10268 SDValue R = Op.getOperand(0); 10269 SDValue Amt = Op.getOperand(1); 10270 LLVMContext *Context = DAG.getContext(); 10271 10272 if (!Subtarget->hasSSE2()) 10273 return SDValue(); 10274 10275 // Optimize shl/srl/sra with constant shift amount. 10276 if (isSplatVector(Amt.getNode())) { 10277 SDValue SclrAmt = Amt->getOperand(0); 10278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10279 uint64_t ShiftAmt = C->getZExtValue(); 10280 10281 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10282 (Subtarget->hasAVX2() && 10283 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10284 if (Op.getOpcode() == ISD::SHL) 10285 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10286 DAG.getConstant(ShiftAmt, MVT::i32)); 10287 if (Op.getOpcode() == ISD::SRL) 10288 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10289 DAG.getConstant(ShiftAmt, MVT::i32)); 10290 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10291 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10292 DAG.getConstant(ShiftAmt, MVT::i32)); 10293 } 10294 10295 if (VT == MVT::v16i8) { 10296 if (Op.getOpcode() == ISD::SHL) { 10297 // Make a large shift. 10298 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10299 DAG.getConstant(ShiftAmt, MVT::i32)); 10300 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10301 // Zero out the rightmost bits. 10302 SmallVector<SDValue, 16> V(16, 10303 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10304 MVT::i8)); 10305 return DAG.getNode(ISD::AND, dl, VT, SHL, 10306 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10307 } 10308 if (Op.getOpcode() == ISD::SRL) { 10309 // Make a large shift. 10310 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10311 DAG.getConstant(ShiftAmt, MVT::i32)); 10312 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10313 // Zero out the leftmost bits. 10314 SmallVector<SDValue, 16> V(16, 10315 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10316 MVT::i8)); 10317 return DAG.getNode(ISD::AND, dl, VT, SRL, 10318 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10319 } 10320 if (Op.getOpcode() == ISD::SRA) { 10321 if (ShiftAmt == 7) { 10322 // R s>> 7 === R s< 0 10323 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10324 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10325 } 10326 10327 // R s>> a === ((R u>> a) ^ m) - m 10328 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10329 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10330 MVT::i8)); 10331 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10332 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10333 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10334 return Res; 10335 } 10336 llvm_unreachable("Unknown shift opcode."); 10337 } 10338 10339 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10340 if (Op.getOpcode() == ISD::SHL) { 10341 // Make a large shift. 10342 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10343 DAG.getConstant(ShiftAmt, MVT::i32)); 10344 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10345 // Zero out the rightmost bits. 10346 SmallVector<SDValue, 32> V(32, 10347 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10348 MVT::i8)); 10349 return DAG.getNode(ISD::AND, dl, VT, SHL, 10350 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10351 } 10352 if (Op.getOpcode() == ISD::SRL) { 10353 // Make a large shift. 10354 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10355 DAG.getConstant(ShiftAmt, MVT::i32)); 10356 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10357 // Zero out the leftmost bits. 10358 SmallVector<SDValue, 32> V(32, 10359 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10360 MVT::i8)); 10361 return DAG.getNode(ISD::AND, dl, VT, SRL, 10362 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10363 } 10364 if (Op.getOpcode() == ISD::SRA) { 10365 if (ShiftAmt == 7) { 10366 // R s>> 7 === R s< 0 10367 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 10368 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10369 } 10370 10371 // R s>> a === ((R u>> a) ^ m) - m 10372 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10373 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10374 MVT::i8)); 10375 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10376 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10377 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10378 return Res; 10379 } 10380 llvm_unreachable("Unknown shift opcode."); 10381 } 10382 } 10383 } 10384 10385 // Lower SHL with variable shift amount. 10386 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10387 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10388 DAG.getConstant(23, MVT::i32)); 10389 10390 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U}; 10391 Constant *C = ConstantDataVector::get(*Context, CV); 10392 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10393 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10394 MachinePointerInfo::getConstantPool(), 10395 false, false, false, 16); 10396 10397 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10398 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10399 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10400 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10401 } 10402 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10403 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10404 10405 // a = a << 5; 10406 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10407 DAG.getConstant(5, MVT::i32)); 10408 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10409 10410 // Turn 'a' into a mask suitable for VSELECT 10411 SDValue VSelM = DAG.getConstant(0x80, VT); 10412 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10413 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10414 10415 SDValue CM1 = DAG.getConstant(0x0f, VT); 10416 SDValue CM2 = DAG.getConstant(0x3f, VT); 10417 10418 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10419 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10420 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10421 DAG.getConstant(4, MVT::i32), DAG); 10422 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10423 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10424 10425 // a += a 10426 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10427 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10428 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10429 10430 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10431 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10432 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10433 DAG.getConstant(2, MVT::i32), DAG); 10434 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10435 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10436 10437 // a += a 10438 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10439 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10440 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10441 10442 // return VSELECT(r, r+r, a); 10443 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10444 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10445 return R; 10446 } 10447 10448 // Decompose 256-bit shifts into smaller 128-bit shifts. 10449 if (VT.getSizeInBits() == 256) { 10450 unsigned NumElems = VT.getVectorNumElements(); 10451 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10452 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10453 10454 // Extract the two vectors 10455 SDValue V1 = Extract128BitVector(R, 0, DAG, dl); 10456 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl); 10457 10458 // Recreate the shift amount vectors 10459 SDValue Amt1, Amt2; 10460 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10461 // Constant shift amount 10462 SmallVector<SDValue, 4> Amt1Csts; 10463 SmallVector<SDValue, 4> Amt2Csts; 10464 for (unsigned i = 0; i != NumElems/2; ++i) 10465 Amt1Csts.push_back(Amt->getOperand(i)); 10466 for (unsigned i = NumElems/2; i != NumElems; ++i) 10467 Amt2Csts.push_back(Amt->getOperand(i)); 10468 10469 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10470 &Amt1Csts[0], NumElems/2); 10471 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10472 &Amt2Csts[0], NumElems/2); 10473 } else { 10474 // Variable shift amount 10475 Amt1 = Extract128BitVector(Amt, 0, DAG, dl); 10476 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl); 10477 } 10478 10479 // Issue new vector shifts for the smaller types 10480 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10481 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10482 10483 // Concatenate the result back 10484 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10485 } 10486 10487 return SDValue(); 10488} 10489 10490SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10491 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10492 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10493 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10494 // has only one use. 10495 SDNode *N = Op.getNode(); 10496 SDValue LHS = N->getOperand(0); 10497 SDValue RHS = N->getOperand(1); 10498 unsigned BaseOp = 0; 10499 unsigned Cond = 0; 10500 DebugLoc DL = Op.getDebugLoc(); 10501 switch (Op.getOpcode()) { 10502 default: llvm_unreachable("Unknown ovf instruction!"); 10503 case ISD::SADDO: 10504 // A subtract of one will be selected as a INC. Note that INC doesn't 10505 // set CF, so we can't do this for UADDO. 10506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10507 if (C->isOne()) { 10508 BaseOp = X86ISD::INC; 10509 Cond = X86::COND_O; 10510 break; 10511 } 10512 BaseOp = X86ISD::ADD; 10513 Cond = X86::COND_O; 10514 break; 10515 case ISD::UADDO: 10516 BaseOp = X86ISD::ADD; 10517 Cond = X86::COND_B; 10518 break; 10519 case ISD::SSUBO: 10520 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10521 // set CF, so we can't do this for USUBO. 10522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10523 if (C->isOne()) { 10524 BaseOp = X86ISD::DEC; 10525 Cond = X86::COND_O; 10526 break; 10527 } 10528 BaseOp = X86ISD::SUB; 10529 Cond = X86::COND_O; 10530 break; 10531 case ISD::USUBO: 10532 BaseOp = X86ISD::SUB; 10533 Cond = X86::COND_B; 10534 break; 10535 case ISD::SMULO: 10536 BaseOp = X86ISD::SMUL; 10537 Cond = X86::COND_O; 10538 break; 10539 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10540 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10541 MVT::i32); 10542 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10543 10544 SDValue SetCC = 10545 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10546 DAG.getConstant(X86::COND_O, MVT::i32), 10547 SDValue(Sum.getNode(), 2)); 10548 10549 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10550 } 10551 } 10552 10553 // Also sets EFLAGS. 10554 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10555 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10556 10557 SDValue SetCC = 10558 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10559 DAG.getConstant(Cond, MVT::i32), 10560 SDValue(Sum.getNode(), 1)); 10561 10562 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10563} 10564 10565SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10566 SelectionDAG &DAG) const { 10567 DebugLoc dl = Op.getDebugLoc(); 10568 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10569 EVT VT = Op.getValueType(); 10570 10571 if (!Subtarget->hasSSE2() || !VT.isVector()) 10572 return SDValue(); 10573 10574 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10575 ExtraVT.getScalarType().getSizeInBits(); 10576 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10577 10578 switch (VT.getSimpleVT().SimpleTy) { 10579 default: return SDValue(); 10580 case MVT::v8i32: 10581 case MVT::v16i16: 10582 if (!Subtarget->hasAVX()) 10583 return SDValue(); 10584 if (!Subtarget->hasAVX2()) { 10585 // needs to be split 10586 unsigned NumElems = VT.getVectorNumElements(); 10587 10588 // Extract the LHS vectors 10589 SDValue LHS = Op.getOperand(0); 10590 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl); 10591 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl); 10592 10593 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10594 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10595 10596 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10597 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10598 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10599 ExtraNumElems/2); 10600 SDValue Extra = DAG.getValueType(ExtraVT); 10601 10602 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10603 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10604 10605 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10606 } 10607 // fall through 10608 case MVT::v4i32: 10609 case MVT::v8i16: { 10610 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10611 Op.getOperand(0), ShAmt, DAG); 10612 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10613 } 10614 } 10615} 10616 10617 10618SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10619 DebugLoc dl = Op.getDebugLoc(); 10620 10621 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10622 // There isn't any reason to disable it if the target processor supports it. 10623 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10624 SDValue Chain = Op.getOperand(0); 10625 SDValue Zero = DAG.getConstant(0, MVT::i32); 10626 SDValue Ops[] = { 10627 DAG.getRegister(X86::ESP, MVT::i32), // Base 10628 DAG.getTargetConstant(1, MVT::i8), // Scale 10629 DAG.getRegister(0, MVT::i32), // Index 10630 DAG.getTargetConstant(0, MVT::i32), // Disp 10631 DAG.getRegister(0, MVT::i32), // Segment. 10632 Zero, 10633 Chain 10634 }; 10635 SDNode *Res = 10636 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10637 array_lengthof(Ops)); 10638 return SDValue(Res, 0); 10639 } 10640 10641 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10642 if (!isDev) 10643 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10644 10645 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10646 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10647 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10648 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10649 10650 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10651 if (!Op1 && !Op2 && !Op3 && Op4) 10652 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10653 10654 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10655 if (Op1 && !Op2 && !Op3 && !Op4) 10656 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10657 10658 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10659 // (MFENCE)>; 10660 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10661} 10662 10663SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10664 SelectionDAG &DAG) const { 10665 DebugLoc dl = Op.getDebugLoc(); 10666 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10667 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10668 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10669 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10670 10671 // The only fence that needs an instruction is a sequentially-consistent 10672 // cross-thread fence. 10673 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10674 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10675 // no-sse2). There isn't any reason to disable it if the target processor 10676 // supports it. 10677 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10678 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10679 10680 SDValue Chain = Op.getOperand(0); 10681 SDValue Zero = DAG.getConstant(0, MVT::i32); 10682 SDValue Ops[] = { 10683 DAG.getRegister(X86::ESP, MVT::i32), // Base 10684 DAG.getTargetConstant(1, MVT::i8), // Scale 10685 DAG.getRegister(0, MVT::i32), // Index 10686 DAG.getTargetConstant(0, MVT::i32), // Disp 10687 DAG.getRegister(0, MVT::i32), // Segment. 10688 Zero, 10689 Chain 10690 }; 10691 SDNode *Res = 10692 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10693 array_lengthof(Ops)); 10694 return SDValue(Res, 0); 10695 } 10696 10697 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10698 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10699} 10700 10701 10702SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10703 EVT T = Op.getValueType(); 10704 DebugLoc DL = Op.getDebugLoc(); 10705 unsigned Reg = 0; 10706 unsigned size = 0; 10707 switch(T.getSimpleVT().SimpleTy) { 10708 default: llvm_unreachable("Invalid value type!"); 10709 case MVT::i8: Reg = X86::AL; size = 1; break; 10710 case MVT::i16: Reg = X86::AX; size = 2; break; 10711 case MVT::i32: Reg = X86::EAX; size = 4; break; 10712 case MVT::i64: 10713 assert(Subtarget->is64Bit() && "Node not type legal!"); 10714 Reg = X86::RAX; size = 8; 10715 break; 10716 } 10717 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10718 Op.getOperand(2), SDValue()); 10719 SDValue Ops[] = { cpIn.getValue(0), 10720 Op.getOperand(1), 10721 Op.getOperand(3), 10722 DAG.getTargetConstant(size, MVT::i8), 10723 cpIn.getValue(1) }; 10724 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10725 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10726 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10727 Ops, 5, T, MMO); 10728 SDValue cpOut = 10729 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10730 return cpOut; 10731} 10732 10733SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10734 SelectionDAG &DAG) const { 10735 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10736 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10737 SDValue TheChain = Op.getOperand(0); 10738 DebugLoc dl = Op.getDebugLoc(); 10739 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10740 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10741 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10742 rax.getValue(2)); 10743 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10744 DAG.getConstant(32, MVT::i8)); 10745 SDValue Ops[] = { 10746 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10747 rdx.getValue(1) 10748 }; 10749 return DAG.getMergeValues(Ops, 2, dl); 10750} 10751 10752SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10753 SelectionDAG &DAG) const { 10754 EVT SrcVT = Op.getOperand(0).getValueType(); 10755 EVT DstVT = Op.getValueType(); 10756 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10757 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10758 assert((DstVT == MVT::i64 || 10759 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10760 "Unexpected custom BITCAST"); 10761 // i64 <=> MMX conversions are Legal. 10762 if (SrcVT==MVT::i64 && DstVT.isVector()) 10763 return Op; 10764 if (DstVT==MVT::i64 && SrcVT.isVector()) 10765 return Op; 10766 // MMX <=> MMX conversions are Legal. 10767 if (SrcVT.isVector() && DstVT.isVector()) 10768 return Op; 10769 // All other conversions need to be expanded. 10770 return SDValue(); 10771} 10772 10773SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10774 SDNode *Node = Op.getNode(); 10775 DebugLoc dl = Node->getDebugLoc(); 10776 EVT T = Node->getValueType(0); 10777 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10778 DAG.getConstant(0, T), Node->getOperand(2)); 10779 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10780 cast<AtomicSDNode>(Node)->getMemoryVT(), 10781 Node->getOperand(0), 10782 Node->getOperand(1), negOp, 10783 cast<AtomicSDNode>(Node)->getSrcValue(), 10784 cast<AtomicSDNode>(Node)->getAlignment(), 10785 cast<AtomicSDNode>(Node)->getOrdering(), 10786 cast<AtomicSDNode>(Node)->getSynchScope()); 10787} 10788 10789static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10790 SDNode *Node = Op.getNode(); 10791 DebugLoc dl = Node->getDebugLoc(); 10792 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10793 10794 // Convert seq_cst store -> xchg 10795 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10796 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10797 // (The only way to get a 16-byte store is cmpxchg16b) 10798 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10799 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10800 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10801 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10802 cast<AtomicSDNode>(Node)->getMemoryVT(), 10803 Node->getOperand(0), 10804 Node->getOperand(1), Node->getOperand(2), 10805 cast<AtomicSDNode>(Node)->getMemOperand(), 10806 cast<AtomicSDNode>(Node)->getOrdering(), 10807 cast<AtomicSDNode>(Node)->getSynchScope()); 10808 return Swap.getValue(1); 10809 } 10810 // Other atomic stores have a simple pattern. 10811 return Op; 10812} 10813 10814static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10815 EVT VT = Op.getNode()->getValueType(0); 10816 10817 // Let legalize expand this if it isn't a legal type yet. 10818 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10819 return SDValue(); 10820 10821 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10822 10823 unsigned Opc; 10824 bool ExtraOp = false; 10825 switch (Op.getOpcode()) { 10826 default: llvm_unreachable("Invalid code"); 10827 case ISD::ADDC: Opc = X86ISD::ADD; break; 10828 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10829 case ISD::SUBC: Opc = X86ISD::SUB; break; 10830 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10831 } 10832 10833 if (!ExtraOp) 10834 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10835 Op.getOperand(1)); 10836 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10837 Op.getOperand(1), Op.getOperand(2)); 10838} 10839 10840/// LowerOperation - Provide custom lowering hooks for some operations. 10841/// 10842SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10843 switch (Op.getOpcode()) { 10844 default: llvm_unreachable("Should not custom lower this!"); 10845 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10846 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10847 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10848 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10849 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10850 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10851 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10852 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10853 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10854 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10855 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10856 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10857 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10858 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10859 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10860 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10861 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10862 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10863 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10864 case ISD::SHL_PARTS: 10865 case ISD::SRA_PARTS: 10866 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10867 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10868 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10869 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10870 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10871 case ISD::FABS: return LowerFABS(Op, DAG); 10872 case ISD::FNEG: return LowerFNEG(Op, DAG); 10873 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10874 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10875 case ISD::SETCC: return LowerSETCC(Op, DAG); 10876 case ISD::SELECT: return LowerSELECT(Op, DAG); 10877 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10878 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10879 case ISD::VASTART: return LowerVASTART(Op, DAG); 10880 case ISD::VAARG: return LowerVAARG(Op, DAG); 10881 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10882 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10883 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10884 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10885 case ISD::FRAME_TO_ARGS_OFFSET: 10886 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10887 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10888 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10889 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10890 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10891 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10892 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10893 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10894 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10895 case ISD::MUL: return LowerMUL(Op, DAG); 10896 case ISD::SRA: 10897 case ISD::SRL: 10898 case ISD::SHL: return LowerShift(Op, DAG); 10899 case ISD::SADDO: 10900 case ISD::UADDO: 10901 case ISD::SSUBO: 10902 case ISD::USUBO: 10903 case ISD::SMULO: 10904 case ISD::UMULO: return LowerXALUO(Op, DAG); 10905 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10906 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10907 case ISD::ADDC: 10908 case ISD::ADDE: 10909 case ISD::SUBC: 10910 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10911 case ISD::ADD: return LowerADD(Op, DAG); 10912 case ISD::SUB: return LowerSUB(Op, DAG); 10913 } 10914} 10915 10916static void ReplaceATOMIC_LOAD(SDNode *Node, 10917 SmallVectorImpl<SDValue> &Results, 10918 SelectionDAG &DAG) { 10919 DebugLoc dl = Node->getDebugLoc(); 10920 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10921 10922 // Convert wide load -> cmpxchg8b/cmpxchg16b 10923 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10924 // (The only way to get a 16-byte load is cmpxchg16b) 10925 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10926 SDValue Zero = DAG.getConstant(0, VT); 10927 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10928 Node->getOperand(0), 10929 Node->getOperand(1), Zero, Zero, 10930 cast<AtomicSDNode>(Node)->getMemOperand(), 10931 cast<AtomicSDNode>(Node)->getOrdering(), 10932 cast<AtomicSDNode>(Node)->getSynchScope()); 10933 Results.push_back(Swap.getValue(0)); 10934 Results.push_back(Swap.getValue(1)); 10935} 10936 10937void X86TargetLowering:: 10938ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10939 SelectionDAG &DAG, unsigned NewOp) const { 10940 DebugLoc dl = Node->getDebugLoc(); 10941 assert (Node->getValueType(0) == MVT::i64 && 10942 "Only know how to expand i64 atomics"); 10943 10944 SDValue Chain = Node->getOperand(0); 10945 SDValue In1 = Node->getOperand(1); 10946 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10947 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10948 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10949 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10950 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10951 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10952 SDValue Result = 10953 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10954 cast<MemSDNode>(Node)->getMemOperand()); 10955 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10956 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10957 Results.push_back(Result.getValue(2)); 10958} 10959 10960/// ReplaceNodeResults - Replace a node with an illegal result type 10961/// with a new node built out of custom code. 10962void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10963 SmallVectorImpl<SDValue>&Results, 10964 SelectionDAG &DAG) const { 10965 DebugLoc dl = N->getDebugLoc(); 10966 switch (N->getOpcode()) { 10967 default: 10968 llvm_unreachable("Do not know how to custom type legalize this operation!"); 10969 case ISD::SIGN_EXTEND_INREG: 10970 case ISD::ADDC: 10971 case ISD::ADDE: 10972 case ISD::SUBC: 10973 case ISD::SUBE: 10974 // We don't want to expand or promote these. 10975 return; 10976 case ISD::FP_TO_SINT: 10977 case ISD::FP_TO_UINT: { 10978 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; 10979 10980 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType())) 10981 return; 10982 10983 std::pair<SDValue,SDValue> Vals = 10984 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true); 10985 SDValue FIST = Vals.first, StackSlot = Vals.second; 10986 if (FIST.getNode() != 0) { 10987 EVT VT = N->getValueType(0); 10988 // Return a load from the stack slot. 10989 if (StackSlot.getNode() != 0) 10990 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10991 MachinePointerInfo(), 10992 false, false, false, 0)); 10993 else 10994 Results.push_back(FIST); 10995 } 10996 return; 10997 } 10998 case ISD::READCYCLECOUNTER: { 10999 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11000 SDValue TheChain = N->getOperand(0); 11001 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 11002 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 11003 rd.getValue(1)); 11004 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 11005 eax.getValue(2)); 11006 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 11007 SDValue Ops[] = { eax, edx }; 11008 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 11009 Results.push_back(edx.getValue(1)); 11010 return; 11011 } 11012 case ISD::ATOMIC_CMP_SWAP: { 11013 EVT T = N->getValueType(0); 11014 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 11015 bool Regs64bit = T == MVT::i128; 11016 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 11017 SDValue cpInL, cpInH; 11018 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11019 DAG.getConstant(0, HalfT)); 11020 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 11021 DAG.getConstant(1, HalfT)); 11022 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 11023 Regs64bit ? X86::RAX : X86::EAX, 11024 cpInL, SDValue()); 11025 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 11026 Regs64bit ? X86::RDX : X86::EDX, 11027 cpInH, cpInL.getValue(1)); 11028 SDValue swapInL, swapInH; 11029 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11030 DAG.getConstant(0, HalfT)); 11031 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 11032 DAG.getConstant(1, HalfT)); 11033 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 11034 Regs64bit ? X86::RBX : X86::EBX, 11035 swapInL, cpInH.getValue(1)); 11036 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 11037 Regs64bit ? X86::RCX : X86::ECX, 11038 swapInH, swapInL.getValue(1)); 11039 SDValue Ops[] = { swapInH.getValue(0), 11040 N->getOperand(1), 11041 swapInH.getValue(1) }; 11042 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 11043 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 11044 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 11045 X86ISD::LCMPXCHG8_DAG; 11046 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 11047 Ops, 3, T, MMO); 11048 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 11049 Regs64bit ? X86::RAX : X86::EAX, 11050 HalfT, Result.getValue(1)); 11051 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 11052 Regs64bit ? X86::RDX : X86::EDX, 11053 HalfT, cpOutL.getValue(2)); 11054 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 11055 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 11056 Results.push_back(cpOutH.getValue(1)); 11057 return; 11058 } 11059 case ISD::ATOMIC_LOAD_ADD: 11060 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 11061 return; 11062 case ISD::ATOMIC_LOAD_AND: 11063 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 11064 return; 11065 case ISD::ATOMIC_LOAD_NAND: 11066 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 11067 return; 11068 case ISD::ATOMIC_LOAD_OR: 11069 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 11070 return; 11071 case ISD::ATOMIC_LOAD_SUB: 11072 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 11073 return; 11074 case ISD::ATOMIC_LOAD_XOR: 11075 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 11076 return; 11077 case ISD::ATOMIC_SWAP: 11078 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 11079 return; 11080 case ISD::ATOMIC_LOAD: 11081 ReplaceATOMIC_LOAD(N, Results, DAG); 11082 } 11083} 11084 11085const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 11086 switch (Opcode) { 11087 default: return NULL; 11088 case X86ISD::BSF: return "X86ISD::BSF"; 11089 case X86ISD::BSR: return "X86ISD::BSR"; 11090 case X86ISD::SHLD: return "X86ISD::SHLD"; 11091 case X86ISD::SHRD: return "X86ISD::SHRD"; 11092 case X86ISD::FAND: return "X86ISD::FAND"; 11093 case X86ISD::FOR: return "X86ISD::FOR"; 11094 case X86ISD::FXOR: return "X86ISD::FXOR"; 11095 case X86ISD::FSRL: return "X86ISD::FSRL"; 11096 case X86ISD::FILD: return "X86ISD::FILD"; 11097 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 11098 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 11099 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 11100 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 11101 case X86ISD::FLD: return "X86ISD::FLD"; 11102 case X86ISD::FST: return "X86ISD::FST"; 11103 case X86ISD::CALL: return "X86ISD::CALL"; 11104 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 11105 case X86ISD::BT: return "X86ISD::BT"; 11106 case X86ISD::CMP: return "X86ISD::CMP"; 11107 case X86ISD::COMI: return "X86ISD::COMI"; 11108 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 11109 case X86ISD::SETCC: return "X86ISD::SETCC"; 11110 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 11111 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 11112 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 11113 case X86ISD::CMOV: return "X86ISD::CMOV"; 11114 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 11115 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 11116 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 11117 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 11118 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 11119 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 11120 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 11121 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 11122 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 11123 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 11124 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 11125 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 11126 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 11127 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 11128 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 11129 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 11130 case X86ISD::BLENDPW: return "X86ISD::BLENDPW"; 11131 case X86ISD::BLENDPS: return "X86ISD::BLENDPS"; 11132 case X86ISD::BLENDPD: return "X86ISD::BLENDPD"; 11133 case X86ISD::HADD: return "X86ISD::HADD"; 11134 case X86ISD::HSUB: return "X86ISD::HSUB"; 11135 case X86ISD::FHADD: return "X86ISD::FHADD"; 11136 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 11137 case X86ISD::FMAX: return "X86ISD::FMAX"; 11138 case X86ISD::FMIN: return "X86ISD::FMIN"; 11139 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 11140 case X86ISD::FRCP: return "X86ISD::FRCP"; 11141 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 11142 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 11143 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 11144 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 11145 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 11146 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r"; 11147 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 11148 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 11149 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 11150 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 11151 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 11152 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 11153 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 11154 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 11155 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 11156 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 11157 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 11158 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 11159 case X86ISD::VSHL: return "X86ISD::VSHL"; 11160 case X86ISD::VSRL: return "X86ISD::VSRL"; 11161 case X86ISD::VSRA: return "X86ISD::VSRA"; 11162 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 11163 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 11164 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 11165 case X86ISD::CMPP: return "X86ISD::CMPP"; 11166 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 11167 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 11168 case X86ISD::ADD: return "X86ISD::ADD"; 11169 case X86ISD::SUB: return "X86ISD::SUB"; 11170 case X86ISD::ADC: return "X86ISD::ADC"; 11171 case X86ISD::SBB: return "X86ISD::SBB"; 11172 case X86ISD::SMUL: return "X86ISD::SMUL"; 11173 case X86ISD::UMUL: return "X86ISD::UMUL"; 11174 case X86ISD::INC: return "X86ISD::INC"; 11175 case X86ISD::DEC: return "X86ISD::DEC"; 11176 case X86ISD::OR: return "X86ISD::OR"; 11177 case X86ISD::XOR: return "X86ISD::XOR"; 11178 case X86ISD::AND: return "X86ISD::AND"; 11179 case X86ISD::ANDN: return "X86ISD::ANDN"; 11180 case X86ISD::BLSI: return "X86ISD::BLSI"; 11181 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 11182 case X86ISD::BLSR: return "X86ISD::BLSR"; 11183 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 11184 case X86ISD::PTEST: return "X86ISD::PTEST"; 11185 case X86ISD::TESTP: return "X86ISD::TESTP"; 11186 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 11187 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 11188 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 11189 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 11190 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 11191 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 11192 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 11193 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 11194 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 11195 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 11196 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 11197 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 11198 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 11199 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 11200 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 11201 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 11202 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 11203 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 11204 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 11205 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 11206 case X86ISD::VPERMV: return "X86ISD::VPERMV"; 11207 case X86ISD::VPERMI: return "X86ISD::VPERMI"; 11208 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ"; 11209 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 11210 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 11211 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 11212 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 11213 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 11214 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL"; 11215 case X86ISD::SAHF: return "X86ISD::SAHF"; 11216 } 11217} 11218 11219// isLegalAddressingMode - Return true if the addressing mode represented 11220// by AM is legal for this target, for a load/store of the specified type. 11221bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 11222 Type *Ty) const { 11223 // X86 supports extremely general addressing modes. 11224 CodeModel::Model M = getTargetMachine().getCodeModel(); 11225 Reloc::Model R = getTargetMachine().getRelocationModel(); 11226 11227 // X86 allows a sign-extended 32-bit immediate field as a displacement. 11228 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 11229 return false; 11230 11231 if (AM.BaseGV) { 11232 unsigned GVFlags = 11233 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11234 11235 // If a reference to this global requires an extra load, we can't fold it. 11236 if (isGlobalStubReference(GVFlags)) 11237 return false; 11238 11239 // If BaseGV requires a register for the PIC base, we cannot also have a 11240 // BaseReg specified. 11241 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11242 return false; 11243 11244 // If lower 4G is not available, then we must use rip-relative addressing. 11245 if ((M != CodeModel::Small || R != Reloc::Static) && 11246 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11247 return false; 11248 } 11249 11250 switch (AM.Scale) { 11251 case 0: 11252 case 1: 11253 case 2: 11254 case 4: 11255 case 8: 11256 // These scales always work. 11257 break; 11258 case 3: 11259 case 5: 11260 case 9: 11261 // These scales are formed with basereg+scalereg. Only accept if there is 11262 // no basereg yet. 11263 if (AM.HasBaseReg) 11264 return false; 11265 break; 11266 default: // Other stuff never works. 11267 return false; 11268 } 11269 11270 return true; 11271} 11272 11273 11274bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11275 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11276 return false; 11277 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11278 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11279 if (NumBits1 <= NumBits2) 11280 return false; 11281 return true; 11282} 11283 11284bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11285 if (!VT1.isInteger() || !VT2.isInteger()) 11286 return false; 11287 unsigned NumBits1 = VT1.getSizeInBits(); 11288 unsigned NumBits2 = VT2.getSizeInBits(); 11289 if (NumBits1 <= NumBits2) 11290 return false; 11291 return true; 11292} 11293 11294bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11295 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11296 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11297} 11298 11299bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11300 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11301 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11302} 11303 11304bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11305 // i16 instructions are longer (0x66 prefix) and potentially slower. 11306 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11307} 11308 11309/// isShuffleMaskLegal - Targets can use this to indicate that they only 11310/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11311/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11312/// are assumed to be legal. 11313bool 11314X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11315 EVT VT) const { 11316 // Very little shuffling can be done for 64-bit vectors right now. 11317 if (VT.getSizeInBits() == 64) 11318 return false; 11319 11320 // FIXME: pshufb, blends, shifts. 11321 return (VT.getVectorNumElements() == 2 || 11322 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11323 isMOVLMask(M, VT) || 11324 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11325 isPSHUFDMask(M, VT) || 11326 isPSHUFHWMask(M, VT) || 11327 isPSHUFLWMask(M, VT) || 11328 isPALIGNRMask(M, VT, Subtarget) || 11329 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11330 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11331 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11332 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11333} 11334 11335bool 11336X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11337 EVT VT) const { 11338 unsigned NumElts = VT.getVectorNumElements(); 11339 // FIXME: This collection of masks seems suspect. 11340 if (NumElts == 2) 11341 return true; 11342 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11343 return (isMOVLMask(Mask, VT) || 11344 isCommutedMOVLMask(Mask, VT, true) || 11345 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11346 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11347 } 11348 return false; 11349} 11350 11351//===----------------------------------------------------------------------===// 11352// X86 Scheduler Hooks 11353//===----------------------------------------------------------------------===// 11354 11355// private utility function 11356MachineBasicBlock * 11357X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11358 MachineBasicBlock *MBB, 11359 unsigned regOpc, 11360 unsigned immOpc, 11361 unsigned LoadOpc, 11362 unsigned CXchgOpc, 11363 unsigned notOpc, 11364 unsigned EAXreg, 11365 const TargetRegisterClass *RC, 11366 bool Invert) const { 11367 // For the atomic bitwise operator, we generate 11368 // thisMBB: 11369 // newMBB: 11370 // ld t1 = [bitinstr.addr] 11371 // op t2 = t1, [bitinstr.val] 11372 // not t3 = t2 (if Invert) 11373 // mov EAX = t1 11374 // lcs dest = [bitinstr.addr], t3 [EAX is implicit] 11375 // bz newMBB 11376 // fallthrough -->nextMBB 11377 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11378 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11379 MachineFunction::iterator MBBIter = MBB; 11380 ++MBBIter; 11381 11382 /// First build the CFG 11383 MachineFunction *F = MBB->getParent(); 11384 MachineBasicBlock *thisMBB = MBB; 11385 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11386 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11387 F->insert(MBBIter, newMBB); 11388 F->insert(MBBIter, nextMBB); 11389 11390 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11391 nextMBB->splice(nextMBB->begin(), thisMBB, 11392 llvm::next(MachineBasicBlock::iterator(bInstr)), 11393 thisMBB->end()); 11394 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11395 11396 // Update thisMBB to fall through to newMBB 11397 thisMBB->addSuccessor(newMBB); 11398 11399 // newMBB jumps to itself and fall through to nextMBB 11400 newMBB->addSuccessor(nextMBB); 11401 newMBB->addSuccessor(newMBB); 11402 11403 // Insert instructions into newMBB based on incoming instruction 11404 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11405 "unexpected number of operands"); 11406 DebugLoc dl = bInstr->getDebugLoc(); 11407 MachineOperand& destOper = bInstr->getOperand(0); 11408 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11409 int numArgs = bInstr->getNumOperands() - 1; 11410 for (int i=0; i < numArgs; ++i) 11411 argOpers[i] = &bInstr->getOperand(i+1); 11412 11413 // x86 address has 4 operands: base, index, scale, and displacement 11414 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11415 int valArgIndx = lastAddrIndx + 1; 11416 11417 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11418 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11419 for (int i=0; i <= lastAddrIndx; ++i) 11420 (*MIB).addOperand(*argOpers[i]); 11421 11422 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11423 assert((argOpers[valArgIndx]->isReg() || 11424 argOpers[valArgIndx]->isImm()) && 11425 "invalid operand"); 11426 if (argOpers[valArgIndx]->isReg()) 11427 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11428 else 11429 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11430 MIB.addReg(t1); 11431 (*MIB).addOperand(*argOpers[valArgIndx]); 11432 11433 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11434 if (Invert) { 11435 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2); 11436 } 11437 else 11438 t3 = t2; 11439 11440 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11441 MIB.addReg(t1); 11442 11443 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11444 for (int i=0; i <= lastAddrIndx; ++i) 11445 (*MIB).addOperand(*argOpers[i]); 11446 MIB.addReg(t3); 11447 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11448 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11449 bInstr->memoperands_end()); 11450 11451 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11452 MIB.addReg(EAXreg); 11453 11454 // insert branch 11455 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11456 11457 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11458 return nextMBB; 11459} 11460 11461// private utility function: 64 bit atomics on 32 bit host. 11462MachineBasicBlock * 11463X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11464 MachineBasicBlock *MBB, 11465 unsigned regOpcL, 11466 unsigned regOpcH, 11467 unsigned immOpcL, 11468 unsigned immOpcH, 11469 bool Invert) const { 11470 // For the atomic bitwise operator, we generate 11471 // thisMBB (instructions are in pairs, except cmpxchg8b) 11472 // ld t1,t2 = [bitinstr.addr] 11473 // newMBB: 11474 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11475 // op t5, t6 <- out1, out2, [bitinstr.val] 11476 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11477 // neg t7, t8 < t5, t6 (if Invert) 11478 // mov ECX, EBX <- t5, t6 11479 // mov EAX, EDX <- t1, t2 11480 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11481 // mov t3, t4 <- EAX, EDX 11482 // bz newMBB 11483 // result in out1, out2 11484 // fallthrough -->nextMBB 11485 11486 const TargetRegisterClass *RC = &X86::GR32RegClass; 11487 const unsigned LoadOpc = X86::MOV32rm; 11488 const unsigned NotOpc = X86::NOT32r; 11489 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11490 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11491 MachineFunction::iterator MBBIter = MBB; 11492 ++MBBIter; 11493 11494 /// First build the CFG 11495 MachineFunction *F = MBB->getParent(); 11496 MachineBasicBlock *thisMBB = MBB; 11497 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11498 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11499 F->insert(MBBIter, newMBB); 11500 F->insert(MBBIter, nextMBB); 11501 11502 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11503 nextMBB->splice(nextMBB->begin(), thisMBB, 11504 llvm::next(MachineBasicBlock::iterator(bInstr)), 11505 thisMBB->end()); 11506 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11507 11508 // Update thisMBB to fall through to newMBB 11509 thisMBB->addSuccessor(newMBB); 11510 11511 // newMBB jumps to itself and fall through to nextMBB 11512 newMBB->addSuccessor(nextMBB); 11513 newMBB->addSuccessor(newMBB); 11514 11515 DebugLoc dl = bInstr->getDebugLoc(); 11516 // Insert instructions into newMBB based on incoming instruction 11517 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11518 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11519 "unexpected number of operands"); 11520 MachineOperand& dest1Oper = bInstr->getOperand(0); 11521 MachineOperand& dest2Oper = bInstr->getOperand(1); 11522 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11523 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11524 argOpers[i] = &bInstr->getOperand(i+2); 11525 11526 // We use some of the operands multiple times, so conservatively just 11527 // clear any kill flags that might be present. 11528 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11529 argOpers[i]->setIsKill(false); 11530 } 11531 11532 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11533 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11534 11535 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11536 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11537 for (int i=0; i <= lastAddrIndx; ++i) 11538 (*MIB).addOperand(*argOpers[i]); 11539 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11540 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11541 // add 4 to displacement. 11542 for (int i=0; i <= lastAddrIndx-2; ++i) 11543 (*MIB).addOperand(*argOpers[i]); 11544 MachineOperand newOp3 = *(argOpers[3]); 11545 if (newOp3.isImm()) 11546 newOp3.setImm(newOp3.getImm()+4); 11547 else 11548 newOp3.setOffset(newOp3.getOffset()+4); 11549 (*MIB).addOperand(newOp3); 11550 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11551 11552 // t3/4 are defined later, at the bottom of the loop 11553 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11554 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11555 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11556 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11557 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11558 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11559 11560 // The subsequent operations should be using the destination registers of 11561 // the PHI instructions. 11562 t1 = dest1Oper.getReg(); 11563 t2 = dest2Oper.getReg(); 11564 11565 int valArgIndx = lastAddrIndx + 1; 11566 assert((argOpers[valArgIndx]->isReg() || 11567 argOpers[valArgIndx]->isImm()) && 11568 "invalid operand"); 11569 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11570 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11571 if (argOpers[valArgIndx]->isReg()) 11572 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11573 else 11574 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11575 if (regOpcL != X86::MOV32rr) 11576 MIB.addReg(t1); 11577 (*MIB).addOperand(*argOpers[valArgIndx]); 11578 assert(argOpers[valArgIndx + 1]->isReg() == 11579 argOpers[valArgIndx]->isReg()); 11580 assert(argOpers[valArgIndx + 1]->isImm() == 11581 argOpers[valArgIndx]->isImm()); 11582 if (argOpers[valArgIndx + 1]->isReg()) 11583 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11584 else 11585 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11586 if (regOpcH != X86::MOV32rr) 11587 MIB.addReg(t2); 11588 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11589 11590 unsigned t7, t8; 11591 if (Invert) { 11592 t7 = F->getRegInfo().createVirtualRegister(RC); 11593 t8 = F->getRegInfo().createVirtualRegister(RC); 11594 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5); 11595 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6); 11596 } else { 11597 t7 = t5; 11598 t8 = t6; 11599 } 11600 11601 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11602 MIB.addReg(t1); 11603 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11604 MIB.addReg(t2); 11605 11606 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11607 MIB.addReg(t7); 11608 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11609 MIB.addReg(t8); 11610 11611 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11612 for (int i=0; i <= lastAddrIndx; ++i) 11613 (*MIB).addOperand(*argOpers[i]); 11614 11615 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11616 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11617 bInstr->memoperands_end()); 11618 11619 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11620 MIB.addReg(X86::EAX); 11621 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11622 MIB.addReg(X86::EDX); 11623 11624 // insert branch 11625 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11626 11627 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11628 return nextMBB; 11629} 11630 11631// private utility function 11632MachineBasicBlock * 11633X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11634 MachineBasicBlock *MBB, 11635 unsigned cmovOpc) const { 11636 // For the atomic min/max operator, we generate 11637 // thisMBB: 11638 // newMBB: 11639 // ld t1 = [min/max.addr] 11640 // mov t2 = [min/max.val] 11641 // cmp t1, t2 11642 // cmov[cond] t2 = t1 11643 // mov EAX = t1 11644 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11645 // bz newMBB 11646 // fallthrough -->nextMBB 11647 // 11648 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11649 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11650 MachineFunction::iterator MBBIter = MBB; 11651 ++MBBIter; 11652 11653 /// First build the CFG 11654 MachineFunction *F = MBB->getParent(); 11655 MachineBasicBlock *thisMBB = MBB; 11656 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11657 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11658 F->insert(MBBIter, newMBB); 11659 F->insert(MBBIter, nextMBB); 11660 11661 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11662 nextMBB->splice(nextMBB->begin(), thisMBB, 11663 llvm::next(MachineBasicBlock::iterator(mInstr)), 11664 thisMBB->end()); 11665 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11666 11667 // Update thisMBB to fall through to newMBB 11668 thisMBB->addSuccessor(newMBB); 11669 11670 // newMBB jumps to newMBB and fall through to nextMBB 11671 newMBB->addSuccessor(nextMBB); 11672 newMBB->addSuccessor(newMBB); 11673 11674 DebugLoc dl = mInstr->getDebugLoc(); 11675 // Insert instructions into newMBB based on incoming instruction 11676 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11677 "unexpected number of operands"); 11678 MachineOperand& destOper = mInstr->getOperand(0); 11679 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11680 int numArgs = mInstr->getNumOperands() - 1; 11681 for (int i=0; i < numArgs; ++i) 11682 argOpers[i] = &mInstr->getOperand(i+1); 11683 11684 // x86 address has 4 operands: base, index, scale, and displacement 11685 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11686 int valArgIndx = lastAddrIndx + 1; 11687 11688 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11689 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11690 for (int i=0; i <= lastAddrIndx; ++i) 11691 (*MIB).addOperand(*argOpers[i]); 11692 11693 // We only support register and immediate values 11694 assert((argOpers[valArgIndx]->isReg() || 11695 argOpers[valArgIndx]->isImm()) && 11696 "invalid operand"); 11697 11698 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11699 if (argOpers[valArgIndx]->isReg()) 11700 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11701 else 11702 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11703 (*MIB).addOperand(*argOpers[valArgIndx]); 11704 11705 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11706 MIB.addReg(t1); 11707 11708 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11709 MIB.addReg(t1); 11710 MIB.addReg(t2); 11711 11712 // Generate movc 11713 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass); 11714 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11715 MIB.addReg(t2); 11716 MIB.addReg(t1); 11717 11718 // Cmp and exchange if none has modified the memory location 11719 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11720 for (int i=0; i <= lastAddrIndx; ++i) 11721 (*MIB).addOperand(*argOpers[i]); 11722 MIB.addReg(t3); 11723 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11724 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11725 mInstr->memoperands_end()); 11726 11727 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11728 MIB.addReg(X86::EAX); 11729 11730 // insert branch 11731 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11732 11733 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11734 return nextMBB; 11735} 11736 11737// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11738// or XMM0_V32I8 in AVX all of this code can be replaced with that 11739// in the .td file. 11740MachineBasicBlock * 11741X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11742 unsigned numArgs, bool memArg) const { 11743 assert(Subtarget->hasSSE42() && 11744 "Target must have SSE4.2 or AVX features enabled"); 11745 11746 DebugLoc dl = MI->getDebugLoc(); 11747 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11748 unsigned Opc; 11749 if (!Subtarget->hasAVX()) { 11750 if (memArg) 11751 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11752 else 11753 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11754 } else { 11755 if (memArg) 11756 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11757 else 11758 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11759 } 11760 11761 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11762 for (unsigned i = 0; i < numArgs; ++i) { 11763 MachineOperand &Op = MI->getOperand(i+1); 11764 if (!(Op.isReg() && Op.isImplicit())) 11765 MIB.addOperand(Op); 11766 } 11767 BuildMI(*BB, MI, dl, 11768 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11769 MI->getOperand(0).getReg()) 11770 .addReg(X86::XMM0); 11771 11772 MI->eraseFromParent(); 11773 return BB; 11774} 11775 11776MachineBasicBlock * 11777X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11778 DebugLoc dl = MI->getDebugLoc(); 11779 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11780 11781 // Address into RAX/EAX, other two args into ECX, EDX. 11782 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11783 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11784 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11785 for (int i = 0; i < X86::AddrNumOperands; ++i) 11786 MIB.addOperand(MI->getOperand(i)); 11787 11788 unsigned ValOps = X86::AddrNumOperands; 11789 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11790 .addReg(MI->getOperand(ValOps).getReg()); 11791 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11792 .addReg(MI->getOperand(ValOps+1).getReg()); 11793 11794 // The instruction doesn't actually take any operands though. 11795 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11796 11797 MI->eraseFromParent(); // The pseudo is gone now. 11798 return BB; 11799} 11800 11801MachineBasicBlock * 11802X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11803 DebugLoc dl = MI->getDebugLoc(); 11804 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11805 11806 // First arg in ECX, the second in EAX. 11807 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11808 .addReg(MI->getOperand(0).getReg()); 11809 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11810 .addReg(MI->getOperand(1).getReg()); 11811 11812 // The instruction doesn't actually take any operands though. 11813 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11814 11815 MI->eraseFromParent(); // The pseudo is gone now. 11816 return BB; 11817} 11818 11819MachineBasicBlock * 11820X86TargetLowering::EmitVAARG64WithCustomInserter( 11821 MachineInstr *MI, 11822 MachineBasicBlock *MBB) const { 11823 // Emit va_arg instruction on X86-64. 11824 11825 // Operands to this pseudo-instruction: 11826 // 0 ) Output : destination address (reg) 11827 // 1-5) Input : va_list address (addr, i64mem) 11828 // 6 ) ArgSize : Size (in bytes) of vararg type 11829 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11830 // 8 ) Align : Alignment of type 11831 // 9 ) EFLAGS (implicit-def) 11832 11833 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11834 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11835 11836 unsigned DestReg = MI->getOperand(0).getReg(); 11837 MachineOperand &Base = MI->getOperand(1); 11838 MachineOperand &Scale = MI->getOperand(2); 11839 MachineOperand &Index = MI->getOperand(3); 11840 MachineOperand &Disp = MI->getOperand(4); 11841 MachineOperand &Segment = MI->getOperand(5); 11842 unsigned ArgSize = MI->getOperand(6).getImm(); 11843 unsigned ArgMode = MI->getOperand(7).getImm(); 11844 unsigned Align = MI->getOperand(8).getImm(); 11845 11846 // Memory Reference 11847 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11848 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11849 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11850 11851 // Machine Information 11852 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11853 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11854 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11855 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11856 DebugLoc DL = MI->getDebugLoc(); 11857 11858 // struct va_list { 11859 // i32 gp_offset 11860 // i32 fp_offset 11861 // i64 overflow_area (address) 11862 // i64 reg_save_area (address) 11863 // } 11864 // sizeof(va_list) = 24 11865 // alignment(va_list) = 8 11866 11867 unsigned TotalNumIntRegs = 6; 11868 unsigned TotalNumXMMRegs = 8; 11869 bool UseGPOffset = (ArgMode == 1); 11870 bool UseFPOffset = (ArgMode == 2); 11871 unsigned MaxOffset = TotalNumIntRegs * 8 + 11872 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11873 11874 /* Align ArgSize to a multiple of 8 */ 11875 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11876 bool NeedsAlign = (Align > 8); 11877 11878 MachineBasicBlock *thisMBB = MBB; 11879 MachineBasicBlock *overflowMBB; 11880 MachineBasicBlock *offsetMBB; 11881 MachineBasicBlock *endMBB; 11882 11883 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11884 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11885 unsigned OffsetReg = 0; 11886 11887 if (!UseGPOffset && !UseFPOffset) { 11888 // If we only pull from the overflow region, we don't create a branch. 11889 // We don't need to alter control flow. 11890 OffsetDestReg = 0; // unused 11891 OverflowDestReg = DestReg; 11892 11893 offsetMBB = NULL; 11894 overflowMBB = thisMBB; 11895 endMBB = thisMBB; 11896 } else { 11897 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11898 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11899 // If not, pull from overflow_area. (branch to overflowMBB) 11900 // 11901 // thisMBB 11902 // | . 11903 // | . 11904 // offsetMBB overflowMBB 11905 // | . 11906 // | . 11907 // endMBB 11908 11909 // Registers for the PHI in endMBB 11910 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11911 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11912 11913 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11914 MachineFunction *MF = MBB->getParent(); 11915 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11916 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11917 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11918 11919 MachineFunction::iterator MBBIter = MBB; 11920 ++MBBIter; 11921 11922 // Insert the new basic blocks 11923 MF->insert(MBBIter, offsetMBB); 11924 MF->insert(MBBIter, overflowMBB); 11925 MF->insert(MBBIter, endMBB); 11926 11927 // Transfer the remainder of MBB and its successor edges to endMBB. 11928 endMBB->splice(endMBB->begin(), thisMBB, 11929 llvm::next(MachineBasicBlock::iterator(MI)), 11930 thisMBB->end()); 11931 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11932 11933 // Make offsetMBB and overflowMBB successors of thisMBB 11934 thisMBB->addSuccessor(offsetMBB); 11935 thisMBB->addSuccessor(overflowMBB); 11936 11937 // endMBB is a successor of both offsetMBB and overflowMBB 11938 offsetMBB->addSuccessor(endMBB); 11939 overflowMBB->addSuccessor(endMBB); 11940 11941 // Load the offset value into a register 11942 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11943 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11944 .addOperand(Base) 11945 .addOperand(Scale) 11946 .addOperand(Index) 11947 .addDisp(Disp, UseFPOffset ? 4 : 0) 11948 .addOperand(Segment) 11949 .setMemRefs(MMOBegin, MMOEnd); 11950 11951 // Check if there is enough room left to pull this argument. 11952 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11953 .addReg(OffsetReg) 11954 .addImm(MaxOffset + 8 - ArgSizeA8); 11955 11956 // Branch to "overflowMBB" if offset >= max 11957 // Fall through to "offsetMBB" otherwise 11958 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11959 .addMBB(overflowMBB); 11960 } 11961 11962 // In offsetMBB, emit code to use the reg_save_area. 11963 if (offsetMBB) { 11964 assert(OffsetReg != 0); 11965 11966 // Read the reg_save_area address. 11967 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11968 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11969 .addOperand(Base) 11970 .addOperand(Scale) 11971 .addOperand(Index) 11972 .addDisp(Disp, 16) 11973 .addOperand(Segment) 11974 .setMemRefs(MMOBegin, MMOEnd); 11975 11976 // Zero-extend the offset 11977 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11978 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11979 .addImm(0) 11980 .addReg(OffsetReg) 11981 .addImm(X86::sub_32bit); 11982 11983 // Add the offset to the reg_save_area to get the final address. 11984 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11985 .addReg(OffsetReg64) 11986 .addReg(RegSaveReg); 11987 11988 // Compute the offset for the next argument 11989 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11990 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11991 .addReg(OffsetReg) 11992 .addImm(UseFPOffset ? 16 : 8); 11993 11994 // Store it back into the va_list. 11995 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11996 .addOperand(Base) 11997 .addOperand(Scale) 11998 .addOperand(Index) 11999 .addDisp(Disp, UseFPOffset ? 4 : 0) 12000 .addOperand(Segment) 12001 .addReg(NextOffsetReg) 12002 .setMemRefs(MMOBegin, MMOEnd); 12003 12004 // Jump to endMBB 12005 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 12006 .addMBB(endMBB); 12007 } 12008 12009 // 12010 // Emit code to use overflow area 12011 // 12012 12013 // Load the overflow_area address into a register. 12014 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 12015 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 12016 .addOperand(Base) 12017 .addOperand(Scale) 12018 .addOperand(Index) 12019 .addDisp(Disp, 8) 12020 .addOperand(Segment) 12021 .setMemRefs(MMOBegin, MMOEnd); 12022 12023 // If we need to align it, do so. Otherwise, just copy the address 12024 // to OverflowDestReg. 12025 if (NeedsAlign) { 12026 // Align the overflow address 12027 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 12028 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 12029 12030 // aligned_addr = (addr + (align-1)) & ~(align-1) 12031 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 12032 .addReg(OverflowAddrReg) 12033 .addImm(Align-1); 12034 12035 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 12036 .addReg(TmpReg) 12037 .addImm(~(uint64_t)(Align-1)); 12038 } else { 12039 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 12040 .addReg(OverflowAddrReg); 12041 } 12042 12043 // Compute the next overflow address after this argument. 12044 // (the overflow address should be kept 8-byte aligned) 12045 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 12046 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 12047 .addReg(OverflowDestReg) 12048 .addImm(ArgSizeA8); 12049 12050 // Store the new overflow address. 12051 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 12052 .addOperand(Base) 12053 .addOperand(Scale) 12054 .addOperand(Index) 12055 .addDisp(Disp, 8) 12056 .addOperand(Segment) 12057 .addReg(NextAddrReg) 12058 .setMemRefs(MMOBegin, MMOEnd); 12059 12060 // If we branched, emit the PHI to the front of endMBB. 12061 if (offsetMBB) { 12062 BuildMI(*endMBB, endMBB->begin(), DL, 12063 TII->get(X86::PHI), DestReg) 12064 .addReg(OffsetDestReg).addMBB(offsetMBB) 12065 .addReg(OverflowDestReg).addMBB(overflowMBB); 12066 } 12067 12068 // Erase the pseudo instruction 12069 MI->eraseFromParent(); 12070 12071 return endMBB; 12072} 12073 12074MachineBasicBlock * 12075X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 12076 MachineInstr *MI, 12077 MachineBasicBlock *MBB) const { 12078 // Emit code to save XMM registers to the stack. The ABI says that the 12079 // number of registers to save is given in %al, so it's theoretically 12080 // possible to do an indirect jump trick to avoid saving all of them, 12081 // however this code takes a simpler approach and just executes all 12082 // of the stores if %al is non-zero. It's less code, and it's probably 12083 // easier on the hardware branch predictor, and stores aren't all that 12084 // expensive anyway. 12085 12086 // Create the new basic blocks. One block contains all the XMM stores, 12087 // and one block is the final destination regardless of whether any 12088 // stores were performed. 12089 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 12090 MachineFunction *F = MBB->getParent(); 12091 MachineFunction::iterator MBBIter = MBB; 12092 ++MBBIter; 12093 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 12094 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 12095 F->insert(MBBIter, XMMSaveMBB); 12096 F->insert(MBBIter, EndMBB); 12097 12098 // Transfer the remainder of MBB and its successor edges to EndMBB. 12099 EndMBB->splice(EndMBB->begin(), MBB, 12100 llvm::next(MachineBasicBlock::iterator(MI)), 12101 MBB->end()); 12102 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 12103 12104 // The original block will now fall through to the XMM save block. 12105 MBB->addSuccessor(XMMSaveMBB); 12106 // The XMMSaveMBB will fall through to the end block. 12107 XMMSaveMBB->addSuccessor(EndMBB); 12108 12109 // Now add the instructions. 12110 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12111 DebugLoc DL = MI->getDebugLoc(); 12112 12113 unsigned CountReg = MI->getOperand(0).getReg(); 12114 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 12115 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 12116 12117 if (!Subtarget->isTargetWin64()) { 12118 // If %al is 0, branch around the XMM save block. 12119 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 12120 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 12121 MBB->addSuccessor(EndMBB); 12122 } 12123 12124 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 12125 // In the XMM save block, save all the XMM argument registers. 12126 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 12127 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 12128 MachineMemOperand *MMO = 12129 F->getMachineMemOperand( 12130 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 12131 MachineMemOperand::MOStore, 12132 /*Size=*/16, /*Align=*/16); 12133 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 12134 .addFrameIndex(RegSaveFrameIndex) 12135 .addImm(/*Scale=*/1) 12136 .addReg(/*IndexReg=*/0) 12137 .addImm(/*Disp=*/Offset) 12138 .addReg(/*Segment=*/0) 12139 .addReg(MI->getOperand(i).getReg()) 12140 .addMemOperand(MMO); 12141 } 12142 12143 MI->eraseFromParent(); // The pseudo instruction is gone now. 12144 12145 return EndMBB; 12146} 12147 12148// The EFLAGS operand of SelectItr might be missing a kill marker 12149// because there were multiple uses of EFLAGS, and ISel didn't know 12150// which to mark. Figure out whether SelectItr should have had a 12151// kill marker, and set it if it should. Returns the correct kill 12152// marker value. 12153static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, 12154 MachineBasicBlock* BB, 12155 const TargetRegisterInfo* TRI) { 12156 // Scan forward through BB for a use/def of EFLAGS. 12157 MachineBasicBlock::iterator miI(llvm::next(SelectItr)); 12158 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { 12159 const MachineInstr& mi = *miI; 12160 if (mi.readsRegister(X86::EFLAGS)) 12161 return false; 12162 if (mi.definesRegister(X86::EFLAGS)) 12163 break; // Should have kill-flag - update below. 12164 } 12165 12166 // If we hit the end of the block, check whether EFLAGS is live into a 12167 // successor. 12168 if (miI == BB->end()) { 12169 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(), 12170 sEnd = BB->succ_end(); 12171 sItr != sEnd; ++sItr) { 12172 MachineBasicBlock* succ = *sItr; 12173 if (succ->isLiveIn(X86::EFLAGS)) 12174 return false; 12175 } 12176 } 12177 12178 // We found a def, or hit the end of the basic block and EFLAGS wasn't live 12179 // out. SelectMI should have a kill flag on EFLAGS. 12180 SelectItr->addRegisterKilled(X86::EFLAGS, TRI); 12181 return true; 12182} 12183 12184MachineBasicBlock * 12185X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 12186 MachineBasicBlock *BB) const { 12187 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12188 DebugLoc DL = MI->getDebugLoc(); 12189 12190 // To "insert" a SELECT_CC instruction, we actually have to insert the 12191 // diamond control-flow pattern. The incoming instruction knows the 12192 // destination vreg to set, the condition code register to branch on, the 12193 // true/false values to select between, and a branch opcode to use. 12194 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12195 MachineFunction::iterator It = BB; 12196 ++It; 12197 12198 // thisMBB: 12199 // ... 12200 // TrueVal = ... 12201 // cmpTY ccX, r1, r2 12202 // bCC copy1MBB 12203 // fallthrough --> copy0MBB 12204 MachineBasicBlock *thisMBB = BB; 12205 MachineFunction *F = BB->getParent(); 12206 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 12207 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 12208 F->insert(It, copy0MBB); 12209 F->insert(It, sinkMBB); 12210 12211 // If the EFLAGS register isn't dead in the terminator, then claim that it's 12212 // live into the sink and copy blocks. 12213 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo(); 12214 if (!MI->killsRegister(X86::EFLAGS) && 12215 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) { 12216 copy0MBB->addLiveIn(X86::EFLAGS); 12217 sinkMBB->addLiveIn(X86::EFLAGS); 12218 } 12219 12220 // Transfer the remainder of BB and its successor edges to sinkMBB. 12221 sinkMBB->splice(sinkMBB->begin(), BB, 12222 llvm::next(MachineBasicBlock::iterator(MI)), 12223 BB->end()); 12224 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 12225 12226 // Add the true and fallthrough blocks as its successors. 12227 BB->addSuccessor(copy0MBB); 12228 BB->addSuccessor(sinkMBB); 12229 12230 // Create the conditional branch instruction. 12231 unsigned Opc = 12232 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 12233 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 12234 12235 // copy0MBB: 12236 // %FalseValue = ... 12237 // # fallthrough to sinkMBB 12238 copy0MBB->addSuccessor(sinkMBB); 12239 12240 // sinkMBB: 12241 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 12242 // ... 12243 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 12244 TII->get(X86::PHI), MI->getOperand(0).getReg()) 12245 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 12246 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 12247 12248 MI->eraseFromParent(); // The pseudo instruction is gone now. 12249 return sinkMBB; 12250} 12251 12252MachineBasicBlock * 12253X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 12254 bool Is64Bit) const { 12255 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12256 DebugLoc DL = MI->getDebugLoc(); 12257 MachineFunction *MF = BB->getParent(); 12258 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 12259 12260 assert(getTargetMachine().Options.EnableSegmentedStacks); 12261 12262 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 12263 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 12264 12265 // BB: 12266 // ... [Till the alloca] 12267 // If stacklet is not large enough, jump to mallocMBB 12268 // 12269 // bumpMBB: 12270 // Allocate by subtracting from RSP 12271 // Jump to continueMBB 12272 // 12273 // mallocMBB: 12274 // Allocate by call to runtime 12275 // 12276 // continueMBB: 12277 // ... 12278 // [rest of original BB] 12279 // 12280 12281 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12282 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12283 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12284 12285 MachineRegisterInfo &MRI = MF->getRegInfo(); 12286 const TargetRegisterClass *AddrRegClass = 12287 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12288 12289 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12290 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12291 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12292 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12293 sizeVReg = MI->getOperand(1).getReg(), 12294 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12295 12296 MachineFunction::iterator MBBIter = BB; 12297 ++MBBIter; 12298 12299 MF->insert(MBBIter, bumpMBB); 12300 MF->insert(MBBIter, mallocMBB); 12301 MF->insert(MBBIter, continueMBB); 12302 12303 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12304 (MachineBasicBlock::iterator(MI)), BB->end()); 12305 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12306 12307 // Add code to the main basic block to check if the stack limit has been hit, 12308 // and if so, jump to mallocMBB otherwise to bumpMBB. 12309 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12310 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12311 .addReg(tmpSPVReg).addReg(sizeVReg); 12312 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12313 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12314 .addReg(SPLimitVReg); 12315 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12316 12317 // bumpMBB simply decreases the stack pointer, since we know the current 12318 // stacklet has enough space. 12319 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12320 .addReg(SPLimitVReg); 12321 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12322 .addReg(SPLimitVReg); 12323 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12324 12325 // Calls into a routine in libgcc to allocate more space from the heap. 12326 const uint32_t *RegMask = 12327 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12328 if (Is64Bit) { 12329 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12330 .addReg(sizeVReg); 12331 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12332 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI) 12333 .addRegMask(RegMask) 12334 .addReg(X86::RAX, RegState::ImplicitDefine); 12335 } else { 12336 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12337 .addImm(12); 12338 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12339 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12340 .addExternalSymbol("__morestack_allocate_stack_space") 12341 .addRegMask(RegMask) 12342 .addReg(X86::EAX, RegState::ImplicitDefine); 12343 } 12344 12345 if (!Is64Bit) 12346 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12347 .addImm(16); 12348 12349 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12350 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12351 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12352 12353 // Set up the CFG correctly. 12354 BB->addSuccessor(bumpMBB); 12355 BB->addSuccessor(mallocMBB); 12356 mallocMBB->addSuccessor(continueMBB); 12357 bumpMBB->addSuccessor(continueMBB); 12358 12359 // Take care of the PHI nodes. 12360 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12361 MI->getOperand(0).getReg()) 12362 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12363 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12364 12365 // Delete the original pseudo instruction. 12366 MI->eraseFromParent(); 12367 12368 // And we're done. 12369 return continueMBB; 12370} 12371 12372MachineBasicBlock * 12373X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12374 MachineBasicBlock *BB) const { 12375 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12376 DebugLoc DL = MI->getDebugLoc(); 12377 12378 assert(!Subtarget->isTargetEnvMacho()); 12379 12380 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12381 // non-trivial part is impdef of ESP. 12382 12383 if (Subtarget->isTargetWin64()) { 12384 if (Subtarget->isTargetCygMing()) { 12385 // ___chkstk(Mingw64): 12386 // Clobbers R10, R11, RAX and EFLAGS. 12387 // Updates RSP. 12388 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12389 .addExternalSymbol("___chkstk") 12390 .addReg(X86::RAX, RegState::Implicit) 12391 .addReg(X86::RSP, RegState::Implicit) 12392 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12393 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12394 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12395 } else { 12396 // __chkstk(MSVCRT): does not update stack pointer. 12397 // Clobbers R10, R11 and EFLAGS. 12398 // FIXME: RAX(allocated size) might be reused and not killed. 12399 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12400 .addExternalSymbol("__chkstk") 12401 .addReg(X86::RAX, RegState::Implicit) 12402 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12403 // RAX has the offset to subtracted from RSP. 12404 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12405 .addReg(X86::RSP) 12406 .addReg(X86::RAX); 12407 } 12408 } else { 12409 const char *StackProbeSymbol = 12410 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12411 12412 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12413 .addExternalSymbol(StackProbeSymbol) 12414 .addReg(X86::EAX, RegState::Implicit) 12415 .addReg(X86::ESP, RegState::Implicit) 12416 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12417 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12418 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12419 } 12420 12421 MI->eraseFromParent(); // The pseudo instruction is gone now. 12422 return BB; 12423} 12424 12425MachineBasicBlock * 12426X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12427 MachineBasicBlock *BB) const { 12428 // This is pretty easy. We're taking the value that we received from 12429 // our load from the relocation, sticking it in either RDI (x86-64) 12430 // or EAX and doing an indirect call. The return value will then 12431 // be in the normal return register. 12432 const X86InstrInfo *TII 12433 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12434 DebugLoc DL = MI->getDebugLoc(); 12435 MachineFunction *F = BB->getParent(); 12436 12437 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12438 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12439 12440 // Get a register mask for the lowered call. 12441 // FIXME: The 32-bit calls have non-standard calling conventions. Use a 12442 // proper register mask. 12443 const uint32_t *RegMask = 12444 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C); 12445 if (Subtarget->is64Bit()) { 12446 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12447 TII->get(X86::MOV64rm), X86::RDI) 12448 .addReg(X86::RIP) 12449 .addImm(0).addReg(0) 12450 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12451 MI->getOperand(3).getTargetFlags()) 12452 .addReg(0); 12453 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12454 addDirectMem(MIB, X86::RDI); 12455 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); 12456 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12457 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12458 TII->get(X86::MOV32rm), X86::EAX) 12459 .addReg(0) 12460 .addImm(0).addReg(0) 12461 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12462 MI->getOperand(3).getTargetFlags()) 12463 .addReg(0); 12464 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12465 addDirectMem(MIB, X86::EAX); 12466 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12467 } else { 12468 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12469 TII->get(X86::MOV32rm), X86::EAX) 12470 .addReg(TII->getGlobalBaseReg(F)) 12471 .addImm(0).addReg(0) 12472 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12473 MI->getOperand(3).getTargetFlags()) 12474 .addReg(0); 12475 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12476 addDirectMem(MIB, X86::EAX); 12477 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); 12478 } 12479 12480 MI->eraseFromParent(); // The pseudo instruction is gone now. 12481 return BB; 12482} 12483 12484MachineBasicBlock * 12485X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12486 MachineBasicBlock *BB) const { 12487 switch (MI->getOpcode()) { 12488 default: llvm_unreachable("Unexpected instr type to insert"); 12489 case X86::TAILJMPd64: 12490 case X86::TAILJMPr64: 12491 case X86::TAILJMPm64: 12492 llvm_unreachable("TAILJMP64 would not be touched here."); 12493 case X86::TCRETURNdi64: 12494 case X86::TCRETURNri64: 12495 case X86::TCRETURNmi64: 12496 return BB; 12497 case X86::WIN_ALLOCA: 12498 return EmitLoweredWinAlloca(MI, BB); 12499 case X86::SEG_ALLOCA_32: 12500 return EmitLoweredSegAlloca(MI, BB, false); 12501 case X86::SEG_ALLOCA_64: 12502 return EmitLoweredSegAlloca(MI, BB, true); 12503 case X86::TLSCall_32: 12504 case X86::TLSCall_64: 12505 return EmitLoweredTLSCall(MI, BB); 12506 case X86::CMOV_GR8: 12507 case X86::CMOV_FR32: 12508 case X86::CMOV_FR64: 12509 case X86::CMOV_V4F32: 12510 case X86::CMOV_V2F64: 12511 case X86::CMOV_V2I64: 12512 case X86::CMOV_V8F32: 12513 case X86::CMOV_V4F64: 12514 case X86::CMOV_V4I64: 12515 case X86::CMOV_GR16: 12516 case X86::CMOV_GR32: 12517 case X86::CMOV_RFP32: 12518 case X86::CMOV_RFP64: 12519 case X86::CMOV_RFP80: 12520 return EmitLoweredSelect(MI, BB); 12521 12522 case X86::FP32_TO_INT16_IN_MEM: 12523 case X86::FP32_TO_INT32_IN_MEM: 12524 case X86::FP32_TO_INT64_IN_MEM: 12525 case X86::FP64_TO_INT16_IN_MEM: 12526 case X86::FP64_TO_INT32_IN_MEM: 12527 case X86::FP64_TO_INT64_IN_MEM: 12528 case X86::FP80_TO_INT16_IN_MEM: 12529 case X86::FP80_TO_INT32_IN_MEM: 12530 case X86::FP80_TO_INT64_IN_MEM: { 12531 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12532 DebugLoc DL = MI->getDebugLoc(); 12533 12534 // Change the floating point control register to use "round towards zero" 12535 // mode when truncating to an integer value. 12536 MachineFunction *F = BB->getParent(); 12537 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12538 addFrameReference(BuildMI(*BB, MI, DL, 12539 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12540 12541 // Load the old value of the high byte of the control word... 12542 unsigned OldCW = 12543 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass); 12544 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12545 CWFrameIdx); 12546 12547 // Set the high part to be round to zero... 12548 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12549 .addImm(0xC7F); 12550 12551 // Reload the modified control word now... 12552 addFrameReference(BuildMI(*BB, MI, DL, 12553 TII->get(X86::FLDCW16m)), CWFrameIdx); 12554 12555 // Restore the memory image of control word to original value 12556 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12557 .addReg(OldCW); 12558 12559 // Get the X86 opcode to use. 12560 unsigned Opc; 12561 switch (MI->getOpcode()) { 12562 default: llvm_unreachable("illegal opcode!"); 12563 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12564 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12565 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12566 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12567 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12568 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12569 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12570 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12571 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12572 } 12573 12574 X86AddressMode AM; 12575 MachineOperand &Op = MI->getOperand(0); 12576 if (Op.isReg()) { 12577 AM.BaseType = X86AddressMode::RegBase; 12578 AM.Base.Reg = Op.getReg(); 12579 } else { 12580 AM.BaseType = X86AddressMode::FrameIndexBase; 12581 AM.Base.FrameIndex = Op.getIndex(); 12582 } 12583 Op = MI->getOperand(1); 12584 if (Op.isImm()) 12585 AM.Scale = Op.getImm(); 12586 Op = MI->getOperand(2); 12587 if (Op.isImm()) 12588 AM.IndexReg = Op.getImm(); 12589 Op = MI->getOperand(3); 12590 if (Op.isGlobal()) { 12591 AM.GV = Op.getGlobal(); 12592 } else { 12593 AM.Disp = Op.getImm(); 12594 } 12595 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12596 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12597 12598 // Reload the original control word now. 12599 addFrameReference(BuildMI(*BB, MI, DL, 12600 TII->get(X86::FLDCW16m)), CWFrameIdx); 12601 12602 MI->eraseFromParent(); // The pseudo instruction is gone now. 12603 return BB; 12604 } 12605 // String/text processing lowering. 12606 case X86::PCMPISTRM128REG: 12607 case X86::VPCMPISTRM128REG: 12608 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12609 case X86::PCMPISTRM128MEM: 12610 case X86::VPCMPISTRM128MEM: 12611 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12612 case X86::PCMPESTRM128REG: 12613 case X86::VPCMPESTRM128REG: 12614 return EmitPCMP(MI, BB, 5, false /* in mem */); 12615 case X86::PCMPESTRM128MEM: 12616 case X86::VPCMPESTRM128MEM: 12617 return EmitPCMP(MI, BB, 5, true /* in mem */); 12618 12619 // Thread synchronization. 12620 case X86::MONITOR: 12621 return EmitMonitor(MI, BB); 12622 case X86::MWAIT: 12623 return EmitMwait(MI, BB); 12624 12625 // Atomic Lowering. 12626 case X86::ATOMAND32: 12627 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12628 X86::AND32ri, X86::MOV32rm, 12629 X86::LCMPXCHG32, 12630 X86::NOT32r, X86::EAX, 12631 &X86::GR32RegClass); 12632 case X86::ATOMOR32: 12633 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12634 X86::OR32ri, X86::MOV32rm, 12635 X86::LCMPXCHG32, 12636 X86::NOT32r, X86::EAX, 12637 &X86::GR32RegClass); 12638 case X86::ATOMXOR32: 12639 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12640 X86::XOR32ri, X86::MOV32rm, 12641 X86::LCMPXCHG32, 12642 X86::NOT32r, X86::EAX, 12643 &X86::GR32RegClass); 12644 case X86::ATOMNAND32: 12645 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12646 X86::AND32ri, X86::MOV32rm, 12647 X86::LCMPXCHG32, 12648 X86::NOT32r, X86::EAX, 12649 &X86::GR32RegClass, true); 12650 case X86::ATOMMIN32: 12651 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12652 case X86::ATOMMAX32: 12653 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12654 case X86::ATOMUMIN32: 12655 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12656 case X86::ATOMUMAX32: 12657 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12658 12659 case X86::ATOMAND16: 12660 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12661 X86::AND16ri, X86::MOV16rm, 12662 X86::LCMPXCHG16, 12663 X86::NOT16r, X86::AX, 12664 &X86::GR16RegClass); 12665 case X86::ATOMOR16: 12666 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12667 X86::OR16ri, X86::MOV16rm, 12668 X86::LCMPXCHG16, 12669 X86::NOT16r, X86::AX, 12670 &X86::GR16RegClass); 12671 case X86::ATOMXOR16: 12672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12673 X86::XOR16ri, X86::MOV16rm, 12674 X86::LCMPXCHG16, 12675 X86::NOT16r, X86::AX, 12676 &X86::GR16RegClass); 12677 case X86::ATOMNAND16: 12678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12679 X86::AND16ri, X86::MOV16rm, 12680 X86::LCMPXCHG16, 12681 X86::NOT16r, X86::AX, 12682 &X86::GR16RegClass, true); 12683 case X86::ATOMMIN16: 12684 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12685 case X86::ATOMMAX16: 12686 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12687 case X86::ATOMUMIN16: 12688 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12689 case X86::ATOMUMAX16: 12690 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12691 12692 case X86::ATOMAND8: 12693 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12694 X86::AND8ri, X86::MOV8rm, 12695 X86::LCMPXCHG8, 12696 X86::NOT8r, X86::AL, 12697 &X86::GR8RegClass); 12698 case X86::ATOMOR8: 12699 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12700 X86::OR8ri, X86::MOV8rm, 12701 X86::LCMPXCHG8, 12702 X86::NOT8r, X86::AL, 12703 &X86::GR8RegClass); 12704 case X86::ATOMXOR8: 12705 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12706 X86::XOR8ri, X86::MOV8rm, 12707 X86::LCMPXCHG8, 12708 X86::NOT8r, X86::AL, 12709 &X86::GR8RegClass); 12710 case X86::ATOMNAND8: 12711 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12712 X86::AND8ri, X86::MOV8rm, 12713 X86::LCMPXCHG8, 12714 X86::NOT8r, X86::AL, 12715 &X86::GR8RegClass, true); 12716 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12717 // This group is for 64-bit host. 12718 case X86::ATOMAND64: 12719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12720 X86::AND64ri32, X86::MOV64rm, 12721 X86::LCMPXCHG64, 12722 X86::NOT64r, X86::RAX, 12723 &X86::GR64RegClass); 12724 case X86::ATOMOR64: 12725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12726 X86::OR64ri32, X86::MOV64rm, 12727 X86::LCMPXCHG64, 12728 X86::NOT64r, X86::RAX, 12729 &X86::GR64RegClass); 12730 case X86::ATOMXOR64: 12731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12732 X86::XOR64ri32, X86::MOV64rm, 12733 X86::LCMPXCHG64, 12734 X86::NOT64r, X86::RAX, 12735 &X86::GR64RegClass); 12736 case X86::ATOMNAND64: 12737 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12738 X86::AND64ri32, X86::MOV64rm, 12739 X86::LCMPXCHG64, 12740 X86::NOT64r, X86::RAX, 12741 &X86::GR64RegClass, true); 12742 case X86::ATOMMIN64: 12743 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12744 case X86::ATOMMAX64: 12745 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12746 case X86::ATOMUMIN64: 12747 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12748 case X86::ATOMUMAX64: 12749 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12750 12751 // This group does 64-bit operations on a 32-bit host. 12752 case X86::ATOMAND6432: 12753 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12754 X86::AND32rr, X86::AND32rr, 12755 X86::AND32ri, X86::AND32ri, 12756 false); 12757 case X86::ATOMOR6432: 12758 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12759 X86::OR32rr, X86::OR32rr, 12760 X86::OR32ri, X86::OR32ri, 12761 false); 12762 case X86::ATOMXOR6432: 12763 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12764 X86::XOR32rr, X86::XOR32rr, 12765 X86::XOR32ri, X86::XOR32ri, 12766 false); 12767 case X86::ATOMNAND6432: 12768 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12769 X86::AND32rr, X86::AND32rr, 12770 X86::AND32ri, X86::AND32ri, 12771 true); 12772 case X86::ATOMADD6432: 12773 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12774 X86::ADD32rr, X86::ADC32rr, 12775 X86::ADD32ri, X86::ADC32ri, 12776 false); 12777 case X86::ATOMSUB6432: 12778 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12779 X86::SUB32rr, X86::SBB32rr, 12780 X86::SUB32ri, X86::SBB32ri, 12781 false); 12782 case X86::ATOMSWAP6432: 12783 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12784 X86::MOV32rr, X86::MOV32rr, 12785 X86::MOV32ri, X86::MOV32ri, 12786 false); 12787 case X86::VASTART_SAVE_XMM_REGS: 12788 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12789 12790 case X86::VAARG_64: 12791 return EmitVAARG64WithCustomInserter(MI, BB); 12792 } 12793} 12794 12795//===----------------------------------------------------------------------===// 12796// X86 Optimization Hooks 12797//===----------------------------------------------------------------------===// 12798 12799void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12800 APInt &KnownZero, 12801 APInt &KnownOne, 12802 const SelectionDAG &DAG, 12803 unsigned Depth) const { 12804 unsigned BitWidth = KnownZero.getBitWidth(); 12805 unsigned Opc = Op.getOpcode(); 12806 assert((Opc >= ISD::BUILTIN_OP_END || 12807 Opc == ISD::INTRINSIC_WO_CHAIN || 12808 Opc == ISD::INTRINSIC_W_CHAIN || 12809 Opc == ISD::INTRINSIC_VOID) && 12810 "Should use MaskedValueIsZero if you don't know whether Op" 12811 " is a target node!"); 12812 12813 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything. 12814 switch (Opc) { 12815 default: break; 12816 case X86ISD::ADD: 12817 case X86ISD::SUB: 12818 case X86ISD::ADC: 12819 case X86ISD::SBB: 12820 case X86ISD::SMUL: 12821 case X86ISD::UMUL: 12822 case X86ISD::INC: 12823 case X86ISD::DEC: 12824 case X86ISD::OR: 12825 case X86ISD::XOR: 12826 case X86ISD::AND: 12827 // These nodes' second result is a boolean. 12828 if (Op.getResNo() == 0) 12829 break; 12830 // Fallthrough 12831 case X86ISD::SETCC: 12832 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); 12833 break; 12834 case ISD::INTRINSIC_WO_CHAIN: { 12835 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12836 unsigned NumLoBits = 0; 12837 switch (IntId) { 12838 default: break; 12839 case Intrinsic::x86_sse_movmsk_ps: 12840 case Intrinsic::x86_avx_movmsk_ps_256: 12841 case Intrinsic::x86_sse2_movmsk_pd: 12842 case Intrinsic::x86_avx_movmsk_pd_256: 12843 case Intrinsic::x86_mmx_pmovmskb: 12844 case Intrinsic::x86_sse2_pmovmskb_128: 12845 case Intrinsic::x86_avx2_pmovmskb: { 12846 // High bits of movmskp{s|d}, pmovmskb are known zero. 12847 switch (IntId) { 12848 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 12849 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12850 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12851 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12852 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12853 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12854 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12855 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12856 } 12857 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits); 12858 break; 12859 } 12860 } 12861 break; 12862 } 12863 } 12864} 12865 12866unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12867 unsigned Depth) const { 12868 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12869 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12870 return Op.getValueType().getScalarType().getSizeInBits(); 12871 12872 // Fallback case. 12873 return 1; 12874} 12875 12876/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12877/// node is a GlobalAddress + offset. 12878bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12879 const GlobalValue* &GA, 12880 int64_t &Offset) const { 12881 if (N->getOpcode() == X86ISD::Wrapper) { 12882 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12883 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12884 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12885 return true; 12886 } 12887 } 12888 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12889} 12890 12891/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12892/// same as extracting the high 128-bit part of 256-bit vector and then 12893/// inserting the result into the low part of a new 256-bit vector 12894static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12895 EVT VT = SVOp->getValueType(0); 12896 unsigned NumElems = VT.getVectorNumElements(); 12897 12898 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12899 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j) 12900 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12901 SVOp->getMaskElt(j) >= 0) 12902 return false; 12903 12904 return true; 12905} 12906 12907/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12908/// same as extracting the low 128-bit part of 256-bit vector and then 12909/// inserting the result into the high part of a new 256-bit vector 12910static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12911 EVT VT = SVOp->getValueType(0); 12912 unsigned NumElems = VT.getVectorNumElements(); 12913 12914 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12915 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j) 12916 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12917 SVOp->getMaskElt(j) >= 0) 12918 return false; 12919 12920 return true; 12921} 12922 12923/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12924static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12925 TargetLowering::DAGCombinerInfo &DCI, 12926 const X86Subtarget* Subtarget) { 12927 DebugLoc dl = N->getDebugLoc(); 12928 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12929 SDValue V1 = SVOp->getOperand(0); 12930 SDValue V2 = SVOp->getOperand(1); 12931 EVT VT = SVOp->getValueType(0); 12932 unsigned NumElems = VT.getVectorNumElements(); 12933 12934 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12935 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12936 // 12937 // 0,0,0,... 12938 // | 12939 // V UNDEF BUILD_VECTOR UNDEF 12940 // \ / \ / 12941 // CONCAT_VECTOR CONCAT_VECTOR 12942 // \ / 12943 // \ / 12944 // RESULT: V + zero extended 12945 // 12946 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12947 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12948 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12949 return SDValue(); 12950 12951 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12952 return SDValue(); 12953 12954 // To match the shuffle mask, the first half of the mask should 12955 // be exactly the first vector, and all the rest a splat with the 12956 // first element of the second one. 12957 for (unsigned i = 0; i != NumElems/2; ++i) 12958 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12959 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12960 return SDValue(); 12961 12962 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12963 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12964 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12965 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12966 SDValue ResNode = 12967 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12968 Ld->getMemoryVT(), 12969 Ld->getPointerInfo(), 12970 Ld->getAlignment(), 12971 false/*isVolatile*/, true/*ReadMem*/, 12972 false/*WriteMem*/); 12973 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12974 } 12975 12976 // Emit a zeroed vector and insert the desired subvector on its 12977 // first half. 12978 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl); 12979 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl); 12980 return DCI.CombineTo(N, InsV); 12981 } 12982 12983 //===--------------------------------------------------------------------===// 12984 // Combine some shuffles into subvector extracts and inserts: 12985 // 12986 12987 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12988 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12989 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl); 12990 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl); 12991 return DCI.CombineTo(N, InsV); 12992 } 12993 12994 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12995 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12996 SDValue V = Extract128BitVector(V1, 0, DAG, dl); 12997 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl); 12998 return DCI.CombineTo(N, InsV); 12999 } 13000 13001 return SDValue(); 13002} 13003 13004/// PerformShuffleCombine - Performs several different shuffle combines. 13005static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 13006 TargetLowering::DAGCombinerInfo &DCI, 13007 const X86Subtarget *Subtarget) { 13008 DebugLoc dl = N->getDebugLoc(); 13009 EVT VT = N->getValueType(0); 13010 13011 // Don't create instructions with illegal types after legalize types has run. 13012 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13013 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 13014 return SDValue(); 13015 13016 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 13017 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 13018 N->getOpcode() == ISD::VECTOR_SHUFFLE) 13019 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); 13020 13021 // Only handle 128 wide vector from here on. 13022 if (VT.getSizeInBits() != 128) 13023 return SDValue(); 13024 13025 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 13026 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 13027 // consecutive, non-overlapping, and in the right order. 13028 SmallVector<SDValue, 16> Elts; 13029 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 13030 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 13031 13032 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 13033} 13034 13035 13036/// DCI, PerformTruncateCombine - Converts truncate operation to 13037/// a sequence of vector shuffle operations. 13038/// It is possible when we truncate 256-bit vector to 128-bit vector 13039 13040SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, 13041 DAGCombinerInfo &DCI) const { 13042 if (!DCI.isBeforeLegalizeOps()) 13043 return SDValue(); 13044 13045 if (!Subtarget->hasAVX()) 13046 return SDValue(); 13047 13048 EVT VT = N->getValueType(0); 13049 SDValue Op = N->getOperand(0); 13050 EVT OpVT = Op.getValueType(); 13051 DebugLoc dl = N->getDebugLoc(); 13052 13053 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) { 13054 13055 if (Subtarget->hasAVX2()) { 13056 // AVX2: v4i64 -> v4i32 13057 13058 // VPERMD 13059 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1}; 13060 13061 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op); 13062 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32), 13063 ShufMask); 13064 13065 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, 13066 DAG.getIntPtrConstant(0)); 13067 } 13068 13069 // AVX: v4i64 -> v4i32 13070 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13071 DAG.getIntPtrConstant(0)); 13072 13073 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13074 DAG.getIntPtrConstant(2)); 13075 13076 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13077 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13078 13079 // PSHUFD 13080 static const int ShufMask1[] = {0, 2, 0, 0}; 13081 13082 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1); 13083 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1); 13084 13085 // MOVLHPS 13086 static const int ShufMask2[] = {0, 1, 4, 5}; 13087 13088 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2); 13089 } 13090 13091 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) { 13092 13093 if (Subtarget->hasAVX2()) { 13094 // AVX2: v8i32 -> v8i16 13095 13096 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op); 13097 13098 // PSHUFB 13099 SmallVector<SDValue,32> pshufbMask; 13100 for (unsigned i = 0; i < 2; ++i) { 13101 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8)); 13102 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8)); 13103 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8)); 13104 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8)); 13105 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8)); 13106 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8)); 13107 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8)); 13108 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8)); 13109 for (unsigned j = 0; j < 8; ++j) 13110 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 13111 } 13112 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8, 13113 &pshufbMask[0], 32); 13114 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV); 13115 13116 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op); 13117 13118 static const int ShufMask[] = {0, 2, -1, -1}; 13119 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64), 13120 &ShufMask[0]); 13121 13122 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op, 13123 DAG.getIntPtrConstant(0)); 13124 13125 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 13126 } 13127 13128 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13129 DAG.getIntPtrConstant(0)); 13130 13131 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op, 13132 DAG.getIntPtrConstant(4)); 13133 13134 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo); 13135 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi); 13136 13137 // PSHUFB 13138 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13, 13139 -1, -1, -1, -1, -1, -1, -1, -1}; 13140 13141 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8), 13142 ShufMask1); 13143 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8), 13144 ShufMask1); 13145 13146 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo); 13147 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi); 13148 13149 // MOVLHPS 13150 static const int ShufMask2[] = {0, 1, 4, 5}; 13151 13152 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2); 13153 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res); 13154 } 13155 13156 return SDValue(); 13157} 13158 13159/// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target 13160/// specific shuffle of a load can be folded into a single element load. 13161/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but 13162/// shuffles have been customed lowered so we need to handle those here. 13163static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, 13164 TargetLowering::DAGCombinerInfo &DCI) { 13165 if (DCI.isBeforeLegalizeOps()) 13166 return SDValue(); 13167 13168 SDValue InVec = N->getOperand(0); 13169 SDValue EltNo = N->getOperand(1); 13170 13171 if (!isa<ConstantSDNode>(EltNo)) 13172 return SDValue(); 13173 13174 EVT VT = InVec.getValueType(); 13175 13176 bool HasShuffleIntoBitcast = false; 13177 if (InVec.getOpcode() == ISD::BITCAST) { 13178 // Don't duplicate a load with other uses. 13179 if (!InVec.hasOneUse()) 13180 return SDValue(); 13181 EVT BCVT = InVec.getOperand(0).getValueType(); 13182 if (BCVT.getVectorNumElements() != VT.getVectorNumElements()) 13183 return SDValue(); 13184 InVec = InVec.getOperand(0); 13185 HasShuffleIntoBitcast = true; 13186 } 13187 13188 if (!isTargetShuffle(InVec.getOpcode())) 13189 return SDValue(); 13190 13191 // Don't duplicate a load with other uses. 13192 if (!InVec.hasOneUse()) 13193 return SDValue(); 13194 13195 SmallVector<int, 16> ShuffleMask; 13196 bool UnaryShuffle; 13197 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle)) 13198 return SDValue(); 13199 13200 // Select the input vector, guarding against out of range extract vector. 13201 unsigned NumElems = VT.getVectorNumElements(); 13202 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 13203 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt]; 13204 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0) 13205 : InVec.getOperand(1); 13206 13207 // If inputs to shuffle are the same for both ops, then allow 2 uses 13208 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1; 13209 13210 if (LdNode.getOpcode() == ISD::BITCAST) { 13211 // Don't duplicate a load with other uses. 13212 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0)) 13213 return SDValue(); 13214 13215 AllowedUses = 1; // only allow 1 load use if we have a bitcast 13216 LdNode = LdNode.getOperand(0); 13217 } 13218 13219 if (!ISD::isNormalLoad(LdNode.getNode())) 13220 return SDValue(); 13221 13222 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode); 13223 13224 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile()) 13225 return SDValue(); 13226 13227 if (HasShuffleIntoBitcast) { 13228 // If there's a bitcast before the shuffle, check if the load type and 13229 // alignment is valid. 13230 unsigned Align = LN0->getAlignment(); 13231 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13232 unsigned NewAlign = TLI.getTargetData()-> 13233 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 13234 13235 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 13236 return SDValue(); 13237 } 13238 13239 // All checks match so transform back to vector_shuffle so that DAG combiner 13240 // can finish the job 13241 DebugLoc dl = N->getDebugLoc(); 13242 13243 // Create shuffle node taking into account the case that its a unary shuffle 13244 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1); 13245 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl, 13246 InVec.getOperand(0), Shuffle, 13247 &ShuffleMask[0]); 13248 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); 13249 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle, 13250 EltNo); 13251} 13252 13253/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 13254/// generation and convert it from being a bunch of shuffles and extracts 13255/// to a simple store and scalar loads to extract the elements. 13256static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 13257 TargetLowering::DAGCombinerInfo &DCI) { 13258 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); 13259 if (NewOp.getNode()) 13260 return NewOp; 13261 13262 SDValue InputVector = N->getOperand(0); 13263 13264 // Only operate on vectors of 4 elements, where the alternative shuffling 13265 // gets to be more expensive. 13266 if (InputVector.getValueType() != MVT::v4i32) 13267 return SDValue(); 13268 13269 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 13270 // single use which is a sign-extend or zero-extend, and all elements are 13271 // used. 13272 SmallVector<SDNode *, 4> Uses; 13273 unsigned ExtractedElements = 0; 13274 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 13275 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 13276 if (UI.getUse().getResNo() != InputVector.getResNo()) 13277 return SDValue(); 13278 13279 SDNode *Extract = *UI; 13280 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 13281 return SDValue(); 13282 13283 if (Extract->getValueType(0) != MVT::i32) 13284 return SDValue(); 13285 if (!Extract->hasOneUse()) 13286 return SDValue(); 13287 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 13288 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 13289 return SDValue(); 13290 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 13291 return SDValue(); 13292 13293 // Record which element was extracted. 13294 ExtractedElements |= 13295 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 13296 13297 Uses.push_back(Extract); 13298 } 13299 13300 // If not all the elements were used, this may not be worthwhile. 13301 if (ExtractedElements != 15) 13302 return SDValue(); 13303 13304 // Ok, we've now decided to do the transformation. 13305 DebugLoc dl = InputVector.getDebugLoc(); 13306 13307 // Store the value to a temporary stack slot. 13308 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 13309 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 13310 MachinePointerInfo(), false, false, 0); 13311 13312 // Replace each use (extract) with a load of the appropriate element. 13313 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 13314 UE = Uses.end(); UI != UE; ++UI) { 13315 SDNode *Extract = *UI; 13316 13317 // cOMpute the element's address. 13318 SDValue Idx = Extract->getOperand(1); 13319 unsigned EltSize = 13320 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 13321 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 13322 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13323 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 13324 13325 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 13326 StackPtr, OffsetVal); 13327 13328 // Load the scalar. 13329 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 13330 ScalarAddr, MachinePointerInfo(), 13331 false, false, false, 0); 13332 13333 // Replace the exact with the load. 13334 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 13335 } 13336 13337 // The replacement was made in place; don't return anything. 13338 return SDValue(); 13339} 13340 13341/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 13342/// nodes. 13343static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 13344 TargetLowering::DAGCombinerInfo &DCI, 13345 const X86Subtarget *Subtarget) { 13346 13347 13348 DebugLoc DL = N->getDebugLoc(); 13349 SDValue Cond = N->getOperand(0); 13350 // Get the LHS/RHS of the select. 13351 SDValue LHS = N->getOperand(1); 13352 SDValue RHS = N->getOperand(2); 13353 EVT VT = LHS.getValueType(); 13354 13355 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 13356 // instructions match the semantics of the common C idiom x<y?x:y but not 13357 // x<=y?x:y, because of how they handle negative zero (which can be 13358 // ignored in unsafe-math mode). 13359 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 13360 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 13361 (Subtarget->hasSSE2() || 13362 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 13363 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13364 13365 unsigned Opcode = 0; 13366 // Check for x CC y ? x : y. 13367 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13368 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13369 switch (CC) { 13370 default: break; 13371 case ISD::SETULT: 13372 // Converting this to a min would handle NaNs incorrectly, and swapping 13373 // the operands would cause it to handle comparisons between positive 13374 // and negative zero incorrectly. 13375 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13376 if (!DAG.getTarget().Options.UnsafeFPMath && 13377 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13378 break; 13379 std::swap(LHS, RHS); 13380 } 13381 Opcode = X86ISD::FMIN; 13382 break; 13383 case ISD::SETOLE: 13384 // Converting this to a min would handle comparisons between positive 13385 // and negative zero incorrectly. 13386 if (!DAG.getTarget().Options.UnsafeFPMath && 13387 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13388 break; 13389 Opcode = X86ISD::FMIN; 13390 break; 13391 case ISD::SETULE: 13392 // Converting this to a min would handle both negative zeros and NaNs 13393 // incorrectly, but we can swap the operands to fix both. 13394 std::swap(LHS, RHS); 13395 case ISD::SETOLT: 13396 case ISD::SETLT: 13397 case ISD::SETLE: 13398 Opcode = X86ISD::FMIN; 13399 break; 13400 13401 case ISD::SETOGE: 13402 // Converting this to a max would handle comparisons between positive 13403 // and negative zero incorrectly. 13404 if (!DAG.getTarget().Options.UnsafeFPMath && 13405 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 13406 break; 13407 Opcode = X86ISD::FMAX; 13408 break; 13409 case ISD::SETUGT: 13410 // Converting this to a max would handle NaNs incorrectly, and swapping 13411 // the operands would cause it to handle comparisons between positive 13412 // and negative zero incorrectly. 13413 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 13414 if (!DAG.getTarget().Options.UnsafeFPMath && 13415 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 13416 break; 13417 std::swap(LHS, RHS); 13418 } 13419 Opcode = X86ISD::FMAX; 13420 break; 13421 case ISD::SETUGE: 13422 // Converting this to a max would handle both negative zeros and NaNs 13423 // incorrectly, but we can swap the operands to fix both. 13424 std::swap(LHS, RHS); 13425 case ISD::SETOGT: 13426 case ISD::SETGT: 13427 case ISD::SETGE: 13428 Opcode = X86ISD::FMAX; 13429 break; 13430 } 13431 // Check for x CC y ? y : x -- a min/max with reversed arms. 13432 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 13433 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 13434 switch (CC) { 13435 default: break; 13436 case ISD::SETOGE: 13437 // Converting this to a min would handle comparisons between positive 13438 // and negative zero incorrectly, and swapping the operands would 13439 // cause it to handle NaNs incorrectly. 13440 if (!DAG.getTarget().Options.UnsafeFPMath && 13441 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 13442 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13443 break; 13444 std::swap(LHS, RHS); 13445 } 13446 Opcode = X86ISD::FMIN; 13447 break; 13448 case ISD::SETUGT: 13449 // Converting this to a min would handle NaNs incorrectly. 13450 if (!DAG.getTarget().Options.UnsafeFPMath && 13451 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 13452 break; 13453 Opcode = X86ISD::FMIN; 13454 break; 13455 case ISD::SETUGE: 13456 // Converting this to a min would handle both negative zeros and NaNs 13457 // incorrectly, but we can swap the operands to fix both. 13458 std::swap(LHS, RHS); 13459 case ISD::SETOGT: 13460 case ISD::SETGT: 13461 case ISD::SETGE: 13462 Opcode = X86ISD::FMIN; 13463 break; 13464 13465 case ISD::SETULT: 13466 // Converting this to a max would handle NaNs incorrectly. 13467 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13468 break; 13469 Opcode = X86ISD::FMAX; 13470 break; 13471 case ISD::SETOLE: 13472 // Converting this to a max would handle comparisons between positive 13473 // and negative zero incorrectly, and swapping the operands would 13474 // cause it to handle NaNs incorrectly. 13475 if (!DAG.getTarget().Options.UnsafeFPMath && 13476 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 13477 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 13478 break; 13479 std::swap(LHS, RHS); 13480 } 13481 Opcode = X86ISD::FMAX; 13482 break; 13483 case ISD::SETULE: 13484 // Converting this to a max would handle both negative zeros and NaNs 13485 // incorrectly, but we can swap the operands to fix both. 13486 std::swap(LHS, RHS); 13487 case ISD::SETOLT: 13488 case ISD::SETLT: 13489 case ISD::SETLE: 13490 Opcode = X86ISD::FMAX; 13491 break; 13492 } 13493 } 13494 13495 if (Opcode) 13496 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13497 } 13498 13499 // If this is a select between two integer constants, try to do some 13500 // optimizations. 13501 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13502 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13503 // Don't do this for crazy integer types. 13504 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13505 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13506 // so that TrueC (the true value) is larger than FalseC. 13507 bool NeedsCondInvert = false; 13508 13509 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13510 // Efficiently invertible. 13511 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13512 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13513 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13514 NeedsCondInvert = true; 13515 std::swap(TrueC, FalseC); 13516 } 13517 13518 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13519 if (FalseC->getAPIntValue() == 0 && 13520 TrueC->getAPIntValue().isPowerOf2()) { 13521 if (NeedsCondInvert) // Invert the condition if needed. 13522 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13523 DAG.getConstant(1, Cond.getValueType())); 13524 13525 // Zero extend the condition if needed. 13526 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13527 13528 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13529 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13530 DAG.getConstant(ShAmt, MVT::i8)); 13531 } 13532 13533 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13534 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13535 if (NeedsCondInvert) // Invert the condition if needed. 13536 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13537 DAG.getConstant(1, Cond.getValueType())); 13538 13539 // Zero extend the condition if needed. 13540 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13541 FalseC->getValueType(0), Cond); 13542 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13543 SDValue(FalseC, 0)); 13544 } 13545 13546 // Optimize cases that will turn into an LEA instruction. This requires 13547 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13548 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13549 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13550 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13551 13552 bool isFastMultiplier = false; 13553 if (Diff < 10) { 13554 switch ((unsigned char)Diff) { 13555 default: break; 13556 case 1: // result = add base, cond 13557 case 2: // result = lea base( , cond*2) 13558 case 3: // result = lea base(cond, cond*2) 13559 case 4: // result = lea base( , cond*4) 13560 case 5: // result = lea base(cond, cond*4) 13561 case 8: // result = lea base( , cond*8) 13562 case 9: // result = lea base(cond, cond*8) 13563 isFastMultiplier = true; 13564 break; 13565 } 13566 } 13567 13568 if (isFastMultiplier) { 13569 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13570 if (NeedsCondInvert) // Invert the condition if needed. 13571 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13572 DAG.getConstant(1, Cond.getValueType())); 13573 13574 // Zero extend the condition if needed. 13575 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13576 Cond); 13577 // Scale the condition by the difference. 13578 if (Diff != 1) 13579 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13580 DAG.getConstant(Diff, Cond.getValueType())); 13581 13582 // Add the base if non-zero. 13583 if (FalseC->getAPIntValue() != 0) 13584 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13585 SDValue(FalseC, 0)); 13586 return Cond; 13587 } 13588 } 13589 } 13590 } 13591 13592 // Canonicalize max and min: 13593 // (x > y) ? x : y -> (x >= y) ? x : y 13594 // (x < y) ? x : y -> (x <= y) ? x : y 13595 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13596 // the need for an extra compare 13597 // against zero. e.g. 13598 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13599 // subl %esi, %edi 13600 // testl %edi, %edi 13601 // movl $0, %eax 13602 // cmovgl %edi, %eax 13603 // => 13604 // xorl %eax, %eax 13605 // subl %esi, $edi 13606 // cmovsl %eax, %edi 13607 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13608 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13609 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13610 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13611 switch (CC) { 13612 default: break; 13613 case ISD::SETLT: 13614 case ISD::SETGT: { 13615 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13616 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13617 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13618 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13619 } 13620 } 13621 } 13622 13623 // If we know that this node is legal then we know that it is going to be 13624 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13625 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13626 // to simplify previous instructions. 13627 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13628 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13629 !DCI.isBeforeLegalize() && 13630 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13631 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13632 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13633 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13634 13635 APInt KnownZero, KnownOne; 13636 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13637 DCI.isBeforeLegalizeOps()); 13638 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13639 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13640 DCI.CommitTargetLoweringOpt(TLO); 13641 } 13642 13643 return SDValue(); 13644} 13645 13646/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13647static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13648 TargetLowering::DAGCombinerInfo &DCI) { 13649 DebugLoc DL = N->getDebugLoc(); 13650 13651 // If the flag operand isn't dead, don't touch this CMOV. 13652 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13653 return SDValue(); 13654 13655 SDValue FalseOp = N->getOperand(0); 13656 SDValue TrueOp = N->getOperand(1); 13657 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13658 SDValue Cond = N->getOperand(3); 13659 if (CC == X86::COND_E || CC == X86::COND_NE) { 13660 switch (Cond.getOpcode()) { 13661 default: break; 13662 case X86ISD::BSR: 13663 case X86ISD::BSF: 13664 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13665 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13666 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13667 } 13668 } 13669 13670 // If this is a select between two integer constants, try to do some 13671 // optimizations. Note that the operands are ordered the opposite of SELECT 13672 // operands. 13673 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13674 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13675 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13676 // larger than FalseC (the false value). 13677 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13678 CC = X86::GetOppositeBranchCondition(CC); 13679 std::swap(TrueC, FalseC); 13680 } 13681 13682 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13683 // This is efficient for any integer data type (including i8/i16) and 13684 // shift amount. 13685 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13686 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13687 DAG.getConstant(CC, MVT::i8), Cond); 13688 13689 // Zero extend the condition if needed. 13690 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13691 13692 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13693 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13694 DAG.getConstant(ShAmt, MVT::i8)); 13695 if (N->getNumValues() == 2) // Dead flag value? 13696 return DCI.CombineTo(N, Cond, SDValue()); 13697 return Cond; 13698 } 13699 13700 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13701 // for any integer data type, including i8/i16. 13702 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13703 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13704 DAG.getConstant(CC, MVT::i8), Cond); 13705 13706 // Zero extend the condition if needed. 13707 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13708 FalseC->getValueType(0), Cond); 13709 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13710 SDValue(FalseC, 0)); 13711 13712 if (N->getNumValues() == 2) // Dead flag value? 13713 return DCI.CombineTo(N, Cond, SDValue()); 13714 return Cond; 13715 } 13716 13717 // Optimize cases that will turn into an LEA instruction. This requires 13718 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13719 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13720 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13721 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13722 13723 bool isFastMultiplier = false; 13724 if (Diff < 10) { 13725 switch ((unsigned char)Diff) { 13726 default: break; 13727 case 1: // result = add base, cond 13728 case 2: // result = lea base( , cond*2) 13729 case 3: // result = lea base(cond, cond*2) 13730 case 4: // result = lea base( , cond*4) 13731 case 5: // result = lea base(cond, cond*4) 13732 case 8: // result = lea base( , cond*8) 13733 case 9: // result = lea base(cond, cond*8) 13734 isFastMultiplier = true; 13735 break; 13736 } 13737 } 13738 13739 if (isFastMultiplier) { 13740 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13741 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13742 DAG.getConstant(CC, MVT::i8), Cond); 13743 // Zero extend the condition if needed. 13744 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13745 Cond); 13746 // Scale the condition by the difference. 13747 if (Diff != 1) 13748 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13749 DAG.getConstant(Diff, Cond.getValueType())); 13750 13751 // Add the base if non-zero. 13752 if (FalseC->getAPIntValue() != 0) 13753 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13754 SDValue(FalseC, 0)); 13755 if (N->getNumValues() == 2) // Dead flag value? 13756 return DCI.CombineTo(N, Cond, SDValue()); 13757 return Cond; 13758 } 13759 } 13760 } 13761 } 13762 return SDValue(); 13763} 13764 13765 13766/// PerformMulCombine - Optimize a single multiply with constant into two 13767/// in order to implement it with two cheaper instructions, e.g. 13768/// LEA + SHL, LEA + LEA. 13769static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13770 TargetLowering::DAGCombinerInfo &DCI) { 13771 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13772 return SDValue(); 13773 13774 EVT VT = N->getValueType(0); 13775 if (VT != MVT::i64) 13776 return SDValue(); 13777 13778 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13779 if (!C) 13780 return SDValue(); 13781 uint64_t MulAmt = C->getZExtValue(); 13782 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13783 return SDValue(); 13784 13785 uint64_t MulAmt1 = 0; 13786 uint64_t MulAmt2 = 0; 13787 if ((MulAmt % 9) == 0) { 13788 MulAmt1 = 9; 13789 MulAmt2 = MulAmt / 9; 13790 } else if ((MulAmt % 5) == 0) { 13791 MulAmt1 = 5; 13792 MulAmt2 = MulAmt / 5; 13793 } else if ((MulAmt % 3) == 0) { 13794 MulAmt1 = 3; 13795 MulAmt2 = MulAmt / 3; 13796 } 13797 if (MulAmt2 && 13798 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13799 DebugLoc DL = N->getDebugLoc(); 13800 13801 if (isPowerOf2_64(MulAmt2) && 13802 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13803 // If second multiplifer is pow2, issue it first. We want the multiply by 13804 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13805 // is an add. 13806 std::swap(MulAmt1, MulAmt2); 13807 13808 SDValue NewMul; 13809 if (isPowerOf2_64(MulAmt1)) 13810 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13811 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13812 else 13813 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13814 DAG.getConstant(MulAmt1, VT)); 13815 13816 if (isPowerOf2_64(MulAmt2)) 13817 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13818 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13819 else 13820 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13821 DAG.getConstant(MulAmt2, VT)); 13822 13823 // Do not add new nodes to DAG combiner worklist. 13824 DCI.CombineTo(N, NewMul, false); 13825 } 13826 return SDValue(); 13827} 13828 13829static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13830 SDValue N0 = N->getOperand(0); 13831 SDValue N1 = N->getOperand(1); 13832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13833 EVT VT = N0.getValueType(); 13834 13835 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13836 // since the result of setcc_c is all zero's or all ones. 13837 if (VT.isInteger() && !VT.isVector() && 13838 N1C && N0.getOpcode() == ISD::AND && 13839 N0.getOperand(1).getOpcode() == ISD::Constant) { 13840 SDValue N00 = N0.getOperand(0); 13841 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13842 ((N00.getOpcode() == ISD::ANY_EXTEND || 13843 N00.getOpcode() == ISD::ZERO_EXTEND) && 13844 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13845 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13846 APInt ShAmt = N1C->getAPIntValue(); 13847 Mask = Mask.shl(ShAmt); 13848 if (Mask != 0) 13849 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13850 N00, DAG.getConstant(Mask, VT)); 13851 } 13852 } 13853 13854 13855 // Hardware support for vector shifts is sparse which makes us scalarize the 13856 // vector operations in many cases. Also, on sandybridge ADD is faster than 13857 // shl. 13858 // (shl V, 1) -> add V,V 13859 if (isSplatVector(N1.getNode())) { 13860 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13861 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13862 // We shift all of the values by one. In many cases we do not have 13863 // hardware support for this operation. This is better expressed as an ADD 13864 // of two values. 13865 if (N1C && (1 == N1C->getZExtValue())) { 13866 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13867 } 13868 } 13869 13870 return SDValue(); 13871} 13872 13873/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13874/// when possible. 13875static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13876 TargetLowering::DAGCombinerInfo &DCI, 13877 const X86Subtarget *Subtarget) { 13878 EVT VT = N->getValueType(0); 13879 if (N->getOpcode() == ISD::SHL) { 13880 SDValue V = PerformSHLCombine(N, DAG); 13881 if (V.getNode()) return V; 13882 } 13883 13884 // On X86 with SSE2 support, we can transform this to a vector shift if 13885 // all elements are shifted by the same amount. We can't do this in legalize 13886 // because the a constant vector is typically transformed to a constant pool 13887 // so we have no knowledge of the shift amount. 13888 if (!Subtarget->hasSSE2()) 13889 return SDValue(); 13890 13891 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13892 (!Subtarget->hasAVX2() || 13893 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13894 return SDValue(); 13895 13896 SDValue ShAmtOp = N->getOperand(1); 13897 EVT EltVT = VT.getVectorElementType(); 13898 DebugLoc DL = N->getDebugLoc(); 13899 SDValue BaseShAmt = SDValue(); 13900 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13901 unsigned NumElts = VT.getVectorNumElements(); 13902 unsigned i = 0; 13903 for (; i != NumElts; ++i) { 13904 SDValue Arg = ShAmtOp.getOperand(i); 13905 if (Arg.getOpcode() == ISD::UNDEF) continue; 13906 BaseShAmt = Arg; 13907 break; 13908 } 13909 // Handle the case where the build_vector is all undef 13910 // FIXME: Should DAG allow this? 13911 if (i == NumElts) 13912 return SDValue(); 13913 13914 for (; i != NumElts; ++i) { 13915 SDValue Arg = ShAmtOp.getOperand(i); 13916 if (Arg.getOpcode() == ISD::UNDEF) continue; 13917 if (Arg != BaseShAmt) { 13918 return SDValue(); 13919 } 13920 } 13921 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13922 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13923 SDValue InVec = ShAmtOp.getOperand(0); 13924 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13925 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13926 unsigned i = 0; 13927 for (; i != NumElts; ++i) { 13928 SDValue Arg = InVec.getOperand(i); 13929 if (Arg.getOpcode() == ISD::UNDEF) continue; 13930 BaseShAmt = Arg; 13931 break; 13932 } 13933 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13934 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13935 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13936 if (C->getZExtValue() == SplatIdx) 13937 BaseShAmt = InVec.getOperand(1); 13938 } 13939 } 13940 if (BaseShAmt.getNode() == 0) { 13941 // Don't create instructions with illegal types after legalize 13942 // types has run. 13943 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && 13944 !DCI.isBeforeLegalize()) 13945 return SDValue(); 13946 13947 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13948 DAG.getIntPtrConstant(0)); 13949 } 13950 } else 13951 return SDValue(); 13952 13953 // The shift amount is an i32. 13954 if (EltVT.bitsGT(MVT::i32)) 13955 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13956 else if (EltVT.bitsLT(MVT::i32)) 13957 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13958 13959 // The shift amount is identical so we can do a vector shift. 13960 SDValue ValOp = N->getOperand(0); 13961 switch (N->getOpcode()) { 13962 default: 13963 llvm_unreachable("Unknown shift opcode!"); 13964 case ISD::SHL: 13965 switch (VT.getSimpleVT().SimpleTy) { 13966 default: return SDValue(); 13967 case MVT::v2i64: 13968 case MVT::v4i32: 13969 case MVT::v8i16: 13970 case MVT::v4i64: 13971 case MVT::v8i32: 13972 case MVT::v16i16: 13973 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13974 } 13975 case ISD::SRA: 13976 switch (VT.getSimpleVT().SimpleTy) { 13977 default: return SDValue(); 13978 case MVT::v4i32: 13979 case MVT::v8i16: 13980 case MVT::v8i32: 13981 case MVT::v16i16: 13982 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13983 } 13984 case ISD::SRL: 13985 switch (VT.getSimpleVT().SimpleTy) { 13986 default: return SDValue(); 13987 case MVT::v2i64: 13988 case MVT::v4i32: 13989 case MVT::v8i16: 13990 case MVT::v4i64: 13991 case MVT::v8i32: 13992 case MVT::v16i16: 13993 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13994 } 13995 } 13996} 13997 13998 13999// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 14000// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 14001// and friends. Likewise for OR -> CMPNEQSS. 14002static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 14003 TargetLowering::DAGCombinerInfo &DCI, 14004 const X86Subtarget *Subtarget) { 14005 unsigned opcode; 14006 14007 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 14008 // we're requiring SSE2 for both. 14009 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 14010 SDValue N0 = N->getOperand(0); 14011 SDValue N1 = N->getOperand(1); 14012 SDValue CMP0 = N0->getOperand(1); 14013 SDValue CMP1 = N1->getOperand(1); 14014 DebugLoc DL = N->getDebugLoc(); 14015 14016 // The SETCCs should both refer to the same CMP. 14017 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 14018 return SDValue(); 14019 14020 SDValue CMP00 = CMP0->getOperand(0); 14021 SDValue CMP01 = CMP0->getOperand(1); 14022 EVT VT = CMP00.getValueType(); 14023 14024 if (VT == MVT::f32 || VT == MVT::f64) { 14025 bool ExpectingFlags = false; 14026 // Check for any users that want flags: 14027 for (SDNode::use_iterator UI = N->use_begin(), 14028 UE = N->use_end(); 14029 !ExpectingFlags && UI != UE; ++UI) 14030 switch (UI->getOpcode()) { 14031 default: 14032 case ISD::BR_CC: 14033 case ISD::BRCOND: 14034 case ISD::SELECT: 14035 ExpectingFlags = true; 14036 break; 14037 case ISD::CopyToReg: 14038 case ISD::SIGN_EXTEND: 14039 case ISD::ZERO_EXTEND: 14040 case ISD::ANY_EXTEND: 14041 break; 14042 } 14043 14044 if (!ExpectingFlags) { 14045 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 14046 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 14047 14048 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 14049 X86::CondCode tmp = cc0; 14050 cc0 = cc1; 14051 cc1 = tmp; 14052 } 14053 14054 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 14055 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 14056 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 14057 X86ISD::NodeType NTOperator = is64BitFP ? 14058 X86ISD::FSETCCsd : X86ISD::FSETCCss; 14059 // FIXME: need symbolic constants for these magic numbers. 14060 // See X86ATTInstPrinter.cpp:printSSECC(). 14061 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 14062 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 14063 DAG.getConstant(x86cc, MVT::i8)); 14064 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 14065 OnesOrZeroesF); 14066 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 14067 DAG.getConstant(1, MVT::i32)); 14068 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 14069 return OneBitOfTruth; 14070 } 14071 } 14072 } 14073 } 14074 return SDValue(); 14075} 14076 14077/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 14078/// so it can be folded inside ANDNP. 14079static bool CanFoldXORWithAllOnes(const SDNode *N) { 14080 EVT VT = N->getValueType(0); 14081 14082 // Match direct AllOnes for 128 and 256-bit vectors 14083 if (ISD::isBuildVectorAllOnes(N)) 14084 return true; 14085 14086 // Look through a bit convert. 14087 if (N->getOpcode() == ISD::BITCAST) 14088 N = N->getOperand(0).getNode(); 14089 14090 // Sometimes the operand may come from a insert_subvector building a 256-bit 14091 // allones vector 14092 if (VT.getSizeInBits() == 256 && 14093 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 14094 SDValue V1 = N->getOperand(0); 14095 SDValue V2 = N->getOperand(1); 14096 14097 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 14098 V1.getOperand(0).getOpcode() == ISD::UNDEF && 14099 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 14100 ISD::isBuildVectorAllOnes(V2.getNode())) 14101 return true; 14102 } 14103 14104 return false; 14105} 14106 14107static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 14108 TargetLowering::DAGCombinerInfo &DCI, 14109 const X86Subtarget *Subtarget) { 14110 if (DCI.isBeforeLegalizeOps()) 14111 return SDValue(); 14112 14113 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14114 if (R.getNode()) 14115 return R; 14116 14117 EVT VT = N->getValueType(0); 14118 14119 // Create ANDN, BLSI, and BLSR instructions 14120 // BLSI is X & (-X) 14121 // BLSR is X & (X-1) 14122 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 14123 SDValue N0 = N->getOperand(0); 14124 SDValue N1 = N->getOperand(1); 14125 DebugLoc DL = N->getDebugLoc(); 14126 14127 // Check LHS for not 14128 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 14129 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 14130 // Check RHS for not 14131 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 14132 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 14133 14134 // Check LHS for neg 14135 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 14136 isZero(N0.getOperand(0))) 14137 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 14138 14139 // Check RHS for neg 14140 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 14141 isZero(N1.getOperand(0))) 14142 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 14143 14144 // Check LHS for X-1 14145 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14146 isAllOnes(N0.getOperand(1))) 14147 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 14148 14149 // Check RHS for X-1 14150 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14151 isAllOnes(N1.getOperand(1))) 14152 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 14153 14154 return SDValue(); 14155 } 14156 14157 // Want to form ANDNP nodes: 14158 // 1) In the hopes of then easily combining them with OR and AND nodes 14159 // to form PBLEND/PSIGN. 14160 // 2) To match ANDN packed intrinsics 14161 if (VT != MVT::v2i64 && VT != MVT::v4i64) 14162 return SDValue(); 14163 14164 SDValue N0 = N->getOperand(0); 14165 SDValue N1 = N->getOperand(1); 14166 DebugLoc DL = N->getDebugLoc(); 14167 14168 // Check LHS for vnot 14169 if (N0.getOpcode() == ISD::XOR && 14170 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 14171 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 14172 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 14173 14174 // Check RHS for vnot 14175 if (N1.getOpcode() == ISD::XOR && 14176 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 14177 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 14178 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 14179 14180 return SDValue(); 14181} 14182 14183static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 14184 TargetLowering::DAGCombinerInfo &DCI, 14185 const X86Subtarget *Subtarget) { 14186 if (DCI.isBeforeLegalizeOps()) 14187 return SDValue(); 14188 14189 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 14190 if (R.getNode()) 14191 return R; 14192 14193 EVT VT = N->getValueType(0); 14194 14195 SDValue N0 = N->getOperand(0); 14196 SDValue N1 = N->getOperand(1); 14197 14198 // look for psign/blend 14199 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 14200 if (!Subtarget->hasSSSE3() || 14201 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 14202 return SDValue(); 14203 14204 // Canonicalize pandn to RHS 14205 if (N0.getOpcode() == X86ISD::ANDNP) 14206 std::swap(N0, N1); 14207 // or (and (m, y), (pandn m, x)) 14208 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 14209 SDValue Mask = N1.getOperand(0); 14210 SDValue X = N1.getOperand(1); 14211 SDValue Y; 14212 if (N0.getOperand(0) == Mask) 14213 Y = N0.getOperand(1); 14214 if (N0.getOperand(1) == Mask) 14215 Y = N0.getOperand(0); 14216 14217 // Check to see if the mask appeared in both the AND and ANDNP and 14218 if (!Y.getNode()) 14219 return SDValue(); 14220 14221 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 14222 // Look through mask bitcast. 14223 if (Mask.getOpcode() == ISD::BITCAST) 14224 Mask = Mask.getOperand(0); 14225 if (X.getOpcode() == ISD::BITCAST) 14226 X = X.getOperand(0); 14227 if (Y.getOpcode() == ISD::BITCAST) 14228 Y = Y.getOperand(0); 14229 14230 EVT MaskVT = Mask.getValueType(); 14231 14232 // Validate that the Mask operand is a vector sra node. 14233 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 14234 // there is no psrai.b 14235 if (Mask.getOpcode() != X86ISD::VSRAI) 14236 return SDValue(); 14237 14238 // Check that the SRA is all signbits. 14239 SDValue SraC = Mask.getOperand(1); 14240 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 14241 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 14242 if ((SraAmt + 1) != EltBits) 14243 return SDValue(); 14244 14245 DebugLoc DL = N->getDebugLoc(); 14246 14247 // Now we know we at least have a plendvb with the mask val. See if 14248 // we can form a psignb/w/d. 14249 // psign = x.type == y.type == mask.type && y = sub(0, x); 14250 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 14251 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 14252 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 14253 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 14254 "Unsupported VT for PSIGN"); 14255 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0)); 14256 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14257 } 14258 // PBLENDVB only available on SSE 4.1 14259 if (!Subtarget->hasSSE41()) 14260 return SDValue(); 14261 14262 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 14263 14264 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 14265 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 14266 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 14267 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 14268 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 14269 } 14270 } 14271 14272 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 14273 return SDValue(); 14274 14275 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 14276 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 14277 std::swap(N0, N1); 14278 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 14279 return SDValue(); 14280 if (!N0.hasOneUse() || !N1.hasOneUse()) 14281 return SDValue(); 14282 14283 SDValue ShAmt0 = N0.getOperand(1); 14284 if (ShAmt0.getValueType() != MVT::i8) 14285 return SDValue(); 14286 SDValue ShAmt1 = N1.getOperand(1); 14287 if (ShAmt1.getValueType() != MVT::i8) 14288 return SDValue(); 14289 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 14290 ShAmt0 = ShAmt0.getOperand(0); 14291 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 14292 ShAmt1 = ShAmt1.getOperand(0); 14293 14294 DebugLoc DL = N->getDebugLoc(); 14295 unsigned Opc = X86ISD::SHLD; 14296 SDValue Op0 = N0.getOperand(0); 14297 SDValue Op1 = N1.getOperand(0); 14298 if (ShAmt0.getOpcode() == ISD::SUB) { 14299 Opc = X86ISD::SHRD; 14300 std::swap(Op0, Op1); 14301 std::swap(ShAmt0, ShAmt1); 14302 } 14303 14304 unsigned Bits = VT.getSizeInBits(); 14305 if (ShAmt1.getOpcode() == ISD::SUB) { 14306 SDValue Sum = ShAmt1.getOperand(0); 14307 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 14308 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 14309 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 14310 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 14311 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 14312 return DAG.getNode(Opc, DL, VT, 14313 Op0, Op1, 14314 DAG.getNode(ISD::TRUNCATE, DL, 14315 MVT::i8, ShAmt0)); 14316 } 14317 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 14318 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 14319 if (ShAmt0C && 14320 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 14321 return DAG.getNode(Opc, DL, VT, 14322 N0.getOperand(0), N1.getOperand(0), 14323 DAG.getNode(ISD::TRUNCATE, DL, 14324 MVT::i8, ShAmt0)); 14325 } 14326 14327 return SDValue(); 14328} 14329 14330// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 14331static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 14332 TargetLowering::DAGCombinerInfo &DCI, 14333 const X86Subtarget *Subtarget) { 14334 if (DCI.isBeforeLegalizeOps()) 14335 return SDValue(); 14336 14337 EVT VT = N->getValueType(0); 14338 14339 if (VT != MVT::i32 && VT != MVT::i64) 14340 return SDValue(); 14341 14342 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 14343 14344 // Create BLSMSK instructions by finding X ^ (X-1) 14345 SDValue N0 = N->getOperand(0); 14346 SDValue N1 = N->getOperand(1); 14347 DebugLoc DL = N->getDebugLoc(); 14348 14349 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 14350 isAllOnes(N0.getOperand(1))) 14351 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 14352 14353 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 14354 isAllOnes(N1.getOperand(1))) 14355 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 14356 14357 return SDValue(); 14358} 14359 14360/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 14361static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 14362 const X86Subtarget *Subtarget) { 14363 LoadSDNode *Ld = cast<LoadSDNode>(N); 14364 EVT RegVT = Ld->getValueType(0); 14365 EVT MemVT = Ld->getMemoryVT(); 14366 DebugLoc dl = Ld->getDebugLoc(); 14367 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14368 14369 ISD::LoadExtType Ext = Ld->getExtensionType(); 14370 14371 // If this is a vector EXT Load then attempt to optimize it using a 14372 // shuffle. We need SSE4 for the shuffles. 14373 // TODO: It is possible to support ZExt by zeroing the undef values 14374 // during the shuffle phase or after the shuffle. 14375 if (RegVT.isVector() && RegVT.isInteger() && 14376 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 14377 assert(MemVT != RegVT && "Cannot extend to the same type"); 14378 assert(MemVT.isVector() && "Must load a vector from memory"); 14379 14380 unsigned NumElems = RegVT.getVectorNumElements(); 14381 unsigned RegSz = RegVT.getSizeInBits(); 14382 unsigned MemSz = MemVT.getSizeInBits(); 14383 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 14384 // All sizes must be a power of two 14385 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 14386 14387 // Attempt to load the original value using a single load op. 14388 // Find a scalar type which is equal to the loaded word size. 14389 MVT SclrLoadTy = MVT::i8; 14390 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14391 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14392 MVT Tp = (MVT::SimpleValueType)tp; 14393 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 14394 SclrLoadTy = Tp; 14395 break; 14396 } 14397 } 14398 14399 // Proceed if a load word is found. 14400 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 14401 14402 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 14403 RegSz/SclrLoadTy.getSizeInBits()); 14404 14405 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 14406 RegSz/MemVT.getScalarType().getSizeInBits()); 14407 // Can't shuffle using an illegal type. 14408 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14409 14410 // Perform a single load. 14411 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 14412 Ld->getBasePtr(), 14413 Ld->getPointerInfo(), Ld->isVolatile(), 14414 Ld->isNonTemporal(), Ld->isInvariant(), 14415 Ld->getAlignment()); 14416 14417 // Insert the word loaded into a vector. 14418 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 14419 LoadUnitVecVT, ScalarLoad); 14420 14421 // Bitcast the loaded value to a vector of the original element type, in 14422 // the size of the target vector type. 14423 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 14424 ScalarInVector); 14425 unsigned SizeRatio = RegSz/MemSz; 14426 14427 // Redistribute the loaded elements into the different locations. 14428 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14429 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 14430 14431 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 14432 DAG.getUNDEF(WideVecVT), 14433 &ShuffleVec[0]); 14434 14435 // Bitcast to the requested type. 14436 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 14437 // Replace the original load with the new sequence 14438 // and return the new chain. 14439 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 14440 return SDValue(ScalarLoad.getNode(), 1); 14441 } 14442 14443 return SDValue(); 14444} 14445 14446/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 14447static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 14448 const X86Subtarget *Subtarget) { 14449 StoreSDNode *St = cast<StoreSDNode>(N); 14450 EVT VT = St->getValue().getValueType(); 14451 EVT StVT = St->getMemoryVT(); 14452 DebugLoc dl = St->getDebugLoc(); 14453 SDValue StoredVal = St->getOperand(1); 14454 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14455 14456 // If we are saving a concatenation of two XMM registers, perform two stores. 14457 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 14458 // 128-bit ones. If in the future the cost becomes only one memory access the 14459 // first version would be better. 14460 if (VT.getSizeInBits() == 256 && 14461 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 14462 StoredVal.getNumOperands() == 2) { 14463 14464 SDValue Value0 = StoredVal.getOperand(0); 14465 SDValue Value1 = StoredVal.getOperand(1); 14466 14467 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 14468 SDValue Ptr0 = St->getBasePtr(); 14469 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 14470 14471 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 14472 St->getPointerInfo(), St->isVolatile(), 14473 St->isNonTemporal(), St->getAlignment()); 14474 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 14475 St->getPointerInfo(), St->isVolatile(), 14476 St->isNonTemporal(), St->getAlignment()); 14477 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 14478 } 14479 14480 // Optimize trunc store (of multiple scalars) to shuffle and store. 14481 // First, pack all of the elements in one place. Next, store to memory 14482 // in fewer chunks. 14483 if (St->isTruncatingStore() && VT.isVector()) { 14484 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14485 unsigned NumElems = VT.getVectorNumElements(); 14486 assert(StVT != VT && "Cannot truncate to the same type"); 14487 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14488 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14489 14490 // From, To sizes and ElemCount must be pow of two 14491 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14492 // We are going to use the original vector elt for storing. 14493 // Accumulated smaller vector elements must be a multiple of the store size. 14494 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14495 14496 unsigned SizeRatio = FromSz / ToSz; 14497 14498 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14499 14500 // Create a type on which we perform the shuffle 14501 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14502 StVT.getScalarType(), NumElems*SizeRatio); 14503 14504 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14505 14506 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14507 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14508 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14509 14510 // Can't shuffle using an illegal type 14511 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14512 14513 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14514 DAG.getUNDEF(WideVecVT), 14515 &ShuffleVec[0]); 14516 // At this point all of the data is stored at the bottom of the 14517 // register. We now need to save it to mem. 14518 14519 // Find the largest store unit 14520 MVT StoreType = MVT::i8; 14521 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14522 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14523 MVT Tp = (MVT::SimpleValueType)tp; 14524 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14525 StoreType = Tp; 14526 } 14527 14528 // Bitcast the original vector into a vector of store-size units 14529 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14530 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14531 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14532 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14533 SmallVector<SDValue, 8> Chains; 14534 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14535 TLI.getPointerTy()); 14536 SDValue Ptr = St->getBasePtr(); 14537 14538 // Perform one or more big stores into memory. 14539 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14540 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14541 StoreType, ShuffWide, 14542 DAG.getIntPtrConstant(i)); 14543 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14544 St->getPointerInfo(), St->isVolatile(), 14545 St->isNonTemporal(), St->getAlignment()); 14546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14547 Chains.push_back(Ch); 14548 } 14549 14550 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14551 Chains.size()); 14552 } 14553 14554 14555 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14556 // the FP state in cases where an emms may be missing. 14557 // A preferable solution to the general problem is to figure out the right 14558 // places to insert EMMS. This qualifies as a quick hack. 14559 14560 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14561 if (VT.getSizeInBits() != 64) 14562 return SDValue(); 14563 14564 const Function *F = DAG.getMachineFunction().getFunction(); 14565 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14566 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14567 && Subtarget->hasSSE2(); 14568 if ((VT.isVector() || 14569 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14570 isa<LoadSDNode>(St->getValue()) && 14571 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14572 St->getChain().hasOneUse() && !St->isVolatile()) { 14573 SDNode* LdVal = St->getValue().getNode(); 14574 LoadSDNode *Ld = 0; 14575 int TokenFactorIndex = -1; 14576 SmallVector<SDValue, 8> Ops; 14577 SDNode* ChainVal = St->getChain().getNode(); 14578 // Must be a store of a load. We currently handle two cases: the load 14579 // is a direct child, and it's under an intervening TokenFactor. It is 14580 // possible to dig deeper under nested TokenFactors. 14581 if (ChainVal == LdVal) 14582 Ld = cast<LoadSDNode>(St->getChain()); 14583 else if (St->getValue().hasOneUse() && 14584 ChainVal->getOpcode() == ISD::TokenFactor) { 14585 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) { 14586 if (ChainVal->getOperand(i).getNode() == LdVal) { 14587 TokenFactorIndex = i; 14588 Ld = cast<LoadSDNode>(St->getValue()); 14589 } else 14590 Ops.push_back(ChainVal->getOperand(i)); 14591 } 14592 } 14593 14594 if (!Ld || !ISD::isNormalLoad(Ld)) 14595 return SDValue(); 14596 14597 // If this is not the MMX case, i.e. we are just turning i64 load/store 14598 // into f64 load/store, avoid the transformation if there are multiple 14599 // uses of the loaded value. 14600 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14601 return SDValue(); 14602 14603 DebugLoc LdDL = Ld->getDebugLoc(); 14604 DebugLoc StDL = N->getDebugLoc(); 14605 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14606 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14607 // pair instead. 14608 if (Subtarget->is64Bit() || F64IsLegal) { 14609 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14610 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14611 Ld->getPointerInfo(), Ld->isVolatile(), 14612 Ld->isNonTemporal(), Ld->isInvariant(), 14613 Ld->getAlignment()); 14614 SDValue NewChain = NewLd.getValue(1); 14615 if (TokenFactorIndex != -1) { 14616 Ops.push_back(NewChain); 14617 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14618 Ops.size()); 14619 } 14620 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14621 St->getPointerInfo(), 14622 St->isVolatile(), St->isNonTemporal(), 14623 St->getAlignment()); 14624 } 14625 14626 // Otherwise, lower to two pairs of 32-bit loads / stores. 14627 SDValue LoAddr = Ld->getBasePtr(); 14628 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14629 DAG.getConstant(4, MVT::i32)); 14630 14631 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14632 Ld->getPointerInfo(), 14633 Ld->isVolatile(), Ld->isNonTemporal(), 14634 Ld->isInvariant(), Ld->getAlignment()); 14635 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14636 Ld->getPointerInfo().getWithOffset(4), 14637 Ld->isVolatile(), Ld->isNonTemporal(), 14638 Ld->isInvariant(), 14639 MinAlign(Ld->getAlignment(), 4)); 14640 14641 SDValue NewChain = LoLd.getValue(1); 14642 if (TokenFactorIndex != -1) { 14643 Ops.push_back(LoLd); 14644 Ops.push_back(HiLd); 14645 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14646 Ops.size()); 14647 } 14648 14649 LoAddr = St->getBasePtr(); 14650 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14651 DAG.getConstant(4, MVT::i32)); 14652 14653 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14654 St->getPointerInfo(), 14655 St->isVolatile(), St->isNonTemporal(), 14656 St->getAlignment()); 14657 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14658 St->getPointerInfo().getWithOffset(4), 14659 St->isVolatile(), 14660 St->isNonTemporal(), 14661 MinAlign(St->getAlignment(), 4)); 14662 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14663 } 14664 return SDValue(); 14665} 14666 14667/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14668/// and return the operands for the horizontal operation in LHS and RHS. A 14669/// horizontal operation performs the binary operation on successive elements 14670/// of its first operand, then on successive elements of its second operand, 14671/// returning the resulting values in a vector. For example, if 14672/// A = < float a0, float a1, float a2, float a3 > 14673/// and 14674/// B = < float b0, float b1, float b2, float b3 > 14675/// then the result of doing a horizontal operation on A and B is 14676/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14677/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14678/// A horizontal-op B, for some already available A and B, and if so then LHS is 14679/// set to A, RHS to B, and the routine returns 'true'. 14680/// Note that the binary operation should have the property that if one of the 14681/// operands is UNDEF then the result is UNDEF. 14682static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14683 // Look for the following pattern: if 14684 // A = < float a0, float a1, float a2, float a3 > 14685 // B = < float b0, float b1, float b2, float b3 > 14686 // and 14687 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14688 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14689 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14690 // which is A horizontal-op B. 14691 14692 // At least one of the operands should be a vector shuffle. 14693 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14694 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14695 return false; 14696 14697 EVT VT = LHS.getValueType(); 14698 14699 assert((VT.is128BitVector() || VT.is256BitVector()) && 14700 "Unsupported vector type for horizontal add/sub"); 14701 14702 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14703 // operate independently on 128-bit lanes. 14704 unsigned NumElts = VT.getVectorNumElements(); 14705 unsigned NumLanes = VT.getSizeInBits()/128; 14706 unsigned NumLaneElts = NumElts / NumLanes; 14707 assert((NumLaneElts % 2 == 0) && 14708 "Vector type should have an even number of elements in each lane"); 14709 unsigned HalfLaneElts = NumLaneElts/2; 14710 14711 // View LHS in the form 14712 // LHS = VECTOR_SHUFFLE A, B, LMask 14713 // If LHS is not a shuffle then pretend it is the shuffle 14714 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14715 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14716 // type VT. 14717 SDValue A, B; 14718 SmallVector<int, 16> LMask(NumElts); 14719 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14720 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14721 A = LHS.getOperand(0); 14722 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14723 B = LHS.getOperand(1); 14724 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14725 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14726 } else { 14727 if (LHS.getOpcode() != ISD::UNDEF) 14728 A = LHS; 14729 for (unsigned i = 0; i != NumElts; ++i) 14730 LMask[i] = i; 14731 } 14732 14733 // Likewise, view RHS in the form 14734 // RHS = VECTOR_SHUFFLE C, D, RMask 14735 SDValue C, D; 14736 SmallVector<int, 16> RMask(NumElts); 14737 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14738 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14739 C = RHS.getOperand(0); 14740 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14741 D = RHS.getOperand(1); 14742 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14743 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14744 } else { 14745 if (RHS.getOpcode() != ISD::UNDEF) 14746 C = RHS; 14747 for (unsigned i = 0; i != NumElts; ++i) 14748 RMask[i] = i; 14749 } 14750 14751 // Check that the shuffles are both shuffling the same vectors. 14752 if (!(A == C && B == D) && !(A == D && B == C)) 14753 return false; 14754 14755 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14756 if (!A.getNode() && !B.getNode()) 14757 return false; 14758 14759 // If A and B occur in reverse order in RHS, then "swap" them (which means 14760 // rewriting the mask). 14761 if (A != C) 14762 CommuteVectorShuffleMask(RMask, NumElts); 14763 14764 // At this point LHS and RHS are equivalent to 14765 // LHS = VECTOR_SHUFFLE A, B, LMask 14766 // RHS = VECTOR_SHUFFLE A, B, RMask 14767 // Check that the masks correspond to performing a horizontal operation. 14768 for (unsigned i = 0; i != NumElts; ++i) { 14769 int LIdx = LMask[i], RIdx = RMask[i]; 14770 14771 // Ignore any UNDEF components. 14772 if (LIdx < 0 || RIdx < 0 || 14773 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14774 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14775 continue; 14776 14777 // Check that successive elements are being operated on. If not, this is 14778 // not a horizontal operation. 14779 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14780 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14781 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14782 if (!(LIdx == Index && RIdx == Index + 1) && 14783 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14784 return false; 14785 } 14786 14787 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14788 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14789 return true; 14790} 14791 14792/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14793static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14794 const X86Subtarget *Subtarget) { 14795 EVT VT = N->getValueType(0); 14796 SDValue LHS = N->getOperand(0); 14797 SDValue RHS = N->getOperand(1); 14798 14799 // Try to synthesize horizontal adds from adds of shuffles. 14800 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14801 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14802 isHorizontalBinOp(LHS, RHS, true)) 14803 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14804 return SDValue(); 14805} 14806 14807/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14808static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14809 const X86Subtarget *Subtarget) { 14810 EVT VT = N->getValueType(0); 14811 SDValue LHS = N->getOperand(0); 14812 SDValue RHS = N->getOperand(1); 14813 14814 // Try to synthesize horizontal subs from subs of shuffles. 14815 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14816 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14817 isHorizontalBinOp(LHS, RHS, false)) 14818 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14819 return SDValue(); 14820} 14821 14822/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14823/// X86ISD::FXOR nodes. 14824static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14825 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14826 // F[X]OR(0.0, x) -> x 14827 // F[X]OR(x, 0.0) -> x 14828 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14829 if (C->getValueAPF().isPosZero()) 14830 return N->getOperand(1); 14831 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14832 if (C->getValueAPF().isPosZero()) 14833 return N->getOperand(0); 14834 return SDValue(); 14835} 14836 14837/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14838static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14839 // FAND(0.0, x) -> 0.0 14840 // FAND(x, 0.0) -> 0.0 14841 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14842 if (C->getValueAPF().isPosZero()) 14843 return N->getOperand(0); 14844 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14845 if (C->getValueAPF().isPosZero()) 14846 return N->getOperand(1); 14847 return SDValue(); 14848} 14849 14850static SDValue PerformBTCombine(SDNode *N, 14851 SelectionDAG &DAG, 14852 TargetLowering::DAGCombinerInfo &DCI) { 14853 // BT ignores high bits in the bit index operand. 14854 SDValue Op1 = N->getOperand(1); 14855 if (Op1.hasOneUse()) { 14856 unsigned BitWidth = Op1.getValueSizeInBits(); 14857 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14858 APInt KnownZero, KnownOne; 14859 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14860 !DCI.isBeforeLegalizeOps()); 14861 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14862 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14863 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14864 DCI.CommitTargetLoweringOpt(TLO); 14865 } 14866 return SDValue(); 14867} 14868 14869static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14870 SDValue Op = N->getOperand(0); 14871 if (Op.getOpcode() == ISD::BITCAST) 14872 Op = Op.getOperand(0); 14873 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14874 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14875 VT.getVectorElementType().getSizeInBits() == 14876 OpVT.getVectorElementType().getSizeInBits()) { 14877 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14878 } 14879 return SDValue(); 14880} 14881 14882static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, 14883 TargetLowering::DAGCombinerInfo &DCI, 14884 const X86Subtarget *Subtarget) { 14885 if (!DCI.isBeforeLegalizeOps()) 14886 return SDValue(); 14887 14888 if (!Subtarget->hasAVX()) 14889 return SDValue(); 14890 14891 EVT VT = N->getValueType(0); 14892 SDValue Op = N->getOperand(0); 14893 EVT OpVT = Op.getValueType(); 14894 DebugLoc dl = N->getDebugLoc(); 14895 14896 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) || 14897 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) { 14898 14899 if (Subtarget->hasAVX2()) 14900 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op); 14901 14902 // Optimize vectors in AVX mode 14903 // Sign extend v8i16 to v8i32 and 14904 // v4i32 to v4i64 14905 // 14906 // Divide input vector into two parts 14907 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1} 14908 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32 14909 // concat the vectors to original VT 14910 14911 unsigned NumElems = OpVT.getVectorNumElements(); 14912 SmallVector<int,8> ShufMask1(NumElems, -1); 14913 for (unsigned i = 0; i != NumElems/2; ++i) 14914 ShufMask1[i] = i; 14915 14916 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14917 &ShufMask1[0]); 14918 14919 SmallVector<int,8> ShufMask2(NumElems, -1); 14920 for (unsigned i = 0; i != NumElems/2; ++i) 14921 ShufMask2[i] = i + NumElems/2; 14922 14923 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT), 14924 &ShufMask2[0]); 14925 14926 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(), 14927 VT.getVectorNumElements()/2); 14928 14929 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo); 14930 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi); 14931 14932 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14933 } 14934 return SDValue(); 14935} 14936 14937static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, 14938 TargetLowering::DAGCombinerInfo &DCI, 14939 const X86Subtarget *Subtarget) { 14940 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14941 // (and (i32 x86isd::setcc_carry), 1) 14942 // This eliminates the zext. This transformation is necessary because 14943 // ISD::SETCC is always legalized to i8. 14944 DebugLoc dl = N->getDebugLoc(); 14945 SDValue N0 = N->getOperand(0); 14946 EVT VT = N->getValueType(0); 14947 EVT OpVT = N0.getValueType(); 14948 14949 if (N0.getOpcode() == ISD::AND && 14950 N0.hasOneUse() && 14951 N0.getOperand(0).hasOneUse()) { 14952 SDValue N00 = N0.getOperand(0); 14953 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14954 return SDValue(); 14955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14956 if (!C || C->getZExtValue() != 1) 14957 return SDValue(); 14958 return DAG.getNode(ISD::AND, dl, VT, 14959 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14960 N00.getOperand(0), N00.getOperand(1)), 14961 DAG.getConstant(1, VT)); 14962 } 14963 14964 // Optimize vectors in AVX mode: 14965 // 14966 // v8i16 -> v8i32 14967 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32. 14968 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32. 14969 // Concat upper and lower parts. 14970 // 14971 // v4i32 -> v4i64 14972 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64. 14973 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64. 14974 // Concat upper and lower parts. 14975 // 14976 if (!DCI.isBeforeLegalizeOps()) 14977 return SDValue(); 14978 14979 if (!Subtarget->hasAVX()) 14980 return SDValue(); 14981 14982 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) || 14983 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) { 14984 14985 if (Subtarget->hasAVX2()) 14986 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0); 14987 14988 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl); 14989 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec); 14990 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec); 14991 14992 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 14993 VT.getVectorNumElements()/2); 14994 14995 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo); 14996 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi); 14997 14998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); 14999 } 15000 15001 return SDValue(); 15002} 15003 15004// Optimize x == -y --> x+y == 0 15005// x != -y --> x+y != 0 15006static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15007 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 15008 SDValue LHS = N->getOperand(0); 15009 SDValue RHS = N->getOperand(1); 15010 15011 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB) 15012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0))) 15013 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) { 15014 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15015 LHS.getValueType(), RHS, LHS.getOperand(1)); 15016 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15017 addV, DAG.getConstant(0, addV.getValueType()), CC); 15018 } 15019 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB) 15020 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0))) 15021 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) { 15022 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(), 15023 RHS.getValueType(), LHS, RHS.getOperand(1)); 15024 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0), 15025 addV, DAG.getConstant(0, addV.getValueType()), CC); 15026 } 15027 return SDValue(); 15028} 15029 15030// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 15031static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 15032 unsigned X86CC = N->getConstantOperandVal(0); 15033 SDValue EFLAG = N->getOperand(1); 15034 DebugLoc DL = N->getDebugLoc(); 15035 15036 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 15037 // a zext and produces an all-ones bit which is more useful than 0/1 in some 15038 // cases. 15039 if (X86CC == X86::COND_B) 15040 return DAG.getNode(ISD::AND, DL, MVT::i8, 15041 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 15042 DAG.getConstant(X86CC, MVT::i8), EFLAG), 15043 DAG.getConstant(1, MVT::i8)); 15044 15045 return SDValue(); 15046} 15047 15048static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) { 15049 SDValue Op0 = N->getOperand(0); 15050 EVT InVT = Op0->getValueType(0); 15051 15052 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) 15053 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15054 DebugLoc dl = N->getDebugLoc(); 15055 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15056 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); 15057 // Notice that we use SINT_TO_FP because we know that the high bits 15058 // are zero and SINT_TO_FP is better supported by the hardware. 15059 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15060 } 15061 15062 return SDValue(); 15063} 15064 15065static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 15066 const X86TargetLowering *XTLI) { 15067 SDValue Op0 = N->getOperand(0); 15068 EVT InVT = Op0->getValueType(0); 15069 15070 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 15071 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15072 DebugLoc dl = N->getDebugLoc(); 15073 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15074 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); 15075 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); 15076 } 15077 15078 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 15079 // a 32-bit target where SSE doesn't support i64->FP operations. 15080 if (Op0.getOpcode() == ISD::LOAD) { 15081 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 15082 EVT VT = Ld->getValueType(0); 15083 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 15084 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 15085 !XTLI->getSubtarget()->is64Bit() && 15086 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 15087 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 15088 Ld->getChain(), Op0, DAG); 15089 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 15090 return FILDChain; 15091 } 15092 } 15093 return SDValue(); 15094} 15095 15096static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) { 15097 EVT VT = N->getValueType(0); 15098 15099 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT() 15100 if (VT == MVT::v8i8 || VT == MVT::v4i8) { 15101 DebugLoc dl = N->getDebugLoc(); 15102 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15103 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0)); 15104 return DAG.getNode(ISD::TRUNCATE, dl, VT, I); 15105 } 15106 15107 return SDValue(); 15108} 15109 15110// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 15111static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 15112 X86TargetLowering::DAGCombinerInfo &DCI) { 15113 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 15114 // the result is either zero or one (depending on the input carry bit). 15115 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 15116 if (X86::isZeroNode(N->getOperand(0)) && 15117 X86::isZeroNode(N->getOperand(1)) && 15118 // We don't have a good way to replace an EFLAGS use, so only do this when 15119 // dead right now. 15120 SDValue(N, 1).use_empty()) { 15121 DebugLoc DL = N->getDebugLoc(); 15122 EVT VT = N->getValueType(0); 15123 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 15124 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 15125 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 15126 DAG.getConstant(X86::COND_B,MVT::i8), 15127 N->getOperand(2)), 15128 DAG.getConstant(1, VT)); 15129 return DCI.CombineTo(N, Res1, CarryOut); 15130 } 15131 15132 return SDValue(); 15133} 15134 15135// fold (add Y, (sete X, 0)) -> adc 0, Y 15136// (add Y, (setne X, 0)) -> sbb -1, Y 15137// (sub (sete X, 0), Y) -> sbb 0, Y 15138// (sub (setne X, 0), Y) -> adc -1, Y 15139static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 15140 DebugLoc DL = N->getDebugLoc(); 15141 15142 // Look through ZExts. 15143 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 15144 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 15145 return SDValue(); 15146 15147 SDValue SetCC = Ext.getOperand(0); 15148 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 15149 return SDValue(); 15150 15151 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 15152 if (CC != X86::COND_E && CC != X86::COND_NE) 15153 return SDValue(); 15154 15155 SDValue Cmp = SetCC.getOperand(1); 15156 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 15157 !X86::isZeroNode(Cmp.getOperand(1)) || 15158 !Cmp.getOperand(0).getValueType().isInteger()) 15159 return SDValue(); 15160 15161 SDValue CmpOp0 = Cmp.getOperand(0); 15162 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 15163 DAG.getConstant(1, CmpOp0.getValueType())); 15164 15165 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 15166 if (CC == X86::COND_NE) 15167 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 15168 DL, OtherVal.getValueType(), OtherVal, 15169 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 15170 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 15171 DL, OtherVal.getValueType(), OtherVal, 15172 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 15173} 15174 15175/// PerformADDCombine - Do target-specific dag combines on integer adds. 15176static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 15177 const X86Subtarget *Subtarget) { 15178 EVT VT = N->getValueType(0); 15179 SDValue Op0 = N->getOperand(0); 15180 SDValue Op1 = N->getOperand(1); 15181 15182 // Try to synthesize horizontal adds from adds of shuffles. 15183 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15184 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15185 isHorizontalBinOp(Op0, Op1, true)) 15186 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 15187 15188 return OptimizeConditionalInDecrement(N, DAG); 15189} 15190 15191static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 15192 const X86Subtarget *Subtarget) { 15193 SDValue Op0 = N->getOperand(0); 15194 SDValue Op1 = N->getOperand(1); 15195 15196 // X86 can't encode an immediate LHS of a sub. See if we can push the 15197 // negation into a preceding instruction. 15198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 15199 // If the RHS of the sub is a XOR with one use and a constant, invert the 15200 // immediate. Then add one to the LHS of the sub so we can turn 15201 // X-Y -> X+~Y+1, saving one register. 15202 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 15203 isa<ConstantSDNode>(Op1.getOperand(1))) { 15204 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 15205 EVT VT = Op0.getValueType(); 15206 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 15207 Op1.getOperand(0), 15208 DAG.getConstant(~XorC, VT)); 15209 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 15210 DAG.getConstant(C->getAPIntValue()+1, VT)); 15211 } 15212 } 15213 15214 // Try to synthesize horizontal adds from adds of shuffles. 15215 EVT VT = N->getValueType(0); 15216 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 15217 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 15218 isHorizontalBinOp(Op0, Op1, true)) 15219 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 15220 15221 return OptimizeConditionalInDecrement(N, DAG); 15222} 15223 15224SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 15225 DAGCombinerInfo &DCI) const { 15226 SelectionDAG &DAG = DCI.DAG; 15227 switch (N->getOpcode()) { 15228 default: break; 15229 case ISD::EXTRACT_VECTOR_ELT: 15230 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); 15231 case ISD::VSELECT: 15232 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 15233 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 15234 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 15235 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 15236 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 15237 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 15238 case ISD::SHL: 15239 case ISD::SRA: 15240 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); 15241 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 15242 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 15243 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 15244 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 15245 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 15246 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG); 15247 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 15248 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG); 15249 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 15250 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 15251 case X86ISD::FXOR: 15252 case X86ISD::FOR: return PerformFORCombine(N, DAG); 15253 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 15254 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 15255 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 15256 case ISD::ANY_EXTEND: 15257 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); 15258 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); 15259 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI); 15260 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG); 15261 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 15262 case X86ISD::SHUFP: // Handle all target specific shuffles 15263 case X86ISD::PALIGN: 15264 case X86ISD::UNPCKH: 15265 case X86ISD::UNPCKL: 15266 case X86ISD::MOVHLPS: 15267 case X86ISD::MOVLHPS: 15268 case X86ISD::PSHUFD: 15269 case X86ISD::PSHUFHW: 15270 case X86ISD::PSHUFLW: 15271 case X86ISD::MOVSS: 15272 case X86ISD::MOVSD: 15273 case X86ISD::VPERMILP: 15274 case X86ISD::VPERM2X128: 15275 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 15276 } 15277 15278 return SDValue(); 15279} 15280 15281/// isTypeDesirableForOp - Return true if the target has native support for 15282/// the specified value type and it is 'desirable' to use the type for the 15283/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 15284/// instruction encodings are longer and some i16 instructions are slow. 15285bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 15286 if (!isTypeLegal(VT)) 15287 return false; 15288 if (VT != MVT::i16) 15289 return true; 15290 15291 switch (Opc) { 15292 default: 15293 return true; 15294 case ISD::LOAD: 15295 case ISD::SIGN_EXTEND: 15296 case ISD::ZERO_EXTEND: 15297 case ISD::ANY_EXTEND: 15298 case ISD::SHL: 15299 case ISD::SRL: 15300 case ISD::SUB: 15301 case ISD::ADD: 15302 case ISD::MUL: 15303 case ISD::AND: 15304 case ISD::OR: 15305 case ISD::XOR: 15306 return false; 15307 } 15308} 15309 15310/// IsDesirableToPromoteOp - This method query the target whether it is 15311/// beneficial for dag combiner to promote the specified node. If true, it 15312/// should return the desired promotion type by reference. 15313bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 15314 EVT VT = Op.getValueType(); 15315 if (VT != MVT::i16) 15316 return false; 15317 15318 bool Promote = false; 15319 bool Commute = false; 15320 switch (Op.getOpcode()) { 15321 default: break; 15322 case ISD::LOAD: { 15323 LoadSDNode *LD = cast<LoadSDNode>(Op); 15324 // If the non-extending load has a single use and it's not live out, then it 15325 // might be folded. 15326 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 15327 Op.hasOneUse()*/) { 15328 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 15329 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 15330 // The only case where we'd want to promote LOAD (rather then it being 15331 // promoted as an operand is when it's only use is liveout. 15332 if (UI->getOpcode() != ISD::CopyToReg) 15333 return false; 15334 } 15335 } 15336 Promote = true; 15337 break; 15338 } 15339 case ISD::SIGN_EXTEND: 15340 case ISD::ZERO_EXTEND: 15341 case ISD::ANY_EXTEND: 15342 Promote = true; 15343 break; 15344 case ISD::SHL: 15345 case ISD::SRL: { 15346 SDValue N0 = Op.getOperand(0); 15347 // Look out for (store (shl (load), x)). 15348 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 15349 return false; 15350 Promote = true; 15351 break; 15352 } 15353 case ISD::ADD: 15354 case ISD::MUL: 15355 case ISD::AND: 15356 case ISD::OR: 15357 case ISD::XOR: 15358 Commute = true; 15359 // fallthrough 15360 case ISD::SUB: { 15361 SDValue N0 = Op.getOperand(0); 15362 SDValue N1 = Op.getOperand(1); 15363 if (!Commute && MayFoldLoad(N1)) 15364 return false; 15365 // Avoid disabling potential load folding opportunities. 15366 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 15367 return false; 15368 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 15369 return false; 15370 Promote = true; 15371 } 15372 } 15373 15374 PVT = MVT::i32; 15375 return Promote; 15376} 15377 15378//===----------------------------------------------------------------------===// 15379// X86 Inline Assembly Support 15380//===----------------------------------------------------------------------===// 15381 15382namespace { 15383 // Helper to match a string separated by whitespace. 15384 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 15385 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 15386 15387 for (unsigned i = 0, e = args.size(); i != e; ++i) { 15388 StringRef piece(*args[i]); 15389 if (!s.startswith(piece)) // Check if the piece matches. 15390 return false; 15391 15392 s = s.substr(piece.size()); 15393 StringRef::size_type pos = s.find_first_not_of(" \t"); 15394 if (pos == 0) // We matched a prefix. 15395 return false; 15396 15397 s = s.substr(pos); 15398 } 15399 15400 return s.empty(); 15401 } 15402 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 15403} 15404 15405bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 15406 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 15407 15408 std::string AsmStr = IA->getAsmString(); 15409 15410 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 15411 if (!Ty || Ty->getBitWidth() % 16 != 0) 15412 return false; 15413 15414 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 15415 SmallVector<StringRef, 4> AsmPieces; 15416 SplitString(AsmStr, AsmPieces, ";\n"); 15417 15418 switch (AsmPieces.size()) { 15419 default: return false; 15420 case 1: 15421 // FIXME: this should verify that we are targeting a 486 or better. If not, 15422 // we will turn this bswap into something that will be lowered to logical 15423 // ops instead of emitting the bswap asm. For now, we don't support 486 or 15424 // lower so don't worry about this. 15425 // bswap $0 15426 if (matchAsm(AsmPieces[0], "bswap", "$0") || 15427 matchAsm(AsmPieces[0], "bswapl", "$0") || 15428 matchAsm(AsmPieces[0], "bswapq", "$0") || 15429 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 15430 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 15431 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 15432 // No need to check constraints, nothing other than the equivalent of 15433 // "=r,0" would be valid here. 15434 return IntrinsicLowering::LowerToByteSwap(CI); 15435 } 15436 15437 // rorw $$8, ${0:w} --> llvm.bswap.i16 15438 if (CI->getType()->isIntegerTy(16) && 15439 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15440 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 15441 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 15442 AsmPieces.clear(); 15443 const std::string &ConstraintsStr = IA->getConstraintString(); 15444 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15445 std::sort(AsmPieces.begin(), AsmPieces.end()); 15446 if (AsmPieces.size() == 4 && 15447 AsmPieces[0] == "~{cc}" && 15448 AsmPieces[1] == "~{dirflag}" && 15449 AsmPieces[2] == "~{flags}" && 15450 AsmPieces[3] == "~{fpsr}") 15451 return IntrinsicLowering::LowerToByteSwap(CI); 15452 } 15453 break; 15454 case 3: 15455 if (CI->getType()->isIntegerTy(32) && 15456 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 15457 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 15458 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 15459 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 15460 AsmPieces.clear(); 15461 const std::string &ConstraintsStr = IA->getConstraintString(); 15462 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 15463 std::sort(AsmPieces.begin(), AsmPieces.end()); 15464 if (AsmPieces.size() == 4 && 15465 AsmPieces[0] == "~{cc}" && 15466 AsmPieces[1] == "~{dirflag}" && 15467 AsmPieces[2] == "~{flags}" && 15468 AsmPieces[3] == "~{fpsr}") 15469 return IntrinsicLowering::LowerToByteSwap(CI); 15470 } 15471 15472 if (CI->getType()->isIntegerTy(64)) { 15473 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 15474 if (Constraints.size() >= 2 && 15475 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 15476 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 15477 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 15478 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 15479 matchAsm(AsmPieces[1], "bswap", "%edx") && 15480 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 15481 return IntrinsicLowering::LowerToByteSwap(CI); 15482 } 15483 } 15484 break; 15485 } 15486 return false; 15487} 15488 15489 15490 15491/// getConstraintType - Given a constraint letter, return the type of 15492/// constraint it is for this target. 15493X86TargetLowering::ConstraintType 15494X86TargetLowering::getConstraintType(const std::string &Constraint) const { 15495 if (Constraint.size() == 1) { 15496 switch (Constraint[0]) { 15497 case 'R': 15498 case 'q': 15499 case 'Q': 15500 case 'f': 15501 case 't': 15502 case 'u': 15503 case 'y': 15504 case 'x': 15505 case 'Y': 15506 case 'l': 15507 return C_RegisterClass; 15508 case 'a': 15509 case 'b': 15510 case 'c': 15511 case 'd': 15512 case 'S': 15513 case 'D': 15514 case 'A': 15515 return C_Register; 15516 case 'I': 15517 case 'J': 15518 case 'K': 15519 case 'L': 15520 case 'M': 15521 case 'N': 15522 case 'G': 15523 case 'C': 15524 case 'e': 15525 case 'Z': 15526 return C_Other; 15527 default: 15528 break; 15529 } 15530 } 15531 return TargetLowering::getConstraintType(Constraint); 15532} 15533 15534/// Examine constraint type and operand type and determine a weight value. 15535/// This object must already have been set up with the operand type 15536/// and the current alternative constraint selected. 15537TargetLowering::ConstraintWeight 15538 X86TargetLowering::getSingleConstraintMatchWeight( 15539 AsmOperandInfo &info, const char *constraint) const { 15540 ConstraintWeight weight = CW_Invalid; 15541 Value *CallOperandVal = info.CallOperandVal; 15542 // If we don't have a value, we can't do a match, 15543 // but allow it at the lowest weight. 15544 if (CallOperandVal == NULL) 15545 return CW_Default; 15546 Type *type = CallOperandVal->getType(); 15547 // Look at the constraint type. 15548 switch (*constraint) { 15549 default: 15550 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 15551 case 'R': 15552 case 'q': 15553 case 'Q': 15554 case 'a': 15555 case 'b': 15556 case 'c': 15557 case 'd': 15558 case 'S': 15559 case 'D': 15560 case 'A': 15561 if (CallOperandVal->getType()->isIntegerTy()) 15562 weight = CW_SpecificReg; 15563 break; 15564 case 'f': 15565 case 't': 15566 case 'u': 15567 if (type->isFloatingPointTy()) 15568 weight = CW_SpecificReg; 15569 break; 15570 case 'y': 15571 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 15572 weight = CW_SpecificReg; 15573 break; 15574 case 'x': 15575 case 'Y': 15576 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 15577 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 15578 weight = CW_Register; 15579 break; 15580 case 'I': 15581 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 15582 if (C->getZExtValue() <= 31) 15583 weight = CW_Constant; 15584 } 15585 break; 15586 case 'J': 15587 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15588 if (C->getZExtValue() <= 63) 15589 weight = CW_Constant; 15590 } 15591 break; 15592 case 'K': 15593 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15594 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 15595 weight = CW_Constant; 15596 } 15597 break; 15598 case 'L': 15599 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15600 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 15601 weight = CW_Constant; 15602 } 15603 break; 15604 case 'M': 15605 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15606 if (C->getZExtValue() <= 3) 15607 weight = CW_Constant; 15608 } 15609 break; 15610 case 'N': 15611 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15612 if (C->getZExtValue() <= 0xff) 15613 weight = CW_Constant; 15614 } 15615 break; 15616 case 'G': 15617 case 'C': 15618 if (dyn_cast<ConstantFP>(CallOperandVal)) { 15619 weight = CW_Constant; 15620 } 15621 break; 15622 case 'e': 15623 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15624 if ((C->getSExtValue() >= -0x80000000LL) && 15625 (C->getSExtValue() <= 0x7fffffffLL)) 15626 weight = CW_Constant; 15627 } 15628 break; 15629 case 'Z': 15630 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 15631 if (C->getZExtValue() <= 0xffffffff) 15632 weight = CW_Constant; 15633 } 15634 break; 15635 } 15636 return weight; 15637} 15638 15639/// LowerXConstraint - try to replace an X constraint, which matches anything, 15640/// with another that has more specific requirements based on the type of the 15641/// corresponding operand. 15642const char *X86TargetLowering:: 15643LowerXConstraint(EVT ConstraintVT) const { 15644 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 15645 // 'f' like normal targets. 15646 if (ConstraintVT.isFloatingPoint()) { 15647 if (Subtarget->hasSSE2()) 15648 return "Y"; 15649 if (Subtarget->hasSSE1()) 15650 return "x"; 15651 } 15652 15653 return TargetLowering::LowerXConstraint(ConstraintVT); 15654} 15655 15656/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15657/// vector. If it is invalid, don't add anything to Ops. 15658void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15659 std::string &Constraint, 15660 std::vector<SDValue>&Ops, 15661 SelectionDAG &DAG) const { 15662 SDValue Result(0, 0); 15663 15664 // Only support length 1 constraints for now. 15665 if (Constraint.length() > 1) return; 15666 15667 char ConstraintLetter = Constraint[0]; 15668 switch (ConstraintLetter) { 15669 default: break; 15670 case 'I': 15671 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15672 if (C->getZExtValue() <= 31) { 15673 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15674 break; 15675 } 15676 } 15677 return; 15678 case 'J': 15679 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15680 if (C->getZExtValue() <= 63) { 15681 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15682 break; 15683 } 15684 } 15685 return; 15686 case 'K': 15687 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15688 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15689 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15690 break; 15691 } 15692 } 15693 return; 15694 case 'N': 15695 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15696 if (C->getZExtValue() <= 255) { 15697 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15698 break; 15699 } 15700 } 15701 return; 15702 case 'e': { 15703 // 32-bit signed value 15704 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15705 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15706 C->getSExtValue())) { 15707 // Widen to 64 bits here to get it sign extended. 15708 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15709 break; 15710 } 15711 // FIXME gcc accepts some relocatable values here too, but only in certain 15712 // memory models; it's complicated. 15713 } 15714 return; 15715 } 15716 case 'Z': { 15717 // 32-bit unsigned value 15718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15719 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15720 C->getZExtValue())) { 15721 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15722 break; 15723 } 15724 } 15725 // FIXME gcc accepts some relocatable values here too, but only in certain 15726 // memory models; it's complicated. 15727 return; 15728 } 15729 case 'i': { 15730 // Literal immediates are always ok. 15731 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15732 // Widen to 64 bits here to get it sign extended. 15733 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15734 break; 15735 } 15736 15737 // In any sort of PIC mode addresses need to be computed at runtime by 15738 // adding in a register or some sort of table lookup. These can't 15739 // be used as immediates. 15740 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15741 return; 15742 15743 // If we are in non-pic codegen mode, we allow the address of a global (with 15744 // an optional displacement) to be used with 'i'. 15745 GlobalAddressSDNode *GA = 0; 15746 int64_t Offset = 0; 15747 15748 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15749 while (1) { 15750 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15751 Offset += GA->getOffset(); 15752 break; 15753 } else if (Op.getOpcode() == ISD::ADD) { 15754 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15755 Offset += C->getZExtValue(); 15756 Op = Op.getOperand(0); 15757 continue; 15758 } 15759 } else if (Op.getOpcode() == ISD::SUB) { 15760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15761 Offset += -C->getZExtValue(); 15762 Op = Op.getOperand(0); 15763 continue; 15764 } 15765 } 15766 15767 // Otherwise, this isn't something we can handle, reject it. 15768 return; 15769 } 15770 15771 const GlobalValue *GV = GA->getGlobal(); 15772 // If we require an extra load to get this address, as in PIC mode, we 15773 // can't accept it. 15774 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15775 getTargetMachine()))) 15776 return; 15777 15778 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15779 GA->getValueType(0), Offset); 15780 break; 15781 } 15782 } 15783 15784 if (Result.getNode()) { 15785 Ops.push_back(Result); 15786 return; 15787 } 15788 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15789} 15790 15791std::pair<unsigned, const TargetRegisterClass*> 15792X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15793 EVT VT) const { 15794 // First, see if this is a constraint that directly corresponds to an LLVM 15795 // register class. 15796 if (Constraint.size() == 1) { 15797 // GCC Constraint Letters 15798 switch (Constraint[0]) { 15799 default: break; 15800 // TODO: Slight differences here in allocation order and leaving 15801 // RIP in the class. Do they matter any more here than they do 15802 // in the normal allocation? 15803 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15804 if (Subtarget->is64Bit()) { 15805 if (VT == MVT::i32 || VT == MVT::f32) 15806 return std::make_pair(0U, &X86::GR32RegClass); 15807 if (VT == MVT::i16) 15808 return std::make_pair(0U, &X86::GR16RegClass); 15809 if (VT == MVT::i8 || VT == MVT::i1) 15810 return std::make_pair(0U, &X86::GR8RegClass); 15811 if (VT == MVT::i64 || VT == MVT::f64) 15812 return std::make_pair(0U, &X86::GR64RegClass); 15813 break; 15814 } 15815 // 32-bit fallthrough 15816 case 'Q': // Q_REGS 15817 if (VT == MVT::i32 || VT == MVT::f32) 15818 return std::make_pair(0U, &X86::GR32_ABCDRegClass); 15819 if (VT == MVT::i16) 15820 return std::make_pair(0U, &X86::GR16_ABCDRegClass); 15821 if (VT == MVT::i8 || VT == MVT::i1) 15822 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass); 15823 if (VT == MVT::i64) 15824 return std::make_pair(0U, &X86::GR64_ABCDRegClass); 15825 break; 15826 case 'r': // GENERAL_REGS 15827 case 'l': // INDEX_REGS 15828 if (VT == MVT::i8 || VT == MVT::i1) 15829 return std::make_pair(0U, &X86::GR8RegClass); 15830 if (VT == MVT::i16) 15831 return std::make_pair(0U, &X86::GR16RegClass); 15832 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15833 return std::make_pair(0U, &X86::GR32RegClass); 15834 return std::make_pair(0U, &X86::GR64RegClass); 15835 case 'R': // LEGACY_REGS 15836 if (VT == MVT::i8 || VT == MVT::i1) 15837 return std::make_pair(0U, &X86::GR8_NOREXRegClass); 15838 if (VT == MVT::i16) 15839 return std::make_pair(0U, &X86::GR16_NOREXRegClass); 15840 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15841 return std::make_pair(0U, &X86::GR32_NOREXRegClass); 15842 return std::make_pair(0U, &X86::GR64_NOREXRegClass); 15843 case 'f': // FP Stack registers. 15844 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15845 // value to the correct fpstack register class. 15846 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15847 return std::make_pair(0U, &X86::RFP32RegClass); 15848 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15849 return std::make_pair(0U, &X86::RFP64RegClass); 15850 return std::make_pair(0U, &X86::RFP80RegClass); 15851 case 'y': // MMX_REGS if MMX allowed. 15852 if (!Subtarget->hasMMX()) break; 15853 return std::make_pair(0U, &X86::VR64RegClass); 15854 case 'Y': // SSE_REGS if SSE2 allowed 15855 if (!Subtarget->hasSSE2()) break; 15856 // FALL THROUGH. 15857 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15858 if (!Subtarget->hasSSE1()) break; 15859 15860 switch (VT.getSimpleVT().SimpleTy) { 15861 default: break; 15862 // Scalar SSE types. 15863 case MVT::f32: 15864 case MVT::i32: 15865 return std::make_pair(0U, &X86::FR32RegClass); 15866 case MVT::f64: 15867 case MVT::i64: 15868 return std::make_pair(0U, &X86::FR64RegClass); 15869 // Vector types. 15870 case MVT::v16i8: 15871 case MVT::v8i16: 15872 case MVT::v4i32: 15873 case MVT::v2i64: 15874 case MVT::v4f32: 15875 case MVT::v2f64: 15876 return std::make_pair(0U, &X86::VR128RegClass); 15877 // AVX types. 15878 case MVT::v32i8: 15879 case MVT::v16i16: 15880 case MVT::v8i32: 15881 case MVT::v4i64: 15882 case MVT::v8f32: 15883 case MVT::v4f64: 15884 return std::make_pair(0U, &X86::VR256RegClass); 15885 } 15886 break; 15887 } 15888 } 15889 15890 // Use the default implementation in TargetLowering to convert the register 15891 // constraint into a member of a register class. 15892 std::pair<unsigned, const TargetRegisterClass*> Res; 15893 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15894 15895 // Not found as a standard register? 15896 if (Res.second == 0) { 15897 // Map st(0) -> st(7) -> ST0 15898 if (Constraint.size() == 7 && Constraint[0] == '{' && 15899 tolower(Constraint[1]) == 's' && 15900 tolower(Constraint[2]) == 't' && 15901 Constraint[3] == '(' && 15902 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15903 Constraint[5] == ')' && 15904 Constraint[6] == '}') { 15905 15906 Res.first = X86::ST0+Constraint[4]-'0'; 15907 Res.second = &X86::RFP80RegClass; 15908 return Res; 15909 } 15910 15911 // GCC allows "st(0)" to be called just plain "st". 15912 if (StringRef("{st}").equals_lower(Constraint)) { 15913 Res.first = X86::ST0; 15914 Res.second = &X86::RFP80RegClass; 15915 return Res; 15916 } 15917 15918 // flags -> EFLAGS 15919 if (StringRef("{flags}").equals_lower(Constraint)) { 15920 Res.first = X86::EFLAGS; 15921 Res.second = &X86::CCRRegClass; 15922 return Res; 15923 } 15924 15925 // 'A' means EAX + EDX. 15926 if (Constraint == "A") { 15927 Res.first = X86::EAX; 15928 Res.second = &X86::GR32_ADRegClass; 15929 return Res; 15930 } 15931 return Res; 15932 } 15933 15934 // Otherwise, check to see if this is a register class of the wrong value 15935 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15936 // turn into {ax},{dx}. 15937 if (Res.second->hasType(VT)) 15938 return Res; // Correct type already, nothing to do. 15939 15940 // All of the single-register GCC register classes map their values onto 15941 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15942 // really want an 8-bit or 32-bit register, map to the appropriate register 15943 // class and return the appropriate register. 15944 if (Res.second == &X86::GR16RegClass) { 15945 if (VT == MVT::i8) { 15946 unsigned DestReg = 0; 15947 switch (Res.first) { 15948 default: break; 15949 case X86::AX: DestReg = X86::AL; break; 15950 case X86::DX: DestReg = X86::DL; break; 15951 case X86::CX: DestReg = X86::CL; break; 15952 case X86::BX: DestReg = X86::BL; break; 15953 } 15954 if (DestReg) { 15955 Res.first = DestReg; 15956 Res.second = &X86::GR8RegClass; 15957 } 15958 } else if (VT == MVT::i32) { 15959 unsigned DestReg = 0; 15960 switch (Res.first) { 15961 default: break; 15962 case X86::AX: DestReg = X86::EAX; break; 15963 case X86::DX: DestReg = X86::EDX; break; 15964 case X86::CX: DestReg = X86::ECX; break; 15965 case X86::BX: DestReg = X86::EBX; break; 15966 case X86::SI: DestReg = X86::ESI; break; 15967 case X86::DI: DestReg = X86::EDI; break; 15968 case X86::BP: DestReg = X86::EBP; break; 15969 case X86::SP: DestReg = X86::ESP; break; 15970 } 15971 if (DestReg) { 15972 Res.first = DestReg; 15973 Res.second = &X86::GR32RegClass; 15974 } 15975 } else if (VT == MVT::i64) { 15976 unsigned DestReg = 0; 15977 switch (Res.first) { 15978 default: break; 15979 case X86::AX: DestReg = X86::RAX; break; 15980 case X86::DX: DestReg = X86::RDX; break; 15981 case X86::CX: DestReg = X86::RCX; break; 15982 case X86::BX: DestReg = X86::RBX; break; 15983 case X86::SI: DestReg = X86::RSI; break; 15984 case X86::DI: DestReg = X86::RDI; break; 15985 case X86::BP: DestReg = X86::RBP; break; 15986 case X86::SP: DestReg = X86::RSP; break; 15987 } 15988 if (DestReg) { 15989 Res.first = DestReg; 15990 Res.second = &X86::GR64RegClass; 15991 } 15992 } 15993 } else if (Res.second == &X86::FR32RegClass || 15994 Res.second == &X86::FR64RegClass || 15995 Res.second == &X86::VR128RegClass) { 15996 // Handle references to XMM physical registers that got mapped into the 15997 // wrong class. This can happen with constraints like {xmm0} where the 15998 // target independent register mapper will just pick the first match it can 15999 // find, ignoring the required type. 16000 if (VT == MVT::f32) 16001 Res.second = &X86::FR32RegClass; 16002 else if (VT == MVT::f64) 16003 Res.second = &X86::FR64RegClass; 16004 else if (X86::VR128RegClass.hasType(VT)) 16005 Res.second = &X86::VR128RegClass; 16006 } 16007 16008 return Res; 16009} 16010