X86ISelLowering.cpp revision 670e53977bf289009bb460538987542c9c46ac90
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86ISelLowering.h" 18#include "X86TargetMachine.h" 19#include "X86TargetObjectFile.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/GlobalAlias.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Function.h" 26#include "llvm/Instructions.h" 27#include "llvm/Intrinsics.h" 28#include "llvm/LLVMContext.h" 29#include "llvm/ADT/BitVector.h" 30#include "llvm/ADT/VectorExtras.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/ErrorHandling.h" 40#include "llvm/Target/TargetOptions.h" 41#include "llvm/ADT/SmallSet.h" 42#include "llvm/ADT/StringExtras.h" 43#include "llvm/Support/CommandLine.h" 44#include "llvm/Support/raw_ostream.h" 45using namespace llvm; 46 47static cl::opt<bool> 48DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 49 50// Disable16Bit - 16-bit operations typically have a larger encoding than 51// corresponding 32-bit instructions, and 16-bit code is slow on some 52// processors. This is an experimental flag to disable 16-bit operations 53// (which forces them to be Legalized to 32-bit operations). 54static cl::opt<bool> 55Disable16Bit("disable-16bit", cl::Hidden, 56 cl::desc("Disable use of 16-bit instructions")); 57 58// Forward declarations. 59static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 60 SDValue V2); 61 62static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 63 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 64 default: llvm_unreachable("unknown subtarget type"); 65 case X86Subtarget::isDarwin: 66 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 67 return new X8664_MachoTargetObjectFile(); 68 return new X8632_MachoTargetObjectFile(); 69 case X86Subtarget::isELF: 70 return new TargetLoweringObjectFileELF(); 71 case X86Subtarget::isMingw: 72 case X86Subtarget::isCygwin: 73 case X86Subtarget::isWindows: 74 return new TargetLoweringObjectFileCOFF(); 75 } 76 77} 78 79X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 80 : TargetLowering(TM, createTLOF(TM)) { 81 Subtarget = &TM.getSubtarget<X86Subtarget>(); 82 X86ScalarSSEf64 = Subtarget->hasSSE2(); 83 X86ScalarSSEf32 = Subtarget->hasSSE1(); 84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 85 86 RegInfo = TM.getRegisterInfo(); 87 TD = getTargetData(); 88 89 // Set up the TargetLowering object. 90 91 // X86 is weird, it always uses i8 for shift amounts and setcc results. 92 setShiftAmountType(MVT::i8); 93 setBooleanContents(ZeroOrOneBooleanContent); 94 setSchedulingPreference(SchedulingForRegPressure); 95 setStackPointerRegisterToSaveRestore(X86StackPtr); 96 97 if (Subtarget->isTargetDarwin()) { 98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 99 setUseUnderscoreSetJmp(false); 100 setUseUnderscoreLongJmp(false); 101 } else if (Subtarget->isTargetMingw()) { 102 // MS runtime is weird: it exports _setjmp, but longjmp! 103 setUseUnderscoreSetJmp(true); 104 setUseUnderscoreLongJmp(false); 105 } else { 106 setUseUnderscoreSetJmp(true); 107 setUseUnderscoreLongJmp(true); 108 } 109 110 // Set up the register classes. 111 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 112 if (!Disable16Bit) 113 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 114 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 115 if (Subtarget->is64Bit()) 116 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 117 118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 119 120 // We don't accept any truncstore of integer registers. 121 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 122 if (!Disable16Bit) 123 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 125 if (!Disable16Bit) 126 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 128 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 129 130 // SETOEQ and SETUNE require checking two conditions. 131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 137 138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 139 // operation. 140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 143 144 if (Subtarget->is64Bit()) { 145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 147 } else if (!UseSoftFloat) { 148 if (X86ScalarSSEf64) { 149 // We have an impenetrably clever algorithm for ui64->double only. 150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 151 } 152 // We have an algorithm for SSE2, and we turn this into a 64-bit 153 // FILD for other targets. 154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 155 } 156 157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 158 // this operation. 159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 161 162 if (!UseSoftFloat) { 163 // SSE has no i16 to fp conversion, only i32 164 if (X86ScalarSSEf32) { 165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 166 // f32 and f64 cases are Legal, f80 case is not 167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 168 } else { 169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 171 } 172 } else { 173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 175 } 176 177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 178 // are Legal, f80 is custom lowered. 179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 181 182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 183 // this operation. 184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 186 187 if (X86ScalarSSEf32) { 188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 189 // f32 and f64 cases are Legal, f80 case is not 190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 191 } else { 192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 194 } 195 196 // Handle FP_TO_UINT by promoting the destination to a larger signed 197 // conversion. 198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 201 202 if (Subtarget->is64Bit()) { 203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 205 } else if (!UseSoftFloat) { 206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 207 // Expand FP_TO_UINT into a select. 208 // FIXME: We would like to use a Custom expander here eventually to do 209 // the optimal thing for SSE vs. the default expansion in the legalizer. 210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 211 else 212 // With SSE3 we can use fisttpll to convert to a signed i64; without 213 // SSE, we're stuck with a fistpll. 214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 215 } 216 217 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 218 if (!X86ScalarSSEf64) { 219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 221 } 222 223 // Scalar integer divide and remainder are lowered to use operations that 224 // produce two results, to match the available instructions. This exposes 225 // the two-result form to trivial CSE, which is able to combine x/y and x%y 226 // into a single instruction. 227 // 228 // Scalar integer multiply-high is also lowered to use two-result 229 // operations, to match the available instructions. However, plain multiply 230 // (low) operations are left as Legal, as there are single-result 231 // instructions for this in x86. Using the two-result multiply instructions 232 // when both high and low results are needed must be arranged by dagcombine. 233 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 234 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 235 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 236 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 237 setOperationAction(ISD::SREM , MVT::i8 , Expand); 238 setOperationAction(ISD::UREM , MVT::i8 , Expand); 239 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 240 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 241 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 242 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 243 setOperationAction(ISD::SREM , MVT::i16 , Expand); 244 setOperationAction(ISD::UREM , MVT::i16 , Expand); 245 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 246 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 247 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 248 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 249 setOperationAction(ISD::SREM , MVT::i32 , Expand); 250 setOperationAction(ISD::UREM , MVT::i32 , Expand); 251 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 252 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 253 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 254 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 255 setOperationAction(ISD::SREM , MVT::i64 , Expand); 256 setOperationAction(ISD::UREM , MVT::i64 , Expand); 257 258 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 259 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 260 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 262 if (Subtarget->is64Bit()) 263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 268 setOperationAction(ISD::FREM , MVT::f32 , Expand); 269 setOperationAction(ISD::FREM , MVT::f64 , Expand); 270 setOperationAction(ISD::FREM , MVT::f80 , Expand); 271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 272 273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 277 if (Disable16Bit) { 278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 280 } else { 281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 283 } 284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 287 if (Subtarget->is64Bit()) { 288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 291 } 292 293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 295 296 // These should be promoted to a larger select which is supported. 297 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 298 // X86 wants to expand cmov itself. 299 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 300 if (Disable16Bit) 301 setOperationAction(ISD::SELECT , MVT::i16 , Expand); 302 else 303 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 304 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 305 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 306 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 307 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 308 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 309 if (Disable16Bit) 310 setOperationAction(ISD::SETCC , MVT::i16 , Expand); 311 else 312 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 313 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 314 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 315 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 316 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 317 if (Subtarget->is64Bit()) { 318 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 319 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 320 } 321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 322 323 // Darwin ABI issue. 324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 328 if (Subtarget->is64Bit()) 329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 331 if (Subtarget->is64Bit()) { 332 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 333 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 334 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 335 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 336 } 337 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 338 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 339 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 340 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 341 if (Subtarget->is64Bit()) { 342 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 343 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 344 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 345 } 346 347 if (Subtarget->hasSSE1()) 348 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 349 350 if (!Subtarget->hasSSE2()) 351 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 352 353 // Expand certain atomics 354 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 355 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 358 359 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 360 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 363 364 if (!Subtarget->is64Bit()) { 365 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 366 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 367 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 368 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 369 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 370 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 371 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 372 } 373 374 // Use the default ISD::DBG_STOPPOINT. 375 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 376 // FIXME - use subtarget debug flags 377 if (!Subtarget->isTargetDarwin() && 378 !Subtarget->isTargetELF() && 379 !Subtarget->isTargetCygMing()) { 380 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); 381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 382 } 383 384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 388 if (Subtarget->is64Bit()) { 389 setExceptionPointerRegister(X86::RAX); 390 setExceptionSelectorRegister(X86::RDX); 391 } else { 392 setExceptionPointerRegister(X86::EAX); 393 setExceptionSelectorRegister(X86::EDX); 394 } 395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 397 398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 399 400 setOperationAction(ISD::TRAP, MVT::Other, Legal); 401 402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 403 setOperationAction(ISD::VASTART , MVT::Other, Custom); 404 setOperationAction(ISD::VAEND , MVT::Other, Expand); 405 if (Subtarget->is64Bit()) { 406 setOperationAction(ISD::VAARG , MVT::Other, Custom); 407 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 408 } else { 409 setOperationAction(ISD::VAARG , MVT::Other, Expand); 410 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 411 } 412 413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 415 if (Subtarget->is64Bit()) 416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 417 if (Subtarget->isTargetCygMing()) 418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 419 else 420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 421 422 if (!UseSoftFloat && X86ScalarSSEf64) { 423 // f32 and f64 use SSE. 424 // Set up the FP register classes. 425 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 426 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 427 428 // Use ANDPD to simulate FABS. 429 setOperationAction(ISD::FABS , MVT::f64, Custom); 430 setOperationAction(ISD::FABS , MVT::f32, Custom); 431 432 // Use XORP to simulate FNEG. 433 setOperationAction(ISD::FNEG , MVT::f64, Custom); 434 setOperationAction(ISD::FNEG , MVT::f32, Custom); 435 436 // Use ANDPD and ORPD to simulate FCOPYSIGN. 437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 439 440 // We don't support sin/cos/fmod 441 setOperationAction(ISD::FSIN , MVT::f64, Expand); 442 setOperationAction(ISD::FCOS , MVT::f64, Expand); 443 setOperationAction(ISD::FSIN , MVT::f32, Expand); 444 setOperationAction(ISD::FCOS , MVT::f32, Expand); 445 446 // Expand FP immediates into loads from the stack, except for the special 447 // cases we handle. 448 addLegalFPImmediate(APFloat(+0.0)); // xorpd 449 addLegalFPImmediate(APFloat(+0.0f)); // xorps 450 } else if (!UseSoftFloat && X86ScalarSSEf32) { 451 // Use SSE for f32, x87 for f64. 452 // Set up the FP register classes. 453 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 455 456 // Use ANDPS to simulate FABS. 457 setOperationAction(ISD::FABS , MVT::f32, Custom); 458 459 // Use XORP to simulate FNEG. 460 setOperationAction(ISD::FNEG , MVT::f32, Custom); 461 462 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 463 464 // Use ANDPS and ORPS to simulate FCOPYSIGN. 465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 467 468 // We don't support sin/cos/fmod 469 setOperationAction(ISD::FSIN , MVT::f32, Expand); 470 setOperationAction(ISD::FCOS , MVT::f32, Expand); 471 472 // Special cases we handle for FP constants. 473 addLegalFPImmediate(APFloat(+0.0f)); // xorps 474 addLegalFPImmediate(APFloat(+0.0)); // FLD0 475 addLegalFPImmediate(APFloat(+1.0)); // FLD1 476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 478 479 if (!UnsafeFPMath) { 480 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 481 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 482 } 483 } else if (!UseSoftFloat) { 484 // f32 and f64 in x87. 485 // Set up the FP register classes. 486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 488 489 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 490 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 493 494 if (!UnsafeFPMath) { 495 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 496 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 497 } 498 addLegalFPImmediate(APFloat(+0.0)); // FLD0 499 addLegalFPImmediate(APFloat(+1.0)); // FLD1 500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 506 } 507 508 // Long double always uses X87. 509 if (!UseSoftFloat) { 510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 511 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 513 { 514 bool ignored; 515 APFloat TmpFlt(+0.0); 516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 517 &ignored); 518 addLegalFPImmediate(TmpFlt); // FLD0 519 TmpFlt.changeSign(); 520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 521 APFloat TmpFlt2(+1.0); 522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 523 &ignored); 524 addLegalFPImmediate(TmpFlt2); // FLD1 525 TmpFlt2.changeSign(); 526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 527 } 528 529 if (!UnsafeFPMath) { 530 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 531 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 532 } 533 } 534 535 // Always use a library call for pow. 536 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 537 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 538 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 539 540 setOperationAction(ISD::FLOG, MVT::f80, Expand); 541 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 542 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 543 setOperationAction(ISD::FEXP, MVT::f80, Expand); 544 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 545 546 // First set operation action for all vector types to either promote 547 // (for widening) or expand (for scalarization). Then we will selectively 548 // turn on ones that can be effectively codegen'd. 549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 599 } 600 601 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 602 // with -msoft-float, disable use of MMX as well. 603 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 604 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 605 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 606 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 607 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 608 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 609 610 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 611 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 612 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 613 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 614 615 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 616 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 617 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 618 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 619 620 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 621 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 622 623 setOperationAction(ISD::AND, MVT::v8i8, Promote); 624 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 625 setOperationAction(ISD::AND, MVT::v4i16, Promote); 626 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 627 setOperationAction(ISD::AND, MVT::v2i32, Promote); 628 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 629 setOperationAction(ISD::AND, MVT::v1i64, Legal); 630 631 setOperationAction(ISD::OR, MVT::v8i8, Promote); 632 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 633 setOperationAction(ISD::OR, MVT::v4i16, Promote); 634 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 635 setOperationAction(ISD::OR, MVT::v2i32, Promote); 636 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 637 setOperationAction(ISD::OR, MVT::v1i64, Legal); 638 639 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 640 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 641 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 642 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 643 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 644 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 645 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 646 647 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 648 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 649 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 650 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 651 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 652 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 653 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 654 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 655 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 656 657 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 659 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 660 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 661 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 662 663 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 664 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 667 668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 669 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 670 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 671 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 672 673 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 674 675 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); 676 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); 677 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 678 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 679 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 680 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 681 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 682 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 683 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 684 } 685 686 if (!UseSoftFloat && Subtarget->hasSSE1()) { 687 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 688 689 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 690 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 691 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 692 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 693 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 694 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 695 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 696 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 697 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 698 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 699 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 700 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 701 } 702 703 if (!UseSoftFloat && Subtarget->hasSSE2()) { 704 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 705 706 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 707 // registers cannot be used even for integer operations. 708 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 709 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 710 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 711 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 712 713 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 714 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 715 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 716 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 717 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 718 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 719 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 720 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 721 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 722 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 723 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 724 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 725 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 726 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 727 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 728 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 729 730 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 731 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 732 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 733 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 734 735 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 736 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 740 741 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 742 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 743 EVT VT = (MVT::SimpleValueType)i; 744 // Do not attempt to custom lower non-power-of-2 vectors 745 if (!isPowerOf2_32(VT.getVectorNumElements())) 746 continue; 747 // Do not attempt to custom lower non-128-bit vectors 748 if (!VT.is128BitVector()) 749 continue; 750 setOperationAction(ISD::BUILD_VECTOR, 751 VT.getSimpleVT().SimpleTy, Custom); 752 setOperationAction(ISD::VECTOR_SHUFFLE, 753 VT.getSimpleVT().SimpleTy, Custom); 754 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 755 VT.getSimpleVT().SimpleTy, Custom); 756 } 757 758 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 759 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 760 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 761 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 762 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 763 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 764 765 if (Subtarget->is64Bit()) { 766 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 767 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 768 } 769 770 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 771 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 772 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 773 EVT VT = SVT; 774 775 // Do not attempt to promote non-128-bit vectors 776 if (!VT.is128BitVector()) { 777 continue; 778 } 779 setOperationAction(ISD::AND, SVT, Promote); 780 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 781 setOperationAction(ISD::OR, SVT, Promote); 782 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 783 setOperationAction(ISD::XOR, SVT, Promote); 784 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 785 setOperationAction(ISD::LOAD, SVT, Promote); 786 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 787 setOperationAction(ISD::SELECT, SVT, Promote); 788 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 789 } 790 791 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 792 793 // Custom lower v2i64 and v2f64 selects. 794 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 795 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 796 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 797 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 798 799 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 800 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 801 if (!DisableMMX && Subtarget->hasMMX()) { 802 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 803 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 804 } 805 } 806 807 if (Subtarget->hasSSE41()) { 808 // FIXME: Do we need to handle scalar-to-vector here? 809 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 810 811 // i8 and i16 vectors are custom , because the source register and source 812 // source memory operand types are not the same width. f32 vectors are 813 // custom since the immediate controlling the insert encodes additional 814 // information. 815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 819 820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 824 825 if (Subtarget->is64Bit()) { 826 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 828 } 829 } 830 831 if (Subtarget->hasSSE42()) { 832 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 833 } 834 835 if (!UseSoftFloat && Subtarget->hasAVX()) { 836 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 837 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 838 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 839 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 840 841 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 842 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 843 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 844 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 845 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 846 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 847 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 848 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 849 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 850 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 851 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 852 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 853 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 854 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 855 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 856 857 // Operations to consider commented out -v16i16 v32i8 858 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 859 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 860 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 861 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 862 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 863 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 864 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 865 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 866 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 867 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 868 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 869 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 870 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 871 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 872 873 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 874 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 875 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 876 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 877 878 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 879 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 880 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 882 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 883 884 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 885 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 888 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 890 891#if 0 892 // Not sure we want to do this since there are no 256-bit integer 893 // operations in AVX 894 895 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 896 // This includes 256-bit vectors 897 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 898 EVT VT = (MVT::SimpleValueType)i; 899 900 // Do not attempt to custom lower non-power-of-2 vectors 901 if (!isPowerOf2_32(VT.getVectorNumElements())) 902 continue; 903 904 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 905 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 906 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 907 } 908 909 if (Subtarget->is64Bit()) { 910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 911 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 912 } 913#endif 914 915#if 0 916 // Not sure we want to do this since there are no 256-bit integer 917 // operations in AVX 918 919 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 920 // Including 256-bit vectors 921 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 922 EVT VT = (MVT::SimpleValueType)i; 923 924 if (!VT.is256BitVector()) { 925 continue; 926 } 927 setOperationAction(ISD::AND, VT, Promote); 928 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 929 setOperationAction(ISD::OR, VT, Promote); 930 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 931 setOperationAction(ISD::XOR, VT, Promote); 932 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 933 setOperationAction(ISD::LOAD, VT, Promote); 934 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 935 setOperationAction(ISD::SELECT, VT, Promote); 936 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 937 } 938 939 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 940#endif 941 } 942 943 // We want to custom lower some of our intrinsics. 944 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 945 946 // Add/Sub/Mul with overflow operations are custom lowered. 947 setOperationAction(ISD::SADDO, MVT::i32, Custom); 948 setOperationAction(ISD::SADDO, MVT::i64, Custom); 949 setOperationAction(ISD::UADDO, MVT::i32, Custom); 950 setOperationAction(ISD::UADDO, MVT::i64, Custom); 951 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 952 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 953 setOperationAction(ISD::USUBO, MVT::i32, Custom); 954 setOperationAction(ISD::USUBO, MVT::i64, Custom); 955 setOperationAction(ISD::SMULO, MVT::i32, Custom); 956 setOperationAction(ISD::SMULO, MVT::i64, Custom); 957 958 if (!Subtarget->is64Bit()) { 959 // These libcalls are not available in 32-bit. 960 setLibcallName(RTLIB::SHL_I128, 0); 961 setLibcallName(RTLIB::SRL_I128, 0); 962 setLibcallName(RTLIB::SRA_I128, 0); 963 } 964 965 // We have target-specific dag combine patterns for the following nodes: 966 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 967 setTargetDAGCombine(ISD::BUILD_VECTOR); 968 setTargetDAGCombine(ISD::SELECT); 969 setTargetDAGCombine(ISD::SHL); 970 setTargetDAGCombine(ISD::SRA); 971 setTargetDAGCombine(ISD::SRL); 972 setTargetDAGCombine(ISD::STORE); 973 setTargetDAGCombine(ISD::MEMBARRIER); 974 if (Subtarget->is64Bit()) 975 setTargetDAGCombine(ISD::MUL); 976 977 computeRegisterProperties(); 978 979 // FIXME: These should be based on subtarget info. Plus, the values should 980 // be smaller when we are in optimizing for size mode. 981 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 982 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 983 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 984 setPrefLoopAlignment(16); 985 benefitFromCodePlacementOpt = true; 986} 987 988 989MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 990 return MVT::i8; 991} 992 993 994/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 995/// the desired ByVal argument alignment. 996static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 997 if (MaxAlign == 16) 998 return; 999 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1000 if (VTy->getBitWidth() == 128) 1001 MaxAlign = 16; 1002 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1003 unsigned EltAlign = 0; 1004 getMaxByValAlign(ATy->getElementType(), EltAlign); 1005 if (EltAlign > MaxAlign) 1006 MaxAlign = EltAlign; 1007 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1008 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1009 unsigned EltAlign = 0; 1010 getMaxByValAlign(STy->getElementType(i), EltAlign); 1011 if (EltAlign > MaxAlign) 1012 MaxAlign = EltAlign; 1013 if (MaxAlign == 16) 1014 break; 1015 } 1016 } 1017 return; 1018} 1019 1020/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1021/// function arguments in the caller parameter area. For X86, aggregates 1022/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1023/// are at 4-byte boundaries. 1024unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1025 if (Subtarget->is64Bit()) { 1026 // Max of 8 and alignment of type. 1027 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1028 if (TyAlign > 8) 1029 return TyAlign; 1030 return 8; 1031 } 1032 1033 unsigned Align = 4; 1034 if (Subtarget->hasSSE1()) 1035 getMaxByValAlign(Ty, Align); 1036 return Align; 1037} 1038 1039/// getOptimalMemOpType - Returns the target specific optimal type for load 1040/// and store operations as a result of memset, memcpy, and memmove 1041/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 1042/// determining it. 1043EVT 1044X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1045 bool isSrcConst, bool isSrcStr, 1046 SelectionDAG &DAG) const { 1047 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1048 // linux. This is because the stack realignment code can't handle certain 1049 // cases like PR2962. This should be removed when PR2962 is fixed. 1050 const Function *F = DAG.getMachineFunction().getFunction(); 1051 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1052 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1053 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1054 return MVT::v4i32; 1055 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1056 return MVT::v4f32; 1057 } 1058 if (Subtarget->is64Bit() && Size >= 8) 1059 return MVT::i64; 1060 return MVT::i32; 1061} 1062 1063/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1064/// jumptable. 1065SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1066 SelectionDAG &DAG) const { 1067 if (usesGlobalOffsetTable()) 1068 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1069 if (!Subtarget->is64Bit()) 1070 // This doesn't have DebugLoc associated with it, but is not really the 1071 // same as a Register. 1072 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1073 getPointerTy()); 1074 return Table; 1075} 1076 1077/// getFunctionAlignment - Return the Log2 alignment of this function. 1078unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1079 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1080} 1081 1082//===----------------------------------------------------------------------===// 1083// Return Value Calling Convention Implementation 1084//===----------------------------------------------------------------------===// 1085 1086#include "X86GenCallingConv.inc" 1087 1088SDValue 1089X86TargetLowering::LowerReturn(SDValue Chain, 1090 CallingConv::ID CallConv, bool isVarArg, 1091 const SmallVectorImpl<ISD::OutputArg> &Outs, 1092 DebugLoc dl, SelectionDAG &DAG) { 1093 1094 SmallVector<CCValAssign, 16> RVLocs; 1095 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1096 RVLocs, *DAG.getContext()); 1097 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1098 1099 // If this is the first return lowered for this function, add the regs to the 1100 // liveout set for the function. 1101 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1102 for (unsigned i = 0; i != RVLocs.size(); ++i) 1103 if (RVLocs[i].isRegLoc()) 1104 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1105 } 1106 1107 SDValue Flag; 1108 1109 SmallVector<SDValue, 6> RetOps; 1110 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1111 // Operand #1 = Bytes To Pop 1112 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16)); 1113 1114 // Copy the result values into the output registers. 1115 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1116 CCValAssign &VA = RVLocs[i]; 1117 assert(VA.isRegLoc() && "Can only return in registers!"); 1118 SDValue ValToCopy = Outs[i].Val; 1119 1120 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1121 // the RET instruction and handled by the FP Stackifier. 1122 if (VA.getLocReg() == X86::ST0 || 1123 VA.getLocReg() == X86::ST1) { 1124 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1125 // change the value to the FP stack register class. 1126 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1127 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1128 RetOps.push_back(ValToCopy); 1129 // Don't emit a copytoreg. 1130 continue; 1131 } 1132 1133 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1134 // which is returned in RAX / RDX. 1135 if (Subtarget->is64Bit()) { 1136 EVT ValVT = ValToCopy.getValueType(); 1137 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1138 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1139 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1140 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1141 } 1142 } 1143 1144 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1145 Flag = Chain.getValue(1); 1146 } 1147 1148 // The x86-64 ABI for returning structs by value requires that we copy 1149 // the sret argument into %rax for the return. We saved the argument into 1150 // a virtual register in the entry block, so now we copy the value out 1151 // and into %rax. 1152 if (Subtarget->is64Bit() && 1153 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1154 MachineFunction &MF = DAG.getMachineFunction(); 1155 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1156 unsigned Reg = FuncInfo->getSRetReturnReg(); 1157 if (!Reg) { 1158 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1159 FuncInfo->setSRetReturnReg(Reg); 1160 } 1161 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1162 1163 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1164 Flag = Chain.getValue(1); 1165 } 1166 1167 RetOps[0] = Chain; // Update chain. 1168 1169 // Add the flag if we have it. 1170 if (Flag.getNode()) 1171 RetOps.push_back(Flag); 1172 1173 return DAG.getNode(X86ISD::RET_FLAG, dl, 1174 MVT::Other, &RetOps[0], RetOps.size()); 1175} 1176 1177/// LowerCallResult - Lower the result values of a call into the 1178/// appropriate copies out of appropriate physical registers. 1179/// 1180SDValue 1181X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1182 CallingConv::ID CallConv, bool isVarArg, 1183 const SmallVectorImpl<ISD::InputArg> &Ins, 1184 DebugLoc dl, SelectionDAG &DAG, 1185 SmallVectorImpl<SDValue> &InVals) { 1186 1187 // Assign locations to each value returned by this call. 1188 SmallVector<CCValAssign, 16> RVLocs; 1189 bool Is64Bit = Subtarget->is64Bit(); 1190 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1191 RVLocs, *DAG.getContext()); 1192 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1193 1194 // Copy all of the result registers out of their specified physreg. 1195 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1196 CCValAssign &VA = RVLocs[i]; 1197 EVT CopyVT = VA.getValVT(); 1198 1199 // If this is x86-64, and we disabled SSE, we can't return FP values 1200 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1201 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1202 llvm_report_error("SSE register return with SSE disabled"); 1203 } 1204 1205 // If this is a call to a function that returns an fp value on the floating 1206 // point stack, but where we prefer to use the value in xmm registers, copy 1207 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1208 if ((VA.getLocReg() == X86::ST0 || 1209 VA.getLocReg() == X86::ST1) && 1210 isScalarFPTypeInSSEReg(VA.getValVT())) { 1211 CopyVT = MVT::f80; 1212 } 1213 1214 SDValue Val; 1215 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1216 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1217 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1218 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1219 MVT::v2i64, InFlag).getValue(1); 1220 Val = Chain.getValue(0); 1221 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1222 Val, DAG.getConstant(0, MVT::i64)); 1223 } else { 1224 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1225 MVT::i64, InFlag).getValue(1); 1226 Val = Chain.getValue(0); 1227 } 1228 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1229 } else { 1230 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1231 CopyVT, InFlag).getValue(1); 1232 Val = Chain.getValue(0); 1233 } 1234 InFlag = Chain.getValue(2); 1235 1236 if (CopyVT != VA.getValVT()) { 1237 // Round the F80 the right size, which also moves to the appropriate xmm 1238 // register. 1239 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1240 // This truncation won't change the value. 1241 DAG.getIntPtrConstant(1)); 1242 } 1243 1244 InVals.push_back(Val); 1245 } 1246 1247 return Chain; 1248} 1249 1250 1251//===----------------------------------------------------------------------===// 1252// C & StdCall & Fast Calling Convention implementation 1253//===----------------------------------------------------------------------===// 1254// StdCall calling convention seems to be standard for many Windows' API 1255// routines and around. It differs from C calling convention just a little: 1256// callee should clean up the stack, not caller. Symbols should be also 1257// decorated in some fancy way :) It doesn't support any vector arguments. 1258// For info on fast calling convention see Fast Calling Convention (tail call) 1259// implementation LowerX86_32FastCCCallTo. 1260 1261/// CallIsStructReturn - Determines whether a call uses struct return 1262/// semantics. 1263static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1264 if (Outs.empty()) 1265 return false; 1266 1267 return Outs[0].Flags.isSRet(); 1268} 1269 1270/// ArgsAreStructReturn - Determines whether a function uses struct 1271/// return semantics. 1272static bool 1273ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1274 if (Ins.empty()) 1275 return false; 1276 1277 return Ins[0].Flags.isSRet(); 1278} 1279 1280/// IsCalleePop - Determines whether the callee is required to pop its 1281/// own arguments. Callee pop is necessary to support tail calls. 1282bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ 1283 if (IsVarArg) 1284 return false; 1285 1286 switch (CallingConv) { 1287 default: 1288 return false; 1289 case CallingConv::X86_StdCall: 1290 return !Subtarget->is64Bit(); 1291 case CallingConv::X86_FastCall: 1292 return !Subtarget->is64Bit(); 1293 case CallingConv::Fast: 1294 return PerformTailCallOpt; 1295 } 1296} 1297 1298/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1299/// given CallingConvention value. 1300CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1301 if (Subtarget->is64Bit()) { 1302 if (Subtarget->isTargetWin64()) 1303 return CC_X86_Win64_C; 1304 else 1305 return CC_X86_64_C; 1306 } 1307 1308 if (CC == CallingConv::X86_FastCall) 1309 return CC_X86_32_FastCall; 1310 else if (CC == CallingConv::Fast) 1311 return CC_X86_32_FastCC; 1312 else 1313 return CC_X86_32_C; 1314} 1315 1316/// NameDecorationForCallConv - Selects the appropriate decoration to 1317/// apply to a MachineFunction containing a given calling convention. 1318NameDecorationStyle 1319X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) { 1320 if (CallConv == CallingConv::X86_FastCall) 1321 return FastCall; 1322 else if (CallConv == CallingConv::X86_StdCall) 1323 return StdCall; 1324 return None; 1325} 1326 1327 1328/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1329/// by "Src" to address "Dst" with size and alignment information specified by 1330/// the specific parameter attribute. The copy will be passed as a byval 1331/// function parameter. 1332static SDValue 1333CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1334 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1335 DebugLoc dl) { 1336 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1337 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1338 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1339} 1340 1341SDValue 1342X86TargetLowering::LowerMemArgument(SDValue Chain, 1343 CallingConv::ID CallConv, 1344 const SmallVectorImpl<ISD::InputArg> &Ins, 1345 DebugLoc dl, SelectionDAG &DAG, 1346 const CCValAssign &VA, 1347 MachineFrameInfo *MFI, 1348 unsigned i) { 1349 1350 // Create the nodes corresponding to a load from this parameter slot. 1351 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1352 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt; 1353 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1354 EVT ValVT; 1355 1356 // If value is passed by pointer we have address passed instead of the value 1357 // itself. 1358 if (VA.getLocInfo() == CCValAssign::Indirect) 1359 ValVT = VA.getLocVT(); 1360 else 1361 ValVT = VA.getValVT(); 1362 1363 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1364 // changed with more analysis. 1365 // In case of tail call optimization mark all arguments mutable. Since they 1366 // could be overwritten by lowering of arguments in case of a tail call. 1367 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1368 VA.getLocMemOffset(), isImmutable); 1369 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1370 if (Flags.isByVal()) 1371 return FIN; 1372 return DAG.getLoad(ValVT, dl, Chain, FIN, 1373 PseudoSourceValue::getFixedStack(FI), 0); 1374} 1375 1376SDValue 1377X86TargetLowering::LowerFormalArguments(SDValue Chain, 1378 CallingConv::ID CallConv, 1379 bool isVarArg, 1380 const SmallVectorImpl<ISD::InputArg> &Ins, 1381 DebugLoc dl, 1382 SelectionDAG &DAG, 1383 SmallVectorImpl<SDValue> &InVals) { 1384 1385 MachineFunction &MF = DAG.getMachineFunction(); 1386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1387 1388 const Function* Fn = MF.getFunction(); 1389 if (Fn->hasExternalLinkage() && 1390 Subtarget->isTargetCygMing() && 1391 Fn->getName() == "main") 1392 FuncInfo->setForceFramePointer(true); 1393 1394 // Decorate the function name. 1395 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv)); 1396 1397 MachineFrameInfo *MFI = MF.getFrameInfo(); 1398 bool Is64Bit = Subtarget->is64Bit(); 1399 bool IsWin64 = Subtarget->isTargetWin64(); 1400 1401 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1402 "Var args not supported with calling convention fastcc"); 1403 1404 // Assign locations to all of the incoming arguments. 1405 SmallVector<CCValAssign, 16> ArgLocs; 1406 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1407 ArgLocs, *DAG.getContext()); 1408 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1409 1410 unsigned LastVal = ~0U; 1411 SDValue ArgValue; 1412 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1413 CCValAssign &VA = ArgLocs[i]; 1414 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1415 // places. 1416 assert(VA.getValNo() != LastVal && 1417 "Don't support value assigned to multiple locs yet"); 1418 LastVal = VA.getValNo(); 1419 1420 if (VA.isRegLoc()) { 1421 EVT RegVT = VA.getLocVT(); 1422 TargetRegisterClass *RC = NULL; 1423 if (RegVT == MVT::i32) 1424 RC = X86::GR32RegisterClass; 1425 else if (Is64Bit && RegVT == MVT::i64) 1426 RC = X86::GR64RegisterClass; 1427 else if (RegVT == MVT::f32) 1428 RC = X86::FR32RegisterClass; 1429 else if (RegVT == MVT::f64) 1430 RC = X86::FR64RegisterClass; 1431 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1432 RC = X86::VR128RegisterClass; 1433 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1434 RC = X86::VR64RegisterClass; 1435 else 1436 llvm_unreachable("Unknown argument type!"); 1437 1438 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1439 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1440 1441 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1442 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1443 // right size. 1444 if (VA.getLocInfo() == CCValAssign::SExt) 1445 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1446 DAG.getValueType(VA.getValVT())); 1447 else if (VA.getLocInfo() == CCValAssign::ZExt) 1448 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1449 DAG.getValueType(VA.getValVT())); 1450 else if (VA.getLocInfo() == CCValAssign::BCvt) 1451 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1452 1453 if (VA.isExtInLoc()) { 1454 // Handle MMX values passed in XMM regs. 1455 if (RegVT.isVector()) { 1456 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1457 ArgValue, DAG.getConstant(0, MVT::i64)); 1458 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1459 } else 1460 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1461 } 1462 } else { 1463 assert(VA.isMemLoc()); 1464 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1465 } 1466 1467 // If value is passed via pointer - do a load. 1468 if (VA.getLocInfo() == CCValAssign::Indirect) 1469 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0); 1470 1471 InVals.push_back(ArgValue); 1472 } 1473 1474 // The x86-64 ABI for returning structs by value requires that we copy 1475 // the sret argument into %rax for the return. Save the argument into 1476 // a virtual register so that we can access it from the return points. 1477 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1478 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1479 unsigned Reg = FuncInfo->getSRetReturnReg(); 1480 if (!Reg) { 1481 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1482 FuncInfo->setSRetReturnReg(Reg); 1483 } 1484 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1485 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1486 } 1487 1488 unsigned StackSize = CCInfo.getNextStackOffset(); 1489 // align stack specially for tail calls 1490 if (PerformTailCallOpt && CallConv == CallingConv::Fast) 1491 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1492 1493 // If the function takes variable number of arguments, make a frame index for 1494 // the start of the first vararg value... for expansion of llvm.va_start. 1495 if (isVarArg) { 1496 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1497 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize); 1498 } 1499 if (Is64Bit) { 1500 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1501 1502 // FIXME: We should really autogenerate these arrays 1503 static const unsigned GPR64ArgRegsWin64[] = { 1504 X86::RCX, X86::RDX, X86::R8, X86::R9 1505 }; 1506 static const unsigned XMMArgRegsWin64[] = { 1507 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1508 }; 1509 static const unsigned GPR64ArgRegs64Bit[] = { 1510 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1511 }; 1512 static const unsigned XMMArgRegs64Bit[] = { 1513 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1514 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1515 }; 1516 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1517 1518 if (IsWin64) { 1519 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1520 GPR64ArgRegs = GPR64ArgRegsWin64; 1521 XMMArgRegs = XMMArgRegsWin64; 1522 } else { 1523 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1524 GPR64ArgRegs = GPR64ArgRegs64Bit; 1525 XMMArgRegs = XMMArgRegs64Bit; 1526 } 1527 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1528 TotalNumIntRegs); 1529 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1530 TotalNumXMMRegs); 1531 1532 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1533 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1534 "SSE register cannot be used when SSE is disabled!"); 1535 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1536 "SSE register cannot be used when SSE is disabled!"); 1537 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1538 // Kernel mode asks for SSE to be disabled, so don't push them 1539 // on the stack. 1540 TotalNumXMMRegs = 0; 1541 1542 // For X86-64, if there are vararg parameters that are passed via 1543 // registers, then we must store them to their spots on the stack so they 1544 // may be loaded by deferencing the result of va_next. 1545 VarArgsGPOffset = NumIntRegs * 8; 1546 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1547 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1548 TotalNumXMMRegs * 16, 16); 1549 1550 // Store the integer parameter registers. 1551 SmallVector<SDValue, 8> MemOps; 1552 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1553 unsigned Offset = VarArgsGPOffset; 1554 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1555 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1556 DAG.getIntPtrConstant(Offset)); 1557 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1558 X86::GR64RegisterClass); 1559 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1560 SDValue Store = 1561 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1562 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1563 Offset); 1564 MemOps.push_back(Store); 1565 Offset += 8; 1566 } 1567 1568 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1569 // Now store the XMM (fp + vector) parameter registers. 1570 SmallVector<SDValue, 11> SaveXMMOps; 1571 SaveXMMOps.push_back(Chain); 1572 1573 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1574 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1575 SaveXMMOps.push_back(ALVal); 1576 1577 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1578 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1579 1580 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1581 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1582 X86::VR128RegisterClass); 1583 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1584 SaveXMMOps.push_back(Val); 1585 } 1586 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1587 MVT::Other, 1588 &SaveXMMOps[0], SaveXMMOps.size())); 1589 } 1590 1591 if (!MemOps.empty()) 1592 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1593 &MemOps[0], MemOps.size()); 1594 } 1595 } 1596 1597 // Some CCs need callee pop. 1598 if (IsCalleePop(isVarArg, CallConv)) { 1599 BytesToPopOnReturn = StackSize; // Callee pops everything. 1600 BytesCallerReserves = 0; 1601 } else { 1602 BytesToPopOnReturn = 0; // Callee pops nothing. 1603 // If this is an sret function, the return should pop the hidden pointer. 1604 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins)) 1605 BytesToPopOnReturn = 4; 1606 BytesCallerReserves = StackSize; 1607 } 1608 1609 if (!Is64Bit) { 1610 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1611 if (CallConv == CallingConv::X86_FastCall) 1612 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1613 } 1614 1615 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1616 1617 return Chain; 1618} 1619 1620SDValue 1621X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1622 SDValue StackPtr, SDValue Arg, 1623 DebugLoc dl, SelectionDAG &DAG, 1624 const CCValAssign &VA, 1625 ISD::ArgFlagsTy Flags) { 1626 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1627 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1628 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1629 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1630 if (Flags.isByVal()) { 1631 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1632 } 1633 return DAG.getStore(Chain, dl, Arg, PtrOff, 1634 PseudoSourceValue::getStack(), LocMemOffset); 1635} 1636 1637/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1638/// optimization is performed and it is required. 1639SDValue 1640X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1641 SDValue &OutRetAddr, 1642 SDValue Chain, 1643 bool IsTailCall, 1644 bool Is64Bit, 1645 int FPDiff, 1646 DebugLoc dl) { 1647 if (!IsTailCall || FPDiff==0) return Chain; 1648 1649 // Adjust the Return address stack slot. 1650 EVT VT = getPointerTy(); 1651 OutRetAddr = getReturnAddressFrameIndex(DAG); 1652 1653 // Load the "old" Return address. 1654 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0); 1655 return SDValue(OutRetAddr.getNode(), 1); 1656} 1657 1658/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1659/// optimization is performed and it is required (FPDiff!=0). 1660static SDValue 1661EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1662 SDValue Chain, SDValue RetAddrFrIdx, 1663 bool Is64Bit, int FPDiff, DebugLoc dl) { 1664 // Store the return address to the appropriate stack slot. 1665 if (!FPDiff) return Chain; 1666 // Calculate the new stack slot for the return address. 1667 int SlotSize = Is64Bit ? 8 : 4; 1668 int NewReturnAddrFI = 1669 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); 1670 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1671 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1672 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1673 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); 1674 return Chain; 1675} 1676 1677SDValue 1678X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1679 CallingConv::ID CallConv, bool isVarArg, 1680 bool isTailCall, 1681 const SmallVectorImpl<ISD::OutputArg> &Outs, 1682 const SmallVectorImpl<ISD::InputArg> &Ins, 1683 DebugLoc dl, SelectionDAG &DAG, 1684 SmallVectorImpl<SDValue> &InVals) { 1685 1686 MachineFunction &MF = DAG.getMachineFunction(); 1687 bool Is64Bit = Subtarget->is64Bit(); 1688 bool IsStructRet = CallIsStructReturn(Outs); 1689 1690 assert((!isTailCall || 1691 (CallConv == CallingConv::Fast && PerformTailCallOpt)) && 1692 "IsEligibleForTailCallOptimization missed a case!"); 1693 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1694 "Var args not supported with calling convention fastcc"); 1695 1696 // Analyze operands of the call, assigning locations to each operand. 1697 SmallVector<CCValAssign, 16> ArgLocs; 1698 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1699 ArgLocs, *DAG.getContext()); 1700 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1701 1702 // Get a count of how many bytes are to be pushed on the stack. 1703 unsigned NumBytes = CCInfo.getNextStackOffset(); 1704 if (PerformTailCallOpt && CallConv == CallingConv::Fast) 1705 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1706 1707 int FPDiff = 0; 1708 if (isTailCall) { 1709 // Lower arguments at fp - stackoffset + fpdiff. 1710 unsigned NumBytesCallerPushed = 1711 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1712 FPDiff = NumBytesCallerPushed - NumBytes; 1713 1714 // Set the delta of movement of the returnaddr stackslot. 1715 // But only set if delta is greater than previous delta. 1716 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1717 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1718 } 1719 1720 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1721 1722 SDValue RetAddrFrIdx; 1723 // Load return adress for tail calls. 1724 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit, 1725 FPDiff, dl); 1726 1727 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1728 SmallVector<SDValue, 8> MemOpChains; 1729 SDValue StackPtr; 1730 1731 // Walk the register/memloc assignments, inserting copies/loads. In the case 1732 // of tail call optimization arguments are handle later. 1733 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1734 CCValAssign &VA = ArgLocs[i]; 1735 EVT RegVT = VA.getLocVT(); 1736 SDValue Arg = Outs[i].Val; 1737 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1738 bool isByVal = Flags.isByVal(); 1739 1740 // Promote the value if needed. 1741 switch (VA.getLocInfo()) { 1742 default: llvm_unreachable("Unknown loc info!"); 1743 case CCValAssign::Full: break; 1744 case CCValAssign::SExt: 1745 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1746 break; 1747 case CCValAssign::ZExt: 1748 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1749 break; 1750 case CCValAssign::AExt: 1751 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1752 // Special case: passing MMX values in XMM registers. 1753 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1754 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1755 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1756 } else 1757 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1758 break; 1759 case CCValAssign::BCvt: 1760 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1761 break; 1762 case CCValAssign::Indirect: { 1763 // Store the argument. 1764 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1765 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1766 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1767 PseudoSourceValue::getFixedStack(FI), 0); 1768 Arg = SpillSlot; 1769 break; 1770 } 1771 } 1772 1773 if (VA.isRegLoc()) { 1774 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1775 } else { 1776 if (!isTailCall || (isTailCall && isByVal)) { 1777 assert(VA.isMemLoc()); 1778 if (StackPtr.getNode() == 0) 1779 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1780 1781 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1782 dl, DAG, VA, Flags)); 1783 } 1784 } 1785 } 1786 1787 if (!MemOpChains.empty()) 1788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1789 &MemOpChains[0], MemOpChains.size()); 1790 1791 // Build a sequence of copy-to-reg nodes chained together with token chain 1792 // and flag operands which copy the outgoing args into registers. 1793 SDValue InFlag; 1794 // Tail call byval lowering might overwrite argument registers so in case of 1795 // tail call optimization the copies to registers are lowered later. 1796 if (!isTailCall) 1797 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1798 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1799 RegsToPass[i].second, InFlag); 1800 InFlag = Chain.getValue(1); 1801 } 1802 1803 1804 if (Subtarget->isPICStyleGOT()) { 1805 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1806 // GOT pointer. 1807 if (!isTailCall) { 1808 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1809 DAG.getNode(X86ISD::GlobalBaseReg, 1810 DebugLoc::getUnknownLoc(), 1811 getPointerTy()), 1812 InFlag); 1813 InFlag = Chain.getValue(1); 1814 } else { 1815 // If we are tail calling and generating PIC/GOT style code load the 1816 // address of the callee into ECX. The value in ecx is used as target of 1817 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1818 // for tail calls on PIC/GOT architectures. Normally we would just put the 1819 // address of GOT into ebx and then call target@PLT. But for tail calls 1820 // ebx would be restored (since ebx is callee saved) before jumping to the 1821 // target@PLT. 1822 1823 // Note: The actual moving to ECX is done further down. 1824 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1825 if (G && !G->getGlobal()->hasHiddenVisibility() && 1826 !G->getGlobal()->hasProtectedVisibility()) 1827 Callee = LowerGlobalAddress(Callee, DAG); 1828 else if (isa<ExternalSymbolSDNode>(Callee)) 1829 Callee = LowerExternalSymbol(Callee, DAG); 1830 } 1831 } 1832 1833 if (Is64Bit && isVarArg) { 1834 // From AMD64 ABI document: 1835 // For calls that may call functions that use varargs or stdargs 1836 // (prototype-less calls or calls to functions containing ellipsis (...) in 1837 // the declaration) %al is used as hidden argument to specify the number 1838 // of SSE registers used. The contents of %al do not need to match exactly 1839 // the number of registers, but must be an ubound on the number of SSE 1840 // registers used and is in the range 0 - 8 inclusive. 1841 1842 // FIXME: Verify this on Win64 1843 // Count the number of XMM registers allocated. 1844 static const unsigned XMMArgRegs[] = { 1845 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1846 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1847 }; 1848 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1849 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1850 && "SSE registers cannot be used when SSE is disabled"); 1851 1852 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1853 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1854 InFlag = Chain.getValue(1); 1855 } 1856 1857 1858 // For tail calls lower the arguments to the 'real' stack slot. 1859 if (isTailCall) { 1860 // Force all the incoming stack arguments to be loaded from the stack 1861 // before any new outgoing arguments are stored to the stack, because the 1862 // outgoing stack slots may alias the incoming argument stack slots, and 1863 // the alias isn't otherwise explicit. This is slightly more conservative 1864 // than necessary, because it means that each store effectively depends 1865 // on every argument instead of just those arguments it would clobber. 1866 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1867 1868 SmallVector<SDValue, 8> MemOpChains2; 1869 SDValue FIN; 1870 int FI = 0; 1871 // Do not flag preceeding copytoreg stuff together with the following stuff. 1872 InFlag = SDValue(); 1873 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1874 CCValAssign &VA = ArgLocs[i]; 1875 if (!VA.isRegLoc()) { 1876 assert(VA.isMemLoc()); 1877 SDValue Arg = Outs[i].Val; 1878 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1879 // Create frame index. 1880 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1881 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1882 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); 1883 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1884 1885 if (Flags.isByVal()) { 1886 // Copy relative to framepointer. 1887 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1888 if (StackPtr.getNode() == 0) 1889 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1890 getPointerTy()); 1891 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 1892 1893 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 1894 ArgChain, 1895 Flags, DAG, dl)); 1896 } else { 1897 // Store relative to framepointer. 1898 MemOpChains2.push_back( 1899 DAG.getStore(ArgChain, dl, Arg, FIN, 1900 PseudoSourceValue::getFixedStack(FI), 0)); 1901 } 1902 } 1903 } 1904 1905 if (!MemOpChains2.empty()) 1906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1907 &MemOpChains2[0], MemOpChains2.size()); 1908 1909 // Copy arguments to their registers. 1910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1912 RegsToPass[i].second, InFlag); 1913 InFlag = Chain.getValue(1); 1914 } 1915 InFlag =SDValue(); 1916 1917 // Store the return address to the appropriate stack slot. 1918 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 1919 FPDiff, dl); 1920 } 1921 1922 // If the callee is a GlobalAddress node (quite common, every direct call is) 1923 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1924 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1925 // We should use extra load for direct calls to dllimported functions in 1926 // non-JIT mode. 1927 GlobalValue *GV = G->getGlobal(); 1928 if (!GV->hasDLLImportLinkage()) { 1929 unsigned char OpFlags = 0; 1930 1931 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1932 // external symbols most go through the PLT in PIC mode. If the symbol 1933 // has hidden or protected visibility, or if it is static or local, then 1934 // we don't need to use the PLT - we can directly call it. 1935 if (Subtarget->isTargetELF() && 1936 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1937 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1938 OpFlags = X86II::MO_PLT; 1939 } else if (Subtarget->isPICStyleStubAny() && 1940 (GV->isDeclaration() || GV->isWeakForLinker()) && 1941 Subtarget->getDarwinVers() < 9) { 1942 // PC-relative references to external symbols should go through $stub, 1943 // unless we're building with the leopard linker or later, which 1944 // automatically synthesizes these stubs. 1945 OpFlags = X86II::MO_DARWIN_STUB; 1946 } 1947 1948 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 1949 G->getOffset(), OpFlags); 1950 } 1951 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1952 unsigned char OpFlags = 0; 1953 1954 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 1955 // symbols should go through the PLT. 1956 if (Subtarget->isTargetELF() && 1957 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1958 OpFlags = X86II::MO_PLT; 1959 } else if (Subtarget->isPICStyleStubAny() && 1960 Subtarget->getDarwinVers() < 9) { 1961 // PC-relative references to external symbols should go through $stub, 1962 // unless we're building with the leopard linker or later, which 1963 // automatically synthesizes these stubs. 1964 OpFlags = X86II::MO_DARWIN_STUB; 1965 } 1966 1967 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 1968 OpFlags); 1969 } else if (isTailCall) { 1970 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX; 1971 1972 Chain = DAG.getCopyToReg(Chain, dl, 1973 DAG.getRegister(Opc, getPointerTy()), 1974 Callee,InFlag); 1975 Callee = DAG.getRegister(Opc, getPointerTy()); 1976 // Add register as live out. 1977 MF.getRegInfo().addLiveOut(Opc); 1978 } 1979 1980 // Returns a chain & a flag for retval copy to use. 1981 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 1982 SmallVector<SDValue, 8> Ops; 1983 1984 if (isTailCall) { 1985 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1986 DAG.getIntPtrConstant(0, true), InFlag); 1987 InFlag = Chain.getValue(1); 1988 } 1989 1990 Ops.push_back(Chain); 1991 Ops.push_back(Callee); 1992 1993 if (isTailCall) 1994 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 1995 1996 // Add argument registers to the end of the list so that they are known live 1997 // into the call. 1998 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1999 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2000 RegsToPass[i].second.getValueType())); 2001 2002 // Add an implicit use GOT pointer in EBX. 2003 if (!isTailCall && Subtarget->isPICStyleGOT()) 2004 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2005 2006 // Add an implicit use of AL for x86 vararg functions. 2007 if (Is64Bit && isVarArg) 2008 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2009 2010 if (InFlag.getNode()) 2011 Ops.push_back(InFlag); 2012 2013 if (isTailCall) { 2014 // If this is the first return lowered for this function, add the regs 2015 // to the liveout set for the function. 2016 if (MF.getRegInfo().liveout_empty()) { 2017 SmallVector<CCValAssign, 16> RVLocs; 2018 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2019 *DAG.getContext()); 2020 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2021 for (unsigned i = 0; i != RVLocs.size(); ++i) 2022 if (RVLocs[i].isRegLoc()) 2023 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2024 } 2025 2026 assert(((Callee.getOpcode() == ISD::Register && 2027 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX || 2028 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) || 2029 Callee.getOpcode() == ISD::TargetExternalSymbol || 2030 Callee.getOpcode() == ISD::TargetGlobalAddress) && 2031 "Expecting an global address, external symbol, or register"); 2032 2033 return DAG.getNode(X86ISD::TC_RETURN, dl, 2034 NodeTys, &Ops[0], Ops.size()); 2035 } 2036 2037 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2038 InFlag = Chain.getValue(1); 2039 2040 // Create the CALLSEQ_END node. 2041 unsigned NumBytesForCalleeToPush; 2042 if (IsCalleePop(isVarArg, CallConv)) 2043 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2044 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet) 2045 // If this is is a call to a struct-return function, the callee 2046 // pops the hidden struct pointer, so we have to push it back. 2047 // This is common for Darwin/X86, Linux & Mingw32 targets. 2048 NumBytesForCalleeToPush = 4; 2049 else 2050 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2051 2052 // Returns a flag for retval copy to use. 2053 Chain = DAG.getCALLSEQ_END(Chain, 2054 DAG.getIntPtrConstant(NumBytes, true), 2055 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2056 true), 2057 InFlag); 2058 InFlag = Chain.getValue(1); 2059 2060 // Handle result values, copying them out of physregs into vregs that we 2061 // return. 2062 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2063 Ins, dl, DAG, InVals); 2064} 2065 2066 2067//===----------------------------------------------------------------------===// 2068// Fast Calling Convention (tail call) implementation 2069//===----------------------------------------------------------------------===// 2070 2071// Like std call, callee cleans arguments, convention except that ECX is 2072// reserved for storing the tail called function address. Only 2 registers are 2073// free for argument passing (inreg). Tail call optimization is performed 2074// provided: 2075// * tailcallopt is enabled 2076// * caller/callee are fastcc 2077// On X86_64 architecture with GOT-style position independent code only local 2078// (within module) calls are supported at the moment. 2079// To keep the stack aligned according to platform abi the function 2080// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2081// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2082// If a tail called function callee has more arguments than the caller the 2083// caller needs to make sure that there is room to move the RETADDR to. This is 2084// achieved by reserving an area the size of the argument delta right after the 2085// original REtADDR, but before the saved framepointer or the spilled registers 2086// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2087// stack layout: 2088// arg1 2089// arg2 2090// RETADDR 2091// [ new RETADDR 2092// move area ] 2093// (possible EBP) 2094// ESI 2095// EDI 2096// local1 .. 2097 2098/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2099/// for a 16 byte align requirement. 2100unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2101 SelectionDAG& DAG) { 2102 MachineFunction &MF = DAG.getMachineFunction(); 2103 const TargetMachine &TM = MF.getTarget(); 2104 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2105 unsigned StackAlignment = TFI.getStackAlignment(); 2106 uint64_t AlignMask = StackAlignment - 1; 2107 int64_t Offset = StackSize; 2108 uint64_t SlotSize = TD->getPointerSize(); 2109 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2110 // Number smaller than 12 so just add the difference. 2111 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2112 } else { 2113 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2114 Offset = ((~AlignMask) & Offset) + StackAlignment + 2115 (StackAlignment-SlotSize); 2116 } 2117 return Offset; 2118} 2119 2120/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2121/// for tail call optimization. Targets which want to do tail call 2122/// optimization should implement this function. 2123bool 2124X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2125 CallingConv::ID CalleeCC, 2126 bool isVarArg, 2127 const SmallVectorImpl<ISD::InputArg> &Ins, 2128 SelectionDAG& DAG) const { 2129 MachineFunction &MF = DAG.getMachineFunction(); 2130 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2131 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC; 2132} 2133 2134FastISel * 2135X86TargetLowering::createFastISel(MachineFunction &mf, 2136 MachineModuleInfo *mmo, 2137 DwarfWriter *dw, 2138 DenseMap<const Value *, unsigned> &vm, 2139 DenseMap<const BasicBlock *, 2140 MachineBasicBlock *> &bm, 2141 DenseMap<const AllocaInst *, int> &am 2142#ifndef NDEBUG 2143 , SmallSet<Instruction*, 8> &cil 2144#endif 2145 ) { 2146 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2147#ifndef NDEBUG 2148 , cil 2149#endif 2150 ); 2151} 2152 2153 2154//===----------------------------------------------------------------------===// 2155// Other Lowering Hooks 2156//===----------------------------------------------------------------------===// 2157 2158 2159SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2160 MachineFunction &MF = DAG.getMachineFunction(); 2161 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2162 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2163 2164 if (ReturnAddrIndex == 0) { 2165 // Set up a frame object for the return address. 2166 uint64_t SlotSize = TD->getPointerSize(); 2167 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize); 2168 FuncInfo->setRAIndex(ReturnAddrIndex); 2169 } 2170 2171 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2172} 2173 2174 2175bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2176 bool hasSymbolicDisplacement) { 2177 // Offset should fit into 32 bit immediate field. 2178 if (!isInt32(Offset)) 2179 return false; 2180 2181 // If we don't have a symbolic displacement - we don't have any extra 2182 // restrictions. 2183 if (!hasSymbolicDisplacement) 2184 return true; 2185 2186 // FIXME: Some tweaks might be needed for medium code model. 2187 if (M != CodeModel::Small && M != CodeModel::Kernel) 2188 return false; 2189 2190 // For small code model we assume that latest object is 16MB before end of 31 2191 // bits boundary. We may also accept pretty large negative constants knowing 2192 // that all objects are in the positive half of address space. 2193 if (M == CodeModel::Small && Offset < 16*1024*1024) 2194 return true; 2195 2196 // For kernel code model we know that all object resist in the negative half 2197 // of 32bits address space. We may not accept negative offsets, since they may 2198 // be just off and we may accept pretty large positive ones. 2199 if (M == CodeModel::Kernel && Offset > 0) 2200 return true; 2201 2202 return false; 2203} 2204 2205/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2206/// specific condition code, returning the condition code and the LHS/RHS of the 2207/// comparison to make. 2208static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2209 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2210 if (!isFP) { 2211 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2212 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2213 // X > -1 -> X == 0, jump !sign. 2214 RHS = DAG.getConstant(0, RHS.getValueType()); 2215 return X86::COND_NS; 2216 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2217 // X < 0 -> X == 0, jump on sign. 2218 return X86::COND_S; 2219 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2220 // X < 1 -> X <= 0 2221 RHS = DAG.getConstant(0, RHS.getValueType()); 2222 return X86::COND_LE; 2223 } 2224 } 2225 2226 switch (SetCCOpcode) { 2227 default: llvm_unreachable("Invalid integer condition!"); 2228 case ISD::SETEQ: return X86::COND_E; 2229 case ISD::SETGT: return X86::COND_G; 2230 case ISD::SETGE: return X86::COND_GE; 2231 case ISD::SETLT: return X86::COND_L; 2232 case ISD::SETLE: return X86::COND_LE; 2233 case ISD::SETNE: return X86::COND_NE; 2234 case ISD::SETULT: return X86::COND_B; 2235 case ISD::SETUGT: return X86::COND_A; 2236 case ISD::SETULE: return X86::COND_BE; 2237 case ISD::SETUGE: return X86::COND_AE; 2238 } 2239 } 2240 2241 // First determine if it is required or is profitable to flip the operands. 2242 2243 // If LHS is a foldable load, but RHS is not, flip the condition. 2244 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2245 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2246 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2247 std::swap(LHS, RHS); 2248 } 2249 2250 switch (SetCCOpcode) { 2251 default: break; 2252 case ISD::SETOLT: 2253 case ISD::SETOLE: 2254 case ISD::SETUGT: 2255 case ISD::SETUGE: 2256 std::swap(LHS, RHS); 2257 break; 2258 } 2259 2260 // On a floating point condition, the flags are set as follows: 2261 // ZF PF CF op 2262 // 0 | 0 | 0 | X > Y 2263 // 0 | 0 | 1 | X < Y 2264 // 1 | 0 | 0 | X == Y 2265 // 1 | 1 | 1 | unordered 2266 switch (SetCCOpcode) { 2267 default: llvm_unreachable("Condcode should be pre-legalized away"); 2268 case ISD::SETUEQ: 2269 case ISD::SETEQ: return X86::COND_E; 2270 case ISD::SETOLT: // flipped 2271 case ISD::SETOGT: 2272 case ISD::SETGT: return X86::COND_A; 2273 case ISD::SETOLE: // flipped 2274 case ISD::SETOGE: 2275 case ISD::SETGE: return X86::COND_AE; 2276 case ISD::SETUGT: // flipped 2277 case ISD::SETULT: 2278 case ISD::SETLT: return X86::COND_B; 2279 case ISD::SETUGE: // flipped 2280 case ISD::SETULE: 2281 case ISD::SETLE: return X86::COND_BE; 2282 case ISD::SETONE: 2283 case ISD::SETNE: return X86::COND_NE; 2284 case ISD::SETUO: return X86::COND_P; 2285 case ISD::SETO: return X86::COND_NP; 2286 } 2287} 2288 2289/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2290/// code. Current x86 isa includes the following FP cmov instructions: 2291/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2292static bool hasFPCMov(unsigned X86CC) { 2293 switch (X86CC) { 2294 default: 2295 return false; 2296 case X86::COND_B: 2297 case X86::COND_BE: 2298 case X86::COND_E: 2299 case X86::COND_P: 2300 case X86::COND_A: 2301 case X86::COND_AE: 2302 case X86::COND_NE: 2303 case X86::COND_NP: 2304 return true; 2305 } 2306} 2307 2308/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2309/// the specified range (L, H]. 2310static bool isUndefOrInRange(int Val, int Low, int Hi) { 2311 return (Val < 0) || (Val >= Low && Val < Hi); 2312} 2313 2314/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2315/// specified value. 2316static bool isUndefOrEqual(int Val, int CmpVal) { 2317 if (Val < 0 || Val == CmpVal) 2318 return true; 2319 return false; 2320} 2321 2322/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2323/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2324/// the second operand. 2325static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2326 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2327 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2328 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2329 return (Mask[0] < 2 && Mask[1] < 2); 2330 return false; 2331} 2332 2333bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2334 SmallVector<int, 8> M; 2335 N->getMask(M); 2336 return ::isPSHUFDMask(M, N->getValueType(0)); 2337} 2338 2339/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2340/// is suitable for input to PSHUFHW. 2341static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2342 if (VT != MVT::v8i16) 2343 return false; 2344 2345 // Lower quadword copied in order or undef. 2346 for (int i = 0; i != 4; ++i) 2347 if (Mask[i] >= 0 && Mask[i] != i) 2348 return false; 2349 2350 // Upper quadword shuffled. 2351 for (int i = 4; i != 8; ++i) 2352 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2353 return false; 2354 2355 return true; 2356} 2357 2358bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2359 SmallVector<int, 8> M; 2360 N->getMask(M); 2361 return ::isPSHUFHWMask(M, N->getValueType(0)); 2362} 2363 2364/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2365/// is suitable for input to PSHUFLW. 2366static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2367 if (VT != MVT::v8i16) 2368 return false; 2369 2370 // Upper quadword copied in order. 2371 for (int i = 4; i != 8; ++i) 2372 if (Mask[i] >= 0 && Mask[i] != i) 2373 return false; 2374 2375 // Lower quadword shuffled. 2376 for (int i = 0; i != 4; ++i) 2377 if (Mask[i] >= 4) 2378 return false; 2379 2380 return true; 2381} 2382 2383bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2384 SmallVector<int, 8> M; 2385 N->getMask(M); 2386 return ::isPSHUFLWMask(M, N->getValueType(0)); 2387} 2388 2389/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2390/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2391static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2392 int NumElems = VT.getVectorNumElements(); 2393 if (NumElems != 2 && NumElems != 4) 2394 return false; 2395 2396 int Half = NumElems / 2; 2397 for (int i = 0; i < Half; ++i) 2398 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2399 return false; 2400 for (int i = Half; i < NumElems; ++i) 2401 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2402 return false; 2403 2404 return true; 2405} 2406 2407bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2408 SmallVector<int, 8> M; 2409 N->getMask(M); 2410 return ::isSHUFPMask(M, N->getValueType(0)); 2411} 2412 2413/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2414/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2415/// half elements to come from vector 1 (which would equal the dest.) and 2416/// the upper half to come from vector 2. 2417static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2418 int NumElems = VT.getVectorNumElements(); 2419 2420 if (NumElems != 2 && NumElems != 4) 2421 return false; 2422 2423 int Half = NumElems / 2; 2424 for (int i = 0; i < Half; ++i) 2425 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2426 return false; 2427 for (int i = Half; i < NumElems; ++i) 2428 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2429 return false; 2430 return true; 2431} 2432 2433static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2434 SmallVector<int, 8> M; 2435 N->getMask(M); 2436 return isCommutedSHUFPMask(M, N->getValueType(0)); 2437} 2438 2439/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2440/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2441bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2442 if (N->getValueType(0).getVectorNumElements() != 4) 2443 return false; 2444 2445 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2446 return isUndefOrEqual(N->getMaskElt(0), 6) && 2447 isUndefOrEqual(N->getMaskElt(1), 7) && 2448 isUndefOrEqual(N->getMaskElt(2), 2) && 2449 isUndefOrEqual(N->getMaskElt(3), 3); 2450} 2451 2452/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2453/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2454bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2455 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2456 2457 if (NumElems != 2 && NumElems != 4) 2458 return false; 2459 2460 for (unsigned i = 0; i < NumElems/2; ++i) 2461 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2462 return false; 2463 2464 for (unsigned i = NumElems/2; i < NumElems; ++i) 2465 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2466 return false; 2467 2468 return true; 2469} 2470 2471/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 2472/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D} 2473/// and MOVLHPS. 2474bool X86::isMOVHPMask(ShuffleVectorSDNode *N) { 2475 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2476 2477 if (NumElems != 2 && NumElems != 4) 2478 return false; 2479 2480 for (unsigned i = 0; i < NumElems/2; ++i) 2481 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2482 return false; 2483 2484 for (unsigned i = 0; i < NumElems/2; ++i) 2485 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2486 return false; 2487 2488 return true; 2489} 2490 2491/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2492/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2493/// <2, 3, 2, 3> 2494bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2495 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2496 2497 if (NumElems != 4) 2498 return false; 2499 2500 return isUndefOrEqual(N->getMaskElt(0), 2) && 2501 isUndefOrEqual(N->getMaskElt(1), 3) && 2502 isUndefOrEqual(N->getMaskElt(2), 2) && 2503 isUndefOrEqual(N->getMaskElt(3), 3); 2504} 2505 2506/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2507/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2508static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2509 bool V2IsSplat = false) { 2510 int NumElts = VT.getVectorNumElements(); 2511 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2512 return false; 2513 2514 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2515 int BitI = Mask[i]; 2516 int BitI1 = Mask[i+1]; 2517 if (!isUndefOrEqual(BitI, j)) 2518 return false; 2519 if (V2IsSplat) { 2520 if (!isUndefOrEqual(BitI1, NumElts)) 2521 return false; 2522 } else { 2523 if (!isUndefOrEqual(BitI1, j + NumElts)) 2524 return false; 2525 } 2526 } 2527 return true; 2528} 2529 2530bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2531 SmallVector<int, 8> M; 2532 N->getMask(M); 2533 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2534} 2535 2536/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2537/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2538static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2539 bool V2IsSplat = false) { 2540 int NumElts = VT.getVectorNumElements(); 2541 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2542 return false; 2543 2544 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2545 int BitI = Mask[i]; 2546 int BitI1 = Mask[i+1]; 2547 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2548 return false; 2549 if (V2IsSplat) { 2550 if (isUndefOrEqual(BitI1, NumElts)) 2551 return false; 2552 } else { 2553 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2554 return false; 2555 } 2556 } 2557 return true; 2558} 2559 2560bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2561 SmallVector<int, 8> M; 2562 N->getMask(M); 2563 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2564} 2565 2566/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2567/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2568/// <0, 0, 1, 1> 2569static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2570 int NumElems = VT.getVectorNumElements(); 2571 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2572 return false; 2573 2574 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2575 int BitI = Mask[i]; 2576 int BitI1 = Mask[i+1]; 2577 if (!isUndefOrEqual(BitI, j)) 2578 return false; 2579 if (!isUndefOrEqual(BitI1, j)) 2580 return false; 2581 } 2582 return true; 2583} 2584 2585bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2586 SmallVector<int, 8> M; 2587 N->getMask(M); 2588 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2589} 2590 2591/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2592/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2593/// <2, 2, 3, 3> 2594static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2595 int NumElems = VT.getVectorNumElements(); 2596 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2597 return false; 2598 2599 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2600 int BitI = Mask[i]; 2601 int BitI1 = Mask[i+1]; 2602 if (!isUndefOrEqual(BitI, j)) 2603 return false; 2604 if (!isUndefOrEqual(BitI1, j)) 2605 return false; 2606 } 2607 return true; 2608} 2609 2610bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2611 SmallVector<int, 8> M; 2612 N->getMask(M); 2613 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2614} 2615 2616/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2617/// specifies a shuffle of elements that is suitable for input to MOVSS, 2618/// MOVSD, and MOVD, i.e. setting the lowest element. 2619static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2620 if (VT.getVectorElementType().getSizeInBits() < 32) 2621 return false; 2622 2623 int NumElts = VT.getVectorNumElements(); 2624 2625 if (!isUndefOrEqual(Mask[0], NumElts)) 2626 return false; 2627 2628 for (int i = 1; i < NumElts; ++i) 2629 if (!isUndefOrEqual(Mask[i], i)) 2630 return false; 2631 2632 return true; 2633} 2634 2635bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2636 SmallVector<int, 8> M; 2637 N->getMask(M); 2638 return ::isMOVLMask(M, N->getValueType(0)); 2639} 2640 2641/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2642/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2643/// element of vector 2 and the other elements to come from vector 1 in order. 2644static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2645 bool V2IsSplat = false, bool V2IsUndef = false) { 2646 int NumOps = VT.getVectorNumElements(); 2647 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2648 return false; 2649 2650 if (!isUndefOrEqual(Mask[0], 0)) 2651 return false; 2652 2653 for (int i = 1; i < NumOps; ++i) 2654 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2655 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2656 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2657 return false; 2658 2659 return true; 2660} 2661 2662static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2663 bool V2IsUndef = false) { 2664 SmallVector<int, 8> M; 2665 N->getMask(M); 2666 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2667} 2668 2669/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2670/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2671bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2672 if (N->getValueType(0).getVectorNumElements() != 4) 2673 return false; 2674 2675 // Expect 1, 1, 3, 3 2676 for (unsigned i = 0; i < 2; ++i) { 2677 int Elt = N->getMaskElt(i); 2678 if (Elt >= 0 && Elt != 1) 2679 return false; 2680 } 2681 2682 bool HasHi = false; 2683 for (unsigned i = 2; i < 4; ++i) { 2684 int Elt = N->getMaskElt(i); 2685 if (Elt >= 0 && Elt != 3) 2686 return false; 2687 if (Elt == 3) 2688 HasHi = true; 2689 } 2690 // Don't use movshdup if it can be done with a shufps. 2691 // FIXME: verify that matching u, u, 3, 3 is what we want. 2692 return HasHi; 2693} 2694 2695/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2696/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2697bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 2698 if (N->getValueType(0).getVectorNumElements() != 4) 2699 return false; 2700 2701 // Expect 0, 0, 2, 2 2702 for (unsigned i = 0; i < 2; ++i) 2703 if (N->getMaskElt(i) > 0) 2704 return false; 2705 2706 bool HasHi = false; 2707 for (unsigned i = 2; i < 4; ++i) { 2708 int Elt = N->getMaskElt(i); 2709 if (Elt >= 0 && Elt != 2) 2710 return false; 2711 if (Elt == 2) 2712 HasHi = true; 2713 } 2714 // Don't use movsldup if it can be done with a shufps. 2715 return HasHi; 2716} 2717 2718/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2719/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2720bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 2721 int e = N->getValueType(0).getVectorNumElements() / 2; 2722 2723 for (int i = 0; i < e; ++i) 2724 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2725 return false; 2726 for (int i = 0; i < e; ++i) 2727 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 2728 return false; 2729 return true; 2730} 2731 2732/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 2733/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 2734/// instructions. 2735unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 2736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2737 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 2738 2739 unsigned Shift = (NumOperands == 4) ? 2 : 1; 2740 unsigned Mask = 0; 2741 for (int i = 0; i < NumOperands; ++i) { 2742 int Val = SVOp->getMaskElt(NumOperands-i-1); 2743 if (Val < 0) Val = 0; 2744 if (Val >= NumOperands) Val -= NumOperands; 2745 Mask |= Val; 2746 if (i != NumOperands - 1) 2747 Mask <<= Shift; 2748 } 2749 return Mask; 2750} 2751 2752/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 2753/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW 2754/// instructions. 2755unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 2756 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2757 unsigned Mask = 0; 2758 // 8 nodes, but we only care about the last 4. 2759 for (unsigned i = 7; i >= 4; --i) { 2760 int Val = SVOp->getMaskElt(i); 2761 if (Val >= 0) 2762 Mask |= (Val - 4); 2763 if (i != 4) 2764 Mask <<= 2; 2765 } 2766 return Mask; 2767} 2768 2769/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 2770/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW 2771/// instructions. 2772unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 2773 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 2774 unsigned Mask = 0; 2775 // 8 nodes, but we only care about the first 4. 2776 for (int i = 3; i >= 0; --i) { 2777 int Val = SVOp->getMaskElt(i); 2778 if (Val >= 0) 2779 Mask |= Val; 2780 if (i != 0) 2781 Mask <<= 2; 2782 } 2783 return Mask; 2784} 2785 2786/// isZeroNode - Returns true if Elt is a constant zero or a floating point 2787/// constant +0.0. 2788bool X86::isZeroNode(SDValue Elt) { 2789 return ((isa<ConstantSDNode>(Elt) && 2790 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 2791 (isa<ConstantFPSDNode>(Elt) && 2792 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 2793} 2794 2795/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 2796/// their permute mask. 2797static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 2798 SelectionDAG &DAG) { 2799 EVT VT = SVOp->getValueType(0); 2800 unsigned NumElems = VT.getVectorNumElements(); 2801 SmallVector<int, 8> MaskVec; 2802 2803 for (unsigned i = 0; i != NumElems; ++i) { 2804 int idx = SVOp->getMaskElt(i); 2805 if (idx < 0) 2806 MaskVec.push_back(idx); 2807 else if (idx < (int)NumElems) 2808 MaskVec.push_back(idx + NumElems); 2809 else 2810 MaskVec.push_back(idx - NumElems); 2811 } 2812 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 2813 SVOp->getOperand(0), &MaskVec[0]); 2814} 2815 2816/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 2817/// the two vector operands have swapped position. 2818static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 2819 unsigned NumElems = VT.getVectorNumElements(); 2820 for (unsigned i = 0; i != NumElems; ++i) { 2821 int idx = Mask[i]; 2822 if (idx < 0) 2823 continue; 2824 else if (idx < (int)NumElems) 2825 Mask[i] = idx + NumElems; 2826 else 2827 Mask[i] = idx - NumElems; 2828 } 2829} 2830 2831/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 2832/// match movhlps. The lower half elements should come from upper half of 2833/// V1 (and in order), and the upper half elements should come from the upper 2834/// half of V2 (and in order). 2835static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 2836 if (Op->getValueType(0).getVectorNumElements() != 4) 2837 return false; 2838 for (unsigned i = 0, e = 2; i != e; ++i) 2839 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 2840 return false; 2841 for (unsigned i = 2; i != 4; ++i) 2842 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 2843 return false; 2844 return true; 2845} 2846 2847/// isScalarLoadToVector - Returns true if the node is a scalar load that 2848/// is promoted to a vector. It also returns the LoadSDNode by reference if 2849/// required. 2850static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 2851 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 2852 return false; 2853 N = N->getOperand(0).getNode(); 2854 if (!ISD::isNON_EXTLoad(N)) 2855 return false; 2856 if (LD) 2857 *LD = cast<LoadSDNode>(N); 2858 return true; 2859} 2860 2861/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 2862/// match movlp{s|d}. The lower half elements should come from lower half of 2863/// V1 (and in order), and the upper half elements should come from the upper 2864/// half of V2 (and in order). And since V1 will become the source of the 2865/// MOVLP, it must be either a vector load or a scalar load to vector. 2866static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 2867 ShuffleVectorSDNode *Op) { 2868 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 2869 return false; 2870 // Is V2 is a vector load, don't do this transformation. We will try to use 2871 // load folding shufps op. 2872 if (ISD::isNON_EXTLoad(V2)) 2873 return false; 2874 2875 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 2876 2877 if (NumElems != 2 && NumElems != 4) 2878 return false; 2879 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 2880 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 2881 return false; 2882 for (unsigned i = NumElems/2; i != NumElems; ++i) 2883 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 2884 return false; 2885 return true; 2886} 2887 2888/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 2889/// all the same. 2890static bool isSplatVector(SDNode *N) { 2891 if (N->getOpcode() != ISD::BUILD_VECTOR) 2892 return false; 2893 2894 SDValue SplatValue = N->getOperand(0); 2895 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 2896 if (N->getOperand(i) != SplatValue) 2897 return false; 2898 return true; 2899} 2900 2901/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 2902/// to an zero vector. 2903/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 2904static bool isZeroShuffle(ShuffleVectorSDNode *N) { 2905 SDValue V1 = N->getOperand(0); 2906 SDValue V2 = N->getOperand(1); 2907 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2908 for (unsigned i = 0; i != NumElems; ++i) { 2909 int Idx = N->getMaskElt(i); 2910 if (Idx >= (int)NumElems) { 2911 unsigned Opc = V2.getOpcode(); 2912 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 2913 continue; 2914 if (Opc != ISD::BUILD_VECTOR || 2915 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 2916 return false; 2917 } else if (Idx >= 0) { 2918 unsigned Opc = V1.getOpcode(); 2919 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 2920 continue; 2921 if (Opc != ISD::BUILD_VECTOR || 2922 !X86::isZeroNode(V1.getOperand(Idx))) 2923 return false; 2924 } 2925 } 2926 return true; 2927} 2928 2929/// getZeroVector - Returns a vector of specified type with all zero elements. 2930/// 2931static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 2932 DebugLoc dl) { 2933 assert(VT.isVector() && "Expected a vector type"); 2934 2935 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2936 // type. This ensures they get CSE'd. 2937 SDValue Vec; 2938 if (VT.getSizeInBits() == 64) { // MMX 2939 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2940 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2941 } else if (HasSSE2) { // SSE2 2942 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 2943 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2944 } else { // SSE1 2945 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 2946 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 2947 } 2948 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2949} 2950 2951/// getOnesVector - Returns a vector of specified type with all bits set. 2952/// 2953static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 2954 assert(VT.isVector() && "Expected a vector type"); 2955 2956 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 2957 // type. This ensures they get CSE'd. 2958 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 2959 SDValue Vec; 2960 if (VT.getSizeInBits() == 64) // MMX 2961 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 2962 else // SSE 2963 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 2964 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 2965} 2966 2967 2968/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 2969/// that point to V2 points to its first element. 2970static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 2971 EVT VT = SVOp->getValueType(0); 2972 unsigned NumElems = VT.getVectorNumElements(); 2973 2974 bool Changed = false; 2975 SmallVector<int, 8> MaskVec; 2976 SVOp->getMask(MaskVec); 2977 2978 for (unsigned i = 0; i != NumElems; ++i) { 2979 if (MaskVec[i] > (int)NumElems) { 2980 MaskVec[i] = NumElems; 2981 Changed = true; 2982 } 2983 } 2984 if (Changed) 2985 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 2986 SVOp->getOperand(1), &MaskVec[0]); 2987 return SDValue(SVOp, 0); 2988} 2989 2990/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 2991/// operation of specified width. 2992static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 2993 SDValue V2) { 2994 unsigned NumElems = VT.getVectorNumElements(); 2995 SmallVector<int, 8> Mask; 2996 Mask.push_back(NumElems); 2997 for (unsigned i = 1; i != NumElems; ++i) 2998 Mask.push_back(i); 2999 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3000} 3001 3002/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3003static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3004 SDValue V2) { 3005 unsigned NumElems = VT.getVectorNumElements(); 3006 SmallVector<int, 8> Mask; 3007 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3008 Mask.push_back(i); 3009 Mask.push_back(i + NumElems); 3010 } 3011 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3012} 3013 3014/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3015static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3016 SDValue V2) { 3017 unsigned NumElems = VT.getVectorNumElements(); 3018 unsigned Half = NumElems/2; 3019 SmallVector<int, 8> Mask; 3020 for (unsigned i = 0; i != Half; ++i) { 3021 Mask.push_back(i + Half); 3022 Mask.push_back(i + NumElems + Half); 3023 } 3024 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3025} 3026 3027/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3028static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3029 bool HasSSE2) { 3030 if (SV->getValueType(0).getVectorNumElements() <= 4) 3031 return SDValue(SV, 0); 3032 3033 EVT PVT = MVT::v4f32; 3034 EVT VT = SV->getValueType(0); 3035 DebugLoc dl = SV->getDebugLoc(); 3036 SDValue V1 = SV->getOperand(0); 3037 int NumElems = VT.getVectorNumElements(); 3038 int EltNo = SV->getSplatIndex(); 3039 3040 // unpack elements to the correct location 3041 while (NumElems > 4) { 3042 if (EltNo < NumElems/2) { 3043 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3044 } else { 3045 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3046 EltNo -= NumElems/2; 3047 } 3048 NumElems >>= 1; 3049 } 3050 3051 // Perform the splat. 3052 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3053 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3054 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3055 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3056} 3057 3058/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3059/// vector of zero or undef vector. This produces a shuffle where the low 3060/// element of V2 is swizzled into the zero/undef vector, landing at element 3061/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3062static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3063 bool isZero, bool HasSSE2, 3064 SelectionDAG &DAG) { 3065 EVT VT = V2.getValueType(); 3066 SDValue V1 = isZero 3067 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3068 unsigned NumElems = VT.getVectorNumElements(); 3069 SmallVector<int, 16> MaskVec; 3070 for (unsigned i = 0; i != NumElems; ++i) 3071 // If this is the insertion idx, put the low elt of V2 here. 3072 MaskVec.push_back(i == Idx ? NumElems : i); 3073 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3074} 3075 3076/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3077/// a shuffle that is zero. 3078static 3079unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3080 bool Low, SelectionDAG &DAG) { 3081 unsigned NumZeros = 0; 3082 for (int i = 0; i < NumElems; ++i) { 3083 unsigned Index = Low ? i : NumElems-i-1; 3084 int Idx = SVOp->getMaskElt(Index); 3085 if (Idx < 0) { 3086 ++NumZeros; 3087 continue; 3088 } 3089 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3090 if (Elt.getNode() && X86::isZeroNode(Elt)) 3091 ++NumZeros; 3092 else 3093 break; 3094 } 3095 return NumZeros; 3096} 3097 3098/// isVectorShift - Returns true if the shuffle can be implemented as a 3099/// logical left or right shift of a vector. 3100/// FIXME: split into pslldqi, psrldqi, palignr variants. 3101static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3102 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3103 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3104 3105 isLeft = true; 3106 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3107 if (!NumZeros) { 3108 isLeft = false; 3109 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3110 if (!NumZeros) 3111 return false; 3112 } 3113 bool SeenV1 = false; 3114 bool SeenV2 = false; 3115 for (int i = NumZeros; i < NumElems; ++i) { 3116 int Val = isLeft ? (i - NumZeros) : i; 3117 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3118 if (Idx < 0) 3119 continue; 3120 if (Idx < NumElems) 3121 SeenV1 = true; 3122 else { 3123 Idx -= NumElems; 3124 SeenV2 = true; 3125 } 3126 if (Idx != Val) 3127 return false; 3128 } 3129 if (SeenV1 && SeenV2) 3130 return false; 3131 3132 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3133 ShAmt = NumZeros; 3134 return true; 3135} 3136 3137 3138/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3139/// 3140static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3141 unsigned NumNonZero, unsigned NumZero, 3142 SelectionDAG &DAG, TargetLowering &TLI) { 3143 if (NumNonZero > 8) 3144 return SDValue(); 3145 3146 DebugLoc dl = Op.getDebugLoc(); 3147 SDValue V(0, 0); 3148 bool First = true; 3149 for (unsigned i = 0; i < 16; ++i) { 3150 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3151 if (ThisIsNonZero && First) { 3152 if (NumZero) 3153 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3154 else 3155 V = DAG.getUNDEF(MVT::v8i16); 3156 First = false; 3157 } 3158 3159 if ((i & 1) != 0) { 3160 SDValue ThisElt(0, 0), LastElt(0, 0); 3161 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3162 if (LastIsNonZero) { 3163 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3164 MVT::i16, Op.getOperand(i-1)); 3165 } 3166 if (ThisIsNonZero) { 3167 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3168 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3169 ThisElt, DAG.getConstant(8, MVT::i8)); 3170 if (LastIsNonZero) 3171 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3172 } else 3173 ThisElt = LastElt; 3174 3175 if (ThisElt.getNode()) 3176 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3177 DAG.getIntPtrConstant(i/2)); 3178 } 3179 } 3180 3181 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3182} 3183 3184/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3185/// 3186static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3187 unsigned NumNonZero, unsigned NumZero, 3188 SelectionDAG &DAG, TargetLowering &TLI) { 3189 if (NumNonZero > 4) 3190 return SDValue(); 3191 3192 DebugLoc dl = Op.getDebugLoc(); 3193 SDValue V(0, 0); 3194 bool First = true; 3195 for (unsigned i = 0; i < 8; ++i) { 3196 bool isNonZero = (NonZeros & (1 << i)) != 0; 3197 if (isNonZero) { 3198 if (First) { 3199 if (NumZero) 3200 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3201 else 3202 V = DAG.getUNDEF(MVT::v8i16); 3203 First = false; 3204 } 3205 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3206 MVT::v8i16, V, Op.getOperand(i), 3207 DAG.getIntPtrConstant(i)); 3208 } 3209 } 3210 3211 return V; 3212} 3213 3214/// getVShift - Return a vector logical shift node. 3215/// 3216static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3217 unsigned NumBits, SelectionDAG &DAG, 3218 const TargetLowering &TLI, DebugLoc dl) { 3219 bool isMMX = VT.getSizeInBits() == 64; 3220 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3221 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3222 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3223 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3224 DAG.getNode(Opc, dl, ShVT, SrcOp, 3225 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3226} 3227 3228SDValue 3229X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3230 DebugLoc dl = Op.getDebugLoc(); 3231 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3232 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3233 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3234 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3235 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3236 // eliminated on x86-32 hosts. 3237 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3238 return Op; 3239 3240 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3241 return getOnesVector(Op.getValueType(), DAG, dl); 3242 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3243 } 3244 3245 EVT VT = Op.getValueType(); 3246 EVT ExtVT = VT.getVectorElementType(); 3247 unsigned EVTBits = ExtVT.getSizeInBits(); 3248 3249 unsigned NumElems = Op.getNumOperands(); 3250 unsigned NumZero = 0; 3251 unsigned NumNonZero = 0; 3252 unsigned NonZeros = 0; 3253 bool IsAllConstants = true; 3254 SmallSet<SDValue, 8> Values; 3255 for (unsigned i = 0; i < NumElems; ++i) { 3256 SDValue Elt = Op.getOperand(i); 3257 if (Elt.getOpcode() == ISD::UNDEF) 3258 continue; 3259 Values.insert(Elt); 3260 if (Elt.getOpcode() != ISD::Constant && 3261 Elt.getOpcode() != ISD::ConstantFP) 3262 IsAllConstants = false; 3263 if (X86::isZeroNode(Elt)) 3264 NumZero++; 3265 else { 3266 NonZeros |= (1 << i); 3267 NumNonZero++; 3268 } 3269 } 3270 3271 if (NumNonZero == 0) { 3272 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3273 return DAG.getUNDEF(VT); 3274 } 3275 3276 // Special case for single non-zero, non-undef, element. 3277 if (NumNonZero == 1) { 3278 unsigned Idx = CountTrailingZeros_32(NonZeros); 3279 SDValue Item = Op.getOperand(Idx); 3280 3281 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3282 // the value are obviously zero, truncate the value to i32 and do the 3283 // insertion that way. Only do this if the value is non-constant or if the 3284 // value is a constant being inserted into element 0. It is cheaper to do 3285 // a constant pool load than it is to do a movd + shuffle. 3286 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3287 (!IsAllConstants || Idx == 0)) { 3288 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3289 // Handle MMX and SSE both. 3290 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3291 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3292 3293 // Truncate the value (which may itself be a constant) to i32, and 3294 // convert it to a vector with movd (S2V+shuffle to zero extend). 3295 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3296 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3297 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3298 Subtarget->hasSSE2(), DAG); 3299 3300 // Now we have our 32-bit value zero extended in the low element of 3301 // a vector. If Idx != 0, swizzle it into place. 3302 if (Idx != 0) { 3303 SmallVector<int, 4> Mask; 3304 Mask.push_back(Idx); 3305 for (unsigned i = 1; i != VecElts; ++i) 3306 Mask.push_back(i); 3307 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3308 DAG.getUNDEF(Item.getValueType()), 3309 &Mask[0]); 3310 } 3311 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3312 } 3313 } 3314 3315 // If we have a constant or non-constant insertion into the low element of 3316 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3317 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3318 // depending on what the source datatype is. 3319 if (Idx == 0) { 3320 if (NumZero == 0) { 3321 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3322 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3323 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3324 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3325 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3326 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3327 DAG); 3328 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3329 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3330 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3331 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3332 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3333 Subtarget->hasSSE2(), DAG); 3334 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3335 } 3336 } 3337 3338 // Is it a vector logical left shift? 3339 if (NumElems == 2 && Idx == 1 && 3340 X86::isZeroNode(Op.getOperand(0)) && 3341 !X86::isZeroNode(Op.getOperand(1))) { 3342 unsigned NumBits = VT.getSizeInBits(); 3343 return getVShift(true, VT, 3344 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3345 VT, Op.getOperand(1)), 3346 NumBits/2, DAG, *this, dl); 3347 } 3348 3349 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3350 return SDValue(); 3351 3352 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3353 // is a non-constant being inserted into an element other than the low one, 3354 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3355 // movd/movss) to move this into the low element, then shuffle it into 3356 // place. 3357 if (EVTBits == 32) { 3358 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3359 3360 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3361 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3362 Subtarget->hasSSE2(), DAG); 3363 SmallVector<int, 8> MaskVec; 3364 for (unsigned i = 0; i < NumElems; i++) 3365 MaskVec.push_back(i == Idx ? 0 : 1); 3366 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3367 } 3368 } 3369 3370 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3371 if (Values.size() == 1) 3372 return SDValue(); 3373 3374 // A vector full of immediates; various special cases are already 3375 // handled, so this is best done with a single constant-pool load. 3376 if (IsAllConstants) 3377 return SDValue(); 3378 3379 // Let legalizer expand 2-wide build_vectors. 3380 if (EVTBits == 64) { 3381 if (NumNonZero == 1) { 3382 // One half is zero or undef. 3383 unsigned Idx = CountTrailingZeros_32(NonZeros); 3384 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3385 Op.getOperand(Idx)); 3386 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3387 Subtarget->hasSSE2(), DAG); 3388 } 3389 return SDValue(); 3390 } 3391 3392 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3393 if (EVTBits == 8 && NumElems == 16) { 3394 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3395 *this); 3396 if (V.getNode()) return V; 3397 } 3398 3399 if (EVTBits == 16 && NumElems == 8) { 3400 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3401 *this); 3402 if (V.getNode()) return V; 3403 } 3404 3405 // If element VT is == 32 bits, turn it into a number of shuffles. 3406 SmallVector<SDValue, 8> V; 3407 V.resize(NumElems); 3408 if (NumElems == 4 && NumZero > 0) { 3409 for (unsigned i = 0; i < 4; ++i) { 3410 bool isZero = !(NonZeros & (1 << i)); 3411 if (isZero) 3412 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3413 else 3414 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3415 } 3416 3417 for (unsigned i = 0; i < 2; ++i) { 3418 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3419 default: break; 3420 case 0: 3421 V[i] = V[i*2]; // Must be a zero vector. 3422 break; 3423 case 1: 3424 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3425 break; 3426 case 2: 3427 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3428 break; 3429 case 3: 3430 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3431 break; 3432 } 3433 } 3434 3435 SmallVector<int, 8> MaskVec; 3436 bool Reverse = (NonZeros & 0x3) == 2; 3437 for (unsigned i = 0; i < 2; ++i) 3438 MaskVec.push_back(Reverse ? 1-i : i); 3439 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3440 for (unsigned i = 0; i < 2; ++i) 3441 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3442 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3443 } 3444 3445 if (Values.size() > 2) { 3446 // If we have SSE 4.1, Expand into a number of inserts unless the number of 3447 // values to be inserted is equal to the number of elements, in which case 3448 // use the unpack code below in the hopes of matching the consecutive elts 3449 // load merge pattern for shuffles. 3450 // FIXME: We could probably just check that here directly. 3451 if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 3452 getSubtarget()->hasSSE41()) { 3453 V[0] = DAG.getUNDEF(VT); 3454 for (unsigned i = 0; i < NumElems; ++i) 3455 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3456 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3457 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3458 return V[0]; 3459 } 3460 // Expand into a number of unpckl*. 3461 // e.g. for v4f32 3462 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3463 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3464 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3465 for (unsigned i = 0; i < NumElems; ++i) 3466 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3467 NumElems >>= 1; 3468 while (NumElems != 0) { 3469 for (unsigned i = 0; i < NumElems; ++i) 3470 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3471 NumElems >>= 1; 3472 } 3473 return V[0]; 3474 } 3475 3476 return SDValue(); 3477} 3478 3479// v8i16 shuffles - Prefer shuffles in the following order: 3480// 1. [all] pshuflw, pshufhw, optional move 3481// 2. [ssse3] 1 x pshufb 3482// 3. [ssse3] 2 x pshufb + 1 x por 3483// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3484static 3485SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3486 SelectionDAG &DAG, X86TargetLowering &TLI) { 3487 SDValue V1 = SVOp->getOperand(0); 3488 SDValue V2 = SVOp->getOperand(1); 3489 DebugLoc dl = SVOp->getDebugLoc(); 3490 SmallVector<int, 8> MaskVals; 3491 3492 // Determine if more than 1 of the words in each of the low and high quadwords 3493 // of the result come from the same quadword of one of the two inputs. Undef 3494 // mask values count as coming from any quadword, for better codegen. 3495 SmallVector<unsigned, 4> LoQuad(4); 3496 SmallVector<unsigned, 4> HiQuad(4); 3497 BitVector InputQuads(4); 3498 for (unsigned i = 0; i < 8; ++i) { 3499 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3500 int EltIdx = SVOp->getMaskElt(i); 3501 MaskVals.push_back(EltIdx); 3502 if (EltIdx < 0) { 3503 ++Quad[0]; 3504 ++Quad[1]; 3505 ++Quad[2]; 3506 ++Quad[3]; 3507 continue; 3508 } 3509 ++Quad[EltIdx / 4]; 3510 InputQuads.set(EltIdx / 4); 3511 } 3512 3513 int BestLoQuad = -1; 3514 unsigned MaxQuad = 1; 3515 for (unsigned i = 0; i < 4; ++i) { 3516 if (LoQuad[i] > MaxQuad) { 3517 BestLoQuad = i; 3518 MaxQuad = LoQuad[i]; 3519 } 3520 } 3521 3522 int BestHiQuad = -1; 3523 MaxQuad = 1; 3524 for (unsigned i = 0; i < 4; ++i) { 3525 if (HiQuad[i] > MaxQuad) { 3526 BestHiQuad = i; 3527 MaxQuad = HiQuad[i]; 3528 } 3529 } 3530 3531 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3532 // of the two input vectors, shuffle them into one input vector so only a 3533 // single pshufb instruction is necessary. If There are more than 2 input 3534 // quads, disable the next transformation since it does not help SSSE3. 3535 bool V1Used = InputQuads[0] || InputQuads[1]; 3536 bool V2Used = InputQuads[2] || InputQuads[3]; 3537 if (TLI.getSubtarget()->hasSSSE3()) { 3538 if (InputQuads.count() == 2 && V1Used && V2Used) { 3539 BestLoQuad = InputQuads.find_first(); 3540 BestHiQuad = InputQuads.find_next(BestLoQuad); 3541 } 3542 if (InputQuads.count() > 2) { 3543 BestLoQuad = -1; 3544 BestHiQuad = -1; 3545 } 3546 } 3547 3548 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3549 // the shuffle mask. If a quad is scored as -1, that means that it contains 3550 // words from all 4 input quadwords. 3551 SDValue NewV; 3552 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3553 SmallVector<int, 8> MaskV; 3554 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 3555 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 3556 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 3557 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3558 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 3559 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3560 3561 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3562 // source words for the shuffle, to aid later transformations. 3563 bool AllWordsInNewV = true; 3564 bool InOrder[2] = { true, true }; 3565 for (unsigned i = 0; i != 8; ++i) { 3566 int idx = MaskVals[i]; 3567 if (idx != (int)i) 3568 InOrder[i/4] = false; 3569 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3570 continue; 3571 AllWordsInNewV = false; 3572 break; 3573 } 3574 3575 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 3576 if (AllWordsInNewV) { 3577 for (int i = 0; i != 8; ++i) { 3578 int idx = MaskVals[i]; 3579 if (idx < 0) 3580 continue; 3581 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 3582 if ((idx != i) && idx < 4) 3583 pshufhw = false; 3584 if ((idx != i) && idx > 3) 3585 pshuflw = false; 3586 } 3587 V1 = NewV; 3588 V2Used = false; 3589 BestLoQuad = 0; 3590 BestHiQuad = 1; 3591 } 3592 3593 // If we've eliminated the use of V2, and the new mask is a pshuflw or 3594 // pshufhw, that's as cheap as it gets. Return the new shuffle. 3595 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 3596 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 3597 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 3598 } 3599 } 3600 3601 // If we have SSSE3, and all words of the result are from 1 input vector, 3602 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 3603 // is present, fall back to case 4. 3604 if (TLI.getSubtarget()->hasSSSE3()) { 3605 SmallVector<SDValue,16> pshufbMask; 3606 3607 // If we have elements from both input vectors, set the high bit of the 3608 // shuffle mask element to zero out elements that come from V2 in the V1 3609 // mask, and elements that come from V1 in the V2 mask, so that the two 3610 // results can be OR'd together. 3611 bool TwoInputs = V1Used && V2Used; 3612 for (unsigned i = 0; i != 8; ++i) { 3613 int EltIdx = MaskVals[i] * 2; 3614 if (TwoInputs && (EltIdx >= 16)) { 3615 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3616 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3617 continue; 3618 } 3619 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3620 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 3621 } 3622 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 3623 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3624 DAG.getNode(ISD::BUILD_VECTOR, dl, 3625 MVT::v16i8, &pshufbMask[0], 16)); 3626 if (!TwoInputs) 3627 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3628 3629 // Calculate the shuffle mask for the second input, shuffle it, and 3630 // OR it with the first shuffled input. 3631 pshufbMask.clear(); 3632 for (unsigned i = 0; i != 8; ++i) { 3633 int EltIdx = MaskVals[i] * 2; 3634 if (EltIdx < 16) { 3635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3636 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3637 continue; 3638 } 3639 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3640 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 3641 } 3642 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 3643 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3644 DAG.getNode(ISD::BUILD_VECTOR, dl, 3645 MVT::v16i8, &pshufbMask[0], 16)); 3646 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3647 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3648 } 3649 3650 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 3651 // and update MaskVals with new element order. 3652 BitVector InOrder(8); 3653 if (BestLoQuad >= 0) { 3654 SmallVector<int, 8> MaskV; 3655 for (int i = 0; i != 4; ++i) { 3656 int idx = MaskVals[i]; 3657 if (idx < 0) { 3658 MaskV.push_back(-1); 3659 InOrder.set(i); 3660 } else if ((idx / 4) == BestLoQuad) { 3661 MaskV.push_back(idx & 3); 3662 InOrder.set(i); 3663 } else { 3664 MaskV.push_back(-1); 3665 } 3666 } 3667 for (unsigned i = 4; i != 8; ++i) 3668 MaskV.push_back(i); 3669 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 3670 &MaskV[0]); 3671 } 3672 3673 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 3674 // and update MaskVals with the new element order. 3675 if (BestHiQuad >= 0) { 3676 SmallVector<int, 8> MaskV; 3677 for (unsigned i = 0; i != 4; ++i) 3678 MaskV.push_back(i); 3679 for (unsigned i = 4; i != 8; ++i) { 3680 int idx = MaskVals[i]; 3681 if (idx < 0) { 3682 MaskV.push_back(-1); 3683 InOrder.set(i); 3684 } else if ((idx / 4) == BestHiQuad) { 3685 MaskV.push_back((idx & 3) + 4); 3686 InOrder.set(i); 3687 } else { 3688 MaskV.push_back(-1); 3689 } 3690 } 3691 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 3692 &MaskV[0]); 3693 } 3694 3695 // In case BestHi & BestLo were both -1, which means each quadword has a word 3696 // from each of the four input quadwords, calculate the InOrder bitvector now 3697 // before falling through to the insert/extract cleanup. 3698 if (BestLoQuad == -1 && BestHiQuad == -1) { 3699 NewV = V1; 3700 for (int i = 0; i != 8; ++i) 3701 if (MaskVals[i] < 0 || MaskVals[i] == i) 3702 InOrder.set(i); 3703 } 3704 3705 // The other elements are put in the right place using pextrw and pinsrw. 3706 for (unsigned i = 0; i != 8; ++i) { 3707 if (InOrder[i]) 3708 continue; 3709 int EltIdx = MaskVals[i]; 3710 if (EltIdx < 0) 3711 continue; 3712 SDValue ExtOp = (EltIdx < 8) 3713 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 3714 DAG.getIntPtrConstant(EltIdx)) 3715 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 3716 DAG.getIntPtrConstant(EltIdx - 8)); 3717 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 3718 DAG.getIntPtrConstant(i)); 3719 } 3720 return NewV; 3721} 3722 3723// v16i8 shuffles - Prefer shuffles in the following order: 3724// 1. [ssse3] 1 x pshufb 3725// 2. [ssse3] 2 x pshufb + 1 x por 3726// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 3727static 3728SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 3729 SelectionDAG &DAG, X86TargetLowering &TLI) { 3730 SDValue V1 = SVOp->getOperand(0); 3731 SDValue V2 = SVOp->getOperand(1); 3732 DebugLoc dl = SVOp->getDebugLoc(); 3733 SmallVector<int, 16> MaskVals; 3734 SVOp->getMask(MaskVals); 3735 3736 // If we have SSSE3, case 1 is generated when all result bytes come from 3737 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 3738 // present, fall back to case 3. 3739 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 3740 bool V1Only = true; 3741 bool V2Only = true; 3742 for (unsigned i = 0; i < 16; ++i) { 3743 int EltIdx = MaskVals[i]; 3744 if (EltIdx < 0) 3745 continue; 3746 if (EltIdx < 16) 3747 V2Only = false; 3748 else 3749 V1Only = false; 3750 } 3751 3752 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 3753 if (TLI.getSubtarget()->hasSSSE3()) { 3754 SmallVector<SDValue,16> pshufbMask; 3755 3756 // If all result elements are from one input vector, then only translate 3757 // undef mask values to 0x80 (zero out result) in the pshufb mask. 3758 // 3759 // Otherwise, we have elements from both input vectors, and must zero out 3760 // elements that come from V2 in the first mask, and V1 in the second mask 3761 // so that we can OR them together. 3762 bool TwoInputs = !(V1Only || V2Only); 3763 for (unsigned i = 0; i != 16; ++i) { 3764 int EltIdx = MaskVals[i]; 3765 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 3766 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3767 continue; 3768 } 3769 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 3770 } 3771 // If all the elements are from V2, assign it to V1 and return after 3772 // building the first pshufb. 3773 if (V2Only) 3774 V1 = V2; 3775 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 3776 DAG.getNode(ISD::BUILD_VECTOR, dl, 3777 MVT::v16i8, &pshufbMask[0], 16)); 3778 if (!TwoInputs) 3779 return V1; 3780 3781 // Calculate the shuffle mask for the second input, shuffle it, and 3782 // OR it with the first shuffled input. 3783 pshufbMask.clear(); 3784 for (unsigned i = 0; i != 16; ++i) { 3785 int EltIdx = MaskVals[i]; 3786 if (EltIdx < 16) { 3787 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 3788 continue; 3789 } 3790 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 3791 } 3792 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 3793 DAG.getNode(ISD::BUILD_VECTOR, dl, 3794 MVT::v16i8, &pshufbMask[0], 16)); 3795 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 3796 } 3797 3798 // No SSSE3 - Calculate in place words and then fix all out of place words 3799 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 3800 // the 16 different words that comprise the two doublequadword input vectors. 3801 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 3802 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 3803 SDValue NewV = V2Only ? V2 : V1; 3804 for (int i = 0; i != 8; ++i) { 3805 int Elt0 = MaskVals[i*2]; 3806 int Elt1 = MaskVals[i*2+1]; 3807 3808 // This word of the result is all undef, skip it. 3809 if (Elt0 < 0 && Elt1 < 0) 3810 continue; 3811 3812 // This word of the result is already in the correct place, skip it. 3813 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 3814 continue; 3815 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 3816 continue; 3817 3818 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 3819 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 3820 SDValue InsElt; 3821 3822 // If Elt0 and Elt1 are defined, are consecutive, and can be load 3823 // using a single extract together, load it and store it. 3824 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 3825 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3826 DAG.getIntPtrConstant(Elt1 / 2)); 3827 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3828 DAG.getIntPtrConstant(i)); 3829 continue; 3830 } 3831 3832 // If Elt1 is defined, extract it from the appropriate source. If the 3833 // source byte is not also odd, shift the extracted word left 8 bits 3834 // otherwise clear the bottom 8 bits if we need to do an or. 3835 if (Elt1 >= 0) { 3836 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 3837 DAG.getIntPtrConstant(Elt1 / 2)); 3838 if ((Elt1 & 1) == 0) 3839 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 3840 DAG.getConstant(8, TLI.getShiftAmountTy())); 3841 else if (Elt0 >= 0) 3842 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 3843 DAG.getConstant(0xFF00, MVT::i16)); 3844 } 3845 // If Elt0 is defined, extract it from the appropriate source. If the 3846 // source byte is not also even, shift the extracted word right 8 bits. If 3847 // Elt1 was also defined, OR the extracted values together before 3848 // inserting them in the result. 3849 if (Elt0 >= 0) { 3850 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 3851 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 3852 if ((Elt0 & 1) != 0) 3853 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 3854 DAG.getConstant(8, TLI.getShiftAmountTy())); 3855 else if (Elt1 >= 0) 3856 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 3857 DAG.getConstant(0x00FF, MVT::i16)); 3858 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 3859 : InsElt0; 3860 } 3861 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 3862 DAG.getIntPtrConstant(i)); 3863 } 3864 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 3865} 3866 3867/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 3868/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 3869/// done when every pair / quad of shuffle mask elements point to elements in 3870/// the right sequence. e.g. 3871/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 3872static 3873SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 3874 SelectionDAG &DAG, 3875 TargetLowering &TLI, DebugLoc dl) { 3876 EVT VT = SVOp->getValueType(0); 3877 SDValue V1 = SVOp->getOperand(0); 3878 SDValue V2 = SVOp->getOperand(1); 3879 unsigned NumElems = VT.getVectorNumElements(); 3880 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 3881 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 3882 EVT MaskEltVT = MaskVT.getVectorElementType(); 3883 EVT NewVT = MaskVT; 3884 switch (VT.getSimpleVT().SimpleTy) { 3885 default: assert(false && "Unexpected!"); 3886 case MVT::v4f32: NewVT = MVT::v2f64; break; 3887 case MVT::v4i32: NewVT = MVT::v2i64; break; 3888 case MVT::v8i16: NewVT = MVT::v4i32; break; 3889 case MVT::v16i8: NewVT = MVT::v4i32; break; 3890 } 3891 3892 if (NewWidth == 2) { 3893 if (VT.isInteger()) 3894 NewVT = MVT::v2i64; 3895 else 3896 NewVT = MVT::v2f64; 3897 } 3898 int Scale = NumElems / NewWidth; 3899 SmallVector<int, 8> MaskVec; 3900 for (unsigned i = 0; i < NumElems; i += Scale) { 3901 int StartIdx = -1; 3902 for (int j = 0; j < Scale; ++j) { 3903 int EltIdx = SVOp->getMaskElt(i+j); 3904 if (EltIdx < 0) 3905 continue; 3906 if (StartIdx == -1) 3907 StartIdx = EltIdx - (EltIdx % Scale); 3908 if (EltIdx != StartIdx + j) 3909 return SDValue(); 3910 } 3911 if (StartIdx == -1) 3912 MaskVec.push_back(-1); 3913 else 3914 MaskVec.push_back(StartIdx / Scale); 3915 } 3916 3917 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 3918 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 3919 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 3920} 3921 3922/// getVZextMovL - Return a zero-extending vector move low node. 3923/// 3924static SDValue getVZextMovL(EVT VT, EVT OpVT, 3925 SDValue SrcOp, SelectionDAG &DAG, 3926 const X86Subtarget *Subtarget, DebugLoc dl) { 3927 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 3928 LoadSDNode *LD = NULL; 3929 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 3930 LD = dyn_cast<LoadSDNode>(SrcOp); 3931 if (!LD) { 3932 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 3933 // instead. 3934 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 3935 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 3936 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 3937 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 3938 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 3939 // PR2108 3940 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 3941 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3942 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 3943 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3944 OpVT, 3945 SrcOp.getOperand(0) 3946 .getOperand(0)))); 3947 } 3948 } 3949 } 3950 3951 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3952 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 3953 DAG.getNode(ISD::BIT_CONVERT, dl, 3954 OpVT, SrcOp))); 3955} 3956 3957/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 3958/// shuffles. 3959static SDValue 3960LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3961 SDValue V1 = SVOp->getOperand(0); 3962 SDValue V2 = SVOp->getOperand(1); 3963 DebugLoc dl = SVOp->getDebugLoc(); 3964 EVT VT = SVOp->getValueType(0); 3965 3966 SmallVector<std::pair<int, int>, 8> Locs; 3967 Locs.resize(4); 3968 SmallVector<int, 8> Mask1(4U, -1); 3969 SmallVector<int, 8> PermMask; 3970 SVOp->getMask(PermMask); 3971 3972 unsigned NumHi = 0; 3973 unsigned NumLo = 0; 3974 for (unsigned i = 0; i != 4; ++i) { 3975 int Idx = PermMask[i]; 3976 if (Idx < 0) { 3977 Locs[i] = std::make_pair(-1, -1); 3978 } else { 3979 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 3980 if (Idx < 4) { 3981 Locs[i] = std::make_pair(0, NumLo); 3982 Mask1[NumLo] = Idx; 3983 NumLo++; 3984 } else { 3985 Locs[i] = std::make_pair(1, NumHi); 3986 if (2+NumHi < 4) 3987 Mask1[2+NumHi] = Idx; 3988 NumHi++; 3989 } 3990 } 3991 } 3992 3993 if (NumLo <= 2 && NumHi <= 2) { 3994 // If no more than two elements come from either vector. This can be 3995 // implemented with two shuffles. First shuffle gather the elements. 3996 // The second shuffle, which takes the first shuffle as both of its 3997 // vector operands, put the elements into the right order. 3998 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 3999 4000 SmallVector<int, 8> Mask2(4U, -1); 4001 4002 for (unsigned i = 0; i != 4; ++i) { 4003 if (Locs[i].first == -1) 4004 continue; 4005 else { 4006 unsigned Idx = (i < 2) ? 0 : 4; 4007 Idx += Locs[i].first * 2 + Locs[i].second; 4008 Mask2[i] = Idx; 4009 } 4010 } 4011 4012 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4013 } else if (NumLo == 3 || NumHi == 3) { 4014 // Otherwise, we must have three elements from one vector, call it X, and 4015 // one element from the other, call it Y. First, use a shufps to build an 4016 // intermediate vector with the one element from Y and the element from X 4017 // that will be in the same half in the final destination (the indexes don't 4018 // matter). Then, use a shufps to build the final vector, taking the half 4019 // containing the element from Y from the intermediate, and the other half 4020 // from X. 4021 if (NumHi == 3) { 4022 // Normalize it so the 3 elements come from V1. 4023 CommuteVectorShuffleMask(PermMask, VT); 4024 std::swap(V1, V2); 4025 } 4026 4027 // Find the element from V2. 4028 unsigned HiIndex; 4029 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4030 int Val = PermMask[HiIndex]; 4031 if (Val < 0) 4032 continue; 4033 if (Val >= 4) 4034 break; 4035 } 4036 4037 Mask1[0] = PermMask[HiIndex]; 4038 Mask1[1] = -1; 4039 Mask1[2] = PermMask[HiIndex^1]; 4040 Mask1[3] = -1; 4041 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4042 4043 if (HiIndex >= 2) { 4044 Mask1[0] = PermMask[0]; 4045 Mask1[1] = PermMask[1]; 4046 Mask1[2] = HiIndex & 1 ? 6 : 4; 4047 Mask1[3] = HiIndex & 1 ? 4 : 6; 4048 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4049 } else { 4050 Mask1[0] = HiIndex & 1 ? 2 : 0; 4051 Mask1[1] = HiIndex & 1 ? 0 : 2; 4052 Mask1[2] = PermMask[2]; 4053 Mask1[3] = PermMask[3]; 4054 if (Mask1[2] >= 0) 4055 Mask1[2] += 4; 4056 if (Mask1[3] >= 0) 4057 Mask1[3] += 4; 4058 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4059 } 4060 } 4061 4062 // Break it into (shuffle shuffle_hi, shuffle_lo). 4063 Locs.clear(); 4064 SmallVector<int,8> LoMask(4U, -1); 4065 SmallVector<int,8> HiMask(4U, -1); 4066 4067 SmallVector<int,8> *MaskPtr = &LoMask; 4068 unsigned MaskIdx = 0; 4069 unsigned LoIdx = 0; 4070 unsigned HiIdx = 2; 4071 for (unsigned i = 0; i != 4; ++i) { 4072 if (i == 2) { 4073 MaskPtr = &HiMask; 4074 MaskIdx = 1; 4075 LoIdx = 0; 4076 HiIdx = 2; 4077 } 4078 int Idx = PermMask[i]; 4079 if (Idx < 0) { 4080 Locs[i] = std::make_pair(-1, -1); 4081 } else if (Idx < 4) { 4082 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4083 (*MaskPtr)[LoIdx] = Idx; 4084 LoIdx++; 4085 } else { 4086 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4087 (*MaskPtr)[HiIdx] = Idx; 4088 HiIdx++; 4089 } 4090 } 4091 4092 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4093 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4094 SmallVector<int, 8> MaskOps; 4095 for (unsigned i = 0; i != 4; ++i) { 4096 if (Locs[i].first == -1) { 4097 MaskOps.push_back(-1); 4098 } else { 4099 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4100 MaskOps.push_back(Idx); 4101 } 4102 } 4103 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4104} 4105 4106SDValue 4107X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4109 SDValue V1 = Op.getOperand(0); 4110 SDValue V2 = Op.getOperand(1); 4111 EVT VT = Op.getValueType(); 4112 DebugLoc dl = Op.getDebugLoc(); 4113 unsigned NumElems = VT.getVectorNumElements(); 4114 bool isMMX = VT.getSizeInBits() == 64; 4115 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4116 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4117 bool V1IsSplat = false; 4118 bool V2IsSplat = false; 4119 4120 if (isZeroShuffle(SVOp)) 4121 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4122 4123 // Promote splats to v4f32. 4124 if (SVOp->isSplat()) { 4125 if (isMMX || NumElems < 4) 4126 return Op; 4127 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4128 } 4129 4130 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4131 // do it! 4132 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4133 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4134 if (NewOp.getNode()) 4135 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4136 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4137 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4138 // FIXME: Figure out a cleaner way to do this. 4139 // Try to make use of movq to zero out the top part. 4140 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4141 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4142 if (NewOp.getNode()) { 4143 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4144 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4145 DAG, Subtarget, dl); 4146 } 4147 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4148 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4149 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4150 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4151 DAG, Subtarget, dl); 4152 } 4153 } 4154 4155 if (X86::isPSHUFDMask(SVOp)) 4156 return Op; 4157 4158 // Check if this can be converted into a logical shift. 4159 bool isLeft = false; 4160 unsigned ShAmt = 0; 4161 SDValue ShVal; 4162 bool isShift = getSubtarget()->hasSSE2() && 4163 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4164 if (isShift && ShVal.hasOneUse()) { 4165 // If the shifted value has multiple uses, it may be cheaper to use 4166 // v_set0 + movlhps or movhlps, etc. 4167 EVT EVT = VT.getVectorElementType(); 4168 ShAmt *= EVT.getSizeInBits(); 4169 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4170 } 4171 4172 if (X86::isMOVLMask(SVOp)) { 4173 if (V1IsUndef) 4174 return V2; 4175 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4176 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4177 if (!isMMX) 4178 return Op; 4179 } 4180 4181 // FIXME: fold these into legal mask. 4182 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4183 X86::isMOVSLDUPMask(SVOp) || 4184 X86::isMOVHLPSMask(SVOp) || 4185 X86::isMOVHPMask(SVOp) || 4186 X86::isMOVLPMask(SVOp))) 4187 return Op; 4188 4189 if (ShouldXformToMOVHLPS(SVOp) || 4190 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4191 return CommuteVectorShuffle(SVOp, DAG); 4192 4193 if (isShift) { 4194 // No better options. Use a vshl / vsrl. 4195 EVT EVT = VT.getVectorElementType(); 4196 ShAmt *= EVT.getSizeInBits(); 4197 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4198 } 4199 4200 bool Commuted = false; 4201 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4202 // 1,1,1,1 -> v8i16 though. 4203 V1IsSplat = isSplatVector(V1.getNode()); 4204 V2IsSplat = isSplatVector(V2.getNode()); 4205 4206 // Canonicalize the splat or undef, if present, to be on the RHS. 4207 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4208 Op = CommuteVectorShuffle(SVOp, DAG); 4209 SVOp = cast<ShuffleVectorSDNode>(Op); 4210 V1 = SVOp->getOperand(0); 4211 V2 = SVOp->getOperand(1); 4212 std::swap(V1IsSplat, V2IsSplat); 4213 std::swap(V1IsUndef, V2IsUndef); 4214 Commuted = true; 4215 } 4216 4217 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4218 // Shuffling low element of v1 into undef, just return v1. 4219 if (V2IsUndef) 4220 return V1; 4221 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4222 // the instruction selector will not match, so get a canonical MOVL with 4223 // swapped operands to undo the commute. 4224 return getMOVL(DAG, dl, VT, V2, V1); 4225 } 4226 4227 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4228 X86::isUNPCKH_v_undef_Mask(SVOp) || 4229 X86::isUNPCKLMask(SVOp) || 4230 X86::isUNPCKHMask(SVOp)) 4231 return Op; 4232 4233 if (V2IsSplat) { 4234 // Normalize mask so all entries that point to V2 points to its first 4235 // element then try to match unpck{h|l} again. If match, return a 4236 // new vector_shuffle with the corrected mask. 4237 SDValue NewMask = NormalizeMask(SVOp, DAG); 4238 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4239 if (NSVOp != SVOp) { 4240 if (X86::isUNPCKLMask(NSVOp, true)) { 4241 return NewMask; 4242 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4243 return NewMask; 4244 } 4245 } 4246 } 4247 4248 if (Commuted) { 4249 // Commute is back and try unpck* again. 4250 // FIXME: this seems wrong. 4251 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4252 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4253 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4254 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4255 X86::isUNPCKLMask(NewSVOp) || 4256 X86::isUNPCKHMask(NewSVOp)) 4257 return NewOp; 4258 } 4259 4260 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4261 4262 // Normalize the node to match x86 shuffle ops if needed 4263 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4264 return CommuteVectorShuffle(SVOp, DAG); 4265 4266 // Check for legal shuffle and return? 4267 SmallVector<int, 16> PermMask; 4268 SVOp->getMask(PermMask); 4269 if (isShuffleMaskLegal(PermMask, VT)) 4270 return Op; 4271 4272 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4273 if (VT == MVT::v8i16) { 4274 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4275 if (NewOp.getNode()) 4276 return NewOp; 4277 } 4278 4279 if (VT == MVT::v16i8) { 4280 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4281 if (NewOp.getNode()) 4282 return NewOp; 4283 } 4284 4285 // Handle all 4 wide cases with a number of shuffles except for MMX. 4286 if (NumElems == 4 && !isMMX) 4287 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4288 4289 return SDValue(); 4290} 4291 4292SDValue 4293X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4294 SelectionDAG &DAG) { 4295 EVT VT = Op.getValueType(); 4296 DebugLoc dl = Op.getDebugLoc(); 4297 if (VT.getSizeInBits() == 8) { 4298 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4299 Op.getOperand(0), Op.getOperand(1)); 4300 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4301 DAG.getValueType(VT)); 4302 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4303 } else if (VT.getSizeInBits() == 16) { 4304 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4305 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4306 if (Idx == 0) 4307 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4308 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4309 DAG.getNode(ISD::BIT_CONVERT, dl, 4310 MVT::v4i32, 4311 Op.getOperand(0)), 4312 Op.getOperand(1))); 4313 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4314 Op.getOperand(0), Op.getOperand(1)); 4315 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4316 DAG.getValueType(VT)); 4317 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4318 } else if (VT == MVT::f32) { 4319 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4320 // the result back to FR32 register. It's only worth matching if the 4321 // result has a single use which is a store or a bitcast to i32. And in 4322 // the case of a store, it's not worth it if the index is a constant 0, 4323 // because a MOVSSmr can be used instead, which is smaller and faster. 4324 if (!Op.hasOneUse()) 4325 return SDValue(); 4326 SDNode *User = *Op.getNode()->use_begin(); 4327 if ((User->getOpcode() != ISD::STORE || 4328 (isa<ConstantSDNode>(Op.getOperand(1)) && 4329 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4330 (User->getOpcode() != ISD::BIT_CONVERT || 4331 User->getValueType(0) != MVT::i32)) 4332 return SDValue(); 4333 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4334 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4335 Op.getOperand(0)), 4336 Op.getOperand(1)); 4337 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4338 } else if (VT == MVT::i32) { 4339 // ExtractPS works with constant index. 4340 if (isa<ConstantSDNode>(Op.getOperand(1))) 4341 return Op; 4342 } 4343 return SDValue(); 4344} 4345 4346 4347SDValue 4348X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4349 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4350 return SDValue(); 4351 4352 if (Subtarget->hasSSE41()) { 4353 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4354 if (Res.getNode()) 4355 return Res; 4356 } 4357 4358 EVT VT = Op.getValueType(); 4359 DebugLoc dl = Op.getDebugLoc(); 4360 // TODO: handle v16i8. 4361 if (VT.getSizeInBits() == 16) { 4362 SDValue Vec = Op.getOperand(0); 4363 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4364 if (Idx == 0) 4365 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4366 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4367 DAG.getNode(ISD::BIT_CONVERT, dl, 4368 MVT::v4i32, Vec), 4369 Op.getOperand(1))); 4370 // Transform it so it match pextrw which produces a 32-bit result. 4371 EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1); 4372 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT, 4373 Op.getOperand(0), Op.getOperand(1)); 4374 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract, 4375 DAG.getValueType(VT)); 4376 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4377 } else if (VT.getSizeInBits() == 32) { 4378 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4379 if (Idx == 0) 4380 return Op; 4381 4382 // SHUFPS the element to the lowest double word, then movss. 4383 int Mask[4] = { Idx, -1, -1, -1 }; 4384 EVT VVT = Op.getOperand(0).getValueType(); 4385 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4386 DAG.getUNDEF(VVT), Mask); 4387 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4388 DAG.getIntPtrConstant(0)); 4389 } else if (VT.getSizeInBits() == 64) { 4390 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4391 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4392 // to match extract_elt for f64. 4393 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4394 if (Idx == 0) 4395 return Op; 4396 4397 // UNPCKHPD the element to the lowest double word, then movsd. 4398 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4399 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4400 int Mask[2] = { 1, -1 }; 4401 EVT VVT = Op.getOperand(0).getValueType(); 4402 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4403 DAG.getUNDEF(VVT), Mask); 4404 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4405 DAG.getIntPtrConstant(0)); 4406 } 4407 4408 return SDValue(); 4409} 4410 4411SDValue 4412X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4413 EVT VT = Op.getValueType(); 4414 EVT EVT = VT.getVectorElementType(); 4415 DebugLoc dl = Op.getDebugLoc(); 4416 4417 SDValue N0 = Op.getOperand(0); 4418 SDValue N1 = Op.getOperand(1); 4419 SDValue N2 = Op.getOperand(2); 4420 4421 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) && 4422 isa<ConstantSDNode>(N2)) { 4423 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4424 : X86ISD::PINSRW; 4425 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4426 // argument. 4427 if (N1.getValueType() != MVT::i32) 4428 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4429 if (N2.getValueType() != MVT::i32) 4430 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4431 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4432 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4433 // Bits [7:6] of the constant are the source select. This will always be 4434 // zero here. The DAG Combiner may combine an extract_elt index into these 4435 // bits. For example (insert (extract, 3), 2) could be matched by putting 4436 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4437 // Bits [5:4] of the constant are the destination select. This is the 4438 // value of the incoming immediate. 4439 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4440 // combine either bitwise AND or insert of float 0.0 to set these bits. 4441 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4442 // Create this as a scalar to vector.. 4443 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4444 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4445 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4446 // PINSR* works with constant index. 4447 return Op; 4448 } 4449 return SDValue(); 4450} 4451 4452SDValue 4453X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4454 EVT VT = Op.getValueType(); 4455 EVT EVT = VT.getVectorElementType(); 4456 4457 if (Subtarget->hasSSE41()) 4458 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4459 4460 if (EVT == MVT::i8) 4461 return SDValue(); 4462 4463 DebugLoc dl = Op.getDebugLoc(); 4464 SDValue N0 = Op.getOperand(0); 4465 SDValue N1 = Op.getOperand(1); 4466 SDValue N2 = Op.getOperand(2); 4467 4468 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4469 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4470 // as its second argument. 4471 if (N1.getValueType() != MVT::i32) 4472 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4473 if (N2.getValueType() != MVT::i32) 4474 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4475 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 4476 } 4477 return SDValue(); 4478} 4479 4480SDValue 4481X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4482 DebugLoc dl = Op.getDebugLoc(); 4483 if (Op.getValueType() == MVT::v2f32) 4484 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4485 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4486 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4487 Op.getOperand(0)))); 4488 4489 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 4490 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 4491 4492 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4493 EVT VT = MVT::v2i32; 4494 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4495 default: break; 4496 case MVT::v16i8: 4497 case MVT::v8i16: 4498 VT = MVT::v4i32; 4499 break; 4500 } 4501 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4502 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4503} 4504 4505// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4506// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4507// one of the above mentioned nodes. It has to be wrapped because otherwise 4508// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4509// be used to form addressing mode. These wrapped nodes will be selected 4510// into MOV32ri. 4511SDValue 4512X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4513 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4514 4515 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4516 // global base reg. 4517 unsigned char OpFlag = 0; 4518 unsigned WrapperKind = X86ISD::Wrapper; 4519 CodeModel::Model M = getTargetMachine().getCodeModel(); 4520 4521 if (Subtarget->isPICStyleRIPRel() && 4522 (M == CodeModel::Small || M == CodeModel::Kernel)) 4523 WrapperKind = X86ISD::WrapperRIP; 4524 else if (Subtarget->isPICStyleGOT()) 4525 OpFlag = X86II::MO_GOTOFF; 4526 else if (Subtarget->isPICStyleStubPIC()) 4527 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4528 4529 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 4530 CP->getAlignment(), 4531 CP->getOffset(), OpFlag); 4532 DebugLoc DL = CP->getDebugLoc(); 4533 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4534 // With PIC, the address is actually $g + Offset. 4535 if (OpFlag) { 4536 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4537 DAG.getNode(X86ISD::GlobalBaseReg, 4538 DebugLoc::getUnknownLoc(), getPointerTy()), 4539 Result); 4540 } 4541 4542 return Result; 4543} 4544 4545SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4546 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4547 4548 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4549 // global base reg. 4550 unsigned char OpFlag = 0; 4551 unsigned WrapperKind = X86ISD::Wrapper; 4552 CodeModel::Model M = getTargetMachine().getCodeModel(); 4553 4554 if (Subtarget->isPICStyleRIPRel() && 4555 (M == CodeModel::Small || M == CodeModel::Kernel)) 4556 WrapperKind = X86ISD::WrapperRIP; 4557 else if (Subtarget->isPICStyleGOT()) 4558 OpFlag = X86II::MO_GOTOFF; 4559 else if (Subtarget->isPICStyleStubPIC()) 4560 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4561 4562 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 4563 OpFlag); 4564 DebugLoc DL = JT->getDebugLoc(); 4565 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4566 4567 // With PIC, the address is actually $g + Offset. 4568 if (OpFlag) { 4569 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4570 DAG.getNode(X86ISD::GlobalBaseReg, 4571 DebugLoc::getUnknownLoc(), getPointerTy()), 4572 Result); 4573 } 4574 4575 return Result; 4576} 4577 4578SDValue 4579X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4580 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4581 4582 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4583 // global base reg. 4584 unsigned char OpFlag = 0; 4585 unsigned WrapperKind = X86ISD::Wrapper; 4586 CodeModel::Model M = getTargetMachine().getCodeModel(); 4587 4588 if (Subtarget->isPICStyleRIPRel() && 4589 (M == CodeModel::Small || M == CodeModel::Kernel)) 4590 WrapperKind = X86ISD::WrapperRIP; 4591 else if (Subtarget->isPICStyleGOT()) 4592 OpFlag = X86II::MO_GOTOFF; 4593 else if (Subtarget->isPICStyleStubPIC()) 4594 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4595 4596 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 4597 4598 DebugLoc DL = Op.getDebugLoc(); 4599 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4600 4601 4602 // With PIC, the address is actually $g + Offset. 4603 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4604 !Subtarget->is64Bit()) { 4605 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4606 DAG.getNode(X86ISD::GlobalBaseReg, 4607 DebugLoc::getUnknownLoc(), 4608 getPointerTy()), 4609 Result); 4610 } 4611 4612 return Result; 4613} 4614 4615SDValue 4616X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 4617 int64_t Offset, 4618 SelectionDAG &DAG) const { 4619 // Create the TargetGlobalAddress node, folding in the constant 4620 // offset if it is legal. 4621 unsigned char OpFlags = 4622 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 4623 CodeModel::Model M = getTargetMachine().getCodeModel(); 4624 SDValue Result; 4625 if (OpFlags == X86II::MO_NO_FLAG && 4626 X86::isOffsetSuitableForCodeModel(Offset, M)) { 4627 // A direct static reference to a global. 4628 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 4629 Offset = 0; 4630 } else { 4631 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 4632 } 4633 4634 if (Subtarget->isPICStyleRIPRel() && 4635 (M == CodeModel::Small || M == CodeModel::Kernel)) 4636 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 4637 else 4638 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 4639 4640 // With PIC, the address is actually $g + Offset. 4641 if (isGlobalRelativeToPICBase(OpFlags)) { 4642 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 4643 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 4644 Result); 4645 } 4646 4647 // For globals that require a load from a stub to get the address, emit the 4648 // load. 4649 if (isGlobalStubReference(OpFlags)) 4650 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 4651 PseudoSourceValue::getGOT(), 0); 4652 4653 // If there was a non-zero offset that we didn't fold, create an explicit 4654 // addition for it. 4655 if (Offset != 0) 4656 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 4657 DAG.getConstant(Offset, getPointerTy())); 4658 4659 return Result; 4660} 4661 4662SDValue 4663X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 4664 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 4665 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 4666 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 4667} 4668 4669static SDValue 4670GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 4671 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 4672 unsigned char OperandFlags) { 4673 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 4674 DebugLoc dl = GA->getDebugLoc(); 4675 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 4676 GA->getValueType(0), 4677 GA->getOffset(), 4678 OperandFlags); 4679 if (InFlag) { 4680 SDValue Ops[] = { Chain, TGA, *InFlag }; 4681 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 4682 } else { 4683 SDValue Ops[] = { Chain, TGA }; 4684 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 4685 } 4686 SDValue Flag = Chain.getValue(1); 4687 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 4688} 4689 4690// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 4691static SDValue 4692LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4693 const EVT PtrVT) { 4694 SDValue InFlag; 4695 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 4696 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 4697 DAG.getNode(X86ISD::GlobalBaseReg, 4698 DebugLoc::getUnknownLoc(), 4699 PtrVT), InFlag); 4700 InFlag = Chain.getValue(1); 4701 4702 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 4703} 4704 4705// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 4706static SDValue 4707LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4708 const EVT PtrVT) { 4709 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 4710 X86::RAX, X86II::MO_TLSGD); 4711} 4712 4713// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 4714// "local exec" model. 4715static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 4716 const EVT PtrVT, TLSModel::Model model, 4717 bool is64Bit) { 4718 DebugLoc dl = GA->getDebugLoc(); 4719 // Get the Thread Pointer 4720 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 4721 DebugLoc::getUnknownLoc(), PtrVT, 4722 DAG.getRegister(is64Bit? X86::FS : X86::GS, 4723 MVT::i32)); 4724 4725 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 4726 NULL, 0); 4727 4728 unsigned char OperandFlags = 0; 4729 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 4730 // initialexec. 4731 unsigned WrapperKind = X86ISD::Wrapper; 4732 if (model == TLSModel::LocalExec) { 4733 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 4734 } else if (is64Bit) { 4735 assert(model == TLSModel::InitialExec); 4736 OperandFlags = X86II::MO_GOTTPOFF; 4737 WrapperKind = X86ISD::WrapperRIP; 4738 } else { 4739 assert(model == TLSModel::InitialExec); 4740 OperandFlags = X86II::MO_INDNTPOFF; 4741 } 4742 4743 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 4744 // exec) 4745 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 4746 GA->getOffset(), OperandFlags); 4747 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 4748 4749 if (model == TLSModel::InitialExec) 4750 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 4751 PseudoSourceValue::getGOT(), 0); 4752 4753 // The address of the thread local variable is the add of the thread 4754 // pointer with the offset of the variable. 4755 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 4756} 4757 4758SDValue 4759X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 4760 // TODO: implement the "local dynamic" model 4761 // TODO: implement the "initial exec"model for pic executables 4762 assert(Subtarget->isTargetELF() && 4763 "TLS not implemented for non-ELF targets"); 4764 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 4765 const GlobalValue *GV = GA->getGlobal(); 4766 4767 // If GV is an alias then use the aliasee for determining 4768 // thread-localness. 4769 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 4770 GV = GA->resolveAliasedGlobal(false); 4771 4772 TLSModel::Model model = getTLSModel(GV, 4773 getTargetMachine().getRelocationModel()); 4774 4775 switch (model) { 4776 case TLSModel::GeneralDynamic: 4777 case TLSModel::LocalDynamic: // not implemented 4778 if (Subtarget->is64Bit()) 4779 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 4780 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 4781 4782 case TLSModel::InitialExec: 4783 case TLSModel::LocalExec: 4784 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 4785 Subtarget->is64Bit()); 4786 } 4787 4788 llvm_unreachable("Unreachable"); 4789 return SDValue(); 4790} 4791 4792 4793/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 4794/// take a 2 x i32 value to shift plus a shift amount. 4795SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 4796 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 4797 EVT VT = Op.getValueType(); 4798 unsigned VTBits = VT.getSizeInBits(); 4799 DebugLoc dl = Op.getDebugLoc(); 4800 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 4801 SDValue ShOpLo = Op.getOperand(0); 4802 SDValue ShOpHi = Op.getOperand(1); 4803 SDValue ShAmt = Op.getOperand(2); 4804 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 4805 DAG.getConstant(VTBits - 1, MVT::i8)) 4806 : DAG.getConstant(0, VT); 4807 4808 SDValue Tmp2, Tmp3; 4809 if (Op.getOpcode() == ISD::SHL_PARTS) { 4810 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 4811 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 4812 } else { 4813 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 4814 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 4815 } 4816 4817 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 4818 DAG.getConstant(VTBits, MVT::i8)); 4819 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, 4820 AndNode, DAG.getConstant(0, MVT::i8)); 4821 4822 SDValue Hi, Lo; 4823 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 4824 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 4825 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 4826 4827 if (Op.getOpcode() == ISD::SHL_PARTS) { 4828 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4829 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4830 } else { 4831 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 4832 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 4833 } 4834 4835 SDValue Ops[2] = { Lo, Hi }; 4836 return DAG.getMergeValues(Ops, 2, dl); 4837} 4838 4839SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 4840 EVT SrcVT = Op.getOperand(0).getValueType(); 4841 4842 if (SrcVT.isVector()) { 4843 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 4844 return Op; 4845 } 4846 return SDValue(); 4847 } 4848 4849 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 4850 "Unknown SINT_TO_FP to lower!"); 4851 4852 // These are really Legal; return the operand so the caller accepts it as 4853 // Legal. 4854 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 4855 return Op; 4856 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 4857 Subtarget->is64Bit()) { 4858 return Op; 4859 } 4860 4861 DebugLoc dl = Op.getDebugLoc(); 4862 unsigned Size = SrcVT.getSizeInBits()/8; 4863 MachineFunction &MF = DAG.getMachineFunction(); 4864 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); 4865 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4866 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 4867 StackSlot, 4868 PseudoSourceValue::getFixedStack(SSFI), 0); 4869 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 4870} 4871 4872SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 4873 SDValue StackSlot, 4874 SelectionDAG &DAG) { 4875 // Build the FILD 4876 DebugLoc dl = Op.getDebugLoc(); 4877 SDVTList Tys; 4878 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 4879 if (useSSE) 4880 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 4881 else 4882 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 4883 SmallVector<SDValue, 8> Ops; 4884 Ops.push_back(Chain); 4885 Ops.push_back(StackSlot); 4886 Ops.push_back(DAG.getValueType(SrcVT)); 4887 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 4888 Tys, &Ops[0], Ops.size()); 4889 4890 if (useSSE) { 4891 Chain = Result.getValue(1); 4892 SDValue InFlag = Result.getValue(2); 4893 4894 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 4895 // shouldn't be necessary except that RFP cannot be live across 4896 // multiple blocks. When stackifier is fixed, they can be uncoupled. 4897 MachineFunction &MF = DAG.getMachineFunction(); 4898 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 4899 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 4900 Tys = DAG.getVTList(MVT::Other); 4901 SmallVector<SDValue, 8> Ops; 4902 Ops.push_back(Chain); 4903 Ops.push_back(Result); 4904 Ops.push_back(StackSlot); 4905 Ops.push_back(DAG.getValueType(Op.getValueType())); 4906 Ops.push_back(InFlag); 4907 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size()); 4908 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 4909 PseudoSourceValue::getFixedStack(SSFI), 0); 4910 } 4911 4912 return Result; 4913} 4914 4915// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 4916SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 4917 // This algorithm is not obvious. Here it is in C code, more or less: 4918 /* 4919 double uint64_to_double( uint32_t hi, uint32_t lo ) { 4920 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 4921 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 4922 4923 // Copy ints to xmm registers. 4924 __m128i xh = _mm_cvtsi32_si128( hi ); 4925 __m128i xl = _mm_cvtsi32_si128( lo ); 4926 4927 // Combine into low half of a single xmm register. 4928 __m128i x = _mm_unpacklo_epi32( xh, xl ); 4929 __m128d d; 4930 double sd; 4931 4932 // Merge in appropriate exponents to give the integer bits the right 4933 // magnitude. 4934 x = _mm_unpacklo_epi32( x, exp ); 4935 4936 // Subtract away the biases to deal with the IEEE-754 double precision 4937 // implicit 1. 4938 d = _mm_sub_pd( (__m128d) x, bias ); 4939 4940 // All conversions up to here are exact. The correctly rounded result is 4941 // calculated using the current rounding mode using the following 4942 // horizontal add. 4943 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 4944 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 4945 // store doesn't really need to be here (except 4946 // maybe to zero the other double) 4947 return sd; 4948 } 4949 */ 4950 4951 DebugLoc dl = Op.getDebugLoc(); 4952 LLVMContext *Context = DAG.getContext(); 4953 4954 // Build some magic constants. 4955 std::vector<Constant*> CV0; 4956 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 4957 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 4958 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 4959 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 4960 Constant *C0 = ConstantVector::get(CV0); 4961 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 4962 4963 std::vector<Constant*> CV1; 4964 CV1.push_back( 4965 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 4966 CV1.push_back( 4967 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 4968 Constant *C1 = ConstantVector::get(CV1); 4969 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 4970 4971 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4972 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4973 Op.getOperand(0), 4974 DAG.getIntPtrConstant(1))); 4975 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 4976 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4977 Op.getOperand(0), 4978 DAG.getIntPtrConstant(0))); 4979 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 4980 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 4981 PseudoSourceValue::getConstantPool(), 0, 4982 false, 16); 4983 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 4984 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 4985 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 4986 PseudoSourceValue::getConstantPool(), 0, 4987 false, 16); 4988 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 4989 4990 // Add the halves; easiest way is to swap them into another reg first. 4991 int ShufMask[2] = { 1, -1 }; 4992 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 4993 DAG.getUNDEF(MVT::v2f64), ShufMask); 4994 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 4995 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 4996 DAG.getIntPtrConstant(0)); 4997} 4998 4999// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5000SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5001 DebugLoc dl = Op.getDebugLoc(); 5002 // FP constant to bias correct the final result. 5003 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5004 MVT::f64); 5005 5006 // Load the 32-bit value into an XMM register. 5007 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5008 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5009 Op.getOperand(0), 5010 DAG.getIntPtrConstant(0))); 5011 5012 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5013 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5014 DAG.getIntPtrConstant(0)); 5015 5016 // Or the load with the bias. 5017 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5018 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5019 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5020 MVT::v2f64, Load)), 5021 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5022 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5023 MVT::v2f64, Bias))); 5024 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5025 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5026 DAG.getIntPtrConstant(0)); 5027 5028 // Subtract the bias. 5029 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5030 5031 // Handle final rounding. 5032 EVT DestVT = Op.getValueType(); 5033 5034 if (DestVT.bitsLT(MVT::f64)) { 5035 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5036 DAG.getIntPtrConstant(0)); 5037 } else if (DestVT.bitsGT(MVT::f64)) { 5038 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5039 } 5040 5041 // Handle final rounding. 5042 return Sub; 5043} 5044 5045SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5046 SDValue N0 = Op.getOperand(0); 5047 DebugLoc dl = Op.getDebugLoc(); 5048 5049 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5050 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5051 // the optimization here. 5052 if (DAG.SignBitIsZero(N0)) 5053 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5054 5055 EVT SrcVT = N0.getValueType(); 5056 if (SrcVT == MVT::i64) { 5057 // We only handle SSE2 f64 target here; caller can expand the rest. 5058 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5059 return SDValue(); 5060 5061 return LowerUINT_TO_FP_i64(Op, DAG); 5062 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5063 return LowerUINT_TO_FP_i32(Op, DAG); 5064 } 5065 5066 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5067 5068 // Make a 64-bit buffer, and use it to build an FILD. 5069 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5070 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5071 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5072 getPointerTy(), StackSlot, WordOff); 5073 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5074 StackSlot, NULL, 0); 5075 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5076 OffsetSlot, NULL, 0); 5077 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5078} 5079 5080std::pair<SDValue,SDValue> X86TargetLowering:: 5081FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5082 DebugLoc dl = Op.getDebugLoc(); 5083 5084 EVT DstTy = Op.getValueType(); 5085 5086 if (!IsSigned) { 5087 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5088 DstTy = MVT::i64; 5089 } 5090 5091 assert(DstTy.getSimpleVT() <= MVT::i64 && 5092 DstTy.getSimpleVT() >= MVT::i16 && 5093 "Unknown FP_TO_SINT to lower!"); 5094 5095 // These are really Legal. 5096 if (DstTy == MVT::i32 && 5097 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5098 return std::make_pair(SDValue(), SDValue()); 5099 if (Subtarget->is64Bit() && 5100 DstTy == MVT::i64 && 5101 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5102 return std::make_pair(SDValue(), SDValue()); 5103 5104 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5105 // stack slot. 5106 MachineFunction &MF = DAG.getMachineFunction(); 5107 unsigned MemSize = DstTy.getSizeInBits()/8; 5108 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5109 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5110 5111 unsigned Opc; 5112 switch (DstTy.getSimpleVT().SimpleTy) { 5113 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5114 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5115 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5116 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5117 } 5118 5119 SDValue Chain = DAG.getEntryNode(); 5120 SDValue Value = Op.getOperand(0); 5121 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5122 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5123 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5124 PseudoSourceValue::getFixedStack(SSFI), 0); 5125 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5126 SDValue Ops[] = { 5127 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5128 }; 5129 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5130 Chain = Value.getValue(1); 5131 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize); 5132 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5133 } 5134 5135 // Build the FP_TO_INT*_IN_MEM 5136 SDValue Ops[] = { Chain, Value, StackSlot }; 5137 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5138 5139 return std::make_pair(FIST, StackSlot); 5140} 5141 5142SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5143 if (Op.getValueType().isVector()) { 5144 if (Op.getValueType() == MVT::v2i32 && 5145 Op.getOperand(0).getValueType() == MVT::v2f64) { 5146 return Op; 5147 } 5148 return SDValue(); 5149 } 5150 5151 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5152 SDValue FIST = Vals.first, StackSlot = Vals.second; 5153 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5154 if (FIST.getNode() == 0) return Op; 5155 5156 // Load the result. 5157 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5158 FIST, StackSlot, NULL, 0); 5159} 5160 5161SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5162 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5163 SDValue FIST = Vals.first, StackSlot = Vals.second; 5164 assert(FIST.getNode() && "Unexpected failure"); 5165 5166 // Load the result. 5167 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5168 FIST, StackSlot, NULL, 0); 5169} 5170 5171SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5172 LLVMContext *Context = DAG.getContext(); 5173 DebugLoc dl = Op.getDebugLoc(); 5174 EVT VT = Op.getValueType(); 5175 EVT EltVT = VT; 5176 if (VT.isVector()) 5177 EltVT = VT.getVectorElementType(); 5178 std::vector<Constant*> CV; 5179 if (EltVT == MVT::f64) { 5180 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5181 CV.push_back(C); 5182 CV.push_back(C); 5183 } else { 5184 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5185 CV.push_back(C); 5186 CV.push_back(C); 5187 CV.push_back(C); 5188 CV.push_back(C); 5189 } 5190 Constant *C = ConstantVector::get(CV); 5191 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5192 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5193 PseudoSourceValue::getConstantPool(), 0, 5194 false, 16); 5195 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5196} 5197 5198SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5199 LLVMContext *Context = DAG.getContext(); 5200 DebugLoc dl = Op.getDebugLoc(); 5201 EVT VT = Op.getValueType(); 5202 EVT EltVT = VT; 5203 if (VT.isVector()) 5204 EltVT = VT.getVectorElementType(); 5205 std::vector<Constant*> CV; 5206 if (EltVT == MVT::f64) { 5207 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5208 CV.push_back(C); 5209 CV.push_back(C); 5210 } else { 5211 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5212 CV.push_back(C); 5213 CV.push_back(C); 5214 CV.push_back(C); 5215 CV.push_back(C); 5216 } 5217 Constant *C = ConstantVector::get(CV); 5218 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5219 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5220 PseudoSourceValue::getConstantPool(), 0, 5221 false, 16); 5222 if (VT.isVector()) { 5223 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5224 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5225 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5226 Op.getOperand(0)), 5227 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5228 } else { 5229 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5230 } 5231} 5232 5233SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5234 LLVMContext *Context = DAG.getContext(); 5235 SDValue Op0 = Op.getOperand(0); 5236 SDValue Op1 = Op.getOperand(1); 5237 DebugLoc dl = Op.getDebugLoc(); 5238 EVT VT = Op.getValueType(); 5239 EVT SrcVT = Op1.getValueType(); 5240 5241 // If second operand is smaller, extend it first. 5242 if (SrcVT.bitsLT(VT)) { 5243 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5244 SrcVT = VT; 5245 } 5246 // And if it is bigger, shrink it first. 5247 if (SrcVT.bitsGT(VT)) { 5248 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5249 SrcVT = VT; 5250 } 5251 5252 // At this point the operands and the result should have the same 5253 // type, and that won't be f80 since that is not custom lowered. 5254 5255 // First get the sign bit of second operand. 5256 std::vector<Constant*> CV; 5257 if (SrcVT == MVT::f64) { 5258 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5259 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5260 } else { 5261 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5262 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5263 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5264 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5265 } 5266 Constant *C = ConstantVector::get(CV); 5267 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5268 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5269 PseudoSourceValue::getConstantPool(), 0, 5270 false, 16); 5271 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5272 5273 // Shift sign bit right or left if the two operands have different types. 5274 if (SrcVT.bitsGT(VT)) { 5275 // Op0 is MVT::f32, Op1 is MVT::f64. 5276 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5277 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5278 DAG.getConstant(32, MVT::i32)); 5279 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5280 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5281 DAG.getIntPtrConstant(0)); 5282 } 5283 5284 // Clear first operand sign bit. 5285 CV.clear(); 5286 if (VT == MVT::f64) { 5287 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5288 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5289 } else { 5290 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5291 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5292 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5293 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5294 } 5295 C = ConstantVector::get(CV); 5296 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5297 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5298 PseudoSourceValue::getConstantPool(), 0, 5299 false, 16); 5300 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5301 5302 // Or the value with the sign bit. 5303 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5304} 5305 5306/// Emit nodes that will be selected as "test Op0,Op0", or something 5307/// equivalent. 5308SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5309 SelectionDAG &DAG) { 5310 DebugLoc dl = Op.getDebugLoc(); 5311 5312 // CF and OF aren't always set the way we want. Determine which 5313 // of these we need. 5314 bool NeedCF = false; 5315 bool NeedOF = false; 5316 switch (X86CC) { 5317 case X86::COND_A: case X86::COND_AE: 5318 case X86::COND_B: case X86::COND_BE: 5319 NeedCF = true; 5320 break; 5321 case X86::COND_G: case X86::COND_GE: 5322 case X86::COND_L: case X86::COND_LE: 5323 case X86::COND_O: case X86::COND_NO: 5324 NeedOF = true; 5325 break; 5326 default: break; 5327 } 5328 5329 // See if we can use the EFLAGS value from the operand instead of 5330 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5331 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5332 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5333 unsigned Opcode = 0; 5334 unsigned NumOperands = 0; 5335 switch (Op.getNode()->getOpcode()) { 5336 case ISD::ADD: 5337 // Due to an isel shortcoming, be conservative if this add is likely to 5338 // be selected as part of a load-modify-store instruction. When the root 5339 // node in a match is a store, isel doesn't know how to remap non-chain 5340 // non-flag uses of other nodes in the match, such as the ADD in this 5341 // case. This leads to the ADD being left around and reselected, with 5342 // the result being two adds in the output. 5343 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5344 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5345 if (UI->getOpcode() == ISD::STORE) 5346 goto default_case; 5347 if (ConstantSDNode *C = 5348 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5349 // An add of one will be selected as an INC. 5350 if (C->getAPIntValue() == 1) { 5351 Opcode = X86ISD::INC; 5352 NumOperands = 1; 5353 break; 5354 } 5355 // An add of negative one (subtract of one) will be selected as a DEC. 5356 if (C->getAPIntValue().isAllOnesValue()) { 5357 Opcode = X86ISD::DEC; 5358 NumOperands = 1; 5359 break; 5360 } 5361 } 5362 // Otherwise use a regular EFLAGS-setting add. 5363 Opcode = X86ISD::ADD; 5364 NumOperands = 2; 5365 break; 5366 case ISD::AND: { 5367 // If the primary and result isn't used, don't bother using X86ISD::AND, 5368 // because a TEST instruction will be better. 5369 bool NonFlagUse = false; 5370 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5371 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5372 if (UI->getOpcode() != ISD::BRCOND && 5373 UI->getOpcode() != ISD::SELECT && 5374 UI->getOpcode() != ISD::SETCC) { 5375 NonFlagUse = true; 5376 break; 5377 } 5378 if (!NonFlagUse) 5379 break; 5380 } 5381 // FALL THROUGH 5382 case ISD::SUB: 5383 case ISD::OR: 5384 case ISD::XOR: 5385 // Due to the ISEL shortcoming noted above, be conservative if this op is 5386 // likely to be selected as part of a load-modify-store instruction. 5387 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5388 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5389 if (UI->getOpcode() == ISD::STORE) 5390 goto default_case; 5391 // Otherwise use a regular EFLAGS-setting instruction. 5392 switch (Op.getNode()->getOpcode()) { 5393 case ISD::SUB: Opcode = X86ISD::SUB; break; 5394 case ISD::OR: Opcode = X86ISD::OR; break; 5395 case ISD::XOR: Opcode = X86ISD::XOR; break; 5396 case ISD::AND: Opcode = X86ISD::AND; break; 5397 default: llvm_unreachable("unexpected operator!"); 5398 } 5399 NumOperands = 2; 5400 break; 5401 case X86ISD::ADD: 5402 case X86ISD::SUB: 5403 case X86ISD::INC: 5404 case X86ISD::DEC: 5405 case X86ISD::OR: 5406 case X86ISD::XOR: 5407 case X86ISD::AND: 5408 return SDValue(Op.getNode(), 1); 5409 default: 5410 default_case: 5411 break; 5412 } 5413 if (Opcode != 0) { 5414 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5415 SmallVector<SDValue, 4> Ops; 5416 for (unsigned i = 0; i != NumOperands; ++i) 5417 Ops.push_back(Op.getOperand(i)); 5418 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5419 DAG.ReplaceAllUsesWith(Op, New); 5420 return SDValue(New.getNode(), 1); 5421 } 5422 } 5423 5424 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5425 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5426 DAG.getConstant(0, Op.getValueType())); 5427} 5428 5429/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5430/// equivalent. 5431SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5432 SelectionDAG &DAG) { 5433 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5434 if (C->getAPIntValue() == 0) 5435 return EmitTest(Op0, X86CC, DAG); 5436 5437 DebugLoc dl = Op0.getDebugLoc(); 5438 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5439} 5440 5441SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5442 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5443 SDValue Op0 = Op.getOperand(0); 5444 SDValue Op1 = Op.getOperand(1); 5445 DebugLoc dl = Op.getDebugLoc(); 5446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5447 5448 // Lower (X & (1 << N)) == 0 to BT(X, N). 5449 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5450 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5451 if (Op0.getOpcode() == ISD::AND && 5452 Op0.hasOneUse() && 5453 Op1.getOpcode() == ISD::Constant && 5454 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5455 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5456 SDValue LHS, RHS; 5457 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5458 if (ConstantSDNode *Op010C = 5459 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5460 if (Op010C->getZExtValue() == 1) { 5461 LHS = Op0.getOperand(0); 5462 RHS = Op0.getOperand(1).getOperand(1); 5463 } 5464 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5465 if (ConstantSDNode *Op000C = 5466 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5467 if (Op000C->getZExtValue() == 1) { 5468 LHS = Op0.getOperand(1); 5469 RHS = Op0.getOperand(0).getOperand(1); 5470 } 5471 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5472 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5473 SDValue AndLHS = Op0.getOperand(0); 5474 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5475 LHS = AndLHS.getOperand(0); 5476 RHS = AndLHS.getOperand(1); 5477 } 5478 } 5479 5480 if (LHS.getNode()) { 5481 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5482 // instruction. Since the shift amount is in-range-or-undefined, we know 5483 // that doing a bittest on the i16 value is ok. We extend to i32 because 5484 // the encoding for the i16 version is larger than the i32 version. 5485 if (LHS.getValueType() == MVT::i8) 5486 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5487 5488 // If the operand types disagree, extend the shift amount to match. Since 5489 // BT ignores high bits (like shifts) we can use anyextend. 5490 if (LHS.getValueType() != RHS.getValueType()) 5491 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5492 5493 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5494 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5495 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5496 DAG.getConstant(Cond, MVT::i8), BT); 5497 } 5498 } 5499 5500 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5501 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5502 5503 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 5504 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5505 DAG.getConstant(X86CC, MVT::i8), Cond); 5506} 5507 5508SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5509 SDValue Cond; 5510 SDValue Op0 = Op.getOperand(0); 5511 SDValue Op1 = Op.getOperand(1); 5512 SDValue CC = Op.getOperand(2); 5513 EVT VT = Op.getValueType(); 5514 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5515 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5516 DebugLoc dl = Op.getDebugLoc(); 5517 5518 if (isFP) { 5519 unsigned SSECC = 8; 5520 EVT VT0 = Op0.getValueType(); 5521 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5522 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5523 bool Swap = false; 5524 5525 switch (SetCCOpcode) { 5526 default: break; 5527 case ISD::SETOEQ: 5528 case ISD::SETEQ: SSECC = 0; break; 5529 case ISD::SETOGT: 5530 case ISD::SETGT: Swap = true; // Fallthrough 5531 case ISD::SETLT: 5532 case ISD::SETOLT: SSECC = 1; break; 5533 case ISD::SETOGE: 5534 case ISD::SETGE: Swap = true; // Fallthrough 5535 case ISD::SETLE: 5536 case ISD::SETOLE: SSECC = 2; break; 5537 case ISD::SETUO: SSECC = 3; break; 5538 case ISD::SETUNE: 5539 case ISD::SETNE: SSECC = 4; break; 5540 case ISD::SETULE: Swap = true; 5541 case ISD::SETUGE: SSECC = 5; break; 5542 case ISD::SETULT: Swap = true; 5543 case ISD::SETUGT: SSECC = 6; break; 5544 case ISD::SETO: SSECC = 7; break; 5545 } 5546 if (Swap) 5547 std::swap(Op0, Op1); 5548 5549 // In the two special cases we can't handle, emit two comparisons. 5550 if (SSECC == 8) { 5551 if (SetCCOpcode == ISD::SETUEQ) { 5552 SDValue UNORD, EQ; 5553 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 5554 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 5555 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 5556 } 5557 else if (SetCCOpcode == ISD::SETONE) { 5558 SDValue ORD, NEQ; 5559 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 5560 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 5561 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 5562 } 5563 llvm_unreachable("Illegal FP comparison"); 5564 } 5565 // Handle all other FP comparisons here. 5566 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 5567 } 5568 5569 // We are handling one of the integer comparisons here. Since SSE only has 5570 // GT and EQ comparisons for integer, swapping operands and multiple 5571 // operations may be required for some comparisons. 5572 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 5573 bool Swap = false, Invert = false, FlipSigns = false; 5574 5575 switch (VT.getSimpleVT().SimpleTy) { 5576 default: break; 5577 case MVT::v8i8: 5578 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 5579 case MVT::v4i16: 5580 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 5581 case MVT::v2i32: 5582 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 5583 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 5584 } 5585 5586 switch (SetCCOpcode) { 5587 default: break; 5588 case ISD::SETNE: Invert = true; 5589 case ISD::SETEQ: Opc = EQOpc; break; 5590 case ISD::SETLT: Swap = true; 5591 case ISD::SETGT: Opc = GTOpc; break; 5592 case ISD::SETGE: Swap = true; 5593 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 5594 case ISD::SETULT: Swap = true; 5595 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 5596 case ISD::SETUGE: Swap = true; 5597 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 5598 } 5599 if (Swap) 5600 std::swap(Op0, Op1); 5601 5602 // Since SSE has no unsigned integer comparisons, we need to flip the sign 5603 // bits of the inputs before performing those operations. 5604 if (FlipSigns) { 5605 EVT EltVT = VT.getVectorElementType(); 5606 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 5607 EltVT); 5608 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 5609 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 5610 SignBits.size()); 5611 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 5612 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 5613 } 5614 5615 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 5616 5617 // If the logical-not of the result is required, perform that now. 5618 if (Invert) 5619 Result = DAG.getNOT(dl, Result, VT); 5620 5621 return Result; 5622} 5623 5624// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 5625static bool isX86LogicalCmp(SDValue Op) { 5626 unsigned Opc = Op.getNode()->getOpcode(); 5627 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 5628 return true; 5629 if (Op.getResNo() == 1 && 5630 (Opc == X86ISD::ADD || 5631 Opc == X86ISD::SUB || 5632 Opc == X86ISD::SMUL || 5633 Opc == X86ISD::UMUL || 5634 Opc == X86ISD::INC || 5635 Opc == X86ISD::DEC || 5636 Opc == X86ISD::OR || 5637 Opc == X86ISD::XOR || 5638 Opc == X86ISD::AND)) 5639 return true; 5640 5641 return false; 5642} 5643 5644SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 5645 bool addTest = true; 5646 SDValue Cond = Op.getOperand(0); 5647 DebugLoc dl = Op.getDebugLoc(); 5648 SDValue CC; 5649 5650 if (Cond.getOpcode() == ISD::SETCC) 5651 Cond = LowerSETCC(Cond, DAG); 5652 5653 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5654 // setting operand in place of the X86ISD::SETCC. 5655 if (Cond.getOpcode() == X86ISD::SETCC) { 5656 CC = Cond.getOperand(0); 5657 5658 SDValue Cmp = Cond.getOperand(1); 5659 unsigned Opc = Cmp.getOpcode(); 5660 EVT VT = Op.getValueType(); 5661 5662 bool IllegalFPCMov = false; 5663 if (VT.isFloatingPoint() && !VT.isVector() && 5664 !isScalarFPTypeInSSEReg(VT)) // FPStack? 5665 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 5666 5667 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 5668 Opc == X86ISD::BT) { // FIXME 5669 Cond = Cmp; 5670 addTest = false; 5671 } 5672 } 5673 5674 if (addTest) { 5675 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5676 Cond = EmitTest(Cond, X86::COND_NE, DAG); 5677 } 5678 5679 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 5680 SmallVector<SDValue, 4> Ops; 5681 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 5682 // condition is true. 5683 Ops.push_back(Op.getOperand(2)); 5684 Ops.push_back(Op.getOperand(1)); 5685 Ops.push_back(CC); 5686 Ops.push_back(Cond); 5687 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size()); 5688} 5689 5690// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 5691// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 5692// from the AND / OR. 5693static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 5694 Opc = Op.getOpcode(); 5695 if (Opc != ISD::OR && Opc != ISD::AND) 5696 return false; 5697 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5698 Op.getOperand(0).hasOneUse() && 5699 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 5700 Op.getOperand(1).hasOneUse()); 5701} 5702 5703// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 5704// 1 and that the SETCC node has a single use. 5705static bool isXor1OfSetCC(SDValue Op) { 5706 if (Op.getOpcode() != ISD::XOR) 5707 return false; 5708 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5709 if (N1C && N1C->getAPIntValue() == 1) { 5710 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 5711 Op.getOperand(0).hasOneUse(); 5712 } 5713 return false; 5714} 5715 5716SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 5717 bool addTest = true; 5718 SDValue Chain = Op.getOperand(0); 5719 SDValue Cond = Op.getOperand(1); 5720 SDValue Dest = Op.getOperand(2); 5721 DebugLoc dl = Op.getDebugLoc(); 5722 SDValue CC; 5723 5724 if (Cond.getOpcode() == ISD::SETCC) 5725 Cond = LowerSETCC(Cond, DAG); 5726#if 0 5727 // FIXME: LowerXALUO doesn't handle these!! 5728 else if (Cond.getOpcode() == X86ISD::ADD || 5729 Cond.getOpcode() == X86ISD::SUB || 5730 Cond.getOpcode() == X86ISD::SMUL || 5731 Cond.getOpcode() == X86ISD::UMUL) 5732 Cond = LowerXALUO(Cond, DAG); 5733#endif 5734 5735 // If condition flag is set by a X86ISD::CMP, then use it as the condition 5736 // setting operand in place of the X86ISD::SETCC. 5737 if (Cond.getOpcode() == X86ISD::SETCC) { 5738 CC = Cond.getOperand(0); 5739 5740 SDValue Cmp = Cond.getOperand(1); 5741 unsigned Opc = Cmp.getOpcode(); 5742 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 5743 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 5744 Cond = Cmp; 5745 addTest = false; 5746 } else { 5747 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 5748 default: break; 5749 case X86::COND_O: 5750 case X86::COND_B: 5751 // These can only come from an arithmetic instruction with overflow, 5752 // e.g. SADDO, UADDO. 5753 Cond = Cond.getNode()->getOperand(1); 5754 addTest = false; 5755 break; 5756 } 5757 } 5758 } else { 5759 unsigned CondOpc; 5760 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 5761 SDValue Cmp = Cond.getOperand(0).getOperand(1); 5762 if (CondOpc == ISD::OR) { 5763 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 5764 // two branches instead of an explicit OR instruction with a 5765 // separate test. 5766 if (Cmp == Cond.getOperand(1).getOperand(1) && 5767 isX86LogicalCmp(Cmp)) { 5768 CC = Cond.getOperand(0).getOperand(0); 5769 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5770 Chain, Dest, CC, Cmp); 5771 CC = Cond.getOperand(1).getOperand(0); 5772 Cond = Cmp; 5773 addTest = false; 5774 } 5775 } else { // ISD::AND 5776 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 5777 // two branches instead of an explicit AND instruction with a 5778 // separate test. However, we only do this if this block doesn't 5779 // have a fall-through edge, because this requires an explicit 5780 // jmp when the condition is false. 5781 if (Cmp == Cond.getOperand(1).getOperand(1) && 5782 isX86LogicalCmp(Cmp) && 5783 Op.getNode()->hasOneUse()) { 5784 X86::CondCode CCode = 5785 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5786 CCode = X86::GetOppositeBranchCondition(CCode); 5787 CC = DAG.getConstant(CCode, MVT::i8); 5788 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 5789 // Look for an unconditional branch following this conditional branch. 5790 // We need this because we need to reverse the successors in order 5791 // to implement FCMP_OEQ. 5792 if (User.getOpcode() == ISD::BR) { 5793 SDValue FalseBB = User.getOperand(1); 5794 SDValue NewBR = 5795 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 5796 assert(NewBR == User); 5797 Dest = FalseBB; 5798 5799 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5800 Chain, Dest, CC, Cmp); 5801 X86::CondCode CCode = 5802 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 5803 CCode = X86::GetOppositeBranchCondition(CCode); 5804 CC = DAG.getConstant(CCode, MVT::i8); 5805 Cond = Cmp; 5806 addTest = false; 5807 } 5808 } 5809 } 5810 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 5811 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 5812 // It should be transformed during dag combiner except when the condition 5813 // is set by a arithmetics with overflow node. 5814 X86::CondCode CCode = 5815 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 5816 CCode = X86::GetOppositeBranchCondition(CCode); 5817 CC = DAG.getConstant(CCode, MVT::i8); 5818 Cond = Cond.getOperand(0).getOperand(1); 5819 addTest = false; 5820 } 5821 } 5822 5823 if (addTest) { 5824 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5825 Cond = EmitTest(Cond, X86::COND_NE, DAG); 5826 } 5827 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 5828 Chain, Dest, CC, Cond); 5829} 5830 5831 5832// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 5833// Calls to _alloca is needed to probe the stack when allocating more than 4k 5834// bytes in one go. Touching the stack at 4K increments is necessary to ensure 5835// that the guard pages used by the OS virtual memory manager are allocated in 5836// correct sequence. 5837SDValue 5838X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 5839 SelectionDAG &DAG) { 5840 assert(Subtarget->isTargetCygMing() && 5841 "This should be used only on Cygwin/Mingw targets"); 5842 DebugLoc dl = Op.getDebugLoc(); 5843 5844 // Get the inputs. 5845 SDValue Chain = Op.getOperand(0); 5846 SDValue Size = Op.getOperand(1); 5847 // FIXME: Ensure alignment here 5848 5849 SDValue Flag; 5850 5851 EVT IntPtr = getPointerTy(); 5852 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 5853 5854 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 5855 5856 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 5857 Flag = Chain.getValue(1); 5858 5859 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5860 SDValue Ops[] = { Chain, 5861 DAG.getTargetExternalSymbol("_alloca", IntPtr), 5862 DAG.getRegister(X86::EAX, IntPtr), 5863 DAG.getRegister(X86StackPtr, SPTy), 5864 Flag }; 5865 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); 5866 Flag = Chain.getValue(1); 5867 5868 Chain = DAG.getCALLSEQ_END(Chain, 5869 DAG.getIntPtrConstant(0, true), 5870 DAG.getIntPtrConstant(0, true), 5871 Flag); 5872 5873 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 5874 5875 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 5876 return DAG.getMergeValues(Ops1, 2, dl); 5877} 5878 5879SDValue 5880X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 5881 SDValue Chain, 5882 SDValue Dst, SDValue Src, 5883 SDValue Size, unsigned Align, 5884 const Value *DstSV, 5885 uint64_t DstSVOff) { 5886 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 5887 5888 // If not DWORD aligned or size is more than the threshold, call the library. 5889 // The libc version is likely to be faster for these cases. It can use the 5890 // address value and run time information about the CPU. 5891 if ((Align & 3) != 0 || 5892 !ConstantSize || 5893 ConstantSize->getZExtValue() > 5894 getSubtarget()->getMaxInlineSizeThreshold()) { 5895 SDValue InFlag(0, 0); 5896 5897 // Check to see if there is a specialized entry-point for memory zeroing. 5898 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 5899 5900 if (const char *bzeroEntry = V && 5901 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 5902 EVT IntPtr = getPointerTy(); 5903 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 5904 TargetLowering::ArgListTy Args; 5905 TargetLowering::ArgListEntry Entry; 5906 Entry.Node = Dst; 5907 Entry.Ty = IntPtrTy; 5908 Args.push_back(Entry); 5909 Entry.Node = Size; 5910 Args.push_back(Entry); 5911 std::pair<SDValue,SDValue> CallResult = 5912 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 5913 false, false, false, false, 5914 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 5915 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl); 5916 return CallResult.second; 5917 } 5918 5919 // Otherwise have the target-independent code call memset. 5920 return SDValue(); 5921 } 5922 5923 uint64_t SizeVal = ConstantSize->getZExtValue(); 5924 SDValue InFlag(0, 0); 5925 EVT AVT; 5926 SDValue Count; 5927 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 5928 unsigned BytesLeft = 0; 5929 bool TwoRepStos = false; 5930 if (ValC) { 5931 unsigned ValReg; 5932 uint64_t Val = ValC->getZExtValue() & 255; 5933 5934 // If the value is a constant, then we can potentially use larger sets. 5935 switch (Align & 3) { 5936 case 2: // WORD aligned 5937 AVT = MVT::i16; 5938 ValReg = X86::AX; 5939 Val = (Val << 8) | Val; 5940 break; 5941 case 0: // DWORD aligned 5942 AVT = MVT::i32; 5943 ValReg = X86::EAX; 5944 Val = (Val << 8) | Val; 5945 Val = (Val << 16) | Val; 5946 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 5947 AVT = MVT::i64; 5948 ValReg = X86::RAX; 5949 Val = (Val << 32) | Val; 5950 } 5951 break; 5952 default: // Byte aligned 5953 AVT = MVT::i8; 5954 ValReg = X86::AL; 5955 Count = DAG.getIntPtrConstant(SizeVal); 5956 break; 5957 } 5958 5959 if (AVT.bitsGT(MVT::i8)) { 5960 unsigned UBytes = AVT.getSizeInBits() / 8; 5961 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 5962 BytesLeft = SizeVal % UBytes; 5963 } 5964 5965 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 5966 InFlag); 5967 InFlag = Chain.getValue(1); 5968 } else { 5969 AVT = MVT::i8; 5970 Count = DAG.getIntPtrConstant(SizeVal); 5971 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 5972 InFlag = Chain.getValue(1); 5973 } 5974 5975 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 5976 X86::ECX, 5977 Count, InFlag); 5978 InFlag = Chain.getValue(1); 5979 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 5980 X86::EDI, 5981 Dst, InFlag); 5982 InFlag = Chain.getValue(1); 5983 5984 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 5985 SmallVector<SDValue, 8> Ops; 5986 Ops.push_back(Chain); 5987 Ops.push_back(DAG.getValueType(AVT)); 5988 Ops.push_back(InFlag); 5989 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 5990 5991 if (TwoRepStos) { 5992 InFlag = Chain.getValue(1); 5993 Count = Size; 5994 EVT CVT = Count.getValueType(); 5995 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 5996 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 5997 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 5998 X86::ECX, 5999 Left, InFlag); 6000 InFlag = Chain.getValue(1); 6001 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6002 Ops.clear(); 6003 Ops.push_back(Chain); 6004 Ops.push_back(DAG.getValueType(MVT::i8)); 6005 Ops.push_back(InFlag); 6006 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); 6007 } else if (BytesLeft) { 6008 // Handle the last 1 - 7 bytes. 6009 unsigned Offset = SizeVal - BytesLeft; 6010 EVT AddrVT = Dst.getValueType(); 6011 EVT SizeVT = Size.getValueType(); 6012 6013 Chain = DAG.getMemset(Chain, dl, 6014 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 6015 DAG.getConstant(Offset, AddrVT)), 6016 Src, 6017 DAG.getConstant(BytesLeft, SizeVT), 6018 Align, DstSV, DstSVOff + Offset); 6019 } 6020 6021 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 6022 return Chain; 6023} 6024 6025SDValue 6026X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 6027 SDValue Chain, SDValue Dst, SDValue Src, 6028 SDValue Size, unsigned Align, 6029 bool AlwaysInline, 6030 const Value *DstSV, uint64_t DstSVOff, 6031 const Value *SrcSV, uint64_t SrcSVOff) { 6032 // This requires the copy size to be a constant, preferrably 6033 // within a subtarget-specific limit. 6034 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6035 if (!ConstantSize) 6036 return SDValue(); 6037 uint64_t SizeVal = ConstantSize->getZExtValue(); 6038 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 6039 return SDValue(); 6040 6041 /// If not DWORD aligned, call the library. 6042 if ((Align & 3) != 0) 6043 return SDValue(); 6044 6045 // DWORD aligned 6046 EVT AVT = MVT::i32; 6047 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 6048 AVT = MVT::i64; 6049 6050 unsigned UBytes = AVT.getSizeInBits() / 8; 6051 unsigned CountVal = SizeVal / UBytes; 6052 SDValue Count = DAG.getIntPtrConstant(CountVal); 6053 unsigned BytesLeft = SizeVal % UBytes; 6054 6055 SDValue InFlag(0, 0); 6056 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6057 X86::ECX, 6058 Count, InFlag); 6059 InFlag = Chain.getValue(1); 6060 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6061 X86::EDI, 6062 Dst, InFlag); 6063 InFlag = Chain.getValue(1); 6064 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6065 X86::ESI, 6066 Src, InFlag); 6067 InFlag = Chain.getValue(1); 6068 6069 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6070 SmallVector<SDValue, 8> Ops; 6071 Ops.push_back(Chain); 6072 Ops.push_back(DAG.getValueType(AVT)); 6073 Ops.push_back(InFlag); 6074 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size()); 6075 6076 SmallVector<SDValue, 4> Results; 6077 Results.push_back(RepMovs); 6078 if (BytesLeft) { 6079 // Handle the last 1 - 7 bytes. 6080 unsigned Offset = SizeVal - BytesLeft; 6081 EVT DstVT = Dst.getValueType(); 6082 EVT SrcVT = Src.getValueType(); 6083 EVT SizeVT = Size.getValueType(); 6084 Results.push_back(DAG.getMemcpy(Chain, dl, 6085 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6086 DAG.getConstant(Offset, DstVT)), 6087 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6088 DAG.getConstant(Offset, SrcVT)), 6089 DAG.getConstant(BytesLeft, SizeVT), 6090 Align, AlwaysInline, 6091 DstSV, DstSVOff + Offset, 6092 SrcSV, SrcSVOff + Offset)); 6093 } 6094 6095 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6096 &Results[0], Results.size()); 6097} 6098 6099SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6100 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6101 DebugLoc dl = Op.getDebugLoc(); 6102 6103 if (!Subtarget->is64Bit()) { 6104 // vastart just stores the address of the VarArgsFrameIndex slot into the 6105 // memory location argument. 6106 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6107 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 6108 } 6109 6110 // __va_list_tag: 6111 // gp_offset (0 - 6 * 8) 6112 // fp_offset (48 - 48 + 8 * 16) 6113 // overflow_arg_area (point to parameters coming in memory). 6114 // reg_save_area 6115 SmallVector<SDValue, 8> MemOps; 6116 SDValue FIN = Op.getOperand(1); 6117 // Store gp_offset 6118 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6119 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6120 FIN, SV, 0); 6121 MemOps.push_back(Store); 6122 6123 // Store fp_offset 6124 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6125 FIN, DAG.getIntPtrConstant(4)); 6126 Store = DAG.getStore(Op.getOperand(0), dl, 6127 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6128 FIN, SV, 0); 6129 MemOps.push_back(Store); 6130 6131 // Store ptr to overflow_arg_area 6132 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6133 FIN, DAG.getIntPtrConstant(4)); 6134 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6135 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0); 6136 MemOps.push_back(Store); 6137 6138 // Store ptr to reg_save_area. 6139 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6140 FIN, DAG.getIntPtrConstant(8)); 6141 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6142 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0); 6143 MemOps.push_back(Store); 6144 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6145 &MemOps[0], MemOps.size()); 6146} 6147 6148SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6149 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6150 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6151 SDValue Chain = Op.getOperand(0); 6152 SDValue SrcPtr = Op.getOperand(1); 6153 SDValue SrcSV = Op.getOperand(2); 6154 6155 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6156 return SDValue(); 6157} 6158 6159SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6160 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6161 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6162 SDValue Chain = Op.getOperand(0); 6163 SDValue DstPtr = Op.getOperand(1); 6164 SDValue SrcPtr = Op.getOperand(2); 6165 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6166 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6167 DebugLoc dl = Op.getDebugLoc(); 6168 6169 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6170 DAG.getIntPtrConstant(24), 8, false, 6171 DstSV, 0, SrcSV, 0); 6172} 6173 6174SDValue 6175X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6176 DebugLoc dl = Op.getDebugLoc(); 6177 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6178 switch (IntNo) { 6179 default: return SDValue(); // Don't custom lower most intrinsics. 6180 // Comparison intrinsics. 6181 case Intrinsic::x86_sse_comieq_ss: 6182 case Intrinsic::x86_sse_comilt_ss: 6183 case Intrinsic::x86_sse_comile_ss: 6184 case Intrinsic::x86_sse_comigt_ss: 6185 case Intrinsic::x86_sse_comige_ss: 6186 case Intrinsic::x86_sse_comineq_ss: 6187 case Intrinsic::x86_sse_ucomieq_ss: 6188 case Intrinsic::x86_sse_ucomilt_ss: 6189 case Intrinsic::x86_sse_ucomile_ss: 6190 case Intrinsic::x86_sse_ucomigt_ss: 6191 case Intrinsic::x86_sse_ucomige_ss: 6192 case Intrinsic::x86_sse_ucomineq_ss: 6193 case Intrinsic::x86_sse2_comieq_sd: 6194 case Intrinsic::x86_sse2_comilt_sd: 6195 case Intrinsic::x86_sse2_comile_sd: 6196 case Intrinsic::x86_sse2_comigt_sd: 6197 case Intrinsic::x86_sse2_comige_sd: 6198 case Intrinsic::x86_sse2_comineq_sd: 6199 case Intrinsic::x86_sse2_ucomieq_sd: 6200 case Intrinsic::x86_sse2_ucomilt_sd: 6201 case Intrinsic::x86_sse2_ucomile_sd: 6202 case Intrinsic::x86_sse2_ucomigt_sd: 6203 case Intrinsic::x86_sse2_ucomige_sd: 6204 case Intrinsic::x86_sse2_ucomineq_sd: { 6205 unsigned Opc = 0; 6206 ISD::CondCode CC = ISD::SETCC_INVALID; 6207 switch (IntNo) { 6208 default: break; 6209 case Intrinsic::x86_sse_comieq_ss: 6210 case Intrinsic::x86_sse2_comieq_sd: 6211 Opc = X86ISD::COMI; 6212 CC = ISD::SETEQ; 6213 break; 6214 case Intrinsic::x86_sse_comilt_ss: 6215 case Intrinsic::x86_sse2_comilt_sd: 6216 Opc = X86ISD::COMI; 6217 CC = ISD::SETLT; 6218 break; 6219 case Intrinsic::x86_sse_comile_ss: 6220 case Intrinsic::x86_sse2_comile_sd: 6221 Opc = X86ISD::COMI; 6222 CC = ISD::SETLE; 6223 break; 6224 case Intrinsic::x86_sse_comigt_ss: 6225 case Intrinsic::x86_sse2_comigt_sd: 6226 Opc = X86ISD::COMI; 6227 CC = ISD::SETGT; 6228 break; 6229 case Intrinsic::x86_sse_comige_ss: 6230 case Intrinsic::x86_sse2_comige_sd: 6231 Opc = X86ISD::COMI; 6232 CC = ISD::SETGE; 6233 break; 6234 case Intrinsic::x86_sse_comineq_ss: 6235 case Intrinsic::x86_sse2_comineq_sd: 6236 Opc = X86ISD::COMI; 6237 CC = ISD::SETNE; 6238 break; 6239 case Intrinsic::x86_sse_ucomieq_ss: 6240 case Intrinsic::x86_sse2_ucomieq_sd: 6241 Opc = X86ISD::UCOMI; 6242 CC = ISD::SETEQ; 6243 break; 6244 case Intrinsic::x86_sse_ucomilt_ss: 6245 case Intrinsic::x86_sse2_ucomilt_sd: 6246 Opc = X86ISD::UCOMI; 6247 CC = ISD::SETLT; 6248 break; 6249 case Intrinsic::x86_sse_ucomile_ss: 6250 case Intrinsic::x86_sse2_ucomile_sd: 6251 Opc = X86ISD::UCOMI; 6252 CC = ISD::SETLE; 6253 break; 6254 case Intrinsic::x86_sse_ucomigt_ss: 6255 case Intrinsic::x86_sse2_ucomigt_sd: 6256 Opc = X86ISD::UCOMI; 6257 CC = ISD::SETGT; 6258 break; 6259 case Intrinsic::x86_sse_ucomige_ss: 6260 case Intrinsic::x86_sse2_ucomige_sd: 6261 Opc = X86ISD::UCOMI; 6262 CC = ISD::SETGE; 6263 break; 6264 case Intrinsic::x86_sse_ucomineq_ss: 6265 case Intrinsic::x86_sse2_ucomineq_sd: 6266 Opc = X86ISD::UCOMI; 6267 CC = ISD::SETNE; 6268 break; 6269 } 6270 6271 SDValue LHS = Op.getOperand(1); 6272 SDValue RHS = Op.getOperand(2); 6273 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6274 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6275 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6276 DAG.getConstant(X86CC, MVT::i8), Cond); 6277 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6278 } 6279 // ptest intrinsics. The intrinsic these come from are designed to return 6280 // an integer value, not just an instruction so lower it to the ptest 6281 // pattern and a setcc for the result. 6282 case Intrinsic::x86_sse41_ptestz: 6283 case Intrinsic::x86_sse41_ptestc: 6284 case Intrinsic::x86_sse41_ptestnzc:{ 6285 unsigned X86CC = 0; 6286 switch (IntNo) { 6287 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6288 case Intrinsic::x86_sse41_ptestz: 6289 // ZF = 1 6290 X86CC = X86::COND_E; 6291 break; 6292 case Intrinsic::x86_sse41_ptestc: 6293 // CF = 1 6294 X86CC = X86::COND_B; 6295 break; 6296 case Intrinsic::x86_sse41_ptestnzc: 6297 // ZF and CF = 0 6298 X86CC = X86::COND_A; 6299 break; 6300 } 6301 6302 SDValue LHS = Op.getOperand(1); 6303 SDValue RHS = Op.getOperand(2); 6304 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6305 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6306 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6307 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6308 } 6309 6310 // Fix vector shift instructions where the last operand is a non-immediate 6311 // i32 value. 6312 case Intrinsic::x86_sse2_pslli_w: 6313 case Intrinsic::x86_sse2_pslli_d: 6314 case Intrinsic::x86_sse2_pslli_q: 6315 case Intrinsic::x86_sse2_psrli_w: 6316 case Intrinsic::x86_sse2_psrli_d: 6317 case Intrinsic::x86_sse2_psrli_q: 6318 case Intrinsic::x86_sse2_psrai_w: 6319 case Intrinsic::x86_sse2_psrai_d: 6320 case Intrinsic::x86_mmx_pslli_w: 6321 case Intrinsic::x86_mmx_pslli_d: 6322 case Intrinsic::x86_mmx_pslli_q: 6323 case Intrinsic::x86_mmx_psrli_w: 6324 case Intrinsic::x86_mmx_psrli_d: 6325 case Intrinsic::x86_mmx_psrli_q: 6326 case Intrinsic::x86_mmx_psrai_w: 6327 case Intrinsic::x86_mmx_psrai_d: { 6328 SDValue ShAmt = Op.getOperand(2); 6329 if (isa<ConstantSDNode>(ShAmt)) 6330 return SDValue(); 6331 6332 unsigned NewIntNo = 0; 6333 EVT ShAmtVT = MVT::v4i32; 6334 switch (IntNo) { 6335 case Intrinsic::x86_sse2_pslli_w: 6336 NewIntNo = Intrinsic::x86_sse2_psll_w; 6337 break; 6338 case Intrinsic::x86_sse2_pslli_d: 6339 NewIntNo = Intrinsic::x86_sse2_psll_d; 6340 break; 6341 case Intrinsic::x86_sse2_pslli_q: 6342 NewIntNo = Intrinsic::x86_sse2_psll_q; 6343 break; 6344 case Intrinsic::x86_sse2_psrli_w: 6345 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6346 break; 6347 case Intrinsic::x86_sse2_psrli_d: 6348 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6349 break; 6350 case Intrinsic::x86_sse2_psrli_q: 6351 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6352 break; 6353 case Intrinsic::x86_sse2_psrai_w: 6354 NewIntNo = Intrinsic::x86_sse2_psra_w; 6355 break; 6356 case Intrinsic::x86_sse2_psrai_d: 6357 NewIntNo = Intrinsic::x86_sse2_psra_d; 6358 break; 6359 default: { 6360 ShAmtVT = MVT::v2i32; 6361 switch (IntNo) { 6362 case Intrinsic::x86_mmx_pslli_w: 6363 NewIntNo = Intrinsic::x86_mmx_psll_w; 6364 break; 6365 case Intrinsic::x86_mmx_pslli_d: 6366 NewIntNo = Intrinsic::x86_mmx_psll_d; 6367 break; 6368 case Intrinsic::x86_mmx_pslli_q: 6369 NewIntNo = Intrinsic::x86_mmx_psll_q; 6370 break; 6371 case Intrinsic::x86_mmx_psrli_w: 6372 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6373 break; 6374 case Intrinsic::x86_mmx_psrli_d: 6375 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6376 break; 6377 case Intrinsic::x86_mmx_psrli_q: 6378 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6379 break; 6380 case Intrinsic::x86_mmx_psrai_w: 6381 NewIntNo = Intrinsic::x86_mmx_psra_w; 6382 break; 6383 case Intrinsic::x86_mmx_psrai_d: 6384 NewIntNo = Intrinsic::x86_mmx_psra_d; 6385 break; 6386 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6387 } 6388 break; 6389 } 6390 } 6391 6392 // The vector shift intrinsics with scalars uses 32b shift amounts but 6393 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 6394 // to be zero. 6395 SDValue ShOps[4]; 6396 ShOps[0] = ShAmt; 6397 ShOps[1] = DAG.getConstant(0, MVT::i32); 6398 if (ShAmtVT == MVT::v4i32) { 6399 ShOps[2] = DAG.getUNDEF(MVT::i32); 6400 ShOps[3] = DAG.getUNDEF(MVT::i32); 6401 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 6402 } else { 6403 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 6404 } 6405 6406 EVT VT = Op.getValueType(); 6407 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 6408 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6409 DAG.getConstant(NewIntNo, MVT::i32), 6410 Op.getOperand(1), ShAmt); 6411 } 6412 } 6413} 6414 6415SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6416 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6417 DebugLoc dl = Op.getDebugLoc(); 6418 6419 if (Depth > 0) { 6420 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6421 SDValue Offset = 6422 DAG.getConstant(TD->getPointerSize(), 6423 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 6424 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6425 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6426 FrameAddr, Offset), 6427 NULL, 0); 6428 } 6429 6430 // Just load the return address. 6431 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 6432 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6433 RetAddrFI, NULL, 0); 6434} 6435 6436SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6437 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6438 MFI->setFrameAddressIsTaken(true); 6439 EVT VT = Op.getValueType(); 6440 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 6441 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6442 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6443 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 6444 while (Depth--) 6445 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 6446 return FrameAddr; 6447} 6448 6449SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6450 SelectionDAG &DAG) { 6451 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6452} 6453 6454SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6455{ 6456 MachineFunction &MF = DAG.getMachineFunction(); 6457 SDValue Chain = Op.getOperand(0); 6458 SDValue Offset = Op.getOperand(1); 6459 SDValue Handler = Op.getOperand(2); 6460 DebugLoc dl = Op.getDebugLoc(); 6461 6462 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6463 getPointerTy()); 6464 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6465 6466 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 6467 DAG.getIntPtrConstant(-TD->getPointerSize())); 6468 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 6469 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0); 6470 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 6471 MF.getRegInfo().addLiveOut(StoreAddrReg); 6472 6473 return DAG.getNode(X86ISD::EH_RETURN, dl, 6474 MVT::Other, 6475 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 6476} 6477 6478SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 6479 SelectionDAG &DAG) { 6480 SDValue Root = Op.getOperand(0); 6481 SDValue Trmp = Op.getOperand(1); // trampoline 6482 SDValue FPtr = Op.getOperand(2); // nested function 6483 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 6484 DebugLoc dl = Op.getDebugLoc(); 6485 6486 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6487 6488 const X86InstrInfo *TII = 6489 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 6490 6491 if (Subtarget->is64Bit()) { 6492 SDValue OutChains[6]; 6493 6494 // Large code-model. 6495 6496 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r); 6497 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri); 6498 6499 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 6500 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 6501 6502 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 6503 6504 // Load the pointer to the nested function into R11. 6505 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 6506 SDValue Addr = Trmp; 6507 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6508 Addr, TrmpAddr, 0); 6509 6510 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6511 DAG.getConstant(2, MVT::i64)); 6512 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2); 6513 6514 // Load the 'nest' parameter value into R10. 6515 // R10 is specified in X86CallingConv.td 6516 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 6517 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6518 DAG.getConstant(10, MVT::i64)); 6519 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6520 Addr, TrmpAddr, 10); 6521 6522 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6523 DAG.getConstant(12, MVT::i64)); 6524 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2); 6525 6526 // Jump to the nested function. 6527 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 6528 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6529 DAG.getConstant(20, MVT::i64)); 6530 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 6531 Addr, TrmpAddr, 20); 6532 6533 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 6534 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 6535 DAG.getConstant(22, MVT::i64)); 6536 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 6537 TrmpAddr, 22); 6538 6539 SDValue Ops[] = 6540 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 6541 return DAG.getMergeValues(Ops, 2, dl); 6542 } else { 6543 const Function *Func = 6544 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 6545 CallingConv::ID CC = Func->getCallingConv(); 6546 unsigned NestReg; 6547 6548 switch (CC) { 6549 default: 6550 llvm_unreachable("Unsupported calling convention"); 6551 case CallingConv::C: 6552 case CallingConv::X86_StdCall: { 6553 // Pass 'nest' parameter in ECX. 6554 // Must be kept in sync with X86CallingConv.td 6555 NestReg = X86::ECX; 6556 6557 // Check that ECX wasn't needed by an 'inreg' parameter. 6558 const FunctionType *FTy = Func->getFunctionType(); 6559 const AttrListPtr &Attrs = Func->getAttributes(); 6560 6561 if (!Attrs.isEmpty() && !Func->isVarArg()) { 6562 unsigned InRegCount = 0; 6563 unsigned Idx = 1; 6564 6565 for (FunctionType::param_iterator I = FTy->param_begin(), 6566 E = FTy->param_end(); I != E; ++I, ++Idx) 6567 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 6568 // FIXME: should only count parameters that are lowered to integers. 6569 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 6570 6571 if (InRegCount > 2) { 6572 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 6573 } 6574 } 6575 break; 6576 } 6577 case CallingConv::X86_FastCall: 6578 case CallingConv::Fast: 6579 // Pass 'nest' parameter in EAX. 6580 // Must be kept in sync with X86CallingConv.td 6581 NestReg = X86::EAX; 6582 break; 6583 } 6584 6585 SDValue OutChains[4]; 6586 SDValue Addr, Disp; 6587 6588 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6589 DAG.getConstant(10, MVT::i32)); 6590 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 6591 6592 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); 6593 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 6594 OutChains[0] = DAG.getStore(Root, dl, 6595 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 6596 Trmp, TrmpAddr, 0); 6597 6598 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6599 DAG.getConstant(1, MVT::i32)); 6600 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1); 6601 6602 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); 6603 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6604 DAG.getConstant(5, MVT::i32)); 6605 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 6606 TrmpAddr, 5, false, 1); 6607 6608 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 6609 DAG.getConstant(6, MVT::i32)); 6610 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1); 6611 6612 SDValue Ops[] = 6613 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 6614 return DAG.getMergeValues(Ops, 2, dl); 6615 } 6616} 6617 6618SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 6619 /* 6620 The rounding mode is in bits 11:10 of FPSR, and has the following 6621 settings: 6622 00 Round to nearest 6623 01 Round to -inf 6624 10 Round to +inf 6625 11 Round to 0 6626 6627 FLT_ROUNDS, on the other hand, expects the following: 6628 -1 Undefined 6629 0 Round to 0 6630 1 Round to nearest 6631 2 Round to +inf 6632 3 Round to -inf 6633 6634 To perform the conversion, we do: 6635 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 6636 */ 6637 6638 MachineFunction &MF = DAG.getMachineFunction(); 6639 const TargetMachine &TM = MF.getTarget(); 6640 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 6641 unsigned StackAlignment = TFI.getStackAlignment(); 6642 EVT VT = Op.getValueType(); 6643 DebugLoc dl = Op.getDebugLoc(); 6644 6645 // Save FP Control Word to stack slot 6646 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); 6647 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 6648 6649 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 6650 DAG.getEntryNode(), StackSlot); 6651 6652 // Load FP Control Word from stack slot 6653 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0); 6654 6655 // Transform as necessary 6656 SDValue CWD1 = 6657 DAG.getNode(ISD::SRL, dl, MVT::i16, 6658 DAG.getNode(ISD::AND, dl, MVT::i16, 6659 CWD, DAG.getConstant(0x800, MVT::i16)), 6660 DAG.getConstant(11, MVT::i8)); 6661 SDValue CWD2 = 6662 DAG.getNode(ISD::SRL, dl, MVT::i16, 6663 DAG.getNode(ISD::AND, dl, MVT::i16, 6664 CWD, DAG.getConstant(0x400, MVT::i16)), 6665 DAG.getConstant(9, MVT::i8)); 6666 6667 SDValue RetVal = 6668 DAG.getNode(ISD::AND, dl, MVT::i16, 6669 DAG.getNode(ISD::ADD, dl, MVT::i16, 6670 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 6671 DAG.getConstant(1, MVT::i16)), 6672 DAG.getConstant(3, MVT::i16)); 6673 6674 6675 return DAG.getNode((VT.getSizeInBits() < 16 ? 6676 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 6677} 6678 6679SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 6680 EVT VT = Op.getValueType(); 6681 EVT OpVT = VT; 6682 unsigned NumBits = VT.getSizeInBits(); 6683 DebugLoc dl = Op.getDebugLoc(); 6684 6685 Op = Op.getOperand(0); 6686 if (VT == MVT::i8) { 6687 // Zero extend to i32 since there is not an i8 bsr. 6688 OpVT = MVT::i32; 6689 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6690 } 6691 6692 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 6693 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6694 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 6695 6696 // If src is zero (i.e. bsr sets ZF), returns NumBits. 6697 SmallVector<SDValue, 4> Ops; 6698 Ops.push_back(Op); 6699 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); 6700 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6701 Ops.push_back(Op.getValue(1)); 6702 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6703 6704 // Finally xor with NumBits-1. 6705 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 6706 6707 if (VT == MVT::i8) 6708 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6709 return Op; 6710} 6711 6712SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 6713 EVT VT = Op.getValueType(); 6714 EVT OpVT = VT; 6715 unsigned NumBits = VT.getSizeInBits(); 6716 DebugLoc dl = Op.getDebugLoc(); 6717 6718 Op = Op.getOperand(0); 6719 if (VT == MVT::i8) { 6720 OpVT = MVT::i32; 6721 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 6722 } 6723 6724 // Issue a bsf (scan bits forward) which also sets EFLAGS. 6725 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 6726 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 6727 6728 // If src is zero (i.e. bsf sets ZF), returns NumBits. 6729 SmallVector<SDValue, 4> Ops; 6730 Ops.push_back(Op); 6731 Ops.push_back(DAG.getConstant(NumBits, OpVT)); 6732 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); 6733 Ops.push_back(Op.getValue(1)); 6734 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); 6735 6736 if (VT == MVT::i8) 6737 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 6738 return Op; 6739} 6740 6741SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 6742 EVT VT = Op.getValueType(); 6743 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 6744 DebugLoc dl = Op.getDebugLoc(); 6745 6746 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 6747 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 6748 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 6749 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 6750 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 6751 // 6752 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 6753 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 6754 // return AloBlo + AloBhi + AhiBlo; 6755 6756 SDValue A = Op.getOperand(0); 6757 SDValue B = Op.getOperand(1); 6758 6759 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6760 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6761 A, DAG.getConstant(32, MVT::i32)); 6762 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6763 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 6764 B, DAG.getConstant(32, MVT::i32)); 6765 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6766 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6767 A, B); 6768 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6769 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6770 A, Bhi); 6771 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6772 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 6773 Ahi, B); 6774 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6775 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6776 AloBhi, DAG.getConstant(32, MVT::i32)); 6777 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6778 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 6779 AhiBlo, DAG.getConstant(32, MVT::i32)); 6780 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 6781 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 6782 return Res; 6783} 6784 6785 6786SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 6787 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 6788 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 6789 // looks for this combo and may remove the "setcc" instruction if the "setcc" 6790 // has only one use. 6791 SDNode *N = Op.getNode(); 6792 SDValue LHS = N->getOperand(0); 6793 SDValue RHS = N->getOperand(1); 6794 unsigned BaseOp = 0; 6795 unsigned Cond = 0; 6796 DebugLoc dl = Op.getDebugLoc(); 6797 6798 switch (Op.getOpcode()) { 6799 default: llvm_unreachable("Unknown ovf instruction!"); 6800 case ISD::SADDO: 6801 // A subtract of one will be selected as a INC. Note that INC doesn't 6802 // set CF, so we can't do this for UADDO. 6803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 6804 if (C->getAPIntValue() == 1) { 6805 BaseOp = X86ISD::INC; 6806 Cond = X86::COND_O; 6807 break; 6808 } 6809 BaseOp = X86ISD::ADD; 6810 Cond = X86::COND_O; 6811 break; 6812 case ISD::UADDO: 6813 BaseOp = X86ISD::ADD; 6814 Cond = X86::COND_B; 6815 break; 6816 case ISD::SSUBO: 6817 // A subtract of one will be selected as a DEC. Note that DEC doesn't 6818 // set CF, so we can't do this for USUBO. 6819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 6820 if (C->getAPIntValue() == 1) { 6821 BaseOp = X86ISD::DEC; 6822 Cond = X86::COND_O; 6823 break; 6824 } 6825 BaseOp = X86ISD::SUB; 6826 Cond = X86::COND_O; 6827 break; 6828 case ISD::USUBO: 6829 BaseOp = X86ISD::SUB; 6830 Cond = X86::COND_B; 6831 break; 6832 case ISD::SMULO: 6833 BaseOp = X86ISD::SMUL; 6834 Cond = X86::COND_O; 6835 break; 6836 case ISD::UMULO: 6837 BaseOp = X86ISD::UMUL; 6838 Cond = X86::COND_B; 6839 break; 6840 } 6841 6842 // Also sets EFLAGS. 6843 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 6844 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 6845 6846 SDValue SetCC = 6847 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 6848 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 6849 6850 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 6851 return Sum; 6852} 6853 6854SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 6855 EVT T = Op.getValueType(); 6856 DebugLoc dl = Op.getDebugLoc(); 6857 unsigned Reg = 0; 6858 unsigned size = 0; 6859 switch(T.getSimpleVT().SimpleTy) { 6860 default: 6861 assert(false && "Invalid value type!"); 6862 case MVT::i8: Reg = X86::AL; size = 1; break; 6863 case MVT::i16: Reg = X86::AX; size = 2; break; 6864 case MVT::i32: Reg = X86::EAX; size = 4; break; 6865 case MVT::i64: 6866 assert(Subtarget->is64Bit() && "Node not type legal!"); 6867 Reg = X86::RAX; size = 8; 6868 break; 6869 } 6870 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 6871 Op.getOperand(2), SDValue()); 6872 SDValue Ops[] = { cpIn.getValue(0), 6873 Op.getOperand(1), 6874 Op.getOperand(3), 6875 DAG.getTargetConstant(size, MVT::i8), 6876 cpIn.getValue(1) }; 6877 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6878 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 6879 SDValue cpOut = 6880 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 6881 return cpOut; 6882} 6883 6884SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 6885 SelectionDAG &DAG) { 6886 assert(Subtarget->is64Bit() && "Result not type legalized?"); 6887 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6888 SDValue TheChain = Op.getOperand(0); 6889 DebugLoc dl = Op.getDebugLoc(); 6890 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 6891 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 6892 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 6893 rax.getValue(2)); 6894 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 6895 DAG.getConstant(32, MVT::i8)); 6896 SDValue Ops[] = { 6897 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 6898 rdx.getValue(1) 6899 }; 6900 return DAG.getMergeValues(Ops, 2, dl); 6901} 6902 6903SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 6904 SDNode *Node = Op.getNode(); 6905 DebugLoc dl = Node->getDebugLoc(); 6906 EVT T = Node->getValueType(0); 6907 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 6908 DAG.getConstant(0, T), Node->getOperand(2)); 6909 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 6910 cast<AtomicSDNode>(Node)->getMemoryVT(), 6911 Node->getOperand(0), 6912 Node->getOperand(1), negOp, 6913 cast<AtomicSDNode>(Node)->getSrcValue(), 6914 cast<AtomicSDNode>(Node)->getAlignment()); 6915} 6916 6917/// LowerOperation - Provide custom lowering hooks for some operations. 6918/// 6919SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 6920 switch (Op.getOpcode()) { 6921 default: llvm_unreachable("Should not custom lower this!"); 6922 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 6923 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 6924 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 6925 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 6926 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 6927 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 6928 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 6929 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 6930 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 6931 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 6932 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 6933 case ISD::SHL_PARTS: 6934 case ISD::SRA_PARTS: 6935 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 6936 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 6937 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 6938 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 6939 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 6940 case ISD::FABS: return LowerFABS(Op, DAG); 6941 case ISD::FNEG: return LowerFNEG(Op, DAG); 6942 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 6943 case ISD::SETCC: return LowerSETCC(Op, DAG); 6944 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 6945 case ISD::SELECT: return LowerSELECT(Op, DAG); 6946 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 6947 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 6948 case ISD::VASTART: return LowerVASTART(Op, DAG); 6949 case ISD::VAARG: return LowerVAARG(Op, DAG); 6950 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 6951 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 6952 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 6953 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 6954 case ISD::FRAME_TO_ARGS_OFFSET: 6955 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 6956 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 6957 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 6958 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 6959 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 6960 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 6961 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 6962 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 6963 case ISD::SADDO: 6964 case ISD::UADDO: 6965 case ISD::SSUBO: 6966 case ISD::USUBO: 6967 case ISD::SMULO: 6968 case ISD::UMULO: return LowerXALUO(Op, DAG); 6969 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 6970 } 6971} 6972 6973void X86TargetLowering:: 6974ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 6975 SelectionDAG &DAG, unsigned NewOp) { 6976 EVT T = Node->getValueType(0); 6977 DebugLoc dl = Node->getDebugLoc(); 6978 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 6979 6980 SDValue Chain = Node->getOperand(0); 6981 SDValue In1 = Node->getOperand(1); 6982 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6983 Node->getOperand(2), DAG.getIntPtrConstant(0)); 6984 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 6985 Node->getOperand(2), DAG.getIntPtrConstant(1)); 6986 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't 6987 // have a MemOperand. Pass the info through as a normal operand. 6988 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); 6989 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; 6990 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 6991 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5); 6992 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 6993 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 6994 Results.push_back(Result.getValue(2)); 6995} 6996 6997/// ReplaceNodeResults - Replace a node with an illegal result type 6998/// with a new node built out of custom code. 6999void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7000 SmallVectorImpl<SDValue>&Results, 7001 SelectionDAG &DAG) { 7002 DebugLoc dl = N->getDebugLoc(); 7003 switch (N->getOpcode()) { 7004 default: 7005 assert(false && "Do not know how to custom type legalize this operation!"); 7006 return; 7007 case ISD::FP_TO_SINT: { 7008 std::pair<SDValue,SDValue> Vals = 7009 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7010 SDValue FIST = Vals.first, StackSlot = Vals.second; 7011 if (FIST.getNode() != 0) { 7012 EVT VT = N->getValueType(0); 7013 // Return a load from the stack slot. 7014 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0)); 7015 } 7016 return; 7017 } 7018 case ISD::READCYCLECOUNTER: { 7019 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7020 SDValue TheChain = N->getOperand(0); 7021 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7022 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7023 rd.getValue(1)); 7024 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7025 eax.getValue(2)); 7026 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7027 SDValue Ops[] = { eax, edx }; 7028 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7029 Results.push_back(edx.getValue(1)); 7030 return; 7031 } 7032 case ISD::ATOMIC_CMP_SWAP: { 7033 EVT T = N->getValueType(0); 7034 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7035 SDValue cpInL, cpInH; 7036 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7037 DAG.getConstant(0, MVT::i32)); 7038 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7039 DAG.getConstant(1, MVT::i32)); 7040 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7041 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7042 cpInL.getValue(1)); 7043 SDValue swapInL, swapInH; 7044 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7045 DAG.getConstant(0, MVT::i32)); 7046 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7047 DAG.getConstant(1, MVT::i32)); 7048 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7049 cpInH.getValue(1)); 7050 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7051 swapInL.getValue(1)); 7052 SDValue Ops[] = { swapInH.getValue(0), 7053 N->getOperand(1), 7054 swapInH.getValue(1) }; 7055 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7056 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7057 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7058 MVT::i32, Result.getValue(1)); 7059 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7060 MVT::i32, cpOutL.getValue(2)); 7061 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7062 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7063 Results.push_back(cpOutH.getValue(1)); 7064 return; 7065 } 7066 case ISD::ATOMIC_LOAD_ADD: 7067 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7068 return; 7069 case ISD::ATOMIC_LOAD_AND: 7070 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7071 return; 7072 case ISD::ATOMIC_LOAD_NAND: 7073 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7074 return; 7075 case ISD::ATOMIC_LOAD_OR: 7076 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7077 return; 7078 case ISD::ATOMIC_LOAD_SUB: 7079 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7080 return; 7081 case ISD::ATOMIC_LOAD_XOR: 7082 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7083 return; 7084 case ISD::ATOMIC_SWAP: 7085 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7086 return; 7087 } 7088} 7089 7090const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7091 switch (Opcode) { 7092 default: return NULL; 7093 case X86ISD::BSF: return "X86ISD::BSF"; 7094 case X86ISD::BSR: return "X86ISD::BSR"; 7095 case X86ISD::SHLD: return "X86ISD::SHLD"; 7096 case X86ISD::SHRD: return "X86ISD::SHRD"; 7097 case X86ISD::FAND: return "X86ISD::FAND"; 7098 case X86ISD::FOR: return "X86ISD::FOR"; 7099 case X86ISD::FXOR: return "X86ISD::FXOR"; 7100 case X86ISD::FSRL: return "X86ISD::FSRL"; 7101 case X86ISD::FILD: return "X86ISD::FILD"; 7102 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7103 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7104 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7105 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7106 case X86ISD::FLD: return "X86ISD::FLD"; 7107 case X86ISD::FST: return "X86ISD::FST"; 7108 case X86ISD::CALL: return "X86ISD::CALL"; 7109 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7110 case X86ISD::BT: return "X86ISD::BT"; 7111 case X86ISD::CMP: return "X86ISD::CMP"; 7112 case X86ISD::COMI: return "X86ISD::COMI"; 7113 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7114 case X86ISD::SETCC: return "X86ISD::SETCC"; 7115 case X86ISD::CMOV: return "X86ISD::CMOV"; 7116 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7117 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7118 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7119 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7120 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7121 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7122 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7123 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7124 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7125 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7126 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7127 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7128 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7129 case X86ISD::FMAX: return "X86ISD::FMAX"; 7130 case X86ISD::FMIN: return "X86ISD::FMIN"; 7131 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7132 case X86ISD::FRCP: return "X86ISD::FRCP"; 7133 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7134 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7135 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7136 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7137 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7138 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7139 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7140 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7141 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7142 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7143 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7144 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7145 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7146 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7147 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7148 case X86ISD::VSHL: return "X86ISD::VSHL"; 7149 case X86ISD::VSRL: return "X86ISD::VSRL"; 7150 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7151 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7152 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7153 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7154 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7155 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7156 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7157 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7158 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7159 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7160 case X86ISD::ADD: return "X86ISD::ADD"; 7161 case X86ISD::SUB: return "X86ISD::SUB"; 7162 case X86ISD::SMUL: return "X86ISD::SMUL"; 7163 case X86ISD::UMUL: return "X86ISD::UMUL"; 7164 case X86ISD::INC: return "X86ISD::INC"; 7165 case X86ISD::DEC: return "X86ISD::DEC"; 7166 case X86ISD::OR: return "X86ISD::OR"; 7167 case X86ISD::XOR: return "X86ISD::XOR"; 7168 case X86ISD::AND: return "X86ISD::AND"; 7169 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7170 case X86ISD::PTEST: return "X86ISD::PTEST"; 7171 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7172 } 7173} 7174 7175// isLegalAddressingMode - Return true if the addressing mode represented 7176// by AM is legal for this target, for a load/store of the specified type. 7177bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7178 const Type *Ty) const { 7179 // X86 supports extremely general addressing modes. 7180 CodeModel::Model M = getTargetMachine().getCodeModel(); 7181 7182 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7183 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7184 return false; 7185 7186 if (AM.BaseGV) { 7187 unsigned GVFlags = 7188 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7189 7190 // If a reference to this global requires an extra load, we can't fold it. 7191 if (isGlobalStubReference(GVFlags)) 7192 return false; 7193 7194 // If BaseGV requires a register for the PIC base, we cannot also have a 7195 // BaseReg specified. 7196 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7197 return false; 7198 7199 // If lower 4G is not available, then we must use rip-relative addressing. 7200 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7201 return false; 7202 } 7203 7204 switch (AM.Scale) { 7205 case 0: 7206 case 1: 7207 case 2: 7208 case 4: 7209 case 8: 7210 // These scales always work. 7211 break; 7212 case 3: 7213 case 5: 7214 case 9: 7215 // These scales are formed with basereg+scalereg. Only accept if there is 7216 // no basereg yet. 7217 if (AM.HasBaseReg) 7218 return false; 7219 break; 7220 default: // Other stuff never works. 7221 return false; 7222 } 7223 7224 return true; 7225} 7226 7227 7228bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7229 if (!Ty1->isInteger() || !Ty2->isInteger()) 7230 return false; 7231 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7232 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7233 if (NumBits1 <= NumBits2) 7234 return false; 7235 return Subtarget->is64Bit() || NumBits1 < 64; 7236} 7237 7238bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7239 if (!VT1.isInteger() || !VT2.isInteger()) 7240 return false; 7241 unsigned NumBits1 = VT1.getSizeInBits(); 7242 unsigned NumBits2 = VT2.getSizeInBits(); 7243 if (NumBits1 <= NumBits2) 7244 return false; 7245 return Subtarget->is64Bit() || NumBits1 < 64; 7246} 7247 7248bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7249 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7250 return Ty1 == Type::getInt32Ty(Ty1->getContext()) && 7251 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit(); 7252} 7253 7254bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7255 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7256 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7257} 7258 7259bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7260 // i16 instructions are longer (0x66 prefix) and potentially slower. 7261 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7262} 7263 7264/// isShuffleMaskLegal - Targets can use this to indicate that they only 7265/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7266/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7267/// are assumed to be legal. 7268bool 7269X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7270 EVT VT) const { 7271 // Only do shuffles on 128-bit vector types for now. 7272 if (VT.getSizeInBits() == 64) 7273 return false; 7274 7275 // FIXME: pshufb, blends, palignr, shifts. 7276 return (VT.getVectorNumElements() == 2 || 7277 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7278 isMOVLMask(M, VT) || 7279 isSHUFPMask(M, VT) || 7280 isPSHUFDMask(M, VT) || 7281 isPSHUFHWMask(M, VT) || 7282 isPSHUFLWMask(M, VT) || 7283 isUNPCKLMask(M, VT) || 7284 isUNPCKHMask(M, VT) || 7285 isUNPCKL_v_undef_Mask(M, VT) || 7286 isUNPCKH_v_undef_Mask(M, VT)); 7287} 7288 7289bool 7290X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7291 EVT VT) const { 7292 unsigned NumElts = VT.getVectorNumElements(); 7293 // FIXME: This collection of masks seems suspect. 7294 if (NumElts == 2) 7295 return true; 7296 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7297 return (isMOVLMask(Mask, VT) || 7298 isCommutedMOVLMask(Mask, VT, true) || 7299 isSHUFPMask(Mask, VT) || 7300 isCommutedSHUFPMask(Mask, VT)); 7301 } 7302 return false; 7303} 7304 7305//===----------------------------------------------------------------------===// 7306// X86 Scheduler Hooks 7307//===----------------------------------------------------------------------===// 7308 7309// private utility function 7310MachineBasicBlock * 7311X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7312 MachineBasicBlock *MBB, 7313 unsigned regOpc, 7314 unsigned immOpc, 7315 unsigned LoadOpc, 7316 unsigned CXchgOpc, 7317 unsigned copyOpc, 7318 unsigned notOpc, 7319 unsigned EAXreg, 7320 TargetRegisterClass *RC, 7321 bool invSrc) const { 7322 // For the atomic bitwise operator, we generate 7323 // thisMBB: 7324 // newMBB: 7325 // ld t1 = [bitinstr.addr] 7326 // op t2 = t1, [bitinstr.val] 7327 // mov EAX = t1 7328 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7329 // bz newMBB 7330 // fallthrough -->nextMBB 7331 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7332 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7333 MachineFunction::iterator MBBIter = MBB; 7334 ++MBBIter; 7335 7336 /// First build the CFG 7337 MachineFunction *F = MBB->getParent(); 7338 MachineBasicBlock *thisMBB = MBB; 7339 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7340 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7341 F->insert(MBBIter, newMBB); 7342 F->insert(MBBIter, nextMBB); 7343 7344 // Move all successors to thisMBB to nextMBB 7345 nextMBB->transferSuccessors(thisMBB); 7346 7347 // Update thisMBB to fall through to newMBB 7348 thisMBB->addSuccessor(newMBB); 7349 7350 // newMBB jumps to itself and fall through to nextMBB 7351 newMBB->addSuccessor(nextMBB); 7352 newMBB->addSuccessor(newMBB); 7353 7354 // Insert instructions into newMBB based on incoming instruction 7355 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 7356 "unexpected number of operands"); 7357 DebugLoc dl = bInstr->getDebugLoc(); 7358 MachineOperand& destOper = bInstr->getOperand(0); 7359 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7360 int numArgs = bInstr->getNumOperands() - 1; 7361 for (int i=0; i < numArgs; ++i) 7362 argOpers[i] = &bInstr->getOperand(i+1); 7363 7364 // x86 address has 4 operands: base, index, scale, and displacement 7365 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7366 int valArgIndx = lastAddrIndx + 1; 7367 7368 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7369 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7370 for (int i=0; i <= lastAddrIndx; ++i) 7371 (*MIB).addOperand(*argOpers[i]); 7372 7373 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7374 if (invSrc) { 7375 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7376 } 7377 else 7378 tt = t1; 7379 7380 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7381 assert((argOpers[valArgIndx]->isReg() || 7382 argOpers[valArgIndx]->isImm()) && 7383 "invalid operand"); 7384 if (argOpers[valArgIndx]->isReg()) 7385 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7386 else 7387 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7388 MIB.addReg(tt); 7389 (*MIB).addOperand(*argOpers[valArgIndx]); 7390 7391 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7392 MIB.addReg(t1); 7393 7394 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7395 for (int i=0; i <= lastAddrIndx; ++i) 7396 (*MIB).addOperand(*argOpers[i]); 7397 MIB.addReg(t2); 7398 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7399 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7400 7401 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7402 MIB.addReg(EAXreg); 7403 7404 // insert branch 7405 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7406 7407 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7408 return nextMBB; 7409} 7410 7411// private utility function: 64 bit atomics on 32 bit host. 7412MachineBasicBlock * 7413X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 7414 MachineBasicBlock *MBB, 7415 unsigned regOpcL, 7416 unsigned regOpcH, 7417 unsigned immOpcL, 7418 unsigned immOpcH, 7419 bool invSrc) const { 7420 // For the atomic bitwise operator, we generate 7421 // thisMBB (instructions are in pairs, except cmpxchg8b) 7422 // ld t1,t2 = [bitinstr.addr] 7423 // newMBB: 7424 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 7425 // op t5, t6 <- out1, out2, [bitinstr.val] 7426 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 7427 // mov ECX, EBX <- t5, t6 7428 // mov EAX, EDX <- t1, t2 7429 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 7430 // mov t3, t4 <- EAX, EDX 7431 // bz newMBB 7432 // result in out1, out2 7433 // fallthrough -->nextMBB 7434 7435 const TargetRegisterClass *RC = X86::GR32RegisterClass; 7436 const unsigned LoadOpc = X86::MOV32rm; 7437 const unsigned copyOpc = X86::MOV32rr; 7438 const unsigned NotOpc = X86::NOT32r; 7439 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7440 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7441 MachineFunction::iterator MBBIter = MBB; 7442 ++MBBIter; 7443 7444 /// First build the CFG 7445 MachineFunction *F = MBB->getParent(); 7446 MachineBasicBlock *thisMBB = MBB; 7447 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7448 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7449 F->insert(MBBIter, newMBB); 7450 F->insert(MBBIter, nextMBB); 7451 7452 // Move all successors to thisMBB to nextMBB 7453 nextMBB->transferSuccessors(thisMBB); 7454 7455 // Update thisMBB to fall through to newMBB 7456 thisMBB->addSuccessor(newMBB); 7457 7458 // newMBB jumps to itself and fall through to nextMBB 7459 newMBB->addSuccessor(nextMBB); 7460 newMBB->addSuccessor(newMBB); 7461 7462 DebugLoc dl = bInstr->getDebugLoc(); 7463 // Insert instructions into newMBB based on incoming instruction 7464 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 7465 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 7466 "unexpected number of operands"); 7467 MachineOperand& dest1Oper = bInstr->getOperand(0); 7468 MachineOperand& dest2Oper = bInstr->getOperand(1); 7469 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7470 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 7471 argOpers[i] = &bInstr->getOperand(i+2); 7472 7473 // x86 address has 4 operands: base, index, scale, and displacement 7474 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7475 7476 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7477 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 7478 for (int i=0; i <= lastAddrIndx; ++i) 7479 (*MIB).addOperand(*argOpers[i]); 7480 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7481 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 7482 // add 4 to displacement. 7483 for (int i=0; i <= lastAddrIndx-2; ++i) 7484 (*MIB).addOperand(*argOpers[i]); 7485 MachineOperand newOp3 = *(argOpers[3]); 7486 if (newOp3.isImm()) 7487 newOp3.setImm(newOp3.getImm()+4); 7488 else 7489 newOp3.setOffset(newOp3.getOffset()+4); 7490 (*MIB).addOperand(newOp3); 7491 (*MIB).addOperand(*argOpers[lastAddrIndx]); 7492 7493 // t3/4 are defined later, at the bottom of the loop 7494 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 7495 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 7496 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 7497 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 7498 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 7499 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 7500 7501 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC); 7502 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC); 7503 if (invSrc) { 7504 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1); 7505 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2); 7506 } else { 7507 tt1 = t1; 7508 tt2 = t2; 7509 } 7510 7511 int valArgIndx = lastAddrIndx + 1; 7512 assert((argOpers[valArgIndx]->isReg() || 7513 argOpers[valArgIndx]->isImm()) && 7514 "invalid operand"); 7515 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 7516 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 7517 if (argOpers[valArgIndx]->isReg()) 7518 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 7519 else 7520 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 7521 if (regOpcL != X86::MOV32rr) 7522 MIB.addReg(tt1); 7523 (*MIB).addOperand(*argOpers[valArgIndx]); 7524 assert(argOpers[valArgIndx + 1]->isReg() == 7525 argOpers[valArgIndx]->isReg()); 7526 assert(argOpers[valArgIndx + 1]->isImm() == 7527 argOpers[valArgIndx]->isImm()); 7528 if (argOpers[valArgIndx + 1]->isReg()) 7529 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 7530 else 7531 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 7532 if (regOpcH != X86::MOV32rr) 7533 MIB.addReg(tt2); 7534 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 7535 7536 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 7537 MIB.addReg(t1); 7538 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 7539 MIB.addReg(t2); 7540 7541 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 7542 MIB.addReg(t5); 7543 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 7544 MIB.addReg(t6); 7545 7546 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 7547 for (int i=0; i <= lastAddrIndx; ++i) 7548 (*MIB).addOperand(*argOpers[i]); 7549 7550 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7551 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin()); 7552 7553 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 7554 MIB.addReg(X86::EAX); 7555 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 7556 MIB.addReg(X86::EDX); 7557 7558 // insert branch 7559 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7560 7561 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7562 return nextMBB; 7563} 7564 7565// private utility function 7566MachineBasicBlock * 7567X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 7568 MachineBasicBlock *MBB, 7569 unsigned cmovOpc) const { 7570 // For the atomic min/max operator, we generate 7571 // thisMBB: 7572 // newMBB: 7573 // ld t1 = [min/max.addr] 7574 // mov t2 = [min/max.val] 7575 // cmp t1, t2 7576 // cmov[cond] t2 = t1 7577 // mov EAX = t1 7578 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7579 // bz newMBB 7580 // fallthrough -->nextMBB 7581 // 7582 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7583 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7584 MachineFunction::iterator MBBIter = MBB; 7585 ++MBBIter; 7586 7587 /// First build the CFG 7588 MachineFunction *F = MBB->getParent(); 7589 MachineBasicBlock *thisMBB = MBB; 7590 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7591 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7592 F->insert(MBBIter, newMBB); 7593 F->insert(MBBIter, nextMBB); 7594 7595 // Move all successors of thisMBB to nextMBB 7596 nextMBB->transferSuccessors(thisMBB); 7597 7598 // Update thisMBB to fall through to newMBB 7599 thisMBB->addSuccessor(newMBB); 7600 7601 // newMBB jumps to newMBB and fall through to nextMBB 7602 newMBB->addSuccessor(nextMBB); 7603 newMBB->addSuccessor(newMBB); 7604 7605 DebugLoc dl = mInstr->getDebugLoc(); 7606 // Insert instructions into newMBB based on incoming instruction 7607 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 7608 "unexpected number of operands"); 7609 MachineOperand& destOper = mInstr->getOperand(0); 7610 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7611 int numArgs = mInstr->getNumOperands() - 1; 7612 for (int i=0; i < numArgs; ++i) 7613 argOpers[i] = &mInstr->getOperand(i+1); 7614 7615 // x86 address has 4 operands: base, index, scale, and displacement 7616 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7617 int valArgIndx = lastAddrIndx + 1; 7618 7619 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7620 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 7621 for (int i=0; i <= lastAddrIndx; ++i) 7622 (*MIB).addOperand(*argOpers[i]); 7623 7624 // We only support register and immediate values 7625 assert((argOpers[valArgIndx]->isReg() || 7626 argOpers[valArgIndx]->isImm()) && 7627 "invalid operand"); 7628 7629 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7630 if (argOpers[valArgIndx]->isReg()) 7631 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7632 else 7633 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 7634 (*MIB).addOperand(*argOpers[valArgIndx]); 7635 7636 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 7637 MIB.addReg(t1); 7638 7639 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 7640 MIB.addReg(t1); 7641 MIB.addReg(t2); 7642 7643 // Generate movc 7644 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 7645 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 7646 MIB.addReg(t2); 7647 MIB.addReg(t1); 7648 7649 // Cmp and exchange if none has modified the memory location 7650 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 7651 for (int i=0; i <= lastAddrIndx; ++i) 7652 (*MIB).addOperand(*argOpers[i]); 7653 MIB.addReg(t3); 7654 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7655 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin()); 7656 7657 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 7658 MIB.addReg(X86::EAX); 7659 7660 // insert branch 7661 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB); 7662 7663 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 7664 return nextMBB; 7665} 7666 7667// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 7668// all of this code can be replaced with that in the .td file. 7669MachineBasicBlock * 7670X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 7671 unsigned numArgs, bool memArg) const { 7672 7673 MachineFunction *F = BB->getParent(); 7674 DebugLoc dl = MI->getDebugLoc(); 7675 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7676 7677 unsigned Opc; 7678 if (memArg) 7679 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 7680 else 7681 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 7682 7683 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 7684 7685 for (unsigned i = 0; i < numArgs; ++i) { 7686 MachineOperand &Op = MI->getOperand(i+1); 7687 7688 if (!(Op.isReg() && Op.isImplicit())) 7689 MIB.addOperand(Op); 7690 } 7691 7692 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 7693 .addReg(X86::XMM0); 7694 7695 F->DeleteMachineInstr(MI); 7696 7697 return BB; 7698} 7699 7700MachineBasicBlock * 7701X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 7702 MachineInstr *MI, 7703 MachineBasicBlock *MBB) const { 7704 // Emit code to save XMM registers to the stack. The ABI says that the 7705 // number of registers to save is given in %al, so it's theoretically 7706 // possible to do an indirect jump trick to avoid saving all of them, 7707 // however this code takes a simpler approach and just executes all 7708 // of the stores if %al is non-zero. It's less code, and it's probably 7709 // easier on the hardware branch predictor, and stores aren't all that 7710 // expensive anyway. 7711 7712 // Create the new basic blocks. One block contains all the XMM stores, 7713 // and one block is the final destination regardless of whether any 7714 // stores were performed. 7715 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7716 MachineFunction *F = MBB->getParent(); 7717 MachineFunction::iterator MBBIter = MBB; 7718 ++MBBIter; 7719 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 7720 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 7721 F->insert(MBBIter, XMMSaveMBB); 7722 F->insert(MBBIter, EndMBB); 7723 7724 // Set up the CFG. 7725 // Move any original successors of MBB to the end block. 7726 EndMBB->transferSuccessors(MBB); 7727 // The original block will now fall through to the XMM save block. 7728 MBB->addSuccessor(XMMSaveMBB); 7729 // The XMMSaveMBB will fall through to the end block. 7730 XMMSaveMBB->addSuccessor(EndMBB); 7731 7732 // Now add the instructions. 7733 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7734 DebugLoc DL = MI->getDebugLoc(); 7735 7736 unsigned CountReg = MI->getOperand(0).getReg(); 7737 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 7738 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 7739 7740 if (!Subtarget->isTargetWin64()) { 7741 // If %al is 0, branch around the XMM save block. 7742 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 7743 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB); 7744 MBB->addSuccessor(EndMBB); 7745 } 7746 7747 // In the XMM save block, save all the XMM argument registers. 7748 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 7749 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 7750 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 7751 .addFrameIndex(RegSaveFrameIndex) 7752 .addImm(/*Scale=*/1) 7753 .addReg(/*IndexReg=*/0) 7754 .addImm(/*Disp=*/Offset) 7755 .addReg(/*Segment=*/0) 7756 .addReg(MI->getOperand(i).getReg()) 7757 .addMemOperand(MachineMemOperand( 7758 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 7759 MachineMemOperand::MOStore, Offset, 7760 /*Size=*/16, /*Align=*/16)); 7761 } 7762 7763 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7764 7765 return EndMBB; 7766} 7767 7768MachineBasicBlock * 7769X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 7770 MachineBasicBlock *BB, 7771 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 7772 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7773 DebugLoc DL = MI->getDebugLoc(); 7774 7775 // To "insert" a SELECT_CC instruction, we actually have to insert the 7776 // diamond control-flow pattern. The incoming instruction knows the 7777 // destination vreg to set, the condition code register to branch on, the 7778 // true/false values to select between, and a branch opcode to use. 7779 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 7780 MachineFunction::iterator It = BB; 7781 ++It; 7782 7783 // thisMBB: 7784 // ... 7785 // TrueVal = ... 7786 // cmpTY ccX, r1, r2 7787 // bCC copy1MBB 7788 // fallthrough --> copy0MBB 7789 MachineBasicBlock *thisMBB = BB; 7790 MachineFunction *F = BB->getParent(); 7791 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 7792 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 7793 unsigned Opc = 7794 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 7795 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 7796 F->insert(It, copy0MBB); 7797 F->insert(It, sinkMBB); 7798 // Update machine-CFG edges by first adding all successors of the current 7799 // block to the new block which will contain the Phi node for the select. 7800 // Also inform sdisel of the edge changes. 7801 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 7802 E = BB->succ_end(); I != E; ++I) { 7803 EM->insert(std::make_pair(*I, sinkMBB)); 7804 sinkMBB->addSuccessor(*I); 7805 } 7806 // Next, remove all successors of the current block, and add the true 7807 // and fallthrough blocks as its successors. 7808 while (!BB->succ_empty()) 7809 BB->removeSuccessor(BB->succ_begin()); 7810 // Add the true and fallthrough blocks as its successors. 7811 BB->addSuccessor(copy0MBB); 7812 BB->addSuccessor(sinkMBB); 7813 7814 // copy0MBB: 7815 // %FalseValue = ... 7816 // # fallthrough to sinkMBB 7817 BB = copy0MBB; 7818 7819 // Update machine-CFG edges 7820 BB->addSuccessor(sinkMBB); 7821 7822 // sinkMBB: 7823 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 7824 // ... 7825 BB = sinkMBB; 7826 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) 7827 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 7828 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 7829 7830 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7831 return BB; 7832} 7833 7834 7835MachineBasicBlock * 7836X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 7837 MachineBasicBlock *BB, 7838 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 7839 switch (MI->getOpcode()) { 7840 default: assert(false && "Unexpected instr type to insert"); 7841 case X86::CMOV_GR8: 7842 case X86::CMOV_V1I64: 7843 case X86::CMOV_FR32: 7844 case X86::CMOV_FR64: 7845 case X86::CMOV_V4F32: 7846 case X86::CMOV_V2F64: 7847 case X86::CMOV_V2I64: 7848 return EmitLoweredSelect(MI, BB, EM); 7849 7850 case X86::FP32_TO_INT16_IN_MEM: 7851 case X86::FP32_TO_INT32_IN_MEM: 7852 case X86::FP32_TO_INT64_IN_MEM: 7853 case X86::FP64_TO_INT16_IN_MEM: 7854 case X86::FP64_TO_INT32_IN_MEM: 7855 case X86::FP64_TO_INT64_IN_MEM: 7856 case X86::FP80_TO_INT16_IN_MEM: 7857 case X86::FP80_TO_INT32_IN_MEM: 7858 case X86::FP80_TO_INT64_IN_MEM: { 7859 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7860 DebugLoc DL = MI->getDebugLoc(); 7861 7862 // Change the floating point control register to use "round towards zero" 7863 // mode when truncating to an integer value. 7864 MachineFunction *F = BB->getParent(); 7865 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); 7866 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); 7867 7868 // Load the old value of the high byte of the control word... 7869 unsigned OldCW = 7870 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 7871 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), 7872 CWFrameIdx); 7873 7874 // Set the high part to be round to zero... 7875 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 7876 .addImm(0xC7F); 7877 7878 // Reload the modified control word now... 7879 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 7880 7881 // Restore the memory image of control word to original value 7882 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 7883 .addReg(OldCW); 7884 7885 // Get the X86 opcode to use. 7886 unsigned Opc; 7887 switch (MI->getOpcode()) { 7888 default: llvm_unreachable("illegal opcode!"); 7889 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 7890 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 7891 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 7892 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 7893 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 7894 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 7895 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 7896 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 7897 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 7898 } 7899 7900 X86AddressMode AM; 7901 MachineOperand &Op = MI->getOperand(0); 7902 if (Op.isReg()) { 7903 AM.BaseType = X86AddressMode::RegBase; 7904 AM.Base.Reg = Op.getReg(); 7905 } else { 7906 AM.BaseType = X86AddressMode::FrameIndexBase; 7907 AM.Base.FrameIndex = Op.getIndex(); 7908 } 7909 Op = MI->getOperand(1); 7910 if (Op.isImm()) 7911 AM.Scale = Op.getImm(); 7912 Op = MI->getOperand(2); 7913 if (Op.isImm()) 7914 AM.IndexReg = Op.getImm(); 7915 Op = MI->getOperand(3); 7916 if (Op.isGlobal()) { 7917 AM.GV = Op.getGlobal(); 7918 } else { 7919 AM.Disp = Op.getImm(); 7920 } 7921 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) 7922 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 7923 7924 // Reload the original control word now. 7925 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 7926 7927 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 7928 return BB; 7929 } 7930 // String/text processing lowering. 7931 case X86::PCMPISTRM128REG: 7932 return EmitPCMP(MI, BB, 3, false /* in-mem */); 7933 case X86::PCMPISTRM128MEM: 7934 return EmitPCMP(MI, BB, 3, true /* in-mem */); 7935 case X86::PCMPESTRM128REG: 7936 return EmitPCMP(MI, BB, 5, false /* in mem */); 7937 case X86::PCMPESTRM128MEM: 7938 return EmitPCMP(MI, BB, 5, true /* in mem */); 7939 7940 // Atomic Lowering. 7941 case X86::ATOMAND32: 7942 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7943 X86::AND32ri, X86::MOV32rm, 7944 X86::LCMPXCHG32, X86::MOV32rr, 7945 X86::NOT32r, X86::EAX, 7946 X86::GR32RegisterClass); 7947 case X86::ATOMOR32: 7948 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 7949 X86::OR32ri, X86::MOV32rm, 7950 X86::LCMPXCHG32, X86::MOV32rr, 7951 X86::NOT32r, X86::EAX, 7952 X86::GR32RegisterClass); 7953 case X86::ATOMXOR32: 7954 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 7955 X86::XOR32ri, X86::MOV32rm, 7956 X86::LCMPXCHG32, X86::MOV32rr, 7957 X86::NOT32r, X86::EAX, 7958 X86::GR32RegisterClass); 7959 case X86::ATOMNAND32: 7960 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 7961 X86::AND32ri, X86::MOV32rm, 7962 X86::LCMPXCHG32, X86::MOV32rr, 7963 X86::NOT32r, X86::EAX, 7964 X86::GR32RegisterClass, true); 7965 case X86::ATOMMIN32: 7966 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 7967 case X86::ATOMMAX32: 7968 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 7969 case X86::ATOMUMIN32: 7970 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 7971 case X86::ATOMUMAX32: 7972 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 7973 7974 case X86::ATOMAND16: 7975 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7976 X86::AND16ri, X86::MOV16rm, 7977 X86::LCMPXCHG16, X86::MOV16rr, 7978 X86::NOT16r, X86::AX, 7979 X86::GR16RegisterClass); 7980 case X86::ATOMOR16: 7981 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 7982 X86::OR16ri, X86::MOV16rm, 7983 X86::LCMPXCHG16, X86::MOV16rr, 7984 X86::NOT16r, X86::AX, 7985 X86::GR16RegisterClass); 7986 case X86::ATOMXOR16: 7987 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 7988 X86::XOR16ri, X86::MOV16rm, 7989 X86::LCMPXCHG16, X86::MOV16rr, 7990 X86::NOT16r, X86::AX, 7991 X86::GR16RegisterClass); 7992 case X86::ATOMNAND16: 7993 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 7994 X86::AND16ri, X86::MOV16rm, 7995 X86::LCMPXCHG16, X86::MOV16rr, 7996 X86::NOT16r, X86::AX, 7997 X86::GR16RegisterClass, true); 7998 case X86::ATOMMIN16: 7999 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8000 case X86::ATOMMAX16: 8001 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8002 case X86::ATOMUMIN16: 8003 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8004 case X86::ATOMUMAX16: 8005 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8006 8007 case X86::ATOMAND8: 8008 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8009 X86::AND8ri, X86::MOV8rm, 8010 X86::LCMPXCHG8, X86::MOV8rr, 8011 X86::NOT8r, X86::AL, 8012 X86::GR8RegisterClass); 8013 case X86::ATOMOR8: 8014 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8015 X86::OR8ri, X86::MOV8rm, 8016 X86::LCMPXCHG8, X86::MOV8rr, 8017 X86::NOT8r, X86::AL, 8018 X86::GR8RegisterClass); 8019 case X86::ATOMXOR8: 8020 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8021 X86::XOR8ri, X86::MOV8rm, 8022 X86::LCMPXCHG8, X86::MOV8rr, 8023 X86::NOT8r, X86::AL, 8024 X86::GR8RegisterClass); 8025 case X86::ATOMNAND8: 8026 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8027 X86::AND8ri, X86::MOV8rm, 8028 X86::LCMPXCHG8, X86::MOV8rr, 8029 X86::NOT8r, X86::AL, 8030 X86::GR8RegisterClass, true); 8031 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8032 // This group is for 64-bit host. 8033 case X86::ATOMAND64: 8034 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8035 X86::AND64ri32, X86::MOV64rm, 8036 X86::LCMPXCHG64, X86::MOV64rr, 8037 X86::NOT64r, X86::RAX, 8038 X86::GR64RegisterClass); 8039 case X86::ATOMOR64: 8040 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8041 X86::OR64ri32, X86::MOV64rm, 8042 X86::LCMPXCHG64, X86::MOV64rr, 8043 X86::NOT64r, X86::RAX, 8044 X86::GR64RegisterClass); 8045 case X86::ATOMXOR64: 8046 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8047 X86::XOR64ri32, X86::MOV64rm, 8048 X86::LCMPXCHG64, X86::MOV64rr, 8049 X86::NOT64r, X86::RAX, 8050 X86::GR64RegisterClass); 8051 case X86::ATOMNAND64: 8052 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8053 X86::AND64ri32, X86::MOV64rm, 8054 X86::LCMPXCHG64, X86::MOV64rr, 8055 X86::NOT64r, X86::RAX, 8056 X86::GR64RegisterClass, true); 8057 case X86::ATOMMIN64: 8058 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8059 case X86::ATOMMAX64: 8060 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8061 case X86::ATOMUMIN64: 8062 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8063 case X86::ATOMUMAX64: 8064 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8065 8066 // This group does 64-bit operations on a 32-bit host. 8067 case X86::ATOMAND6432: 8068 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8069 X86::AND32rr, X86::AND32rr, 8070 X86::AND32ri, X86::AND32ri, 8071 false); 8072 case X86::ATOMOR6432: 8073 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8074 X86::OR32rr, X86::OR32rr, 8075 X86::OR32ri, X86::OR32ri, 8076 false); 8077 case X86::ATOMXOR6432: 8078 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8079 X86::XOR32rr, X86::XOR32rr, 8080 X86::XOR32ri, X86::XOR32ri, 8081 false); 8082 case X86::ATOMNAND6432: 8083 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8084 X86::AND32rr, X86::AND32rr, 8085 X86::AND32ri, X86::AND32ri, 8086 true); 8087 case X86::ATOMADD6432: 8088 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8089 X86::ADD32rr, X86::ADC32rr, 8090 X86::ADD32ri, X86::ADC32ri, 8091 false); 8092 case X86::ATOMSUB6432: 8093 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8094 X86::SUB32rr, X86::SBB32rr, 8095 X86::SUB32ri, X86::SBB32ri, 8096 false); 8097 case X86::ATOMSWAP6432: 8098 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8099 X86::MOV32rr, X86::MOV32rr, 8100 X86::MOV32ri, X86::MOV32ri, 8101 false); 8102 case X86::VASTART_SAVE_XMM_REGS: 8103 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8104 } 8105} 8106 8107//===----------------------------------------------------------------------===// 8108// X86 Optimization Hooks 8109//===----------------------------------------------------------------------===// 8110 8111void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8112 const APInt &Mask, 8113 APInt &KnownZero, 8114 APInt &KnownOne, 8115 const SelectionDAG &DAG, 8116 unsigned Depth) const { 8117 unsigned Opc = Op.getOpcode(); 8118 assert((Opc >= ISD::BUILTIN_OP_END || 8119 Opc == ISD::INTRINSIC_WO_CHAIN || 8120 Opc == ISD::INTRINSIC_W_CHAIN || 8121 Opc == ISD::INTRINSIC_VOID) && 8122 "Should use MaskedValueIsZero if you don't know whether Op" 8123 " is a target node!"); 8124 8125 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8126 switch (Opc) { 8127 default: break; 8128 case X86ISD::ADD: 8129 case X86ISD::SUB: 8130 case X86ISD::SMUL: 8131 case X86ISD::UMUL: 8132 case X86ISD::INC: 8133 case X86ISD::DEC: 8134 case X86ISD::OR: 8135 case X86ISD::XOR: 8136 case X86ISD::AND: 8137 // These nodes' second result is a boolean. 8138 if (Op.getResNo() == 0) 8139 break; 8140 // Fallthrough 8141 case X86ISD::SETCC: 8142 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8143 Mask.getBitWidth() - 1); 8144 break; 8145 } 8146} 8147 8148/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8149/// node is a GlobalAddress + offset. 8150bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8151 GlobalValue* &GA, int64_t &Offset) const{ 8152 if (N->getOpcode() == X86ISD::Wrapper) { 8153 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8154 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8155 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8156 return true; 8157 } 8158 } 8159 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8160} 8161 8162static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, 8163 const TargetLowering &TLI) { 8164 GlobalValue *GV; 8165 int64_t Offset = 0; 8166 if (TLI.isGAPlusOffset(Base, GV, Offset)) 8167 return (GV->getAlignment() >= N && (Offset % N) == 0); 8168 // DAG combine handles the stack object case. 8169 return false; 8170} 8171 8172static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, 8173 EVT EVT, LoadSDNode *&LDBase, 8174 unsigned &LastLoadedElt, 8175 SelectionDAG &DAG, MachineFrameInfo *MFI, 8176 const TargetLowering &TLI) { 8177 LDBase = NULL; 8178 LastLoadedElt = -1U; 8179 for (unsigned i = 0; i < NumElems; ++i) { 8180 if (N->getMaskElt(i) < 0) { 8181 if (!LDBase) 8182 return false; 8183 continue; 8184 } 8185 8186 SDValue Elt = DAG.getShuffleScalarElt(N, i); 8187 if (!Elt.getNode() || 8188 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 8189 return false; 8190 if (!LDBase) { 8191 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 8192 return false; 8193 LDBase = cast<LoadSDNode>(Elt.getNode()); 8194 LastLoadedElt = i; 8195 continue; 8196 } 8197 if (Elt.getOpcode() == ISD::UNDEF) 8198 continue; 8199 8200 LoadSDNode *LD = cast<LoadSDNode>(Elt); 8201 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI)) 8202 return false; 8203 LastLoadedElt = i; 8204 } 8205 return true; 8206} 8207 8208/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8209/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8210/// if the load addresses are consecutive, non-overlapping, and in the right 8211/// order. In the case of v2i64, it will see if it can rewrite the 8212/// shuffle to be an appropriate build vector so it can take advantage of 8213// performBuildVectorCombine. 8214static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8215 const TargetLowering &TLI) { 8216 DebugLoc dl = N->getDebugLoc(); 8217 EVT VT = N->getValueType(0); 8218 EVT EVT = VT.getVectorElementType(); 8219 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8220 unsigned NumElems = VT.getVectorNumElements(); 8221 8222 if (VT.getSizeInBits() != 128) 8223 return SDValue(); 8224 8225 // Try to combine a vector_shuffle into a 128-bit load. 8226 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8227 LoadSDNode *LD = NULL; 8228 unsigned LastLoadedElt; 8229 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG, 8230 MFI, TLI)) 8231 return SDValue(); 8232 8233 if (LastLoadedElt == NumElems - 1) { 8234 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI)) 8235 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8236 LD->getSrcValue(), LD->getSrcValueOffset(), 8237 LD->isVolatile()); 8238 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8239 LD->getSrcValue(), LD->getSrcValueOffset(), 8240 LD->isVolatile(), LD->getAlignment()); 8241 } else if (NumElems == 4 && LastLoadedElt == 1) { 8242 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 8243 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 8244 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 8245 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 8246 } 8247 return SDValue(); 8248} 8249 8250/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8251static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8252 const X86Subtarget *Subtarget) { 8253 DebugLoc DL = N->getDebugLoc(); 8254 SDValue Cond = N->getOperand(0); 8255 // Get the LHS/RHS of the select. 8256 SDValue LHS = N->getOperand(1); 8257 SDValue RHS = N->getOperand(2); 8258 8259 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 8260 // instructions have the peculiarity that if either operand is a NaN, 8261 // they chose what we call the RHS operand (and as such are not symmetric). 8262 // It happens that this matches the semantics of the common C idiom 8263 // x<y?x:y and related forms, so we can recognize these cases. 8264 if (Subtarget->hasSSE2() && 8265 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 8266 Cond.getOpcode() == ISD::SETCC) { 8267 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 8268 8269 unsigned Opcode = 0; 8270 // Check for x CC y ? x : y. 8271 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 8272 switch (CC) { 8273 default: break; 8274 case ISD::SETULT: 8275 // This can be a min if we can prove that at least one of the operands 8276 // is not a nan. 8277 if (!FiniteOnlyFPMath()) { 8278 if (DAG.isKnownNeverNaN(RHS)) { 8279 // Put the potential NaN in the RHS so that SSE will preserve it. 8280 std::swap(LHS, RHS); 8281 } else if (!DAG.isKnownNeverNaN(LHS)) 8282 break; 8283 } 8284 Opcode = X86ISD::FMIN; 8285 break; 8286 case ISD::SETOLE: 8287 // This can be a min if we can prove that at least one of the operands 8288 // is not a nan. 8289 if (!FiniteOnlyFPMath()) { 8290 if (DAG.isKnownNeverNaN(LHS)) { 8291 // Put the potential NaN in the RHS so that SSE will preserve it. 8292 std::swap(LHS, RHS); 8293 } else if (!DAG.isKnownNeverNaN(RHS)) 8294 break; 8295 } 8296 Opcode = X86ISD::FMIN; 8297 break; 8298 case ISD::SETULE: 8299 // This can be a min, but if either operand is a NaN we need it to 8300 // preserve the original LHS. 8301 std::swap(LHS, RHS); 8302 case ISD::SETOLT: 8303 case ISD::SETLT: 8304 case ISD::SETLE: 8305 Opcode = X86ISD::FMIN; 8306 break; 8307 8308 case ISD::SETOGE: 8309 // This can be a max if we can prove that at least one of the operands 8310 // is not a nan. 8311 if (!FiniteOnlyFPMath()) { 8312 if (DAG.isKnownNeverNaN(LHS)) { 8313 // Put the potential NaN in the RHS so that SSE will preserve it. 8314 std::swap(LHS, RHS); 8315 } else if (!DAG.isKnownNeverNaN(RHS)) 8316 break; 8317 } 8318 Opcode = X86ISD::FMAX; 8319 break; 8320 case ISD::SETUGT: 8321 // This can be a max if we can prove that at least one of the operands 8322 // is not a nan. 8323 if (!FiniteOnlyFPMath()) { 8324 if (DAG.isKnownNeverNaN(RHS)) { 8325 // Put the potential NaN in the RHS so that SSE will preserve it. 8326 std::swap(LHS, RHS); 8327 } else if (!DAG.isKnownNeverNaN(LHS)) 8328 break; 8329 } 8330 Opcode = X86ISD::FMAX; 8331 break; 8332 case ISD::SETUGE: 8333 // This can be a max, but if either operand is a NaN we need it to 8334 // preserve the original LHS. 8335 std::swap(LHS, RHS); 8336 case ISD::SETOGT: 8337 case ISD::SETGT: 8338 case ISD::SETGE: 8339 Opcode = X86ISD::FMAX; 8340 break; 8341 } 8342 // Check for x CC y ? y : x -- a min/max with reversed arms. 8343 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 8344 switch (CC) { 8345 default: break; 8346 case ISD::SETOGE: 8347 // This can be a min if we can prove that at least one of the operands 8348 // is not a nan. 8349 if (!FiniteOnlyFPMath()) { 8350 if (DAG.isKnownNeverNaN(RHS)) { 8351 // Put the potential NaN in the RHS so that SSE will preserve it. 8352 std::swap(LHS, RHS); 8353 } else if (!DAG.isKnownNeverNaN(LHS)) 8354 break; 8355 } 8356 Opcode = X86ISD::FMIN; 8357 break; 8358 case ISD::SETUGT: 8359 // This can be a min if we can prove that at least one of the operands 8360 // is not a nan. 8361 if (!FiniteOnlyFPMath()) { 8362 if (DAG.isKnownNeverNaN(LHS)) { 8363 // Put the potential NaN in the RHS so that SSE will preserve it. 8364 std::swap(LHS, RHS); 8365 } else if (!DAG.isKnownNeverNaN(RHS)) 8366 break; 8367 } 8368 Opcode = X86ISD::FMIN; 8369 break; 8370 case ISD::SETUGE: 8371 // This can be a min, but if either operand is a NaN we need it to 8372 // preserve the original LHS. 8373 std::swap(LHS, RHS); 8374 case ISD::SETOGT: 8375 case ISD::SETGT: 8376 case ISD::SETGE: 8377 Opcode = X86ISD::FMIN; 8378 break; 8379 8380 case ISD::SETULT: 8381 // This can be a max if we can prove that at least one of the operands 8382 // is not a nan. 8383 if (!FiniteOnlyFPMath()) { 8384 if (DAG.isKnownNeverNaN(LHS)) { 8385 // Put the potential NaN in the RHS so that SSE will preserve it. 8386 std::swap(LHS, RHS); 8387 } else if (!DAG.isKnownNeverNaN(RHS)) 8388 break; 8389 } 8390 Opcode = X86ISD::FMAX; 8391 break; 8392 case ISD::SETOLE: 8393 // This can be a max if we can prove that at least one of the operands 8394 // is not a nan. 8395 if (!FiniteOnlyFPMath()) { 8396 if (DAG.isKnownNeverNaN(RHS)) { 8397 // Put the potential NaN in the RHS so that SSE will preserve it. 8398 std::swap(LHS, RHS); 8399 } else if (!DAG.isKnownNeverNaN(LHS)) 8400 break; 8401 } 8402 Opcode = X86ISD::FMAX; 8403 break; 8404 case ISD::SETULE: 8405 // This can be a max, but if either operand is a NaN we need it to 8406 // preserve the original LHS. 8407 std::swap(LHS, RHS); 8408 case ISD::SETOLT: 8409 case ISD::SETLT: 8410 case ISD::SETLE: 8411 Opcode = X86ISD::FMAX; 8412 break; 8413 } 8414 } 8415 8416 if (Opcode) 8417 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 8418 } 8419 8420 // If this is a select between two integer constants, try to do some 8421 // optimizations. 8422 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 8423 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 8424 // Don't do this for crazy integer types. 8425 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 8426 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 8427 // so that TrueC (the true value) is larger than FalseC. 8428 bool NeedsCondInvert = false; 8429 8430 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 8431 // Efficiently invertible. 8432 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 8433 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 8434 isa<ConstantSDNode>(Cond.getOperand(1))))) { 8435 NeedsCondInvert = true; 8436 std::swap(TrueC, FalseC); 8437 } 8438 8439 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 8440 if (FalseC->getAPIntValue() == 0 && 8441 TrueC->getAPIntValue().isPowerOf2()) { 8442 if (NeedsCondInvert) // Invert the condition if needed. 8443 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8444 DAG.getConstant(1, Cond.getValueType())); 8445 8446 // Zero extend the condition if needed. 8447 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 8448 8449 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8450 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 8451 DAG.getConstant(ShAmt, MVT::i8)); 8452 } 8453 8454 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 8455 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8456 if (NeedsCondInvert) // Invert the condition if needed. 8457 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8458 DAG.getConstant(1, Cond.getValueType())); 8459 8460 // Zero extend the condition if needed. 8461 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8462 FalseC->getValueType(0), Cond); 8463 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8464 SDValue(FalseC, 0)); 8465 } 8466 8467 // Optimize cases that will turn into an LEA instruction. This requires 8468 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 8469 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 8470 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 8471 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 8472 8473 bool isFastMultiplier = false; 8474 if (Diff < 10) { 8475 switch ((unsigned char)Diff) { 8476 default: break; 8477 case 1: // result = add base, cond 8478 case 2: // result = lea base( , cond*2) 8479 case 3: // result = lea base(cond, cond*2) 8480 case 4: // result = lea base( , cond*4) 8481 case 5: // result = lea base(cond, cond*4) 8482 case 8: // result = lea base( , cond*8) 8483 case 9: // result = lea base(cond, cond*8) 8484 isFastMultiplier = true; 8485 break; 8486 } 8487 } 8488 8489 if (isFastMultiplier) { 8490 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 8491 if (NeedsCondInvert) // Invert the condition if needed. 8492 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8493 DAG.getConstant(1, Cond.getValueType())); 8494 8495 // Zero extend the condition if needed. 8496 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 8497 Cond); 8498 // Scale the condition by the difference. 8499 if (Diff != 1) 8500 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 8501 DAG.getConstant(Diff, Cond.getValueType())); 8502 8503 // Add the base if non-zero. 8504 if (FalseC->getAPIntValue() != 0) 8505 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8506 SDValue(FalseC, 0)); 8507 return Cond; 8508 } 8509 } 8510 } 8511 } 8512 8513 return SDValue(); 8514} 8515 8516/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 8517static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 8518 TargetLowering::DAGCombinerInfo &DCI) { 8519 DebugLoc DL = N->getDebugLoc(); 8520 8521 // If the flag operand isn't dead, don't touch this CMOV. 8522 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 8523 return SDValue(); 8524 8525 // If this is a select between two integer constants, try to do some 8526 // optimizations. Note that the operands are ordered the opposite of SELECT 8527 // operands. 8528 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 8529 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 8530 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 8531 // larger than FalseC (the false value). 8532 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 8533 8534 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 8535 CC = X86::GetOppositeBranchCondition(CC); 8536 std::swap(TrueC, FalseC); 8537 } 8538 8539 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 8540 // This is efficient for any integer data type (including i8/i16) and 8541 // shift amount. 8542 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 8543 SDValue Cond = N->getOperand(3); 8544 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8545 DAG.getConstant(CC, MVT::i8), Cond); 8546 8547 // Zero extend the condition if needed. 8548 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 8549 8550 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8551 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 8552 DAG.getConstant(ShAmt, MVT::i8)); 8553 if (N->getNumValues() == 2) // Dead flag value? 8554 return DCI.CombineTo(N, Cond, SDValue()); 8555 return Cond; 8556 } 8557 8558 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 8559 // for any integer data type, including i8/i16. 8560 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8561 SDValue Cond = N->getOperand(3); 8562 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8563 DAG.getConstant(CC, MVT::i8), Cond); 8564 8565 // Zero extend the condition if needed. 8566 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8567 FalseC->getValueType(0), Cond); 8568 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8569 SDValue(FalseC, 0)); 8570 8571 if (N->getNumValues() == 2) // Dead flag value? 8572 return DCI.CombineTo(N, Cond, SDValue()); 8573 return Cond; 8574 } 8575 8576 // Optimize cases that will turn into an LEA instruction. This requires 8577 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 8578 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 8579 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 8580 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 8581 8582 bool isFastMultiplier = false; 8583 if (Diff < 10) { 8584 switch ((unsigned char)Diff) { 8585 default: break; 8586 case 1: // result = add base, cond 8587 case 2: // result = lea base( , cond*2) 8588 case 3: // result = lea base(cond, cond*2) 8589 case 4: // result = lea base( , cond*4) 8590 case 5: // result = lea base(cond, cond*4) 8591 case 8: // result = lea base( , cond*8) 8592 case 9: // result = lea base(cond, cond*8) 8593 isFastMultiplier = true; 8594 break; 8595 } 8596 } 8597 8598 if (isFastMultiplier) { 8599 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 8600 SDValue Cond = N->getOperand(3); 8601 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 8602 DAG.getConstant(CC, MVT::i8), Cond); 8603 // Zero extend the condition if needed. 8604 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 8605 Cond); 8606 // Scale the condition by the difference. 8607 if (Diff != 1) 8608 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 8609 DAG.getConstant(Diff, Cond.getValueType())); 8610 8611 // Add the base if non-zero. 8612 if (FalseC->getAPIntValue() != 0) 8613 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8614 SDValue(FalseC, 0)); 8615 if (N->getNumValues() == 2) // Dead flag value? 8616 return DCI.CombineTo(N, Cond, SDValue()); 8617 return Cond; 8618 } 8619 } 8620 } 8621 } 8622 return SDValue(); 8623} 8624 8625 8626/// PerformMulCombine - Optimize a single multiply with constant into two 8627/// in order to implement it with two cheaper instructions, e.g. 8628/// LEA + SHL, LEA + LEA. 8629static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 8630 TargetLowering::DAGCombinerInfo &DCI) { 8631 if (DAG.getMachineFunction(). 8632 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 8633 return SDValue(); 8634 8635 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 8636 return SDValue(); 8637 8638 EVT VT = N->getValueType(0); 8639 if (VT != MVT::i64) 8640 return SDValue(); 8641 8642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8643 if (!C) 8644 return SDValue(); 8645 uint64_t MulAmt = C->getZExtValue(); 8646 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 8647 return SDValue(); 8648 8649 uint64_t MulAmt1 = 0; 8650 uint64_t MulAmt2 = 0; 8651 if ((MulAmt % 9) == 0) { 8652 MulAmt1 = 9; 8653 MulAmt2 = MulAmt / 9; 8654 } else if ((MulAmt % 5) == 0) { 8655 MulAmt1 = 5; 8656 MulAmt2 = MulAmt / 5; 8657 } else if ((MulAmt % 3) == 0) { 8658 MulAmt1 = 3; 8659 MulAmt2 = MulAmt / 3; 8660 } 8661 if (MulAmt2 && 8662 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 8663 DebugLoc DL = N->getDebugLoc(); 8664 8665 if (isPowerOf2_64(MulAmt2) && 8666 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 8667 // If second multiplifer is pow2, issue it first. We want the multiply by 8668 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 8669 // is an add. 8670 std::swap(MulAmt1, MulAmt2); 8671 8672 SDValue NewMul; 8673 if (isPowerOf2_64(MulAmt1)) 8674 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 8675 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 8676 else 8677 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 8678 DAG.getConstant(MulAmt1, VT)); 8679 8680 if (isPowerOf2_64(MulAmt2)) 8681 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 8682 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 8683 else 8684 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 8685 DAG.getConstant(MulAmt2, VT)); 8686 8687 // Do not add new nodes to DAG combiner worklist. 8688 DCI.CombineTo(N, NewMul, false); 8689 } 8690 return SDValue(); 8691} 8692 8693 8694/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 8695/// when possible. 8696static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 8697 const X86Subtarget *Subtarget) { 8698 // On X86 with SSE2 support, we can transform this to a vector shift if 8699 // all elements are shifted by the same amount. We can't do this in legalize 8700 // because the a constant vector is typically transformed to a constant pool 8701 // so we have no knowledge of the shift amount. 8702 if (!Subtarget->hasSSE2()) 8703 return SDValue(); 8704 8705 EVT VT = N->getValueType(0); 8706 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 8707 return SDValue(); 8708 8709 SDValue ShAmtOp = N->getOperand(1); 8710 EVT EltVT = VT.getVectorElementType(); 8711 DebugLoc DL = N->getDebugLoc(); 8712 SDValue BaseShAmt = SDValue(); 8713 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 8714 unsigned NumElts = VT.getVectorNumElements(); 8715 unsigned i = 0; 8716 for (; i != NumElts; ++i) { 8717 SDValue Arg = ShAmtOp.getOperand(i); 8718 if (Arg.getOpcode() == ISD::UNDEF) continue; 8719 BaseShAmt = Arg; 8720 break; 8721 } 8722 for (; i != NumElts; ++i) { 8723 SDValue Arg = ShAmtOp.getOperand(i); 8724 if (Arg.getOpcode() == ISD::UNDEF) continue; 8725 if (Arg != BaseShAmt) { 8726 return SDValue(); 8727 } 8728 } 8729 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 8730 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 8731 SDValue InVec = ShAmtOp.getOperand(0); 8732 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8733 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 8734 unsigned i = 0; 8735 for (; i != NumElts; ++i) { 8736 SDValue Arg = InVec.getOperand(i); 8737 if (Arg.getOpcode() == ISD::UNDEF) continue; 8738 BaseShAmt = Arg; 8739 break; 8740 } 8741 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 8742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 8743 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 8744 if (C->getZExtValue() == SplatIdx) 8745 BaseShAmt = InVec.getOperand(1); 8746 } 8747 } 8748 if (BaseShAmt.getNode() == 0) 8749 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 8750 DAG.getIntPtrConstant(0)); 8751 } else 8752 return SDValue(); 8753 8754 // The shift amount is an i32. 8755 if (EltVT.bitsGT(MVT::i32)) 8756 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 8757 else if (EltVT.bitsLT(MVT::i32)) 8758 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 8759 8760 // The shift amount is identical so we can do a vector shift. 8761 SDValue ValOp = N->getOperand(0); 8762 switch (N->getOpcode()) { 8763 default: 8764 llvm_unreachable("Unknown shift opcode!"); 8765 break; 8766 case ISD::SHL: 8767 if (VT == MVT::v2i64) 8768 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8769 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 8770 ValOp, BaseShAmt); 8771 if (VT == MVT::v4i32) 8772 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8773 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 8774 ValOp, BaseShAmt); 8775 if (VT == MVT::v8i16) 8776 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8777 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 8778 ValOp, BaseShAmt); 8779 break; 8780 case ISD::SRA: 8781 if (VT == MVT::v4i32) 8782 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8783 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 8784 ValOp, BaseShAmt); 8785 if (VT == MVT::v8i16) 8786 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8787 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 8788 ValOp, BaseShAmt); 8789 break; 8790 case ISD::SRL: 8791 if (VT == MVT::v2i64) 8792 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8793 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 8794 ValOp, BaseShAmt); 8795 if (VT == MVT::v4i32) 8796 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8797 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 8798 ValOp, BaseShAmt); 8799 if (VT == MVT::v8i16) 8800 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 8801 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 8802 ValOp, BaseShAmt); 8803 break; 8804 } 8805 return SDValue(); 8806} 8807 8808/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 8809static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 8810 const X86Subtarget *Subtarget) { 8811 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 8812 // the FP state in cases where an emms may be missing. 8813 // A preferable solution to the general problem is to figure out the right 8814 // places to insert EMMS. This qualifies as a quick hack. 8815 8816 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 8817 StoreSDNode *St = cast<StoreSDNode>(N); 8818 EVT VT = St->getValue().getValueType(); 8819 if (VT.getSizeInBits() != 64) 8820 return SDValue(); 8821 8822 const Function *F = DAG.getMachineFunction().getFunction(); 8823 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 8824 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 8825 && Subtarget->hasSSE2(); 8826 if ((VT.isVector() || 8827 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 8828 isa<LoadSDNode>(St->getValue()) && 8829 !cast<LoadSDNode>(St->getValue())->isVolatile() && 8830 St->getChain().hasOneUse() && !St->isVolatile()) { 8831 SDNode* LdVal = St->getValue().getNode(); 8832 LoadSDNode *Ld = 0; 8833 int TokenFactorIndex = -1; 8834 SmallVector<SDValue, 8> Ops; 8835 SDNode* ChainVal = St->getChain().getNode(); 8836 // Must be a store of a load. We currently handle two cases: the load 8837 // is a direct child, and it's under an intervening TokenFactor. It is 8838 // possible to dig deeper under nested TokenFactors. 8839 if (ChainVal == LdVal) 8840 Ld = cast<LoadSDNode>(St->getChain()); 8841 else if (St->getValue().hasOneUse() && 8842 ChainVal->getOpcode() == ISD::TokenFactor) { 8843 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 8844 if (ChainVal->getOperand(i).getNode() == LdVal) { 8845 TokenFactorIndex = i; 8846 Ld = cast<LoadSDNode>(St->getValue()); 8847 } else 8848 Ops.push_back(ChainVal->getOperand(i)); 8849 } 8850 } 8851 8852 if (!Ld || !ISD::isNormalLoad(Ld)) 8853 return SDValue(); 8854 8855 // If this is not the MMX case, i.e. we are just turning i64 load/store 8856 // into f64 load/store, avoid the transformation if there are multiple 8857 // uses of the loaded value. 8858 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 8859 return SDValue(); 8860 8861 DebugLoc LdDL = Ld->getDebugLoc(); 8862 DebugLoc StDL = N->getDebugLoc(); 8863 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 8864 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 8865 // pair instead. 8866 if (Subtarget->is64Bit() || F64IsLegal) { 8867 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 8868 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 8869 Ld->getBasePtr(), Ld->getSrcValue(), 8870 Ld->getSrcValueOffset(), Ld->isVolatile(), 8871 Ld->getAlignment()); 8872 SDValue NewChain = NewLd.getValue(1); 8873 if (TokenFactorIndex != -1) { 8874 Ops.push_back(NewChain); 8875 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 8876 Ops.size()); 8877 } 8878 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 8879 St->getSrcValue(), St->getSrcValueOffset(), 8880 St->isVolatile(), St->getAlignment()); 8881 } 8882 8883 // Otherwise, lower to two pairs of 32-bit loads / stores. 8884 SDValue LoAddr = Ld->getBasePtr(); 8885 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 8886 DAG.getConstant(4, MVT::i32)); 8887 8888 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 8889 Ld->getSrcValue(), Ld->getSrcValueOffset(), 8890 Ld->isVolatile(), Ld->getAlignment()); 8891 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 8892 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 8893 Ld->isVolatile(), 8894 MinAlign(Ld->getAlignment(), 4)); 8895 8896 SDValue NewChain = LoLd.getValue(1); 8897 if (TokenFactorIndex != -1) { 8898 Ops.push_back(LoLd); 8899 Ops.push_back(HiLd); 8900 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 8901 Ops.size()); 8902 } 8903 8904 LoAddr = St->getBasePtr(); 8905 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 8906 DAG.getConstant(4, MVT::i32)); 8907 8908 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 8909 St->getSrcValue(), St->getSrcValueOffset(), 8910 St->isVolatile(), St->getAlignment()); 8911 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 8912 St->getSrcValue(), 8913 St->getSrcValueOffset() + 4, 8914 St->isVolatile(), 8915 MinAlign(St->getAlignment(), 4)); 8916 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 8917 } 8918 return SDValue(); 8919} 8920 8921/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 8922/// X86ISD::FXOR nodes. 8923static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 8924 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 8925 // F[X]OR(0.0, x) -> x 8926 // F[X]OR(x, 0.0) -> x 8927 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8928 if (C->getValueAPF().isPosZero()) 8929 return N->getOperand(1); 8930 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8931 if (C->getValueAPF().isPosZero()) 8932 return N->getOperand(0); 8933 return SDValue(); 8934} 8935 8936/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 8937static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 8938 // FAND(0.0, x) -> 0.0 8939 // FAND(x, 0.0) -> 0.0 8940 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 8941 if (C->getValueAPF().isPosZero()) 8942 return N->getOperand(0); 8943 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 8944 if (C->getValueAPF().isPosZero()) 8945 return N->getOperand(1); 8946 return SDValue(); 8947} 8948 8949static SDValue PerformBTCombine(SDNode *N, 8950 SelectionDAG &DAG, 8951 TargetLowering::DAGCombinerInfo &DCI) { 8952 // BT ignores high bits in the bit index operand. 8953 SDValue Op1 = N->getOperand(1); 8954 if (Op1.hasOneUse()) { 8955 unsigned BitWidth = Op1.getValueSizeInBits(); 8956 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 8957 APInt KnownZero, KnownOne; 8958 TargetLowering::TargetLoweringOpt TLO(DAG); 8959 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8960 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 8961 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 8962 DCI.CommitTargetLoweringOpt(TLO); 8963 } 8964 return SDValue(); 8965} 8966 8967static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 8968 SDValue Op = N->getOperand(0); 8969 if (Op.getOpcode() == ISD::BIT_CONVERT) 8970 Op = Op.getOperand(0); 8971 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 8972 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 8973 VT.getVectorElementType().getSizeInBits() == 8974 OpVT.getVectorElementType().getSizeInBits()) { 8975 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 8976 } 8977 return SDValue(); 8978} 8979 8980// On X86 and X86-64, atomic operations are lowered to locked instructions. 8981// Locked instructions, in turn, have implicit fence semantics (all memory 8982// operations are flushed before issuing the locked instruction, and the 8983// are not buffered), so we can fold away the common pattern of 8984// fence-atomic-fence. 8985static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 8986 SDValue atomic = N->getOperand(0); 8987 switch (atomic.getOpcode()) { 8988 case ISD::ATOMIC_CMP_SWAP: 8989 case ISD::ATOMIC_SWAP: 8990 case ISD::ATOMIC_LOAD_ADD: 8991 case ISD::ATOMIC_LOAD_SUB: 8992 case ISD::ATOMIC_LOAD_AND: 8993 case ISD::ATOMIC_LOAD_OR: 8994 case ISD::ATOMIC_LOAD_XOR: 8995 case ISD::ATOMIC_LOAD_NAND: 8996 case ISD::ATOMIC_LOAD_MIN: 8997 case ISD::ATOMIC_LOAD_MAX: 8998 case ISD::ATOMIC_LOAD_UMIN: 8999 case ISD::ATOMIC_LOAD_UMAX: 9000 break; 9001 default: 9002 return SDValue(); 9003 } 9004 9005 SDValue fence = atomic.getOperand(0); 9006 if (fence.getOpcode() != ISD::MEMBARRIER) 9007 return SDValue(); 9008 9009 switch (atomic.getOpcode()) { 9010 case ISD::ATOMIC_CMP_SWAP: 9011 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9012 atomic.getOperand(1), atomic.getOperand(2), 9013 atomic.getOperand(3)); 9014 case ISD::ATOMIC_SWAP: 9015 case ISD::ATOMIC_LOAD_ADD: 9016 case ISD::ATOMIC_LOAD_SUB: 9017 case ISD::ATOMIC_LOAD_AND: 9018 case ISD::ATOMIC_LOAD_OR: 9019 case ISD::ATOMIC_LOAD_XOR: 9020 case ISD::ATOMIC_LOAD_NAND: 9021 case ISD::ATOMIC_LOAD_MIN: 9022 case ISD::ATOMIC_LOAD_MAX: 9023 case ISD::ATOMIC_LOAD_UMIN: 9024 case ISD::ATOMIC_LOAD_UMAX: 9025 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9026 atomic.getOperand(1), atomic.getOperand(2)); 9027 default: 9028 return SDValue(); 9029 } 9030} 9031 9032SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9033 DAGCombinerInfo &DCI) const { 9034 SelectionDAG &DAG = DCI.DAG; 9035 switch (N->getOpcode()) { 9036 default: break; 9037 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9038 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9039 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9040 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9041 case ISD::SHL: 9042 case ISD::SRA: 9043 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9044 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9045 case X86ISD::FXOR: 9046 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9047 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9048 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9049 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9050 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 9051 } 9052 9053 return SDValue(); 9054} 9055 9056//===----------------------------------------------------------------------===// 9057// X86 Inline Assembly Support 9058//===----------------------------------------------------------------------===// 9059 9060static bool LowerToBSwap(CallInst *CI) { 9061 // FIXME: this should verify that we are targetting a 486 or better. If not, 9062 // we will turn this bswap into something that will be lowered to logical ops 9063 // instead of emitting the bswap asm. For now, we don't support 486 or lower 9064 // so don't worry about this. 9065 9066 // Verify this is a simple bswap. 9067 if (CI->getNumOperands() != 2 || 9068 CI->getType() != CI->getOperand(1)->getType() || 9069 !CI->getType()->isInteger()) 9070 return false; 9071 9072 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9073 if (!Ty || Ty->getBitWidth() % 16 != 0) 9074 return false; 9075 9076 // Okay, we can do this xform, do so now. 9077 const Type *Tys[] = { Ty }; 9078 Module *M = CI->getParent()->getParent()->getParent(); 9079 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 9080 9081 Value *Op = CI->getOperand(1); 9082 Op = CallInst::Create(Int, Op, CI->getName(), CI); 9083 9084 CI->replaceAllUsesWith(Op); 9085 CI->eraseFromParent(); 9086 return true; 9087} 9088 9089bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 9090 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9091 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 9092 9093 std::string AsmStr = IA->getAsmString(); 9094 9095 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 9096 std::vector<std::string> AsmPieces; 9097 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 9098 9099 switch (AsmPieces.size()) { 9100 default: return false; 9101 case 1: 9102 AsmStr = AsmPieces[0]; 9103 AsmPieces.clear(); 9104 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 9105 9106 // bswap $0 9107 if (AsmPieces.size() == 2 && 9108 (AsmPieces[0] == "bswap" || 9109 AsmPieces[0] == "bswapq" || 9110 AsmPieces[0] == "bswapl") && 9111 (AsmPieces[1] == "$0" || 9112 AsmPieces[1] == "${0:q}")) { 9113 // No need to check constraints, nothing other than the equivalent of 9114 // "=r,0" would be valid here. 9115 return LowerToBSwap(CI); 9116 } 9117 // rorw $$8, ${0:w} --> llvm.bswap.i16 9118 if (CI->getType() == Type::getInt16Ty(CI->getContext()) && 9119 AsmPieces.size() == 3 && 9120 AsmPieces[0] == "rorw" && 9121 AsmPieces[1] == "$$8," && 9122 AsmPieces[2] == "${0:w}" && 9123 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") { 9124 return LowerToBSwap(CI); 9125 } 9126 break; 9127 case 3: 9128 if (CI->getType() == Type::getInt64Ty(CI->getContext()) && 9129 Constraints.size() >= 2 && 9130 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 9131 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 9132 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 9133 std::vector<std::string> Words; 9134 SplitString(AsmPieces[0], Words, " \t"); 9135 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 9136 Words.clear(); 9137 SplitString(AsmPieces[1], Words, " \t"); 9138 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 9139 Words.clear(); 9140 SplitString(AsmPieces[2], Words, " \t,"); 9141 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 9142 Words[2] == "%edx") { 9143 return LowerToBSwap(CI); 9144 } 9145 } 9146 } 9147 } 9148 break; 9149 } 9150 return false; 9151} 9152 9153 9154 9155/// getConstraintType - Given a constraint letter, return the type of 9156/// constraint it is for this target. 9157X86TargetLowering::ConstraintType 9158X86TargetLowering::getConstraintType(const std::string &Constraint) const { 9159 if (Constraint.size() == 1) { 9160 switch (Constraint[0]) { 9161 case 'A': 9162 return C_Register; 9163 case 'f': 9164 case 'r': 9165 case 'R': 9166 case 'l': 9167 case 'q': 9168 case 'Q': 9169 case 'x': 9170 case 'y': 9171 case 'Y': 9172 return C_RegisterClass; 9173 case 'e': 9174 case 'Z': 9175 return C_Other; 9176 default: 9177 break; 9178 } 9179 } 9180 return TargetLowering::getConstraintType(Constraint); 9181} 9182 9183/// LowerXConstraint - try to replace an X constraint, which matches anything, 9184/// with another that has more specific requirements based on the type of the 9185/// corresponding operand. 9186const char *X86TargetLowering:: 9187LowerXConstraint(EVT ConstraintVT) const { 9188 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 9189 // 'f' like normal targets. 9190 if (ConstraintVT.isFloatingPoint()) { 9191 if (Subtarget->hasSSE2()) 9192 return "Y"; 9193 if (Subtarget->hasSSE1()) 9194 return "x"; 9195 } 9196 9197 return TargetLowering::LowerXConstraint(ConstraintVT); 9198} 9199 9200/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 9201/// vector. If it is invalid, don't add anything to Ops. 9202void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 9203 char Constraint, 9204 bool hasMemory, 9205 std::vector<SDValue>&Ops, 9206 SelectionDAG &DAG) const { 9207 SDValue Result(0, 0); 9208 9209 switch (Constraint) { 9210 default: break; 9211 case 'I': 9212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9213 if (C->getZExtValue() <= 31) { 9214 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9215 break; 9216 } 9217 } 9218 return; 9219 case 'J': 9220 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9221 if (C->getZExtValue() <= 63) { 9222 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9223 break; 9224 } 9225 } 9226 return; 9227 case 'K': 9228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9229 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 9230 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9231 break; 9232 } 9233 } 9234 return; 9235 case 'N': 9236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9237 if (C->getZExtValue() <= 255) { 9238 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9239 break; 9240 } 9241 } 9242 return; 9243 case 'e': { 9244 // 32-bit signed value 9245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9246 const ConstantInt *CI = C->getConstantIntValue(); 9247 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9248 C->getSExtValue())) { 9249 // Widen to 64 bits here to get it sign extended. 9250 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 9251 break; 9252 } 9253 // FIXME gcc accepts some relocatable values here too, but only in certain 9254 // memory models; it's complicated. 9255 } 9256 return; 9257 } 9258 case 'Z': { 9259 // 32-bit unsigned value 9260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9261 const ConstantInt *CI = C->getConstantIntValue(); 9262 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9263 C->getZExtValue())) { 9264 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9265 break; 9266 } 9267 } 9268 // FIXME gcc accepts some relocatable values here too, but only in certain 9269 // memory models; it's complicated. 9270 return; 9271 } 9272 case 'i': { 9273 // Literal immediates are always ok. 9274 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 9275 // Widen to 64 bits here to get it sign extended. 9276 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 9277 break; 9278 } 9279 9280 // If we are in non-pic codegen mode, we allow the address of a global (with 9281 // an optional displacement) to be used with 'i'. 9282 GlobalAddressSDNode *GA = 0; 9283 int64_t Offset = 0; 9284 9285 // Match either (GA), (GA+C), (GA+C1+C2), etc. 9286 while (1) { 9287 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 9288 Offset += GA->getOffset(); 9289 break; 9290 } else if (Op.getOpcode() == ISD::ADD) { 9291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9292 Offset += C->getZExtValue(); 9293 Op = Op.getOperand(0); 9294 continue; 9295 } 9296 } else if (Op.getOpcode() == ISD::SUB) { 9297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9298 Offset += -C->getZExtValue(); 9299 Op = Op.getOperand(0); 9300 continue; 9301 } 9302 } 9303 9304 // Otherwise, this isn't something we can handle, reject it. 9305 return; 9306 } 9307 9308 GlobalValue *GV = GA->getGlobal(); 9309 // If we require an extra load to get this address, as in PIC mode, we 9310 // can't accept it. 9311 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 9312 getTargetMachine()))) 9313 return; 9314 9315 if (hasMemory) 9316 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 9317 else 9318 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 9319 Result = Op; 9320 break; 9321 } 9322 } 9323 9324 if (Result.getNode()) { 9325 Ops.push_back(Result); 9326 return; 9327 } 9328 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 9329 Ops, DAG); 9330} 9331 9332std::vector<unsigned> X86TargetLowering:: 9333getRegClassForInlineAsmConstraint(const std::string &Constraint, 9334 EVT VT) const { 9335 if (Constraint.size() == 1) { 9336 // FIXME: not handling fp-stack yet! 9337 switch (Constraint[0]) { // GCC X86 Constraint Letters 9338 default: break; // Unknown constraint letter 9339 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 9340 if (Subtarget->is64Bit()) { 9341 if (VT == MVT::i32) 9342 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 9343 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 9344 X86::R10D,X86::R11D,X86::R12D, 9345 X86::R13D,X86::R14D,X86::R15D, 9346 X86::EBP, X86::ESP, 0); 9347 else if (VT == MVT::i16) 9348 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 9349 X86::SI, X86::DI, X86::R8W,X86::R9W, 9350 X86::R10W,X86::R11W,X86::R12W, 9351 X86::R13W,X86::R14W,X86::R15W, 9352 X86::BP, X86::SP, 0); 9353 else if (VT == MVT::i8) 9354 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 9355 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 9356 X86::R10B,X86::R11B,X86::R12B, 9357 X86::R13B,X86::R14B,X86::R15B, 9358 X86::BPL, X86::SPL, 0); 9359 9360 else if (VT == MVT::i64) 9361 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 9362 X86::RSI, X86::RDI, X86::R8, X86::R9, 9363 X86::R10, X86::R11, X86::R12, 9364 X86::R13, X86::R14, X86::R15, 9365 X86::RBP, X86::RSP, 0); 9366 9367 break; 9368 } 9369 // 32-bit fallthrough 9370 case 'Q': // Q_REGS 9371 if (VT == MVT::i32) 9372 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 9373 else if (VT == MVT::i16) 9374 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 9375 else if (VT == MVT::i8) 9376 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 9377 else if (VT == MVT::i64) 9378 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 9379 break; 9380 } 9381 } 9382 9383 return std::vector<unsigned>(); 9384} 9385 9386std::pair<unsigned, const TargetRegisterClass*> 9387X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 9388 EVT VT) const { 9389 // First, see if this is a constraint that directly corresponds to an LLVM 9390 // register class. 9391 if (Constraint.size() == 1) { 9392 // GCC Constraint Letters 9393 switch (Constraint[0]) { 9394 default: break; 9395 case 'r': // GENERAL_REGS 9396 case 'R': // LEGACY_REGS 9397 case 'l': // INDEX_REGS 9398 if (VT == MVT::i8) 9399 return std::make_pair(0U, X86::GR8RegisterClass); 9400 if (VT == MVT::i16) 9401 return std::make_pair(0U, X86::GR16RegisterClass); 9402 if (VT == MVT::i32 || !Subtarget->is64Bit()) 9403 return std::make_pair(0U, X86::GR32RegisterClass); 9404 return std::make_pair(0U, X86::GR64RegisterClass); 9405 case 'f': // FP Stack registers. 9406 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 9407 // value to the correct fpstack register class. 9408 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 9409 return std::make_pair(0U, X86::RFP32RegisterClass); 9410 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 9411 return std::make_pair(0U, X86::RFP64RegisterClass); 9412 return std::make_pair(0U, X86::RFP80RegisterClass); 9413 case 'y': // MMX_REGS if MMX allowed. 9414 if (!Subtarget->hasMMX()) break; 9415 return std::make_pair(0U, X86::VR64RegisterClass); 9416 case 'Y': // SSE_REGS if SSE2 allowed 9417 if (!Subtarget->hasSSE2()) break; 9418 // FALL THROUGH. 9419 case 'x': // SSE_REGS if SSE1 allowed 9420 if (!Subtarget->hasSSE1()) break; 9421 9422 switch (VT.getSimpleVT().SimpleTy) { 9423 default: break; 9424 // Scalar SSE types. 9425 case MVT::f32: 9426 case MVT::i32: 9427 return std::make_pair(0U, X86::FR32RegisterClass); 9428 case MVT::f64: 9429 case MVT::i64: 9430 return std::make_pair(0U, X86::FR64RegisterClass); 9431 // Vector types. 9432 case MVT::v16i8: 9433 case MVT::v8i16: 9434 case MVT::v4i32: 9435 case MVT::v2i64: 9436 case MVT::v4f32: 9437 case MVT::v2f64: 9438 return std::make_pair(0U, X86::VR128RegisterClass); 9439 } 9440 break; 9441 } 9442 } 9443 9444 // Use the default implementation in TargetLowering to convert the register 9445 // constraint into a member of a register class. 9446 std::pair<unsigned, const TargetRegisterClass*> Res; 9447 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 9448 9449 // Not found as a standard register? 9450 if (Res.second == 0) { 9451 // Map st(0) -> st(7) -> ST0 9452 if (Constraint.size() == 7 && Constraint[0] == '{' && 9453 tolower(Constraint[1]) == 's' && 9454 tolower(Constraint[2]) == 't' && 9455 Constraint[3] == '(' && 9456 (Constraint[4] >= '0' && Constraint[4] <= '7') && 9457 Constraint[5] == ')' && 9458 Constraint[6] == '}') { 9459 9460 Res.first = X86::ST0+Constraint[4]-'0'; 9461 Res.second = X86::RFP80RegisterClass; 9462 return Res; 9463 } 9464 9465 // GCC allows "st(0)" to be called just plain "st". 9466 if (StringsEqualNoCase("{st}", Constraint)) { 9467 Res.first = X86::ST0; 9468 Res.second = X86::RFP80RegisterClass; 9469 return Res; 9470 } 9471 9472 // flags -> EFLAGS 9473 if (StringsEqualNoCase("{flags}", Constraint)) { 9474 Res.first = X86::EFLAGS; 9475 Res.second = X86::CCRRegisterClass; 9476 return Res; 9477 } 9478 9479 // 'A' means EAX + EDX. 9480 if (Constraint == "A") { 9481 Res.first = X86::EAX; 9482 Res.second = X86::GR32_ADRegisterClass; 9483 return Res; 9484 } 9485 return Res; 9486 } 9487 9488 // Otherwise, check to see if this is a register class of the wrong value 9489 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 9490 // turn into {ax},{dx}. 9491 if (Res.second->hasType(VT)) 9492 return Res; // Correct type already, nothing to do. 9493 9494 // All of the single-register GCC register classes map their values onto 9495 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 9496 // really want an 8-bit or 32-bit register, map to the appropriate register 9497 // class and return the appropriate register. 9498 if (Res.second == X86::GR16RegisterClass) { 9499 if (VT == MVT::i8) { 9500 unsigned DestReg = 0; 9501 switch (Res.first) { 9502 default: break; 9503 case X86::AX: DestReg = X86::AL; break; 9504 case X86::DX: DestReg = X86::DL; break; 9505 case X86::CX: DestReg = X86::CL; break; 9506 case X86::BX: DestReg = X86::BL; break; 9507 } 9508 if (DestReg) { 9509 Res.first = DestReg; 9510 Res.second = X86::GR8RegisterClass; 9511 } 9512 } else if (VT == MVT::i32) { 9513 unsigned DestReg = 0; 9514 switch (Res.first) { 9515 default: break; 9516 case X86::AX: DestReg = X86::EAX; break; 9517 case X86::DX: DestReg = X86::EDX; break; 9518 case X86::CX: DestReg = X86::ECX; break; 9519 case X86::BX: DestReg = X86::EBX; break; 9520 case X86::SI: DestReg = X86::ESI; break; 9521 case X86::DI: DestReg = X86::EDI; break; 9522 case X86::BP: DestReg = X86::EBP; break; 9523 case X86::SP: DestReg = X86::ESP; break; 9524 } 9525 if (DestReg) { 9526 Res.first = DestReg; 9527 Res.second = X86::GR32RegisterClass; 9528 } 9529 } else if (VT == MVT::i64) { 9530 unsigned DestReg = 0; 9531 switch (Res.first) { 9532 default: break; 9533 case X86::AX: DestReg = X86::RAX; break; 9534 case X86::DX: DestReg = X86::RDX; break; 9535 case X86::CX: DestReg = X86::RCX; break; 9536 case X86::BX: DestReg = X86::RBX; break; 9537 case X86::SI: DestReg = X86::RSI; break; 9538 case X86::DI: DestReg = X86::RDI; break; 9539 case X86::BP: DestReg = X86::RBP; break; 9540 case X86::SP: DestReg = X86::RSP; break; 9541 } 9542 if (DestReg) { 9543 Res.first = DestReg; 9544 Res.second = X86::GR64RegisterClass; 9545 } 9546 } 9547 } else if (Res.second == X86::FR32RegisterClass || 9548 Res.second == X86::FR64RegisterClass || 9549 Res.second == X86::VR128RegisterClass) { 9550 // Handle references to XMM physical registers that got mapped into the 9551 // wrong class. This can happen with constraints like {xmm0} where the 9552 // target independent register mapper will just pick the first match it can 9553 // find, ignoring the required type. 9554 if (VT == MVT::f32) 9555 Res.second = X86::FR32RegisterClass; 9556 else if (VT == MVT::f64) 9557 Res.second = X86::FR64RegisterClass; 9558 else if (X86::VR128RegisterClass->hasType(VT)) 9559 Res.second = X86::VR128RegisterClass; 9560 } 9561 9562 return Res; 9563} 9564 9565//===----------------------------------------------------------------------===// 9566// X86 Widen vector type 9567//===----------------------------------------------------------------------===// 9568 9569/// getWidenVectorType: given a vector type, returns the type to widen 9570/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 9571/// If there is no vector type that we want to widen to, returns MVT::Other 9572/// When and where to widen is target dependent based on the cost of 9573/// scalarizing vs using the wider vector type. 9574 9575EVT X86TargetLowering::getWidenVectorType(EVT VT) const { 9576 assert(VT.isVector()); 9577 if (isTypeLegal(VT)) 9578 return VT; 9579 9580 // TODO: In computeRegisterProperty, we can compute the list of legal vector 9581 // type based on element type. This would speed up our search (though 9582 // it may not be worth it since the size of the list is relatively 9583 // small). 9584 EVT EltVT = VT.getVectorElementType(); 9585 unsigned NElts = VT.getVectorNumElements(); 9586 9587 // On X86, it make sense to widen any vector wider than 1 9588 if (NElts <= 1) 9589 return MVT::Other; 9590 9591 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 9592 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 9593 EVT SVT = (MVT::SimpleValueType)nVT; 9594 9595 if (isTypeLegal(SVT) && 9596 SVT.getVectorElementType() == EltVT && 9597 SVT.getVectorNumElements() > NElts) 9598 return SVT; 9599 } 9600 return MVT::Other; 9601} 9602