X86ISelLowering.cpp revision 67609fd0eb05a49cc4636d507398034393dcf302
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86TargetMachine.h" 20#include "X86TargetObjectFile.h" 21#include "Utils/X86ShuffleDecode.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/IntrinsicLowering.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineFunction.h" 34#include "llvm/CodeGen/MachineInstrBuilder.h" 35#include "llvm/CodeGen/MachineJumpTableInfo.h" 36#include "llvm/CodeGen/MachineModuleInfo.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCExpr.h" 41#include "llvm/MC/MCSymbol.h" 42#include "llvm/ADT/BitVector.h" 43#include "llvm/ADT/SmallSet.h" 44#include "llvm/ADT/Statistic.h" 45#include "llvm/ADT/StringExtras.h" 46#include "llvm/ADT/VariadicFunction.h" 47#include "llvm/Support/CallSite.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/Dwarf.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetOptions.h" 55using namespace llvm; 56using namespace dwarf; 57 58STATISTIC(NumTailCalls, "Number of tail calls"); 59 60static cl::opt<bool> UseRegMask("x86-use-regmask", 61 cl::desc("Use register masks for x86 calls")); 62 63// Forward declarations. 64static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 65 SDValue V2); 66 67static SDValue Insert128BitVector(SDValue Result, 68 SDValue Vec, 69 SDValue Idx, 70 SelectionDAG &DAG, 71 DebugLoc dl); 72 73static SDValue Extract128BitVector(SDValue Vec, 74 SDValue Idx, 75 SelectionDAG &DAG, 76 DebugLoc dl); 77 78/// Generate a DAG to grab 128-bits from a vector > 128 bits. This 79/// sets things up to match to an AVX VEXTRACTF128 instruction or a 80/// simple subregister reference. Idx is an index in the 128 bits we 81/// want. It need not be aligned to a 128-bit bounday. That makes 82/// lowering EXTRACT_VECTOR_ELT operations easier. 83static SDValue Extract128BitVector(SDValue Vec, 84 SDValue Idx, 85 SelectionDAG &DAG, 86 DebugLoc dl) { 87 EVT VT = Vec.getValueType(); 88 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 89 EVT ElVT = VT.getVectorElementType(); 90 int Factor = VT.getSizeInBits()/128; 91 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 92 VT.getVectorNumElements()/Factor); 93 94 // Extract from UNDEF is UNDEF. 95 if (Vec.getOpcode() == ISD::UNDEF) 96 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 97 98 if (isa<ConstantSDNode>(Idx)) { 99 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 100 101 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 102 // we can match to VEXTRACTF128. 103 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 104 105 // This is the index of the first element of the 128-bit chunk 106 // we want. 107 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 108 * ElemsPerChunk); 109 110 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 111 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 112 VecIdx); 113 114 return Result; 115 } 116 117 return SDValue(); 118} 119 120/// Generate a DAG to put 128-bits into a vector > 128 bits. This 121/// sets things up to match to an AVX VINSERTF128 instruction or a 122/// simple superregister reference. Idx is an index in the 128 bits 123/// we want. It need not be aligned to a 128-bit bounday. That makes 124/// lowering INSERT_VECTOR_ELT operations easier. 125static SDValue Insert128BitVector(SDValue Result, 126 SDValue Vec, 127 SDValue Idx, 128 SelectionDAG &DAG, 129 DebugLoc dl) { 130 if (isa<ConstantSDNode>(Idx)) { 131 EVT VT = Vec.getValueType(); 132 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 133 134 EVT ElVT = VT.getVectorElementType(); 135 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 136 EVT ResultVT = Result.getValueType(); 137 138 // Insert the relevant 128 bits. 139 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 140 141 // This is the index of the first element of the 128-bit chunk 142 // we want. 143 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 144 * ElemsPerChunk); 145 146 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 147 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 148 VecIdx); 149 return Result; 150 } 151 152 return SDValue(); 153} 154 155static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 156 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 157 bool is64Bit = Subtarget->is64Bit(); 158 159 if (Subtarget->isTargetEnvMacho()) { 160 if (is64Bit) 161 return new X8664_MachoTargetObjectFile(); 162 return new TargetLoweringObjectFileMachO(); 163 } 164 165 if (Subtarget->isTargetELF()) 166 return new TargetLoweringObjectFileELF(); 167 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 168 return new TargetLoweringObjectFileCOFF(); 169 llvm_unreachable("unknown subtarget type"); 170} 171 172X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 173 : TargetLowering(TM, createTLOF(TM)) { 174 Subtarget = &TM.getSubtarget<X86Subtarget>(); 175 X86ScalarSSEf64 = Subtarget->hasSSE2(); 176 X86ScalarSSEf32 = Subtarget->hasSSE1(); 177 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 178 179 RegInfo = TM.getRegisterInfo(); 180 TD = getTargetData(); 181 182 // Set up the TargetLowering object. 183 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 184 185 // X86 is weird, it always uses i8 for shift amounts and setcc results. 186 setBooleanContents(ZeroOrOneBooleanContent); 187 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 188 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 189 190 // For 64-bit since we have so many registers use the ILP scheduler, for 191 // 32-bit code use the register pressure specific scheduling. 192 if (Subtarget->is64Bit()) 193 setSchedulingPreference(Sched::ILP); 194 else 195 setSchedulingPreference(Sched::RegPressure); 196 setStackPointerRegisterToSaveRestore(X86StackPtr); 197 198 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 199 // Setup Windows compiler runtime calls. 200 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 201 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 202 setLibcallName(RTLIB::SREM_I64, "_allrem"); 203 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 204 setLibcallName(RTLIB::MUL_I64, "_allmul"); 205 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 206 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 207 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 209 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 210 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 211 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 212 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 213 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 214 } 215 216 if (Subtarget->isTargetDarwin()) { 217 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 218 setUseUnderscoreSetJmp(false); 219 setUseUnderscoreLongJmp(false); 220 } else if (Subtarget->isTargetMingw()) { 221 // MS runtime is weird: it exports _setjmp, but longjmp! 222 setUseUnderscoreSetJmp(true); 223 setUseUnderscoreLongJmp(false); 224 } else { 225 setUseUnderscoreSetJmp(true); 226 setUseUnderscoreLongJmp(true); 227 } 228 229 // Set up the register classes. 230 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 231 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 232 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 233 if (Subtarget->is64Bit()) 234 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 235 236 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 237 238 // We don't accept any truncstore of integer registers. 239 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 240 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 241 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 242 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 243 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 244 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 245 246 // SETOEQ and SETUNE require checking two conditions. 247 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 248 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 249 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 250 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 251 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 252 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 253 254 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 255 // operation. 256 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 257 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 258 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 259 260 if (Subtarget->is64Bit()) { 261 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 263 } else if (!TM.Options.UseSoftFloat) { 264 // We have an algorithm for SSE2->double, and we turn this into a 265 // 64-bit FILD followed by conditional FADD for other targets. 266 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 267 // We have an algorithm for SSE2, and we turn this into a 64-bit 268 // FILD for other targets. 269 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 270 } 271 272 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 273 // this operation. 274 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 275 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 276 277 if (!TM.Options.UseSoftFloat) { 278 // SSE has no i16 to fp conversion, only i32 279 if (X86ScalarSSEf32) { 280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 281 // f32 and f64 cases are Legal, f80 case is not 282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 283 } else { 284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 286 } 287 } else { 288 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 289 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 290 } 291 292 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 293 // are Legal, f80 is custom lowered. 294 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 295 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 296 297 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 298 // this operation. 299 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 300 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 301 302 if (X86ScalarSSEf32) { 303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 304 // f32 and f64 cases are Legal, f80 case is not 305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 306 } else { 307 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 308 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 309 } 310 311 // Handle FP_TO_UINT by promoting the destination to a larger signed 312 // conversion. 313 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 314 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 315 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 316 317 if (Subtarget->is64Bit()) { 318 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 320 } else if (!TM.Options.UseSoftFloat) { 321 // Since AVX is a superset of SSE3, only check for SSE here. 322 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 323 // Expand FP_TO_UINT into a select. 324 // FIXME: We would like to use a Custom expander here eventually to do 325 // the optimal thing for SSE vs. the default expansion in the legalizer. 326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 327 else 328 // With SSE3 we can use fisttpll to convert to a signed i64; without 329 // SSE, we're stuck with a fistpll. 330 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 331 } 332 333 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 334 if (!X86ScalarSSEf64) { 335 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 336 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 337 if (Subtarget->is64Bit()) { 338 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 339 // Without SSE, i64->f64 goes through memory. 340 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 341 } 342 } 343 344 // Scalar integer divide and remainder are lowered to use operations that 345 // produce two results, to match the available instructions. This exposes 346 // the two-result form to trivial CSE, which is able to combine x/y and x%y 347 // into a single instruction. 348 // 349 // Scalar integer multiply-high is also lowered to use two-result 350 // operations, to match the available instructions. However, plain multiply 351 // (low) operations are left as Legal, as there are single-result 352 // instructions for this in x86. Using the two-result multiply instructions 353 // when both high and low results are needed must be arranged by dagcombine. 354 for (unsigned i = 0, e = 4; i != e; ++i) { 355 MVT VT = IntVTs[i]; 356 setOperationAction(ISD::MULHS, VT, Expand); 357 setOperationAction(ISD::MULHU, VT, Expand); 358 setOperationAction(ISD::SDIV, VT, Expand); 359 setOperationAction(ISD::UDIV, VT, Expand); 360 setOperationAction(ISD::SREM, VT, Expand); 361 setOperationAction(ISD::UREM, VT, Expand); 362 363 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 364 setOperationAction(ISD::ADDC, VT, Custom); 365 setOperationAction(ISD::ADDE, VT, Custom); 366 setOperationAction(ISD::SUBC, VT, Custom); 367 setOperationAction(ISD::SUBE, VT, Custom); 368 } 369 370 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 371 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 372 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 373 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 374 if (Subtarget->is64Bit()) 375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 378 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 379 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 380 setOperationAction(ISD::FREM , MVT::f32 , Expand); 381 setOperationAction(ISD::FREM , MVT::f64 , Expand); 382 setOperationAction(ISD::FREM , MVT::f80 , Expand); 383 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 384 385 // Promote the i8 variants and force them on up to i32 which has a shorter 386 // encoding. 387 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 388 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); 389 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); 390 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); 391 if (Subtarget->hasBMI()) { 392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); 393 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); 394 if (Subtarget->is64Bit()) 395 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 396 } else { 397 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 398 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 399 if (Subtarget->is64Bit()) 400 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 401 } 402 403 if (Subtarget->hasLZCNT()) { 404 // When promoting the i8 variants, force them to i32 for a shorter 405 // encoding. 406 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 407 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); 408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); 409 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); 410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); 411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); 412 if (Subtarget->is64Bit()) 413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 414 } else { 415 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 416 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 417 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom); 419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom); 420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom); 421 if (Subtarget->is64Bit()) { 422 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 424 } 425 } 426 427 if (Subtarget->hasPOPCNT()) { 428 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 429 } else { 430 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 431 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 432 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 433 if (Subtarget->is64Bit()) 434 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 435 } 436 437 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 438 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 439 440 // These should be promoted to a larger select which is supported. 441 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 442 // X86 wants to expand cmov itself. 443 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 444 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 445 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 446 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 447 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 448 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 449 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 450 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 451 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 452 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 453 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 454 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 455 if (Subtarget->is64Bit()) { 456 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 457 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 458 } 459 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 460 461 // Darwin ABI issue. 462 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 463 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 464 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 465 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 466 if (Subtarget->is64Bit()) 467 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 468 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 469 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 470 if (Subtarget->is64Bit()) { 471 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 472 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 473 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 474 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 475 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 476 } 477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 478 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 479 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 480 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 481 if (Subtarget->is64Bit()) { 482 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 483 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 484 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 485 } 486 487 if (Subtarget->hasSSE1()) 488 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 489 490 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 491 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 492 493 // On X86 and X86-64, atomic operations are lowered to locked instructions. 494 // Locked instructions, in turn, have implicit fence semantics (all memory 495 // operations are flushed before issuing the locked instruction, and they 496 // are not buffered), so we can fold away the common pattern of 497 // fence-atomic-fence. 498 setShouldFoldAtomicFences(true); 499 500 // Expand certain atomics 501 for (unsigned i = 0, e = 4; i != e; ++i) { 502 MVT VT = IntVTs[i]; 503 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 504 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 505 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 506 } 507 508 if (!Subtarget->is64Bit()) { 509 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 510 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 511 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 512 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 513 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 514 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 515 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 516 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 517 } 518 519 if (Subtarget->hasCmpxchg16b()) { 520 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 521 } 522 523 // FIXME - use subtarget debug flags 524 if (!Subtarget->isTargetDarwin() && 525 !Subtarget->isTargetELF() && 526 !Subtarget->isTargetCygMing()) { 527 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 528 } 529 530 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 531 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 532 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 533 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 534 if (Subtarget->is64Bit()) { 535 setExceptionPointerRegister(X86::RAX); 536 setExceptionSelectorRegister(X86::RDX); 537 } else { 538 setExceptionPointerRegister(X86::EAX); 539 setExceptionSelectorRegister(X86::EDX); 540 } 541 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 542 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 543 544 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 545 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 546 547 setOperationAction(ISD::TRAP, MVT::Other, Legal); 548 549 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 550 setOperationAction(ISD::VASTART , MVT::Other, Custom); 551 setOperationAction(ISD::VAEND , MVT::Other, Expand); 552 if (Subtarget->is64Bit()) { 553 setOperationAction(ISD::VAARG , MVT::Other, Custom); 554 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 555 } else { 556 setOperationAction(ISD::VAARG , MVT::Other, Expand); 557 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 558 } 559 560 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 561 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 562 563 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 565 MVT::i64 : MVT::i32, Custom); 566 else if (TM.Options.EnableSegmentedStacks) 567 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 568 MVT::i64 : MVT::i32, Custom); 569 else 570 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 571 MVT::i64 : MVT::i32, Expand); 572 573 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) { 574 // f32 and f64 use SSE. 575 // Set up the FP register classes. 576 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 577 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 578 579 // Use ANDPD to simulate FABS. 580 setOperationAction(ISD::FABS , MVT::f64, Custom); 581 setOperationAction(ISD::FABS , MVT::f32, Custom); 582 583 // Use XORP to simulate FNEG. 584 setOperationAction(ISD::FNEG , MVT::f64, Custom); 585 setOperationAction(ISD::FNEG , MVT::f32, Custom); 586 587 // Use ANDPD and ORPD to simulate FCOPYSIGN. 588 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 589 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 590 591 // Lower this to FGETSIGNx86 plus an AND. 592 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 593 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 594 595 // We don't support sin/cos/fmod 596 setOperationAction(ISD::FSIN , MVT::f64, Expand); 597 setOperationAction(ISD::FCOS , MVT::f64, Expand); 598 setOperationAction(ISD::FSIN , MVT::f32, Expand); 599 setOperationAction(ISD::FCOS , MVT::f32, Expand); 600 601 // Expand FP immediates into loads from the stack, except for the special 602 // cases we handle. 603 addLegalFPImmediate(APFloat(+0.0)); // xorpd 604 addLegalFPImmediate(APFloat(+0.0f)); // xorps 605 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) { 606 // Use SSE for f32, x87 for f64. 607 // Set up the FP register classes. 608 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 609 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 610 611 // Use ANDPS to simulate FABS. 612 setOperationAction(ISD::FABS , MVT::f32, Custom); 613 614 // Use XORP to simulate FNEG. 615 setOperationAction(ISD::FNEG , MVT::f32, Custom); 616 617 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 618 619 // Use ANDPS and ORPS to simulate FCOPYSIGN. 620 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 622 623 // We don't support sin/cos/fmod 624 setOperationAction(ISD::FSIN , MVT::f32, Expand); 625 setOperationAction(ISD::FCOS , MVT::f32, Expand); 626 627 // Special cases we handle for FP constants. 628 addLegalFPImmediate(APFloat(+0.0f)); // xorps 629 addLegalFPImmediate(APFloat(+0.0)); // FLD0 630 addLegalFPImmediate(APFloat(+1.0)); // FLD1 631 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 632 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 633 634 if (!TM.Options.UnsafeFPMath) { 635 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 636 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 637 } 638 } else if (!TM.Options.UseSoftFloat) { 639 // f32 and f64 in x87. 640 // Set up the FP register classes. 641 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 642 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 643 644 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 645 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 646 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 647 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 648 649 if (!TM.Options.UnsafeFPMath) { 650 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 651 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 652 } 653 addLegalFPImmediate(APFloat(+0.0)); // FLD0 654 addLegalFPImmediate(APFloat(+1.0)); // FLD1 655 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 656 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 657 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 658 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 659 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 660 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 661 } 662 663 // We don't support FMA. 664 setOperationAction(ISD::FMA, MVT::f64, Expand); 665 setOperationAction(ISD::FMA, MVT::f32, Expand); 666 667 // Long double always uses X87. 668 if (!TM.Options.UseSoftFloat) { 669 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 670 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 671 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 672 { 673 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 674 addLegalFPImmediate(TmpFlt); // FLD0 675 TmpFlt.changeSign(); 676 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 677 678 bool ignored; 679 APFloat TmpFlt2(+1.0); 680 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 681 &ignored); 682 addLegalFPImmediate(TmpFlt2); // FLD1 683 TmpFlt2.changeSign(); 684 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 685 } 686 687 if (!TM.Options.UnsafeFPMath) { 688 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 689 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 690 } 691 692 setOperationAction(ISD::FFLOOR, MVT::f80, Expand); 693 setOperationAction(ISD::FCEIL, MVT::f80, Expand); 694 setOperationAction(ISD::FTRUNC, MVT::f80, Expand); 695 setOperationAction(ISD::FRINT, MVT::f80, Expand); 696 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); 697 setOperationAction(ISD::FMA, MVT::f80, Expand); 698 } 699 700 // Always use a library call for pow. 701 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 702 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 703 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 704 705 setOperationAction(ISD::FLOG, MVT::f80, Expand); 706 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 707 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 708 setOperationAction(ISD::FEXP, MVT::f80, Expand); 709 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 710 711 // First set operation action for all vector types to either promote 712 // (for widening) or expand (for scalarization). Then we will selectively 713 // turn on ones that can be effectively codegen'd. 714 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 715 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 716 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 731 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 733 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 734 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 736 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 741 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 742 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 743 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 744 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 745 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 746 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 747 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 748 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 749 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 750 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand); 751 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 752 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 753 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 754 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 756 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 757 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 758 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 760 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 761 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 762 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 763 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 765 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 767 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 768 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 769 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 770 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 771 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 772 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 773 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 774 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 775 setTruncStoreAction((MVT::SimpleValueType)VT, 776 (MVT::SimpleValueType)InnerVT, Expand); 777 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 778 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 779 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 780 } 781 782 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 783 // with -msoft-float, disable use of MMX as well. 784 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) { 785 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 786 // No operations on x86mmx supported, everything uses intrinsics. 787 } 788 789 // MMX-sized vectors (other than x86mmx) are expected to be expanded 790 // into smaller operations. 791 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 792 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 793 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 794 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 795 setOperationAction(ISD::AND, MVT::v8i8, Expand); 796 setOperationAction(ISD::AND, MVT::v4i16, Expand); 797 setOperationAction(ISD::AND, MVT::v2i32, Expand); 798 setOperationAction(ISD::AND, MVT::v1i64, Expand); 799 setOperationAction(ISD::OR, MVT::v8i8, Expand); 800 setOperationAction(ISD::OR, MVT::v4i16, Expand); 801 setOperationAction(ISD::OR, MVT::v2i32, Expand); 802 setOperationAction(ISD::OR, MVT::v1i64, Expand); 803 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 804 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 805 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 806 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 808 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 809 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 810 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 811 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 812 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 813 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 814 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 815 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 816 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 817 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 818 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 819 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 820 821 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) { 822 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 823 824 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 825 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 826 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 827 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 828 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 829 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 830 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 831 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 832 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 833 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 834 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 835 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 836 } 837 838 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { 839 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 840 841 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 842 // registers cannot be used even for integer operations. 843 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 844 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 845 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 846 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 847 848 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 849 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 850 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 851 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 852 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 853 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 854 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 855 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 856 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 857 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 858 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 859 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 860 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 861 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 862 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 863 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 864 865 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 866 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 867 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 868 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 869 870 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 871 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 872 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 873 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 875 876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 877 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 878 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 879 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 880 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 881 882 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 883 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 884 EVT VT = (MVT::SimpleValueType)i; 885 // Do not attempt to custom lower non-power-of-2 vectors 886 if (!isPowerOf2_32(VT.getVectorNumElements())) 887 continue; 888 // Do not attempt to custom lower non-128-bit vectors 889 if (!VT.is128BitVector()) 890 continue; 891 setOperationAction(ISD::BUILD_VECTOR, 892 VT.getSimpleVT().SimpleTy, Custom); 893 setOperationAction(ISD::VECTOR_SHUFFLE, 894 VT.getSimpleVT().SimpleTy, Custom); 895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 896 VT.getSimpleVT().SimpleTy, Custom); 897 } 898 899 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 900 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 901 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 902 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 905 906 if (Subtarget->is64Bit()) { 907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 909 } 910 911 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 912 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 913 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 914 EVT VT = SVT; 915 916 // Do not attempt to promote non-128-bit vectors 917 if (!VT.is128BitVector()) 918 continue; 919 920 setOperationAction(ISD::AND, SVT, Promote); 921 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 922 setOperationAction(ISD::OR, SVT, Promote); 923 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 924 setOperationAction(ISD::XOR, SVT, Promote); 925 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 926 setOperationAction(ISD::LOAD, SVT, Promote); 927 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 928 setOperationAction(ISD::SELECT, SVT, Promote); 929 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 930 } 931 932 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 933 934 // Custom lower v2i64 and v2f64 selects. 935 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 936 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 937 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 938 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 939 940 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 941 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 942 } 943 944 if (Subtarget->hasSSE41()) { 945 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 946 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 947 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 948 setOperationAction(ISD::FRINT, MVT::f32, Legal); 949 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 950 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 951 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 952 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 953 setOperationAction(ISD::FRINT, MVT::f64, Legal); 954 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 955 956 // FIXME: Do we need to handle scalar-to-vector here? 957 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 958 959 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 960 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 961 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 962 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 963 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 964 965 // i8 and i16 vectors are custom , because the source register and source 966 // source memory operand types are not the same width. f32 vectors are 967 // custom since the immediate controlling the insert encodes additional 968 // information. 969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 973 974 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 975 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 978 979 // FIXME: these should be Legal but thats only for the case where 980 // the index is constant. For now custom expand to deal with that. 981 if (Subtarget->is64Bit()) { 982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 984 } 985 } 986 987 if (Subtarget->hasSSE2()) { 988 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 989 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 990 991 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 992 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 993 994 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 995 setOperationAction(ISD::SRA, MVT::v16i8, Custom); 996 997 if (Subtarget->hasAVX2()) { 998 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 999 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 1000 1001 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 1002 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 1003 1004 setOperationAction(ISD::SRA, MVT::v4i32, Legal); 1005 } else { 1006 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1007 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1008 1009 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1010 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1011 1012 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 1013 } 1014 } 1015 1016 if (Subtarget->hasSSE42()) 1017 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 1018 1019 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) { 1020 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 1021 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 1022 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 1023 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 1024 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 1025 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 1026 1027 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 1028 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 1029 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 1030 1031 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 1032 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 1033 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 1034 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 1035 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 1036 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 1037 1038 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 1039 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1040 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 1041 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 1042 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 1043 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 1044 1045 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1046 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1047 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1048 1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1051 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1052 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1053 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1054 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1055 1056 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1057 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1058 1059 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1060 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1061 1062 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1063 setOperationAction(ISD::SRA, MVT::v32i8, Custom); 1064 1065 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1066 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1067 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1068 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1069 1070 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1071 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1072 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1073 1074 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1075 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1076 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1077 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1078 1079 if (Subtarget->hasAVX2()) { 1080 setOperationAction(ISD::ADD, MVT::v4i64, Legal); 1081 setOperationAction(ISD::ADD, MVT::v8i32, Legal); 1082 setOperationAction(ISD::ADD, MVT::v16i16, Legal); 1083 setOperationAction(ISD::ADD, MVT::v32i8, Legal); 1084 1085 setOperationAction(ISD::SUB, MVT::v4i64, Legal); 1086 setOperationAction(ISD::SUB, MVT::v8i32, Legal); 1087 setOperationAction(ISD::SUB, MVT::v16i16, Legal); 1088 setOperationAction(ISD::SUB, MVT::v32i8, Legal); 1089 1090 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1091 setOperationAction(ISD::MUL, MVT::v8i32, Legal); 1092 setOperationAction(ISD::MUL, MVT::v16i16, Legal); 1093 // Don't lower v32i8 because there is no 128-bit byte mul 1094 1095 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); 1096 1097 setOperationAction(ISD::SRL, MVT::v4i64, Legal); 1098 setOperationAction(ISD::SRL, MVT::v8i32, Legal); 1099 1100 setOperationAction(ISD::SHL, MVT::v4i64, Legal); 1101 setOperationAction(ISD::SHL, MVT::v8i32, Legal); 1102 1103 setOperationAction(ISD::SRA, MVT::v8i32, Legal); 1104 } else { 1105 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1106 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1107 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1108 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1109 1110 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1111 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1112 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1113 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1114 1115 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1116 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1117 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1118 // Don't lower v32i8 because there is no 128-bit byte mul 1119 1120 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1121 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1122 1123 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1124 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1125 1126 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1127 } 1128 1129 // Custom lower several nodes for 256-bit types. 1130 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1131 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1132 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1133 EVT VT = SVT; 1134 1135 // Extract subvector is special because the value type 1136 // (result) is 128-bit but the source is 256-bit wide. 1137 if (VT.is128BitVector()) 1138 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1139 1140 // Do not attempt to custom lower other non-256-bit vectors 1141 if (!VT.is256BitVector()) 1142 continue; 1143 1144 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1145 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1146 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1147 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1148 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1149 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1150 } 1151 1152 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1153 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1154 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1155 EVT VT = SVT; 1156 1157 // Do not attempt to promote non-256-bit vectors 1158 if (!VT.is256BitVector()) 1159 continue; 1160 1161 setOperationAction(ISD::AND, SVT, Promote); 1162 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1163 setOperationAction(ISD::OR, SVT, Promote); 1164 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1165 setOperationAction(ISD::XOR, SVT, Promote); 1166 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1167 setOperationAction(ISD::LOAD, SVT, Promote); 1168 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1169 setOperationAction(ISD::SELECT, SVT, Promote); 1170 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1171 } 1172 } 1173 1174 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1175 // of this type with custom code. 1176 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1177 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1178 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 1179 Custom); 1180 } 1181 1182 // We want to custom lower some of our intrinsics. 1183 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1184 1185 1186 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1187 // handle type legalization for these operations here. 1188 // 1189 // FIXME: We really should do custom legalization for addition and 1190 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1191 // than generic legalization for 64-bit multiplication-with-overflow, though. 1192 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1193 // Add/Sub/Mul with overflow operations are custom lowered. 1194 MVT VT = IntVTs[i]; 1195 setOperationAction(ISD::SADDO, VT, Custom); 1196 setOperationAction(ISD::UADDO, VT, Custom); 1197 setOperationAction(ISD::SSUBO, VT, Custom); 1198 setOperationAction(ISD::USUBO, VT, Custom); 1199 setOperationAction(ISD::SMULO, VT, Custom); 1200 setOperationAction(ISD::UMULO, VT, Custom); 1201 } 1202 1203 // There are no 8-bit 3-address imul/mul instructions 1204 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1205 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1206 1207 if (!Subtarget->is64Bit()) { 1208 // These libcalls are not available in 32-bit. 1209 setLibcallName(RTLIB::SHL_I128, 0); 1210 setLibcallName(RTLIB::SRL_I128, 0); 1211 setLibcallName(RTLIB::SRA_I128, 0); 1212 } 1213 1214 // We have target-specific dag combine patterns for the following nodes: 1215 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1216 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1217 setTargetDAGCombine(ISD::VSELECT); 1218 setTargetDAGCombine(ISD::SELECT); 1219 setTargetDAGCombine(ISD::SHL); 1220 setTargetDAGCombine(ISD::SRA); 1221 setTargetDAGCombine(ISD::SRL); 1222 setTargetDAGCombine(ISD::OR); 1223 setTargetDAGCombine(ISD::AND); 1224 setTargetDAGCombine(ISD::ADD); 1225 setTargetDAGCombine(ISD::FADD); 1226 setTargetDAGCombine(ISD::FSUB); 1227 setTargetDAGCombine(ISD::SUB); 1228 setTargetDAGCombine(ISD::LOAD); 1229 setTargetDAGCombine(ISD::STORE); 1230 setTargetDAGCombine(ISD::ZERO_EXTEND); 1231 setTargetDAGCombine(ISD::SINT_TO_FP); 1232 if (Subtarget->is64Bit()) 1233 setTargetDAGCombine(ISD::MUL); 1234 if (Subtarget->hasBMI()) 1235 setTargetDAGCombine(ISD::XOR); 1236 1237 computeRegisterProperties(); 1238 1239 // On Darwin, -Os means optimize for size without hurting performance, 1240 // do not reduce the limit. 1241 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1242 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1243 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1244 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1245 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1246 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1247 setPrefLoopAlignment(4); // 2^4 bytes. 1248 benefitFromCodePlacementOpt = true; 1249 1250 setPrefFunctionAlignment(4); // 2^4 bytes. 1251} 1252 1253 1254EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1255 if (!VT.isVector()) return MVT::i8; 1256 return VT.changeVectorElementTypeToInteger(); 1257} 1258 1259 1260/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1261/// the desired ByVal argument alignment. 1262static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1263 if (MaxAlign == 16) 1264 return; 1265 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1266 if (VTy->getBitWidth() == 128) 1267 MaxAlign = 16; 1268 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1269 unsigned EltAlign = 0; 1270 getMaxByValAlign(ATy->getElementType(), EltAlign); 1271 if (EltAlign > MaxAlign) 1272 MaxAlign = EltAlign; 1273 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1274 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1275 unsigned EltAlign = 0; 1276 getMaxByValAlign(STy->getElementType(i), EltAlign); 1277 if (EltAlign > MaxAlign) 1278 MaxAlign = EltAlign; 1279 if (MaxAlign == 16) 1280 break; 1281 } 1282 } 1283 return; 1284} 1285 1286/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1287/// function arguments in the caller parameter area. For X86, aggregates 1288/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1289/// are at 4-byte boundaries. 1290unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1291 if (Subtarget->is64Bit()) { 1292 // Max of 8 and alignment of type. 1293 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1294 if (TyAlign > 8) 1295 return TyAlign; 1296 return 8; 1297 } 1298 1299 unsigned Align = 4; 1300 if (Subtarget->hasSSE1()) 1301 getMaxByValAlign(Ty, Align); 1302 return Align; 1303} 1304 1305/// getOptimalMemOpType - Returns the target specific optimal type for load 1306/// and store operations as a result of memset, memcpy, and memmove 1307/// lowering. If DstAlign is zero that means it's safe to destination 1308/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1309/// means there isn't a need to check it against alignment requirement, 1310/// probably because the source does not need to be loaded. If 1311/// 'IsZeroVal' is true, that means it's safe to return a 1312/// non-scalar-integer type, e.g. empty string source, constant, or loaded 1313/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1314/// constant so it does not need to be loaded. 1315/// It returns EVT::Other if the type should be determined using generic 1316/// target-independent logic. 1317EVT 1318X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1319 unsigned DstAlign, unsigned SrcAlign, 1320 bool IsZeroVal, 1321 bool MemcpyStrSrc, 1322 MachineFunction &MF) const { 1323 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1324 // linux. This is because the stack realignment code can't handle certain 1325 // cases like PR2962. This should be removed when PR2962 is fixed. 1326 const Function *F = MF.getFunction(); 1327 if (IsZeroVal && 1328 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1329 if (Size >= 16 && 1330 (Subtarget->isUnalignedMemAccessFast() || 1331 ((DstAlign == 0 || DstAlign >= 16) && 1332 (SrcAlign == 0 || SrcAlign >= 16))) && 1333 Subtarget->getStackAlignment() >= 16) { 1334 if (Subtarget->getStackAlignment() >= 32) { 1335 if (Subtarget->hasAVX2()) 1336 return MVT::v8i32; 1337 if (Subtarget->hasAVX()) 1338 return MVT::v8f32; 1339 } 1340 if (Subtarget->hasSSE2()) 1341 return MVT::v4i32; 1342 if (Subtarget->hasSSE1()) 1343 return MVT::v4f32; 1344 } else if (!MemcpyStrSrc && Size >= 8 && 1345 !Subtarget->is64Bit() && 1346 Subtarget->getStackAlignment() >= 8 && 1347 Subtarget->hasSSE2()) { 1348 // Do not use f64 to lower memcpy if source is string constant. It's 1349 // better to use i32 to avoid the loads. 1350 return MVT::f64; 1351 } 1352 } 1353 if (Subtarget->is64Bit() && Size >= 8) 1354 return MVT::i64; 1355 return MVT::i32; 1356} 1357 1358/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1359/// current function. The returned value is a member of the 1360/// MachineJumpTableInfo::JTEntryKind enum. 1361unsigned X86TargetLowering::getJumpTableEncoding() const { 1362 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1363 // symbol. 1364 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1365 Subtarget->isPICStyleGOT()) 1366 return MachineJumpTableInfo::EK_Custom32; 1367 1368 // Otherwise, use the normal jump table encoding heuristics. 1369 return TargetLowering::getJumpTableEncoding(); 1370} 1371 1372const MCExpr * 1373X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1374 const MachineBasicBlock *MBB, 1375 unsigned uid,MCContext &Ctx) const{ 1376 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1377 Subtarget->isPICStyleGOT()); 1378 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1379 // entries. 1380 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1381 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1382} 1383 1384/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1385/// jumptable. 1386SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1387 SelectionDAG &DAG) const { 1388 if (!Subtarget->is64Bit()) 1389 // This doesn't have DebugLoc associated with it, but is not really the 1390 // same as a Register. 1391 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1392 return Table; 1393} 1394 1395/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1396/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1397/// MCExpr. 1398const MCExpr *X86TargetLowering:: 1399getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1400 MCContext &Ctx) const { 1401 // X86-64 uses RIP relative addressing based on the jump table label. 1402 if (Subtarget->isPICStyleRIPRel()) 1403 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1404 1405 // Otherwise, the reference is relative to the PIC base. 1406 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1407} 1408 1409// FIXME: Why this routine is here? Move to RegInfo! 1410std::pair<const TargetRegisterClass*, uint8_t> 1411X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1412 const TargetRegisterClass *RRC = 0; 1413 uint8_t Cost = 1; 1414 switch (VT.getSimpleVT().SimpleTy) { 1415 default: 1416 return TargetLowering::findRepresentativeClass(VT); 1417 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1418 RRC = (Subtarget->is64Bit() 1419 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1420 break; 1421 case MVT::x86mmx: 1422 RRC = X86::VR64RegisterClass; 1423 break; 1424 case MVT::f32: case MVT::f64: 1425 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1426 case MVT::v4f32: case MVT::v2f64: 1427 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1428 case MVT::v4f64: 1429 RRC = X86::VR128RegisterClass; 1430 break; 1431 } 1432 return std::make_pair(RRC, Cost); 1433} 1434 1435bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1436 unsigned &Offset) const { 1437 if (!Subtarget->isTargetLinux()) 1438 return false; 1439 1440 if (Subtarget->is64Bit()) { 1441 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1442 Offset = 0x28; 1443 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1444 AddressSpace = 256; 1445 else 1446 AddressSpace = 257; 1447 } else { 1448 // %gs:0x14 on i386 1449 Offset = 0x14; 1450 AddressSpace = 256; 1451 } 1452 return true; 1453} 1454 1455 1456//===----------------------------------------------------------------------===// 1457// Return Value Calling Convention Implementation 1458//===----------------------------------------------------------------------===// 1459 1460#include "X86GenCallingConv.inc" 1461 1462bool 1463X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1464 MachineFunction &MF, bool isVarArg, 1465 const SmallVectorImpl<ISD::OutputArg> &Outs, 1466 LLVMContext &Context) const { 1467 SmallVector<CCValAssign, 16> RVLocs; 1468 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1469 RVLocs, Context); 1470 return CCInfo.CheckReturn(Outs, RetCC_X86); 1471} 1472 1473SDValue 1474X86TargetLowering::LowerReturn(SDValue Chain, 1475 CallingConv::ID CallConv, bool isVarArg, 1476 const SmallVectorImpl<ISD::OutputArg> &Outs, 1477 const SmallVectorImpl<SDValue> &OutVals, 1478 DebugLoc dl, SelectionDAG &DAG) const { 1479 MachineFunction &MF = DAG.getMachineFunction(); 1480 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1481 1482 SmallVector<CCValAssign, 16> RVLocs; 1483 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1484 RVLocs, *DAG.getContext()); 1485 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1486 1487 // Add the regs to the liveout set for the function. 1488 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1489 for (unsigned i = 0; i != RVLocs.size(); ++i) 1490 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1491 MRI.addLiveOut(RVLocs[i].getLocReg()); 1492 1493 SDValue Flag; 1494 1495 SmallVector<SDValue, 6> RetOps; 1496 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1497 // Operand #1 = Bytes To Pop 1498 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1499 MVT::i16)); 1500 1501 // Copy the result values into the output registers. 1502 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1503 CCValAssign &VA = RVLocs[i]; 1504 assert(VA.isRegLoc() && "Can only return in registers!"); 1505 SDValue ValToCopy = OutVals[i]; 1506 EVT ValVT = ValToCopy.getValueType(); 1507 1508 // If this is x86-64, and we disabled SSE, we can't return FP values, 1509 // or SSE or MMX vectors. 1510 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1511 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1512 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) { 1513 report_fatal_error("SSE register return with SSE disabled"); 1514 } 1515 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1516 // llvm-gcc has never done it right and no one has noticed, so this 1517 // should be OK for now. 1518 if (ValVT == MVT::f64 && 1519 (Subtarget->is64Bit() && !Subtarget->hasSSE2())) 1520 report_fatal_error("SSE2 register return with SSE2 disabled"); 1521 1522 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1523 // the RET instruction and handled by the FP Stackifier. 1524 if (VA.getLocReg() == X86::ST0 || 1525 VA.getLocReg() == X86::ST1) { 1526 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1527 // change the value to the FP stack register class. 1528 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1529 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1530 RetOps.push_back(ValToCopy); 1531 // Don't emit a copytoreg. 1532 continue; 1533 } 1534 1535 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1536 // which is returned in RAX / RDX. 1537 if (Subtarget->is64Bit()) { 1538 if (ValVT == MVT::x86mmx) { 1539 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1540 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1541 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1542 ValToCopy); 1543 // If we don't have SSE2 available, convert to v4f32 so the generated 1544 // register is legal. 1545 if (!Subtarget->hasSSE2()) 1546 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1547 } 1548 } 1549 } 1550 1551 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1552 Flag = Chain.getValue(1); 1553 } 1554 1555 // The x86-64 ABI for returning structs by value requires that we copy 1556 // the sret argument into %rax for the return. We saved the argument into 1557 // a virtual register in the entry block, so now we copy the value out 1558 // and into %rax. 1559 if (Subtarget->is64Bit() && 1560 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1561 MachineFunction &MF = DAG.getMachineFunction(); 1562 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1563 unsigned Reg = FuncInfo->getSRetReturnReg(); 1564 assert(Reg && 1565 "SRetReturnReg should have been set in LowerFormalArguments()."); 1566 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1567 1568 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1569 Flag = Chain.getValue(1); 1570 1571 // RAX now acts like a return value. 1572 MRI.addLiveOut(X86::RAX); 1573 } 1574 1575 RetOps[0] = Chain; // Update chain. 1576 1577 // Add the flag if we have it. 1578 if (Flag.getNode()) 1579 RetOps.push_back(Flag); 1580 1581 return DAG.getNode(X86ISD::RET_FLAG, dl, 1582 MVT::Other, &RetOps[0], RetOps.size()); 1583} 1584 1585bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1586 if (N->getNumValues() != 1) 1587 return false; 1588 if (!N->hasNUsesOfValue(1, 0)) 1589 return false; 1590 1591 SDNode *Copy = *N->use_begin(); 1592 if (Copy->getOpcode() != ISD::CopyToReg && 1593 Copy->getOpcode() != ISD::FP_EXTEND) 1594 return false; 1595 1596 bool HasRet = false; 1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1598 UI != UE; ++UI) { 1599 if (UI->getOpcode() != X86ISD::RET_FLAG) 1600 return false; 1601 HasRet = true; 1602 } 1603 1604 return HasRet; 1605} 1606 1607EVT 1608X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1609 ISD::NodeType ExtendKind) const { 1610 MVT ReturnMVT; 1611 // TODO: Is this also valid on 32-bit? 1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1613 ReturnMVT = MVT::i8; 1614 else 1615 ReturnMVT = MVT::i32; 1616 1617 EVT MinVT = getRegisterType(Context, ReturnMVT); 1618 return VT.bitsLT(MinVT) ? MinVT : VT; 1619} 1620 1621/// LowerCallResult - Lower the result values of a call into the 1622/// appropriate copies out of appropriate physical registers. 1623/// 1624SDValue 1625X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1626 CallingConv::ID CallConv, bool isVarArg, 1627 const SmallVectorImpl<ISD::InputArg> &Ins, 1628 DebugLoc dl, SelectionDAG &DAG, 1629 SmallVectorImpl<SDValue> &InVals) const { 1630 1631 // Assign locations to each value returned by this call. 1632 SmallVector<CCValAssign, 16> RVLocs; 1633 bool Is64Bit = Subtarget->is64Bit(); 1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1635 getTargetMachine(), RVLocs, *DAG.getContext()); 1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1637 1638 // Copy all of the result registers out of their specified physreg. 1639 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1640 CCValAssign &VA = RVLocs[i]; 1641 EVT CopyVT = VA.getValVT(); 1642 1643 // If this is x86-64, and we disabled SSE, we can't return FP values 1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1646 report_fatal_error("SSE register return with SSE disabled"); 1647 } 1648 1649 SDValue Val; 1650 1651 // If this is a call to a function that returns an fp value on the floating 1652 // point stack, we must guarantee the the value is popped from the stack, so 1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1654 // if the return value is not used. We use the FpPOP_RETVAL instruction 1655 // instead. 1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1657 // If we prefer to use the value in xmm registers, copy it out as f80 and 1658 // use a truncate to move it from fp stack reg to xmm reg. 1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1660 SDValue Ops[] = { Chain, InFlag }; 1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1662 MVT::Other, MVT::Glue, Ops, 2), 1); 1663 Val = Chain.getValue(0); 1664 1665 // Round the f80 to the right size, which also moves it to the appropriate 1666 // xmm register. 1667 if (CopyVT != VA.getValVT()) 1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1669 // This truncation won't change the value. 1670 DAG.getIntPtrConstant(1)); 1671 } else { 1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1673 CopyVT, InFlag).getValue(1); 1674 Val = Chain.getValue(0); 1675 } 1676 InFlag = Chain.getValue(2); 1677 InVals.push_back(Val); 1678 } 1679 1680 return Chain; 1681} 1682 1683 1684//===----------------------------------------------------------------------===// 1685// C & StdCall & Fast Calling Convention implementation 1686//===----------------------------------------------------------------------===// 1687// StdCall calling convention seems to be standard for many Windows' API 1688// routines and around. It differs from C calling convention just a little: 1689// callee should clean up the stack, not caller. Symbols should be also 1690// decorated in some fancy way :) It doesn't support any vector arguments. 1691// For info on fast calling convention see Fast Calling Convention (tail call) 1692// implementation LowerX86_32FastCCCallTo. 1693 1694/// CallIsStructReturn - Determines whether a call uses struct return 1695/// semantics. 1696static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1697 if (Outs.empty()) 1698 return false; 1699 1700 return Outs[0].Flags.isSRet(); 1701} 1702 1703/// ArgsAreStructReturn - Determines whether a function uses struct 1704/// return semantics. 1705static bool 1706ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1707 if (Ins.empty()) 1708 return false; 1709 1710 return Ins[0].Flags.isSRet(); 1711} 1712 1713/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1714/// by "Src" to address "Dst" with size and alignment information specified by 1715/// the specific parameter attribute. The copy will be passed as a byval 1716/// function parameter. 1717static SDValue 1718CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1720 DebugLoc dl) { 1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1722 1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1724 /*isVolatile*/false, /*AlwaysInline=*/true, 1725 MachinePointerInfo(), MachinePointerInfo()); 1726} 1727 1728/// IsTailCallConvention - Return true if the calling convention is one that 1729/// supports tail call optimization. 1730static bool IsTailCallConvention(CallingConv::ID CC) { 1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1732} 1733 1734bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls) 1736 return false; 1737 1738 CallSite CS(CI); 1739 CallingConv::ID CalleeCC = CS.getCallingConv(); 1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1741 return false; 1742 1743 return true; 1744} 1745 1746/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1747/// a tailcall target by changing its ABI. 1748static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, 1749 bool GuaranteedTailCallOpt) { 1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1751} 1752 1753SDValue 1754X86TargetLowering::LowerMemArgument(SDValue Chain, 1755 CallingConv::ID CallConv, 1756 const SmallVectorImpl<ISD::InputArg> &Ins, 1757 DebugLoc dl, SelectionDAG &DAG, 1758 const CCValAssign &VA, 1759 MachineFrameInfo *MFI, 1760 unsigned i) const { 1761 // Create the nodes corresponding to a load from this parameter slot. 1762 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv, 1764 getTargetMachine().Options.GuaranteedTailCallOpt); 1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1766 EVT ValVT; 1767 1768 // If value is passed by pointer we have address passed instead of the value 1769 // itself. 1770 if (VA.getLocInfo() == CCValAssign::Indirect) 1771 ValVT = VA.getLocVT(); 1772 else 1773 ValVT = VA.getValVT(); 1774 1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1776 // changed with more analysis. 1777 // In case of tail call optimization mark all arguments mutable. Since they 1778 // could be overwritten by lowering of arguments in case of a tail call. 1779 if (Flags.isByVal()) { 1780 unsigned Bytes = Flags.getByValSize(); 1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1783 return DAG.getFrameIndex(FI, getPointerTy()); 1784 } else { 1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1786 VA.getLocMemOffset(), isImmutable); 1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1788 return DAG.getLoad(ValVT, dl, Chain, FIN, 1789 MachinePointerInfo::getFixedStack(FI), 1790 false, false, false, 0); 1791 } 1792} 1793 1794SDValue 1795X86TargetLowering::LowerFormalArguments(SDValue Chain, 1796 CallingConv::ID CallConv, 1797 bool isVarArg, 1798 const SmallVectorImpl<ISD::InputArg> &Ins, 1799 DebugLoc dl, 1800 SelectionDAG &DAG, 1801 SmallVectorImpl<SDValue> &InVals) 1802 const { 1803 MachineFunction &MF = DAG.getMachineFunction(); 1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1805 1806 const Function* Fn = MF.getFunction(); 1807 if (Fn->hasExternalLinkage() && 1808 Subtarget->isTargetCygMing() && 1809 Fn->getName() == "main") 1810 FuncInfo->setForceFramePointer(true); 1811 1812 MachineFrameInfo *MFI = MF.getFrameInfo(); 1813 bool Is64Bit = Subtarget->is64Bit(); 1814 bool IsWindows = Subtarget->isTargetWindows(); 1815 bool IsWin64 = Subtarget->isTargetWin64(); 1816 1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1818 "Var args not supported with calling convention fastcc or ghc"); 1819 1820 // Assign locations to all of the incoming arguments. 1821 SmallVector<CCValAssign, 16> ArgLocs; 1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1823 ArgLocs, *DAG.getContext()); 1824 1825 // Allocate shadow area for Win64 1826 if (IsWin64) { 1827 CCInfo.AllocateStack(32, 8); 1828 } 1829 1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1831 1832 unsigned LastVal = ~0U; 1833 SDValue ArgValue; 1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1835 CCValAssign &VA = ArgLocs[i]; 1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1837 // places. 1838 assert(VA.getValNo() != LastVal && 1839 "Don't support value assigned to multiple locs yet"); 1840 (void)LastVal; 1841 LastVal = VA.getValNo(); 1842 1843 if (VA.isRegLoc()) { 1844 EVT RegVT = VA.getLocVT(); 1845 TargetRegisterClass *RC = NULL; 1846 if (RegVT == MVT::i32) 1847 RC = X86::GR32RegisterClass; 1848 else if (Is64Bit && RegVT == MVT::i64) 1849 RC = X86::GR64RegisterClass; 1850 else if (RegVT == MVT::f32) 1851 RC = X86::FR32RegisterClass; 1852 else if (RegVT == MVT::f64) 1853 RC = X86::FR64RegisterClass; 1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1855 RC = X86::VR256RegisterClass; 1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1857 RC = X86::VR128RegisterClass; 1858 else if (RegVT == MVT::x86mmx) 1859 RC = X86::VR64RegisterClass; 1860 else 1861 llvm_unreachable("Unknown argument type!"); 1862 1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1865 1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1868 // right size. 1869 if (VA.getLocInfo() == CCValAssign::SExt) 1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1871 DAG.getValueType(VA.getValVT())); 1872 else if (VA.getLocInfo() == CCValAssign::ZExt) 1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1874 DAG.getValueType(VA.getValVT())); 1875 else if (VA.getLocInfo() == CCValAssign::BCvt) 1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1877 1878 if (VA.isExtInLoc()) { 1879 // Handle MMX values passed in XMM regs. 1880 if (RegVT.isVector()) { 1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1882 ArgValue); 1883 } else 1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1885 } 1886 } else { 1887 assert(VA.isMemLoc()); 1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1889 } 1890 1891 // If value is passed via pointer - do a load. 1892 if (VA.getLocInfo() == CCValAssign::Indirect) 1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1894 MachinePointerInfo(), false, false, false, 0); 1895 1896 InVals.push_back(ArgValue); 1897 } 1898 1899 // The x86-64 ABI for returning structs by value requires that we copy 1900 // the sret argument into %rax for the return. Save the argument into 1901 // a virtual register so that we can access it from the return points. 1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1904 unsigned Reg = FuncInfo->getSRetReturnReg(); 1905 if (!Reg) { 1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1907 FuncInfo->setSRetReturnReg(Reg); 1908 } 1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1911 } 1912 1913 unsigned StackSize = CCInfo.getNextStackOffset(); 1914 // Align stack specially for tail calls. 1915 if (FuncIsMadeTailCallSafe(CallConv, 1916 MF.getTarget().Options.GuaranteedTailCallOpt)) 1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1918 1919 // If the function takes variable number of arguments, make a frame index for 1920 // the start of the first vararg value... for expansion of llvm.va_start. 1921 if (isVarArg) { 1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1923 CallConv != CallingConv::X86_ThisCall)) { 1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1925 } 1926 if (Is64Bit) { 1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1928 1929 // FIXME: We should really autogenerate these arrays 1930 static const unsigned GPR64ArgRegsWin64[] = { 1931 X86::RCX, X86::RDX, X86::R8, X86::R9 1932 }; 1933 static const unsigned GPR64ArgRegs64Bit[] = { 1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1935 }; 1936 static const unsigned XMMArgRegs64Bit[] = { 1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1939 }; 1940 const unsigned *GPR64ArgRegs; 1941 unsigned NumXMMRegs = 0; 1942 1943 if (IsWin64) { 1944 // The XMM registers which might contain var arg parameters are shadowed 1945 // in their paired GPR. So we only need to save the GPR to their home 1946 // slots. 1947 TotalNumIntRegs = 4; 1948 GPR64ArgRegs = GPR64ArgRegsWin64; 1949 } else { 1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1951 GPR64ArgRegs = GPR64ArgRegs64Bit; 1952 1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, 1954 TotalNumXMMRegs); 1955 } 1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1957 TotalNumIntRegs); 1958 1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1961 "SSE register cannot be used when SSE is disabled!"); 1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat && 1963 NoImplicitFloatOps) && 1964 "SSE register cannot be used when SSE is disabled!"); 1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps || 1966 !Subtarget->hasSSE1()) 1967 // Kernel mode asks for SSE to be disabled, so don't push them 1968 // on the stack. 1969 TotalNumXMMRegs = 0; 1970 1971 if (IsWin64) { 1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1973 // Get to the caller-allocated home save location. Add 8 to account 1974 // for the return address. 1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1976 FuncInfo->setRegSaveFrameIndex( 1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1978 // Fixup to set vararg frame on shadow area (4 x i64). 1979 if (NumIntRegs < 4) 1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1981 } else { 1982 // For X86-64, if there are vararg parameters that are passed via 1983 // registers, then we must store them to their spots on the stack so 1984 // they may be loaded by deferencing the result of va_next. 1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1987 FuncInfo->setRegSaveFrameIndex( 1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1989 false)); 1990 } 1991 1992 // Store the integer parameter registers. 1993 SmallVector<SDValue, 8> MemOps; 1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1995 getPointerTy()); 1996 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1999 DAG.getIntPtrConstant(Offset)); 2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 2001 X86::GR64RegisterClass); 2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2003 SDValue Store = 2004 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2005 MachinePointerInfo::getFixedStack( 2006 FuncInfo->getRegSaveFrameIndex(), Offset), 2007 false, false, 0); 2008 MemOps.push_back(Store); 2009 Offset += 8; 2010 } 2011 2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 2013 // Now store the XMM (fp + vector) parameter registers. 2014 SmallVector<SDValue, 11> SaveXMMOps; 2015 SaveXMMOps.push_back(Chain); 2016 2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 2019 SaveXMMOps.push_back(ALVal); 2020 2021 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2022 FuncInfo->getRegSaveFrameIndex())); 2023 SaveXMMOps.push_back(DAG.getIntPtrConstant( 2024 FuncInfo->getVarArgsFPOffset())); 2025 2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 2028 X86::VR128RegisterClass); 2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 2030 SaveXMMOps.push_back(Val); 2031 } 2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2033 MVT::Other, 2034 &SaveXMMOps[0], SaveXMMOps.size())); 2035 } 2036 2037 if (!MemOps.empty()) 2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2039 &MemOps[0], MemOps.size()); 2040 } 2041 } 2042 2043 // Some CCs need callee pop. 2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2045 MF.getTarget().Options.GuaranteedTailCallOpt)) { 2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 2047 } else { 2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 2049 // If this is an sret function, the return should pop the hidden pointer. 2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2051 ArgsAreStructReturn(Ins)) 2052 FuncInfo->setBytesToPopOnReturn(4); 2053 } 2054 2055 if (!Is64Bit) { 2056 // RegSaveFrameIndex is X86-64 only. 2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 2058 if (CallConv == CallingConv::X86_FastCall || 2059 CallConv == CallingConv::X86_ThisCall) 2060 // fastcc functions can't have varargs. 2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 2062 } 2063 2064 FuncInfo->setArgumentStackSize(StackSize); 2065 2066 return Chain; 2067} 2068 2069SDValue 2070X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 2071 SDValue StackPtr, SDValue Arg, 2072 DebugLoc dl, SelectionDAG &DAG, 2073 const CCValAssign &VA, 2074 ISD::ArgFlagsTy Flags) const { 2075 unsigned LocMemOffset = VA.getLocMemOffset(); 2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2078 if (Flags.isByVal()) 2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 2080 2081 return DAG.getStore(Chain, dl, Arg, PtrOff, 2082 MachinePointerInfo::getStack(LocMemOffset), 2083 false, false, 0); 2084} 2085 2086/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 2087/// optimization is performed and it is required. 2088SDValue 2089X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2090 SDValue &OutRetAddr, SDValue Chain, 2091 bool IsTailCall, bool Is64Bit, 2092 int FPDiff, DebugLoc dl) const { 2093 // Adjust the Return address stack slot. 2094 EVT VT = getPointerTy(); 2095 OutRetAddr = getReturnAddressFrameIndex(DAG); 2096 2097 // Load the "old" Return address. 2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2099 false, false, false, 0); 2100 return SDValue(OutRetAddr.getNode(), 1); 2101} 2102 2103/// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2104/// optimization is performed and it is required (FPDiff!=0). 2105static SDValue 2106EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2107 SDValue Chain, SDValue RetAddrFrIdx, 2108 bool Is64Bit, int FPDiff, DebugLoc dl) { 2109 // Store the return address to the appropriate stack slot. 2110 if (!FPDiff) return Chain; 2111 // Calculate the new stack slot for the return address. 2112 int SlotSize = Is64Bit ? 8 : 4; 2113 int NewReturnAddrFI = 2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2119 false, false, 0); 2120 return Chain; 2121} 2122 2123SDValue 2124X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2125 CallingConv::ID CallConv, bool isVarArg, 2126 bool &isTailCall, 2127 const SmallVectorImpl<ISD::OutputArg> &Outs, 2128 const SmallVectorImpl<SDValue> &OutVals, 2129 const SmallVectorImpl<ISD::InputArg> &Ins, 2130 DebugLoc dl, SelectionDAG &DAG, 2131 SmallVectorImpl<SDValue> &InVals) const { 2132 MachineFunction &MF = DAG.getMachineFunction(); 2133 bool Is64Bit = Subtarget->is64Bit(); 2134 bool IsWin64 = Subtarget->isTargetWin64(); 2135 bool IsWindows = Subtarget->isTargetWindows(); 2136 bool IsStructRet = CallIsStructReturn(Outs); 2137 bool IsSibcall = false; 2138 2139 if (MF.getTarget().Options.DisableTailCalls) 2140 isTailCall = false; 2141 2142 if (isTailCall) { 2143 // Check if it's really possible to do a tail call. 2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2146 Outs, OutVals, Ins, DAG); 2147 2148 // Sibcalls are automatically detected tailcalls which do not require 2149 // ABI changes. 2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall) 2151 IsSibcall = true; 2152 2153 if (isTailCall) 2154 ++NumTailCalls; 2155 } 2156 2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2158 "Var args not supported with calling convention fastcc or ghc"); 2159 2160 // Analyze operands of the call, assigning locations to each operand. 2161 SmallVector<CCValAssign, 16> ArgLocs; 2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2163 ArgLocs, *DAG.getContext()); 2164 2165 // Allocate shadow area for Win64 2166 if (IsWin64) { 2167 CCInfo.AllocateStack(32, 8); 2168 } 2169 2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2171 2172 // Get a count of how many bytes are to be pushed on the stack. 2173 unsigned NumBytes = CCInfo.getNextStackOffset(); 2174 if (IsSibcall) 2175 // This is a sibcall. The memory operands are available in caller's 2176 // own caller's stack. 2177 NumBytes = 0; 2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt && 2179 IsTailCallConvention(CallConv)) 2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2181 2182 int FPDiff = 0; 2183 if (isTailCall && !IsSibcall) { 2184 // Lower arguments at fp - stackoffset + fpdiff. 2185 unsigned NumBytesCallerPushed = 2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2187 FPDiff = NumBytesCallerPushed - NumBytes; 2188 2189 // Set the delta of movement of the returnaddr stackslot. 2190 // But only set if delta is greater than previous delta. 2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2193 } 2194 2195 if (!IsSibcall) 2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2197 2198 SDValue RetAddrFrIdx; 2199 // Load return address for tail calls. 2200 if (isTailCall && FPDiff) 2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2202 Is64Bit, FPDiff, dl); 2203 2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2205 SmallVector<SDValue, 8> MemOpChains; 2206 SDValue StackPtr; 2207 2208 // Walk the register/memloc assignments, inserting copies/loads. In the case 2209 // of tail call optimization arguments are handle later. 2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2211 CCValAssign &VA = ArgLocs[i]; 2212 EVT RegVT = VA.getLocVT(); 2213 SDValue Arg = OutVals[i]; 2214 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2215 bool isByVal = Flags.isByVal(); 2216 2217 // Promote the value if needed. 2218 switch (VA.getLocInfo()) { 2219 default: llvm_unreachable("Unknown loc info!"); 2220 case CCValAssign::Full: break; 2221 case CCValAssign::SExt: 2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2223 break; 2224 case CCValAssign::ZExt: 2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2226 break; 2227 case CCValAssign::AExt: 2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2229 // Special case: passing MMX values in XMM registers. 2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2233 } else 2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2235 break; 2236 case CCValAssign::BCvt: 2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2238 break; 2239 case CCValAssign::Indirect: { 2240 // Store the argument. 2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2244 MachinePointerInfo::getFixedStack(FI), 2245 false, false, 0); 2246 Arg = SpillSlot; 2247 break; 2248 } 2249 } 2250 2251 if (VA.isRegLoc()) { 2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2253 if (isVarArg && IsWin64) { 2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2255 // shadow reg if callee is a varargs function. 2256 unsigned ShadowReg = 0; 2257 switch (VA.getLocReg()) { 2258 case X86::XMM0: ShadowReg = X86::RCX; break; 2259 case X86::XMM1: ShadowReg = X86::RDX; break; 2260 case X86::XMM2: ShadowReg = X86::R8; break; 2261 case X86::XMM3: ShadowReg = X86::R9; break; 2262 } 2263 if (ShadowReg) 2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2265 } 2266 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2267 assert(VA.isMemLoc()); 2268 if (StackPtr.getNode() == 0) 2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2271 dl, DAG, VA, Flags)); 2272 } 2273 } 2274 2275 if (!MemOpChains.empty()) 2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2277 &MemOpChains[0], MemOpChains.size()); 2278 2279 // Build a sequence of copy-to-reg nodes chained together with token chain 2280 // and flag operands which copy the outgoing args into registers. 2281 SDValue InFlag; 2282 // Tail call byval lowering might overwrite argument registers so in case of 2283 // tail call optimization the copies to registers are lowered later. 2284 if (!isTailCall) 2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2287 RegsToPass[i].second, InFlag); 2288 InFlag = Chain.getValue(1); 2289 } 2290 2291 if (Subtarget->isPICStyleGOT()) { 2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2293 // GOT pointer. 2294 if (!isTailCall) { 2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2296 DAG.getNode(X86ISD::GlobalBaseReg, 2297 DebugLoc(), getPointerTy()), 2298 InFlag); 2299 InFlag = Chain.getValue(1); 2300 } else { 2301 // If we are tail calling and generating PIC/GOT style code load the 2302 // address of the callee into ECX. The value in ecx is used as target of 2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2304 // for tail calls on PIC/GOT architectures. Normally we would just put the 2305 // address of GOT into ebx and then call target@PLT. But for tail calls 2306 // ebx would be restored (since ebx is callee saved) before jumping to the 2307 // target@PLT. 2308 2309 // Note: The actual moving to ECX is done further down. 2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2311 if (G && !G->getGlobal()->hasHiddenVisibility() && 2312 !G->getGlobal()->hasProtectedVisibility()) 2313 Callee = LowerGlobalAddress(Callee, DAG); 2314 else if (isa<ExternalSymbolSDNode>(Callee)) 2315 Callee = LowerExternalSymbol(Callee, DAG); 2316 } 2317 } 2318 2319 if (Is64Bit && isVarArg && !IsWin64) { 2320 // From AMD64 ABI document: 2321 // For calls that may call functions that use varargs or stdargs 2322 // (prototype-less calls or calls to functions containing ellipsis (...) in 2323 // the declaration) %al is used as hidden argument to specify the number 2324 // of SSE registers used. The contents of %al do not need to match exactly 2325 // the number of registers, but must be an ubound on the number of SSE 2326 // registers used and is in the range 0 - 8 inclusive. 2327 2328 // Count the number of XMM registers allocated. 2329 static const unsigned XMMArgRegs[] = { 2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2332 }; 2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2334 assert((Subtarget->hasSSE1() || !NumXMMRegs) 2335 && "SSE registers cannot be used when SSE is disabled"); 2336 2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2339 InFlag = Chain.getValue(1); 2340 } 2341 2342 2343 // For tail calls lower the arguments to the 'real' stack slot. 2344 if (isTailCall) { 2345 // Force all the incoming stack arguments to be loaded from the stack 2346 // before any new outgoing arguments are stored to the stack, because the 2347 // outgoing stack slots may alias the incoming argument stack slots, and 2348 // the alias isn't otherwise explicit. This is slightly more conservative 2349 // than necessary, because it means that each store effectively depends 2350 // on every argument instead of just those arguments it would clobber. 2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2352 2353 SmallVector<SDValue, 8> MemOpChains2; 2354 SDValue FIN; 2355 int FI = 0; 2356 // Do not flag preceding copytoreg stuff together with the following stuff. 2357 InFlag = SDValue(); 2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2360 CCValAssign &VA = ArgLocs[i]; 2361 if (VA.isRegLoc()) 2362 continue; 2363 assert(VA.isMemLoc()); 2364 SDValue Arg = OutVals[i]; 2365 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2366 // Create frame index. 2367 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2370 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2371 2372 if (Flags.isByVal()) { 2373 // Copy relative to framepointer. 2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2375 if (StackPtr.getNode() == 0) 2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2377 getPointerTy()); 2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2379 2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2381 ArgChain, 2382 Flags, DAG, dl)); 2383 } else { 2384 // Store relative to framepointer. 2385 MemOpChains2.push_back( 2386 DAG.getStore(ArgChain, dl, Arg, FIN, 2387 MachinePointerInfo::getFixedStack(FI), 2388 false, false, 0)); 2389 } 2390 } 2391 } 2392 2393 if (!MemOpChains2.empty()) 2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2395 &MemOpChains2[0], MemOpChains2.size()); 2396 2397 // Copy arguments to their registers. 2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2400 RegsToPass[i].second, InFlag); 2401 InFlag = Chain.getValue(1); 2402 } 2403 InFlag =SDValue(); 2404 2405 // Store the return address to the appropriate stack slot. 2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2407 FPDiff, dl); 2408 } 2409 2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2412 // In the 64-bit large code model, we have to make all calls 2413 // through a register, since the call instruction's 32-bit 2414 // pc-relative offset may not be large enough to hold the whole 2415 // address. 2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2417 // If the callee is a GlobalAddress node (quite common, every direct call 2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2419 // it. 2420 2421 // We should use extra load for direct calls to dllimported functions in 2422 // non-JIT mode. 2423 const GlobalValue *GV = G->getGlobal(); 2424 if (!GV->hasDLLImportLinkage()) { 2425 unsigned char OpFlags = 0; 2426 bool ExtraLoad = false; 2427 unsigned WrapperKind = ISD::DELETED_NODE; 2428 2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2430 // external symbols most go through the PLT in PIC mode. If the symbol 2431 // has hidden or protected visibility, or if it is static or local, then 2432 // we don't need to use the PLT - we can directly call it. 2433 if (Subtarget->isTargetELF() && 2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2436 OpFlags = X86II::MO_PLT; 2437 } else if (Subtarget->isPICStyleStubAny() && 2438 (GV->isDeclaration() || GV->isWeakForLinker()) && 2439 (!Subtarget->getTargetTriple().isMacOSX() || 2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2441 // PC-relative references to external symbols should go through $stub, 2442 // unless we're building with the leopard linker or later, which 2443 // automatically synthesizes these stubs. 2444 OpFlags = X86II::MO_DARWIN_STUB; 2445 } else if (Subtarget->isPICStyleRIPRel() && 2446 isa<Function>(GV) && 2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2448 // If the function is marked as non-lazy, generate an indirect call 2449 // which loads from the GOT directly. This avoids runtime overhead 2450 // at the cost of eager binding (and one extra byte of encoding). 2451 OpFlags = X86II::MO_GOTPCREL; 2452 WrapperKind = X86ISD::WrapperRIP; 2453 ExtraLoad = true; 2454 } 2455 2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2457 G->getOffset(), OpFlags); 2458 2459 // Add a wrapper if needed. 2460 if (WrapperKind != ISD::DELETED_NODE) 2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2462 // Add extra indirection if needed. 2463 if (ExtraLoad) 2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2465 MachinePointerInfo::getGOT(), 2466 false, false, false, 0); 2467 } 2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2469 unsigned char OpFlags = 0; 2470 2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2472 // external symbols should go through the PLT. 2473 if (Subtarget->isTargetELF() && 2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2475 OpFlags = X86II::MO_PLT; 2476 } else if (Subtarget->isPICStyleStubAny() && 2477 (!Subtarget->getTargetTriple().isMacOSX() || 2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2479 // PC-relative references to external symbols should go through $stub, 2480 // unless we're building with the leopard linker or later, which 2481 // automatically synthesizes these stubs. 2482 OpFlags = X86II::MO_DARWIN_STUB; 2483 } 2484 2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2486 OpFlags); 2487 } 2488 2489 // Returns a chain & a flag for retval copy to use. 2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2491 SmallVector<SDValue, 8> Ops; 2492 2493 if (!IsSibcall && isTailCall) { 2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2495 DAG.getIntPtrConstant(0, true), InFlag); 2496 InFlag = Chain.getValue(1); 2497 } 2498 2499 Ops.push_back(Chain); 2500 Ops.push_back(Callee); 2501 2502 if (isTailCall) 2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2504 2505 // Add argument registers to the end of the list so that they are known live 2506 // into the call. 2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2509 RegsToPass[i].second.getValueType())); 2510 2511 // Add an implicit use GOT pointer in EBX. 2512 if (!isTailCall && Subtarget->isPICStyleGOT()) 2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2514 2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2516 if (Is64Bit && isVarArg && !IsWin64) 2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2518 2519 // Experimental: Add a register mask operand representing the call-preserved 2520 // registers. 2521 if (UseRegMask) { 2522 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2523 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 2524 Ops.push_back(DAG.getRegisterMask(Mask)); 2525 } 2526 2527 if (InFlag.getNode()) 2528 Ops.push_back(InFlag); 2529 2530 if (isTailCall) { 2531 // We used to do: 2532 //// If this is the first return lowered for this function, add the regs 2533 //// to the liveout set for the function. 2534 // This isn't right, although it's probably harmless on x86; liveouts 2535 // should be computed from returns not tail calls. Consider a void 2536 // function making a tail call to a function returning int. 2537 return DAG.getNode(X86ISD::TC_RETURN, dl, 2538 NodeTys, &Ops[0], Ops.size()); 2539 } 2540 2541 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2542 InFlag = Chain.getValue(1); 2543 2544 // Create the CALLSEQ_END node. 2545 unsigned NumBytesForCalleeToPush; 2546 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, 2547 getTargetMachine().Options.GuaranteedTailCallOpt)) 2548 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2549 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows && 2550 IsStructRet) 2551 // If this is a call to a struct-return function, the callee 2552 // pops the hidden struct pointer, so we have to push it back. 2553 // This is common for Darwin/X86, Linux & Mingw32 targets. 2554 // For MSVC Win32 targets, the caller pops the hidden struct pointer. 2555 NumBytesForCalleeToPush = 4; 2556 else 2557 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2558 2559 // Returns a flag for retval copy to use. 2560 if (!IsSibcall) { 2561 Chain = DAG.getCALLSEQ_END(Chain, 2562 DAG.getIntPtrConstant(NumBytes, true), 2563 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2564 true), 2565 InFlag); 2566 InFlag = Chain.getValue(1); 2567 } 2568 2569 // Handle result values, copying them out of physregs into vregs that we 2570 // return. 2571 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2572 Ins, dl, DAG, InVals); 2573} 2574 2575 2576//===----------------------------------------------------------------------===// 2577// Fast Calling Convention (tail call) implementation 2578//===----------------------------------------------------------------------===// 2579 2580// Like std call, callee cleans arguments, convention except that ECX is 2581// reserved for storing the tail called function address. Only 2 registers are 2582// free for argument passing (inreg). Tail call optimization is performed 2583// provided: 2584// * tailcallopt is enabled 2585// * caller/callee are fastcc 2586// On X86_64 architecture with GOT-style position independent code only local 2587// (within module) calls are supported at the moment. 2588// To keep the stack aligned according to platform abi the function 2589// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2590// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2591// If a tail called function callee has more arguments than the caller the 2592// caller needs to make sure that there is room to move the RETADDR to. This is 2593// achieved by reserving an area the size of the argument delta right after the 2594// original REtADDR, but before the saved framepointer or the spilled registers 2595// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2596// stack layout: 2597// arg1 2598// arg2 2599// RETADDR 2600// [ new RETADDR 2601// move area ] 2602// (possible EBP) 2603// ESI 2604// EDI 2605// local1 .. 2606 2607/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2608/// for a 16 byte align requirement. 2609unsigned 2610X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2611 SelectionDAG& DAG) const { 2612 MachineFunction &MF = DAG.getMachineFunction(); 2613 const TargetMachine &TM = MF.getTarget(); 2614 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2615 unsigned StackAlignment = TFI.getStackAlignment(); 2616 uint64_t AlignMask = StackAlignment - 1; 2617 int64_t Offset = StackSize; 2618 uint64_t SlotSize = TD->getPointerSize(); 2619 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2620 // Number smaller than 12 so just add the difference. 2621 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2622 } else { 2623 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2624 Offset = ((~AlignMask) & Offset) + StackAlignment + 2625 (StackAlignment-SlotSize); 2626 } 2627 return Offset; 2628} 2629 2630/// MatchingStackOffset - Return true if the given stack call argument is 2631/// already available in the same position (relatively) of the caller's 2632/// incoming argument stack. 2633static 2634bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2635 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2636 const X86InstrInfo *TII) { 2637 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2638 int FI = INT_MAX; 2639 if (Arg.getOpcode() == ISD::CopyFromReg) { 2640 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2641 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2642 return false; 2643 MachineInstr *Def = MRI->getVRegDef(VR); 2644 if (!Def) 2645 return false; 2646 if (!Flags.isByVal()) { 2647 if (!TII->isLoadFromStackSlot(Def, FI)) 2648 return false; 2649 } else { 2650 unsigned Opcode = Def->getOpcode(); 2651 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2652 Def->getOperand(1).isFI()) { 2653 FI = Def->getOperand(1).getIndex(); 2654 Bytes = Flags.getByValSize(); 2655 } else 2656 return false; 2657 } 2658 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2659 if (Flags.isByVal()) 2660 // ByVal argument is passed in as a pointer but it's now being 2661 // dereferenced. e.g. 2662 // define @foo(%struct.X* %A) { 2663 // tail call @bar(%struct.X* byval %A) 2664 // } 2665 return false; 2666 SDValue Ptr = Ld->getBasePtr(); 2667 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2668 if (!FINode) 2669 return false; 2670 FI = FINode->getIndex(); 2671 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2672 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2673 FI = FINode->getIndex(); 2674 Bytes = Flags.getByValSize(); 2675 } else 2676 return false; 2677 2678 assert(FI != INT_MAX); 2679 if (!MFI->isFixedObjectIndex(FI)) 2680 return false; 2681 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2682} 2683 2684/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2685/// for tail call optimization. Targets which want to do tail call 2686/// optimization should implement this function. 2687bool 2688X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2689 CallingConv::ID CalleeCC, 2690 bool isVarArg, 2691 bool isCalleeStructRet, 2692 bool isCallerStructRet, 2693 const SmallVectorImpl<ISD::OutputArg> &Outs, 2694 const SmallVectorImpl<SDValue> &OutVals, 2695 const SmallVectorImpl<ISD::InputArg> &Ins, 2696 SelectionDAG& DAG) const { 2697 if (!IsTailCallConvention(CalleeCC) && 2698 CalleeCC != CallingConv::C) 2699 return false; 2700 2701 // If -tailcallopt is specified, make fastcc functions tail-callable. 2702 const MachineFunction &MF = DAG.getMachineFunction(); 2703 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2704 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2705 bool CCMatch = CallerCC == CalleeCC; 2706 2707 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 2708 if (IsTailCallConvention(CalleeCC) && CCMatch) 2709 return true; 2710 return false; 2711 } 2712 2713 // Look for obvious safe cases to perform tail call optimization that do not 2714 // require ABI changes. This is what gcc calls sibcall. 2715 2716 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2717 // emit a special epilogue. 2718 if (RegInfo->needsStackRealignment(MF)) 2719 return false; 2720 2721 // Also avoid sibcall optimization if either caller or callee uses struct 2722 // return semantics. 2723 if (isCalleeStructRet || isCallerStructRet) 2724 return false; 2725 2726 // An stdcall caller is expected to clean up its arguments; the callee 2727 // isn't going to do that. 2728 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2729 return false; 2730 2731 // Do not sibcall optimize vararg calls unless all arguments are passed via 2732 // registers. 2733 if (isVarArg && !Outs.empty()) { 2734 2735 // Optimizing for varargs on Win64 is unlikely to be safe without 2736 // additional testing. 2737 if (Subtarget->isTargetWin64()) 2738 return false; 2739 2740 SmallVector<CCValAssign, 16> ArgLocs; 2741 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2742 getTargetMachine(), ArgLocs, *DAG.getContext()); 2743 2744 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2745 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2746 if (!ArgLocs[i].isRegLoc()) 2747 return false; 2748 } 2749 2750 // If the call result is in ST0 / ST1, it needs to be popped off the x87 2751 // stack. Therefore, if it's not used by the call it is not safe to optimize 2752 // this into a sibcall. 2753 bool Unused = false; 2754 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2755 if (!Ins[i].Used) { 2756 Unused = true; 2757 break; 2758 } 2759 } 2760 if (Unused) { 2761 SmallVector<CCValAssign, 16> RVLocs; 2762 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2763 getTargetMachine(), RVLocs, *DAG.getContext()); 2764 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2765 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2766 CCValAssign &VA = RVLocs[i]; 2767 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2768 return false; 2769 } 2770 } 2771 2772 // If the calling conventions do not match, then we'd better make sure the 2773 // results are returned in the same way as what the caller expects. 2774 if (!CCMatch) { 2775 SmallVector<CCValAssign, 16> RVLocs1; 2776 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2777 getTargetMachine(), RVLocs1, *DAG.getContext()); 2778 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2779 2780 SmallVector<CCValAssign, 16> RVLocs2; 2781 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2782 getTargetMachine(), RVLocs2, *DAG.getContext()); 2783 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2784 2785 if (RVLocs1.size() != RVLocs2.size()) 2786 return false; 2787 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2788 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2789 return false; 2790 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2791 return false; 2792 if (RVLocs1[i].isRegLoc()) { 2793 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2794 return false; 2795 } else { 2796 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2797 return false; 2798 } 2799 } 2800 } 2801 2802 // If the callee takes no arguments then go on to check the results of the 2803 // call. 2804 if (!Outs.empty()) { 2805 // Check if stack adjustment is needed. For now, do not do this if any 2806 // argument is passed on the stack. 2807 SmallVector<CCValAssign, 16> ArgLocs; 2808 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2809 getTargetMachine(), ArgLocs, *DAG.getContext()); 2810 2811 // Allocate shadow area for Win64 2812 if (Subtarget->isTargetWin64()) { 2813 CCInfo.AllocateStack(32, 8); 2814 } 2815 2816 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2817 if (CCInfo.getNextStackOffset()) { 2818 MachineFunction &MF = DAG.getMachineFunction(); 2819 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2820 return false; 2821 2822 // Check if the arguments are already laid out in the right way as 2823 // the caller's fixed stack objects. 2824 MachineFrameInfo *MFI = MF.getFrameInfo(); 2825 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2826 const X86InstrInfo *TII = 2827 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2829 CCValAssign &VA = ArgLocs[i]; 2830 SDValue Arg = OutVals[i]; 2831 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2832 if (VA.getLocInfo() == CCValAssign::Indirect) 2833 return false; 2834 if (!VA.isRegLoc()) { 2835 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2836 MFI, MRI, TII)) 2837 return false; 2838 } 2839 } 2840 } 2841 2842 // If the tailcall address may be in a register, then make sure it's 2843 // possible to register allocate for it. In 32-bit, the call address can 2844 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2845 // callee-saved registers are restored. These happen to be the same 2846 // registers used to pass 'inreg' arguments so watch out for those. 2847 if (!Subtarget->is64Bit() && 2848 !isa<GlobalAddressSDNode>(Callee) && 2849 !isa<ExternalSymbolSDNode>(Callee)) { 2850 unsigned NumInRegs = 0; 2851 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2852 CCValAssign &VA = ArgLocs[i]; 2853 if (!VA.isRegLoc()) 2854 continue; 2855 unsigned Reg = VA.getLocReg(); 2856 switch (Reg) { 2857 default: break; 2858 case X86::EAX: case X86::EDX: case X86::ECX: 2859 if (++NumInRegs == 3) 2860 return false; 2861 break; 2862 } 2863 } 2864 } 2865 } 2866 2867 return true; 2868} 2869 2870FastISel * 2871X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2872 return X86::createFastISel(funcInfo); 2873} 2874 2875 2876//===----------------------------------------------------------------------===// 2877// Other Lowering Hooks 2878//===----------------------------------------------------------------------===// 2879 2880static bool MayFoldLoad(SDValue Op) { 2881 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2882} 2883 2884static bool MayFoldIntoStore(SDValue Op) { 2885 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2886} 2887 2888static bool isTargetShuffle(unsigned Opcode) { 2889 switch(Opcode) { 2890 default: return false; 2891 case X86ISD::PSHUFD: 2892 case X86ISD::PSHUFHW: 2893 case X86ISD::PSHUFLW: 2894 case X86ISD::SHUFP: 2895 case X86ISD::PALIGN: 2896 case X86ISD::MOVLHPS: 2897 case X86ISD::MOVLHPD: 2898 case X86ISD::MOVHLPS: 2899 case X86ISD::MOVLPS: 2900 case X86ISD::MOVLPD: 2901 case X86ISD::MOVSHDUP: 2902 case X86ISD::MOVSLDUP: 2903 case X86ISD::MOVDDUP: 2904 case X86ISD::MOVSS: 2905 case X86ISD::MOVSD: 2906 case X86ISD::UNPCKL: 2907 case X86ISD::UNPCKH: 2908 case X86ISD::VPERMILP: 2909 case X86ISD::VPERM2X128: 2910 return true; 2911 } 2912} 2913 2914static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2915 SDValue V1, SelectionDAG &DAG) { 2916 switch(Opc) { 2917 default: llvm_unreachable("Unknown x86 shuffle node"); 2918 case X86ISD::MOVSHDUP: 2919 case X86ISD::MOVSLDUP: 2920 case X86ISD::MOVDDUP: 2921 return DAG.getNode(Opc, dl, VT, V1); 2922 } 2923} 2924 2925static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2926 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2927 switch(Opc) { 2928 default: llvm_unreachable("Unknown x86 shuffle node"); 2929 case X86ISD::PSHUFD: 2930 case X86ISD::PSHUFHW: 2931 case X86ISD::PSHUFLW: 2932 case X86ISD::VPERMILP: 2933 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2934 } 2935} 2936 2937static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2938 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2939 switch(Opc) { 2940 default: llvm_unreachable("Unknown x86 shuffle node"); 2941 case X86ISD::PALIGN: 2942 case X86ISD::SHUFP: 2943 case X86ISD::VPERM2X128: 2944 return DAG.getNode(Opc, dl, VT, V1, V2, 2945 DAG.getConstant(TargetMask, MVT::i8)); 2946 } 2947} 2948 2949static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2950 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2951 switch(Opc) { 2952 default: llvm_unreachable("Unknown x86 shuffle node"); 2953 case X86ISD::MOVLHPS: 2954 case X86ISD::MOVLHPD: 2955 case X86ISD::MOVHLPS: 2956 case X86ISD::MOVLPS: 2957 case X86ISD::MOVLPD: 2958 case X86ISD::MOVSS: 2959 case X86ISD::MOVSD: 2960 case X86ISD::UNPCKL: 2961 case X86ISD::UNPCKH: 2962 return DAG.getNode(Opc, dl, VT, V1, V2); 2963 } 2964} 2965 2966SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2967 MachineFunction &MF = DAG.getMachineFunction(); 2968 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2969 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2970 2971 if (ReturnAddrIndex == 0) { 2972 // Set up a frame object for the return address. 2973 uint64_t SlotSize = TD->getPointerSize(); 2974 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2975 false); 2976 FuncInfo->setRAIndex(ReturnAddrIndex); 2977 } 2978 2979 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2980} 2981 2982 2983bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2984 bool hasSymbolicDisplacement) { 2985 // Offset should fit into 32 bit immediate field. 2986 if (!isInt<32>(Offset)) 2987 return false; 2988 2989 // If we don't have a symbolic displacement - we don't have any extra 2990 // restrictions. 2991 if (!hasSymbolicDisplacement) 2992 return true; 2993 2994 // FIXME: Some tweaks might be needed for medium code model. 2995 if (M != CodeModel::Small && M != CodeModel::Kernel) 2996 return false; 2997 2998 // For small code model we assume that latest object is 16MB before end of 31 2999 // bits boundary. We may also accept pretty large negative constants knowing 3000 // that all objects are in the positive half of address space. 3001 if (M == CodeModel::Small && Offset < 16*1024*1024) 3002 return true; 3003 3004 // For kernel code model we know that all object resist in the negative half 3005 // of 32bits address space. We may not accept negative offsets, since they may 3006 // be just off and we may accept pretty large positive ones. 3007 if (M == CodeModel::Kernel && Offset > 0) 3008 return true; 3009 3010 return false; 3011} 3012 3013/// isCalleePop - Determines whether the callee is required to pop its 3014/// own arguments. Callee pop is necessary to support tail calls. 3015bool X86::isCalleePop(CallingConv::ID CallingConv, 3016 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 3017 if (IsVarArg) 3018 return false; 3019 3020 switch (CallingConv) { 3021 default: 3022 return false; 3023 case CallingConv::X86_StdCall: 3024 return !is64Bit; 3025 case CallingConv::X86_FastCall: 3026 return !is64Bit; 3027 case CallingConv::X86_ThisCall: 3028 return !is64Bit; 3029 case CallingConv::Fast: 3030 return TailCallOpt; 3031 case CallingConv::GHC: 3032 return TailCallOpt; 3033 } 3034} 3035 3036/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 3037/// specific condition code, returning the condition code and the LHS/RHS of the 3038/// comparison to make. 3039static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 3040 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 3041 if (!isFP) { 3042 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3043 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 3044 // X > -1 -> X == 0, jump !sign. 3045 RHS = DAG.getConstant(0, RHS.getValueType()); 3046 return X86::COND_NS; 3047 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 3048 // X < 0 -> X == 0, jump on sign. 3049 return X86::COND_S; 3050 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 3051 // X < 1 -> X <= 0 3052 RHS = DAG.getConstant(0, RHS.getValueType()); 3053 return X86::COND_LE; 3054 } 3055 } 3056 3057 switch (SetCCOpcode) { 3058 default: llvm_unreachable("Invalid integer condition!"); 3059 case ISD::SETEQ: return X86::COND_E; 3060 case ISD::SETGT: return X86::COND_G; 3061 case ISD::SETGE: return X86::COND_GE; 3062 case ISD::SETLT: return X86::COND_L; 3063 case ISD::SETLE: return X86::COND_LE; 3064 case ISD::SETNE: return X86::COND_NE; 3065 case ISD::SETULT: return X86::COND_B; 3066 case ISD::SETUGT: return X86::COND_A; 3067 case ISD::SETULE: return X86::COND_BE; 3068 case ISD::SETUGE: return X86::COND_AE; 3069 } 3070 } 3071 3072 // First determine if it is required or is profitable to flip the operands. 3073 3074 // If LHS is a foldable load, but RHS is not, flip the condition. 3075 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3076 !ISD::isNON_EXTLoad(RHS.getNode())) { 3077 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3078 std::swap(LHS, RHS); 3079 } 3080 3081 switch (SetCCOpcode) { 3082 default: break; 3083 case ISD::SETOLT: 3084 case ISD::SETOLE: 3085 case ISD::SETUGT: 3086 case ISD::SETUGE: 3087 std::swap(LHS, RHS); 3088 break; 3089 } 3090 3091 // On a floating point condition, the flags are set as follows: 3092 // ZF PF CF op 3093 // 0 | 0 | 0 | X > Y 3094 // 0 | 0 | 1 | X < Y 3095 // 1 | 0 | 0 | X == Y 3096 // 1 | 1 | 1 | unordered 3097 switch (SetCCOpcode) { 3098 default: llvm_unreachable("Condcode should be pre-legalized away"); 3099 case ISD::SETUEQ: 3100 case ISD::SETEQ: return X86::COND_E; 3101 case ISD::SETOLT: // flipped 3102 case ISD::SETOGT: 3103 case ISD::SETGT: return X86::COND_A; 3104 case ISD::SETOLE: // flipped 3105 case ISD::SETOGE: 3106 case ISD::SETGE: return X86::COND_AE; 3107 case ISD::SETUGT: // flipped 3108 case ISD::SETULT: 3109 case ISD::SETLT: return X86::COND_B; 3110 case ISD::SETUGE: // flipped 3111 case ISD::SETULE: 3112 case ISD::SETLE: return X86::COND_BE; 3113 case ISD::SETONE: 3114 case ISD::SETNE: return X86::COND_NE; 3115 case ISD::SETUO: return X86::COND_P; 3116 case ISD::SETO: return X86::COND_NP; 3117 case ISD::SETOEQ: 3118 case ISD::SETUNE: return X86::COND_INVALID; 3119 } 3120} 3121 3122/// hasFPCMov - is there a floating point cmov for the specific X86 condition 3123/// code. Current x86 isa includes the following FP cmov instructions: 3124/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3125static bool hasFPCMov(unsigned X86CC) { 3126 switch (X86CC) { 3127 default: 3128 return false; 3129 case X86::COND_B: 3130 case X86::COND_BE: 3131 case X86::COND_E: 3132 case X86::COND_P: 3133 case X86::COND_A: 3134 case X86::COND_AE: 3135 case X86::COND_NE: 3136 case X86::COND_NP: 3137 return true; 3138 } 3139} 3140 3141/// isFPImmLegal - Returns true if the target can instruction select the 3142/// specified FP immediate natively. If false, the legalizer will 3143/// materialize the FP immediate as a load from a constant pool. 3144bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3145 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3146 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3147 return true; 3148 } 3149 return false; 3150} 3151 3152/// isUndefOrInRange - Return true if Val is undef or if its value falls within 3153/// the specified range (L, H]. 3154static bool isUndefOrInRange(int Val, int Low, int Hi) { 3155 return (Val < 0) || (Val >= Low && Val < Hi); 3156} 3157 3158/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3159/// specified value. 3160static bool isUndefOrEqual(int Val, int CmpVal) { 3161 if (Val < 0 || Val == CmpVal) 3162 return true; 3163 return false; 3164} 3165 3166/// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3167/// from position Pos and ending in Pos+Size, falls within the specified 3168/// sequential range (L, L+Pos]. or is undef. 3169static bool isSequentialOrUndefInRange(ArrayRef<int> Mask, 3170 int Pos, int Size, int Low) { 3171 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3172 if (!isUndefOrEqual(Mask[i], Low)) 3173 return false; 3174 return true; 3175} 3176 3177/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3178/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3179/// the second operand. 3180static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) { 3181 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3182 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3183 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3184 return (Mask[0] < 2 && Mask[1] < 2); 3185 return false; 3186} 3187 3188bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3189 return ::isPSHUFDMask(N->getMask(), N->getValueType(0)); 3190} 3191 3192/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3193/// is suitable for input to PSHUFHW. 3194static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) { 3195 if (VT != MVT::v8i16) 3196 return false; 3197 3198 // Lower quadword copied in order or undef. 3199 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0)) 3200 return false; 3201 3202 // Upper quadword shuffled. 3203 for (unsigned i = 4; i != 8; ++i) 3204 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3205 return false; 3206 3207 return true; 3208} 3209 3210bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3211 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0)); 3212} 3213 3214/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3215/// is suitable for input to PSHUFLW. 3216static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) { 3217 if (VT != MVT::v8i16) 3218 return false; 3219 3220 // Upper quadword copied in order. 3221 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4)) 3222 return false; 3223 3224 // Lower quadword shuffled. 3225 for (unsigned i = 0; i != 4; ++i) 3226 if (Mask[i] >= 4) 3227 return false; 3228 3229 return true; 3230} 3231 3232bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3233 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0)); 3234} 3235 3236/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3237/// is suitable for input to PALIGNR. 3238static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, 3239 const X86Subtarget *Subtarget) { 3240 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) || 3241 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())) 3242 return false; 3243 3244 unsigned NumElts = VT.getVectorNumElements(); 3245 unsigned NumLanes = VT.getSizeInBits()/128; 3246 unsigned NumLaneElts = NumElts/NumLanes; 3247 3248 // Do not handle 64-bit element shuffles with palignr. 3249 if (NumLaneElts == 2) 3250 return false; 3251 3252 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) { 3253 unsigned i; 3254 for (i = 0; i != NumLaneElts; ++i) { 3255 if (Mask[i+l] >= 0) 3256 break; 3257 } 3258 3259 // Lane is all undef, go to next lane 3260 if (i == NumLaneElts) 3261 continue; 3262 3263 int Start = Mask[i+l]; 3264 3265 // Make sure its in this lane in one of the sources 3266 if (!isUndefOrInRange(Start, l, l+NumLaneElts) && 3267 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts)) 3268 return false; 3269 3270 // If not lane 0, then we must match lane 0 3271 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l)) 3272 return false; 3273 3274 // Correct second source to be contiguous with first source 3275 if (Start >= (int)NumElts) 3276 Start -= NumElts - NumLaneElts; 3277 3278 // Make sure we're shifting in the right direction. 3279 if (Start <= (int)(i+l)) 3280 return false; 3281 3282 Start -= i; 3283 3284 // Check the rest of the elements to see if they are consecutive. 3285 for (++i; i != NumLaneElts; ++i) { 3286 int Idx = Mask[i+l]; 3287 3288 // Make sure its in this lane 3289 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) && 3290 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts)) 3291 return false; 3292 3293 // If not lane 0, then we must match lane 0 3294 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l)) 3295 return false; 3296 3297 if (Idx >= (int)NumElts) 3298 Idx -= NumElts - NumLaneElts; 3299 3300 if (!isUndefOrEqual(Idx, Start+i)) 3301 return false; 3302 3303 } 3304 } 3305 3306 return true; 3307} 3308 3309/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3310/// the two vector operands have swapped position. 3311static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, 3312 unsigned NumElems) { 3313 for (unsigned i = 0; i != NumElems; ++i) { 3314 int idx = Mask[i]; 3315 if (idx < 0) 3316 continue; 3317 else if (idx < (int)NumElems) 3318 Mask[i] = idx + NumElems; 3319 else 3320 Mask[i] = idx - NumElems; 3321 } 3322} 3323 3324/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3325/// specifies a shuffle of elements that is suitable for input to 128/256-bit 3326/// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be 3327/// reverse of what x86 shuffles want. 3328static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX, 3329 bool Commuted = false) { 3330 if (!HasAVX && VT.getSizeInBits() == 256) 3331 return false; 3332 3333 unsigned NumElems = VT.getVectorNumElements(); 3334 unsigned NumLanes = VT.getSizeInBits()/128; 3335 unsigned NumLaneElems = NumElems/NumLanes; 3336 3337 if (NumLaneElems != 2 && NumLaneElems != 4) 3338 return false; 3339 3340 // VSHUFPSY divides the resulting vector into 4 chunks. 3341 // The sources are also splitted into 4 chunks, and each destination 3342 // chunk must come from a different source chunk. 3343 // 3344 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3345 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3346 // 3347 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3348 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3349 // 3350 // VSHUFPDY divides the resulting vector into 4 chunks. 3351 // The sources are also splitted into 4 chunks, and each destination 3352 // chunk must come from a different source chunk. 3353 // 3354 // SRC1 => X3 X2 X1 X0 3355 // SRC2 => Y3 Y2 Y1 Y0 3356 // 3357 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0 3358 // 3359 unsigned HalfLaneElems = NumLaneElems/2; 3360 for (unsigned l = 0; l != NumElems; l += NumLaneElems) { 3361 for (unsigned i = 0; i != NumLaneElems; ++i) { 3362 int Idx = Mask[i+l]; 3363 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0); 3364 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems)) 3365 return false; 3366 // For VSHUFPSY, the mask of the second half must be the same as the 3367 // first but with the appropriate offsets. This works in the same way as 3368 // VPERMILPS works with masks. 3369 if (NumElems != 8 || l == 0 || Mask[i] < 0) 3370 continue; 3371 if (!isUndefOrEqual(Idx, Mask[i]+l)) 3372 return false; 3373 } 3374 } 3375 3376 return true; 3377} 3378 3379bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) { 3380 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX); 3381} 3382 3383/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3384/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3385bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3386 EVT VT = N->getValueType(0); 3387 unsigned NumElems = VT.getVectorNumElements(); 3388 3389 if (VT.getSizeInBits() != 128) 3390 return false; 3391 3392 if (NumElems != 4) 3393 return false; 3394 3395 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3396 return isUndefOrEqual(N->getMaskElt(0), 6) && 3397 isUndefOrEqual(N->getMaskElt(1), 7) && 3398 isUndefOrEqual(N->getMaskElt(2), 2) && 3399 isUndefOrEqual(N->getMaskElt(3), 3); 3400} 3401 3402/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3403/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3404/// <2, 3, 2, 3> 3405bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3406 EVT VT = N->getValueType(0); 3407 unsigned NumElems = VT.getVectorNumElements(); 3408 3409 if (VT.getSizeInBits() != 128) 3410 return false; 3411 3412 if (NumElems != 4) 3413 return false; 3414 3415 return isUndefOrEqual(N->getMaskElt(0), 2) && 3416 isUndefOrEqual(N->getMaskElt(1), 3) && 3417 isUndefOrEqual(N->getMaskElt(2), 2) && 3418 isUndefOrEqual(N->getMaskElt(3), 3); 3419} 3420 3421/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3422/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3423bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3424 EVT VT = N->getValueType(0); 3425 3426 if (VT.getSizeInBits() != 128) 3427 return false; 3428 3429 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3430 3431 if (NumElems != 2 && NumElems != 4) 3432 return false; 3433 3434 for (unsigned i = 0; i < NumElems/2; ++i) 3435 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3436 return false; 3437 3438 for (unsigned i = NumElems/2; i < NumElems; ++i) 3439 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3440 return false; 3441 3442 return true; 3443} 3444 3445/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3446/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3447bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3448 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3449 3450 if ((NumElems != 2 && NumElems != 4) 3451 || N->getValueType(0).getSizeInBits() > 128) 3452 return false; 3453 3454 for (unsigned i = 0; i < NumElems/2; ++i) 3455 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3456 return false; 3457 3458 for (unsigned i = 0; i < NumElems/2; ++i) 3459 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3460 return false; 3461 3462 return true; 3463} 3464 3465/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3466/// specifies a shuffle of elements that is suitable for input to UNPCKL. 3467static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT, 3468 bool HasAVX2, bool V2IsSplat = false) { 3469 unsigned NumElts = VT.getVectorNumElements(); 3470 3471 assert((VT.is128BitVector() || VT.is256BitVector()) && 3472 "Unsupported vector type for unpckh"); 3473 3474 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3475 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3476 return false; 3477 3478 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3479 // independently on 128-bit lanes. 3480 unsigned NumLanes = VT.getSizeInBits()/128; 3481 unsigned NumLaneElts = NumElts/NumLanes; 3482 3483 for (unsigned l = 0; l != NumLanes; ++l) { 3484 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3485 i != (l+1)*NumLaneElts; 3486 i += 2, ++j) { 3487 int BitI = Mask[i]; 3488 int BitI1 = Mask[i+1]; 3489 if (!isUndefOrEqual(BitI, j)) 3490 return false; 3491 if (V2IsSplat) { 3492 if (!isUndefOrEqual(BitI1, NumElts)) 3493 return false; 3494 } else { 3495 if (!isUndefOrEqual(BitI1, j + NumElts)) 3496 return false; 3497 } 3498 } 3499 } 3500 3501 return true; 3502} 3503 3504bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3505 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat); 3506} 3507 3508/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3509/// specifies a shuffle of elements that is suitable for input to UNPCKH. 3510static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT, 3511 bool HasAVX2, bool V2IsSplat = false) { 3512 unsigned NumElts = VT.getVectorNumElements(); 3513 3514 assert((VT.is128BitVector() || VT.is256BitVector()) && 3515 "Unsupported vector type for unpckh"); 3516 3517 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3518 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3519 return false; 3520 3521 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3522 // independently on 128-bit lanes. 3523 unsigned NumLanes = VT.getSizeInBits()/128; 3524 unsigned NumLaneElts = NumElts/NumLanes; 3525 3526 for (unsigned l = 0; l != NumLanes; ++l) { 3527 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3528 i != (l+1)*NumLaneElts; i += 2, ++j) { 3529 int BitI = Mask[i]; 3530 int BitI1 = Mask[i+1]; 3531 if (!isUndefOrEqual(BitI, j)) 3532 return false; 3533 if (V2IsSplat) { 3534 if (isUndefOrEqual(BitI1, NumElts)) 3535 return false; 3536 } else { 3537 if (!isUndefOrEqual(BitI1, j+NumElts)) 3538 return false; 3539 } 3540 } 3541 } 3542 return true; 3543} 3544 3545bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) { 3546 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat); 3547} 3548 3549/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3550/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3551/// <0, 0, 1, 1> 3552static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, 3553 bool HasAVX2) { 3554 unsigned NumElts = VT.getVectorNumElements(); 3555 3556 assert((VT.is128BitVector() || VT.is256BitVector()) && 3557 "Unsupported vector type for unpckh"); 3558 3559 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3560 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3561 return false; 3562 3563 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3564 // FIXME: Need a better way to get rid of this, there's no latency difference 3565 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3566 // the former later. We should also remove the "_undef" special mask. 3567 if (NumElts == 4 && VT.getSizeInBits() == 256) 3568 return false; 3569 3570 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3571 // independently on 128-bit lanes. 3572 unsigned NumLanes = VT.getSizeInBits()/128; 3573 unsigned NumLaneElts = NumElts/NumLanes; 3574 3575 for (unsigned l = 0; l != NumLanes; ++l) { 3576 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts; 3577 i != (l+1)*NumLaneElts; 3578 i += 2, ++j) { 3579 int BitI = Mask[i]; 3580 int BitI1 = Mask[i+1]; 3581 3582 if (!isUndefOrEqual(BitI, j)) 3583 return false; 3584 if (!isUndefOrEqual(BitI1, j)) 3585 return false; 3586 } 3587 } 3588 3589 return true; 3590} 3591 3592bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3593 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2); 3594} 3595 3596/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3597/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3598/// <2, 2, 3, 3> 3599static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) { 3600 unsigned NumElts = VT.getVectorNumElements(); 3601 3602 assert((VT.is128BitVector() || VT.is256BitVector()) && 3603 "Unsupported vector type for unpckh"); 3604 3605 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 && 3606 (!HasAVX2 || (NumElts != 16 && NumElts != 32))) 3607 return false; 3608 3609 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3610 // independently on 128-bit lanes. 3611 unsigned NumLanes = VT.getSizeInBits()/128; 3612 unsigned NumLaneElts = NumElts/NumLanes; 3613 3614 for (unsigned l = 0; l != NumLanes; ++l) { 3615 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2; 3616 i != (l+1)*NumLaneElts; i += 2, ++j) { 3617 int BitI = Mask[i]; 3618 int BitI1 = Mask[i+1]; 3619 if (!isUndefOrEqual(BitI, j)) 3620 return false; 3621 if (!isUndefOrEqual(BitI1, j)) 3622 return false; 3623 } 3624 } 3625 return true; 3626} 3627 3628bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) { 3629 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2); 3630} 3631 3632/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3633/// specifies a shuffle of elements that is suitable for input to MOVSS, 3634/// MOVSD, and MOVD, i.e. setting the lowest element. 3635static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) { 3636 if (VT.getVectorElementType().getSizeInBits() < 32) 3637 return false; 3638 if (VT.getSizeInBits() == 256) 3639 return false; 3640 3641 unsigned NumElts = VT.getVectorNumElements(); 3642 3643 if (!isUndefOrEqual(Mask[0], NumElts)) 3644 return false; 3645 3646 for (unsigned i = 1; i != NumElts; ++i) 3647 if (!isUndefOrEqual(Mask[i], i)) 3648 return false; 3649 3650 return true; 3651} 3652 3653bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3654 return ::isMOVLMask(N->getMask(), N->getValueType(0)); 3655} 3656 3657/// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered 3658/// as permutations between 128-bit chunks or halves. As an example: this 3659/// shuffle bellow: 3660/// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3661/// The first half comes from the second half of V1 and the second half from the 3662/// the second half of V2. 3663static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3664 if (!HasAVX || VT.getSizeInBits() != 256) 3665 return false; 3666 3667 // The shuffle result is divided into half A and half B. In total the two 3668 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3669 // B must come from C, D, E or F. 3670 unsigned HalfSize = VT.getVectorNumElements()/2; 3671 bool MatchA = false, MatchB = false; 3672 3673 // Check if A comes from one of C, D, E, F. 3674 for (unsigned Half = 0; Half != 4; ++Half) { 3675 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3676 MatchA = true; 3677 break; 3678 } 3679 } 3680 3681 // Check if B comes from one of C, D, E, F. 3682 for (unsigned Half = 0; Half != 4; ++Half) { 3683 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3684 MatchB = true; 3685 break; 3686 } 3687 } 3688 3689 return MatchA && MatchB; 3690} 3691 3692/// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle 3693/// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions. 3694static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) { 3695 EVT VT = SVOp->getValueType(0); 3696 3697 unsigned HalfSize = VT.getVectorNumElements()/2; 3698 3699 unsigned FstHalf = 0, SndHalf = 0; 3700 for (unsigned i = 0; i < HalfSize; ++i) { 3701 if (SVOp->getMaskElt(i) > 0) { 3702 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3703 break; 3704 } 3705 } 3706 for (unsigned i = HalfSize; i < HalfSize*2; ++i) { 3707 if (SVOp->getMaskElt(i) > 0) { 3708 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3709 break; 3710 } 3711 } 3712 3713 return (FstHalf | (SndHalf << 4)); 3714} 3715 3716/// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand 3717/// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3718/// Note that VPERMIL mask matching is different depending whether theunderlying 3719/// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3720/// to the same elements of the low, but to the higher half of the source. 3721/// In VPERMILPD the two lanes could be shuffled independently of each other 3722/// with the same restriction that lanes can't be crossed. 3723static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3724 if (!HasAVX) 3725 return false; 3726 3727 unsigned NumElts = VT.getVectorNumElements(); 3728 // Only match 256-bit with 32/64-bit types 3729 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8)) 3730 return false; 3731 3732 unsigned NumLanes = VT.getSizeInBits()/128; 3733 unsigned LaneSize = NumElts/NumLanes; 3734 for (unsigned l = 0; l != NumElts; l += LaneSize) { 3735 for (unsigned i = 0; i != LaneSize; ++i) { 3736 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize)) 3737 return false; 3738 if (NumElts != 8 || l == 0) 3739 continue; 3740 // VPERMILPS handling 3741 if (Mask[i] < 0) 3742 continue; 3743 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l)) 3744 return false; 3745 } 3746 } 3747 3748 return true; 3749} 3750 3751/// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle 3752/// the specified VECTOR_MASK mask with VPERMILPS/D* instructions. 3753static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) { 3754 EVT VT = SVOp->getValueType(0); 3755 3756 unsigned NumElts = VT.getVectorNumElements(); 3757 unsigned NumLanes = VT.getSizeInBits()/128; 3758 unsigned LaneSize = NumElts/NumLanes; 3759 3760 // Although the mask is equal for both lanes do it twice to get the cases 3761 // where a mask will match because the same mask element is undef on the 3762 // first half but valid on the second. This would get pathological cases 3763 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3764 unsigned Shift = (LaneSize == 4) ? 2 : 1; 3765 unsigned Mask = 0; 3766 for (unsigned i = 0; i != NumElts; ++i) { 3767 int MaskElt = SVOp->getMaskElt(i); 3768 if (MaskElt < 0) 3769 continue; 3770 MaskElt %= LaneSize; 3771 unsigned Shamt = i; 3772 // VPERMILPSY, the mask of the first half must be equal to the second one 3773 if (NumElts == 8) Shamt %= LaneSize; 3774 Mask |= MaskElt << (Shamt*Shift); 3775 } 3776 3777 return Mask; 3778} 3779 3780/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3781/// of what x86 movss want. X86 movs requires the lowest element to be lowest 3782/// element of vector 2 and the other elements to come from vector 1 in order. 3783static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT, 3784 bool V2IsSplat = false, bool V2IsUndef = false) { 3785 unsigned NumOps = VT.getVectorNumElements(); 3786 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3787 return false; 3788 3789 if (!isUndefOrEqual(Mask[0], 0)) 3790 return false; 3791 3792 for (unsigned i = 1; i != NumOps; ++i) 3793 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3794 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3795 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3796 return false; 3797 3798 return true; 3799} 3800 3801static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3802 bool V2IsUndef = false) { 3803 return isCommutedMOVLMask(N->getMask(), N->getValueType(0), 3804 V2IsSplat, V2IsUndef); 3805} 3806 3807/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3808/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3809/// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3810bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3811 const X86Subtarget *Subtarget) { 3812 if (!Subtarget->hasSSE3()) 3813 return false; 3814 3815 // The second vector must be undef 3816 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3817 return false; 3818 3819 EVT VT = N->getValueType(0); 3820 unsigned NumElems = VT.getVectorNumElements(); 3821 3822 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3823 (VT.getSizeInBits() == 256 && NumElems != 8)) 3824 return false; 3825 3826 // "i+1" is the value the indexed mask element must have 3827 for (unsigned i = 0; i < NumElems; i += 2) 3828 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3829 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3830 return false; 3831 3832 return true; 3833} 3834 3835/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3836/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3837/// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3838bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3839 const X86Subtarget *Subtarget) { 3840 if (!Subtarget->hasSSE3()) 3841 return false; 3842 3843 // The second vector must be undef 3844 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3845 return false; 3846 3847 EVT VT = N->getValueType(0); 3848 unsigned NumElems = VT.getVectorNumElements(); 3849 3850 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3851 (VT.getSizeInBits() == 256 && NumElems != 8)) 3852 return false; 3853 3854 // "i" is the value the indexed mask element must have 3855 for (unsigned i = 0; i != NumElems; i += 2) 3856 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3857 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3858 return false; 3859 3860 return true; 3861} 3862 3863/// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3864/// specifies a shuffle of elements that is suitable for input to 256-bit 3865/// version of MOVDDUP. 3866static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) { 3867 unsigned NumElts = VT.getVectorNumElements(); 3868 3869 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4) 3870 return false; 3871 3872 for (unsigned i = 0; i != NumElts/2; ++i) 3873 if (!isUndefOrEqual(Mask[i], 0)) 3874 return false; 3875 for (unsigned i = NumElts/2; i != NumElts; ++i) 3876 if (!isUndefOrEqual(Mask[i], NumElts/2)) 3877 return false; 3878 return true; 3879} 3880 3881/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3882/// specifies a shuffle of elements that is suitable for input to 128-bit 3883/// version of MOVDDUP. 3884bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3885 EVT VT = N->getValueType(0); 3886 3887 if (VT.getSizeInBits() != 128) 3888 return false; 3889 3890 unsigned e = VT.getVectorNumElements() / 2; 3891 for (unsigned i = 0; i != e; ++i) 3892 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3893 return false; 3894 for (unsigned i = 0; i != e; ++i) 3895 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3896 return false; 3897 return true; 3898} 3899 3900/// isVEXTRACTF128Index - Return true if the specified 3901/// EXTRACT_SUBVECTOR operand specifies a vector extract that is 3902/// suitable for input to VEXTRACTF128. 3903bool X86::isVEXTRACTF128Index(SDNode *N) { 3904 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 3905 return false; 3906 3907 // The index should be aligned on a 128-bit boundary. 3908 uint64_t Index = 3909 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 3910 3911 unsigned VL = N->getValueType(0).getVectorNumElements(); 3912 unsigned VBits = N->getValueType(0).getSizeInBits(); 3913 unsigned ElSize = VBits / VL; 3914 bool Result = (Index * ElSize) % 128 == 0; 3915 3916 return Result; 3917} 3918 3919/// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 3920/// operand specifies a subvector insert that is suitable for input to 3921/// VINSERTF128. 3922bool X86::isVINSERTF128Index(SDNode *N) { 3923 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 3924 return false; 3925 3926 // The index should be aligned on a 128-bit boundary. 3927 uint64_t Index = 3928 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 3929 3930 unsigned VL = N->getValueType(0).getVectorNumElements(); 3931 unsigned VBits = N->getValueType(0).getSizeInBits(); 3932 unsigned ElSize = VBits / VL; 3933 bool Result = (Index * ElSize) % 128 == 0; 3934 3935 return Result; 3936} 3937 3938/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3939/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3940/// Handles 128-bit and 256-bit. 3941unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) { 3942 EVT VT = N->getValueType(0); 3943 3944 assert((VT.is128BitVector() || VT.is256BitVector()) && 3945 "Unsupported vector type for PSHUF/SHUFP"); 3946 3947 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate 3948 // independently on 128-bit lanes. 3949 unsigned NumElts = VT.getVectorNumElements(); 3950 unsigned NumLanes = VT.getSizeInBits()/128; 3951 unsigned NumLaneElts = NumElts/NumLanes; 3952 3953 assert((NumLaneElts == 2 || NumLaneElts == 4) && 3954 "Only supports 2 or 4 elements per lane"); 3955 3956 unsigned Shift = (NumLaneElts == 4) ? 1 : 0; 3957 unsigned Mask = 0; 3958 for (unsigned i = 0; i != NumElts; ++i) { 3959 int Elt = N->getMaskElt(i); 3960 if (Elt < 0) continue; 3961 Elt %= NumLaneElts; 3962 unsigned ShAmt = i << Shift; 3963 if (ShAmt >= 8) ShAmt -= 8; 3964 Mask |= Elt << ShAmt; 3965 } 3966 3967 return Mask; 3968} 3969 3970/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3971/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3972unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3974 unsigned Mask = 0; 3975 // 8 nodes, but we only care about the last 4. 3976 for (unsigned i = 7; i >= 4; --i) { 3977 int Val = SVOp->getMaskElt(i); 3978 if (Val >= 0) 3979 Mask |= (Val - 4); 3980 if (i != 4) 3981 Mask <<= 2; 3982 } 3983 return Mask; 3984} 3985 3986/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3987/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3988unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3990 unsigned Mask = 0; 3991 // 8 nodes, but we only care about the first 4. 3992 for (int i = 3; i >= 0; --i) { 3993 int Val = SVOp->getMaskElt(i); 3994 if (Val >= 0) 3995 Mask |= Val; 3996 if (i != 0) 3997 Mask <<= 2; 3998 } 3999 return Mask; 4000} 4001 4002/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4003/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4004static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) { 4005 EVT VT = SVOp->getValueType(0); 4006 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3; 4007 4008 unsigned NumElts = VT.getVectorNumElements(); 4009 unsigned NumLanes = VT.getSizeInBits()/128; 4010 unsigned NumLaneElts = NumElts/NumLanes; 4011 4012 int Val = 0; 4013 unsigned i; 4014 for (i = 0; i != NumElts; ++i) { 4015 Val = SVOp->getMaskElt(i); 4016 if (Val >= 0) 4017 break; 4018 } 4019 if (Val >= (int)NumElts) 4020 Val -= NumElts - NumLaneElts; 4021 4022 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4023 return (Val - i) * EltSize; 4024} 4025 4026/// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4027/// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4028/// instructions. 4029unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4030 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4031 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4032 4033 uint64_t Index = 4034 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4035 4036 EVT VecVT = N->getOperand(0).getValueType(); 4037 EVT ElVT = VecVT.getVectorElementType(); 4038 4039 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4040 return Index / NumElemsPerChunk; 4041} 4042 4043/// getInsertVINSERTF128Immediate - Return the appropriate immediate 4044/// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4045/// instructions. 4046unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4047 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4048 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4049 4050 uint64_t Index = 4051 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4052 4053 EVT VecVT = N->getValueType(0); 4054 EVT ElVT = VecVT.getVectorElementType(); 4055 4056 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4057 return Index / NumElemsPerChunk; 4058} 4059 4060/// isZeroNode - Returns true if Elt is a constant zero or a floating point 4061/// constant +0.0. 4062bool X86::isZeroNode(SDValue Elt) { 4063 return ((isa<ConstantSDNode>(Elt) && 4064 cast<ConstantSDNode>(Elt)->isNullValue()) || 4065 (isa<ConstantFPSDNode>(Elt) && 4066 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4067} 4068 4069/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4070/// their permute mask. 4071static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4072 SelectionDAG &DAG) { 4073 EVT VT = SVOp->getValueType(0); 4074 unsigned NumElems = VT.getVectorNumElements(); 4075 SmallVector<int, 8> MaskVec; 4076 4077 for (unsigned i = 0; i != NumElems; ++i) { 4078 int idx = SVOp->getMaskElt(i); 4079 if (idx < 0) 4080 MaskVec.push_back(idx); 4081 else if (idx < (int)NumElems) 4082 MaskVec.push_back(idx + NumElems); 4083 else 4084 MaskVec.push_back(idx - NumElems); 4085 } 4086 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4087 SVOp->getOperand(0), &MaskVec[0]); 4088} 4089 4090/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4091/// match movhlps. The lower half elements should come from upper half of 4092/// V1 (and in order), and the upper half elements should come from the upper 4093/// half of V2 (and in order). 4094static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4095 EVT VT = Op->getValueType(0); 4096 if (VT.getSizeInBits() != 128) 4097 return false; 4098 if (VT.getVectorNumElements() != 4) 4099 return false; 4100 for (unsigned i = 0, e = 2; i != e; ++i) 4101 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4102 return false; 4103 for (unsigned i = 2; i != 4; ++i) 4104 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4105 return false; 4106 return true; 4107} 4108 4109/// isScalarLoadToVector - Returns true if the node is a scalar load that 4110/// is promoted to a vector. It also returns the LoadSDNode by reference if 4111/// required. 4112static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4113 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4114 return false; 4115 N = N->getOperand(0).getNode(); 4116 if (!ISD::isNON_EXTLoad(N)) 4117 return false; 4118 if (LD) 4119 *LD = cast<LoadSDNode>(N); 4120 return true; 4121} 4122 4123// Test whether the given value is a vector value which will be legalized 4124// into a load. 4125static bool WillBeConstantPoolLoad(SDNode *N) { 4126 if (N->getOpcode() != ISD::BUILD_VECTOR) 4127 return false; 4128 4129 // Check for any non-constant elements. 4130 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 4131 switch (N->getOperand(i).getNode()->getOpcode()) { 4132 case ISD::UNDEF: 4133 case ISD::ConstantFP: 4134 case ISD::Constant: 4135 break; 4136 default: 4137 return false; 4138 } 4139 4140 // Vectors of all-zeros and all-ones are materialized with special 4141 // instructions rather than being loaded. 4142 return !ISD::isBuildVectorAllZeros(N) && 4143 !ISD::isBuildVectorAllOnes(N); 4144} 4145 4146/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4147/// match movlp{s|d}. The lower half elements should come from lower half of 4148/// V1 (and in order), and the upper half elements should come from the upper 4149/// half of V2 (and in order). And since V1 will become the source of the 4150/// MOVLP, it must be either a vector load or a scalar load to vector. 4151static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4152 ShuffleVectorSDNode *Op) { 4153 EVT VT = Op->getValueType(0); 4154 if (VT.getSizeInBits() != 128) 4155 return false; 4156 4157 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4158 return false; 4159 // Is V2 is a vector load, don't do this transformation. We will try to use 4160 // load folding shufps op. 4161 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2)) 4162 return false; 4163 4164 unsigned NumElems = VT.getVectorNumElements(); 4165 4166 if (NumElems != 2 && NumElems != 4) 4167 return false; 4168 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4169 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4170 return false; 4171 for (unsigned i = NumElems/2; i != NumElems; ++i) 4172 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4173 return false; 4174 return true; 4175} 4176 4177/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4178/// all the same. 4179static bool isSplatVector(SDNode *N) { 4180 if (N->getOpcode() != ISD::BUILD_VECTOR) 4181 return false; 4182 4183 SDValue SplatValue = N->getOperand(0); 4184 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4185 if (N->getOperand(i) != SplatValue) 4186 return false; 4187 return true; 4188} 4189 4190/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4191/// to an zero vector. 4192/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4193static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4194 SDValue V1 = N->getOperand(0); 4195 SDValue V2 = N->getOperand(1); 4196 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4197 for (unsigned i = 0; i != NumElems; ++i) { 4198 int Idx = N->getMaskElt(i); 4199 if (Idx >= (int)NumElems) { 4200 unsigned Opc = V2.getOpcode(); 4201 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4202 continue; 4203 if (Opc != ISD::BUILD_VECTOR || 4204 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4205 return false; 4206 } else if (Idx >= 0) { 4207 unsigned Opc = V1.getOpcode(); 4208 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4209 continue; 4210 if (Opc != ISD::BUILD_VECTOR || 4211 !X86::isZeroNode(V1.getOperand(Idx))) 4212 return false; 4213 } 4214 } 4215 return true; 4216} 4217 4218/// getZeroVector - Returns a vector of specified type with all zero elements. 4219/// 4220static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2, 4221 SelectionDAG &DAG, DebugLoc dl) { 4222 assert(VT.isVector() && "Expected a vector type"); 4223 4224 // Always build SSE zero vectors as <4 x i32> bitcasted 4225 // to their dest type. This ensures they get CSE'd. 4226 SDValue Vec; 4227 if (VT.getSizeInBits() == 128) { // SSE 4228 if (HasSSE2) { // SSE2 4229 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4231 } else { // SSE1 4232 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4233 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4234 } 4235 } else if (VT.getSizeInBits() == 256) { // AVX 4236 if (HasAVX2) { // AVX2 4237 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4238 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4239 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4240 } else { 4241 // 256-bit logic and arithmetic instructions in AVX are all 4242 // floating-point, no support for integer ops. Emit fp zeroed vectors. 4243 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4244 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4245 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4246 } 4247 } 4248 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4249} 4250 4251/// getOnesVector - Returns a vector of specified type with all bits set. 4252/// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with 4253/// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. 4254/// Then bitcast to their original type, ensuring they get CSE'd. 4255static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, 4256 DebugLoc dl) { 4257 assert(VT.isVector() && "Expected a vector type"); 4258 assert((VT.is128BitVector() || VT.is256BitVector()) 4259 && "Expected a 128-bit or 256-bit vector type"); 4260 4261 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4262 SDValue Vec; 4263 if (VT.getSizeInBits() == 256) { 4264 if (HasAVX2) { // AVX2 4265 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4266 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8); 4267 } else { // AVX 4268 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4269 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4270 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4271 Vec = Insert128BitVector(InsV, Vec, 4272 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4273 } 4274 } else { 4275 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4276 } 4277 4278 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4279} 4280 4281/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4282/// that point to V2 points to its first element. 4283static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4284 EVT VT = SVOp->getValueType(0); 4285 unsigned NumElems = VT.getVectorNumElements(); 4286 4287 bool Changed = false; 4288 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end()); 4289 4290 for (unsigned i = 0; i != NumElems; ++i) { 4291 if (MaskVec[i] > (int)NumElems) { 4292 MaskVec[i] = NumElems; 4293 Changed = true; 4294 } 4295 } 4296 if (Changed) 4297 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4298 SVOp->getOperand(1), &MaskVec[0]); 4299 return SDValue(SVOp, 0); 4300} 4301 4302/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4303/// operation of specified width. 4304static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4305 SDValue V2) { 4306 unsigned NumElems = VT.getVectorNumElements(); 4307 SmallVector<int, 8> Mask; 4308 Mask.push_back(NumElems); 4309 for (unsigned i = 1; i != NumElems; ++i) 4310 Mask.push_back(i); 4311 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4312} 4313 4314/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4315static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4316 SDValue V2) { 4317 unsigned NumElems = VT.getVectorNumElements(); 4318 SmallVector<int, 8> Mask; 4319 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4320 Mask.push_back(i); 4321 Mask.push_back(i + NumElems); 4322 } 4323 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4324} 4325 4326/// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4327static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4328 SDValue V2) { 4329 unsigned NumElems = VT.getVectorNumElements(); 4330 unsigned Half = NumElems/2; 4331 SmallVector<int, 8> Mask; 4332 for (unsigned i = 0; i != Half; ++i) { 4333 Mask.push_back(i + Half); 4334 Mask.push_back(i + NumElems + Half); 4335 } 4336 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4337} 4338 4339// PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4340// a generic shuffle instruction because the target has no such instructions. 4341// Generate shuffles which repeat i16 and i8 several times until they can be 4342// represented by v4f32 and then be manipulated by target suported shuffles. 4343static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4344 EVT VT = V.getValueType(); 4345 int NumElems = VT.getVectorNumElements(); 4346 DebugLoc dl = V.getDebugLoc(); 4347 4348 while (NumElems > 4) { 4349 if (EltNo < NumElems/2) { 4350 V = getUnpackl(DAG, dl, VT, V, V); 4351 } else { 4352 V = getUnpackh(DAG, dl, VT, V, V); 4353 EltNo -= NumElems/2; 4354 } 4355 NumElems >>= 1; 4356 } 4357 return V; 4358} 4359 4360/// getLegalSplat - Generate a legal splat with supported x86 shuffles 4361static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4362 EVT VT = V.getValueType(); 4363 DebugLoc dl = V.getDebugLoc(); 4364 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4365 && "Vector size not supported"); 4366 4367 if (VT.getSizeInBits() == 128) { 4368 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4369 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4370 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4371 &SplatMask[0]); 4372 } else { 4373 // To use VPERMILPS to splat scalars, the second half of indicies must 4374 // refer to the higher part, which is a duplication of the lower one, 4375 // because VPERMILPS can only handle in-lane permutations. 4376 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4377 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4378 4379 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4380 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4381 &SplatMask[0]); 4382 } 4383 4384 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4385} 4386 4387/// PromoteSplat - Splat is promoted to target supported vector shuffles. 4388static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4389 EVT SrcVT = SV->getValueType(0); 4390 SDValue V1 = SV->getOperand(0); 4391 DebugLoc dl = SV->getDebugLoc(); 4392 4393 int EltNo = SV->getSplatIndex(); 4394 int NumElems = SrcVT.getVectorNumElements(); 4395 unsigned Size = SrcVT.getSizeInBits(); 4396 4397 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4398 "Unknown how to promote splat for type"); 4399 4400 // Extract the 128-bit part containing the splat element and update 4401 // the splat element index when it refers to the higher register. 4402 if (Size == 256) { 4403 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0; 4404 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4405 if (Idx > 0) 4406 EltNo -= NumElems/2; 4407 } 4408 4409 // All i16 and i8 vector types can't be used directly by a generic shuffle 4410 // instruction because the target has no such instruction. Generate shuffles 4411 // which repeat i16 and i8 several times until they fit in i32, and then can 4412 // be manipulated by target suported shuffles. 4413 EVT EltVT = SrcVT.getVectorElementType(); 4414 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4415 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4416 4417 // Recreate the 256-bit vector and place the same 128-bit vector 4418 // into the low and high part. This is necessary because we want 4419 // to use VPERM* to shuffle the vectors 4420 if (Size == 256) { 4421 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4422 DAG.getConstant(0, MVT::i32), DAG, dl); 4423 V1 = Insert128BitVector(InsV, V1, 4424 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4425 } 4426 4427 return getLegalSplat(DAG, V1, EltNo); 4428} 4429 4430/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4431/// vector of zero or undef vector. This produces a shuffle where the low 4432/// element of V2 is swizzled into the zero/undef vector, landing at element 4433/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4434static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4435 bool IsZero, 4436 const X86Subtarget *Subtarget, 4437 SelectionDAG &DAG) { 4438 EVT VT = V2.getValueType(); 4439 SDValue V1 = IsZero 4440 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG, 4441 V2.getDebugLoc()) : DAG.getUNDEF(VT); 4442 unsigned NumElems = VT.getVectorNumElements(); 4443 SmallVector<int, 16> MaskVec; 4444 for (unsigned i = 0; i != NumElems; ++i) 4445 // If this is the insertion idx, put the low elt of V2 here. 4446 MaskVec.push_back(i == Idx ? NumElems : i); 4447 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4448} 4449 4450/// getShuffleScalarElt - Returns the scalar element that will make up the ith 4451/// element of the result of the vector shuffle. 4452static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4453 unsigned Depth) { 4454 if (Depth == 6) 4455 return SDValue(); // Limit search depth. 4456 4457 SDValue V = SDValue(N, 0); 4458 EVT VT = V.getValueType(); 4459 unsigned Opcode = V.getOpcode(); 4460 4461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4463 Index = SV->getMaskElt(Index); 4464 4465 if (Index < 0) 4466 return DAG.getUNDEF(VT.getVectorElementType()); 4467 4468 int NumElems = VT.getVectorNumElements(); 4469 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4470 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4471 } 4472 4473 // Recurse into target specific vector shuffles to find scalars. 4474 if (isTargetShuffle(Opcode)) { 4475 int NumElems = VT.getVectorNumElements(); 4476 SmallVector<unsigned, 16> ShuffleMask; 4477 SDValue ImmN; 4478 4479 switch(Opcode) { 4480 case X86ISD::SHUFP: 4481 ImmN = N->getOperand(N->getNumOperands()-1); 4482 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4483 ShuffleMask); 4484 break; 4485 case X86ISD::UNPCKH: 4486 DecodeUNPCKHMask(VT, ShuffleMask); 4487 break; 4488 case X86ISD::UNPCKL: 4489 DecodeUNPCKLMask(VT, ShuffleMask); 4490 break; 4491 case X86ISD::MOVHLPS: 4492 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4493 break; 4494 case X86ISD::MOVLHPS: 4495 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4496 break; 4497 case X86ISD::PSHUFD: 4498 ImmN = N->getOperand(N->getNumOperands()-1); 4499 DecodePSHUFMask(NumElems, 4500 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4501 ShuffleMask); 4502 break; 4503 case X86ISD::PSHUFHW: 4504 ImmN = N->getOperand(N->getNumOperands()-1); 4505 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4506 ShuffleMask); 4507 break; 4508 case X86ISD::PSHUFLW: 4509 ImmN = N->getOperand(N->getNumOperands()-1); 4510 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4511 ShuffleMask); 4512 break; 4513 case X86ISD::MOVSS: 4514 case X86ISD::MOVSD: { 4515 // The index 0 always comes from the first element of the second source, 4516 // this is why MOVSS and MOVSD are used in the first place. The other 4517 // elements come from the other positions of the first source vector. 4518 unsigned OpNum = (Index == 0) ? 1 : 0; 4519 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4520 Depth+1); 4521 } 4522 case X86ISD::VPERMILP: 4523 ImmN = N->getOperand(N->getNumOperands()-1); 4524 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4525 ShuffleMask); 4526 break; 4527 case X86ISD::VPERM2X128: 4528 ImmN = N->getOperand(N->getNumOperands()-1); 4529 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4530 ShuffleMask); 4531 break; 4532 case X86ISD::MOVDDUP: 4533 case X86ISD::MOVLHPD: 4534 case X86ISD::MOVLPD: 4535 case X86ISD::MOVLPS: 4536 case X86ISD::MOVSHDUP: 4537 case X86ISD::MOVSLDUP: 4538 case X86ISD::PALIGN: 4539 return SDValue(); // Not yet implemented. 4540 default: 4541 assert(0 && "unknown target shuffle node"); 4542 return SDValue(); 4543 } 4544 4545 Index = ShuffleMask[Index]; 4546 if (Index < 0) 4547 return DAG.getUNDEF(VT.getVectorElementType()); 4548 4549 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4550 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4551 Depth+1); 4552 } 4553 4554 // Actual nodes that may contain scalar elements 4555 if (Opcode == ISD::BITCAST) { 4556 V = V.getOperand(0); 4557 EVT SrcVT = V.getValueType(); 4558 unsigned NumElems = VT.getVectorNumElements(); 4559 4560 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4561 return SDValue(); 4562 } 4563 4564 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4565 return (Index == 0) ? V.getOperand(0) 4566 : DAG.getUNDEF(VT.getVectorElementType()); 4567 4568 if (V.getOpcode() == ISD::BUILD_VECTOR) 4569 return V.getOperand(Index); 4570 4571 return SDValue(); 4572} 4573 4574/// getNumOfConsecutiveZeros - Return the number of elements of a vector 4575/// shuffle operation which come from a consecutively from a zero. The 4576/// search can start in two different directions, from left or right. 4577static 4578unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4579 bool ZerosFromLeft, SelectionDAG &DAG) { 4580 int i = 0; 4581 4582 while (i < NumElems) { 4583 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4584 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4585 if (!(Elt.getNode() && 4586 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4587 break; 4588 ++i; 4589 } 4590 4591 return i; 4592} 4593 4594/// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4595/// MaskE correspond consecutively to elements from one of the vector operands, 4596/// starting from its index OpIdx. Also tell OpNum which source vector operand. 4597static 4598bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4599 int OpIdx, int NumElems, unsigned &OpNum) { 4600 bool SeenV1 = false; 4601 bool SeenV2 = false; 4602 4603 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4604 int Idx = SVOp->getMaskElt(i); 4605 // Ignore undef indicies 4606 if (Idx < 0) 4607 continue; 4608 4609 if (Idx < NumElems) 4610 SeenV1 = true; 4611 else 4612 SeenV2 = true; 4613 4614 // Only accept consecutive elements from the same vector 4615 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4616 return false; 4617 } 4618 4619 OpNum = SeenV1 ? 0 : 1; 4620 return true; 4621} 4622 4623/// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4624/// logical left shift of a vector. 4625static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4626 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4627 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4628 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4629 false /* check zeros from right */, DAG); 4630 unsigned OpSrc; 4631 4632 if (!NumZeros) 4633 return false; 4634 4635 // Considering the elements in the mask that are not consecutive zeros, 4636 // check if they consecutively come from only one of the source vectors. 4637 // 4638 // V1 = {X, A, B, C} 0 4639 // \ \ \ / 4640 // vector_shuffle V1, V2 <1, 2, 3, X> 4641 // 4642 if (!isShuffleMaskConsecutive(SVOp, 4643 0, // Mask Start Index 4644 NumElems-NumZeros-1, // Mask End Index 4645 NumZeros, // Where to start looking in the src vector 4646 NumElems, // Number of elements in vector 4647 OpSrc)) // Which source operand ? 4648 return false; 4649 4650 isLeft = false; 4651 ShAmt = NumZeros; 4652 ShVal = SVOp->getOperand(OpSrc); 4653 return true; 4654} 4655 4656/// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4657/// logical left shift of a vector. 4658static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4659 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4660 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4661 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4662 true /* check zeros from left */, DAG); 4663 unsigned OpSrc; 4664 4665 if (!NumZeros) 4666 return false; 4667 4668 // Considering the elements in the mask that are not consecutive zeros, 4669 // check if they consecutively come from only one of the source vectors. 4670 // 4671 // 0 { A, B, X, X } = V2 4672 // / \ / / 4673 // vector_shuffle V1, V2 <X, X, 4, 5> 4674 // 4675 if (!isShuffleMaskConsecutive(SVOp, 4676 NumZeros, // Mask Start Index 4677 NumElems-1, // Mask End Index 4678 0, // Where to start looking in the src vector 4679 NumElems, // Number of elements in vector 4680 OpSrc)) // Which source operand ? 4681 return false; 4682 4683 isLeft = true; 4684 ShAmt = NumZeros; 4685 ShVal = SVOp->getOperand(OpSrc); 4686 return true; 4687} 4688 4689/// isVectorShift - Returns true if the shuffle can be implemented as a 4690/// logical left or right shift of a vector. 4691static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4692 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4693 // Although the logic below support any bitwidth size, there are no 4694 // shift instructions which handle more than 128-bit vectors. 4695 if (SVOp->getValueType(0).getSizeInBits() > 128) 4696 return false; 4697 4698 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4699 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4700 return true; 4701 4702 return false; 4703} 4704 4705/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4706/// 4707static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4708 unsigned NumNonZero, unsigned NumZero, 4709 SelectionDAG &DAG, 4710 const TargetLowering &TLI) { 4711 if (NumNonZero > 8) 4712 return SDValue(); 4713 4714 DebugLoc dl = Op.getDebugLoc(); 4715 SDValue V(0, 0); 4716 bool First = true; 4717 for (unsigned i = 0; i < 16; ++i) { 4718 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4719 if (ThisIsNonZero && First) { 4720 if (NumZero) 4721 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false, 4722 DAG, dl); 4723 else 4724 V = DAG.getUNDEF(MVT::v8i16); 4725 First = false; 4726 } 4727 4728 if ((i & 1) != 0) { 4729 SDValue ThisElt(0, 0), LastElt(0, 0); 4730 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4731 if (LastIsNonZero) { 4732 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4733 MVT::i16, Op.getOperand(i-1)); 4734 } 4735 if (ThisIsNonZero) { 4736 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4737 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4738 ThisElt, DAG.getConstant(8, MVT::i8)); 4739 if (LastIsNonZero) 4740 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4741 } else 4742 ThisElt = LastElt; 4743 4744 if (ThisElt.getNode()) 4745 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4746 DAG.getIntPtrConstant(i/2)); 4747 } 4748 } 4749 4750 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4751} 4752 4753/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4754/// 4755static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4756 unsigned NumNonZero, unsigned NumZero, 4757 SelectionDAG &DAG, 4758 const TargetLowering &TLI) { 4759 if (NumNonZero > 4) 4760 return SDValue(); 4761 4762 DebugLoc dl = Op.getDebugLoc(); 4763 SDValue V(0, 0); 4764 bool First = true; 4765 for (unsigned i = 0; i < 8; ++i) { 4766 bool isNonZero = (NonZeros & (1 << i)) != 0; 4767 if (isNonZero) { 4768 if (First) { 4769 if (NumZero) 4770 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false, 4771 DAG, dl); 4772 else 4773 V = DAG.getUNDEF(MVT::v8i16); 4774 First = false; 4775 } 4776 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4777 MVT::v8i16, V, Op.getOperand(i), 4778 DAG.getIntPtrConstant(i)); 4779 } 4780 } 4781 4782 return V; 4783} 4784 4785/// getVShift - Return a vector logical shift node. 4786/// 4787static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4788 unsigned NumBits, SelectionDAG &DAG, 4789 const TargetLowering &TLI, DebugLoc dl) { 4790 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4791 EVT ShVT = MVT::v2i64; 4792 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ; 4793 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4794 return DAG.getNode(ISD::BITCAST, dl, VT, 4795 DAG.getNode(Opc, dl, ShVT, SrcOp, 4796 DAG.getConstant(NumBits, 4797 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4798} 4799 4800SDValue 4801X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4802 SelectionDAG &DAG) const { 4803 4804 // Check if the scalar load can be widened into a vector load. And if 4805 // the address is "base + cst" see if the cst can be "absorbed" into 4806 // the shuffle mask. 4807 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4808 SDValue Ptr = LD->getBasePtr(); 4809 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4810 return SDValue(); 4811 EVT PVT = LD->getValueType(0); 4812 if (PVT != MVT::i32 && PVT != MVT::f32) 4813 return SDValue(); 4814 4815 int FI = -1; 4816 int64_t Offset = 0; 4817 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4818 FI = FINode->getIndex(); 4819 Offset = 0; 4820 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4821 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4822 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4823 Offset = Ptr.getConstantOperandVal(1); 4824 Ptr = Ptr.getOperand(0); 4825 } else { 4826 return SDValue(); 4827 } 4828 4829 // FIXME: 256-bit vector instructions don't require a strict alignment, 4830 // improve this code to support it better. 4831 unsigned RequiredAlign = VT.getSizeInBits()/8; 4832 SDValue Chain = LD->getChain(); 4833 // Make sure the stack object alignment is at least 16 or 32. 4834 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4835 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4836 if (MFI->isFixedObjectIndex(FI)) { 4837 // Can't change the alignment. FIXME: It's possible to compute 4838 // the exact stack offset and reference FI + adjust offset instead. 4839 // If someone *really* cares about this. That's the way to implement it. 4840 return SDValue(); 4841 } else { 4842 MFI->setObjectAlignment(FI, RequiredAlign); 4843 } 4844 } 4845 4846 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4847 // Ptr + (Offset & ~15). 4848 if (Offset < 0) 4849 return SDValue(); 4850 if ((Offset % RequiredAlign) & 3) 4851 return SDValue(); 4852 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4853 if (StartOffset) 4854 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4855 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4856 4857 int EltNo = (Offset - StartOffset) >> 2; 4858 int NumElems = VT.getVectorNumElements(); 4859 4860 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4861 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4862 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4863 LD->getPointerInfo().getWithOffset(StartOffset), 4864 false, false, false, 0); 4865 4866 // Canonicalize it to a v4i32 or v8i32 shuffle. 4867 SmallVector<int, 8> Mask; 4868 for (int i = 0; i < NumElems; ++i) 4869 Mask.push_back(EltNo); 4870 4871 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4872 return DAG.getNode(ISD::BITCAST, dl, NVT, 4873 DAG.getVectorShuffle(CanonVT, dl, V1, 4874 DAG.getUNDEF(CanonVT),&Mask[0])); 4875 } 4876 4877 return SDValue(); 4878} 4879 4880/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4881/// vector of type 'VT', see if the elements can be replaced by a single large 4882/// load which has the same value as a build_vector whose operands are 'elts'. 4883/// 4884/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4885/// 4886/// FIXME: we'd also like to handle the case where the last elements are zero 4887/// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4888/// There's even a handy isZeroNode for that purpose. 4889static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4890 DebugLoc &DL, SelectionDAG &DAG) { 4891 EVT EltVT = VT.getVectorElementType(); 4892 unsigned NumElems = Elts.size(); 4893 4894 LoadSDNode *LDBase = NULL; 4895 unsigned LastLoadedElt = -1U; 4896 4897 // For each element in the initializer, see if we've found a load or an undef. 4898 // If we don't find an initial load element, or later load elements are 4899 // non-consecutive, bail out. 4900 for (unsigned i = 0; i < NumElems; ++i) { 4901 SDValue Elt = Elts[i]; 4902 4903 if (!Elt.getNode() || 4904 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 4905 return SDValue(); 4906 if (!LDBase) { 4907 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 4908 return SDValue(); 4909 LDBase = cast<LoadSDNode>(Elt.getNode()); 4910 LastLoadedElt = i; 4911 continue; 4912 } 4913 if (Elt.getOpcode() == ISD::UNDEF) 4914 continue; 4915 4916 LoadSDNode *LD = cast<LoadSDNode>(Elt); 4917 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 4918 return SDValue(); 4919 LastLoadedElt = i; 4920 } 4921 4922 // If we have found an entire vector of loads and undefs, then return a large 4923 // load of the entire vector width starting at the base pointer. If we found 4924 // consecutive loads for the low half, generate a vzext_load node. 4925 if (LastLoadedElt == NumElems - 1) { 4926 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 4927 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4928 LDBase->getPointerInfo(), 4929 LDBase->isVolatile(), LDBase->isNonTemporal(), 4930 LDBase->isInvariant(), 0); 4931 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 4932 LDBase->getPointerInfo(), 4933 LDBase->isVolatile(), LDBase->isNonTemporal(), 4934 LDBase->isInvariant(), LDBase->getAlignment()); 4935 } else if (NumElems == 4 && LastLoadedElt == 1 && 4936 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 4937 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 4938 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 4939 SDValue ResNode = 4940 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 4941 LDBase->getPointerInfo(), 4942 LDBase->getAlignment(), 4943 false/*isVolatile*/, true/*ReadMem*/, 4944 false/*WriteMem*/); 4945 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 4946 } 4947 return SDValue(); 4948} 4949 4950/// isVectorBroadcast - Check if the node chain is suitable to be xformed to 4951/// a vbroadcast node. We support two patterns: 4952/// 1. A splat BUILD_VECTOR which uses a single scalar load. 4953/// 2. A splat shuffle which uses a scalar_to_vector node which comes from 4954/// a scalar load. 4955/// The scalar load node is returned when a pattern is found, 4956/// or SDValue() otherwise. 4957static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) { 4958 if (!Subtarget->hasAVX()) 4959 return SDValue(); 4960 4961 EVT VT = Op.getValueType(); 4962 SDValue V = Op; 4963 4964 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 4965 V = V.getOperand(0); 4966 4967 //A suspected load to be broadcasted. 4968 SDValue Ld; 4969 4970 switch (V.getOpcode()) { 4971 default: 4972 // Unknown pattern found. 4973 return SDValue(); 4974 4975 case ISD::BUILD_VECTOR: { 4976 // The BUILD_VECTOR node must be a splat. 4977 if (!isSplatVector(V.getNode())) 4978 return SDValue(); 4979 4980 Ld = V.getOperand(0); 4981 4982 // The suspected load node has several users. Make sure that all 4983 // of its users are from the BUILD_VECTOR node. 4984 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0)) 4985 return SDValue(); 4986 break; 4987 } 4988 4989 case ISD::VECTOR_SHUFFLE: { 4990 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4991 4992 // Shuffles must have a splat mask where the first element is 4993 // broadcasted. 4994 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0) 4995 return SDValue(); 4996 4997 SDValue Sc = Op.getOperand(0); 4998 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) 4999 return SDValue(); 5000 5001 Ld = Sc.getOperand(0); 5002 5003 // The scalar_to_vector node and the suspected 5004 // load node must have exactly one user. 5005 if (!Sc.hasOneUse() || !Ld.hasOneUse()) 5006 return SDValue(); 5007 break; 5008 } 5009 } 5010 5011 // The scalar source must be a normal load. 5012 if (!ISD::isNormalLoad(Ld.getNode())) 5013 return SDValue(); 5014 5015 bool Is256 = VT.getSizeInBits() == 256; 5016 bool Is128 = VT.getSizeInBits() == 128; 5017 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); 5018 5019 // VBroadcast to YMM 5020 if (Is256 && (ScalarSize == 32 || ScalarSize == 64)) 5021 return Ld; 5022 5023 // VBroadcast to XMM 5024 if (Is128 && (ScalarSize == 32)) 5025 return Ld; 5026 5027 // The integer check is needed for the 64-bit into 128-bit so it doesn't match 5028 // double since there is vbroadcastsd xmm 5029 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) { 5030 // VBroadcast to YMM 5031 if (Is256 && (ScalarSize == 8 || ScalarSize == 16)) 5032 return Ld; 5033 5034 // VBroadcast to XMM 5035 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)) 5036 return Ld; 5037 } 5038 5039 // Unsupported broadcast. 5040 return SDValue(); 5041} 5042 5043SDValue 5044X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5045 DebugLoc dl = Op.getDebugLoc(); 5046 5047 EVT VT = Op.getValueType(); 5048 EVT ExtVT = VT.getVectorElementType(); 5049 unsigned NumElems = Op.getNumOperands(); 5050 5051 // Vectors containing all zeros can be matched by pxor and xorps later 5052 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5053 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5054 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5055 if (VT == MVT::v4i32 || VT == MVT::v8i32) 5056 return Op; 5057 5058 return getZeroVector(VT, Subtarget->hasSSE2(), 5059 Subtarget->hasAVX2(), DAG, dl); 5060 } 5061 5062 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5063 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use 5064 // vpcmpeqd on 256-bit vectors. 5065 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5066 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2())) 5067 return Op; 5068 5069 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl); 5070 } 5071 5072 SDValue LD = isVectorBroadcast(Op, Subtarget); 5073 if (LD.getNode()) 5074 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 5075 5076 unsigned EVTBits = ExtVT.getSizeInBits(); 5077 5078 unsigned NumZero = 0; 5079 unsigned NumNonZero = 0; 5080 unsigned NonZeros = 0; 5081 bool IsAllConstants = true; 5082 SmallSet<SDValue, 8> Values; 5083 for (unsigned i = 0; i < NumElems; ++i) { 5084 SDValue Elt = Op.getOperand(i); 5085 if (Elt.getOpcode() == ISD::UNDEF) 5086 continue; 5087 Values.insert(Elt); 5088 if (Elt.getOpcode() != ISD::Constant && 5089 Elt.getOpcode() != ISD::ConstantFP) 5090 IsAllConstants = false; 5091 if (X86::isZeroNode(Elt)) 5092 NumZero++; 5093 else { 5094 NonZeros |= (1 << i); 5095 NumNonZero++; 5096 } 5097 } 5098 5099 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5100 if (NumNonZero == 0) 5101 return DAG.getUNDEF(VT); 5102 5103 // Special case for single non-zero, non-undef, element. 5104 if (NumNonZero == 1) { 5105 unsigned Idx = CountTrailingZeros_32(NonZeros); 5106 SDValue Item = Op.getOperand(Idx); 5107 5108 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5109 // the value are obviously zero, truncate the value to i32 and do the 5110 // insertion that way. Only do this if the value is non-constant or if the 5111 // value is a constant being inserted into element 0. It is cheaper to do 5112 // a constant pool load than it is to do a movd + shuffle. 5113 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5114 (!IsAllConstants || Idx == 0)) { 5115 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5116 // Handle SSE only. 5117 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5118 EVT VecVT = MVT::v4i32; 5119 unsigned VecElts = 4; 5120 5121 // Truncate the value (which may itself be a constant) to i32, and 5122 // convert it to a vector with movd (S2V+shuffle to zero extend). 5123 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5124 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5125 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5126 5127 // Now we have our 32-bit value zero extended in the low element of 5128 // a vector. If Idx != 0, swizzle it into place. 5129 if (Idx != 0) { 5130 SmallVector<int, 4> Mask; 5131 Mask.push_back(Idx); 5132 for (unsigned i = 1; i != VecElts; ++i) 5133 Mask.push_back(i); 5134 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5135 DAG.getUNDEF(Item.getValueType()), 5136 &Mask[0]); 5137 } 5138 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5139 } 5140 } 5141 5142 // If we have a constant or non-constant insertion into the low element of 5143 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5144 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5145 // depending on what the source datatype is. 5146 if (Idx == 0) { 5147 if (NumZero == 0) 5148 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5149 5150 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5151 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5152 if (VT.getSizeInBits() == 256) { 5153 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(), 5154 Subtarget->hasAVX2(), DAG, dl); 5155 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec, 5156 Item, DAG.getIntPtrConstant(0)); 5157 } 5158 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5159 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5160 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5161 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5162 } 5163 5164 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5165 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5166 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item); 5167 if (VT.getSizeInBits() == 256) { 5168 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(), 5169 Subtarget->hasAVX2(), DAG, dl); 5170 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32), 5171 DAG, dl); 5172 } else { 5173 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5174 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG); 5175 } 5176 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5177 } 5178 } 5179 5180 // Is it a vector logical left shift? 5181 if (NumElems == 2 && Idx == 1 && 5182 X86::isZeroNode(Op.getOperand(0)) && 5183 !X86::isZeroNode(Op.getOperand(1))) { 5184 unsigned NumBits = VT.getSizeInBits(); 5185 return getVShift(true, VT, 5186 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5187 VT, Op.getOperand(1)), 5188 NumBits/2, DAG, *this, dl); 5189 } 5190 5191 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5192 return SDValue(); 5193 5194 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5195 // is a non-constant being inserted into an element other than the low one, 5196 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5197 // movd/movss) to move this into the low element, then shuffle it into 5198 // place. 5199 if (EVTBits == 32) { 5200 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5201 5202 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5203 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG); 5204 SmallVector<int, 8> MaskVec; 5205 for (unsigned i = 0; i < NumElems; i++) 5206 MaskVec.push_back(i == Idx ? 0 : 1); 5207 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5208 } 5209 } 5210 5211 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5212 if (Values.size() == 1) { 5213 if (EVTBits == 32) { 5214 // Instead of a shuffle like this: 5215 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5216 // Check if it's possible to issue this instead. 5217 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5218 unsigned Idx = CountTrailingZeros_32(NonZeros); 5219 SDValue Item = Op.getOperand(Idx); 5220 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5221 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5222 } 5223 return SDValue(); 5224 } 5225 5226 // A vector full of immediates; various special cases are already 5227 // handled, so this is best done with a single constant-pool load. 5228 if (IsAllConstants) 5229 return SDValue(); 5230 5231 // For AVX-length vectors, build the individual 128-bit pieces and use 5232 // shuffles to put them in place. 5233 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5234 SmallVector<SDValue, 32> V; 5235 for (unsigned i = 0; i < NumElems; ++i) 5236 V.push_back(Op.getOperand(i)); 5237 5238 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5239 5240 // Build both the lower and upper subvector. 5241 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5242 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5243 NumElems/2); 5244 5245 // Recreate the wider vector with the lower and upper part. 5246 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5247 DAG.getConstant(0, MVT::i32), DAG, dl); 5248 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5249 DAG, dl); 5250 } 5251 5252 // Let legalizer expand 2-wide build_vectors. 5253 if (EVTBits == 64) { 5254 if (NumNonZero == 1) { 5255 // One half is zero or undef. 5256 unsigned Idx = CountTrailingZeros_32(NonZeros); 5257 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5258 Op.getOperand(Idx)); 5259 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG); 5260 } 5261 return SDValue(); 5262 } 5263 5264 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5265 if (EVTBits == 8 && NumElems == 16) { 5266 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5267 *this); 5268 if (V.getNode()) return V; 5269 } 5270 5271 if (EVTBits == 16 && NumElems == 8) { 5272 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5273 *this); 5274 if (V.getNode()) return V; 5275 } 5276 5277 // If element VT is == 32 bits, turn it into a number of shuffles. 5278 SmallVector<SDValue, 8> V; 5279 V.resize(NumElems); 5280 if (NumElems == 4 && NumZero > 0) { 5281 for (unsigned i = 0; i < 4; ++i) { 5282 bool isZero = !(NonZeros & (1 << i)); 5283 if (isZero) 5284 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), 5285 DAG, dl); 5286 else 5287 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5288 } 5289 5290 for (unsigned i = 0; i < 2; ++i) { 5291 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5292 default: break; 5293 case 0: 5294 V[i] = V[i*2]; // Must be a zero vector. 5295 break; 5296 case 1: 5297 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5298 break; 5299 case 2: 5300 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5301 break; 5302 case 3: 5303 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5304 break; 5305 } 5306 } 5307 5308 SmallVector<int, 8> MaskVec; 5309 bool Reverse = (NonZeros & 0x3) == 2; 5310 for (unsigned i = 0; i < 2; ++i) 5311 MaskVec.push_back(Reverse ? 1-i : i); 5312 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5313 for (unsigned i = 0; i < 2; ++i) 5314 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5315 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5316 } 5317 5318 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5319 // Check for a build vector of consecutive loads. 5320 for (unsigned i = 0; i < NumElems; ++i) 5321 V[i] = Op.getOperand(i); 5322 5323 // Check for elements which are consecutive loads. 5324 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5325 if (LD.getNode()) 5326 return LD; 5327 5328 // For SSE 4.1, use insertps to put the high elements into the low element. 5329 if (getSubtarget()->hasSSE41()) { 5330 SDValue Result; 5331 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5332 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5333 else 5334 Result = DAG.getUNDEF(VT); 5335 5336 for (unsigned i = 1; i < NumElems; ++i) { 5337 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5338 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5339 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5340 } 5341 return Result; 5342 } 5343 5344 // Otherwise, expand into a number of unpckl*, start by extending each of 5345 // our (non-undef) elements to the full vector width with the element in the 5346 // bottom slot of the vector (which generates no code for SSE). 5347 for (unsigned i = 0; i < NumElems; ++i) { 5348 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5349 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5350 else 5351 V[i] = DAG.getUNDEF(VT); 5352 } 5353 5354 // Next, we iteratively mix elements, e.g. for v4f32: 5355 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5356 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5357 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5358 unsigned EltStride = NumElems >> 1; 5359 while (EltStride != 0) { 5360 for (unsigned i = 0; i < EltStride; ++i) { 5361 // If V[i+EltStride] is undef and this is the first round of mixing, 5362 // then it is safe to just drop this shuffle: V[i] is already in the 5363 // right place, the one element (since it's the first round) being 5364 // inserted as undef can be dropped. This isn't safe for successive 5365 // rounds because they will permute elements within both vectors. 5366 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5367 EltStride == NumElems/2) 5368 continue; 5369 5370 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5371 } 5372 EltStride >>= 1; 5373 } 5374 return V[0]; 5375 } 5376 return SDValue(); 5377} 5378 5379// LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5380// them in a MMX register. This is better than doing a stack convert. 5381static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5382 DebugLoc dl = Op.getDebugLoc(); 5383 EVT ResVT = Op.getValueType(); 5384 5385 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5386 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5387 int Mask[2]; 5388 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5389 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5390 InVec = Op.getOperand(1); 5391 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5392 unsigned NumElts = ResVT.getVectorNumElements(); 5393 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5394 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5395 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5396 } else { 5397 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5398 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5399 Mask[0] = 0; Mask[1] = 2; 5400 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5401 } 5402 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5403} 5404 5405// LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5406// to create 256-bit vectors from two other 128-bit ones. 5407static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5408 DebugLoc dl = Op.getDebugLoc(); 5409 EVT ResVT = Op.getValueType(); 5410 5411 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5412 5413 SDValue V1 = Op.getOperand(0); 5414 SDValue V2 = Op.getOperand(1); 5415 unsigned NumElems = ResVT.getVectorNumElements(); 5416 5417 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5418 DAG.getConstant(0, MVT::i32), DAG, dl); 5419 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5420 DAG, dl); 5421} 5422 5423SDValue 5424X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5425 EVT ResVT = Op.getValueType(); 5426 5427 assert(Op.getNumOperands() == 2); 5428 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5429 "Unsupported CONCAT_VECTORS for value type"); 5430 5431 // We support concatenate two MMX registers and place them in a MMX register. 5432 // This is better than doing a stack convert. 5433 if (ResVT.is128BitVector()) 5434 return LowerMMXCONCAT_VECTORS(Op, DAG); 5435 5436 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5437 // from two other 128-bit ones. 5438 return LowerAVXCONCAT_VECTORS(Op, DAG); 5439} 5440 5441// v8i16 shuffles - Prefer shuffles in the following order: 5442// 1. [all] pshuflw, pshufhw, optional move 5443// 2. [ssse3] 1 x pshufb 5444// 3. [ssse3] 2 x pshufb + 1 x por 5445// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5446SDValue 5447X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5448 SelectionDAG &DAG) const { 5449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5450 SDValue V1 = SVOp->getOperand(0); 5451 SDValue V2 = SVOp->getOperand(1); 5452 DebugLoc dl = SVOp->getDebugLoc(); 5453 SmallVector<int, 8> MaskVals; 5454 5455 // Determine if more than 1 of the words in each of the low and high quadwords 5456 // of the result come from the same quadword of one of the two inputs. Undef 5457 // mask values count as coming from any quadword, for better codegen. 5458 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5459 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5460 BitVector InputQuads(4); 5461 for (unsigned i = 0; i < 8; ++i) { 5462 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5463 int EltIdx = SVOp->getMaskElt(i); 5464 MaskVals.push_back(EltIdx); 5465 if (EltIdx < 0) { 5466 ++Quad[0]; 5467 ++Quad[1]; 5468 ++Quad[2]; 5469 ++Quad[3]; 5470 continue; 5471 } 5472 ++Quad[EltIdx / 4]; 5473 InputQuads.set(EltIdx / 4); 5474 } 5475 5476 int BestLoQuad = -1; 5477 unsigned MaxQuad = 1; 5478 for (unsigned i = 0; i < 4; ++i) { 5479 if (LoQuad[i] > MaxQuad) { 5480 BestLoQuad = i; 5481 MaxQuad = LoQuad[i]; 5482 } 5483 } 5484 5485 int BestHiQuad = -1; 5486 MaxQuad = 1; 5487 for (unsigned i = 0; i < 4; ++i) { 5488 if (HiQuad[i] > MaxQuad) { 5489 BestHiQuad = i; 5490 MaxQuad = HiQuad[i]; 5491 } 5492 } 5493 5494 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5495 // of the two input vectors, shuffle them into one input vector so only a 5496 // single pshufb instruction is necessary. If There are more than 2 input 5497 // quads, disable the next transformation since it does not help SSSE3. 5498 bool V1Used = InputQuads[0] || InputQuads[1]; 5499 bool V2Used = InputQuads[2] || InputQuads[3]; 5500 if (Subtarget->hasSSSE3()) { 5501 if (InputQuads.count() == 2 && V1Used && V2Used) { 5502 BestLoQuad = InputQuads.find_first(); 5503 BestHiQuad = InputQuads.find_next(BestLoQuad); 5504 } 5505 if (InputQuads.count() > 2) { 5506 BestLoQuad = -1; 5507 BestHiQuad = -1; 5508 } 5509 } 5510 5511 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5512 // the shuffle mask. If a quad is scored as -1, that means that it contains 5513 // words from all 4 input quadwords. 5514 SDValue NewV; 5515 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5516 SmallVector<int, 8> MaskV; 5517 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5518 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5519 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5520 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5521 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5522 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5523 5524 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5525 // source words for the shuffle, to aid later transformations. 5526 bool AllWordsInNewV = true; 5527 bool InOrder[2] = { true, true }; 5528 for (unsigned i = 0; i != 8; ++i) { 5529 int idx = MaskVals[i]; 5530 if (idx != (int)i) 5531 InOrder[i/4] = false; 5532 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5533 continue; 5534 AllWordsInNewV = false; 5535 break; 5536 } 5537 5538 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5539 if (AllWordsInNewV) { 5540 for (int i = 0; i != 8; ++i) { 5541 int idx = MaskVals[i]; 5542 if (idx < 0) 5543 continue; 5544 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5545 if ((idx != i) && idx < 4) 5546 pshufhw = false; 5547 if ((idx != i) && idx > 3) 5548 pshuflw = false; 5549 } 5550 V1 = NewV; 5551 V2Used = false; 5552 BestLoQuad = 0; 5553 BestHiQuad = 1; 5554 } 5555 5556 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5557 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5558 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5559 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5560 unsigned TargetMask = 0; 5561 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5562 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5563 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5564 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5565 V1 = NewV.getOperand(0); 5566 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5567 } 5568 } 5569 5570 // If we have SSSE3, and all words of the result are from 1 input vector, 5571 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5572 // is present, fall back to case 4. 5573 if (Subtarget->hasSSSE3()) { 5574 SmallVector<SDValue,16> pshufbMask; 5575 5576 // If we have elements from both input vectors, set the high bit of the 5577 // shuffle mask element to zero out elements that come from V2 in the V1 5578 // mask, and elements that come from V1 in the V2 mask, so that the two 5579 // results can be OR'd together. 5580 bool TwoInputs = V1Used && V2Used; 5581 for (unsigned i = 0; i != 8; ++i) { 5582 int EltIdx = MaskVals[i] * 2; 5583 if (TwoInputs && (EltIdx >= 16)) { 5584 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5585 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5586 continue; 5587 } 5588 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5589 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5590 } 5591 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5592 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5593 DAG.getNode(ISD::BUILD_VECTOR, dl, 5594 MVT::v16i8, &pshufbMask[0], 16)); 5595 if (!TwoInputs) 5596 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5597 5598 // Calculate the shuffle mask for the second input, shuffle it, and 5599 // OR it with the first shuffled input. 5600 pshufbMask.clear(); 5601 for (unsigned i = 0; i != 8; ++i) { 5602 int EltIdx = MaskVals[i] * 2; 5603 if (EltIdx < 16) { 5604 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5605 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5606 continue; 5607 } 5608 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5609 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5610 } 5611 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5612 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5613 DAG.getNode(ISD::BUILD_VECTOR, dl, 5614 MVT::v16i8, &pshufbMask[0], 16)); 5615 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5616 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5617 } 5618 5619 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5620 // and update MaskVals with new element order. 5621 BitVector InOrder(8); 5622 if (BestLoQuad >= 0) { 5623 SmallVector<int, 8> MaskV; 5624 for (int i = 0; i != 4; ++i) { 5625 int idx = MaskVals[i]; 5626 if (idx < 0) { 5627 MaskV.push_back(-1); 5628 InOrder.set(i); 5629 } else if ((idx / 4) == BestLoQuad) { 5630 MaskV.push_back(idx & 3); 5631 InOrder.set(i); 5632 } else { 5633 MaskV.push_back(-1); 5634 } 5635 } 5636 for (unsigned i = 4; i != 8; ++i) 5637 MaskV.push_back(i); 5638 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5639 &MaskV[0]); 5640 5641 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5642 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5643 NewV.getOperand(0), 5644 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5645 DAG); 5646 } 5647 5648 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5649 // and update MaskVals with the new element order. 5650 if (BestHiQuad >= 0) { 5651 SmallVector<int, 8> MaskV; 5652 for (unsigned i = 0; i != 4; ++i) 5653 MaskV.push_back(i); 5654 for (unsigned i = 4; i != 8; ++i) { 5655 int idx = MaskVals[i]; 5656 if (idx < 0) { 5657 MaskV.push_back(-1); 5658 InOrder.set(i); 5659 } else if ((idx / 4) == BestHiQuad) { 5660 MaskV.push_back((idx & 3) + 4); 5661 InOrder.set(i); 5662 } else { 5663 MaskV.push_back(-1); 5664 } 5665 } 5666 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5667 &MaskV[0]); 5668 5669 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) 5670 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5671 NewV.getOperand(0), 5672 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5673 DAG); 5674 } 5675 5676 // In case BestHi & BestLo were both -1, which means each quadword has a word 5677 // from each of the four input quadwords, calculate the InOrder bitvector now 5678 // before falling through to the insert/extract cleanup. 5679 if (BestLoQuad == -1 && BestHiQuad == -1) { 5680 NewV = V1; 5681 for (int i = 0; i != 8; ++i) 5682 if (MaskVals[i] < 0 || MaskVals[i] == i) 5683 InOrder.set(i); 5684 } 5685 5686 // The other elements are put in the right place using pextrw and pinsrw. 5687 for (unsigned i = 0; i != 8; ++i) { 5688 if (InOrder[i]) 5689 continue; 5690 int EltIdx = MaskVals[i]; 5691 if (EltIdx < 0) 5692 continue; 5693 SDValue ExtOp = (EltIdx < 8) 5694 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5695 DAG.getIntPtrConstant(EltIdx)) 5696 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5697 DAG.getIntPtrConstant(EltIdx - 8)); 5698 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5699 DAG.getIntPtrConstant(i)); 5700 } 5701 return NewV; 5702} 5703 5704// v16i8 shuffles - Prefer shuffles in the following order: 5705// 1. [ssse3] 1 x pshufb 5706// 2. [ssse3] 2 x pshufb + 1 x por 5707// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5708static 5709SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5710 SelectionDAG &DAG, 5711 const X86TargetLowering &TLI) { 5712 SDValue V1 = SVOp->getOperand(0); 5713 SDValue V2 = SVOp->getOperand(1); 5714 DebugLoc dl = SVOp->getDebugLoc(); 5715 ArrayRef<int> MaskVals = SVOp->getMask(); 5716 5717 // If we have SSSE3, case 1 is generated when all result bytes come from 5718 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5719 // present, fall back to case 3. 5720 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5721 bool V1Only = true; 5722 bool V2Only = true; 5723 for (unsigned i = 0; i < 16; ++i) { 5724 int EltIdx = MaskVals[i]; 5725 if (EltIdx < 0) 5726 continue; 5727 if (EltIdx < 16) 5728 V2Only = false; 5729 else 5730 V1Only = false; 5731 } 5732 5733 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5734 if (TLI.getSubtarget()->hasSSSE3()) { 5735 SmallVector<SDValue,16> pshufbMask; 5736 5737 // If all result elements are from one input vector, then only translate 5738 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5739 // 5740 // Otherwise, we have elements from both input vectors, and must zero out 5741 // elements that come from V2 in the first mask, and V1 in the second mask 5742 // so that we can OR them together. 5743 bool TwoInputs = !(V1Only || V2Only); 5744 for (unsigned i = 0; i != 16; ++i) { 5745 int EltIdx = MaskVals[i]; 5746 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5747 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5748 continue; 5749 } 5750 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5751 } 5752 // If all the elements are from V2, assign it to V1 and return after 5753 // building the first pshufb. 5754 if (V2Only) 5755 V1 = V2; 5756 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5757 DAG.getNode(ISD::BUILD_VECTOR, dl, 5758 MVT::v16i8, &pshufbMask[0], 16)); 5759 if (!TwoInputs) 5760 return V1; 5761 5762 // Calculate the shuffle mask for the second input, shuffle it, and 5763 // OR it with the first shuffled input. 5764 pshufbMask.clear(); 5765 for (unsigned i = 0; i != 16; ++i) { 5766 int EltIdx = MaskVals[i]; 5767 if (EltIdx < 16) { 5768 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5769 continue; 5770 } 5771 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5772 } 5773 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5774 DAG.getNode(ISD::BUILD_VECTOR, dl, 5775 MVT::v16i8, &pshufbMask[0], 16)); 5776 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5777 } 5778 5779 // No SSSE3 - Calculate in place words and then fix all out of place words 5780 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5781 // the 16 different words that comprise the two doublequadword input vectors. 5782 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5783 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5784 SDValue NewV = V2Only ? V2 : V1; 5785 for (int i = 0; i != 8; ++i) { 5786 int Elt0 = MaskVals[i*2]; 5787 int Elt1 = MaskVals[i*2+1]; 5788 5789 // This word of the result is all undef, skip it. 5790 if (Elt0 < 0 && Elt1 < 0) 5791 continue; 5792 5793 // This word of the result is already in the correct place, skip it. 5794 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5795 continue; 5796 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5797 continue; 5798 5799 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5800 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5801 SDValue InsElt; 5802 5803 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5804 // using a single extract together, load it and store it. 5805 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5806 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5807 DAG.getIntPtrConstant(Elt1 / 2)); 5808 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5809 DAG.getIntPtrConstant(i)); 5810 continue; 5811 } 5812 5813 // If Elt1 is defined, extract it from the appropriate source. If the 5814 // source byte is not also odd, shift the extracted word left 8 bits 5815 // otherwise clear the bottom 8 bits if we need to do an or. 5816 if (Elt1 >= 0) { 5817 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5818 DAG.getIntPtrConstant(Elt1 / 2)); 5819 if ((Elt1 & 1) == 0) 5820 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5821 DAG.getConstant(8, 5822 TLI.getShiftAmountTy(InsElt.getValueType()))); 5823 else if (Elt0 >= 0) 5824 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5825 DAG.getConstant(0xFF00, MVT::i16)); 5826 } 5827 // If Elt0 is defined, extract it from the appropriate source. If the 5828 // source byte is not also even, shift the extracted word right 8 bits. If 5829 // Elt1 was also defined, OR the extracted values together before 5830 // inserting them in the result. 5831 if (Elt0 >= 0) { 5832 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5833 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5834 if ((Elt0 & 1) != 0) 5835 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5836 DAG.getConstant(8, 5837 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5838 else if (Elt1 >= 0) 5839 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5840 DAG.getConstant(0x00FF, MVT::i16)); 5841 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5842 : InsElt0; 5843 } 5844 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5845 DAG.getIntPtrConstant(i)); 5846 } 5847 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5848} 5849 5850/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5851/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5852/// done when every pair / quad of shuffle mask elements point to elements in 5853/// the right sequence. e.g. 5854/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5855static 5856SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5857 SelectionDAG &DAG, DebugLoc dl) { 5858 EVT VT = SVOp->getValueType(0); 5859 SDValue V1 = SVOp->getOperand(0); 5860 SDValue V2 = SVOp->getOperand(1); 5861 unsigned NumElems = VT.getVectorNumElements(); 5862 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5863 EVT NewVT; 5864 switch (VT.getSimpleVT().SimpleTy) { 5865 default: assert(false && "Unexpected!"); 5866 case MVT::v4f32: NewVT = MVT::v2f64; break; 5867 case MVT::v4i32: NewVT = MVT::v2i64; break; 5868 case MVT::v8i16: NewVT = MVT::v4i32; break; 5869 case MVT::v16i8: NewVT = MVT::v4i32; break; 5870 } 5871 5872 int Scale = NumElems / NewWidth; 5873 SmallVector<int, 8> MaskVec; 5874 for (unsigned i = 0; i < NumElems; i += Scale) { 5875 int StartIdx = -1; 5876 for (int j = 0; j < Scale; ++j) { 5877 int EltIdx = SVOp->getMaskElt(i+j); 5878 if (EltIdx < 0) 5879 continue; 5880 if (StartIdx == -1) 5881 StartIdx = EltIdx - (EltIdx % Scale); 5882 if (EltIdx != StartIdx + j) 5883 return SDValue(); 5884 } 5885 if (StartIdx == -1) 5886 MaskVec.push_back(-1); 5887 else 5888 MaskVec.push_back(StartIdx / Scale); 5889 } 5890 5891 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5892 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5893 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5894} 5895 5896/// getVZextMovL - Return a zero-extending vector move low node. 5897/// 5898static SDValue getVZextMovL(EVT VT, EVT OpVT, 5899 SDValue SrcOp, SelectionDAG &DAG, 5900 const X86Subtarget *Subtarget, DebugLoc dl) { 5901 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5902 LoadSDNode *LD = NULL; 5903 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5904 LD = dyn_cast<LoadSDNode>(SrcOp); 5905 if (!LD) { 5906 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5907 // instead. 5908 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5909 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5910 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5911 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5912 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5913 // PR2108 5914 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5915 return DAG.getNode(ISD::BITCAST, dl, VT, 5916 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5917 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5918 OpVT, 5919 SrcOp.getOperand(0) 5920 .getOperand(0)))); 5921 } 5922 } 5923 } 5924 5925 return DAG.getNode(ISD::BITCAST, dl, VT, 5926 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5927 DAG.getNode(ISD::BITCAST, dl, 5928 OpVT, SrcOp))); 5929} 5930 5931/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5932/// which could not be matched by any known target speficic shuffle 5933static SDValue 5934LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5935 EVT VT = SVOp->getValueType(0); 5936 5937 unsigned NumElems = VT.getVectorNumElements(); 5938 unsigned NumLaneElems = NumElems / 2; 5939 5940 int MinRange[2][2] = { { static_cast<int>(NumElems), 5941 static_cast<int>(NumElems) }, 5942 { static_cast<int>(NumElems), 5943 static_cast<int>(NumElems) } }; 5944 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } }; 5945 5946 // Collect used ranges for each source in each lane 5947 for (unsigned l = 0; l < 2; ++l) { 5948 unsigned LaneStart = l*NumLaneElems; 5949 for (unsigned i = 0; i != NumLaneElems; ++i) { 5950 int Idx = SVOp->getMaskElt(i+LaneStart); 5951 if (Idx < 0) 5952 continue; 5953 5954 int Input = 0; 5955 if (Idx >= (int)NumElems) { 5956 Idx -= NumElems; 5957 Input = 1; 5958 } 5959 5960 if (Idx > MaxRange[l][Input]) 5961 MaxRange[l][Input] = Idx; 5962 if (Idx < MinRange[l][Input]) 5963 MinRange[l][Input] = Idx; 5964 } 5965 } 5966 5967 // Make sure each range is 128-bits 5968 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } }; 5969 for (unsigned l = 0; l < 2; ++l) { 5970 for (unsigned Input = 0; Input < 2; ++Input) { 5971 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0) 5972 continue; 5973 5974 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems) 5975 ExtractIdx[l][Input] = 0; 5976 else if (MinRange[l][Input] >= (int)NumLaneElems && 5977 MaxRange[l][Input] < (int)NumElems) 5978 ExtractIdx[l][Input] = NumLaneElems; 5979 else 5980 return SDValue(); 5981 } 5982 } 5983 5984 DebugLoc dl = SVOp->getDebugLoc(); 5985 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 5986 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2); 5987 5988 SDValue Ops[2][2]; 5989 for (unsigned l = 0; l < 2; ++l) { 5990 for (unsigned Input = 0; Input < 2; ++Input) { 5991 if (ExtractIdx[l][Input] >= 0) 5992 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input), 5993 DAG.getConstant(ExtractIdx[l][Input], MVT::i32), 5994 DAG, dl); 5995 else 5996 Ops[l][Input] = DAG.getUNDEF(NVT); 5997 } 5998 } 5999 6000 // Generate 128-bit shuffles 6001 SmallVector<int, 16> Mask1, Mask2; 6002 for (unsigned i = 0; i != NumLaneElems; ++i) { 6003 int Elt = SVOp->getMaskElt(i); 6004 if (Elt >= (int)NumElems) { 6005 Elt %= NumLaneElems; 6006 Elt += NumLaneElems; 6007 } else if (Elt >= 0) { 6008 Elt %= NumLaneElems; 6009 } 6010 Mask1.push_back(Elt); 6011 } 6012 for (unsigned i = NumLaneElems; i != NumElems; ++i) { 6013 int Elt = SVOp->getMaskElt(i); 6014 if (Elt >= (int)NumElems) { 6015 Elt %= NumLaneElems; 6016 Elt += NumLaneElems; 6017 } else if (Elt >= 0) { 6018 Elt %= NumLaneElems; 6019 } 6020 Mask2.push_back(Elt); 6021 } 6022 6023 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]); 6024 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]); 6025 6026 // Concatenate the result back 6027 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1, 6028 DAG.getConstant(0, MVT::i32), DAG, dl); 6029 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32), 6030 DAG, dl); 6031} 6032 6033/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6034/// 4 elements, and match them with several different shuffle types. 6035static SDValue 6036LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6037 SDValue V1 = SVOp->getOperand(0); 6038 SDValue V2 = SVOp->getOperand(1); 6039 DebugLoc dl = SVOp->getDebugLoc(); 6040 EVT VT = SVOp->getValueType(0); 6041 6042 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6043 6044 SmallVector<std::pair<int, int>, 8> Locs; 6045 Locs.resize(4); 6046 SmallVector<int, 8> Mask1(4U, -1); 6047 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end()); 6048 6049 unsigned NumHi = 0; 6050 unsigned NumLo = 0; 6051 for (unsigned i = 0; i != 4; ++i) { 6052 int Idx = PermMask[i]; 6053 if (Idx < 0) { 6054 Locs[i] = std::make_pair(-1, -1); 6055 } else { 6056 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6057 if (Idx < 4) { 6058 Locs[i] = std::make_pair(0, NumLo); 6059 Mask1[NumLo] = Idx; 6060 NumLo++; 6061 } else { 6062 Locs[i] = std::make_pair(1, NumHi); 6063 if (2+NumHi < 4) 6064 Mask1[2+NumHi] = Idx; 6065 NumHi++; 6066 } 6067 } 6068 } 6069 6070 if (NumLo <= 2 && NumHi <= 2) { 6071 // If no more than two elements come from either vector. This can be 6072 // implemented with two shuffles. First shuffle gather the elements. 6073 // The second shuffle, which takes the first shuffle as both of its 6074 // vector operands, put the elements into the right order. 6075 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6076 6077 SmallVector<int, 8> Mask2(4U, -1); 6078 6079 for (unsigned i = 0; i != 4; ++i) { 6080 if (Locs[i].first == -1) 6081 continue; 6082 else { 6083 unsigned Idx = (i < 2) ? 0 : 4; 6084 Idx += Locs[i].first * 2 + Locs[i].second; 6085 Mask2[i] = Idx; 6086 } 6087 } 6088 6089 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6090 } else if (NumLo == 3 || NumHi == 3) { 6091 // Otherwise, we must have three elements from one vector, call it X, and 6092 // one element from the other, call it Y. First, use a shufps to build an 6093 // intermediate vector with the one element from Y and the element from X 6094 // that will be in the same half in the final destination (the indexes don't 6095 // matter). Then, use a shufps to build the final vector, taking the half 6096 // containing the element from Y from the intermediate, and the other half 6097 // from X. 6098 if (NumHi == 3) { 6099 // Normalize it so the 3 elements come from V1. 6100 CommuteVectorShuffleMask(PermMask, 4); 6101 std::swap(V1, V2); 6102 } 6103 6104 // Find the element from V2. 6105 unsigned HiIndex; 6106 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6107 int Val = PermMask[HiIndex]; 6108 if (Val < 0) 6109 continue; 6110 if (Val >= 4) 6111 break; 6112 } 6113 6114 Mask1[0] = PermMask[HiIndex]; 6115 Mask1[1] = -1; 6116 Mask1[2] = PermMask[HiIndex^1]; 6117 Mask1[3] = -1; 6118 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6119 6120 if (HiIndex >= 2) { 6121 Mask1[0] = PermMask[0]; 6122 Mask1[1] = PermMask[1]; 6123 Mask1[2] = HiIndex & 1 ? 6 : 4; 6124 Mask1[3] = HiIndex & 1 ? 4 : 6; 6125 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6126 } else { 6127 Mask1[0] = HiIndex & 1 ? 2 : 0; 6128 Mask1[1] = HiIndex & 1 ? 0 : 2; 6129 Mask1[2] = PermMask[2]; 6130 Mask1[3] = PermMask[3]; 6131 if (Mask1[2] >= 0) 6132 Mask1[2] += 4; 6133 if (Mask1[3] >= 0) 6134 Mask1[3] += 4; 6135 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6136 } 6137 } 6138 6139 // Break it into (shuffle shuffle_hi, shuffle_lo). 6140 Locs.clear(); 6141 Locs.resize(4); 6142 SmallVector<int,8> LoMask(4U, -1); 6143 SmallVector<int,8> HiMask(4U, -1); 6144 6145 SmallVector<int,8> *MaskPtr = &LoMask; 6146 unsigned MaskIdx = 0; 6147 unsigned LoIdx = 0; 6148 unsigned HiIdx = 2; 6149 for (unsigned i = 0; i != 4; ++i) { 6150 if (i == 2) { 6151 MaskPtr = &HiMask; 6152 MaskIdx = 1; 6153 LoIdx = 0; 6154 HiIdx = 2; 6155 } 6156 int Idx = PermMask[i]; 6157 if (Idx < 0) { 6158 Locs[i] = std::make_pair(-1, -1); 6159 } else if (Idx < 4) { 6160 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6161 (*MaskPtr)[LoIdx] = Idx; 6162 LoIdx++; 6163 } else { 6164 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6165 (*MaskPtr)[HiIdx] = Idx; 6166 HiIdx++; 6167 } 6168 } 6169 6170 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6171 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6172 SmallVector<int, 8> MaskOps; 6173 for (unsigned i = 0; i != 4; ++i) { 6174 if (Locs[i].first == -1) { 6175 MaskOps.push_back(-1); 6176 } else { 6177 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6178 MaskOps.push_back(Idx); 6179 } 6180 } 6181 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6182} 6183 6184static bool MayFoldVectorLoad(SDValue V) { 6185 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6186 V = V.getOperand(0); 6187 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6188 V = V.getOperand(0); 6189 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && 6190 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) 6191 // BUILD_VECTOR (load), undef 6192 V = V.getOperand(0); 6193 if (MayFoldLoad(V)) 6194 return true; 6195 return false; 6196} 6197 6198// FIXME: the version above should always be used. Since there's 6199// a bug where several vector shuffles can't be folded because the 6200// DAG is not updated during lowering and a node claims to have two 6201// uses while it only has one, use this version, and let isel match 6202// another instruction if the load really happens to have more than 6203// one use. Remove this version after this bug get fixed. 6204// rdar://8434668, PR8156 6205static bool RelaxedMayFoldVectorLoad(SDValue V) { 6206 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6207 V = V.getOperand(0); 6208 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6209 V = V.getOperand(0); 6210 if (ISD::isNormalLoad(V.getNode())) 6211 return true; 6212 return false; 6213} 6214 6215/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6216/// a vector extract, and if both can be later optimized into a single load. 6217/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6218/// here because otherwise a target specific shuffle node is going to be 6219/// emitted for this shuffle, and the optimization not done. 6220/// FIXME: This is probably not the best approach, but fix the problem 6221/// until the right path is decided. 6222static 6223bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6224 const TargetLowering &TLI) { 6225 EVT VT = V.getValueType(); 6226 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6227 6228 // Be sure that the vector shuffle is present in a pattern like this: 6229 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6230 if (!V.hasOneUse()) 6231 return false; 6232 6233 SDNode *N = *V.getNode()->use_begin(); 6234 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6235 return false; 6236 6237 SDValue EltNo = N->getOperand(1); 6238 if (!isa<ConstantSDNode>(EltNo)) 6239 return false; 6240 6241 // If the bit convert changed the number of elements, it is unsafe 6242 // to examine the mask. 6243 bool HasShuffleIntoBitcast = false; 6244 if (V.getOpcode() == ISD::BITCAST) { 6245 EVT SrcVT = V.getOperand(0).getValueType(); 6246 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6247 return false; 6248 V = V.getOperand(0); 6249 HasShuffleIntoBitcast = true; 6250 } 6251 6252 // Select the input vector, guarding against out of range extract vector. 6253 unsigned NumElems = VT.getVectorNumElements(); 6254 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6255 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6256 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6257 6258 // If we are accessing the upper part of a YMM register 6259 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of 6260 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point 6261 // because the legalization of N did not happen yet. 6262 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256) 6263 return false; 6264 6265 // Skip one more bit_convert if necessary 6266 if (V.getOpcode() == ISD::BITCAST) 6267 V = V.getOperand(0); 6268 6269 if (!ISD::isNormalLoad(V.getNode())) 6270 return false; 6271 6272 // Is the original load suitable? 6273 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6274 6275 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6276 return false; 6277 6278 if (!HasShuffleIntoBitcast) 6279 return true; 6280 6281 // If there's a bitcast before the shuffle, check if the load type and 6282 // alignment is valid. 6283 unsigned Align = LN0->getAlignment(); 6284 unsigned NewAlign = 6285 TLI.getTargetData()->getABITypeAlignment( 6286 VT.getTypeForEVT(*DAG.getContext())); 6287 6288 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6289 return false; 6290 6291 return true; 6292} 6293 6294static 6295SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6296 EVT VT = Op.getValueType(); 6297 6298 // Canonizalize to v2f64. 6299 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6300 return DAG.getNode(ISD::BITCAST, dl, VT, 6301 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6302 V1, DAG)); 6303} 6304 6305static 6306SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6307 bool HasSSE2) { 6308 SDValue V1 = Op.getOperand(0); 6309 SDValue V2 = Op.getOperand(1); 6310 EVT VT = Op.getValueType(); 6311 6312 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6313 6314 if (HasSSE2 && VT == MVT::v2f64) 6315 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6316 6317 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6318 return DAG.getNode(ISD::BITCAST, dl, VT, 6319 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6320 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6321 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6322} 6323 6324static 6325SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6326 SDValue V1 = Op.getOperand(0); 6327 SDValue V2 = Op.getOperand(1); 6328 EVT VT = Op.getValueType(); 6329 6330 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6331 "unsupported shuffle type"); 6332 6333 if (V2.getOpcode() == ISD::UNDEF) 6334 V2 = V1; 6335 6336 // v4i32 or v4f32 6337 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6338} 6339 6340static 6341SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { 6342 SDValue V1 = Op.getOperand(0); 6343 SDValue V2 = Op.getOperand(1); 6344 EVT VT = Op.getValueType(); 6345 unsigned NumElems = VT.getVectorNumElements(); 6346 6347 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6348 // operand of these instructions is only memory, so check if there's a 6349 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6350 // same masks. 6351 bool CanFoldLoad = false; 6352 6353 // Trivial case, when V2 comes from a load. 6354 if (MayFoldVectorLoad(V2)) 6355 CanFoldLoad = true; 6356 6357 // When V1 is a load, it can be folded later into a store in isel, example: 6358 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6359 // turns into: 6360 // (MOVLPSmr addr:$src1, VR128:$src2) 6361 // So, recognize this potential and also use MOVLPS or MOVLPD 6362 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6363 CanFoldLoad = true; 6364 6365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6366 if (CanFoldLoad) { 6367 if (HasSSE2 && NumElems == 2) 6368 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6369 6370 if (NumElems == 4) 6371 // If we don't care about the second element, procede to use movss. 6372 if (SVOp->getMaskElt(1) != -1) 6373 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6374 } 6375 6376 // movl and movlp will both match v2i64, but v2i64 is never matched by 6377 // movl earlier because we make it strict to avoid messing with the movlp load 6378 // folding logic (see the code above getMOVLP call). Match it here then, 6379 // this is horrible, but will stay like this until we move all shuffle 6380 // matching to x86 specific nodes. Note that for the 1st condition all 6381 // types are matched with movsd. 6382 if (HasSSE2) { 6383 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6384 // as to remove this logic from here, as much as possible 6385 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6386 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6387 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6388 } 6389 6390 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6391 6392 // Invert the operand order and use SHUFPS to match it. 6393 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1, 6394 X86::getShuffleSHUFImmediate(SVOp), DAG); 6395} 6396 6397static 6398SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6399 const TargetLowering &TLI, 6400 const X86Subtarget *Subtarget) { 6401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6402 EVT VT = Op.getValueType(); 6403 DebugLoc dl = Op.getDebugLoc(); 6404 SDValue V1 = Op.getOperand(0); 6405 SDValue V2 = Op.getOperand(1); 6406 6407 if (isZeroShuffle(SVOp)) 6408 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), 6409 DAG, dl); 6410 6411 // Handle splat operations 6412 if (SVOp->isSplat()) { 6413 unsigned NumElem = VT.getVectorNumElements(); 6414 int Size = VT.getSizeInBits(); 6415 // Special case, this is the only place now where it's allowed to return 6416 // a vector_shuffle operation without using a target specific node, because 6417 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6418 // this be moved to DAGCombine instead? 6419 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6420 return Op; 6421 6422 // Use vbroadcast whenever the splat comes from a foldable load 6423 SDValue LD = isVectorBroadcast(Op, Subtarget); 6424 if (LD.getNode()) 6425 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD); 6426 6427 // Handle splats by matching through known shuffle masks 6428 if ((Size == 128 && NumElem <= 4) || 6429 (Size == 256 && NumElem < 8)) 6430 return SDValue(); 6431 6432 // All remaning splats are promoted to target supported vector shuffles. 6433 return PromoteSplat(SVOp, DAG); 6434 } 6435 6436 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6437 // do it! 6438 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6439 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6440 if (NewOp.getNode()) 6441 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6442 } else if ((VT == MVT::v4i32 || 6443 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 6444 // FIXME: Figure out a cleaner way to do this. 6445 // Try to make use of movq to zero out the top part. 6446 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6447 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6448 if (NewOp.getNode()) { 6449 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6450 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6451 DAG, Subtarget, dl); 6452 } 6453 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6454 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6455 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6456 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6457 DAG, Subtarget, dl); 6458 } 6459 } 6460 return SDValue(); 6461} 6462 6463SDValue 6464X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6465 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6466 SDValue V1 = Op.getOperand(0); 6467 SDValue V2 = Op.getOperand(1); 6468 EVT VT = Op.getValueType(); 6469 DebugLoc dl = Op.getDebugLoc(); 6470 unsigned NumElems = VT.getVectorNumElements(); 6471 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6472 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6473 bool V1IsSplat = false; 6474 bool V2IsSplat = false; 6475 bool HasSSE2 = Subtarget->hasSSE2(); 6476 bool HasAVX = Subtarget->hasAVX(); 6477 bool HasAVX2 = Subtarget->hasAVX2(); 6478 MachineFunction &MF = DAG.getMachineFunction(); 6479 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6480 6481 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles"); 6482 6483 if (V1IsUndef && V2IsUndef) 6484 return DAG.getUNDEF(VT); 6485 6486 assert(!V1IsUndef && "Op 1 of shuffle should not be undef"); 6487 6488 // Vector shuffle lowering takes 3 steps: 6489 // 6490 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6491 // narrowing and commutation of operands should be handled. 6492 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6493 // shuffle nodes. 6494 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6495 // so the shuffle can be broken into other shuffles and the legalizer can 6496 // try the lowering again. 6497 // 6498 // The general idea is that no vector_shuffle operation should be left to 6499 // be matched during isel, all of them must be converted to a target specific 6500 // node here. 6501 6502 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6503 // narrowing and commutation of operands should be handled. The actual code 6504 // doesn't include all of those, work in progress... 6505 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6506 if (NewOp.getNode()) 6507 return NewOp; 6508 6509 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6510 // unpckh_undef). Only use pshufd if speed is more important than size. 6511 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2)) 6512 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6513 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2)) 6514 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6515 6516 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() && 6517 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6518 return getMOVDDup(Op, dl, V1, DAG); 6519 6520 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6521 return getMOVHighToLow(Op, dl, DAG); 6522 6523 // Use to match splats 6524 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef && 6525 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6526 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6527 6528 if (X86::isPSHUFDMask(SVOp)) { 6529 // The actual implementation will match the mask in the if above and then 6530 // during isel it can match several different instructions, not only pshufd 6531 // as its name says, sad but true, emulate the behavior for now... 6532 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6533 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6534 6535 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6536 6537 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6538 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6539 6540 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1, 6541 TargetMask, DAG); 6542 } 6543 6544 // Check if this can be converted into a logical shift. 6545 bool isLeft = false; 6546 unsigned ShAmt = 0; 6547 SDValue ShVal; 6548 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6549 if (isShift && ShVal.hasOneUse()) { 6550 // If the shifted value has multiple uses, it may be cheaper to use 6551 // v_set0 + movlhps or movhlps, etc. 6552 EVT EltVT = VT.getVectorElementType(); 6553 ShAmt *= EltVT.getSizeInBits(); 6554 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6555 } 6556 6557 if (X86::isMOVLMask(SVOp)) { 6558 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6559 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6560 if (!X86::isMOVLPMask(SVOp)) { 6561 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6562 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6563 6564 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6565 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6566 } 6567 } 6568 6569 // FIXME: fold these into legal mask. 6570 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2)) 6571 return getMOVLowToHigh(Op, dl, DAG, HasSSE2); 6572 6573 if (X86::isMOVHLPSMask(SVOp)) 6574 return getMOVHighToLow(Op, dl, DAG); 6575 6576 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6577 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6578 6579 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6580 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6581 6582 if (X86::isMOVLPMask(SVOp)) 6583 return getMOVLP(Op, dl, DAG, HasSSE2); 6584 6585 if (ShouldXformToMOVHLPS(SVOp) || 6586 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6587 return CommuteVectorShuffle(SVOp, DAG); 6588 6589 if (isShift) { 6590 // No better options. Use a vshldq / vsrldq. 6591 EVT EltVT = VT.getVectorElementType(); 6592 ShAmt *= EltVT.getSizeInBits(); 6593 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6594 } 6595 6596 bool Commuted = false; 6597 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6598 // 1,1,1,1 -> v8i16 though. 6599 V1IsSplat = isSplatVector(V1.getNode()); 6600 V2IsSplat = isSplatVector(V2.getNode()); 6601 6602 // Canonicalize the splat or undef, if present, to be on the RHS. 6603 if (V1IsSplat && !V2IsSplat) { 6604 Op = CommuteVectorShuffle(SVOp, DAG); 6605 SVOp = cast<ShuffleVectorSDNode>(Op); 6606 V1 = SVOp->getOperand(0); 6607 V2 = SVOp->getOperand(1); 6608 std::swap(V1IsSplat, V2IsSplat); 6609 Commuted = true; 6610 } 6611 6612 ArrayRef<int> M = SVOp->getMask(); 6613 6614 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) { 6615 // Shuffling low element of v1 into undef, just return v1. 6616 if (V2IsUndef) 6617 return V1; 6618 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6619 // the instruction selector will not match, so get a canonical MOVL with 6620 // swapped operands to undo the commute. 6621 return getMOVL(DAG, dl, VT, V2, V1); 6622 } 6623 6624 if (isUNPCKLMask(M, VT, HasAVX2)) 6625 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG); 6626 6627 if (isUNPCKHMask(M, VT, HasAVX2)) 6628 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG); 6629 6630 if (V2IsSplat) { 6631 // Normalize mask so all entries that point to V2 points to its first 6632 // element then try to match unpck{h|l} again. If match, return a 6633 // new vector_shuffle with the corrected mask. 6634 SDValue NewMask = NormalizeMask(SVOp, DAG); 6635 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6636 if (NSVOp != SVOp) { 6637 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) { 6638 return NewMask; 6639 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) { 6640 return NewMask; 6641 } 6642 } 6643 } 6644 6645 if (Commuted) { 6646 // Commute is back and try unpck* again. 6647 // FIXME: this seems wrong. 6648 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6649 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6650 6651 if (X86::isUNPCKLMask(NewSVOp, HasAVX2)) 6652 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG); 6653 6654 if (X86::isUNPCKHMask(NewSVOp, HasAVX2)) 6655 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG); 6656 } 6657 6658 // Normalize the node to match x86 shuffle ops if needed 6659 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true))) 6660 return CommuteVectorShuffle(SVOp, DAG); 6661 6662 // The checks below are all present in isShuffleMaskLegal, but they are 6663 // inlined here right now to enable us to directly emit target specific 6664 // nodes, and remove one by one until they don't return Op anymore. 6665 6666 if (isPALIGNRMask(M, VT, Subtarget)) 6667 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6668 getShufflePALIGNRImmediate(SVOp), 6669 DAG); 6670 6671 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6672 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6673 if (VT == MVT::v2f64 || VT == MVT::v2i64) 6674 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6675 } 6676 6677 if (isPSHUFHWMask(M, VT)) 6678 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6679 X86::getShufflePSHUFHWImmediate(SVOp), 6680 DAG); 6681 6682 if (isPSHUFLWMask(M, VT)) 6683 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6684 X86::getShufflePSHUFLWImmediate(SVOp), 6685 DAG); 6686 6687 if (isSHUFPMask(M, VT, HasAVX)) 6688 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2, 6689 X86::getShuffleSHUFImmediate(SVOp), DAG); 6690 6691 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2)) 6692 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG); 6693 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2)) 6694 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG); 6695 6696 //===--------------------------------------------------------------------===// 6697 // Generate target specific nodes for 128 or 256-bit shuffles only 6698 // supported in the AVX instruction set. 6699 // 6700 6701 // Handle VMOVDDUPY permutations 6702 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX)) 6703 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6704 6705 // Handle VPERMILPS/D* permutations 6706 if (isVPERMILPMask(M, VT, HasAVX)) 6707 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, 6708 getShuffleVPERMILPImmediate(SVOp), DAG); 6709 6710 // Handle VPERM2F128/VPERM2I128 permutations 6711 if (isVPERM2X128Mask(M, VT, HasAVX)) 6712 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, 6713 V2, getShuffleVPERM2X128Immediate(SVOp), DAG); 6714 6715 //===--------------------------------------------------------------------===// 6716 // Since no target specific shuffle was selected for this generic one, 6717 // lower it into other known shuffles. FIXME: this isn't true yet, but 6718 // this is the plan. 6719 // 6720 6721 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6722 if (VT == MVT::v8i16) { 6723 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6724 if (NewOp.getNode()) 6725 return NewOp; 6726 } 6727 6728 if (VT == MVT::v16i8) { 6729 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6730 if (NewOp.getNode()) 6731 return NewOp; 6732 } 6733 6734 // Handle all 128-bit wide vectors with 4 elements, and match them with 6735 // several different shuffle types. 6736 if (NumElems == 4 && VT.getSizeInBits() == 128) 6737 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6738 6739 // Handle general 256-bit shuffles 6740 if (VT.is256BitVector()) 6741 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6742 6743 return SDValue(); 6744} 6745 6746SDValue 6747X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6748 SelectionDAG &DAG) const { 6749 EVT VT = Op.getValueType(); 6750 DebugLoc dl = Op.getDebugLoc(); 6751 6752 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6753 return SDValue(); 6754 6755 if (VT.getSizeInBits() == 8) { 6756 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6757 Op.getOperand(0), Op.getOperand(1)); 6758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6759 DAG.getValueType(VT)); 6760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6761 } else if (VT.getSizeInBits() == 16) { 6762 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6763 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6764 if (Idx == 0) 6765 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6766 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6767 DAG.getNode(ISD::BITCAST, dl, 6768 MVT::v4i32, 6769 Op.getOperand(0)), 6770 Op.getOperand(1))); 6771 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6772 Op.getOperand(0), Op.getOperand(1)); 6773 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6774 DAG.getValueType(VT)); 6775 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6776 } else if (VT == MVT::f32) { 6777 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6778 // the result back to FR32 register. It's only worth matching if the 6779 // result has a single use which is a store or a bitcast to i32. And in 6780 // the case of a store, it's not worth it if the index is a constant 0, 6781 // because a MOVSSmr can be used instead, which is smaller and faster. 6782 if (!Op.hasOneUse()) 6783 return SDValue(); 6784 SDNode *User = *Op.getNode()->use_begin(); 6785 if ((User->getOpcode() != ISD::STORE || 6786 (isa<ConstantSDNode>(Op.getOperand(1)) && 6787 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6788 (User->getOpcode() != ISD::BITCAST || 6789 User->getValueType(0) != MVT::i32)) 6790 return SDValue(); 6791 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6792 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6793 Op.getOperand(0)), 6794 Op.getOperand(1)); 6795 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6796 } else if (VT == MVT::i32 || VT == MVT::i64) { 6797 // ExtractPS/pextrq works with constant index. 6798 if (isa<ConstantSDNode>(Op.getOperand(1))) 6799 return Op; 6800 } 6801 return SDValue(); 6802} 6803 6804 6805SDValue 6806X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6807 SelectionDAG &DAG) const { 6808 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6809 return SDValue(); 6810 6811 SDValue Vec = Op.getOperand(0); 6812 EVT VecVT = Vec.getValueType(); 6813 6814 // If this is a 256-bit vector result, first extract the 128-bit vector and 6815 // then extract the element from the 128-bit vector. 6816 if (VecVT.getSizeInBits() == 256) { 6817 DebugLoc dl = Op.getNode()->getDebugLoc(); 6818 unsigned NumElems = VecVT.getVectorNumElements(); 6819 SDValue Idx = Op.getOperand(1); 6820 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6821 6822 // Get the 128-bit vector. 6823 bool Upper = IdxVal >= NumElems/2; 6824 Vec = Extract128BitVector(Vec, 6825 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6826 6827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6828 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6829 } 6830 6831 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6832 6833 if (Subtarget->hasSSE41()) { 6834 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6835 if (Res.getNode()) 6836 return Res; 6837 } 6838 6839 EVT VT = Op.getValueType(); 6840 DebugLoc dl = Op.getDebugLoc(); 6841 // TODO: handle v16i8. 6842 if (VT.getSizeInBits() == 16) { 6843 SDValue Vec = Op.getOperand(0); 6844 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6845 if (Idx == 0) 6846 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6847 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6848 DAG.getNode(ISD::BITCAST, dl, 6849 MVT::v4i32, Vec), 6850 Op.getOperand(1))); 6851 // Transform it so it match pextrw which produces a 32-bit result. 6852 EVT EltVT = MVT::i32; 6853 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6854 Op.getOperand(0), Op.getOperand(1)); 6855 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6856 DAG.getValueType(VT)); 6857 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6858 } else if (VT.getSizeInBits() == 32) { 6859 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6860 if (Idx == 0) 6861 return Op; 6862 6863 // SHUFPS the element to the lowest double word, then movss. 6864 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6865 EVT VVT = Op.getOperand(0).getValueType(); 6866 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6867 DAG.getUNDEF(VVT), Mask); 6868 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6869 DAG.getIntPtrConstant(0)); 6870 } else if (VT.getSizeInBits() == 64) { 6871 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6872 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6873 // to match extract_elt for f64. 6874 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6875 if (Idx == 0) 6876 return Op; 6877 6878 // UNPCKHPD the element to the lowest double word, then movsd. 6879 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6880 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6881 int Mask[2] = { 1, -1 }; 6882 EVT VVT = Op.getOperand(0).getValueType(); 6883 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6884 DAG.getUNDEF(VVT), Mask); 6885 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6886 DAG.getIntPtrConstant(0)); 6887 } 6888 6889 return SDValue(); 6890} 6891 6892SDValue 6893X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6894 SelectionDAG &DAG) const { 6895 EVT VT = Op.getValueType(); 6896 EVT EltVT = VT.getVectorElementType(); 6897 DebugLoc dl = Op.getDebugLoc(); 6898 6899 SDValue N0 = Op.getOperand(0); 6900 SDValue N1 = Op.getOperand(1); 6901 SDValue N2 = Op.getOperand(2); 6902 6903 if (VT.getSizeInBits() == 256) 6904 return SDValue(); 6905 6906 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 6907 isa<ConstantSDNode>(N2)) { 6908 unsigned Opc; 6909 if (VT == MVT::v8i16) 6910 Opc = X86ISD::PINSRW; 6911 else if (VT == MVT::v16i8) 6912 Opc = X86ISD::PINSRB; 6913 else 6914 Opc = X86ISD::PINSRB; 6915 6916 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 6917 // argument. 6918 if (N1.getValueType() != MVT::i32) 6919 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6920 if (N2.getValueType() != MVT::i32) 6921 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6922 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 6923 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 6924 // Bits [7:6] of the constant are the source select. This will always be 6925 // zero here. The DAG Combiner may combine an extract_elt index into these 6926 // bits. For example (insert (extract, 3), 2) could be matched by putting 6927 // the '3' into bits [7:6] of X86ISD::INSERTPS. 6928 // Bits [5:4] of the constant are the destination select. This is the 6929 // value of the incoming immediate. 6930 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 6931 // combine either bitwise AND or insert of float 0.0 to set these bits. 6932 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 6933 // Create this as a scalar to vector.. 6934 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 6935 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 6936 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) && 6937 isa<ConstantSDNode>(N2)) { 6938 // PINSR* works with constant index. 6939 return Op; 6940 } 6941 return SDValue(); 6942} 6943 6944SDValue 6945X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 6946 EVT VT = Op.getValueType(); 6947 EVT EltVT = VT.getVectorElementType(); 6948 6949 DebugLoc dl = Op.getDebugLoc(); 6950 SDValue N0 = Op.getOperand(0); 6951 SDValue N1 = Op.getOperand(1); 6952 SDValue N2 = Op.getOperand(2); 6953 6954 // If this is a 256-bit vector result, first extract the 128-bit vector, 6955 // insert the element into the extracted half and then place it back. 6956 if (VT.getSizeInBits() == 256) { 6957 if (!isa<ConstantSDNode>(N2)) 6958 return SDValue(); 6959 6960 // Get the desired 128-bit vector half. 6961 unsigned NumElems = VT.getVectorNumElements(); 6962 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 6963 bool Upper = IdxVal >= NumElems/2; 6964 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 6965 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 6966 6967 // Insert the element into the desired half. 6968 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 6969 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 6970 6971 // Insert the changed part back to the 256-bit vector 6972 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 6973 } 6974 6975 if (Subtarget->hasSSE41()) 6976 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 6977 6978 if (EltVT == MVT::i8) 6979 return SDValue(); 6980 6981 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 6982 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 6983 // as its second argument. 6984 if (N1.getValueType() != MVT::i32) 6985 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 6986 if (N2.getValueType() != MVT::i32) 6987 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 6988 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 6989 } 6990 return SDValue(); 6991} 6992 6993SDValue 6994X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 6995 LLVMContext *Context = DAG.getContext(); 6996 DebugLoc dl = Op.getDebugLoc(); 6997 EVT OpVT = Op.getValueType(); 6998 6999 // If this is a 256-bit vector result, first insert into a 128-bit 7000 // vector and then insert into the 256-bit vector. 7001 if (OpVT.getSizeInBits() > 128) { 7002 // Insert into a 128-bit vector. 7003 EVT VT128 = EVT::getVectorVT(*Context, 7004 OpVT.getVectorElementType(), 7005 OpVT.getVectorNumElements() / 2); 7006 7007 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7008 7009 // Insert the 128-bit vector. 7010 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7011 DAG.getConstant(0, MVT::i32), 7012 DAG, dl); 7013 } 7014 7015 if (Op.getValueType() == MVT::v1i64 && 7016 Op.getOperand(0).getValueType() == MVT::i64) 7017 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7018 7019 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7020 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7021 "Expected an SSE type!"); 7022 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7023 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7024} 7025 7026// Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7027// a simple subregister reference or explicit instructions to grab 7028// upper bits of a vector. 7029SDValue 7030X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7031 if (Subtarget->hasAVX()) { 7032 DebugLoc dl = Op.getNode()->getDebugLoc(); 7033 SDValue Vec = Op.getNode()->getOperand(0); 7034 SDValue Idx = Op.getNode()->getOperand(1); 7035 7036 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7037 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7038 return Extract128BitVector(Vec, Idx, DAG, dl); 7039 } 7040 } 7041 return SDValue(); 7042} 7043 7044// Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7045// simple superregister reference or explicit instructions to insert 7046// the upper bits of a vector. 7047SDValue 7048X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7049 if (Subtarget->hasAVX()) { 7050 DebugLoc dl = Op.getNode()->getDebugLoc(); 7051 SDValue Vec = Op.getNode()->getOperand(0); 7052 SDValue SubVec = Op.getNode()->getOperand(1); 7053 SDValue Idx = Op.getNode()->getOperand(2); 7054 7055 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7056 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7057 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7058 } 7059 } 7060 return SDValue(); 7061} 7062 7063// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7064// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7065// one of the above mentioned nodes. It has to be wrapped because otherwise 7066// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7067// be used to form addressing mode. These wrapped nodes will be selected 7068// into MOV32ri. 7069SDValue 7070X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7071 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7072 7073 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7074 // global base reg. 7075 unsigned char OpFlag = 0; 7076 unsigned WrapperKind = X86ISD::Wrapper; 7077 CodeModel::Model M = getTargetMachine().getCodeModel(); 7078 7079 if (Subtarget->isPICStyleRIPRel() && 7080 (M == CodeModel::Small || M == CodeModel::Kernel)) 7081 WrapperKind = X86ISD::WrapperRIP; 7082 else if (Subtarget->isPICStyleGOT()) 7083 OpFlag = X86II::MO_GOTOFF; 7084 else if (Subtarget->isPICStyleStubPIC()) 7085 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7086 7087 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7088 CP->getAlignment(), 7089 CP->getOffset(), OpFlag); 7090 DebugLoc DL = CP->getDebugLoc(); 7091 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7092 // With PIC, the address is actually $g + Offset. 7093 if (OpFlag) { 7094 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7095 DAG.getNode(X86ISD::GlobalBaseReg, 7096 DebugLoc(), getPointerTy()), 7097 Result); 7098 } 7099 7100 return Result; 7101} 7102 7103SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7104 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7105 7106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7107 // global base reg. 7108 unsigned char OpFlag = 0; 7109 unsigned WrapperKind = X86ISD::Wrapper; 7110 CodeModel::Model M = getTargetMachine().getCodeModel(); 7111 7112 if (Subtarget->isPICStyleRIPRel() && 7113 (M == CodeModel::Small || M == CodeModel::Kernel)) 7114 WrapperKind = X86ISD::WrapperRIP; 7115 else if (Subtarget->isPICStyleGOT()) 7116 OpFlag = X86II::MO_GOTOFF; 7117 else if (Subtarget->isPICStyleStubPIC()) 7118 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7119 7120 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7121 OpFlag); 7122 DebugLoc DL = JT->getDebugLoc(); 7123 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7124 7125 // With PIC, the address is actually $g + Offset. 7126 if (OpFlag) 7127 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7128 DAG.getNode(X86ISD::GlobalBaseReg, 7129 DebugLoc(), getPointerTy()), 7130 Result); 7131 7132 return Result; 7133} 7134 7135SDValue 7136X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7137 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7138 7139 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7140 // global base reg. 7141 unsigned char OpFlag = 0; 7142 unsigned WrapperKind = X86ISD::Wrapper; 7143 CodeModel::Model M = getTargetMachine().getCodeModel(); 7144 7145 if (Subtarget->isPICStyleRIPRel() && 7146 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7147 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7148 OpFlag = X86II::MO_GOTPCREL; 7149 WrapperKind = X86ISD::WrapperRIP; 7150 } else if (Subtarget->isPICStyleGOT()) { 7151 OpFlag = X86II::MO_GOT; 7152 } else if (Subtarget->isPICStyleStubPIC()) { 7153 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7154 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7155 OpFlag = X86II::MO_DARWIN_NONLAZY; 7156 } 7157 7158 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7159 7160 DebugLoc DL = Op.getDebugLoc(); 7161 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7162 7163 7164 // With PIC, the address is actually $g + Offset. 7165 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7166 !Subtarget->is64Bit()) { 7167 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7168 DAG.getNode(X86ISD::GlobalBaseReg, 7169 DebugLoc(), getPointerTy()), 7170 Result); 7171 } 7172 7173 // For symbols that require a load from a stub to get the address, emit the 7174 // load. 7175 if (isGlobalStubReference(OpFlag)) 7176 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7177 MachinePointerInfo::getGOT(), false, false, false, 0); 7178 7179 return Result; 7180} 7181 7182SDValue 7183X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7184 // Create the TargetBlockAddressAddress node. 7185 unsigned char OpFlags = 7186 Subtarget->ClassifyBlockAddressReference(); 7187 CodeModel::Model M = getTargetMachine().getCodeModel(); 7188 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7189 DebugLoc dl = Op.getDebugLoc(); 7190 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7191 /*isTarget=*/true, OpFlags); 7192 7193 if (Subtarget->isPICStyleRIPRel() && 7194 (M == CodeModel::Small || M == CodeModel::Kernel)) 7195 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7196 else 7197 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7198 7199 // With PIC, the address is actually $g + Offset. 7200 if (isGlobalRelativeToPICBase(OpFlags)) { 7201 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7202 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7203 Result); 7204 } 7205 7206 return Result; 7207} 7208 7209SDValue 7210X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7211 int64_t Offset, 7212 SelectionDAG &DAG) const { 7213 // Create the TargetGlobalAddress node, folding in the constant 7214 // offset if it is legal. 7215 unsigned char OpFlags = 7216 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7217 CodeModel::Model M = getTargetMachine().getCodeModel(); 7218 SDValue Result; 7219 if (OpFlags == X86II::MO_NO_FLAG && 7220 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7221 // A direct static reference to a global. 7222 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7223 Offset = 0; 7224 } else { 7225 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7226 } 7227 7228 if (Subtarget->isPICStyleRIPRel() && 7229 (M == CodeModel::Small || M == CodeModel::Kernel)) 7230 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7231 else 7232 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7233 7234 // With PIC, the address is actually $g + Offset. 7235 if (isGlobalRelativeToPICBase(OpFlags)) { 7236 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7237 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7238 Result); 7239 } 7240 7241 // For globals that require a load from a stub to get the address, emit the 7242 // load. 7243 if (isGlobalStubReference(OpFlags)) 7244 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7245 MachinePointerInfo::getGOT(), false, false, false, 0); 7246 7247 // If there was a non-zero offset that we didn't fold, create an explicit 7248 // addition for it. 7249 if (Offset != 0) 7250 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7251 DAG.getConstant(Offset, getPointerTy())); 7252 7253 return Result; 7254} 7255 7256SDValue 7257X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7258 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7259 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7260 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7261} 7262 7263static SDValue 7264GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7265 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7266 unsigned char OperandFlags) { 7267 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7268 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7269 DebugLoc dl = GA->getDebugLoc(); 7270 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7271 GA->getValueType(0), 7272 GA->getOffset(), 7273 OperandFlags); 7274 if (InFlag) { 7275 SDValue Ops[] = { Chain, TGA, *InFlag }; 7276 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7277 } else { 7278 SDValue Ops[] = { Chain, TGA }; 7279 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7280 } 7281 7282 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7283 MFI->setAdjustsStack(true); 7284 7285 SDValue Flag = Chain.getValue(1); 7286 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7287} 7288 7289// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7290static SDValue 7291LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7292 const EVT PtrVT) { 7293 SDValue InFlag; 7294 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7295 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7296 DAG.getNode(X86ISD::GlobalBaseReg, 7297 DebugLoc(), PtrVT), InFlag); 7298 InFlag = Chain.getValue(1); 7299 7300 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7301} 7302 7303// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7304static SDValue 7305LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7306 const EVT PtrVT) { 7307 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7308 X86::RAX, X86II::MO_TLSGD); 7309} 7310 7311// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7312// "local exec" model. 7313static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7314 const EVT PtrVT, TLSModel::Model model, 7315 bool is64Bit) { 7316 DebugLoc dl = GA->getDebugLoc(); 7317 7318 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7319 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7320 is64Bit ? 257 : 256)); 7321 7322 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7323 DAG.getIntPtrConstant(0), 7324 MachinePointerInfo(Ptr), 7325 false, false, false, 0); 7326 7327 unsigned char OperandFlags = 0; 7328 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7329 // initialexec. 7330 unsigned WrapperKind = X86ISD::Wrapper; 7331 if (model == TLSModel::LocalExec) { 7332 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7333 } else if (is64Bit) { 7334 assert(model == TLSModel::InitialExec); 7335 OperandFlags = X86II::MO_GOTTPOFF; 7336 WrapperKind = X86ISD::WrapperRIP; 7337 } else { 7338 assert(model == TLSModel::InitialExec); 7339 OperandFlags = X86II::MO_INDNTPOFF; 7340 } 7341 7342 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7343 // exec) 7344 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7345 GA->getValueType(0), 7346 GA->getOffset(), OperandFlags); 7347 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7348 7349 if (model == TLSModel::InitialExec) 7350 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7351 MachinePointerInfo::getGOT(), false, false, false, 0); 7352 7353 // The address of the thread local variable is the add of the thread 7354 // pointer with the offset of the variable. 7355 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7356} 7357 7358SDValue 7359X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7360 7361 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7362 const GlobalValue *GV = GA->getGlobal(); 7363 7364 if (Subtarget->isTargetELF()) { 7365 // TODO: implement the "local dynamic" model 7366 // TODO: implement the "initial exec"model for pic executables 7367 7368 // If GV is an alias then use the aliasee for determining 7369 // thread-localness. 7370 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7371 GV = GA->resolveAliasedGlobal(false); 7372 7373 TLSModel::Model model 7374 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7375 7376 switch (model) { 7377 case TLSModel::GeneralDynamic: 7378 case TLSModel::LocalDynamic: // not implemented 7379 if (Subtarget->is64Bit()) 7380 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7381 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7382 7383 case TLSModel::InitialExec: 7384 case TLSModel::LocalExec: 7385 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7386 Subtarget->is64Bit()); 7387 } 7388 } else if (Subtarget->isTargetDarwin()) { 7389 // Darwin only has one model of TLS. Lower to that. 7390 unsigned char OpFlag = 0; 7391 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7392 X86ISD::WrapperRIP : X86ISD::Wrapper; 7393 7394 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7395 // global base reg. 7396 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7397 !Subtarget->is64Bit(); 7398 if (PIC32) 7399 OpFlag = X86II::MO_TLVP_PIC_BASE; 7400 else 7401 OpFlag = X86II::MO_TLVP; 7402 DebugLoc DL = Op.getDebugLoc(); 7403 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7404 GA->getValueType(0), 7405 GA->getOffset(), OpFlag); 7406 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7407 7408 // With PIC32, the address is actually $g + Offset. 7409 if (PIC32) 7410 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7411 DAG.getNode(X86ISD::GlobalBaseReg, 7412 DebugLoc(), getPointerTy()), 7413 Offset); 7414 7415 // Lowering the machine isd will make sure everything is in the right 7416 // location. 7417 SDValue Chain = DAG.getEntryNode(); 7418 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7419 SDValue Args[] = { Chain, Offset }; 7420 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7421 7422 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7423 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7424 MFI->setAdjustsStack(true); 7425 7426 // And our return value (tls address) is in the standard call return value 7427 // location. 7428 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7429 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(), 7430 Chain.getValue(1)); 7431 } 7432 7433 llvm_unreachable("TLS not implemented for this target."); 7434} 7435 7436 7437/// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values 7438/// and take a 2 x i32 value to shift plus a shift amount. 7439SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{ 7440 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7441 EVT VT = Op.getValueType(); 7442 unsigned VTBits = VT.getSizeInBits(); 7443 DebugLoc dl = Op.getDebugLoc(); 7444 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7445 SDValue ShOpLo = Op.getOperand(0); 7446 SDValue ShOpHi = Op.getOperand(1); 7447 SDValue ShAmt = Op.getOperand(2); 7448 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7449 DAG.getConstant(VTBits - 1, MVT::i8)) 7450 : DAG.getConstant(0, VT); 7451 7452 SDValue Tmp2, Tmp3; 7453 if (Op.getOpcode() == ISD::SHL_PARTS) { 7454 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7455 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7456 } else { 7457 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7458 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7459 } 7460 7461 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7462 DAG.getConstant(VTBits, MVT::i8)); 7463 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7464 AndNode, DAG.getConstant(0, MVT::i8)); 7465 7466 SDValue Hi, Lo; 7467 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7468 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7469 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7470 7471 if (Op.getOpcode() == ISD::SHL_PARTS) { 7472 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7473 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7474 } else { 7475 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7476 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7477 } 7478 7479 SDValue Ops[2] = { Lo, Hi }; 7480 return DAG.getMergeValues(Ops, 2, dl); 7481} 7482 7483SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7484 SelectionDAG &DAG) const { 7485 EVT SrcVT = Op.getOperand(0).getValueType(); 7486 7487 if (SrcVT.isVector()) 7488 return SDValue(); 7489 7490 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7491 "Unknown SINT_TO_FP to lower!"); 7492 7493 // These are really Legal; return the operand so the caller accepts it as 7494 // Legal. 7495 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7496 return Op; 7497 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7498 Subtarget->is64Bit()) { 7499 return Op; 7500 } 7501 7502 DebugLoc dl = Op.getDebugLoc(); 7503 unsigned Size = SrcVT.getSizeInBits()/8; 7504 MachineFunction &MF = DAG.getMachineFunction(); 7505 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7506 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7507 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7508 StackSlot, 7509 MachinePointerInfo::getFixedStack(SSFI), 7510 false, false, 0); 7511 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7512} 7513 7514SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7515 SDValue StackSlot, 7516 SelectionDAG &DAG) const { 7517 // Build the FILD 7518 DebugLoc DL = Op.getDebugLoc(); 7519 SDVTList Tys; 7520 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7521 if (useSSE) 7522 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7523 else 7524 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7525 7526 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7527 7528 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7529 MachineMemOperand *MMO; 7530 if (FI) { 7531 int SSFI = FI->getIndex(); 7532 MMO = 7533 DAG.getMachineFunction() 7534 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7535 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7536 } else { 7537 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7538 StackSlot = StackSlot.getOperand(1); 7539 } 7540 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7541 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7542 X86ISD::FILD, DL, 7543 Tys, Ops, array_lengthof(Ops), 7544 SrcVT, MMO); 7545 7546 if (useSSE) { 7547 Chain = Result.getValue(1); 7548 SDValue InFlag = Result.getValue(2); 7549 7550 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7551 // shouldn't be necessary except that RFP cannot be live across 7552 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7553 MachineFunction &MF = DAG.getMachineFunction(); 7554 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7555 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7556 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7557 Tys = DAG.getVTList(MVT::Other); 7558 SDValue Ops[] = { 7559 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7560 }; 7561 MachineMemOperand *MMO = 7562 DAG.getMachineFunction() 7563 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7564 MachineMemOperand::MOStore, SSFISize, SSFISize); 7565 7566 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7567 Ops, array_lengthof(Ops), 7568 Op.getValueType(), MMO); 7569 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7570 MachinePointerInfo::getFixedStack(SSFI), 7571 false, false, false, 0); 7572 } 7573 7574 return Result; 7575} 7576 7577// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7578SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7579 SelectionDAG &DAG) const { 7580 // This algorithm is not obvious. Here it is what we're trying to output: 7581 /* 7582 movq %rax, %xmm0 7583 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } 7584 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } 7585 #ifdef __SSE3__ 7586 haddpd %xmm0, %xmm0 7587 #else 7588 pshufd $0x4e, %xmm0, %xmm1 7589 addpd %xmm1, %xmm0 7590 #endif 7591 */ 7592 7593 DebugLoc dl = Op.getDebugLoc(); 7594 LLVMContext *Context = DAG.getContext(); 7595 7596 // Build some magic constants. 7597 SmallVector<Constant*,4> CV0; 7598 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7599 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7600 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7601 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7602 Constant *C0 = ConstantVector::get(CV0); 7603 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7604 7605 SmallVector<Constant*,2> CV1; 7606 CV1.push_back( 7607 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7608 CV1.push_back( 7609 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7610 Constant *C1 = ConstantVector::get(CV1); 7611 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7612 7613 // Load the 64-bit value into an XMM register. 7614 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 7615 Op.getOperand(0)); 7616 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7617 MachinePointerInfo::getConstantPool(), 7618 false, false, false, 16); 7619 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, 7620 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1), 7621 CLod0); 7622 7623 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7624 MachinePointerInfo::getConstantPool(), 7625 false, false, false, 16); 7626 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1); 7627 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7628 SDValue Result; 7629 7630 if (Subtarget->hasSSE3()) { 7631 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'. 7632 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub); 7633 } else { 7634 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub); 7635 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32, 7636 S2F, 0x4E, DAG); 7637 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64, 7638 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle), 7639 Sub); 7640 } 7641 7642 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result, 7643 DAG.getIntPtrConstant(0)); 7644} 7645 7646// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7647SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7648 SelectionDAG &DAG) const { 7649 DebugLoc dl = Op.getDebugLoc(); 7650 // FP constant to bias correct the final result. 7651 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7652 MVT::f64); 7653 7654 // Load the 32-bit value into an XMM register. 7655 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7656 Op.getOperand(0)); 7657 7658 // Zero out the upper parts of the register. 7659 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG); 7660 7661 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7662 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7663 DAG.getIntPtrConstant(0)); 7664 7665 // Or the load with the bias. 7666 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7667 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7668 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7669 MVT::v2f64, Load)), 7670 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7671 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7672 MVT::v2f64, Bias))); 7673 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7675 DAG.getIntPtrConstant(0)); 7676 7677 // Subtract the bias. 7678 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7679 7680 // Handle final rounding. 7681 EVT DestVT = Op.getValueType(); 7682 7683 if (DestVT.bitsLT(MVT::f64)) { 7684 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7685 DAG.getIntPtrConstant(0)); 7686 } else if (DestVT.bitsGT(MVT::f64)) { 7687 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7688 } 7689 7690 // Handle final rounding. 7691 return Sub; 7692} 7693 7694SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7695 SelectionDAG &DAG) const { 7696 SDValue N0 = Op.getOperand(0); 7697 DebugLoc dl = Op.getDebugLoc(); 7698 7699 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7700 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7701 // the optimization here. 7702 if (DAG.SignBitIsZero(N0)) 7703 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7704 7705 EVT SrcVT = N0.getValueType(); 7706 EVT DstVT = Op.getValueType(); 7707 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7708 return LowerUINT_TO_FP_i64(Op, DAG); 7709 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7710 return LowerUINT_TO_FP_i32(Op, DAG); 7711 else if (Subtarget->is64Bit() && 7712 SrcVT == MVT::i64 && DstVT == MVT::f32) 7713 return SDValue(); 7714 7715 // Make a 64-bit buffer, and use it to build an FILD. 7716 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7717 if (SrcVT == MVT::i32) { 7718 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7719 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7720 getPointerTy(), StackSlot, WordOff); 7721 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7722 StackSlot, MachinePointerInfo(), 7723 false, false, 0); 7724 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7725 OffsetSlot, MachinePointerInfo(), 7726 false, false, 0); 7727 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7728 return Fild; 7729 } 7730 7731 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7732 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7733 StackSlot, MachinePointerInfo(), 7734 false, false, 0); 7735 // For i64 source, we need to add the appropriate power of 2 if the input 7736 // was negative. This is the same as the optimization in 7737 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7738 // we must be careful to do the computation in x87 extended precision, not 7739 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7740 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7741 MachineMemOperand *MMO = 7742 DAG.getMachineFunction() 7743 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7744 MachineMemOperand::MOLoad, 8, 8); 7745 7746 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7747 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7748 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7749 MVT::i64, MMO); 7750 7751 APInt FF(32, 0x5F800000ULL); 7752 7753 // Check whether the sign bit is set. 7754 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7755 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7756 ISD::SETLT); 7757 7758 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7759 SDValue FudgePtr = DAG.getConstantPool( 7760 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7761 getPointerTy()); 7762 7763 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7764 SDValue Zero = DAG.getIntPtrConstant(0); 7765 SDValue Four = DAG.getIntPtrConstant(4); 7766 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7767 Zero, Four); 7768 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7769 7770 // Load the value out, extending it from f32 to f80. 7771 // FIXME: Avoid the extend by constructing the right constant pool? 7772 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7773 FudgePtr, MachinePointerInfo::getConstantPool(), 7774 MVT::f32, false, false, 4); 7775 // Extend everything to 80 bits to force it to be done on x87. 7776 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7777 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7778} 7779 7780std::pair<SDValue,SDValue> X86TargetLowering:: 7781FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7782 DebugLoc DL = Op.getDebugLoc(); 7783 7784 EVT DstTy = Op.getValueType(); 7785 7786 if (!IsSigned) { 7787 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7788 DstTy = MVT::i64; 7789 } 7790 7791 assert(DstTy.getSimpleVT() <= MVT::i64 && 7792 DstTy.getSimpleVT() >= MVT::i16 && 7793 "Unknown FP_TO_SINT to lower!"); 7794 7795 // These are really Legal. 7796 if (DstTy == MVT::i32 && 7797 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7798 return std::make_pair(SDValue(), SDValue()); 7799 if (Subtarget->is64Bit() && 7800 DstTy == MVT::i64 && 7801 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7802 return std::make_pair(SDValue(), SDValue()); 7803 7804 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7805 // stack slot. 7806 MachineFunction &MF = DAG.getMachineFunction(); 7807 unsigned MemSize = DstTy.getSizeInBits()/8; 7808 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7809 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7810 7811 7812 7813 unsigned Opc; 7814 switch (DstTy.getSimpleVT().SimpleTy) { 7815 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7816 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7817 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7818 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7819 } 7820 7821 SDValue Chain = DAG.getEntryNode(); 7822 SDValue Value = Op.getOperand(0); 7823 EVT TheVT = Op.getOperand(0).getValueType(); 7824 if (isScalarFPTypeInSSEReg(TheVT)) { 7825 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7826 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7827 MachinePointerInfo::getFixedStack(SSFI), 7828 false, false, 0); 7829 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7830 SDValue Ops[] = { 7831 Chain, StackSlot, DAG.getValueType(TheVT) 7832 }; 7833 7834 MachineMemOperand *MMO = 7835 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7836 MachineMemOperand::MOLoad, MemSize, MemSize); 7837 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7838 DstTy, MMO); 7839 Chain = Value.getValue(1); 7840 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7841 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7842 } 7843 7844 MachineMemOperand *MMO = 7845 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7846 MachineMemOperand::MOStore, MemSize, MemSize); 7847 7848 // Build the FP_TO_INT*_IN_MEM 7849 SDValue Ops[] = { Chain, Value, StackSlot }; 7850 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7851 Ops, 3, DstTy, MMO); 7852 7853 return std::make_pair(FIST, StackSlot); 7854} 7855 7856SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7857 SelectionDAG &DAG) const { 7858 if (Op.getValueType().isVector()) 7859 return SDValue(); 7860 7861 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7862 SDValue FIST = Vals.first, StackSlot = Vals.second; 7863 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7864 if (FIST.getNode() == 0) return Op; 7865 7866 // Load the result. 7867 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7868 FIST, StackSlot, MachinePointerInfo(), 7869 false, false, false, 0); 7870} 7871 7872SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7873 SelectionDAG &DAG) const { 7874 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7875 SDValue FIST = Vals.first, StackSlot = Vals.second; 7876 assert(FIST.getNode() && "Unexpected failure"); 7877 7878 // Load the result. 7879 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7880 FIST, StackSlot, MachinePointerInfo(), 7881 false, false, false, 0); 7882} 7883 7884SDValue X86TargetLowering::LowerFABS(SDValue Op, 7885 SelectionDAG &DAG) const { 7886 LLVMContext *Context = DAG.getContext(); 7887 DebugLoc dl = Op.getDebugLoc(); 7888 EVT VT = Op.getValueType(); 7889 EVT EltVT = VT; 7890 if (VT.isVector()) 7891 EltVT = VT.getVectorElementType(); 7892 SmallVector<Constant*,4> CV; 7893 if (EltVT == MVT::f64) { 7894 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 7895 CV.assign(2, C); 7896 } else { 7897 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 7898 CV.assign(4, C); 7899 } 7900 Constant *C = ConstantVector::get(CV); 7901 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7902 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7903 MachinePointerInfo::getConstantPool(), 7904 false, false, false, 16); 7905 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 7906} 7907 7908SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 7909 LLVMContext *Context = DAG.getContext(); 7910 DebugLoc dl = Op.getDebugLoc(); 7911 EVT VT = Op.getValueType(); 7912 EVT EltVT = VT; 7913 unsigned NumElts = VT == MVT::f64 ? 2 : 4; 7914 if (VT.isVector()) { 7915 EltVT = VT.getVectorElementType(); 7916 NumElts = VT.getVectorNumElements(); 7917 } 7918 SmallVector<Constant*,8> CV; 7919 if (EltVT == MVT::f64) { 7920 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 7921 CV.assign(NumElts, C); 7922 } else { 7923 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 7924 CV.assign(NumElts, C); 7925 } 7926 Constant *C = ConstantVector::get(CV); 7927 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7928 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 7929 MachinePointerInfo::getConstantPool(), 7930 false, false, false, 16); 7931 if (VT.isVector()) { 7932 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64; 7933 return DAG.getNode(ISD::BITCAST, dl, VT, 7934 DAG.getNode(ISD::XOR, dl, XORVT, 7935 DAG.getNode(ISD::BITCAST, dl, XORVT, 7936 Op.getOperand(0)), 7937 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask))); 7938 } else { 7939 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 7940 } 7941} 7942 7943SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 7944 LLVMContext *Context = DAG.getContext(); 7945 SDValue Op0 = Op.getOperand(0); 7946 SDValue Op1 = Op.getOperand(1); 7947 DebugLoc dl = Op.getDebugLoc(); 7948 EVT VT = Op.getValueType(); 7949 EVT SrcVT = Op1.getValueType(); 7950 7951 // If second operand is smaller, extend it first. 7952 if (SrcVT.bitsLT(VT)) { 7953 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 7954 SrcVT = VT; 7955 } 7956 // And if it is bigger, shrink it first. 7957 if (SrcVT.bitsGT(VT)) { 7958 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 7959 SrcVT = VT; 7960 } 7961 7962 // At this point the operands and the result should have the same 7963 // type, and that won't be f80 since that is not custom lowered. 7964 7965 // First get the sign bit of second operand. 7966 SmallVector<Constant*,4> CV; 7967 if (SrcVT == MVT::f64) { 7968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7970 } else { 7971 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 7972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7973 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7974 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 7975 } 7976 Constant *C = ConstantVector::get(CV); 7977 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 7978 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 7979 MachinePointerInfo::getConstantPool(), 7980 false, false, false, 16); 7981 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 7982 7983 // Shift sign bit right or left if the two operands have different types. 7984 if (SrcVT.bitsGT(VT)) { 7985 // Op0 is MVT::f32, Op1 is MVT::f64. 7986 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 7987 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 7988 DAG.getConstant(32, MVT::i32)); 7989 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 7990 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 7991 DAG.getIntPtrConstant(0)); 7992 } 7993 7994 // Clear first operand sign bit. 7995 CV.clear(); 7996 if (VT == MVT::f64) { 7997 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 7998 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 7999 } else { 8000 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8004 } 8005 C = ConstantVector::get(CV); 8006 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8007 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8008 MachinePointerInfo::getConstantPool(), 8009 false, false, false, 16); 8010 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8011 8012 // Or the value with the sign bit. 8013 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8014} 8015 8016SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8017 SDValue N0 = Op.getOperand(0); 8018 DebugLoc dl = Op.getDebugLoc(); 8019 EVT VT = Op.getValueType(); 8020 8021 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8022 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8023 DAG.getConstant(1, VT)); 8024 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8025} 8026 8027/// Emit nodes that will be selected as "test Op0,Op0", or something 8028/// equivalent. 8029SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8030 SelectionDAG &DAG) const { 8031 DebugLoc dl = Op.getDebugLoc(); 8032 8033 // CF and OF aren't always set the way we want. Determine which 8034 // of these we need. 8035 bool NeedCF = false; 8036 bool NeedOF = false; 8037 switch (X86CC) { 8038 default: break; 8039 case X86::COND_A: case X86::COND_AE: 8040 case X86::COND_B: case X86::COND_BE: 8041 NeedCF = true; 8042 break; 8043 case X86::COND_G: case X86::COND_GE: 8044 case X86::COND_L: case X86::COND_LE: 8045 case X86::COND_O: case X86::COND_NO: 8046 NeedOF = true; 8047 break; 8048 } 8049 8050 // See if we can use the EFLAGS value from the operand instead of 8051 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8052 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8053 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8054 // Emit a CMP with 0, which is the TEST pattern. 8055 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8056 DAG.getConstant(0, Op.getValueType())); 8057 8058 unsigned Opcode = 0; 8059 unsigned NumOperands = 0; 8060 switch (Op.getNode()->getOpcode()) { 8061 case ISD::ADD: 8062 // Due to an isel shortcoming, be conservative if this add is likely to be 8063 // selected as part of a load-modify-store instruction. When the root node 8064 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8065 // uses of other nodes in the match, such as the ADD in this case. This 8066 // leads to the ADD being left around and reselected, with the result being 8067 // two adds in the output. Alas, even if none our users are stores, that 8068 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8069 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8070 // climbing the DAG back to the root, and it doesn't seem to be worth the 8071 // effort. 8072 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8073 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8074 if (UI->getOpcode() != ISD::CopyToReg && 8075 UI->getOpcode() != ISD::SETCC && 8076 UI->getOpcode() != ISD::STORE) 8077 goto default_case; 8078 8079 if (ConstantSDNode *C = 8080 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8081 // An add of one will be selected as an INC. 8082 if (C->getAPIntValue() == 1) { 8083 Opcode = X86ISD::INC; 8084 NumOperands = 1; 8085 break; 8086 } 8087 8088 // An add of negative one (subtract of one) will be selected as a DEC. 8089 if (C->getAPIntValue().isAllOnesValue()) { 8090 Opcode = X86ISD::DEC; 8091 NumOperands = 1; 8092 break; 8093 } 8094 } 8095 8096 // Otherwise use a regular EFLAGS-setting add. 8097 Opcode = X86ISD::ADD; 8098 NumOperands = 2; 8099 break; 8100 case ISD::AND: { 8101 // If the primary and result isn't used, don't bother using X86ISD::AND, 8102 // because a TEST instruction will be better. 8103 bool NonFlagUse = false; 8104 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8105 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8106 SDNode *User = *UI; 8107 unsigned UOpNo = UI.getOperandNo(); 8108 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8109 // Look pass truncate. 8110 UOpNo = User->use_begin().getOperandNo(); 8111 User = *User->use_begin(); 8112 } 8113 8114 if (User->getOpcode() != ISD::BRCOND && 8115 User->getOpcode() != ISD::SETCC && 8116 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8117 NonFlagUse = true; 8118 break; 8119 } 8120 } 8121 8122 if (!NonFlagUse) 8123 break; 8124 } 8125 // FALL THROUGH 8126 case ISD::SUB: 8127 case ISD::OR: 8128 case ISD::XOR: 8129 // Due to the ISEL shortcoming noted above, be conservative if this op is 8130 // likely to be selected as part of a load-modify-store instruction. 8131 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8132 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8133 if (UI->getOpcode() == ISD::STORE) 8134 goto default_case; 8135 8136 // Otherwise use a regular EFLAGS-setting instruction. 8137 switch (Op.getNode()->getOpcode()) { 8138 default: llvm_unreachable("unexpected operator!"); 8139 case ISD::SUB: Opcode = X86ISD::SUB; break; 8140 case ISD::OR: Opcode = X86ISD::OR; break; 8141 case ISD::XOR: Opcode = X86ISD::XOR; break; 8142 case ISD::AND: Opcode = X86ISD::AND; break; 8143 } 8144 8145 NumOperands = 2; 8146 break; 8147 case X86ISD::ADD: 8148 case X86ISD::SUB: 8149 case X86ISD::INC: 8150 case X86ISD::DEC: 8151 case X86ISD::OR: 8152 case X86ISD::XOR: 8153 case X86ISD::AND: 8154 return SDValue(Op.getNode(), 1); 8155 default: 8156 default_case: 8157 break; 8158 } 8159 8160 if (Opcode == 0) 8161 // Emit a CMP with 0, which is the TEST pattern. 8162 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8163 DAG.getConstant(0, Op.getValueType())); 8164 8165 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8166 SmallVector<SDValue, 4> Ops; 8167 for (unsigned i = 0; i != NumOperands; ++i) 8168 Ops.push_back(Op.getOperand(i)); 8169 8170 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8171 DAG.ReplaceAllUsesWith(Op, New); 8172 return SDValue(New.getNode(), 1); 8173} 8174 8175/// Emit nodes that will be selected as "cmp Op0,Op1", or something 8176/// equivalent. 8177SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8178 SelectionDAG &DAG) const { 8179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8180 if (C->getAPIntValue() == 0) 8181 return EmitTest(Op0, X86CC, DAG); 8182 8183 DebugLoc dl = Op0.getDebugLoc(); 8184 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8185} 8186 8187/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8188/// if it's possible. 8189SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8190 DebugLoc dl, SelectionDAG &DAG) const { 8191 SDValue Op0 = And.getOperand(0); 8192 SDValue Op1 = And.getOperand(1); 8193 if (Op0.getOpcode() == ISD::TRUNCATE) 8194 Op0 = Op0.getOperand(0); 8195 if (Op1.getOpcode() == ISD::TRUNCATE) 8196 Op1 = Op1.getOperand(0); 8197 8198 SDValue LHS, RHS; 8199 if (Op1.getOpcode() == ISD::SHL) 8200 std::swap(Op0, Op1); 8201 if (Op0.getOpcode() == ISD::SHL) { 8202 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8203 if (And00C->getZExtValue() == 1) { 8204 // If we looked past a truncate, check that it's only truncating away 8205 // known zeros. 8206 unsigned BitWidth = Op0.getValueSizeInBits(); 8207 unsigned AndBitWidth = And.getValueSizeInBits(); 8208 if (BitWidth > AndBitWidth) { 8209 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8210 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8211 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8212 return SDValue(); 8213 } 8214 LHS = Op1; 8215 RHS = Op0.getOperand(1); 8216 } 8217 } else if (Op1.getOpcode() == ISD::Constant) { 8218 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8219 uint64_t AndRHSVal = AndRHS->getZExtValue(); 8220 SDValue AndLHS = Op0; 8221 8222 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) { 8223 LHS = AndLHS.getOperand(0); 8224 RHS = AndLHS.getOperand(1); 8225 } 8226 8227 // Use BT if the immediate can't be encoded in a TEST instruction. 8228 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) { 8229 LHS = AndLHS; 8230 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType()); 8231 } 8232 } 8233 8234 if (LHS.getNode()) { 8235 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8236 // instruction. Since the shift amount is in-range-or-undefined, we know 8237 // that doing a bittest on the i32 value is ok. We extend to i32 because 8238 // the encoding for the i16 version is larger than the i32 version. 8239 // Also promote i16 to i32 for performance / code size reason. 8240 if (LHS.getValueType() == MVT::i8 || 8241 LHS.getValueType() == MVT::i16) 8242 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8243 8244 // If the operand types disagree, extend the shift amount to match. Since 8245 // BT ignores high bits (like shifts) we can use anyextend. 8246 if (LHS.getValueType() != RHS.getValueType()) 8247 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8248 8249 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8250 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8251 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8252 DAG.getConstant(Cond, MVT::i8), BT); 8253 } 8254 8255 return SDValue(); 8256} 8257 8258SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8259 8260 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8261 8262 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8263 SDValue Op0 = Op.getOperand(0); 8264 SDValue Op1 = Op.getOperand(1); 8265 DebugLoc dl = Op.getDebugLoc(); 8266 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8267 8268 // Optimize to BT if possible. 8269 // Lower (X & (1 << N)) == 0 to BT(X, N). 8270 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8271 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8272 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8273 Op1.getOpcode() == ISD::Constant && 8274 cast<ConstantSDNode>(Op1)->isNullValue() && 8275 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8276 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8277 if (NewSetCC.getNode()) 8278 return NewSetCC; 8279 } 8280 8281 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8282 // these. 8283 if (Op1.getOpcode() == ISD::Constant && 8284 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8285 cast<ConstantSDNode>(Op1)->isNullValue()) && 8286 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8287 8288 // If the input is a setcc, then reuse the input setcc or use a new one with 8289 // the inverted condition. 8290 if (Op0.getOpcode() == X86ISD::SETCC) { 8291 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8292 bool Invert = (CC == ISD::SETNE) ^ 8293 cast<ConstantSDNode>(Op1)->isNullValue(); 8294 if (!Invert) return Op0; 8295 8296 CCode = X86::GetOppositeBranchCondition(CCode); 8297 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8298 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8299 } 8300 } 8301 8302 bool isFP = Op1.getValueType().isFloatingPoint(); 8303 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8304 if (X86CC == X86::COND_INVALID) 8305 return SDValue(); 8306 8307 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8308 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8309 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8310} 8311 8312// Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8313// ones, and then concatenate the result back. 8314static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8315 EVT VT = Op.getValueType(); 8316 8317 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8318 "Unsupported value type for operation"); 8319 8320 int NumElems = VT.getVectorNumElements(); 8321 DebugLoc dl = Op.getDebugLoc(); 8322 SDValue CC = Op.getOperand(2); 8323 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8324 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8325 8326 // Extract the LHS vectors 8327 SDValue LHS = Op.getOperand(0); 8328 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8329 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8330 8331 // Extract the RHS vectors 8332 SDValue RHS = Op.getOperand(1); 8333 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8334 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8335 8336 // Issue the operation on the smaller types and concatenate the result back 8337 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8338 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8339 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8340 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8341 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8342} 8343 8344 8345SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8346 SDValue Cond; 8347 SDValue Op0 = Op.getOperand(0); 8348 SDValue Op1 = Op.getOperand(1); 8349 SDValue CC = Op.getOperand(2); 8350 EVT VT = Op.getValueType(); 8351 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8352 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8353 DebugLoc dl = Op.getDebugLoc(); 8354 8355 if (isFP) { 8356 unsigned SSECC = 8; 8357 EVT EltVT = Op0.getValueType().getVectorElementType(); 8358 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8359 8360 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8361 bool Swap = false; 8362 8363 // SSE Condition code mapping: 8364 // 0 - EQ 8365 // 1 - LT 8366 // 2 - LE 8367 // 3 - UNORD 8368 // 4 - NEQ 8369 // 5 - NLT 8370 // 6 - NLE 8371 // 7 - ORD 8372 switch (SetCCOpcode) { 8373 default: break; 8374 case ISD::SETOEQ: 8375 case ISD::SETEQ: SSECC = 0; break; 8376 case ISD::SETOGT: 8377 case ISD::SETGT: Swap = true; // Fallthrough 8378 case ISD::SETLT: 8379 case ISD::SETOLT: SSECC = 1; break; 8380 case ISD::SETOGE: 8381 case ISD::SETGE: Swap = true; // Fallthrough 8382 case ISD::SETLE: 8383 case ISD::SETOLE: SSECC = 2; break; 8384 case ISD::SETUO: SSECC = 3; break; 8385 case ISD::SETUNE: 8386 case ISD::SETNE: SSECC = 4; break; 8387 case ISD::SETULE: Swap = true; 8388 case ISD::SETUGE: SSECC = 5; break; 8389 case ISD::SETULT: Swap = true; 8390 case ISD::SETUGT: SSECC = 6; break; 8391 case ISD::SETO: SSECC = 7; break; 8392 } 8393 if (Swap) 8394 std::swap(Op0, Op1); 8395 8396 // In the two special cases we can't handle, emit two comparisons. 8397 if (SSECC == 8) { 8398 if (SetCCOpcode == ISD::SETUEQ) { 8399 SDValue UNORD, EQ; 8400 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8401 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8402 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8403 } else if (SetCCOpcode == ISD::SETONE) { 8404 SDValue ORD, NEQ; 8405 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8406 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8407 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8408 } 8409 llvm_unreachable("Illegal FP comparison"); 8410 } 8411 // Handle all other FP comparisons here. 8412 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8413 } 8414 8415 // Break 256-bit integer vector compare into smaller ones. 8416 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 8417 return Lower256IntVSETCC(Op, DAG); 8418 8419 // We are handling one of the integer comparisons here. Since SSE only has 8420 // GT and EQ comparisons for integer, swapping operands and multiple 8421 // operations may be required for some comparisons. 8422 unsigned Opc = 0; 8423 bool Swap = false, Invert = false, FlipSigns = false; 8424 8425 switch (SetCCOpcode) { 8426 default: break; 8427 case ISD::SETNE: Invert = true; 8428 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break; 8429 case ISD::SETLT: Swap = true; 8430 case ISD::SETGT: Opc = X86ISD::PCMPGT; break; 8431 case ISD::SETGE: Swap = true; 8432 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break; 8433 case ISD::SETULT: Swap = true; 8434 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break; 8435 case ISD::SETUGE: Swap = true; 8436 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break; 8437 } 8438 if (Swap) 8439 std::swap(Op0, Op1); 8440 8441 // Check that the operation in question is available (most are plain SSE2, 8442 // but PCMPGTQ and PCMPEQQ have different requirements). 8443 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42()) 8444 return SDValue(); 8445 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41()) 8446 return SDValue(); 8447 8448 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8449 // bits of the inputs before performing those operations. 8450 if (FlipSigns) { 8451 EVT EltVT = VT.getVectorElementType(); 8452 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8453 EltVT); 8454 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8455 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8456 SignBits.size()); 8457 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8458 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8459 } 8460 8461 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8462 8463 // If the logical-not of the result is required, perform that now. 8464 if (Invert) 8465 Result = DAG.getNOT(dl, Result, VT); 8466 8467 return Result; 8468} 8469 8470// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8471static bool isX86LogicalCmp(SDValue Op) { 8472 unsigned Opc = Op.getNode()->getOpcode(); 8473 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8474 return true; 8475 if (Op.getResNo() == 1 && 8476 (Opc == X86ISD::ADD || 8477 Opc == X86ISD::SUB || 8478 Opc == X86ISD::ADC || 8479 Opc == X86ISD::SBB || 8480 Opc == X86ISD::SMUL || 8481 Opc == X86ISD::UMUL || 8482 Opc == X86ISD::INC || 8483 Opc == X86ISD::DEC || 8484 Opc == X86ISD::OR || 8485 Opc == X86ISD::XOR || 8486 Opc == X86ISD::AND)) 8487 return true; 8488 8489 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8490 return true; 8491 8492 return false; 8493} 8494 8495static bool isZero(SDValue V) { 8496 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8497 return C && C->isNullValue(); 8498} 8499 8500static bool isAllOnes(SDValue V) { 8501 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8502 return C && C->isAllOnesValue(); 8503} 8504 8505SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8506 bool addTest = true; 8507 SDValue Cond = Op.getOperand(0); 8508 SDValue Op1 = Op.getOperand(1); 8509 SDValue Op2 = Op.getOperand(2); 8510 DebugLoc DL = Op.getDebugLoc(); 8511 SDValue CC; 8512 8513 if (Cond.getOpcode() == ISD::SETCC) { 8514 SDValue NewCond = LowerSETCC(Cond, DAG); 8515 if (NewCond.getNode()) 8516 Cond = NewCond; 8517 } 8518 8519 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8520 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8521 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8522 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8523 if (Cond.getOpcode() == X86ISD::SETCC && 8524 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8525 isZero(Cond.getOperand(1).getOperand(1))) { 8526 SDValue Cmp = Cond.getOperand(1); 8527 8528 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8529 8530 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8531 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8532 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8533 8534 SDValue CmpOp0 = Cmp.getOperand(0); 8535 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8536 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8537 8538 SDValue Res = // Res = 0 or -1. 8539 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8540 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8541 8542 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8543 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8544 8545 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8546 if (N2C == 0 || !N2C->isNullValue()) 8547 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8548 return Res; 8549 } 8550 } 8551 8552 // Look past (and (setcc_carry (cmp ...)), 1). 8553 if (Cond.getOpcode() == ISD::AND && 8554 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8556 if (C && C->getAPIntValue() == 1) 8557 Cond = Cond.getOperand(0); 8558 } 8559 8560 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8561 // setting operand in place of the X86ISD::SETCC. 8562 unsigned CondOpcode = Cond.getOpcode(); 8563 if (CondOpcode == X86ISD::SETCC || 8564 CondOpcode == X86ISD::SETCC_CARRY) { 8565 CC = Cond.getOperand(0); 8566 8567 SDValue Cmp = Cond.getOperand(1); 8568 unsigned Opc = Cmp.getOpcode(); 8569 EVT VT = Op.getValueType(); 8570 8571 bool IllegalFPCMov = false; 8572 if (VT.isFloatingPoint() && !VT.isVector() && 8573 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8574 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8575 8576 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8577 Opc == X86ISD::BT) { // FIXME 8578 Cond = Cmp; 8579 addTest = false; 8580 } 8581 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8582 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8583 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8584 Cond.getOperand(0).getValueType() != MVT::i8)) { 8585 SDValue LHS = Cond.getOperand(0); 8586 SDValue RHS = Cond.getOperand(1); 8587 unsigned X86Opcode; 8588 unsigned X86Cond; 8589 SDVTList VTs; 8590 switch (CondOpcode) { 8591 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8592 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8593 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8594 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8595 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8596 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8597 default: llvm_unreachable("unexpected overflowing operator"); 8598 } 8599 if (CondOpcode == ISD::UMULO) 8600 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8601 MVT::i32); 8602 else 8603 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8604 8605 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS); 8606 8607 if (CondOpcode == ISD::UMULO) 8608 Cond = X86Op.getValue(2); 8609 else 8610 Cond = X86Op.getValue(1); 8611 8612 CC = DAG.getConstant(X86Cond, MVT::i8); 8613 addTest = false; 8614 } 8615 8616 if (addTest) { 8617 // Look pass the truncate. 8618 if (Cond.getOpcode() == ISD::TRUNCATE) 8619 Cond = Cond.getOperand(0); 8620 8621 // We know the result of AND is compared against zero. Try to match 8622 // it to BT. 8623 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8624 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8625 if (NewSetCC.getNode()) { 8626 CC = NewSetCC.getOperand(0); 8627 Cond = NewSetCC.getOperand(1); 8628 addTest = false; 8629 } 8630 } 8631 } 8632 8633 if (addTest) { 8634 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8635 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8636 } 8637 8638 // a < b ? -1 : 0 -> RES = ~setcc_carry 8639 // a < b ? 0 : -1 -> RES = setcc_carry 8640 // a >= b ? -1 : 0 -> RES = setcc_carry 8641 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8642 if (Cond.getOpcode() == X86ISD::CMP) { 8643 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8644 8645 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8646 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8647 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8648 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8649 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8650 return DAG.getNOT(DL, Res, Res.getValueType()); 8651 return Res; 8652 } 8653 } 8654 8655 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8656 // condition is true. 8657 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8658 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8659 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8660} 8661 8662// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8663// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8664// from the AND / OR. 8665static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8666 Opc = Op.getOpcode(); 8667 if (Opc != ISD::OR && Opc != ISD::AND) 8668 return false; 8669 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8670 Op.getOperand(0).hasOneUse() && 8671 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8672 Op.getOperand(1).hasOneUse()); 8673} 8674 8675// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8676// 1 and that the SETCC node has a single use. 8677static bool isXor1OfSetCC(SDValue Op) { 8678 if (Op.getOpcode() != ISD::XOR) 8679 return false; 8680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8681 if (N1C && N1C->getAPIntValue() == 1) { 8682 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8683 Op.getOperand(0).hasOneUse(); 8684 } 8685 return false; 8686} 8687 8688SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8689 bool addTest = true; 8690 SDValue Chain = Op.getOperand(0); 8691 SDValue Cond = Op.getOperand(1); 8692 SDValue Dest = Op.getOperand(2); 8693 DebugLoc dl = Op.getDebugLoc(); 8694 SDValue CC; 8695 bool Inverted = false; 8696 8697 if (Cond.getOpcode() == ISD::SETCC) { 8698 // Check for setcc([su]{add,sub,mul}o == 0). 8699 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ && 8700 isa<ConstantSDNode>(Cond.getOperand(1)) && 8701 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() && 8702 Cond.getOperand(0).getResNo() == 1 && 8703 (Cond.getOperand(0).getOpcode() == ISD::SADDO || 8704 Cond.getOperand(0).getOpcode() == ISD::UADDO || 8705 Cond.getOperand(0).getOpcode() == ISD::SSUBO || 8706 Cond.getOperand(0).getOpcode() == ISD::USUBO || 8707 Cond.getOperand(0).getOpcode() == ISD::SMULO || 8708 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { 8709 Inverted = true; 8710 Cond = Cond.getOperand(0); 8711 } else { 8712 SDValue NewCond = LowerSETCC(Cond, DAG); 8713 if (NewCond.getNode()) 8714 Cond = NewCond; 8715 } 8716 } 8717#if 0 8718 // FIXME: LowerXALUO doesn't handle these!! 8719 else if (Cond.getOpcode() == X86ISD::ADD || 8720 Cond.getOpcode() == X86ISD::SUB || 8721 Cond.getOpcode() == X86ISD::SMUL || 8722 Cond.getOpcode() == X86ISD::UMUL) 8723 Cond = LowerXALUO(Cond, DAG); 8724#endif 8725 8726 // Look pass (and (setcc_carry (cmp ...)), 1). 8727 if (Cond.getOpcode() == ISD::AND && 8728 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8729 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8730 if (C && C->getAPIntValue() == 1) 8731 Cond = Cond.getOperand(0); 8732 } 8733 8734 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8735 // setting operand in place of the X86ISD::SETCC. 8736 unsigned CondOpcode = Cond.getOpcode(); 8737 if (CondOpcode == X86ISD::SETCC || 8738 CondOpcode == X86ISD::SETCC_CARRY) { 8739 CC = Cond.getOperand(0); 8740 8741 SDValue Cmp = Cond.getOperand(1); 8742 unsigned Opc = Cmp.getOpcode(); 8743 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8744 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8745 Cond = Cmp; 8746 addTest = false; 8747 } else { 8748 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8749 default: break; 8750 case X86::COND_O: 8751 case X86::COND_B: 8752 // These can only come from an arithmetic instruction with overflow, 8753 // e.g. SADDO, UADDO. 8754 Cond = Cond.getNode()->getOperand(1); 8755 addTest = false; 8756 break; 8757 } 8758 } 8759 } 8760 CondOpcode = Cond.getOpcode(); 8761 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO || 8762 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO || 8763 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && 8764 Cond.getOperand(0).getValueType() != MVT::i8)) { 8765 SDValue LHS = Cond.getOperand(0); 8766 SDValue RHS = Cond.getOperand(1); 8767 unsigned X86Opcode; 8768 unsigned X86Cond; 8769 SDVTList VTs; 8770 switch (CondOpcode) { 8771 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break; 8772 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break; 8773 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break; 8774 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break; 8775 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; 8776 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; 8777 default: llvm_unreachable("unexpected overflowing operator"); 8778 } 8779 if (Inverted) 8780 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond); 8781 if (CondOpcode == ISD::UMULO) 8782 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), 8783 MVT::i32); 8784 else 8785 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32); 8786 8787 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS); 8788 8789 if (CondOpcode == ISD::UMULO) 8790 Cond = X86Op.getValue(2); 8791 else 8792 Cond = X86Op.getValue(1); 8793 8794 CC = DAG.getConstant(X86Cond, MVT::i8); 8795 addTest = false; 8796 } else { 8797 unsigned CondOpc; 8798 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8799 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8800 if (CondOpc == ISD::OR) { 8801 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8802 // two branches instead of an explicit OR instruction with a 8803 // separate test. 8804 if (Cmp == Cond.getOperand(1).getOperand(1) && 8805 isX86LogicalCmp(Cmp)) { 8806 CC = Cond.getOperand(0).getOperand(0); 8807 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8808 Chain, Dest, CC, Cmp); 8809 CC = Cond.getOperand(1).getOperand(0); 8810 Cond = Cmp; 8811 addTest = false; 8812 } 8813 } else { // ISD::AND 8814 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8815 // two branches instead of an explicit AND instruction with a 8816 // separate test. However, we only do this if this block doesn't 8817 // have a fall-through edge, because this requires an explicit 8818 // jmp when the condition is false. 8819 if (Cmp == Cond.getOperand(1).getOperand(1) && 8820 isX86LogicalCmp(Cmp) && 8821 Op.getNode()->hasOneUse()) { 8822 X86::CondCode CCode = 8823 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8824 CCode = X86::GetOppositeBranchCondition(CCode); 8825 CC = DAG.getConstant(CCode, MVT::i8); 8826 SDNode *User = *Op.getNode()->use_begin(); 8827 // Look for an unconditional branch following this conditional branch. 8828 // We need this because we need to reverse the successors in order 8829 // to implement FCMP_OEQ. 8830 if (User->getOpcode() == ISD::BR) { 8831 SDValue FalseBB = User->getOperand(1); 8832 SDNode *NewBR = 8833 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8834 assert(NewBR == User); 8835 (void)NewBR; 8836 Dest = FalseBB; 8837 8838 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8839 Chain, Dest, CC, Cmp); 8840 X86::CondCode CCode = 8841 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8842 CCode = X86::GetOppositeBranchCondition(CCode); 8843 CC = DAG.getConstant(CCode, MVT::i8); 8844 Cond = Cmp; 8845 addTest = false; 8846 } 8847 } 8848 } 8849 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8850 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8851 // It should be transformed during dag combiner except when the condition 8852 // is set by a arithmetics with overflow node. 8853 X86::CondCode CCode = 8854 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8855 CCode = X86::GetOppositeBranchCondition(CCode); 8856 CC = DAG.getConstant(CCode, MVT::i8); 8857 Cond = Cond.getOperand(0).getOperand(1); 8858 addTest = false; 8859 } else if (Cond.getOpcode() == ISD::SETCC && 8860 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { 8861 // For FCMP_OEQ, we can emit 8862 // two branches instead of an explicit AND instruction with a 8863 // separate test. However, we only do this if this block doesn't 8864 // have a fall-through edge, because this requires an explicit 8865 // jmp when the condition is false. 8866 if (Op.getNode()->hasOneUse()) { 8867 SDNode *User = *Op.getNode()->use_begin(); 8868 // Look for an unconditional branch following this conditional branch. 8869 // We need this because we need to reverse the successors in order 8870 // to implement FCMP_OEQ. 8871 if (User->getOpcode() == ISD::BR) { 8872 SDValue FalseBB = User->getOperand(1); 8873 SDNode *NewBR = 8874 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8875 assert(NewBR == User); 8876 (void)NewBR; 8877 Dest = FalseBB; 8878 8879 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8880 Cond.getOperand(0), Cond.getOperand(1)); 8881 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8882 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8883 Chain, Dest, CC, Cmp); 8884 CC = DAG.getConstant(X86::COND_P, MVT::i8); 8885 Cond = Cmp; 8886 addTest = false; 8887 } 8888 } 8889 } else if (Cond.getOpcode() == ISD::SETCC && 8890 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) { 8891 // For FCMP_UNE, we can emit 8892 // two branches instead of an explicit AND instruction with a 8893 // separate test. However, we only do this if this block doesn't 8894 // have a fall-through edge, because this requires an explicit 8895 // jmp when the condition is false. 8896 if (Op.getNode()->hasOneUse()) { 8897 SDNode *User = *Op.getNode()->use_begin(); 8898 // Look for an unconditional branch following this conditional branch. 8899 // We need this because we need to reverse the successors in order 8900 // to implement FCMP_UNE. 8901 if (User->getOpcode() == ISD::BR) { 8902 SDValue FalseBB = User->getOperand(1); 8903 SDNode *NewBR = 8904 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8905 assert(NewBR == User); 8906 (void)NewBR; 8907 8908 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 8909 Cond.getOperand(0), Cond.getOperand(1)); 8910 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8911 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8912 Chain, Dest, CC, Cmp); 8913 CC = DAG.getConstant(X86::COND_NP, MVT::i8); 8914 Cond = Cmp; 8915 addTest = false; 8916 Dest = FalseBB; 8917 } 8918 } 8919 } 8920 } 8921 8922 if (addTest) { 8923 // Look pass the truncate. 8924 if (Cond.getOpcode() == ISD::TRUNCATE) 8925 Cond = Cond.getOperand(0); 8926 8927 // We know the result of AND is compared against zero. Try to match 8928 // it to BT. 8929 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8930 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8931 if (NewSetCC.getNode()) { 8932 CC = NewSetCC.getOperand(0); 8933 Cond = NewSetCC.getOperand(1); 8934 addTest = false; 8935 } 8936 } 8937 } 8938 8939 if (addTest) { 8940 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8941 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8942 } 8943 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8944 Chain, Dest, CC, Cond); 8945} 8946 8947 8948// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8949// Calls to _alloca is needed to probe the stack when allocating more than 4k 8950// bytes in one go. Touching the stack at 4K increments is necessary to ensure 8951// that the guard pages used by the OS virtual memory manager are allocated in 8952// correct sequence. 8953SDValue 8954X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8955 SelectionDAG &DAG) const { 8956 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8957 getTargetMachine().Options.EnableSegmentedStacks) && 8958 "This should be used only on Windows targets or when segmented stacks " 8959 "are being used"); 8960 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8961 DebugLoc dl = Op.getDebugLoc(); 8962 8963 // Get the inputs. 8964 SDValue Chain = Op.getOperand(0); 8965 SDValue Size = Op.getOperand(1); 8966 // FIXME: Ensure alignment here 8967 8968 bool Is64Bit = Subtarget->is64Bit(); 8969 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8970 8971 if (getTargetMachine().Options.EnableSegmentedStacks) { 8972 MachineFunction &MF = DAG.getMachineFunction(); 8973 MachineRegisterInfo &MRI = MF.getRegInfo(); 8974 8975 if (Is64Bit) { 8976 // The 64 bit implementation of segmented stacks needs to clobber both r10 8977 // r11. This makes it impossible to use it along with nested parameters. 8978 const Function *F = MF.getFunction(); 8979 8980 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8981 I != E; I++) 8982 if (I->hasNestAttr()) 8983 report_fatal_error("Cannot use segmented stacks with functions that " 8984 "have nested arguments."); 8985 } 8986 8987 const TargetRegisterClass *AddrRegClass = 8988 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8989 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8990 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8991 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8992 DAG.getRegister(Vreg, SPTy)); 8993 SDValue Ops1[2] = { Value, Chain }; 8994 return DAG.getMergeValues(Ops1, 2, dl); 8995 } else { 8996 SDValue Flag; 8997 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8998 8999 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 9000 Flag = Chain.getValue(1); 9001 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 9002 9003 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 9004 Flag = Chain.getValue(1); 9005 9006 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 9007 9008 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 9009 return DAG.getMergeValues(Ops1, 2, dl); 9010 } 9011} 9012 9013SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 9014 MachineFunction &MF = DAG.getMachineFunction(); 9015 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 9016 9017 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9018 DebugLoc DL = Op.getDebugLoc(); 9019 9020 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 9021 // vastart just stores the address of the VarArgsFrameIndex slot into the 9022 // memory location argument. 9023 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9024 getPointerTy()); 9025 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 9026 MachinePointerInfo(SV), false, false, 0); 9027 } 9028 9029 // __va_list_tag: 9030 // gp_offset (0 - 6 * 8) 9031 // fp_offset (48 - 48 + 8 * 16) 9032 // overflow_arg_area (point to parameters coming in memory). 9033 // reg_save_area 9034 SmallVector<SDValue, 8> MemOps; 9035 SDValue FIN = Op.getOperand(1); 9036 // Store gp_offset 9037 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9038 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9039 MVT::i32), 9040 FIN, MachinePointerInfo(SV), false, false, 0); 9041 MemOps.push_back(Store); 9042 9043 // Store fp_offset 9044 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9045 FIN, DAG.getIntPtrConstant(4)); 9046 Store = DAG.getStore(Op.getOperand(0), DL, 9047 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9048 MVT::i32), 9049 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9050 MemOps.push_back(Store); 9051 9052 // Store ptr to overflow_arg_area 9053 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9054 FIN, DAG.getIntPtrConstant(4)); 9055 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9056 getPointerTy()); 9057 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9058 MachinePointerInfo(SV, 8), 9059 false, false, 0); 9060 MemOps.push_back(Store); 9061 9062 // Store ptr to reg_save_area. 9063 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9064 FIN, DAG.getIntPtrConstant(8)); 9065 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9066 getPointerTy()); 9067 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9068 MachinePointerInfo(SV, 16), false, false, 0); 9069 MemOps.push_back(Store); 9070 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9071 &MemOps[0], MemOps.size()); 9072} 9073 9074SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9075 assert(Subtarget->is64Bit() && 9076 "LowerVAARG only handles 64-bit va_arg!"); 9077 assert((Subtarget->isTargetLinux() || 9078 Subtarget->isTargetDarwin()) && 9079 "Unhandled target in LowerVAARG"); 9080 assert(Op.getNode()->getNumOperands() == 4); 9081 SDValue Chain = Op.getOperand(0); 9082 SDValue SrcPtr = Op.getOperand(1); 9083 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9084 unsigned Align = Op.getConstantOperandVal(3); 9085 DebugLoc dl = Op.getDebugLoc(); 9086 9087 EVT ArgVT = Op.getNode()->getValueType(0); 9088 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9089 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9090 uint8_t ArgMode; 9091 9092 // Decide which area this value should be read from. 9093 // TODO: Implement the AMD64 ABI in its entirety. This simple 9094 // selection mechanism works only for the basic types. 9095 if (ArgVT == MVT::f80) { 9096 llvm_unreachable("va_arg for f80 not yet implemented"); 9097 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9098 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9099 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9100 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9101 } else { 9102 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9103 } 9104 9105 if (ArgMode == 2) { 9106 // Sanity Check: Make sure using fp_offset makes sense. 9107 assert(!getTargetMachine().Options.UseSoftFloat && 9108 !(DAG.getMachineFunction() 9109 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9110 Subtarget->hasSSE1()); 9111 } 9112 9113 // Insert VAARG_64 node into the DAG 9114 // VAARG_64 returns two values: Variable Argument Address, Chain 9115 SmallVector<SDValue, 11> InstOps; 9116 InstOps.push_back(Chain); 9117 InstOps.push_back(SrcPtr); 9118 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9119 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9120 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9121 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9122 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9123 VTs, &InstOps[0], InstOps.size(), 9124 MVT::i64, 9125 MachinePointerInfo(SV), 9126 /*Align=*/0, 9127 /*Volatile=*/false, 9128 /*ReadMem=*/true, 9129 /*WriteMem=*/true); 9130 Chain = VAARG.getValue(1); 9131 9132 // Load the next argument and return it 9133 return DAG.getLoad(ArgVT, dl, 9134 Chain, 9135 VAARG, 9136 MachinePointerInfo(), 9137 false, false, false, 0); 9138} 9139 9140SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9141 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9142 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9143 SDValue Chain = Op.getOperand(0); 9144 SDValue DstPtr = Op.getOperand(1); 9145 SDValue SrcPtr = Op.getOperand(2); 9146 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9147 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9148 DebugLoc DL = Op.getDebugLoc(); 9149 9150 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9151 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9152 false, 9153 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9154} 9155 9156SDValue 9157X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9158 DebugLoc dl = Op.getDebugLoc(); 9159 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9160 switch (IntNo) { 9161 default: return SDValue(); // Don't custom lower most intrinsics. 9162 // Comparison intrinsics. 9163 case Intrinsic::x86_sse_comieq_ss: 9164 case Intrinsic::x86_sse_comilt_ss: 9165 case Intrinsic::x86_sse_comile_ss: 9166 case Intrinsic::x86_sse_comigt_ss: 9167 case Intrinsic::x86_sse_comige_ss: 9168 case Intrinsic::x86_sse_comineq_ss: 9169 case Intrinsic::x86_sse_ucomieq_ss: 9170 case Intrinsic::x86_sse_ucomilt_ss: 9171 case Intrinsic::x86_sse_ucomile_ss: 9172 case Intrinsic::x86_sse_ucomigt_ss: 9173 case Intrinsic::x86_sse_ucomige_ss: 9174 case Intrinsic::x86_sse_ucomineq_ss: 9175 case Intrinsic::x86_sse2_comieq_sd: 9176 case Intrinsic::x86_sse2_comilt_sd: 9177 case Intrinsic::x86_sse2_comile_sd: 9178 case Intrinsic::x86_sse2_comigt_sd: 9179 case Intrinsic::x86_sse2_comige_sd: 9180 case Intrinsic::x86_sse2_comineq_sd: 9181 case Intrinsic::x86_sse2_ucomieq_sd: 9182 case Intrinsic::x86_sse2_ucomilt_sd: 9183 case Intrinsic::x86_sse2_ucomile_sd: 9184 case Intrinsic::x86_sse2_ucomigt_sd: 9185 case Intrinsic::x86_sse2_ucomige_sd: 9186 case Intrinsic::x86_sse2_ucomineq_sd: { 9187 unsigned Opc = 0; 9188 ISD::CondCode CC = ISD::SETCC_INVALID; 9189 switch (IntNo) { 9190 default: break; 9191 case Intrinsic::x86_sse_comieq_ss: 9192 case Intrinsic::x86_sse2_comieq_sd: 9193 Opc = X86ISD::COMI; 9194 CC = ISD::SETEQ; 9195 break; 9196 case Intrinsic::x86_sse_comilt_ss: 9197 case Intrinsic::x86_sse2_comilt_sd: 9198 Opc = X86ISD::COMI; 9199 CC = ISD::SETLT; 9200 break; 9201 case Intrinsic::x86_sse_comile_ss: 9202 case Intrinsic::x86_sse2_comile_sd: 9203 Opc = X86ISD::COMI; 9204 CC = ISD::SETLE; 9205 break; 9206 case Intrinsic::x86_sse_comigt_ss: 9207 case Intrinsic::x86_sse2_comigt_sd: 9208 Opc = X86ISD::COMI; 9209 CC = ISD::SETGT; 9210 break; 9211 case Intrinsic::x86_sse_comige_ss: 9212 case Intrinsic::x86_sse2_comige_sd: 9213 Opc = X86ISD::COMI; 9214 CC = ISD::SETGE; 9215 break; 9216 case Intrinsic::x86_sse_comineq_ss: 9217 case Intrinsic::x86_sse2_comineq_sd: 9218 Opc = X86ISD::COMI; 9219 CC = ISD::SETNE; 9220 break; 9221 case Intrinsic::x86_sse_ucomieq_ss: 9222 case Intrinsic::x86_sse2_ucomieq_sd: 9223 Opc = X86ISD::UCOMI; 9224 CC = ISD::SETEQ; 9225 break; 9226 case Intrinsic::x86_sse_ucomilt_ss: 9227 case Intrinsic::x86_sse2_ucomilt_sd: 9228 Opc = X86ISD::UCOMI; 9229 CC = ISD::SETLT; 9230 break; 9231 case Intrinsic::x86_sse_ucomile_ss: 9232 case Intrinsic::x86_sse2_ucomile_sd: 9233 Opc = X86ISD::UCOMI; 9234 CC = ISD::SETLE; 9235 break; 9236 case Intrinsic::x86_sse_ucomigt_ss: 9237 case Intrinsic::x86_sse2_ucomigt_sd: 9238 Opc = X86ISD::UCOMI; 9239 CC = ISD::SETGT; 9240 break; 9241 case Intrinsic::x86_sse_ucomige_ss: 9242 case Intrinsic::x86_sse2_ucomige_sd: 9243 Opc = X86ISD::UCOMI; 9244 CC = ISD::SETGE; 9245 break; 9246 case Intrinsic::x86_sse_ucomineq_ss: 9247 case Intrinsic::x86_sse2_ucomineq_sd: 9248 Opc = X86ISD::UCOMI; 9249 CC = ISD::SETNE; 9250 break; 9251 } 9252 9253 SDValue LHS = Op.getOperand(1); 9254 SDValue RHS = Op.getOperand(2); 9255 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9256 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9257 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9258 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9259 DAG.getConstant(X86CC, MVT::i8), Cond); 9260 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9261 } 9262 // Arithmetic intrinsics. 9263 case Intrinsic::x86_sse3_hadd_ps: 9264 case Intrinsic::x86_sse3_hadd_pd: 9265 case Intrinsic::x86_avx_hadd_ps_256: 9266 case Intrinsic::x86_avx_hadd_pd_256: 9267 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9268 Op.getOperand(1), Op.getOperand(2)); 9269 case Intrinsic::x86_sse3_hsub_ps: 9270 case Intrinsic::x86_sse3_hsub_pd: 9271 case Intrinsic::x86_avx_hsub_ps_256: 9272 case Intrinsic::x86_avx_hsub_pd_256: 9273 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9274 Op.getOperand(1), Op.getOperand(2)); 9275 case Intrinsic::x86_avx2_psllv_d: 9276 case Intrinsic::x86_avx2_psllv_q: 9277 case Intrinsic::x86_avx2_psllv_d_256: 9278 case Intrinsic::x86_avx2_psllv_q_256: 9279 return DAG.getNode(ISD::SHL, dl, Op.getValueType(), 9280 Op.getOperand(1), Op.getOperand(2)); 9281 case Intrinsic::x86_avx2_psrlv_d: 9282 case Intrinsic::x86_avx2_psrlv_q: 9283 case Intrinsic::x86_avx2_psrlv_d_256: 9284 case Intrinsic::x86_avx2_psrlv_q_256: 9285 return DAG.getNode(ISD::SRL, dl, Op.getValueType(), 9286 Op.getOperand(1), Op.getOperand(2)); 9287 case Intrinsic::x86_avx2_psrav_d: 9288 case Intrinsic::x86_avx2_psrav_d_256: 9289 return DAG.getNode(ISD::SRA, dl, Op.getValueType(), 9290 Op.getOperand(1), Op.getOperand(2)); 9291 9292 // ptest and testp intrinsics. The intrinsic these come from are designed to 9293 // return an integer value, not just an instruction so lower it to the ptest 9294 // or testp pattern and a setcc for the result. 9295 case Intrinsic::x86_sse41_ptestz: 9296 case Intrinsic::x86_sse41_ptestc: 9297 case Intrinsic::x86_sse41_ptestnzc: 9298 case Intrinsic::x86_avx_ptestz_256: 9299 case Intrinsic::x86_avx_ptestc_256: 9300 case Intrinsic::x86_avx_ptestnzc_256: 9301 case Intrinsic::x86_avx_vtestz_ps: 9302 case Intrinsic::x86_avx_vtestc_ps: 9303 case Intrinsic::x86_avx_vtestnzc_ps: 9304 case Intrinsic::x86_avx_vtestz_pd: 9305 case Intrinsic::x86_avx_vtestc_pd: 9306 case Intrinsic::x86_avx_vtestnzc_pd: 9307 case Intrinsic::x86_avx_vtestz_ps_256: 9308 case Intrinsic::x86_avx_vtestc_ps_256: 9309 case Intrinsic::x86_avx_vtestnzc_ps_256: 9310 case Intrinsic::x86_avx_vtestz_pd_256: 9311 case Intrinsic::x86_avx_vtestc_pd_256: 9312 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9313 bool IsTestPacked = false; 9314 unsigned X86CC = 0; 9315 switch (IntNo) { 9316 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9317 case Intrinsic::x86_avx_vtestz_ps: 9318 case Intrinsic::x86_avx_vtestz_pd: 9319 case Intrinsic::x86_avx_vtestz_ps_256: 9320 case Intrinsic::x86_avx_vtestz_pd_256: 9321 IsTestPacked = true; // Fallthrough 9322 case Intrinsic::x86_sse41_ptestz: 9323 case Intrinsic::x86_avx_ptestz_256: 9324 // ZF = 1 9325 X86CC = X86::COND_E; 9326 break; 9327 case Intrinsic::x86_avx_vtestc_ps: 9328 case Intrinsic::x86_avx_vtestc_pd: 9329 case Intrinsic::x86_avx_vtestc_ps_256: 9330 case Intrinsic::x86_avx_vtestc_pd_256: 9331 IsTestPacked = true; // Fallthrough 9332 case Intrinsic::x86_sse41_ptestc: 9333 case Intrinsic::x86_avx_ptestc_256: 9334 // CF = 1 9335 X86CC = X86::COND_B; 9336 break; 9337 case Intrinsic::x86_avx_vtestnzc_ps: 9338 case Intrinsic::x86_avx_vtestnzc_pd: 9339 case Intrinsic::x86_avx_vtestnzc_ps_256: 9340 case Intrinsic::x86_avx_vtestnzc_pd_256: 9341 IsTestPacked = true; // Fallthrough 9342 case Intrinsic::x86_sse41_ptestnzc: 9343 case Intrinsic::x86_avx_ptestnzc_256: 9344 // ZF and CF = 0 9345 X86CC = X86::COND_A; 9346 break; 9347 } 9348 9349 SDValue LHS = Op.getOperand(1); 9350 SDValue RHS = Op.getOperand(2); 9351 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9352 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9353 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9354 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9355 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9356 } 9357 9358 // Fix vector shift instructions where the last operand is a non-immediate 9359 // i32 value. 9360 case Intrinsic::x86_avx2_pslli_w: 9361 case Intrinsic::x86_avx2_pslli_d: 9362 case Intrinsic::x86_avx2_pslli_q: 9363 case Intrinsic::x86_avx2_psrli_w: 9364 case Intrinsic::x86_avx2_psrli_d: 9365 case Intrinsic::x86_avx2_psrli_q: 9366 case Intrinsic::x86_avx2_psrai_w: 9367 case Intrinsic::x86_avx2_psrai_d: 9368 case Intrinsic::x86_sse2_pslli_w: 9369 case Intrinsic::x86_sse2_pslli_d: 9370 case Intrinsic::x86_sse2_pslli_q: 9371 case Intrinsic::x86_sse2_psrli_w: 9372 case Intrinsic::x86_sse2_psrli_d: 9373 case Intrinsic::x86_sse2_psrli_q: 9374 case Intrinsic::x86_sse2_psrai_w: 9375 case Intrinsic::x86_sse2_psrai_d: 9376 case Intrinsic::x86_mmx_pslli_w: 9377 case Intrinsic::x86_mmx_pslli_d: 9378 case Intrinsic::x86_mmx_pslli_q: 9379 case Intrinsic::x86_mmx_psrli_w: 9380 case Intrinsic::x86_mmx_psrli_d: 9381 case Intrinsic::x86_mmx_psrli_q: 9382 case Intrinsic::x86_mmx_psrai_w: 9383 case Intrinsic::x86_mmx_psrai_d: { 9384 SDValue ShAmt = Op.getOperand(2); 9385 if (isa<ConstantSDNode>(ShAmt)) 9386 return SDValue(); 9387 9388 unsigned NewIntNo = 0; 9389 EVT ShAmtVT = MVT::v4i32; 9390 switch (IntNo) { 9391 case Intrinsic::x86_sse2_pslli_w: 9392 NewIntNo = Intrinsic::x86_sse2_psll_w; 9393 break; 9394 case Intrinsic::x86_sse2_pslli_d: 9395 NewIntNo = Intrinsic::x86_sse2_psll_d; 9396 break; 9397 case Intrinsic::x86_sse2_pslli_q: 9398 NewIntNo = Intrinsic::x86_sse2_psll_q; 9399 break; 9400 case Intrinsic::x86_sse2_psrli_w: 9401 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9402 break; 9403 case Intrinsic::x86_sse2_psrli_d: 9404 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9405 break; 9406 case Intrinsic::x86_sse2_psrli_q: 9407 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9408 break; 9409 case Intrinsic::x86_sse2_psrai_w: 9410 NewIntNo = Intrinsic::x86_sse2_psra_w; 9411 break; 9412 case Intrinsic::x86_sse2_psrai_d: 9413 NewIntNo = Intrinsic::x86_sse2_psra_d; 9414 break; 9415 case Intrinsic::x86_avx2_pslli_w: 9416 NewIntNo = Intrinsic::x86_avx2_psll_w; 9417 break; 9418 case Intrinsic::x86_avx2_pslli_d: 9419 NewIntNo = Intrinsic::x86_avx2_psll_d; 9420 break; 9421 case Intrinsic::x86_avx2_pslli_q: 9422 NewIntNo = Intrinsic::x86_avx2_psll_q; 9423 break; 9424 case Intrinsic::x86_avx2_psrli_w: 9425 NewIntNo = Intrinsic::x86_avx2_psrl_w; 9426 break; 9427 case Intrinsic::x86_avx2_psrli_d: 9428 NewIntNo = Intrinsic::x86_avx2_psrl_d; 9429 break; 9430 case Intrinsic::x86_avx2_psrli_q: 9431 NewIntNo = Intrinsic::x86_avx2_psrl_q; 9432 break; 9433 case Intrinsic::x86_avx2_psrai_w: 9434 NewIntNo = Intrinsic::x86_avx2_psra_w; 9435 break; 9436 case Intrinsic::x86_avx2_psrai_d: 9437 NewIntNo = Intrinsic::x86_avx2_psra_d; 9438 break; 9439 default: { 9440 ShAmtVT = MVT::v2i32; 9441 switch (IntNo) { 9442 case Intrinsic::x86_mmx_pslli_w: 9443 NewIntNo = Intrinsic::x86_mmx_psll_w; 9444 break; 9445 case Intrinsic::x86_mmx_pslli_d: 9446 NewIntNo = Intrinsic::x86_mmx_psll_d; 9447 break; 9448 case Intrinsic::x86_mmx_pslli_q: 9449 NewIntNo = Intrinsic::x86_mmx_psll_q; 9450 break; 9451 case Intrinsic::x86_mmx_psrli_w: 9452 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9453 break; 9454 case Intrinsic::x86_mmx_psrli_d: 9455 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9456 break; 9457 case Intrinsic::x86_mmx_psrli_q: 9458 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9459 break; 9460 case Intrinsic::x86_mmx_psrai_w: 9461 NewIntNo = Intrinsic::x86_mmx_psra_w; 9462 break; 9463 case Intrinsic::x86_mmx_psrai_d: 9464 NewIntNo = Intrinsic::x86_mmx_psra_d; 9465 break; 9466 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9467 } 9468 break; 9469 } 9470 } 9471 9472 // The vector shift intrinsics with scalars uses 32b shift amounts but 9473 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9474 // to be zero. 9475 SDValue ShOps[4]; 9476 ShOps[0] = ShAmt; 9477 ShOps[1] = DAG.getConstant(0, MVT::i32); 9478 if (ShAmtVT == MVT::v4i32) { 9479 ShOps[2] = DAG.getUNDEF(MVT::i32); 9480 ShOps[3] = DAG.getUNDEF(MVT::i32); 9481 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9482 } else { 9483 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9484// FIXME this must be lowered to get rid of the invalid type. 9485 } 9486 9487 EVT VT = Op.getValueType(); 9488 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9489 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9490 DAG.getConstant(NewIntNo, MVT::i32), 9491 Op.getOperand(1), ShAmt); 9492 } 9493 } 9494} 9495 9496SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9497 SelectionDAG &DAG) const { 9498 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9499 MFI->setReturnAddressIsTaken(true); 9500 9501 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9502 DebugLoc dl = Op.getDebugLoc(); 9503 9504 if (Depth > 0) { 9505 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9506 SDValue Offset = 9507 DAG.getConstant(TD->getPointerSize(), 9508 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9509 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9510 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9511 FrameAddr, Offset), 9512 MachinePointerInfo(), false, false, false, 0); 9513 } 9514 9515 // Just load the return address. 9516 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9517 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9518 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 9519} 9520 9521SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9522 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9523 MFI->setFrameAddressIsTaken(true); 9524 9525 EVT VT = Op.getValueType(); 9526 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9527 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9528 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9529 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9530 while (Depth--) 9531 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9532 MachinePointerInfo(), 9533 false, false, false, 0); 9534 return FrameAddr; 9535} 9536 9537SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9538 SelectionDAG &DAG) const { 9539 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9540} 9541 9542SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9543 MachineFunction &MF = DAG.getMachineFunction(); 9544 SDValue Chain = Op.getOperand(0); 9545 SDValue Offset = Op.getOperand(1); 9546 SDValue Handler = Op.getOperand(2); 9547 DebugLoc dl = Op.getDebugLoc(); 9548 9549 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9550 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9551 getPointerTy()); 9552 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9553 9554 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9555 DAG.getIntPtrConstant(TD->getPointerSize())); 9556 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9557 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9558 false, false, 0); 9559 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9560 MF.getRegInfo().addLiveOut(StoreAddrReg); 9561 9562 return DAG.getNode(X86ISD::EH_RETURN, dl, 9563 MVT::Other, 9564 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9565} 9566 9567SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9568 SelectionDAG &DAG) const { 9569 return Op.getOperand(0); 9570} 9571 9572SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9573 SelectionDAG &DAG) const { 9574 SDValue Root = Op.getOperand(0); 9575 SDValue Trmp = Op.getOperand(1); // trampoline 9576 SDValue FPtr = Op.getOperand(2); // nested function 9577 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9578 DebugLoc dl = Op.getDebugLoc(); 9579 9580 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9581 9582 if (Subtarget->is64Bit()) { 9583 SDValue OutChains[6]; 9584 9585 // Large code-model. 9586 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9587 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9588 9589 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9590 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9591 9592 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9593 9594 // Load the pointer to the nested function into R11. 9595 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9596 SDValue Addr = Trmp; 9597 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9598 Addr, MachinePointerInfo(TrmpAddr), 9599 false, false, 0); 9600 9601 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9602 DAG.getConstant(2, MVT::i64)); 9603 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9604 MachinePointerInfo(TrmpAddr, 2), 9605 false, false, 2); 9606 9607 // Load the 'nest' parameter value into R10. 9608 // R10 is specified in X86CallingConv.td 9609 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9610 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9611 DAG.getConstant(10, MVT::i64)); 9612 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9613 Addr, MachinePointerInfo(TrmpAddr, 10), 9614 false, false, 0); 9615 9616 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9617 DAG.getConstant(12, MVT::i64)); 9618 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9619 MachinePointerInfo(TrmpAddr, 12), 9620 false, false, 2); 9621 9622 // Jump to the nested function. 9623 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9624 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9625 DAG.getConstant(20, MVT::i64)); 9626 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9627 Addr, MachinePointerInfo(TrmpAddr, 20), 9628 false, false, 0); 9629 9630 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9631 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9632 DAG.getConstant(22, MVT::i64)); 9633 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9634 MachinePointerInfo(TrmpAddr, 22), 9635 false, false, 0); 9636 9637 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9638 } else { 9639 const Function *Func = 9640 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9641 CallingConv::ID CC = Func->getCallingConv(); 9642 unsigned NestReg; 9643 9644 switch (CC) { 9645 default: 9646 llvm_unreachable("Unsupported calling convention"); 9647 case CallingConv::C: 9648 case CallingConv::X86_StdCall: { 9649 // Pass 'nest' parameter in ECX. 9650 // Must be kept in sync with X86CallingConv.td 9651 NestReg = X86::ECX; 9652 9653 // Check that ECX wasn't needed by an 'inreg' parameter. 9654 FunctionType *FTy = Func->getFunctionType(); 9655 const AttrListPtr &Attrs = Func->getAttributes(); 9656 9657 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9658 unsigned InRegCount = 0; 9659 unsigned Idx = 1; 9660 9661 for (FunctionType::param_iterator I = FTy->param_begin(), 9662 E = FTy->param_end(); I != E; ++I, ++Idx) 9663 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9664 // FIXME: should only count parameters that are lowered to integers. 9665 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9666 9667 if (InRegCount > 2) { 9668 report_fatal_error("Nest register in use - reduce number of inreg" 9669 " parameters!"); 9670 } 9671 } 9672 break; 9673 } 9674 case CallingConv::X86_FastCall: 9675 case CallingConv::X86_ThisCall: 9676 case CallingConv::Fast: 9677 // Pass 'nest' parameter in EAX. 9678 // Must be kept in sync with X86CallingConv.td 9679 NestReg = X86::EAX; 9680 break; 9681 } 9682 9683 SDValue OutChains[4]; 9684 SDValue Addr, Disp; 9685 9686 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9687 DAG.getConstant(10, MVT::i32)); 9688 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9689 9690 // This is storing the opcode for MOV32ri. 9691 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9692 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9693 OutChains[0] = DAG.getStore(Root, dl, 9694 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9695 Trmp, MachinePointerInfo(TrmpAddr), 9696 false, false, 0); 9697 9698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9699 DAG.getConstant(1, MVT::i32)); 9700 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9701 MachinePointerInfo(TrmpAddr, 1), 9702 false, false, 1); 9703 9704 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9705 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9706 DAG.getConstant(5, MVT::i32)); 9707 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9708 MachinePointerInfo(TrmpAddr, 5), 9709 false, false, 1); 9710 9711 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9712 DAG.getConstant(6, MVT::i32)); 9713 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9714 MachinePointerInfo(TrmpAddr, 6), 9715 false, false, 1); 9716 9717 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9718 } 9719} 9720 9721SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9722 SelectionDAG &DAG) const { 9723 /* 9724 The rounding mode is in bits 11:10 of FPSR, and has the following 9725 settings: 9726 00 Round to nearest 9727 01 Round to -inf 9728 10 Round to +inf 9729 11 Round to 0 9730 9731 FLT_ROUNDS, on the other hand, expects the following: 9732 -1 Undefined 9733 0 Round to 0 9734 1 Round to nearest 9735 2 Round to +inf 9736 3 Round to -inf 9737 9738 To perform the conversion, we do: 9739 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9740 */ 9741 9742 MachineFunction &MF = DAG.getMachineFunction(); 9743 const TargetMachine &TM = MF.getTarget(); 9744 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9745 unsigned StackAlignment = TFI.getStackAlignment(); 9746 EVT VT = Op.getValueType(); 9747 DebugLoc DL = Op.getDebugLoc(); 9748 9749 // Save FP Control Word to stack slot 9750 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9751 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9752 9753 9754 MachineMemOperand *MMO = 9755 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9756 MachineMemOperand::MOStore, 2, 2); 9757 9758 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9759 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9760 DAG.getVTList(MVT::Other), 9761 Ops, 2, MVT::i16, MMO); 9762 9763 // Load FP Control Word from stack slot 9764 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9765 MachinePointerInfo(), false, false, false, 0); 9766 9767 // Transform as necessary 9768 SDValue CWD1 = 9769 DAG.getNode(ISD::SRL, DL, MVT::i16, 9770 DAG.getNode(ISD::AND, DL, MVT::i16, 9771 CWD, DAG.getConstant(0x800, MVT::i16)), 9772 DAG.getConstant(11, MVT::i8)); 9773 SDValue CWD2 = 9774 DAG.getNode(ISD::SRL, DL, MVT::i16, 9775 DAG.getNode(ISD::AND, DL, MVT::i16, 9776 CWD, DAG.getConstant(0x400, MVT::i16)), 9777 DAG.getConstant(9, MVT::i8)); 9778 9779 SDValue RetVal = 9780 DAG.getNode(ISD::AND, DL, MVT::i16, 9781 DAG.getNode(ISD::ADD, DL, MVT::i16, 9782 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9783 DAG.getConstant(1, MVT::i16)), 9784 DAG.getConstant(3, MVT::i16)); 9785 9786 9787 return DAG.getNode((VT.getSizeInBits() < 16 ? 9788 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9789} 9790 9791SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9792 EVT VT = Op.getValueType(); 9793 EVT OpVT = VT; 9794 unsigned NumBits = VT.getSizeInBits(); 9795 DebugLoc dl = Op.getDebugLoc(); 9796 9797 Op = Op.getOperand(0); 9798 if (VT == MVT::i8) { 9799 // Zero extend to i32 since there is not an i8 bsr. 9800 OpVT = MVT::i32; 9801 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9802 } 9803 9804 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9805 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9806 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9807 9808 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9809 SDValue Ops[] = { 9810 Op, 9811 DAG.getConstant(NumBits+NumBits-1, OpVT), 9812 DAG.getConstant(X86::COND_E, MVT::i8), 9813 Op.getValue(1) 9814 }; 9815 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9816 9817 // Finally xor with NumBits-1. 9818 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9819 9820 if (VT == MVT::i8) 9821 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9822 return Op; 9823} 9824 9825SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op, 9826 SelectionDAG &DAG) const { 9827 EVT VT = Op.getValueType(); 9828 EVT OpVT = VT; 9829 unsigned NumBits = VT.getSizeInBits(); 9830 DebugLoc dl = Op.getDebugLoc(); 9831 9832 Op = Op.getOperand(0); 9833 if (VT == MVT::i8) { 9834 // Zero extend to i32 since there is not an i8 bsr. 9835 OpVT = MVT::i32; 9836 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9837 } 9838 9839 // Issue a bsr (scan bits in reverse). 9840 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9841 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9842 9843 // And xor with NumBits-1. 9844 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9845 9846 if (VT == MVT::i8) 9847 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9848 return Op; 9849} 9850 9851SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9852 EVT VT = Op.getValueType(); 9853 unsigned NumBits = VT.getSizeInBits(); 9854 DebugLoc dl = Op.getDebugLoc(); 9855 Op = Op.getOperand(0); 9856 9857 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9858 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 9859 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9860 9861 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9862 SDValue Ops[] = { 9863 Op, 9864 DAG.getConstant(NumBits, VT), 9865 DAG.getConstant(X86::COND_E, MVT::i8), 9866 Op.getValue(1) 9867 }; 9868 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops)); 9869} 9870 9871// Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9872// ones, and then concatenate the result back. 9873static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9874 EVT VT = Op.getValueType(); 9875 9876 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9877 "Unsupported value type for operation"); 9878 9879 int NumElems = VT.getVectorNumElements(); 9880 DebugLoc dl = Op.getDebugLoc(); 9881 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9882 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9883 9884 // Extract the LHS vectors 9885 SDValue LHS = Op.getOperand(0); 9886 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9887 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9888 9889 // Extract the RHS vectors 9890 SDValue RHS = Op.getOperand(1); 9891 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9892 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9893 9894 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9895 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9896 9897 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9898 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9899 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9900} 9901 9902SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9903 assert(Op.getValueType().getSizeInBits() == 256 && 9904 Op.getValueType().isInteger() && 9905 "Only handle AVX 256-bit vector integer operation"); 9906 return Lower256IntArith(Op, DAG); 9907} 9908 9909SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9910 assert(Op.getValueType().getSizeInBits() == 256 && 9911 Op.getValueType().isInteger() && 9912 "Only handle AVX 256-bit vector integer operation"); 9913 return Lower256IntArith(Op, DAG); 9914} 9915 9916SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9917 EVT VT = Op.getValueType(); 9918 9919 // Decompose 256-bit ops into smaller 128-bit ops. 9920 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()) 9921 return Lower256IntArith(Op, DAG); 9922 9923 DebugLoc dl = Op.getDebugLoc(); 9924 9925 SDValue A = Op.getOperand(0); 9926 SDValue B = Op.getOperand(1); 9927 9928 if (VT == MVT::v4i64) { 9929 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2"); 9930 9931 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32); 9932 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32); 9933 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b ); 9934 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi ); 9935 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b ); 9936 // 9937 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 ); 9938 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 ); 9939 // return AloBlo + AloBhi + AhiBlo; 9940 9941 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9942 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9943 A, DAG.getConstant(32, MVT::i32)); 9944 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9945 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32), 9946 B, DAG.getConstant(32, MVT::i32)); 9947 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9948 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9949 A, B); 9950 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9951 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9952 A, Bhi); 9953 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9954 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32), 9955 Ahi, B); 9956 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9957 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9958 AloBhi, DAG.getConstant(32, MVT::i32)); 9959 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9960 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32), 9961 AhiBlo, DAG.getConstant(32, MVT::i32)); 9962 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9963 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9964 return Res; 9965 } 9966 9967 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9968 9969 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9970 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9971 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9972 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9973 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9974 // 9975 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9976 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9977 // return AloBlo + AloBhi + AhiBlo; 9978 9979 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9980 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9981 A, DAG.getConstant(32, MVT::i32)); 9982 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9983 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9984 B, DAG.getConstant(32, MVT::i32)); 9985 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9986 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9987 A, B); 9988 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9989 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9990 A, Bhi); 9991 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9992 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9993 Ahi, B); 9994 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9995 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9996 AloBhi, DAG.getConstant(32, MVT::i32)); 9997 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9998 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9999 AhiBlo, DAG.getConstant(32, MVT::i32)); 10000 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 10001 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 10002 return Res; 10003} 10004 10005// getTargetVShiftNOde - Handle vector element shifts where the shift amount 10006// may or may not be a constant. Takes immediate version of shift as input. 10007static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, 10008 SDValue SrcOp, SDValue ShAmt, 10009 SelectionDAG &DAG) { 10010 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32"); 10011 10012 if (isa<ConstantSDNode>(ShAmt)) { 10013 switch (Opc) { 10014 default: llvm_unreachable("Unknown target vector shift node"); 10015 case X86ISD::VSHLI: 10016 case X86ISD::VSRLI: 10017 case X86ISD::VSRAI: 10018 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 10019 } 10020 } 10021 10022 // Change opcode to non-immediate version 10023 switch (Opc) { 10024 default: llvm_unreachable("Unknown target vector shift node"); 10025 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break; 10026 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break; 10027 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break; 10028 } 10029 10030 // Need to build a vector containing shift amount 10031 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0 10032 SDValue ShOps[4]; 10033 ShOps[0] = ShAmt; 10034 ShOps[1] = DAG.getConstant(0, MVT::i32); 10035 ShOps[2] = DAG.getUNDEF(MVT::i32); 10036 ShOps[3] = DAG.getUNDEF(MVT::i32); 10037 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4); 10038 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 10039 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt); 10040} 10041 10042SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 10043 10044 EVT VT = Op.getValueType(); 10045 DebugLoc dl = Op.getDebugLoc(); 10046 SDValue R = Op.getOperand(0); 10047 SDValue Amt = Op.getOperand(1); 10048 LLVMContext *Context = DAG.getContext(); 10049 10050 if (!Subtarget->hasSSE2()) 10051 return SDValue(); 10052 10053 // Optimize shl/srl/sra with constant shift amount. 10054 if (isSplatVector(Amt.getNode())) { 10055 SDValue SclrAmt = Amt->getOperand(0); 10056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 10057 uint64_t ShiftAmt = C->getZExtValue(); 10058 10059 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || 10060 (Subtarget->hasAVX2() && 10061 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) { 10062 if (Op.getOpcode() == ISD::SHL) 10063 return DAG.getNode(X86ISD::VSHLI, dl, VT, R, 10064 DAG.getConstant(ShiftAmt, MVT::i32)); 10065 if (Op.getOpcode() == ISD::SRL) 10066 return DAG.getNode(X86ISD::VSRLI, dl, VT, R, 10067 DAG.getConstant(ShiftAmt, MVT::i32)); 10068 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64) 10069 return DAG.getNode(X86ISD::VSRAI, dl, VT, R, 10070 DAG.getConstant(ShiftAmt, MVT::i32)); 10071 } 10072 10073 if (VT == MVT::v16i8) { 10074 if (Op.getOpcode() == ISD::SHL) { 10075 // Make a large shift. 10076 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, 10077 DAG.getConstant(ShiftAmt, MVT::i32)); 10078 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10079 // Zero out the rightmost bits. 10080 SmallVector<SDValue, 16> V(16, 10081 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10082 MVT::i8)); 10083 return DAG.getNode(ISD::AND, dl, VT, SHL, 10084 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10085 } 10086 if (Op.getOpcode() == ISD::SRL) { 10087 // Make a large shift. 10088 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, 10089 DAG.getConstant(ShiftAmt, MVT::i32)); 10090 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10091 // Zero out the leftmost bits. 10092 SmallVector<SDValue, 16> V(16, 10093 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10094 MVT::i8)); 10095 return DAG.getNode(ISD::AND, dl, VT, SRL, 10096 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16)); 10097 } 10098 if (Op.getOpcode() == ISD::SRA) { 10099 if (ShiftAmt == 7) { 10100 // R s>> 7 === R s< 0 10101 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true, 10102 /* HasAVX2 */false, DAG, dl); 10103 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10104 } 10105 10106 // R s>> a === ((R u>> a) ^ m) - m 10107 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10108 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, 10109 MVT::i8)); 10110 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16); 10111 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10112 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10113 return Res; 10114 } 10115 } 10116 10117 if (Subtarget->hasAVX2() && VT == MVT::v32i8) { 10118 if (Op.getOpcode() == ISD::SHL) { 10119 // Make a large shift. 10120 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, 10121 DAG.getConstant(ShiftAmt, MVT::i32)); 10122 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL); 10123 // Zero out the rightmost bits. 10124 SmallVector<SDValue, 32> V(32, 10125 DAG.getConstant(uint8_t(-1U << ShiftAmt), 10126 MVT::i8)); 10127 return DAG.getNode(ISD::AND, dl, VT, SHL, 10128 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10129 } 10130 if (Op.getOpcode() == ISD::SRL) { 10131 // Make a large shift. 10132 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, 10133 DAG.getConstant(ShiftAmt, MVT::i32)); 10134 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL); 10135 // Zero out the leftmost bits. 10136 SmallVector<SDValue, 32> V(32, 10137 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, 10138 MVT::i8)); 10139 return DAG.getNode(ISD::AND, dl, VT, SRL, 10140 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32)); 10141 } 10142 if (Op.getOpcode() == ISD::SRA) { 10143 if (ShiftAmt == 7) { 10144 // R s>> 7 === R s< 0 10145 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, 10146 true /* HasAVX2 */, DAG, dl); 10147 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R); 10148 } 10149 10150 // R s>> a === ((R u>> a) ^ m) - m 10151 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10152 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt, 10153 MVT::i8)); 10154 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32); 10155 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask); 10156 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask); 10157 return Res; 10158 } 10159 } 10160 } 10161 } 10162 10163 // Lower SHL with variable shift amount. 10164 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 10165 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1), 10166 DAG.getConstant(23, MVT::i32)); 10167 10168 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 10169 10170 std::vector<Constant*> CV(4, CI); 10171 Constant *C = ConstantVector::get(CV); 10172 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10173 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10174 MachinePointerInfo::getConstantPool(), 10175 false, false, false, 16); 10176 10177 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 10178 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 10179 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 10180 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 10181 } 10182 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 10183 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq."); 10184 10185 // a = a << 5; 10186 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1), 10187 DAG.getConstant(5, MVT::i32)); 10188 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op); 10189 10190 // Turn 'a' into a mask suitable for VSELECT 10191 SDValue VSelM = DAG.getConstant(0x80, VT); 10192 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10193 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10194 10195 SDValue CM1 = DAG.getConstant(0x0f, VT); 10196 SDValue CM2 = DAG.getConstant(0x3f, VT); 10197 10198 // r = VSELECT(r, psllw(r & (char16)15, 4), a); 10199 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1); 10200 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10201 DAG.getConstant(4, MVT::i32), DAG); 10202 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10203 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10204 10205 // a += a 10206 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10207 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10208 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10209 10210 // r = VSELECT(r, psllw(r & (char16)63, 2), a); 10211 M = DAG.getNode(ISD::AND, dl, VT, R, CM2); 10212 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 10213 DAG.getConstant(2, MVT::i32), DAG); 10214 M = DAG.getNode(ISD::BITCAST, dl, VT, M); 10215 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R); 10216 10217 // a += a 10218 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10219 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op); 10220 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM); 10221 10222 // return VSELECT(r, r+r, a); 10223 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, 10224 DAG.getNode(ISD::ADD, dl, VT, R, R), R); 10225 return R; 10226 } 10227 10228 // Decompose 256-bit shifts into smaller 128-bit shifts. 10229 if (VT.getSizeInBits() == 256) { 10230 unsigned NumElems = VT.getVectorNumElements(); 10231 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10232 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10233 10234 // Extract the two vectors 10235 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 10236 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 10237 DAG, dl); 10238 10239 // Recreate the shift amount vectors 10240 SDValue Amt1, Amt2; 10241 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10242 // Constant shift amount 10243 SmallVector<SDValue, 4> Amt1Csts; 10244 SmallVector<SDValue, 4> Amt2Csts; 10245 for (unsigned i = 0; i != NumElems/2; ++i) 10246 Amt1Csts.push_back(Amt->getOperand(i)); 10247 for (unsigned i = NumElems/2; i != NumElems; ++i) 10248 Amt2Csts.push_back(Amt->getOperand(i)); 10249 10250 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10251 &Amt1Csts[0], NumElems/2); 10252 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 10253 &Amt2Csts[0], NumElems/2); 10254 } else { 10255 // Variable shift amount 10256 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10257 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 10258 DAG, dl); 10259 } 10260 10261 // Issue new vector shifts for the smaller types 10262 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 10263 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 10264 10265 // Concatenate the result back 10266 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 10267 } 10268 10269 return SDValue(); 10270} 10271 10272SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10273 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10274 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10275 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10276 // has only one use. 10277 SDNode *N = Op.getNode(); 10278 SDValue LHS = N->getOperand(0); 10279 SDValue RHS = N->getOperand(1); 10280 unsigned BaseOp = 0; 10281 unsigned Cond = 0; 10282 DebugLoc DL = Op.getDebugLoc(); 10283 switch (Op.getOpcode()) { 10284 default: llvm_unreachable("Unknown ovf instruction!"); 10285 case ISD::SADDO: 10286 // A subtract of one will be selected as a INC. Note that INC doesn't 10287 // set CF, so we can't do this for UADDO. 10288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10289 if (C->isOne()) { 10290 BaseOp = X86ISD::INC; 10291 Cond = X86::COND_O; 10292 break; 10293 } 10294 BaseOp = X86ISD::ADD; 10295 Cond = X86::COND_O; 10296 break; 10297 case ISD::UADDO: 10298 BaseOp = X86ISD::ADD; 10299 Cond = X86::COND_B; 10300 break; 10301 case ISD::SSUBO: 10302 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10303 // set CF, so we can't do this for USUBO. 10304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10305 if (C->isOne()) { 10306 BaseOp = X86ISD::DEC; 10307 Cond = X86::COND_O; 10308 break; 10309 } 10310 BaseOp = X86ISD::SUB; 10311 Cond = X86::COND_O; 10312 break; 10313 case ISD::USUBO: 10314 BaseOp = X86ISD::SUB; 10315 Cond = X86::COND_B; 10316 break; 10317 case ISD::SMULO: 10318 BaseOp = X86ISD::SMUL; 10319 Cond = X86::COND_O; 10320 break; 10321 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10322 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10323 MVT::i32); 10324 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10325 10326 SDValue SetCC = 10327 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10328 DAG.getConstant(X86::COND_O, MVT::i32), 10329 SDValue(Sum.getNode(), 2)); 10330 10331 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10332 } 10333 } 10334 10335 // Also sets EFLAGS. 10336 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10337 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10338 10339 SDValue SetCC = 10340 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10341 DAG.getConstant(Cond, MVT::i32), 10342 SDValue(Sum.getNode(), 1)); 10343 10344 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10345} 10346 10347SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, 10348 SelectionDAG &DAG) const { 10349 DebugLoc dl = Op.getDebugLoc(); 10350 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 10351 EVT VT = Op.getValueType(); 10352 10353 if (!Subtarget->hasSSE2() || !VT.isVector()) 10354 return SDValue(); 10355 10356 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10357 ExtraVT.getScalarType().getSizeInBits(); 10358 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10359 10360 switch (VT.getSimpleVT().SimpleTy) { 10361 default: return SDValue(); 10362 case MVT::v8i32: 10363 case MVT::v16i16: 10364 if (!Subtarget->hasAVX()) 10365 return SDValue(); 10366 if (!Subtarget->hasAVX2()) { 10367 // needs to be split 10368 int NumElems = VT.getVectorNumElements(); 10369 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 10370 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 10371 10372 // Extract the LHS vectors 10373 SDValue LHS = Op.getOperand(0); 10374 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 10375 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 10376 10377 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 10378 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 10379 10380 EVT ExtraEltVT = ExtraVT.getVectorElementType(); 10381 int ExtraNumElems = ExtraVT.getVectorNumElements(); 10382 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT, 10383 ExtraNumElems/2); 10384 SDValue Extra = DAG.getValueType(ExtraVT); 10385 10386 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra); 10387 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra); 10388 10389 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);; 10390 } 10391 // fall through 10392 case MVT::v4i32: 10393 case MVT::v8i16: { 10394 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, 10395 Op.getOperand(0), ShAmt, DAG); 10396 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG); 10397 } 10398 } 10399} 10400 10401 10402SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10403 DebugLoc dl = Op.getDebugLoc(); 10404 10405 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10406 // There isn't any reason to disable it if the target processor supports it. 10407 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) { 10408 SDValue Chain = Op.getOperand(0); 10409 SDValue Zero = DAG.getConstant(0, MVT::i32); 10410 SDValue Ops[] = { 10411 DAG.getRegister(X86::ESP, MVT::i32), // Base 10412 DAG.getTargetConstant(1, MVT::i8), // Scale 10413 DAG.getRegister(0, MVT::i32), // Index 10414 DAG.getTargetConstant(0, MVT::i32), // Disp 10415 DAG.getRegister(0, MVT::i32), // Segment. 10416 Zero, 10417 Chain 10418 }; 10419 SDNode *Res = 10420 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10421 array_lengthof(Ops)); 10422 return SDValue(Res, 0); 10423 } 10424 10425 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10426 if (!isDev) 10427 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10428 10429 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10430 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10431 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10432 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10433 10434 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10435 if (!Op1 && !Op2 && !Op3 && Op4) 10436 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10437 10438 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10439 if (Op1 && !Op2 && !Op3 && !Op4) 10440 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10441 10442 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10443 // (MFENCE)>; 10444 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10445} 10446 10447SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10448 SelectionDAG &DAG) const { 10449 DebugLoc dl = Op.getDebugLoc(); 10450 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10451 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10452 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10453 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10454 10455 // The only fence that needs an instruction is a sequentially-consistent 10456 // cross-thread fence. 10457 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10458 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10459 // no-sse2). There isn't any reason to disable it if the target processor 10460 // supports it. 10461 if (Subtarget->hasSSE2() || Subtarget->is64Bit()) 10462 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10463 10464 SDValue Chain = Op.getOperand(0); 10465 SDValue Zero = DAG.getConstant(0, MVT::i32); 10466 SDValue Ops[] = { 10467 DAG.getRegister(X86::ESP, MVT::i32), // Base 10468 DAG.getTargetConstant(1, MVT::i8), // Scale 10469 DAG.getRegister(0, MVT::i32), // Index 10470 DAG.getTargetConstant(0, MVT::i32), // Disp 10471 DAG.getRegister(0, MVT::i32), // Segment. 10472 Zero, 10473 Chain 10474 }; 10475 SDNode *Res = 10476 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10477 array_lengthof(Ops)); 10478 return SDValue(Res, 0); 10479 } 10480 10481 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10482 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10483} 10484 10485 10486SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10487 EVT T = Op.getValueType(); 10488 DebugLoc DL = Op.getDebugLoc(); 10489 unsigned Reg = 0; 10490 unsigned size = 0; 10491 switch(T.getSimpleVT().SimpleTy) { 10492 default: 10493 assert(false && "Invalid value type!"); 10494 case MVT::i8: Reg = X86::AL; size = 1; break; 10495 case MVT::i16: Reg = X86::AX; size = 2; break; 10496 case MVT::i32: Reg = X86::EAX; size = 4; break; 10497 case MVT::i64: 10498 assert(Subtarget->is64Bit() && "Node not type legal!"); 10499 Reg = X86::RAX; size = 8; 10500 break; 10501 } 10502 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10503 Op.getOperand(2), SDValue()); 10504 SDValue Ops[] = { cpIn.getValue(0), 10505 Op.getOperand(1), 10506 Op.getOperand(3), 10507 DAG.getTargetConstant(size, MVT::i8), 10508 cpIn.getValue(1) }; 10509 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10510 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10511 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10512 Ops, 5, T, MMO); 10513 SDValue cpOut = 10514 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10515 return cpOut; 10516} 10517 10518SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10519 SelectionDAG &DAG) const { 10520 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10521 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10522 SDValue TheChain = Op.getOperand(0); 10523 DebugLoc dl = Op.getDebugLoc(); 10524 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10525 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10526 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10527 rax.getValue(2)); 10528 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10529 DAG.getConstant(32, MVT::i8)); 10530 SDValue Ops[] = { 10531 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10532 rdx.getValue(1) 10533 }; 10534 return DAG.getMergeValues(Ops, 2, dl); 10535} 10536 10537SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10538 SelectionDAG &DAG) const { 10539 EVT SrcVT = Op.getOperand(0).getValueType(); 10540 EVT DstVT = Op.getValueType(); 10541 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() && 10542 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10543 assert((DstVT == MVT::i64 || 10544 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10545 "Unexpected custom BITCAST"); 10546 // i64 <=> MMX conversions are Legal. 10547 if (SrcVT==MVT::i64 && DstVT.isVector()) 10548 return Op; 10549 if (DstVT==MVT::i64 && SrcVT.isVector()) 10550 return Op; 10551 // MMX <=> MMX conversions are Legal. 10552 if (SrcVT.isVector() && DstVT.isVector()) 10553 return Op; 10554 // All other conversions need to be expanded. 10555 return SDValue(); 10556} 10557 10558SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10559 SDNode *Node = Op.getNode(); 10560 DebugLoc dl = Node->getDebugLoc(); 10561 EVT T = Node->getValueType(0); 10562 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10563 DAG.getConstant(0, T), Node->getOperand(2)); 10564 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10565 cast<AtomicSDNode>(Node)->getMemoryVT(), 10566 Node->getOperand(0), 10567 Node->getOperand(1), negOp, 10568 cast<AtomicSDNode>(Node)->getSrcValue(), 10569 cast<AtomicSDNode>(Node)->getAlignment(), 10570 cast<AtomicSDNode>(Node)->getOrdering(), 10571 cast<AtomicSDNode>(Node)->getSynchScope()); 10572} 10573 10574static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10575 SDNode *Node = Op.getNode(); 10576 DebugLoc dl = Node->getDebugLoc(); 10577 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10578 10579 // Convert seq_cst store -> xchg 10580 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10581 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10582 // (The only way to get a 16-byte store is cmpxchg16b) 10583 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10584 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10585 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10586 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10587 cast<AtomicSDNode>(Node)->getMemoryVT(), 10588 Node->getOperand(0), 10589 Node->getOperand(1), Node->getOperand(2), 10590 cast<AtomicSDNode>(Node)->getMemOperand(), 10591 cast<AtomicSDNode>(Node)->getOrdering(), 10592 cast<AtomicSDNode>(Node)->getSynchScope()); 10593 return Swap.getValue(1); 10594 } 10595 // Other atomic stores have a simple pattern. 10596 return Op; 10597} 10598 10599static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10600 EVT VT = Op.getNode()->getValueType(0); 10601 10602 // Let legalize expand this if it isn't a legal type yet. 10603 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10604 return SDValue(); 10605 10606 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10607 10608 unsigned Opc; 10609 bool ExtraOp = false; 10610 switch (Op.getOpcode()) { 10611 default: assert(0 && "Invalid code"); 10612 case ISD::ADDC: Opc = X86ISD::ADD; break; 10613 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10614 case ISD::SUBC: Opc = X86ISD::SUB; break; 10615 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10616 } 10617 10618 if (!ExtraOp) 10619 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10620 Op.getOperand(1)); 10621 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10622 Op.getOperand(1), Op.getOperand(2)); 10623} 10624 10625/// LowerOperation - Provide custom lowering hooks for some operations. 10626/// 10627SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10628 switch (Op.getOpcode()) { 10629 default: llvm_unreachable("Should not custom lower this!"); 10630 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10631 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10632 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10633 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10634 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10635 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10636 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10637 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10638 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10639 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10640 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10641 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10642 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10643 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10644 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10645 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10646 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10647 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10648 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10649 case ISD::SHL_PARTS: 10650 case ISD::SRA_PARTS: 10651 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10652 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10653 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10654 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10655 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10656 case ISD::FABS: return LowerFABS(Op, DAG); 10657 case ISD::FNEG: return LowerFNEG(Op, DAG); 10658 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10659 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10660 case ISD::SETCC: return LowerSETCC(Op, DAG); 10661 case ISD::SELECT: return LowerSELECT(Op, DAG); 10662 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10663 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10664 case ISD::VASTART: return LowerVASTART(Op, DAG); 10665 case ISD::VAARG: return LowerVAARG(Op, DAG); 10666 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10667 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10668 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10669 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10670 case ISD::FRAME_TO_ARGS_OFFSET: 10671 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10672 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10673 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10674 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10675 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10676 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10677 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10678 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG); 10679 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10680 case ISD::MUL: return LowerMUL(Op, DAG); 10681 case ISD::SRA: 10682 case ISD::SRL: 10683 case ISD::SHL: return LowerShift(Op, DAG); 10684 case ISD::SADDO: 10685 case ISD::UADDO: 10686 case ISD::SSUBO: 10687 case ISD::USUBO: 10688 case ISD::SMULO: 10689 case ISD::UMULO: return LowerXALUO(Op, DAG); 10690 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10691 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10692 case ISD::ADDC: 10693 case ISD::ADDE: 10694 case ISD::SUBC: 10695 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10696 case ISD::ADD: return LowerADD(Op, DAG); 10697 case ISD::SUB: return LowerSUB(Op, DAG); 10698 } 10699} 10700 10701static void ReplaceATOMIC_LOAD(SDNode *Node, 10702 SmallVectorImpl<SDValue> &Results, 10703 SelectionDAG &DAG) { 10704 DebugLoc dl = Node->getDebugLoc(); 10705 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10706 10707 // Convert wide load -> cmpxchg8b/cmpxchg16b 10708 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10709 // (The only way to get a 16-byte load is cmpxchg16b) 10710 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10711 SDValue Zero = DAG.getConstant(0, VT); 10712 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10713 Node->getOperand(0), 10714 Node->getOperand(1), Zero, Zero, 10715 cast<AtomicSDNode>(Node)->getMemOperand(), 10716 cast<AtomicSDNode>(Node)->getOrdering(), 10717 cast<AtomicSDNode>(Node)->getSynchScope()); 10718 Results.push_back(Swap.getValue(0)); 10719 Results.push_back(Swap.getValue(1)); 10720} 10721 10722void X86TargetLowering:: 10723ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10724 SelectionDAG &DAG, unsigned NewOp) const { 10725 DebugLoc dl = Node->getDebugLoc(); 10726 assert (Node->getValueType(0) == MVT::i64 && 10727 "Only know how to expand i64 atomics"); 10728 10729 SDValue Chain = Node->getOperand(0); 10730 SDValue In1 = Node->getOperand(1); 10731 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10732 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10733 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10734 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10735 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10736 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10737 SDValue Result = 10738 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10739 cast<MemSDNode>(Node)->getMemOperand()); 10740 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10741 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10742 Results.push_back(Result.getValue(2)); 10743} 10744 10745/// ReplaceNodeResults - Replace a node with an illegal result type 10746/// with a new node built out of custom code. 10747void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10748 SmallVectorImpl<SDValue>&Results, 10749 SelectionDAG &DAG) const { 10750 DebugLoc dl = N->getDebugLoc(); 10751 switch (N->getOpcode()) { 10752 default: 10753 assert(false && "Do not know how to custom type legalize this operation!"); 10754 return; 10755 case ISD::SIGN_EXTEND_INREG: 10756 case ISD::ADDC: 10757 case ISD::ADDE: 10758 case ISD::SUBC: 10759 case ISD::SUBE: 10760 // We don't want to expand or promote these. 10761 return; 10762 case ISD::FP_TO_SINT: { 10763 std::pair<SDValue,SDValue> Vals = 10764 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10765 SDValue FIST = Vals.first, StackSlot = Vals.second; 10766 if (FIST.getNode() != 0) { 10767 EVT VT = N->getValueType(0); 10768 // Return a load from the stack slot. 10769 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10770 MachinePointerInfo(), 10771 false, false, false, 0)); 10772 } 10773 return; 10774 } 10775 case ISD::READCYCLECOUNTER: { 10776 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10777 SDValue TheChain = N->getOperand(0); 10778 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10779 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10780 rd.getValue(1)); 10781 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10782 eax.getValue(2)); 10783 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10784 SDValue Ops[] = { eax, edx }; 10785 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10786 Results.push_back(edx.getValue(1)); 10787 return; 10788 } 10789 case ISD::ATOMIC_CMP_SWAP: { 10790 EVT T = N->getValueType(0); 10791 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10792 bool Regs64bit = T == MVT::i128; 10793 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10794 SDValue cpInL, cpInH; 10795 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10796 DAG.getConstant(0, HalfT)); 10797 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10798 DAG.getConstant(1, HalfT)); 10799 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10800 Regs64bit ? X86::RAX : X86::EAX, 10801 cpInL, SDValue()); 10802 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10803 Regs64bit ? X86::RDX : X86::EDX, 10804 cpInH, cpInL.getValue(1)); 10805 SDValue swapInL, swapInH; 10806 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10807 DAG.getConstant(0, HalfT)); 10808 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10809 DAG.getConstant(1, HalfT)); 10810 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10811 Regs64bit ? X86::RBX : X86::EBX, 10812 swapInL, cpInH.getValue(1)); 10813 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10814 Regs64bit ? X86::RCX : X86::ECX, 10815 swapInH, swapInL.getValue(1)); 10816 SDValue Ops[] = { swapInH.getValue(0), 10817 N->getOperand(1), 10818 swapInH.getValue(1) }; 10819 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10820 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10821 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10822 X86ISD::LCMPXCHG8_DAG; 10823 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10824 Ops, 3, T, MMO); 10825 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10826 Regs64bit ? X86::RAX : X86::EAX, 10827 HalfT, Result.getValue(1)); 10828 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10829 Regs64bit ? X86::RDX : X86::EDX, 10830 HalfT, cpOutL.getValue(2)); 10831 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10832 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10833 Results.push_back(cpOutH.getValue(1)); 10834 return; 10835 } 10836 case ISD::ATOMIC_LOAD_ADD: 10837 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10838 return; 10839 case ISD::ATOMIC_LOAD_AND: 10840 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10841 return; 10842 case ISD::ATOMIC_LOAD_NAND: 10843 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10844 return; 10845 case ISD::ATOMIC_LOAD_OR: 10846 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10847 return; 10848 case ISD::ATOMIC_LOAD_SUB: 10849 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10850 return; 10851 case ISD::ATOMIC_LOAD_XOR: 10852 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10853 return; 10854 case ISD::ATOMIC_SWAP: 10855 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10856 return; 10857 case ISD::ATOMIC_LOAD: 10858 ReplaceATOMIC_LOAD(N, Results, DAG); 10859 } 10860} 10861 10862const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10863 switch (Opcode) { 10864 default: return NULL; 10865 case X86ISD::BSF: return "X86ISD::BSF"; 10866 case X86ISD::BSR: return "X86ISD::BSR"; 10867 case X86ISD::SHLD: return "X86ISD::SHLD"; 10868 case X86ISD::SHRD: return "X86ISD::SHRD"; 10869 case X86ISD::FAND: return "X86ISD::FAND"; 10870 case X86ISD::FOR: return "X86ISD::FOR"; 10871 case X86ISD::FXOR: return "X86ISD::FXOR"; 10872 case X86ISD::FSRL: return "X86ISD::FSRL"; 10873 case X86ISD::FILD: return "X86ISD::FILD"; 10874 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10875 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10876 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10877 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10878 case X86ISD::FLD: return "X86ISD::FLD"; 10879 case X86ISD::FST: return "X86ISD::FST"; 10880 case X86ISD::CALL: return "X86ISD::CALL"; 10881 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10882 case X86ISD::BT: return "X86ISD::BT"; 10883 case X86ISD::CMP: return "X86ISD::CMP"; 10884 case X86ISD::COMI: return "X86ISD::COMI"; 10885 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10886 case X86ISD::SETCC: return "X86ISD::SETCC"; 10887 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10888 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10889 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10890 case X86ISD::CMOV: return "X86ISD::CMOV"; 10891 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10892 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10893 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10894 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10895 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10896 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10897 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10898 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10899 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10900 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10901 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10902 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10903 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10904 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10905 case X86ISD::PSIGN: return "X86ISD::PSIGN"; 10906 case X86ISD::BLENDV: return "X86ISD::BLENDV"; 10907 case X86ISD::HADD: return "X86ISD::HADD"; 10908 case X86ISD::HSUB: return "X86ISD::HSUB"; 10909 case X86ISD::FHADD: return "X86ISD::FHADD"; 10910 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10911 case X86ISD::FMAX: return "X86ISD::FMAX"; 10912 case X86ISD::FMIN: return "X86ISD::FMIN"; 10913 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10914 case X86ISD::FRCP: return "X86ISD::FRCP"; 10915 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10916 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10917 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10918 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10919 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10920 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10921 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10922 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10923 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10924 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10925 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10926 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10927 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10928 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10929 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10930 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ"; 10931 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ"; 10932 case X86ISD::VSHL: return "X86ISD::VSHL"; 10933 case X86ISD::VSRL: return "X86ISD::VSRL"; 10934 case X86ISD::VSRA: return "X86ISD::VSRA"; 10935 case X86ISD::VSHLI: return "X86ISD::VSHLI"; 10936 case X86ISD::VSRLI: return "X86ISD::VSRLI"; 10937 case X86ISD::VSRAI: return "X86ISD::VSRAI"; 10938 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10939 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10940 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ"; 10941 case X86ISD::PCMPGT: return "X86ISD::PCMPGT"; 10942 case X86ISD::ADD: return "X86ISD::ADD"; 10943 case X86ISD::SUB: return "X86ISD::SUB"; 10944 case X86ISD::ADC: return "X86ISD::ADC"; 10945 case X86ISD::SBB: return "X86ISD::SBB"; 10946 case X86ISD::SMUL: return "X86ISD::SMUL"; 10947 case X86ISD::UMUL: return "X86ISD::UMUL"; 10948 case X86ISD::INC: return "X86ISD::INC"; 10949 case X86ISD::DEC: return "X86ISD::DEC"; 10950 case X86ISD::OR: return "X86ISD::OR"; 10951 case X86ISD::XOR: return "X86ISD::XOR"; 10952 case X86ISD::AND: return "X86ISD::AND"; 10953 case X86ISD::ANDN: return "X86ISD::ANDN"; 10954 case X86ISD::BLSI: return "X86ISD::BLSI"; 10955 case X86ISD::BLSMSK: return "X86ISD::BLSMSK"; 10956 case X86ISD::BLSR: return "X86ISD::BLSR"; 10957 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10958 case X86ISD::PTEST: return "X86ISD::PTEST"; 10959 case X86ISD::TESTP: return "X86ISD::TESTP"; 10960 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10961 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10962 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10963 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10964 case X86ISD::SHUFP: return "X86ISD::SHUFP"; 10965 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10966 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10967 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10968 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10969 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10970 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10971 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10972 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10973 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10974 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10975 case X86ISD::UNPCKL: return "X86ISD::UNPCKL"; 10976 case X86ISD::UNPCKH: return "X86ISD::UNPCKH"; 10977 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 10978 case X86ISD::VPERMILP: return "X86ISD::VPERMILP"; 10979 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128"; 10980 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 10981 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 10982 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 10983 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 10984 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 10985 } 10986} 10987 10988// isLegalAddressingMode - Return true if the addressing mode represented 10989// by AM is legal for this target, for a load/store of the specified type. 10990bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 10991 Type *Ty) const { 10992 // X86 supports extremely general addressing modes. 10993 CodeModel::Model M = getTargetMachine().getCodeModel(); 10994 Reloc::Model R = getTargetMachine().getRelocationModel(); 10995 10996 // X86 allows a sign-extended 32-bit immediate field as a displacement. 10997 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 10998 return false; 10999 11000 if (AM.BaseGV) { 11001 unsigned GVFlags = 11002 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 11003 11004 // If a reference to this global requires an extra load, we can't fold it. 11005 if (isGlobalStubReference(GVFlags)) 11006 return false; 11007 11008 // If BaseGV requires a register for the PIC base, we cannot also have a 11009 // BaseReg specified. 11010 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 11011 return false; 11012 11013 // If lower 4G is not available, then we must use rip-relative addressing. 11014 if ((M != CodeModel::Small || R != Reloc::Static) && 11015 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 11016 return false; 11017 } 11018 11019 switch (AM.Scale) { 11020 case 0: 11021 case 1: 11022 case 2: 11023 case 4: 11024 case 8: 11025 // These scales always work. 11026 break; 11027 case 3: 11028 case 5: 11029 case 9: 11030 // These scales are formed with basereg+scalereg. Only accept if there is 11031 // no basereg yet. 11032 if (AM.HasBaseReg) 11033 return false; 11034 break; 11035 default: // Other stuff never works. 11036 return false; 11037 } 11038 11039 return true; 11040} 11041 11042 11043bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 11044 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 11045 return false; 11046 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 11047 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 11048 if (NumBits1 <= NumBits2) 11049 return false; 11050 return true; 11051} 11052 11053bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 11054 if (!VT1.isInteger() || !VT2.isInteger()) 11055 return false; 11056 unsigned NumBits1 = VT1.getSizeInBits(); 11057 unsigned NumBits2 = VT2.getSizeInBits(); 11058 if (NumBits1 <= NumBits2) 11059 return false; 11060 return true; 11061} 11062 11063bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 11064 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11065 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 11066} 11067 11068bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 11069 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 11070 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 11071} 11072 11073bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 11074 // i16 instructions are longer (0x66 prefix) and potentially slower. 11075 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 11076} 11077 11078/// isShuffleMaskLegal - Targets can use this to indicate that they only 11079/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 11080/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 11081/// are assumed to be legal. 11082bool 11083X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 11084 EVT VT) const { 11085 // Very little shuffling can be done for 64-bit vectors right now. 11086 if (VT.getSizeInBits() == 64) 11087 return false; 11088 11089 // FIXME: pshufb, blends, shifts. 11090 return (VT.getVectorNumElements() == 2 || 11091 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 11092 isMOVLMask(M, VT) || 11093 isSHUFPMask(M, VT, Subtarget->hasAVX()) || 11094 isPSHUFDMask(M, VT) || 11095 isPSHUFHWMask(M, VT) || 11096 isPSHUFLWMask(M, VT) || 11097 isPALIGNRMask(M, VT, Subtarget) || 11098 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) || 11099 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) || 11100 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) || 11101 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2())); 11102} 11103 11104bool 11105X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 11106 EVT VT) const { 11107 unsigned NumElts = VT.getVectorNumElements(); 11108 // FIXME: This collection of masks seems suspect. 11109 if (NumElts == 2) 11110 return true; 11111 if (NumElts == 4 && VT.getSizeInBits() == 128) { 11112 return (isMOVLMask(Mask, VT) || 11113 isCommutedMOVLMask(Mask, VT, true) || 11114 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) || 11115 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true)); 11116 } 11117 return false; 11118} 11119 11120//===----------------------------------------------------------------------===// 11121// X86 Scheduler Hooks 11122//===----------------------------------------------------------------------===// 11123 11124// private utility function 11125MachineBasicBlock * 11126X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 11127 MachineBasicBlock *MBB, 11128 unsigned regOpc, 11129 unsigned immOpc, 11130 unsigned LoadOpc, 11131 unsigned CXchgOpc, 11132 unsigned notOpc, 11133 unsigned EAXreg, 11134 TargetRegisterClass *RC, 11135 bool invSrc) const { 11136 // For the atomic bitwise operator, we generate 11137 // thisMBB: 11138 // newMBB: 11139 // ld t1 = [bitinstr.addr] 11140 // op t2 = t1, [bitinstr.val] 11141 // mov EAX = t1 11142 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11143 // bz newMBB 11144 // fallthrough -->nextMBB 11145 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11146 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11147 MachineFunction::iterator MBBIter = MBB; 11148 ++MBBIter; 11149 11150 /// First build the CFG 11151 MachineFunction *F = MBB->getParent(); 11152 MachineBasicBlock *thisMBB = MBB; 11153 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11154 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11155 F->insert(MBBIter, newMBB); 11156 F->insert(MBBIter, nextMBB); 11157 11158 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11159 nextMBB->splice(nextMBB->begin(), thisMBB, 11160 llvm::next(MachineBasicBlock::iterator(bInstr)), 11161 thisMBB->end()); 11162 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11163 11164 // Update thisMBB to fall through to newMBB 11165 thisMBB->addSuccessor(newMBB); 11166 11167 // newMBB jumps to itself and fall through to nextMBB 11168 newMBB->addSuccessor(nextMBB); 11169 newMBB->addSuccessor(newMBB); 11170 11171 // Insert instructions into newMBB based on incoming instruction 11172 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11173 "unexpected number of operands"); 11174 DebugLoc dl = bInstr->getDebugLoc(); 11175 MachineOperand& destOper = bInstr->getOperand(0); 11176 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11177 int numArgs = bInstr->getNumOperands() - 1; 11178 for (int i=0; i < numArgs; ++i) 11179 argOpers[i] = &bInstr->getOperand(i+1); 11180 11181 // x86 address has 4 operands: base, index, scale, and displacement 11182 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11183 int valArgIndx = lastAddrIndx + 1; 11184 11185 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11186 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 11187 for (int i=0; i <= lastAddrIndx; ++i) 11188 (*MIB).addOperand(*argOpers[i]); 11189 11190 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 11191 if (invSrc) { 11192 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 11193 } 11194 else 11195 tt = t1; 11196 11197 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11198 assert((argOpers[valArgIndx]->isReg() || 11199 argOpers[valArgIndx]->isImm()) && 11200 "invalid operand"); 11201 if (argOpers[valArgIndx]->isReg()) 11202 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 11203 else 11204 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 11205 MIB.addReg(tt); 11206 (*MIB).addOperand(*argOpers[valArgIndx]); 11207 11208 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 11209 MIB.addReg(t1); 11210 11211 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 11212 for (int i=0; i <= lastAddrIndx; ++i) 11213 (*MIB).addOperand(*argOpers[i]); 11214 MIB.addReg(t2); 11215 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11216 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11217 bInstr->memoperands_end()); 11218 11219 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11220 MIB.addReg(EAXreg); 11221 11222 // insert branch 11223 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11224 11225 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11226 return nextMBB; 11227} 11228 11229// private utility function: 64 bit atomics on 32 bit host. 11230MachineBasicBlock * 11231X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11232 MachineBasicBlock *MBB, 11233 unsigned regOpcL, 11234 unsigned regOpcH, 11235 unsigned immOpcL, 11236 unsigned immOpcH, 11237 bool invSrc) const { 11238 // For the atomic bitwise operator, we generate 11239 // thisMBB (instructions are in pairs, except cmpxchg8b) 11240 // ld t1,t2 = [bitinstr.addr] 11241 // newMBB: 11242 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11243 // op t5, t6 <- out1, out2, [bitinstr.val] 11244 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11245 // mov ECX, EBX <- t5, t6 11246 // mov EAX, EDX <- t1, t2 11247 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11248 // mov t3, t4 <- EAX, EDX 11249 // bz newMBB 11250 // result in out1, out2 11251 // fallthrough -->nextMBB 11252 11253 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11254 const unsigned LoadOpc = X86::MOV32rm; 11255 const unsigned NotOpc = X86::NOT32r; 11256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11257 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11258 MachineFunction::iterator MBBIter = MBB; 11259 ++MBBIter; 11260 11261 /// First build the CFG 11262 MachineFunction *F = MBB->getParent(); 11263 MachineBasicBlock *thisMBB = MBB; 11264 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11265 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11266 F->insert(MBBIter, newMBB); 11267 F->insert(MBBIter, nextMBB); 11268 11269 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11270 nextMBB->splice(nextMBB->begin(), thisMBB, 11271 llvm::next(MachineBasicBlock::iterator(bInstr)), 11272 thisMBB->end()); 11273 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11274 11275 // Update thisMBB to fall through to newMBB 11276 thisMBB->addSuccessor(newMBB); 11277 11278 // newMBB jumps to itself and fall through to nextMBB 11279 newMBB->addSuccessor(nextMBB); 11280 newMBB->addSuccessor(newMBB); 11281 11282 DebugLoc dl = bInstr->getDebugLoc(); 11283 // Insert instructions into newMBB based on incoming instruction 11284 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11285 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11286 "unexpected number of operands"); 11287 MachineOperand& dest1Oper = bInstr->getOperand(0); 11288 MachineOperand& dest2Oper = bInstr->getOperand(1); 11289 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11290 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11291 argOpers[i] = &bInstr->getOperand(i+2); 11292 11293 // We use some of the operands multiple times, so conservatively just 11294 // clear any kill flags that might be present. 11295 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11296 argOpers[i]->setIsKill(false); 11297 } 11298 11299 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11300 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11301 11302 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11303 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11304 for (int i=0; i <= lastAddrIndx; ++i) 11305 (*MIB).addOperand(*argOpers[i]); 11306 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11307 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11308 // add 4 to displacement. 11309 for (int i=0; i <= lastAddrIndx-2; ++i) 11310 (*MIB).addOperand(*argOpers[i]); 11311 MachineOperand newOp3 = *(argOpers[3]); 11312 if (newOp3.isImm()) 11313 newOp3.setImm(newOp3.getImm()+4); 11314 else 11315 newOp3.setOffset(newOp3.getOffset()+4); 11316 (*MIB).addOperand(newOp3); 11317 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11318 11319 // t3/4 are defined later, at the bottom of the loop 11320 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11321 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11322 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11323 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11324 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11325 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11326 11327 // The subsequent operations should be using the destination registers of 11328 //the PHI instructions. 11329 if (invSrc) { 11330 t1 = F->getRegInfo().createVirtualRegister(RC); 11331 t2 = F->getRegInfo().createVirtualRegister(RC); 11332 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11333 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11334 } else { 11335 t1 = dest1Oper.getReg(); 11336 t2 = dest2Oper.getReg(); 11337 } 11338 11339 int valArgIndx = lastAddrIndx + 1; 11340 assert((argOpers[valArgIndx]->isReg() || 11341 argOpers[valArgIndx]->isImm()) && 11342 "invalid operand"); 11343 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11344 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11345 if (argOpers[valArgIndx]->isReg()) 11346 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11347 else 11348 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11349 if (regOpcL != X86::MOV32rr) 11350 MIB.addReg(t1); 11351 (*MIB).addOperand(*argOpers[valArgIndx]); 11352 assert(argOpers[valArgIndx + 1]->isReg() == 11353 argOpers[valArgIndx]->isReg()); 11354 assert(argOpers[valArgIndx + 1]->isImm() == 11355 argOpers[valArgIndx]->isImm()); 11356 if (argOpers[valArgIndx + 1]->isReg()) 11357 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11358 else 11359 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11360 if (regOpcH != X86::MOV32rr) 11361 MIB.addReg(t2); 11362 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11363 11364 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11365 MIB.addReg(t1); 11366 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11367 MIB.addReg(t2); 11368 11369 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11370 MIB.addReg(t5); 11371 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11372 MIB.addReg(t6); 11373 11374 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11375 for (int i=0; i <= lastAddrIndx; ++i) 11376 (*MIB).addOperand(*argOpers[i]); 11377 11378 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11379 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11380 bInstr->memoperands_end()); 11381 11382 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11383 MIB.addReg(X86::EAX); 11384 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11385 MIB.addReg(X86::EDX); 11386 11387 // insert branch 11388 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11389 11390 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11391 return nextMBB; 11392} 11393 11394// private utility function 11395MachineBasicBlock * 11396X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11397 MachineBasicBlock *MBB, 11398 unsigned cmovOpc) const { 11399 // For the atomic min/max operator, we generate 11400 // thisMBB: 11401 // newMBB: 11402 // ld t1 = [min/max.addr] 11403 // mov t2 = [min/max.val] 11404 // cmp t1, t2 11405 // cmov[cond] t2 = t1 11406 // mov EAX = t1 11407 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11408 // bz newMBB 11409 // fallthrough -->nextMBB 11410 // 11411 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11412 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11413 MachineFunction::iterator MBBIter = MBB; 11414 ++MBBIter; 11415 11416 /// First build the CFG 11417 MachineFunction *F = MBB->getParent(); 11418 MachineBasicBlock *thisMBB = MBB; 11419 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11420 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11421 F->insert(MBBIter, newMBB); 11422 F->insert(MBBIter, nextMBB); 11423 11424 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11425 nextMBB->splice(nextMBB->begin(), thisMBB, 11426 llvm::next(MachineBasicBlock::iterator(mInstr)), 11427 thisMBB->end()); 11428 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11429 11430 // Update thisMBB to fall through to newMBB 11431 thisMBB->addSuccessor(newMBB); 11432 11433 // newMBB jumps to newMBB and fall through to nextMBB 11434 newMBB->addSuccessor(nextMBB); 11435 newMBB->addSuccessor(newMBB); 11436 11437 DebugLoc dl = mInstr->getDebugLoc(); 11438 // Insert instructions into newMBB based on incoming instruction 11439 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11440 "unexpected number of operands"); 11441 MachineOperand& destOper = mInstr->getOperand(0); 11442 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11443 int numArgs = mInstr->getNumOperands() - 1; 11444 for (int i=0; i < numArgs; ++i) 11445 argOpers[i] = &mInstr->getOperand(i+1); 11446 11447 // x86 address has 4 operands: base, index, scale, and displacement 11448 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11449 int valArgIndx = lastAddrIndx + 1; 11450 11451 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11452 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11453 for (int i=0; i <= lastAddrIndx; ++i) 11454 (*MIB).addOperand(*argOpers[i]); 11455 11456 // We only support register and immediate values 11457 assert((argOpers[valArgIndx]->isReg() || 11458 argOpers[valArgIndx]->isImm()) && 11459 "invalid operand"); 11460 11461 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11462 if (argOpers[valArgIndx]->isReg()) 11463 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11464 else 11465 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11466 (*MIB).addOperand(*argOpers[valArgIndx]); 11467 11468 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11469 MIB.addReg(t1); 11470 11471 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11472 MIB.addReg(t1); 11473 MIB.addReg(t2); 11474 11475 // Generate movc 11476 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11477 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11478 MIB.addReg(t2); 11479 MIB.addReg(t1); 11480 11481 // Cmp and exchange if none has modified the memory location 11482 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11483 for (int i=0; i <= lastAddrIndx; ++i) 11484 (*MIB).addOperand(*argOpers[i]); 11485 MIB.addReg(t3); 11486 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11487 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11488 mInstr->memoperands_end()); 11489 11490 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11491 MIB.addReg(X86::EAX); 11492 11493 // insert branch 11494 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11495 11496 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11497 return nextMBB; 11498} 11499 11500// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11501// or XMM0_V32I8 in AVX all of this code can be replaced with that 11502// in the .td file. 11503MachineBasicBlock * 11504X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11505 unsigned numArgs, bool memArg) const { 11506 assert(Subtarget->hasSSE42() && 11507 "Target must have SSE4.2 or AVX features enabled"); 11508 11509 DebugLoc dl = MI->getDebugLoc(); 11510 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11511 unsigned Opc; 11512 if (!Subtarget->hasAVX()) { 11513 if (memArg) 11514 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11515 else 11516 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11517 } else { 11518 if (memArg) 11519 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11520 else 11521 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11522 } 11523 11524 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11525 for (unsigned i = 0; i < numArgs; ++i) { 11526 MachineOperand &Op = MI->getOperand(i+1); 11527 if (!(Op.isReg() && Op.isImplicit())) 11528 MIB.addOperand(Op); 11529 } 11530 BuildMI(*BB, MI, dl, 11531 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11532 MI->getOperand(0).getReg()) 11533 .addReg(X86::XMM0); 11534 11535 MI->eraseFromParent(); 11536 return BB; 11537} 11538 11539MachineBasicBlock * 11540X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11541 DebugLoc dl = MI->getDebugLoc(); 11542 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11543 11544 // Address into RAX/EAX, other two args into ECX, EDX. 11545 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11546 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11547 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11548 for (int i = 0; i < X86::AddrNumOperands; ++i) 11549 MIB.addOperand(MI->getOperand(i)); 11550 11551 unsigned ValOps = X86::AddrNumOperands; 11552 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11553 .addReg(MI->getOperand(ValOps).getReg()); 11554 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11555 .addReg(MI->getOperand(ValOps+1).getReg()); 11556 11557 // The instruction doesn't actually take any operands though. 11558 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11559 11560 MI->eraseFromParent(); // The pseudo is gone now. 11561 return BB; 11562} 11563 11564MachineBasicBlock * 11565X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11566 DebugLoc dl = MI->getDebugLoc(); 11567 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11568 11569 // First arg in ECX, the second in EAX. 11570 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11571 .addReg(MI->getOperand(0).getReg()); 11572 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11573 .addReg(MI->getOperand(1).getReg()); 11574 11575 // The instruction doesn't actually take any operands though. 11576 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11577 11578 MI->eraseFromParent(); // The pseudo is gone now. 11579 return BB; 11580} 11581 11582MachineBasicBlock * 11583X86TargetLowering::EmitVAARG64WithCustomInserter( 11584 MachineInstr *MI, 11585 MachineBasicBlock *MBB) const { 11586 // Emit va_arg instruction on X86-64. 11587 11588 // Operands to this pseudo-instruction: 11589 // 0 ) Output : destination address (reg) 11590 // 1-5) Input : va_list address (addr, i64mem) 11591 // 6 ) ArgSize : Size (in bytes) of vararg type 11592 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11593 // 8 ) Align : Alignment of type 11594 // 9 ) EFLAGS (implicit-def) 11595 11596 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11597 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11598 11599 unsigned DestReg = MI->getOperand(0).getReg(); 11600 MachineOperand &Base = MI->getOperand(1); 11601 MachineOperand &Scale = MI->getOperand(2); 11602 MachineOperand &Index = MI->getOperand(3); 11603 MachineOperand &Disp = MI->getOperand(4); 11604 MachineOperand &Segment = MI->getOperand(5); 11605 unsigned ArgSize = MI->getOperand(6).getImm(); 11606 unsigned ArgMode = MI->getOperand(7).getImm(); 11607 unsigned Align = MI->getOperand(8).getImm(); 11608 11609 // Memory Reference 11610 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11611 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11612 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11613 11614 // Machine Information 11615 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11616 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11617 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11618 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11619 DebugLoc DL = MI->getDebugLoc(); 11620 11621 // struct va_list { 11622 // i32 gp_offset 11623 // i32 fp_offset 11624 // i64 overflow_area (address) 11625 // i64 reg_save_area (address) 11626 // } 11627 // sizeof(va_list) = 24 11628 // alignment(va_list) = 8 11629 11630 unsigned TotalNumIntRegs = 6; 11631 unsigned TotalNumXMMRegs = 8; 11632 bool UseGPOffset = (ArgMode == 1); 11633 bool UseFPOffset = (ArgMode == 2); 11634 unsigned MaxOffset = TotalNumIntRegs * 8 + 11635 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11636 11637 /* Align ArgSize to a multiple of 8 */ 11638 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11639 bool NeedsAlign = (Align > 8); 11640 11641 MachineBasicBlock *thisMBB = MBB; 11642 MachineBasicBlock *overflowMBB; 11643 MachineBasicBlock *offsetMBB; 11644 MachineBasicBlock *endMBB; 11645 11646 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11647 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11648 unsigned OffsetReg = 0; 11649 11650 if (!UseGPOffset && !UseFPOffset) { 11651 // If we only pull from the overflow region, we don't create a branch. 11652 // We don't need to alter control flow. 11653 OffsetDestReg = 0; // unused 11654 OverflowDestReg = DestReg; 11655 11656 offsetMBB = NULL; 11657 overflowMBB = thisMBB; 11658 endMBB = thisMBB; 11659 } else { 11660 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11661 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11662 // If not, pull from overflow_area. (branch to overflowMBB) 11663 // 11664 // thisMBB 11665 // | . 11666 // | . 11667 // offsetMBB overflowMBB 11668 // | . 11669 // | . 11670 // endMBB 11671 11672 // Registers for the PHI in endMBB 11673 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11674 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11675 11676 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11677 MachineFunction *MF = MBB->getParent(); 11678 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11679 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11680 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11681 11682 MachineFunction::iterator MBBIter = MBB; 11683 ++MBBIter; 11684 11685 // Insert the new basic blocks 11686 MF->insert(MBBIter, offsetMBB); 11687 MF->insert(MBBIter, overflowMBB); 11688 MF->insert(MBBIter, endMBB); 11689 11690 // Transfer the remainder of MBB and its successor edges to endMBB. 11691 endMBB->splice(endMBB->begin(), thisMBB, 11692 llvm::next(MachineBasicBlock::iterator(MI)), 11693 thisMBB->end()); 11694 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11695 11696 // Make offsetMBB and overflowMBB successors of thisMBB 11697 thisMBB->addSuccessor(offsetMBB); 11698 thisMBB->addSuccessor(overflowMBB); 11699 11700 // endMBB is a successor of both offsetMBB and overflowMBB 11701 offsetMBB->addSuccessor(endMBB); 11702 overflowMBB->addSuccessor(endMBB); 11703 11704 // Load the offset value into a register 11705 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11706 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11707 .addOperand(Base) 11708 .addOperand(Scale) 11709 .addOperand(Index) 11710 .addDisp(Disp, UseFPOffset ? 4 : 0) 11711 .addOperand(Segment) 11712 .setMemRefs(MMOBegin, MMOEnd); 11713 11714 // Check if there is enough room left to pull this argument. 11715 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11716 .addReg(OffsetReg) 11717 .addImm(MaxOffset + 8 - ArgSizeA8); 11718 11719 // Branch to "overflowMBB" if offset >= max 11720 // Fall through to "offsetMBB" otherwise 11721 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11722 .addMBB(overflowMBB); 11723 } 11724 11725 // In offsetMBB, emit code to use the reg_save_area. 11726 if (offsetMBB) { 11727 assert(OffsetReg != 0); 11728 11729 // Read the reg_save_area address. 11730 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11731 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11732 .addOperand(Base) 11733 .addOperand(Scale) 11734 .addOperand(Index) 11735 .addDisp(Disp, 16) 11736 .addOperand(Segment) 11737 .setMemRefs(MMOBegin, MMOEnd); 11738 11739 // Zero-extend the offset 11740 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11741 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11742 .addImm(0) 11743 .addReg(OffsetReg) 11744 .addImm(X86::sub_32bit); 11745 11746 // Add the offset to the reg_save_area to get the final address. 11747 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11748 .addReg(OffsetReg64) 11749 .addReg(RegSaveReg); 11750 11751 // Compute the offset for the next argument 11752 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11753 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11754 .addReg(OffsetReg) 11755 .addImm(UseFPOffset ? 16 : 8); 11756 11757 // Store it back into the va_list. 11758 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11759 .addOperand(Base) 11760 .addOperand(Scale) 11761 .addOperand(Index) 11762 .addDisp(Disp, UseFPOffset ? 4 : 0) 11763 .addOperand(Segment) 11764 .addReg(NextOffsetReg) 11765 .setMemRefs(MMOBegin, MMOEnd); 11766 11767 // Jump to endMBB 11768 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11769 .addMBB(endMBB); 11770 } 11771 11772 // 11773 // Emit code to use overflow area 11774 // 11775 11776 // Load the overflow_area address into a register. 11777 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11778 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11779 .addOperand(Base) 11780 .addOperand(Scale) 11781 .addOperand(Index) 11782 .addDisp(Disp, 8) 11783 .addOperand(Segment) 11784 .setMemRefs(MMOBegin, MMOEnd); 11785 11786 // If we need to align it, do so. Otherwise, just copy the address 11787 // to OverflowDestReg. 11788 if (NeedsAlign) { 11789 // Align the overflow address 11790 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11791 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11792 11793 // aligned_addr = (addr + (align-1)) & ~(align-1) 11794 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11795 .addReg(OverflowAddrReg) 11796 .addImm(Align-1); 11797 11798 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11799 .addReg(TmpReg) 11800 .addImm(~(uint64_t)(Align-1)); 11801 } else { 11802 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11803 .addReg(OverflowAddrReg); 11804 } 11805 11806 // Compute the next overflow address after this argument. 11807 // (the overflow address should be kept 8-byte aligned) 11808 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11809 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11810 .addReg(OverflowDestReg) 11811 .addImm(ArgSizeA8); 11812 11813 // Store the new overflow address. 11814 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11815 .addOperand(Base) 11816 .addOperand(Scale) 11817 .addOperand(Index) 11818 .addDisp(Disp, 8) 11819 .addOperand(Segment) 11820 .addReg(NextAddrReg) 11821 .setMemRefs(MMOBegin, MMOEnd); 11822 11823 // If we branched, emit the PHI to the front of endMBB. 11824 if (offsetMBB) { 11825 BuildMI(*endMBB, endMBB->begin(), DL, 11826 TII->get(X86::PHI), DestReg) 11827 .addReg(OffsetDestReg).addMBB(offsetMBB) 11828 .addReg(OverflowDestReg).addMBB(overflowMBB); 11829 } 11830 11831 // Erase the pseudo instruction 11832 MI->eraseFromParent(); 11833 11834 return endMBB; 11835} 11836 11837MachineBasicBlock * 11838X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11839 MachineInstr *MI, 11840 MachineBasicBlock *MBB) const { 11841 // Emit code to save XMM registers to the stack. The ABI says that the 11842 // number of registers to save is given in %al, so it's theoretically 11843 // possible to do an indirect jump trick to avoid saving all of them, 11844 // however this code takes a simpler approach and just executes all 11845 // of the stores if %al is non-zero. It's less code, and it's probably 11846 // easier on the hardware branch predictor, and stores aren't all that 11847 // expensive anyway. 11848 11849 // Create the new basic blocks. One block contains all the XMM stores, 11850 // and one block is the final destination regardless of whether any 11851 // stores were performed. 11852 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11853 MachineFunction *F = MBB->getParent(); 11854 MachineFunction::iterator MBBIter = MBB; 11855 ++MBBIter; 11856 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11857 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11858 F->insert(MBBIter, XMMSaveMBB); 11859 F->insert(MBBIter, EndMBB); 11860 11861 // Transfer the remainder of MBB and its successor edges to EndMBB. 11862 EndMBB->splice(EndMBB->begin(), MBB, 11863 llvm::next(MachineBasicBlock::iterator(MI)), 11864 MBB->end()); 11865 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11866 11867 // The original block will now fall through to the XMM save block. 11868 MBB->addSuccessor(XMMSaveMBB); 11869 // The XMMSaveMBB will fall through to the end block. 11870 XMMSaveMBB->addSuccessor(EndMBB); 11871 11872 // Now add the instructions. 11873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11874 DebugLoc DL = MI->getDebugLoc(); 11875 11876 unsigned CountReg = MI->getOperand(0).getReg(); 11877 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11878 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11879 11880 if (!Subtarget->isTargetWin64()) { 11881 // If %al is 0, branch around the XMM save block. 11882 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11883 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11884 MBB->addSuccessor(EndMBB); 11885 } 11886 11887 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11888 // In the XMM save block, save all the XMM argument registers. 11889 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11890 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11891 MachineMemOperand *MMO = 11892 F->getMachineMemOperand( 11893 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11894 MachineMemOperand::MOStore, 11895 /*Size=*/16, /*Align=*/16); 11896 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11897 .addFrameIndex(RegSaveFrameIndex) 11898 .addImm(/*Scale=*/1) 11899 .addReg(/*IndexReg=*/0) 11900 .addImm(/*Disp=*/Offset) 11901 .addReg(/*Segment=*/0) 11902 .addReg(MI->getOperand(i).getReg()) 11903 .addMemOperand(MMO); 11904 } 11905 11906 MI->eraseFromParent(); // The pseudo instruction is gone now. 11907 11908 return EndMBB; 11909} 11910 11911MachineBasicBlock * 11912X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11913 MachineBasicBlock *BB) const { 11914 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11915 DebugLoc DL = MI->getDebugLoc(); 11916 11917 // To "insert" a SELECT_CC instruction, we actually have to insert the 11918 // diamond control-flow pattern. The incoming instruction knows the 11919 // destination vreg to set, the condition code register to branch on, the 11920 // true/false values to select between, and a branch opcode to use. 11921 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11922 MachineFunction::iterator It = BB; 11923 ++It; 11924 11925 // thisMBB: 11926 // ... 11927 // TrueVal = ... 11928 // cmpTY ccX, r1, r2 11929 // bCC copy1MBB 11930 // fallthrough --> copy0MBB 11931 MachineBasicBlock *thisMBB = BB; 11932 MachineFunction *F = BB->getParent(); 11933 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11934 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11935 F->insert(It, copy0MBB); 11936 F->insert(It, sinkMBB); 11937 11938 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11939 // live into the sink and copy blocks. 11940 if (!MI->killsRegister(X86::EFLAGS)) { 11941 copy0MBB->addLiveIn(X86::EFLAGS); 11942 sinkMBB->addLiveIn(X86::EFLAGS); 11943 } 11944 11945 // Transfer the remainder of BB and its successor edges to sinkMBB. 11946 sinkMBB->splice(sinkMBB->begin(), BB, 11947 llvm::next(MachineBasicBlock::iterator(MI)), 11948 BB->end()); 11949 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11950 11951 // Add the true and fallthrough blocks as its successors. 11952 BB->addSuccessor(copy0MBB); 11953 BB->addSuccessor(sinkMBB); 11954 11955 // Create the conditional branch instruction. 11956 unsigned Opc = 11957 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11958 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11959 11960 // copy0MBB: 11961 // %FalseValue = ... 11962 // # fallthrough to sinkMBB 11963 copy0MBB->addSuccessor(sinkMBB); 11964 11965 // sinkMBB: 11966 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11967 // ... 11968 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11969 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11970 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11971 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11972 11973 MI->eraseFromParent(); // The pseudo instruction is gone now. 11974 return sinkMBB; 11975} 11976 11977MachineBasicBlock * 11978X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 11979 bool Is64Bit) const { 11980 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11981 DebugLoc DL = MI->getDebugLoc(); 11982 MachineFunction *MF = BB->getParent(); 11983 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11984 11985 assert(getTargetMachine().Options.EnableSegmentedStacks); 11986 11987 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 11988 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 11989 11990 // BB: 11991 // ... [Till the alloca] 11992 // If stacklet is not large enough, jump to mallocMBB 11993 // 11994 // bumpMBB: 11995 // Allocate by subtracting from RSP 11996 // Jump to continueMBB 11997 // 11998 // mallocMBB: 11999 // Allocate by call to runtime 12000 // 12001 // continueMBB: 12002 // ... 12003 // [rest of original BB] 12004 // 12005 12006 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12007 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12008 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 12009 12010 MachineRegisterInfo &MRI = MF->getRegInfo(); 12011 const TargetRegisterClass *AddrRegClass = 12012 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 12013 12014 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12015 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 12016 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 12017 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass), 12018 sizeVReg = MI->getOperand(1).getReg(), 12019 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 12020 12021 MachineFunction::iterator MBBIter = BB; 12022 ++MBBIter; 12023 12024 MF->insert(MBBIter, bumpMBB); 12025 MF->insert(MBBIter, mallocMBB); 12026 MF->insert(MBBIter, continueMBB); 12027 12028 continueMBB->splice(continueMBB->begin(), BB, llvm::next 12029 (MachineBasicBlock::iterator(MI)), BB->end()); 12030 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 12031 12032 // Add code to the main basic block to check if the stack limit has been hit, 12033 // and if so, jump to mallocMBB otherwise to bumpMBB. 12034 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 12035 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) 12036 .addReg(tmpSPVReg).addReg(sizeVReg); 12037 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 12038 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg) 12039 .addReg(SPLimitVReg); 12040 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 12041 12042 // bumpMBB simply decreases the stack pointer, since we know the current 12043 // stacklet has enough space. 12044 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 12045 .addReg(SPLimitVReg); 12046 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 12047 .addReg(SPLimitVReg); 12048 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12049 12050 // Calls into a routine in libgcc to allocate more space from the heap. 12051 if (Is64Bit) { 12052 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 12053 .addReg(sizeVReg); 12054 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 12055 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 12056 } else { 12057 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 12058 .addImm(12); 12059 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 12060 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 12061 .addExternalSymbol("__morestack_allocate_stack_space"); 12062 } 12063 12064 if (!Is64Bit) 12065 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 12066 .addImm(16); 12067 12068 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 12069 .addReg(Is64Bit ? X86::RAX : X86::EAX); 12070 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 12071 12072 // Set up the CFG correctly. 12073 BB->addSuccessor(bumpMBB); 12074 BB->addSuccessor(mallocMBB); 12075 mallocMBB->addSuccessor(continueMBB); 12076 bumpMBB->addSuccessor(continueMBB); 12077 12078 // Take care of the PHI nodes. 12079 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 12080 MI->getOperand(0).getReg()) 12081 .addReg(mallocPtrVReg).addMBB(mallocMBB) 12082 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 12083 12084 // Delete the original pseudo instruction. 12085 MI->eraseFromParent(); 12086 12087 // And we're done. 12088 return continueMBB; 12089} 12090 12091MachineBasicBlock * 12092X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 12093 MachineBasicBlock *BB) const { 12094 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12095 DebugLoc DL = MI->getDebugLoc(); 12096 12097 assert(!Subtarget->isTargetEnvMacho()); 12098 12099 // The lowering is pretty easy: we're just emitting the call to _alloca. The 12100 // non-trivial part is impdef of ESP. 12101 12102 if (Subtarget->isTargetWin64()) { 12103 if (Subtarget->isTargetCygMing()) { 12104 // ___chkstk(Mingw64): 12105 // Clobbers R10, R11, RAX and EFLAGS. 12106 // Updates RSP. 12107 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12108 .addExternalSymbol("___chkstk") 12109 .addReg(X86::RAX, RegState::Implicit) 12110 .addReg(X86::RSP, RegState::Implicit) 12111 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12112 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12113 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12114 } else { 12115 // __chkstk(MSVCRT): does not update stack pointer. 12116 // Clobbers R10, R11 and EFLAGS. 12117 // FIXME: RAX(allocated size) might be reused and not killed. 12118 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 12119 .addExternalSymbol("__chkstk") 12120 .addReg(X86::RAX, RegState::Implicit) 12121 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12122 // RAX has the offset to subtracted from RSP. 12123 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 12124 .addReg(X86::RSP) 12125 .addReg(X86::RAX); 12126 } 12127 } else { 12128 const char *StackProbeSymbol = 12129 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 12130 12131 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 12132 .addExternalSymbol(StackProbeSymbol) 12133 .addReg(X86::EAX, RegState::Implicit) 12134 .addReg(X86::ESP, RegState::Implicit) 12135 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 12136 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 12137 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 12138 } 12139 12140 MI->eraseFromParent(); // The pseudo instruction is gone now. 12141 return BB; 12142} 12143 12144MachineBasicBlock * 12145X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 12146 MachineBasicBlock *BB) const { 12147 // This is pretty easy. We're taking the value that we received from 12148 // our load from the relocation, sticking it in either RDI (x86-64) 12149 // or EAX and doing an indirect call. The return value will then 12150 // be in the normal return register. 12151 const X86InstrInfo *TII 12152 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 12153 DebugLoc DL = MI->getDebugLoc(); 12154 MachineFunction *F = BB->getParent(); 12155 12156 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 12157 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 12158 12159 if (Subtarget->is64Bit()) { 12160 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12161 TII->get(X86::MOV64rm), X86::RDI) 12162 .addReg(X86::RIP) 12163 .addImm(0).addReg(0) 12164 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12165 MI->getOperand(3).getTargetFlags()) 12166 .addReg(0); 12167 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 12168 addDirectMem(MIB, X86::RDI); 12169 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 12170 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12171 TII->get(X86::MOV32rm), X86::EAX) 12172 .addReg(0) 12173 .addImm(0).addReg(0) 12174 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12175 MI->getOperand(3).getTargetFlags()) 12176 .addReg(0); 12177 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12178 addDirectMem(MIB, X86::EAX); 12179 } else { 12180 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 12181 TII->get(X86::MOV32rm), X86::EAX) 12182 .addReg(TII->getGlobalBaseReg(F)) 12183 .addImm(0).addReg(0) 12184 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 12185 MI->getOperand(3).getTargetFlags()) 12186 .addReg(0); 12187 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 12188 addDirectMem(MIB, X86::EAX); 12189 } 12190 12191 MI->eraseFromParent(); // The pseudo instruction is gone now. 12192 return BB; 12193} 12194 12195MachineBasicBlock * 12196X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 12197 MachineBasicBlock *BB) const { 12198 switch (MI->getOpcode()) { 12199 default: assert(0 && "Unexpected instr type to insert"); 12200 case X86::TAILJMPd64: 12201 case X86::TAILJMPr64: 12202 case X86::TAILJMPm64: 12203 assert(0 && "TAILJMP64 would not be touched here."); 12204 case X86::TCRETURNdi64: 12205 case X86::TCRETURNri64: 12206 case X86::TCRETURNmi64: 12207 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 12208 // On AMD64, additional defs should be added before register allocation. 12209 if (!Subtarget->isTargetWin64()) { 12210 MI->addRegisterDefined(X86::RSI); 12211 MI->addRegisterDefined(X86::RDI); 12212 MI->addRegisterDefined(X86::XMM6); 12213 MI->addRegisterDefined(X86::XMM7); 12214 MI->addRegisterDefined(X86::XMM8); 12215 MI->addRegisterDefined(X86::XMM9); 12216 MI->addRegisterDefined(X86::XMM10); 12217 MI->addRegisterDefined(X86::XMM11); 12218 MI->addRegisterDefined(X86::XMM12); 12219 MI->addRegisterDefined(X86::XMM13); 12220 MI->addRegisterDefined(X86::XMM14); 12221 MI->addRegisterDefined(X86::XMM15); 12222 } 12223 return BB; 12224 case X86::WIN_ALLOCA: 12225 return EmitLoweredWinAlloca(MI, BB); 12226 case X86::SEG_ALLOCA_32: 12227 return EmitLoweredSegAlloca(MI, BB, false); 12228 case X86::SEG_ALLOCA_64: 12229 return EmitLoweredSegAlloca(MI, BB, true); 12230 case X86::TLSCall_32: 12231 case X86::TLSCall_64: 12232 return EmitLoweredTLSCall(MI, BB); 12233 case X86::CMOV_GR8: 12234 case X86::CMOV_FR32: 12235 case X86::CMOV_FR64: 12236 case X86::CMOV_V4F32: 12237 case X86::CMOV_V2F64: 12238 case X86::CMOV_V2I64: 12239 case X86::CMOV_V8F32: 12240 case X86::CMOV_V4F64: 12241 case X86::CMOV_V4I64: 12242 case X86::CMOV_GR16: 12243 case X86::CMOV_GR32: 12244 case X86::CMOV_RFP32: 12245 case X86::CMOV_RFP64: 12246 case X86::CMOV_RFP80: 12247 return EmitLoweredSelect(MI, BB); 12248 12249 case X86::FP32_TO_INT16_IN_MEM: 12250 case X86::FP32_TO_INT32_IN_MEM: 12251 case X86::FP32_TO_INT64_IN_MEM: 12252 case X86::FP64_TO_INT16_IN_MEM: 12253 case X86::FP64_TO_INT32_IN_MEM: 12254 case X86::FP64_TO_INT64_IN_MEM: 12255 case X86::FP80_TO_INT16_IN_MEM: 12256 case X86::FP80_TO_INT32_IN_MEM: 12257 case X86::FP80_TO_INT64_IN_MEM: { 12258 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12259 DebugLoc DL = MI->getDebugLoc(); 12260 12261 // Change the floating point control register to use "round towards zero" 12262 // mode when truncating to an integer value. 12263 MachineFunction *F = BB->getParent(); 12264 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12265 addFrameReference(BuildMI(*BB, MI, DL, 12266 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12267 12268 // Load the old value of the high byte of the control word... 12269 unsigned OldCW = 12270 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12271 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12272 CWFrameIdx); 12273 12274 // Set the high part to be round to zero... 12275 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12276 .addImm(0xC7F); 12277 12278 // Reload the modified control word now... 12279 addFrameReference(BuildMI(*BB, MI, DL, 12280 TII->get(X86::FLDCW16m)), CWFrameIdx); 12281 12282 // Restore the memory image of control word to original value 12283 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12284 .addReg(OldCW); 12285 12286 // Get the X86 opcode to use. 12287 unsigned Opc; 12288 switch (MI->getOpcode()) { 12289 default: llvm_unreachable("illegal opcode!"); 12290 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12291 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12292 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12293 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12294 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12295 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12296 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12297 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12298 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12299 } 12300 12301 X86AddressMode AM; 12302 MachineOperand &Op = MI->getOperand(0); 12303 if (Op.isReg()) { 12304 AM.BaseType = X86AddressMode::RegBase; 12305 AM.Base.Reg = Op.getReg(); 12306 } else { 12307 AM.BaseType = X86AddressMode::FrameIndexBase; 12308 AM.Base.FrameIndex = Op.getIndex(); 12309 } 12310 Op = MI->getOperand(1); 12311 if (Op.isImm()) 12312 AM.Scale = Op.getImm(); 12313 Op = MI->getOperand(2); 12314 if (Op.isImm()) 12315 AM.IndexReg = Op.getImm(); 12316 Op = MI->getOperand(3); 12317 if (Op.isGlobal()) { 12318 AM.GV = Op.getGlobal(); 12319 } else { 12320 AM.Disp = Op.getImm(); 12321 } 12322 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12323 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12324 12325 // Reload the original control word now. 12326 addFrameReference(BuildMI(*BB, MI, DL, 12327 TII->get(X86::FLDCW16m)), CWFrameIdx); 12328 12329 MI->eraseFromParent(); // The pseudo instruction is gone now. 12330 return BB; 12331 } 12332 // String/text processing lowering. 12333 case X86::PCMPISTRM128REG: 12334 case X86::VPCMPISTRM128REG: 12335 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12336 case X86::PCMPISTRM128MEM: 12337 case X86::VPCMPISTRM128MEM: 12338 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12339 case X86::PCMPESTRM128REG: 12340 case X86::VPCMPESTRM128REG: 12341 return EmitPCMP(MI, BB, 5, false /* in mem */); 12342 case X86::PCMPESTRM128MEM: 12343 case X86::VPCMPESTRM128MEM: 12344 return EmitPCMP(MI, BB, 5, true /* in mem */); 12345 12346 // Thread synchronization. 12347 case X86::MONITOR: 12348 return EmitMonitor(MI, BB); 12349 case X86::MWAIT: 12350 return EmitMwait(MI, BB); 12351 12352 // Atomic Lowering. 12353 case X86::ATOMAND32: 12354 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12355 X86::AND32ri, X86::MOV32rm, 12356 X86::LCMPXCHG32, 12357 X86::NOT32r, X86::EAX, 12358 X86::GR32RegisterClass); 12359 case X86::ATOMOR32: 12360 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12361 X86::OR32ri, X86::MOV32rm, 12362 X86::LCMPXCHG32, 12363 X86::NOT32r, X86::EAX, 12364 X86::GR32RegisterClass); 12365 case X86::ATOMXOR32: 12366 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12367 X86::XOR32ri, X86::MOV32rm, 12368 X86::LCMPXCHG32, 12369 X86::NOT32r, X86::EAX, 12370 X86::GR32RegisterClass); 12371 case X86::ATOMNAND32: 12372 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12373 X86::AND32ri, X86::MOV32rm, 12374 X86::LCMPXCHG32, 12375 X86::NOT32r, X86::EAX, 12376 X86::GR32RegisterClass, true); 12377 case X86::ATOMMIN32: 12378 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12379 case X86::ATOMMAX32: 12380 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12381 case X86::ATOMUMIN32: 12382 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12383 case X86::ATOMUMAX32: 12384 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12385 12386 case X86::ATOMAND16: 12387 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12388 X86::AND16ri, X86::MOV16rm, 12389 X86::LCMPXCHG16, 12390 X86::NOT16r, X86::AX, 12391 X86::GR16RegisterClass); 12392 case X86::ATOMOR16: 12393 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12394 X86::OR16ri, X86::MOV16rm, 12395 X86::LCMPXCHG16, 12396 X86::NOT16r, X86::AX, 12397 X86::GR16RegisterClass); 12398 case X86::ATOMXOR16: 12399 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12400 X86::XOR16ri, X86::MOV16rm, 12401 X86::LCMPXCHG16, 12402 X86::NOT16r, X86::AX, 12403 X86::GR16RegisterClass); 12404 case X86::ATOMNAND16: 12405 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12406 X86::AND16ri, X86::MOV16rm, 12407 X86::LCMPXCHG16, 12408 X86::NOT16r, X86::AX, 12409 X86::GR16RegisterClass, true); 12410 case X86::ATOMMIN16: 12411 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12412 case X86::ATOMMAX16: 12413 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12414 case X86::ATOMUMIN16: 12415 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12416 case X86::ATOMUMAX16: 12417 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12418 12419 case X86::ATOMAND8: 12420 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12421 X86::AND8ri, X86::MOV8rm, 12422 X86::LCMPXCHG8, 12423 X86::NOT8r, X86::AL, 12424 X86::GR8RegisterClass); 12425 case X86::ATOMOR8: 12426 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12427 X86::OR8ri, X86::MOV8rm, 12428 X86::LCMPXCHG8, 12429 X86::NOT8r, X86::AL, 12430 X86::GR8RegisterClass); 12431 case X86::ATOMXOR8: 12432 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12433 X86::XOR8ri, X86::MOV8rm, 12434 X86::LCMPXCHG8, 12435 X86::NOT8r, X86::AL, 12436 X86::GR8RegisterClass); 12437 case X86::ATOMNAND8: 12438 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12439 X86::AND8ri, X86::MOV8rm, 12440 X86::LCMPXCHG8, 12441 X86::NOT8r, X86::AL, 12442 X86::GR8RegisterClass, true); 12443 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12444 // This group is for 64-bit host. 12445 case X86::ATOMAND64: 12446 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12447 X86::AND64ri32, X86::MOV64rm, 12448 X86::LCMPXCHG64, 12449 X86::NOT64r, X86::RAX, 12450 X86::GR64RegisterClass); 12451 case X86::ATOMOR64: 12452 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12453 X86::OR64ri32, X86::MOV64rm, 12454 X86::LCMPXCHG64, 12455 X86::NOT64r, X86::RAX, 12456 X86::GR64RegisterClass); 12457 case X86::ATOMXOR64: 12458 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12459 X86::XOR64ri32, X86::MOV64rm, 12460 X86::LCMPXCHG64, 12461 X86::NOT64r, X86::RAX, 12462 X86::GR64RegisterClass); 12463 case X86::ATOMNAND64: 12464 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12465 X86::AND64ri32, X86::MOV64rm, 12466 X86::LCMPXCHG64, 12467 X86::NOT64r, X86::RAX, 12468 X86::GR64RegisterClass, true); 12469 case X86::ATOMMIN64: 12470 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12471 case X86::ATOMMAX64: 12472 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12473 case X86::ATOMUMIN64: 12474 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12475 case X86::ATOMUMAX64: 12476 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12477 12478 // This group does 64-bit operations on a 32-bit host. 12479 case X86::ATOMAND6432: 12480 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12481 X86::AND32rr, X86::AND32rr, 12482 X86::AND32ri, X86::AND32ri, 12483 false); 12484 case X86::ATOMOR6432: 12485 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12486 X86::OR32rr, X86::OR32rr, 12487 X86::OR32ri, X86::OR32ri, 12488 false); 12489 case X86::ATOMXOR6432: 12490 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12491 X86::XOR32rr, X86::XOR32rr, 12492 X86::XOR32ri, X86::XOR32ri, 12493 false); 12494 case X86::ATOMNAND6432: 12495 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12496 X86::AND32rr, X86::AND32rr, 12497 X86::AND32ri, X86::AND32ri, 12498 true); 12499 case X86::ATOMADD6432: 12500 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12501 X86::ADD32rr, X86::ADC32rr, 12502 X86::ADD32ri, X86::ADC32ri, 12503 false); 12504 case X86::ATOMSUB6432: 12505 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12506 X86::SUB32rr, X86::SBB32rr, 12507 X86::SUB32ri, X86::SBB32ri, 12508 false); 12509 case X86::ATOMSWAP6432: 12510 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12511 X86::MOV32rr, X86::MOV32rr, 12512 X86::MOV32ri, X86::MOV32ri, 12513 false); 12514 case X86::VASTART_SAVE_XMM_REGS: 12515 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12516 12517 case X86::VAARG_64: 12518 return EmitVAARG64WithCustomInserter(MI, BB); 12519 } 12520} 12521 12522//===----------------------------------------------------------------------===// 12523// X86 Optimization Hooks 12524//===----------------------------------------------------------------------===// 12525 12526void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12527 const APInt &Mask, 12528 APInt &KnownZero, 12529 APInt &KnownOne, 12530 const SelectionDAG &DAG, 12531 unsigned Depth) const { 12532 unsigned Opc = Op.getOpcode(); 12533 assert((Opc >= ISD::BUILTIN_OP_END || 12534 Opc == ISD::INTRINSIC_WO_CHAIN || 12535 Opc == ISD::INTRINSIC_W_CHAIN || 12536 Opc == ISD::INTRINSIC_VOID) && 12537 "Should use MaskedValueIsZero if you don't know whether Op" 12538 " is a target node!"); 12539 12540 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12541 switch (Opc) { 12542 default: break; 12543 case X86ISD::ADD: 12544 case X86ISD::SUB: 12545 case X86ISD::ADC: 12546 case X86ISD::SBB: 12547 case X86ISD::SMUL: 12548 case X86ISD::UMUL: 12549 case X86ISD::INC: 12550 case X86ISD::DEC: 12551 case X86ISD::OR: 12552 case X86ISD::XOR: 12553 case X86ISD::AND: 12554 // These nodes' second result is a boolean. 12555 if (Op.getResNo() == 0) 12556 break; 12557 // Fallthrough 12558 case X86ISD::SETCC: 12559 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12560 Mask.getBitWidth() - 1); 12561 break; 12562 case ISD::INTRINSIC_WO_CHAIN: { 12563 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12564 unsigned NumLoBits = 0; 12565 switch (IntId) { 12566 default: break; 12567 case Intrinsic::x86_sse_movmsk_ps: 12568 case Intrinsic::x86_avx_movmsk_ps_256: 12569 case Intrinsic::x86_sse2_movmsk_pd: 12570 case Intrinsic::x86_avx_movmsk_pd_256: 12571 case Intrinsic::x86_mmx_pmovmskb: 12572 case Intrinsic::x86_sse2_pmovmskb_128: 12573 case Intrinsic::x86_avx2_pmovmskb: { 12574 // High bits of movmskp{s|d}, pmovmskb are known zero. 12575 switch (IntId) { 12576 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12577 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12578 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12579 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12580 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12581 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12582 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break; 12583 } 12584 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12585 Mask.getBitWidth() - NumLoBits); 12586 break; 12587 } 12588 } 12589 break; 12590 } 12591 } 12592} 12593 12594unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12595 unsigned Depth) const { 12596 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12597 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12598 return Op.getValueType().getScalarType().getSizeInBits(); 12599 12600 // Fallback case. 12601 return 1; 12602} 12603 12604/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12605/// node is a GlobalAddress + offset. 12606bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12607 const GlobalValue* &GA, 12608 int64_t &Offset) const { 12609 if (N->getOpcode() == X86ISD::Wrapper) { 12610 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12611 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12612 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12613 return true; 12614 } 12615 } 12616 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12617} 12618 12619/// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12620/// same as extracting the high 128-bit part of 256-bit vector and then 12621/// inserting the result into the low part of a new 256-bit vector 12622static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12623 EVT VT = SVOp->getValueType(0); 12624 int NumElems = VT.getVectorNumElements(); 12625 12626 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12627 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12628 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12629 SVOp->getMaskElt(j) >= 0) 12630 return false; 12631 12632 return true; 12633} 12634 12635/// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12636/// same as extracting the low 128-bit part of 256-bit vector and then 12637/// inserting the result into the high part of a new 256-bit vector 12638static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12639 EVT VT = SVOp->getValueType(0); 12640 int NumElems = VT.getVectorNumElements(); 12641 12642 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12643 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12644 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12645 SVOp->getMaskElt(j) >= 0) 12646 return false; 12647 12648 return true; 12649} 12650 12651/// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12652static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12653 TargetLowering::DAGCombinerInfo &DCI, 12654 bool HasAVX2) { 12655 DebugLoc dl = N->getDebugLoc(); 12656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12657 SDValue V1 = SVOp->getOperand(0); 12658 SDValue V2 = SVOp->getOperand(1); 12659 EVT VT = SVOp->getValueType(0); 12660 int NumElems = VT.getVectorNumElements(); 12661 12662 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12663 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12664 // 12665 // 0,0,0,... 12666 // | 12667 // V UNDEF BUILD_VECTOR UNDEF 12668 // \ / \ / 12669 // CONCAT_VECTOR CONCAT_VECTOR 12670 // \ / 12671 // \ / 12672 // RESULT: V + zero extended 12673 // 12674 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12675 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12676 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12677 return SDValue(); 12678 12679 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12680 return SDValue(); 12681 12682 // To match the shuffle mask, the first half of the mask should 12683 // be exactly the first vector, and all the rest a splat with the 12684 // first element of the second one. 12685 for (int i = 0; i < NumElems/2; ++i) 12686 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12687 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12688 return SDValue(); 12689 12690 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD. 12691 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) { 12692 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other); 12693 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() }; 12694 SDValue ResNode = 12695 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2, 12696 Ld->getMemoryVT(), 12697 Ld->getPointerInfo(), 12698 Ld->getAlignment(), 12699 false/*isVolatile*/, true/*ReadMem*/, 12700 false/*WriteMem*/); 12701 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode); 12702 } 12703 12704 // Emit a zeroed vector and insert the desired subvector on its 12705 // first half. 12706 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl); 12707 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12708 DAG.getConstant(0, MVT::i32), DAG, dl); 12709 return DCI.CombineTo(N, InsV); 12710 } 12711 12712 //===--------------------------------------------------------------------===// 12713 // Combine some shuffles into subvector extracts and inserts: 12714 // 12715 12716 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12717 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12718 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12719 DAG, dl); 12720 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12721 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12722 return DCI.CombineTo(N, InsV); 12723 } 12724 12725 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12726 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12727 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12728 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12729 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12730 return DCI.CombineTo(N, InsV); 12731 } 12732 12733 return SDValue(); 12734} 12735 12736/// PerformShuffleCombine - Performs several different shuffle combines. 12737static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12738 TargetLowering::DAGCombinerInfo &DCI, 12739 const X86Subtarget *Subtarget) { 12740 DebugLoc dl = N->getDebugLoc(); 12741 EVT VT = N->getValueType(0); 12742 12743 // Don't create instructions with illegal types after legalize types has run. 12744 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12745 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12746 return SDValue(); 12747 12748 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12749 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12750 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12751 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2()); 12752 12753 // Only handle 128 wide vector from here on. 12754 if (VT.getSizeInBits() != 128) 12755 return SDValue(); 12756 12757 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12758 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12759 // consecutive, non-overlapping, and in the right order. 12760 SmallVector<SDValue, 16> Elts; 12761 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12762 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12763 12764 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12765} 12766 12767/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12768/// generation and convert it from being a bunch of shuffles and extracts 12769/// to a simple store and scalar loads to extract the elements. 12770static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12771 const TargetLowering &TLI) { 12772 SDValue InputVector = N->getOperand(0); 12773 12774 // Only operate on vectors of 4 elements, where the alternative shuffling 12775 // gets to be more expensive. 12776 if (InputVector.getValueType() != MVT::v4i32) 12777 return SDValue(); 12778 12779 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12780 // single use which is a sign-extend or zero-extend, and all elements are 12781 // used. 12782 SmallVector<SDNode *, 4> Uses; 12783 unsigned ExtractedElements = 0; 12784 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12785 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12786 if (UI.getUse().getResNo() != InputVector.getResNo()) 12787 return SDValue(); 12788 12789 SDNode *Extract = *UI; 12790 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12791 return SDValue(); 12792 12793 if (Extract->getValueType(0) != MVT::i32) 12794 return SDValue(); 12795 if (!Extract->hasOneUse()) 12796 return SDValue(); 12797 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12798 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12799 return SDValue(); 12800 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12801 return SDValue(); 12802 12803 // Record which element was extracted. 12804 ExtractedElements |= 12805 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12806 12807 Uses.push_back(Extract); 12808 } 12809 12810 // If not all the elements were used, this may not be worthwhile. 12811 if (ExtractedElements != 15) 12812 return SDValue(); 12813 12814 // Ok, we've now decided to do the transformation. 12815 DebugLoc dl = InputVector.getDebugLoc(); 12816 12817 // Store the value to a temporary stack slot. 12818 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12819 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12820 MachinePointerInfo(), false, false, 0); 12821 12822 // Replace each use (extract) with a load of the appropriate element. 12823 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12824 UE = Uses.end(); UI != UE; ++UI) { 12825 SDNode *Extract = *UI; 12826 12827 // cOMpute the element's address. 12828 SDValue Idx = Extract->getOperand(1); 12829 unsigned EltSize = 12830 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12831 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12832 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12833 12834 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12835 StackPtr, OffsetVal); 12836 12837 // Load the scalar. 12838 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12839 ScalarAddr, MachinePointerInfo(), 12840 false, false, false, 0); 12841 12842 // Replace the exact with the load. 12843 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12844 } 12845 12846 // The replacement was made in place; don't return anything. 12847 return SDValue(); 12848} 12849 12850/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12851/// nodes. 12852static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12853 TargetLowering::DAGCombinerInfo &DCI, 12854 const X86Subtarget *Subtarget) { 12855 DebugLoc DL = N->getDebugLoc(); 12856 SDValue Cond = N->getOperand(0); 12857 // Get the LHS/RHS of the select. 12858 SDValue LHS = N->getOperand(1); 12859 SDValue RHS = N->getOperand(2); 12860 EVT VT = LHS.getValueType(); 12861 12862 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12863 // instructions match the semantics of the common C idiom x<y?x:y but not 12864 // x<=y?x:y, because of how they handle negative zero (which can be 12865 // ignored in unsafe-math mode). 12866 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 12867 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 12868 (Subtarget->hasSSE2() || 12869 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 12870 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12871 12872 unsigned Opcode = 0; 12873 // Check for x CC y ? x : y. 12874 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12875 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12876 switch (CC) { 12877 default: break; 12878 case ISD::SETULT: 12879 // Converting this to a min would handle NaNs incorrectly, and swapping 12880 // the operands would cause it to handle comparisons between positive 12881 // and negative zero incorrectly. 12882 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12883 if (!DAG.getTarget().Options.UnsafeFPMath && 12884 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12885 break; 12886 std::swap(LHS, RHS); 12887 } 12888 Opcode = X86ISD::FMIN; 12889 break; 12890 case ISD::SETOLE: 12891 // Converting this to a min would handle comparisons between positive 12892 // and negative zero incorrectly. 12893 if (!DAG.getTarget().Options.UnsafeFPMath && 12894 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12895 break; 12896 Opcode = X86ISD::FMIN; 12897 break; 12898 case ISD::SETULE: 12899 // Converting this to a min would handle both negative zeros and NaNs 12900 // incorrectly, but we can swap the operands to fix both. 12901 std::swap(LHS, RHS); 12902 case ISD::SETOLT: 12903 case ISD::SETLT: 12904 case ISD::SETLE: 12905 Opcode = X86ISD::FMIN; 12906 break; 12907 12908 case ISD::SETOGE: 12909 // Converting this to a max would handle comparisons between positive 12910 // and negative zero incorrectly. 12911 if (!DAG.getTarget().Options.UnsafeFPMath && 12912 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12913 break; 12914 Opcode = X86ISD::FMAX; 12915 break; 12916 case ISD::SETUGT: 12917 // Converting this to a max would handle NaNs incorrectly, and swapping 12918 // the operands would cause it to handle comparisons between positive 12919 // and negative zero incorrectly. 12920 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12921 if (!DAG.getTarget().Options.UnsafeFPMath && 12922 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12923 break; 12924 std::swap(LHS, RHS); 12925 } 12926 Opcode = X86ISD::FMAX; 12927 break; 12928 case ISD::SETUGE: 12929 // Converting this to a max would handle both negative zeros and NaNs 12930 // incorrectly, but we can swap the operands to fix both. 12931 std::swap(LHS, RHS); 12932 case ISD::SETOGT: 12933 case ISD::SETGT: 12934 case ISD::SETGE: 12935 Opcode = X86ISD::FMAX; 12936 break; 12937 } 12938 // Check for x CC y ? y : x -- a min/max with reversed arms. 12939 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12940 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12941 switch (CC) { 12942 default: break; 12943 case ISD::SETOGE: 12944 // Converting this to a min would handle comparisons between positive 12945 // and negative zero incorrectly, and swapping the operands would 12946 // cause it to handle NaNs incorrectly. 12947 if (!DAG.getTarget().Options.UnsafeFPMath && 12948 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12949 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12950 break; 12951 std::swap(LHS, RHS); 12952 } 12953 Opcode = X86ISD::FMIN; 12954 break; 12955 case ISD::SETUGT: 12956 // Converting this to a min would handle NaNs incorrectly. 12957 if (!DAG.getTarget().Options.UnsafeFPMath && 12958 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12959 break; 12960 Opcode = X86ISD::FMIN; 12961 break; 12962 case ISD::SETUGE: 12963 // Converting this to a min would handle both negative zeros and NaNs 12964 // incorrectly, but we can swap the operands to fix both. 12965 std::swap(LHS, RHS); 12966 case ISD::SETOGT: 12967 case ISD::SETGT: 12968 case ISD::SETGE: 12969 Opcode = X86ISD::FMIN; 12970 break; 12971 12972 case ISD::SETULT: 12973 // Converting this to a max would handle NaNs incorrectly. 12974 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12975 break; 12976 Opcode = X86ISD::FMAX; 12977 break; 12978 case ISD::SETOLE: 12979 // Converting this to a max would handle comparisons between positive 12980 // and negative zero incorrectly, and swapping the operands would 12981 // cause it to handle NaNs incorrectly. 12982 if (!DAG.getTarget().Options.UnsafeFPMath && 12983 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 12984 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12985 break; 12986 std::swap(LHS, RHS); 12987 } 12988 Opcode = X86ISD::FMAX; 12989 break; 12990 case ISD::SETULE: 12991 // Converting this to a max would handle both negative zeros and NaNs 12992 // incorrectly, but we can swap the operands to fix both. 12993 std::swap(LHS, RHS); 12994 case ISD::SETOLT: 12995 case ISD::SETLT: 12996 case ISD::SETLE: 12997 Opcode = X86ISD::FMAX; 12998 break; 12999 } 13000 } 13001 13002 if (Opcode) 13003 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 13004 } 13005 13006 // If this is a select between two integer constants, try to do some 13007 // optimizations. 13008 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 13009 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 13010 // Don't do this for crazy integer types. 13011 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 13012 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 13013 // so that TrueC (the true value) is larger than FalseC. 13014 bool NeedsCondInvert = false; 13015 13016 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 13017 // Efficiently invertible. 13018 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 13019 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 13020 isa<ConstantSDNode>(Cond.getOperand(1))))) { 13021 NeedsCondInvert = true; 13022 std::swap(TrueC, FalseC); 13023 } 13024 13025 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 13026 if (FalseC->getAPIntValue() == 0 && 13027 TrueC->getAPIntValue().isPowerOf2()) { 13028 if (NeedsCondInvert) // Invert the condition if needed. 13029 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13030 DAG.getConstant(1, Cond.getValueType())); 13031 13032 // Zero extend the condition if needed. 13033 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 13034 13035 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13036 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 13037 DAG.getConstant(ShAmt, MVT::i8)); 13038 } 13039 13040 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 13041 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13042 if (NeedsCondInvert) // Invert the condition if needed. 13043 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13044 DAG.getConstant(1, Cond.getValueType())); 13045 13046 // Zero extend the condition if needed. 13047 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13048 FalseC->getValueType(0), Cond); 13049 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13050 SDValue(FalseC, 0)); 13051 } 13052 13053 // Optimize cases that will turn into an LEA instruction. This requires 13054 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13055 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13056 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13057 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13058 13059 bool isFastMultiplier = false; 13060 if (Diff < 10) { 13061 switch ((unsigned char)Diff) { 13062 default: break; 13063 case 1: // result = add base, cond 13064 case 2: // result = lea base( , cond*2) 13065 case 3: // result = lea base(cond, cond*2) 13066 case 4: // result = lea base( , cond*4) 13067 case 5: // result = lea base(cond, cond*4) 13068 case 8: // result = lea base( , cond*8) 13069 case 9: // result = lea base(cond, cond*8) 13070 isFastMultiplier = true; 13071 break; 13072 } 13073 } 13074 13075 if (isFastMultiplier) { 13076 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13077 if (NeedsCondInvert) // Invert the condition if needed. 13078 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 13079 DAG.getConstant(1, Cond.getValueType())); 13080 13081 // Zero extend the condition if needed. 13082 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13083 Cond); 13084 // Scale the condition by the difference. 13085 if (Diff != 1) 13086 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13087 DAG.getConstant(Diff, Cond.getValueType())); 13088 13089 // Add the base if non-zero. 13090 if (FalseC->getAPIntValue() != 0) 13091 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13092 SDValue(FalseC, 0)); 13093 return Cond; 13094 } 13095 } 13096 } 13097 } 13098 13099 // Canonicalize max and min: 13100 // (x > y) ? x : y -> (x >= y) ? x : y 13101 // (x < y) ? x : y -> (x <= y) ? x : y 13102 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates 13103 // the need for an extra compare 13104 // against zero. e.g. 13105 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0 13106 // subl %esi, %edi 13107 // testl %edi, %edi 13108 // movl $0, %eax 13109 // cmovgl %edi, %eax 13110 // => 13111 // xorl %eax, %eax 13112 // subl %esi, $edi 13113 // cmovsl %eax, %edi 13114 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC && 13115 DAG.isEqualTo(LHS, Cond.getOperand(0)) && 13116 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 13117 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 13118 switch (CC) { 13119 default: break; 13120 case ISD::SETLT: 13121 case ISD::SETGT: { 13122 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE; 13123 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(), 13124 Cond.getOperand(0), Cond.getOperand(1), NewCC); 13125 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS); 13126 } 13127 } 13128 } 13129 13130 // If we know that this node is legal then we know that it is going to be 13131 // matched by one of the SSE/AVX BLEND instructions. These instructions only 13132 // depend on the highest bit in each word. Try to use SimplifyDemandedBits 13133 // to simplify previous instructions. 13134 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13135 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && 13136 !DCI.isBeforeLegalize() && 13137 TLI.isOperationLegal(ISD::VSELECT, VT)) { 13138 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits(); 13139 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); 13140 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1); 13141 13142 APInt KnownZero, KnownOne; 13143 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), 13144 DCI.isBeforeLegalizeOps()); 13145 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) || 13146 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO)) 13147 DCI.CommitTargetLoweringOpt(TLO); 13148 } 13149 13150 return SDValue(); 13151} 13152 13153/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 13154static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 13155 TargetLowering::DAGCombinerInfo &DCI) { 13156 DebugLoc DL = N->getDebugLoc(); 13157 13158 // If the flag operand isn't dead, don't touch this CMOV. 13159 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 13160 return SDValue(); 13161 13162 SDValue FalseOp = N->getOperand(0); 13163 SDValue TrueOp = N->getOperand(1); 13164 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 13165 SDValue Cond = N->getOperand(3); 13166 if (CC == X86::COND_E || CC == X86::COND_NE) { 13167 switch (Cond.getOpcode()) { 13168 default: break; 13169 case X86ISD::BSR: 13170 case X86ISD::BSF: 13171 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 13172 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 13173 return (CC == X86::COND_E) ? FalseOp : TrueOp; 13174 } 13175 } 13176 13177 // If this is a select between two integer constants, try to do some 13178 // optimizations. Note that the operands are ordered the opposite of SELECT 13179 // operands. 13180 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 13181 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 13182 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 13183 // larger than FalseC (the false value). 13184 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 13185 CC = X86::GetOppositeBranchCondition(CC); 13186 std::swap(TrueC, FalseC); 13187 } 13188 13189 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 13190 // This is efficient for any integer data type (including i8/i16) and 13191 // shift amount. 13192 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 13193 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13194 DAG.getConstant(CC, MVT::i8), Cond); 13195 13196 // Zero extend the condition if needed. 13197 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 13198 13199 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 13200 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 13201 DAG.getConstant(ShAmt, MVT::i8)); 13202 if (N->getNumValues() == 2) // Dead flag value? 13203 return DCI.CombineTo(N, Cond, SDValue()); 13204 return Cond; 13205 } 13206 13207 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 13208 // for any integer data type, including i8/i16. 13209 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 13210 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13211 DAG.getConstant(CC, MVT::i8), Cond); 13212 13213 // Zero extend the condition if needed. 13214 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 13215 FalseC->getValueType(0), Cond); 13216 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13217 SDValue(FalseC, 0)); 13218 13219 if (N->getNumValues() == 2) // Dead flag value? 13220 return DCI.CombineTo(N, Cond, SDValue()); 13221 return Cond; 13222 } 13223 13224 // Optimize cases that will turn into an LEA instruction. This requires 13225 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 13226 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 13227 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 13228 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 13229 13230 bool isFastMultiplier = false; 13231 if (Diff < 10) { 13232 switch ((unsigned char)Diff) { 13233 default: break; 13234 case 1: // result = add base, cond 13235 case 2: // result = lea base( , cond*2) 13236 case 3: // result = lea base(cond, cond*2) 13237 case 4: // result = lea base( , cond*4) 13238 case 5: // result = lea base(cond, cond*4) 13239 case 8: // result = lea base( , cond*8) 13240 case 9: // result = lea base(cond, cond*8) 13241 isFastMultiplier = true; 13242 break; 13243 } 13244 } 13245 13246 if (isFastMultiplier) { 13247 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 13248 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 13249 DAG.getConstant(CC, MVT::i8), Cond); 13250 // Zero extend the condition if needed. 13251 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 13252 Cond); 13253 // Scale the condition by the difference. 13254 if (Diff != 1) 13255 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 13256 DAG.getConstant(Diff, Cond.getValueType())); 13257 13258 // Add the base if non-zero. 13259 if (FalseC->getAPIntValue() != 0) 13260 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 13261 SDValue(FalseC, 0)); 13262 if (N->getNumValues() == 2) // Dead flag value? 13263 return DCI.CombineTo(N, Cond, SDValue()); 13264 return Cond; 13265 } 13266 } 13267 } 13268 } 13269 return SDValue(); 13270} 13271 13272 13273/// PerformMulCombine - Optimize a single multiply with constant into two 13274/// in order to implement it with two cheaper instructions, e.g. 13275/// LEA + SHL, LEA + LEA. 13276static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 13277 TargetLowering::DAGCombinerInfo &DCI) { 13278 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 13279 return SDValue(); 13280 13281 EVT VT = N->getValueType(0); 13282 if (VT != MVT::i64) 13283 return SDValue(); 13284 13285 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 13286 if (!C) 13287 return SDValue(); 13288 uint64_t MulAmt = C->getZExtValue(); 13289 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 13290 return SDValue(); 13291 13292 uint64_t MulAmt1 = 0; 13293 uint64_t MulAmt2 = 0; 13294 if ((MulAmt % 9) == 0) { 13295 MulAmt1 = 9; 13296 MulAmt2 = MulAmt / 9; 13297 } else if ((MulAmt % 5) == 0) { 13298 MulAmt1 = 5; 13299 MulAmt2 = MulAmt / 5; 13300 } else if ((MulAmt % 3) == 0) { 13301 MulAmt1 = 3; 13302 MulAmt2 = MulAmt / 3; 13303 } 13304 if (MulAmt2 && 13305 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13306 DebugLoc DL = N->getDebugLoc(); 13307 13308 if (isPowerOf2_64(MulAmt2) && 13309 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13310 // If second multiplifer is pow2, issue it first. We want the multiply by 13311 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13312 // is an add. 13313 std::swap(MulAmt1, MulAmt2); 13314 13315 SDValue NewMul; 13316 if (isPowerOf2_64(MulAmt1)) 13317 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13318 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13319 else 13320 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13321 DAG.getConstant(MulAmt1, VT)); 13322 13323 if (isPowerOf2_64(MulAmt2)) 13324 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13325 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13326 else 13327 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13328 DAG.getConstant(MulAmt2, VT)); 13329 13330 // Do not add new nodes to DAG combiner worklist. 13331 DCI.CombineTo(N, NewMul, false); 13332 } 13333 return SDValue(); 13334} 13335 13336static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13337 SDValue N0 = N->getOperand(0); 13338 SDValue N1 = N->getOperand(1); 13339 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13340 EVT VT = N0.getValueType(); 13341 13342 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13343 // since the result of setcc_c is all zero's or all ones. 13344 if (VT.isInteger() && !VT.isVector() && 13345 N1C && N0.getOpcode() == ISD::AND && 13346 N0.getOperand(1).getOpcode() == ISD::Constant) { 13347 SDValue N00 = N0.getOperand(0); 13348 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13349 ((N00.getOpcode() == ISD::ANY_EXTEND || 13350 N00.getOpcode() == ISD::ZERO_EXTEND) && 13351 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13352 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13353 APInt ShAmt = N1C->getAPIntValue(); 13354 Mask = Mask.shl(ShAmt); 13355 if (Mask != 0) 13356 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13357 N00, DAG.getConstant(Mask, VT)); 13358 } 13359 } 13360 13361 13362 // Hardware support for vector shifts is sparse which makes us scalarize the 13363 // vector operations in many cases. Also, on sandybridge ADD is faster than 13364 // shl. 13365 // (shl V, 1) -> add V,V 13366 if (isSplatVector(N1.getNode())) { 13367 assert(N0.getValueType().isVector() && "Invalid vector shift type"); 13368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0)); 13369 // We shift all of the values by one. In many cases we do not have 13370 // hardware support for this operation. This is better expressed as an ADD 13371 // of two values. 13372 if (N1C && (1 == N1C->getZExtValue())) { 13373 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0); 13374 } 13375 } 13376 13377 return SDValue(); 13378} 13379 13380/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13381/// when possible. 13382static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13383 const X86Subtarget *Subtarget) { 13384 EVT VT = N->getValueType(0); 13385 if (N->getOpcode() == ISD::SHL) { 13386 SDValue V = PerformSHLCombine(N, DAG); 13387 if (V.getNode()) return V; 13388 } 13389 13390 // On X86 with SSE2 support, we can transform this to a vector shift if 13391 // all elements are shifted by the same amount. We can't do this in legalize 13392 // because the a constant vector is typically transformed to a constant pool 13393 // so we have no knowledge of the shift amount. 13394 if (!Subtarget->hasSSE2()) 13395 return SDValue(); 13396 13397 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 && 13398 (!Subtarget->hasAVX2() || 13399 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) 13400 return SDValue(); 13401 13402 SDValue ShAmtOp = N->getOperand(1); 13403 EVT EltVT = VT.getVectorElementType(); 13404 DebugLoc DL = N->getDebugLoc(); 13405 SDValue BaseShAmt = SDValue(); 13406 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13407 unsigned NumElts = VT.getVectorNumElements(); 13408 unsigned i = 0; 13409 for (; i != NumElts; ++i) { 13410 SDValue Arg = ShAmtOp.getOperand(i); 13411 if (Arg.getOpcode() == ISD::UNDEF) continue; 13412 BaseShAmt = Arg; 13413 break; 13414 } 13415 // Handle the case where the build_vector is all undef 13416 // FIXME: Should DAG allow this? 13417 if (i == NumElts) 13418 return SDValue(); 13419 13420 for (; i != NumElts; ++i) { 13421 SDValue Arg = ShAmtOp.getOperand(i); 13422 if (Arg.getOpcode() == ISD::UNDEF) continue; 13423 if (Arg != BaseShAmt) { 13424 return SDValue(); 13425 } 13426 } 13427 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13428 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13429 SDValue InVec = ShAmtOp.getOperand(0); 13430 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13431 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13432 unsigned i = 0; 13433 for (; i != NumElts; ++i) { 13434 SDValue Arg = InVec.getOperand(i); 13435 if (Arg.getOpcode() == ISD::UNDEF) continue; 13436 BaseShAmt = Arg; 13437 break; 13438 } 13439 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13441 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13442 if (C->getZExtValue() == SplatIdx) 13443 BaseShAmt = InVec.getOperand(1); 13444 } 13445 } 13446 if (BaseShAmt.getNode() == 0) 13447 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13448 DAG.getIntPtrConstant(0)); 13449 } else 13450 return SDValue(); 13451 13452 // The shift amount is an i32. 13453 if (EltVT.bitsGT(MVT::i32)) 13454 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13455 else if (EltVT.bitsLT(MVT::i32)) 13456 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13457 13458 // The shift amount is identical so we can do a vector shift. 13459 SDValue ValOp = N->getOperand(0); 13460 switch (N->getOpcode()) { 13461 default: 13462 llvm_unreachable("Unknown shift opcode!"); 13463 case ISD::SHL: 13464 switch (VT.getSimpleVT().SimpleTy) { 13465 default: return SDValue(); 13466 case MVT::v2i64: 13467 case MVT::v4i32: 13468 case MVT::v8i16: 13469 case MVT::v4i64: 13470 case MVT::v8i32: 13471 case MVT::v16i16: 13472 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG); 13473 } 13474 case ISD::SRA: 13475 switch (VT.getSimpleVT().SimpleTy) { 13476 default: return SDValue(); 13477 case MVT::v4i32: 13478 case MVT::v8i16: 13479 case MVT::v8i32: 13480 case MVT::v16i16: 13481 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG); 13482 } 13483 case ISD::SRL: 13484 switch (VT.getSimpleVT().SimpleTy) { 13485 default: return SDValue(); 13486 case MVT::v2i64: 13487 case MVT::v4i32: 13488 case MVT::v8i16: 13489 case MVT::v4i64: 13490 case MVT::v8i32: 13491 case MVT::v16i16: 13492 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG); 13493 } 13494 } 13495} 13496 13497 13498// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13499// where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13500// and friends. Likewise for OR -> CMPNEQSS. 13501static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13502 TargetLowering::DAGCombinerInfo &DCI, 13503 const X86Subtarget *Subtarget) { 13504 unsigned opcode; 13505 13506 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13507 // we're requiring SSE2 for both. 13508 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13509 SDValue N0 = N->getOperand(0); 13510 SDValue N1 = N->getOperand(1); 13511 SDValue CMP0 = N0->getOperand(1); 13512 SDValue CMP1 = N1->getOperand(1); 13513 DebugLoc DL = N->getDebugLoc(); 13514 13515 // The SETCCs should both refer to the same CMP. 13516 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13517 return SDValue(); 13518 13519 SDValue CMP00 = CMP0->getOperand(0); 13520 SDValue CMP01 = CMP0->getOperand(1); 13521 EVT VT = CMP00.getValueType(); 13522 13523 if (VT == MVT::f32 || VT == MVT::f64) { 13524 bool ExpectingFlags = false; 13525 // Check for any users that want flags: 13526 for (SDNode::use_iterator UI = N->use_begin(), 13527 UE = N->use_end(); 13528 !ExpectingFlags && UI != UE; ++UI) 13529 switch (UI->getOpcode()) { 13530 default: 13531 case ISD::BR_CC: 13532 case ISD::BRCOND: 13533 case ISD::SELECT: 13534 ExpectingFlags = true; 13535 break; 13536 case ISD::CopyToReg: 13537 case ISD::SIGN_EXTEND: 13538 case ISD::ZERO_EXTEND: 13539 case ISD::ANY_EXTEND: 13540 break; 13541 } 13542 13543 if (!ExpectingFlags) { 13544 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13545 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13546 13547 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13548 X86::CondCode tmp = cc0; 13549 cc0 = cc1; 13550 cc1 = tmp; 13551 } 13552 13553 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13554 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13555 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13556 X86ISD::NodeType NTOperator = is64BitFP ? 13557 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13558 // FIXME: need symbolic constants for these magic numbers. 13559 // See X86ATTInstPrinter.cpp:printSSECC(). 13560 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13561 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13562 DAG.getConstant(x86cc, MVT::i8)); 13563 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13564 OnesOrZeroesF); 13565 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13566 DAG.getConstant(1, MVT::i32)); 13567 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13568 return OneBitOfTruth; 13569 } 13570 } 13571 } 13572 } 13573 return SDValue(); 13574} 13575 13576/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13577/// so it can be folded inside ANDNP. 13578static bool CanFoldXORWithAllOnes(const SDNode *N) { 13579 EVT VT = N->getValueType(0); 13580 13581 // Match direct AllOnes for 128 and 256-bit vectors 13582 if (ISD::isBuildVectorAllOnes(N)) 13583 return true; 13584 13585 // Look through a bit convert. 13586 if (N->getOpcode() == ISD::BITCAST) 13587 N = N->getOperand(0).getNode(); 13588 13589 // Sometimes the operand may come from a insert_subvector building a 256-bit 13590 // allones vector 13591 if (VT.getSizeInBits() == 256 && 13592 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13593 SDValue V1 = N->getOperand(0); 13594 SDValue V2 = N->getOperand(1); 13595 13596 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13597 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13598 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13599 ISD::isBuildVectorAllOnes(V2.getNode())) 13600 return true; 13601 } 13602 13603 return false; 13604} 13605 13606static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13607 TargetLowering::DAGCombinerInfo &DCI, 13608 const X86Subtarget *Subtarget) { 13609 if (DCI.isBeforeLegalizeOps()) 13610 return SDValue(); 13611 13612 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13613 if (R.getNode()) 13614 return R; 13615 13616 EVT VT = N->getValueType(0); 13617 13618 // Create ANDN, BLSI, and BLSR instructions 13619 // BLSI is X & (-X) 13620 // BLSR is X & (X-1) 13621 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13622 SDValue N0 = N->getOperand(0); 13623 SDValue N1 = N->getOperand(1); 13624 DebugLoc DL = N->getDebugLoc(); 13625 13626 // Check LHS for not 13627 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13628 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13629 // Check RHS for not 13630 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13631 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13632 13633 // Check LHS for neg 13634 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 && 13635 isZero(N0.getOperand(0))) 13636 return DAG.getNode(X86ISD::BLSI, DL, VT, N1); 13637 13638 // Check RHS for neg 13639 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 && 13640 isZero(N1.getOperand(0))) 13641 return DAG.getNode(X86ISD::BLSI, DL, VT, N0); 13642 13643 // Check LHS for X-1 13644 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13645 isAllOnes(N0.getOperand(1))) 13646 return DAG.getNode(X86ISD::BLSR, DL, VT, N1); 13647 13648 // Check RHS for X-1 13649 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13650 isAllOnes(N1.getOperand(1))) 13651 return DAG.getNode(X86ISD::BLSR, DL, VT, N0); 13652 13653 return SDValue(); 13654 } 13655 13656 // Want to form ANDNP nodes: 13657 // 1) In the hopes of then easily combining them with OR and AND nodes 13658 // to form PBLEND/PSIGN. 13659 // 2) To match ANDN packed intrinsics 13660 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13661 return SDValue(); 13662 13663 SDValue N0 = N->getOperand(0); 13664 SDValue N1 = N->getOperand(1); 13665 DebugLoc DL = N->getDebugLoc(); 13666 13667 // Check LHS for vnot 13668 if (N0.getOpcode() == ISD::XOR && 13669 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13670 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13671 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13672 13673 // Check RHS for vnot 13674 if (N1.getOpcode() == ISD::XOR && 13675 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13676 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13677 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13678 13679 return SDValue(); 13680} 13681 13682static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13683 TargetLowering::DAGCombinerInfo &DCI, 13684 const X86Subtarget *Subtarget) { 13685 if (DCI.isBeforeLegalizeOps()) 13686 return SDValue(); 13687 13688 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13689 if (R.getNode()) 13690 return R; 13691 13692 EVT VT = N->getValueType(0); 13693 13694 SDValue N0 = N->getOperand(0); 13695 SDValue N1 = N->getOperand(1); 13696 13697 // look for psign/blend 13698 if (VT == MVT::v2i64 || VT == MVT::v4i64) { 13699 if (!Subtarget->hasSSSE3() || 13700 (VT == MVT::v4i64 && !Subtarget->hasAVX2())) 13701 return SDValue(); 13702 13703 // Canonicalize pandn to RHS 13704 if (N0.getOpcode() == X86ISD::ANDNP) 13705 std::swap(N0, N1); 13706 // or (and (m, y), (pandn m, x)) 13707 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13708 SDValue Mask = N1.getOperand(0); 13709 SDValue X = N1.getOperand(1); 13710 SDValue Y; 13711 if (N0.getOperand(0) == Mask) 13712 Y = N0.getOperand(1); 13713 if (N0.getOperand(1) == Mask) 13714 Y = N0.getOperand(0); 13715 13716 // Check to see if the mask appeared in both the AND and ANDNP and 13717 if (!Y.getNode()) 13718 return SDValue(); 13719 13720 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13721 if (Mask.getOpcode() != ISD::BITCAST || 13722 X.getOpcode() != ISD::BITCAST || 13723 Y.getOpcode() != ISD::BITCAST) 13724 return SDValue(); 13725 13726 // Look through mask bitcast. 13727 Mask = Mask.getOperand(0); 13728 EVT MaskVT = Mask.getValueType(); 13729 13730 // Validate that the Mask operand is a vector sra node. 13731 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13732 // there is no psrai.b 13733 SDValue SraSrc, SraC; 13734 if (Mask.getOpcode() == ISD::INTRINSIC_WO_CHAIN) { 13735 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13736 case Intrinsic::x86_sse2_psrai_w: 13737 case Intrinsic::x86_sse2_psrai_d: 13738 case Intrinsic::x86_avx2_psrai_w: 13739 case Intrinsic::x86_avx2_psrai_d: 13740 break; 13741 default: return SDValue(); 13742 } 13743 13744 SraSrc = Mask.getOperand(1); 13745 SraC = Mask.getOperand(2); 13746 } else if (Mask.getOpcode() == X86ISD::VSRAI) { 13747 SraSrc = Mask.getOperand(0); 13748 SraC = Mask.getOperand(1); 13749 } else 13750 return SDValue(); 13751 13752 // Check that the SRA is all signbits. 13753 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13754 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13755 if ((SraAmt + 1) != EltBits) 13756 return SDValue(); 13757 13758 DebugLoc DL = N->getDebugLoc(); 13759 13760 // Now we know we at least have a plendvb with the mask val. See if 13761 // we can form a psignb/w/d. 13762 // psign = x.type == y.type == mask.type && y = sub(0, x); 13763 X = X.getOperand(0); 13764 Y = Y.getOperand(0); 13765 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13766 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13767 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) { 13768 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) && 13769 "Unsupported VT for PSIGN"); 13770 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, SraSrc); 13771 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13772 } 13773 // PBLENDVB only available on SSE 4.1 13774 if (!Subtarget->hasSSE41()) 13775 return SDValue(); 13776 13777 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8; 13778 13779 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X); 13780 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y); 13781 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask); 13782 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X); 13783 return DAG.getNode(ISD::BITCAST, DL, VT, Mask); 13784 } 13785 } 13786 13787 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) 13788 return SDValue(); 13789 13790 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13791 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13792 std::swap(N0, N1); 13793 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13794 return SDValue(); 13795 if (!N0.hasOneUse() || !N1.hasOneUse()) 13796 return SDValue(); 13797 13798 SDValue ShAmt0 = N0.getOperand(1); 13799 if (ShAmt0.getValueType() != MVT::i8) 13800 return SDValue(); 13801 SDValue ShAmt1 = N1.getOperand(1); 13802 if (ShAmt1.getValueType() != MVT::i8) 13803 return SDValue(); 13804 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13805 ShAmt0 = ShAmt0.getOperand(0); 13806 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13807 ShAmt1 = ShAmt1.getOperand(0); 13808 13809 DebugLoc DL = N->getDebugLoc(); 13810 unsigned Opc = X86ISD::SHLD; 13811 SDValue Op0 = N0.getOperand(0); 13812 SDValue Op1 = N1.getOperand(0); 13813 if (ShAmt0.getOpcode() == ISD::SUB) { 13814 Opc = X86ISD::SHRD; 13815 std::swap(Op0, Op1); 13816 std::swap(ShAmt0, ShAmt1); 13817 } 13818 13819 unsigned Bits = VT.getSizeInBits(); 13820 if (ShAmt1.getOpcode() == ISD::SUB) { 13821 SDValue Sum = ShAmt1.getOperand(0); 13822 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13823 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13824 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13825 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13826 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13827 return DAG.getNode(Opc, DL, VT, 13828 Op0, Op1, 13829 DAG.getNode(ISD::TRUNCATE, DL, 13830 MVT::i8, ShAmt0)); 13831 } 13832 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13833 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13834 if (ShAmt0C && 13835 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13836 return DAG.getNode(Opc, DL, VT, 13837 N0.getOperand(0), N1.getOperand(0), 13838 DAG.getNode(ISD::TRUNCATE, DL, 13839 MVT::i8, ShAmt0)); 13840 } 13841 13842 return SDValue(); 13843} 13844 13845// PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes 13846static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, 13847 TargetLowering::DAGCombinerInfo &DCI, 13848 const X86Subtarget *Subtarget) { 13849 if (DCI.isBeforeLegalizeOps()) 13850 return SDValue(); 13851 13852 EVT VT = N->getValueType(0); 13853 13854 if (VT != MVT::i32 && VT != MVT::i64) 13855 return SDValue(); 13856 13857 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions"); 13858 13859 // Create BLSMSK instructions by finding X ^ (X-1) 13860 SDValue N0 = N->getOperand(0); 13861 SDValue N1 = N->getOperand(1); 13862 DebugLoc DL = N->getDebugLoc(); 13863 13864 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 13865 isAllOnes(N0.getOperand(1))) 13866 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1); 13867 13868 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 && 13869 isAllOnes(N1.getOperand(1))) 13870 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0); 13871 13872 return SDValue(); 13873} 13874 13875/// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13876static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13877 const X86Subtarget *Subtarget) { 13878 LoadSDNode *Ld = cast<LoadSDNode>(N); 13879 EVT RegVT = Ld->getValueType(0); 13880 EVT MemVT = Ld->getMemoryVT(); 13881 DebugLoc dl = Ld->getDebugLoc(); 13882 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13883 13884 ISD::LoadExtType Ext = Ld->getExtensionType(); 13885 13886 // If this is a vector EXT Load then attempt to optimize it using a 13887 // shuffle. We need SSE4 for the shuffles. 13888 // TODO: It is possible to support ZExt by zeroing the undef values 13889 // during the shuffle phase or after the shuffle. 13890 if (RegVT.isVector() && RegVT.isInteger() && 13891 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 13892 assert(MemVT != RegVT && "Cannot extend to the same type"); 13893 assert(MemVT.isVector() && "Must load a vector from memory"); 13894 13895 unsigned NumElems = RegVT.getVectorNumElements(); 13896 unsigned RegSz = RegVT.getSizeInBits(); 13897 unsigned MemSz = MemVT.getSizeInBits(); 13898 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 13899 // All sizes must be a power of two 13900 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 13901 13902 // Attempt to load the original value using a single load op. 13903 // Find a scalar type which is equal to the loaded word size. 13904 MVT SclrLoadTy = MVT::i8; 13905 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13906 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13907 MVT Tp = (MVT::SimpleValueType)tp; 13908 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 13909 SclrLoadTy = Tp; 13910 break; 13911 } 13912 } 13913 13914 // Proceed if a load word is found. 13915 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 13916 13917 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 13918 RegSz/SclrLoadTy.getSizeInBits()); 13919 13920 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 13921 RegSz/MemVT.getScalarType().getSizeInBits()); 13922 // Can't shuffle using an illegal type. 13923 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13924 13925 // Perform a single load. 13926 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 13927 Ld->getBasePtr(), 13928 Ld->getPointerInfo(), Ld->isVolatile(), 13929 Ld->isNonTemporal(), Ld->isInvariant(), 13930 Ld->getAlignment()); 13931 13932 // Insert the word loaded into a vector. 13933 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 13934 LoadUnitVecVT, ScalarLoad); 13935 13936 // Bitcast the loaded value to a vector of the original element type, in 13937 // the size of the target vector type. 13938 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, 13939 ScalarInVector); 13940 unsigned SizeRatio = RegSz/MemSz; 13941 13942 // Redistribute the loaded elements into the different locations. 13943 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13944 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 13945 13946 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 13947 DAG.getUNDEF(SlicedVec.getValueType()), 13948 ShuffleVec.data()); 13949 13950 // Bitcast to the requested type. 13951 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 13952 // Replace the original load with the new sequence 13953 // and return the new chain. 13954 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 13955 return SDValue(ScalarLoad.getNode(), 1); 13956 } 13957 13958 return SDValue(); 13959} 13960 13961/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 13962static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 13963 const X86Subtarget *Subtarget) { 13964 StoreSDNode *St = cast<StoreSDNode>(N); 13965 EVT VT = St->getValue().getValueType(); 13966 EVT StVT = St->getMemoryVT(); 13967 DebugLoc dl = St->getDebugLoc(); 13968 SDValue StoredVal = St->getOperand(1); 13969 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13970 13971 // If we are saving a concatenation of two XMM registers, perform two stores. 13972 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 13973 // 128-bit ones. If in the future the cost becomes only one memory access the 13974 // first version would be better. 13975 if (VT.getSizeInBits() == 256 && 13976 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 13977 StoredVal.getNumOperands() == 2) { 13978 13979 SDValue Value0 = StoredVal.getOperand(0); 13980 SDValue Value1 = StoredVal.getOperand(1); 13981 13982 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 13983 SDValue Ptr0 = St->getBasePtr(); 13984 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 13985 13986 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 13987 St->getPointerInfo(), St->isVolatile(), 13988 St->isNonTemporal(), St->getAlignment()); 13989 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 13990 St->getPointerInfo(), St->isVolatile(), 13991 St->isNonTemporal(), St->getAlignment()); 13992 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 13993 } 13994 13995 // Optimize trunc store (of multiple scalars) to shuffle and store. 13996 // First, pack all of the elements in one place. Next, store to memory 13997 // in fewer chunks. 13998 if (St->isTruncatingStore() && VT.isVector()) { 13999 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14000 unsigned NumElems = VT.getVectorNumElements(); 14001 assert(StVT != VT && "Cannot truncate to the same type"); 14002 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 14003 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 14004 14005 // From, To sizes and ElemCount must be pow of two 14006 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 14007 // We are going to use the original vector elt for storing. 14008 // Accumulated smaller vector elements must be a multiple of the store size. 14009 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 14010 14011 unsigned SizeRatio = FromSz / ToSz; 14012 14013 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 14014 14015 // Create a type on which we perform the shuffle 14016 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 14017 StVT.getScalarType(), NumElems*SizeRatio); 14018 14019 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 14020 14021 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 14022 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 14023 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 14024 14025 // Can't shuffle using an illegal type 14026 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 14027 14028 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 14029 DAG.getUNDEF(WideVec.getValueType()), 14030 ShuffleVec.data()); 14031 // At this point all of the data is stored at the bottom of the 14032 // register. We now need to save it to mem. 14033 14034 // Find the largest store unit 14035 MVT StoreType = MVT::i8; 14036 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 14037 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 14038 MVT Tp = (MVT::SimpleValueType)tp; 14039 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 14040 StoreType = Tp; 14041 } 14042 14043 // Bitcast the original vector into a vector of store-size units 14044 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 14045 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 14046 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 14047 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 14048 SmallVector<SDValue, 8> Chains; 14049 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 14050 TLI.getPointerTy()); 14051 SDValue Ptr = St->getBasePtr(); 14052 14053 // Perform one or more big stores into memory. 14054 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 14055 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 14056 StoreType, ShuffWide, 14057 DAG.getIntPtrConstant(i)); 14058 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 14059 St->getPointerInfo(), St->isVolatile(), 14060 St->isNonTemporal(), St->getAlignment()); 14061 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 14062 Chains.push_back(Ch); 14063 } 14064 14065 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 14066 Chains.size()); 14067 } 14068 14069 14070 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 14071 // the FP state in cases where an emms may be missing. 14072 // A preferable solution to the general problem is to figure out the right 14073 // places to insert EMMS. This qualifies as a quick hack. 14074 14075 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 14076 if (VT.getSizeInBits() != 64) 14077 return SDValue(); 14078 14079 const Function *F = DAG.getMachineFunction().getFunction(); 14080 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 14081 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps 14082 && Subtarget->hasSSE2(); 14083 if ((VT.isVector() || 14084 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 14085 isa<LoadSDNode>(St->getValue()) && 14086 !cast<LoadSDNode>(St->getValue())->isVolatile() && 14087 St->getChain().hasOneUse() && !St->isVolatile()) { 14088 SDNode* LdVal = St->getValue().getNode(); 14089 LoadSDNode *Ld = 0; 14090 int TokenFactorIndex = -1; 14091 SmallVector<SDValue, 8> Ops; 14092 SDNode* ChainVal = St->getChain().getNode(); 14093 // Must be a store of a load. We currently handle two cases: the load 14094 // is a direct child, and it's under an intervening TokenFactor. It is 14095 // possible to dig deeper under nested TokenFactors. 14096 if (ChainVal == LdVal) 14097 Ld = cast<LoadSDNode>(St->getChain()); 14098 else if (St->getValue().hasOneUse() && 14099 ChainVal->getOpcode() == ISD::TokenFactor) { 14100 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 14101 if (ChainVal->getOperand(i).getNode() == LdVal) { 14102 TokenFactorIndex = i; 14103 Ld = cast<LoadSDNode>(St->getValue()); 14104 } else 14105 Ops.push_back(ChainVal->getOperand(i)); 14106 } 14107 } 14108 14109 if (!Ld || !ISD::isNormalLoad(Ld)) 14110 return SDValue(); 14111 14112 // If this is not the MMX case, i.e. we are just turning i64 load/store 14113 // into f64 load/store, avoid the transformation if there are multiple 14114 // uses of the loaded value. 14115 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 14116 return SDValue(); 14117 14118 DebugLoc LdDL = Ld->getDebugLoc(); 14119 DebugLoc StDL = N->getDebugLoc(); 14120 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 14121 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 14122 // pair instead. 14123 if (Subtarget->is64Bit() || F64IsLegal) { 14124 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 14125 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 14126 Ld->getPointerInfo(), Ld->isVolatile(), 14127 Ld->isNonTemporal(), Ld->isInvariant(), 14128 Ld->getAlignment()); 14129 SDValue NewChain = NewLd.getValue(1); 14130 if (TokenFactorIndex != -1) { 14131 Ops.push_back(NewChain); 14132 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14133 Ops.size()); 14134 } 14135 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 14136 St->getPointerInfo(), 14137 St->isVolatile(), St->isNonTemporal(), 14138 St->getAlignment()); 14139 } 14140 14141 // Otherwise, lower to two pairs of 32-bit loads / stores. 14142 SDValue LoAddr = Ld->getBasePtr(); 14143 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 14144 DAG.getConstant(4, MVT::i32)); 14145 14146 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 14147 Ld->getPointerInfo(), 14148 Ld->isVolatile(), Ld->isNonTemporal(), 14149 Ld->isInvariant(), Ld->getAlignment()); 14150 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 14151 Ld->getPointerInfo().getWithOffset(4), 14152 Ld->isVolatile(), Ld->isNonTemporal(), 14153 Ld->isInvariant(), 14154 MinAlign(Ld->getAlignment(), 4)); 14155 14156 SDValue NewChain = LoLd.getValue(1); 14157 if (TokenFactorIndex != -1) { 14158 Ops.push_back(LoLd); 14159 Ops.push_back(HiLd); 14160 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 14161 Ops.size()); 14162 } 14163 14164 LoAddr = St->getBasePtr(); 14165 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 14166 DAG.getConstant(4, MVT::i32)); 14167 14168 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 14169 St->getPointerInfo(), 14170 St->isVolatile(), St->isNonTemporal(), 14171 St->getAlignment()); 14172 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 14173 St->getPointerInfo().getWithOffset(4), 14174 St->isVolatile(), 14175 St->isNonTemporal(), 14176 MinAlign(St->getAlignment(), 4)); 14177 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 14178 } 14179 return SDValue(); 14180} 14181 14182/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 14183/// and return the operands for the horizontal operation in LHS and RHS. A 14184/// horizontal operation performs the binary operation on successive elements 14185/// of its first operand, then on successive elements of its second operand, 14186/// returning the resulting values in a vector. For example, if 14187/// A = < float a0, float a1, float a2, float a3 > 14188/// and 14189/// B = < float b0, float b1, float b2, float b3 > 14190/// then the result of doing a horizontal operation on A and B is 14191/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 14192/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 14193/// A horizontal-op B, for some already available A and B, and if so then LHS is 14194/// set to A, RHS to B, and the routine returns 'true'. 14195/// Note that the binary operation should have the property that if one of the 14196/// operands is UNDEF then the result is UNDEF. 14197static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) { 14198 // Look for the following pattern: if 14199 // A = < float a0, float a1, float a2, float a3 > 14200 // B = < float b0, float b1, float b2, float b3 > 14201 // and 14202 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 14203 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 14204 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 14205 // which is A horizontal-op B. 14206 14207 // At least one of the operands should be a vector shuffle. 14208 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 14209 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 14210 return false; 14211 14212 EVT VT = LHS.getValueType(); 14213 14214 assert((VT.is128BitVector() || VT.is256BitVector()) && 14215 "Unsupported vector type for horizontal add/sub"); 14216 14217 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to 14218 // operate independently on 128-bit lanes. 14219 unsigned NumElts = VT.getVectorNumElements(); 14220 unsigned NumLanes = VT.getSizeInBits()/128; 14221 unsigned NumLaneElts = NumElts / NumLanes; 14222 assert((NumLaneElts % 2 == 0) && 14223 "Vector type should have an even number of elements in each lane"); 14224 unsigned HalfLaneElts = NumLaneElts/2; 14225 14226 // View LHS in the form 14227 // LHS = VECTOR_SHUFFLE A, B, LMask 14228 // If LHS is not a shuffle then pretend it is the shuffle 14229 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 14230 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 14231 // type VT. 14232 SDValue A, B; 14233 SmallVector<int, 16> LMask(NumElts); 14234 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14235 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 14236 A = LHS.getOperand(0); 14237 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 14238 B = LHS.getOperand(1); 14239 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(); 14240 std::copy(Mask.begin(), Mask.end(), LMask.begin()); 14241 } else { 14242 if (LHS.getOpcode() != ISD::UNDEF) 14243 A = LHS; 14244 for (unsigned i = 0; i != NumElts; ++i) 14245 LMask[i] = i; 14246 } 14247 14248 // Likewise, view RHS in the form 14249 // RHS = VECTOR_SHUFFLE C, D, RMask 14250 SDValue C, D; 14251 SmallVector<int, 16> RMask(NumElts); 14252 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 14253 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 14254 C = RHS.getOperand(0); 14255 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 14256 D = RHS.getOperand(1); 14257 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(); 14258 std::copy(Mask.begin(), Mask.end(), RMask.begin()); 14259 } else { 14260 if (RHS.getOpcode() != ISD::UNDEF) 14261 C = RHS; 14262 for (unsigned i = 0; i != NumElts; ++i) 14263 RMask[i] = i; 14264 } 14265 14266 // Check that the shuffles are both shuffling the same vectors. 14267 if (!(A == C && B == D) && !(A == D && B == C)) 14268 return false; 14269 14270 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 14271 if (!A.getNode() && !B.getNode()) 14272 return false; 14273 14274 // If A and B occur in reverse order in RHS, then "swap" them (which means 14275 // rewriting the mask). 14276 if (A != C) 14277 CommuteVectorShuffleMask(RMask, NumElts); 14278 14279 // At this point LHS and RHS are equivalent to 14280 // LHS = VECTOR_SHUFFLE A, B, LMask 14281 // RHS = VECTOR_SHUFFLE A, B, RMask 14282 // Check that the masks correspond to performing a horizontal operation. 14283 for (unsigned i = 0; i != NumElts; ++i) { 14284 int LIdx = LMask[i], RIdx = RMask[i]; 14285 14286 // Ignore any UNDEF components. 14287 if (LIdx < 0 || RIdx < 0 || 14288 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) || 14289 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts))) 14290 continue; 14291 14292 // Check that successive elements are being operated on. If not, this is 14293 // not a horizontal operation. 14294 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs 14295 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts; 14296 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart; 14297 if (!(LIdx == Index && RIdx == Index + 1) && 14298 !(IsCommutative && LIdx == Index + 1 && RIdx == Index)) 14299 return false; 14300 } 14301 14302 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 14303 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 14304 return true; 14305} 14306 14307/// PerformFADDCombine - Do target-specific dag combines on floating point adds. 14308static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 14309 const X86Subtarget *Subtarget) { 14310 EVT VT = N->getValueType(0); 14311 SDValue LHS = N->getOperand(0); 14312 SDValue RHS = N->getOperand(1); 14313 14314 // Try to synthesize horizontal adds from adds of shuffles. 14315 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14316 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14317 isHorizontalBinOp(LHS, RHS, true)) 14318 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 14319 return SDValue(); 14320} 14321 14322/// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 14323static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 14324 const X86Subtarget *Subtarget) { 14325 EVT VT = N->getValueType(0); 14326 SDValue LHS = N->getOperand(0); 14327 SDValue RHS = N->getOperand(1); 14328 14329 // Try to synthesize horizontal subs from subs of shuffles. 14330 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) || 14331 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) && 14332 isHorizontalBinOp(LHS, RHS, false)) 14333 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 14334 return SDValue(); 14335} 14336 14337/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 14338/// X86ISD::FXOR nodes. 14339static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 14340 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 14341 // F[X]OR(0.0, x) -> x 14342 // F[X]OR(x, 0.0) -> x 14343 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14344 if (C->getValueAPF().isPosZero()) 14345 return N->getOperand(1); 14346 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14347 if (C->getValueAPF().isPosZero()) 14348 return N->getOperand(0); 14349 return SDValue(); 14350} 14351 14352/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 14353static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 14354 // FAND(0.0, x) -> 0.0 14355 // FAND(x, 0.0) -> 0.0 14356 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 14357 if (C->getValueAPF().isPosZero()) 14358 return N->getOperand(0); 14359 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 14360 if (C->getValueAPF().isPosZero()) 14361 return N->getOperand(1); 14362 return SDValue(); 14363} 14364 14365static SDValue PerformBTCombine(SDNode *N, 14366 SelectionDAG &DAG, 14367 TargetLowering::DAGCombinerInfo &DCI) { 14368 // BT ignores high bits in the bit index operand. 14369 SDValue Op1 = N->getOperand(1); 14370 if (Op1.hasOneUse()) { 14371 unsigned BitWidth = Op1.getValueSizeInBits(); 14372 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 14373 APInt KnownZero, KnownOne; 14374 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 14375 !DCI.isBeforeLegalizeOps()); 14376 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 14377 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 14378 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 14379 DCI.CommitTargetLoweringOpt(TLO); 14380 } 14381 return SDValue(); 14382} 14383 14384static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 14385 SDValue Op = N->getOperand(0); 14386 if (Op.getOpcode() == ISD::BITCAST) 14387 Op = Op.getOperand(0); 14388 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14389 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14390 VT.getVectorElementType().getSizeInBits() == 14391 OpVT.getVectorElementType().getSizeInBits()) { 14392 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14393 } 14394 return SDValue(); 14395} 14396 14397static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14398 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14399 // (and (i32 x86isd::setcc_carry), 1) 14400 // This eliminates the zext. This transformation is necessary because 14401 // ISD::SETCC is always legalized to i8. 14402 DebugLoc dl = N->getDebugLoc(); 14403 SDValue N0 = N->getOperand(0); 14404 EVT VT = N->getValueType(0); 14405 if (N0.getOpcode() == ISD::AND && 14406 N0.hasOneUse() && 14407 N0.getOperand(0).hasOneUse()) { 14408 SDValue N00 = N0.getOperand(0); 14409 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14410 return SDValue(); 14411 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14412 if (!C || C->getZExtValue() != 1) 14413 return SDValue(); 14414 return DAG.getNode(ISD::AND, dl, VT, 14415 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14416 N00.getOperand(0), N00.getOperand(1)), 14417 DAG.getConstant(1, VT)); 14418 } 14419 14420 return SDValue(); 14421} 14422 14423// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14424static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14425 unsigned X86CC = N->getConstantOperandVal(0); 14426 SDValue EFLAG = N->getOperand(1); 14427 DebugLoc DL = N->getDebugLoc(); 14428 14429 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14430 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14431 // cases. 14432 if (X86CC == X86::COND_B) 14433 return DAG.getNode(ISD::AND, DL, MVT::i8, 14434 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14435 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14436 DAG.getConstant(1, MVT::i8)); 14437 14438 return SDValue(); 14439} 14440 14441static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14442 const X86TargetLowering *XTLI) { 14443 SDValue Op0 = N->getOperand(0); 14444 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14445 // a 32-bit target where SSE doesn't support i64->FP operations. 14446 if (Op0.getOpcode() == ISD::LOAD) { 14447 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14448 EVT VT = Ld->getValueType(0); 14449 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14450 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14451 !XTLI->getSubtarget()->is64Bit() && 14452 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14453 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14454 Ld->getChain(), Op0, DAG); 14455 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14456 return FILDChain; 14457 } 14458 } 14459 return SDValue(); 14460} 14461 14462// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14463static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14464 X86TargetLowering::DAGCombinerInfo &DCI) { 14465 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14466 // the result is either zero or one (depending on the input carry bit). 14467 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14468 if (X86::isZeroNode(N->getOperand(0)) && 14469 X86::isZeroNode(N->getOperand(1)) && 14470 // We don't have a good way to replace an EFLAGS use, so only do this when 14471 // dead right now. 14472 SDValue(N, 1).use_empty()) { 14473 DebugLoc DL = N->getDebugLoc(); 14474 EVT VT = N->getValueType(0); 14475 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14476 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14477 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14478 DAG.getConstant(X86::COND_B,MVT::i8), 14479 N->getOperand(2)), 14480 DAG.getConstant(1, VT)); 14481 return DCI.CombineTo(N, Res1, CarryOut); 14482 } 14483 14484 return SDValue(); 14485} 14486 14487// fold (add Y, (sete X, 0)) -> adc 0, Y 14488// (add Y, (setne X, 0)) -> sbb -1, Y 14489// (sub (sete X, 0), Y) -> sbb 0, Y 14490// (sub (setne X, 0), Y) -> adc -1, Y 14491static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14492 DebugLoc DL = N->getDebugLoc(); 14493 14494 // Look through ZExts. 14495 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14496 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14497 return SDValue(); 14498 14499 SDValue SetCC = Ext.getOperand(0); 14500 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14501 return SDValue(); 14502 14503 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14504 if (CC != X86::COND_E && CC != X86::COND_NE) 14505 return SDValue(); 14506 14507 SDValue Cmp = SetCC.getOperand(1); 14508 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14509 !X86::isZeroNode(Cmp.getOperand(1)) || 14510 !Cmp.getOperand(0).getValueType().isInteger()) 14511 return SDValue(); 14512 14513 SDValue CmpOp0 = Cmp.getOperand(0); 14514 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14515 DAG.getConstant(1, CmpOp0.getValueType())); 14516 14517 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14518 if (CC == X86::COND_NE) 14519 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14520 DL, OtherVal.getValueType(), OtherVal, 14521 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14522 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14523 DL, OtherVal.getValueType(), OtherVal, 14524 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14525} 14526 14527/// PerformADDCombine - Do target-specific dag combines on integer adds. 14528static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, 14529 const X86Subtarget *Subtarget) { 14530 EVT VT = N->getValueType(0); 14531 SDValue Op0 = N->getOperand(0); 14532 SDValue Op1 = N->getOperand(1); 14533 14534 // Try to synthesize horizontal adds from adds of shuffles. 14535 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14536 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14537 isHorizontalBinOp(Op0, Op1, true)) 14538 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); 14539 14540 return OptimizeConditionalInDecrement(N, DAG); 14541} 14542 14543static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, 14544 const X86Subtarget *Subtarget) { 14545 SDValue Op0 = N->getOperand(0); 14546 SDValue Op1 = N->getOperand(1); 14547 14548 // X86 can't encode an immediate LHS of a sub. See if we can push the 14549 // negation into a preceding instruction. 14550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14551 // If the RHS of the sub is a XOR with one use and a constant, invert the 14552 // immediate. Then add one to the LHS of the sub so we can turn 14553 // X-Y -> X+~Y+1, saving one register. 14554 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14555 isa<ConstantSDNode>(Op1.getOperand(1))) { 14556 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14557 EVT VT = Op0.getValueType(); 14558 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14559 Op1.getOperand(0), 14560 DAG.getConstant(~XorC, VT)); 14561 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14562 DAG.getConstant(C->getAPIntValue()+1, VT)); 14563 } 14564 } 14565 14566 // Try to synthesize horizontal adds from adds of shuffles. 14567 EVT VT = N->getValueType(0); 14568 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || 14569 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && 14570 isHorizontalBinOp(Op0, Op1, true)) 14571 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1); 14572 14573 return OptimizeConditionalInDecrement(N, DAG); 14574} 14575 14576SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14577 DAGCombinerInfo &DCI) const { 14578 SelectionDAG &DAG = DCI.DAG; 14579 switch (N->getOpcode()) { 14580 default: break; 14581 case ISD::EXTRACT_VECTOR_ELT: 14582 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14583 case ISD::VSELECT: 14584 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget); 14585 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14586 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget); 14587 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget); 14588 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14589 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14590 case ISD::SHL: 14591 case ISD::SRA: 14592 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14593 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14594 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14595 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); 14596 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14597 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14598 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14599 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14600 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14601 case X86ISD::FXOR: 14602 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14603 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14604 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14605 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14606 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14607 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14608 case X86ISD::SHUFP: // Handle all target specific shuffles 14609 case X86ISD::PALIGN: 14610 case X86ISD::UNPCKH: 14611 case X86ISD::UNPCKL: 14612 case X86ISD::MOVHLPS: 14613 case X86ISD::MOVLHPS: 14614 case X86ISD::PSHUFD: 14615 case X86ISD::PSHUFHW: 14616 case X86ISD::PSHUFLW: 14617 case X86ISD::MOVSS: 14618 case X86ISD::MOVSD: 14619 case X86ISD::VPERMILP: 14620 case X86ISD::VPERM2X128: 14621 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14622 } 14623 14624 return SDValue(); 14625} 14626 14627/// isTypeDesirableForOp - Return true if the target has native support for 14628/// the specified value type and it is 'desirable' to use the type for the 14629/// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14630/// instruction encodings are longer and some i16 instructions are slow. 14631bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14632 if (!isTypeLegal(VT)) 14633 return false; 14634 if (VT != MVT::i16) 14635 return true; 14636 14637 switch (Opc) { 14638 default: 14639 return true; 14640 case ISD::LOAD: 14641 case ISD::SIGN_EXTEND: 14642 case ISD::ZERO_EXTEND: 14643 case ISD::ANY_EXTEND: 14644 case ISD::SHL: 14645 case ISD::SRL: 14646 case ISD::SUB: 14647 case ISD::ADD: 14648 case ISD::MUL: 14649 case ISD::AND: 14650 case ISD::OR: 14651 case ISD::XOR: 14652 return false; 14653 } 14654} 14655 14656/// IsDesirableToPromoteOp - This method query the target whether it is 14657/// beneficial for dag combiner to promote the specified node. If true, it 14658/// should return the desired promotion type by reference. 14659bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14660 EVT VT = Op.getValueType(); 14661 if (VT != MVT::i16) 14662 return false; 14663 14664 bool Promote = false; 14665 bool Commute = false; 14666 switch (Op.getOpcode()) { 14667 default: break; 14668 case ISD::LOAD: { 14669 LoadSDNode *LD = cast<LoadSDNode>(Op); 14670 // If the non-extending load has a single use and it's not live out, then it 14671 // might be folded. 14672 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14673 Op.hasOneUse()*/) { 14674 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14675 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14676 // The only case where we'd want to promote LOAD (rather then it being 14677 // promoted as an operand is when it's only use is liveout. 14678 if (UI->getOpcode() != ISD::CopyToReg) 14679 return false; 14680 } 14681 } 14682 Promote = true; 14683 break; 14684 } 14685 case ISD::SIGN_EXTEND: 14686 case ISD::ZERO_EXTEND: 14687 case ISD::ANY_EXTEND: 14688 Promote = true; 14689 break; 14690 case ISD::SHL: 14691 case ISD::SRL: { 14692 SDValue N0 = Op.getOperand(0); 14693 // Look out for (store (shl (load), x)). 14694 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14695 return false; 14696 Promote = true; 14697 break; 14698 } 14699 case ISD::ADD: 14700 case ISD::MUL: 14701 case ISD::AND: 14702 case ISD::OR: 14703 case ISD::XOR: 14704 Commute = true; 14705 // fallthrough 14706 case ISD::SUB: { 14707 SDValue N0 = Op.getOperand(0); 14708 SDValue N1 = Op.getOperand(1); 14709 if (!Commute && MayFoldLoad(N1)) 14710 return false; 14711 // Avoid disabling potential load folding opportunities. 14712 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14713 return false; 14714 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14715 return false; 14716 Promote = true; 14717 } 14718 } 14719 14720 PVT = MVT::i32; 14721 return Promote; 14722} 14723 14724//===----------------------------------------------------------------------===// 14725// X86 Inline Assembly Support 14726//===----------------------------------------------------------------------===// 14727 14728namespace { 14729 // Helper to match a string separated by whitespace. 14730 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) { 14731 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace. 14732 14733 for (unsigned i = 0, e = args.size(); i != e; ++i) { 14734 StringRef piece(*args[i]); 14735 if (!s.startswith(piece)) // Check if the piece matches. 14736 return false; 14737 14738 s = s.substr(piece.size()); 14739 StringRef::size_type pos = s.find_first_not_of(" \t"); 14740 if (pos == 0) // We matched a prefix. 14741 return false; 14742 14743 s = s.substr(pos); 14744 } 14745 14746 return s.empty(); 14747 } 14748 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={}; 14749} 14750 14751bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14752 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14753 14754 std::string AsmStr = IA->getAsmString(); 14755 14756 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14757 if (!Ty || Ty->getBitWidth() % 16 != 0) 14758 return false; 14759 14760 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14761 SmallVector<StringRef, 4> AsmPieces; 14762 SplitString(AsmStr, AsmPieces, ";\n"); 14763 14764 switch (AsmPieces.size()) { 14765 default: return false; 14766 case 1: 14767 // FIXME: this should verify that we are targeting a 486 or better. If not, 14768 // we will turn this bswap into something that will be lowered to logical 14769 // ops instead of emitting the bswap asm. For now, we don't support 486 or 14770 // lower so don't worry about this. 14771 // bswap $0 14772 if (matchAsm(AsmPieces[0], "bswap", "$0") || 14773 matchAsm(AsmPieces[0], "bswapl", "$0") || 14774 matchAsm(AsmPieces[0], "bswapq", "$0") || 14775 matchAsm(AsmPieces[0], "bswap", "${0:q}") || 14776 matchAsm(AsmPieces[0], "bswapl", "${0:q}") || 14777 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) { 14778 // No need to check constraints, nothing other than the equivalent of 14779 // "=r,0" would be valid here. 14780 return IntrinsicLowering::LowerToByteSwap(CI); 14781 } 14782 14783 // rorw $$8, ${0:w} --> llvm.bswap.i16 14784 if (CI->getType()->isIntegerTy(16) && 14785 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14786 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") || 14787 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) { 14788 AsmPieces.clear(); 14789 const std::string &ConstraintsStr = IA->getConstraintString(); 14790 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14791 std::sort(AsmPieces.begin(), AsmPieces.end()); 14792 if (AsmPieces.size() == 4 && 14793 AsmPieces[0] == "~{cc}" && 14794 AsmPieces[1] == "~{dirflag}" && 14795 AsmPieces[2] == "~{flags}" && 14796 AsmPieces[3] == "~{fpsr}") 14797 return IntrinsicLowering::LowerToByteSwap(CI); 14798 } 14799 break; 14800 case 3: 14801 if (CI->getType()->isIntegerTy(32) && 14802 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 && 14803 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") && 14804 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") && 14805 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) { 14806 AsmPieces.clear(); 14807 const std::string &ConstraintsStr = IA->getConstraintString(); 14808 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14809 std::sort(AsmPieces.begin(), AsmPieces.end()); 14810 if (AsmPieces.size() == 4 && 14811 AsmPieces[0] == "~{cc}" && 14812 AsmPieces[1] == "~{dirflag}" && 14813 AsmPieces[2] == "~{flags}" && 14814 AsmPieces[3] == "~{fpsr}") 14815 return IntrinsicLowering::LowerToByteSwap(CI); 14816 } 14817 14818 if (CI->getType()->isIntegerTy(64)) { 14819 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14820 if (Constraints.size() >= 2 && 14821 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14822 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14823 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14824 if (matchAsm(AsmPieces[0], "bswap", "%eax") && 14825 matchAsm(AsmPieces[1], "bswap", "%edx") && 14826 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx")) 14827 return IntrinsicLowering::LowerToByteSwap(CI); 14828 } 14829 } 14830 break; 14831 } 14832 return false; 14833} 14834 14835 14836 14837/// getConstraintType - Given a constraint letter, return the type of 14838/// constraint it is for this target. 14839X86TargetLowering::ConstraintType 14840X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14841 if (Constraint.size() == 1) { 14842 switch (Constraint[0]) { 14843 case 'R': 14844 case 'q': 14845 case 'Q': 14846 case 'f': 14847 case 't': 14848 case 'u': 14849 case 'y': 14850 case 'x': 14851 case 'Y': 14852 case 'l': 14853 return C_RegisterClass; 14854 case 'a': 14855 case 'b': 14856 case 'c': 14857 case 'd': 14858 case 'S': 14859 case 'D': 14860 case 'A': 14861 return C_Register; 14862 case 'I': 14863 case 'J': 14864 case 'K': 14865 case 'L': 14866 case 'M': 14867 case 'N': 14868 case 'G': 14869 case 'C': 14870 case 'e': 14871 case 'Z': 14872 return C_Other; 14873 default: 14874 break; 14875 } 14876 } 14877 return TargetLowering::getConstraintType(Constraint); 14878} 14879 14880/// Examine constraint type and operand type and determine a weight value. 14881/// This object must already have been set up with the operand type 14882/// and the current alternative constraint selected. 14883TargetLowering::ConstraintWeight 14884 X86TargetLowering::getSingleConstraintMatchWeight( 14885 AsmOperandInfo &info, const char *constraint) const { 14886 ConstraintWeight weight = CW_Invalid; 14887 Value *CallOperandVal = info.CallOperandVal; 14888 // If we don't have a value, we can't do a match, 14889 // but allow it at the lowest weight. 14890 if (CallOperandVal == NULL) 14891 return CW_Default; 14892 Type *type = CallOperandVal->getType(); 14893 // Look at the constraint type. 14894 switch (*constraint) { 14895 default: 14896 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 14897 case 'R': 14898 case 'q': 14899 case 'Q': 14900 case 'a': 14901 case 'b': 14902 case 'c': 14903 case 'd': 14904 case 'S': 14905 case 'D': 14906 case 'A': 14907 if (CallOperandVal->getType()->isIntegerTy()) 14908 weight = CW_SpecificReg; 14909 break; 14910 case 'f': 14911 case 't': 14912 case 'u': 14913 if (type->isFloatingPointTy()) 14914 weight = CW_SpecificReg; 14915 break; 14916 case 'y': 14917 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 14918 weight = CW_SpecificReg; 14919 break; 14920 case 'x': 14921 case 'Y': 14922 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || 14923 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX())) 14924 weight = CW_Register; 14925 break; 14926 case 'I': 14927 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 14928 if (C->getZExtValue() <= 31) 14929 weight = CW_Constant; 14930 } 14931 break; 14932 case 'J': 14933 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14934 if (C->getZExtValue() <= 63) 14935 weight = CW_Constant; 14936 } 14937 break; 14938 case 'K': 14939 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14940 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 14941 weight = CW_Constant; 14942 } 14943 break; 14944 case 'L': 14945 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14946 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 14947 weight = CW_Constant; 14948 } 14949 break; 14950 case 'M': 14951 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14952 if (C->getZExtValue() <= 3) 14953 weight = CW_Constant; 14954 } 14955 break; 14956 case 'N': 14957 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14958 if (C->getZExtValue() <= 0xff) 14959 weight = CW_Constant; 14960 } 14961 break; 14962 case 'G': 14963 case 'C': 14964 if (dyn_cast<ConstantFP>(CallOperandVal)) { 14965 weight = CW_Constant; 14966 } 14967 break; 14968 case 'e': 14969 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14970 if ((C->getSExtValue() >= -0x80000000LL) && 14971 (C->getSExtValue() <= 0x7fffffffLL)) 14972 weight = CW_Constant; 14973 } 14974 break; 14975 case 'Z': 14976 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14977 if (C->getZExtValue() <= 0xffffffff) 14978 weight = CW_Constant; 14979 } 14980 break; 14981 } 14982 return weight; 14983} 14984 14985/// LowerXConstraint - try to replace an X constraint, which matches anything, 14986/// with another that has more specific requirements based on the type of the 14987/// corresponding operand. 14988const char *X86TargetLowering:: 14989LowerXConstraint(EVT ConstraintVT) const { 14990 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 14991 // 'f' like normal targets. 14992 if (ConstraintVT.isFloatingPoint()) { 14993 if (Subtarget->hasSSE2()) 14994 return "Y"; 14995 if (Subtarget->hasSSE1()) 14996 return "x"; 14997 } 14998 14999 return TargetLowering::LowerXConstraint(ConstraintVT); 15000} 15001 15002/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 15003/// vector. If it is invalid, don't add anything to Ops. 15004void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 15005 std::string &Constraint, 15006 std::vector<SDValue>&Ops, 15007 SelectionDAG &DAG) const { 15008 SDValue Result(0, 0); 15009 15010 // Only support length 1 constraints for now. 15011 if (Constraint.length() > 1) return; 15012 15013 char ConstraintLetter = Constraint[0]; 15014 switch (ConstraintLetter) { 15015 default: break; 15016 case 'I': 15017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15018 if (C->getZExtValue() <= 31) { 15019 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15020 break; 15021 } 15022 } 15023 return; 15024 case 'J': 15025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15026 if (C->getZExtValue() <= 63) { 15027 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15028 break; 15029 } 15030 } 15031 return; 15032 case 'K': 15033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15034 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 15035 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15036 break; 15037 } 15038 } 15039 return; 15040 case 'N': 15041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15042 if (C->getZExtValue() <= 255) { 15043 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15044 break; 15045 } 15046 } 15047 return; 15048 case 'e': { 15049 // 32-bit signed value 15050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15051 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15052 C->getSExtValue())) { 15053 // Widen to 64 bits here to get it sign extended. 15054 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 15055 break; 15056 } 15057 // FIXME gcc accepts some relocatable values here too, but only in certain 15058 // memory models; it's complicated. 15059 } 15060 return; 15061 } 15062 case 'Z': { 15063 // 32-bit unsigned value 15064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 15065 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 15066 C->getZExtValue())) { 15067 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 15068 break; 15069 } 15070 } 15071 // FIXME gcc accepts some relocatable values here too, but only in certain 15072 // memory models; it's complicated. 15073 return; 15074 } 15075 case 'i': { 15076 // Literal immediates are always ok. 15077 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 15078 // Widen to 64 bits here to get it sign extended. 15079 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 15080 break; 15081 } 15082 15083 // In any sort of PIC mode addresses need to be computed at runtime by 15084 // adding in a register or some sort of table lookup. These can't 15085 // be used as immediates. 15086 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 15087 return; 15088 15089 // If we are in non-pic codegen mode, we allow the address of a global (with 15090 // an optional displacement) to be used with 'i'. 15091 GlobalAddressSDNode *GA = 0; 15092 int64_t Offset = 0; 15093 15094 // Match either (GA), (GA+C), (GA+C1+C2), etc. 15095 while (1) { 15096 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 15097 Offset += GA->getOffset(); 15098 break; 15099 } else if (Op.getOpcode() == ISD::ADD) { 15100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15101 Offset += C->getZExtValue(); 15102 Op = Op.getOperand(0); 15103 continue; 15104 } 15105 } else if (Op.getOpcode() == ISD::SUB) { 15106 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 15107 Offset += -C->getZExtValue(); 15108 Op = Op.getOperand(0); 15109 continue; 15110 } 15111 } 15112 15113 // Otherwise, this isn't something we can handle, reject it. 15114 return; 15115 } 15116 15117 const GlobalValue *GV = GA->getGlobal(); 15118 // If we require an extra load to get this address, as in PIC mode, we 15119 // can't accept it. 15120 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 15121 getTargetMachine()))) 15122 return; 15123 15124 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 15125 GA->getValueType(0), Offset); 15126 break; 15127 } 15128 } 15129 15130 if (Result.getNode()) { 15131 Ops.push_back(Result); 15132 return; 15133 } 15134 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 15135} 15136 15137std::pair<unsigned, const TargetRegisterClass*> 15138X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 15139 EVT VT) const { 15140 // First, see if this is a constraint that directly corresponds to an LLVM 15141 // register class. 15142 if (Constraint.size() == 1) { 15143 // GCC Constraint Letters 15144 switch (Constraint[0]) { 15145 default: break; 15146 // TODO: Slight differences here in allocation order and leaving 15147 // RIP in the class. Do they matter any more here than they do 15148 // in the normal allocation? 15149 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 15150 if (Subtarget->is64Bit()) { 15151 if (VT == MVT::i32 || VT == MVT::f32) 15152 return std::make_pair(0U, X86::GR32RegisterClass); 15153 else if (VT == MVT::i16) 15154 return std::make_pair(0U, X86::GR16RegisterClass); 15155 else if (VT == MVT::i8 || VT == MVT::i1) 15156 return std::make_pair(0U, X86::GR8RegisterClass); 15157 else if (VT == MVT::i64 || VT == MVT::f64) 15158 return std::make_pair(0U, X86::GR64RegisterClass); 15159 break; 15160 } 15161 // 32-bit fallthrough 15162 case 'Q': // Q_REGS 15163 if (VT == MVT::i32 || VT == MVT::f32) 15164 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 15165 else if (VT == MVT::i16) 15166 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 15167 else if (VT == MVT::i8 || VT == MVT::i1) 15168 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 15169 else if (VT == MVT::i64) 15170 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 15171 break; 15172 case 'r': // GENERAL_REGS 15173 case 'l': // INDEX_REGS 15174 if (VT == MVT::i8 || VT == MVT::i1) 15175 return std::make_pair(0U, X86::GR8RegisterClass); 15176 if (VT == MVT::i16) 15177 return std::make_pair(0U, X86::GR16RegisterClass); 15178 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 15179 return std::make_pair(0U, X86::GR32RegisterClass); 15180 return std::make_pair(0U, X86::GR64RegisterClass); 15181 case 'R': // LEGACY_REGS 15182 if (VT == MVT::i8 || VT == MVT::i1) 15183 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 15184 if (VT == MVT::i16) 15185 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 15186 if (VT == MVT::i32 || !Subtarget->is64Bit()) 15187 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 15188 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 15189 case 'f': // FP Stack registers. 15190 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 15191 // value to the correct fpstack register class. 15192 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 15193 return std::make_pair(0U, X86::RFP32RegisterClass); 15194 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 15195 return std::make_pair(0U, X86::RFP64RegisterClass); 15196 return std::make_pair(0U, X86::RFP80RegisterClass); 15197 case 'y': // MMX_REGS if MMX allowed. 15198 if (!Subtarget->hasMMX()) break; 15199 return std::make_pair(0U, X86::VR64RegisterClass); 15200 case 'Y': // SSE_REGS if SSE2 allowed 15201 if (!Subtarget->hasSSE2()) break; 15202 // FALL THROUGH. 15203 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed 15204 if (!Subtarget->hasSSE1()) break; 15205 15206 switch (VT.getSimpleVT().SimpleTy) { 15207 default: break; 15208 // Scalar SSE types. 15209 case MVT::f32: 15210 case MVT::i32: 15211 return std::make_pair(0U, X86::FR32RegisterClass); 15212 case MVT::f64: 15213 case MVT::i64: 15214 return std::make_pair(0U, X86::FR64RegisterClass); 15215 // Vector types. 15216 case MVT::v16i8: 15217 case MVT::v8i16: 15218 case MVT::v4i32: 15219 case MVT::v2i64: 15220 case MVT::v4f32: 15221 case MVT::v2f64: 15222 return std::make_pair(0U, X86::VR128RegisterClass); 15223 // AVX types. 15224 case MVT::v32i8: 15225 case MVT::v16i16: 15226 case MVT::v8i32: 15227 case MVT::v4i64: 15228 case MVT::v8f32: 15229 case MVT::v4f64: 15230 return std::make_pair(0U, X86::VR256RegisterClass); 15231 15232 } 15233 break; 15234 } 15235 } 15236 15237 // Use the default implementation in TargetLowering to convert the register 15238 // constraint into a member of a register class. 15239 std::pair<unsigned, const TargetRegisterClass*> Res; 15240 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 15241 15242 // Not found as a standard register? 15243 if (Res.second == 0) { 15244 // Map st(0) -> st(7) -> ST0 15245 if (Constraint.size() == 7 && Constraint[0] == '{' && 15246 tolower(Constraint[1]) == 's' && 15247 tolower(Constraint[2]) == 't' && 15248 Constraint[3] == '(' && 15249 (Constraint[4] >= '0' && Constraint[4] <= '7') && 15250 Constraint[5] == ')' && 15251 Constraint[6] == '}') { 15252 15253 Res.first = X86::ST0+Constraint[4]-'0'; 15254 Res.second = X86::RFP80RegisterClass; 15255 return Res; 15256 } 15257 15258 // GCC allows "st(0)" to be called just plain "st". 15259 if (StringRef("{st}").equals_lower(Constraint)) { 15260 Res.first = X86::ST0; 15261 Res.second = X86::RFP80RegisterClass; 15262 return Res; 15263 } 15264 15265 // flags -> EFLAGS 15266 if (StringRef("{flags}").equals_lower(Constraint)) { 15267 Res.first = X86::EFLAGS; 15268 Res.second = X86::CCRRegisterClass; 15269 return Res; 15270 } 15271 15272 // 'A' means EAX + EDX. 15273 if (Constraint == "A") { 15274 Res.first = X86::EAX; 15275 Res.second = X86::GR32_ADRegisterClass; 15276 return Res; 15277 } 15278 return Res; 15279 } 15280 15281 // Otherwise, check to see if this is a register class of the wrong value 15282 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 15283 // turn into {ax},{dx}. 15284 if (Res.second->hasType(VT)) 15285 return Res; // Correct type already, nothing to do. 15286 15287 // All of the single-register GCC register classes map their values onto 15288 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 15289 // really want an 8-bit or 32-bit register, map to the appropriate register 15290 // class and return the appropriate register. 15291 if (Res.second == X86::GR16RegisterClass) { 15292 if (VT == MVT::i8) { 15293 unsigned DestReg = 0; 15294 switch (Res.first) { 15295 default: break; 15296 case X86::AX: DestReg = X86::AL; break; 15297 case X86::DX: DestReg = X86::DL; break; 15298 case X86::CX: DestReg = X86::CL; break; 15299 case X86::BX: DestReg = X86::BL; break; 15300 } 15301 if (DestReg) { 15302 Res.first = DestReg; 15303 Res.second = X86::GR8RegisterClass; 15304 } 15305 } else if (VT == MVT::i32) { 15306 unsigned DestReg = 0; 15307 switch (Res.first) { 15308 default: break; 15309 case X86::AX: DestReg = X86::EAX; break; 15310 case X86::DX: DestReg = X86::EDX; break; 15311 case X86::CX: DestReg = X86::ECX; break; 15312 case X86::BX: DestReg = X86::EBX; break; 15313 case X86::SI: DestReg = X86::ESI; break; 15314 case X86::DI: DestReg = X86::EDI; break; 15315 case X86::BP: DestReg = X86::EBP; break; 15316 case X86::SP: DestReg = X86::ESP; break; 15317 } 15318 if (DestReg) { 15319 Res.first = DestReg; 15320 Res.second = X86::GR32RegisterClass; 15321 } 15322 } else if (VT == MVT::i64) { 15323 unsigned DestReg = 0; 15324 switch (Res.first) { 15325 default: break; 15326 case X86::AX: DestReg = X86::RAX; break; 15327 case X86::DX: DestReg = X86::RDX; break; 15328 case X86::CX: DestReg = X86::RCX; break; 15329 case X86::BX: DestReg = X86::RBX; break; 15330 case X86::SI: DestReg = X86::RSI; break; 15331 case X86::DI: DestReg = X86::RDI; break; 15332 case X86::BP: DestReg = X86::RBP; break; 15333 case X86::SP: DestReg = X86::RSP; break; 15334 } 15335 if (DestReg) { 15336 Res.first = DestReg; 15337 Res.second = X86::GR64RegisterClass; 15338 } 15339 } 15340 } else if (Res.second == X86::FR32RegisterClass || 15341 Res.second == X86::FR64RegisterClass || 15342 Res.second == X86::VR128RegisterClass) { 15343 // Handle references to XMM physical registers that got mapped into the 15344 // wrong class. This can happen with constraints like {xmm0} where the 15345 // target independent register mapper will just pick the first match it can 15346 // find, ignoring the required type. 15347 if (VT == MVT::f32) 15348 Res.second = X86::FR32RegisterClass; 15349 else if (VT == MVT::f64) 15350 Res.second = X86::FR64RegisterClass; 15351 else if (X86::VR128RegisterClass->hasType(VT)) 15352 Res.second = X86::VR128RegisterClass; 15353 } 15354 15355 return Res; 15356} 15357