X86ISelLowering.cpp revision 67c9d42f93a13286a6977686f9d1ed172d2ced0a
1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86MCTargetExpr.h" 20#include "X86TargetMachine.h" 21#include "X86TargetObjectFile.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/Function.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/LLVMContext.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineJumpTableInfo.h" 35#include "llvm/CodeGen/MachineModuleInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/PseudoSourceValue.h" 38#include "llvm/MC/MCAsmInfo.h" 39#include "llvm/MC/MCContext.h" 40#include "llvm/MC/MCSymbol.h" 41#include "llvm/ADT/BitVector.h" 42#include "llvm/ADT/SmallSet.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/StringExtras.h" 45#include "llvm/ADT/VectorExtras.h" 46#include "llvm/Support/CommandLine.h" 47#include "llvm/Support/Debug.h" 48#include "llvm/Support/ErrorHandling.h" 49#include "llvm/Support/MathExtras.h" 50#include "llvm/Support/raw_ostream.h" 51using namespace llvm; 52 53STATISTIC(NumTailCalls, "Number of tail calls"); 54 55static cl::opt<bool> 56DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); 57 58// Disable16Bit - 16-bit operations typically have a larger encoding than 59// corresponding 32-bit instructions, and 16-bit code is slow on some 60// processors. This is an experimental flag to disable 16-bit operations 61// (which forces them to be Legalized to 32-bit operations). 62static cl::opt<bool> 63Disable16Bit("disable-16bit", cl::Hidden, 64 cl::desc("Disable use of 16-bit instructions")); 65 66// Forward declarations. 67static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 68 SDValue V2); 69 70static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 71 switch (TM.getSubtarget<X86Subtarget>().TargetType) { 72 default: llvm_unreachable("unknown subtarget type"); 73 case X86Subtarget::isDarwin: 74 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 75 return new X8664_MachoTargetObjectFile(); 76 return new X8632_MachoTargetObjectFile(); 77 case X86Subtarget::isELF: 78 return new TargetLoweringObjectFileELF(); 79 case X86Subtarget::isMingw: 80 case X86Subtarget::isCygwin: 81 case X86Subtarget::isWindows: 82 return new TargetLoweringObjectFileCOFF(); 83 } 84 85} 86 87X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 88 : TargetLowering(TM, createTLOF(TM)) { 89 Subtarget = &TM.getSubtarget<X86Subtarget>(); 90 X86ScalarSSEf64 = Subtarget->hasSSE2(); 91 X86ScalarSSEf32 = Subtarget->hasSSE1(); 92 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 93 94 RegInfo = TM.getRegisterInfo(); 95 TD = getTargetData(); 96 97 // Set up the TargetLowering object. 98 99 // X86 is weird, it always uses i8 for shift amounts and setcc results. 100 setShiftAmountType(MVT::i8); 101 setBooleanContents(ZeroOrOneBooleanContent); 102 setSchedulingPreference(SchedulingForRegPressure); 103 setStackPointerRegisterToSaveRestore(X86StackPtr); 104 105 if (Subtarget->isTargetDarwin()) { 106 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 107 setUseUnderscoreSetJmp(false); 108 setUseUnderscoreLongJmp(false); 109 } else if (Subtarget->isTargetMingw()) { 110 // MS runtime is weird: it exports _setjmp, but longjmp! 111 setUseUnderscoreSetJmp(true); 112 setUseUnderscoreLongJmp(false); 113 } else { 114 setUseUnderscoreSetJmp(true); 115 setUseUnderscoreLongJmp(true); 116 } 117 118 // Set up the register classes. 119 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 120 if (!Disable16Bit) 121 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 122 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 123 if (Subtarget->is64Bit()) 124 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 125 126 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 127 128 // We don't accept any truncstore of integer registers. 129 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 130 if (!Disable16Bit) 131 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 132 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 133 if (!Disable16Bit) 134 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 135 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 136 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 137 138 // SETOEQ and SETUNE require checking two conditions. 139 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 140 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 141 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 142 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 143 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 144 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 145 146 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 147 // operation. 148 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 149 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 150 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 151 152 if (Subtarget->is64Bit()) { 153 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 154 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 155 } else if (!UseSoftFloat) { 156 if (X86ScalarSSEf64) { 157 // We have an impenetrably clever algorithm for ui64->double only. 158 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 159 } 160 // We have an algorithm for SSE2, and we turn this into a 64-bit 161 // FILD for other targets. 162 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 163 } 164 165 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 166 // this operation. 167 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 168 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 169 170 if (!UseSoftFloat) { 171 // SSE has no i16 to fp conversion, only i32 172 if (X86ScalarSSEf32) { 173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 174 // f32 and f64 cases are Legal, f80 case is not 175 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 176 } else { 177 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 179 } 180 } else { 181 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 182 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 183 } 184 185 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 186 // are Legal, f80 is custom lowered. 187 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 188 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 189 190 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 191 // this operation. 192 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 193 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 194 195 if (X86ScalarSSEf32) { 196 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 197 // f32 and f64 cases are Legal, f80 case is not 198 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 199 } else { 200 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 202 } 203 204 // Handle FP_TO_UINT by promoting the destination to a larger signed 205 // conversion. 206 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 207 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 208 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 209 210 if (Subtarget->is64Bit()) { 211 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 213 } else if (!UseSoftFloat) { 214 if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) 215 // Expand FP_TO_UINT into a select. 216 // FIXME: We would like to use a Custom expander here eventually to do 217 // the optimal thing for SSE vs. the default expansion in the legalizer. 218 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 219 else 220 // With SSE3 we can use fisttpll to convert to a signed i64; without 221 // SSE, we're stuck with a fistpll. 222 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 223 } 224 225 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 226 if (!X86ScalarSSEf64) { 227 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); 228 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); 229 } 230 231 // Scalar integer divide and remainder are lowered to use operations that 232 // produce two results, to match the available instructions. This exposes 233 // the two-result form to trivial CSE, which is able to combine x/y and x%y 234 // into a single instruction. 235 // 236 // Scalar integer multiply-high is also lowered to use two-result 237 // operations, to match the available instructions. However, plain multiply 238 // (low) operations are left as Legal, as there are single-result 239 // instructions for this in x86. Using the two-result multiply instructions 240 // when both high and low results are needed must be arranged by dagcombine. 241 setOperationAction(ISD::MULHS , MVT::i8 , Expand); 242 setOperationAction(ISD::MULHU , MVT::i8 , Expand); 243 setOperationAction(ISD::SDIV , MVT::i8 , Expand); 244 setOperationAction(ISD::UDIV , MVT::i8 , Expand); 245 setOperationAction(ISD::SREM , MVT::i8 , Expand); 246 setOperationAction(ISD::UREM , MVT::i8 , Expand); 247 setOperationAction(ISD::MULHS , MVT::i16 , Expand); 248 setOperationAction(ISD::MULHU , MVT::i16 , Expand); 249 setOperationAction(ISD::SDIV , MVT::i16 , Expand); 250 setOperationAction(ISD::UDIV , MVT::i16 , Expand); 251 setOperationAction(ISD::SREM , MVT::i16 , Expand); 252 setOperationAction(ISD::UREM , MVT::i16 , Expand); 253 setOperationAction(ISD::MULHS , MVT::i32 , Expand); 254 setOperationAction(ISD::MULHU , MVT::i32 , Expand); 255 setOperationAction(ISD::SDIV , MVT::i32 , Expand); 256 setOperationAction(ISD::UDIV , MVT::i32 , Expand); 257 setOperationAction(ISD::SREM , MVT::i32 , Expand); 258 setOperationAction(ISD::UREM , MVT::i32 , Expand); 259 setOperationAction(ISD::MULHS , MVT::i64 , Expand); 260 setOperationAction(ISD::MULHU , MVT::i64 , Expand); 261 setOperationAction(ISD::SDIV , MVT::i64 , Expand); 262 setOperationAction(ISD::UDIV , MVT::i64 , Expand); 263 setOperationAction(ISD::SREM , MVT::i64 , Expand); 264 setOperationAction(ISD::UREM , MVT::i64 , Expand); 265 266 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 267 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 268 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 269 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 270 if (Subtarget->is64Bit()) 271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 275 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 276 setOperationAction(ISD::FREM , MVT::f32 , Expand); 277 setOperationAction(ISD::FREM , MVT::f64 , Expand); 278 setOperationAction(ISD::FREM , MVT::f80 , Expand); 279 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 280 281 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 282 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 283 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 284 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 285 if (Disable16Bit) { 286 setOperationAction(ISD::CTTZ , MVT::i16 , Expand); 287 setOperationAction(ISD::CTLZ , MVT::i16 , Expand); 288 } else { 289 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 290 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 291 } 292 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 293 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 294 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 295 if (Subtarget->is64Bit()) { 296 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 297 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 298 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 299 } 300 301 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 302 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 303 304 // These should be promoted to a larger select which is supported. 305 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 306 // X86 wants to expand cmov itself. 307 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 308 if (Disable16Bit) 309 setOperationAction(ISD::SELECT , MVT::i16 , Expand); 310 else 311 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 312 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 313 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 314 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 315 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 316 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 317 if (Disable16Bit) 318 setOperationAction(ISD::SETCC , MVT::i16 , Expand); 319 else 320 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 321 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 322 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 323 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 324 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 325 if (Subtarget->is64Bit()) { 326 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 327 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 328 } 329 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 330 331 // Darwin ABI issue. 332 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 333 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 334 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 335 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 336 if (Subtarget->is64Bit()) 337 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 338 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 339 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 340 if (Subtarget->is64Bit()) { 341 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 342 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 343 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 344 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 345 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 346 } 347 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 348 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 349 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 350 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 351 if (Subtarget->is64Bit()) { 352 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 353 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 354 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 355 } 356 357 if (Subtarget->hasSSE1()) 358 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 359 360 if (!Subtarget->hasSSE2()) 361 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 362 363 // Expand certain atomics 364 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); 365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); 366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); 367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 368 369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); 370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); 371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); 372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 373 374 if (!Subtarget->is64Bit()) { 375 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 376 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 377 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 378 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 379 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 380 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 381 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 382 } 383 384 // FIXME - use subtarget debug flags 385 if (!Subtarget->isTargetDarwin() && 386 !Subtarget->isTargetELF() && 387 !Subtarget->isTargetCygMing()) { 388 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 389 } 390 391 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 392 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 393 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 394 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 395 if (Subtarget->is64Bit()) { 396 setExceptionPointerRegister(X86::RAX); 397 setExceptionSelectorRegister(X86::RDX); 398 } else { 399 setExceptionPointerRegister(X86::EAX); 400 setExceptionSelectorRegister(X86::EDX); 401 } 402 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 404 405 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 406 407 setOperationAction(ISD::TRAP, MVT::Other, Legal); 408 409 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 410 setOperationAction(ISD::VASTART , MVT::Other, Custom); 411 setOperationAction(ISD::VAEND , MVT::Other, Expand); 412 if (Subtarget->is64Bit()) { 413 setOperationAction(ISD::VAARG , MVT::Other, Custom); 414 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 415 } else { 416 setOperationAction(ISD::VAARG , MVT::Other, Expand); 417 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 418 } 419 420 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 421 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 422 if (Subtarget->is64Bit()) 423 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 424 if (Subtarget->isTargetCygMing()) 425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 426 else 427 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 428 429 if (!UseSoftFloat && X86ScalarSSEf64) { 430 // f32 and f64 use SSE. 431 // Set up the FP register classes. 432 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 433 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 434 435 // Use ANDPD to simulate FABS. 436 setOperationAction(ISD::FABS , MVT::f64, Custom); 437 setOperationAction(ISD::FABS , MVT::f32, Custom); 438 439 // Use XORP to simulate FNEG. 440 setOperationAction(ISD::FNEG , MVT::f64, Custom); 441 setOperationAction(ISD::FNEG , MVT::f32, Custom); 442 443 // Use ANDPD and ORPD to simulate FCOPYSIGN. 444 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 445 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 446 447 // We don't support sin/cos/fmod 448 setOperationAction(ISD::FSIN , MVT::f64, Expand); 449 setOperationAction(ISD::FCOS , MVT::f64, Expand); 450 setOperationAction(ISD::FSIN , MVT::f32, Expand); 451 setOperationAction(ISD::FCOS , MVT::f32, Expand); 452 453 // Expand FP immediates into loads from the stack, except for the special 454 // cases we handle. 455 addLegalFPImmediate(APFloat(+0.0)); // xorpd 456 addLegalFPImmediate(APFloat(+0.0f)); // xorps 457 } else if (!UseSoftFloat && X86ScalarSSEf32) { 458 // Use SSE for f32, x87 for f64. 459 // Set up the FP register classes. 460 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 461 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 462 463 // Use ANDPS to simulate FABS. 464 setOperationAction(ISD::FABS , MVT::f32, Custom); 465 466 // Use XORP to simulate FNEG. 467 setOperationAction(ISD::FNEG , MVT::f32, Custom); 468 469 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 470 471 // Use ANDPS and ORPS to simulate FCOPYSIGN. 472 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 473 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 474 475 // We don't support sin/cos/fmod 476 setOperationAction(ISD::FSIN , MVT::f32, Expand); 477 setOperationAction(ISD::FCOS , MVT::f32, Expand); 478 479 // Special cases we handle for FP constants. 480 addLegalFPImmediate(APFloat(+0.0f)); // xorps 481 addLegalFPImmediate(APFloat(+0.0)); // FLD0 482 addLegalFPImmediate(APFloat(+1.0)); // FLD1 483 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 484 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 485 486 if (!UnsafeFPMath) { 487 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 488 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 489 } 490 } else if (!UseSoftFloat) { 491 // f32 and f64 in x87. 492 // Set up the FP register classes. 493 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 494 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 495 496 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 497 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 498 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 499 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 500 501 if (!UnsafeFPMath) { 502 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 503 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 504 } 505 addLegalFPImmediate(APFloat(+0.0)); // FLD0 506 addLegalFPImmediate(APFloat(+1.0)); // FLD1 507 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 508 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 509 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 510 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 511 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 512 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 513 } 514 515 // Long double always uses X87. 516 if (!UseSoftFloat) { 517 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 518 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 519 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 520 { 521 bool ignored; 522 APFloat TmpFlt(+0.0); 523 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 524 &ignored); 525 addLegalFPImmediate(TmpFlt); // FLD0 526 TmpFlt.changeSign(); 527 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 528 APFloat TmpFlt2(+1.0); 529 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 530 &ignored); 531 addLegalFPImmediate(TmpFlt2); // FLD1 532 TmpFlt2.changeSign(); 533 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 534 } 535 536 if (!UnsafeFPMath) { 537 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 538 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 539 } 540 } 541 542 // Always use a library call for pow. 543 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 544 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 545 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 546 547 setOperationAction(ISD::FLOG, MVT::f80, Expand); 548 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 549 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 550 setOperationAction(ISD::FEXP, MVT::f80, Expand); 551 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 552 553 // First set operation action for all vector types to either promote 554 // (for widening) or expand (for scalarization). Then we will selectively 555 // turn on ones that can be effectively codegen'd. 556 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 557 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 558 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 560 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 561 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 562 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 563 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 564 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 565 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 566 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 567 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 568 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 569 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 570 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 571 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 572 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 573 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 574 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 575 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 576 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 577 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 578 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 579 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 580 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 581 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 582 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 583 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 584 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 585 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 586 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 587 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 588 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 589 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 590 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 591 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 592 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 593 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 594 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 595 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 596 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); 597 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 598 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 599 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 600 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 601 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 602 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 603 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 604 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 605 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 606 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 607 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 608 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 609 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 610 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 611 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 612 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 613 setTruncStoreAction((MVT::SimpleValueType)VT, 614 (MVT::SimpleValueType)InnerVT, Expand); 615 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 616 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 617 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 618 } 619 620 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 621 // with -msoft-float, disable use of MMX as well. 622 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { 623 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); 624 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); 625 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); 626 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); 627 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); 628 629 setOperationAction(ISD::ADD, MVT::v8i8, Legal); 630 setOperationAction(ISD::ADD, MVT::v4i16, Legal); 631 setOperationAction(ISD::ADD, MVT::v2i32, Legal); 632 setOperationAction(ISD::ADD, MVT::v1i64, Legal); 633 634 setOperationAction(ISD::SUB, MVT::v8i8, Legal); 635 setOperationAction(ISD::SUB, MVT::v4i16, Legal); 636 setOperationAction(ISD::SUB, MVT::v2i32, Legal); 637 setOperationAction(ISD::SUB, MVT::v1i64, Legal); 638 639 setOperationAction(ISD::MULHS, MVT::v4i16, Legal); 640 setOperationAction(ISD::MUL, MVT::v4i16, Legal); 641 642 setOperationAction(ISD::AND, MVT::v8i8, Promote); 643 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); 644 setOperationAction(ISD::AND, MVT::v4i16, Promote); 645 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); 646 setOperationAction(ISD::AND, MVT::v2i32, Promote); 647 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); 648 setOperationAction(ISD::AND, MVT::v1i64, Legal); 649 650 setOperationAction(ISD::OR, MVT::v8i8, Promote); 651 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); 652 setOperationAction(ISD::OR, MVT::v4i16, Promote); 653 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); 654 setOperationAction(ISD::OR, MVT::v2i32, Promote); 655 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); 656 setOperationAction(ISD::OR, MVT::v1i64, Legal); 657 658 setOperationAction(ISD::XOR, MVT::v8i8, Promote); 659 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); 660 setOperationAction(ISD::XOR, MVT::v4i16, Promote); 661 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); 662 setOperationAction(ISD::XOR, MVT::v2i32, Promote); 663 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); 664 setOperationAction(ISD::XOR, MVT::v1i64, Legal); 665 666 setOperationAction(ISD::LOAD, MVT::v8i8, Promote); 667 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); 668 setOperationAction(ISD::LOAD, MVT::v4i16, Promote); 669 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); 670 setOperationAction(ISD::LOAD, MVT::v2i32, Promote); 671 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); 672 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); 673 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); 674 setOperationAction(ISD::LOAD, MVT::v1i64, Legal); 675 676 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); 677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); 678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); 679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); 680 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); 681 682 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); 683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); 684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); 685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); 686 687 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); 688 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); 689 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); 690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); 691 692 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); 693 694 setOperationAction(ISD::SELECT, MVT::v8i8, Promote); 695 setOperationAction(ISD::SELECT, MVT::v4i16, Promote); 696 setOperationAction(ISD::SELECT, MVT::v2i32, Promote); 697 setOperationAction(ISD::SELECT, MVT::v1i64, Custom); 698 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); 699 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); 700 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); 701 } 702 703 if (!UseSoftFloat && Subtarget->hasSSE1()) { 704 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 705 706 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 707 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 708 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 709 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 710 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 711 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 712 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 713 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 714 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 716 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 717 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); 718 } 719 720 if (!UseSoftFloat && Subtarget->hasSSE2()) { 721 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 722 723 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 724 // registers cannot be used even for integer operations. 725 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 726 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 727 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 728 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 729 730 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 731 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 732 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 733 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 734 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 735 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 736 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 737 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 738 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 739 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 740 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 741 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 742 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 743 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 744 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 745 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 746 747 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); 748 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); 749 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); 750 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); 751 752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 754 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 757 758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 763 764 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 765 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 766 EVT VT = (MVT::SimpleValueType)i; 767 // Do not attempt to custom lower non-power-of-2 vectors 768 if (!isPowerOf2_32(VT.getVectorNumElements())) 769 continue; 770 // Do not attempt to custom lower non-128-bit vectors 771 if (!VT.is128BitVector()) 772 continue; 773 setOperationAction(ISD::BUILD_VECTOR, 774 VT.getSimpleVT().SimpleTy, Custom); 775 setOperationAction(ISD::VECTOR_SHUFFLE, 776 VT.getSimpleVT().SimpleTy, Custom); 777 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 778 VT.getSimpleVT().SimpleTy, Custom); 779 } 780 781 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 783 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 787 788 if (Subtarget->is64Bit()) { 789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 791 } 792 793 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 794 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 795 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 796 EVT VT = SVT; 797 798 // Do not attempt to promote non-128-bit vectors 799 if (!VT.is128BitVector()) { 800 continue; 801 } 802 setOperationAction(ISD::AND, SVT, Promote); 803 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 804 setOperationAction(ISD::OR, SVT, Promote); 805 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 806 setOperationAction(ISD::XOR, SVT, Promote); 807 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 808 setOperationAction(ISD::LOAD, SVT, Promote); 809 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 810 setOperationAction(ISD::SELECT, SVT, Promote); 811 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 812 } 813 814 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 815 816 // Custom lower v2i64 and v2f64 selects. 817 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 818 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 819 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 820 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 821 822 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 823 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 824 if (!DisableMMX && Subtarget->hasMMX()) { 825 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); 826 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 827 } 828 } 829 830 if (Subtarget->hasSSE41()) { 831 // FIXME: Do we need to handle scalar-to-vector here? 832 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 833 834 // i8 and i16 vectors are custom , because the source register and source 835 // source memory operand types are not the same width. f32 vectors are 836 // custom since the immediate controlling the insert encodes additional 837 // information. 838 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 842 843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 844 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 845 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 847 848 if (Subtarget->is64Bit()) { 849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 851 } 852 } 853 854 if (Subtarget->hasSSE42()) { 855 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); 856 } 857 858 if (!UseSoftFloat && Subtarget->hasAVX()) { 859 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 860 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 861 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 862 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 863 864 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 865 setOperationAction(ISD::LOAD, MVT::v8i32, Legal); 866 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 867 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 868 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 869 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 870 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 871 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 872 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 873 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 874 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); 875 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); 876 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); 877 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 878 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); 879 880 // Operations to consider commented out -v16i16 v32i8 881 //setOperationAction(ISD::ADD, MVT::v16i16, Legal); 882 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 883 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 884 //setOperationAction(ISD::SUB, MVT::v32i8, Legal); 885 //setOperationAction(ISD::SUB, MVT::v16i16, Legal); 886 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 887 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 888 //setOperationAction(ISD::MUL, MVT::v16i16, Legal); 889 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 890 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 891 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 892 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 893 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 894 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 895 896 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); 897 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); 898 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); 899 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); 900 901 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); 902 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); 903 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); 904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); 905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); 906 907 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); 909 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); 910 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); 911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); 912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); 913 914#if 0 915 // Not sure we want to do this since there are no 256-bit integer 916 // operations in AVX 917 918 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 919 // This includes 256-bit vectors 920 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { 921 EVT VT = (MVT::SimpleValueType)i; 922 923 // Do not attempt to custom lower non-power-of-2 vectors 924 if (!isPowerOf2_32(VT.getVectorNumElements())) 925 continue; 926 927 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); 928 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); 929 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 930 } 931 932 if (Subtarget->is64Bit()) { 933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); 934 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); 935 } 936#endif 937 938#if 0 939 // Not sure we want to do this since there are no 256-bit integer 940 // operations in AVX 941 942 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. 943 // Including 256-bit vectors 944 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { 945 EVT VT = (MVT::SimpleValueType)i; 946 947 if (!VT.is256BitVector()) { 948 continue; 949 } 950 setOperationAction(ISD::AND, VT, Promote); 951 AddPromotedToType (ISD::AND, VT, MVT::v4i64); 952 setOperationAction(ISD::OR, VT, Promote); 953 AddPromotedToType (ISD::OR, VT, MVT::v4i64); 954 setOperationAction(ISD::XOR, VT, Promote); 955 AddPromotedToType (ISD::XOR, VT, MVT::v4i64); 956 setOperationAction(ISD::LOAD, VT, Promote); 957 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); 958 setOperationAction(ISD::SELECT, VT, Promote); 959 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); 960 } 961 962 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 963#endif 964 } 965 966 // We want to custom lower some of our intrinsics. 967 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 968 969 // Add/Sub/Mul with overflow operations are custom lowered. 970 setOperationAction(ISD::SADDO, MVT::i32, Custom); 971 setOperationAction(ISD::SADDO, MVT::i64, Custom); 972 setOperationAction(ISD::UADDO, MVT::i32, Custom); 973 setOperationAction(ISD::UADDO, MVT::i64, Custom); 974 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 975 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 976 setOperationAction(ISD::USUBO, MVT::i32, Custom); 977 setOperationAction(ISD::USUBO, MVT::i64, Custom); 978 setOperationAction(ISD::SMULO, MVT::i32, Custom); 979 setOperationAction(ISD::SMULO, MVT::i64, Custom); 980 981 if (!Subtarget->is64Bit()) { 982 // These libcalls are not available in 32-bit. 983 setLibcallName(RTLIB::SHL_I128, 0); 984 setLibcallName(RTLIB::SRL_I128, 0); 985 setLibcallName(RTLIB::SRA_I128, 0); 986 } 987 988 // We have target-specific dag combine patterns for the following nodes: 989 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 990 setTargetDAGCombine(ISD::BUILD_VECTOR); 991 setTargetDAGCombine(ISD::SELECT); 992 setTargetDAGCombine(ISD::SHL); 993 setTargetDAGCombine(ISD::SRA); 994 setTargetDAGCombine(ISD::SRL); 995 setTargetDAGCombine(ISD::OR); 996 setTargetDAGCombine(ISD::STORE); 997 setTargetDAGCombine(ISD::MEMBARRIER); 998 setTargetDAGCombine(ISD::ZERO_EXTEND); 999 if (Subtarget->is64Bit()) 1000 setTargetDAGCombine(ISD::MUL); 1001 1002 computeRegisterProperties(); 1003 1004 // FIXME: These should be based on subtarget info. Plus, the values should 1005 // be smaller when we are in optimizing for size mode. 1006 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1007 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores 1008 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores 1009 setPrefLoopAlignment(16); 1010 benefitFromCodePlacementOpt = true; 1011} 1012 1013 1014MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { 1015 return MVT::i8; 1016} 1017 1018 1019/// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1020/// the desired ByVal argument alignment. 1021static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) { 1022 if (MaxAlign == 16) 1023 return; 1024 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1025 if (VTy->getBitWidth() == 128) 1026 MaxAlign = 16; 1027 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1028 unsigned EltAlign = 0; 1029 getMaxByValAlign(ATy->getElementType(), EltAlign); 1030 if (EltAlign > MaxAlign) 1031 MaxAlign = EltAlign; 1032 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) { 1033 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1034 unsigned EltAlign = 0; 1035 getMaxByValAlign(STy->getElementType(i), EltAlign); 1036 if (EltAlign > MaxAlign) 1037 MaxAlign = EltAlign; 1038 if (MaxAlign == 16) 1039 break; 1040 } 1041 } 1042 return; 1043} 1044 1045/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1046/// function arguments in the caller parameter area. For X86, aggregates 1047/// that contain SSE vectors are placed at 16-byte boundaries while the rest 1048/// are at 4-byte boundaries. 1049unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1050 if (Subtarget->is64Bit()) { 1051 // Max of 8 and alignment of type. 1052 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1053 if (TyAlign > 8) 1054 return TyAlign; 1055 return 8; 1056 } 1057 1058 unsigned Align = 4; 1059 if (Subtarget->hasSSE1()) 1060 getMaxByValAlign(Ty, Align); 1061 return Align; 1062} 1063 1064/// getOptimalMemOpType - Returns the target specific optimal type for load 1065/// and store operations as a result of memset, memcpy, and memmove 1066/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for 1067/// determining it. 1068EVT 1069X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, 1070 bool isSrcConst, bool isSrcStr, 1071 SelectionDAG &DAG) const { 1072 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1073 // linux. This is because the stack realignment code can't handle certain 1074 // cases like PR2962. This should be removed when PR2962 is fixed. 1075 const Function *F = DAG.getMachineFunction().getFunction(); 1076 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 1077 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { 1078 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) 1079 return MVT::v4i32; 1080 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) 1081 return MVT::v4f32; 1082 } 1083 if (Subtarget->is64Bit() && Size >= 8) 1084 return MVT::i64; 1085 return MVT::i32; 1086} 1087 1088/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1089/// current function. The returned value is a member of the 1090/// MachineJumpTableInfo::JTEntryKind enum. 1091unsigned X86TargetLowering::getJumpTableEncoding() const { 1092 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1093 // symbol. 1094 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1095 Subtarget->isPICStyleGOT()) 1096 return MachineJumpTableInfo::EK_Custom32; 1097 1098 // Otherwise, use the normal jump table encoding heuristics. 1099 return TargetLowering::getJumpTableEncoding(); 1100} 1101 1102/// getPICBaseSymbol - Return the X86-32 PIC base. 1103MCSymbol * 1104X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF, 1105 MCContext &Ctx) const { 1106 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo(); 1107 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+ 1108 Twine(MF->getFunctionNumber())+"$pb"); 1109} 1110 1111 1112const MCExpr * 1113X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1114 const MachineBasicBlock *MBB, 1115 unsigned uid,MCContext &Ctx) const{ 1116 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1117 Subtarget->isPICStyleGOT()); 1118 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1119 // entries. 1120 return X86MCTargetExpr::Create(MBB->getSymbol(Ctx), 1121 X86MCTargetExpr::GOTOFF, Ctx); 1122} 1123 1124/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1125/// jumptable. 1126SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1127 SelectionDAG &DAG) const { 1128 if (!Subtarget->is64Bit()) 1129 // This doesn't have DebugLoc associated with it, but is not really the 1130 // same as a Register. 1131 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(), 1132 getPointerTy()); 1133 return Table; 1134} 1135 1136/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1137/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1138/// MCExpr. 1139const MCExpr *X86TargetLowering:: 1140getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1141 MCContext &Ctx) const { 1142 // X86-64 uses RIP relative addressing based on the jump table label. 1143 if (Subtarget->isPICStyleRIPRel()) 1144 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1145 1146 // Otherwise, the reference is relative to the PIC base. 1147 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx); 1148} 1149 1150/// getFunctionAlignment - Return the Log2 alignment of this function. 1151unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { 1152 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; 1153} 1154 1155//===----------------------------------------------------------------------===// 1156// Return Value Calling Convention Implementation 1157//===----------------------------------------------------------------------===// 1158 1159#include "X86GenCallingConv.inc" 1160 1161bool 1162X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1163 const SmallVectorImpl<EVT> &OutTys, 1164 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1165 SelectionDAG &DAG) { 1166 SmallVector<CCValAssign, 16> RVLocs; 1167 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1168 RVLocs, *DAG.getContext()); 1169 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86); 1170} 1171 1172SDValue 1173X86TargetLowering::LowerReturn(SDValue Chain, 1174 CallingConv::ID CallConv, bool isVarArg, 1175 const SmallVectorImpl<ISD::OutputArg> &Outs, 1176 DebugLoc dl, SelectionDAG &DAG) { 1177 1178 SmallVector<CCValAssign, 16> RVLocs; 1179 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1180 RVLocs, *DAG.getContext()); 1181 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1182 1183 // Add the regs to the liveout set for the function. 1184 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1185 for (unsigned i = 0; i != RVLocs.size(); ++i) 1186 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1187 MRI.addLiveOut(RVLocs[i].getLocReg()); 1188 1189 SDValue Flag; 1190 1191 SmallVector<SDValue, 6> RetOps; 1192 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1193 // Operand #1 = Bytes To Pop 1194 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16)); 1195 1196 // Copy the result values into the output registers. 1197 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1198 CCValAssign &VA = RVLocs[i]; 1199 assert(VA.isRegLoc() && "Can only return in registers!"); 1200 SDValue ValToCopy = Outs[i].Val; 1201 1202 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1203 // the RET instruction and handled by the FP Stackifier. 1204 if (VA.getLocReg() == X86::ST0 || 1205 VA.getLocReg() == X86::ST1) { 1206 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1207 // change the value to the FP stack register class. 1208 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1209 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1210 RetOps.push_back(ValToCopy); 1211 // Don't emit a copytoreg. 1212 continue; 1213 } 1214 1215 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1216 // which is returned in RAX / RDX. 1217 if (Subtarget->is64Bit()) { 1218 EVT ValVT = ValToCopy.getValueType(); 1219 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { 1220 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); 1221 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) 1222 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); 1223 } 1224 } 1225 1226 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1227 Flag = Chain.getValue(1); 1228 } 1229 1230 // The x86-64 ABI for returning structs by value requires that we copy 1231 // the sret argument into %rax for the return. We saved the argument into 1232 // a virtual register in the entry block, so now we copy the value out 1233 // and into %rax. 1234 if (Subtarget->is64Bit() && 1235 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1236 MachineFunction &MF = DAG.getMachineFunction(); 1237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1238 unsigned Reg = FuncInfo->getSRetReturnReg(); 1239 if (!Reg) { 1240 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64)); 1241 FuncInfo->setSRetReturnReg(Reg); 1242 } 1243 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1244 1245 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1246 Flag = Chain.getValue(1); 1247 1248 // RAX now acts like a return value. 1249 MRI.addLiveOut(X86::RAX); 1250 } 1251 1252 RetOps[0] = Chain; // Update chain. 1253 1254 // Add the flag if we have it. 1255 if (Flag.getNode()) 1256 RetOps.push_back(Flag); 1257 1258 return DAG.getNode(X86ISD::RET_FLAG, dl, 1259 MVT::Other, &RetOps[0], RetOps.size()); 1260} 1261 1262/// LowerCallResult - Lower the result values of a call into the 1263/// appropriate copies out of appropriate physical registers. 1264/// 1265SDValue 1266X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1267 CallingConv::ID CallConv, bool isVarArg, 1268 const SmallVectorImpl<ISD::InputArg> &Ins, 1269 DebugLoc dl, SelectionDAG &DAG, 1270 SmallVectorImpl<SDValue> &InVals) { 1271 1272 // Assign locations to each value returned by this call. 1273 SmallVector<CCValAssign, 16> RVLocs; 1274 bool Is64Bit = Subtarget->is64Bit(); 1275 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1276 RVLocs, *DAG.getContext()); 1277 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1278 1279 // Copy all of the result registers out of their specified physreg. 1280 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1281 CCValAssign &VA = RVLocs[i]; 1282 EVT CopyVT = VA.getValVT(); 1283 1284 // If this is x86-64, and we disabled SSE, we can't return FP values 1285 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1286 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { 1287 llvm_report_error("SSE register return with SSE disabled"); 1288 } 1289 1290 // If this is a call to a function that returns an fp value on the floating 1291 // point stack, but where we prefer to use the value in xmm registers, copy 1292 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1293 if ((VA.getLocReg() == X86::ST0 || 1294 VA.getLocReg() == X86::ST1) && 1295 isScalarFPTypeInSSEReg(VA.getValVT())) { 1296 CopyVT = MVT::f80; 1297 } 1298 1299 SDValue Val; 1300 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { 1301 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. 1302 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1303 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1304 MVT::v2i64, InFlag).getValue(1); 1305 Val = Chain.getValue(0); 1306 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1307 Val, DAG.getConstant(0, MVT::i64)); 1308 } else { 1309 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1310 MVT::i64, InFlag).getValue(1); 1311 Val = Chain.getValue(0); 1312 } 1313 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); 1314 } else { 1315 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1316 CopyVT, InFlag).getValue(1); 1317 Val = Chain.getValue(0); 1318 } 1319 InFlag = Chain.getValue(2); 1320 1321 if (CopyVT != VA.getValVT()) { 1322 // Round the F80 the right size, which also moves to the appropriate xmm 1323 // register. 1324 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1325 // This truncation won't change the value. 1326 DAG.getIntPtrConstant(1)); 1327 } 1328 1329 InVals.push_back(Val); 1330 } 1331 1332 return Chain; 1333} 1334 1335 1336//===----------------------------------------------------------------------===// 1337// C & StdCall & Fast Calling Convention implementation 1338//===----------------------------------------------------------------------===// 1339// StdCall calling convention seems to be standard for many Windows' API 1340// routines and around. It differs from C calling convention just a little: 1341// callee should clean up the stack, not caller. Symbols should be also 1342// decorated in some fancy way :) It doesn't support any vector arguments. 1343// For info on fast calling convention see Fast Calling Convention (tail call) 1344// implementation LowerX86_32FastCCCallTo. 1345 1346/// CallIsStructReturn - Determines whether a call uses struct return 1347/// semantics. 1348static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1349 if (Outs.empty()) 1350 return false; 1351 1352 return Outs[0].Flags.isSRet(); 1353} 1354 1355/// ArgsAreStructReturn - Determines whether a function uses struct 1356/// return semantics. 1357static bool 1358ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1359 if (Ins.empty()) 1360 return false; 1361 1362 return Ins[0].Flags.isSRet(); 1363} 1364 1365/// IsCalleePop - Determines whether the callee is required to pop its 1366/// own arguments. Callee pop is necessary to support tail calls. 1367bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ 1368 if (IsVarArg) 1369 return false; 1370 1371 switch (CallingConv) { 1372 default: 1373 return false; 1374 case CallingConv::X86_StdCall: 1375 return !Subtarget->is64Bit(); 1376 case CallingConv::X86_FastCall: 1377 return !Subtarget->is64Bit(); 1378 case CallingConv::Fast: 1379 return GuaranteedTailCallOpt; 1380 } 1381} 1382 1383/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1384/// given CallingConvention value. 1385CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const { 1386 if (Subtarget->is64Bit()) { 1387 if (Subtarget->isTargetWin64()) 1388 return CC_X86_Win64_C; 1389 else 1390 return CC_X86_64_C; 1391 } 1392 1393 if (CC == CallingConv::X86_FastCall) 1394 return CC_X86_32_FastCall; 1395 else if (CC == CallingConv::Fast) 1396 return CC_X86_32_FastCC; 1397 else 1398 return CC_X86_32_C; 1399} 1400 1401/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1402/// by "Src" to address "Dst" with size and alignment information specified by 1403/// the specific parameter attribute. The copy will be passed as a byval 1404/// function parameter. 1405static SDValue 1406CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1407 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1408 DebugLoc dl) { 1409 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1410 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1411 /*AlwaysInline=*/true, NULL, 0, NULL, 0); 1412} 1413 1414/// FuncIsMadeTailCallSafe - Return true if the function is being made into 1415/// a tailcall target by changing its ABI. 1416static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1417 return GuaranteedTailCallOpt && CC == CallingConv::Fast; 1418} 1419 1420SDValue 1421X86TargetLowering::LowerMemArgument(SDValue Chain, 1422 CallingConv::ID CallConv, 1423 const SmallVectorImpl<ISD::InputArg> &Ins, 1424 DebugLoc dl, SelectionDAG &DAG, 1425 const CCValAssign &VA, 1426 MachineFrameInfo *MFI, 1427 unsigned i) { 1428 // Create the nodes corresponding to a load from this parameter slot. 1429 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1430 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1431 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1432 EVT ValVT; 1433 1434 // If value is passed by pointer we have address passed instead of the value 1435 // itself. 1436 if (VA.getLocInfo() == CCValAssign::Indirect) 1437 ValVT = VA.getLocVT(); 1438 else 1439 ValVT = VA.getValVT(); 1440 1441 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1442 // changed with more analysis. 1443 // In case of tail call optimization mark all arguments mutable. Since they 1444 // could be overwritten by lowering of arguments in case of a tail call. 1445 if (Flags.isByVal()) { 1446 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 1447 VA.getLocMemOffset(), isImmutable, false); 1448 return DAG.getFrameIndex(FI, getPointerTy()); 1449 } else { 1450 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1451 VA.getLocMemOffset(), isImmutable, false); 1452 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1453 return DAG.getLoad(ValVT, dl, Chain, FIN, 1454 PseudoSourceValue::getFixedStack(FI), 0, 1455 false, false, 0); 1456 } 1457} 1458 1459SDValue 1460X86TargetLowering::LowerFormalArguments(SDValue Chain, 1461 CallingConv::ID CallConv, 1462 bool isVarArg, 1463 const SmallVectorImpl<ISD::InputArg> &Ins, 1464 DebugLoc dl, 1465 SelectionDAG &DAG, 1466 SmallVectorImpl<SDValue> &InVals) { 1467 1468 MachineFunction &MF = DAG.getMachineFunction(); 1469 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1470 1471 const Function* Fn = MF.getFunction(); 1472 if (Fn->hasExternalLinkage() && 1473 Subtarget->isTargetCygMing() && 1474 Fn->getName() == "main") 1475 FuncInfo->setForceFramePointer(true); 1476 1477 MachineFrameInfo *MFI = MF.getFrameInfo(); 1478 bool Is64Bit = Subtarget->is64Bit(); 1479 bool IsWin64 = Subtarget->isTargetWin64(); 1480 1481 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1482 "Var args not supported with calling convention fastcc"); 1483 1484 // Assign locations to all of the incoming arguments. 1485 SmallVector<CCValAssign, 16> ArgLocs; 1486 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1487 ArgLocs, *DAG.getContext()); 1488 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); 1489 1490 unsigned LastVal = ~0U; 1491 SDValue ArgValue; 1492 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1493 CCValAssign &VA = ArgLocs[i]; 1494 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1495 // places. 1496 assert(VA.getValNo() != LastVal && 1497 "Don't support value assigned to multiple locs yet"); 1498 LastVal = VA.getValNo(); 1499 1500 if (VA.isRegLoc()) { 1501 EVT RegVT = VA.getLocVT(); 1502 TargetRegisterClass *RC = NULL; 1503 if (RegVT == MVT::i32) 1504 RC = X86::GR32RegisterClass; 1505 else if (Is64Bit && RegVT == MVT::i64) 1506 RC = X86::GR64RegisterClass; 1507 else if (RegVT == MVT::f32) 1508 RC = X86::FR32RegisterClass; 1509 else if (RegVT == MVT::f64) 1510 RC = X86::FR64RegisterClass; 1511 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1512 RC = X86::VR128RegisterClass; 1513 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64) 1514 RC = X86::VR64RegisterClass; 1515 else 1516 llvm_unreachable("Unknown argument type!"); 1517 1518 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1519 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1520 1521 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1522 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1523 // right size. 1524 if (VA.getLocInfo() == CCValAssign::SExt) 1525 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1526 DAG.getValueType(VA.getValVT())); 1527 else if (VA.getLocInfo() == CCValAssign::ZExt) 1528 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1529 DAG.getValueType(VA.getValVT())); 1530 else if (VA.getLocInfo() == CCValAssign::BCvt) 1531 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1532 1533 if (VA.isExtInLoc()) { 1534 // Handle MMX values passed in XMM regs. 1535 if (RegVT.isVector()) { 1536 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, 1537 ArgValue, DAG.getConstant(0, MVT::i64)); 1538 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1539 } else 1540 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1541 } 1542 } else { 1543 assert(VA.isMemLoc()); 1544 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1545 } 1546 1547 // If value is passed via pointer - do a load. 1548 if (VA.getLocInfo() == CCValAssign::Indirect) 1549 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0, 1550 false, false, 0); 1551 1552 InVals.push_back(ArgValue); 1553 } 1554 1555 // The x86-64 ABI for returning structs by value requires that we copy 1556 // the sret argument into %rax for the return. Save the argument into 1557 // a virtual register so that we can access it from the return points. 1558 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1559 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1560 unsigned Reg = FuncInfo->getSRetReturnReg(); 1561 if (!Reg) { 1562 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1563 FuncInfo->setSRetReturnReg(Reg); 1564 } 1565 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1566 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1567 } 1568 1569 unsigned StackSize = CCInfo.getNextStackOffset(); 1570 // Align stack specially for tail calls. 1571 if (FuncIsMadeTailCallSafe(CallConv)) 1572 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1573 1574 // If the function takes variable number of arguments, make a frame index for 1575 // the start of the first vararg value... for expansion of llvm.va_start. 1576 if (isVarArg) { 1577 if (Is64Bit || CallConv != CallingConv::X86_FastCall) { 1578 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false); 1579 } 1580 if (Is64Bit) { 1581 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1582 1583 // FIXME: We should really autogenerate these arrays 1584 static const unsigned GPR64ArgRegsWin64[] = { 1585 X86::RCX, X86::RDX, X86::R8, X86::R9 1586 }; 1587 static const unsigned XMMArgRegsWin64[] = { 1588 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1589 }; 1590 static const unsigned GPR64ArgRegs64Bit[] = { 1591 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1592 }; 1593 static const unsigned XMMArgRegs64Bit[] = { 1594 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1595 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1596 }; 1597 const unsigned *GPR64ArgRegs, *XMMArgRegs; 1598 1599 if (IsWin64) { 1600 TotalNumIntRegs = 4; TotalNumXMMRegs = 4; 1601 GPR64ArgRegs = GPR64ArgRegsWin64; 1602 XMMArgRegs = XMMArgRegsWin64; 1603 } else { 1604 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1605 GPR64ArgRegs = GPR64ArgRegs64Bit; 1606 XMMArgRegs = XMMArgRegs64Bit; 1607 } 1608 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1609 TotalNumIntRegs); 1610 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 1611 TotalNumXMMRegs); 1612 1613 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1614 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) && 1615 "SSE register cannot be used when SSE is disabled!"); 1616 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1617 "SSE register cannot be used when SSE is disabled!"); 1618 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1()) 1619 // Kernel mode asks for SSE to be disabled, so don't push them 1620 // on the stack. 1621 TotalNumXMMRegs = 0; 1622 1623 // For X86-64, if there are vararg parameters that are passed via 1624 // registers, then we must store them to their spots on the stack so they 1625 // may be loaded by deferencing the result of va_next. 1626 VarArgsGPOffset = NumIntRegs * 8; 1627 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16; 1628 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 + 1629 TotalNumXMMRegs * 16, 16, 1630 false); 1631 1632 // Store the integer parameter registers. 1633 SmallVector<SDValue, 8> MemOps; 1634 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 1635 unsigned Offset = VarArgsGPOffset; 1636 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1637 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1638 DAG.getIntPtrConstant(Offset)); 1639 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1640 X86::GR64RegisterClass); 1641 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1642 SDValue Store = 1643 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1644 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 1645 Offset, false, false, 0); 1646 MemOps.push_back(Store); 1647 Offset += 8; 1648 } 1649 1650 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1651 // Now store the XMM (fp + vector) parameter registers. 1652 SmallVector<SDValue, 11> SaveXMMOps; 1653 SaveXMMOps.push_back(Chain); 1654 1655 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1656 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1657 SaveXMMOps.push_back(ALVal); 1658 1659 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex)); 1660 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset)); 1661 1662 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1663 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], 1664 X86::VR128RegisterClass); 1665 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1666 SaveXMMOps.push_back(Val); 1667 } 1668 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1669 MVT::Other, 1670 &SaveXMMOps[0], SaveXMMOps.size())); 1671 } 1672 1673 if (!MemOps.empty()) 1674 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1675 &MemOps[0], MemOps.size()); 1676 } 1677 } 1678 1679 // Some CCs need callee pop. 1680 if (IsCalleePop(isVarArg, CallConv)) { 1681 BytesToPopOnReturn = StackSize; // Callee pops everything. 1682 } else { 1683 BytesToPopOnReturn = 0; // Callee pops nothing. 1684 // If this is an sret function, the return should pop the hidden pointer. 1685 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins)) 1686 BytesToPopOnReturn = 4; 1687 } 1688 1689 if (!Is64Bit) { 1690 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only. 1691 if (CallConv == CallingConv::X86_FastCall) 1692 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs. 1693 } 1694 1695 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); 1696 1697 return Chain; 1698} 1699 1700SDValue 1701X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1702 SDValue StackPtr, SDValue Arg, 1703 DebugLoc dl, SelectionDAG &DAG, 1704 const CCValAssign &VA, 1705 ISD::ArgFlagsTy Flags) { 1706 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); 1707 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); 1708 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1709 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1710 if (Flags.isByVal()) { 1711 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1712 } 1713 return DAG.getStore(Chain, dl, Arg, PtrOff, 1714 PseudoSourceValue::getStack(), LocMemOffset, 1715 false, false, 0); 1716} 1717 1718/// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1719/// optimization is performed and it is required. 1720SDValue 1721X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 1722 SDValue &OutRetAddr, SDValue Chain, 1723 bool IsTailCall, bool Is64Bit, 1724 int FPDiff, DebugLoc dl) { 1725 // Adjust the Return address stack slot. 1726 EVT VT = getPointerTy(); 1727 OutRetAddr = getReturnAddressFrameIndex(DAG); 1728 1729 // Load the "old" Return address. 1730 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0); 1731 return SDValue(OutRetAddr.getNode(), 1); 1732} 1733 1734/// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call 1735/// optimization is performed and it is required (FPDiff!=0). 1736static SDValue 1737EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 1738 SDValue Chain, SDValue RetAddrFrIdx, 1739 bool Is64Bit, int FPDiff, DebugLoc dl) { 1740 // Store the return address to the appropriate stack slot. 1741 if (!FPDiff) return Chain; 1742 // Calculate the new stack slot for the return address. 1743 int SlotSize = Is64Bit ? 8 : 4; 1744 int NewReturnAddrFI = 1745 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, true,false); 1746 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 1747 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 1748 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 1749 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0, 1750 false, false, 0); 1751 return Chain; 1752} 1753 1754SDValue 1755X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1756 CallingConv::ID CallConv, bool isVarArg, 1757 bool &isTailCall, 1758 const SmallVectorImpl<ISD::OutputArg> &Outs, 1759 const SmallVectorImpl<ISD::InputArg> &Ins, 1760 DebugLoc dl, SelectionDAG &DAG, 1761 SmallVectorImpl<SDValue> &InVals) { 1762 MachineFunction &MF = DAG.getMachineFunction(); 1763 bool Is64Bit = Subtarget->is64Bit(); 1764 bool IsStructRet = CallIsStructReturn(Outs); 1765 bool IsSibcall = false; 1766 1767 if (isTailCall) { 1768 // Check if it's really possible to do a tail call. 1769 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 1770 Outs, Ins, DAG); 1771 1772 // Sibcalls are automatically detected tailcalls which do not require 1773 // ABI changes. 1774 if (!GuaranteedTailCallOpt && isTailCall) 1775 IsSibcall = true; 1776 1777 if (isTailCall) 1778 ++NumTailCalls; 1779 } 1780 1781 assert(!(isVarArg && CallConv == CallingConv::Fast) && 1782 "Var args not supported with calling convention fastcc"); 1783 1784 // Analyze operands of the call, assigning locations to each operand. 1785 SmallVector<CCValAssign, 16> ArgLocs; 1786 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 1787 ArgLocs, *DAG.getContext()); 1788 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1789 1790 // Get a count of how many bytes are to be pushed on the stack. 1791 unsigned NumBytes = CCInfo.getNextStackOffset(); 1792 if (IsSibcall) 1793 // This is a sibcall. The memory operands are available in caller's 1794 // own caller's stack. 1795 NumBytes = 0; 1796 else if (GuaranteedTailCallOpt && CallConv == CallingConv::Fast) 1797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 1798 1799 int FPDiff = 0; 1800 if (isTailCall && !IsSibcall) { 1801 // Lower arguments at fp - stackoffset + fpdiff. 1802 unsigned NumBytesCallerPushed = 1803 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 1804 FPDiff = NumBytesCallerPushed - NumBytes; 1805 1806 // Set the delta of movement of the returnaddr stackslot. 1807 // But only set if delta is greater than previous delta. 1808 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 1809 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 1810 } 1811 1812 if (!IsSibcall) 1813 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1814 1815 SDValue RetAddrFrIdx; 1816 // Load return adress for tail calls. 1817 if (isTailCall && FPDiff) 1818 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 1819 Is64Bit, FPDiff, dl); 1820 1821 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1822 SmallVector<SDValue, 8> MemOpChains; 1823 SDValue StackPtr; 1824 1825 // Walk the register/memloc assignments, inserting copies/loads. In the case 1826 // of tail call optimization arguments are handle later. 1827 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1828 CCValAssign &VA = ArgLocs[i]; 1829 EVT RegVT = VA.getLocVT(); 1830 SDValue Arg = Outs[i].Val; 1831 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1832 bool isByVal = Flags.isByVal(); 1833 1834 // Promote the value if needed. 1835 switch (VA.getLocInfo()) { 1836 default: llvm_unreachable("Unknown loc info!"); 1837 case CCValAssign::Full: break; 1838 case CCValAssign::SExt: 1839 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 1840 break; 1841 case CCValAssign::ZExt: 1842 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 1843 break; 1844 case CCValAssign::AExt: 1845 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 1846 // Special case: passing MMX values in XMM registers. 1847 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); 1848 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 1849 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 1850 } else 1851 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 1852 break; 1853 case CCValAssign::BCvt: 1854 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg); 1855 break; 1856 case CCValAssign::Indirect: { 1857 // Store the argument. 1858 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 1859 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 1860 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 1861 PseudoSourceValue::getFixedStack(FI), 0, 1862 false, false, 0); 1863 Arg = SpillSlot; 1864 break; 1865 } 1866 } 1867 1868 if (VA.isRegLoc()) { 1869 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1870 } else if (!IsSibcall && (!isTailCall || isByVal)) { 1871 assert(VA.isMemLoc()); 1872 if (StackPtr.getNode() == 0) 1873 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 1874 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1875 dl, DAG, VA, Flags)); 1876 } 1877 } 1878 1879 if (!MemOpChains.empty()) 1880 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1881 &MemOpChains[0], MemOpChains.size()); 1882 1883 // Build a sequence of copy-to-reg nodes chained together with token chain 1884 // and flag operands which copy the outgoing args into registers. 1885 SDValue InFlag; 1886 // Tail call byval lowering might overwrite argument registers so in case of 1887 // tail call optimization the copies to registers are lowered later. 1888 if (!isTailCall) 1889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1890 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1891 RegsToPass[i].second, InFlag); 1892 InFlag = Chain.getValue(1); 1893 } 1894 1895 if (Subtarget->isPICStyleGOT()) { 1896 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1897 // GOT pointer. 1898 if (!isTailCall) { 1899 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 1900 DAG.getNode(X86ISD::GlobalBaseReg, 1901 DebugLoc::getUnknownLoc(), 1902 getPointerTy()), 1903 InFlag); 1904 InFlag = Chain.getValue(1); 1905 } else { 1906 // If we are tail calling and generating PIC/GOT style code load the 1907 // address of the callee into ECX. The value in ecx is used as target of 1908 // the tail jump. This is done to circumvent the ebx/callee-saved problem 1909 // for tail calls on PIC/GOT architectures. Normally we would just put the 1910 // address of GOT into ebx and then call target@PLT. But for tail calls 1911 // ebx would be restored (since ebx is callee saved) before jumping to the 1912 // target@PLT. 1913 1914 // Note: The actual moving to ECX is done further down. 1915 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 1916 if (G && !G->getGlobal()->hasHiddenVisibility() && 1917 !G->getGlobal()->hasProtectedVisibility()) 1918 Callee = LowerGlobalAddress(Callee, DAG); 1919 else if (isa<ExternalSymbolSDNode>(Callee)) 1920 Callee = LowerExternalSymbol(Callee, DAG); 1921 } 1922 } 1923 1924 if (Is64Bit && isVarArg) { 1925 // From AMD64 ABI document: 1926 // For calls that may call functions that use varargs or stdargs 1927 // (prototype-less calls or calls to functions containing ellipsis (...) in 1928 // the declaration) %al is used as hidden argument to specify the number 1929 // of SSE registers used. The contents of %al do not need to match exactly 1930 // the number of registers, but must be an ubound on the number of SSE 1931 // registers used and is in the range 0 - 8 inclusive. 1932 1933 // FIXME: Verify this on Win64 1934 // Count the number of XMM registers allocated. 1935 static const unsigned XMMArgRegs[] = { 1936 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1937 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1938 }; 1939 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1940 assert((Subtarget->hasSSE1() || !NumXMMRegs) 1941 && "SSE registers cannot be used when SSE is disabled"); 1942 1943 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 1944 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 1945 InFlag = Chain.getValue(1); 1946 } 1947 1948 1949 // For tail calls lower the arguments to the 'real' stack slot. 1950 if (isTailCall) { 1951 // Force all the incoming stack arguments to be loaded from the stack 1952 // before any new outgoing arguments are stored to the stack, because the 1953 // outgoing stack slots may alias the incoming argument stack slots, and 1954 // the alias isn't otherwise explicit. This is slightly more conservative 1955 // than necessary, because it means that each store effectively depends 1956 // on every argument instead of just those arguments it would clobber. 1957 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 1958 1959 SmallVector<SDValue, 8> MemOpChains2; 1960 SDValue FIN; 1961 int FI = 0; 1962 // Do not flag preceeding copytoreg stuff together with the following stuff. 1963 InFlag = SDValue(); 1964 if (GuaranteedTailCallOpt) { 1965 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1966 CCValAssign &VA = ArgLocs[i]; 1967 if (VA.isRegLoc()) 1968 continue; 1969 assert(VA.isMemLoc()); 1970 SDValue Arg = Outs[i].Val; 1971 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1972 // Create frame index. 1973 int32_t Offset = VA.getLocMemOffset()+FPDiff; 1974 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 1975 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false); 1976 FIN = DAG.getFrameIndex(FI, getPointerTy()); 1977 1978 if (Flags.isByVal()) { 1979 // Copy relative to framepointer. 1980 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 1981 if (StackPtr.getNode() == 0) 1982 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 1983 getPointerTy()); 1984 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 1985 1986 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 1987 ArgChain, 1988 Flags, DAG, dl)); 1989 } else { 1990 // Store relative to framepointer. 1991 MemOpChains2.push_back( 1992 DAG.getStore(ArgChain, dl, Arg, FIN, 1993 PseudoSourceValue::getFixedStack(FI), 0, 1994 false, false, 0)); 1995 } 1996 } 1997 } 1998 1999 if (!MemOpChains2.empty()) 2000 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2001 &MemOpChains2[0], MemOpChains2.size()); 2002 2003 // Copy arguments to their registers. 2004 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2005 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2006 RegsToPass[i].second, InFlag); 2007 InFlag = Chain.getValue(1); 2008 } 2009 InFlag =SDValue(); 2010 2011 // Store the return address to the appropriate stack slot. 2012 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2013 FPDiff, dl); 2014 } 2015 2016 bool WasGlobalOrExternal = false; 2017 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2018 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2019 // In the 64-bit large code model, we have to make all calls 2020 // through a register, since the call instruction's 32-bit 2021 // pc-relative offset may not be large enough to hold the whole 2022 // address. 2023 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2024 WasGlobalOrExternal = true; 2025 // If the callee is a GlobalAddress node (quite common, every direct call 2026 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2027 // it. 2028 2029 // We should use extra load for direct calls to dllimported functions in 2030 // non-JIT mode. 2031 GlobalValue *GV = G->getGlobal(); 2032 if (!GV->hasDLLImportLinkage()) { 2033 unsigned char OpFlags = 0; 2034 2035 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2036 // external symbols most go through the PLT in PIC mode. If the symbol 2037 // has hidden or protected visibility, or if it is static or local, then 2038 // we don't need to use the PLT - we can directly call it. 2039 if (Subtarget->isTargetELF() && 2040 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2041 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2042 OpFlags = X86II::MO_PLT; 2043 } else if (Subtarget->isPICStyleStubAny() && 2044 (GV->isDeclaration() || GV->isWeakForLinker()) && 2045 Subtarget->getDarwinVers() < 9) { 2046 // PC-relative references to external symbols should go through $stub, 2047 // unless we're building with the leopard linker or later, which 2048 // automatically synthesizes these stubs. 2049 OpFlags = X86II::MO_DARWIN_STUB; 2050 } 2051 2052 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(), 2053 G->getOffset(), OpFlags); 2054 } 2055 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2056 WasGlobalOrExternal = true; 2057 unsigned char OpFlags = 0; 2058 2059 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external 2060 // symbols should go through the PLT. 2061 if (Subtarget->isTargetELF() && 2062 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2063 OpFlags = X86II::MO_PLT; 2064 } else if (Subtarget->isPICStyleStubAny() && 2065 Subtarget->getDarwinVers() < 9) { 2066 // PC-relative references to external symbols should go through $stub, 2067 // unless we're building with the leopard linker or later, which 2068 // automatically synthesizes these stubs. 2069 OpFlags = X86II::MO_DARWIN_STUB; 2070 } 2071 2072 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2073 OpFlags); 2074 } 2075 2076 if (isTailCall && !WasGlobalOrExternal) { 2077 // Force the address into a (call preserved) caller-saved register since 2078 // tailcall must happen after callee-saved registers are poped. 2079 // FIXME: Give it a special register class that contains caller-saved 2080 // register instead? 2081 unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX; 2082 Chain = DAG.getCopyToReg(Chain, dl, 2083 DAG.getRegister(TCReg, getPointerTy()), 2084 Callee,InFlag); 2085 Callee = DAG.getRegister(TCReg, getPointerTy()); 2086 } 2087 2088 // Returns a chain & a flag for retval copy to use. 2089 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 2090 SmallVector<SDValue, 8> Ops; 2091 2092 if (!IsSibcall && isTailCall) { 2093 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2094 DAG.getIntPtrConstant(0, true), InFlag); 2095 InFlag = Chain.getValue(1); 2096 } 2097 2098 Ops.push_back(Chain); 2099 Ops.push_back(Callee); 2100 2101 if (isTailCall) 2102 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2103 2104 // Add argument registers to the end of the list so that they are known live 2105 // into the call. 2106 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2107 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2108 RegsToPass[i].second.getValueType())); 2109 2110 // Add an implicit use GOT pointer in EBX. 2111 if (!isTailCall && Subtarget->isPICStyleGOT()) 2112 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2113 2114 // Add an implicit use of AL for x86 vararg functions. 2115 if (Is64Bit && isVarArg) 2116 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2117 2118 if (InFlag.getNode()) 2119 Ops.push_back(InFlag); 2120 2121 if (isTailCall) { 2122 // If this is the first return lowered for this function, add the regs 2123 // to the liveout set for the function. 2124 if (MF.getRegInfo().liveout_empty()) { 2125 SmallVector<CCValAssign, 16> RVLocs; 2126 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2127 *DAG.getContext()); 2128 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2129 for (unsigned i = 0; i != RVLocs.size(); ++i) 2130 if (RVLocs[i].isRegLoc()) 2131 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2132 } 2133 2134 assert(((Callee.getOpcode() == ISD::Register && 2135 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX || 2136 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) || 2137 Callee.getOpcode() == ISD::TargetExternalSymbol || 2138 Callee.getOpcode() == ISD::TargetGlobalAddress) && 2139 "Expecting a global address, external symbol, or scratch register"); 2140 2141 return DAG.getNode(X86ISD::TC_RETURN, dl, 2142 NodeTys, &Ops[0], Ops.size()); 2143 } 2144 2145 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2146 InFlag = Chain.getValue(1); 2147 2148 // Create the CALLSEQ_END node. 2149 unsigned NumBytesForCalleeToPush; 2150 if (IsCalleePop(isVarArg, CallConv)) 2151 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2152 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet) 2153 // If this is a call to a struct-return function, the callee 2154 // pops the hidden struct pointer, so we have to push it back. 2155 // This is common for Darwin/X86, Linux & Mingw32 targets. 2156 NumBytesForCalleeToPush = 4; 2157 else 2158 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2159 2160 // Returns a flag for retval copy to use. 2161 if (!IsSibcall) { 2162 Chain = DAG.getCALLSEQ_END(Chain, 2163 DAG.getIntPtrConstant(NumBytes, true), 2164 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2165 true), 2166 InFlag); 2167 InFlag = Chain.getValue(1); 2168 } 2169 2170 // Handle result values, copying them out of physregs into vregs that we 2171 // return. 2172 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2173 Ins, dl, DAG, InVals); 2174} 2175 2176 2177//===----------------------------------------------------------------------===// 2178// Fast Calling Convention (tail call) implementation 2179//===----------------------------------------------------------------------===// 2180 2181// Like std call, callee cleans arguments, convention except that ECX is 2182// reserved for storing the tail called function address. Only 2 registers are 2183// free for argument passing (inreg). Tail call optimization is performed 2184// provided: 2185// * tailcallopt is enabled 2186// * caller/callee are fastcc 2187// On X86_64 architecture with GOT-style position independent code only local 2188// (within module) calls are supported at the moment. 2189// To keep the stack aligned according to platform abi the function 2190// GetAlignedArgumentStackSize ensures that argument delta is always multiples 2191// of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2192// If a tail called function callee has more arguments than the caller the 2193// caller needs to make sure that there is room to move the RETADDR to. This is 2194// achieved by reserving an area the size of the argument delta right after the 2195// original REtADDR, but before the saved framepointer or the spilled registers 2196// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2197// stack layout: 2198// arg1 2199// arg2 2200// RETADDR 2201// [ new RETADDR 2202// move area ] 2203// (possible EBP) 2204// ESI 2205// EDI 2206// local1 .. 2207 2208/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2209/// for a 16 byte align requirement. 2210unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2211 SelectionDAG& DAG) { 2212 MachineFunction &MF = DAG.getMachineFunction(); 2213 const TargetMachine &TM = MF.getTarget(); 2214 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 2215 unsigned StackAlignment = TFI.getStackAlignment(); 2216 uint64_t AlignMask = StackAlignment - 1; 2217 int64_t Offset = StackSize; 2218 uint64_t SlotSize = TD->getPointerSize(); 2219 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2220 // Number smaller than 12 so just add the difference. 2221 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2222 } else { 2223 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2224 Offset = ((~AlignMask) & Offset) + StackAlignment + 2225 (StackAlignment-SlotSize); 2226 } 2227 return Offset; 2228} 2229 2230/// MatchingStackOffset - Return true if the given stack call argument is 2231/// already available in the same position (relatively) of the caller's 2232/// incoming argument stack. 2233static 2234bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2235 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2236 const X86InstrInfo *TII) { 2237 int FI; 2238 if (Arg.getOpcode() == ISD::CopyFromReg) { 2239 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2240 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR)) 2241 return false; 2242 MachineInstr *Def = MRI->getVRegDef(VR); 2243 if (!Def) 2244 return false; 2245 if (!Flags.isByVal()) { 2246 if (!TII->isLoadFromStackSlot(Def, FI)) 2247 return false; 2248 } else { 2249 unsigned Opcode = Def->getOpcode(); 2250 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2251 Def->getOperand(1).isFI()) { 2252 FI = Def->getOperand(1).getIndex(); 2253 if (MFI->getObjectSize(FI) != Flags.getByValSize()) 2254 return false; 2255 } else 2256 return false; 2257 } 2258 } else { 2259 LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg); 2260 if (!Ld) 2261 return false; 2262 SDValue Ptr = Ld->getBasePtr(); 2263 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2264 if (!FINode) 2265 return false; 2266 FI = FINode->getIndex(); 2267 } 2268 2269 if (!MFI->isFixedObjectIndex(FI)) 2270 return false; 2271 return Offset == MFI->getObjectOffset(FI); 2272} 2273 2274/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2275/// for tail call optimization. Targets which want to do tail call 2276/// optimization should implement this function. 2277bool 2278X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2279 CallingConv::ID CalleeCC, 2280 bool isVarArg, 2281 const SmallVectorImpl<ISD::OutputArg> &Outs, 2282 const SmallVectorImpl<ISD::InputArg> &Ins, 2283 SelectionDAG& DAG) const { 2284 if (CalleeCC != CallingConv::Fast && 2285 CalleeCC != CallingConv::C) 2286 return false; 2287 2288 // If -tailcallopt is specified, make fastcc functions tail-callable. 2289 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2290 if (GuaranteedTailCallOpt) { 2291 if (CalleeCC == CallingConv::Fast && 2292 CallerF->getCallingConv() == CalleeCC) 2293 return true; 2294 return false; 2295 } 2296 2297 // Look for obvious safe cases to perform tail call optimization that does not 2298 // requite ABI changes. This is what gcc calls sibcall. 2299 2300 // Do not tail call optimize vararg calls for now. 2301 if (isVarArg) 2302 return false; 2303 2304 // If the callee takes no arguments then go on to check the results of the 2305 // call. 2306 if (!Outs.empty()) { 2307 // Check if stack adjustment is needed. For now, do not do this if any 2308 // argument is passed on the stack. 2309 SmallVector<CCValAssign, 16> ArgLocs; 2310 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), 2311 ArgLocs, *DAG.getContext()); 2312 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC)); 2313 if (CCInfo.getNextStackOffset()) { 2314 MachineFunction &MF = DAG.getMachineFunction(); 2315 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2316 return false; 2317 if (Subtarget->isTargetWin64()) 2318 // Win64 ABI has additional complications. 2319 return false; 2320 2321 // Check if the arguments are already laid out in the right way as 2322 // the caller's fixed stack objects. 2323 MachineFrameInfo *MFI = MF.getFrameInfo(); 2324 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2325 const X86InstrInfo *TII = 2326 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2327 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2328 CCValAssign &VA = ArgLocs[i]; 2329 EVT RegVT = VA.getLocVT(); 2330 SDValue Arg = Outs[i].Val; 2331 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2332 if (VA.getLocInfo() == CCValAssign::Indirect) 2333 return false; 2334 if (!VA.isRegLoc()) { 2335 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2336 MFI, MRI, TII)) 2337 return false; 2338 } 2339 } 2340 } 2341 } 2342 2343 return true; 2344} 2345 2346FastISel * 2347X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, 2348 DwarfWriter *dw, 2349 DenseMap<const Value *, unsigned> &vm, 2350 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm, 2351 DenseMap<const AllocaInst *, int> &am 2352#ifndef NDEBUG 2353 , SmallSet<Instruction*, 8> &cil 2354#endif 2355 ) { 2356 return X86::createFastISel(mf, mmo, dw, vm, bm, am 2357#ifndef NDEBUG 2358 , cil 2359#endif 2360 ); 2361} 2362 2363 2364//===----------------------------------------------------------------------===// 2365// Other Lowering Hooks 2366//===----------------------------------------------------------------------===// 2367 2368 2369SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 2370 MachineFunction &MF = DAG.getMachineFunction(); 2371 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2372 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2373 2374 if (ReturnAddrIndex == 0) { 2375 // Set up a frame object for the return address. 2376 uint64_t SlotSize = TD->getPointerSize(); 2377 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2378 true, false); 2379 FuncInfo->setRAIndex(ReturnAddrIndex); 2380 } 2381 2382 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2383} 2384 2385 2386bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2387 bool hasSymbolicDisplacement) { 2388 // Offset should fit into 32 bit immediate field. 2389 if (!isInt32(Offset)) 2390 return false; 2391 2392 // If we don't have a symbolic displacement - we don't have any extra 2393 // restrictions. 2394 if (!hasSymbolicDisplacement) 2395 return true; 2396 2397 // FIXME: Some tweaks might be needed for medium code model. 2398 if (M != CodeModel::Small && M != CodeModel::Kernel) 2399 return false; 2400 2401 // For small code model we assume that latest object is 16MB before end of 31 2402 // bits boundary. We may also accept pretty large negative constants knowing 2403 // that all objects are in the positive half of address space. 2404 if (M == CodeModel::Small && Offset < 16*1024*1024) 2405 return true; 2406 2407 // For kernel code model we know that all object resist in the negative half 2408 // of 32bits address space. We may not accept negative offsets, since they may 2409 // be just off and we may accept pretty large positive ones. 2410 if (M == CodeModel::Kernel && Offset > 0) 2411 return true; 2412 2413 return false; 2414} 2415 2416/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2417/// specific condition code, returning the condition code and the LHS/RHS of the 2418/// comparison to make. 2419static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2420 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2421 if (!isFP) { 2422 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2423 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2424 // X > -1 -> X == 0, jump !sign. 2425 RHS = DAG.getConstant(0, RHS.getValueType()); 2426 return X86::COND_NS; 2427 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2428 // X < 0 -> X == 0, jump on sign. 2429 return X86::COND_S; 2430 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2431 // X < 1 -> X <= 0 2432 RHS = DAG.getConstant(0, RHS.getValueType()); 2433 return X86::COND_LE; 2434 } 2435 } 2436 2437 switch (SetCCOpcode) { 2438 default: llvm_unreachable("Invalid integer condition!"); 2439 case ISD::SETEQ: return X86::COND_E; 2440 case ISD::SETGT: return X86::COND_G; 2441 case ISD::SETGE: return X86::COND_GE; 2442 case ISD::SETLT: return X86::COND_L; 2443 case ISD::SETLE: return X86::COND_LE; 2444 case ISD::SETNE: return X86::COND_NE; 2445 case ISD::SETULT: return X86::COND_B; 2446 case ISD::SETUGT: return X86::COND_A; 2447 case ISD::SETULE: return X86::COND_BE; 2448 case ISD::SETUGE: return X86::COND_AE; 2449 } 2450 } 2451 2452 // First determine if it is required or is profitable to flip the operands. 2453 2454 // If LHS is a foldable load, but RHS is not, flip the condition. 2455 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) && 2456 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) { 2457 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 2458 std::swap(LHS, RHS); 2459 } 2460 2461 switch (SetCCOpcode) { 2462 default: break; 2463 case ISD::SETOLT: 2464 case ISD::SETOLE: 2465 case ISD::SETUGT: 2466 case ISD::SETUGE: 2467 std::swap(LHS, RHS); 2468 break; 2469 } 2470 2471 // On a floating point condition, the flags are set as follows: 2472 // ZF PF CF op 2473 // 0 | 0 | 0 | X > Y 2474 // 0 | 0 | 1 | X < Y 2475 // 1 | 0 | 0 | X == Y 2476 // 1 | 1 | 1 | unordered 2477 switch (SetCCOpcode) { 2478 default: llvm_unreachable("Condcode should be pre-legalized away"); 2479 case ISD::SETUEQ: 2480 case ISD::SETEQ: return X86::COND_E; 2481 case ISD::SETOLT: // flipped 2482 case ISD::SETOGT: 2483 case ISD::SETGT: return X86::COND_A; 2484 case ISD::SETOLE: // flipped 2485 case ISD::SETOGE: 2486 case ISD::SETGE: return X86::COND_AE; 2487 case ISD::SETUGT: // flipped 2488 case ISD::SETULT: 2489 case ISD::SETLT: return X86::COND_B; 2490 case ISD::SETUGE: // flipped 2491 case ISD::SETULE: 2492 case ISD::SETLE: return X86::COND_BE; 2493 case ISD::SETONE: 2494 case ISD::SETNE: return X86::COND_NE; 2495 case ISD::SETUO: return X86::COND_P; 2496 case ISD::SETO: return X86::COND_NP; 2497 case ISD::SETOEQ: 2498 case ISD::SETUNE: return X86::COND_INVALID; 2499 } 2500} 2501 2502/// hasFPCMov - is there a floating point cmov for the specific X86 condition 2503/// code. Current x86 isa includes the following FP cmov instructions: 2504/// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 2505static bool hasFPCMov(unsigned X86CC) { 2506 switch (X86CC) { 2507 default: 2508 return false; 2509 case X86::COND_B: 2510 case X86::COND_BE: 2511 case X86::COND_E: 2512 case X86::COND_P: 2513 case X86::COND_A: 2514 case X86::COND_AE: 2515 case X86::COND_NE: 2516 case X86::COND_NP: 2517 return true; 2518 } 2519} 2520 2521/// isFPImmLegal - Returns true if the target can instruction select the 2522/// specified FP immediate natively. If false, the legalizer will 2523/// materialize the FP immediate as a load from a constant pool. 2524bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2525 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 2526 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 2527 return true; 2528 } 2529 return false; 2530} 2531 2532/// isUndefOrInRange - Return true if Val is undef or if its value falls within 2533/// the specified range (L, H]. 2534static bool isUndefOrInRange(int Val, int Low, int Hi) { 2535 return (Val < 0) || (Val >= Low && Val < Hi); 2536} 2537 2538/// isUndefOrEqual - Val is either less than zero (undef) or equal to the 2539/// specified value. 2540static bool isUndefOrEqual(int Val, int CmpVal) { 2541 if (Val < 0 || Val == CmpVal) 2542 return true; 2543 return false; 2544} 2545 2546/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 2547/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 2548/// the second operand. 2549static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2550 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) 2551 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 2552 if (VT == MVT::v2f64 || VT == MVT::v2i64) 2553 return (Mask[0] < 2 && Mask[1] < 2); 2554 return false; 2555} 2556 2557bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 2558 SmallVector<int, 8> M; 2559 N->getMask(M); 2560 return ::isPSHUFDMask(M, N->getValueType(0)); 2561} 2562 2563/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 2564/// is suitable for input to PSHUFHW. 2565static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2566 if (VT != MVT::v8i16) 2567 return false; 2568 2569 // Lower quadword copied in order or undef. 2570 for (int i = 0; i != 4; ++i) 2571 if (Mask[i] >= 0 && Mask[i] != i) 2572 return false; 2573 2574 // Upper quadword shuffled. 2575 for (int i = 4; i != 8; ++i) 2576 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 2577 return false; 2578 2579 return true; 2580} 2581 2582bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 2583 SmallVector<int, 8> M; 2584 N->getMask(M); 2585 return ::isPSHUFHWMask(M, N->getValueType(0)); 2586} 2587 2588/// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 2589/// is suitable for input to PSHUFLW. 2590static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2591 if (VT != MVT::v8i16) 2592 return false; 2593 2594 // Upper quadword copied in order. 2595 for (int i = 4; i != 8; ++i) 2596 if (Mask[i] >= 0 && Mask[i] != i) 2597 return false; 2598 2599 // Lower quadword shuffled. 2600 for (int i = 0; i != 4; ++i) 2601 if (Mask[i] >= 4) 2602 return false; 2603 2604 return true; 2605} 2606 2607bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 2608 SmallVector<int, 8> M; 2609 N->getMask(M); 2610 return ::isPSHUFLWMask(M, N->getValueType(0)); 2611} 2612 2613/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 2614/// is suitable for input to PALIGNR. 2615static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 2616 bool hasSSSE3) { 2617 int i, e = VT.getVectorNumElements(); 2618 2619 // Do not handle v2i64 / v2f64 shuffles with palignr. 2620 if (e < 4 || !hasSSSE3) 2621 return false; 2622 2623 for (i = 0; i != e; ++i) 2624 if (Mask[i] >= 0) 2625 break; 2626 2627 // All undef, not a palignr. 2628 if (i == e) 2629 return false; 2630 2631 // Determine if it's ok to perform a palignr with only the LHS, since we 2632 // don't have access to the actual shuffle elements to see if RHS is undef. 2633 bool Unary = Mask[i] < (int)e; 2634 bool NeedsUnary = false; 2635 2636 int s = Mask[i] - i; 2637 2638 // Check the rest of the elements to see if they are consecutive. 2639 for (++i; i != e; ++i) { 2640 int m = Mask[i]; 2641 if (m < 0) 2642 continue; 2643 2644 Unary = Unary && (m < (int)e); 2645 NeedsUnary = NeedsUnary || (m < s); 2646 2647 if (NeedsUnary && !Unary) 2648 return false; 2649 if (Unary && m != ((s+i) & (e-1))) 2650 return false; 2651 if (!Unary && m != (s+i)) 2652 return false; 2653 } 2654 return true; 2655} 2656 2657bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) { 2658 SmallVector<int, 8> M; 2659 N->getMask(M); 2660 return ::isPALIGNRMask(M, N->getValueType(0), true); 2661} 2662 2663/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 2664/// specifies a shuffle of elements that is suitable for input to SHUFP*. 2665static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2666 int NumElems = VT.getVectorNumElements(); 2667 if (NumElems != 2 && NumElems != 4) 2668 return false; 2669 2670 int Half = NumElems / 2; 2671 for (int i = 0; i < Half; ++i) 2672 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2673 return false; 2674 for (int i = Half; i < NumElems; ++i) 2675 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2676 return false; 2677 2678 return true; 2679} 2680 2681bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 2682 SmallVector<int, 8> M; 2683 N->getMask(M); 2684 return ::isSHUFPMask(M, N->getValueType(0)); 2685} 2686 2687/// isCommutedSHUFP - Returns true if the shuffle mask is exactly 2688/// the reverse of what x86 shuffles want. x86 shuffles requires the lower 2689/// half elements to come from vector 1 (which would equal the dest.) and 2690/// the upper half to come from vector 2. 2691static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2692 int NumElems = VT.getVectorNumElements(); 2693 2694 if (NumElems != 2 && NumElems != 4) 2695 return false; 2696 2697 int Half = NumElems / 2; 2698 for (int i = 0; i < Half; ++i) 2699 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 2700 return false; 2701 for (int i = Half; i < NumElems; ++i) 2702 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 2703 return false; 2704 return true; 2705} 2706 2707static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 2708 SmallVector<int, 8> M; 2709 N->getMask(M); 2710 return isCommutedSHUFPMask(M, N->getValueType(0)); 2711} 2712 2713/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 2714/// specifies a shuffle of elements that is suitable for input to MOVHLPS. 2715bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 2716 if (N->getValueType(0).getVectorNumElements() != 4) 2717 return false; 2718 2719 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 2720 return isUndefOrEqual(N->getMaskElt(0), 6) && 2721 isUndefOrEqual(N->getMaskElt(1), 7) && 2722 isUndefOrEqual(N->getMaskElt(2), 2) && 2723 isUndefOrEqual(N->getMaskElt(3), 3); 2724} 2725 2726/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 2727/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 2728/// <2, 3, 2, 3> 2729bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 2730 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2731 2732 if (NumElems != 4) 2733 return false; 2734 2735 return isUndefOrEqual(N->getMaskElt(0), 2) && 2736 isUndefOrEqual(N->getMaskElt(1), 3) && 2737 isUndefOrEqual(N->getMaskElt(2), 2) && 2738 isUndefOrEqual(N->getMaskElt(3), 3); 2739} 2740 2741/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 2742/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 2743bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 2744 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2745 2746 if (NumElems != 2 && NumElems != 4) 2747 return false; 2748 2749 for (unsigned i = 0; i < NumElems/2; ++i) 2750 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 2751 return false; 2752 2753 for (unsigned i = NumElems/2; i < NumElems; ++i) 2754 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2755 return false; 2756 2757 return true; 2758} 2759 2760/// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 2761/// specifies a shuffle of elements that is suitable for input to MOVLHPS. 2762bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 2763 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 2764 2765 if (NumElems != 2 && NumElems != 4) 2766 return false; 2767 2768 for (unsigned i = 0; i < NumElems/2; ++i) 2769 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2770 return false; 2771 2772 for (unsigned i = 0; i < NumElems/2; ++i) 2773 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 2774 return false; 2775 2776 return true; 2777} 2778 2779/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 2780/// specifies a shuffle of elements that is suitable for input to UNPCKL. 2781static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2782 bool V2IsSplat = false) { 2783 int NumElts = VT.getVectorNumElements(); 2784 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2785 return false; 2786 2787 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2788 int BitI = Mask[i]; 2789 int BitI1 = Mask[i+1]; 2790 if (!isUndefOrEqual(BitI, j)) 2791 return false; 2792 if (V2IsSplat) { 2793 if (!isUndefOrEqual(BitI1, NumElts)) 2794 return false; 2795 } else { 2796 if (!isUndefOrEqual(BitI1, j + NumElts)) 2797 return false; 2798 } 2799 } 2800 return true; 2801} 2802 2803bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2804 SmallVector<int, 8> M; 2805 N->getMask(M); 2806 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 2807} 2808 2809/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 2810/// specifies a shuffle of elements that is suitable for input to UNPCKH. 2811static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 2812 bool V2IsSplat = false) { 2813 int NumElts = VT.getVectorNumElements(); 2814 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) 2815 return false; 2816 2817 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) { 2818 int BitI = Mask[i]; 2819 int BitI1 = Mask[i+1]; 2820 if (!isUndefOrEqual(BitI, j + NumElts/2)) 2821 return false; 2822 if (V2IsSplat) { 2823 if (isUndefOrEqual(BitI1, NumElts)) 2824 return false; 2825 } else { 2826 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts)) 2827 return false; 2828 } 2829 } 2830 return true; 2831} 2832 2833bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 2834 SmallVector<int, 8> M; 2835 N->getMask(M); 2836 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 2837} 2838 2839/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 2840/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 2841/// <0, 0, 1, 1> 2842static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2843 int NumElems = VT.getVectorNumElements(); 2844 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2845 return false; 2846 2847 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) { 2848 int BitI = Mask[i]; 2849 int BitI1 = Mask[i+1]; 2850 if (!isUndefOrEqual(BitI, j)) 2851 return false; 2852 if (!isUndefOrEqual(BitI1, j)) 2853 return false; 2854 } 2855 return true; 2856} 2857 2858bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 2859 SmallVector<int, 8> M; 2860 N->getMask(M); 2861 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 2862} 2863 2864/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 2865/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 2866/// <2, 2, 3, 3> 2867static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 2868 int NumElems = VT.getVectorNumElements(); 2869 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 2870 return false; 2871 2872 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 2873 int BitI = Mask[i]; 2874 int BitI1 = Mask[i+1]; 2875 if (!isUndefOrEqual(BitI, j)) 2876 return false; 2877 if (!isUndefOrEqual(BitI1, j)) 2878 return false; 2879 } 2880 return true; 2881} 2882 2883bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 2884 SmallVector<int, 8> M; 2885 N->getMask(M); 2886 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 2887} 2888 2889/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 2890/// specifies a shuffle of elements that is suitable for input to MOVSS, 2891/// MOVSD, and MOVD, i.e. setting the lowest element. 2892static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 2893 if (VT.getVectorElementType().getSizeInBits() < 32) 2894 return false; 2895 2896 int NumElts = VT.getVectorNumElements(); 2897 2898 if (!isUndefOrEqual(Mask[0], NumElts)) 2899 return false; 2900 2901 for (int i = 1; i < NumElts; ++i) 2902 if (!isUndefOrEqual(Mask[i], i)) 2903 return false; 2904 2905 return true; 2906} 2907 2908bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 2909 SmallVector<int, 8> M; 2910 N->getMask(M); 2911 return ::isMOVLMask(M, N->getValueType(0)); 2912} 2913 2914/// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 2915/// of what x86 movss want. X86 movs requires the lowest element to be lowest 2916/// element of vector 2 and the other elements to come from vector 1 in order. 2917static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 2918 bool V2IsSplat = false, bool V2IsUndef = false) { 2919 int NumOps = VT.getVectorNumElements(); 2920 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 2921 return false; 2922 2923 if (!isUndefOrEqual(Mask[0], 0)) 2924 return false; 2925 2926 for (int i = 1; i < NumOps; ++i) 2927 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 2928 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 2929 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 2930 return false; 2931 2932 return true; 2933} 2934 2935static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 2936 bool V2IsUndef = false) { 2937 SmallVector<int, 8> M; 2938 N->getMask(M); 2939 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 2940} 2941 2942/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2943/// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 2944bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) { 2945 if (N->getValueType(0).getVectorNumElements() != 4) 2946 return false; 2947 2948 // Expect 1, 1, 3, 3 2949 for (unsigned i = 0; i < 2; ++i) { 2950 int Elt = N->getMaskElt(i); 2951 if (Elt >= 0 && Elt != 1) 2952 return false; 2953 } 2954 2955 bool HasHi = false; 2956 for (unsigned i = 2; i < 4; ++i) { 2957 int Elt = N->getMaskElt(i); 2958 if (Elt >= 0 && Elt != 3) 2959 return false; 2960 if (Elt == 3) 2961 HasHi = true; 2962 } 2963 // Don't use movshdup if it can be done with a shufps. 2964 // FIXME: verify that matching u, u, 3, 3 is what we want. 2965 return HasHi; 2966} 2967 2968/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2969/// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 2970bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) { 2971 if (N->getValueType(0).getVectorNumElements() != 4) 2972 return false; 2973 2974 // Expect 0, 0, 2, 2 2975 for (unsigned i = 0; i < 2; ++i) 2976 if (N->getMaskElt(i) > 0) 2977 return false; 2978 2979 bool HasHi = false; 2980 for (unsigned i = 2; i < 4; ++i) { 2981 int Elt = N->getMaskElt(i); 2982 if (Elt >= 0 && Elt != 2) 2983 return false; 2984 if (Elt == 2) 2985 HasHi = true; 2986 } 2987 // Don't use movsldup if it can be done with a shufps. 2988 return HasHi; 2989} 2990 2991/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 2992/// specifies a shuffle of elements that is suitable for input to MOVDDUP. 2993bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 2994 int e = N->getValueType(0).getVectorNumElements() / 2; 2995 2996 for (int i = 0; i < e; ++i) 2997 if (!isUndefOrEqual(N->getMaskElt(i), i)) 2998 return false; 2999 for (int i = 0; i < e; ++i) 3000 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3001 return false; 3002 return true; 3003} 3004 3005/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 3006/// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 3007unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 3008 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3009 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 3010 3011 unsigned Shift = (NumOperands == 4) ? 2 : 1; 3012 unsigned Mask = 0; 3013 for (int i = 0; i < NumOperands; ++i) { 3014 int Val = SVOp->getMaskElt(NumOperands-i-1); 3015 if (Val < 0) Val = 0; 3016 if (Val >= NumOperands) Val -= NumOperands; 3017 Mask |= Val; 3018 if (i != NumOperands - 1) 3019 Mask <<= Shift; 3020 } 3021 return Mask; 3022} 3023 3024/// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 3025/// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 3026unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 3027 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3028 unsigned Mask = 0; 3029 // 8 nodes, but we only care about the last 4. 3030 for (unsigned i = 7; i >= 4; --i) { 3031 int Val = SVOp->getMaskElt(i); 3032 if (Val >= 0) 3033 Mask |= (Val - 4); 3034 if (i != 4) 3035 Mask <<= 2; 3036 } 3037 return Mask; 3038} 3039 3040/// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 3041/// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 3042unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 3043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3044 unsigned Mask = 0; 3045 // 8 nodes, but we only care about the first 4. 3046 for (int i = 3; i >= 0; --i) { 3047 int Val = SVOp->getMaskElt(i); 3048 if (Val >= 0) 3049 Mask |= Val; 3050 if (i != 0) 3051 Mask <<= 2; 3052 } 3053 return Mask; 3054} 3055 3056/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 3057/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 3058unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 3059 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3060 EVT VVT = N->getValueType(0); 3061 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 3062 int Val = 0; 3063 3064 unsigned i, e; 3065 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 3066 Val = SVOp->getMaskElt(i); 3067 if (Val >= 0) 3068 break; 3069 } 3070 return (Val - i) * EltSize; 3071} 3072 3073/// isZeroNode - Returns true if Elt is a constant zero or a floating point 3074/// constant +0.0. 3075bool X86::isZeroNode(SDValue Elt) { 3076 return ((isa<ConstantSDNode>(Elt) && 3077 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) || 3078 (isa<ConstantFPSDNode>(Elt) && 3079 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 3080} 3081 3082/// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 3083/// their permute mask. 3084static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 3085 SelectionDAG &DAG) { 3086 EVT VT = SVOp->getValueType(0); 3087 unsigned NumElems = VT.getVectorNumElements(); 3088 SmallVector<int, 8> MaskVec; 3089 3090 for (unsigned i = 0; i != NumElems; ++i) { 3091 int idx = SVOp->getMaskElt(i); 3092 if (idx < 0) 3093 MaskVec.push_back(idx); 3094 else if (idx < (int)NumElems) 3095 MaskVec.push_back(idx + NumElems); 3096 else 3097 MaskVec.push_back(idx - NumElems); 3098 } 3099 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 3100 SVOp->getOperand(0), &MaskVec[0]); 3101} 3102 3103/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 3104/// the two vector operands have swapped position. 3105static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 3106 unsigned NumElems = VT.getVectorNumElements(); 3107 for (unsigned i = 0; i != NumElems; ++i) { 3108 int idx = Mask[i]; 3109 if (idx < 0) 3110 continue; 3111 else if (idx < (int)NumElems) 3112 Mask[i] = idx + NumElems; 3113 else 3114 Mask[i] = idx - NumElems; 3115 } 3116} 3117 3118/// ShouldXformToMOVHLPS - Return true if the node should be transformed to 3119/// match movhlps. The lower half elements should come from upper half of 3120/// V1 (and in order), and the upper half elements should come from the upper 3121/// half of V2 (and in order). 3122static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 3123 if (Op->getValueType(0).getVectorNumElements() != 4) 3124 return false; 3125 for (unsigned i = 0, e = 2; i != e; ++i) 3126 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 3127 return false; 3128 for (unsigned i = 2; i != 4; ++i) 3129 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 3130 return false; 3131 return true; 3132} 3133 3134/// isScalarLoadToVector - Returns true if the node is a scalar load that 3135/// is promoted to a vector. It also returns the LoadSDNode by reference if 3136/// required. 3137static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 3138 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 3139 return false; 3140 N = N->getOperand(0).getNode(); 3141 if (!ISD::isNON_EXTLoad(N)) 3142 return false; 3143 if (LD) 3144 *LD = cast<LoadSDNode>(N); 3145 return true; 3146} 3147 3148/// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 3149/// match movlp{s|d}. The lower half elements should come from lower half of 3150/// V1 (and in order), and the upper half elements should come from the upper 3151/// half of V2 (and in order). And since V1 will become the source of the 3152/// MOVLP, it must be either a vector load or a scalar load to vector. 3153static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 3154 ShuffleVectorSDNode *Op) { 3155 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 3156 return false; 3157 // Is V2 is a vector load, don't do this transformation. We will try to use 3158 // load folding shufps op. 3159 if (ISD::isNON_EXTLoad(V2)) 3160 return false; 3161 3162 unsigned NumElems = Op->getValueType(0).getVectorNumElements(); 3163 3164 if (NumElems != 2 && NumElems != 4) 3165 return false; 3166 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 3167 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 3168 return false; 3169 for (unsigned i = NumElems/2; i != NumElems; ++i) 3170 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 3171 return false; 3172 return true; 3173} 3174 3175/// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 3176/// all the same. 3177static bool isSplatVector(SDNode *N) { 3178 if (N->getOpcode() != ISD::BUILD_VECTOR) 3179 return false; 3180 3181 SDValue SplatValue = N->getOperand(0); 3182 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 3183 if (N->getOperand(i) != SplatValue) 3184 return false; 3185 return true; 3186} 3187 3188/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 3189/// to an zero vector. 3190/// FIXME: move to dag combiner / method on ShuffleVectorSDNode 3191static bool isZeroShuffle(ShuffleVectorSDNode *N) { 3192 SDValue V1 = N->getOperand(0); 3193 SDValue V2 = N->getOperand(1); 3194 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3195 for (unsigned i = 0; i != NumElems; ++i) { 3196 int Idx = N->getMaskElt(i); 3197 if (Idx >= (int)NumElems) { 3198 unsigned Opc = V2.getOpcode(); 3199 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 3200 continue; 3201 if (Opc != ISD::BUILD_VECTOR || 3202 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 3203 return false; 3204 } else if (Idx >= 0) { 3205 unsigned Opc = V1.getOpcode(); 3206 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 3207 continue; 3208 if (Opc != ISD::BUILD_VECTOR || 3209 !X86::isZeroNode(V1.getOperand(Idx))) 3210 return false; 3211 } 3212 } 3213 return true; 3214} 3215 3216/// getZeroVector - Returns a vector of specified type with all zero elements. 3217/// 3218static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, 3219 DebugLoc dl) { 3220 assert(VT.isVector() && "Expected a vector type"); 3221 3222 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3223 // type. This ensures they get CSE'd. 3224 SDValue Vec; 3225 if (VT.getSizeInBits() == 64) { // MMX 3226 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3227 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3228 } else if (HasSSE2) { // SSE2 3229 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 3230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3231 } else { // SSE1 3232 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 3233 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 3234 } 3235 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3236} 3237 3238/// getOnesVector - Returns a vector of specified type with all bits set. 3239/// 3240static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3241 assert(VT.isVector() && "Expected a vector type"); 3242 3243 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest 3244 // type. This ensures they get CSE'd. 3245 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 3246 SDValue Vec; 3247 if (VT.getSizeInBits() == 64) // MMX 3248 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); 3249 else // SSE 3250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 3251 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); 3252} 3253 3254 3255/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 3256/// that point to V2 points to its first element. 3257static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 3258 EVT VT = SVOp->getValueType(0); 3259 unsigned NumElems = VT.getVectorNumElements(); 3260 3261 bool Changed = false; 3262 SmallVector<int, 8> MaskVec; 3263 SVOp->getMask(MaskVec); 3264 3265 for (unsigned i = 0; i != NumElems; ++i) { 3266 if (MaskVec[i] > (int)NumElems) { 3267 MaskVec[i] = NumElems; 3268 Changed = true; 3269 } 3270 } 3271 if (Changed) 3272 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 3273 SVOp->getOperand(1), &MaskVec[0]); 3274 return SDValue(SVOp, 0); 3275} 3276 3277/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 3278/// operation of specified width. 3279static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3280 SDValue V2) { 3281 unsigned NumElems = VT.getVectorNumElements(); 3282 SmallVector<int, 8> Mask; 3283 Mask.push_back(NumElems); 3284 for (unsigned i = 1; i != NumElems; ++i) 3285 Mask.push_back(i); 3286 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3287} 3288 3289/// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 3290static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3291 SDValue V2) { 3292 unsigned NumElems = VT.getVectorNumElements(); 3293 SmallVector<int, 8> Mask; 3294 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 3295 Mask.push_back(i); 3296 Mask.push_back(i + NumElems); 3297 } 3298 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3299} 3300 3301/// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. 3302static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 3303 SDValue V2) { 3304 unsigned NumElems = VT.getVectorNumElements(); 3305 unsigned Half = NumElems/2; 3306 SmallVector<int, 8> Mask; 3307 for (unsigned i = 0; i != Half; ++i) { 3308 Mask.push_back(i + Half); 3309 Mask.push_back(i + NumElems + Half); 3310 } 3311 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 3312} 3313 3314/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32. 3315static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, 3316 bool HasSSE2) { 3317 if (SV->getValueType(0).getVectorNumElements() <= 4) 3318 return SDValue(SV, 0); 3319 3320 EVT PVT = MVT::v4f32; 3321 EVT VT = SV->getValueType(0); 3322 DebugLoc dl = SV->getDebugLoc(); 3323 SDValue V1 = SV->getOperand(0); 3324 int NumElems = VT.getVectorNumElements(); 3325 int EltNo = SV->getSplatIndex(); 3326 3327 // unpack elements to the correct location 3328 while (NumElems > 4) { 3329 if (EltNo < NumElems/2) { 3330 V1 = getUnpackl(DAG, dl, VT, V1, V1); 3331 } else { 3332 V1 = getUnpackh(DAG, dl, VT, V1, V1); 3333 EltNo -= NumElems/2; 3334 } 3335 NumElems >>= 1; 3336 } 3337 3338 // Perform the splat. 3339 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 3340 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1); 3341 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]); 3342 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1); 3343} 3344 3345/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 3346/// vector of zero or undef vector. This produces a shuffle where the low 3347/// element of V2 is swizzled into the zero/undef vector, landing at element 3348/// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 3349static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 3350 bool isZero, bool HasSSE2, 3351 SelectionDAG &DAG) { 3352 EVT VT = V2.getValueType(); 3353 SDValue V1 = isZero 3354 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 3355 unsigned NumElems = VT.getVectorNumElements(); 3356 SmallVector<int, 16> MaskVec; 3357 for (unsigned i = 0; i != NumElems; ++i) 3358 // If this is the insertion idx, put the low elt of V2 here. 3359 MaskVec.push_back(i == Idx ? NumElems : i); 3360 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 3361} 3362 3363/// getNumOfConsecutiveZeros - Return the number of elements in a result of 3364/// a shuffle that is zero. 3365static 3366unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems, 3367 bool Low, SelectionDAG &DAG) { 3368 unsigned NumZeros = 0; 3369 for (int i = 0; i < NumElems; ++i) { 3370 unsigned Index = Low ? i : NumElems-i-1; 3371 int Idx = SVOp->getMaskElt(Index); 3372 if (Idx < 0) { 3373 ++NumZeros; 3374 continue; 3375 } 3376 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index); 3377 if (Elt.getNode() && X86::isZeroNode(Elt)) 3378 ++NumZeros; 3379 else 3380 break; 3381 } 3382 return NumZeros; 3383} 3384 3385/// isVectorShift - Returns true if the shuffle can be implemented as a 3386/// logical left or right shift of a vector. 3387/// FIXME: split into pslldqi, psrldqi, palignr variants. 3388static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 3389 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 3390 int NumElems = SVOp->getValueType(0).getVectorNumElements(); 3391 3392 isLeft = true; 3393 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG); 3394 if (!NumZeros) { 3395 isLeft = false; 3396 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG); 3397 if (!NumZeros) 3398 return false; 3399 } 3400 bool SeenV1 = false; 3401 bool SeenV2 = false; 3402 for (int i = NumZeros; i < NumElems; ++i) { 3403 int Val = isLeft ? (i - NumZeros) : i; 3404 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros)); 3405 if (Idx < 0) 3406 continue; 3407 if (Idx < NumElems) 3408 SeenV1 = true; 3409 else { 3410 Idx -= NumElems; 3411 SeenV2 = true; 3412 } 3413 if (Idx != Val) 3414 return false; 3415 } 3416 if (SeenV1 && SeenV2) 3417 return false; 3418 3419 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1); 3420 ShAmt = NumZeros; 3421 return true; 3422} 3423 3424 3425/// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 3426/// 3427static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 3428 unsigned NumNonZero, unsigned NumZero, 3429 SelectionDAG &DAG, TargetLowering &TLI) { 3430 if (NumNonZero > 8) 3431 return SDValue(); 3432 3433 DebugLoc dl = Op.getDebugLoc(); 3434 SDValue V(0, 0); 3435 bool First = true; 3436 for (unsigned i = 0; i < 16; ++i) { 3437 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 3438 if (ThisIsNonZero && First) { 3439 if (NumZero) 3440 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3441 else 3442 V = DAG.getUNDEF(MVT::v8i16); 3443 First = false; 3444 } 3445 3446 if ((i & 1) != 0) { 3447 SDValue ThisElt(0, 0), LastElt(0, 0); 3448 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 3449 if (LastIsNonZero) { 3450 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 3451 MVT::i16, Op.getOperand(i-1)); 3452 } 3453 if (ThisIsNonZero) { 3454 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 3455 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 3456 ThisElt, DAG.getConstant(8, MVT::i8)); 3457 if (LastIsNonZero) 3458 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 3459 } else 3460 ThisElt = LastElt; 3461 3462 if (ThisElt.getNode()) 3463 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 3464 DAG.getIntPtrConstant(i/2)); 3465 } 3466 } 3467 3468 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); 3469} 3470 3471/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 3472/// 3473static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 3474 unsigned NumNonZero, unsigned NumZero, 3475 SelectionDAG &DAG, TargetLowering &TLI) { 3476 if (NumNonZero > 4) 3477 return SDValue(); 3478 3479 DebugLoc dl = Op.getDebugLoc(); 3480 SDValue V(0, 0); 3481 bool First = true; 3482 for (unsigned i = 0; i < 8; ++i) { 3483 bool isNonZero = (NonZeros & (1 << i)) != 0; 3484 if (isNonZero) { 3485 if (First) { 3486 if (NumZero) 3487 V = getZeroVector(MVT::v8i16, true, DAG, dl); 3488 else 3489 V = DAG.getUNDEF(MVT::v8i16); 3490 First = false; 3491 } 3492 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 3493 MVT::v8i16, V, Op.getOperand(i), 3494 DAG.getIntPtrConstant(i)); 3495 } 3496 } 3497 3498 return V; 3499} 3500 3501/// getVShift - Return a vector logical shift node. 3502/// 3503static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 3504 unsigned NumBits, SelectionDAG &DAG, 3505 const TargetLowering &TLI, DebugLoc dl) { 3506 bool isMMX = VT.getSizeInBits() == 64; 3507 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; 3508 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 3509 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); 3510 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3511 DAG.getNode(Opc, dl, ShVT, SrcOp, 3512 DAG.getConstant(NumBits, TLI.getShiftAmountTy()))); 3513} 3514 3515SDValue 3516X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 3517 SelectionDAG &DAG) { 3518 3519 // Check if the scalar load can be widened into a vector load. And if 3520 // the address is "base + cst" see if the cst can be "absorbed" into 3521 // the shuffle mask. 3522 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 3523 SDValue Ptr = LD->getBasePtr(); 3524 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 3525 return SDValue(); 3526 EVT PVT = LD->getValueType(0); 3527 if (PVT != MVT::i32 && PVT != MVT::f32) 3528 return SDValue(); 3529 3530 int FI = -1; 3531 int64_t Offset = 0; 3532 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 3533 FI = FINode->getIndex(); 3534 Offset = 0; 3535 } else if (Ptr.getOpcode() == ISD::ADD && 3536 isa<ConstantSDNode>(Ptr.getOperand(1)) && 3537 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 3538 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 3539 Offset = Ptr.getConstantOperandVal(1); 3540 Ptr = Ptr.getOperand(0); 3541 } else { 3542 return SDValue(); 3543 } 3544 3545 SDValue Chain = LD->getChain(); 3546 // Make sure the stack object alignment is at least 16. 3547 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3548 if (DAG.InferPtrAlignment(Ptr) < 16) { 3549 if (MFI->isFixedObjectIndex(FI)) { 3550 // Can't change the alignment. FIXME: It's possible to compute 3551 // the exact stack offset and reference FI + adjust offset instead. 3552 // If someone *really* cares about this. That's the way to implement it. 3553 return SDValue(); 3554 } else { 3555 MFI->setObjectAlignment(FI, 16); 3556 } 3557 } 3558 3559 // (Offset % 16) must be multiple of 4. Then address is then 3560 // Ptr + (Offset & ~15). 3561 if (Offset < 0) 3562 return SDValue(); 3563 if ((Offset % 16) & 3) 3564 return SDValue(); 3565 int64_t StartOffset = Offset & ~15; 3566 if (StartOffset) 3567 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 3568 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 3569 3570 int EltNo = (Offset - StartOffset) >> 2; 3571 int Mask[4] = { EltNo, EltNo, EltNo, EltNo }; 3572 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32; 3573 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0, 3574 false, false, 0); 3575 // Canonicalize it to a v4i32 shuffle. 3576 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1); 3577 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 3578 DAG.getVectorShuffle(MVT::v4i32, dl, V1, 3579 DAG.getUNDEF(MVT::v4i32), &Mask[0])); 3580 } 3581 3582 return SDValue(); 3583} 3584 3585SDValue 3586X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { 3587 DebugLoc dl = Op.getDebugLoc(); 3588 // All zero's are handled with pxor, all one's are handled with pcmpeqd. 3589 if (ISD::isBuildVectorAllZeros(Op.getNode()) 3590 || ISD::isBuildVectorAllOnes(Op.getNode())) { 3591 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to 3592 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are 3593 // eliminated on x86-32 hosts. 3594 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) 3595 return Op; 3596 3597 if (ISD::isBuildVectorAllOnes(Op.getNode())) 3598 return getOnesVector(Op.getValueType(), DAG, dl); 3599 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); 3600 } 3601 3602 EVT VT = Op.getValueType(); 3603 EVT ExtVT = VT.getVectorElementType(); 3604 unsigned EVTBits = ExtVT.getSizeInBits(); 3605 3606 unsigned NumElems = Op.getNumOperands(); 3607 unsigned NumZero = 0; 3608 unsigned NumNonZero = 0; 3609 unsigned NonZeros = 0; 3610 bool IsAllConstants = true; 3611 SmallSet<SDValue, 8> Values; 3612 for (unsigned i = 0; i < NumElems; ++i) { 3613 SDValue Elt = Op.getOperand(i); 3614 if (Elt.getOpcode() == ISD::UNDEF) 3615 continue; 3616 Values.insert(Elt); 3617 if (Elt.getOpcode() != ISD::Constant && 3618 Elt.getOpcode() != ISD::ConstantFP) 3619 IsAllConstants = false; 3620 if (X86::isZeroNode(Elt)) 3621 NumZero++; 3622 else { 3623 NonZeros |= (1 << i); 3624 NumNonZero++; 3625 } 3626 } 3627 3628 if (NumNonZero == 0) { 3629 // All undef vector. Return an UNDEF. All zero vectors were handled above. 3630 return DAG.getUNDEF(VT); 3631 } 3632 3633 // Special case for single non-zero, non-undef, element. 3634 if (NumNonZero == 1) { 3635 unsigned Idx = CountTrailingZeros_32(NonZeros); 3636 SDValue Item = Op.getOperand(Idx); 3637 3638 // If this is an insertion of an i64 value on x86-32, and if the top bits of 3639 // the value are obviously zero, truncate the value to i32 and do the 3640 // insertion that way. Only do this if the value is non-constant or if the 3641 // value is a constant being inserted into element 0. It is cheaper to do 3642 // a constant pool load than it is to do a movd + shuffle. 3643 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 3644 (!IsAllConstants || Idx == 0)) { 3645 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 3646 // Handle MMX and SSE both. 3647 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; 3648 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; 3649 3650 // Truncate the value (which may itself be a constant) to i32, and 3651 // convert it to a vector with movd (S2V+shuffle to zero extend). 3652 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 3653 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 3654 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3655 Subtarget->hasSSE2(), DAG); 3656 3657 // Now we have our 32-bit value zero extended in the low element of 3658 // a vector. If Idx != 0, swizzle it into place. 3659 if (Idx != 0) { 3660 SmallVector<int, 4> Mask; 3661 Mask.push_back(Idx); 3662 for (unsigned i = 1; i != VecElts; ++i) 3663 Mask.push_back(i); 3664 Item = DAG.getVectorShuffle(VecVT, dl, Item, 3665 DAG.getUNDEF(Item.getValueType()), 3666 &Mask[0]); 3667 } 3668 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item); 3669 } 3670 } 3671 3672 // If we have a constant or non-constant insertion into the low element of 3673 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 3674 // the rest of the elements. This will be matched as movd/movq/movss/movsd 3675 // depending on what the source datatype is. 3676 if (Idx == 0) { 3677 if (NumZero == 0) { 3678 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3679 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 3680 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 3681 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3682 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 3683 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), 3684 DAG); 3685 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 3686 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 3687 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; 3688 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 3689 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 3690 Subtarget->hasSSE2(), DAG); 3691 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item); 3692 } 3693 } 3694 3695 // Is it a vector logical left shift? 3696 if (NumElems == 2 && Idx == 1 && 3697 X86::isZeroNode(Op.getOperand(0)) && 3698 !X86::isZeroNode(Op.getOperand(1))) { 3699 unsigned NumBits = VT.getSizeInBits(); 3700 return getVShift(true, VT, 3701 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 3702 VT, Op.getOperand(1)), 3703 NumBits/2, DAG, *this, dl); 3704 } 3705 3706 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 3707 return SDValue(); 3708 3709 // Otherwise, if this is a vector with i32 or f32 elements, and the element 3710 // is a non-constant being inserted into an element other than the low one, 3711 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 3712 // movd/movss) to move this into the low element, then shuffle it into 3713 // place. 3714 if (EVTBits == 32) { 3715 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 3716 3717 // Turn it into a shuffle of zero and zero-extended scalar to vector. 3718 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 3719 Subtarget->hasSSE2(), DAG); 3720 SmallVector<int, 8> MaskVec; 3721 for (unsigned i = 0; i < NumElems; i++) 3722 MaskVec.push_back(i == Idx ? 0 : 1); 3723 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 3724 } 3725 } 3726 3727 // Splat is obviously ok. Let legalizer expand it to a shuffle. 3728 if (Values.size() == 1) { 3729 if (EVTBits == 32) { 3730 // Instead of a shuffle like this: 3731 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 3732 // Check if it's possible to issue this instead. 3733 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 3734 unsigned Idx = CountTrailingZeros_32(NonZeros); 3735 SDValue Item = Op.getOperand(Idx); 3736 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 3737 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 3738 } 3739 return SDValue(); 3740 } 3741 3742 // A vector full of immediates; various special cases are already 3743 // handled, so this is best done with a single constant-pool load. 3744 if (IsAllConstants) 3745 return SDValue(); 3746 3747 // Let legalizer expand 2-wide build_vectors. 3748 if (EVTBits == 64) { 3749 if (NumNonZero == 1) { 3750 // One half is zero or undef. 3751 unsigned Idx = CountTrailingZeros_32(NonZeros); 3752 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 3753 Op.getOperand(Idx)); 3754 return getShuffleVectorZeroOrUndef(V2, Idx, true, 3755 Subtarget->hasSSE2(), DAG); 3756 } 3757 return SDValue(); 3758 } 3759 3760 // If element VT is < 32 bits, convert it to inserts into a zero vector. 3761 if (EVTBits == 8 && NumElems == 16) { 3762 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 3763 *this); 3764 if (V.getNode()) return V; 3765 } 3766 3767 if (EVTBits == 16 && NumElems == 8) { 3768 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 3769 *this); 3770 if (V.getNode()) return V; 3771 } 3772 3773 // If element VT is == 32 bits, turn it into a number of shuffles. 3774 SmallVector<SDValue, 8> V; 3775 V.resize(NumElems); 3776 if (NumElems == 4 && NumZero > 0) { 3777 for (unsigned i = 0; i < 4; ++i) { 3778 bool isZero = !(NonZeros & (1 << i)); 3779 if (isZero) 3780 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 3781 else 3782 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3783 } 3784 3785 for (unsigned i = 0; i < 2; ++i) { 3786 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 3787 default: break; 3788 case 0: 3789 V[i] = V[i*2]; // Must be a zero vector. 3790 break; 3791 case 1: 3792 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 3793 break; 3794 case 2: 3795 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 3796 break; 3797 case 3: 3798 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 3799 break; 3800 } 3801 } 3802 3803 SmallVector<int, 8> MaskVec; 3804 bool Reverse = (NonZeros & 0x3) == 2; 3805 for (unsigned i = 0; i < 2; ++i) 3806 MaskVec.push_back(Reverse ? 1-i : i); 3807 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 3808 for (unsigned i = 0; i < 2; ++i) 3809 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 3810 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 3811 } 3812 3813 if (Values.size() > 2) { 3814 // If we have SSE 4.1, Expand into a number of inserts unless the number of 3815 // values to be inserted is equal to the number of elements, in which case 3816 // use the unpack code below in the hopes of matching the consecutive elts 3817 // load merge pattern for shuffles. 3818 // FIXME: We could probably just check that here directly. 3819 if (Values.size() < NumElems && VT.getSizeInBits() == 128 && 3820 getSubtarget()->hasSSE41()) { 3821 V[0] = DAG.getUNDEF(VT); 3822 for (unsigned i = 0; i < NumElems; ++i) 3823 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 3824 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0], 3825 Op.getOperand(i), DAG.getIntPtrConstant(i)); 3826 return V[0]; 3827 } 3828 // Expand into a number of unpckl*. 3829 // e.g. for v4f32 3830 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 3831 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 3832 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 3833 for (unsigned i = 0; i < NumElems; ++i) 3834 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 3835 NumElems >>= 1; 3836 while (NumElems != 0) { 3837 for (unsigned i = 0; i < NumElems; ++i) 3838 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]); 3839 NumElems >>= 1; 3840 } 3841 return V[0]; 3842 } 3843 3844 return SDValue(); 3845} 3846 3847SDValue 3848X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 3849 // We support concatenate two MMX registers and place them in a MMX 3850 // register. This is better than doing a stack convert. 3851 DebugLoc dl = Op.getDebugLoc(); 3852 EVT ResVT = Op.getValueType(); 3853 assert(Op.getNumOperands() == 2); 3854 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 3855 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 3856 int Mask[2]; 3857 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0)); 3858 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3859 InVec = Op.getOperand(1); 3860 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 3861 unsigned NumElts = ResVT.getVectorNumElements(); 3862 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3863 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 3864 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 3865 } else { 3866 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec); 3867 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 3868 Mask[0] = 0; Mask[1] = 2; 3869 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 3870 } 3871 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp); 3872} 3873 3874// v8i16 shuffles - Prefer shuffles in the following order: 3875// 1. [all] pshuflw, pshufhw, optional move 3876// 2. [ssse3] 1 x pshufb 3877// 3. [ssse3] 2 x pshufb + 1 x por 3878// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 3879static 3880SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, 3881 SelectionDAG &DAG, X86TargetLowering &TLI) { 3882 SDValue V1 = SVOp->getOperand(0); 3883 SDValue V2 = SVOp->getOperand(1); 3884 DebugLoc dl = SVOp->getDebugLoc(); 3885 SmallVector<int, 8> MaskVals; 3886 3887 // Determine if more than 1 of the words in each of the low and high quadwords 3888 // of the result come from the same quadword of one of the two inputs. Undef 3889 // mask values count as coming from any quadword, for better codegen. 3890 SmallVector<unsigned, 4> LoQuad(4); 3891 SmallVector<unsigned, 4> HiQuad(4); 3892 BitVector InputQuads(4); 3893 for (unsigned i = 0; i < 8; ++i) { 3894 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad; 3895 int EltIdx = SVOp->getMaskElt(i); 3896 MaskVals.push_back(EltIdx); 3897 if (EltIdx < 0) { 3898 ++Quad[0]; 3899 ++Quad[1]; 3900 ++Quad[2]; 3901 ++Quad[3]; 3902 continue; 3903 } 3904 ++Quad[EltIdx / 4]; 3905 InputQuads.set(EltIdx / 4); 3906 } 3907 3908 int BestLoQuad = -1; 3909 unsigned MaxQuad = 1; 3910 for (unsigned i = 0; i < 4; ++i) { 3911 if (LoQuad[i] > MaxQuad) { 3912 BestLoQuad = i; 3913 MaxQuad = LoQuad[i]; 3914 } 3915 } 3916 3917 int BestHiQuad = -1; 3918 MaxQuad = 1; 3919 for (unsigned i = 0; i < 4; ++i) { 3920 if (HiQuad[i] > MaxQuad) { 3921 BestHiQuad = i; 3922 MaxQuad = HiQuad[i]; 3923 } 3924 } 3925 3926 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 3927 // of the two input vectors, shuffle them into one input vector so only a 3928 // single pshufb instruction is necessary. If There are more than 2 input 3929 // quads, disable the next transformation since it does not help SSSE3. 3930 bool V1Used = InputQuads[0] || InputQuads[1]; 3931 bool V2Used = InputQuads[2] || InputQuads[3]; 3932 if (TLI.getSubtarget()->hasSSSE3()) { 3933 if (InputQuads.count() == 2 && V1Used && V2Used) { 3934 BestLoQuad = InputQuads.find_first(); 3935 BestHiQuad = InputQuads.find_next(BestLoQuad); 3936 } 3937 if (InputQuads.count() > 2) { 3938 BestLoQuad = -1; 3939 BestHiQuad = -1; 3940 } 3941 } 3942 3943 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 3944 // the shuffle mask. If a quad is scored as -1, that means that it contains 3945 // words from all 4 input quadwords. 3946 SDValue NewV; 3947 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 3948 SmallVector<int, 8> MaskV; 3949 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 3950 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 3951 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 3952 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), 3953 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); 3954 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); 3955 3956 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 3957 // source words for the shuffle, to aid later transformations. 3958 bool AllWordsInNewV = true; 3959 bool InOrder[2] = { true, true }; 3960 for (unsigned i = 0; i != 8; ++i) { 3961 int idx = MaskVals[i]; 3962 if (idx != (int)i) 3963 InOrder[i/4] = false; 3964 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 3965 continue; 3966 AllWordsInNewV = false; 3967 break; 3968 } 3969 3970 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 3971 if (AllWordsInNewV) { 3972 for (int i = 0; i != 8; ++i) { 3973 int idx = MaskVals[i]; 3974 if (idx < 0) 3975 continue; 3976 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 3977 if ((idx != i) && idx < 4) 3978 pshufhw = false; 3979 if ((idx != i) && idx > 3) 3980 pshuflw = false; 3981 } 3982 V1 = NewV; 3983 V2Used = false; 3984 BestLoQuad = 0; 3985 BestHiQuad = 1; 3986 } 3987 3988 // If we've eliminated the use of V2, and the new mask is a pshuflw or 3989 // pshufhw, that's as cheap as it gets. Return the new shuffle. 3990 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 3991 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 3992 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 3993 } 3994 } 3995 3996 // If we have SSSE3, and all words of the result are from 1 input vector, 3997 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 3998 // is present, fall back to case 4. 3999 if (TLI.getSubtarget()->hasSSSE3()) { 4000 SmallVector<SDValue,16> pshufbMask; 4001 4002 // If we have elements from both input vectors, set the high bit of the 4003 // shuffle mask element to zero out elements that come from V2 in the V1 4004 // mask, and elements that come from V1 in the V2 mask, so that the two 4005 // results can be OR'd together. 4006 bool TwoInputs = V1Used && V2Used; 4007 for (unsigned i = 0; i != 8; ++i) { 4008 int EltIdx = MaskVals[i] * 2; 4009 if (TwoInputs && (EltIdx >= 16)) { 4010 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4011 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4012 continue; 4013 } 4014 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4015 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 4016 } 4017 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); 4018 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4019 DAG.getNode(ISD::BUILD_VECTOR, dl, 4020 MVT::v16i8, &pshufbMask[0], 16)); 4021 if (!TwoInputs) 4022 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4023 4024 // Calculate the shuffle mask for the second input, shuffle it, and 4025 // OR it with the first shuffled input. 4026 pshufbMask.clear(); 4027 for (unsigned i = 0; i != 8; ++i) { 4028 int EltIdx = MaskVals[i] * 2; 4029 if (EltIdx < 16) { 4030 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4031 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4032 continue; 4033 } 4034 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4035 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 4036 } 4037 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); 4038 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4039 DAG.getNode(ISD::BUILD_VECTOR, dl, 4040 MVT::v16i8, &pshufbMask[0], 16)); 4041 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4042 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4043 } 4044 4045 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 4046 // and update MaskVals with new element order. 4047 BitVector InOrder(8); 4048 if (BestLoQuad >= 0) { 4049 SmallVector<int, 8> MaskV; 4050 for (int i = 0; i != 4; ++i) { 4051 int idx = MaskVals[i]; 4052 if (idx < 0) { 4053 MaskV.push_back(-1); 4054 InOrder.set(i); 4055 } else if ((idx / 4) == BestLoQuad) { 4056 MaskV.push_back(idx & 3); 4057 InOrder.set(i); 4058 } else { 4059 MaskV.push_back(-1); 4060 } 4061 } 4062 for (unsigned i = 4; i != 8; ++i) 4063 MaskV.push_back(i); 4064 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4065 &MaskV[0]); 4066 } 4067 4068 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 4069 // and update MaskVals with the new element order. 4070 if (BestHiQuad >= 0) { 4071 SmallVector<int, 8> MaskV; 4072 for (unsigned i = 0; i != 4; ++i) 4073 MaskV.push_back(i); 4074 for (unsigned i = 4; i != 8; ++i) { 4075 int idx = MaskVals[i]; 4076 if (idx < 0) { 4077 MaskV.push_back(-1); 4078 InOrder.set(i); 4079 } else if ((idx / 4) == BestHiQuad) { 4080 MaskV.push_back((idx & 3) + 4); 4081 InOrder.set(i); 4082 } else { 4083 MaskV.push_back(-1); 4084 } 4085 } 4086 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 4087 &MaskV[0]); 4088 } 4089 4090 // In case BestHi & BestLo were both -1, which means each quadword has a word 4091 // from each of the four input quadwords, calculate the InOrder bitvector now 4092 // before falling through to the insert/extract cleanup. 4093 if (BestLoQuad == -1 && BestHiQuad == -1) { 4094 NewV = V1; 4095 for (int i = 0; i != 8; ++i) 4096 if (MaskVals[i] < 0 || MaskVals[i] == i) 4097 InOrder.set(i); 4098 } 4099 4100 // The other elements are put in the right place using pextrw and pinsrw. 4101 for (unsigned i = 0; i != 8; ++i) { 4102 if (InOrder[i]) 4103 continue; 4104 int EltIdx = MaskVals[i]; 4105 if (EltIdx < 0) 4106 continue; 4107 SDValue ExtOp = (EltIdx < 8) 4108 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 4109 DAG.getIntPtrConstant(EltIdx)) 4110 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 4111 DAG.getIntPtrConstant(EltIdx - 8)); 4112 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 4113 DAG.getIntPtrConstant(i)); 4114 } 4115 return NewV; 4116} 4117 4118// v16i8 shuffles - Prefer shuffles in the following order: 4119// 1. [ssse3] 1 x pshufb 4120// 2. [ssse3] 2 x pshufb + 1 x por 4121// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 4122static 4123SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 4124 SelectionDAG &DAG, X86TargetLowering &TLI) { 4125 SDValue V1 = SVOp->getOperand(0); 4126 SDValue V2 = SVOp->getOperand(1); 4127 DebugLoc dl = SVOp->getDebugLoc(); 4128 SmallVector<int, 16> MaskVals; 4129 SVOp->getMask(MaskVals); 4130 4131 // If we have SSSE3, case 1 is generated when all result bytes come from 4132 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 4133 // present, fall back to case 3. 4134 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 4135 bool V1Only = true; 4136 bool V2Only = true; 4137 for (unsigned i = 0; i < 16; ++i) { 4138 int EltIdx = MaskVals[i]; 4139 if (EltIdx < 0) 4140 continue; 4141 if (EltIdx < 16) 4142 V2Only = false; 4143 else 4144 V1Only = false; 4145 } 4146 4147 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 4148 if (TLI.getSubtarget()->hasSSSE3()) { 4149 SmallVector<SDValue,16> pshufbMask; 4150 4151 // If all result elements are from one input vector, then only translate 4152 // undef mask values to 0x80 (zero out result) in the pshufb mask. 4153 // 4154 // Otherwise, we have elements from both input vectors, and must zero out 4155 // elements that come from V2 in the first mask, and V1 in the second mask 4156 // so that we can OR them together. 4157 bool TwoInputs = !(V1Only || V2Only); 4158 for (unsigned i = 0; i != 16; ++i) { 4159 int EltIdx = MaskVals[i]; 4160 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 4161 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4162 continue; 4163 } 4164 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 4165 } 4166 // If all the elements are from V2, assign it to V1 and return after 4167 // building the first pshufb. 4168 if (V2Only) 4169 V1 = V2; 4170 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 4171 DAG.getNode(ISD::BUILD_VECTOR, dl, 4172 MVT::v16i8, &pshufbMask[0], 16)); 4173 if (!TwoInputs) 4174 return V1; 4175 4176 // Calculate the shuffle mask for the second input, shuffle it, and 4177 // OR it with the first shuffled input. 4178 pshufbMask.clear(); 4179 for (unsigned i = 0; i != 16; ++i) { 4180 int EltIdx = MaskVals[i]; 4181 if (EltIdx < 16) { 4182 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 4183 continue; 4184 } 4185 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 4186 } 4187 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 4188 DAG.getNode(ISD::BUILD_VECTOR, dl, 4189 MVT::v16i8, &pshufbMask[0], 16)); 4190 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 4191 } 4192 4193 // No SSSE3 - Calculate in place words and then fix all out of place words 4194 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 4195 // the 16 different words that comprise the two doublequadword input vectors. 4196 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); 4197 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); 4198 SDValue NewV = V2Only ? V2 : V1; 4199 for (int i = 0; i != 8; ++i) { 4200 int Elt0 = MaskVals[i*2]; 4201 int Elt1 = MaskVals[i*2+1]; 4202 4203 // This word of the result is all undef, skip it. 4204 if (Elt0 < 0 && Elt1 < 0) 4205 continue; 4206 4207 // This word of the result is already in the correct place, skip it. 4208 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 4209 continue; 4210 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 4211 continue; 4212 4213 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 4214 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 4215 SDValue InsElt; 4216 4217 // If Elt0 and Elt1 are defined, are consecutive, and can be load 4218 // using a single extract together, load it and store it. 4219 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 4220 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4221 DAG.getIntPtrConstant(Elt1 / 2)); 4222 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4223 DAG.getIntPtrConstant(i)); 4224 continue; 4225 } 4226 4227 // If Elt1 is defined, extract it from the appropriate source. If the 4228 // source byte is not also odd, shift the extracted word left 8 bits 4229 // otherwise clear the bottom 8 bits if we need to do an or. 4230 if (Elt1 >= 0) { 4231 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 4232 DAG.getIntPtrConstant(Elt1 / 2)); 4233 if ((Elt1 & 1) == 0) 4234 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 4235 DAG.getConstant(8, TLI.getShiftAmountTy())); 4236 else if (Elt0 >= 0) 4237 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 4238 DAG.getConstant(0xFF00, MVT::i16)); 4239 } 4240 // If Elt0 is defined, extract it from the appropriate source. If the 4241 // source byte is not also even, shift the extracted word right 8 bits. If 4242 // Elt1 was also defined, OR the extracted values together before 4243 // inserting them in the result. 4244 if (Elt0 >= 0) { 4245 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 4246 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 4247 if ((Elt0 & 1) != 0) 4248 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 4249 DAG.getConstant(8, TLI.getShiftAmountTy())); 4250 else if (Elt1 >= 0) 4251 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 4252 DAG.getConstant(0x00FF, MVT::i16)); 4253 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 4254 : InsElt0; 4255 } 4256 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 4257 DAG.getIntPtrConstant(i)); 4258 } 4259 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); 4260} 4261 4262/// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 4263/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be 4264/// done when every pair / quad of shuffle mask elements point to elements in 4265/// the right sequence. e.g. 4266/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> 4267static 4268SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 4269 SelectionDAG &DAG, 4270 TargetLowering &TLI, DebugLoc dl) { 4271 EVT VT = SVOp->getValueType(0); 4272 SDValue V1 = SVOp->getOperand(0); 4273 SDValue V2 = SVOp->getOperand(1); 4274 unsigned NumElems = VT.getVectorNumElements(); 4275 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 4276 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); 4277 EVT MaskEltVT = MaskVT.getVectorElementType(); 4278 EVT NewVT = MaskVT; 4279 switch (VT.getSimpleVT().SimpleTy) { 4280 default: assert(false && "Unexpected!"); 4281 case MVT::v4f32: NewVT = MVT::v2f64; break; 4282 case MVT::v4i32: NewVT = MVT::v2i64; break; 4283 case MVT::v8i16: NewVT = MVT::v4i32; break; 4284 case MVT::v16i8: NewVT = MVT::v4i32; break; 4285 } 4286 4287 if (NewWidth == 2) { 4288 if (VT.isInteger()) 4289 NewVT = MVT::v2i64; 4290 else 4291 NewVT = MVT::v2f64; 4292 } 4293 int Scale = NumElems / NewWidth; 4294 SmallVector<int, 8> MaskVec; 4295 for (unsigned i = 0; i < NumElems; i += Scale) { 4296 int StartIdx = -1; 4297 for (int j = 0; j < Scale; ++j) { 4298 int EltIdx = SVOp->getMaskElt(i+j); 4299 if (EltIdx < 0) 4300 continue; 4301 if (StartIdx == -1) 4302 StartIdx = EltIdx - (EltIdx % Scale); 4303 if (EltIdx != StartIdx + j) 4304 return SDValue(); 4305 } 4306 if (StartIdx == -1) 4307 MaskVec.push_back(-1); 4308 else 4309 MaskVec.push_back(StartIdx / Scale); 4310 } 4311 4312 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1); 4313 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2); 4314 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 4315} 4316 4317/// getVZextMovL - Return a zero-extending vector move low node. 4318/// 4319static SDValue getVZextMovL(EVT VT, EVT OpVT, 4320 SDValue SrcOp, SelectionDAG &DAG, 4321 const X86Subtarget *Subtarget, DebugLoc dl) { 4322 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 4323 LoadSDNode *LD = NULL; 4324 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 4325 LD = dyn_cast<LoadSDNode>(SrcOp); 4326 if (!LD) { 4327 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 4328 // instead. 4329 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 4330 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) && 4331 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 4332 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && 4333 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 4334 // PR2108 4335 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 4336 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4337 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4338 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 4339 OpVT, 4340 SrcOp.getOperand(0) 4341 .getOperand(0)))); 4342 } 4343 } 4344 } 4345 4346 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4347 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 4348 DAG.getNode(ISD::BIT_CONVERT, dl, 4349 OpVT, SrcOp))); 4350} 4351 4352/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of 4353/// shuffles. 4354static SDValue 4355LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4356 SDValue V1 = SVOp->getOperand(0); 4357 SDValue V2 = SVOp->getOperand(1); 4358 DebugLoc dl = SVOp->getDebugLoc(); 4359 EVT VT = SVOp->getValueType(0); 4360 4361 SmallVector<std::pair<int, int>, 8> Locs; 4362 Locs.resize(4); 4363 SmallVector<int, 8> Mask1(4U, -1); 4364 SmallVector<int, 8> PermMask; 4365 SVOp->getMask(PermMask); 4366 4367 unsigned NumHi = 0; 4368 unsigned NumLo = 0; 4369 for (unsigned i = 0; i != 4; ++i) { 4370 int Idx = PermMask[i]; 4371 if (Idx < 0) { 4372 Locs[i] = std::make_pair(-1, -1); 4373 } else { 4374 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 4375 if (Idx < 4) { 4376 Locs[i] = std::make_pair(0, NumLo); 4377 Mask1[NumLo] = Idx; 4378 NumLo++; 4379 } else { 4380 Locs[i] = std::make_pair(1, NumHi); 4381 if (2+NumHi < 4) 4382 Mask1[2+NumHi] = Idx; 4383 NumHi++; 4384 } 4385 } 4386 } 4387 4388 if (NumLo <= 2 && NumHi <= 2) { 4389 // If no more than two elements come from either vector. This can be 4390 // implemented with two shuffles. First shuffle gather the elements. 4391 // The second shuffle, which takes the first shuffle as both of its 4392 // vector operands, put the elements into the right order. 4393 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4394 4395 SmallVector<int, 8> Mask2(4U, -1); 4396 4397 for (unsigned i = 0; i != 4; ++i) { 4398 if (Locs[i].first == -1) 4399 continue; 4400 else { 4401 unsigned Idx = (i < 2) ? 0 : 4; 4402 Idx += Locs[i].first * 2 + Locs[i].second; 4403 Mask2[i] = Idx; 4404 } 4405 } 4406 4407 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 4408 } else if (NumLo == 3 || NumHi == 3) { 4409 // Otherwise, we must have three elements from one vector, call it X, and 4410 // one element from the other, call it Y. First, use a shufps to build an 4411 // intermediate vector with the one element from Y and the element from X 4412 // that will be in the same half in the final destination (the indexes don't 4413 // matter). Then, use a shufps to build the final vector, taking the half 4414 // containing the element from Y from the intermediate, and the other half 4415 // from X. 4416 if (NumHi == 3) { 4417 // Normalize it so the 3 elements come from V1. 4418 CommuteVectorShuffleMask(PermMask, VT); 4419 std::swap(V1, V2); 4420 } 4421 4422 // Find the element from V2. 4423 unsigned HiIndex; 4424 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 4425 int Val = PermMask[HiIndex]; 4426 if (Val < 0) 4427 continue; 4428 if (Val >= 4) 4429 break; 4430 } 4431 4432 Mask1[0] = PermMask[HiIndex]; 4433 Mask1[1] = -1; 4434 Mask1[2] = PermMask[HiIndex^1]; 4435 Mask1[3] = -1; 4436 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4437 4438 if (HiIndex >= 2) { 4439 Mask1[0] = PermMask[0]; 4440 Mask1[1] = PermMask[1]; 4441 Mask1[2] = HiIndex & 1 ? 6 : 4; 4442 Mask1[3] = HiIndex & 1 ? 4 : 6; 4443 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 4444 } else { 4445 Mask1[0] = HiIndex & 1 ? 2 : 0; 4446 Mask1[1] = HiIndex & 1 ? 0 : 2; 4447 Mask1[2] = PermMask[2]; 4448 Mask1[3] = PermMask[3]; 4449 if (Mask1[2] >= 0) 4450 Mask1[2] += 4; 4451 if (Mask1[3] >= 0) 4452 Mask1[3] += 4; 4453 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 4454 } 4455 } 4456 4457 // Break it into (shuffle shuffle_hi, shuffle_lo). 4458 Locs.clear(); 4459 SmallVector<int,8> LoMask(4U, -1); 4460 SmallVector<int,8> HiMask(4U, -1); 4461 4462 SmallVector<int,8> *MaskPtr = &LoMask; 4463 unsigned MaskIdx = 0; 4464 unsigned LoIdx = 0; 4465 unsigned HiIdx = 2; 4466 for (unsigned i = 0; i != 4; ++i) { 4467 if (i == 2) { 4468 MaskPtr = &HiMask; 4469 MaskIdx = 1; 4470 LoIdx = 0; 4471 HiIdx = 2; 4472 } 4473 int Idx = PermMask[i]; 4474 if (Idx < 0) { 4475 Locs[i] = std::make_pair(-1, -1); 4476 } else if (Idx < 4) { 4477 Locs[i] = std::make_pair(MaskIdx, LoIdx); 4478 (*MaskPtr)[LoIdx] = Idx; 4479 LoIdx++; 4480 } else { 4481 Locs[i] = std::make_pair(MaskIdx, HiIdx); 4482 (*MaskPtr)[HiIdx] = Idx; 4483 HiIdx++; 4484 } 4485 } 4486 4487 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 4488 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 4489 SmallVector<int, 8> MaskOps; 4490 for (unsigned i = 0; i != 4; ++i) { 4491 if (Locs[i].first == -1) { 4492 MaskOps.push_back(-1); 4493 } else { 4494 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 4495 MaskOps.push_back(Idx); 4496 } 4497 } 4498 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 4499} 4500 4501SDValue 4502X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4503 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4504 SDValue V1 = Op.getOperand(0); 4505 SDValue V2 = Op.getOperand(1); 4506 EVT VT = Op.getValueType(); 4507 DebugLoc dl = Op.getDebugLoc(); 4508 unsigned NumElems = VT.getVectorNumElements(); 4509 bool isMMX = VT.getSizeInBits() == 64; 4510 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 4511 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 4512 bool V1IsSplat = false; 4513 bool V2IsSplat = false; 4514 4515 if (isZeroShuffle(SVOp)) 4516 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); 4517 4518 // Promote splats to v4f32. 4519 if (SVOp->isSplat()) { 4520 if (isMMX || NumElems < 4) 4521 return Op; 4522 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2()); 4523 } 4524 4525 // If the shuffle can be profitably rewritten as a narrower shuffle, then 4526 // do it! 4527 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 4528 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4529 if (NewOp.getNode()) 4530 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 4531 LowerVECTOR_SHUFFLE(NewOp, DAG)); 4532 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { 4533 // FIXME: Figure out a cleaner way to do this. 4534 // Try to make use of movq to zero out the top part. 4535 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 4536 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4537 if (NewOp.getNode()) { 4538 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 4539 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 4540 DAG, Subtarget, dl); 4541 } 4542 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 4543 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); 4544 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 4545 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 4546 DAG, Subtarget, dl); 4547 } 4548 } 4549 4550 if (X86::isPSHUFDMask(SVOp)) 4551 return Op; 4552 4553 // Check if this can be converted into a logical shift. 4554 bool isLeft = false; 4555 unsigned ShAmt = 0; 4556 SDValue ShVal; 4557 bool isShift = getSubtarget()->hasSSE2() && 4558 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 4559 if (isShift && ShVal.hasOneUse()) { 4560 // If the shifted value has multiple uses, it may be cheaper to use 4561 // v_set0 + movlhps or movhlps, etc. 4562 EVT EltVT = VT.getVectorElementType(); 4563 ShAmt *= EltVT.getSizeInBits(); 4564 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4565 } 4566 4567 if (X86::isMOVLMask(SVOp)) { 4568 if (V1IsUndef) 4569 return V2; 4570 if (ISD::isBuildVectorAllZeros(V1.getNode())) 4571 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 4572 if (!isMMX) 4573 return Op; 4574 } 4575 4576 // FIXME: fold these into legal mask. 4577 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || 4578 X86::isMOVSLDUPMask(SVOp) || 4579 X86::isMOVHLPSMask(SVOp) || 4580 X86::isMOVLHPSMask(SVOp) || 4581 X86::isMOVLPMask(SVOp))) 4582 return Op; 4583 4584 if (ShouldXformToMOVHLPS(SVOp) || 4585 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 4586 return CommuteVectorShuffle(SVOp, DAG); 4587 4588 if (isShift) { 4589 // No better options. Use a vshl / vsrl. 4590 EVT EltVT = VT.getVectorElementType(); 4591 ShAmt *= EltVT.getSizeInBits(); 4592 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 4593 } 4594 4595 bool Commuted = false; 4596 // FIXME: This should also accept a bitcast of a splat? Be careful, not 4597 // 1,1,1,1 -> v8i16 though. 4598 V1IsSplat = isSplatVector(V1.getNode()); 4599 V2IsSplat = isSplatVector(V2.getNode()); 4600 4601 // Canonicalize the splat or undef, if present, to be on the RHS. 4602 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 4603 Op = CommuteVectorShuffle(SVOp, DAG); 4604 SVOp = cast<ShuffleVectorSDNode>(Op); 4605 V1 = SVOp->getOperand(0); 4606 V2 = SVOp->getOperand(1); 4607 std::swap(V1IsSplat, V2IsSplat); 4608 std::swap(V1IsUndef, V2IsUndef); 4609 Commuted = true; 4610 } 4611 4612 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 4613 // Shuffling low element of v1 into undef, just return v1. 4614 if (V2IsUndef) 4615 return V1; 4616 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 4617 // the instruction selector will not match, so get a canonical MOVL with 4618 // swapped operands to undo the commute. 4619 return getMOVL(DAG, dl, VT, V2, V1); 4620 } 4621 4622 if (X86::isUNPCKL_v_undef_Mask(SVOp) || 4623 X86::isUNPCKH_v_undef_Mask(SVOp) || 4624 X86::isUNPCKLMask(SVOp) || 4625 X86::isUNPCKHMask(SVOp)) 4626 return Op; 4627 4628 if (V2IsSplat) { 4629 // Normalize mask so all entries that point to V2 points to its first 4630 // element then try to match unpck{h|l} again. If match, return a 4631 // new vector_shuffle with the corrected mask. 4632 SDValue NewMask = NormalizeMask(SVOp, DAG); 4633 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 4634 if (NSVOp != SVOp) { 4635 if (X86::isUNPCKLMask(NSVOp, true)) { 4636 return NewMask; 4637 } else if (X86::isUNPCKHMask(NSVOp, true)) { 4638 return NewMask; 4639 } 4640 } 4641 } 4642 4643 if (Commuted) { 4644 // Commute is back and try unpck* again. 4645 // FIXME: this seems wrong. 4646 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 4647 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 4648 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || 4649 X86::isUNPCKH_v_undef_Mask(NewSVOp) || 4650 X86::isUNPCKLMask(NewSVOp) || 4651 X86::isUNPCKHMask(NewSVOp)) 4652 return NewOp; 4653 } 4654 4655 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. 4656 4657 // Normalize the node to match x86 shuffle ops if needed 4658 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 4659 return CommuteVectorShuffle(SVOp, DAG); 4660 4661 // Check for legal shuffle and return? 4662 SmallVector<int, 16> PermMask; 4663 SVOp->getMask(PermMask); 4664 if (isShuffleMaskLegal(PermMask, VT)) 4665 return Op; 4666 4667 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 4668 if (VT == MVT::v8i16) { 4669 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); 4670 if (NewOp.getNode()) 4671 return NewOp; 4672 } 4673 4674 if (VT == MVT::v16i8) { 4675 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 4676 if (NewOp.getNode()) 4677 return NewOp; 4678 } 4679 4680 // Handle all 4 wide cases with a number of shuffles except for MMX. 4681 if (NumElems == 4 && !isMMX) 4682 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG); 4683 4684 return SDValue(); 4685} 4686 4687SDValue 4688X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 4689 SelectionDAG &DAG) { 4690 EVT VT = Op.getValueType(); 4691 DebugLoc dl = Op.getDebugLoc(); 4692 if (VT.getSizeInBits() == 8) { 4693 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 4694 Op.getOperand(0), Op.getOperand(1)); 4695 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4696 DAG.getValueType(VT)); 4697 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4698 } else if (VT.getSizeInBits() == 16) { 4699 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4700 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 4701 if (Idx == 0) 4702 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4703 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4704 DAG.getNode(ISD::BIT_CONVERT, dl, 4705 MVT::v4i32, 4706 Op.getOperand(0)), 4707 Op.getOperand(1))); 4708 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 4709 Op.getOperand(0), Op.getOperand(1)); 4710 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 4711 DAG.getValueType(VT)); 4712 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4713 } else if (VT == MVT::f32) { 4714 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 4715 // the result back to FR32 register. It's only worth matching if the 4716 // result has a single use which is a store or a bitcast to i32. And in 4717 // the case of a store, it's not worth it if the index is a constant 0, 4718 // because a MOVSSmr can be used instead, which is smaller and faster. 4719 if (!Op.hasOneUse()) 4720 return SDValue(); 4721 SDNode *User = *Op.getNode()->use_begin(); 4722 if ((User->getOpcode() != ISD::STORE || 4723 (isa<ConstantSDNode>(Op.getOperand(1)) && 4724 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 4725 (User->getOpcode() != ISD::BIT_CONVERT || 4726 User->getValueType(0) != MVT::i32)) 4727 return SDValue(); 4728 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4729 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, 4730 Op.getOperand(0)), 4731 Op.getOperand(1)); 4732 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); 4733 } else if (VT == MVT::i32) { 4734 // ExtractPS works with constant index. 4735 if (isa<ConstantSDNode>(Op.getOperand(1))) 4736 return Op; 4737 } 4738 return SDValue(); 4739} 4740 4741 4742SDValue 4743X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4744 if (!isa<ConstantSDNode>(Op.getOperand(1))) 4745 return SDValue(); 4746 4747 if (Subtarget->hasSSE41()) { 4748 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 4749 if (Res.getNode()) 4750 return Res; 4751 } 4752 4753 EVT VT = Op.getValueType(); 4754 DebugLoc dl = Op.getDebugLoc(); 4755 // TODO: handle v16i8. 4756 if (VT.getSizeInBits() == 16) { 4757 SDValue Vec = Op.getOperand(0); 4758 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4759 if (Idx == 0) 4760 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 4761 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 4762 DAG.getNode(ISD::BIT_CONVERT, dl, 4763 MVT::v4i32, Vec), 4764 Op.getOperand(1))); 4765 // Transform it so it match pextrw which produces a 32-bit result. 4766 EVT EltVT = MVT::i32; 4767 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 4768 Op.getOperand(0), Op.getOperand(1)); 4769 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 4770 DAG.getValueType(VT)); 4771 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 4772 } else if (VT.getSizeInBits() == 32) { 4773 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4774 if (Idx == 0) 4775 return Op; 4776 4777 // SHUFPS the element to the lowest double word, then movss. 4778 int Mask[4] = { Idx, -1, -1, -1 }; 4779 EVT VVT = Op.getOperand(0).getValueType(); 4780 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4781 DAG.getUNDEF(VVT), Mask); 4782 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4783 DAG.getIntPtrConstant(0)); 4784 } else if (VT.getSizeInBits() == 64) { 4785 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 4786 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 4787 // to match extract_elt for f64. 4788 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 4789 if (Idx == 0) 4790 return Op; 4791 4792 // UNPCKHPD the element to the lowest double word, then movsd. 4793 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 4794 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 4795 int Mask[2] = { 1, -1 }; 4796 EVT VVT = Op.getOperand(0).getValueType(); 4797 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 4798 DAG.getUNDEF(VVT), Mask); 4799 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 4800 DAG.getIntPtrConstant(0)); 4801 } 4802 4803 return SDValue(); 4804} 4805 4806SDValue 4807X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ 4808 EVT VT = Op.getValueType(); 4809 EVT EltVT = VT.getVectorElementType(); 4810 DebugLoc dl = Op.getDebugLoc(); 4811 4812 SDValue N0 = Op.getOperand(0); 4813 SDValue N1 = Op.getOperand(1); 4814 SDValue N2 = Op.getOperand(2); 4815 4816 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 4817 isa<ConstantSDNode>(N2)) { 4818 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB 4819 : X86ISD::PINSRW; 4820 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 4821 // argument. 4822 if (N1.getValueType() != MVT::i32) 4823 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4824 if (N2.getValueType() != MVT::i32) 4825 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4826 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 4827 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 4828 // Bits [7:6] of the constant are the source select. This will always be 4829 // zero here. The DAG Combiner may combine an extract_elt index into these 4830 // bits. For example (insert (extract, 3), 2) could be matched by putting 4831 // the '3' into bits [7:6] of X86ISD::INSERTPS. 4832 // Bits [5:4] of the constant are the destination select. This is the 4833 // value of the incoming immediate. 4834 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 4835 // combine either bitwise AND or insert of float 0.0 to set these bits. 4836 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 4837 // Create this as a scalar to vector.. 4838 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 4839 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 4840 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 4841 // PINSR* works with constant index. 4842 return Op; 4843 } 4844 return SDValue(); 4845} 4846 4847SDValue 4848X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4849 EVT VT = Op.getValueType(); 4850 EVT EltVT = VT.getVectorElementType(); 4851 4852 if (Subtarget->hasSSE41()) 4853 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 4854 4855 if (EltVT == MVT::i8) 4856 return SDValue(); 4857 4858 DebugLoc dl = Op.getDebugLoc(); 4859 SDValue N0 = Op.getOperand(0); 4860 SDValue N1 = Op.getOperand(1); 4861 SDValue N2 = Op.getOperand(2); 4862 4863 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 4864 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 4865 // as its second argument. 4866 if (N1.getValueType() != MVT::i32) 4867 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 4868 if (N2.getValueType() != MVT::i32) 4869 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 4870 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 4871 } 4872 return SDValue(); 4873} 4874 4875SDValue 4876X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { 4877 DebugLoc dl = Op.getDebugLoc(); 4878 if (Op.getValueType() == MVT::v2f32) 4879 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, 4880 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, 4881 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, 4882 Op.getOperand(0)))); 4883 4884 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) 4885 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 4886 4887 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 4888 EVT VT = MVT::v2i32; 4889 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4890 default: break; 4891 case MVT::v16i8: 4892 case MVT::v8i16: 4893 VT = MVT::v4i32; 4894 break; 4895 } 4896 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), 4897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt)); 4898} 4899 4900// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 4901// their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 4902// one of the above mentioned nodes. It has to be wrapped because otherwise 4903// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 4904// be used to form addressing mode. These wrapped nodes will be selected 4905// into MOV32ri. 4906SDValue 4907X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 4908 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 4909 4910 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4911 // global base reg. 4912 unsigned char OpFlag = 0; 4913 unsigned WrapperKind = X86ISD::Wrapper; 4914 CodeModel::Model M = getTargetMachine().getCodeModel(); 4915 4916 if (Subtarget->isPICStyleRIPRel() && 4917 (M == CodeModel::Small || M == CodeModel::Kernel)) 4918 WrapperKind = X86ISD::WrapperRIP; 4919 else if (Subtarget->isPICStyleGOT()) 4920 OpFlag = X86II::MO_GOTOFF; 4921 else if (Subtarget->isPICStyleStubPIC()) 4922 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4923 4924 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 4925 CP->getAlignment(), 4926 CP->getOffset(), OpFlag); 4927 DebugLoc DL = CP->getDebugLoc(); 4928 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4929 // With PIC, the address is actually $g + Offset. 4930 if (OpFlag) { 4931 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4932 DAG.getNode(X86ISD::GlobalBaseReg, 4933 DebugLoc::getUnknownLoc(), getPointerTy()), 4934 Result); 4935 } 4936 4937 return Result; 4938} 4939 4940SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { 4941 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 4942 4943 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4944 // global base reg. 4945 unsigned char OpFlag = 0; 4946 unsigned WrapperKind = X86ISD::Wrapper; 4947 CodeModel::Model M = getTargetMachine().getCodeModel(); 4948 4949 if (Subtarget->isPICStyleRIPRel() && 4950 (M == CodeModel::Small || M == CodeModel::Kernel)) 4951 WrapperKind = X86ISD::WrapperRIP; 4952 else if (Subtarget->isPICStyleGOT()) 4953 OpFlag = X86II::MO_GOTOFF; 4954 else if (Subtarget->isPICStyleStubPIC()) 4955 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4956 4957 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 4958 OpFlag); 4959 DebugLoc DL = JT->getDebugLoc(); 4960 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4961 4962 // With PIC, the address is actually $g + Offset. 4963 if (OpFlag) { 4964 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 4965 DAG.getNode(X86ISD::GlobalBaseReg, 4966 DebugLoc::getUnknownLoc(), getPointerTy()), 4967 Result); 4968 } 4969 4970 return Result; 4971} 4972 4973SDValue 4974X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { 4975 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 4976 4977 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 4978 // global base reg. 4979 unsigned char OpFlag = 0; 4980 unsigned WrapperKind = X86ISD::Wrapper; 4981 CodeModel::Model M = getTargetMachine().getCodeModel(); 4982 4983 if (Subtarget->isPICStyleRIPRel() && 4984 (M == CodeModel::Small || M == CodeModel::Kernel)) 4985 WrapperKind = X86ISD::WrapperRIP; 4986 else if (Subtarget->isPICStyleGOT()) 4987 OpFlag = X86II::MO_GOTOFF; 4988 else if (Subtarget->isPICStyleStubPIC()) 4989 OpFlag = X86II::MO_PIC_BASE_OFFSET; 4990 4991 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 4992 4993 DebugLoc DL = Op.getDebugLoc(); 4994 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 4995 4996 4997 // With PIC, the address is actually $g + Offset. 4998 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 4999 !Subtarget->is64Bit()) { 5000 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 5001 DAG.getNode(X86ISD::GlobalBaseReg, 5002 DebugLoc::getUnknownLoc(), 5003 getPointerTy()), 5004 Result); 5005 } 5006 5007 return Result; 5008} 5009 5010SDValue 5011X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { 5012 // Create the TargetBlockAddressAddress node. 5013 unsigned char OpFlags = 5014 Subtarget->ClassifyBlockAddressReference(); 5015 CodeModel::Model M = getTargetMachine().getCodeModel(); 5016 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 5017 DebugLoc dl = Op.getDebugLoc(); 5018 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 5019 /*isTarget=*/true, OpFlags); 5020 5021 if (Subtarget->isPICStyleRIPRel() && 5022 (M == CodeModel::Small || M == CodeModel::Kernel)) 5023 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5024 else 5025 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5026 5027 // With PIC, the address is actually $g + Offset. 5028 if (isGlobalRelativeToPICBase(OpFlags)) { 5029 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5030 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5031 Result); 5032 } 5033 5034 return Result; 5035} 5036 5037SDValue 5038X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 5039 int64_t Offset, 5040 SelectionDAG &DAG) const { 5041 // Create the TargetGlobalAddress node, folding in the constant 5042 // offset if it is legal. 5043 unsigned char OpFlags = 5044 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 5045 CodeModel::Model M = getTargetMachine().getCodeModel(); 5046 SDValue Result; 5047 if (OpFlags == X86II::MO_NO_FLAG && 5048 X86::isOffsetSuitableForCodeModel(Offset, M)) { 5049 // A direct static reference to a global. 5050 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 5051 Offset = 0; 5052 } else { 5053 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 5054 } 5055 5056 if (Subtarget->isPICStyleRIPRel() && 5057 (M == CodeModel::Small || M == CodeModel::Kernel)) 5058 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 5059 else 5060 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 5061 5062 // With PIC, the address is actually $g + Offset. 5063 if (isGlobalRelativeToPICBase(OpFlags)) { 5064 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 5065 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 5066 Result); 5067 } 5068 5069 // For globals that require a load from a stub to get the address, emit the 5070 // load. 5071 if (isGlobalStubReference(OpFlags)) 5072 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 5073 PseudoSourceValue::getGOT(), 0, false, false, 0); 5074 5075 // If there was a non-zero offset that we didn't fold, create an explicit 5076 // addition for it. 5077 if (Offset != 0) 5078 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 5079 DAG.getConstant(Offset, getPointerTy())); 5080 5081 return Result; 5082} 5083 5084SDValue 5085X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 5086 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 5087 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 5088 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 5089} 5090 5091static SDValue 5092GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 5093 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 5094 unsigned char OperandFlags) { 5095 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 5096 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 5097 DebugLoc dl = GA->getDebugLoc(); 5098 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), 5099 GA->getValueType(0), 5100 GA->getOffset(), 5101 OperandFlags); 5102 if (InFlag) { 5103 SDValue Ops[] = { Chain, TGA, *InFlag }; 5104 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 5105 } else { 5106 SDValue Ops[] = { Chain, TGA }; 5107 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 5108 } 5109 5110 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 5111 MFI->setHasCalls(true); 5112 5113 SDValue Flag = Chain.getValue(1); 5114 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 5115} 5116 5117// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 5118static SDValue 5119LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5120 const EVT PtrVT) { 5121 SDValue InFlag; 5122 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 5123 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 5124 DAG.getNode(X86ISD::GlobalBaseReg, 5125 DebugLoc::getUnknownLoc(), 5126 PtrVT), InFlag); 5127 InFlag = Chain.getValue(1); 5128 5129 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 5130} 5131 5132// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 5133static SDValue 5134LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5135 const EVT PtrVT) { 5136 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 5137 X86::RAX, X86II::MO_TLSGD); 5138} 5139 5140// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 5141// "local exec" model. 5142static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 5143 const EVT PtrVT, TLSModel::Model model, 5144 bool is64Bit) { 5145 DebugLoc dl = GA->getDebugLoc(); 5146 // Get the Thread Pointer 5147 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, 5148 DebugLoc::getUnknownLoc(), PtrVT, 5149 DAG.getRegister(is64Bit? X86::FS : X86::GS, 5150 MVT::i32)); 5151 5152 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, 5153 NULL, 0, false, false, 0); 5154 5155 unsigned char OperandFlags = 0; 5156 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 5157 // initialexec. 5158 unsigned WrapperKind = X86ISD::Wrapper; 5159 if (model == TLSModel::LocalExec) { 5160 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 5161 } else if (is64Bit) { 5162 assert(model == TLSModel::InitialExec); 5163 OperandFlags = X86II::MO_GOTTPOFF; 5164 WrapperKind = X86ISD::WrapperRIP; 5165 } else { 5166 assert(model == TLSModel::InitialExec); 5167 OperandFlags = X86II::MO_INDNTPOFF; 5168 } 5169 5170 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 5171 // exec) 5172 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), 5173 GA->getOffset(), OperandFlags); 5174 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 5175 5176 if (model == TLSModel::InitialExec) 5177 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 5178 PseudoSourceValue::getGOT(), 0, false, false, 0); 5179 5180 // The address of the thread local variable is the add of the thread 5181 // pointer with the offset of the variable. 5182 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 5183} 5184 5185SDValue 5186X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 5187 // TODO: implement the "local dynamic" model 5188 // TODO: implement the "initial exec"model for pic executables 5189 assert(Subtarget->isTargetELF() && 5190 "TLS not implemented for non-ELF targets"); 5191 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 5192 const GlobalValue *GV = GA->getGlobal(); 5193 5194 // If GV is an alias then use the aliasee for determining 5195 // thread-localness. 5196 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 5197 GV = GA->resolveAliasedGlobal(false); 5198 5199 TLSModel::Model model = getTLSModel(GV, 5200 getTargetMachine().getRelocationModel()); 5201 5202 switch (model) { 5203 case TLSModel::GeneralDynamic: 5204 case TLSModel::LocalDynamic: // not implemented 5205 if (Subtarget->is64Bit()) 5206 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 5207 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 5208 5209 case TLSModel::InitialExec: 5210 case TLSModel::LocalExec: 5211 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 5212 Subtarget->is64Bit()); 5213 } 5214 5215 llvm_unreachable("Unreachable"); 5216 return SDValue(); 5217} 5218 5219 5220/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and 5221/// take a 2 x i32 value to shift plus a shift amount. 5222SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { 5223 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 5224 EVT VT = Op.getValueType(); 5225 unsigned VTBits = VT.getSizeInBits(); 5226 DebugLoc dl = Op.getDebugLoc(); 5227 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 5228 SDValue ShOpLo = Op.getOperand(0); 5229 SDValue ShOpHi = Op.getOperand(1); 5230 SDValue ShAmt = Op.getOperand(2); 5231 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 5232 DAG.getConstant(VTBits - 1, MVT::i8)) 5233 : DAG.getConstant(0, VT); 5234 5235 SDValue Tmp2, Tmp3; 5236 if (Op.getOpcode() == ISD::SHL_PARTS) { 5237 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 5238 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 5239 } else { 5240 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 5241 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 5242 } 5243 5244 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 5245 DAG.getConstant(VTBits, MVT::i8)); 5246 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, 5247 AndNode, DAG.getConstant(0, MVT::i8)); 5248 5249 SDValue Hi, Lo; 5250 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 5251 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 5252 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 5253 5254 if (Op.getOpcode() == ISD::SHL_PARTS) { 5255 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5256 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5257 } else { 5258 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 5259 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 5260 } 5261 5262 SDValue Ops[2] = { Lo, Hi }; 5263 return DAG.getMergeValues(Ops, 2, dl); 5264} 5265 5266SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5267 EVT SrcVT = Op.getOperand(0).getValueType(); 5268 5269 if (SrcVT.isVector()) { 5270 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { 5271 return Op; 5272 } 5273 return SDValue(); 5274 } 5275 5276 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 5277 "Unknown SINT_TO_FP to lower!"); 5278 5279 // These are really Legal; return the operand so the caller accepts it as 5280 // Legal. 5281 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 5282 return Op; 5283 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 5284 Subtarget->is64Bit()) { 5285 return Op; 5286 } 5287 5288 DebugLoc dl = Op.getDebugLoc(); 5289 unsigned Size = SrcVT.getSizeInBits()/8; 5290 MachineFunction &MF = DAG.getMachineFunction(); 5291 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 5292 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5293 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5294 StackSlot, 5295 PseudoSourceValue::getFixedStack(SSFI), 0, 5296 false, false, 0); 5297 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 5298} 5299 5300SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 5301 SDValue StackSlot, 5302 SelectionDAG &DAG) { 5303 // Build the FILD 5304 DebugLoc dl = Op.getDebugLoc(); 5305 SDVTList Tys; 5306 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 5307 if (useSSE) 5308 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); 5309 else 5310 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 5311 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 5312 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl, 5313 Tys, Ops, array_lengthof(Ops)); 5314 5315 if (useSSE) { 5316 Chain = Result.getValue(1); 5317 SDValue InFlag = Result.getValue(2); 5318 5319 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 5320 // shouldn't be necessary except that RFP cannot be live across 5321 // multiple blocks. When stackifier is fixed, they can be uncoupled. 5322 MachineFunction &MF = DAG.getMachineFunction(); 5323 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 5324 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5325 Tys = DAG.getVTList(MVT::Other); 5326 SDValue Ops[] = { 5327 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 5328 }; 5329 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops)); 5330 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot, 5331 PseudoSourceValue::getFixedStack(SSFI), 0, 5332 false, false, 0); 5333 } 5334 5335 return Result; 5336} 5337 5338// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 5339SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { 5340 // This algorithm is not obvious. Here it is in C code, more or less: 5341 /* 5342 double uint64_to_double( uint32_t hi, uint32_t lo ) { 5343 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 5344 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 5345 5346 // Copy ints to xmm registers. 5347 __m128i xh = _mm_cvtsi32_si128( hi ); 5348 __m128i xl = _mm_cvtsi32_si128( lo ); 5349 5350 // Combine into low half of a single xmm register. 5351 __m128i x = _mm_unpacklo_epi32( xh, xl ); 5352 __m128d d; 5353 double sd; 5354 5355 // Merge in appropriate exponents to give the integer bits the right 5356 // magnitude. 5357 x = _mm_unpacklo_epi32( x, exp ); 5358 5359 // Subtract away the biases to deal with the IEEE-754 double precision 5360 // implicit 1. 5361 d = _mm_sub_pd( (__m128d) x, bias ); 5362 5363 // All conversions up to here are exact. The correctly rounded result is 5364 // calculated using the current rounding mode using the following 5365 // horizontal add. 5366 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 5367 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 5368 // store doesn't really need to be here (except 5369 // maybe to zero the other double) 5370 return sd; 5371 } 5372 */ 5373 5374 DebugLoc dl = Op.getDebugLoc(); 5375 LLVMContext *Context = DAG.getContext(); 5376 5377 // Build some magic constants. 5378 std::vector<Constant*> CV0; 5379 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 5380 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 5381 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5382 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 5383 Constant *C0 = ConstantVector::get(CV0); 5384 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 5385 5386 std::vector<Constant*> CV1; 5387 CV1.push_back( 5388 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 5389 CV1.push_back( 5390 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 5391 Constant *C1 = ConstantVector::get(CV1); 5392 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 5393 5394 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5395 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5396 Op.getOperand(0), 5397 DAG.getIntPtrConstant(1))); 5398 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5399 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5400 Op.getOperand(0), 5401 DAG.getIntPtrConstant(0))); 5402 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 5403 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 5404 PseudoSourceValue::getConstantPool(), 0, 5405 false, false, 16); 5406 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 5407 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); 5408 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 5409 PseudoSourceValue::getConstantPool(), 0, 5410 false, false, 16); 5411 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 5412 5413 // Add the halves; easiest way is to swap them into another reg first. 5414 int ShufMask[2] = { 1, -1 }; 5415 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 5416 DAG.getUNDEF(MVT::v2f64), ShufMask); 5417 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 5418 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 5419 DAG.getIntPtrConstant(0)); 5420} 5421 5422// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 5423SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { 5424 DebugLoc dl = Op.getDebugLoc(); 5425 // FP constant to bias correct the final result. 5426 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 5427 MVT::f64); 5428 5429 // Load the 32-bit value into an XMM register. 5430 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 5431 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5432 Op.getOperand(0), 5433 DAG.getIntPtrConstant(0))); 5434 5435 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5436 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), 5437 DAG.getIntPtrConstant(0)); 5438 5439 // Or the load with the bias. 5440 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 5441 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5442 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5443 MVT::v2f64, Load)), 5444 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5445 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5446 MVT::v2f64, Bias))); 5447 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 5448 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), 5449 DAG.getIntPtrConstant(0)); 5450 5451 // Subtract the bias. 5452 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 5453 5454 // Handle final rounding. 5455 EVT DestVT = Op.getValueType(); 5456 5457 if (DestVT.bitsLT(MVT::f64)) { 5458 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 5459 DAG.getIntPtrConstant(0)); 5460 } else if (DestVT.bitsGT(MVT::f64)) { 5461 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 5462 } 5463 5464 // Handle final rounding. 5465 return Sub; 5466} 5467 5468SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 5469 SDValue N0 = Op.getOperand(0); 5470 DebugLoc dl = Op.getDebugLoc(); 5471 5472 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 5473 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 5474 // the optimization here. 5475 if (DAG.SignBitIsZero(N0)) 5476 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 5477 5478 EVT SrcVT = N0.getValueType(); 5479 if (SrcVT == MVT::i64) { 5480 // We only handle SSE2 f64 target here; caller can expand the rest. 5481 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) 5482 return SDValue(); 5483 5484 return LowerUINT_TO_FP_i64(Op, DAG); 5485 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { 5486 return LowerUINT_TO_FP_i32(Op, DAG); 5487 } 5488 5489 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); 5490 5491 // Make a 64-bit buffer, and use it to build an FILD. 5492 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 5493 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 5494 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 5495 getPointerTy(), StackSlot, WordOff); 5496 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 5497 StackSlot, NULL, 0, false, false, 0); 5498 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 5499 OffsetSlot, NULL, 0, false, false, 0); 5500 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 5501} 5502 5503std::pair<SDValue,SDValue> X86TargetLowering:: 5504FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { 5505 DebugLoc dl = Op.getDebugLoc(); 5506 5507 EVT DstTy = Op.getValueType(); 5508 5509 if (!IsSigned) { 5510 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 5511 DstTy = MVT::i64; 5512 } 5513 5514 assert(DstTy.getSimpleVT() <= MVT::i64 && 5515 DstTy.getSimpleVT() >= MVT::i16 && 5516 "Unknown FP_TO_SINT to lower!"); 5517 5518 // These are really Legal. 5519 if (DstTy == MVT::i32 && 5520 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5521 return std::make_pair(SDValue(), SDValue()); 5522 if (Subtarget->is64Bit() && 5523 DstTy == MVT::i64 && 5524 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 5525 return std::make_pair(SDValue(), SDValue()); 5526 5527 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 5528 // stack slot. 5529 MachineFunction &MF = DAG.getMachineFunction(); 5530 unsigned MemSize = DstTy.getSizeInBits()/8; 5531 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5532 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5533 5534 unsigned Opc; 5535 switch (DstTy.getSimpleVT().SimpleTy) { 5536 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 5537 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 5538 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 5539 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 5540 } 5541 5542 SDValue Chain = DAG.getEntryNode(); 5543 SDValue Value = Op.getOperand(0); 5544 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { 5545 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 5546 Chain = DAG.getStore(Chain, dl, Value, StackSlot, 5547 PseudoSourceValue::getFixedStack(SSFI), 0, 5548 false, false, 0); 5549 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 5550 SDValue Ops[] = { 5551 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) 5552 }; 5553 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3); 5554 Chain = Value.getValue(1); 5555 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 5556 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 5557 } 5558 5559 // Build the FP_TO_INT*_IN_MEM 5560 SDValue Ops[] = { Chain, Value, StackSlot }; 5561 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); 5562 5563 return std::make_pair(FIST, StackSlot); 5564} 5565 5566SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 5567 if (Op.getValueType().isVector()) { 5568 if (Op.getValueType() == MVT::v2i32 && 5569 Op.getOperand(0).getValueType() == MVT::v2f64) { 5570 return Op; 5571 } 5572 return SDValue(); 5573 } 5574 5575 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 5576 SDValue FIST = Vals.first, StackSlot = Vals.second; 5577 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 5578 if (FIST.getNode() == 0) return Op; 5579 5580 // Load the result. 5581 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5582 FIST, StackSlot, NULL, 0, false, false, 0); 5583} 5584 5585SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { 5586 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 5587 SDValue FIST = Vals.first, StackSlot = Vals.second; 5588 assert(FIST.getNode() && "Unexpected failure"); 5589 5590 // Load the result. 5591 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 5592 FIST, StackSlot, NULL, 0, false, false, 0); 5593} 5594 5595SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { 5596 LLVMContext *Context = DAG.getContext(); 5597 DebugLoc dl = Op.getDebugLoc(); 5598 EVT VT = Op.getValueType(); 5599 EVT EltVT = VT; 5600 if (VT.isVector()) 5601 EltVT = VT.getVectorElementType(); 5602 std::vector<Constant*> CV; 5603 if (EltVT == MVT::f64) { 5604 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 5605 CV.push_back(C); 5606 CV.push_back(C); 5607 } else { 5608 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 5609 CV.push_back(C); 5610 CV.push_back(C); 5611 CV.push_back(C); 5612 CV.push_back(C); 5613 } 5614 Constant *C = ConstantVector::get(CV); 5615 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5616 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5617 PseudoSourceValue::getConstantPool(), 0, 5618 false, false, 16); 5619 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 5620} 5621 5622SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { 5623 LLVMContext *Context = DAG.getContext(); 5624 DebugLoc dl = Op.getDebugLoc(); 5625 EVT VT = Op.getValueType(); 5626 EVT EltVT = VT; 5627 if (VT.isVector()) 5628 EltVT = VT.getVectorElementType(); 5629 std::vector<Constant*> CV; 5630 if (EltVT == MVT::f64) { 5631 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 5632 CV.push_back(C); 5633 CV.push_back(C); 5634 } else { 5635 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 5636 CV.push_back(C); 5637 CV.push_back(C); 5638 CV.push_back(C); 5639 CV.push_back(C); 5640 } 5641 Constant *C = ConstantVector::get(CV); 5642 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5643 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5644 PseudoSourceValue::getConstantPool(), 0, 5645 false, false, 16); 5646 if (VT.isVector()) { 5647 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, 5648 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 5649 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, 5650 Op.getOperand(0)), 5651 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); 5652 } else { 5653 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 5654 } 5655} 5656 5657SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 5658 LLVMContext *Context = DAG.getContext(); 5659 SDValue Op0 = Op.getOperand(0); 5660 SDValue Op1 = Op.getOperand(1); 5661 DebugLoc dl = Op.getDebugLoc(); 5662 EVT VT = Op.getValueType(); 5663 EVT SrcVT = Op1.getValueType(); 5664 5665 // If second operand is smaller, extend it first. 5666 if (SrcVT.bitsLT(VT)) { 5667 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 5668 SrcVT = VT; 5669 } 5670 // And if it is bigger, shrink it first. 5671 if (SrcVT.bitsGT(VT)) { 5672 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 5673 SrcVT = VT; 5674 } 5675 5676 // At this point the operands and the result should have the same 5677 // type, and that won't be f80 since that is not custom lowered. 5678 5679 // First get the sign bit of second operand. 5680 std::vector<Constant*> CV; 5681 if (SrcVT == MVT::f64) { 5682 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 5683 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5684 } else { 5685 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 5686 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5687 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5688 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5689 } 5690 Constant *C = ConstantVector::get(CV); 5691 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5692 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 5693 PseudoSourceValue::getConstantPool(), 0, 5694 false, false, 16); 5695 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 5696 5697 // Shift sign bit right or left if the two operands have different types. 5698 if (SrcVT.bitsGT(VT)) { 5699 // Op0 is MVT::f32, Op1 is MVT::f64. 5700 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 5701 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 5702 DAG.getConstant(32, MVT::i32)); 5703 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); 5704 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 5705 DAG.getIntPtrConstant(0)); 5706 } 5707 5708 // Clear first operand sign bit. 5709 CV.clear(); 5710 if (VT == MVT::f64) { 5711 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 5712 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 5713 } else { 5714 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 5715 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5716 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5717 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 5718 } 5719 C = ConstantVector::get(CV); 5720 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 5721 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5722 PseudoSourceValue::getConstantPool(), 0, 5723 false, false, 16); 5724 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 5725 5726 // Or the value with the sign bit. 5727 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 5728} 5729 5730/// Emit nodes that will be selected as "test Op0,Op0", or something 5731/// equivalent. 5732SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 5733 SelectionDAG &DAG) { 5734 DebugLoc dl = Op.getDebugLoc(); 5735 5736 // CF and OF aren't always set the way we want. Determine which 5737 // of these we need. 5738 bool NeedCF = false; 5739 bool NeedOF = false; 5740 switch (X86CC) { 5741 case X86::COND_A: case X86::COND_AE: 5742 case X86::COND_B: case X86::COND_BE: 5743 NeedCF = true; 5744 break; 5745 case X86::COND_G: case X86::COND_GE: 5746 case X86::COND_L: case X86::COND_LE: 5747 case X86::COND_O: case X86::COND_NO: 5748 NeedOF = true; 5749 break; 5750 default: break; 5751 } 5752 5753 // See if we can use the EFLAGS value from the operand instead of 5754 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 5755 // we prove that the arithmetic won't overflow, we can't use OF or CF. 5756 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) { 5757 unsigned Opcode = 0; 5758 unsigned NumOperands = 0; 5759 switch (Op.getNode()->getOpcode()) { 5760 case ISD::ADD: 5761 // Due to an isel shortcoming, be conservative if this add is likely to 5762 // be selected as part of a load-modify-store instruction. When the root 5763 // node in a match is a store, isel doesn't know how to remap non-chain 5764 // non-flag uses of other nodes in the match, such as the ADD in this 5765 // case. This leads to the ADD being left around and reselected, with 5766 // the result being two adds in the output. 5767 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5768 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5769 if (UI->getOpcode() == ISD::STORE) 5770 goto default_case; 5771 if (ConstantSDNode *C = 5772 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 5773 // An add of one will be selected as an INC. 5774 if (C->getAPIntValue() == 1) { 5775 Opcode = X86ISD::INC; 5776 NumOperands = 1; 5777 break; 5778 } 5779 // An add of negative one (subtract of one) will be selected as a DEC. 5780 if (C->getAPIntValue().isAllOnesValue()) { 5781 Opcode = X86ISD::DEC; 5782 NumOperands = 1; 5783 break; 5784 } 5785 } 5786 // Otherwise use a regular EFLAGS-setting add. 5787 Opcode = X86ISD::ADD; 5788 NumOperands = 2; 5789 break; 5790 case ISD::AND: { 5791 // If the primary and result isn't used, don't bother using X86ISD::AND, 5792 // because a TEST instruction will be better. 5793 bool NonFlagUse = false; 5794 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5795 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 5796 SDNode *User = *UI; 5797 unsigned UOpNo = UI.getOperandNo(); 5798 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 5799 // Look pass truncate. 5800 UOpNo = User->use_begin().getOperandNo(); 5801 User = *User->use_begin(); 5802 } 5803 if (User->getOpcode() != ISD::BRCOND && 5804 User->getOpcode() != ISD::SETCC && 5805 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 5806 NonFlagUse = true; 5807 break; 5808 } 5809 } 5810 if (!NonFlagUse) 5811 break; 5812 } 5813 // FALL THROUGH 5814 case ISD::SUB: 5815 case ISD::OR: 5816 case ISD::XOR: 5817 // Due to the ISEL shortcoming noted above, be conservative if this op is 5818 // likely to be selected as part of a load-modify-store instruction. 5819 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 5820 UE = Op.getNode()->use_end(); UI != UE; ++UI) 5821 if (UI->getOpcode() == ISD::STORE) 5822 goto default_case; 5823 // Otherwise use a regular EFLAGS-setting instruction. 5824 switch (Op.getNode()->getOpcode()) { 5825 case ISD::SUB: Opcode = X86ISD::SUB; break; 5826 case ISD::OR: Opcode = X86ISD::OR; break; 5827 case ISD::XOR: Opcode = X86ISD::XOR; break; 5828 case ISD::AND: Opcode = X86ISD::AND; break; 5829 default: llvm_unreachable("unexpected operator!"); 5830 } 5831 NumOperands = 2; 5832 break; 5833 case X86ISD::ADD: 5834 case X86ISD::SUB: 5835 case X86ISD::INC: 5836 case X86ISD::DEC: 5837 case X86ISD::OR: 5838 case X86ISD::XOR: 5839 case X86ISD::AND: 5840 return SDValue(Op.getNode(), 1); 5841 default: 5842 default_case: 5843 break; 5844 } 5845 if (Opcode != 0) { 5846 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 5847 SmallVector<SDValue, 4> Ops; 5848 for (unsigned i = 0; i != NumOperands; ++i) 5849 Ops.push_back(Op.getOperand(i)); 5850 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 5851 DAG.ReplaceAllUsesWith(Op, New); 5852 return SDValue(New.getNode(), 1); 5853 } 5854 } 5855 5856 // Otherwise just emit a CMP with 0, which is the TEST pattern. 5857 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 5858 DAG.getConstant(0, Op.getValueType())); 5859} 5860 5861/// Emit nodes that will be selected as "cmp Op0,Op1", or something 5862/// equivalent. 5863SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 5864 SelectionDAG &DAG) { 5865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 5866 if (C->getAPIntValue() == 0) 5867 return EmitTest(Op0, X86CC, DAG); 5868 5869 DebugLoc dl = Op0.getDebugLoc(); 5870 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 5871} 5872 5873/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 5874/// if it's possible. 5875static SDValue LowerToBT(SDValue Op0, ISD::CondCode CC, 5876 DebugLoc dl, SelectionDAG &DAG) { 5877 SDValue LHS, RHS; 5878 if (Op0.getOperand(1).getOpcode() == ISD::SHL) { 5879 if (ConstantSDNode *Op010C = 5880 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0))) 5881 if (Op010C->getZExtValue() == 1) { 5882 LHS = Op0.getOperand(0); 5883 RHS = Op0.getOperand(1).getOperand(1); 5884 } 5885 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) { 5886 if (ConstantSDNode *Op000C = 5887 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0))) 5888 if (Op000C->getZExtValue() == 1) { 5889 LHS = Op0.getOperand(1); 5890 RHS = Op0.getOperand(0).getOperand(1); 5891 } 5892 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) { 5893 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1)); 5894 SDValue AndLHS = Op0.getOperand(0); 5895 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 5896 LHS = AndLHS.getOperand(0); 5897 RHS = AndLHS.getOperand(1); 5898 } 5899 } 5900 5901 if (LHS.getNode()) { 5902 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT 5903 // instruction. Since the shift amount is in-range-or-undefined, we know 5904 // that doing a bittest on the i16 value is ok. We extend to i32 because 5905 // the encoding for the i16 version is larger than the i32 version. 5906 if (LHS.getValueType() == MVT::i8) 5907 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 5908 5909 // If the operand types disagree, extend the shift amount to match. Since 5910 // BT ignores high bits (like shifts) we can use anyextend. 5911 if (LHS.getValueType() != RHS.getValueType()) 5912 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 5913 5914 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 5915 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 5916 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5917 DAG.getConstant(Cond, MVT::i8), BT); 5918 } 5919 5920 return SDValue(); 5921} 5922 5923SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 5924 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 5925 SDValue Op0 = Op.getOperand(0); 5926 SDValue Op1 = Op.getOperand(1); 5927 DebugLoc dl = Op.getDebugLoc(); 5928 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5929 5930 // Optimize to BT if possible. 5931 // Lower (X & (1 << N)) == 0 to BT(X, N). 5932 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 5933 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 5934 if (Op0.getOpcode() == ISD::AND && 5935 Op0.hasOneUse() && 5936 Op1.getOpcode() == ISD::Constant && 5937 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 && 5938 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 5939 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 5940 if (NewSetCC.getNode()) 5941 return NewSetCC; 5942 } 5943 5944 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5945 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 5946 if (X86CC == X86::COND_INVALID) 5947 return SDValue(); 5948 5949 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); 5950 5951 // Use sbb x, x to materialize carry bit into a GPR. 5952 if (X86CC == X86::COND_B) 5953 return DAG.getNode(ISD::AND, dl, MVT::i8, 5954 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8, 5955 DAG.getConstant(X86CC, MVT::i8), Cond), 5956 DAG.getConstant(1, MVT::i8)); 5957 5958 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 5959 DAG.getConstant(X86CC, MVT::i8), Cond); 5960} 5961 5962SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 5963 SDValue Cond; 5964 SDValue Op0 = Op.getOperand(0); 5965 SDValue Op1 = Op.getOperand(1); 5966 SDValue CC = Op.getOperand(2); 5967 EVT VT = Op.getValueType(); 5968 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 5969 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 5970 DebugLoc dl = Op.getDebugLoc(); 5971 5972 if (isFP) { 5973 unsigned SSECC = 8; 5974 EVT VT0 = Op0.getValueType(); 5975 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); 5976 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 5977 bool Swap = false; 5978 5979 switch (SetCCOpcode) { 5980 default: break; 5981 case ISD::SETOEQ: 5982 case ISD::SETEQ: SSECC = 0; break; 5983 case ISD::SETOGT: 5984 case ISD::SETGT: Swap = true; // Fallthrough 5985 case ISD::SETLT: 5986 case ISD::SETOLT: SSECC = 1; break; 5987 case ISD::SETOGE: 5988 case ISD::SETGE: Swap = true; // Fallthrough 5989 case ISD::SETLE: 5990 case ISD::SETOLE: SSECC = 2; break; 5991 case ISD::SETUO: SSECC = 3; break; 5992 case ISD::SETUNE: 5993 case ISD::SETNE: SSECC = 4; break; 5994 case ISD::SETULE: Swap = true; 5995 case ISD::SETUGE: SSECC = 5; break; 5996 case ISD::SETULT: Swap = true; 5997 case ISD::SETUGT: SSECC = 6; break; 5998 case ISD::SETO: SSECC = 7; break; 5999 } 6000 if (Swap) 6001 std::swap(Op0, Op1); 6002 6003 // In the two special cases we can't handle, emit two comparisons. 6004 if (SSECC == 8) { 6005 if (SetCCOpcode == ISD::SETUEQ) { 6006 SDValue UNORD, EQ; 6007 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 6008 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 6009 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 6010 } 6011 else if (SetCCOpcode == ISD::SETONE) { 6012 SDValue ORD, NEQ; 6013 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 6014 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 6015 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 6016 } 6017 llvm_unreachable("Illegal FP comparison"); 6018 } 6019 // Handle all other FP comparisons here. 6020 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 6021 } 6022 6023 // We are handling one of the integer comparisons here. Since SSE only has 6024 // GT and EQ comparisons for integer, swapping operands and multiple 6025 // operations may be required for some comparisons. 6026 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 6027 bool Swap = false, Invert = false, FlipSigns = false; 6028 6029 switch (VT.getSimpleVT().SimpleTy) { 6030 default: break; 6031 case MVT::v8i8: 6032 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 6033 case MVT::v4i16: 6034 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 6035 case MVT::v2i32: 6036 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 6037 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 6038 } 6039 6040 switch (SetCCOpcode) { 6041 default: break; 6042 case ISD::SETNE: Invert = true; 6043 case ISD::SETEQ: Opc = EQOpc; break; 6044 case ISD::SETLT: Swap = true; 6045 case ISD::SETGT: Opc = GTOpc; break; 6046 case ISD::SETGE: Swap = true; 6047 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 6048 case ISD::SETULT: Swap = true; 6049 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 6050 case ISD::SETUGE: Swap = true; 6051 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 6052 } 6053 if (Swap) 6054 std::swap(Op0, Op1); 6055 6056 // Since SSE has no unsigned integer comparisons, we need to flip the sign 6057 // bits of the inputs before performing those operations. 6058 if (FlipSigns) { 6059 EVT EltVT = VT.getVectorElementType(); 6060 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 6061 EltVT); 6062 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 6063 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 6064 SignBits.size()); 6065 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 6066 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 6067 } 6068 6069 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 6070 6071 // If the logical-not of the result is required, perform that now. 6072 if (Invert) 6073 Result = DAG.getNOT(dl, Result, VT); 6074 6075 return Result; 6076} 6077 6078// isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 6079static bool isX86LogicalCmp(SDValue Op) { 6080 unsigned Opc = Op.getNode()->getOpcode(); 6081 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 6082 return true; 6083 if (Op.getResNo() == 1 && 6084 (Opc == X86ISD::ADD || 6085 Opc == X86ISD::SUB || 6086 Opc == X86ISD::SMUL || 6087 Opc == X86ISD::UMUL || 6088 Opc == X86ISD::INC || 6089 Opc == X86ISD::DEC || 6090 Opc == X86ISD::OR || 6091 Opc == X86ISD::XOR || 6092 Opc == X86ISD::AND)) 6093 return true; 6094 6095 return false; 6096} 6097 6098SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { 6099 bool addTest = true; 6100 SDValue Cond = Op.getOperand(0); 6101 DebugLoc dl = Op.getDebugLoc(); 6102 SDValue CC; 6103 6104 if (Cond.getOpcode() == ISD::SETCC) { 6105 SDValue NewCond = LowerSETCC(Cond, DAG); 6106 if (NewCond.getNode()) 6107 Cond = NewCond; 6108 } 6109 6110 // (select (x == 0), -1, 0) -> (sign_bit (x - 1)) 6111 SDValue Op1 = Op.getOperand(1); 6112 SDValue Op2 = Op.getOperand(2); 6113 if (Cond.getOpcode() == X86ISD::SETCC && 6114 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) { 6115 SDValue Cmp = Cond.getOperand(1); 6116 if (Cmp.getOpcode() == X86ISD::CMP) { 6117 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1); 6118 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 6119 ConstantSDNode *RHSC = 6120 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode()); 6121 if (N1C && N1C->isAllOnesValue() && 6122 N2C && N2C->isNullValue() && 6123 RHSC && RHSC->isNullValue()) { 6124 SDValue CmpOp0 = Cmp.getOperand(0); 6125 Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(), 6126 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 6127 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(), 6128 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 6129 } 6130 } 6131 } 6132 6133 // Look pass (and (setcc_carry (cmp ...)), 1). 6134 if (Cond.getOpcode() == ISD::AND && 6135 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6136 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6137 if (C && C->getAPIntValue() == 1) 6138 Cond = Cond.getOperand(0); 6139 } 6140 6141 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6142 // setting operand in place of the X86ISD::SETCC. 6143 if (Cond.getOpcode() == X86ISD::SETCC || 6144 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6145 CC = Cond.getOperand(0); 6146 6147 SDValue Cmp = Cond.getOperand(1); 6148 unsigned Opc = Cmp.getOpcode(); 6149 EVT VT = Op.getValueType(); 6150 6151 bool IllegalFPCMov = false; 6152 if (VT.isFloatingPoint() && !VT.isVector() && 6153 !isScalarFPTypeInSSEReg(VT)) // FPStack? 6154 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 6155 6156 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 6157 Opc == X86ISD::BT) { // FIXME 6158 Cond = Cmp; 6159 addTest = false; 6160 } 6161 } 6162 6163 if (addTest) { 6164 // Look pass the truncate. 6165 if (Cond.getOpcode() == ISD::TRUNCATE) 6166 Cond = Cond.getOperand(0); 6167 6168 // We know the result of AND is compared against zero. Try to match 6169 // it to BT. 6170 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6171 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6172 if (NewSetCC.getNode()) { 6173 CC = NewSetCC.getOperand(0); 6174 Cond = NewSetCC.getOperand(1); 6175 addTest = false; 6176 } 6177 } 6178 } 6179 6180 if (addTest) { 6181 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6182 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6183 } 6184 6185 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 6186 // condition is true. 6187 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 6188 SDValue Ops[] = { Op2, Op1, CC, Cond }; 6189 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops)); 6190} 6191 6192// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 6193// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 6194// from the AND / OR. 6195static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 6196 Opc = Op.getOpcode(); 6197 if (Opc != ISD::OR && Opc != ISD::AND) 6198 return false; 6199 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6200 Op.getOperand(0).hasOneUse() && 6201 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 6202 Op.getOperand(1).hasOneUse()); 6203} 6204 6205// isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 6206// 1 and that the SETCC node has a single use. 6207static bool isXor1OfSetCC(SDValue Op) { 6208 if (Op.getOpcode() != ISD::XOR) 6209 return false; 6210 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6211 if (N1C && N1C->getAPIntValue() == 1) { 6212 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 6213 Op.getOperand(0).hasOneUse(); 6214 } 6215 return false; 6216} 6217 6218SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { 6219 bool addTest = true; 6220 SDValue Chain = Op.getOperand(0); 6221 SDValue Cond = Op.getOperand(1); 6222 SDValue Dest = Op.getOperand(2); 6223 DebugLoc dl = Op.getDebugLoc(); 6224 SDValue CC; 6225 6226 if (Cond.getOpcode() == ISD::SETCC) { 6227 SDValue NewCond = LowerSETCC(Cond, DAG); 6228 if (NewCond.getNode()) 6229 Cond = NewCond; 6230 } 6231#if 0 6232 // FIXME: LowerXALUO doesn't handle these!! 6233 else if (Cond.getOpcode() == X86ISD::ADD || 6234 Cond.getOpcode() == X86ISD::SUB || 6235 Cond.getOpcode() == X86ISD::SMUL || 6236 Cond.getOpcode() == X86ISD::UMUL) 6237 Cond = LowerXALUO(Cond, DAG); 6238#endif 6239 6240 // Look pass (and (setcc_carry (cmp ...)), 1). 6241 if (Cond.getOpcode() == ISD::AND && 6242 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 6243 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 6244 if (C && C->getAPIntValue() == 1) 6245 Cond = Cond.getOperand(0); 6246 } 6247 6248 // If condition flag is set by a X86ISD::CMP, then use it as the condition 6249 // setting operand in place of the X86ISD::SETCC. 6250 if (Cond.getOpcode() == X86ISD::SETCC || 6251 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 6252 CC = Cond.getOperand(0); 6253 6254 SDValue Cmp = Cond.getOperand(1); 6255 unsigned Opc = Cmp.getOpcode(); 6256 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 6257 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 6258 Cond = Cmp; 6259 addTest = false; 6260 } else { 6261 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 6262 default: break; 6263 case X86::COND_O: 6264 case X86::COND_B: 6265 // These can only come from an arithmetic instruction with overflow, 6266 // e.g. SADDO, UADDO. 6267 Cond = Cond.getNode()->getOperand(1); 6268 addTest = false; 6269 break; 6270 } 6271 } 6272 } else { 6273 unsigned CondOpc; 6274 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 6275 SDValue Cmp = Cond.getOperand(0).getOperand(1); 6276 if (CondOpc == ISD::OR) { 6277 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 6278 // two branches instead of an explicit OR instruction with a 6279 // separate test. 6280 if (Cmp == Cond.getOperand(1).getOperand(1) && 6281 isX86LogicalCmp(Cmp)) { 6282 CC = Cond.getOperand(0).getOperand(0); 6283 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6284 Chain, Dest, CC, Cmp); 6285 CC = Cond.getOperand(1).getOperand(0); 6286 Cond = Cmp; 6287 addTest = false; 6288 } 6289 } else { // ISD::AND 6290 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 6291 // two branches instead of an explicit AND instruction with a 6292 // separate test. However, we only do this if this block doesn't 6293 // have a fall-through edge, because this requires an explicit 6294 // jmp when the condition is false. 6295 if (Cmp == Cond.getOperand(1).getOperand(1) && 6296 isX86LogicalCmp(Cmp) && 6297 Op.getNode()->hasOneUse()) { 6298 X86::CondCode CCode = 6299 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6300 CCode = X86::GetOppositeBranchCondition(CCode); 6301 CC = DAG.getConstant(CCode, MVT::i8); 6302 SDValue User = SDValue(*Op.getNode()->use_begin(), 0); 6303 // Look for an unconditional branch following this conditional branch. 6304 // We need this because we need to reverse the successors in order 6305 // to implement FCMP_OEQ. 6306 if (User.getOpcode() == ISD::BR) { 6307 SDValue FalseBB = User.getOperand(1); 6308 SDValue NewBR = 6309 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); 6310 assert(NewBR == User); 6311 Dest = FalseBB; 6312 6313 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6314 Chain, Dest, CC, Cmp); 6315 X86::CondCode CCode = 6316 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 6317 CCode = X86::GetOppositeBranchCondition(CCode); 6318 CC = DAG.getConstant(CCode, MVT::i8); 6319 Cond = Cmp; 6320 addTest = false; 6321 } 6322 } 6323 } 6324 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 6325 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 6326 // It should be transformed during dag combiner except when the condition 6327 // is set by a arithmetics with overflow node. 6328 X86::CondCode CCode = 6329 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 6330 CCode = X86::GetOppositeBranchCondition(CCode); 6331 CC = DAG.getConstant(CCode, MVT::i8); 6332 Cond = Cond.getOperand(0).getOperand(1); 6333 addTest = false; 6334 } 6335 } 6336 6337 if (addTest) { 6338 // Look pass the truncate. 6339 if (Cond.getOpcode() == ISD::TRUNCATE) 6340 Cond = Cond.getOperand(0); 6341 6342 // We know the result of AND is compared against zero. Try to match 6343 // it to BT. 6344 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 6345 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 6346 if (NewSetCC.getNode()) { 6347 CC = NewSetCC.getOperand(0); 6348 Cond = NewSetCC.getOperand(1); 6349 addTest = false; 6350 } 6351 } 6352 } 6353 6354 if (addTest) { 6355 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 6356 Cond = EmitTest(Cond, X86::COND_NE, DAG); 6357 } 6358 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 6359 Chain, Dest, CC, Cond); 6360} 6361 6362 6363// Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 6364// Calls to _alloca is needed to probe the stack when allocating more than 4k 6365// bytes in one go. Touching the stack at 4K increments is necessary to ensure 6366// that the guard pages used by the OS virtual memory manager are allocated in 6367// correct sequence. 6368SDValue 6369X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 6370 SelectionDAG &DAG) { 6371 assert(Subtarget->isTargetCygMing() && 6372 "This should be used only on Cygwin/Mingw targets"); 6373 DebugLoc dl = Op.getDebugLoc(); 6374 6375 // Get the inputs. 6376 SDValue Chain = Op.getOperand(0); 6377 SDValue Size = Op.getOperand(1); 6378 // FIXME: Ensure alignment here 6379 6380 SDValue Flag; 6381 6382 EVT IntPtr = getPointerTy(); 6383 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; 6384 6385 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 6386 6387 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); 6388 Flag = Chain.getValue(1); 6389 6390 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 6391 SDValue Ops[] = { Chain, 6392 DAG.getTargetExternalSymbol("_alloca", IntPtr), 6393 DAG.getRegister(X86::EAX, IntPtr), 6394 DAG.getRegister(X86StackPtr, SPTy), 6395 Flag }; 6396 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5); 6397 Flag = Chain.getValue(1); 6398 6399 Chain = DAG.getCALLSEQ_END(Chain, 6400 DAG.getIntPtrConstant(0, true), 6401 DAG.getIntPtrConstant(0, true), 6402 Flag); 6403 6404 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 6405 6406 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 6407 return DAG.getMergeValues(Ops1, 2, dl); 6408} 6409 6410SDValue 6411X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 6412 SDValue Chain, 6413 SDValue Dst, SDValue Src, 6414 SDValue Size, unsigned Align, 6415 const Value *DstSV, 6416 uint64_t DstSVOff) { 6417 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6418 6419 // If not DWORD aligned or size is more than the threshold, call the library. 6420 // The libc version is likely to be faster for these cases. It can use the 6421 // address value and run time information about the CPU. 6422 if ((Align & 3) != 0 || 6423 !ConstantSize || 6424 ConstantSize->getZExtValue() > 6425 getSubtarget()->getMaxInlineSizeThreshold()) { 6426 SDValue InFlag(0, 0); 6427 6428 // Check to see if there is a specialized entry-point for memory zeroing. 6429 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src); 6430 6431 if (const char *bzeroEntry = V && 6432 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { 6433 EVT IntPtr = getPointerTy(); 6434 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext()); 6435 TargetLowering::ArgListTy Args; 6436 TargetLowering::ArgListEntry Entry; 6437 Entry.Node = Dst; 6438 Entry.Ty = IntPtrTy; 6439 Args.push_back(Entry); 6440 Entry.Node = Size; 6441 Args.push_back(Entry); 6442 std::pair<SDValue,SDValue> CallResult = 6443 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), 6444 false, false, false, false, 6445 0, CallingConv::C, false, /*isReturnValueUsed=*/false, 6446 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl, 6447 DAG.GetOrdering(Chain.getNode())); 6448 return CallResult.second; 6449 } 6450 6451 // Otherwise have the target-independent code call memset. 6452 return SDValue(); 6453 } 6454 6455 uint64_t SizeVal = ConstantSize->getZExtValue(); 6456 SDValue InFlag(0, 0); 6457 EVT AVT; 6458 SDValue Count; 6459 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); 6460 unsigned BytesLeft = 0; 6461 bool TwoRepStos = false; 6462 if (ValC) { 6463 unsigned ValReg; 6464 uint64_t Val = ValC->getZExtValue() & 255; 6465 6466 // If the value is a constant, then we can potentially use larger sets. 6467 switch (Align & 3) { 6468 case 2: // WORD aligned 6469 AVT = MVT::i16; 6470 ValReg = X86::AX; 6471 Val = (Val << 8) | Val; 6472 break; 6473 case 0: // DWORD aligned 6474 AVT = MVT::i32; 6475 ValReg = X86::EAX; 6476 Val = (Val << 8) | Val; 6477 Val = (Val << 16) | Val; 6478 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 6479 AVT = MVT::i64; 6480 ValReg = X86::RAX; 6481 Val = (Val << 32) | Val; 6482 } 6483 break; 6484 default: // Byte aligned 6485 AVT = MVT::i8; 6486 ValReg = X86::AL; 6487 Count = DAG.getIntPtrConstant(SizeVal); 6488 break; 6489 } 6490 6491 if (AVT.bitsGT(MVT::i8)) { 6492 unsigned UBytes = AVT.getSizeInBits() / 8; 6493 Count = DAG.getIntPtrConstant(SizeVal / UBytes); 6494 BytesLeft = SizeVal % UBytes; 6495 } 6496 6497 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT), 6498 InFlag); 6499 InFlag = Chain.getValue(1); 6500 } else { 6501 AVT = MVT::i8; 6502 Count = DAG.getIntPtrConstant(SizeVal); 6503 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); 6504 InFlag = Chain.getValue(1); 6505 } 6506 6507 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6508 X86::ECX, 6509 Count, InFlag); 6510 InFlag = Chain.getValue(1); 6511 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6512 X86::EDI, 6513 Dst, InFlag); 6514 InFlag = Chain.getValue(1); 6515 6516 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6517 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6518 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6519 6520 if (TwoRepStos) { 6521 InFlag = Chain.getValue(1); 6522 Count = Size; 6523 EVT CVT = Count.getValueType(); 6524 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, 6525 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 6526 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 6527 X86::ECX, 6528 Left, InFlag); 6529 InFlag = Chain.getValue(1); 6530 Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6531 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag }; 6532 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops)); 6533 } else if (BytesLeft) { 6534 // Handle the last 1 - 7 bytes. 6535 unsigned Offset = SizeVal - BytesLeft; 6536 EVT AddrVT = Dst.getValueType(); 6537 EVT SizeVT = Size.getValueType(); 6538 6539 Chain = DAG.getMemset(Chain, dl, 6540 DAG.getNode(ISD::ADD, dl, AddrVT, Dst, 6541 DAG.getConstant(Offset, AddrVT)), 6542 Src, 6543 DAG.getConstant(BytesLeft, SizeVT), 6544 Align, DstSV, DstSVOff + Offset); 6545 } 6546 6547 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. 6548 return Chain; 6549} 6550 6551SDValue 6552X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 6553 SDValue Chain, SDValue Dst, SDValue Src, 6554 SDValue Size, unsigned Align, 6555 bool AlwaysInline, 6556 const Value *DstSV, uint64_t DstSVOff, 6557 const Value *SrcSV, uint64_t SrcSVOff) { 6558 // This requires the copy size to be a constant, preferrably 6559 // within a subtarget-specific limit. 6560 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 6561 if (!ConstantSize) 6562 return SDValue(); 6563 uint64_t SizeVal = ConstantSize->getZExtValue(); 6564 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 6565 return SDValue(); 6566 6567 /// If not DWORD aligned, call the library. 6568 if ((Align & 3) != 0) 6569 return SDValue(); 6570 6571 // DWORD aligned 6572 EVT AVT = MVT::i32; 6573 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned 6574 AVT = MVT::i64; 6575 6576 unsigned UBytes = AVT.getSizeInBits() / 8; 6577 unsigned CountVal = SizeVal / UBytes; 6578 SDValue Count = DAG.getIntPtrConstant(CountVal); 6579 unsigned BytesLeft = SizeVal % UBytes; 6580 6581 SDValue InFlag(0, 0); 6582 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : 6583 X86::ECX, 6584 Count, InFlag); 6585 InFlag = Chain.getValue(1); 6586 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : 6587 X86::EDI, 6588 Dst, InFlag); 6589 InFlag = Chain.getValue(1); 6590 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI : 6591 X86::ESI, 6592 Src, InFlag); 6593 InFlag = Chain.getValue(1); 6594 6595 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 6596 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag }; 6597 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops, 6598 array_lengthof(Ops)); 6599 6600 SmallVector<SDValue, 4> Results; 6601 Results.push_back(RepMovs); 6602 if (BytesLeft) { 6603 // Handle the last 1 - 7 bytes. 6604 unsigned Offset = SizeVal - BytesLeft; 6605 EVT DstVT = Dst.getValueType(); 6606 EVT SrcVT = Src.getValueType(); 6607 EVT SizeVT = Size.getValueType(); 6608 Results.push_back(DAG.getMemcpy(Chain, dl, 6609 DAG.getNode(ISD::ADD, dl, DstVT, Dst, 6610 DAG.getConstant(Offset, DstVT)), 6611 DAG.getNode(ISD::ADD, dl, SrcVT, Src, 6612 DAG.getConstant(Offset, SrcVT)), 6613 DAG.getConstant(BytesLeft, SizeVT), 6614 Align, AlwaysInline, 6615 DstSV, DstSVOff + Offset, 6616 SrcSV, SrcSVOff + Offset)); 6617 } 6618 6619 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6620 &Results[0], Results.size()); 6621} 6622 6623SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { 6624 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 6625 DebugLoc dl = Op.getDebugLoc(); 6626 6627 if (!Subtarget->is64Bit()) { 6628 // vastart just stores the address of the VarArgsFrameIndex slot into the 6629 // memory location argument. 6630 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6631 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 6632 false, false, 0); 6633 } 6634 6635 // __va_list_tag: 6636 // gp_offset (0 - 6 * 8) 6637 // fp_offset (48 - 48 + 8 * 16) 6638 // overflow_arg_area (point to parameters coming in memory). 6639 // reg_save_area 6640 SmallVector<SDValue, 8> MemOps; 6641 SDValue FIN = Op.getOperand(1); 6642 // Store gp_offset 6643 SDValue Store = DAG.getStore(Op.getOperand(0), dl, 6644 DAG.getConstant(VarArgsGPOffset, MVT::i32), 6645 FIN, SV, 0, false, false, 0); 6646 MemOps.push_back(Store); 6647 6648 // Store fp_offset 6649 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6650 FIN, DAG.getIntPtrConstant(4)); 6651 Store = DAG.getStore(Op.getOperand(0), dl, 6652 DAG.getConstant(VarArgsFPOffset, MVT::i32), 6653 FIN, SV, 0, false, false, 0); 6654 MemOps.push_back(Store); 6655 6656 // Store ptr to overflow_arg_area 6657 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6658 FIN, DAG.getIntPtrConstant(4)); 6659 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 6660 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0, 6661 false, false, 0); 6662 MemOps.push_back(Store); 6663 6664 // Store ptr to reg_save_area. 6665 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), 6666 FIN, DAG.getIntPtrConstant(8)); 6667 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); 6668 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0, 6669 false, false, 0); 6670 MemOps.push_back(Store); 6671 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 6672 &MemOps[0], MemOps.size()); 6673} 6674 6675SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { 6676 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6677 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); 6678 SDValue Chain = Op.getOperand(0); 6679 SDValue SrcPtr = Op.getOperand(1); 6680 SDValue SrcSV = Op.getOperand(2); 6681 6682 llvm_report_error("VAArgInst is not yet implemented for x86-64!"); 6683 return SDValue(); 6684} 6685 6686SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { 6687 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 6688 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 6689 SDValue Chain = Op.getOperand(0); 6690 SDValue DstPtr = Op.getOperand(1); 6691 SDValue SrcPtr = Op.getOperand(2); 6692 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 6693 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 6694 DebugLoc dl = Op.getDebugLoc(); 6695 6696 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, 6697 DAG.getIntPtrConstant(24), 8, false, 6698 DstSV, 0, SrcSV, 0); 6699} 6700 6701SDValue 6702X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 6703 DebugLoc dl = Op.getDebugLoc(); 6704 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6705 switch (IntNo) { 6706 default: return SDValue(); // Don't custom lower most intrinsics. 6707 // Comparison intrinsics. 6708 case Intrinsic::x86_sse_comieq_ss: 6709 case Intrinsic::x86_sse_comilt_ss: 6710 case Intrinsic::x86_sse_comile_ss: 6711 case Intrinsic::x86_sse_comigt_ss: 6712 case Intrinsic::x86_sse_comige_ss: 6713 case Intrinsic::x86_sse_comineq_ss: 6714 case Intrinsic::x86_sse_ucomieq_ss: 6715 case Intrinsic::x86_sse_ucomilt_ss: 6716 case Intrinsic::x86_sse_ucomile_ss: 6717 case Intrinsic::x86_sse_ucomigt_ss: 6718 case Intrinsic::x86_sse_ucomige_ss: 6719 case Intrinsic::x86_sse_ucomineq_ss: 6720 case Intrinsic::x86_sse2_comieq_sd: 6721 case Intrinsic::x86_sse2_comilt_sd: 6722 case Intrinsic::x86_sse2_comile_sd: 6723 case Intrinsic::x86_sse2_comigt_sd: 6724 case Intrinsic::x86_sse2_comige_sd: 6725 case Intrinsic::x86_sse2_comineq_sd: 6726 case Intrinsic::x86_sse2_ucomieq_sd: 6727 case Intrinsic::x86_sse2_ucomilt_sd: 6728 case Intrinsic::x86_sse2_ucomile_sd: 6729 case Intrinsic::x86_sse2_ucomigt_sd: 6730 case Intrinsic::x86_sse2_ucomige_sd: 6731 case Intrinsic::x86_sse2_ucomineq_sd: { 6732 unsigned Opc = 0; 6733 ISD::CondCode CC = ISD::SETCC_INVALID; 6734 switch (IntNo) { 6735 default: break; 6736 case Intrinsic::x86_sse_comieq_ss: 6737 case Intrinsic::x86_sse2_comieq_sd: 6738 Opc = X86ISD::COMI; 6739 CC = ISD::SETEQ; 6740 break; 6741 case Intrinsic::x86_sse_comilt_ss: 6742 case Intrinsic::x86_sse2_comilt_sd: 6743 Opc = X86ISD::COMI; 6744 CC = ISD::SETLT; 6745 break; 6746 case Intrinsic::x86_sse_comile_ss: 6747 case Intrinsic::x86_sse2_comile_sd: 6748 Opc = X86ISD::COMI; 6749 CC = ISD::SETLE; 6750 break; 6751 case Intrinsic::x86_sse_comigt_ss: 6752 case Intrinsic::x86_sse2_comigt_sd: 6753 Opc = X86ISD::COMI; 6754 CC = ISD::SETGT; 6755 break; 6756 case Intrinsic::x86_sse_comige_ss: 6757 case Intrinsic::x86_sse2_comige_sd: 6758 Opc = X86ISD::COMI; 6759 CC = ISD::SETGE; 6760 break; 6761 case Intrinsic::x86_sse_comineq_ss: 6762 case Intrinsic::x86_sse2_comineq_sd: 6763 Opc = X86ISD::COMI; 6764 CC = ISD::SETNE; 6765 break; 6766 case Intrinsic::x86_sse_ucomieq_ss: 6767 case Intrinsic::x86_sse2_ucomieq_sd: 6768 Opc = X86ISD::UCOMI; 6769 CC = ISD::SETEQ; 6770 break; 6771 case Intrinsic::x86_sse_ucomilt_ss: 6772 case Intrinsic::x86_sse2_ucomilt_sd: 6773 Opc = X86ISD::UCOMI; 6774 CC = ISD::SETLT; 6775 break; 6776 case Intrinsic::x86_sse_ucomile_ss: 6777 case Intrinsic::x86_sse2_ucomile_sd: 6778 Opc = X86ISD::UCOMI; 6779 CC = ISD::SETLE; 6780 break; 6781 case Intrinsic::x86_sse_ucomigt_ss: 6782 case Intrinsic::x86_sse2_ucomigt_sd: 6783 Opc = X86ISD::UCOMI; 6784 CC = ISD::SETGT; 6785 break; 6786 case Intrinsic::x86_sse_ucomige_ss: 6787 case Intrinsic::x86_sse2_ucomige_sd: 6788 Opc = X86ISD::UCOMI; 6789 CC = ISD::SETGE; 6790 break; 6791 case Intrinsic::x86_sse_ucomineq_ss: 6792 case Intrinsic::x86_sse2_ucomineq_sd: 6793 Opc = X86ISD::UCOMI; 6794 CC = ISD::SETNE; 6795 break; 6796 } 6797 6798 SDValue LHS = Op.getOperand(1); 6799 SDValue RHS = Op.getOperand(2); 6800 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 6801 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 6802 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 6803 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 6804 DAG.getConstant(X86CC, MVT::i8), Cond); 6805 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6806 } 6807 // ptest intrinsics. The intrinsic these come from are designed to return 6808 // an integer value, not just an instruction so lower it to the ptest 6809 // pattern and a setcc for the result. 6810 case Intrinsic::x86_sse41_ptestz: 6811 case Intrinsic::x86_sse41_ptestc: 6812 case Intrinsic::x86_sse41_ptestnzc:{ 6813 unsigned X86CC = 0; 6814 switch (IntNo) { 6815 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 6816 case Intrinsic::x86_sse41_ptestz: 6817 // ZF = 1 6818 X86CC = X86::COND_E; 6819 break; 6820 case Intrinsic::x86_sse41_ptestc: 6821 // CF = 1 6822 X86CC = X86::COND_B; 6823 break; 6824 case Intrinsic::x86_sse41_ptestnzc: 6825 // ZF and CF = 0 6826 X86CC = X86::COND_A; 6827 break; 6828 } 6829 6830 SDValue LHS = Op.getOperand(1); 6831 SDValue RHS = Op.getOperand(2); 6832 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); 6833 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 6834 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 6835 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 6836 } 6837 6838 // Fix vector shift instructions where the last operand is a non-immediate 6839 // i32 value. 6840 case Intrinsic::x86_sse2_pslli_w: 6841 case Intrinsic::x86_sse2_pslli_d: 6842 case Intrinsic::x86_sse2_pslli_q: 6843 case Intrinsic::x86_sse2_psrli_w: 6844 case Intrinsic::x86_sse2_psrli_d: 6845 case Intrinsic::x86_sse2_psrli_q: 6846 case Intrinsic::x86_sse2_psrai_w: 6847 case Intrinsic::x86_sse2_psrai_d: 6848 case Intrinsic::x86_mmx_pslli_w: 6849 case Intrinsic::x86_mmx_pslli_d: 6850 case Intrinsic::x86_mmx_pslli_q: 6851 case Intrinsic::x86_mmx_psrli_w: 6852 case Intrinsic::x86_mmx_psrli_d: 6853 case Intrinsic::x86_mmx_psrli_q: 6854 case Intrinsic::x86_mmx_psrai_w: 6855 case Intrinsic::x86_mmx_psrai_d: { 6856 SDValue ShAmt = Op.getOperand(2); 6857 if (isa<ConstantSDNode>(ShAmt)) 6858 return SDValue(); 6859 6860 unsigned NewIntNo = 0; 6861 EVT ShAmtVT = MVT::v4i32; 6862 switch (IntNo) { 6863 case Intrinsic::x86_sse2_pslli_w: 6864 NewIntNo = Intrinsic::x86_sse2_psll_w; 6865 break; 6866 case Intrinsic::x86_sse2_pslli_d: 6867 NewIntNo = Intrinsic::x86_sse2_psll_d; 6868 break; 6869 case Intrinsic::x86_sse2_pslli_q: 6870 NewIntNo = Intrinsic::x86_sse2_psll_q; 6871 break; 6872 case Intrinsic::x86_sse2_psrli_w: 6873 NewIntNo = Intrinsic::x86_sse2_psrl_w; 6874 break; 6875 case Intrinsic::x86_sse2_psrli_d: 6876 NewIntNo = Intrinsic::x86_sse2_psrl_d; 6877 break; 6878 case Intrinsic::x86_sse2_psrli_q: 6879 NewIntNo = Intrinsic::x86_sse2_psrl_q; 6880 break; 6881 case Intrinsic::x86_sse2_psrai_w: 6882 NewIntNo = Intrinsic::x86_sse2_psra_w; 6883 break; 6884 case Intrinsic::x86_sse2_psrai_d: 6885 NewIntNo = Intrinsic::x86_sse2_psra_d; 6886 break; 6887 default: { 6888 ShAmtVT = MVT::v2i32; 6889 switch (IntNo) { 6890 case Intrinsic::x86_mmx_pslli_w: 6891 NewIntNo = Intrinsic::x86_mmx_psll_w; 6892 break; 6893 case Intrinsic::x86_mmx_pslli_d: 6894 NewIntNo = Intrinsic::x86_mmx_psll_d; 6895 break; 6896 case Intrinsic::x86_mmx_pslli_q: 6897 NewIntNo = Intrinsic::x86_mmx_psll_q; 6898 break; 6899 case Intrinsic::x86_mmx_psrli_w: 6900 NewIntNo = Intrinsic::x86_mmx_psrl_w; 6901 break; 6902 case Intrinsic::x86_mmx_psrli_d: 6903 NewIntNo = Intrinsic::x86_mmx_psrl_d; 6904 break; 6905 case Intrinsic::x86_mmx_psrli_q: 6906 NewIntNo = Intrinsic::x86_mmx_psrl_q; 6907 break; 6908 case Intrinsic::x86_mmx_psrai_w: 6909 NewIntNo = Intrinsic::x86_mmx_psra_w; 6910 break; 6911 case Intrinsic::x86_mmx_psrai_d: 6912 NewIntNo = Intrinsic::x86_mmx_psra_d; 6913 break; 6914 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 6915 } 6916 break; 6917 } 6918 } 6919 6920 // The vector shift intrinsics with scalars uses 32b shift amounts but 6921 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 6922 // to be zero. 6923 SDValue ShOps[4]; 6924 ShOps[0] = ShAmt; 6925 ShOps[1] = DAG.getConstant(0, MVT::i32); 6926 if (ShAmtVT == MVT::v4i32) { 6927 ShOps[2] = DAG.getUNDEF(MVT::i32); 6928 ShOps[3] = DAG.getUNDEF(MVT::i32); 6929 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 6930 } else { 6931 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 6932 } 6933 6934 EVT VT = Op.getValueType(); 6935 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt); 6936 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 6937 DAG.getConstant(NewIntNo, MVT::i32), 6938 Op.getOperand(1), ShAmt); 6939 } 6940 } 6941} 6942 6943SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 6944 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6945 DebugLoc dl = Op.getDebugLoc(); 6946 6947 if (Depth > 0) { 6948 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 6949 SDValue Offset = 6950 DAG.getConstant(TD->getPointerSize(), 6951 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 6952 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6953 DAG.getNode(ISD::ADD, dl, getPointerTy(), 6954 FrameAddr, Offset), 6955 NULL, 0, false, false, 0); 6956 } 6957 6958 // Just load the return address. 6959 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 6960 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 6961 RetAddrFI, NULL, 0, false, false, 0); 6962} 6963 6964SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 6965 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 6966 MFI->setFrameAddressIsTaken(true); 6967 EVT VT = Op.getValueType(); 6968 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 6969 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 6970 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 6971 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 6972 while (Depth--) 6973 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0, 6974 false, false, 0); 6975 return FrameAddr; 6976} 6977 6978SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 6979 SelectionDAG &DAG) { 6980 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 6981} 6982 6983SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 6984{ 6985 MachineFunction &MF = DAG.getMachineFunction(); 6986 SDValue Chain = Op.getOperand(0); 6987 SDValue Offset = Op.getOperand(1); 6988 SDValue Handler = Op.getOperand(2); 6989 DebugLoc dl = Op.getDebugLoc(); 6990 6991 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP, 6992 getPointerTy()); 6993 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 6994 6995 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame, 6996 DAG.getIntPtrConstant(-TD->getPointerSize())); 6997 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 6998 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0); 6999 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 7000 MF.getRegInfo().addLiveOut(StoreAddrReg); 7001 7002 return DAG.getNode(X86ISD::EH_RETURN, dl, 7003 MVT::Other, 7004 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 7005} 7006 7007SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, 7008 SelectionDAG &DAG) { 7009 SDValue Root = Op.getOperand(0); 7010 SDValue Trmp = Op.getOperand(1); // trampoline 7011 SDValue FPtr = Op.getOperand(2); // nested function 7012 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 7013 DebugLoc dl = Op.getDebugLoc(); 7014 7015 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 7016 7017 if (Subtarget->is64Bit()) { 7018 SDValue OutChains[6]; 7019 7020 // Large code-model. 7021 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 7022 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 7023 7024 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10); 7025 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11); 7026 7027 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 7028 7029 // Load the pointer to the nested function into R11. 7030 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 7031 SDValue Addr = Trmp; 7032 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7033 Addr, TrmpAddr, 0, false, false, 0); 7034 7035 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7036 DAG.getConstant(2, MVT::i64)); 7037 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, 7038 false, false, 2); 7039 7040 // Load the 'nest' parameter value into R10. 7041 // R10 is specified in X86CallingConv.td 7042 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 7043 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7044 DAG.getConstant(10, MVT::i64)); 7045 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7046 Addr, TrmpAddr, 10, false, false, 0); 7047 7048 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7049 DAG.getConstant(12, MVT::i64)); 7050 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, 7051 false, false, 2); 7052 7053 // Jump to the nested function. 7054 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 7055 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7056 DAG.getConstant(20, MVT::i64)); 7057 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 7058 Addr, TrmpAddr, 20, false, false, 0); 7059 7060 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 7061 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 7062 DAG.getConstant(22, MVT::i64)); 7063 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 7064 TrmpAddr, 22, false, false, 0); 7065 7066 SDValue Ops[] = 7067 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; 7068 return DAG.getMergeValues(Ops, 2, dl); 7069 } else { 7070 const Function *Func = 7071 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 7072 CallingConv::ID CC = Func->getCallingConv(); 7073 unsigned NestReg; 7074 7075 switch (CC) { 7076 default: 7077 llvm_unreachable("Unsupported calling convention"); 7078 case CallingConv::C: 7079 case CallingConv::X86_StdCall: { 7080 // Pass 'nest' parameter in ECX. 7081 // Must be kept in sync with X86CallingConv.td 7082 NestReg = X86::ECX; 7083 7084 // Check that ECX wasn't needed by an 'inreg' parameter. 7085 const FunctionType *FTy = Func->getFunctionType(); 7086 const AttrListPtr &Attrs = Func->getAttributes(); 7087 7088 if (!Attrs.isEmpty() && !Func->isVarArg()) { 7089 unsigned InRegCount = 0; 7090 unsigned Idx = 1; 7091 7092 for (FunctionType::param_iterator I = FTy->param_begin(), 7093 E = FTy->param_end(); I != E; ++I, ++Idx) 7094 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 7095 // FIXME: should only count parameters that are lowered to integers. 7096 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 7097 7098 if (InRegCount > 2) { 7099 llvm_report_error("Nest register in use - reduce number of inreg parameters!"); 7100 } 7101 } 7102 break; 7103 } 7104 case CallingConv::X86_FastCall: 7105 case CallingConv::Fast: 7106 // Pass 'nest' parameter in EAX. 7107 // Must be kept in sync with X86CallingConv.td 7108 NestReg = X86::EAX; 7109 break; 7110 } 7111 7112 SDValue OutChains[4]; 7113 SDValue Addr, Disp; 7114 7115 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7116 DAG.getConstant(10, MVT::i32)); 7117 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 7118 7119 // This is storing the opcode for MOV32ri. 7120 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 7121 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); 7122 OutChains[0] = DAG.getStore(Root, dl, 7123 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 7124 Trmp, TrmpAddr, 0, false, false, 0); 7125 7126 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7127 DAG.getConstant(1, MVT::i32)); 7128 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, 7129 false, false, 1); 7130 7131 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 7132 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7133 DAG.getConstant(5, MVT::i32)); 7134 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 7135 TrmpAddr, 5, false, false, 1); 7136 7137 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 7138 DAG.getConstant(6, MVT::i32)); 7139 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, 7140 false, false, 1); 7141 7142 SDValue Ops[] = 7143 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; 7144 return DAG.getMergeValues(Ops, 2, dl); 7145 } 7146} 7147 7148SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { 7149 /* 7150 The rounding mode is in bits 11:10 of FPSR, and has the following 7151 settings: 7152 00 Round to nearest 7153 01 Round to -inf 7154 10 Round to +inf 7155 11 Round to 0 7156 7157 FLT_ROUNDS, on the other hand, expects the following: 7158 -1 Undefined 7159 0 Round to 0 7160 1 Round to nearest 7161 2 Round to +inf 7162 3 Round to -inf 7163 7164 To perform the conversion, we do: 7165 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 7166 */ 7167 7168 MachineFunction &MF = DAG.getMachineFunction(); 7169 const TargetMachine &TM = MF.getTarget(); 7170 const TargetFrameInfo &TFI = *TM.getFrameInfo(); 7171 unsigned StackAlignment = TFI.getStackAlignment(); 7172 EVT VT = Op.getValueType(); 7173 DebugLoc dl = Op.getDebugLoc(); 7174 7175 // Save FP Control Word to stack slot 7176 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 7177 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7178 7179 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, 7180 DAG.getEntryNode(), StackSlot); 7181 7182 // Load FP Control Word from stack slot 7183 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0, 7184 false, false, 0); 7185 7186 // Transform as necessary 7187 SDValue CWD1 = 7188 DAG.getNode(ISD::SRL, dl, MVT::i16, 7189 DAG.getNode(ISD::AND, dl, MVT::i16, 7190 CWD, DAG.getConstant(0x800, MVT::i16)), 7191 DAG.getConstant(11, MVT::i8)); 7192 SDValue CWD2 = 7193 DAG.getNode(ISD::SRL, dl, MVT::i16, 7194 DAG.getNode(ISD::AND, dl, MVT::i16, 7195 CWD, DAG.getConstant(0x400, MVT::i16)), 7196 DAG.getConstant(9, MVT::i8)); 7197 7198 SDValue RetVal = 7199 DAG.getNode(ISD::AND, dl, MVT::i16, 7200 DAG.getNode(ISD::ADD, dl, MVT::i16, 7201 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), 7202 DAG.getConstant(1, MVT::i16)), 7203 DAG.getConstant(3, MVT::i16)); 7204 7205 7206 return DAG.getNode((VT.getSizeInBits() < 16 ? 7207 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 7208} 7209 7210SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { 7211 EVT VT = Op.getValueType(); 7212 EVT OpVT = VT; 7213 unsigned NumBits = VT.getSizeInBits(); 7214 DebugLoc dl = Op.getDebugLoc(); 7215 7216 Op = Op.getOperand(0); 7217 if (VT == MVT::i8) { 7218 // Zero extend to i32 since there is not an i8 bsr. 7219 OpVT = MVT::i32; 7220 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7221 } 7222 7223 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 7224 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7225 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 7226 7227 // If src is zero (i.e. bsr sets ZF), returns NumBits. 7228 SDValue Ops[] = { 7229 Op, 7230 DAG.getConstant(NumBits+NumBits-1, OpVT), 7231 DAG.getConstant(X86::COND_E, MVT::i8), 7232 Op.getValue(1) 7233 }; 7234 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7235 7236 // Finally xor with NumBits-1. 7237 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 7238 7239 if (VT == MVT::i8) 7240 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7241 return Op; 7242} 7243 7244SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { 7245 EVT VT = Op.getValueType(); 7246 EVT OpVT = VT; 7247 unsigned NumBits = VT.getSizeInBits(); 7248 DebugLoc dl = Op.getDebugLoc(); 7249 7250 Op = Op.getOperand(0); 7251 if (VT == MVT::i8) { 7252 OpVT = MVT::i32; 7253 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 7254 } 7255 7256 // Issue a bsf (scan bits forward) which also sets EFLAGS. 7257 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 7258 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 7259 7260 // If src is zero (i.e. bsf sets ZF), returns NumBits. 7261 SDValue Ops[] = { 7262 Op, 7263 DAG.getConstant(NumBits, OpVT), 7264 DAG.getConstant(X86::COND_E, MVT::i8), 7265 Op.getValue(1) 7266 }; 7267 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 7268 7269 if (VT == MVT::i8) 7270 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 7271 return Op; 7272} 7273 7274SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { 7275 EVT VT = Op.getValueType(); 7276 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 7277 DebugLoc dl = Op.getDebugLoc(); 7278 7279 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 7280 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 7281 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 7282 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 7283 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 7284 // 7285 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 7286 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 7287 // return AloBlo + AloBhi + AhiBlo; 7288 7289 SDValue A = Op.getOperand(0); 7290 SDValue B = Op.getOperand(1); 7291 7292 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7293 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7294 A, DAG.getConstant(32, MVT::i32)); 7295 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7296 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 7297 B, DAG.getConstant(32, MVT::i32)); 7298 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7299 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7300 A, B); 7301 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7302 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7303 A, Bhi); 7304 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7305 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 7306 Ahi, B); 7307 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7308 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7309 AloBhi, DAG.getConstant(32, MVT::i32)); 7310 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 7311 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 7312 AhiBlo, DAG.getConstant(32, MVT::i32)); 7313 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 7314 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 7315 return Res; 7316} 7317 7318 7319SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { 7320 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 7321 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 7322 // looks for this combo and may remove the "setcc" instruction if the "setcc" 7323 // has only one use. 7324 SDNode *N = Op.getNode(); 7325 SDValue LHS = N->getOperand(0); 7326 SDValue RHS = N->getOperand(1); 7327 unsigned BaseOp = 0; 7328 unsigned Cond = 0; 7329 DebugLoc dl = Op.getDebugLoc(); 7330 7331 switch (Op.getOpcode()) { 7332 default: llvm_unreachable("Unknown ovf instruction!"); 7333 case ISD::SADDO: 7334 // A subtract of one will be selected as a INC. Note that INC doesn't 7335 // set CF, so we can't do this for UADDO. 7336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7337 if (C->getAPIntValue() == 1) { 7338 BaseOp = X86ISD::INC; 7339 Cond = X86::COND_O; 7340 break; 7341 } 7342 BaseOp = X86ISD::ADD; 7343 Cond = X86::COND_O; 7344 break; 7345 case ISD::UADDO: 7346 BaseOp = X86ISD::ADD; 7347 Cond = X86::COND_B; 7348 break; 7349 case ISD::SSUBO: 7350 // A subtract of one will be selected as a DEC. Note that DEC doesn't 7351 // set CF, so we can't do this for USUBO. 7352 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) 7353 if (C->getAPIntValue() == 1) { 7354 BaseOp = X86ISD::DEC; 7355 Cond = X86::COND_O; 7356 break; 7357 } 7358 BaseOp = X86ISD::SUB; 7359 Cond = X86::COND_O; 7360 break; 7361 case ISD::USUBO: 7362 BaseOp = X86ISD::SUB; 7363 Cond = X86::COND_B; 7364 break; 7365 case ISD::SMULO: 7366 BaseOp = X86ISD::SMUL; 7367 Cond = X86::COND_O; 7368 break; 7369 case ISD::UMULO: 7370 BaseOp = X86ISD::UMUL; 7371 Cond = X86::COND_B; 7372 break; 7373 } 7374 7375 // Also sets EFLAGS. 7376 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 7377 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); 7378 7379 SDValue SetCC = 7380 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), 7381 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); 7382 7383 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); 7384 return Sum; 7385} 7386 7387SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { 7388 EVT T = Op.getValueType(); 7389 DebugLoc dl = Op.getDebugLoc(); 7390 unsigned Reg = 0; 7391 unsigned size = 0; 7392 switch(T.getSimpleVT().SimpleTy) { 7393 default: 7394 assert(false && "Invalid value type!"); 7395 case MVT::i8: Reg = X86::AL; size = 1; break; 7396 case MVT::i16: Reg = X86::AX; size = 2; break; 7397 case MVT::i32: Reg = X86::EAX; size = 4; break; 7398 case MVT::i64: 7399 assert(Subtarget->is64Bit() && "Node not type legal!"); 7400 Reg = X86::RAX; size = 8; 7401 break; 7402 } 7403 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg, 7404 Op.getOperand(2), SDValue()); 7405 SDValue Ops[] = { cpIn.getValue(0), 7406 Op.getOperand(1), 7407 Op.getOperand(3), 7408 DAG.getTargetConstant(size, MVT::i8), 7409 cpIn.getValue(1) }; 7410 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7411 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); 7412 SDValue cpOut = 7413 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); 7414 return cpOut; 7415} 7416 7417SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 7418 SelectionDAG &DAG) { 7419 assert(Subtarget->is64Bit() && "Result not type legalized?"); 7420 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7421 SDValue TheChain = Op.getOperand(0); 7422 DebugLoc dl = Op.getDebugLoc(); 7423 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7424 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 7425 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 7426 rax.getValue(2)); 7427 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 7428 DAG.getConstant(32, MVT::i8)); 7429 SDValue Ops[] = { 7430 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 7431 rdx.getValue(1) 7432 }; 7433 return DAG.getMergeValues(Ops, 2, dl); 7434} 7435 7436SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { 7437 SDNode *Node = Op.getNode(); 7438 DebugLoc dl = Node->getDebugLoc(); 7439 EVT T = Node->getValueType(0); 7440 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 7441 DAG.getConstant(0, T), Node->getOperand(2)); 7442 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 7443 cast<AtomicSDNode>(Node)->getMemoryVT(), 7444 Node->getOperand(0), 7445 Node->getOperand(1), negOp, 7446 cast<AtomicSDNode>(Node)->getSrcValue(), 7447 cast<AtomicSDNode>(Node)->getAlignment()); 7448} 7449 7450/// LowerOperation - Provide custom lowering hooks for some operations. 7451/// 7452SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 7453 switch (Op.getOpcode()) { 7454 default: llvm_unreachable("Should not custom lower this!"); 7455 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 7456 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 7457 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 7458 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 7459 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 7460 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 7461 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 7462 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 7463 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 7464 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 7465 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 7466 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 7467 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 7468 case ISD::SHL_PARTS: 7469 case ISD::SRA_PARTS: 7470 case ISD::SRL_PARTS: return LowerShift(Op, DAG); 7471 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 7472 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 7473 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 7474 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 7475 case ISD::FABS: return LowerFABS(Op, DAG); 7476 case ISD::FNEG: return LowerFNEG(Op, DAG); 7477 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 7478 case ISD::SETCC: return LowerSETCC(Op, DAG); 7479 case ISD::VSETCC: return LowerVSETCC(Op, DAG); 7480 case ISD::SELECT: return LowerSELECT(Op, DAG); 7481 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 7482 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 7483 case ISD::VASTART: return LowerVASTART(Op, DAG); 7484 case ISD::VAARG: return LowerVAARG(Op, DAG); 7485 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 7486 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 7487 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 7488 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 7489 case ISD::FRAME_TO_ARGS_OFFSET: 7490 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 7491 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 7492 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 7493 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 7494 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 7495 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 7496 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 7497 case ISD::MUL: return LowerMUL_V2I64(Op, DAG); 7498 case ISD::SADDO: 7499 case ISD::UADDO: 7500 case ISD::SSUBO: 7501 case ISD::USUBO: 7502 case ISD::SMULO: 7503 case ISD::UMULO: return LowerXALUO(Op, DAG); 7504 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 7505 } 7506} 7507 7508void X86TargetLowering:: 7509ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 7510 SelectionDAG &DAG, unsigned NewOp) { 7511 EVT T = Node->getValueType(0); 7512 DebugLoc dl = Node->getDebugLoc(); 7513 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 7514 7515 SDValue Chain = Node->getOperand(0); 7516 SDValue In1 = Node->getOperand(1); 7517 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7518 Node->getOperand(2), DAG.getIntPtrConstant(0)); 7519 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7520 Node->getOperand(2), DAG.getIntPtrConstant(1)); 7521 SDValue Ops[] = { Chain, In1, In2L, In2H }; 7522 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 7523 SDValue Result = 7524 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 7525 cast<MemSDNode>(Node)->getMemOperand()); 7526 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 7527 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7528 Results.push_back(Result.getValue(2)); 7529} 7530 7531/// ReplaceNodeResults - Replace a node with an illegal result type 7532/// with a new node built out of custom code. 7533void X86TargetLowering::ReplaceNodeResults(SDNode *N, 7534 SmallVectorImpl<SDValue>&Results, 7535 SelectionDAG &DAG) { 7536 DebugLoc dl = N->getDebugLoc(); 7537 switch (N->getOpcode()) { 7538 default: 7539 assert(false && "Do not know how to custom type legalize this operation!"); 7540 return; 7541 case ISD::FP_TO_SINT: { 7542 std::pair<SDValue,SDValue> Vals = 7543 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 7544 SDValue FIST = Vals.first, StackSlot = Vals.second; 7545 if (FIST.getNode() != 0) { 7546 EVT VT = N->getValueType(0); 7547 // Return a load from the stack slot. 7548 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0, 7549 false, false, 0)); 7550 } 7551 return; 7552 } 7553 case ISD::READCYCLECOUNTER: { 7554 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7555 SDValue TheChain = N->getOperand(0); 7556 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 7557 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 7558 rd.getValue(1)); 7559 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 7560 eax.getValue(2)); 7561 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 7562 SDValue Ops[] = { eax, edx }; 7563 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 7564 Results.push_back(edx.getValue(1)); 7565 return; 7566 } 7567 case ISD::ATOMIC_CMP_SWAP: { 7568 EVT T = N->getValueType(0); 7569 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); 7570 SDValue cpInL, cpInH; 7571 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7572 DAG.getConstant(0, MVT::i32)); 7573 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), 7574 DAG.getConstant(1, MVT::i32)); 7575 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); 7576 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, 7577 cpInL.getValue(1)); 7578 SDValue swapInL, swapInH; 7579 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7580 DAG.getConstant(0, MVT::i32)); 7581 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), 7582 DAG.getConstant(1, MVT::i32)); 7583 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, 7584 cpInH.getValue(1)); 7585 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, 7586 swapInL.getValue(1)); 7587 SDValue Ops[] = { swapInH.getValue(0), 7588 N->getOperand(1), 7589 swapInH.getValue(1) }; 7590 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); 7591 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); 7592 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, 7593 MVT::i32, Result.getValue(1)); 7594 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, 7595 MVT::i32, cpOutL.getValue(2)); 7596 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 7597 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 7598 Results.push_back(cpOutH.getValue(1)); 7599 return; 7600 } 7601 case ISD::ATOMIC_LOAD_ADD: 7602 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 7603 return; 7604 case ISD::ATOMIC_LOAD_AND: 7605 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 7606 return; 7607 case ISD::ATOMIC_LOAD_NAND: 7608 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 7609 return; 7610 case ISD::ATOMIC_LOAD_OR: 7611 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 7612 return; 7613 case ISD::ATOMIC_LOAD_SUB: 7614 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 7615 return; 7616 case ISD::ATOMIC_LOAD_XOR: 7617 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 7618 return; 7619 case ISD::ATOMIC_SWAP: 7620 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 7621 return; 7622 } 7623} 7624 7625const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 7626 switch (Opcode) { 7627 default: return NULL; 7628 case X86ISD::BSF: return "X86ISD::BSF"; 7629 case X86ISD::BSR: return "X86ISD::BSR"; 7630 case X86ISD::SHLD: return "X86ISD::SHLD"; 7631 case X86ISD::SHRD: return "X86ISD::SHRD"; 7632 case X86ISD::FAND: return "X86ISD::FAND"; 7633 case X86ISD::FOR: return "X86ISD::FOR"; 7634 case X86ISD::FXOR: return "X86ISD::FXOR"; 7635 case X86ISD::FSRL: return "X86ISD::FSRL"; 7636 case X86ISD::FILD: return "X86ISD::FILD"; 7637 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 7638 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 7639 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 7640 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 7641 case X86ISD::FLD: return "X86ISD::FLD"; 7642 case X86ISD::FST: return "X86ISD::FST"; 7643 case X86ISD::CALL: return "X86ISD::CALL"; 7644 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 7645 case X86ISD::BT: return "X86ISD::BT"; 7646 case X86ISD::CMP: return "X86ISD::CMP"; 7647 case X86ISD::COMI: return "X86ISD::COMI"; 7648 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 7649 case X86ISD::SETCC: return "X86ISD::SETCC"; 7650 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 7651 case X86ISD::CMOV: return "X86ISD::CMOV"; 7652 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 7653 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 7654 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 7655 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 7656 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 7657 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 7658 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 7659 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 7660 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 7661 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 7662 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 7663 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 7664 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 7665 case X86ISD::FMAX: return "X86ISD::FMAX"; 7666 case X86ISD::FMIN: return "X86ISD::FMIN"; 7667 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 7668 case X86ISD::FRCP: return "X86ISD::FRCP"; 7669 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 7670 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress"; 7671 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 7672 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 7673 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 7674 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 7675 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 7676 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 7677 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 7678 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 7679 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 7680 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 7681 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 7682 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 7683 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 7684 case X86ISD::VSHL: return "X86ISD::VSHL"; 7685 case X86ISD::VSRL: return "X86ISD::VSRL"; 7686 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 7687 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 7688 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 7689 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 7690 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 7691 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 7692 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 7693 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 7694 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 7695 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 7696 case X86ISD::ADD: return "X86ISD::ADD"; 7697 case X86ISD::SUB: return "X86ISD::SUB"; 7698 case X86ISD::SMUL: return "X86ISD::SMUL"; 7699 case X86ISD::UMUL: return "X86ISD::UMUL"; 7700 case X86ISD::INC: return "X86ISD::INC"; 7701 case X86ISD::DEC: return "X86ISD::DEC"; 7702 case X86ISD::OR: return "X86ISD::OR"; 7703 case X86ISD::XOR: return "X86ISD::XOR"; 7704 case X86ISD::AND: return "X86ISD::AND"; 7705 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 7706 case X86ISD::PTEST: return "X86ISD::PTEST"; 7707 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 7708 } 7709} 7710 7711// isLegalAddressingMode - Return true if the addressing mode represented 7712// by AM is legal for this target, for a load/store of the specified type. 7713bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 7714 const Type *Ty) const { 7715 // X86 supports extremely general addressing modes. 7716 CodeModel::Model M = getTargetMachine().getCodeModel(); 7717 7718 // X86 allows a sign-extended 32-bit immediate field as a displacement. 7719 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 7720 return false; 7721 7722 if (AM.BaseGV) { 7723 unsigned GVFlags = 7724 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 7725 7726 // If a reference to this global requires an extra load, we can't fold it. 7727 if (isGlobalStubReference(GVFlags)) 7728 return false; 7729 7730 // If BaseGV requires a register for the PIC base, we cannot also have a 7731 // BaseReg specified. 7732 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 7733 return false; 7734 7735 // If lower 4G is not available, then we must use rip-relative addressing. 7736 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 7737 return false; 7738 } 7739 7740 switch (AM.Scale) { 7741 case 0: 7742 case 1: 7743 case 2: 7744 case 4: 7745 case 8: 7746 // These scales always work. 7747 break; 7748 case 3: 7749 case 5: 7750 case 9: 7751 // These scales are formed with basereg+scalereg. Only accept if there is 7752 // no basereg yet. 7753 if (AM.HasBaseReg) 7754 return false; 7755 break; 7756 default: // Other stuff never works. 7757 return false; 7758 } 7759 7760 return true; 7761} 7762 7763 7764bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { 7765 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 7766 return false; 7767 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 7768 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 7769 if (NumBits1 <= NumBits2) 7770 return false; 7771 return Subtarget->is64Bit() || NumBits1 < 64; 7772} 7773 7774bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 7775 if (!VT1.isInteger() || !VT2.isInteger()) 7776 return false; 7777 unsigned NumBits1 = VT1.getSizeInBits(); 7778 unsigned NumBits2 = VT2.getSizeInBits(); 7779 if (NumBits1 <= NumBits2) 7780 return false; 7781 return Subtarget->is64Bit() || NumBits1 < 64; 7782} 7783 7784bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { 7785 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7786 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 7787} 7788 7789bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 7790 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 7791 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 7792} 7793 7794bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 7795 // i16 instructions are longer (0x66 prefix) and potentially slower. 7796 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 7797} 7798 7799/// isShuffleMaskLegal - Targets can use this to indicate that they only 7800/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 7801/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 7802/// are assumed to be legal. 7803bool 7804X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 7805 EVT VT) const { 7806 // Only do shuffles on 128-bit vector types for now. 7807 if (VT.getSizeInBits() == 64) 7808 return false; 7809 7810 // FIXME: pshufb, blends, shifts. 7811 return (VT.getVectorNumElements() == 2 || 7812 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 7813 isMOVLMask(M, VT) || 7814 isSHUFPMask(M, VT) || 7815 isPSHUFDMask(M, VT) || 7816 isPSHUFHWMask(M, VT) || 7817 isPSHUFLWMask(M, VT) || 7818 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || 7819 isUNPCKLMask(M, VT) || 7820 isUNPCKHMask(M, VT) || 7821 isUNPCKL_v_undef_Mask(M, VT) || 7822 isUNPCKH_v_undef_Mask(M, VT)); 7823} 7824 7825bool 7826X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 7827 EVT VT) const { 7828 unsigned NumElts = VT.getVectorNumElements(); 7829 // FIXME: This collection of masks seems suspect. 7830 if (NumElts == 2) 7831 return true; 7832 if (NumElts == 4 && VT.getSizeInBits() == 128) { 7833 return (isMOVLMask(Mask, VT) || 7834 isCommutedMOVLMask(Mask, VT, true) || 7835 isSHUFPMask(Mask, VT) || 7836 isCommutedSHUFPMask(Mask, VT)); 7837 } 7838 return false; 7839} 7840 7841//===----------------------------------------------------------------------===// 7842// X86 Scheduler Hooks 7843//===----------------------------------------------------------------------===// 7844 7845// private utility function 7846MachineBasicBlock * 7847X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 7848 MachineBasicBlock *MBB, 7849 unsigned regOpc, 7850 unsigned immOpc, 7851 unsigned LoadOpc, 7852 unsigned CXchgOpc, 7853 unsigned copyOpc, 7854 unsigned notOpc, 7855 unsigned EAXreg, 7856 TargetRegisterClass *RC, 7857 bool invSrc) const { 7858 // For the atomic bitwise operator, we generate 7859 // thisMBB: 7860 // newMBB: 7861 // ld t1 = [bitinstr.addr] 7862 // op t2 = t1, [bitinstr.val] 7863 // mov EAX = t1 7864 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 7865 // bz newMBB 7866 // fallthrough -->nextMBB 7867 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7868 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7869 MachineFunction::iterator MBBIter = MBB; 7870 ++MBBIter; 7871 7872 /// First build the CFG 7873 MachineFunction *F = MBB->getParent(); 7874 MachineBasicBlock *thisMBB = MBB; 7875 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7876 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7877 F->insert(MBBIter, newMBB); 7878 F->insert(MBBIter, nextMBB); 7879 7880 // Move all successors to thisMBB to nextMBB 7881 nextMBB->transferSuccessors(thisMBB); 7882 7883 // Update thisMBB to fall through to newMBB 7884 thisMBB->addSuccessor(newMBB); 7885 7886 // newMBB jumps to itself and fall through to nextMBB 7887 newMBB->addSuccessor(nextMBB); 7888 newMBB->addSuccessor(newMBB); 7889 7890 // Insert instructions into newMBB based on incoming instruction 7891 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && 7892 "unexpected number of operands"); 7893 DebugLoc dl = bInstr->getDebugLoc(); 7894 MachineOperand& destOper = bInstr->getOperand(0); 7895 MachineOperand* argOpers[2 + X86AddrNumOperands]; 7896 int numArgs = bInstr->getNumOperands() - 1; 7897 for (int i=0; i < numArgs; ++i) 7898 argOpers[i] = &bInstr->getOperand(i+1); 7899 7900 // x86 address has 4 operands: base, index, scale, and displacement 7901 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 7902 int valArgIndx = lastAddrIndx + 1; 7903 7904 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 7905 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 7906 for (int i=0; i <= lastAddrIndx; ++i) 7907 (*MIB).addOperand(*argOpers[i]); 7908 7909 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 7910 if (invSrc) { 7911 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 7912 } 7913 else 7914 tt = t1; 7915 7916 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 7917 assert((argOpers[valArgIndx]->isReg() || 7918 argOpers[valArgIndx]->isImm()) && 7919 "invalid operand"); 7920 if (argOpers[valArgIndx]->isReg()) 7921 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 7922 else 7923 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 7924 MIB.addReg(tt); 7925 (*MIB).addOperand(*argOpers[valArgIndx]); 7926 7927 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); 7928 MIB.addReg(t1); 7929 7930 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 7931 for (int i=0; i <= lastAddrIndx; ++i) 7932 (*MIB).addOperand(*argOpers[i]); 7933 MIB.addReg(t2); 7934 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 7935 (*MIB).setMemRefs(bInstr->memoperands_begin(), 7936 bInstr->memoperands_end()); 7937 7938 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); 7939 MIB.addReg(EAXreg); 7940 7941 // insert branch 7942 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 7943 7944 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 7945 return nextMBB; 7946} 7947 7948// private utility function: 64 bit atomics on 32 bit host. 7949MachineBasicBlock * 7950X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 7951 MachineBasicBlock *MBB, 7952 unsigned regOpcL, 7953 unsigned regOpcH, 7954 unsigned immOpcL, 7955 unsigned immOpcH, 7956 bool invSrc) const { 7957 // For the atomic bitwise operator, we generate 7958 // thisMBB (instructions are in pairs, except cmpxchg8b) 7959 // ld t1,t2 = [bitinstr.addr] 7960 // newMBB: 7961 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 7962 // op t5, t6 <- out1, out2, [bitinstr.val] 7963 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 7964 // mov ECX, EBX <- t5, t6 7965 // mov EAX, EDX <- t1, t2 7966 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 7967 // mov t3, t4 <- EAX, EDX 7968 // bz newMBB 7969 // result in out1, out2 7970 // fallthrough -->nextMBB 7971 7972 const TargetRegisterClass *RC = X86::GR32RegisterClass; 7973 const unsigned LoadOpc = X86::MOV32rm; 7974 const unsigned copyOpc = X86::MOV32rr; 7975 const unsigned NotOpc = X86::NOT32r; 7976 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 7977 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 7978 MachineFunction::iterator MBBIter = MBB; 7979 ++MBBIter; 7980 7981 /// First build the CFG 7982 MachineFunction *F = MBB->getParent(); 7983 MachineBasicBlock *thisMBB = MBB; 7984 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 7985 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 7986 F->insert(MBBIter, newMBB); 7987 F->insert(MBBIter, nextMBB); 7988 7989 // Move all successors to thisMBB to nextMBB 7990 nextMBB->transferSuccessors(thisMBB); 7991 7992 // Update thisMBB to fall through to newMBB 7993 thisMBB->addSuccessor(newMBB); 7994 7995 // newMBB jumps to itself and fall through to nextMBB 7996 newMBB->addSuccessor(nextMBB); 7997 newMBB->addSuccessor(newMBB); 7998 7999 DebugLoc dl = bInstr->getDebugLoc(); 8000 // Insert instructions into newMBB based on incoming instruction 8001 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 8002 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && 8003 "unexpected number of operands"); 8004 MachineOperand& dest1Oper = bInstr->getOperand(0); 8005 MachineOperand& dest2Oper = bInstr->getOperand(1); 8006 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8007 for (int i=0; i < 2 + X86AddrNumOperands; ++i) 8008 argOpers[i] = &bInstr->getOperand(i+2); 8009 8010 // x86 address has 5 operands: base, index, scale, displacement, and segment. 8011 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8012 8013 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 8014 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 8015 for (int i=0; i <= lastAddrIndx; ++i) 8016 (*MIB).addOperand(*argOpers[i]); 8017 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 8018 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 8019 // add 4 to displacement. 8020 for (int i=0; i <= lastAddrIndx-2; ++i) 8021 (*MIB).addOperand(*argOpers[i]); 8022 MachineOperand newOp3 = *(argOpers[3]); 8023 if (newOp3.isImm()) 8024 newOp3.setImm(newOp3.getImm()+4); 8025 else 8026 newOp3.setOffset(newOp3.getOffset()+4); 8027 (*MIB).addOperand(newOp3); 8028 (*MIB).addOperand(*argOpers[lastAddrIndx]); 8029 8030 // t3/4 are defined later, at the bottom of the loop 8031 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 8032 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 8033 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 8034 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 8035 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 8036 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 8037 8038 // The subsequent operations should be using the destination registers of 8039 //the PHI instructions. 8040 if (invSrc) { 8041 t1 = F->getRegInfo().createVirtualRegister(RC); 8042 t2 = F->getRegInfo().createVirtualRegister(RC); 8043 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 8044 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 8045 } else { 8046 t1 = dest1Oper.getReg(); 8047 t2 = dest2Oper.getReg(); 8048 } 8049 8050 int valArgIndx = lastAddrIndx + 1; 8051 assert((argOpers[valArgIndx]->isReg() || 8052 argOpers[valArgIndx]->isImm()) && 8053 "invalid operand"); 8054 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 8055 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 8056 if (argOpers[valArgIndx]->isReg()) 8057 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 8058 else 8059 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 8060 if (regOpcL != X86::MOV32rr) 8061 MIB.addReg(t1); 8062 (*MIB).addOperand(*argOpers[valArgIndx]); 8063 assert(argOpers[valArgIndx + 1]->isReg() == 8064 argOpers[valArgIndx]->isReg()); 8065 assert(argOpers[valArgIndx + 1]->isImm() == 8066 argOpers[valArgIndx]->isImm()); 8067 if (argOpers[valArgIndx + 1]->isReg()) 8068 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 8069 else 8070 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 8071 if (regOpcH != X86::MOV32rr) 8072 MIB.addReg(t2); 8073 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 8074 8075 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); 8076 MIB.addReg(t1); 8077 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); 8078 MIB.addReg(t2); 8079 8080 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); 8081 MIB.addReg(t5); 8082 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); 8083 MIB.addReg(t6); 8084 8085 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 8086 for (int i=0; i <= lastAddrIndx; ++i) 8087 (*MIB).addOperand(*argOpers[i]); 8088 8089 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8090 (*MIB).setMemRefs(bInstr->memoperands_begin(), 8091 bInstr->memoperands_end()); 8092 8093 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); 8094 MIB.addReg(X86::EAX); 8095 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); 8096 MIB.addReg(X86::EDX); 8097 8098 // insert branch 8099 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8100 8101 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. 8102 return nextMBB; 8103} 8104 8105// private utility function 8106MachineBasicBlock * 8107X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 8108 MachineBasicBlock *MBB, 8109 unsigned cmovOpc) const { 8110 // For the atomic min/max operator, we generate 8111 // thisMBB: 8112 // newMBB: 8113 // ld t1 = [min/max.addr] 8114 // mov t2 = [min/max.val] 8115 // cmp t1, t2 8116 // cmov[cond] t2 = t1 8117 // mov EAX = t1 8118 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 8119 // bz newMBB 8120 // fallthrough -->nextMBB 8121 // 8122 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8123 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8124 MachineFunction::iterator MBBIter = MBB; 8125 ++MBBIter; 8126 8127 /// First build the CFG 8128 MachineFunction *F = MBB->getParent(); 8129 MachineBasicBlock *thisMBB = MBB; 8130 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 8131 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 8132 F->insert(MBBIter, newMBB); 8133 F->insert(MBBIter, nextMBB); 8134 8135 // Move all successors of thisMBB to nextMBB 8136 nextMBB->transferSuccessors(thisMBB); 8137 8138 // Update thisMBB to fall through to newMBB 8139 thisMBB->addSuccessor(newMBB); 8140 8141 // newMBB jumps to newMBB and fall through to nextMBB 8142 newMBB->addSuccessor(nextMBB); 8143 newMBB->addSuccessor(newMBB); 8144 8145 DebugLoc dl = mInstr->getDebugLoc(); 8146 // Insert instructions into newMBB based on incoming instruction 8147 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && 8148 "unexpected number of operands"); 8149 MachineOperand& destOper = mInstr->getOperand(0); 8150 MachineOperand* argOpers[2 + X86AddrNumOperands]; 8151 int numArgs = mInstr->getNumOperands() - 1; 8152 for (int i=0; i < numArgs; ++i) 8153 argOpers[i] = &mInstr->getOperand(i+1); 8154 8155 // x86 address has 4 operands: base, index, scale, and displacement 8156 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3] 8157 int valArgIndx = lastAddrIndx + 1; 8158 8159 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8160 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 8161 for (int i=0; i <= lastAddrIndx; ++i) 8162 (*MIB).addOperand(*argOpers[i]); 8163 8164 // We only support register and immediate values 8165 assert((argOpers[valArgIndx]->isReg() || 8166 argOpers[valArgIndx]->isImm()) && 8167 "invalid operand"); 8168 8169 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8170 if (argOpers[valArgIndx]->isReg()) 8171 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8172 else 8173 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 8174 (*MIB).addOperand(*argOpers[valArgIndx]); 8175 8176 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); 8177 MIB.addReg(t1); 8178 8179 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 8180 MIB.addReg(t1); 8181 MIB.addReg(t2); 8182 8183 // Generate movc 8184 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 8185 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 8186 MIB.addReg(t2); 8187 MIB.addReg(t1); 8188 8189 // Cmp and exchange if none has modified the memory location 8190 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 8191 for (int i=0; i <= lastAddrIndx; ++i) 8192 (*MIB).addOperand(*argOpers[i]); 8193 MIB.addReg(t3); 8194 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 8195 (*MIB).setMemRefs(mInstr->memoperands_begin(), 8196 mInstr->memoperands_end()); 8197 8198 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); 8199 MIB.addReg(X86::EAX); 8200 8201 // insert branch 8202 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 8203 8204 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. 8205 return nextMBB; 8206} 8207 8208// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 8209// all of this code can be replaced with that in the .td file. 8210MachineBasicBlock * 8211X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 8212 unsigned numArgs, bool memArg) const { 8213 8214 MachineFunction *F = BB->getParent(); 8215 DebugLoc dl = MI->getDebugLoc(); 8216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8217 8218 unsigned Opc; 8219 if (memArg) 8220 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 8221 else 8222 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 8223 8224 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc)); 8225 8226 for (unsigned i = 0; i < numArgs; ++i) { 8227 MachineOperand &Op = MI->getOperand(i+1); 8228 8229 if (!(Op.isReg() && Op.isImplicit())) 8230 MIB.addOperand(Op); 8231 } 8232 8233 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) 8234 .addReg(X86::XMM0); 8235 8236 F->DeleteMachineInstr(MI); 8237 8238 return BB; 8239} 8240 8241MachineBasicBlock * 8242X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 8243 MachineInstr *MI, 8244 MachineBasicBlock *MBB) const { 8245 // Emit code to save XMM registers to the stack. The ABI says that the 8246 // number of registers to save is given in %al, so it's theoretically 8247 // possible to do an indirect jump trick to avoid saving all of them, 8248 // however this code takes a simpler approach and just executes all 8249 // of the stores if %al is non-zero. It's less code, and it's probably 8250 // easier on the hardware branch predictor, and stores aren't all that 8251 // expensive anyway. 8252 8253 // Create the new basic blocks. One block contains all the XMM stores, 8254 // and one block is the final destination regardless of whether any 8255 // stores were performed. 8256 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 8257 MachineFunction *F = MBB->getParent(); 8258 MachineFunction::iterator MBBIter = MBB; 8259 ++MBBIter; 8260 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 8261 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 8262 F->insert(MBBIter, XMMSaveMBB); 8263 F->insert(MBBIter, EndMBB); 8264 8265 // Set up the CFG. 8266 // Move any original successors of MBB to the end block. 8267 EndMBB->transferSuccessors(MBB); 8268 // The original block will now fall through to the XMM save block. 8269 MBB->addSuccessor(XMMSaveMBB); 8270 // The XMMSaveMBB will fall through to the end block. 8271 XMMSaveMBB->addSuccessor(EndMBB); 8272 8273 // Now add the instructions. 8274 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8275 DebugLoc DL = MI->getDebugLoc(); 8276 8277 unsigned CountReg = MI->getOperand(0).getReg(); 8278 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 8279 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 8280 8281 if (!Subtarget->isTargetWin64()) { 8282 // If %al is 0, branch around the XMM save block. 8283 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 8284 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 8285 MBB->addSuccessor(EndMBB); 8286 } 8287 8288 // In the XMM save block, save all the XMM argument registers. 8289 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 8290 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 8291 MachineMemOperand *MMO = 8292 F->getMachineMemOperand( 8293 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 8294 MachineMemOperand::MOStore, Offset, 8295 /*Size=*/16, /*Align=*/16); 8296 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr)) 8297 .addFrameIndex(RegSaveFrameIndex) 8298 .addImm(/*Scale=*/1) 8299 .addReg(/*IndexReg=*/0) 8300 .addImm(/*Disp=*/Offset) 8301 .addReg(/*Segment=*/0) 8302 .addReg(MI->getOperand(i).getReg()) 8303 .addMemOperand(MMO); 8304 } 8305 8306 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8307 8308 return EndMBB; 8309} 8310 8311MachineBasicBlock * 8312X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 8313 MachineBasicBlock *BB, 8314 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8315 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8316 DebugLoc DL = MI->getDebugLoc(); 8317 8318 // To "insert" a SELECT_CC instruction, we actually have to insert the 8319 // diamond control-flow pattern. The incoming instruction knows the 8320 // destination vreg to set, the condition code register to branch on, the 8321 // true/false values to select between, and a branch opcode to use. 8322 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 8323 MachineFunction::iterator It = BB; 8324 ++It; 8325 8326 // thisMBB: 8327 // ... 8328 // TrueVal = ... 8329 // cmpTY ccX, r1, r2 8330 // bCC copy1MBB 8331 // fallthrough --> copy0MBB 8332 MachineBasicBlock *thisMBB = BB; 8333 MachineFunction *F = BB->getParent(); 8334 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 8335 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 8336 unsigned Opc = 8337 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 8338 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 8339 F->insert(It, copy0MBB); 8340 F->insert(It, sinkMBB); 8341 // Update machine-CFG edges by first adding all successors of the current 8342 // block to the new block which will contain the Phi node for the select. 8343 // Also inform sdisel of the edge changes. 8344 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 8345 E = BB->succ_end(); I != E; ++I) { 8346 EM->insert(std::make_pair(*I, sinkMBB)); 8347 sinkMBB->addSuccessor(*I); 8348 } 8349 // Next, remove all successors of the current block, and add the true 8350 // and fallthrough blocks as its successors. 8351 while (!BB->succ_empty()) 8352 BB->removeSuccessor(BB->succ_begin()); 8353 // Add the true and fallthrough blocks as its successors. 8354 BB->addSuccessor(copy0MBB); 8355 BB->addSuccessor(sinkMBB); 8356 8357 // copy0MBB: 8358 // %FalseValue = ... 8359 // # fallthrough to sinkMBB 8360 BB = copy0MBB; 8361 8362 // Update machine-CFG edges 8363 BB->addSuccessor(sinkMBB); 8364 8365 // sinkMBB: 8366 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 8367 // ... 8368 BB = sinkMBB; 8369 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) 8370 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 8371 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 8372 8373 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8374 return BB; 8375} 8376 8377 8378MachineBasicBlock * 8379X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 8380 MachineBasicBlock *BB, 8381 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 8382 switch (MI->getOpcode()) { 8383 default: assert(false && "Unexpected instr type to insert"); 8384 case X86::CMOV_GR8: 8385 case X86::CMOV_V1I64: 8386 case X86::CMOV_FR32: 8387 case X86::CMOV_FR64: 8388 case X86::CMOV_V4F32: 8389 case X86::CMOV_V2F64: 8390 case X86::CMOV_V2I64: 8391 return EmitLoweredSelect(MI, BB, EM); 8392 8393 case X86::FP32_TO_INT16_IN_MEM: 8394 case X86::FP32_TO_INT32_IN_MEM: 8395 case X86::FP32_TO_INT64_IN_MEM: 8396 case X86::FP64_TO_INT16_IN_MEM: 8397 case X86::FP64_TO_INT32_IN_MEM: 8398 case X86::FP64_TO_INT64_IN_MEM: 8399 case X86::FP80_TO_INT16_IN_MEM: 8400 case X86::FP80_TO_INT32_IN_MEM: 8401 case X86::FP80_TO_INT64_IN_MEM: { 8402 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 8403 DebugLoc DL = MI->getDebugLoc(); 8404 8405 // Change the floating point control register to use "round towards zero" 8406 // mode when truncating to an integer value. 8407 MachineFunction *F = BB->getParent(); 8408 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 8409 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); 8410 8411 // Load the old value of the high byte of the control word... 8412 unsigned OldCW = 8413 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 8414 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), 8415 CWFrameIdx); 8416 8417 // Set the high part to be round to zero... 8418 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 8419 .addImm(0xC7F); 8420 8421 // Reload the modified control word now... 8422 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8423 8424 // Restore the memory image of control word to original value 8425 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 8426 .addReg(OldCW); 8427 8428 // Get the X86 opcode to use. 8429 unsigned Opc; 8430 switch (MI->getOpcode()) { 8431 default: llvm_unreachable("illegal opcode!"); 8432 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 8433 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 8434 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 8435 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 8436 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 8437 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 8438 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 8439 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 8440 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 8441 } 8442 8443 X86AddressMode AM; 8444 MachineOperand &Op = MI->getOperand(0); 8445 if (Op.isReg()) { 8446 AM.BaseType = X86AddressMode::RegBase; 8447 AM.Base.Reg = Op.getReg(); 8448 } else { 8449 AM.BaseType = X86AddressMode::FrameIndexBase; 8450 AM.Base.FrameIndex = Op.getIndex(); 8451 } 8452 Op = MI->getOperand(1); 8453 if (Op.isImm()) 8454 AM.Scale = Op.getImm(); 8455 Op = MI->getOperand(2); 8456 if (Op.isImm()) 8457 AM.IndexReg = Op.getImm(); 8458 Op = MI->getOperand(3); 8459 if (Op.isGlobal()) { 8460 AM.GV = Op.getGlobal(); 8461 } else { 8462 AM.Disp = Op.getImm(); 8463 } 8464 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) 8465 .addReg(MI->getOperand(X86AddrNumOperands).getReg()); 8466 8467 // Reload the original control word now. 8468 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); 8469 8470 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 8471 return BB; 8472 } 8473 // String/text processing lowering. 8474 case X86::PCMPISTRM128REG: 8475 return EmitPCMP(MI, BB, 3, false /* in-mem */); 8476 case X86::PCMPISTRM128MEM: 8477 return EmitPCMP(MI, BB, 3, true /* in-mem */); 8478 case X86::PCMPESTRM128REG: 8479 return EmitPCMP(MI, BB, 5, false /* in mem */); 8480 case X86::PCMPESTRM128MEM: 8481 return EmitPCMP(MI, BB, 5, true /* in mem */); 8482 8483 // Atomic Lowering. 8484 case X86::ATOMAND32: 8485 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8486 X86::AND32ri, X86::MOV32rm, 8487 X86::LCMPXCHG32, X86::MOV32rr, 8488 X86::NOT32r, X86::EAX, 8489 X86::GR32RegisterClass); 8490 case X86::ATOMOR32: 8491 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 8492 X86::OR32ri, X86::MOV32rm, 8493 X86::LCMPXCHG32, X86::MOV32rr, 8494 X86::NOT32r, X86::EAX, 8495 X86::GR32RegisterClass); 8496 case X86::ATOMXOR32: 8497 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 8498 X86::XOR32ri, X86::MOV32rm, 8499 X86::LCMPXCHG32, X86::MOV32rr, 8500 X86::NOT32r, X86::EAX, 8501 X86::GR32RegisterClass); 8502 case X86::ATOMNAND32: 8503 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 8504 X86::AND32ri, X86::MOV32rm, 8505 X86::LCMPXCHG32, X86::MOV32rr, 8506 X86::NOT32r, X86::EAX, 8507 X86::GR32RegisterClass, true); 8508 case X86::ATOMMIN32: 8509 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 8510 case X86::ATOMMAX32: 8511 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 8512 case X86::ATOMUMIN32: 8513 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 8514 case X86::ATOMUMAX32: 8515 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 8516 8517 case X86::ATOMAND16: 8518 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8519 X86::AND16ri, X86::MOV16rm, 8520 X86::LCMPXCHG16, X86::MOV16rr, 8521 X86::NOT16r, X86::AX, 8522 X86::GR16RegisterClass); 8523 case X86::ATOMOR16: 8524 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 8525 X86::OR16ri, X86::MOV16rm, 8526 X86::LCMPXCHG16, X86::MOV16rr, 8527 X86::NOT16r, X86::AX, 8528 X86::GR16RegisterClass); 8529 case X86::ATOMXOR16: 8530 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 8531 X86::XOR16ri, X86::MOV16rm, 8532 X86::LCMPXCHG16, X86::MOV16rr, 8533 X86::NOT16r, X86::AX, 8534 X86::GR16RegisterClass); 8535 case X86::ATOMNAND16: 8536 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 8537 X86::AND16ri, X86::MOV16rm, 8538 X86::LCMPXCHG16, X86::MOV16rr, 8539 X86::NOT16r, X86::AX, 8540 X86::GR16RegisterClass, true); 8541 case X86::ATOMMIN16: 8542 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 8543 case X86::ATOMMAX16: 8544 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 8545 case X86::ATOMUMIN16: 8546 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 8547 case X86::ATOMUMAX16: 8548 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 8549 8550 case X86::ATOMAND8: 8551 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8552 X86::AND8ri, X86::MOV8rm, 8553 X86::LCMPXCHG8, X86::MOV8rr, 8554 X86::NOT8r, X86::AL, 8555 X86::GR8RegisterClass); 8556 case X86::ATOMOR8: 8557 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 8558 X86::OR8ri, X86::MOV8rm, 8559 X86::LCMPXCHG8, X86::MOV8rr, 8560 X86::NOT8r, X86::AL, 8561 X86::GR8RegisterClass); 8562 case X86::ATOMXOR8: 8563 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 8564 X86::XOR8ri, X86::MOV8rm, 8565 X86::LCMPXCHG8, X86::MOV8rr, 8566 X86::NOT8r, X86::AL, 8567 X86::GR8RegisterClass); 8568 case X86::ATOMNAND8: 8569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 8570 X86::AND8ri, X86::MOV8rm, 8571 X86::LCMPXCHG8, X86::MOV8rr, 8572 X86::NOT8r, X86::AL, 8573 X86::GR8RegisterClass, true); 8574 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 8575 // This group is for 64-bit host. 8576 case X86::ATOMAND64: 8577 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8578 X86::AND64ri32, X86::MOV64rm, 8579 X86::LCMPXCHG64, X86::MOV64rr, 8580 X86::NOT64r, X86::RAX, 8581 X86::GR64RegisterClass); 8582 case X86::ATOMOR64: 8583 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 8584 X86::OR64ri32, X86::MOV64rm, 8585 X86::LCMPXCHG64, X86::MOV64rr, 8586 X86::NOT64r, X86::RAX, 8587 X86::GR64RegisterClass); 8588 case X86::ATOMXOR64: 8589 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 8590 X86::XOR64ri32, X86::MOV64rm, 8591 X86::LCMPXCHG64, X86::MOV64rr, 8592 X86::NOT64r, X86::RAX, 8593 X86::GR64RegisterClass); 8594 case X86::ATOMNAND64: 8595 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 8596 X86::AND64ri32, X86::MOV64rm, 8597 X86::LCMPXCHG64, X86::MOV64rr, 8598 X86::NOT64r, X86::RAX, 8599 X86::GR64RegisterClass, true); 8600 case X86::ATOMMIN64: 8601 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 8602 case X86::ATOMMAX64: 8603 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 8604 case X86::ATOMUMIN64: 8605 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 8606 case X86::ATOMUMAX64: 8607 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 8608 8609 // This group does 64-bit operations on a 32-bit host. 8610 case X86::ATOMAND6432: 8611 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8612 X86::AND32rr, X86::AND32rr, 8613 X86::AND32ri, X86::AND32ri, 8614 false); 8615 case X86::ATOMOR6432: 8616 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8617 X86::OR32rr, X86::OR32rr, 8618 X86::OR32ri, X86::OR32ri, 8619 false); 8620 case X86::ATOMXOR6432: 8621 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8622 X86::XOR32rr, X86::XOR32rr, 8623 X86::XOR32ri, X86::XOR32ri, 8624 false); 8625 case X86::ATOMNAND6432: 8626 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8627 X86::AND32rr, X86::AND32rr, 8628 X86::AND32ri, X86::AND32ri, 8629 true); 8630 case X86::ATOMADD6432: 8631 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8632 X86::ADD32rr, X86::ADC32rr, 8633 X86::ADD32ri, X86::ADC32ri, 8634 false); 8635 case X86::ATOMSUB6432: 8636 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8637 X86::SUB32rr, X86::SBB32rr, 8638 X86::SUB32ri, X86::SBB32ri, 8639 false); 8640 case X86::ATOMSWAP6432: 8641 return EmitAtomicBit6432WithCustomInserter(MI, BB, 8642 X86::MOV32rr, X86::MOV32rr, 8643 X86::MOV32ri, X86::MOV32ri, 8644 false); 8645 case X86::VASTART_SAVE_XMM_REGS: 8646 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 8647 } 8648} 8649 8650//===----------------------------------------------------------------------===// 8651// X86 Optimization Hooks 8652//===----------------------------------------------------------------------===// 8653 8654void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8655 const APInt &Mask, 8656 APInt &KnownZero, 8657 APInt &KnownOne, 8658 const SelectionDAG &DAG, 8659 unsigned Depth) const { 8660 unsigned Opc = Op.getOpcode(); 8661 assert((Opc >= ISD::BUILTIN_OP_END || 8662 Opc == ISD::INTRINSIC_WO_CHAIN || 8663 Opc == ISD::INTRINSIC_W_CHAIN || 8664 Opc == ISD::INTRINSIC_VOID) && 8665 "Should use MaskedValueIsZero if you don't know whether Op" 8666 " is a target node!"); 8667 8668 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 8669 switch (Opc) { 8670 default: break; 8671 case X86ISD::ADD: 8672 case X86ISD::SUB: 8673 case X86ISD::SMUL: 8674 case X86ISD::UMUL: 8675 case X86ISD::INC: 8676 case X86ISD::DEC: 8677 case X86ISD::OR: 8678 case X86ISD::XOR: 8679 case X86ISD::AND: 8680 // These nodes' second result is a boolean. 8681 if (Op.getResNo() == 0) 8682 break; 8683 // Fallthrough 8684 case X86ISD::SETCC: 8685 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 8686 Mask.getBitWidth() - 1); 8687 break; 8688 } 8689} 8690 8691/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 8692/// node is a GlobalAddress + offset. 8693bool X86TargetLowering::isGAPlusOffset(SDNode *N, 8694 GlobalValue* &GA, int64_t &Offset) const{ 8695 if (N->getOpcode() == X86ISD::Wrapper) { 8696 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 8697 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 8698 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 8699 return true; 8700 } 8701 } 8702 return TargetLowering::isGAPlusOffset(N, GA, Offset); 8703} 8704 8705static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, 8706 EVT EltVT, LoadSDNode *&LDBase, 8707 unsigned &LastLoadedElt, 8708 SelectionDAG &DAG, MachineFrameInfo *MFI, 8709 const TargetLowering &TLI) { 8710 LDBase = NULL; 8711 LastLoadedElt = -1U; 8712 for (unsigned i = 0; i < NumElems; ++i) { 8713 if (N->getMaskElt(i) < 0) { 8714 if (!LDBase) 8715 return false; 8716 continue; 8717 } 8718 8719 SDValue Elt = DAG.getShuffleScalarElt(N, i); 8720 if (!Elt.getNode() || 8721 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 8722 return false; 8723 if (!LDBase) { 8724 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 8725 return false; 8726 LDBase = cast<LoadSDNode>(Elt.getNode()); 8727 LastLoadedElt = i; 8728 continue; 8729 } 8730 if (Elt.getOpcode() == ISD::UNDEF) 8731 continue; 8732 8733 LoadSDNode *LD = cast<LoadSDNode>(Elt); 8734 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 8735 return false; 8736 LastLoadedElt = i; 8737 } 8738 return true; 8739} 8740 8741/// PerformShuffleCombine - Combine a vector_shuffle that is equal to 8742/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load 8743/// if the load addresses are consecutive, non-overlapping, and in the right 8744/// order. In the case of v2i64, it will see if it can rewrite the 8745/// shuffle to be an appropriate build vector so it can take advantage of 8746// performBuildVectorCombine. 8747static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 8748 const TargetLowering &TLI) { 8749 DebugLoc dl = N->getDebugLoc(); 8750 EVT VT = N->getValueType(0); 8751 EVT EltVT = VT.getVectorElementType(); 8752 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8753 unsigned NumElems = VT.getVectorNumElements(); 8754 8755 if (VT.getSizeInBits() != 128) 8756 return SDValue(); 8757 8758 // Try to combine a vector_shuffle into a 128-bit load. 8759 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8760 LoadSDNode *LD = NULL; 8761 unsigned LastLoadedElt; 8762 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG, 8763 MFI, TLI)) 8764 return SDValue(); 8765 8766 if (LastLoadedElt == NumElems - 1) { 8767 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16) 8768 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8769 LD->getSrcValue(), LD->getSrcValueOffset(), 8770 LD->isVolatile(), LD->isNonTemporal(), 0); 8771 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(), 8772 LD->getSrcValue(), LD->getSrcValueOffset(), 8773 LD->isVolatile(), LD->isNonTemporal(), 8774 LD->getAlignment()); 8775 } else if (NumElems == 4 && LastLoadedElt == 1) { 8776 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 8777 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; 8778 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); 8779 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); 8780 } 8781 return SDValue(); 8782} 8783 8784/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. 8785static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 8786 const X86Subtarget *Subtarget) { 8787 DebugLoc DL = N->getDebugLoc(); 8788 SDValue Cond = N->getOperand(0); 8789 // Get the LHS/RHS of the select. 8790 SDValue LHS = N->getOperand(1); 8791 SDValue RHS = N->getOperand(2); 8792 8793 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 8794 // instructions have the peculiarity that if either operand is a NaN, 8795 // they chose what we call the RHS operand (and as such are not symmetric). 8796 // It happens that this matches the semantics of the common C idiom 8797 // x<y?x:y and related forms, so we can recognize these cases. 8798 if (Subtarget->hasSSE2() && 8799 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && 8800 Cond.getOpcode() == ISD::SETCC) { 8801 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 8802 8803 unsigned Opcode = 0; 8804 // Check for x CC y ? x : y. 8805 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) { 8806 switch (CC) { 8807 default: break; 8808 case ISD::SETULT: 8809 // This can be a min if we can prove that at least one of the operands 8810 // is not a nan. 8811 if (!FiniteOnlyFPMath()) { 8812 if (DAG.isKnownNeverNaN(RHS)) { 8813 // Put the potential NaN in the RHS so that SSE will preserve it. 8814 std::swap(LHS, RHS); 8815 } else if (!DAG.isKnownNeverNaN(LHS)) 8816 break; 8817 } 8818 Opcode = X86ISD::FMIN; 8819 break; 8820 case ISD::SETOLE: 8821 // This can be a min if we can prove that at least one of the operands 8822 // is not a nan. 8823 if (!FiniteOnlyFPMath()) { 8824 if (DAG.isKnownNeverNaN(LHS)) { 8825 // Put the potential NaN in the RHS so that SSE will preserve it. 8826 std::swap(LHS, RHS); 8827 } else if (!DAG.isKnownNeverNaN(RHS)) 8828 break; 8829 } 8830 Opcode = X86ISD::FMIN; 8831 break; 8832 case ISD::SETULE: 8833 // This can be a min, but if either operand is a NaN we need it to 8834 // preserve the original LHS. 8835 std::swap(LHS, RHS); 8836 case ISD::SETOLT: 8837 case ISD::SETLT: 8838 case ISD::SETLE: 8839 Opcode = X86ISD::FMIN; 8840 break; 8841 8842 case ISD::SETOGE: 8843 // This can be a max if we can prove that at least one of the operands 8844 // is not a nan. 8845 if (!FiniteOnlyFPMath()) { 8846 if (DAG.isKnownNeverNaN(LHS)) { 8847 // Put the potential NaN in the RHS so that SSE will preserve it. 8848 std::swap(LHS, RHS); 8849 } else if (!DAG.isKnownNeverNaN(RHS)) 8850 break; 8851 } 8852 Opcode = X86ISD::FMAX; 8853 break; 8854 case ISD::SETUGT: 8855 // This can be a max if we can prove that at least one of the operands 8856 // is not a nan. 8857 if (!FiniteOnlyFPMath()) { 8858 if (DAG.isKnownNeverNaN(RHS)) { 8859 // Put the potential NaN in the RHS so that SSE will preserve it. 8860 std::swap(LHS, RHS); 8861 } else if (!DAG.isKnownNeverNaN(LHS)) 8862 break; 8863 } 8864 Opcode = X86ISD::FMAX; 8865 break; 8866 case ISD::SETUGE: 8867 // This can be a max, but if either operand is a NaN we need it to 8868 // preserve the original LHS. 8869 std::swap(LHS, RHS); 8870 case ISD::SETOGT: 8871 case ISD::SETGT: 8872 case ISD::SETGE: 8873 Opcode = X86ISD::FMAX; 8874 break; 8875 } 8876 // Check for x CC y ? y : x -- a min/max with reversed arms. 8877 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) { 8878 switch (CC) { 8879 default: break; 8880 case ISD::SETOGE: 8881 // This can be a min if we can prove that at least one of the operands 8882 // is not a nan. 8883 if (!FiniteOnlyFPMath()) { 8884 if (DAG.isKnownNeverNaN(RHS)) { 8885 // Put the potential NaN in the RHS so that SSE will preserve it. 8886 std::swap(LHS, RHS); 8887 } else if (!DAG.isKnownNeverNaN(LHS)) 8888 break; 8889 } 8890 Opcode = X86ISD::FMIN; 8891 break; 8892 case ISD::SETUGT: 8893 // This can be a min if we can prove that at least one of the operands 8894 // is not a nan. 8895 if (!FiniteOnlyFPMath()) { 8896 if (DAG.isKnownNeverNaN(LHS)) { 8897 // Put the potential NaN in the RHS so that SSE will preserve it. 8898 std::swap(LHS, RHS); 8899 } else if (!DAG.isKnownNeverNaN(RHS)) 8900 break; 8901 } 8902 Opcode = X86ISD::FMIN; 8903 break; 8904 case ISD::SETUGE: 8905 // This can be a min, but if either operand is a NaN we need it to 8906 // preserve the original LHS. 8907 std::swap(LHS, RHS); 8908 case ISD::SETOGT: 8909 case ISD::SETGT: 8910 case ISD::SETGE: 8911 Opcode = X86ISD::FMIN; 8912 break; 8913 8914 case ISD::SETULT: 8915 // This can be a max if we can prove that at least one of the operands 8916 // is not a nan. 8917 if (!FiniteOnlyFPMath()) { 8918 if (DAG.isKnownNeverNaN(LHS)) { 8919 // Put the potential NaN in the RHS so that SSE will preserve it. 8920 std::swap(LHS, RHS); 8921 } else if (!DAG.isKnownNeverNaN(RHS)) 8922 break; 8923 } 8924 Opcode = X86ISD::FMAX; 8925 break; 8926 case ISD::SETOLE: 8927 // This can be a max if we can prove that at least one of the operands 8928 // is not a nan. 8929 if (!FiniteOnlyFPMath()) { 8930 if (DAG.isKnownNeverNaN(RHS)) { 8931 // Put the potential NaN in the RHS so that SSE will preserve it. 8932 std::swap(LHS, RHS); 8933 } else if (!DAG.isKnownNeverNaN(LHS)) 8934 break; 8935 } 8936 Opcode = X86ISD::FMAX; 8937 break; 8938 case ISD::SETULE: 8939 // This can be a max, but if either operand is a NaN we need it to 8940 // preserve the original LHS. 8941 std::swap(LHS, RHS); 8942 case ISD::SETOLT: 8943 case ISD::SETLT: 8944 case ISD::SETLE: 8945 Opcode = X86ISD::FMAX; 8946 break; 8947 } 8948 } 8949 8950 if (Opcode) 8951 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 8952 } 8953 8954 // If this is a select between two integer constants, try to do some 8955 // optimizations. 8956 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 8957 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 8958 // Don't do this for crazy integer types. 8959 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 8960 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 8961 // so that TrueC (the true value) is larger than FalseC. 8962 bool NeedsCondInvert = false; 8963 8964 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 8965 // Efficiently invertible. 8966 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 8967 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 8968 isa<ConstantSDNode>(Cond.getOperand(1))))) { 8969 NeedsCondInvert = true; 8970 std::swap(TrueC, FalseC); 8971 } 8972 8973 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 8974 if (FalseC->getAPIntValue() == 0 && 8975 TrueC->getAPIntValue().isPowerOf2()) { 8976 if (NeedsCondInvert) // Invert the condition if needed. 8977 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8978 DAG.getConstant(1, Cond.getValueType())); 8979 8980 // Zero extend the condition if needed. 8981 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 8982 8983 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 8984 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 8985 DAG.getConstant(ShAmt, MVT::i8)); 8986 } 8987 8988 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 8989 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 8990 if (NeedsCondInvert) // Invert the condition if needed. 8991 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 8992 DAG.getConstant(1, Cond.getValueType())); 8993 8994 // Zero extend the condition if needed. 8995 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 8996 FalseC->getValueType(0), Cond); 8997 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 8998 SDValue(FalseC, 0)); 8999 } 9000 9001 // Optimize cases that will turn into an LEA instruction. This requires 9002 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9003 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9004 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9005 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9006 9007 bool isFastMultiplier = false; 9008 if (Diff < 10) { 9009 switch ((unsigned char)Diff) { 9010 default: break; 9011 case 1: // result = add base, cond 9012 case 2: // result = lea base( , cond*2) 9013 case 3: // result = lea base(cond, cond*2) 9014 case 4: // result = lea base( , cond*4) 9015 case 5: // result = lea base(cond, cond*4) 9016 case 8: // result = lea base( , cond*8) 9017 case 9: // result = lea base(cond, cond*8) 9018 isFastMultiplier = true; 9019 break; 9020 } 9021 } 9022 9023 if (isFastMultiplier) { 9024 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9025 if (NeedsCondInvert) // Invert the condition if needed. 9026 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 9027 DAG.getConstant(1, Cond.getValueType())); 9028 9029 // Zero extend the condition if needed. 9030 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9031 Cond); 9032 // Scale the condition by the difference. 9033 if (Diff != 1) 9034 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9035 DAG.getConstant(Diff, Cond.getValueType())); 9036 9037 // Add the base if non-zero. 9038 if (FalseC->getAPIntValue() != 0) 9039 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9040 SDValue(FalseC, 0)); 9041 return Cond; 9042 } 9043 } 9044 } 9045 } 9046 9047 return SDValue(); 9048} 9049 9050/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 9051static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 9052 TargetLowering::DAGCombinerInfo &DCI) { 9053 DebugLoc DL = N->getDebugLoc(); 9054 9055 // If the flag operand isn't dead, don't touch this CMOV. 9056 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 9057 return SDValue(); 9058 9059 // If this is a select between two integer constants, try to do some 9060 // optimizations. Note that the operands are ordered the opposite of SELECT 9061 // operands. 9062 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 9063 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 9064 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 9065 // larger than FalseC (the false value). 9066 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 9067 9068 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 9069 CC = X86::GetOppositeBranchCondition(CC); 9070 std::swap(TrueC, FalseC); 9071 } 9072 9073 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 9074 // This is efficient for any integer data type (including i8/i16) and 9075 // shift amount. 9076 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 9077 SDValue Cond = N->getOperand(3); 9078 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9079 DAG.getConstant(CC, MVT::i8), Cond); 9080 9081 // Zero extend the condition if needed. 9082 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 9083 9084 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 9085 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 9086 DAG.getConstant(ShAmt, MVT::i8)); 9087 if (N->getNumValues() == 2) // Dead flag value? 9088 return DCI.CombineTo(N, Cond, SDValue()); 9089 return Cond; 9090 } 9091 9092 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 9093 // for any integer data type, including i8/i16. 9094 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 9095 SDValue Cond = N->getOperand(3); 9096 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9097 DAG.getConstant(CC, MVT::i8), Cond); 9098 9099 // Zero extend the condition if needed. 9100 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 9101 FalseC->getValueType(0), Cond); 9102 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9103 SDValue(FalseC, 0)); 9104 9105 if (N->getNumValues() == 2) // Dead flag value? 9106 return DCI.CombineTo(N, Cond, SDValue()); 9107 return Cond; 9108 } 9109 9110 // Optimize cases that will turn into an LEA instruction. This requires 9111 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 9112 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 9113 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 9114 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 9115 9116 bool isFastMultiplier = false; 9117 if (Diff < 10) { 9118 switch ((unsigned char)Diff) { 9119 default: break; 9120 case 1: // result = add base, cond 9121 case 2: // result = lea base( , cond*2) 9122 case 3: // result = lea base(cond, cond*2) 9123 case 4: // result = lea base( , cond*4) 9124 case 5: // result = lea base(cond, cond*4) 9125 case 8: // result = lea base( , cond*8) 9126 case 9: // result = lea base(cond, cond*8) 9127 isFastMultiplier = true; 9128 break; 9129 } 9130 } 9131 9132 if (isFastMultiplier) { 9133 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 9134 SDValue Cond = N->getOperand(3); 9135 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 9136 DAG.getConstant(CC, MVT::i8), Cond); 9137 // Zero extend the condition if needed. 9138 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 9139 Cond); 9140 // Scale the condition by the difference. 9141 if (Diff != 1) 9142 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 9143 DAG.getConstant(Diff, Cond.getValueType())); 9144 9145 // Add the base if non-zero. 9146 if (FalseC->getAPIntValue() != 0) 9147 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 9148 SDValue(FalseC, 0)); 9149 if (N->getNumValues() == 2) // Dead flag value? 9150 return DCI.CombineTo(N, Cond, SDValue()); 9151 return Cond; 9152 } 9153 } 9154 } 9155 } 9156 return SDValue(); 9157} 9158 9159 9160/// PerformMulCombine - Optimize a single multiply with constant into two 9161/// in order to implement it with two cheaper instructions, e.g. 9162/// LEA + SHL, LEA + LEA. 9163static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 9164 TargetLowering::DAGCombinerInfo &DCI) { 9165 if (DAG.getMachineFunction(). 9166 getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 9167 return SDValue(); 9168 9169 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 9170 return SDValue(); 9171 9172 EVT VT = N->getValueType(0); 9173 if (VT != MVT::i64) 9174 return SDValue(); 9175 9176 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9177 if (!C) 9178 return SDValue(); 9179 uint64_t MulAmt = C->getZExtValue(); 9180 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 9181 return SDValue(); 9182 9183 uint64_t MulAmt1 = 0; 9184 uint64_t MulAmt2 = 0; 9185 if ((MulAmt % 9) == 0) { 9186 MulAmt1 = 9; 9187 MulAmt2 = MulAmt / 9; 9188 } else if ((MulAmt % 5) == 0) { 9189 MulAmt1 = 5; 9190 MulAmt2 = MulAmt / 5; 9191 } else if ((MulAmt % 3) == 0) { 9192 MulAmt1 = 3; 9193 MulAmt2 = MulAmt / 3; 9194 } 9195 if (MulAmt2 && 9196 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 9197 DebugLoc DL = N->getDebugLoc(); 9198 9199 if (isPowerOf2_64(MulAmt2) && 9200 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 9201 // If second multiplifer is pow2, issue it first. We want the multiply by 9202 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 9203 // is an add. 9204 std::swap(MulAmt1, MulAmt2); 9205 9206 SDValue NewMul; 9207 if (isPowerOf2_64(MulAmt1)) 9208 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 9209 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 9210 else 9211 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 9212 DAG.getConstant(MulAmt1, VT)); 9213 9214 if (isPowerOf2_64(MulAmt2)) 9215 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 9216 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 9217 else 9218 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 9219 DAG.getConstant(MulAmt2, VT)); 9220 9221 // Do not add new nodes to DAG combiner worklist. 9222 DCI.CombineTo(N, NewMul, false); 9223 } 9224 return SDValue(); 9225} 9226 9227static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 9228 SDValue N0 = N->getOperand(0); 9229 SDValue N1 = N->getOperand(1); 9230 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 9231 EVT VT = N0.getValueType(); 9232 9233 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 9234 // since the result of setcc_c is all zero's or all ones. 9235 if (N1C && N0.getOpcode() == ISD::AND && 9236 N0.getOperand(1).getOpcode() == ISD::Constant) { 9237 SDValue N00 = N0.getOperand(0); 9238 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 9239 ((N00.getOpcode() == ISD::ANY_EXTEND || 9240 N00.getOpcode() == ISD::ZERO_EXTEND) && 9241 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 9242 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 9243 APInt ShAmt = N1C->getAPIntValue(); 9244 Mask = Mask.shl(ShAmt); 9245 if (Mask != 0) 9246 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 9247 N00, DAG.getConstant(Mask, VT)); 9248 } 9249 } 9250 9251 return SDValue(); 9252} 9253 9254/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 9255/// when possible. 9256static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 9257 const X86Subtarget *Subtarget) { 9258 EVT VT = N->getValueType(0); 9259 if (!VT.isVector() && VT.isInteger() && 9260 N->getOpcode() == ISD::SHL) 9261 return PerformSHLCombine(N, DAG); 9262 9263 // On X86 with SSE2 support, we can transform this to a vector shift if 9264 // all elements are shifted by the same amount. We can't do this in legalize 9265 // because the a constant vector is typically transformed to a constant pool 9266 // so we have no knowledge of the shift amount. 9267 if (!Subtarget->hasSSE2()) 9268 return SDValue(); 9269 9270 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 9271 return SDValue(); 9272 9273 SDValue ShAmtOp = N->getOperand(1); 9274 EVT EltVT = VT.getVectorElementType(); 9275 DebugLoc DL = N->getDebugLoc(); 9276 SDValue BaseShAmt = SDValue(); 9277 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 9278 unsigned NumElts = VT.getVectorNumElements(); 9279 unsigned i = 0; 9280 for (; i != NumElts; ++i) { 9281 SDValue Arg = ShAmtOp.getOperand(i); 9282 if (Arg.getOpcode() == ISD::UNDEF) continue; 9283 BaseShAmt = Arg; 9284 break; 9285 } 9286 for (; i != NumElts; ++i) { 9287 SDValue Arg = ShAmtOp.getOperand(i); 9288 if (Arg.getOpcode() == ISD::UNDEF) continue; 9289 if (Arg != BaseShAmt) { 9290 return SDValue(); 9291 } 9292 } 9293 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 9294 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 9295 SDValue InVec = ShAmtOp.getOperand(0); 9296 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 9297 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 9298 unsigned i = 0; 9299 for (; i != NumElts; ++i) { 9300 SDValue Arg = InVec.getOperand(i); 9301 if (Arg.getOpcode() == ISD::UNDEF) continue; 9302 BaseShAmt = Arg; 9303 break; 9304 } 9305 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 9306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 9307 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 9308 if (C->getZExtValue() == SplatIdx) 9309 BaseShAmt = InVec.getOperand(1); 9310 } 9311 } 9312 if (BaseShAmt.getNode() == 0) 9313 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 9314 DAG.getIntPtrConstant(0)); 9315 } else 9316 return SDValue(); 9317 9318 // The shift amount is an i32. 9319 if (EltVT.bitsGT(MVT::i32)) 9320 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 9321 else if (EltVT.bitsLT(MVT::i32)) 9322 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 9323 9324 // The shift amount is identical so we can do a vector shift. 9325 SDValue ValOp = N->getOperand(0); 9326 switch (N->getOpcode()) { 9327 default: 9328 llvm_unreachable("Unknown shift opcode!"); 9329 break; 9330 case ISD::SHL: 9331 if (VT == MVT::v2i64) 9332 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9333 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9334 ValOp, BaseShAmt); 9335 if (VT == MVT::v4i32) 9336 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9337 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9338 ValOp, BaseShAmt); 9339 if (VT == MVT::v8i16) 9340 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9341 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9342 ValOp, BaseShAmt); 9343 break; 9344 case ISD::SRA: 9345 if (VT == MVT::v4i32) 9346 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9347 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9348 ValOp, BaseShAmt); 9349 if (VT == MVT::v8i16) 9350 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9351 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9352 ValOp, BaseShAmt); 9353 break; 9354 case ISD::SRL: 9355 if (VT == MVT::v2i64) 9356 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9357 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9358 ValOp, BaseShAmt); 9359 if (VT == MVT::v4i32) 9360 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9361 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9362 ValOp, BaseShAmt); 9363 if (VT == MVT::v8i16) 9364 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 9365 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9366 ValOp, BaseShAmt); 9367 break; 9368 } 9369 return SDValue(); 9370} 9371 9372static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 9373 const X86Subtarget *Subtarget) { 9374 EVT VT = N->getValueType(0); 9375 if (VT != MVT::i64 || !Subtarget->is64Bit()) 9376 return SDValue(); 9377 9378 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 9379 SDValue N0 = N->getOperand(0); 9380 SDValue N1 = N->getOperand(1); 9381 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 9382 std::swap(N0, N1); 9383 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 9384 return SDValue(); 9385 9386 SDValue ShAmt0 = N0.getOperand(1); 9387 if (ShAmt0.getValueType() != MVT::i8) 9388 return SDValue(); 9389 SDValue ShAmt1 = N1.getOperand(1); 9390 if (ShAmt1.getValueType() != MVT::i8) 9391 return SDValue(); 9392 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 9393 ShAmt0 = ShAmt0.getOperand(0); 9394 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 9395 ShAmt1 = ShAmt1.getOperand(0); 9396 9397 DebugLoc DL = N->getDebugLoc(); 9398 unsigned Opc = X86ISD::SHLD; 9399 SDValue Op0 = N0.getOperand(0); 9400 SDValue Op1 = N1.getOperand(0); 9401 if (ShAmt0.getOpcode() == ISD::SUB) { 9402 Opc = X86ISD::SHRD; 9403 std::swap(Op0, Op1); 9404 std::swap(ShAmt0, ShAmt1); 9405 } 9406 9407 if (ShAmt1.getOpcode() == ISD::SUB) { 9408 SDValue Sum = ShAmt1.getOperand(0); 9409 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 9410 if (SumC->getSExtValue() == 64 && 9411 ShAmt1.getOperand(1) == ShAmt0) 9412 return DAG.getNode(Opc, DL, VT, 9413 Op0, Op1, 9414 DAG.getNode(ISD::TRUNCATE, DL, 9415 MVT::i8, ShAmt0)); 9416 } 9417 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 9418 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 9419 if (ShAmt0C && 9420 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64) 9421 return DAG.getNode(Opc, DL, VT, 9422 N0.getOperand(0), N1.getOperand(0), 9423 DAG.getNode(ISD::TRUNCATE, DL, 9424 MVT::i8, ShAmt0)); 9425 } 9426 9427 return SDValue(); 9428} 9429 9430/// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 9431static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 9432 const X86Subtarget *Subtarget) { 9433 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 9434 // the FP state in cases where an emms may be missing. 9435 // A preferable solution to the general problem is to figure out the right 9436 // places to insert EMMS. This qualifies as a quick hack. 9437 9438 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 9439 StoreSDNode *St = cast<StoreSDNode>(N); 9440 EVT VT = St->getValue().getValueType(); 9441 if (VT.getSizeInBits() != 64) 9442 return SDValue(); 9443 9444 const Function *F = DAG.getMachineFunction().getFunction(); 9445 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 9446 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 9447 && Subtarget->hasSSE2(); 9448 if ((VT.isVector() || 9449 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 9450 isa<LoadSDNode>(St->getValue()) && 9451 !cast<LoadSDNode>(St->getValue())->isVolatile() && 9452 St->getChain().hasOneUse() && !St->isVolatile()) { 9453 SDNode* LdVal = St->getValue().getNode(); 9454 LoadSDNode *Ld = 0; 9455 int TokenFactorIndex = -1; 9456 SmallVector<SDValue, 8> Ops; 9457 SDNode* ChainVal = St->getChain().getNode(); 9458 // Must be a store of a load. We currently handle two cases: the load 9459 // is a direct child, and it's under an intervening TokenFactor. It is 9460 // possible to dig deeper under nested TokenFactors. 9461 if (ChainVal == LdVal) 9462 Ld = cast<LoadSDNode>(St->getChain()); 9463 else if (St->getValue().hasOneUse() && 9464 ChainVal->getOpcode() == ISD::TokenFactor) { 9465 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 9466 if (ChainVal->getOperand(i).getNode() == LdVal) { 9467 TokenFactorIndex = i; 9468 Ld = cast<LoadSDNode>(St->getValue()); 9469 } else 9470 Ops.push_back(ChainVal->getOperand(i)); 9471 } 9472 } 9473 9474 if (!Ld || !ISD::isNormalLoad(Ld)) 9475 return SDValue(); 9476 9477 // If this is not the MMX case, i.e. we are just turning i64 load/store 9478 // into f64 load/store, avoid the transformation if there are multiple 9479 // uses of the loaded value. 9480 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 9481 return SDValue(); 9482 9483 DebugLoc LdDL = Ld->getDebugLoc(); 9484 DebugLoc StDL = N->getDebugLoc(); 9485 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 9486 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 9487 // pair instead. 9488 if (Subtarget->is64Bit() || F64IsLegal) { 9489 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 9490 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), 9491 Ld->getBasePtr(), Ld->getSrcValue(), 9492 Ld->getSrcValueOffset(), Ld->isVolatile(), 9493 Ld->isNonTemporal(), Ld->getAlignment()); 9494 SDValue NewChain = NewLd.getValue(1); 9495 if (TokenFactorIndex != -1) { 9496 Ops.push_back(NewChain); 9497 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9498 Ops.size()); 9499 } 9500 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 9501 St->getSrcValue(), St->getSrcValueOffset(), 9502 St->isVolatile(), St->isNonTemporal(), 9503 St->getAlignment()); 9504 } 9505 9506 // Otherwise, lower to two pairs of 32-bit loads / stores. 9507 SDValue LoAddr = Ld->getBasePtr(); 9508 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 9509 DAG.getConstant(4, MVT::i32)); 9510 9511 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 9512 Ld->getSrcValue(), Ld->getSrcValueOffset(), 9513 Ld->isVolatile(), Ld->isNonTemporal(), 9514 Ld->getAlignment()); 9515 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 9516 Ld->getSrcValue(), Ld->getSrcValueOffset()+4, 9517 Ld->isVolatile(), Ld->isNonTemporal(), 9518 MinAlign(Ld->getAlignment(), 4)); 9519 9520 SDValue NewChain = LoLd.getValue(1); 9521 if (TokenFactorIndex != -1) { 9522 Ops.push_back(LoLd); 9523 Ops.push_back(HiLd); 9524 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 9525 Ops.size()); 9526 } 9527 9528 LoAddr = St->getBasePtr(); 9529 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 9530 DAG.getConstant(4, MVT::i32)); 9531 9532 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 9533 St->getSrcValue(), St->getSrcValueOffset(), 9534 St->isVolatile(), St->isNonTemporal(), 9535 St->getAlignment()); 9536 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 9537 St->getSrcValue(), 9538 St->getSrcValueOffset() + 4, 9539 St->isVolatile(), 9540 St->isNonTemporal(), 9541 MinAlign(St->getAlignment(), 4)); 9542 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 9543 } 9544 return SDValue(); 9545} 9546 9547/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 9548/// X86ISD::FXOR nodes. 9549static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 9550 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 9551 // F[X]OR(0.0, x) -> x 9552 // F[X]OR(x, 0.0) -> x 9553 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9554 if (C->getValueAPF().isPosZero()) 9555 return N->getOperand(1); 9556 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9557 if (C->getValueAPF().isPosZero()) 9558 return N->getOperand(0); 9559 return SDValue(); 9560} 9561 9562/// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 9563static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 9564 // FAND(0.0, x) -> 0.0 9565 // FAND(x, 0.0) -> 0.0 9566 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 9567 if (C->getValueAPF().isPosZero()) 9568 return N->getOperand(0); 9569 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 9570 if (C->getValueAPF().isPosZero()) 9571 return N->getOperand(1); 9572 return SDValue(); 9573} 9574 9575static SDValue PerformBTCombine(SDNode *N, 9576 SelectionDAG &DAG, 9577 TargetLowering::DAGCombinerInfo &DCI) { 9578 // BT ignores high bits in the bit index operand. 9579 SDValue Op1 = N->getOperand(1); 9580 if (Op1.hasOneUse()) { 9581 unsigned BitWidth = Op1.getValueSizeInBits(); 9582 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 9583 APInt KnownZero, KnownOne; 9584 TargetLowering::TargetLoweringOpt TLO(DAG); 9585 TargetLowering &TLI = DAG.getTargetLoweringInfo(); 9586 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 9587 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 9588 DCI.CommitTargetLoweringOpt(TLO); 9589 } 9590 return SDValue(); 9591} 9592 9593static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 9594 SDValue Op = N->getOperand(0); 9595 if (Op.getOpcode() == ISD::BIT_CONVERT) 9596 Op = Op.getOperand(0); 9597 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 9598 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 9599 VT.getVectorElementType().getSizeInBits() == 9600 OpVT.getVectorElementType().getSizeInBits()) { 9601 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); 9602 } 9603 return SDValue(); 9604} 9605 9606// On X86 and X86-64, atomic operations are lowered to locked instructions. 9607// Locked instructions, in turn, have implicit fence semantics (all memory 9608// operations are flushed before issuing the locked instruction, and the 9609// are not buffered), so we can fold away the common pattern of 9610// fence-atomic-fence. 9611static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) { 9612 SDValue atomic = N->getOperand(0); 9613 switch (atomic.getOpcode()) { 9614 case ISD::ATOMIC_CMP_SWAP: 9615 case ISD::ATOMIC_SWAP: 9616 case ISD::ATOMIC_LOAD_ADD: 9617 case ISD::ATOMIC_LOAD_SUB: 9618 case ISD::ATOMIC_LOAD_AND: 9619 case ISD::ATOMIC_LOAD_OR: 9620 case ISD::ATOMIC_LOAD_XOR: 9621 case ISD::ATOMIC_LOAD_NAND: 9622 case ISD::ATOMIC_LOAD_MIN: 9623 case ISD::ATOMIC_LOAD_MAX: 9624 case ISD::ATOMIC_LOAD_UMIN: 9625 case ISD::ATOMIC_LOAD_UMAX: 9626 break; 9627 default: 9628 return SDValue(); 9629 } 9630 9631 SDValue fence = atomic.getOperand(0); 9632 if (fence.getOpcode() != ISD::MEMBARRIER) 9633 return SDValue(); 9634 9635 switch (atomic.getOpcode()) { 9636 case ISD::ATOMIC_CMP_SWAP: 9637 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9638 atomic.getOperand(1), atomic.getOperand(2), 9639 atomic.getOperand(3)); 9640 case ISD::ATOMIC_SWAP: 9641 case ISD::ATOMIC_LOAD_ADD: 9642 case ISD::ATOMIC_LOAD_SUB: 9643 case ISD::ATOMIC_LOAD_AND: 9644 case ISD::ATOMIC_LOAD_OR: 9645 case ISD::ATOMIC_LOAD_XOR: 9646 case ISD::ATOMIC_LOAD_NAND: 9647 case ISD::ATOMIC_LOAD_MIN: 9648 case ISD::ATOMIC_LOAD_MAX: 9649 case ISD::ATOMIC_LOAD_UMIN: 9650 case ISD::ATOMIC_LOAD_UMAX: 9651 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), 9652 atomic.getOperand(1), atomic.getOperand(2)); 9653 default: 9654 return SDValue(); 9655 } 9656} 9657 9658static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 9659 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 9660 // (and (i32 x86isd::setcc_carry), 1) 9661 // This eliminates the zext. This transformation is necessary because 9662 // ISD::SETCC is always legalized to i8. 9663 DebugLoc dl = N->getDebugLoc(); 9664 SDValue N0 = N->getOperand(0); 9665 EVT VT = N->getValueType(0); 9666 if (N0.getOpcode() == ISD::AND && 9667 N0.hasOneUse() && 9668 N0.getOperand(0).hasOneUse()) { 9669 SDValue N00 = N0.getOperand(0); 9670 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 9671 return SDValue(); 9672 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 9673 if (!C || C->getZExtValue() != 1) 9674 return SDValue(); 9675 return DAG.getNode(ISD::AND, dl, VT, 9676 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 9677 N00.getOperand(0), N00.getOperand(1)), 9678 DAG.getConstant(1, VT)); 9679 } 9680 9681 return SDValue(); 9682} 9683 9684SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 9685 DAGCombinerInfo &DCI) const { 9686 SelectionDAG &DAG = DCI.DAG; 9687 switch (N->getOpcode()) { 9688 default: break; 9689 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); 9690 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 9691 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 9692 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 9693 case ISD::SHL: 9694 case ISD::SRA: 9695 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 9696 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget); 9697 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 9698 case X86ISD::FXOR: 9699 case X86ISD::FOR: return PerformFORCombine(N, DAG); 9700 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 9701 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 9702 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 9703 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG); 9704 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 9705 } 9706 9707 return SDValue(); 9708} 9709 9710//===----------------------------------------------------------------------===// 9711// X86 Inline Assembly Support 9712//===----------------------------------------------------------------------===// 9713 9714static bool LowerToBSwap(CallInst *CI) { 9715 // FIXME: this should verify that we are targetting a 486 or better. If not, 9716 // we will turn this bswap into something that will be lowered to logical ops 9717 // instead of emitting the bswap asm. For now, we don't support 486 or lower 9718 // so don't worry about this. 9719 9720 // Verify this is a simple bswap. 9721 if (CI->getNumOperands() != 2 || 9722 CI->getType() != CI->getOperand(1)->getType() || 9723 !CI->getType()->isIntegerTy()) 9724 return false; 9725 9726 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 9727 if (!Ty || Ty->getBitWidth() % 16 != 0) 9728 return false; 9729 9730 // Okay, we can do this xform, do so now. 9731 const Type *Tys[] = { Ty }; 9732 Module *M = CI->getParent()->getParent()->getParent(); 9733 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1); 9734 9735 Value *Op = CI->getOperand(1); 9736 Op = CallInst::Create(Int, Op, CI->getName(), CI); 9737 9738 CI->replaceAllUsesWith(Op); 9739 CI->eraseFromParent(); 9740 return true; 9741} 9742 9743bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 9744 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 9745 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints(); 9746 9747 std::string AsmStr = IA->getAsmString(); 9748 9749 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 9750 SmallVector<StringRef, 4> AsmPieces; 9751 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator? 9752 9753 switch (AsmPieces.size()) { 9754 default: return false; 9755 case 1: 9756 AsmStr = AsmPieces[0]; 9757 AsmPieces.clear(); 9758 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 9759 9760 // bswap $0 9761 if (AsmPieces.size() == 2 && 9762 (AsmPieces[0] == "bswap" || 9763 AsmPieces[0] == "bswapq" || 9764 AsmPieces[0] == "bswapl") && 9765 (AsmPieces[1] == "$0" || 9766 AsmPieces[1] == "${0:q}")) { 9767 // No need to check constraints, nothing other than the equivalent of 9768 // "=r,0" would be valid here. 9769 return LowerToBSwap(CI); 9770 } 9771 // rorw $$8, ${0:w} --> llvm.bswap.i16 9772 if (CI->getType()->isIntegerTy(16) && 9773 AsmPieces.size() == 3 && 9774 AsmPieces[0] == "rorw" && 9775 AsmPieces[1] == "$$8," && 9776 AsmPieces[2] == "${0:w}" && 9777 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") { 9778 return LowerToBSwap(CI); 9779 } 9780 break; 9781 case 3: 9782 if (CI->getType()->isIntegerTy(64) && 9783 Constraints.size() >= 2 && 9784 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 9785 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 9786 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 9787 SmallVector<StringRef, 4> Words; 9788 SplitString(AsmPieces[0], Words, " \t"); 9789 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 9790 Words.clear(); 9791 SplitString(AsmPieces[1], Words, " \t"); 9792 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 9793 Words.clear(); 9794 SplitString(AsmPieces[2], Words, " \t,"); 9795 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 9796 Words[2] == "%edx") { 9797 return LowerToBSwap(CI); 9798 } 9799 } 9800 } 9801 } 9802 break; 9803 } 9804 return false; 9805} 9806 9807 9808 9809/// getConstraintType - Given a constraint letter, return the type of 9810/// constraint it is for this target. 9811X86TargetLowering::ConstraintType 9812X86TargetLowering::getConstraintType(const std::string &Constraint) const { 9813 if (Constraint.size() == 1) { 9814 switch (Constraint[0]) { 9815 case 'A': 9816 return C_Register; 9817 case 'f': 9818 case 'r': 9819 case 'R': 9820 case 'l': 9821 case 'q': 9822 case 'Q': 9823 case 'x': 9824 case 'y': 9825 case 'Y': 9826 return C_RegisterClass; 9827 case 'e': 9828 case 'Z': 9829 return C_Other; 9830 default: 9831 break; 9832 } 9833 } 9834 return TargetLowering::getConstraintType(Constraint); 9835} 9836 9837/// LowerXConstraint - try to replace an X constraint, which matches anything, 9838/// with another that has more specific requirements based on the type of the 9839/// corresponding operand. 9840const char *X86TargetLowering:: 9841LowerXConstraint(EVT ConstraintVT) const { 9842 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 9843 // 'f' like normal targets. 9844 if (ConstraintVT.isFloatingPoint()) { 9845 if (Subtarget->hasSSE2()) 9846 return "Y"; 9847 if (Subtarget->hasSSE1()) 9848 return "x"; 9849 } 9850 9851 return TargetLowering::LowerXConstraint(ConstraintVT); 9852} 9853 9854/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 9855/// vector. If it is invalid, don't add anything to Ops. 9856void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 9857 char Constraint, 9858 bool hasMemory, 9859 std::vector<SDValue>&Ops, 9860 SelectionDAG &DAG) const { 9861 SDValue Result(0, 0); 9862 9863 switch (Constraint) { 9864 default: break; 9865 case 'I': 9866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9867 if (C->getZExtValue() <= 31) { 9868 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9869 break; 9870 } 9871 } 9872 return; 9873 case 'J': 9874 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9875 if (C->getZExtValue() <= 63) { 9876 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9877 break; 9878 } 9879 } 9880 return; 9881 case 'K': 9882 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9883 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 9884 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9885 break; 9886 } 9887 } 9888 return; 9889 case 'N': 9890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9891 if (C->getZExtValue() <= 255) { 9892 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9893 break; 9894 } 9895 } 9896 return; 9897 case 'e': { 9898 // 32-bit signed value 9899 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9900 const ConstantInt *CI = C->getConstantIntValue(); 9901 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9902 C->getSExtValue())) { 9903 // Widen to 64 bits here to get it sign extended. 9904 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 9905 break; 9906 } 9907 // FIXME gcc accepts some relocatable values here too, but only in certain 9908 // memory models; it's complicated. 9909 } 9910 return; 9911 } 9912 case 'Z': { 9913 // 32-bit unsigned value 9914 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 9915 const ConstantInt *CI = C->getConstantIntValue(); 9916 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 9917 C->getZExtValue())) { 9918 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 9919 break; 9920 } 9921 } 9922 // FIXME gcc accepts some relocatable values here too, but only in certain 9923 // memory models; it's complicated. 9924 return; 9925 } 9926 case 'i': { 9927 // Literal immediates are always ok. 9928 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 9929 // Widen to 64 bits here to get it sign extended. 9930 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 9931 break; 9932 } 9933 9934 // If we are in non-pic codegen mode, we allow the address of a global (with 9935 // an optional displacement) to be used with 'i'. 9936 GlobalAddressSDNode *GA = 0; 9937 int64_t Offset = 0; 9938 9939 // Match either (GA), (GA+C), (GA+C1+C2), etc. 9940 while (1) { 9941 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 9942 Offset += GA->getOffset(); 9943 break; 9944 } else if (Op.getOpcode() == ISD::ADD) { 9945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9946 Offset += C->getZExtValue(); 9947 Op = Op.getOperand(0); 9948 continue; 9949 } 9950 } else if (Op.getOpcode() == ISD::SUB) { 9951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 9952 Offset += -C->getZExtValue(); 9953 Op = Op.getOperand(0); 9954 continue; 9955 } 9956 } 9957 9958 // Otherwise, this isn't something we can handle, reject it. 9959 return; 9960 } 9961 9962 GlobalValue *GV = GA->getGlobal(); 9963 // If we require an extra load to get this address, as in PIC mode, we 9964 // can't accept it. 9965 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 9966 getTargetMachine()))) 9967 return; 9968 9969 if (hasMemory) 9970 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 9971 else 9972 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset); 9973 Result = Op; 9974 break; 9975 } 9976 } 9977 9978 if (Result.getNode()) { 9979 Ops.push_back(Result); 9980 return; 9981 } 9982 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 9983 Ops, DAG); 9984} 9985 9986std::vector<unsigned> X86TargetLowering:: 9987getRegClassForInlineAsmConstraint(const std::string &Constraint, 9988 EVT VT) const { 9989 if (Constraint.size() == 1) { 9990 // FIXME: not handling fp-stack yet! 9991 switch (Constraint[0]) { // GCC X86 Constraint Letters 9992 default: break; // Unknown constraint letter 9993 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 9994 if (Subtarget->is64Bit()) { 9995 if (VT == MVT::i32) 9996 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 9997 X86::ESI, X86::EDI, X86::R8D, X86::R9D, 9998 X86::R10D,X86::R11D,X86::R12D, 9999 X86::R13D,X86::R14D,X86::R15D, 10000 X86::EBP, X86::ESP, 0); 10001 else if (VT == MVT::i16) 10002 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 10003 X86::SI, X86::DI, X86::R8W,X86::R9W, 10004 X86::R10W,X86::R11W,X86::R12W, 10005 X86::R13W,X86::R14W,X86::R15W, 10006 X86::BP, X86::SP, 0); 10007 else if (VT == MVT::i8) 10008 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 10009 X86::SIL, X86::DIL, X86::R8B,X86::R9B, 10010 X86::R10B,X86::R11B,X86::R12B, 10011 X86::R13B,X86::R14B,X86::R15B, 10012 X86::BPL, X86::SPL, 0); 10013 10014 else if (VT == MVT::i64) 10015 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 10016 X86::RSI, X86::RDI, X86::R8, X86::R9, 10017 X86::R10, X86::R11, X86::R12, 10018 X86::R13, X86::R14, X86::R15, 10019 X86::RBP, X86::RSP, 0); 10020 10021 break; 10022 } 10023 // 32-bit fallthrough 10024 case 'Q': // Q_REGS 10025 if (VT == MVT::i32) 10026 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); 10027 else if (VT == MVT::i16) 10028 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); 10029 else if (VT == MVT::i8) 10030 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); 10031 else if (VT == MVT::i64) 10032 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); 10033 break; 10034 } 10035 } 10036 10037 return std::vector<unsigned>(); 10038} 10039 10040std::pair<unsigned, const TargetRegisterClass*> 10041X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 10042 EVT VT) const { 10043 // First, see if this is a constraint that directly corresponds to an LLVM 10044 // register class. 10045 if (Constraint.size() == 1) { 10046 // GCC Constraint Letters 10047 switch (Constraint[0]) { 10048 default: break; 10049 case 'r': // GENERAL_REGS 10050 case 'l': // INDEX_REGS 10051 if (VT == MVT::i8) 10052 return std::make_pair(0U, X86::GR8RegisterClass); 10053 if (VT == MVT::i16) 10054 return std::make_pair(0U, X86::GR16RegisterClass); 10055 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10056 return std::make_pair(0U, X86::GR32RegisterClass); 10057 return std::make_pair(0U, X86::GR64RegisterClass); 10058 case 'R': // LEGACY_REGS 10059 if (VT == MVT::i8) 10060 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 10061 if (VT == MVT::i16) 10062 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 10063 if (VT == MVT::i32 || !Subtarget->is64Bit()) 10064 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 10065 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 10066 case 'f': // FP Stack registers. 10067 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 10068 // value to the correct fpstack register class. 10069 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 10070 return std::make_pair(0U, X86::RFP32RegisterClass); 10071 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 10072 return std::make_pair(0U, X86::RFP64RegisterClass); 10073 return std::make_pair(0U, X86::RFP80RegisterClass); 10074 case 'y': // MMX_REGS if MMX allowed. 10075 if (!Subtarget->hasMMX()) break; 10076 return std::make_pair(0U, X86::VR64RegisterClass); 10077 case 'Y': // SSE_REGS if SSE2 allowed 10078 if (!Subtarget->hasSSE2()) break; 10079 // FALL THROUGH. 10080 case 'x': // SSE_REGS if SSE1 allowed 10081 if (!Subtarget->hasSSE1()) break; 10082 10083 switch (VT.getSimpleVT().SimpleTy) { 10084 default: break; 10085 // Scalar SSE types. 10086 case MVT::f32: 10087 case MVT::i32: 10088 return std::make_pair(0U, X86::FR32RegisterClass); 10089 case MVT::f64: 10090 case MVT::i64: 10091 return std::make_pair(0U, X86::FR64RegisterClass); 10092 // Vector types. 10093 case MVT::v16i8: 10094 case MVT::v8i16: 10095 case MVT::v4i32: 10096 case MVT::v2i64: 10097 case MVT::v4f32: 10098 case MVT::v2f64: 10099 return std::make_pair(0U, X86::VR128RegisterClass); 10100 } 10101 break; 10102 } 10103 } 10104 10105 // Use the default implementation in TargetLowering to convert the register 10106 // constraint into a member of a register class. 10107 std::pair<unsigned, const TargetRegisterClass*> Res; 10108 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 10109 10110 // Not found as a standard register? 10111 if (Res.second == 0) { 10112 // Map st(0) -> st(7) -> ST0 10113 if (Constraint.size() == 7 && Constraint[0] == '{' && 10114 tolower(Constraint[1]) == 's' && 10115 tolower(Constraint[2]) == 't' && 10116 Constraint[3] == '(' && 10117 (Constraint[4] >= '0' && Constraint[4] <= '7') && 10118 Constraint[5] == ')' && 10119 Constraint[6] == '}') { 10120 10121 Res.first = X86::ST0+Constraint[4]-'0'; 10122 Res.second = X86::RFP80RegisterClass; 10123 return Res; 10124 } 10125 10126 // GCC allows "st(0)" to be called just plain "st". 10127 if (StringRef("{st}").equals_lower(Constraint)) { 10128 Res.first = X86::ST0; 10129 Res.second = X86::RFP80RegisterClass; 10130 return Res; 10131 } 10132 10133 // flags -> EFLAGS 10134 if (StringRef("{flags}").equals_lower(Constraint)) { 10135 Res.first = X86::EFLAGS; 10136 Res.second = X86::CCRRegisterClass; 10137 return Res; 10138 } 10139 10140 // 'A' means EAX + EDX. 10141 if (Constraint == "A") { 10142 Res.first = X86::EAX; 10143 Res.second = X86::GR32_ADRegisterClass; 10144 return Res; 10145 } 10146 return Res; 10147 } 10148 10149 // Otherwise, check to see if this is a register class of the wrong value 10150 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 10151 // turn into {ax},{dx}. 10152 if (Res.second->hasType(VT)) 10153 return Res; // Correct type already, nothing to do. 10154 10155 // All of the single-register GCC register classes map their values onto 10156 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 10157 // really want an 8-bit or 32-bit register, map to the appropriate register 10158 // class and return the appropriate register. 10159 if (Res.second == X86::GR16RegisterClass) { 10160 if (VT == MVT::i8) { 10161 unsigned DestReg = 0; 10162 switch (Res.first) { 10163 default: break; 10164 case X86::AX: DestReg = X86::AL; break; 10165 case X86::DX: DestReg = X86::DL; break; 10166 case X86::CX: DestReg = X86::CL; break; 10167 case X86::BX: DestReg = X86::BL; break; 10168 } 10169 if (DestReg) { 10170 Res.first = DestReg; 10171 Res.second = X86::GR8RegisterClass; 10172 } 10173 } else if (VT == MVT::i32) { 10174 unsigned DestReg = 0; 10175 switch (Res.first) { 10176 default: break; 10177 case X86::AX: DestReg = X86::EAX; break; 10178 case X86::DX: DestReg = X86::EDX; break; 10179 case X86::CX: DestReg = X86::ECX; break; 10180 case X86::BX: DestReg = X86::EBX; break; 10181 case X86::SI: DestReg = X86::ESI; break; 10182 case X86::DI: DestReg = X86::EDI; break; 10183 case X86::BP: DestReg = X86::EBP; break; 10184 case X86::SP: DestReg = X86::ESP; break; 10185 } 10186 if (DestReg) { 10187 Res.first = DestReg; 10188 Res.second = X86::GR32RegisterClass; 10189 } 10190 } else if (VT == MVT::i64) { 10191 unsigned DestReg = 0; 10192 switch (Res.first) { 10193 default: break; 10194 case X86::AX: DestReg = X86::RAX; break; 10195 case X86::DX: DestReg = X86::RDX; break; 10196 case X86::CX: DestReg = X86::RCX; break; 10197 case X86::BX: DestReg = X86::RBX; break; 10198 case X86::SI: DestReg = X86::RSI; break; 10199 case X86::DI: DestReg = X86::RDI; break; 10200 case X86::BP: DestReg = X86::RBP; break; 10201 case X86::SP: DestReg = X86::RSP; break; 10202 } 10203 if (DestReg) { 10204 Res.first = DestReg; 10205 Res.second = X86::GR64RegisterClass; 10206 } 10207 } 10208 } else if (Res.second == X86::FR32RegisterClass || 10209 Res.second == X86::FR64RegisterClass || 10210 Res.second == X86::VR128RegisterClass) { 10211 // Handle references to XMM physical registers that got mapped into the 10212 // wrong class. This can happen with constraints like {xmm0} where the 10213 // target independent register mapper will just pick the first match it can 10214 // find, ignoring the required type. 10215 if (VT == MVT::f32) 10216 Res.second = X86::FR32RegisterClass; 10217 else if (VT == MVT::f64) 10218 Res.second = X86::FR64RegisterClass; 10219 else if (X86::VR128RegisterClass->hasType(VT)) 10220 Res.second = X86::VR128RegisterClass; 10221 } 10222 10223 return Res; 10224} 10225 10226//===----------------------------------------------------------------------===// 10227// X86 Widen vector type 10228//===----------------------------------------------------------------------===// 10229 10230/// getWidenVectorType: given a vector type, returns the type to widen 10231/// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 10232/// If there is no vector type that we want to widen to, returns MVT::Other 10233/// When and where to widen is target dependent based on the cost of 10234/// scalarizing vs using the wider vector type. 10235 10236EVT X86TargetLowering::getWidenVectorType(EVT VT) const { 10237 assert(VT.isVector()); 10238 if (isTypeLegal(VT)) 10239 return VT; 10240 10241 // TODO: In computeRegisterProperty, we can compute the list of legal vector 10242 // type based on element type. This would speed up our search (though 10243 // it may not be worth it since the size of the list is relatively 10244 // small). 10245 EVT EltVT = VT.getVectorElementType(); 10246 unsigned NElts = VT.getVectorNumElements(); 10247 10248 // On X86, it make sense to widen any vector wider than 1 10249 if (NElts <= 1) 10250 return MVT::Other; 10251 10252 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; 10253 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 10254 EVT SVT = (MVT::SimpleValueType)nVT; 10255 10256 if (isTypeLegal(SVT) && 10257 SVT.getVectorElementType() == EltVT && 10258 SVT.getVectorNumElements() > NElts) 10259 return SVT; 10260 } 10261 return MVT::Other; 10262} 10263